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Merge tag 'linux-can-fixes-for-3.15-20140424' of git://gitorious.org/linux-can/linux-can
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
41#define DRV_VERSION_MINOR 3
db446094 42#define DRV_VERSION_BUILD 36
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e
SN		 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X710), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_D), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 79 /* required last entry */
80 {0, }
81};
82MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
83
84#define I40E_MAX_VF_COUNT 128
85static int debug = -1;
86module_param(debug, int, 0);
87MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
88
89MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
90MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_VERSION);
93
94/**
95 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
96 * @hw: pointer to the HW structure
97 * @mem: ptr to mem struct to fill out
98 * @size: size of memory requested
99 * @alignment: what to align the allocation to
100 **/
101int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
102 u64 size, u32 alignment)
103{
104 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
105
106 mem->size = ALIGN(size, alignment);
107 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
108 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 109 if (!mem->va)
110 return -ENOMEM;
41c445ff 111
93bc73b8 112 return 0;
41c445ff
JB		 113}
114
115/**
116 * i40e_free_dma_mem_d - OS specific memory free for shared code
117 * @hw: pointer to the HW structure
118 * @mem: ptr to mem struct to free
119 **/
120int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
121{
122 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
123
124 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
125 mem->va = NULL;
126 mem->pa = 0;
127 mem->size = 0;
128
129 return 0;
130}
131
132/**
133 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
134 * @hw: pointer to the HW structure
135 * @mem: ptr to mem struct to fill out
136 * @size: size of memory requested
137 **/
138int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
139 u32 size)
140{
141 mem->size = size;
142 mem->va = kzalloc(size, GFP_KERNEL);
143
93bc73b8
JB		 144 if (!mem->va)
145 return -ENOMEM;
41c445ff 146
93bc73b8 147 return 0;
41c445ff
JB		 148}
149
150/**
151 * i40e_free_virt_mem_d - OS specific memory free for shared code
152 * @hw: pointer to the HW structure
153 * @mem: ptr to mem struct to free
154 **/
155int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
156{
157 /* it's ok to kfree a NULL pointer */
158 kfree(mem->va);
159 mem->va = NULL;
160 mem->size = 0;
161
162 return 0;
163}
164
165/**
166 * i40e_get_lump - find a lump of free generic resource
167 * @pf: board private structure
168 * @pile: the pile of resource to search
169 * @needed: the number of items needed
170 * @id: an owner id to stick on the items assigned
171 *
172 * Returns the base item index of the lump, or negative for error
173 *
174 * The search_hint trick and lack of advanced fit-finding only work
175 * because we're highly likely to have all the same size lump requests.
176 * Linear search time and any fragmentation should be minimal.
177 **/
178static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
179 u16 needed, u16 id)
180{
181 int ret = -ENOMEM;
ddf434ac 182 int i, j;
41c445ff
JB		 183
184 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
185 dev_info(&pf->pdev->dev,
186 "param err: pile=%p needed=%d id=0x%04x\n",
187 pile, needed, id);
188 return -EINVAL;
189 }
190
191 /* start the linear search with an imperfect hint */
192 i = pile->search_hint;
ddf434ac 193 while (i < pile->num_entries) {
41c445ff
JB		 194 /* skip already allocated entries */
195 if (pile->list[i] & I40E_PILE_VALID_BIT) {
196 i++;
197 continue;
198 }
199
200 /* do we have enough in this lump? */
201 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
202 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
203 break;
204 }
205
206 if (j == needed) {
207 /* there was enough, so assign it to the requestor */
208 for (j = 0; j < needed; j++)
209 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
210 ret = i;
211 pile->search_hint = i + j;
ddf434ac 212 break;
41c445ff
JB		 213 } else {
214 /* not enough, so skip over it and continue looking */
215 i += j;
216 }
217 }
218
219 return ret;
220}
221
222/**
223 * i40e_put_lump - return a lump of generic resource
224 * @pile: the pile of resource to search
225 * @index: the base item index
226 * @id: the owner id of the items assigned
227 *
228 * Returns the count of items in the lump
229 **/
230static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
231{
232 int valid_id = (id | I40E_PILE_VALID_BIT);
233 int count = 0;
234 int i;
235
236 if (!pile || index >= pile->num_entries)
237 return -EINVAL;
238
239 for (i = index;
240 i < pile->num_entries && pile->list[i] == valid_id;
241 i++) {
242 pile->list[i] = 0;
243 count++;
244 }
245
246 if (count && index < pile->search_hint)
247 pile->search_hint = index;
248
249 return count;
250}
251
252/**
253 * i40e_service_event_schedule - Schedule the service task to wake up
254 * @pf: board private structure
255 *
256 * If not already scheduled, this puts the task into the work queue
257 **/
258static void i40e_service_event_schedule(struct i40e_pf *pf)
259{
260 if (!test_bit(__I40E_DOWN, &pf->state) &&
261 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
262 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
263 schedule_work(&pf->service_task);
264}
265
266/**
267 * i40e_tx_timeout - Respond to a Tx Hang
268 * @netdev: network interface device structure
269 *
270 * If any port has noticed a Tx timeout, it is likely that the whole
271 * device is munged, not just the one netdev port, so go for the full
272 * reset.
273 **/
274static void i40e_tx_timeout(struct net_device *netdev)
275{
276 struct i40e_netdev_priv *np = netdev_priv(netdev);
277 struct i40e_vsi *vsi = np->vsi;
278 struct i40e_pf *pf = vsi->back;
279
280 pf->tx_timeout_count++;
281
282 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
283 pf->tx_timeout_recovery_level = 0;
284 pf->tx_timeout_last_recovery = jiffies;
285 netdev_info(netdev, "tx_timeout recovery level %d\n",
286 pf->tx_timeout_recovery_level);
287
288 switch (pf->tx_timeout_recovery_level) {
289 case 0:
290 /* disable and re-enable queues for the VSI */
291 if (in_interrupt()) {
292 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
293 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
294 } else {
295 i40e_vsi_reinit_locked(vsi);
296 }
297 break;
298 case 1:
299 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
300 break;
301 case 2:
302 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
303 break;
304 case 3:
305 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
306 break;
307 default:
308 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 309 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 310 i40e_down(vsi);
311 break;
312 }
313 i40e_service_event_schedule(pf);
314 pf->tx_timeout_recovery_level++;
315}
316
317/**
318 * i40e_release_rx_desc - Store the new tail and head values
319 * @rx_ring: ring to bump
320 * @val: new head index
321 **/
322static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
323{
324 rx_ring->next_to_use = val;
325
326 /* Force memory writes to complete before letting h/w
327 * know there are new descriptors to fetch. (Only
328 * applicable for weak-ordered memory model archs,
329 * such as IA-64).
330 */
331 wmb();
332 writel(val, rx_ring->tail);
333}
334
335/**
336 * i40e_get_vsi_stats_struct - Get System Network Statistics
337 * @vsi: the VSI we care about
338 *
339 * Returns the address of the device statistics structure.
340 * The statistics are actually updated from the service task.
341 **/
342struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
343{
344 return &vsi->net_stats;
345}
346
347/**
348 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
349 * @netdev: network interface device structure
350 *
351 * Returns the address of the device statistics structure.
352 * The statistics are actually updated from the service task.
353 **/
354static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
355 struct net_device *netdev,
980e9b11 356 struct rtnl_link_stats64 *stats)
41c445ff
JB		 357{
358 struct i40e_netdev_priv *np = netdev_priv(netdev);
359 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 360 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
361 int i;
362
bc7d338f
ASJ		 363 if (test_bit(__I40E_DOWN, &vsi->state))
364 return stats;
365
3c325ced
JB		 366 if (!vsi->tx_rings)
367 return stats;
368
980e9b11
AD		 369 rcu_read_lock();
370 for (i = 0; i < vsi->num_queue_pairs; i++) {
371 struct i40e_ring *tx_ring, *rx_ring;
372 u64 bytes, packets;
373 unsigned int start;
374
375 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
376 if (!tx_ring)
377 continue;
378
379 do {
57a7744e 380 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 381 packets = tx_ring->stats.packets;
382 bytes = tx_ring->stats.bytes;
57a7744e 383 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 384
385 stats->tx_packets += packets;
386 stats->tx_bytes += bytes;
387 rx_ring = &tx_ring[1];
388
389 do {
57a7744e 390 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 391 packets = rx_ring->stats.packets;
392 bytes = rx_ring->stats.bytes;
57a7744e 393 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 394
980e9b11
AD		 395 stats->rx_packets += packets;
396 stats->rx_bytes += bytes;
397 }
398 rcu_read_unlock();
399
400 /* following stats updated by ixgbe_watchdog_task() */
401 stats->multicast = vsi_stats->multicast;
402 stats->tx_errors = vsi_stats->tx_errors;
403 stats->tx_dropped = vsi_stats->tx_dropped;
404 stats->rx_errors = vsi_stats->rx_errors;
405 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
406 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 407
980e9b11 408 return stats;
41c445ff
JB		 409}
410
411/**
412 * i40e_vsi_reset_stats - Resets all stats of the given vsi
413 * @vsi: the VSI to have its stats reset
414 **/
415void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
416{
417 struct rtnl_link_stats64 *ns;
418 int i;
419
420 if (!vsi)
421 return;
422
423 ns = i40e_get_vsi_stats_struct(vsi);
424 memset(ns, 0, sizeof(*ns));
425 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
426 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
427 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 428 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 429 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 430 memset(&vsi->rx_rings[i]->stats, 0 ,
431 sizeof(vsi->rx_rings[i]->stats));
432 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
433 sizeof(vsi->rx_rings[i]->rx_stats));
434 memset(&vsi->tx_rings[i]->stats, 0 ,
435 sizeof(vsi->tx_rings[i]->stats));
436 memset(&vsi->tx_rings[i]->tx_stats, 0,
437 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 438 }
8e9dca53 439 }
41c445ff
JB		 440 vsi->stat_offsets_loaded = false;
441}
442
443/**
444 * i40e_pf_reset_stats - Reset all of the stats for the given pf
445 * @pf: the PF to be reset
446 **/
447void i40e_pf_reset_stats(struct i40e_pf *pf)
448{
449 memset(&pf->stats, 0, sizeof(pf->stats));
450 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
451 pf->stat_offsets_loaded = false;
452}
453
454/**
455 * i40e_stat_update48 - read and update a 48 bit stat from the chip
456 * @hw: ptr to the hardware info
457 * @hireg: the high 32 bit reg to read
458 * @loreg: the low 32 bit reg to read
459 * @offset_loaded: has the initial offset been loaded yet
460 * @offset: ptr to current offset value
461 * @stat: ptr to the stat
462 *
463 * Since the device stats are not reset at PFReset, they likely will not
464 * be zeroed when the driver starts. We'll save the first values read
465 * and use them as offsets to be subtracted from the raw values in order
466 * to report stats that count from zero. In the process, we also manage
467 * the potential roll-over.
468 **/
469static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
470 bool offset_loaded, u64 *offset, u64 *stat)
471{
472 u64 new_data;
473
ab60085e 474 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 475 new_data = rd32(hw, loreg);
476 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
477 } else {
478 new_data = rd64(hw, loreg);
479 }
480 if (!offset_loaded)
481 *offset = new_data;
482 if (likely(new_data >= *offset))
483 *stat = new_data - *offset;
484 else
485 *stat = (new_data + ((u64)1 << 48)) - *offset;
486 *stat &= 0xFFFFFFFFFFFFULL;
487}
488
489/**
490 * i40e_stat_update32 - read and update a 32 bit stat from the chip
491 * @hw: ptr to the hardware info
492 * @reg: the hw reg to read
493 * @offset_loaded: has the initial offset been loaded yet
494 * @offset: ptr to current offset value
495 * @stat: ptr to the stat
496 **/
497static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
498 bool offset_loaded, u64 *offset, u64 *stat)
499{
500 u32 new_data;
501
502 new_data = rd32(hw, reg);
503 if (!offset_loaded)
504 *offset = new_data;
505 if (likely(new_data >= *offset))
506 *stat = (u32)(new_data - *offset);
507 else
508 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
509}
510
511/**
512 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
513 * @vsi: the VSI to be updated
514 **/
515void i40e_update_eth_stats(struct i40e_vsi *vsi)
516{
517 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
518 struct i40e_pf *pf = vsi->back;
519 struct i40e_hw *hw = &pf->hw;
520 struct i40e_eth_stats *oes;
521 struct i40e_eth_stats *es; /* device's eth stats */
522
523 es = &vsi->eth_stats;
524 oes = &vsi->eth_stats_offsets;
525
526 /* Gather up the stats that the hw collects */
527 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->tx_errors, &es->tx_errors);
530 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
531 vsi->stat_offsets_loaded,
532 &oes->rx_discards, &es->rx_discards);
533
534 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
535 I40E_GLV_GORCL(stat_idx),
536 vsi->stat_offsets_loaded,
537 &oes->rx_bytes, &es->rx_bytes);
538 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
539 I40E_GLV_UPRCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->rx_unicast, &es->rx_unicast);
542 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
543 I40E_GLV_MPRCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_multicast, &es->rx_multicast);
546 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
547 I40E_GLV_BPRCL(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->rx_broadcast, &es->rx_broadcast);
550
551 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
552 I40E_GLV_GOTCL(stat_idx),
553 vsi->stat_offsets_loaded,
554 &oes->tx_bytes, &es->tx_bytes);
555 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
556 I40E_GLV_UPTCL(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_unicast, &es->tx_unicast);
559 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
560 I40E_GLV_MPTCL(stat_idx),
561 vsi->stat_offsets_loaded,
562 &oes->tx_multicast, &es->tx_multicast);
563 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
564 I40E_GLV_BPTCL(stat_idx),
565 vsi->stat_offsets_loaded,
566 &oes->tx_broadcast, &es->tx_broadcast);
567 vsi->stat_offsets_loaded = true;
568}
569
570/**
571 * i40e_update_veb_stats - Update Switch component statistics
572 * @veb: the VEB being updated
573 **/
574static void i40e_update_veb_stats(struct i40e_veb *veb)
575{
576 struct i40e_pf *pf = veb->pf;
577 struct i40e_hw *hw = &pf->hw;
578 struct i40e_eth_stats *oes;
579 struct i40e_eth_stats *es; /* device's eth stats */
580 int idx = 0;
581
582 idx = veb->stats_idx;
583 es = &veb->stats;
584 oes = &veb->stats_offsets;
585
586 /* Gather up the stats that the hw collects */
587 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
588 veb->stat_offsets_loaded,
589 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 590 if (hw->revision_id > 0)
591 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
592 veb->stat_offsets_loaded,
593 &oes->rx_unknown_protocol,
594 &es->rx_unknown_protocol);
41c445ff
JB		 595 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_bytes, &es->rx_bytes);
598 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_unicast, &es->rx_unicast);
601 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_multicast, &es->rx_multicast);
604 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
605 veb->stat_offsets_loaded,
606 &oes->rx_broadcast, &es->rx_broadcast);
607
608 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_bytes, &es->tx_bytes);
611 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_unicast, &es->tx_unicast);
614 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_multicast, &es->tx_multicast);
617 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
618 veb->stat_offsets_loaded,
619 &oes->tx_broadcast, &es->tx_broadcast);
620 veb->stat_offsets_loaded = true;
621}
622
623/**
624 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
625 * @pf: the corresponding PF
626 *
627 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
628 **/
629static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
630{
631 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
632 struct i40e_hw_port_stats *nsd = &pf->stats;
633 struct i40e_hw *hw = &pf->hw;
634 u64 xoff = 0;
635 u16 i, v;
636
637 if ((hw->fc.current_mode != I40E_FC_FULL) &&
638 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
639 return;
640
641 xoff = nsd->link_xoff_rx;
642 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
643 pf->stat_offsets_loaded,
644 &osd->link_xoff_rx, &nsd->link_xoff_rx);
645
646 /* No new LFC xoff rx */
647 if (!(nsd->link_xoff_rx - xoff))
648 return;
649
650 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
651 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
652 struct i40e_vsi *vsi = pf->vsi[v];
653
654 if (!vsi)
655 continue;
656
657 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 658 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 659 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
660 }
661 }
662}
663
664/**
665 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
666 * @pf: the corresponding PF
667 *
668 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
669 **/
670static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
671{
672 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
673 struct i40e_hw_port_stats *nsd = &pf->stats;
674 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
675 struct i40e_dcbx_config *dcb_cfg;
676 struct i40e_hw *hw = &pf->hw;
677 u16 i, v;
678 u8 tc;
679
680 dcb_cfg = &hw->local_dcbx_config;
681
682 /* See if DCB enabled with PFC TC */
683 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
684 !(dcb_cfg->pfc.pfcenable)) {
685 i40e_update_link_xoff_rx(pf);
686 return;
687 }
688
689 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
690 u64 prio_xoff = nsd->priority_xoff_rx[i];
691 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
692 pf->stat_offsets_loaded,
693 &osd->priority_xoff_rx[i],
694 &nsd->priority_xoff_rx[i]);
695
696 /* No new PFC xoff rx */
697 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
698 continue;
699 /* Get the TC for given priority */
700 tc = dcb_cfg->etscfg.prioritytable[i];
701 xoff[tc] = true;
702 }
703
704 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
705 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
706 struct i40e_vsi *vsi = pf->vsi[v];
707
708 if (!vsi)
709 continue;
710
711 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 712 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 713
714 tc = ring->dcb_tc;
715 if (xoff[tc])
716 clear_bit(__I40E_HANG_CHECK_ARMED,
717 &ring->state);
718 }
719 }
720}
721
722/**
723 * i40e_update_stats - Update the board statistics counters.
724 * @vsi: the VSI to be updated
725 *
726 * There are a few instances where we store the same stat in a
727 * couple of different structs. This is partly because we have
728 * the netdev stats that need to be filled out, which is slightly
729 * different from the "eth_stats" defined by the chip and used in
730 * VF communications. We sort it all out here in a central place.
731 **/
732void i40e_update_stats(struct i40e_vsi *vsi)
733{
734 struct i40e_pf *pf = vsi->back;
735 struct i40e_hw *hw = &pf->hw;
736 struct rtnl_link_stats64 *ons;
737 struct rtnl_link_stats64 *ns; /* netdev stats */
738 struct i40e_eth_stats *oes;
739 struct i40e_eth_stats *es; /* device's eth stats */
740 u32 tx_restart, tx_busy;
741 u32 rx_page, rx_buf;
742 u64 rx_p, rx_b;
743 u64 tx_p, tx_b;
bee5af7e 744 u32 val;
41c445ff
JB		 745 int i;
746 u16 q;
747
748 if (test_bit(__I40E_DOWN, &vsi->state) ||
749 test_bit(__I40E_CONFIG_BUSY, &pf->state))
750 return;
751
752 ns = i40e_get_vsi_stats_struct(vsi);
753 ons = &vsi->net_stats_offsets;
754 es = &vsi->eth_stats;
755 oes = &vsi->eth_stats_offsets;
756
757 /* Gather up the netdev and vsi stats that the driver collects
758 * on the fly during packet processing
759 */
760 rx_b = rx_p = 0;
761 tx_b = tx_p = 0;
762 tx_restart = tx_busy = 0;
763 rx_page = 0;
764 rx_buf = 0;
980e9b11 765 rcu_read_lock();
41c445ff
JB		 766 for (q = 0; q < vsi->num_queue_pairs; q++) {
767 struct i40e_ring *p;
980e9b11
AD		 768 u64 bytes, packets;
769 unsigned int start;
770
771 /* locate Tx ring */
772 p = ACCESS_ONCE(vsi->tx_rings[q]);
773
774 do {
57a7744e 775 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 776 packets = p->stats.packets;
777 bytes = p->stats.bytes;
57a7744e 778 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 779 tx_b += bytes;
780 tx_p += packets;
781 tx_restart += p->tx_stats.restart_queue;
782 tx_busy += p->tx_stats.tx_busy;
41c445ff 783
980e9b11
AD		 784 /* Rx queue is part of the same block as Tx queue */
785 p = &p[1];
786 do {
57a7744e 787 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 788 packets = p->stats.packets;
789 bytes = p->stats.bytes;
57a7744e 790 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 791 rx_b += bytes;
792 rx_p += packets;
420136cc
MW		 793 rx_buf += p->rx_stats.alloc_buff_failed;
794 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 795 }
980e9b11 796 rcu_read_unlock();
41c445ff
JB		 797 vsi->tx_restart = tx_restart;
798 vsi->tx_busy = tx_busy;
799 vsi->rx_page_failed = rx_page;
800 vsi->rx_buf_failed = rx_buf;
801
802 ns->rx_packets = rx_p;
803 ns->rx_bytes = rx_b;
804 ns->tx_packets = tx_p;
805 ns->tx_bytes = tx_b;
806
807 i40e_update_eth_stats(vsi);
808 /* update netdev stats from eth stats */
809 ons->rx_errors = oes->rx_errors;
810 ns->rx_errors = es->rx_errors;
811 ons->tx_errors = oes->tx_errors;
812 ns->tx_errors = es->tx_errors;
813 ons->multicast = oes->rx_multicast;
814 ns->multicast = es->rx_multicast;
815 ons->tx_dropped = oes->tx_discards;
816 ns->tx_dropped = es->tx_discards;
817
818 /* Get the port data only if this is the main PF VSI */
819 if (vsi == pf->vsi[pf->lan_vsi]) {
820 struct i40e_hw_port_stats *nsd = &pf->stats;
821 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
822
823 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
824 I40E_GLPRT_GORCL(hw->port),
825 pf->stat_offsets_loaded,
826 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
827 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
828 I40E_GLPRT_GOTCL(hw->port),
829 pf->stat_offsets_loaded,
830 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
831 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
832 pf->stat_offsets_loaded,
833 &osd->eth.rx_discards,
834 &nsd->eth.rx_discards);
835 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
836 pf->stat_offsets_loaded,
837 &osd->eth.tx_discards,
838 &nsd->eth.tx_discards);
839 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
840 I40E_GLPRT_MPRCL(hw->port),
841 pf->stat_offsets_loaded,
842 &osd->eth.rx_multicast,
843 &nsd->eth.rx_multicast);
844
845 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
846 pf->stat_offsets_loaded,
847 &osd->tx_dropped_link_down,
848 &nsd->tx_dropped_link_down);
849
850 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
851 pf->stat_offsets_loaded,
852 &osd->crc_errors, &nsd->crc_errors);
853 ns->rx_crc_errors = nsd->crc_errors;
854
855 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
856 pf->stat_offsets_loaded,
857 &osd->illegal_bytes, &nsd->illegal_bytes);
858 ns->rx_errors = nsd->crc_errors
859 + nsd->illegal_bytes;
860
861 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->mac_local_faults,
864 &nsd->mac_local_faults);
865 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
866 pf->stat_offsets_loaded,
867 &osd->mac_remote_faults,
868 &nsd->mac_remote_faults);
869
870 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
871 pf->stat_offsets_loaded,
872 &osd->rx_length_errors,
873 &nsd->rx_length_errors);
874 ns->rx_length_errors = nsd->rx_length_errors;
875
876 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
877 pf->stat_offsets_loaded,
878 &osd->link_xon_rx, &nsd->link_xon_rx);
879 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->link_xon_tx, &nsd->link_xon_tx);
882 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
883 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
884 pf->stat_offsets_loaded,
885 &osd->link_xoff_tx, &nsd->link_xoff_tx);
886
887 for (i = 0; i < 8; i++) {
888 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
889 pf->stat_offsets_loaded,
890 &osd->priority_xon_rx[i],
891 &nsd->priority_xon_rx[i]);
892 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
893 pf->stat_offsets_loaded,
894 &osd->priority_xon_tx[i],
895 &nsd->priority_xon_tx[i]);
896 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
897 pf->stat_offsets_loaded,
898 &osd->priority_xoff_tx[i],
899 &nsd->priority_xoff_tx[i]);
900 i40e_stat_update32(hw,
901 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
902 pf->stat_offsets_loaded,
903 &osd->priority_xon_2_xoff[i],
904 &nsd->priority_xon_2_xoff[i]);
905 }
906
907 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
908 I40E_GLPRT_PRC64L(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->rx_size_64, &nsd->rx_size_64);
911 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
912 I40E_GLPRT_PRC127L(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->rx_size_127, &nsd->rx_size_127);
915 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
916 I40E_GLPRT_PRC255L(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->rx_size_255, &nsd->rx_size_255);
919 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
920 I40E_GLPRT_PRC511L(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->rx_size_511, &nsd->rx_size_511);
923 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
924 I40E_GLPRT_PRC1023L(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->rx_size_1023, &nsd->rx_size_1023);
927 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
928 I40E_GLPRT_PRC1522L(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->rx_size_1522, &nsd->rx_size_1522);
931 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
932 I40E_GLPRT_PRC9522L(hw->port),
933 pf->stat_offsets_loaded,
934 &osd->rx_size_big, &nsd->rx_size_big);
935
936 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
937 I40E_GLPRT_PTC64L(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->tx_size_64, &nsd->tx_size_64);
940 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
941 I40E_GLPRT_PTC127L(hw->port),
942 pf->stat_offsets_loaded,
943 &osd->tx_size_127, &nsd->tx_size_127);
944 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
945 I40E_GLPRT_PTC255L(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->tx_size_255, &nsd->tx_size_255);
948 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
949 I40E_GLPRT_PTC511L(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->tx_size_511, &nsd->tx_size_511);
952 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
953 I40E_GLPRT_PTC1023L(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_size_1023, &nsd->tx_size_1023);
956 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
957 I40E_GLPRT_PTC1522L(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->tx_size_1522, &nsd->tx_size_1522);
960 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
961 I40E_GLPRT_PTC9522L(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->tx_size_big, &nsd->tx_size_big);
964
965 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->rx_undersize, &nsd->rx_undersize);
968 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
969 pf->stat_offsets_loaded,
970 &osd->rx_fragments, &nsd->rx_fragments);
971 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->rx_oversize, &nsd->rx_oversize);
974 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
975 pf->stat_offsets_loaded,
976 &osd->rx_jabber, &nsd->rx_jabber);
bee5af7e
ASJ		 977
978 val = rd32(hw, I40E_PRTPM_EEE_STAT);
979 nsd->tx_lpi_status =
980 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
981 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
982 nsd->rx_lpi_status =
983 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
984 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
985 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
986 pf->stat_offsets_loaded,
987 &osd->tx_lpi_count, &nsd->tx_lpi_count);
988 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
989 pf->stat_offsets_loaded,
990 &osd->rx_lpi_count, &nsd->rx_lpi_count);
41c445ff
JB		 991 }
992
993 pf->stat_offsets_loaded = true;
994}
995
996/**
997 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
998 * @vsi: the VSI to be searched
999 * @macaddr: the MAC address
1000 * @vlan: the vlan
1001 * @is_vf: make sure its a vf filter, else doesn't matter
1002 * @is_netdev: make sure its a netdev filter, else doesn't matter
1003 *
1004 * Returns ptr to the filter object or NULL
1005 **/
1006static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1007 u8 *macaddr, s16 vlan,
1008 bool is_vf, bool is_netdev)
1009{
1010 struct i40e_mac_filter *f;
1011
1012 if (!vsi || !macaddr)
1013 return NULL;
1014
1015 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1016 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1017 (vlan == f->vlan) &&
1018 (!is_vf || f->is_vf) &&
1019 (!is_netdev || f->is_netdev))
1020 return f;
1021 }
1022 return NULL;
1023}
1024
1025/**
1026 * i40e_find_mac - Find a mac addr in the macvlan filters list
1027 * @vsi: the VSI to be searched
1028 * @macaddr: the MAC address we are searching for
1029 * @is_vf: make sure its a vf filter, else doesn't matter
1030 * @is_netdev: make sure its a netdev filter, else doesn't matter
1031 *
1032 * Returns the first filter with the provided MAC address or NULL if
1033 * MAC address was not found
1034 **/
1035struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1036 bool is_vf, bool is_netdev)
1037{
1038 struct i40e_mac_filter *f;
1039
1040 if (!vsi || !macaddr)
1041 return NULL;
1042
1043 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1044 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1045 (!is_vf || f->is_vf) &&
1046 (!is_netdev || f->is_netdev))
1047 return f;
1048 }
1049 return NULL;
1050}
1051
1052/**
1053 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1054 * @vsi: the VSI to be searched
1055 *
1056 * Returns true if VSI is in vlan mode or false otherwise
1057 **/
1058bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1059{
1060 struct i40e_mac_filter *f;
1061
1062 /* Only -1 for all the filters denotes not in vlan mode
1063 * so we have to go through all the list in order to make sure
1064 */
1065 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1066 if (f->vlan >= 0)
1067 return true;
1068 }
1069
1070 return false;
1071}
1072
1073/**
1074 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1075 * @vsi: the VSI to be searched
1076 * @macaddr: the mac address to be filtered
1077 * @is_vf: true if it is a vf
1078 * @is_netdev: true if it is a netdev
1079 *
1080 * Goes through all the macvlan filters and adds a
1081 * macvlan filter for each unique vlan that already exists
1082 *
1083 * Returns first filter found on success, else NULL
1084 **/
1085struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1086 bool is_vf, bool is_netdev)
1087{
1088 struct i40e_mac_filter *f;
1089
1090 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1091 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1092 is_vf, is_netdev)) {
1093 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1094 is_vf, is_netdev))
41c445ff
JB		 1095 return NULL;
1096 }
1097 }
1098
1099 return list_first_entry_or_null(&vsi->mac_filter_list,
1100 struct i40e_mac_filter, list);
1101}
1102
1103/**
1104 * i40e_add_filter - Add a mac/vlan filter to the VSI
1105 * @vsi: the VSI to be searched
1106 * @macaddr: the MAC address
1107 * @vlan: the vlan
1108 * @is_vf: make sure its a vf filter, else doesn't matter
1109 * @is_netdev: make sure its a netdev filter, else doesn't matter
1110 *
1111 * Returns ptr to the filter object or NULL when no memory available.
1112 **/
1113struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1114 u8 *macaddr, s16 vlan,
1115 bool is_vf, bool is_netdev)
1116{
1117 struct i40e_mac_filter *f;
1118
1119 if (!vsi || !macaddr)
1120 return NULL;
1121
1122 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1123 if (!f) {
1124 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1125 if (!f)
1126 goto add_filter_out;
1127
1128 memcpy(f->macaddr, macaddr, ETH_ALEN);
1129 f->vlan = vlan;
1130 f->changed = true;
1131
1132 INIT_LIST_HEAD(&f->list);
1133 list_add(&f->list, &vsi->mac_filter_list);
1134 }
1135
1136 /* increment counter and add a new flag if needed */
1137 if (is_vf) {
1138 if (!f->is_vf) {
1139 f->is_vf = true;
1140 f->counter++;
1141 }
1142 } else if (is_netdev) {
1143 if (!f->is_netdev) {
1144 f->is_netdev = true;
1145 f->counter++;
1146 }
1147 } else {
1148 f->counter++;
1149 }
1150
1151 /* changed tells sync_filters_subtask to
1152 * push the filter down to the firmware
1153 */
1154 if (f->changed) {
1155 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1156 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1157 }
1158
1159add_filter_out:
1160 return f;
1161}
1162
1163/**
1164 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1165 * @vsi: the VSI to be searched
1166 * @macaddr: the MAC address
1167 * @vlan: the vlan
1168 * @is_vf: make sure it's a vf filter, else doesn't matter
1169 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1170 **/
1171void i40e_del_filter(struct i40e_vsi *vsi,
1172 u8 *macaddr, s16 vlan,
1173 bool is_vf, bool is_netdev)
1174{
1175 struct i40e_mac_filter *f;
1176
1177 if (!vsi || !macaddr)
1178 return;
1179
1180 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1181 if (!f || f->counter == 0)
1182 return;
1183
1184 if (is_vf) {
1185 if (f->is_vf) {
1186 f->is_vf = false;
1187 f->counter--;
1188 }
1189 } else if (is_netdev) {
1190 if (f->is_netdev) {
1191 f->is_netdev = false;
1192 f->counter--;
1193 }
1194 } else {
1195 /* make sure we don't remove a filter in use by vf or netdev */
1196 int min_f = 0;
1197 min_f += (f->is_vf ? 1 : 0);
1198 min_f += (f->is_netdev ? 1 : 0);
1199
1200 if (f->counter > min_f)
1201 f->counter--;
1202 }
1203
1204 /* counter == 0 tells sync_filters_subtask to
1205 * remove the filter from the firmware's list
1206 */
1207 if (f->counter == 0) {
1208 f->changed = true;
1209 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1210 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1211 }
1212}
1213
1214/**
1215 * i40e_set_mac - NDO callback to set mac address
1216 * @netdev: network interface device structure
1217 * @p: pointer to an address structure
1218 *
1219 * Returns 0 on success, negative on failure
1220 **/
1221static int i40e_set_mac(struct net_device *netdev, void *p)
1222{
1223 struct i40e_netdev_priv *np = netdev_priv(netdev);
1224 struct i40e_vsi *vsi = np->vsi;
1225 struct sockaddr *addr = p;
1226 struct i40e_mac_filter *f;
1227
1228 if (!is_valid_ether_addr(addr->sa_data))
1229 return -EADDRNOTAVAIL;
1230
1231 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1232
1233 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1234 return 0;
1235
80f6428f
ASJ		 1236 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1237 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1238 return -EADDRNOTAVAIL;
1239
41c445ff
JB		 1240 if (vsi->type == I40E_VSI_MAIN) {
1241 i40e_status ret;
1242 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1243 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1244 addr->sa_data, NULL);
1245 if (ret) {
1246 netdev_info(netdev,
1247 "Addr change for Main VSI failed: %d\n",
1248 ret);
1249 return -EADDRNOTAVAIL;
1250 }
1251
1252 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1253 }
1254
1255 /* In order to be sure to not drop any packets, add the new address
1256 * then delete the old one.
1257 */
1258 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1259 if (!f)
1260 return -ENOMEM;
1261
1262 i40e_sync_vsi_filters(vsi);
1263 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1264 i40e_sync_vsi_filters(vsi);
1265
1266 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1267
1268 return 0;
1269}
1270
1271/**
1272 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1273 * @vsi: the VSI being setup
1274 * @ctxt: VSI context structure
1275 * @enabled_tc: Enabled TCs bitmap
1276 * @is_add: True if called before Add VSI
1277 *
1278 * Setup VSI queue mapping for enabled traffic classes.
1279 **/
1280static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1281 struct i40e_vsi_context *ctxt,
1282 u8 enabled_tc,
1283 bool is_add)
1284{
1285 struct i40e_pf *pf = vsi->back;
1286 u16 sections = 0;
1287 u8 netdev_tc = 0;
1288 u16 numtc = 0;
1289 u16 qcount;
1290 u8 offset;
1291 u16 qmap;
1292 int i;
4e3b35b0 1293 u16 num_tc_qps = 0;
41c445ff
JB		 1294
1295 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1296 offset = 0;
1297
1298 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1299 /* Find numtc from enabled TC bitmap */
1300 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1301 if (enabled_tc & (1 << i)) /* TC is enabled */
1302 numtc++;
1303 }
1304 if (!numtc) {
1305 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1306 numtc = 1;
1307 }
1308 } else {
1309 /* At least TC0 is enabled in case of non-DCB case */
1310 numtc = 1;
1311 }
1312
1313 vsi->tc_config.numtc = numtc;
1314 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1315 /* Number of queues per enabled TC */
1316 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1317 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1318
1319 /* Setup queue offset/count for all TCs for given VSI */
1320 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1321 /* See if the given TC is enabled for the given VSI */
1322 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1323 int pow, num_qps;
1324
41c445ff
JB		 1325 switch (vsi->type) {
1326 case I40E_VSI_MAIN:
4e3b35b0 1327 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1328 break;
1329 case I40E_VSI_FDIR:
1330 case I40E_VSI_SRIOV:
1331 case I40E_VSI_VMDQ2:
1332 default:
4e3b35b0 1333 qcount = num_tc_qps;
41c445ff
JB		 1334 WARN_ON(i != 0);
1335 break;
1336 }
4e3b35b0
NP		 1337 vsi->tc_config.tc_info[i].qoffset = offset;
1338 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1339
1340 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1341 num_qps = qcount;
41c445ff 1342 pow = 0;
4e3b35b0 1343 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1344 pow++;
1345 num_qps >>= 1;
1346 }
1347
1348 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1349 qmap =
1350 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1351 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1352
4e3b35b0 1353 offset += qcount;
41c445ff
JB		 1354 } else {
1355 /* TC is not enabled so set the offset to
1356 * default queue and allocate one queue
1357 * for the given TC.
1358 */
1359 vsi->tc_config.tc_info[i].qoffset = 0;
1360 vsi->tc_config.tc_info[i].qcount = 1;
1361 vsi->tc_config.tc_info[i].netdev_tc = 0;
1362
1363 qmap = 0;
1364 }
1365 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1366 }
1367
1368 /* Set actual Tx/Rx queue pairs */
1369 vsi->num_queue_pairs = offset;
1370
1371 /* Scheduler section valid can only be set for ADD VSI */
1372 if (is_add) {
1373 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1374
1375 ctxt->info.up_enable_bits = enabled_tc;
1376 }
1377 if (vsi->type == I40E_VSI_SRIOV) {
1378 ctxt->info.mapping_flags |=
1379 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1380 for (i = 0; i < vsi->num_queue_pairs; i++)
1381 ctxt->info.queue_mapping[i] =
1382 cpu_to_le16(vsi->base_queue + i);
1383 } else {
1384 ctxt->info.mapping_flags |=
1385 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1386 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1387 }
1388 ctxt->info.valid_sections |= cpu_to_le16(sections);
1389}
1390
1391/**
1392 * i40e_set_rx_mode - NDO callback to set the netdev filters
1393 * @netdev: network interface device structure
1394 **/
1395static void i40e_set_rx_mode(struct net_device *netdev)
1396{
1397 struct i40e_netdev_priv *np = netdev_priv(netdev);
1398 struct i40e_mac_filter *f, *ftmp;
1399 struct i40e_vsi *vsi = np->vsi;
1400 struct netdev_hw_addr *uca;
1401 struct netdev_hw_addr *mca;
1402 struct netdev_hw_addr *ha;
1403
1404 /* add addr if not already in the filter list */
1405 netdev_for_each_uc_addr(uca, netdev) {
1406 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1407 if (i40e_is_vsi_in_vlan(vsi))
1408 i40e_put_mac_in_vlan(vsi, uca->addr,
1409 false, true);
1410 else
1411 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1412 false, true);
1413 }
1414 }
1415
1416 netdev_for_each_mc_addr(mca, netdev) {
1417 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1418 if (i40e_is_vsi_in_vlan(vsi))
1419 i40e_put_mac_in_vlan(vsi, mca->addr,
1420 false, true);
1421 else
1422 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1423 false, true);
1424 }
1425 }
1426
1427 /* remove filter if not in netdev list */
1428 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1429 bool found = false;
1430
1431 if (!f->is_netdev)
1432 continue;
1433
1434 if (is_multicast_ether_addr(f->macaddr)) {
1435 netdev_for_each_mc_addr(mca, netdev) {
1436 if (ether_addr_equal(mca->addr, f->macaddr)) {
1437 found = true;
1438 break;
1439 }
1440 }
1441 } else {
1442 netdev_for_each_uc_addr(uca, netdev) {
1443 if (ether_addr_equal(uca->addr, f->macaddr)) {
1444 found = true;
1445 break;
1446 }
1447 }
1448
1449 for_each_dev_addr(netdev, ha) {
1450 if (ether_addr_equal(ha->addr, f->macaddr)) {
1451 found = true;
1452 break;
1453 }
1454 }
1455 }
1456 if (!found)
1457 i40e_del_filter(
1458 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1459 }
1460
1461 /* check for other flag changes */
1462 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1463 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1464 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1465 }
1466}
1467
1468/**
1469 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1470 * @vsi: ptr to the VSI
1471 *
1472 * Push any outstanding VSI filter changes through the AdminQ.
1473 *
1474 * Returns 0 or error value
1475 **/
1476int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1477{
1478 struct i40e_mac_filter *f, *ftmp;
1479 bool promisc_forced_on = false;
1480 bool add_happened = false;
1481 int filter_list_len = 0;
1482 u32 changed_flags = 0;
dcae29be 1483 i40e_status aq_ret = 0;
41c445ff
JB		 1484 struct i40e_pf *pf;
1485 int num_add = 0;
1486 int num_del = 0;
1487 u16 cmd_flags;
1488
1489 /* empty array typed pointers, kcalloc later */
1490 struct i40e_aqc_add_macvlan_element_data *add_list;
1491 struct i40e_aqc_remove_macvlan_element_data *del_list;
1492
1493 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1494 usleep_range(1000, 2000);
1495 pf = vsi->back;
1496
1497 if (vsi->netdev) {
1498 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1499 vsi->current_netdev_flags = vsi->netdev->flags;
1500 }
1501
1502 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1503 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1504
1505 filter_list_len = pf->hw.aq.asq_buf_size /
1506 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1507 del_list = kcalloc(filter_list_len,
1508 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1509 GFP_KERNEL);
1510 if (!del_list)
1511 return -ENOMEM;
1512
1513 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1514 if (!f->changed)
1515 continue;
1516
1517 if (f->counter != 0)
1518 continue;
1519 f->changed = false;
1520 cmd_flags = 0;
1521
1522 /* add to delete list */
1523 memcpy(del_list[num_del].mac_addr,
1524 f->macaddr, ETH_ALEN);
1525 del_list[num_del].vlan_tag =
1526 cpu_to_le16((u16)(f->vlan ==
1527 I40E_VLAN_ANY ? 0 : f->vlan));
1528
41c445ff
JB		 1529 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1530 del_list[num_del].flags = cmd_flags;
1531 num_del++;
1532
1533 /* unlink from filter list */
1534 list_del(&f->list);
1535 kfree(f);
1536
1537 /* flush a full buffer */
1538 if (num_del == filter_list_len) {
dcae29be 1539 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1540 vsi->seid, del_list, num_del,
1541 NULL);
1542 num_del = 0;
1543 memset(del_list, 0, sizeof(*del_list));
1544
dcae29be 1545 if (aq_ret)
41c445ff
JB		 1546 dev_info(&pf->pdev->dev,
1547 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1548 aq_ret,
41c445ff
JB		 1549 pf->hw.aq.asq_last_status);
1550 }
1551 }
1552 if (num_del) {
dcae29be 1553 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1554 del_list, num_del, NULL);
1555 num_del = 0;
1556
dcae29be 1557 if (aq_ret)
41c445ff
JB		 1558 dev_info(&pf->pdev->dev,
1559 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1560 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1561 }
1562
1563 kfree(del_list);
1564 del_list = NULL;
1565
1566 /* do all the adds now */
1567 filter_list_len = pf->hw.aq.asq_buf_size /
1568 sizeof(struct i40e_aqc_add_macvlan_element_data),
1569 add_list = kcalloc(filter_list_len,
1570 sizeof(struct i40e_aqc_add_macvlan_element_data),
1571 GFP_KERNEL);
1572 if (!add_list)
1573 return -ENOMEM;
1574
1575 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1576 if (!f->changed)
1577 continue;
1578
1579 if (f->counter == 0)
1580 continue;
1581 f->changed = false;
1582 add_happened = true;
1583 cmd_flags = 0;
1584
1585 /* add to add array */
1586 memcpy(add_list[num_add].mac_addr,
1587 f->macaddr, ETH_ALEN);
1588 add_list[num_add].vlan_tag =
1589 cpu_to_le16(
1590 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1591 add_list[num_add].queue_number = 0;
1592
1593 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1594 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1595 num_add++;
1596
1597 /* flush a full buffer */
1598 if (num_add == filter_list_len) {
dcae29be
JB		 1599 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1600 add_list, num_add,
1601 NULL);
41c445ff
JB		 1602 num_add = 0;
1603
dcae29be 1604 if (aq_ret)
41c445ff
JB		 1605 break;
1606 memset(add_list, 0, sizeof(*add_list));
1607 }
1608 }
1609 if (num_add) {
dcae29be
JB		 1610 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1611 add_list, num_add, NULL);
41c445ff
JB		 1612 num_add = 0;
1613 }
1614 kfree(add_list);
1615 add_list = NULL;
1616
dcae29be 1617 if (add_happened && (!aq_ret)) {
41c445ff 1618 /* do nothing */;
dcae29be 1619 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1620 dev_info(&pf->pdev->dev,
1621 "add filter failed, err %d, aq_err %d\n",
dcae29be 1622 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1623 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1624 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1625 &vsi->state)) {
1626 promisc_forced_on = true;
1627 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1628 &vsi->state);
1629 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1630 }
1631 }
1632 }
1633
1634 /* check for changes in promiscuous modes */
1635 if (changed_flags & IFF_ALLMULTI) {
1636 bool cur_multipromisc;
1637 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1638 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1639 vsi->seid,
1640 cur_multipromisc,
1641 NULL);
1642 if (aq_ret)
41c445ff
JB		 1643 dev_info(&pf->pdev->dev,
1644 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1645 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1646 }
1647 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1648 bool cur_promisc;
1649 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1650 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1651 &vsi->state));
dcae29be
JB		 1652 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1653 vsi->seid,
1654 cur_promisc, NULL);
1655 if (aq_ret)
41c445ff
JB		 1656 dev_info(&pf->pdev->dev,
1657 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1658 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1659 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1660 vsi->seid,
1661 cur_promisc, NULL);
1662 if (aq_ret)
1663 dev_info(&pf->pdev->dev,
1664 "set brdcast promisc failed, err %d, aq_err %d\n",
1665 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1666 }
1667
1668 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1669 return 0;
1670}
1671
1672/**
1673 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1674 * @pf: board private structure
1675 **/
1676static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1677{
1678 int v;
1679
1680 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1681 return;
1682 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1683
1684 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1685 if (pf->vsi[v] &&
1686 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1687 i40e_sync_vsi_filters(pf->vsi[v]);
1688 }
1689}
1690
1691/**
1692 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1693 * @netdev: network interface device structure
1694 * @new_mtu: new value for maximum frame size
1695 *
1696 * Returns 0 on success, negative on failure
1697 **/
1698static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1699{
1700 struct i40e_netdev_priv *np = netdev_priv(netdev);
1701 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1702 struct i40e_vsi *vsi = np->vsi;
1703
1704 /* MTU < 68 is an error and causes problems on some kernels */
1705 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1706 return -EINVAL;
1707
1708 netdev_info(netdev, "changing MTU from %d to %d\n",
1709 netdev->mtu, new_mtu);
1710 netdev->mtu = new_mtu;
1711 if (netif_running(netdev))
1712 i40e_vsi_reinit_locked(vsi);
1713
1714 return 0;
1715}
1716
beb0dff1
JK		 1717/**
1718 * i40e_ioctl - Access the hwtstamp interface
1719 * @netdev: network interface device structure
1720 * @ifr: interface request data
1721 * @cmd: ioctl command
1722 **/
1723int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1724{
1725 struct i40e_netdev_priv *np = netdev_priv(netdev);
1726 struct i40e_pf *pf = np->vsi->back;
1727
1728 switch (cmd) {
1729 case SIOCGHWTSTAMP:
1730 return i40e_ptp_get_ts_config(pf, ifr);
1731 case SIOCSHWTSTAMP:
1732 return i40e_ptp_set_ts_config(pf, ifr);
1733 default:
1734 return -EOPNOTSUPP;
1735 }
1736}
1737
41c445ff
JB		 1738/**
1739 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1740 * @vsi: the vsi being adjusted
1741 **/
1742void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1743{
1744 struct i40e_vsi_context ctxt;
1745 i40e_status ret;
1746
1747 if ((vsi->info.valid_sections &
1748 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1749 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1750 return; /* already enabled */
1751
1752 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1753 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1754 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1755
1756 ctxt.seid = vsi->seid;
1757 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1758 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1759 if (ret) {
1760 dev_info(&vsi->back->pdev->dev,
1761 "%s: update vsi failed, aq_err=%d\n",
1762 __func__, vsi->back->hw.aq.asq_last_status);
1763 }
1764}
1765
1766/**
1767 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1768 * @vsi: the vsi being adjusted
1769 **/
1770void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1771{
1772 struct i40e_vsi_context ctxt;
1773 i40e_status ret;
1774
1775 if ((vsi->info.valid_sections &
1776 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1777 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1778 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1779 return; /* already disabled */
1780
1781 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1782 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1783 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1784
1785 ctxt.seid = vsi->seid;
1786 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1787 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1788 if (ret) {
1789 dev_info(&vsi->back->pdev->dev,
1790 "%s: update vsi failed, aq_err=%d\n",
1791 __func__, vsi->back->hw.aq.asq_last_status);
1792 }
1793}
1794
1795/**
1796 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1797 * @netdev: network interface to be adjusted
1798 * @features: netdev features to test if VLAN offload is enabled or not
1799 **/
1800static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1801{
1802 struct i40e_netdev_priv *np = netdev_priv(netdev);
1803 struct i40e_vsi *vsi = np->vsi;
1804
1805 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1806 i40e_vlan_stripping_enable(vsi);
1807 else
1808 i40e_vlan_stripping_disable(vsi);
1809}
1810
1811/**
1812 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1813 * @vsi: the vsi being configured
1814 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1815 **/
1816int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1817{
1818 struct i40e_mac_filter *f, *add_f;
1819 bool is_netdev, is_vf;
41c445ff
JB		 1820
1821 is_vf = (vsi->type == I40E_VSI_SRIOV);
1822 is_netdev = !!(vsi->netdev);
1823
1824 if (is_netdev) {
1825 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1826 is_vf, is_netdev);
1827 if (!add_f) {
1828 dev_info(&vsi->back->pdev->dev,
1829 "Could not add vlan filter %d for %pM\n",
1830 vid, vsi->netdev->dev_addr);
1831 return -ENOMEM;
1832 }
1833 }
1834
1835 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1836 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1837 if (!add_f) {
1838 dev_info(&vsi->back->pdev->dev,
1839 "Could not add vlan filter %d for %pM\n",
1840 vid, f->macaddr);
1841 return -ENOMEM;
1842 }
1843 }
1844
41c445ff
JB		 1845 /* Now if we add a vlan tag, make sure to check if it is the first
1846 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1847 * with 0, so we now accept untagged and specified tagged traffic
1848 * (and not any taged and untagged)
1849 */
1850 if (vid > 0) {
1851 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1852 I40E_VLAN_ANY,
1853 is_vf, is_netdev)) {
1854 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1855 I40E_VLAN_ANY, is_vf, is_netdev);
1856 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1857 is_vf, is_netdev);
1858 if (!add_f) {
1859 dev_info(&vsi->back->pdev->dev,
1860 "Could not add filter 0 for %pM\n",
1861 vsi->netdev->dev_addr);
1862 return -ENOMEM;
1863 }
1864 }
8d82a7c5 1865 }
41c445ff 1866
8d82a7c5
GR		 1867 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1868 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1869 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1870 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1871 is_vf, is_netdev)) {
1872 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1873 is_vf, is_netdev);
1874 add_f = i40e_add_filter(vsi, f->macaddr,
1875 0, is_vf, is_netdev);
1876 if (!add_f) {
1877 dev_info(&vsi->back->pdev->dev,
1878 "Could not add filter 0 for %pM\n",
1879 f->macaddr);
1880 return -ENOMEM;
1881 }
1882 }
1883 }
41c445ff
JB		 1884 }
1885
80f6428f
ASJ		 1886 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1887 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1888 return 0;
1889
1890 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1891}
1892
1893/**
1894 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1895 * @vsi: the vsi being configured
1896 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1897 *
1898 * Return: 0 on success or negative otherwise
41c445ff
JB		 1899 **/
1900int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1901{
1902 struct net_device *netdev = vsi->netdev;
1903 struct i40e_mac_filter *f, *add_f;
1904 bool is_vf, is_netdev;
1905 int filter_count = 0;
41c445ff
JB		 1906
1907 is_vf = (vsi->type == I40E_VSI_SRIOV);
1908 is_netdev = !!(netdev);
1909
1910 if (is_netdev)
1911 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1912
1913 list_for_each_entry(f, &vsi->mac_filter_list, list)
1914 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1915
41c445ff
JB		 1916 /* go through all the filters for this VSI and if there is only
1917 * vid == 0 it means there are no other filters, so vid 0 must
1918 * be replaced with -1. This signifies that we should from now
1919 * on accept any traffic (with any tag present, or untagged)
1920 */
1921 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1922 if (is_netdev) {
1923 if (f->vlan &&
1924 ether_addr_equal(netdev->dev_addr, f->macaddr))
1925 filter_count++;
1926 }
1927
1928 if (f->vlan)
1929 filter_count++;
1930 }
1931
1932 if (!filter_count && is_netdev) {
1933 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1934 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1935 is_vf, is_netdev);
1936 if (!f) {
1937 dev_info(&vsi->back->pdev->dev,
1938 "Could not add filter %d for %pM\n",
1939 I40E_VLAN_ANY, netdev->dev_addr);
1940 return -ENOMEM;
1941 }
1942 }
1943
1944 if (!filter_count) {
1945 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1946 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1947 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1948 is_vf, is_netdev);
1949 if (!add_f) {
1950 dev_info(&vsi->back->pdev->dev,
1951 "Could not add filter %d for %pM\n",
1952 I40E_VLAN_ANY, f->macaddr);
1953 return -ENOMEM;
1954 }
1955 }
1956 }
1957
80f6428f
ASJ		 1958 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1959 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1960 return 0;
1961
41c445ff
JB		 1962 return i40e_sync_vsi_filters(vsi);
1963}
1964
1965/**
1966 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1967 * @netdev: network interface to be adjusted
1968 * @vid: vlan id to be added
078b5876
JB		 1969 *
1970 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1971 **/
1972static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1973 __always_unused __be16 proto, u16 vid)
1974{
1975 struct i40e_netdev_priv *np = netdev_priv(netdev);
1976 struct i40e_vsi *vsi = np->vsi;
078b5876 1977 int ret = 0;
41c445ff
JB		 1978
1979 if (vid > 4095)
078b5876
JB		 1980 return -EINVAL;
1981
1982 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1983
6982d429
ASJ		 1984 /* If the network stack called us with vid = 0 then
1985 * it is asking to receive priority tagged packets with
1986 * vlan id 0. Our HW receives them by default when configured
1987 * to receive untagged packets so there is no need to add an
1988 * extra filter for vlan 0 tagged packets.
41c445ff 1989 */
6982d429
ASJ		 1990 if (vid)
1991 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 1992
078b5876
JB		 1993 if (!ret && (vid < VLAN_N_VID))
1994 set_bit(vid, vsi->active_vlans);
41c445ff 1995
078b5876 1996 return ret;
41c445ff
JB		 1997}
1998
1999/**
2000 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2001 * @netdev: network interface to be adjusted
2002 * @vid: vlan id to be removed
078b5876 2003 *
fdfd943e 2004 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2005 **/
2006static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2007 __always_unused __be16 proto, u16 vid)
2008{
2009 struct i40e_netdev_priv *np = netdev_priv(netdev);
2010 struct i40e_vsi *vsi = np->vsi;
2011
078b5876
JB		 2012 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2013
41c445ff
JB		 2014 /* return code is ignored as there is nothing a user
2015 * can do about failure to remove and a log message was
078b5876 2016 * already printed from the other function
41c445ff
JB		 2017 */
2018 i40e_vsi_kill_vlan(vsi, vid);
2019
2020 clear_bit(vid, vsi->active_vlans);
078b5876 2021
41c445ff
JB		 2022 return 0;
2023}
2024
2025/**
2026 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2027 * @vsi: the vsi being brought back up
2028 **/
2029static void i40e_restore_vlan(struct i40e_vsi *vsi)
2030{
2031 u16 vid;
2032
2033 if (!vsi->netdev)
2034 return;
2035
2036 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2037
2038 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2039 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2040 vid);
2041}
2042
2043/**
2044 * i40e_vsi_add_pvid - Add pvid for the VSI
2045 * @vsi: the vsi being adjusted
2046 * @vid: the vlan id to set as a PVID
2047 **/
dcae29be 2048int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2049{
2050 struct i40e_vsi_context ctxt;
dcae29be 2051 i40e_status aq_ret;
41c445ff
JB		 2052
2053 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2054 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2055 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2056 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2057 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2058
2059 ctxt.seid = vsi->seid;
2060 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2061 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2062 if (aq_ret) {
41c445ff
JB		 2063 dev_info(&vsi->back->pdev->dev,
2064 "%s: update vsi failed, aq_err=%d\n",
2065 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2066 return -ENOENT;
41c445ff
JB		 2067 }
2068
dcae29be 2069 return 0;
41c445ff
JB		 2070}
2071
2072/**
2073 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2074 * @vsi: the vsi being adjusted
2075 *
2076 * Just use the vlan_rx_register() service to put it back to normal
2077 **/
2078void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2079{
6c12fcbf
GR		 2080 i40e_vlan_stripping_disable(vsi);
2081
41c445ff 2082 vsi->info.pvid = 0;
41c445ff
JB		 2083}
2084
2085/**
2086 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2087 * @vsi: ptr to the VSI
2088 *
2089 * If this function returns with an error, then it's possible one or
2090 * more of the rings is populated (while the rest are not). It is the
2091 * callers duty to clean those orphaned rings.
2092 *
2093 * Return 0 on success, negative on failure
2094 **/
2095static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2096{
2097 int i, err = 0;
2098
2099 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2100 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2101
2102 return err;
2103}
2104
2105/**
2106 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2107 * @vsi: ptr to the VSI
2108 *
2109 * Free VSI's transmit software resources
2110 **/
2111static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2112{
2113 int i;
2114
8e9dca53
GR		 2115 if (!vsi->tx_rings)
2116 return;
2117
41c445ff 2118 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2119 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2120 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2121}
2122
2123/**
2124 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2125 * @vsi: ptr to the VSI
2126 *
2127 * If this function returns with an error, then it's possible one or
2128 * more of the rings is populated (while the rest are not). It is the
2129 * callers duty to clean those orphaned rings.
2130 *
2131 * Return 0 on success, negative on failure
2132 **/
2133static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2134{
2135 int i, err = 0;
2136
2137 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2138 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2139 return err;
2140}
2141
2142/**
2143 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2144 * @vsi: ptr to the VSI
2145 *
2146 * Free all receive software resources
2147 **/
2148static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2149{
2150 int i;
2151
8e9dca53
GR		 2152 if (!vsi->rx_rings)
2153 return;
2154
41c445ff 2155 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2156 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2157 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2158}
2159
2160/**
2161 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2162 * @ring: The Tx ring to configure
2163 *
2164 * Configure the Tx descriptor ring in the HMC context.
2165 **/
2166static int i40e_configure_tx_ring(struct i40e_ring *ring)
2167{
2168 struct i40e_vsi *vsi = ring->vsi;
2169 u16 pf_q = vsi->base_queue + ring->queue_index;
2170 struct i40e_hw *hw = &vsi->back->hw;
2171 struct i40e_hmc_obj_txq tx_ctx;
2172 i40e_status err = 0;
2173 u32 qtx_ctl = 0;
2174
2175 /* some ATR related tx ring init */
60ea5f83 2176 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2177 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2178 ring->atr_count = 0;
2179 } else {
2180 ring->atr_sample_rate = 0;
2181 }
2182
2183 /* initialize XPS */
2184 if (ring->q_vector && ring->netdev &&
4e3b35b0 2185 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2186 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2187 netif_set_xps_queue(ring->netdev,
2188 &ring->q_vector->affinity_mask,
2189 ring->queue_index);
2190
2191 /* clear the context structure first */
2192 memset(&tx_ctx, 0, sizeof(tx_ctx));
2193
2194 tx_ctx.new_context = 1;
2195 tx_ctx.base = (ring->dma / 128);
2196 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2197 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2198 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2199 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2200 /* FDIR VSI tx ring can still use RS bit and writebacks */
2201 if (vsi->type != I40E_VSI_FDIR)
2202 tx_ctx.head_wb_ena = 1;
2203 tx_ctx.head_wb_addr = ring->dma +
2204 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2205
2206 /* As part of VSI creation/update, FW allocates certain
2207 * Tx arbitration queue sets for each TC enabled for
2208 * the VSI. The FW returns the handles to these queue
2209 * sets as part of the response buffer to Add VSI,
2210 * Update VSI, etc. AQ commands. It is expected that
2211 * these queue set handles be associated with the Tx
2212 * queues by the driver as part of the TX queue context
2213 * initialization. This has to be done regardless of
2214 * DCB as by default everything is mapped to TC0.
2215 */
2216 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2217 tx_ctx.rdylist_act = 0;
2218
2219 /* clear the context in the HMC */
2220 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2221 if (err) {
2222 dev_info(&vsi->back->pdev->dev,
2223 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2224 ring->queue_index, pf_q, err);
2225 return -ENOMEM;
2226 }
2227
2228 /* set the context in the HMC */
2229 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2230 if (err) {
2231 dev_info(&vsi->back->pdev->dev,
2232 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2233 ring->queue_index, pf_q, err);
2234 return -ENOMEM;
2235 }
2236
2237 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2238 if (vsi->type == I40E_VSI_VMDQ2)
2239 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2240 else
2241 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2242 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2243 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2244 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2245 i40e_flush(hw);
2246
2247 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2248
2249 /* cache tail off for easier writes later */
2250 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2251
2252 return 0;
2253}
2254
2255/**
2256 * i40e_configure_rx_ring - Configure a receive ring context
2257 * @ring: The Rx ring to configure
2258 *
2259 * Configure the Rx descriptor ring in the HMC context.
2260 **/
2261static int i40e_configure_rx_ring(struct i40e_ring *ring)
2262{
2263 struct i40e_vsi *vsi = ring->vsi;
2264 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2265 u16 pf_q = vsi->base_queue + ring->queue_index;
2266 struct i40e_hw *hw = &vsi->back->hw;
2267 struct i40e_hmc_obj_rxq rx_ctx;
2268 i40e_status err = 0;
2269
2270 ring->state = 0;
2271
2272 /* clear the context structure first */
2273 memset(&rx_ctx, 0, sizeof(rx_ctx));
2274
2275 ring->rx_buf_len = vsi->rx_buf_len;
2276 ring->rx_hdr_len = vsi->rx_hdr_len;
2277
2278 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2279 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2280
2281 rx_ctx.base = (ring->dma / 128);
2282 rx_ctx.qlen = ring->count;
2283
2284 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2285 set_ring_16byte_desc_enabled(ring);
2286 rx_ctx.dsize = 0;
2287 } else {
2288 rx_ctx.dsize = 1;
2289 }
2290
2291 rx_ctx.dtype = vsi->dtype;
2292 if (vsi->dtype) {
2293 set_ring_ps_enabled(ring);
2294 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2295 I40E_RX_SPLIT_IP |
2296 I40E_RX_SPLIT_TCP_UDP |
2297 I40E_RX_SPLIT_SCTP;
2298 } else {
2299 rx_ctx.hsplit_0 = 0;
2300 }
2301
2302 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2303 (chain_len * ring->rx_buf_len));
2304 rx_ctx.tphrdesc_ena = 1;
2305 rx_ctx.tphwdesc_ena = 1;
2306 rx_ctx.tphdata_ena = 1;
2307 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2308 if (hw->revision_id == 0)
2309 rx_ctx.lrxqthresh = 0;
2310 else
2311 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2312 rx_ctx.crcstrip = 1;
2313 rx_ctx.l2tsel = 1;
2314 rx_ctx.showiv = 1;
2315
2316 /* clear the context in the HMC */
2317 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2318 if (err) {
2319 dev_info(&vsi->back->pdev->dev,
2320 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2321 ring->queue_index, pf_q, err);
2322 return -ENOMEM;
2323 }
2324
2325 /* set the context in the HMC */
2326 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2327 if (err) {
2328 dev_info(&vsi->back->pdev->dev,
2329 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2330 ring->queue_index, pf_q, err);
2331 return -ENOMEM;
2332 }
2333
2334 /* cache tail for quicker writes, and clear the reg before use */
2335 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2336 writel(0, ring->tail);
2337
2338 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2339
2340 return 0;
2341}
2342
2343/**
2344 * i40e_vsi_configure_tx - Configure the VSI for Tx
2345 * @vsi: VSI structure describing this set of rings and resources
2346 *
2347 * Configure the Tx VSI for operation.
2348 **/
2349static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2350{
2351 int err = 0;
2352 u16 i;
2353
9f65e15b
AD		 2354 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2355 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2356
2357 return err;
2358}
2359
2360/**
2361 * i40e_vsi_configure_rx - Configure the VSI for Rx
2362 * @vsi: the VSI being configured
2363 *
2364 * Configure the Rx VSI for operation.
2365 **/
2366static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2367{
2368 int err = 0;
2369 u16 i;
2370
2371 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2372 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2373 + ETH_FCS_LEN + VLAN_HLEN;
2374 else
2375 vsi->max_frame = I40E_RXBUFFER_2048;
2376
2377 /* figure out correct receive buffer length */
2378 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2379 I40E_FLAG_RX_PS_ENABLED)) {
2380 case I40E_FLAG_RX_1BUF_ENABLED:
2381 vsi->rx_hdr_len = 0;
2382 vsi->rx_buf_len = vsi->max_frame;
2383 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2384 break;
2385 case I40E_FLAG_RX_PS_ENABLED:
2386 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2387 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2388 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2389 break;
2390 default:
2391 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2392 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2393 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2394 break;
2395 }
2396
2397 /* round up for the chip's needs */
2398 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2399 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2400 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2401 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2402
2403 /* set up individual rings */
2404 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2405 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2406
2407 return err;
2408}
2409
2410/**
2411 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2412 * @vsi: ptr to the VSI
2413 **/
2414static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2415{
2416 u16 qoffset, qcount;
2417 int i, n;
2418
2419 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2420 return;
2421
2422 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2423 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2424 continue;
2425
2426 qoffset = vsi->tc_config.tc_info[n].qoffset;
2427 qcount = vsi->tc_config.tc_info[n].qcount;
2428 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2429 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2430 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2431 rx_ring->dcb_tc = n;
2432 tx_ring->dcb_tc = n;
2433 }
2434 }
2435}
2436
2437/**
2438 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2439 * @vsi: ptr to the VSI
2440 **/
2441static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2442{
2443 if (vsi->netdev)
2444 i40e_set_rx_mode(vsi->netdev);
2445}
2446
17a73f6b
JG		 2447/**
2448 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2449 * @vsi: Pointer to the targeted VSI
2450 *
2451 * This function replays the hlist on the hw where all the SB Flow Director
2452 * filters were saved.
2453 **/
2454static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2455{
2456 struct i40e_fdir_filter *filter;
2457 struct i40e_pf *pf = vsi->back;
2458 struct hlist_node *node;
2459
55a5e60b
ASJ		 2460 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2461 return;
2462
17a73f6b
JG		 2463 hlist_for_each_entry_safe(filter, node,
2464 &pf->fdir_filter_list, fdir_node) {
2465 i40e_add_del_fdir(vsi, filter, true);
2466 }
2467}
2468
41c445ff
JB		 2469/**
2470 * i40e_vsi_configure - Set up the VSI for action
2471 * @vsi: the VSI being configured
2472 **/
2473static int i40e_vsi_configure(struct i40e_vsi *vsi)
2474{
2475 int err;
2476
2477 i40e_set_vsi_rx_mode(vsi);
2478 i40e_restore_vlan(vsi);
2479 i40e_vsi_config_dcb_rings(vsi);
2480 err = i40e_vsi_configure_tx(vsi);
2481 if (!err)
2482 err = i40e_vsi_configure_rx(vsi);
2483
2484 return err;
2485}
2486
2487/**
2488 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2489 * @vsi: the VSI being configured
2490 **/
2491static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2492{
2493 struct i40e_pf *pf = vsi->back;
2494 struct i40e_q_vector *q_vector;
2495 struct i40e_hw *hw = &pf->hw;
2496 u16 vector;
2497 int i, q;
2498 u32 val;
2499 u32 qp;
2500
2501 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2502 * and PFINT_LNKLSTn registers, e.g.:
2503 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2504 */
2505 qp = vsi->base_queue;
2506 vector = vsi->base_vector;
493fb300
AD		 2507 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2508 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2509 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2510 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2511 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2512 q_vector->rx.itr);
2513 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2514 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2515 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2516 q_vector->tx.itr);
2517
2518 /* Linked list for the queuepairs assigned to this vector */
2519 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2520 for (q = 0; q < q_vector->num_ringpairs; q++) {
2521 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2522 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2523 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2524 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2525 (I40E_QUEUE_TYPE_TX
2526 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2527
2528 wr32(hw, I40E_QINT_RQCTL(qp), val);
2529
2530 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2531 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2532 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2533 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2534 (I40E_QUEUE_TYPE_RX
2535 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2536
2537 /* Terminate the linked list */
2538 if (q == (q_vector->num_ringpairs - 1))
2539 val |= (I40E_QUEUE_END_OF_LIST
2540 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2541
2542 wr32(hw, I40E_QINT_TQCTL(qp), val);
2543 qp++;
2544 }
2545 }
2546
2547 i40e_flush(hw);
2548}
2549
2550/**
2551 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2552 * @hw: ptr to the hardware info
2553 **/
2554static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2555{
2556 u32 val;
2557
2558 /* clear things first */
2559 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2560 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2561
2562 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2563 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2564 I40E_PFINT_ICR0_ENA_GRST_MASK |
2565 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2566 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2567 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2568 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2569 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2570 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2571 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2572
2573 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2574
2575 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2576 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2577 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2578
2579 /* OTHER_ITR_IDX = 0 */
2580 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2581}
2582
2583/**
2584 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2585 * @vsi: the VSI being configured
2586 **/
2587static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2588{
493fb300 2589 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2590 struct i40e_pf *pf = vsi->back;
2591 struct i40e_hw *hw = &pf->hw;
2592 u32 val;
2593
2594 /* set the ITR configuration */
2595 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2596 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2597 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2598 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2599 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2600 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2601
2602 i40e_enable_misc_int_causes(hw);
2603
2604 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2605 wr32(hw, I40E_PFINT_LNKLST0, 0);
2606
f29eaa3d 2607 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2608 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2609 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2610 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2611
2612 wr32(hw, I40E_QINT_RQCTL(0), val);
2613
2614 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2615 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2616 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2617
2618 wr32(hw, I40E_QINT_TQCTL(0), val);
2619 i40e_flush(hw);
2620}
2621
2ef28cfb
MW		 2622/**
2623 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2624 * @pf: board private structure
2625 **/
2626void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2627{
2628 struct i40e_hw *hw = &pf->hw;
2629
2630 wr32(hw, I40E_PFINT_DYN_CTL0,
2631 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2632 i40e_flush(hw);
2633}
2634
41c445ff
JB		 2635/**
2636 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2637 * @pf: board private structure
2638 **/
116a57d4 2639void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2640{
2641 struct i40e_hw *hw = &pf->hw;
2642 u32 val;
2643
2644 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2645 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2646 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2647
2648 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2649 i40e_flush(hw);
2650}
2651
2652/**
2653 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2654 * @vsi: pointer to a vsi
2655 * @vector: enable a particular Hw Interrupt vector
2656 **/
2657void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2658{
2659 struct i40e_pf *pf = vsi->back;
2660 struct i40e_hw *hw = &pf->hw;
2661 u32 val;
2662
2663 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2664 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2665 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2666 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2667 /* skip the flush */
41c445ff
JB		 2668}
2669
2670/**
2671 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2672 * @irq: interrupt number
2673 * @data: pointer to a q_vector
2674 **/
2675static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2676{
2677 struct i40e_q_vector *q_vector = data;
2678
cd0b6fa6 2679 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2680 return IRQ_HANDLED;
2681
2682 napi_schedule(&q_vector->napi);
2683
2684 return IRQ_HANDLED;
2685}
2686
41c445ff
JB		 2687/**
2688 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2689 * @vsi: the VSI being configured
2690 * @basename: name for the vector
2691 *
2692 * Allocates MSI-X vectors and requests interrupts from the kernel.
2693 **/
2694static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2695{
2696 int q_vectors = vsi->num_q_vectors;
2697 struct i40e_pf *pf = vsi->back;
2698 int base = vsi->base_vector;
2699 int rx_int_idx = 0;
2700 int tx_int_idx = 0;
2701 int vector, err;
2702
2703 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2704 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2705
cd0b6fa6 2706 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2707 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2708 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2709 tx_int_idx++;
cd0b6fa6 2710 } else if (q_vector->rx.ring) {
41c445ff
JB		 2711 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2712 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2713 } else if (q_vector->tx.ring) {
41c445ff
JB		 2714 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2715 "%s-%s-%d", basename, "tx", tx_int_idx++);
2716 } else {
2717 /* skip this unused q_vector */
2718 continue;
2719 }
2720 err = request_irq(pf->msix_entries[base + vector].vector,
2721 vsi->irq_handler,
2722 0,
2723 q_vector->name,
2724 q_vector);
2725 if (err) {
2726 dev_info(&pf->pdev->dev,
2727 "%s: request_irq failed, error: %d\n",
2728 __func__, err);
2729 goto free_queue_irqs;
2730 }
2731 /* assign the mask for this irq */
2732 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2733 &q_vector->affinity_mask);
2734 }
2735
2736 return 0;
2737
2738free_queue_irqs:
2739 while (vector) {
2740 vector--;
2741 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2742 NULL);
2743 free_irq(pf->msix_entries[base + vector].vector,
2744 &(vsi->q_vectors[vector]));
2745 }
2746 return err;
2747}
2748
2749/**
2750 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2751 * @vsi: the VSI being un-configured
2752 **/
2753static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2754{
2755 struct i40e_pf *pf = vsi->back;
2756 struct i40e_hw *hw = &pf->hw;
2757 int base = vsi->base_vector;
2758 int i;
2759
2760 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2761 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2762 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2763 }
2764
2765 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2766 for (i = vsi->base_vector;
2767 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2768 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2769
2770 i40e_flush(hw);
2771 for (i = 0; i < vsi->num_q_vectors; i++)
2772 synchronize_irq(pf->msix_entries[i + base].vector);
2773 } else {
2774 /* Legacy and MSI mode - this stops all interrupt handling */
2775 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2776 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2777 i40e_flush(hw);
2778 synchronize_irq(pf->pdev->irq);
2779 }
2780}
2781
2782/**
2783 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2784 * @vsi: the VSI being configured
2785 **/
2786static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2787{
2788 struct i40e_pf *pf = vsi->back;
2789 int i;
2790
2791 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2792 for (i = vsi->base_vector;
2793 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2794 i40e_irq_dynamic_enable(vsi, i);
2795 } else {
2796 i40e_irq_dynamic_enable_icr0(pf);
2797 }
2798
1022cb6c 2799 i40e_flush(&pf->hw);
41c445ff
JB		 2800 return 0;
2801}
2802
2803/**
2804 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2805 * @pf: board private structure
2806 **/
2807static void i40e_stop_misc_vector(struct i40e_pf *pf)
2808{
2809 /* Disable ICR 0 */
2810 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2811 i40e_flush(&pf->hw);
2812}
2813
2814/**
2815 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2816 * @irq: interrupt number
2817 * @data: pointer to a q_vector
2818 *
2819 * This is the handler used for all MSI/Legacy interrupts, and deals
2820 * with both queue and non-queue interrupts. This is also used in
2821 * MSIX mode to handle the non-queue interrupts.
2822 **/
2823static irqreturn_t i40e_intr(int irq, void *data)
2824{
2825 struct i40e_pf *pf = (struct i40e_pf *)data;
2826 struct i40e_hw *hw = &pf->hw;
5e823066 2827 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2828 u32 icr0, icr0_remaining;
2829 u32 val, ena_mask;
2830
2831 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2832 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2833
116a57d4
SN		 2834 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2835 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2836 goto enable_intr;
41c445ff 2837
cd92e72f
SN		 2838 /* if interrupt but no bits showing, must be SWINT */
2839 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2840 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2841 pf->sw_int_count++;
2842
41c445ff
JB		 2843 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2844 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2845
2846 /* temporarily disable queue cause for NAPI processing */
2847 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2848 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2849 wr32(hw, I40E_QINT_RQCTL(0), qval);
2850
2851 qval = rd32(hw, I40E_QINT_TQCTL(0));
2852 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2853 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2854
2855 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2856 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2857 }
2858
2859 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2860 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2861 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2862 }
2863
2864 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2865 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2866 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2867 }
2868
2869 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2870 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2871 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2872 }
2873
2874 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2875 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2876 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2877 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2878 val = rd32(hw, I40E_GLGEN_RSTAT);
2879 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2880 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2881 if (val == I40E_RESET_CORER) {
41c445ff 2882 pf->corer_count++;
4eb3f768 2883 } else if (val == I40E_RESET_GLOBR) {
41c445ff 2884 pf->globr_count++;
4eb3f768 2885 } else if (val == I40E_RESET_EMPR) {
41c445ff 2886 pf->empr_count++;
4eb3f768
SN		 2887 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
2888 }
41c445ff
JB		 2889 }
2890
9c010ee0
ASJ		 2891 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2892 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2893 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2894 }
2895
beb0dff1
JK		 2896 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2897 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2898
2899 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
2900 ena_mask &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2901 i40e_ptp_tx_hwtstamp(pf);
2902 prttsyn_stat &= ~I40E_PRTTSYN_STAT_0_TXTIME_MASK;
2903 }
2904
2905 wr32(hw, I40E_PRTTSYN_STAT_0, prttsyn_stat);
2906 }
2907
41c445ff
JB		 2908 /* If a critical error is pending we have no choice but to reset the
2909 * device.
2910 * Report and mask out any remaining unexpected interrupts.
2911 */
2912 icr0_remaining = icr0 & ena_mask;
2913 if (icr0_remaining) {
2914 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2915 icr0_remaining);
9c010ee0 2916 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 2917 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 2918 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 2919 dev_info(&pf->pdev->dev, "device will be reset\n");
2920 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2921 i40e_service_event_schedule(pf);
41c445ff
JB		 2922 }
2923 ena_mask &= ~icr0_remaining;
2924 }
5e823066 2925 ret = IRQ_HANDLED;
41c445ff 2926
5e823066 2927enable_intr:
41c445ff
JB		 2928 /* re-enable interrupt causes */
2929 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2930 if (!test_bit(__I40E_DOWN, &pf->state)) {
2931 i40e_service_event_schedule(pf);
2932 i40e_irq_dynamic_enable_icr0(pf);
2933 }
2934
5e823066 2935 return ret;
41c445ff
JB		 2936}
2937
cbf61325
ASJ		 2938/**
2939 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2940 * @tx_ring: tx ring to clean
2941 * @budget: how many cleans we're allowed
2942 *
2943 * Returns true if there's any budget left (e.g. the clean is finished)
2944 **/
2945static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
2946{
2947 struct i40e_vsi *vsi = tx_ring->vsi;
2948 u16 i = tx_ring->next_to_clean;
2949 struct i40e_tx_buffer *tx_buf;
2950 struct i40e_tx_desc *tx_desc;
2951
2952 tx_buf = &tx_ring->tx_bi[i];
2953 tx_desc = I40E_TX_DESC(tx_ring, i);
2954 i -= tx_ring->count;
2955
2956 do {
2957 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
2958
2959 /* if next_to_watch is not set then there is no work pending */
2960 if (!eop_desc)
2961 break;
2962
2963 /* prevent any other reads prior to eop_desc */
2964 read_barrier_depends();
2965
2966 /* if the descriptor isn't done, no work yet to do */
2967 if (!(eop_desc->cmd_type_offset_bsz &
2968 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
2969 break;
2970
2971 /* clear next_to_watch to prevent false hangs */
2972 tx_buf->next_to_watch = NULL;
2973
2974 /* unmap skb header data */
2975 dma_unmap_single(tx_ring->dev,
2976 dma_unmap_addr(tx_buf, dma),
2977 dma_unmap_len(tx_buf, len),
2978 DMA_TO_DEVICE);
2979
2980 dma_unmap_len_set(tx_buf, len, 0);
2981
2982
2983 /* move to the next desc and buffer to clean */
2984 tx_buf++;
2985 tx_desc++;
2986 i++;
2987 if (unlikely(!i)) {
2988 i -= tx_ring->count;
2989 tx_buf = tx_ring->tx_bi;
2990 tx_desc = I40E_TX_DESC(tx_ring, 0);
2991 }
2992
2993 /* update budget accounting */
2994 budget--;
2995 } while (likely(budget));
2996
2997 i += tx_ring->count;
2998 tx_ring->next_to_clean = i;
2999
3000 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3001 i40e_irq_dynamic_enable(vsi,
3002 tx_ring->q_vector->v_idx + vsi->base_vector);
3003 }
3004 return budget > 0;
3005}
3006
3007/**
3008 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3009 * @irq: interrupt number
3010 * @data: pointer to a q_vector
3011 **/
3012static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3013{
3014 struct i40e_q_vector *q_vector = data;
3015 struct i40e_vsi *vsi;
3016
3017 if (!q_vector->tx.ring)
3018 return IRQ_HANDLED;
3019
3020 vsi = q_vector->tx.ring->vsi;
3021 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3022
3023 return IRQ_HANDLED;
3024}
3025
41c445ff 3026/**
cd0b6fa6 3027 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3028 * @vsi: the VSI being configured
3029 * @v_idx: vector index
cd0b6fa6 3030 * @qp_idx: queue pair index
41c445ff 3031 **/
cd0b6fa6 3032static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3033{
493fb300 3034 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3035 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3036 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3037
3038 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3039 tx_ring->next = q_vector->tx.ring;
3040 q_vector->tx.ring = tx_ring;
41c445ff 3041 q_vector->tx.count++;
cd0b6fa6
AD		 3042
3043 rx_ring->q_vector = q_vector;
3044 rx_ring->next = q_vector->rx.ring;
3045 q_vector->rx.ring = rx_ring;
3046 q_vector->rx.count++;
41c445ff
JB		 3047}
3048
3049/**
3050 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3051 * @vsi: the VSI being configured
3052 *
3053 * This function maps descriptor rings to the queue-specific vectors
3054 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3055 * one vector per queue pair, but on a constrained vector budget, we
3056 * group the queue pairs as "efficiently" as possible.
3057 **/
3058static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3059{
3060 int qp_remaining = vsi->num_queue_pairs;
3061 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3062 int num_ringpairs;
41c445ff
JB		 3063 int v_start = 0;
3064 int qp_idx = 0;
3065
3066 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3067 * group them so there are multiple queues per vector.
3068 */
3069 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3070 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3071
3072 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3073
3074 q_vector->num_ringpairs = num_ringpairs;
3075
3076 q_vector->rx.count = 0;
3077 q_vector->tx.count = 0;
3078 q_vector->rx.ring = NULL;
3079 q_vector->tx.ring = NULL;
3080
3081 while (num_ringpairs--) {
3082 map_vector_to_qp(vsi, v_start, qp_idx);
3083 qp_idx++;
3084 qp_remaining--;
41c445ff
JB		 3085 }
3086 }
3087}
3088
3089/**
3090 * i40e_vsi_request_irq - Request IRQ from the OS
3091 * @vsi: the VSI being configured
3092 * @basename: name for the vector
3093 **/
3094static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3095{
3096 struct i40e_pf *pf = vsi->back;
3097 int err;
3098
3099 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3100 err = i40e_vsi_request_irq_msix(vsi, basename);
3101 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3102 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3103 pf->misc_int_name, pf);
3104 else
3105 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3106 pf->misc_int_name, pf);
3107
3108 if (err)
3109 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3110
3111 return err;
3112}
3113
3114#ifdef CONFIG_NET_POLL_CONTROLLER
3115/**
3116 * i40e_netpoll - A Polling 'interrupt'handler
3117 * @netdev: network interface device structure
3118 *
3119 * This is used by netconsole to send skbs without having to re-enable
3120 * interrupts. It's not called while the normal interrupt routine is executing.
3121 **/
3122static void i40e_netpoll(struct net_device *netdev)
3123{
3124 struct i40e_netdev_priv *np = netdev_priv(netdev);
3125 struct i40e_vsi *vsi = np->vsi;
3126 struct i40e_pf *pf = vsi->back;
3127 int i;
3128
3129 /* if interface is down do nothing */
3130 if (test_bit(__I40E_DOWN, &vsi->state))
3131 return;
3132
3133 pf->flags |= I40E_FLAG_IN_NETPOLL;
3134 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3135 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3136 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3137 } else {
3138 i40e_intr(pf->pdev->irq, netdev);
3139 }
3140 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3141}
3142#endif
3143
3144/**
3145 * i40e_vsi_control_tx - Start or stop a VSI's rings
3146 * @vsi: the VSI being configured
3147 * @enable: start or stop the rings
3148 **/
3149static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3150{
3151 struct i40e_pf *pf = vsi->back;
3152 struct i40e_hw *hw = &pf->hw;
3153 int i, j, pf_q;
3154 u32 tx_reg;
3155
3156 pf_q = vsi->base_queue;
3157 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3158 for (j = 0; j < 50; j++) {
41c445ff 3159 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3160 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3161 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3162 break;
3163 usleep_range(1000, 2000);
3164 }
fda972f6
MW		 3165 /* Skip if the queue is already in the requested state */
3166 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3167 continue;
3168 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3169 continue;
41c445ff
JB		 3170
3171 /* turn on/off the queue */
c5c9eb9e
SN		 3172 if (enable) {
3173 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3174 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3175 } else {
41c445ff 3176 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3177 }
41c445ff
JB		 3178
3179 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3180
3181 /* wait for the change to finish */
3182 for (j = 0; j < 10; j++) {
3183 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3184 if (enable) {
3185 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3186 break;
3187 } else {
3188 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3189 break;
3190 }
3191
3192 udelay(10);
3193 }
3194 if (j >= 10) {
3195 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3196 pf_q, (enable ? "en" : "dis"));
3197 return -ETIMEDOUT;
3198 }
3199 }
3200
7134f9ce
JB		 3201 if (hw->revision_id == 0)
3202 mdelay(50);
3203
41c445ff
JB		 3204 return 0;
3205}
3206
3207/**
3208 * i40e_vsi_control_rx - Start or stop a VSI's rings
3209 * @vsi: the VSI being configured
3210 * @enable: start or stop the rings
3211 **/
3212static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3213{
3214 struct i40e_pf *pf = vsi->back;
3215 struct i40e_hw *hw = &pf->hw;
3216 int i, j, pf_q;
3217 u32 rx_reg;
3218
3219 pf_q = vsi->base_queue;
3220 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3221 for (j = 0; j < 50; j++) {
41c445ff 3222 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3223 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3224 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3225 break;
3226 usleep_range(1000, 2000);
3227 }
41c445ff
JB		 3228
3229 if (enable) {
3230 /* is STAT set ? */
3231 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3232 continue;
3233 } else {
3234 /* is !STAT set ? */
3235 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3236 continue;
3237 }
3238
3239 /* turn on/off the queue */
3240 if (enable)
6c5ef620 3241 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3242 else
6c5ef620 3243 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3244 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3245
3246 /* wait for the change to finish */
3247 for (j = 0; j < 10; j++) {
3248 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3249
3250 if (enable) {
3251 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3252 break;
3253 } else {
3254 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3255 break;
3256 }
3257
3258 udelay(10);
3259 }
3260 if (j >= 10) {
3261 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3262 pf_q, (enable ? "en" : "dis"));
3263 return -ETIMEDOUT;
3264 }
3265 }
3266
3267 return 0;
3268}
3269
3270/**
3271 * i40e_vsi_control_rings - Start or stop a VSI's rings
3272 * @vsi: the VSI being configured
3273 * @enable: start or stop the rings
3274 **/
fc18eaa0 3275int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3276{
3b867b28 3277 int ret = 0;
41c445ff
JB		 3278
3279 /* do rx first for enable and last for disable */
3280 if (request) {
3281 ret = i40e_vsi_control_rx(vsi, request);
3282 if (ret)
3283 return ret;
3284 ret = i40e_vsi_control_tx(vsi, request);
3285 } else {
3b867b28
ASJ		 3286 /* Ignore return value, we need to shutdown whatever we can */
3287 i40e_vsi_control_tx(vsi, request);
3288 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3289 }
3290
3291 return ret;
3292}
3293
3294/**
3295 * i40e_vsi_free_irq - Free the irq association with the OS
3296 * @vsi: the VSI being configured
3297 **/
3298static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3299{
3300 struct i40e_pf *pf = vsi->back;
3301 struct i40e_hw *hw = &pf->hw;
3302 int base = vsi->base_vector;
3303 u32 val, qp;
3304 int i;
3305
3306 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3307 if (!vsi->q_vectors)
3308 return;
3309
3310 for (i = 0; i < vsi->num_q_vectors; i++) {
3311 u16 vector = i + base;
3312
3313 /* free only the irqs that were actually requested */
78681b1f
SN		 3314 if (!vsi->q_vectors[i] ||
3315 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3316 continue;
3317
3318 /* clear the affinity_mask in the IRQ descriptor */
3319 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3320 NULL);
3321 free_irq(pf->msix_entries[vector].vector,
493fb300 3322 vsi->q_vectors[i]);
41c445ff
JB		 3323
3324 /* Tear down the interrupt queue link list
3325 *
3326 * We know that they come in pairs and always
3327 * the Rx first, then the Tx. To clear the
3328 * link list, stick the EOL value into the
3329 * next_q field of the registers.
3330 */
3331 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3332 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3333 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3334 val |= I40E_QUEUE_END_OF_LIST
3335 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3336 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3337
3338 while (qp != I40E_QUEUE_END_OF_LIST) {
3339 u32 next;
3340
3341 val = rd32(hw, I40E_QINT_RQCTL(qp));
3342
3343 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3344 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3345 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3346 I40E_QINT_RQCTL_INTEVENT_MASK);
3347
3348 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3349 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3350
3351 wr32(hw, I40E_QINT_RQCTL(qp), val);
3352
3353 val = rd32(hw, I40E_QINT_TQCTL(qp));
3354
3355 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3356 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3357
3358 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3359 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3360 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3361 I40E_QINT_TQCTL_INTEVENT_MASK);
3362
3363 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3364 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3365
3366 wr32(hw, I40E_QINT_TQCTL(qp), val);
3367 qp = next;
3368 }
3369 }
3370 } else {
3371 free_irq(pf->pdev->irq, pf);
3372
3373 val = rd32(hw, I40E_PFINT_LNKLST0);
3374 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3375 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3376 val |= I40E_QUEUE_END_OF_LIST
3377 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3378 wr32(hw, I40E_PFINT_LNKLST0, val);
3379
3380 val = rd32(hw, I40E_QINT_RQCTL(qp));
3381 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3382 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3383 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3384 I40E_QINT_RQCTL_INTEVENT_MASK);
3385
3386 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3387 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3388
3389 wr32(hw, I40E_QINT_RQCTL(qp), val);
3390
3391 val = rd32(hw, I40E_QINT_TQCTL(qp));
3392
3393 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3394 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3395 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3396 I40E_QINT_TQCTL_INTEVENT_MASK);
3397
3398 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3399 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3400
3401 wr32(hw, I40E_QINT_TQCTL(qp), val);
3402 }
3403}
3404
493fb300
AD		 3405/**
3406 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3407 * @vsi: the VSI being configured
3408 * @v_idx: Index of vector to be freed
3409 *
3410 * This function frees the memory allocated to the q_vector. In addition if
3411 * NAPI is enabled it will delete any references to the NAPI struct prior
3412 * to freeing the q_vector.
3413 **/
3414static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3415{
3416 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3417 struct i40e_ring *ring;
493fb300
AD		 3418
3419 if (!q_vector)
3420 return;
3421
3422 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3423 i40e_for_each_ring(ring, q_vector->tx)
3424 ring->q_vector = NULL;
3425
3426 i40e_for_each_ring(ring, q_vector->rx)
3427 ring->q_vector = NULL;
493fb300
AD		 3428
3429 /* only VSI w/ an associated netdev is set up w/ NAPI */
3430 if (vsi->netdev)
3431 netif_napi_del(&q_vector->napi);
3432
3433 vsi->q_vectors[v_idx] = NULL;
3434
3435 kfree_rcu(q_vector, rcu);
3436}
3437
41c445ff
JB		 3438/**
3439 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3440 * @vsi: the VSI being un-configured
3441 *
3442 * This frees the memory allocated to the q_vectors and
3443 * deletes references to the NAPI struct.
3444 **/
3445static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3446{
3447 int v_idx;
3448
493fb300
AD		 3449 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3450 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3451}
3452
3453/**
3454 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3455 * @pf: board private structure
3456 **/
3457static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3458{
3459 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3460 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3461 pci_disable_msix(pf->pdev);
3462 kfree(pf->msix_entries);
3463 pf->msix_entries = NULL;
3464 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3465 pci_disable_msi(pf->pdev);
3466 }
3467 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3468}
3469
3470/**
3471 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3472 * @pf: board private structure
3473 *
3474 * We go through and clear interrupt specific resources and reset the structure
3475 * to pre-load conditions
3476 **/
3477static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3478{
3479 int i;
3480
3481 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3482 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3483 if (pf->vsi[i])
3484 i40e_vsi_free_q_vectors(pf->vsi[i]);
3485 i40e_reset_interrupt_capability(pf);
3486}
3487
3488/**
3489 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3490 * @vsi: the VSI being configured
3491 **/
3492static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3493{
3494 int q_idx;
3495
3496 if (!vsi->netdev)
3497 return;
3498
3499 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3500 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3501}
3502
3503/**
3504 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3505 * @vsi: the VSI being configured
3506 **/
3507static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3508{
3509 int q_idx;
3510
3511 if (!vsi->netdev)
3512 return;
3513
3514 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3515 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3516}
3517
3518/**
3519 * i40e_quiesce_vsi - Pause a given VSI
3520 * @vsi: the VSI being paused
3521 **/
3522static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3523{
3524 if (test_bit(__I40E_DOWN, &vsi->state))
3525 return;
3526
3527 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3528 if (vsi->netdev && netif_running(vsi->netdev)) {
3529 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3530 } else {
3531 set_bit(__I40E_DOWN, &vsi->state);
3532 i40e_down(vsi);
3533 }
3534}
3535
3536/**
3537 * i40e_unquiesce_vsi - Resume a given VSI
3538 * @vsi: the VSI being resumed
3539 **/
3540static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3541{
3542 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3543 return;
3544
3545 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3546 if (vsi->netdev && netif_running(vsi->netdev))
3547 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3548 else
3549 i40e_up(vsi); /* this clears the DOWN bit */
3550}
3551
3552/**
3553 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3554 * @pf: the PF
3555 **/
3556static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3557{
3558 int v;
3559
3560 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3561 if (pf->vsi[v])
3562 i40e_quiesce_vsi(pf->vsi[v]);
3563 }
3564}
3565
3566/**
3567 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3568 * @pf: the PF
3569 **/
3570static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3571{
3572 int v;
3573
3574 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3575 if (pf->vsi[v])
3576 i40e_unquiesce_vsi(pf->vsi[v]);
3577 }
3578}
3579
3580/**
3581 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3582 * @dcbcfg: the corresponding DCBx configuration structure
3583 *
3584 * Return the number of TCs from given DCBx configuration
3585 **/
3586static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3587{
078b5876
JB		 3588 u8 num_tc = 0;
3589 int i;
41c445ff
JB		 3590
3591 /* Scan the ETS Config Priority Table to find
3592 * traffic class enabled for a given priority
3593 * and use the traffic class index to get the
3594 * number of traffic classes enabled
3595 */
3596 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3597 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3598 num_tc = dcbcfg->etscfg.prioritytable[i];
3599 }
3600
3601 /* Traffic class index starts from zero so
3602 * increment to return the actual count
3603 */
078b5876 3604 return num_tc + 1;
41c445ff
JB		 3605}
3606
3607/**
3608 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3609 * @dcbcfg: the corresponding DCBx configuration structure
3610 *
3611 * Query the current DCB configuration and return the number of
3612 * traffic classes enabled from the given DCBX config
3613 **/
3614static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3615{
3616 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3617 u8 enabled_tc = 1;
3618 u8 i;
3619
3620 for (i = 0; i < num_tc; i++)
3621 enabled_tc |= 1 << i;
3622
3623 return enabled_tc;
3624}
3625
3626/**
3627 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3628 * @pf: PF being queried
3629 *
3630 * Return number of traffic classes enabled for the given PF
3631 **/
3632static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3633{
3634 struct i40e_hw *hw = &pf->hw;
3635 u8 i, enabled_tc;
3636 u8 num_tc = 0;
3637 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3638
3639 /* If DCB is not enabled then always in single TC */
3640 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3641 return 1;
3642
3643 /* MFP mode return count of enabled TCs for this PF */
3644 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3645 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3646 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3647 if (enabled_tc & (1 << i))
3648 num_tc++;
3649 }
3650 return num_tc;
3651 }
3652
3653 /* SFP mode will be enabled for all TCs on port */
3654 return i40e_dcb_get_num_tc(dcbcfg);
3655}
3656
3657/**
3658 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3659 * @pf: PF being queried
3660 *
3661 * Return a bitmap for first enabled traffic class for this PF.
3662 **/
3663static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3664{
3665 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3666 u8 i = 0;
3667
3668 if (!enabled_tc)
3669 return 0x1; /* TC0 */
3670
3671 /* Find the first enabled TC */
3672 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3673 if (enabled_tc & (1 << i))
3674 break;
3675 }
3676
3677 return 1 << i;
3678}
3679
3680/**
3681 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3682 * @pf: PF being queried
3683 *
3684 * Return a bitmap for enabled traffic classes for this PF.
3685 **/
3686static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3687{
3688 /* If DCB is not enabled for this PF then just return default TC */
3689 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3690 return i40e_pf_get_default_tc(pf);
3691
3692 /* MFP mode will have enabled TCs set by FW */
3693 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3694 return pf->hw.func_caps.enabled_tcmap;
3695
3696 /* SFP mode we want PF to be enabled for all TCs */
3697 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3698}
3699
3700/**
3701 * i40e_vsi_get_bw_info - Query VSI BW Information
3702 * @vsi: the VSI being queried
3703 *
3704 * Returns 0 on success, negative value on failure
3705 **/
3706static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3707{
3708 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3709 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3710 struct i40e_pf *pf = vsi->back;
3711 struct i40e_hw *hw = &pf->hw;
dcae29be 3712 i40e_status aq_ret;
41c445ff 3713 u32 tc_bw_max;
41c445ff
JB		 3714 int i;
3715
3716 /* Get the VSI level BW configuration */
dcae29be
JB		 3717 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3718 if (aq_ret) {
41c445ff
JB		 3719 dev_info(&pf->pdev->dev,
3720 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3721 aq_ret, pf->hw.aq.asq_last_status);
3722 return -EINVAL;
41c445ff
JB		 3723 }
3724
3725 /* Get the VSI level BW configuration per TC */
dcae29be 3726 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3727 NULL);
dcae29be 3728 if (aq_ret) {
41c445ff
JB		 3729 dev_info(&pf->pdev->dev,
3730 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3731 aq_ret, pf->hw.aq.asq_last_status);
3732 return -EINVAL;
41c445ff
JB		 3733 }
3734
3735 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3736 dev_info(&pf->pdev->dev,
3737 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3738 bw_config.tc_valid_bits,
3739 bw_ets_config.tc_valid_bits);
3740 /* Still continuing */
3741 }
3742
3743 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3744 vsi->bw_max_quanta = bw_config.max_bw;
3745 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3746 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3747 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3748 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3749 vsi->bw_ets_limit_credits[i] =
3750 le16_to_cpu(bw_ets_config.credits[i]);
3751 /* 3 bits out of 4 for each TC */
3752 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3753 }
078b5876 3754
dcae29be 3755 return 0;
41c445ff
JB		 3756}
3757
3758/**
3759 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3760 * @vsi: the VSI being configured
3761 * @enabled_tc: TC bitmap
3762 * @bw_credits: BW shared credits per TC
3763 *
3764 * Returns 0 on success, negative value on failure
3765 **/
dcae29be 3766static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3767 u8 *bw_share)
3768{
3769 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3770 i40e_status aq_ret;
3771 int i;
41c445ff
JB		 3772
3773 bw_data.tc_valid_bits = enabled_tc;
3774 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3775 bw_data.tc_bw_credits[i] = bw_share[i];
3776
dcae29be
JB		 3777 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3778 NULL);
3779 if (aq_ret) {
41c445ff 3780 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3781 "AQ command Config VSI BW allocation per TC failed = %d\n",
3782 vsi->back->hw.aq.asq_last_status);
dcae29be 3783 return -EINVAL;
41c445ff
JB		 3784 }
3785
3786 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3787 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3788
dcae29be 3789 return 0;
41c445ff
JB		 3790}
3791
3792/**
3793 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3794 * @vsi: the VSI being configured
3795 * @enabled_tc: TC map to be enabled
3796 *
3797 **/
3798static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3799{
3800 struct net_device *netdev = vsi->netdev;
3801 struct i40e_pf *pf = vsi->back;
3802 struct i40e_hw *hw = &pf->hw;
3803 u8 netdev_tc = 0;
3804 int i;
3805 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3806
3807 if (!netdev)
3808 return;
3809
3810 if (!enabled_tc) {
3811 netdev_reset_tc(netdev);
3812 return;
3813 }
3814
3815 /* Set up actual enabled TCs on the VSI */
3816 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3817 return;
3818
3819 /* set per TC queues for the VSI */
3820 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3821 /* Only set TC queues for enabled tcs
3822 *
3823 * e.g. For a VSI that has TC0 and TC3 enabled the
3824 * enabled_tc bitmap would be 0x00001001; the driver
3825 * will set the numtc for netdev as 2 that will be
3826 * referenced by the netdev layer as TC 0 and 1.
3827 */
3828 if (vsi->tc_config.enabled_tc & (1 << i))
3829 netdev_set_tc_queue(netdev,
3830 vsi->tc_config.tc_info[i].netdev_tc,
3831 vsi->tc_config.tc_info[i].qcount,
3832 vsi->tc_config.tc_info[i].qoffset);
3833 }
3834
3835 /* Assign UP2TC map for the VSI */
3836 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3837 /* Get the actual TC# for the UP */
3838 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3839 /* Get the mapped netdev TC# for the UP */
3840 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3841 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3842 }
3843}
3844
3845/**
3846 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3847 * @vsi: the VSI being configured
3848 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3849 **/
3850static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3851 struct i40e_vsi_context *ctxt)
3852{
3853 /* copy just the sections touched not the entire info
3854 * since not all sections are valid as returned by
3855 * update vsi params
3856 */
3857 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3858 memcpy(&vsi->info.queue_mapping,
3859 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3860 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3861 sizeof(vsi->info.tc_mapping));
3862}
3863
3864/**
3865 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3866 * @vsi: VSI to be configured
3867 * @enabled_tc: TC bitmap
3868 *
3869 * This configures a particular VSI for TCs that are mapped to the
3870 * given TC bitmap. It uses default bandwidth share for TCs across
3871 * VSIs to configure TC for a particular VSI.
3872 *
3873 * NOTE:
3874 * It is expected that the VSI queues have been quisced before calling
3875 * this function.
3876 **/
3877static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3878{
3879 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3880 struct i40e_vsi_context ctxt;
3881 int ret = 0;
3882 int i;
3883
3884 /* Check if enabled_tc is same as existing or new TCs */
3885 if (vsi->tc_config.enabled_tc == enabled_tc)
3886 return ret;
3887
3888 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3889 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3890 if (enabled_tc & (1 << i))
3891 bw_share[i] = 1;
3892 }
3893
3894 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3895 if (ret) {
3896 dev_info(&vsi->back->pdev->dev,
3897 "Failed configuring TC map %d for VSI %d\n",
3898 enabled_tc, vsi->seid);
3899 goto out;
3900 }
3901
3902 /* Update Queue Pairs Mapping for currently enabled UPs */
3903 ctxt.seid = vsi->seid;
3904 ctxt.pf_num = vsi->back->hw.pf_id;
3905 ctxt.vf_num = 0;
3906 ctxt.uplink_seid = vsi->uplink_seid;
3907 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3908 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3909
3910 /* Update the VSI after updating the VSI queue-mapping information */
3911 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3912 if (ret) {
3913 dev_info(&vsi->back->pdev->dev,
3914 "update vsi failed, aq_err=%d\n",
3915 vsi->back->hw.aq.asq_last_status);
3916 goto out;
3917 }
3918 /* update the local VSI info with updated queue map */
3919 i40e_vsi_update_queue_map(vsi, &ctxt);
3920 vsi->info.valid_sections = 0;
3921
3922 /* Update current VSI BW information */
3923 ret = i40e_vsi_get_bw_info(vsi);
3924 if (ret) {
3925 dev_info(&vsi->back->pdev->dev,
3926 "Failed updating vsi bw info, aq_err=%d\n",
3927 vsi->back->hw.aq.asq_last_status);
3928 goto out;
3929 }
3930
3931 /* Update the netdev TC setup */
3932 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3933out:
3934 return ret;
3935}
3936
4e3b35b0
NP		 3937/**
3938 * i40e_veb_config_tc - Configure TCs for given VEB
3939 * @veb: given VEB
3940 * @enabled_tc: TC bitmap
3941 *
3942 * Configures given TC bitmap for VEB (switching) element
3943 **/
3944int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
3945{
3946 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
3947 struct i40e_pf *pf = veb->pf;
3948 int ret = 0;
3949 int i;
3950
3951 /* No TCs or already enabled TCs just return */
3952 if (!enabled_tc || veb->enabled_tc == enabled_tc)
3953 return ret;
3954
3955 bw_data.tc_valid_bits = enabled_tc;
3956 /* bw_data.absolute_credits is not set (relative) */
3957
3958 /* Enable ETS TCs with equal BW Share for now */
3959 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3960 if (enabled_tc & (1 << i))
3961 bw_data.tc_bw_share_credits[i] = 1;
3962 }
3963
3964 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
3965 &bw_data, NULL);
3966 if (ret) {
3967 dev_info(&pf->pdev->dev,
3968 "veb bw config failed, aq_err=%d\n",
3969 pf->hw.aq.asq_last_status);
3970 goto out;
3971 }
3972
3973 /* Update the BW information */
3974 ret = i40e_veb_get_bw_info(veb);
3975 if (ret) {
3976 dev_info(&pf->pdev->dev,
3977 "Failed getting veb bw config, aq_err=%d\n",
3978 pf->hw.aq.asq_last_status);
3979 }
3980
3981out:
3982 return ret;
3983}
3984
3985#ifdef CONFIG_I40E_DCB
3986/**
3987 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
3988 * @pf: PF struct
3989 *
3990 * Reconfigure VEB/VSIs on a given PF; it is assumed that
3991 * the caller would've quiesce all the VSIs before calling
3992 * this function
3993 **/
3994static void i40e_dcb_reconfigure(struct i40e_pf *pf)
3995{
3996 u8 tc_map = 0;
3997 int ret;
3998 u8 v;
3999
4000 /* Enable the TCs available on PF to all VEBs */
4001 tc_map = i40e_pf_get_tc_map(pf);
4002 for (v = 0; v < I40E_MAX_VEB; v++) {
4003 if (!pf->veb[v])
4004 continue;
4005 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4006 if (ret) {
4007 dev_info(&pf->pdev->dev,
4008 "Failed configuring TC for VEB seid=%d\n",
4009 pf->veb[v]->seid);
4010 /* Will try to configure as many components */
4011 }
4012 }
4013
4014 /* Update each VSI */
4015 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4016 if (!pf->vsi[v])
4017 continue;
4018
4019 /* - Enable all TCs for the LAN VSI
4020 * - For all others keep them at TC0 for now
4021 */
4022 if (v == pf->lan_vsi)
4023 tc_map = i40e_pf_get_tc_map(pf);
4024 else
4025 tc_map = i40e_pf_get_default_tc(pf);
4026
4027 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4028 if (ret) {
4029 dev_info(&pf->pdev->dev,
4030 "Failed configuring TC for VSI seid=%d\n",
4031 pf->vsi[v]->seid);
4032 /* Will try to configure as many components */
4033 } else {
4034 if (pf->vsi[v]->netdev)
4035 i40e_dcbnl_set_all(pf->vsi[v]);
4036 }
4037 }
4038}
4039
4040/**
4041 * i40e_init_pf_dcb - Initialize DCB configuration
4042 * @pf: PF being configured
4043 *
4044 * Query the current DCB configuration and cache it
4045 * in the hardware structure
4046 **/
4047static int i40e_init_pf_dcb(struct i40e_pf *pf)
4048{
4049 struct i40e_hw *hw = &pf->hw;
4050 int err = 0;
4051
4052 if (pf->hw.func_caps.npar_enable)
4053 goto out;
4054
4055 /* Get the initial DCB configuration */
4056 err = i40e_init_dcb(hw);
4057 if (!err) {
4058 /* Device/Function is not DCBX capable */
4059 if ((!hw->func_caps.dcb) ||
4060 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4061 dev_info(&pf->pdev->dev,
4062 "DCBX offload is not supported or is disabled for this PF.\n");
4063
4064 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4065 goto out;
4066
4067 } else {
4068 /* When status is not DISABLED then DCBX in FW */
4069 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4070 DCB_CAP_DCBX_VER_IEEE;
4071 pf->flags |= I40E_FLAG_DCB_ENABLED;
4072 }
4073 }
4074
4075out:
4076 return err;
4077}
4078#endif /* CONFIG_I40E_DCB */
4079
41c445ff
JB		 4080/**
4081 * i40e_up_complete - Finish the last steps of bringing up a connection
4082 * @vsi: the VSI being configured
4083 **/
4084static int i40e_up_complete(struct i40e_vsi *vsi)
4085{
4086 struct i40e_pf *pf = vsi->back;
4087 int err;
4088
4089 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4090 i40e_vsi_configure_msix(vsi);
4091 else
4092 i40e_configure_msi_and_legacy(vsi);
4093
4094 /* start rings */
4095 err = i40e_vsi_control_rings(vsi, true);
4096 if (err)
4097 return err;
4098
4099 clear_bit(__I40E_DOWN, &vsi->state);
4100 i40e_napi_enable_all(vsi);
4101 i40e_vsi_enable_irq(vsi);
4102
4103 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4104 (vsi->netdev)) {
6d779b41 4105 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 4106 netif_tx_start_all_queues(vsi->netdev);
4107 netif_carrier_on(vsi->netdev);
6d779b41
AS		 4108 } else if (vsi->netdev) {
4109 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff 4110 }
ca64fa4e
ASJ		 4111
4112 /* replay FDIR SB filters */
4113 if (vsi->type == I40E_VSI_FDIR)
4114 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4115 i40e_service_event_schedule(pf);
4116
4117 return 0;
4118}
4119
4120/**
4121 * i40e_vsi_reinit_locked - Reset the VSI
4122 * @vsi: the VSI being configured
4123 *
4124 * Rebuild the ring structs after some configuration
4125 * has changed, e.g. MTU size.
4126 **/
4127static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4128{
4129 struct i40e_pf *pf = vsi->back;
4130
4131 WARN_ON(in_interrupt());
4132 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4133 usleep_range(1000, 2000);
4134 i40e_down(vsi);
4135
4136 /* Give a VF some time to respond to the reset. The
4137 * two second wait is based upon the watchdog cycle in
4138 * the VF driver.
4139 */
4140 if (vsi->type == I40E_VSI_SRIOV)
4141 msleep(2000);
4142 i40e_up(vsi);
4143 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4144}
4145
4146/**
4147 * i40e_up - Bring the connection back up after being down
4148 * @vsi: the VSI being configured
4149 **/
4150int i40e_up(struct i40e_vsi *vsi)
4151{
4152 int err;
4153
4154 err = i40e_vsi_configure(vsi);
4155 if (!err)
4156 err = i40e_up_complete(vsi);
4157
4158 return err;
4159}
4160
4161/**
4162 * i40e_down - Shutdown the connection processing
4163 * @vsi: the VSI being stopped
4164 **/
4165void i40e_down(struct i40e_vsi *vsi)
4166{
4167 int i;
4168
4169 /* It is assumed that the caller of this function
4170 * sets the vsi->state __I40E_DOWN bit.
4171 */
4172 if (vsi->netdev) {
4173 netif_carrier_off(vsi->netdev);
4174 netif_tx_disable(vsi->netdev);
4175 }
4176 i40e_vsi_disable_irq(vsi);
4177 i40e_vsi_control_rings(vsi, false);
4178 i40e_napi_disable_all(vsi);
4179
4180 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4181 i40e_clean_tx_ring(vsi->tx_rings[i]);
4182 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4183 }
4184}
4185
4186/**
4187 * i40e_setup_tc - configure multiple traffic classes
4188 * @netdev: net device to configure
4189 * @tc: number of traffic classes to enable
4190 **/
4191static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4192{
4193 struct i40e_netdev_priv *np = netdev_priv(netdev);
4194 struct i40e_vsi *vsi = np->vsi;
4195 struct i40e_pf *pf = vsi->back;
4196 u8 enabled_tc = 0;
4197 int ret = -EINVAL;
4198 int i;
4199
4200 /* Check if DCB enabled to continue */
4201 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4202 netdev_info(netdev, "DCB is not enabled for adapter\n");
4203 goto exit;
4204 }
4205
4206 /* Check if MFP enabled */
4207 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4208 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4209 goto exit;
4210 }
4211
4212 /* Check whether tc count is within enabled limit */
4213 if (tc > i40e_pf_get_num_tc(pf)) {
4214 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4215 goto exit;
4216 }
4217
4218 /* Generate TC map for number of tc requested */
4219 for (i = 0; i < tc; i++)
4220 enabled_tc |= (1 << i);
4221
4222 /* Requesting same TC configuration as already enabled */
4223 if (enabled_tc == vsi->tc_config.enabled_tc)
4224 return 0;
4225
4226 /* Quiesce VSI queues */
4227 i40e_quiesce_vsi(vsi);
4228
4229 /* Configure VSI for enabled TCs */
4230 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4231 if (ret) {
4232 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4233 vsi->seid);
4234 goto exit;
4235 }
4236
4237 /* Unquiesce VSI */
4238 i40e_unquiesce_vsi(vsi);
4239
4240exit:
4241 return ret;
4242}
4243
4244/**
4245 * i40e_open - Called when a network interface is made active
4246 * @netdev: network interface device structure
4247 *
4248 * The open entry point is called when a network interface is made
4249 * active by the system (IFF_UP). At this point all resources needed
4250 * for transmit and receive operations are allocated, the interrupt
4251 * handler is registered with the OS, the netdev watchdog subtask is
4252 * enabled, and the stack is notified that the interface is ready.
4253 *
4254 * Returns 0 on success, negative value on failure
4255 **/
4256static int i40e_open(struct net_device *netdev)
4257{
4258 struct i40e_netdev_priv *np = netdev_priv(netdev);
4259 struct i40e_vsi *vsi = np->vsi;
4260 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4261 int err;
4262
4eb3f768
SN		 4263 /* disallow open during test or if eeprom is broken */
4264 if (test_bit(__I40E_TESTING, &pf->state) ||
4265 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4266 return -EBUSY;
4267
4268 netif_carrier_off(netdev);
4269
6c167f58
EK		 4270 err = i40e_vsi_open(vsi);
4271 if (err)
4272 return err;
4273
059dab69
JB		 4274 /* configure global TSO hardware offload settings */
4275 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4276 TCP_FLAG_FIN) >> 16);
4277 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4278 TCP_FLAG_FIN |
4279 TCP_FLAG_CWR) >> 16);
4280 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4281
6c167f58
EK		 4282#ifdef CONFIG_I40E_VXLAN
4283 vxlan_get_rx_port(netdev);
4284#endif
4285
4286 return 0;
4287}
4288
4289/**
4290 * i40e_vsi_open -
4291 * @vsi: the VSI to open
4292 *
4293 * Finish initialization of the VSI.
4294 *
4295 * Returns 0 on success, negative value on failure
4296 **/
4297int i40e_vsi_open(struct i40e_vsi *vsi)
4298{
4299 struct i40e_pf *pf = vsi->back;
4300 char int_name[IFNAMSIZ];
4301 int err;
4302
41c445ff
JB		 4303 /* allocate descriptors */
4304 err = i40e_vsi_setup_tx_resources(vsi);
4305 if (err)
4306 goto err_setup_tx;
4307 err = i40e_vsi_setup_rx_resources(vsi);
4308 if (err)
4309 goto err_setup_rx;
4310
4311 err = i40e_vsi_configure(vsi);
4312 if (err)
4313 goto err_setup_rx;
4314
6c167f58
EK		 4315 if (!vsi->netdev) {
4316 err = EINVAL;
4317 goto err_setup_rx;
4318 }
41c445ff 4319 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
6c167f58 4320 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
41c445ff
JB		 4321 err = i40e_vsi_request_irq(vsi, int_name);
4322 if (err)
4323 goto err_setup_rx;
4324
25946ddb 4325 /* Notify the stack of the actual queue counts. */
6c167f58 4326 err = netif_set_real_num_tx_queues(vsi->netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4327 if (err)
4328 goto err_set_queues;
4329
6c167f58 4330 err = netif_set_real_num_rx_queues(vsi->netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4331 if (err)
4332 goto err_set_queues;
4333
41c445ff
JB		 4334 err = i40e_up_complete(vsi);
4335 if (err)
4336 goto err_up_complete;
4337
41c445ff
JB		 4338 return 0;
4339
4340err_up_complete:
4341 i40e_down(vsi);
25946ddb 4342err_set_queues:
41c445ff
JB		 4343 i40e_vsi_free_irq(vsi);
4344err_setup_rx:
4345 i40e_vsi_free_rx_resources(vsi);
4346err_setup_tx:
4347 i40e_vsi_free_tx_resources(vsi);
4348 if (vsi == pf->vsi[pf->lan_vsi])
4349 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4350
4351 return err;
4352}
4353
17a73f6b
JG		 4354/**
4355 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4356 * @pf: Pointer to pf
4357 *
4358 * This function destroys the hlist where all the Flow Director
4359 * filters were saved.
4360 **/
4361static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4362{
4363 struct i40e_fdir_filter *filter;
4364 struct hlist_node *node2;
4365
4366 hlist_for_each_entry_safe(filter, node2,
4367 &pf->fdir_filter_list, fdir_node) {
4368 hlist_del(&filter->fdir_node);
4369 kfree(filter);
4370 }
4371 pf->fdir_pf_active_filters = 0;
4372}
4373
41c445ff
JB		 4374/**
4375 * i40e_close - Disables a network interface
4376 * @netdev: network interface device structure
4377 *
4378 * The close entry point is called when an interface is de-activated
4379 * by the OS. The hardware is still under the driver's control, but
4380 * this netdev interface is disabled.
4381 *
4382 * Returns 0, this is not allowed to fail
4383 **/
4384static int i40e_close(struct net_device *netdev)
4385{
4386 struct i40e_netdev_priv *np = netdev_priv(netdev);
4387 struct i40e_vsi *vsi = np->vsi;
4388
4389 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4390 return 0;
4391
4392 i40e_down(vsi);
4393 i40e_vsi_free_irq(vsi);
4394
4395 i40e_vsi_free_tx_resources(vsi);
4396 i40e_vsi_free_rx_resources(vsi);
4397
4398 return 0;
4399}
4400
4401/**
4402 * i40e_do_reset - Start a PF or Core Reset sequence
4403 * @pf: board private structure
4404 * @reset_flags: which reset is requested
4405 *
4406 * The essential difference in resets is that the PF Reset
4407 * doesn't clear the packet buffers, doesn't reset the PE
4408 * firmware, and doesn't bother the other PFs on the chip.
4409 **/
4410void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4411{
4412 u32 val;
4413
4414 WARN_ON(in_interrupt());
4415
4416 /* do the biggest reset indicated */
4417 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4418
4419 /* Request a Global Reset
4420 *
4421 * This will start the chip's countdown to the actual full
4422 * chip reset event, and a warning interrupt to be sent
4423 * to all PFs, including the requestor. Our handler
4424 * for the warning interrupt will deal with the shutdown
4425 * and recovery of the switch setup.
4426 */
69bfb110 4427 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4428 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4429 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4430 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4431
4432 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4433
4434 /* Request a Core Reset
4435 *
4436 * Same as Global Reset, except does *not* include the MAC/PHY
4437 */
69bfb110 4438 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4439 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4440 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4441 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4442 i40e_flush(&pf->hw);
4443
7823fe34
SN		 4444 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4445
4446 /* Request a Firmware Reset
4447 *
4448 * Same as Global reset, plus restarting the
4449 * embedded firmware engine.
4450 */
4451 /* enable EMP Reset */
4452 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4453 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4454 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4455
4456 /* force the reset */
4457 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4458 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4459 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4460 i40e_flush(&pf->hw);
4461
41c445ff
JB		 4462 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4463
4464 /* Request a PF Reset
4465 *
4466 * Resets only the PF-specific registers
4467 *
4468 * This goes directly to the tear-down and rebuild of
4469 * the switch, since we need to do all the recovery as
4470 * for the Core Reset.
4471 */
69bfb110 4472 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4473 i40e_handle_reset_warning(pf);
4474
4475 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4476 int v;
4477
4478 /* Find the VSI(s) that requested a re-init */
4479 dev_info(&pf->pdev->dev,
4480 "VSI reinit requested\n");
4481 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4482 struct i40e_vsi *vsi = pf->vsi[v];
4483 if (vsi != NULL &&
4484 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4485 i40e_vsi_reinit_locked(pf->vsi[v]);
4486 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4487 }
4488 }
4489
4490 /* no further action needed, so return now */
4491 return;
4492 } else {
4493 dev_info(&pf->pdev->dev,
4494 "bad reset request 0x%08x\n", reset_flags);
4495 return;
4496 }
4497}
4498
4e3b35b0
NP		 4499#ifdef CONFIG_I40E_DCB
4500/**
4501 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4502 * @pf: board private structure
4503 * @old_cfg: current DCB config
4504 * @new_cfg: new DCB config
4505 **/
4506bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4507 struct i40e_dcbx_config *old_cfg,
4508 struct i40e_dcbx_config *new_cfg)
4509{
4510 bool need_reconfig = false;
4511
4512 /* Check if ETS configuration has changed */
4513 if (memcmp(&new_cfg->etscfg,
4514 &old_cfg->etscfg,
4515 sizeof(new_cfg->etscfg))) {
4516 /* If Priority Table has changed reconfig is needed */
4517 if (memcmp(&new_cfg->etscfg.prioritytable,
4518 &old_cfg->etscfg.prioritytable,
4519 sizeof(new_cfg->etscfg.prioritytable))) {
4520 need_reconfig = true;
69bfb110 4521 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4522 }
4523
4524 if (memcmp(&new_cfg->etscfg.tcbwtable,
4525 &old_cfg->etscfg.tcbwtable,
4526 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4527 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4528
4529 if (memcmp(&new_cfg->etscfg.tsatable,
4530 &old_cfg->etscfg.tsatable,
4531 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4532 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4533 }
4534
4535 /* Check if PFC configuration has changed */
4536 if (memcmp(&new_cfg->pfc,
4537 &old_cfg->pfc,
4538 sizeof(new_cfg->pfc))) {
4539 need_reconfig = true;
69bfb110 4540 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4541 }
4542
4543 /* Check if APP Table has changed */
4544 if (memcmp(&new_cfg->app,
4545 &old_cfg->app,
3d9667a9 4546 sizeof(new_cfg->app))) {
4e3b35b0 4547 need_reconfig = true;
69bfb110 4548 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4549 }
4e3b35b0
NP		 4550
4551 return need_reconfig;
4552}
4553
4554/**
4555 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4556 * @pf: board private structure
4557 * @e: event info posted on ARQ
4558 **/
4559static int i40e_handle_lldp_event(struct i40e_pf *pf,
4560 struct i40e_arq_event_info *e)
4561{
4562 struct i40e_aqc_lldp_get_mib *mib =
4563 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4564 struct i40e_hw *hw = &pf->hw;
4565 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4566 struct i40e_dcbx_config tmp_dcbx_cfg;
4567 bool need_reconfig = false;
4568 int ret = 0;
4569 u8 type;
4570
4571 /* Ignore if event is not for Nearest Bridge */
4572 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4573 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4574 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4575 return ret;
4576
4577 /* Check MIB Type and return if event for Remote MIB update */
4578 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4579 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4580 /* Update the remote cached instance and return */
4581 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4582 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4583 &hw->remote_dcbx_config);
4584 goto exit;
4585 }
4586
4587 /* Convert/store the DCBX data from LLDPDU temporarily */
4588 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4589 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4590 if (ret) {
4591 /* Error in LLDPDU parsing return */
4592 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4593 goto exit;
4594 }
4595
4596 /* No change detected in DCBX configs */
4597 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4598 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4599 goto exit;
4600 }
4601
4602 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4603
4604 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4605
4606 /* Overwrite the new configuration */
4607 *dcbx_cfg = tmp_dcbx_cfg;
4608
4609 if (!need_reconfig)
4610 goto exit;
4611
4612 /* Reconfiguration needed quiesce all VSIs */
4613 i40e_pf_quiesce_all_vsi(pf);
4614
4615 /* Changes in configuration update VEB/VSI */
4616 i40e_dcb_reconfigure(pf);
4617
4618 i40e_pf_unquiesce_all_vsi(pf);
4619exit:
4620 return ret;
4621}
4622#endif /* CONFIG_I40E_DCB */
4623
23326186
ASJ		 4624/**
4625 * i40e_do_reset_safe - Protected reset path for userland calls.
4626 * @pf: board private structure
4627 * @reset_flags: which reset is requested
4628 *
4629 **/
4630void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4631{
4632 rtnl_lock();
4633 i40e_do_reset(pf, reset_flags);
4634 rtnl_unlock();
4635}
4636
41c445ff
JB		 4637/**
4638 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4639 * @pf: board private structure
4640 * @e: event info posted on ARQ
4641 *
4642 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4643 * and VF queues
4644 **/
4645static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4646 struct i40e_arq_event_info *e)
4647{
4648 struct i40e_aqc_lan_overflow *data =
4649 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4650 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4651 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4652 struct i40e_hw *hw = &pf->hw;
4653 struct i40e_vf *vf;
4654 u16 vf_id;
4655
69bfb110
JB		 4656 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4657 queue, qtx_ctl);
41c445ff
JB		 4658
4659 /* Queue belongs to VF, find the VF and issue VF reset */
4660 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4661 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4662 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4663 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4664 vf_id -= hw->func_caps.vf_base_id;
4665 vf = &pf->vf[vf_id];
4666 i40e_vc_notify_vf_reset(vf);
4667 /* Allow VF to process pending reset notification */
4668 msleep(20);
4669 i40e_reset_vf(vf, false);
4670 }
4671}
4672
4673/**
4674 * i40e_service_event_complete - Finish up the service event
4675 * @pf: board private structure
4676 **/
4677static void i40e_service_event_complete(struct i40e_pf *pf)
4678{
4679 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4680
4681 /* flush memory to make sure state is correct before next watchog */
4682 smp_mb__before_clear_bit();
4683 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4684}
4685
55a5e60b
ASJ		 4686/**
4687 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4688 * @pf: board private structure
4689 **/
4690int i40e_get_current_fd_count(struct i40e_pf *pf)
4691{
4692 int val, fcnt_prog;
4693 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4694 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4695 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4696 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4697 return fcnt_prog;
4698}
4699
4700/**
4701 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4702 * @pf: board private structure
4703 **/
4704void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4705{
4706 u32 fcnt_prog, fcnt_avail;
4707
4708 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4709 * to re-enable
4710 */
4711 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4712 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4713 return;
4714 fcnt_prog = i40e_get_current_fd_count(pf);
4715 fcnt_avail = pf->hw.fdir_shared_filter_count +
4716 pf->fdir_pf_filter_count;
4717 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4718 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4719 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4720 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4721 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4722 }
4723 }
4724 /* Wait for some more space to be available to turn on ATR */
4725 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4726 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4727 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4728 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4729 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4730 }
4731 }
4732}
4733
41c445ff
JB		 4734/**
4735 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4736 * @pf: board private structure
4737 **/
4738static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4739{
4740 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4741 return;
4742
41c445ff
JB		 4743 /* if interface is down do nothing */
4744 if (test_bit(__I40E_DOWN, &pf->state))
4745 return;
55a5e60b
ASJ		 4746 i40e_fdir_check_and_reenable(pf);
4747
4748 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4749 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4750 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 4751}
4752
4753/**
4754 * i40e_vsi_link_event - notify VSI of a link event
4755 * @vsi: vsi to be notified
4756 * @link_up: link up or down
4757 **/
4758static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4759{
4760 if (!vsi)
4761 return;
4762
4763 switch (vsi->type) {
4764 case I40E_VSI_MAIN:
4765 if (!vsi->netdev || !vsi->netdev_registered)
4766 break;
4767
4768 if (link_up) {
4769 netif_carrier_on(vsi->netdev);
4770 netif_tx_wake_all_queues(vsi->netdev);
4771 } else {
4772 netif_carrier_off(vsi->netdev);
4773 netif_tx_stop_all_queues(vsi->netdev);
4774 }
4775 break;
4776
4777 case I40E_VSI_SRIOV:
4778 break;
4779
4780 case I40E_VSI_VMDQ2:
4781 case I40E_VSI_CTRL:
4782 case I40E_VSI_MIRROR:
4783 default:
4784 /* there is no notification for other VSIs */
4785 break;
4786 }
4787}
4788
4789/**
4790 * i40e_veb_link_event - notify elements on the veb of a link event
4791 * @veb: veb to be notified
4792 * @link_up: link up or down
4793 **/
4794static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4795{
4796 struct i40e_pf *pf;
4797 int i;
4798
4799 if (!veb || !veb->pf)
4800 return;
4801 pf = veb->pf;
4802
4803 /* depth first... */
4804 for (i = 0; i < I40E_MAX_VEB; i++)
4805 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4806 i40e_veb_link_event(pf->veb[i], link_up);
4807
4808 /* ... now the local VSIs */
4809 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4810 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4811 i40e_vsi_link_event(pf->vsi[i], link_up);
4812}
4813
4814/**
4815 * i40e_link_event - Update netif_carrier status
4816 * @pf: board private structure
4817 **/
4818static void i40e_link_event(struct i40e_pf *pf)
4819{
4820 bool new_link, old_link;
4821
4822 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4823 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4824
4825 if (new_link == old_link)
4826 return;
4827
6d779b41
AS		 4828 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4829 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4830 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4831
4832 /* Notify the base of the switch tree connected to
4833 * the link. Floating VEBs are not notified.
4834 */
4835 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4836 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4837 else
4838 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4839
4840 if (pf->vf)
4841 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4842
4843 if (pf->flags & I40E_FLAG_PTP)
4844 i40e_ptp_set_increment(pf);
41c445ff
JB		 4845}
4846
4847/**
4848 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4849 * @pf: board private structure
4850 *
4851 * Set the per-queue flags to request a check for stuck queues in the irq
4852 * clean functions, then force interrupts to be sure the irq clean is called.
4853 **/
4854static void i40e_check_hang_subtask(struct i40e_pf *pf)
4855{
4856 int i, v;
4857
4858 /* If we're down or resetting, just bail */
4859 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4860 return;
4861
4862 /* for each VSI/netdev
4863 * for each Tx queue
4864 * set the check flag
4865 * for each q_vector
4866 * force an interrupt
4867 */
4868 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4869 struct i40e_vsi *vsi = pf->vsi[v];
4870 int armed = 0;
4871
4872 if (!pf->vsi[v] ||
4873 test_bit(__I40E_DOWN, &vsi->state) ||
4874 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4875 continue;
4876
4877 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4878 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4879 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4880 &vsi->tx_rings[i]->state))
41c445ff
JB		 4881 armed++;
4882 }
4883
4884 if (armed) {
4885 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4886 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4887 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4888 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4889 } else {
4890 u16 vec = vsi->base_vector - 1;
4891 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4892 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4893 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4894 wr32(&vsi->back->hw,
4895 I40E_PFINT_DYN_CTLN(vec), val);
4896 }
4897 i40e_flush(&vsi->back->hw);
4898 }
4899 }
4900}
4901
4902/**
4903 * i40e_watchdog_subtask - Check and bring link up
4904 * @pf: board private structure
4905 **/
4906static void i40e_watchdog_subtask(struct i40e_pf *pf)
4907{
4908 int i;
4909
4910 /* if interface is down do nothing */
4911 if (test_bit(__I40E_DOWN, &pf->state) ||
4912 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4913 return;
4914
4915 /* Update the stats for active netdevs so the network stack
4916 * can look at updated numbers whenever it cares to
4917 */
4918 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4919 if (pf->vsi[i] && pf->vsi[i]->netdev)
4920 i40e_update_stats(pf->vsi[i]);
4921
4922 /* Update the stats for the active switching components */
4923 for (i = 0; i < I40E_MAX_VEB; i++)
4924 if (pf->veb[i])
4925 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 4926
4927 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 4928}
4929
4930/**
4931 * i40e_reset_subtask - Set up for resetting the device and driver
4932 * @pf: board private structure
4933 **/
4934static void i40e_reset_subtask(struct i40e_pf *pf)
4935{
4936 u32 reset_flags = 0;
4937
23326186 4938 rtnl_lock();
41c445ff
JB		 4939 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4940 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4941 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4942 }
4943 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4944 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4945 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4946 }
4947 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4948 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4949 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4950 }
4951 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4952 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4953 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4954 }
4955
4956 /* If there's a recovery already waiting, it takes
4957 * precedence before starting a new reset sequence.
4958 */
4959 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4960 i40e_handle_reset_warning(pf);
23326186 4961 goto unlock;
41c445ff
JB		 4962 }
4963
4964 /* If we're already down or resetting, just bail */
4965 if (reset_flags &&
4966 !test_bit(__I40E_DOWN, &pf->state) &&
4967 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4968 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4969
4970unlock:
4971 rtnl_unlock();
41c445ff
JB		 4972}
4973
4974/**
4975 * i40e_handle_link_event - Handle link event
4976 * @pf: board private structure
4977 * @e: event info posted on ARQ
4978 **/
4979static void i40e_handle_link_event(struct i40e_pf *pf,
4980 struct i40e_arq_event_info *e)
4981{
4982 struct i40e_hw *hw = &pf->hw;
4983 struct i40e_aqc_get_link_status *status =
4984 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4985 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4986
4987 /* save off old link status information */
4988 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4989 sizeof(pf->hw.phy.link_info_old));
4990
4991 /* update link status */
4992 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4993 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4994 hw_link_info->link_info = status->link_info;
4995 hw_link_info->an_info = status->an_info;
4996 hw_link_info->ext_info = status->ext_info;
4997 hw_link_info->lse_enable =
4998 le16_to_cpu(status->command_flags) &
4999 I40E_AQ_LSE_ENABLE;
5000
5001 /* process the event */
5002 i40e_link_event(pf);
5003
5004 /* Do a new status request to re-enable LSE reporting
5005 * and load new status information into the hw struct,
5006 * then see if the status changed while processing the
5007 * initial event.
5008 */
5009 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
5010 i40e_link_event(pf);
5011}
5012
5013/**
5014 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5015 * @pf: board private structure
5016 **/
5017static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5018{
5019 struct i40e_arq_event_info event;
5020 struct i40e_hw *hw = &pf->hw;
5021 u16 pending, i = 0;
5022 i40e_status ret;
5023 u16 opcode;
5024 u32 val;
5025
5026 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5027 return;
5028
3197ce22 5029 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5030 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5031 if (!event.msg_buf)
5032 return;
5033
5034 do {
2f019123 5035 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5036 ret = i40e_clean_arq_element(hw, &event, &pending);
5037 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5038 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5039 break;
5040 } else if (ret) {
5041 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5042 break;
5043 }
5044
5045 opcode = le16_to_cpu(event.desc.opcode);
5046 switch (opcode) {
5047
5048 case i40e_aqc_opc_get_link_status:
5049 i40e_handle_link_event(pf, &event);
5050 break;
5051 case i40e_aqc_opc_send_msg_to_pf:
5052 ret = i40e_vc_process_vf_msg(pf,
5053 le16_to_cpu(event.desc.retval),
5054 le32_to_cpu(event.desc.cookie_high),
5055 le32_to_cpu(event.desc.cookie_low),
5056 event.msg_buf,
5057 event.msg_size);
5058 break;
5059 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5060 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5061#ifdef CONFIG_I40E_DCB
5062 rtnl_lock();
5063 ret = i40e_handle_lldp_event(pf, &event);
5064 rtnl_unlock();
5065#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5066 break;
5067 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5068 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5069 i40e_handle_lan_overflow_event(pf, &event);
5070 break;
0467bc91
SN		 5071 case i40e_aqc_opc_send_msg_to_peer:
5072 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5073 break;
41c445ff
JB		 5074 default:
5075 dev_info(&pf->pdev->dev,
0467bc91
SN		 5076 "ARQ Error: Unknown event 0x%04x received\n",
5077 opcode);
41c445ff
JB		 5078 break;
5079 }
5080 } while (pending && (i++ < pf->adminq_work_limit));
5081
5082 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5083 /* re-enable Admin queue interrupt cause */
5084 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5085 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5086 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5087 i40e_flush(hw);
5088
5089 kfree(event.msg_buf);
5090}
5091
4eb3f768
SN		 5092/**
5093 * i40e_verify_eeprom - make sure eeprom is good to use
5094 * @pf: board private structure
5095 **/
5096static void i40e_verify_eeprom(struct i40e_pf *pf)
5097{
5098 int err;
5099
5100 err = i40e_diag_eeprom_test(&pf->hw);
5101 if (err) {
5102 /* retry in case of garbage read */
5103 err = i40e_diag_eeprom_test(&pf->hw);
5104 if (err) {
5105 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5106 err);
5107 set_bit(__I40E_BAD_EEPROM, &pf->state);
5108 }
5109 }
5110
5111 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5112 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5113 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5114 }
5115}
5116
41c445ff
JB		 5117/**
5118 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5119 * @veb: pointer to the VEB instance
5120 *
5121 * This is a recursive function that first builds the attached VSIs then
5122 * recurses in to build the next layer of VEB. We track the connections
5123 * through our own index numbers because the seid's from the HW could
5124 * change across the reset.
5125 **/
5126static int i40e_reconstitute_veb(struct i40e_veb *veb)
5127{
5128 struct i40e_vsi *ctl_vsi = NULL;
5129 struct i40e_pf *pf = veb->pf;
5130 int v, veb_idx;
5131 int ret;
5132
5133 /* build VSI that owns this VEB, temporarily attached to base VEB */
5134 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
5135 if (pf->vsi[v] &&
5136 pf->vsi[v]->veb_idx == veb->idx &&
5137 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5138 ctl_vsi = pf->vsi[v];
5139 break;
5140 }
5141 }
5142 if (!ctl_vsi) {
5143 dev_info(&pf->pdev->dev,
5144 "missing owner VSI for veb_idx %d\n", veb->idx);
5145 ret = -ENOENT;
5146 goto end_reconstitute;
5147 }
5148 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5149 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5150 ret = i40e_add_vsi(ctl_vsi);
5151 if (ret) {
5152 dev_info(&pf->pdev->dev,
5153 "rebuild of owner VSI failed: %d\n", ret);
5154 goto end_reconstitute;
5155 }
5156 i40e_vsi_reset_stats(ctl_vsi);
5157
5158 /* create the VEB in the switch and move the VSI onto the VEB */
5159 ret = i40e_add_veb(veb, ctl_vsi);
5160 if (ret)
5161 goto end_reconstitute;
5162
5163 /* create the remaining VSIs attached to this VEB */
5164 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5165 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5166 continue;
5167
5168 if (pf->vsi[v]->veb_idx == veb->idx) {
5169 struct i40e_vsi *vsi = pf->vsi[v];
5170 vsi->uplink_seid = veb->seid;
5171 ret = i40e_add_vsi(vsi);
5172 if (ret) {
5173 dev_info(&pf->pdev->dev,
5174 "rebuild of vsi_idx %d failed: %d\n",
5175 v, ret);
5176 goto end_reconstitute;
5177 }
5178 i40e_vsi_reset_stats(vsi);
5179 }
5180 }
5181
5182 /* create any VEBs attached to this VEB - RECURSION */
5183 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5184 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5185 pf->veb[veb_idx]->uplink_seid = veb->seid;
5186 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5187 if (ret)
5188 break;
5189 }
5190 }
5191
5192end_reconstitute:
5193 return ret;
5194}
5195
5196/**
5197 * i40e_get_capabilities - get info about the HW
5198 * @pf: the PF struct
5199 **/
5200static int i40e_get_capabilities(struct i40e_pf *pf)
5201{
5202 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5203 u16 data_size;
5204 int buf_len;
5205 int err;
5206
5207 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5208 do {
5209 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5210 if (!cap_buf)
5211 return -ENOMEM;
5212
5213 /* this loads the data into the hw struct for us */
5214 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5215 &data_size,
5216 i40e_aqc_opc_list_func_capabilities,
5217 NULL);
5218 /* data loaded, buffer no longer needed */
5219 kfree(cap_buf);
5220
5221 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5222 /* retry with a larger buffer */
5223 buf_len = data_size;
5224 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5225 dev_info(&pf->pdev->dev,
5226 "capability discovery failed: aq=%d\n",
5227 pf->hw.aq.asq_last_status);
5228 return -ENODEV;
5229 }
5230 } while (err);
5231
d0b10249
JB		 5232 /* increment MSI-X count because current FW skips one */
5233 pf->hw.func_caps.num_msix_vectors++;
7134f9ce 5234
ac71b7ba
ASJ		 5235 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5236 (pf->hw.aq.fw_maj_ver < 2)) {
5237 pf->hw.func_caps.num_msix_vectors++;
5238 pf->hw.func_caps.num_msix_vectors_vf++;
5239 }
5240
41c445ff
JB		 5241 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5242 dev_info(&pf->pdev->dev,
5243 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5244 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5245 pf->hw.func_caps.num_msix_vectors,
5246 pf->hw.func_caps.num_msix_vectors_vf,
5247 pf->hw.func_caps.fd_filters_guaranteed,
5248 pf->hw.func_caps.fd_filters_best_effort,
5249 pf->hw.func_caps.num_tx_qp,
5250 pf->hw.func_caps.num_vsis);
5251
7134f9ce
JB		 5252#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5253 + pf->hw.func_caps.num_vfs)
5254 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5255 dev_info(&pf->pdev->dev,
5256 "got num_vsis %d, setting num_vsis to %d\n",
5257 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5258 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5259 }
5260
41c445ff
JB		 5261 return 0;
5262}
5263
cbf61325
ASJ		 5264static int i40e_vsi_clear(struct i40e_vsi *vsi);
5265
41c445ff 5266/**
cbf61325 5267 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5268 * @pf: board private structure
5269 **/
cbf61325 5270static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5271{
5272 struct i40e_vsi *vsi;
5273 bool new_vsi = false;
5274 int err, i;
5275
cbf61325 5276 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5277 return;
5278
cbf61325 5279 /* find existing VSI and see if it needs configuring */
41c445ff 5280 vsi = NULL;
cbf61325
ASJ		 5281 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5282 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5283 vsi = pf->vsi[i];
cbf61325
ASJ		 5284 break;
5285 }
5286 }
5287
5288 /* create a new VSI if none exists */
41c445ff 5289 if (!vsi) {
cbf61325
ASJ		 5290 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5291 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5292 if (!vsi) {
5293 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
cbf61325 5294 goto err_vsi;
41c445ff
JB		 5295 }
5296 new_vsi = true;
5297 }
cbf61325 5298 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5299
5300 err = i40e_vsi_setup_tx_resources(vsi);
cbf61325
ASJ		 5301 if (err)
5302 goto err_setup_tx;
5303 err = i40e_vsi_setup_rx_resources(vsi);
5304 if (err)
5305 goto err_setup_rx;
5306
5307 if (new_vsi) {
41c445ff 5308 char int_name[IFNAMSIZ + 9];
cbf61325
ASJ		 5309 err = i40e_vsi_configure(vsi);
5310 if (err)
5311 goto err_setup_rx;
41c445ff
JB		 5312 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
5313 dev_driver_string(&pf->pdev->dev));
5314 err = i40e_vsi_request_irq(vsi, int_name);
cbf61325
ASJ		 5315 if (err)
5316 goto err_setup_rx;
41c445ff 5317 err = i40e_up_complete(vsi);
cbf61325
ASJ		 5318 if (err)
5319 goto err_up_complete;
17a73f6b 5320 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
cbf61325 5321 }
41c445ff 5322
cbf61325
ASJ		 5323 return;
5324
5325err_up_complete:
5326 i40e_down(vsi);
5327 i40e_vsi_free_irq(vsi);
5328err_setup_rx:
5329 i40e_vsi_free_rx_resources(vsi);
5330err_setup_tx:
5331 i40e_vsi_free_tx_resources(vsi);
5332err_vsi:
5333 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5334 i40e_vsi_clear(vsi);
41c445ff
JB		 5335}
5336
5337/**
5338 * i40e_fdir_teardown - release the Flow Director resources
5339 * @pf: board private structure
5340 **/
5341static void i40e_fdir_teardown(struct i40e_pf *pf)
5342{
5343 int i;
5344
17a73f6b 5345 i40e_fdir_filter_exit(pf);
41c445ff
JB		 5346 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5347 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5348 i40e_vsi_release(pf->vsi[i]);
5349 break;
5350 }
5351 }
5352}
5353
5354/**
f650a38b 5355 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5356 * @pf: board private structure
5357 *
f650a38b
ASJ		 5358 * Close up the VFs and other things in prep for pf Reset.
5359 **/
5360static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5361{
41c445ff
JB		 5362 struct i40e_hw *hw = &pf->hw;
5363 i40e_status ret;
5364 u32 v;
5365
5366 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5367 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5368 return 0;
41c445ff 5369
69bfb110 5370 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5371
37f0be6d
ASJ		 5372 if (i40e_check_asq_alive(hw))
5373 i40e_vc_notify_reset(pf);
41c445ff
JB		 5374
5375 /* quiesce the VSIs and their queues that are not already DOWN */
5376 i40e_pf_quiesce_all_vsi(pf);
5377
5378 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5379 if (pf->vsi[v])
5380 pf->vsi[v]->seid = 0;
5381 }
5382
5383 i40e_shutdown_adminq(&pf->hw);
5384
f650a38b
ASJ		 5385 /* call shutdown HMC */
5386 ret = i40e_shutdown_lan_hmc(hw);
5387 if (ret) {
5388 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
5389 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5390 }
5391 return ret;
5392}
5393
5394/**
4dda12e6 5395 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5396 * @pf: board private structure
bc7d338f 5397 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5398 **/
bc7d338f 5399static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 5400{
5401 struct i40e_driver_version dv;
5402 struct i40e_hw *hw = &pf->hw;
5403 i40e_status ret;
5404 u32 v;
5405
41c445ff
JB		 5406 /* Now we wait for GRST to settle out.
5407 * We don't have to delete the VEBs or VSIs from the hw switch
5408 * because the reset will make them disappear.
5409 */
5410 ret = i40e_pf_reset(hw);
5411 if (ret)
5412 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
5413 pf->pfr_count++;
5414
5415 if (test_bit(__I40E_DOWN, &pf->state))
5416 goto end_core_reset;
69bfb110 5417 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5418
5419 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5420 ret = i40e_init_adminq(&pf->hw);
5421 if (ret) {
5422 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5423 goto end_core_reset;
5424 }
5425
4eb3f768
SN		 5426 /* re-verify the eeprom if we just had an EMP reset */
5427 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5428 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5429 i40e_verify_eeprom(pf);
5430 }
5431
41c445ff
JB		 5432 ret = i40e_get_capabilities(pf);
5433 if (ret) {
5434 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5435 ret);
5436 goto end_core_reset;
5437 }
5438
41c445ff
JB		 5439 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5440 hw->func_caps.num_rx_qp,
5441 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5442 if (ret) {
5443 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5444 goto end_core_reset;
5445 }
5446 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5447 if (ret) {
5448 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5449 goto end_core_reset;
5450 }
5451
4e3b35b0
NP		 5452#ifdef CONFIG_I40E_DCB
5453 ret = i40e_init_pf_dcb(pf);
5454 if (ret) {
5455 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5456 goto end_core_reset;
5457 }
5458#endif /* CONFIG_I40E_DCB */
5459
41c445ff 5460 /* do basic switch setup */
bc7d338f 5461 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5462 if (ret)
5463 goto end_core_reset;
5464
5465 /* Rebuild the VSIs and VEBs that existed before reset.
5466 * They are still in our local switch element arrays, so only
5467 * need to rebuild the switch model in the HW.
5468 *
5469 * If there were VEBs but the reconstitution failed, we'll try
5470 * try to recover minimal use by getting the basic PF VSI working.
5471 */
5472 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5473 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5474 /* find the one VEB connected to the MAC, and find orphans */
5475 for (v = 0; v < I40E_MAX_VEB; v++) {
5476 if (!pf->veb[v])
5477 continue;
5478
5479 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5480 pf->veb[v]->uplink_seid == 0) {
5481 ret = i40e_reconstitute_veb(pf->veb[v]);
5482
5483 if (!ret)
5484 continue;
5485
5486 /* If Main VEB failed, we're in deep doodoo,
5487 * so give up rebuilding the switch and set up
5488 * for minimal rebuild of PF VSI.
5489 * If orphan failed, we'll report the error
5490 * but try to keep going.
5491 */
5492 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5493 dev_info(&pf->pdev->dev,
5494 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5495 ret);
5496 pf->vsi[pf->lan_vsi]->uplink_seid
5497 = pf->mac_seid;
5498 break;
5499 } else if (pf->veb[v]->uplink_seid == 0) {
5500 dev_info(&pf->pdev->dev,
5501 "rebuild of orphan VEB failed: %d\n",
5502 ret);
5503 }
5504 }
5505 }
5506 }
5507
5508 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5509 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5510 /* no VEB, so rebuild only the Main VSI */
5511 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5512 if (ret) {
5513 dev_info(&pf->pdev->dev,
5514 "rebuild of Main VSI failed: %d\n", ret);
5515 goto end_core_reset;
5516 }
5517 }
5518
5519 /* reinit the misc interrupt */
5520 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5521 ret = i40e_setup_misc_vector(pf);
5522
5523 /* restart the VSIs that were rebuilt and running before the reset */
5524 i40e_pf_unquiesce_all_vsi(pf);
5525
69f64b2b
MW		 5526 if (pf->num_alloc_vfs) {
5527 for (v = 0; v < pf->num_alloc_vfs; v++)
5528 i40e_reset_vf(&pf->vf[v], true);
5529 }
5530
41c445ff
JB		 5531 /* tell the firmware that we're starting */
5532 dv.major_version = DRV_VERSION_MAJOR;
5533 dv.minor_version = DRV_VERSION_MINOR;
5534 dv.build_version = DRV_VERSION_BUILD;
5535 dv.subbuild_version = 0;
5536 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5537
69bfb110 5538 dev_info(&pf->pdev->dev, "reset complete\n");
41c445ff
JB		 5539
5540end_core_reset:
5541 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5542}
5543
f650a38b
ASJ		 5544/**
5545 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5546 * @pf: board private structure
5547 *
5548 * Close up the VFs and other things in prep for a Core Reset,
5549 * then get ready to rebuild the world.
5550 **/
5551static void i40e_handle_reset_warning(struct i40e_pf *pf)
5552{
5553 i40e_status ret;
5554
5555 ret = i40e_prep_for_reset(pf);
5556 if (!ret)
bc7d338f 5557 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5558}
5559
41c445ff
JB		 5560/**
5561 * i40e_handle_mdd_event
5562 * @pf: pointer to the pf structure
5563 *
5564 * Called from the MDD irq handler to identify possibly malicious vfs
5565 **/
5566static void i40e_handle_mdd_event(struct i40e_pf *pf)
5567{
5568 struct i40e_hw *hw = &pf->hw;
5569 bool mdd_detected = false;
5570 struct i40e_vf *vf;
5571 u32 reg;
5572 int i;
5573
5574 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5575 return;
5576
5577 /* find what triggered the MDD event */
5578 reg = rd32(hw, I40E_GL_MDET_TX);
5579 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5580 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5581 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5582 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5583 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5584 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5585 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5586 dev_info(&pf->pdev->dev,
f29eaa3d 5587 "Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n",
41c445ff
JB		 5588 event, queue, func);
5589 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5590 mdd_detected = true;
5591 }
5592 reg = rd32(hw, I40E_GL_MDET_RX);
5593 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5594 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5595 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5596 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5597 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5598 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5599 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5600 dev_info(&pf->pdev->dev,
f29eaa3d 5601 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5602 event, queue, func);
5603 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5604 mdd_detected = true;
5605 }
5606
5607 /* see if one of the VFs needs its hand slapped */
5608 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5609 vf = &(pf->vf[i]);
5610 reg = rd32(hw, I40E_VP_MDET_TX(i));
5611 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5612 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5613 vf->num_mdd_events++;
5614 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5615 }
5616
5617 reg = rd32(hw, I40E_VP_MDET_RX(i));
5618 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5619 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5620 vf->num_mdd_events++;
5621 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5622 }
5623
5624 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5625 dev_info(&pf->pdev->dev,
5626 "Too many MDD events on VF %d, disabled\n", i);
5627 dev_info(&pf->pdev->dev,
5628 "Use PF Control I/F to re-enable the VF\n");
5629 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5630 }
5631 }
5632
5633 /* re-enable mdd interrupt cause */
5634 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5635 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5636 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5637 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5638 i40e_flush(hw);
5639}
5640
a1c9a9d9
JK		 5641#ifdef CONFIG_I40E_VXLAN
5642/**
5643 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5644 * @pf: board private structure
5645 **/
5646static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5647{
5648 const int vxlan_hdr_qwords = 4;
5649 struct i40e_hw *hw = &pf->hw;
5650 i40e_status ret;
5651 u8 filter_index;
5652 __be16 port;
5653 int i;
5654
5655 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5656 return;
5657
5658 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5659
5660 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5661 if (pf->pending_vxlan_bitmap & (1 << i)) {
5662 pf->pending_vxlan_bitmap &= ~(1 << i);
5663 port = pf->vxlan_ports[i];
5664 ret = port ?
5665 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5666 vxlan_hdr_qwords,
5667 I40E_AQC_TUNNEL_TYPE_VXLAN,
5668 &filter_index, NULL)
5669 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5670
5671 if (ret) {
5672 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5673 port ? "adding" : "deleting",
5674 ntohs(port), port ? i : i);
5675
5676 pf->vxlan_ports[i] = 0;
5677 } else {
5678 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5679 port ? "Added" : "Deleted",
5680 ntohs(port), port ? i : filter_index);
5681 }
5682 }
5683 }
5684}
5685
5686#endif
41c445ff
JB		 5687/**
5688 * i40e_service_task - Run the driver's async subtasks
5689 * @work: pointer to work_struct containing our data
5690 **/
5691static void i40e_service_task(struct work_struct *work)
5692{
5693 struct i40e_pf *pf = container_of(work,
5694 struct i40e_pf,
5695 service_task);
5696 unsigned long start_time = jiffies;
5697
5698 i40e_reset_subtask(pf);
5699 i40e_handle_mdd_event(pf);
5700 i40e_vc_process_vflr_event(pf);
5701 i40e_watchdog_subtask(pf);
5702 i40e_fdir_reinit_subtask(pf);
5703 i40e_check_hang_subtask(pf);
5704 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5705#ifdef CONFIG_I40E_VXLAN
5706 i40e_sync_vxlan_filters_subtask(pf);
5707#endif
41c445ff
JB		 5708 i40e_clean_adminq_subtask(pf);
5709
5710 i40e_service_event_complete(pf);
5711
5712 /* If the tasks have taken longer than one timer cycle or there
5713 * is more work to be done, reschedule the service task now
5714 * rather than wait for the timer to tick again.
5715 */
5716 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5717 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5718 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5719 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5720 i40e_service_event_schedule(pf);
5721}
5722
5723/**
5724 * i40e_service_timer - timer callback
5725 * @data: pointer to PF struct
5726 **/
5727static void i40e_service_timer(unsigned long data)
5728{
5729 struct i40e_pf *pf = (struct i40e_pf *)data;
5730
5731 mod_timer(&pf->service_timer,
5732 round_jiffies(jiffies + pf->service_timer_period));
5733 i40e_service_event_schedule(pf);
5734}
5735
5736/**
5737 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5738 * @vsi: the VSI being configured
5739 **/
5740static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5741{
5742 struct i40e_pf *pf = vsi->back;
5743
5744 switch (vsi->type) {
5745 case I40E_VSI_MAIN:
5746 vsi->alloc_queue_pairs = pf->num_lan_qps;
5747 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5748 I40E_REQ_DESCRIPTOR_MULTIPLE);
5749 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5750 vsi->num_q_vectors = pf->num_lan_msix;
5751 else
5752 vsi->num_q_vectors = 1;
5753
5754 break;
5755
5756 case I40E_VSI_FDIR:
5757 vsi->alloc_queue_pairs = 1;
5758 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5759 I40E_REQ_DESCRIPTOR_MULTIPLE);
5760 vsi->num_q_vectors = 1;
5761 break;
5762
5763 case I40E_VSI_VMDQ2:
5764 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5765 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5766 I40E_REQ_DESCRIPTOR_MULTIPLE);
5767 vsi->num_q_vectors = pf->num_vmdq_msix;
5768 break;
5769
5770 case I40E_VSI_SRIOV:
5771 vsi->alloc_queue_pairs = pf->num_vf_qps;
5772 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5773 I40E_REQ_DESCRIPTOR_MULTIPLE);
5774 break;
5775
5776 default:
5777 WARN_ON(1);
5778 return -ENODATA;
5779 }
5780
5781 return 0;
5782}
5783
f650a38b
ASJ		 5784/**
5785 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5786 * @type: VSI pointer
bc7d338f 5787 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5788 *
5789 * On error: returns error code (negative)
5790 * On success: returns 0
5791 **/
bc7d338f 5792static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5793{
5794 int size;
5795 int ret = 0;
5796
ac6c5e3d 5797 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5798 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5799 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5800 if (!vsi->tx_rings)
5801 return -ENOMEM;
f650a38b
ASJ		 5802 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5803
bc7d338f
ASJ		 5804 if (alloc_qvectors) {
5805 /* allocate memory for q_vector pointers */
5806 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5807 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5808 if (!vsi->q_vectors) {
5809 ret = -ENOMEM;
5810 goto err_vectors;
5811 }
f650a38b
ASJ		 5812 }
5813 return ret;
5814
5815err_vectors:
5816 kfree(vsi->tx_rings);
5817 return ret;
5818}
5819
41c445ff
JB		 5820/**
5821 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5822 * @pf: board private structure
5823 * @type: type of VSI
5824 *
5825 * On error: returns error code (negative)
5826 * On success: returns vsi index in PF (positive)
5827 **/
5828static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5829{
5830 int ret = -ENODEV;
5831 struct i40e_vsi *vsi;
5832 int vsi_idx;
5833 int i;
5834
5835 /* Need to protect the allocation of the VSIs at the PF level */
5836 mutex_lock(&pf->switch_mutex);
5837
5838 /* VSI list may be fragmented if VSI creation/destruction has
5839 * been happening. We can afford to do a quick scan to look
5840 * for any free VSIs in the list.
5841 *
5842 * find next empty vsi slot, looping back around if necessary
5843 */
5844 i = pf->next_vsi;
5845 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5846 i++;
5847 if (i >= pf->hw.func_caps.num_vsis) {
5848 i = 0;
5849 while (i < pf->next_vsi && pf->vsi[i])
5850 i++;
5851 }
5852
5853 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5854 vsi_idx = i; /* Found one! */
5855 } else {
5856 ret = -ENODEV;
493fb300 5857 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5858 }
5859 pf->next_vsi = ++i;
5860
5861 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5862 if (!vsi) {
5863 ret = -ENOMEM;
493fb300 5864 goto unlock_pf;
41c445ff
JB		 5865 }
5866 vsi->type = type;
5867 vsi->back = pf;
5868 set_bit(__I40E_DOWN, &vsi->state);
5869 vsi->flags = 0;
5870 vsi->idx = vsi_idx;
5871 vsi->rx_itr_setting = pf->rx_itr_default;
5872 vsi->tx_itr_setting = pf->tx_itr_default;
5873 vsi->netdev_registered = false;
5874 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5875 INIT_LIST_HEAD(&vsi->mac_filter_list);
5876
9f65e15b
AD		 5877 ret = i40e_set_num_rings_in_vsi(vsi);
5878 if (ret)
5879 goto err_rings;
5880
bc7d338f 5881 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5882 if (ret)
9f65e15b 5883 goto err_rings;
493fb300 5884
41c445ff
JB		 5885 /* Setup default MSIX irq handler for VSI */
5886 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5887
5888 pf->vsi[vsi_idx] = vsi;
5889 ret = vsi_idx;
493fb300
AD		 5890 goto unlock_pf;
5891
9f65e15b 5892err_rings:
493fb300
AD		 5893 pf->next_vsi = i - 1;
5894 kfree(vsi);
5895unlock_pf:
41c445ff
JB		 5896 mutex_unlock(&pf->switch_mutex);
5897 return ret;
5898}
5899
f650a38b
ASJ		 5900/**
5901 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5902 * @type: VSI pointer
bc7d338f 5903 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5904 *
5905 * On error: returns error code (negative)
5906 * On success: returns 0
5907 **/
bc7d338f 5908static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5909{
5910 /* free the ring and vector containers */
bc7d338f
ASJ		 5911 if (free_qvectors) {
5912 kfree(vsi->q_vectors);
5913 vsi->q_vectors = NULL;
5914 }
f650a38b
ASJ		 5915 kfree(vsi->tx_rings);
5916 vsi->tx_rings = NULL;
5917 vsi->rx_rings = NULL;
5918}
5919
41c445ff
JB		 5920/**
5921 * i40e_vsi_clear - Deallocate the VSI provided
5922 * @vsi: the VSI being un-configured
5923 **/
5924static int i40e_vsi_clear(struct i40e_vsi *vsi)
5925{
5926 struct i40e_pf *pf;
5927
5928 if (!vsi)
5929 return 0;
5930
5931 if (!vsi->back)
5932 goto free_vsi;
5933 pf = vsi->back;
5934
5935 mutex_lock(&pf->switch_mutex);
5936 if (!pf->vsi[vsi->idx]) {
5937 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5938 vsi->idx, vsi->idx, vsi, vsi->type);
5939 goto unlock_vsi;
5940 }
5941
5942 if (pf->vsi[vsi->idx] != vsi) {
5943 dev_err(&pf->pdev->dev,
5944 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5945 pf->vsi[vsi->idx]->idx,
5946 pf->vsi[vsi->idx],
5947 pf->vsi[vsi->idx]->type,
5948 vsi->idx, vsi, vsi->type);
5949 goto unlock_vsi;
5950 }
5951
5952 /* updates the pf for this cleared vsi */
5953 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5954 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5955
bc7d338f 5956 i40e_vsi_free_arrays(vsi, true);
493fb300 5957
41c445ff
JB		 5958 pf->vsi[vsi->idx] = NULL;
5959 if (vsi->idx < pf->next_vsi)
5960 pf->next_vsi = vsi->idx;
5961
5962unlock_vsi:
5963 mutex_unlock(&pf->switch_mutex);
5964free_vsi:
5965 kfree(vsi);
5966
5967 return 0;
5968}
5969
9f65e15b
AD		 5970/**
5971 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5972 * @vsi: the VSI being cleaned
5973 **/
be1d5eea 5974static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5975{
5976 int i;
5977
8e9dca53 5978 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5979 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5980 kfree_rcu(vsi->tx_rings[i], rcu);
5981 vsi->tx_rings[i] = NULL;
5982 vsi->rx_rings[i] = NULL;
5983 }
be1d5eea 5984 }
9f65e15b
AD		 5985}
5986
41c445ff
JB		 5987/**
5988 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5989 * @vsi: the VSI being configured
5990 **/
5991static int i40e_alloc_rings(struct i40e_vsi *vsi)
5992{
5993 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5994 int i;
5995
41c445ff 5996 /* Set basic values in the rings to be used later during open() */
d7397644 5997 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5998 struct i40e_ring *tx_ring;
5999 struct i40e_ring *rx_ring;
6000
ac6c5e3d 6001 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6002 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6003 if (!tx_ring)
6004 goto err_out;
41c445ff
JB		 6005
6006 tx_ring->queue_index = i;
6007 tx_ring->reg_idx = vsi->base_queue + i;
6008 tx_ring->ring_active = false;
6009 tx_ring->vsi = vsi;
6010 tx_ring->netdev = vsi->netdev;
6011 tx_ring->dev = &pf->pdev->dev;
6012 tx_ring->count = vsi->num_desc;
6013 tx_ring->size = 0;
6014 tx_ring->dcb_tc = 0;
9f65e15b 6015 vsi->tx_rings[i] = tx_ring;
41c445ff 6016
9f65e15b 6017 rx_ring = &tx_ring[1];
41c445ff
JB		 6018 rx_ring->queue_index = i;
6019 rx_ring->reg_idx = vsi->base_queue + i;
6020 rx_ring->ring_active = false;
6021 rx_ring->vsi = vsi;
6022 rx_ring->netdev = vsi->netdev;
6023 rx_ring->dev = &pf->pdev->dev;
6024 rx_ring->count = vsi->num_desc;
6025 rx_ring->size = 0;
6026 rx_ring->dcb_tc = 0;
6027 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6028 set_ring_16byte_desc_enabled(rx_ring);
6029 else
6030 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6031 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6032 }
6033
6034 return 0;
9f65e15b
AD		 6035
6036err_out:
6037 i40e_vsi_clear_rings(vsi);
6038 return -ENOMEM;
41c445ff
JB		 6039}
6040
6041/**
6042 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6043 * @pf: board private structure
6044 * @vectors: the number of MSI-X vectors to request
6045 *
6046 * Returns the number of vectors reserved, or error
6047 **/
6048static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6049{
7b37f376
AG		 6050 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6051 I40E_MIN_MSIX, vectors);
6052 if (vectors < 0) {
41c445ff 6053 dev_info(&pf->pdev->dev,
7b37f376 6054 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6055 vectors = 0;
6056 }
6057
7b37f376
AG		 6058 pf->num_msix_entries = vectors;
6059
41c445ff
JB		 6060 return vectors;
6061}
6062
6063/**
6064 * i40e_init_msix - Setup the MSIX capability
6065 * @pf: board private structure
6066 *
6067 * Work with the OS to set up the MSIX vectors needed.
6068 *
6069 * Returns 0 on success, negative on failure
6070 **/
6071static int i40e_init_msix(struct i40e_pf *pf)
6072{
6073 i40e_status err = 0;
6074 struct i40e_hw *hw = &pf->hw;
6075 int v_budget, i;
6076 int vec;
6077
6078 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6079 return -ENODEV;
6080
6081 /* The number of vectors we'll request will be comprised of:
6082 * - Add 1 for "other" cause for Admin Queue events, etc.
6083 * - The number of LAN queue pairs
f8ff1464
ASJ		 6084 * - Queues being used for RSS.
6085 * We don't need as many as max_rss_size vectors.
6086 * use rss_size instead in the calculation since that
6087 * is governed by number of cpus in the system.
6088 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6089 * - The number of VMDq pairs
6090 * Once we count this up, try the request.
6091 *
6092 * If we can't get what we want, we'll simplify to nearly nothing
6093 * and try again. If that still fails, we punt.
6094 */
f8ff1464 6095 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6096 pf->num_vmdq_msix = pf->num_vmdq_qps;
6097 v_budget = 1 + pf->num_lan_msix;
6098 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6099 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6100 v_budget++;
6101
6102 /* Scale down if necessary, and the rings will share vectors */
6103 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6104
6105 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6106 GFP_KERNEL);
6107 if (!pf->msix_entries)
6108 return -ENOMEM;
6109
6110 for (i = 0; i < v_budget; i++)
6111 pf->msix_entries[i].entry = i;
6112 vec = i40e_reserve_msix_vectors(pf, v_budget);
6113 if (vec < I40E_MIN_MSIX) {
6114 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6115 kfree(pf->msix_entries);
6116 pf->msix_entries = NULL;
6117 return -ENODEV;
6118
6119 } else if (vec == I40E_MIN_MSIX) {
6120 /* Adjust for minimal MSIX use */
77fa28be 6121 dev_info(&pf->pdev->dev, "Features disabled, not enough MSI-X vectors\n");
41c445ff
JB		 6122 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6123 pf->num_vmdq_vsis = 0;
6124 pf->num_vmdq_qps = 0;
6125 pf->num_vmdq_msix = 0;
6126 pf->num_lan_qps = 1;
6127 pf->num_lan_msix = 1;
6128
6129 } else if (vec != v_budget) {
6130 /* Scale vector usage down */
6131 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
6132 vec--; /* reserve the misc vector */
6133
6134 /* partition out the remaining vectors */
6135 switch (vec) {
6136 case 2:
6137 pf->num_vmdq_vsis = 1;
6138 pf->num_lan_msix = 1;
6139 break;
6140 case 3:
6141 pf->num_vmdq_vsis = 1;
6142 pf->num_lan_msix = 2;
6143 break;
6144 default:
6145 pf->num_lan_msix = min_t(int, (vec / 2),
6146 pf->num_lan_qps);
6147 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6148 I40E_DEFAULT_NUM_VMDQ_VSI);
6149 break;
6150 }
6151 }
6152
6153 return err;
6154}
6155
493fb300 6156/**
90e04070 6157 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6158 * @vsi: the VSI being configured
6159 * @v_idx: index of the vector in the vsi struct
6160 *
6161 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6162 **/
90e04070 6163static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6164{
6165 struct i40e_q_vector *q_vector;
6166
6167 /* allocate q_vector */
6168 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6169 if (!q_vector)
6170 return -ENOMEM;
6171
6172 q_vector->vsi = vsi;
6173 q_vector->v_idx = v_idx;
6174 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6175 if (vsi->netdev)
6176 netif_napi_add(vsi->netdev, &q_vector->napi,
6177 i40e_napi_poll, vsi->work_limit);
6178
cd0b6fa6
AD		 6179 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6180 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6181
493fb300
AD		 6182 /* tie q_vector and vsi together */
6183 vsi->q_vectors[v_idx] = q_vector;
6184
6185 return 0;
6186}
6187
41c445ff 6188/**
90e04070 6189 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6190 * @vsi: the VSI being configured
6191 *
6192 * We allocate one q_vector per queue interrupt. If allocation fails we
6193 * return -ENOMEM.
6194 **/
90e04070 6195static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6196{
6197 struct i40e_pf *pf = vsi->back;
6198 int v_idx, num_q_vectors;
493fb300 6199 int err;
41c445ff
JB		 6200
6201 /* if not MSIX, give the one vector only to the LAN VSI */
6202 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6203 num_q_vectors = vsi->num_q_vectors;
6204 else if (vsi == pf->vsi[pf->lan_vsi])
6205 num_q_vectors = 1;
6206 else
6207 return -EINVAL;
6208
41c445ff 6209 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6210 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6211 if (err)
6212 goto err_out;
41c445ff
JB		 6213 }
6214
6215 return 0;
493fb300
AD		 6216
6217err_out:
6218 while (v_idx--)
6219 i40e_free_q_vector(vsi, v_idx);
6220
6221 return err;
41c445ff
JB		 6222}
6223
6224/**
6225 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6226 * @pf: board private structure to initialize
6227 **/
6228static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6229{
6230 int err = 0;
6231
6232 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6233 err = i40e_init_msix(pf);
6234 if (err) {
60ea5f83
JB		 6235 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6236 I40E_FLAG_RSS_ENABLED |
6237 I40E_FLAG_DCB_ENABLED |
6238 I40E_FLAG_SRIOV_ENABLED |
6239 I40E_FLAG_FD_SB_ENABLED |
6240 I40E_FLAG_FD_ATR_ENABLED |
6241 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6242
6243 /* rework the queue expectations without MSIX */
6244 i40e_determine_queue_usage(pf);
6245 }
6246 }
6247
6248 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6249 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6250 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6251 err = pci_enable_msi(pf->pdev);
6252 if (err) {
958a3e3b 6253 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6254 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6255 }
6256 }
6257
958a3e3b 6258 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6259 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6260
41c445ff
JB		 6261 /* track first vector for misc interrupts */
6262 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6263}
6264
6265/**
6266 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6267 * @pf: board private structure
6268 *
6269 * This sets up the handler for MSIX 0, which is used to manage the
6270 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6271 * when in MSI or Legacy interrupt mode.
6272 **/
6273static int i40e_setup_misc_vector(struct i40e_pf *pf)
6274{
6275 struct i40e_hw *hw = &pf->hw;
6276 int err = 0;
6277
6278 /* Only request the irq if this is the first time through, and
6279 * not when we're rebuilding after a Reset
6280 */
6281 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6282 err = request_irq(pf->msix_entries[0].vector,
6283 i40e_intr, 0, pf->misc_int_name, pf);
6284 if (err) {
6285 dev_info(&pf->pdev->dev,
77fa28be
CS		 6286 "request_irq for %s failed: %d\n",
6287 pf->misc_int_name, err);
41c445ff
JB		 6288 return -EFAULT;
6289 }
6290 }
6291
6292 i40e_enable_misc_int_causes(hw);
6293
6294 /* associate no queues to the misc vector */
6295 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6296 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6297
6298 i40e_flush(hw);
6299
6300 i40e_irq_dynamic_enable_icr0(pf);
6301
6302 return err;
6303}
6304
6305/**
6306 * i40e_config_rss - Prepare for RSS if used
6307 * @pf: board private structure
6308 **/
6309static int i40e_config_rss(struct i40e_pf *pf)
6310{
41c445ff
JB		 6311 /* Set of random keys generated using kernel random number generator */
6312 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6313 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6314 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6315 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6316 struct i40e_hw *hw = &pf->hw;
6317 u32 lut = 0;
6318 int i, j;
6319 u64 hena;
41c445ff
JB		 6320
6321 /* Fill out hash function seed */
6322 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6323 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6324
6325 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6326 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6327 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6328 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6329 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6330 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6331
6332 /* Populate the LUT with max no. of queues in round robin fashion */
6333 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6334
6335 /* The assumption is that lan qp count will be the highest
6336 * qp count for any PF VSI that needs RSS.
6337 * If multiple VSIs need RSS support, all the qp counts
6338 * for those VSIs should be a power of 2 for RSS to work.
6339 * If LAN VSI is the only consumer for RSS then this requirement
6340 * is not necessary.
6341 */
6342 if (j == pf->rss_size)
6343 j = 0;
6344 /* lut = 4-byte sliding window of 4 lut entries */
6345 lut = (lut << 8) | (j &
6346 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6347 /* On i = 3, we have 4 entries in lut; write to the register */
6348 if ((i & 3) == 3)
6349 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6350 }
6351 i40e_flush(hw);
6352
6353 return 0;
6354}
6355
f8ff1464
ASJ		 6356/**
6357 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6358 * @pf: board private structure
6359 * @queue_count: the requested queue count for rss.
6360 *
6361 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6362 * count which may be different from the requested queue count.
6363 **/
6364int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6365{
6366 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6367 return 0;
6368
6369 queue_count = min_t(int, queue_count, pf->rss_size_max);
6370 queue_count = rounddown_pow_of_two(queue_count);
6371
6372 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6373 i40e_prep_for_reset(pf);
6374
f8ff1464
ASJ		 6375 pf->rss_size = queue_count;
6376
6377 i40e_reset_and_rebuild(pf, true);
6378 i40e_config_rss(pf);
6379 }
6380 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6381 return pf->rss_size;
6382}
6383
41c445ff
JB		 6384/**
6385 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6386 * @pf: board private structure to initialize
6387 *
6388 * i40e_sw_init initializes the Adapter private data structure.
6389 * Fields are initialized based on PCI device information and
6390 * OS network device settings (MTU size).
6391 **/
6392static int i40e_sw_init(struct i40e_pf *pf)
6393{
6394 int err = 0;
6395 int size;
6396
6397 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6398 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6399 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6400 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6401 if (I40E_DEBUG_USER & debug)
6402 pf->hw.debug_mask = debug;
6403 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6404 I40E_DEFAULT_MSG_ENABLE);
6405 }
6406
6407 /* Set default capability flags */
6408 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6409 I40E_FLAG_MSI_ENABLED |
6410 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6411 I40E_FLAG_RX_1BUF_ENABLED;
6412
7134f9ce
JB		 6413 /* Depending on PF configurations, it is possible that the RSS
6414 * maximum might end up larger than the available queues
6415 */
41c445ff 6416 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6417 pf->rss_size_max = min_t(int, pf->rss_size_max,
6418 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6419 if (pf->hw.func_caps.rss) {
6420 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6421 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6422 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6423 } else {
6424 pf->rss_size = 1;
6425 }
6426
2050bc65
CS		 6427 /* MFP mode enabled */
6428 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6429 pf->flags |= I40E_FLAG_MFP_ENABLED;
6430 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6431 }
6432
cbf61325
ASJ		 6433 /* FW/NVM is not yet fixed in this regard */
6434 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6435 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6436 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6437 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 6438 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6439 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 6440 } else {
6441 dev_info(&pf->pdev->dev,
0b67584f 6442 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6443 }
cbf61325
ASJ		 6444 pf->fdir_pf_filter_count =
6445 pf->hw.func_caps.fd_filters_guaranteed;
6446 pf->hw.fdir_shared_filter_count =
6447 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6448 }
6449
6450 if (pf->hw.func_caps.vmdq) {
6451 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6452 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6453 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6454 }
6455
41c445ff
JB		 6456#ifdef CONFIG_PCI_IOV
6457 if (pf->hw.func_caps.num_vfs) {
6458 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6459 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6460 pf->num_req_vfs = min_t(int,
6461 pf->hw.func_caps.num_vfs,
6462 I40E_MAX_VF_COUNT);
6463 }
6464#endif /* CONFIG_PCI_IOV */
6465 pf->eeprom_version = 0xDEAD;
6466 pf->lan_veb = I40E_NO_VEB;
6467 pf->lan_vsi = I40E_NO_VSI;
6468
6469 /* set up queue assignment tracking */
6470 size = sizeof(struct i40e_lump_tracking)
6471 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6472 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6473 if (!pf->qp_pile) {
6474 err = -ENOMEM;
6475 goto sw_init_done;
6476 }
6477 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6478 pf->qp_pile->search_hint = 0;
6479
6480 /* set up vector assignment tracking */
6481 size = sizeof(struct i40e_lump_tracking)
6482 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6483 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6484 if (!pf->irq_pile) {
6485 kfree(pf->qp_pile);
6486 err = -ENOMEM;
6487 goto sw_init_done;
6488 }
6489 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6490 pf->irq_pile->search_hint = 0;
6491
6492 mutex_init(&pf->switch_mutex);
6493
6494sw_init_done:
6495 return err;
6496}
6497
7c3c288b
ASJ		 6498/**
6499 * i40e_set_ntuple - set the ntuple feature flag and take action
6500 * @pf: board private structure to initialize
6501 * @features: the feature set that the stack is suggesting
6502 *
6503 * returns a bool to indicate if reset needs to happen
6504 **/
6505bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6506{
6507 bool need_reset = false;
6508
6509 /* Check if Flow Director n-tuple support was enabled or disabled. If
6510 * the state changed, we need to reset.
6511 */
6512 if (features & NETIF_F_NTUPLE) {
6513 /* Enable filters and mark for reset */
6514 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6515 need_reset = true;
6516 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6517 } else {
6518 /* turn off filters, mark for reset and clear SW filter list */
6519 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6520 need_reset = true;
6521 i40e_fdir_filter_exit(pf);
6522 }
6523 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6524 /* if ATR was disabled it can be re-enabled. */
6525 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6526 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6527 }
6528 return need_reset;
6529}
6530
41c445ff
JB		 6531/**
6532 * i40e_set_features - set the netdev feature flags
6533 * @netdev: ptr to the netdev being adjusted
6534 * @features: the feature set that the stack is suggesting
6535 **/
6536static int i40e_set_features(struct net_device *netdev,
6537 netdev_features_t features)
6538{
6539 struct i40e_netdev_priv *np = netdev_priv(netdev);
6540 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6541 struct i40e_pf *pf = vsi->back;
6542 bool need_reset;
41c445ff
JB		 6543
6544 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6545 i40e_vlan_stripping_enable(vsi);
6546 else
6547 i40e_vlan_stripping_disable(vsi);
6548
7c3c288b
ASJ		 6549 need_reset = i40e_set_ntuple(pf, features);
6550
6551 if (need_reset)
6552 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6553
41c445ff
JB		 6554 return 0;
6555}
6556
a1c9a9d9
JK		 6557#ifdef CONFIG_I40E_VXLAN
6558/**
6559 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6560 * @pf: board private structure
6561 * @port: The UDP port to look up
6562 *
6563 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6564 **/
6565static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6566{
6567 u8 i;
6568
6569 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6570 if (pf->vxlan_ports[i] == port)
6571 return i;
6572 }
6573
6574 return i;
6575}
6576
6577/**
6578 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6579 * @netdev: This physical port's netdev
6580 * @sa_family: Socket Family that VXLAN is notifying us about
6581 * @port: New UDP port number that VXLAN started listening to
6582 **/
6583static void i40e_add_vxlan_port(struct net_device *netdev,
6584 sa_family_t sa_family, __be16 port)
6585{
6586 struct i40e_netdev_priv *np = netdev_priv(netdev);
6587 struct i40e_vsi *vsi = np->vsi;
6588 struct i40e_pf *pf = vsi->back;
6589 u8 next_idx;
6590 u8 idx;
6591
6592 if (sa_family == AF_INET6)
6593 return;
6594
6595 idx = i40e_get_vxlan_port_idx(pf, port);
6596
6597 /* Check if port already exists */
6598 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6599 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6600 return;
6601 }
6602
6603 /* Now check if there is space to add the new port */
6604 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6605
6606 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6607 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6608 ntohs(port));
6609 return;
6610 }
6611
6612 /* New port: add it and mark its index in the bitmap */
6613 pf->vxlan_ports[next_idx] = port;
6614 pf->pending_vxlan_bitmap |= (1 << next_idx);
6615
6616 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6617}
6618
6619/**
6620 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6621 * @netdev: This physical port's netdev
6622 * @sa_family: Socket Family that VXLAN is notifying us about
6623 * @port: UDP port number that VXLAN stopped listening to
6624 **/
6625static void i40e_del_vxlan_port(struct net_device *netdev,
6626 sa_family_t sa_family, __be16 port)
6627{
6628 struct i40e_netdev_priv *np = netdev_priv(netdev);
6629 struct i40e_vsi *vsi = np->vsi;
6630 struct i40e_pf *pf = vsi->back;
6631 u8 idx;
6632
6633 if (sa_family == AF_INET6)
6634 return;
6635
6636 idx = i40e_get_vxlan_port_idx(pf, port);
6637
6638 /* Check if port already exists */
6639 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6640 /* if port exists, set it to 0 (mark for deletion)
6641 * and make it pending
6642 */
6643 pf->vxlan_ports[idx] = 0;
6644
6645 pf->pending_vxlan_bitmap |= (1 << idx);
6646
6647 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6648 } else {
6649 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6650 ntohs(port));
6651 }
6652}
6653
6654#endif
41c445ff
JB		 6655static const struct net_device_ops i40e_netdev_ops = {
6656 .ndo_open = i40e_open,
6657 .ndo_stop = i40e_close,
6658 .ndo_start_xmit = i40e_lan_xmit_frame,
6659 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6660 .ndo_set_rx_mode = i40e_set_rx_mode,
6661 .ndo_validate_addr = eth_validate_addr,
6662 .ndo_set_mac_address = i40e_set_mac,
6663 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6664 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6665 .ndo_tx_timeout = i40e_tx_timeout,
6666 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6667 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6668#ifdef CONFIG_NET_POLL_CONTROLLER
6669 .ndo_poll_controller = i40e_netpoll,
6670#endif
6671 .ndo_setup_tc = i40e_setup_tc,
6672 .ndo_set_features = i40e_set_features,
6673 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6674 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6675 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6676 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 6677 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
a1c9a9d9
JK		 6678#ifdef CONFIG_I40E_VXLAN
6679 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6680 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6681#endif
41c445ff
JB		 6682};
6683
6684/**
6685 * i40e_config_netdev - Setup the netdev flags
6686 * @vsi: the VSI being configured
6687 *
6688 * Returns 0 on success, negative value on failure
6689 **/
6690static int i40e_config_netdev(struct i40e_vsi *vsi)
6691{
1a10370a 6692 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6693 struct i40e_pf *pf = vsi->back;
6694 struct i40e_hw *hw = &pf->hw;
6695 struct i40e_netdev_priv *np;
6696 struct net_device *netdev;
6697 u8 mac_addr[ETH_ALEN];
6698 int etherdev_size;
6699
6700 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6701 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6702 if (!netdev)
6703 return -ENOMEM;
6704
6705 vsi->netdev = netdev;
6706 np = netdev_priv(netdev);
6707 np->vsi = vsi;
6708
d70e941b 6709 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 6710 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 6711 NETIF_F_TSO;
41c445ff
JB		 6712
6713 netdev->features = NETIF_F_SG |
6714 NETIF_F_IP_CSUM |
6715 NETIF_F_SCTP_CSUM |
6716 NETIF_F_HIGHDMA |
6717 NETIF_F_GSO_UDP_TUNNEL |
6718 NETIF_F_HW_VLAN_CTAG_TX |
6719 NETIF_F_HW_VLAN_CTAG_RX |
6720 NETIF_F_HW_VLAN_CTAG_FILTER |
6721 NETIF_F_IPV6_CSUM |
6722 NETIF_F_TSO |
059dab69 6723 NETIF_F_TSO_ECN |
41c445ff
JB		 6724 NETIF_F_TSO6 |
6725 NETIF_F_RXCSUM |
7c3c288b 6726 NETIF_F_NTUPLE |
41c445ff
JB		 6727 NETIF_F_RXHASH |
6728 0;
6729
6730 /* copy netdev features into list of user selectable features */
6731 netdev->hw_features |= netdev->features;
6732
6733 if (vsi->type == I40E_VSI_MAIN) {
6734 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6735 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6736 } else {
6737 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6738 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6739 pf->vsi[pf->lan_vsi]->netdev->name);
6740 random_ether_addr(mac_addr);
6741 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6742 }
1a10370a 6743 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6744
6745 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6746 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6747 /* vlan gets same features (except vlan offload)
6748 * after any tweaks for specific VSI types
6749 */
6750 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6751 NETIF_F_HW_VLAN_CTAG_RX |
6752 NETIF_F_HW_VLAN_CTAG_FILTER);
6753 netdev->priv_flags |= IFF_UNICAST_FLT;
6754 netdev->priv_flags |= IFF_SUPP_NOFCS;
6755 /* Setup netdev TC information */
6756 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6757
6758 netdev->netdev_ops = &i40e_netdev_ops;
6759 netdev->watchdog_timeo = 5 * HZ;
6760 i40e_set_ethtool_ops(netdev);
6761
6762 return 0;
6763}
6764
6765/**
6766 * i40e_vsi_delete - Delete a VSI from the switch
6767 * @vsi: the VSI being removed
6768 *
6769 * Returns 0 on success, negative value on failure
6770 **/
6771static void i40e_vsi_delete(struct i40e_vsi *vsi)
6772{
6773 /* remove default VSI is not allowed */
6774 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6775 return;
6776
41c445ff
JB		 6777 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6778 return;
6779}
6780
6781/**
6782 * i40e_add_vsi - Add a VSI to the switch
6783 * @vsi: the VSI being configured
6784 *
6785 * This initializes a VSI context depending on the VSI type to be added and
6786 * passes it down to the add_vsi aq command.
6787 **/
6788static int i40e_add_vsi(struct i40e_vsi *vsi)
6789{
6790 int ret = -ENODEV;
6791 struct i40e_mac_filter *f, *ftmp;
6792 struct i40e_pf *pf = vsi->back;
6793 struct i40e_hw *hw = &pf->hw;
6794 struct i40e_vsi_context ctxt;
6795 u8 enabled_tc = 0x1; /* TC0 enabled */
6796 int f_count = 0;
6797
6798 memset(&ctxt, 0, sizeof(ctxt));
6799 switch (vsi->type) {
6800 case I40E_VSI_MAIN:
6801 /* The PF's main VSI is already setup as part of the
6802 * device initialization, so we'll not bother with
6803 * the add_vsi call, but we will retrieve the current
6804 * VSI context.
6805 */
6806 ctxt.seid = pf->main_vsi_seid;
6807 ctxt.pf_num = pf->hw.pf_id;
6808 ctxt.vf_num = 0;
6809 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6810 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6811 if (ret) {
6812 dev_info(&pf->pdev->dev,
6813 "couldn't get pf vsi config, err %d, aq_err %d\n",
6814 ret, pf->hw.aq.asq_last_status);
6815 return -ENOENT;
6816 }
6817 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6818 vsi->info.valid_sections = 0;
6819
6820 vsi->seid = ctxt.seid;
6821 vsi->id = ctxt.vsi_number;
6822
6823 enabled_tc = i40e_pf_get_tc_map(pf);
6824
6825 /* MFP mode setup queue map and update VSI */
6826 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6827 memset(&ctxt, 0, sizeof(ctxt));
6828 ctxt.seid = pf->main_vsi_seid;
6829 ctxt.pf_num = pf->hw.pf_id;
6830 ctxt.vf_num = 0;
6831 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6832 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6833 if (ret) {
6834 dev_info(&pf->pdev->dev,
6835 "update vsi failed, aq_err=%d\n",
6836 pf->hw.aq.asq_last_status);
6837 ret = -ENOENT;
6838 goto err;
6839 }
6840 /* update the local VSI info queue map */
6841 i40e_vsi_update_queue_map(vsi, &ctxt);
6842 vsi->info.valid_sections = 0;
6843 } else {
6844 /* Default/Main VSI is only enabled for TC0
6845 * reconfigure it to enable all TCs that are
6846 * available on the port in SFP mode.
6847 */
6848 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6849 if (ret) {
6850 dev_info(&pf->pdev->dev,
6851 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6852 enabled_tc, ret,
6853 pf->hw.aq.asq_last_status);
6854 ret = -ENOENT;
6855 }
6856 }
6857 break;
6858
6859 case I40E_VSI_FDIR:
cbf61325
ASJ		 6860 ctxt.pf_num = hw->pf_id;
6861 ctxt.vf_num = 0;
6862 ctxt.uplink_seid = vsi->uplink_seid;
6863 ctxt.connection_type = 0x1; /* regular data port */
6864 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 6865 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 6866 break;
6867
6868 case I40E_VSI_VMDQ2:
6869 ctxt.pf_num = hw->pf_id;
6870 ctxt.vf_num = 0;
6871 ctxt.uplink_seid = vsi->uplink_seid;
6872 ctxt.connection_type = 0x1; /* regular data port */
6873 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6874
6875 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6876
6877 /* This VSI is connected to VEB so the switch_id
6878 * should be set to zero by default.
6879 */
6880 ctxt.info.switch_id = 0;
6881 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6882 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6883
6884 /* Setup the VSI tx/rx queue map for TC0 only for now */
6885 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6886 break;
6887
6888 case I40E_VSI_SRIOV:
6889 ctxt.pf_num = hw->pf_id;
6890 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6891 ctxt.uplink_seid = vsi->uplink_seid;
6892 ctxt.connection_type = 0x1; /* regular data port */
6893 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6894
6895 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6896
6897 /* This VSI is connected to VEB so the switch_id
6898 * should be set to zero by default.
6899 */
6900 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6901
6902 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6903 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6904 /* Setup the VSI tx/rx queue map for TC0 only for now */
6905 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6906 break;
6907
6908 default:
6909 return -ENODEV;
6910 }
6911
6912 if (vsi->type != I40E_VSI_MAIN) {
6913 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6914 if (ret) {
6915 dev_info(&vsi->back->pdev->dev,
6916 "add vsi failed, aq_err=%d\n",
6917 vsi->back->hw.aq.asq_last_status);
6918 ret = -ENOENT;
6919 goto err;
6920 }
6921 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6922 vsi->info.valid_sections = 0;
6923 vsi->seid = ctxt.seid;
6924 vsi->id = ctxt.vsi_number;
6925 }
6926
6927 /* If macvlan filters already exist, force them to get loaded */
6928 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6929 f->changed = true;
6930 f_count++;
6931 }
6932 if (f_count) {
6933 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6934 pf->flags |= I40E_FLAG_FILTER_SYNC;
6935 }
6936
6937 /* Update VSI BW information */
6938 ret = i40e_vsi_get_bw_info(vsi);
6939 if (ret) {
6940 dev_info(&pf->pdev->dev,
6941 "couldn't get vsi bw info, err %d, aq_err %d\n",
6942 ret, pf->hw.aq.asq_last_status);
6943 /* VSI is already added so not tearing that up */
6944 ret = 0;
6945 }
6946
6947err:
6948 return ret;
6949}
6950
6951/**
6952 * i40e_vsi_release - Delete a VSI and free its resources
6953 * @vsi: the VSI being removed
6954 *
6955 * Returns 0 on success or < 0 on error
6956 **/
6957int i40e_vsi_release(struct i40e_vsi *vsi)
6958{
6959 struct i40e_mac_filter *f, *ftmp;
6960 struct i40e_veb *veb = NULL;
6961 struct i40e_pf *pf;
6962 u16 uplink_seid;
6963 int i, n;
6964
6965 pf = vsi->back;
6966
6967 /* release of a VEB-owner or last VSI is not allowed */
6968 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6969 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6970 vsi->seid, vsi->uplink_seid);
6971 return -ENODEV;
6972 }
6973 if (vsi == pf->vsi[pf->lan_vsi] &&
6974 !test_bit(__I40E_DOWN, &pf->state)) {
6975 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6976 return -ENODEV;
6977 }
6978
6979 uplink_seid = vsi->uplink_seid;
6980 if (vsi->type != I40E_VSI_SRIOV) {
6981 if (vsi->netdev_registered) {
6982 vsi->netdev_registered = false;
6983 if (vsi->netdev) {
6984 /* results in a call to i40e_close() */
6985 unregister_netdev(vsi->netdev);
41c445ff
JB		 6986 }
6987 } else {
6988 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6989 i40e_down(vsi);
6990 i40e_vsi_free_irq(vsi);
6991 i40e_vsi_free_tx_resources(vsi);
6992 i40e_vsi_free_rx_resources(vsi);
6993 }
6994 i40e_vsi_disable_irq(vsi);
6995 }
6996
6997 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6998 i40e_del_filter(vsi, f->macaddr, f->vlan,
6999 f->is_vf, f->is_netdev);
7000 i40e_sync_vsi_filters(vsi);
7001
7002 i40e_vsi_delete(vsi);
7003 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7004 if (vsi->netdev) {
7005 free_netdev(vsi->netdev);
7006 vsi->netdev = NULL;
7007 }
41c445ff
JB		 7008 i40e_vsi_clear_rings(vsi);
7009 i40e_vsi_clear(vsi);
7010
7011 /* If this was the last thing on the VEB, except for the
7012 * controlling VSI, remove the VEB, which puts the controlling
7013 * VSI onto the next level down in the switch.
7014 *
7015 * Well, okay, there's one more exception here: don't remove
7016 * the orphan VEBs yet. We'll wait for an explicit remove request
7017 * from up the network stack.
7018 */
7019 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7020 if (pf->vsi[i] &&
7021 pf->vsi[i]->uplink_seid == uplink_seid &&
7022 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7023 n++; /* count the VSIs */
7024 }
7025 }
7026 for (i = 0; i < I40E_MAX_VEB; i++) {
7027 if (!pf->veb[i])
7028 continue;
7029 if (pf->veb[i]->uplink_seid == uplink_seid)
7030 n++; /* count the VEBs */
7031 if (pf->veb[i]->seid == uplink_seid)
7032 veb = pf->veb[i];
7033 }
7034 if (n == 0 && veb && veb->uplink_seid != 0)
7035 i40e_veb_release(veb);
7036
7037 return 0;
7038}
7039
7040/**
7041 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7042 * @vsi: ptr to the VSI
7043 *
7044 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7045 * corresponding SW VSI structure and initializes num_queue_pairs for the
7046 * newly allocated VSI.
7047 *
7048 * Returns 0 on success or negative on failure
7049 **/
7050static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7051{
7052 int ret = -ENOENT;
7053 struct i40e_pf *pf = vsi->back;
7054
493fb300 7055 if (vsi->q_vectors[0]) {
41c445ff
JB		 7056 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7057 vsi->seid);
7058 return -EEXIST;
7059 }
7060
7061 if (vsi->base_vector) {
f29eaa3d 7062 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7063 vsi->seid, vsi->base_vector);
7064 return -EEXIST;
7065 }
7066
90e04070 7067 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7068 if (ret) {
7069 dev_info(&pf->pdev->dev,
7070 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7071 vsi->num_q_vectors, vsi->seid, ret);
7072 vsi->num_q_vectors = 0;
7073 goto vector_setup_out;
7074 }
7075
958a3e3b
SN		 7076 if (vsi->num_q_vectors)
7077 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7078 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7079 if (vsi->base_vector < 0) {
7080 dev_info(&pf->pdev->dev,
f29eaa3d 7081 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7082 vsi->seid, vsi->base_vector);
7083 i40e_vsi_free_q_vectors(vsi);
7084 ret = -ENOENT;
7085 goto vector_setup_out;
7086 }
7087
7088vector_setup_out:
7089 return ret;
7090}
7091
bc7d338f
ASJ		 7092/**
7093 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7094 * @vsi: pointer to the vsi.
7095 *
7096 * This re-allocates a vsi's queue resources.
7097 *
7098 * Returns pointer to the successfully allocated and configured VSI sw struct
7099 * on success, otherwise returns NULL on failure.
7100 **/
7101static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7102{
7103 struct i40e_pf *pf = vsi->back;
7104 u8 enabled_tc;
7105 int ret;
7106
7107 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7108 i40e_vsi_clear_rings(vsi);
7109
7110 i40e_vsi_free_arrays(vsi, false);
7111 i40e_set_num_rings_in_vsi(vsi);
7112 ret = i40e_vsi_alloc_arrays(vsi, false);
7113 if (ret)
7114 goto err_vsi;
7115
7116 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7117 if (ret < 0) {
7118 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7119 vsi->seid, ret);
7120 goto err_vsi;
7121 }
7122 vsi->base_queue = ret;
7123
7124 /* Update the FW view of the VSI. Force a reset of TC and queue
7125 * layout configurations.
7126 */
7127 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7128 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7129 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7130 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7131
7132 /* assign it some queues */
7133 ret = i40e_alloc_rings(vsi);
7134 if (ret)
7135 goto err_rings;
7136
7137 /* map all of the rings to the q_vectors */
7138 i40e_vsi_map_rings_to_vectors(vsi);
7139 return vsi;
7140
7141err_rings:
7142 i40e_vsi_free_q_vectors(vsi);
7143 if (vsi->netdev_registered) {
7144 vsi->netdev_registered = false;
7145 unregister_netdev(vsi->netdev);
7146 free_netdev(vsi->netdev);
7147 vsi->netdev = NULL;
7148 }
7149 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7150err_vsi:
7151 i40e_vsi_clear(vsi);
7152 return NULL;
7153}
7154
41c445ff
JB		 7155/**
7156 * i40e_vsi_setup - Set up a VSI by a given type
7157 * @pf: board private structure
7158 * @type: VSI type
7159 * @uplink_seid: the switch element to link to
7160 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7161 *
7162 * This allocates the sw VSI structure and its queue resources, then add a VSI
7163 * to the identified VEB.
7164 *
7165 * Returns pointer to the successfully allocated and configure VSI sw struct on
7166 * success, otherwise returns NULL on failure.
7167 **/
7168struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7169 u16 uplink_seid, u32 param1)
7170{
7171 struct i40e_vsi *vsi = NULL;
7172 struct i40e_veb *veb = NULL;
7173 int ret, i;
7174 int v_idx;
7175
7176 /* The requested uplink_seid must be either
7177 * - the PF's port seid
7178 * no VEB is needed because this is the PF
7179 * or this is a Flow Director special case VSI
7180 * - seid of an existing VEB
7181 * - seid of a VSI that owns an existing VEB
7182 * - seid of a VSI that doesn't own a VEB
7183 * a new VEB is created and the VSI becomes the owner
7184 * - seid of the PF VSI, which is what creates the first VEB
7185 * this is a special case of the previous
7186 *
7187 * Find which uplink_seid we were given and create a new VEB if needed
7188 */
7189 for (i = 0; i < I40E_MAX_VEB; i++) {
7190 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7191 veb = pf->veb[i];
7192 break;
7193 }
7194 }
7195
7196 if (!veb && uplink_seid != pf->mac_seid) {
7197
7198 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7199 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7200 vsi = pf->vsi[i];
7201 break;
7202 }
7203 }
7204 if (!vsi) {
7205 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7206 uplink_seid);
7207 return NULL;
7208 }
7209
7210 if (vsi->uplink_seid == pf->mac_seid)
7211 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7212 vsi->tc_config.enabled_tc);
7213 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7214 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7215 vsi->tc_config.enabled_tc);
7216
7217 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7218 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7219 veb = pf->veb[i];
7220 }
7221 if (!veb) {
7222 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7223 return NULL;
7224 }
7225
7226 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7227 uplink_seid = veb->seid;
7228 }
7229
7230 /* get vsi sw struct */
7231 v_idx = i40e_vsi_mem_alloc(pf, type);
7232 if (v_idx < 0)
7233 goto err_alloc;
7234 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7235 if (!vsi)
7236 goto err_alloc;
41c445ff
JB		 7237 vsi->type = type;
7238 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7239
7240 if (type == I40E_VSI_MAIN)
7241 pf->lan_vsi = v_idx;
7242 else if (type == I40E_VSI_SRIOV)
7243 vsi->vf_id = param1;
7244 /* assign it some queues */
cbf61325
ASJ		 7245 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7246 vsi->idx);
41c445ff
JB		 7247 if (ret < 0) {
7248 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7249 vsi->seid, ret);
7250 goto err_vsi;
7251 }
7252 vsi->base_queue = ret;
7253
7254 /* get a VSI from the hardware */
7255 vsi->uplink_seid = uplink_seid;
7256 ret = i40e_add_vsi(vsi);
7257 if (ret)
7258 goto err_vsi;
7259
7260 switch (vsi->type) {
7261 /* setup the netdev if needed */
7262 case I40E_VSI_MAIN:
7263 case I40E_VSI_VMDQ2:
7264 ret = i40e_config_netdev(vsi);
7265 if (ret)
7266 goto err_netdev;
7267 ret = register_netdev(vsi->netdev);
7268 if (ret)
7269 goto err_netdev;
7270 vsi->netdev_registered = true;
7271 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7272#ifdef CONFIG_I40E_DCB
7273 /* Setup DCB netlink interface */
7274 i40e_dcbnl_setup(vsi);
7275#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7276 /* fall through */
7277
7278 case I40E_VSI_FDIR:
7279 /* set up vectors and rings if needed */
7280 ret = i40e_vsi_setup_vectors(vsi);
7281 if (ret)
7282 goto err_msix;
7283
7284 ret = i40e_alloc_rings(vsi);
7285 if (ret)
7286 goto err_rings;
7287
7288 /* map all of the rings to the q_vectors */
7289 i40e_vsi_map_rings_to_vectors(vsi);
7290
7291 i40e_vsi_reset_stats(vsi);
7292 break;
7293
7294 default:
7295 /* no netdev or rings for the other VSI types */
7296 break;
7297 }
7298
7299 return vsi;
7300
7301err_rings:
7302 i40e_vsi_free_q_vectors(vsi);
7303err_msix:
7304 if (vsi->netdev_registered) {
7305 vsi->netdev_registered = false;
7306 unregister_netdev(vsi->netdev);
7307 free_netdev(vsi->netdev);
7308 vsi->netdev = NULL;
7309 }
7310err_netdev:
7311 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7312err_vsi:
7313 i40e_vsi_clear(vsi);
7314err_alloc:
7315 return NULL;
7316}
7317
7318/**
7319 * i40e_veb_get_bw_info - Query VEB BW information
7320 * @veb: the veb to query
7321 *
7322 * Query the Tx scheduler BW configuration data for given VEB
7323 **/
7324static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7325{
7326 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7327 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7328 struct i40e_pf *pf = veb->pf;
7329 struct i40e_hw *hw = &pf->hw;
7330 u32 tc_bw_max;
7331 int ret = 0;
7332 int i;
7333
7334 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7335 &bw_data, NULL);
7336 if (ret) {
7337 dev_info(&pf->pdev->dev,
7338 "query veb bw config failed, aq_err=%d\n",
7339 hw->aq.asq_last_status);
7340 goto out;
7341 }
7342
7343 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7344 &ets_data, NULL);
7345 if (ret) {
7346 dev_info(&pf->pdev->dev,
7347 "query veb bw ets config failed, aq_err=%d\n",
7348 hw->aq.asq_last_status);
7349 goto out;
7350 }
7351
7352 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7353 veb->bw_max_quanta = ets_data.tc_bw_max;
7354 veb->is_abs_credits = bw_data.absolute_credits_enable;
7355 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7356 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7357 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7358 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7359 veb->bw_tc_limit_credits[i] =
7360 le16_to_cpu(bw_data.tc_bw_limits[i]);
7361 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7362 }
7363
7364out:
7365 return ret;
7366}
7367
7368/**
7369 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7370 * @pf: board private structure
7371 *
7372 * On error: returns error code (negative)
7373 * On success: returns vsi index in PF (positive)
7374 **/
7375static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7376{
7377 int ret = -ENOENT;
7378 struct i40e_veb *veb;
7379 int i;
7380
7381 /* Need to protect the allocation of switch elements at the PF level */
7382 mutex_lock(&pf->switch_mutex);
7383
7384 /* VEB list may be fragmented if VEB creation/destruction has
7385 * been happening. We can afford to do a quick scan to look
7386 * for any free slots in the list.
7387 *
7388 * find next empty veb slot, looping back around if necessary
7389 */
7390 i = 0;
7391 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7392 i++;
7393 if (i >= I40E_MAX_VEB) {
7394 ret = -ENOMEM;
7395 goto err_alloc_veb; /* out of VEB slots! */
7396 }
7397
7398 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7399 if (!veb) {
7400 ret = -ENOMEM;
7401 goto err_alloc_veb;
7402 }
7403 veb->pf = pf;
7404 veb->idx = i;
7405 veb->enabled_tc = 1;
7406
7407 pf->veb[i] = veb;
7408 ret = i;
7409err_alloc_veb:
7410 mutex_unlock(&pf->switch_mutex);
7411 return ret;
7412}
7413
7414/**
7415 * i40e_switch_branch_release - Delete a branch of the switch tree
7416 * @branch: where to start deleting
7417 *
7418 * This uses recursion to find the tips of the branch to be
7419 * removed, deleting until we get back to and can delete this VEB.
7420 **/
7421static void i40e_switch_branch_release(struct i40e_veb *branch)
7422{
7423 struct i40e_pf *pf = branch->pf;
7424 u16 branch_seid = branch->seid;
7425 u16 veb_idx = branch->idx;
7426 int i;
7427
7428 /* release any VEBs on this VEB - RECURSION */
7429 for (i = 0; i < I40E_MAX_VEB; i++) {
7430 if (!pf->veb[i])
7431 continue;
7432 if (pf->veb[i]->uplink_seid == branch->seid)
7433 i40e_switch_branch_release(pf->veb[i]);
7434 }
7435
7436 /* Release the VSIs on this VEB, but not the owner VSI.
7437 *
7438 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7439 * the VEB itself, so don't use (*branch) after this loop.
7440 */
7441 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7442 if (!pf->vsi[i])
7443 continue;
7444 if (pf->vsi[i]->uplink_seid == branch_seid &&
7445 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7446 i40e_vsi_release(pf->vsi[i]);
7447 }
7448 }
7449
7450 /* There's one corner case where the VEB might not have been
7451 * removed, so double check it here and remove it if needed.
7452 * This case happens if the veb was created from the debugfs
7453 * commands and no VSIs were added to it.
7454 */
7455 if (pf->veb[veb_idx])
7456 i40e_veb_release(pf->veb[veb_idx]);
7457}
7458
7459/**
7460 * i40e_veb_clear - remove veb struct
7461 * @veb: the veb to remove
7462 **/
7463static void i40e_veb_clear(struct i40e_veb *veb)
7464{
7465 if (!veb)
7466 return;
7467
7468 if (veb->pf) {
7469 struct i40e_pf *pf = veb->pf;
7470
7471 mutex_lock(&pf->switch_mutex);
7472 if (pf->veb[veb->idx] == veb)
7473 pf->veb[veb->idx] = NULL;
7474 mutex_unlock(&pf->switch_mutex);
7475 }
7476
7477 kfree(veb);
7478}
7479
7480/**
7481 * i40e_veb_release - Delete a VEB and free its resources
7482 * @veb: the VEB being removed
7483 **/
7484void i40e_veb_release(struct i40e_veb *veb)
7485{
7486 struct i40e_vsi *vsi = NULL;
7487 struct i40e_pf *pf;
7488 int i, n = 0;
7489
7490 pf = veb->pf;
7491
7492 /* find the remaining VSI and check for extras */
7493 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7494 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7495 n++;
7496 vsi = pf->vsi[i];
7497 }
7498 }
7499 if (n != 1) {
7500 dev_info(&pf->pdev->dev,
7501 "can't remove VEB %d with %d VSIs left\n",
7502 veb->seid, n);
7503 return;
7504 }
7505
7506 /* move the remaining VSI to uplink veb */
7507 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7508 if (veb->uplink_seid) {
7509 vsi->uplink_seid = veb->uplink_seid;
7510 if (veb->uplink_seid == pf->mac_seid)
7511 vsi->veb_idx = I40E_NO_VEB;
7512 else
7513 vsi->veb_idx = veb->veb_idx;
7514 } else {
7515 /* floating VEB */
7516 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7517 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7518 }
7519
7520 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7521 i40e_veb_clear(veb);
7522
7523 return;
7524}
7525
7526/**
7527 * i40e_add_veb - create the VEB in the switch
7528 * @veb: the VEB to be instantiated
7529 * @vsi: the controlling VSI
7530 **/
7531static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7532{
56747264 7533 bool is_default = false;
e1c51b95 7534 bool is_cloud = false;
41c445ff
JB		 7535 int ret;
7536
7537 /* get a VEB from the hardware */
7538 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7539 veb->enabled_tc, is_default,
7540 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7541 if (ret) {
7542 dev_info(&veb->pf->pdev->dev,
7543 "couldn't add VEB, err %d, aq_err %d\n",
7544 ret, veb->pf->hw.aq.asq_last_status);
7545 return -EPERM;
7546 }
7547
7548 /* get statistics counter */
7549 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7550 &veb->stats_idx, NULL, NULL, NULL);
7551 if (ret) {
7552 dev_info(&veb->pf->pdev->dev,
7553 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7554 ret, veb->pf->hw.aq.asq_last_status);
7555 return -EPERM;
7556 }
7557 ret = i40e_veb_get_bw_info(veb);
7558 if (ret) {
7559 dev_info(&veb->pf->pdev->dev,
7560 "couldn't get VEB bw info, err %d, aq_err %d\n",
7561 ret, veb->pf->hw.aq.asq_last_status);
7562 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7563 return -ENOENT;
7564 }
7565
7566 vsi->uplink_seid = veb->seid;
7567 vsi->veb_idx = veb->idx;
7568 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7569
7570 return 0;
7571}
7572
7573/**
7574 * i40e_veb_setup - Set up a VEB
7575 * @pf: board private structure
7576 * @flags: VEB setup flags
7577 * @uplink_seid: the switch element to link to
7578 * @vsi_seid: the initial VSI seid
7579 * @enabled_tc: Enabled TC bit-map
7580 *
7581 * This allocates the sw VEB structure and links it into the switch
7582 * It is possible and legal for this to be a duplicate of an already
7583 * existing VEB. It is also possible for both uplink and vsi seids
7584 * to be zero, in order to create a floating VEB.
7585 *
7586 * Returns pointer to the successfully allocated VEB sw struct on
7587 * success, otherwise returns NULL on failure.
7588 **/
7589struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7590 u16 uplink_seid, u16 vsi_seid,
7591 u8 enabled_tc)
7592{
7593 struct i40e_veb *veb, *uplink_veb = NULL;
7594 int vsi_idx, veb_idx;
7595 int ret;
7596
7597 /* if one seid is 0, the other must be 0 to create a floating relay */
7598 if ((uplink_seid == 0 || vsi_seid == 0) &&
7599 (uplink_seid + vsi_seid != 0)) {
7600 dev_info(&pf->pdev->dev,
7601 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7602 uplink_seid, vsi_seid);
7603 return NULL;
7604 }
7605
7606 /* make sure there is such a vsi and uplink */
7607 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7608 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7609 break;
7610 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7611 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7612 vsi_seid);
7613 return NULL;
7614 }
7615
7616 if (uplink_seid && uplink_seid != pf->mac_seid) {
7617 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7618 if (pf->veb[veb_idx] &&
7619 pf->veb[veb_idx]->seid == uplink_seid) {
7620 uplink_veb = pf->veb[veb_idx];
7621 break;
7622 }
7623 }
7624 if (!uplink_veb) {
7625 dev_info(&pf->pdev->dev,
7626 "uplink seid %d not found\n", uplink_seid);
7627 return NULL;
7628 }
7629 }
7630
7631 /* get veb sw struct */
7632 veb_idx = i40e_veb_mem_alloc(pf);
7633 if (veb_idx < 0)
7634 goto err_alloc;
7635 veb = pf->veb[veb_idx];
7636 veb->flags = flags;
7637 veb->uplink_seid = uplink_seid;
7638 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7639 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7640
7641 /* create the VEB in the switch */
7642 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7643 if (ret)
7644 goto err_veb;
7645
7646 return veb;
7647
7648err_veb:
7649 i40e_veb_clear(veb);
7650err_alloc:
7651 return NULL;
7652}
7653
7654/**
7655 * i40e_setup_pf_switch_element - set pf vars based on switch type
7656 * @pf: board private structure
7657 * @ele: element we are building info from
7658 * @num_reported: total number of elements
7659 * @printconfig: should we print the contents
7660 *
7661 * helper function to assist in extracting a few useful SEID values.
7662 **/
7663static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7664 struct i40e_aqc_switch_config_element_resp *ele,
7665 u16 num_reported, bool printconfig)
7666{
7667 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7668 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7669 u8 element_type = ele->element_type;
7670 u16 seid = le16_to_cpu(ele->seid);
7671
7672 if (printconfig)
7673 dev_info(&pf->pdev->dev,
7674 "type=%d seid=%d uplink=%d downlink=%d\n",
7675 element_type, seid, uplink_seid, downlink_seid);
7676
7677 switch (element_type) {
7678 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7679 pf->mac_seid = seid;
7680 break;
7681 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7682 /* Main VEB? */
7683 if (uplink_seid != pf->mac_seid)
7684 break;
7685 if (pf->lan_veb == I40E_NO_VEB) {
7686 int v;
7687
7688 /* find existing or else empty VEB */
7689 for (v = 0; v < I40E_MAX_VEB; v++) {
7690 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7691 pf->lan_veb = v;
7692 break;
7693 }
7694 }
7695 if (pf->lan_veb == I40E_NO_VEB) {
7696 v = i40e_veb_mem_alloc(pf);
7697 if (v < 0)
7698 break;
7699 pf->lan_veb = v;
7700 }
7701 }
7702
7703 pf->veb[pf->lan_veb]->seid = seid;
7704 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7705 pf->veb[pf->lan_veb]->pf = pf;
7706 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7707 break;
7708 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7709 if (num_reported != 1)
7710 break;
7711 /* This is immediately after a reset so we can assume this is
7712 * the PF's VSI
7713 */
7714 pf->mac_seid = uplink_seid;
7715 pf->pf_seid = downlink_seid;
7716 pf->main_vsi_seid = seid;
7717 if (printconfig)
7718 dev_info(&pf->pdev->dev,
7719 "pf_seid=%d main_vsi_seid=%d\n",
7720 pf->pf_seid, pf->main_vsi_seid);
7721 break;
7722 case I40E_SWITCH_ELEMENT_TYPE_PF:
7723 case I40E_SWITCH_ELEMENT_TYPE_VF:
7724 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7725 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7726 case I40E_SWITCH_ELEMENT_TYPE_PE:
7727 case I40E_SWITCH_ELEMENT_TYPE_PA:
7728 /* ignore these for now */
7729 break;
7730 default:
7731 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7732 element_type, seid);
7733 break;
7734 }
7735}
7736
7737/**
7738 * i40e_fetch_switch_configuration - Get switch config from firmware
7739 * @pf: board private structure
7740 * @printconfig: should we print the contents
7741 *
7742 * Get the current switch configuration from the device and
7743 * extract a few useful SEID values.
7744 **/
7745int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7746{
7747 struct i40e_aqc_get_switch_config_resp *sw_config;
7748 u16 next_seid = 0;
7749 int ret = 0;
7750 u8 *aq_buf;
7751 int i;
7752
7753 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7754 if (!aq_buf)
7755 return -ENOMEM;
7756
7757 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7758 do {
7759 u16 num_reported, num_total;
7760
7761 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7762 I40E_AQ_LARGE_BUF,
7763 &next_seid, NULL);
7764 if (ret) {
7765 dev_info(&pf->pdev->dev,
7766 "get switch config failed %d aq_err=%x\n",
7767 ret, pf->hw.aq.asq_last_status);
7768 kfree(aq_buf);
7769 return -ENOENT;
7770 }
7771
7772 num_reported = le16_to_cpu(sw_config->header.num_reported);
7773 num_total = le16_to_cpu(sw_config->header.num_total);
7774
7775 if (printconfig)
7776 dev_info(&pf->pdev->dev,
7777 "header: %d reported %d total\n",
7778 num_reported, num_total);
7779
7780 if (num_reported) {
7781 int sz = sizeof(*sw_config) * num_reported;
7782
7783 kfree(pf->sw_config);
7784 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7785 if (pf->sw_config)
7786 memcpy(pf->sw_config, sw_config, sz);
7787 }
7788
7789 for (i = 0; i < num_reported; i++) {
7790 struct i40e_aqc_switch_config_element_resp *ele =
7791 &sw_config->element[i];
7792
7793 i40e_setup_pf_switch_element(pf, ele, num_reported,
7794 printconfig);
7795 }
7796 } while (next_seid != 0);
7797
7798 kfree(aq_buf);
7799 return ret;
7800}
7801
7802/**
7803 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7804 * @pf: board private structure
bc7d338f 7805 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7806 *
7807 * Returns 0 on success, negative value on failure
7808 **/
bc7d338f 7809static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7810{
895106a5 7811 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7812 int ret;
7813
7814 /* find out what's out there already */
7815 ret = i40e_fetch_switch_configuration(pf, false);
7816 if (ret) {
7817 dev_info(&pf->pdev->dev,
7818 "couldn't fetch switch config, err %d, aq_err %d\n",
7819 ret, pf->hw.aq.asq_last_status);
7820 return ret;
7821 }
7822 i40e_pf_reset_stats(pf);
7823
41c445ff 7824 /* first time setup */
bc7d338f 7825 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7826 struct i40e_vsi *vsi = NULL;
7827 u16 uplink_seid;
7828
7829 /* Set up the PF VSI associated with the PF's main VSI
7830 * that is already in the HW switch
7831 */
7832 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7833 uplink_seid = pf->veb[pf->lan_veb]->seid;
7834 else
7835 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7836 if (pf->lan_vsi == I40E_NO_VSI)
7837 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7838 else if (reinit)
7839 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7840 if (!vsi) {
7841 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7842 i40e_fdir_teardown(pf);
7843 return -EAGAIN;
7844 }
41c445ff
JB		 7845 } else {
7846 /* force a reset of TC and queue layout configurations */
7847 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7848 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7849 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7850 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7851 }
7852 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7853
cbf61325
ASJ		 7854 i40e_fdir_sb_setup(pf);
7855
41c445ff
JB		 7856 /* Setup static PF queue filter control settings */
7857 ret = i40e_setup_pf_filter_control(pf);
7858 if (ret) {
7859 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7860 ret);
7861 /* Failure here should not stop continuing other steps */
7862 }
7863
7864 /* enable RSS in the HW, even for only one queue, as the stack can use
7865 * the hash
7866 */
7867 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7868 i40e_config_rss(pf);
7869
7870 /* fill in link information and enable LSE reporting */
7871 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7872 i40e_link_event(pf);
7873
d52c20b7 7874 /* Initialize user-specific link properties */
41c445ff
JB		 7875 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7876 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7877 /* requested_mode is set in probe or by ethtool */
7878 if (!pf->fc_autoneg_status)
7879 goto no_autoneg;
7880
7881 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7882 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7883 pf->hw.fc.current_mode = I40E_FC_FULL;
7884 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7885 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7886 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7887 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7888 else
d52c20b7
JB		 7889 pf->hw.fc.current_mode = I40E_FC_NONE;
7890
7891 /* sync the flow control settings with the auto-neg values */
7892 switch (pf->hw.fc.current_mode) {
7893 case I40E_FC_FULL:
7894 txfc = 1;
7895 rxfc = 1;
7896 break;
7897 case I40E_FC_TX_PAUSE:
7898 txfc = 1;
7899 rxfc = 0;
7900 break;
7901 case I40E_FC_RX_PAUSE:
7902 txfc = 0;
7903 rxfc = 1;
7904 break;
7905 case I40E_FC_NONE:
7906 case I40E_FC_DEFAULT:
7907 txfc = 0;
7908 rxfc = 0;
7909 break;
7910 case I40E_FC_PFC:
7911 /* TBD */
7912 break;
7913 /* no default case, we have to handle all possibilities here */
7914 }
7915
7916 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7917
7918 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7919 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7920 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7921
7922 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7923
d52c20b7
JB		 7924 goto fc_complete;
7925
7926no_autoneg:
7927 /* disable L2 flow control, user can turn it on if they wish */
7928 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7929 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7930 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7931
7932fc_complete:
beb0dff1
JK		 7933 i40e_ptp_init(pf);
7934
41c445ff
JB		 7935 return ret;
7936}
7937
41c445ff
JB		 7938/**
7939 * i40e_determine_queue_usage - Work out queue distribution
7940 * @pf: board private structure
7941 **/
7942static void i40e_determine_queue_usage(struct i40e_pf *pf)
7943{
41c445ff
JB		 7944 int queues_left;
7945
7946 pf->num_lan_qps = 0;
41c445ff
JB		 7947
7948 /* Find the max queues to be put into basic use. We'll always be
7949 * using TC0, whether or not DCB is running, and TC0 will get the
7950 * big RSS set.
7951 */
7952 queues_left = pf->hw.func_caps.num_tx_qp;
7953
cbf61325
ASJ		 7954 if ((queues_left == 1) ||
7955 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
7956 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
7957 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 7958 /* one qp for PF, no queues for anything else */
7959 queues_left = 0;
7960 pf->rss_size = pf->num_lan_qps = 1;
7961
7962 /* make sure all the fancies are disabled */
60ea5f83
JB		 7963 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
7964 I40E_FLAG_FD_SB_ENABLED |
7965 I40E_FLAG_FD_ATR_ENABLED |
7966 I40E_FLAG_DCB_ENABLED |
7967 I40E_FLAG_SRIOV_ENABLED |
7968 I40E_FLAG_VMDQ_ENABLED);
41c445ff 7969 } else {
cbf61325
ASJ		 7970 /* Not enough queues for all TCs */
7971 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
7972 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
7973 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
7974 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
7975 }
7976 pf->num_lan_qps = pf->rss_size_max;
7977 queues_left -= pf->num_lan_qps;
7978 }
7979
7980 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7981 if (queues_left > 1) {
7982 queues_left -= 1; /* save 1 queue for FD */
7983 } else {
7984 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7985 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
7986 }
41c445ff
JB		 7987 }
7988
7989 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7990 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 7991 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
7992 (queues_left / pf->num_vf_qps));
41c445ff
JB		 7993 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7994 }
7995
7996 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7997 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7998 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7999 (queues_left / pf->num_vmdq_qps));
8000 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8001 }
8002
f8ff1464 8003 pf->queues_left = queues_left;
41c445ff
JB		 8004 return;
8005}
8006
8007/**
8008 * i40e_setup_pf_filter_control - Setup PF static filter control
8009 * @pf: PF to be setup
8010 *
8011 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8012 * settings. If PE/FCoE are enabled then it will also set the per PF
8013 * based filter sizes required for them. It also enables Flow director,
8014 * ethertype and macvlan type filter settings for the pf.
8015 *
8016 * Returns 0 on success, negative on failure
8017 **/
8018static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8019{
8020 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8021
8022 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8023
8024 /* Flow Director is enabled */
60ea5f83 8025 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8026 settings->enable_fdir = true;
8027
8028 /* Ethtype and MACVLAN filters enabled for PF */
8029 settings->enable_ethtype = true;
8030 settings->enable_macvlan = true;
8031
8032 if (i40e_set_filter_control(&pf->hw, settings))
8033 return -ENOENT;
8034
8035 return 0;
8036}
8037
0c22b3dd
JB		 8038#define INFO_STRING_LEN 255
8039static void i40e_print_features(struct i40e_pf *pf)
8040{
8041 struct i40e_hw *hw = &pf->hw;
8042 char *buf, *string;
8043
8044 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8045 if (!string) {
8046 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8047 return;
8048 }
8049
8050 buf = string;
8051
8052 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8053#ifdef CONFIG_PCI_IOV
8054 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8055#endif
8056 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8057 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8058
8059 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8060 buf += sprintf(buf, "RSS ");
8061 buf += sprintf(buf, "FDir ");
8062 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
8063 buf += sprintf(buf, "ATR ");
8064 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
8065 buf += sprintf(buf, "NTUPLE ");
8066 if (pf->flags & I40E_FLAG_DCB_ENABLED)
8067 buf += sprintf(buf, "DCB ");
8068 if (pf->flags & I40E_FLAG_PTP)
8069 buf += sprintf(buf, "PTP ");
8070
8071 BUG_ON(buf > (string + INFO_STRING_LEN));
8072 dev_info(&pf->pdev->dev, "%s\n", string);
8073 kfree(string);
8074}
8075
41c445ff
JB		 8076/**
8077 * i40e_probe - Device initialization routine
8078 * @pdev: PCI device information struct
8079 * @ent: entry in i40e_pci_tbl
8080 *
8081 * i40e_probe initializes a pf identified by a pci_dev structure.
8082 * The OS initialization, configuring of the pf private structure,
8083 * and a hardware reset occur.
8084 *
8085 * Returns 0 on success, negative on failure
8086 **/
8087static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8088{
8089 struct i40e_driver_version dv;
8090 struct i40e_pf *pf;
8091 struct i40e_hw *hw;
93cd765b 8092 static u16 pfs_found;
d4dfb81a 8093 u16 link_status;
41c445ff
JB		 8094 int err = 0;
8095 u32 len;
8096
8097 err = pci_enable_device_mem(pdev);
8098 if (err)
8099 return err;
8100
8101 /* set up for high or low dma */
6494294f 8102 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8103 if (err) {
e3e3bfdd
JS		 8104 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8105 if (err) {
8106 dev_err(&pdev->dev,
8107 "DMA configuration failed: 0x%x\n", err);
8108 goto err_dma;
8109 }
41c445ff
JB		 8110 }
8111
8112 /* set up pci connections */
8113 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8114 IORESOURCE_MEM), i40e_driver_name);
8115 if (err) {
8116 dev_info(&pdev->dev,
8117 "pci_request_selected_regions failed %d\n", err);
8118 goto err_pci_reg;
8119 }
8120
8121 pci_enable_pcie_error_reporting(pdev);
8122 pci_set_master(pdev);
8123
8124 /* Now that we have a PCI connection, we need to do the
8125 * low level device setup. This is primarily setting up
8126 * the Admin Queue structures and then querying for the
8127 * device's current profile information.
8128 */
8129 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8130 if (!pf) {
8131 err = -ENOMEM;
8132 goto err_pf_alloc;
8133 }
8134 pf->next_vsi = 0;
8135 pf->pdev = pdev;
8136 set_bit(__I40E_DOWN, &pf->state);
8137
8138 hw = &pf->hw;
8139 hw->back = pf;
8140 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8141 pci_resource_len(pdev, 0));
8142 if (!hw->hw_addr) {
8143 err = -EIO;
8144 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8145 (unsigned int)pci_resource_start(pdev, 0),
8146 (unsigned int)pci_resource_len(pdev, 0), err);
8147 goto err_ioremap;
8148 }
8149 hw->vendor_id = pdev->vendor;
8150 hw->device_id = pdev->device;
8151 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8152 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8153 hw->subsystem_device_id = pdev->subsystem_device;
8154 hw->bus.device = PCI_SLOT(pdev->devfn);
8155 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8156 pf->instance = pfs_found;
41c445ff 8157
7134f9ce
JB		 8158 /* do a special CORER for clearing PXE mode once at init */
8159 if (hw->revision_id == 0 &&
8160 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8161 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8162 i40e_flush(hw);
8163 msleep(200);
8164 pf->corer_count++;
8165
8166 i40e_clear_pxe_mode(hw);
8167 }
8168
41c445ff
JB		 8169 /* Reset here to make sure all is clean and to define PF 'n' */
8170 err = i40e_pf_reset(hw);
8171 if (err) {
8172 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8173 goto err_pf_reset;
8174 }
8175 pf->pfr_count++;
8176
8177 hw->aq.num_arq_entries = I40E_AQ_LEN;
8178 hw->aq.num_asq_entries = I40E_AQ_LEN;
8179 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8180 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8181 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8182 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8183 "%s-pf%d:misc",
8184 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8185
8186 err = i40e_init_shared_code(hw);
8187 if (err) {
8188 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8189 goto err_pf_reset;
8190 }
8191
d52c20b7
JB		 8192 /* set up a default setting for link flow control */
8193 pf->hw.fc.requested_mode = I40E_FC_NONE;
8194
41c445ff
JB		 8195 err = i40e_init_adminq(hw);
8196 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8197 if (err) {
8198 dev_info(&pdev->dev,
8199 "init_adminq failed: %d expecting API %02x.%02x\n",
8200 err,
8201 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8202 goto err_pf_reset;
8203 }
8204
4eb3f768
SN		 8205 i40e_verify_eeprom(pf);
8206
6ff4ef86 8207 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8208 err = i40e_get_capabilities(pf);
8209 if (err)
8210 goto err_adminq_setup;
8211
8212 err = i40e_sw_init(pf);
8213 if (err) {
8214 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8215 goto err_sw_init;
8216 }
8217
8218 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8219 hw->func_caps.num_rx_qp,
8220 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8221 if (err) {
8222 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8223 goto err_init_lan_hmc;
8224 }
8225
8226 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8227 if (err) {
8228 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8229 err = -ENOENT;
8230 goto err_configure_lan_hmc;
8231 }
8232
8233 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8234 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8235 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8236 err = -EIO;
8237 goto err_mac_addr;
8238 }
8239 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
8240 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
8241
8242 pci_set_drvdata(pdev, pf);
8243 pci_save_state(pdev);
4e3b35b0
NP		 8244#ifdef CONFIG_I40E_DCB
8245 err = i40e_init_pf_dcb(pf);
8246 if (err) {
8247 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
8248 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8249 goto err_init_dcb;
8250 }
8251#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8252
8253 /* set up periodic task facility */
8254 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8255 pf->service_timer_period = HZ;
8256
8257 INIT_WORK(&pf->service_task, i40e_service_task);
8258 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8259 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8260 pf->link_check_timeout = jiffies;
8261
8e2773ae
SN		 8262 /* WoL defaults to disabled */
8263 pf->wol_en = false;
8264 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8265
41c445ff
JB		 8266 /* set up the main switch operations */
8267 i40e_determine_queue_usage(pf);
8268 i40e_init_interrupt_scheme(pf);
8269
8270 /* Set up the *vsi struct based on the number of VSIs in the HW,
8271 * and set up our local tracking of the MAIN PF vsi.
8272 */
8273 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
8274 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8275 if (!pf->vsi) {
8276 err = -ENOMEM;
41c445ff 8277 goto err_switch_setup;
ed87ac09 8278 }
41c445ff 8279
bc7d338f 8280 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8281 if (err) {
8282 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8283 goto err_vsis;
8284 }
8285
8286 /* The main driver is (mostly) up and happy. We need to set this state
8287 * before setting up the misc vector or we get a race and the vector
8288 * ends up disabled forever.
8289 */
8290 clear_bit(__I40E_DOWN, &pf->state);
8291
8292 /* In case of MSIX we are going to setup the misc vector right here
8293 * to handle admin queue events etc. In case of legacy and MSI
8294 * the misc functionality and queue processing is combined in
8295 * the same vector and that gets setup at open.
8296 */
8297 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8298 err = i40e_setup_misc_vector(pf);
8299 if (err) {
8300 dev_info(&pdev->dev,
8301 "setup of misc vector failed: %d\n", err);
8302 goto err_vsis;
8303 }
8304 }
8305
8306 /* prep for VF support */
8307 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8308 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8309 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8310 u32 val;
8311
8312 /* disable link interrupts for VFs */
8313 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8314 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8315 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8316 i40e_flush(hw);
4aeec010
MW		 8317
8318 if (pci_num_vf(pdev)) {
8319 dev_info(&pdev->dev,
8320 "Active VFs found, allocating resources.\n");
8321 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8322 if (err)
8323 dev_info(&pdev->dev,
8324 "Error %d allocating resources for existing VFs\n",
8325 err);
8326 }
41c445ff
JB		 8327 }
8328
93cd765b
ASJ		 8329 pfs_found++;
8330
41c445ff
JB		 8331 i40e_dbg_pf_init(pf);
8332
8333 /* tell the firmware that we're starting */
8334 dv.major_version = DRV_VERSION_MAJOR;
8335 dv.minor_version = DRV_VERSION_MINOR;
8336 dv.build_version = DRV_VERSION_BUILD;
8337 dv.subbuild_version = 0;
8338 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
8339
8340 /* since everything's happy, start the service_task timer */
8341 mod_timer(&pf->service_timer,
8342 round_jiffies(jiffies + pf->service_timer_period));
8343
d4dfb81a
CS		 8344 /* Get the negotiated link width and speed from PCI config space */
8345 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8346
8347 i40e_set_pci_config_data(hw, link_status);
8348
69bfb110 8349 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8350 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8351 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8352 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8353 "Unknown"),
8354 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8355 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8356 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8357 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8358 "Unknown"));
8359
8360 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8361 hw->bus.speed < i40e_bus_speed_8000) {
8362 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8363 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8364 }
8365
0c22b3dd
JB		 8366 /* print a string summarizing features */
8367 i40e_print_features(pf);
8368
41c445ff
JB		 8369 return 0;
8370
8371 /* Unwind what we've done if something failed in the setup */
8372err_vsis:
8373 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8374 i40e_clear_interrupt_scheme(pf);
8375 kfree(pf->vsi);
04b03013
SN		 8376err_switch_setup:
8377 i40e_reset_interrupt_capability(pf);
41c445ff 8378 del_timer_sync(&pf->service_timer);
4e3b35b0
NP		 8379#ifdef CONFIG_I40E_DCB
8380err_init_dcb:
8381#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8382err_mac_addr:
8383err_configure_lan_hmc:
8384 (void)i40e_shutdown_lan_hmc(hw);
8385err_init_lan_hmc:
8386 kfree(pf->qp_pile);
8387 kfree(pf->irq_pile);
8388err_sw_init:
8389err_adminq_setup:
8390 (void)i40e_shutdown_adminq(hw);
8391err_pf_reset:
8392 iounmap(hw->hw_addr);
8393err_ioremap:
8394 kfree(pf);
8395err_pf_alloc:
8396 pci_disable_pcie_error_reporting(pdev);
8397 pci_release_selected_regions(pdev,
8398 pci_select_bars(pdev, IORESOURCE_MEM));
8399err_pci_reg:
8400err_dma:
8401 pci_disable_device(pdev);
8402 return err;
8403}
8404
8405/**
8406 * i40e_remove - Device removal routine
8407 * @pdev: PCI device information struct
8408 *
8409 * i40e_remove is called by the PCI subsystem to alert the driver
8410 * that is should release a PCI device. This could be caused by a
8411 * Hot-Plug event, or because the driver is going to be removed from
8412 * memory.
8413 **/
8414static void i40e_remove(struct pci_dev *pdev)
8415{
8416 struct i40e_pf *pf = pci_get_drvdata(pdev);
8417 i40e_status ret_code;
8418 u32 reg;
8419 int i;
8420
8421 i40e_dbg_pf_exit(pf);
8422
beb0dff1
JK		 8423 i40e_ptp_stop(pf);
8424
41c445ff
JB		 8425 /* no more scheduling of any task */
8426 set_bit(__I40E_DOWN, &pf->state);
8427 del_timer_sync(&pf->service_timer);
8428 cancel_work_sync(&pf->service_task);
8429
eb2d80bc
MW		 8430 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8431 i40e_free_vfs(pf);
8432 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8433 }
8434
41c445ff
JB		 8435 i40e_fdir_teardown(pf);
8436
8437 /* If there is a switch structure or any orphans, remove them.
8438 * This will leave only the PF's VSI remaining.
8439 */
8440 for (i = 0; i < I40E_MAX_VEB; i++) {
8441 if (!pf->veb[i])
8442 continue;
8443
8444 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8445 pf->veb[i]->uplink_seid == 0)
8446 i40e_switch_branch_release(pf->veb[i]);
8447 }
8448
8449 /* Now we can shutdown the PF's VSI, just before we kill
8450 * adminq and hmc.
8451 */
8452 if (pf->vsi[pf->lan_vsi])
8453 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8454
8455 i40e_stop_misc_vector(pf);
8456 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8457 synchronize_irq(pf->msix_entries[0].vector);
8458 free_irq(pf->msix_entries[0].vector, pf);
8459 }
8460
8461 /* shutdown and destroy the HMC */
8462 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8463 if (ret_code)
8464 dev_warn(&pdev->dev,
8465 "Failed to destroy the HMC resources: %d\n", ret_code);
8466
8467 /* shutdown the adminq */
41c445ff
JB		 8468 ret_code = i40e_shutdown_adminq(&pf->hw);
8469 if (ret_code)
8470 dev_warn(&pdev->dev,
8471 "Failed to destroy the Admin Queue resources: %d\n",
8472 ret_code);
8473
8474 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8475 i40e_clear_interrupt_scheme(pf);
8476 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8477 if (pf->vsi[i]) {
8478 i40e_vsi_clear_rings(pf->vsi[i]);
8479 i40e_vsi_clear(pf->vsi[i]);
8480 pf->vsi[i] = NULL;
8481 }
8482 }
8483
8484 for (i = 0; i < I40E_MAX_VEB; i++) {
8485 kfree(pf->veb[i]);
8486 pf->veb[i] = NULL;
8487 }
8488
8489 kfree(pf->qp_pile);
8490 kfree(pf->irq_pile);
8491 kfree(pf->sw_config);
8492 kfree(pf->vsi);
8493
8494 /* force a PF reset to clean anything leftover */
8495 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8496 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8497 i40e_flush(&pf->hw);
8498
8499 iounmap(pf->hw.hw_addr);
8500 kfree(pf);
8501 pci_release_selected_regions(pdev,
8502 pci_select_bars(pdev, IORESOURCE_MEM));
8503
8504 pci_disable_pcie_error_reporting(pdev);
8505 pci_disable_device(pdev);
8506}
8507
8508/**
8509 * i40e_pci_error_detected - warning that something funky happened in PCI land
8510 * @pdev: PCI device information struct
8511 *
8512 * Called to warn that something happened and the error handling steps
8513 * are in progress. Allows the driver to quiesce things, be ready for
8514 * remediation.
8515 **/
8516static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8517 enum pci_channel_state error)
8518{
8519 struct i40e_pf *pf = pci_get_drvdata(pdev);
8520
8521 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8522
8523 /* shutdown all operations */
9007bccd
SN		 8524 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8525 rtnl_lock();
8526 i40e_prep_for_reset(pf);
8527 rtnl_unlock();
8528 }
41c445ff
JB		 8529
8530 /* Request a slot reset */
8531 return PCI_ERS_RESULT_NEED_RESET;
8532}
8533
8534/**
8535 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8536 * @pdev: PCI device information struct
8537 *
8538 * Called to find if the driver can work with the device now that
8539 * the pci slot has been reset. If a basic connection seems good
8540 * (registers are readable and have sane content) then return a
8541 * happy little PCI_ERS_RESULT_xxx.
8542 **/
8543static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8544{
8545 struct i40e_pf *pf = pci_get_drvdata(pdev);
8546 pci_ers_result_t result;
8547 int err;
8548 u32 reg;
8549
8550 dev_info(&pdev->dev, "%s\n", __func__);
8551 if (pci_enable_device_mem(pdev)) {
8552 dev_info(&pdev->dev,
8553 "Cannot re-enable PCI device after reset.\n");
8554 result = PCI_ERS_RESULT_DISCONNECT;
8555 } else {
8556 pci_set_master(pdev);
8557 pci_restore_state(pdev);
8558 pci_save_state(pdev);
8559 pci_wake_from_d3(pdev, false);
8560
8561 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8562 if (reg == 0)
8563 result = PCI_ERS_RESULT_RECOVERED;
8564 else
8565 result = PCI_ERS_RESULT_DISCONNECT;
8566 }
8567
8568 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8569 if (err) {
8570 dev_info(&pdev->dev,
8571 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8572 err);
8573 /* non-fatal, continue */
8574 }
8575
8576 return result;
8577}
8578
8579/**
8580 * i40e_pci_error_resume - restart operations after PCI error recovery
8581 * @pdev: PCI device information struct
8582 *
8583 * Called to allow the driver to bring things back up after PCI error
8584 * and/or reset recovery has finished.
8585 **/
8586static void i40e_pci_error_resume(struct pci_dev *pdev)
8587{
8588 struct i40e_pf *pf = pci_get_drvdata(pdev);
8589
8590 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8591 if (test_bit(__I40E_SUSPENDED, &pf->state))
8592 return;
8593
8594 rtnl_lock();
41c445ff 8595 i40e_handle_reset_warning(pf);
9007bccd
SN		 8596 rtnl_lock();
8597}
8598
8599/**
8600 * i40e_shutdown - PCI callback for shutting down
8601 * @pdev: PCI device information struct
8602 **/
8603static void i40e_shutdown(struct pci_dev *pdev)
8604{
8605 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8606 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8607
8608 set_bit(__I40E_SUSPENDED, &pf->state);
8609 set_bit(__I40E_DOWN, &pf->state);
8610 rtnl_lock();
8611 i40e_prep_for_reset(pf);
8612 rtnl_unlock();
8613
8e2773ae
SN		 8614 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8615 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8616
9007bccd 8617 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8618 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8619 pci_set_power_state(pdev, PCI_D3hot);
8620 }
8621}
8622
8623#ifdef CONFIG_PM
8624/**
8625 * i40e_suspend - PCI callback for moving to D3
8626 * @pdev: PCI device information struct
8627 **/
8628static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8629{
8630 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8631 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8632
8633 set_bit(__I40E_SUSPENDED, &pf->state);
8634 set_bit(__I40E_DOWN, &pf->state);
8635 rtnl_lock();
8636 i40e_prep_for_reset(pf);
8637 rtnl_unlock();
8638
8e2773ae
SN		 8639 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8640 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8641
8642 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8643 pci_set_power_state(pdev, PCI_D3hot);
8644
8645 return 0;
41c445ff
JB		 8646}
8647
9007bccd
SN		 8648/**
8649 * i40e_resume - PCI callback for waking up from D3
8650 * @pdev: PCI device information struct
8651 **/
8652static int i40e_resume(struct pci_dev *pdev)
8653{
8654 struct i40e_pf *pf = pci_get_drvdata(pdev);
8655 u32 err;
8656
8657 pci_set_power_state(pdev, PCI_D0);
8658 pci_restore_state(pdev);
8659 /* pci_restore_state() clears dev->state_saves, so
8660 * call pci_save_state() again to restore it.
8661 */
8662 pci_save_state(pdev);
8663
8664 err = pci_enable_device_mem(pdev);
8665 if (err) {
8666 dev_err(&pdev->dev,
8667 "%s: Cannot enable PCI device from suspend\n",
8668 __func__);
8669 return err;
8670 }
8671 pci_set_master(pdev);
8672
8673 /* no wakeup events while running */
8674 pci_wake_from_d3(pdev, false);
8675
8676 /* handling the reset will rebuild the device state */
8677 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8678 clear_bit(__I40E_DOWN, &pf->state);
8679 rtnl_lock();
8680 i40e_reset_and_rebuild(pf, false);
8681 rtnl_unlock();
8682 }
8683
8684 return 0;
8685}
8686
8687#endif
41c445ff
JB		 8688static const struct pci_error_handlers i40e_err_handler = {
8689 .error_detected = i40e_pci_error_detected,
8690 .slot_reset = i40e_pci_error_slot_reset,
8691 .resume = i40e_pci_error_resume,
8692};
8693
8694static struct pci_driver i40e_driver = {
8695 .name = i40e_driver_name,
8696 .id_table = i40e_pci_tbl,
8697 .probe = i40e_probe,
8698 .remove = i40e_remove,
9007bccd
SN		 8699#ifdef CONFIG_PM
8700 .suspend = i40e_suspend,
8701 .resume = i40e_resume,
8702#endif
8703 .shutdown = i40e_shutdown,
41c445ff
JB		 8704 .err_handler = &i40e_err_handler,
8705 .sriov_configure = i40e_pci_sriov_configure,
8706};
8707
8708/**
8709 * i40e_init_module - Driver registration routine
8710 *
8711 * i40e_init_module is the first routine called when the driver is
8712 * loaded. All it does is register with the PCI subsystem.
8713 **/
8714static int __init i40e_init_module(void)
8715{
8716 pr_info("%s: %s - version %s\n", i40e_driver_name,
8717 i40e_driver_string, i40e_driver_version_str);
8718 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8719 i40e_dbg_init();
8720 return pci_register_driver(&i40e_driver);
8721}
8722module_init(i40e_init_module);
8723
8724/**
8725 * i40e_exit_module - Driver exit cleanup routine
8726 *
8727 * i40e_exit_module is called just before the driver is removed
8728 * from memory.
8729 **/
8730static void __exit i40e_exit_module(void)
8731{
8732 pci_unregister_driver(&i40e_driver);
8733 i40e_dbg_exit();
8734}
8735module_exit(i40e_exit_module);
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