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i40evf: fix oops in watchdog handler
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
a1c9a9d9
JK		 29#ifdef CONFIG_I40E_VXLAN
30#include <net/vxlan.h>
31#endif
41c445ff
JB		 32
33const char i40e_driver_name[] = "i40e";
34static const char i40e_driver_string[] =
35 "Intel(R) Ethernet Connection XL710 Network Driver";
36
37#define DRV_KERN "-k"
38
39#define DRV_VERSION_MAJOR 0
40#define DRV_VERSION_MINOR 3
db446094 41#define DRV_VERSION_BUILD 36
41c445ff
JB		 42#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
43 __stringify(DRV_VERSION_MINOR) "." \
44 __stringify(DRV_VERSION_BUILD) DRV_KERN
45const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 46static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 47
48/* a bit of forward declarations */
49static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
50static void i40e_handle_reset_warning(struct i40e_pf *pf);
51static int i40e_add_vsi(struct i40e_vsi *vsi);
52static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 53static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 54static int i40e_setup_misc_vector(struct i40e_pf *pf);
55static void i40e_determine_queue_usage(struct i40e_pf *pf);
56static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 57static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 58static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 59
60/* i40e_pci_tbl - PCI Device ID Table
61 *
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e
SN		 68 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X710), 0},
70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_D), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
273static void i40e_tx_timeout(struct net_device *netdev)
274{
275 struct i40e_netdev_priv *np = netdev_priv(netdev);
276 struct i40e_vsi *vsi = np->vsi;
277 struct i40e_pf *pf = vsi->back;
278
279 pf->tx_timeout_count++;
280
281 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
282 pf->tx_timeout_recovery_level = 0;
283 pf->tx_timeout_last_recovery = jiffies;
284 netdev_info(netdev, "tx_timeout recovery level %d\n",
285 pf->tx_timeout_recovery_level);
286
287 switch (pf->tx_timeout_recovery_level) {
288 case 0:
289 /* disable and re-enable queues for the VSI */
290 if (in_interrupt()) {
291 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
292 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
293 } else {
294 i40e_vsi_reinit_locked(vsi);
295 }
296 break;
297 case 1:
298 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
299 break;
300 case 2:
301 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
302 break;
303 case 3:
304 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
305 break;
306 default:
307 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 308 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 309 i40e_down(vsi);
310 break;
311 }
312 i40e_service_event_schedule(pf);
313 pf->tx_timeout_recovery_level++;
314}
315
316/**
317 * i40e_release_rx_desc - Store the new tail and head values
318 * @rx_ring: ring to bump
319 * @val: new head index
320 **/
321static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
322{
323 rx_ring->next_to_use = val;
324
325 /* Force memory writes to complete before letting h/w
326 * know there are new descriptors to fetch. (Only
327 * applicable for weak-ordered memory model archs,
328 * such as IA-64).
329 */
330 wmb();
331 writel(val, rx_ring->tail);
332}
333
334/**
335 * i40e_get_vsi_stats_struct - Get System Network Statistics
336 * @vsi: the VSI we care about
337 *
338 * Returns the address of the device statistics structure.
339 * The statistics are actually updated from the service task.
340 **/
341struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
342{
343 return &vsi->net_stats;
344}
345
346/**
347 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
348 * @netdev: network interface device structure
349 *
350 * Returns the address of the device statistics structure.
351 * The statistics are actually updated from the service task.
352 **/
353static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
354 struct net_device *netdev,
980e9b11 355 struct rtnl_link_stats64 *stats)
41c445ff
JB		 356{
357 struct i40e_netdev_priv *np = netdev_priv(netdev);
358 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 359 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
360 int i;
361
bc7d338f
ASJ		 362 if (test_bit(__I40E_DOWN, &vsi->state))
363 return stats;
364
3c325ced
JB		 365 if (!vsi->tx_rings)
366 return stats;
367
980e9b11
AD		 368 rcu_read_lock();
369 for (i = 0; i < vsi->num_queue_pairs; i++) {
370 struct i40e_ring *tx_ring, *rx_ring;
371 u64 bytes, packets;
372 unsigned int start;
373
374 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
375 if (!tx_ring)
376 continue;
377
378 do {
57a7744e 379 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 380 packets = tx_ring->stats.packets;
381 bytes = tx_ring->stats.bytes;
57a7744e 382 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 383
384 stats->tx_packets += packets;
385 stats->tx_bytes += bytes;
386 rx_ring = &tx_ring[1];
387
388 do {
57a7744e 389 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 390 packets = rx_ring->stats.packets;
391 bytes = rx_ring->stats.bytes;
57a7744e 392 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 393
980e9b11
AD		 394 stats->rx_packets += packets;
395 stats->rx_bytes += bytes;
396 }
397 rcu_read_unlock();
398
399 /* following stats updated by ixgbe_watchdog_task() */
400 stats->multicast = vsi_stats->multicast;
401 stats->tx_errors = vsi_stats->tx_errors;
402 stats->tx_dropped = vsi_stats->tx_dropped;
403 stats->rx_errors = vsi_stats->rx_errors;
404 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
405 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 406
980e9b11 407 return stats;
41c445ff
JB		 408}
409
410/**
411 * i40e_vsi_reset_stats - Resets all stats of the given vsi
412 * @vsi: the VSI to have its stats reset
413 **/
414void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
415{
416 struct rtnl_link_stats64 *ns;
417 int i;
418
419 if (!vsi)
420 return;
421
422 ns = i40e_get_vsi_stats_struct(vsi);
423 memset(ns, 0, sizeof(*ns));
424 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
425 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
426 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 427 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 428 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 429 memset(&vsi->rx_rings[i]->stats, 0 ,
430 sizeof(vsi->rx_rings[i]->stats));
431 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
432 sizeof(vsi->rx_rings[i]->rx_stats));
433 memset(&vsi->tx_rings[i]->stats, 0 ,
434 sizeof(vsi->tx_rings[i]->stats));
435 memset(&vsi->tx_rings[i]->tx_stats, 0,
436 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 437 }
8e9dca53 438 }
41c445ff
JB		 439 vsi->stat_offsets_loaded = false;
440}
441
442/**
443 * i40e_pf_reset_stats - Reset all of the stats for the given pf
444 * @pf: the PF to be reset
445 **/
446void i40e_pf_reset_stats(struct i40e_pf *pf)
447{
448 memset(&pf->stats, 0, sizeof(pf->stats));
449 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
450 pf->stat_offsets_loaded = false;
451}
452
453/**
454 * i40e_stat_update48 - read and update a 48 bit stat from the chip
455 * @hw: ptr to the hardware info
456 * @hireg: the high 32 bit reg to read
457 * @loreg: the low 32 bit reg to read
458 * @offset_loaded: has the initial offset been loaded yet
459 * @offset: ptr to current offset value
460 * @stat: ptr to the stat
461 *
462 * Since the device stats are not reset at PFReset, they likely will not
463 * be zeroed when the driver starts. We'll save the first values read
464 * and use them as offsets to be subtracted from the raw values in order
465 * to report stats that count from zero. In the process, we also manage
466 * the potential roll-over.
467 **/
468static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
469 bool offset_loaded, u64 *offset, u64 *stat)
470{
471 u64 new_data;
472
ab60085e 473 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 474 new_data = rd32(hw, loreg);
475 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
476 } else {
477 new_data = rd64(hw, loreg);
478 }
479 if (!offset_loaded)
480 *offset = new_data;
481 if (likely(new_data >= *offset))
482 *stat = new_data - *offset;
483 else
484 *stat = (new_data + ((u64)1 << 48)) - *offset;
485 *stat &= 0xFFFFFFFFFFFFULL;
486}
487
488/**
489 * i40e_stat_update32 - read and update a 32 bit stat from the chip
490 * @hw: ptr to the hardware info
491 * @reg: the hw reg to read
492 * @offset_loaded: has the initial offset been loaded yet
493 * @offset: ptr to current offset value
494 * @stat: ptr to the stat
495 **/
496static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
497 bool offset_loaded, u64 *offset, u64 *stat)
498{
499 u32 new_data;
500
501 new_data = rd32(hw, reg);
502 if (!offset_loaded)
503 *offset = new_data;
504 if (likely(new_data >= *offset))
505 *stat = (u32)(new_data - *offset);
506 else
507 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
508}
509
510/**
511 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
512 * @vsi: the VSI to be updated
513 **/
514void i40e_update_eth_stats(struct i40e_vsi *vsi)
515{
516 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
517 struct i40e_pf *pf = vsi->back;
518 struct i40e_hw *hw = &pf->hw;
519 struct i40e_eth_stats *oes;
520 struct i40e_eth_stats *es; /* device's eth stats */
521
522 es = &vsi->eth_stats;
523 oes = &vsi->eth_stats_offsets;
524
525 /* Gather up the stats that the hw collects */
526 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
527 vsi->stat_offsets_loaded,
528 &oes->tx_errors, &es->tx_errors);
529 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
530 vsi->stat_offsets_loaded,
531 &oes->rx_discards, &es->rx_discards);
532
533 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
534 I40E_GLV_GORCL(stat_idx),
535 vsi->stat_offsets_loaded,
536 &oes->rx_bytes, &es->rx_bytes);
537 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
538 I40E_GLV_UPRCL(stat_idx),
539 vsi->stat_offsets_loaded,
540 &oes->rx_unicast, &es->rx_unicast);
541 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
542 I40E_GLV_MPRCL(stat_idx),
543 vsi->stat_offsets_loaded,
544 &oes->rx_multicast, &es->rx_multicast);
545 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
546 I40E_GLV_BPRCL(stat_idx),
547 vsi->stat_offsets_loaded,
548 &oes->rx_broadcast, &es->rx_broadcast);
549
550 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
551 I40E_GLV_GOTCL(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->tx_bytes, &es->tx_bytes);
554 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
555 I40E_GLV_UPTCL(stat_idx),
556 vsi->stat_offsets_loaded,
557 &oes->tx_unicast, &es->tx_unicast);
558 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
559 I40E_GLV_MPTCL(stat_idx),
560 vsi->stat_offsets_loaded,
561 &oes->tx_multicast, &es->tx_multicast);
562 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
563 I40E_GLV_BPTCL(stat_idx),
564 vsi->stat_offsets_loaded,
565 &oes->tx_broadcast, &es->tx_broadcast);
566 vsi->stat_offsets_loaded = true;
567}
568
569/**
570 * i40e_update_veb_stats - Update Switch component statistics
571 * @veb: the VEB being updated
572 **/
573static void i40e_update_veb_stats(struct i40e_veb *veb)
574{
575 struct i40e_pf *pf = veb->pf;
576 struct i40e_hw *hw = &pf->hw;
577 struct i40e_eth_stats *oes;
578 struct i40e_eth_stats *es; /* device's eth stats */
579 int idx = 0;
580
581 idx = veb->stats_idx;
582 es = &veb->stats;
583 oes = &veb->stats_offsets;
584
585 /* Gather up the stats that the hw collects */
586 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
587 veb->stat_offsets_loaded,
588 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 589 if (hw->revision_id > 0)
590 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
591 veb->stat_offsets_loaded,
592 &oes->rx_unknown_protocol,
593 &es->rx_unknown_protocol);
41c445ff
JB		 594 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
595 veb->stat_offsets_loaded,
596 &oes->rx_bytes, &es->rx_bytes);
597 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
598 veb->stat_offsets_loaded,
599 &oes->rx_unicast, &es->rx_unicast);
600 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
601 veb->stat_offsets_loaded,
602 &oes->rx_multicast, &es->rx_multicast);
603 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
604 veb->stat_offsets_loaded,
605 &oes->rx_broadcast, &es->rx_broadcast);
606
607 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
608 veb->stat_offsets_loaded,
609 &oes->tx_bytes, &es->tx_bytes);
610 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
611 veb->stat_offsets_loaded,
612 &oes->tx_unicast, &es->tx_unicast);
613 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
614 veb->stat_offsets_loaded,
615 &oes->tx_multicast, &es->tx_multicast);
616 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
617 veb->stat_offsets_loaded,
618 &oes->tx_broadcast, &es->tx_broadcast);
619 veb->stat_offsets_loaded = true;
620}
621
622/**
623 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
624 * @pf: the corresponding PF
625 *
626 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
627 **/
628static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
629{
630 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
631 struct i40e_hw_port_stats *nsd = &pf->stats;
632 struct i40e_hw *hw = &pf->hw;
633 u64 xoff = 0;
634 u16 i, v;
635
636 if ((hw->fc.current_mode != I40E_FC_FULL) &&
637 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
638 return;
639
640 xoff = nsd->link_xoff_rx;
641 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
642 pf->stat_offsets_loaded,
643 &osd->link_xoff_rx, &nsd->link_xoff_rx);
644
645 /* No new LFC xoff rx */
646 if (!(nsd->link_xoff_rx - xoff))
647 return;
648
649 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
650 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
651 struct i40e_vsi *vsi = pf->vsi[v];
652
653 if (!vsi)
654 continue;
655
656 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 657 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 658 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
659 }
660 }
661}
662
663/**
664 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
665 * @pf: the corresponding PF
666 *
667 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
668 **/
669static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
670{
671 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
672 struct i40e_hw_port_stats *nsd = &pf->stats;
673 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
674 struct i40e_dcbx_config *dcb_cfg;
675 struct i40e_hw *hw = &pf->hw;
676 u16 i, v;
677 u8 tc;
678
679 dcb_cfg = &hw->local_dcbx_config;
680
681 /* See if DCB enabled with PFC TC */
682 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
683 !(dcb_cfg->pfc.pfcenable)) {
684 i40e_update_link_xoff_rx(pf);
685 return;
686 }
687
688 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
689 u64 prio_xoff = nsd->priority_xoff_rx[i];
690 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
691 pf->stat_offsets_loaded,
692 &osd->priority_xoff_rx[i],
693 &nsd->priority_xoff_rx[i]);
694
695 /* No new PFC xoff rx */
696 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
697 continue;
698 /* Get the TC for given priority */
699 tc = dcb_cfg->etscfg.prioritytable[i];
700 xoff[tc] = true;
701 }
702
703 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
704 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
705 struct i40e_vsi *vsi = pf->vsi[v];
706
707 if (!vsi)
708 continue;
709
710 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 711 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 712
713 tc = ring->dcb_tc;
714 if (xoff[tc])
715 clear_bit(__I40E_HANG_CHECK_ARMED,
716 &ring->state);
717 }
718 }
719}
720
721/**
722 * i40e_update_stats - Update the board statistics counters.
723 * @vsi: the VSI to be updated
724 *
725 * There are a few instances where we store the same stat in a
726 * couple of different structs. This is partly because we have
727 * the netdev stats that need to be filled out, which is slightly
728 * different from the "eth_stats" defined by the chip and used in
729 * VF communications. We sort it all out here in a central place.
730 **/
731void i40e_update_stats(struct i40e_vsi *vsi)
732{
733 struct i40e_pf *pf = vsi->back;
734 struct i40e_hw *hw = &pf->hw;
735 struct rtnl_link_stats64 *ons;
736 struct rtnl_link_stats64 *ns; /* netdev stats */
737 struct i40e_eth_stats *oes;
738 struct i40e_eth_stats *es; /* device's eth stats */
739 u32 tx_restart, tx_busy;
740 u32 rx_page, rx_buf;
741 u64 rx_p, rx_b;
742 u64 tx_p, tx_b;
bee5af7e 743 u32 val;
41c445ff
JB		 744 int i;
745 u16 q;
746
747 if (test_bit(__I40E_DOWN, &vsi->state) ||
748 test_bit(__I40E_CONFIG_BUSY, &pf->state))
749 return;
750
751 ns = i40e_get_vsi_stats_struct(vsi);
752 ons = &vsi->net_stats_offsets;
753 es = &vsi->eth_stats;
754 oes = &vsi->eth_stats_offsets;
755
756 /* Gather up the netdev and vsi stats that the driver collects
757 * on the fly during packet processing
758 */
759 rx_b = rx_p = 0;
760 tx_b = tx_p = 0;
761 tx_restart = tx_busy = 0;
762 rx_page = 0;
763 rx_buf = 0;
980e9b11 764 rcu_read_lock();
41c445ff
JB		 765 for (q = 0; q < vsi->num_queue_pairs; q++) {
766 struct i40e_ring *p;
980e9b11
AD		 767 u64 bytes, packets;
768 unsigned int start;
769
770 /* locate Tx ring */
771 p = ACCESS_ONCE(vsi->tx_rings[q]);
772
773 do {
57a7744e 774 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 775 packets = p->stats.packets;
776 bytes = p->stats.bytes;
57a7744e 777 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 778 tx_b += bytes;
779 tx_p += packets;
780 tx_restart += p->tx_stats.restart_queue;
781 tx_busy += p->tx_stats.tx_busy;
41c445ff 782
980e9b11
AD		 783 /* Rx queue is part of the same block as Tx queue */
784 p = &p[1];
785 do {
57a7744e 786 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 787 packets = p->stats.packets;
788 bytes = p->stats.bytes;
57a7744e 789 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 790 rx_b += bytes;
791 rx_p += packets;
420136cc
MW		 792 rx_buf += p->rx_stats.alloc_buff_failed;
793 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 794 }
980e9b11 795 rcu_read_unlock();
41c445ff
JB		 796 vsi->tx_restart = tx_restart;
797 vsi->tx_busy = tx_busy;
798 vsi->rx_page_failed = rx_page;
799 vsi->rx_buf_failed = rx_buf;
800
801 ns->rx_packets = rx_p;
802 ns->rx_bytes = rx_b;
803 ns->tx_packets = tx_p;
804 ns->tx_bytes = tx_b;
805
806 i40e_update_eth_stats(vsi);
807 /* update netdev stats from eth stats */
808 ons->rx_errors = oes->rx_errors;
809 ns->rx_errors = es->rx_errors;
810 ons->tx_errors = oes->tx_errors;
811 ns->tx_errors = es->tx_errors;
812 ons->multicast = oes->rx_multicast;
813 ns->multicast = es->rx_multicast;
814 ons->tx_dropped = oes->tx_discards;
815 ns->tx_dropped = es->tx_discards;
816
817 /* Get the port data only if this is the main PF VSI */
818 if (vsi == pf->vsi[pf->lan_vsi]) {
819 struct i40e_hw_port_stats *nsd = &pf->stats;
820 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
821
822 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
823 I40E_GLPRT_GORCL(hw->port),
824 pf->stat_offsets_loaded,
825 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
826 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
827 I40E_GLPRT_GOTCL(hw->port),
828 pf->stat_offsets_loaded,
829 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
830 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
831 pf->stat_offsets_loaded,
832 &osd->eth.rx_discards,
833 &nsd->eth.rx_discards);
834 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
835 pf->stat_offsets_loaded,
836 &osd->eth.tx_discards,
837 &nsd->eth.tx_discards);
838 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
839 I40E_GLPRT_MPRCL(hw->port),
840 pf->stat_offsets_loaded,
841 &osd->eth.rx_multicast,
842 &nsd->eth.rx_multicast);
843
844 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
845 pf->stat_offsets_loaded,
846 &osd->tx_dropped_link_down,
847 &nsd->tx_dropped_link_down);
848
849 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
850 pf->stat_offsets_loaded,
851 &osd->crc_errors, &nsd->crc_errors);
852 ns->rx_crc_errors = nsd->crc_errors;
853
854 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
855 pf->stat_offsets_loaded,
856 &osd->illegal_bytes, &nsd->illegal_bytes);
857 ns->rx_errors = nsd->crc_errors
858 + nsd->illegal_bytes;
859
860 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
861 pf->stat_offsets_loaded,
862 &osd->mac_local_faults,
863 &nsd->mac_local_faults);
864 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
865 pf->stat_offsets_loaded,
866 &osd->mac_remote_faults,
867 &nsd->mac_remote_faults);
868
869 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
870 pf->stat_offsets_loaded,
871 &osd->rx_length_errors,
872 &nsd->rx_length_errors);
873 ns->rx_length_errors = nsd->rx_length_errors;
874
875 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
876 pf->stat_offsets_loaded,
877 &osd->link_xon_rx, &nsd->link_xon_rx);
878 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
879 pf->stat_offsets_loaded,
880 &osd->link_xon_tx, &nsd->link_xon_tx);
881 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
882 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
883 pf->stat_offsets_loaded,
884 &osd->link_xoff_tx, &nsd->link_xoff_tx);
885
886 for (i = 0; i < 8; i++) {
887 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
888 pf->stat_offsets_loaded,
889 &osd->priority_xon_rx[i],
890 &nsd->priority_xon_rx[i]);
891 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
892 pf->stat_offsets_loaded,
893 &osd->priority_xon_tx[i],
894 &nsd->priority_xon_tx[i]);
895 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
896 pf->stat_offsets_loaded,
897 &osd->priority_xoff_tx[i],
898 &nsd->priority_xoff_tx[i]);
899 i40e_stat_update32(hw,
900 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
901 pf->stat_offsets_loaded,
902 &osd->priority_xon_2_xoff[i],
903 &nsd->priority_xon_2_xoff[i]);
904 }
905
906 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
907 I40E_GLPRT_PRC64L(hw->port),
908 pf->stat_offsets_loaded,
909 &osd->rx_size_64, &nsd->rx_size_64);
910 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
911 I40E_GLPRT_PRC127L(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->rx_size_127, &nsd->rx_size_127);
914 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
915 I40E_GLPRT_PRC255L(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->rx_size_255, &nsd->rx_size_255);
918 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
919 I40E_GLPRT_PRC511L(hw->port),
920 pf->stat_offsets_loaded,
921 &osd->rx_size_511, &nsd->rx_size_511);
922 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
923 I40E_GLPRT_PRC1023L(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->rx_size_1023, &nsd->rx_size_1023);
926 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
927 I40E_GLPRT_PRC1522L(hw->port),
928 pf->stat_offsets_loaded,
929 &osd->rx_size_1522, &nsd->rx_size_1522);
930 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
931 I40E_GLPRT_PRC9522L(hw->port),
932 pf->stat_offsets_loaded,
933 &osd->rx_size_big, &nsd->rx_size_big);
934
935 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
936 I40E_GLPRT_PTC64L(hw->port),
937 pf->stat_offsets_loaded,
938 &osd->tx_size_64, &nsd->tx_size_64);
939 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
940 I40E_GLPRT_PTC127L(hw->port),
941 pf->stat_offsets_loaded,
942 &osd->tx_size_127, &nsd->tx_size_127);
943 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
944 I40E_GLPRT_PTC255L(hw->port),
945 pf->stat_offsets_loaded,
946 &osd->tx_size_255, &nsd->tx_size_255);
947 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
948 I40E_GLPRT_PTC511L(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->tx_size_511, &nsd->tx_size_511);
951 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
952 I40E_GLPRT_PTC1023L(hw->port),
953 pf->stat_offsets_loaded,
954 &osd->tx_size_1023, &nsd->tx_size_1023);
955 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
956 I40E_GLPRT_PTC1522L(hw->port),
957 pf->stat_offsets_loaded,
958 &osd->tx_size_1522, &nsd->tx_size_1522);
959 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
960 I40E_GLPRT_PTC9522L(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->tx_size_big, &nsd->tx_size_big);
963
964 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->rx_undersize, &nsd->rx_undersize);
967 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->rx_fragments, &nsd->rx_fragments);
970 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_oversize, &nsd->rx_oversize);
973 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
974 pf->stat_offsets_loaded,
975 &osd->rx_jabber, &nsd->rx_jabber);
bee5af7e
ASJ		 976
977 val = rd32(hw, I40E_PRTPM_EEE_STAT);
978 nsd->tx_lpi_status =
979 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
980 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
981 nsd->rx_lpi_status =
982 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
983 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
984 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
985 pf->stat_offsets_loaded,
986 &osd->tx_lpi_count, &nsd->tx_lpi_count);
987 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
988 pf->stat_offsets_loaded,
989 &osd->rx_lpi_count, &nsd->rx_lpi_count);
41c445ff
JB		 990 }
991
992 pf->stat_offsets_loaded = true;
993}
994
995/**
996 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
997 * @vsi: the VSI to be searched
998 * @macaddr: the MAC address
999 * @vlan: the vlan
1000 * @is_vf: make sure its a vf filter, else doesn't matter
1001 * @is_netdev: make sure its a netdev filter, else doesn't matter
1002 *
1003 * Returns ptr to the filter object or NULL
1004 **/
1005static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1006 u8 *macaddr, s16 vlan,
1007 bool is_vf, bool is_netdev)
1008{
1009 struct i40e_mac_filter *f;
1010
1011 if (!vsi || !macaddr)
1012 return NULL;
1013
1014 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1015 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1016 (vlan == f->vlan) &&
1017 (!is_vf || f->is_vf) &&
1018 (!is_netdev || f->is_netdev))
1019 return f;
1020 }
1021 return NULL;
1022}
1023
1024/**
1025 * i40e_find_mac - Find a mac addr in the macvlan filters list
1026 * @vsi: the VSI to be searched
1027 * @macaddr: the MAC address we are searching for
1028 * @is_vf: make sure its a vf filter, else doesn't matter
1029 * @is_netdev: make sure its a netdev filter, else doesn't matter
1030 *
1031 * Returns the first filter with the provided MAC address or NULL if
1032 * MAC address was not found
1033 **/
1034struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1035 bool is_vf, bool is_netdev)
1036{
1037 struct i40e_mac_filter *f;
1038
1039 if (!vsi || !macaddr)
1040 return NULL;
1041
1042 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1043 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1044 (!is_vf || f->is_vf) &&
1045 (!is_netdev || f->is_netdev))
1046 return f;
1047 }
1048 return NULL;
1049}
1050
1051/**
1052 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1053 * @vsi: the VSI to be searched
1054 *
1055 * Returns true if VSI is in vlan mode or false otherwise
1056 **/
1057bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1058{
1059 struct i40e_mac_filter *f;
1060
1061 /* Only -1 for all the filters denotes not in vlan mode
1062 * so we have to go through all the list in order to make sure
1063 */
1064 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1065 if (f->vlan >= 0)
1066 return true;
1067 }
1068
1069 return false;
1070}
1071
1072/**
1073 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1074 * @vsi: the VSI to be searched
1075 * @macaddr: the mac address to be filtered
1076 * @is_vf: true if it is a vf
1077 * @is_netdev: true if it is a netdev
1078 *
1079 * Goes through all the macvlan filters and adds a
1080 * macvlan filter for each unique vlan that already exists
1081 *
1082 * Returns first filter found on success, else NULL
1083 **/
1084struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1085 bool is_vf, bool is_netdev)
1086{
1087 struct i40e_mac_filter *f;
1088
1089 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1090 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1091 is_vf, is_netdev)) {
1092 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1093 is_vf, is_netdev))
41c445ff
JB		 1094 return NULL;
1095 }
1096 }
1097
1098 return list_first_entry_or_null(&vsi->mac_filter_list,
1099 struct i40e_mac_filter, list);
1100}
1101
1102/**
1103 * i40e_add_filter - Add a mac/vlan filter to the VSI
1104 * @vsi: the VSI to be searched
1105 * @macaddr: the MAC address
1106 * @vlan: the vlan
1107 * @is_vf: make sure its a vf filter, else doesn't matter
1108 * @is_netdev: make sure its a netdev filter, else doesn't matter
1109 *
1110 * Returns ptr to the filter object or NULL when no memory available.
1111 **/
1112struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1113 u8 *macaddr, s16 vlan,
1114 bool is_vf, bool is_netdev)
1115{
1116 struct i40e_mac_filter *f;
1117
1118 if (!vsi || !macaddr)
1119 return NULL;
1120
1121 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1122 if (!f) {
1123 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1124 if (!f)
1125 goto add_filter_out;
1126
1127 memcpy(f->macaddr, macaddr, ETH_ALEN);
1128 f->vlan = vlan;
1129 f->changed = true;
1130
1131 INIT_LIST_HEAD(&f->list);
1132 list_add(&f->list, &vsi->mac_filter_list);
1133 }
1134
1135 /* increment counter and add a new flag if needed */
1136 if (is_vf) {
1137 if (!f->is_vf) {
1138 f->is_vf = true;
1139 f->counter++;
1140 }
1141 } else if (is_netdev) {
1142 if (!f->is_netdev) {
1143 f->is_netdev = true;
1144 f->counter++;
1145 }
1146 } else {
1147 f->counter++;
1148 }
1149
1150 /* changed tells sync_filters_subtask to
1151 * push the filter down to the firmware
1152 */
1153 if (f->changed) {
1154 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1155 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1156 }
1157
1158add_filter_out:
1159 return f;
1160}
1161
1162/**
1163 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1164 * @vsi: the VSI to be searched
1165 * @macaddr: the MAC address
1166 * @vlan: the vlan
1167 * @is_vf: make sure it's a vf filter, else doesn't matter
1168 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1169 **/
1170void i40e_del_filter(struct i40e_vsi *vsi,
1171 u8 *macaddr, s16 vlan,
1172 bool is_vf, bool is_netdev)
1173{
1174 struct i40e_mac_filter *f;
1175
1176 if (!vsi || !macaddr)
1177 return;
1178
1179 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1180 if (!f || f->counter == 0)
1181 return;
1182
1183 if (is_vf) {
1184 if (f->is_vf) {
1185 f->is_vf = false;
1186 f->counter--;
1187 }
1188 } else if (is_netdev) {
1189 if (f->is_netdev) {
1190 f->is_netdev = false;
1191 f->counter--;
1192 }
1193 } else {
1194 /* make sure we don't remove a filter in use by vf or netdev */
1195 int min_f = 0;
1196 min_f += (f->is_vf ? 1 : 0);
1197 min_f += (f->is_netdev ? 1 : 0);
1198
1199 if (f->counter > min_f)
1200 f->counter--;
1201 }
1202
1203 /* counter == 0 tells sync_filters_subtask to
1204 * remove the filter from the firmware's list
1205 */
1206 if (f->counter == 0) {
1207 f->changed = true;
1208 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1209 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1210 }
1211}
1212
1213/**
1214 * i40e_set_mac - NDO callback to set mac address
1215 * @netdev: network interface device structure
1216 * @p: pointer to an address structure
1217 *
1218 * Returns 0 on success, negative on failure
1219 **/
1220static int i40e_set_mac(struct net_device *netdev, void *p)
1221{
1222 struct i40e_netdev_priv *np = netdev_priv(netdev);
1223 struct i40e_vsi *vsi = np->vsi;
1224 struct sockaddr *addr = p;
1225 struct i40e_mac_filter *f;
1226
1227 if (!is_valid_ether_addr(addr->sa_data))
1228 return -EADDRNOTAVAIL;
1229
1230 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1231
1232 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1233 return 0;
1234
80f6428f
ASJ		 1235 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1236 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1237 return -EADDRNOTAVAIL;
1238
41c445ff
JB		 1239 if (vsi->type == I40E_VSI_MAIN) {
1240 i40e_status ret;
1241 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1242 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1243 addr->sa_data, NULL);
1244 if (ret) {
1245 netdev_info(netdev,
1246 "Addr change for Main VSI failed: %d\n",
1247 ret);
1248 return -EADDRNOTAVAIL;
1249 }
1250
1251 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1252 }
1253
1254 /* In order to be sure to not drop any packets, add the new address
1255 * then delete the old one.
1256 */
1257 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1258 if (!f)
1259 return -ENOMEM;
1260
1261 i40e_sync_vsi_filters(vsi);
1262 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1263 i40e_sync_vsi_filters(vsi);
1264
1265 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1266
1267 return 0;
1268}
1269
1270/**
1271 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1272 * @vsi: the VSI being setup
1273 * @ctxt: VSI context structure
1274 * @enabled_tc: Enabled TCs bitmap
1275 * @is_add: True if called before Add VSI
1276 *
1277 * Setup VSI queue mapping for enabled traffic classes.
1278 **/
1279static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1280 struct i40e_vsi_context *ctxt,
1281 u8 enabled_tc,
1282 bool is_add)
1283{
1284 struct i40e_pf *pf = vsi->back;
1285 u16 sections = 0;
1286 u8 netdev_tc = 0;
1287 u16 numtc = 0;
1288 u16 qcount;
1289 u8 offset;
1290 u16 qmap;
1291 int i;
4e3b35b0 1292 u16 num_tc_qps = 0;
41c445ff
JB		 1293
1294 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1295 offset = 0;
1296
1297 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1298 /* Find numtc from enabled TC bitmap */
1299 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1300 if (enabled_tc & (1 << i)) /* TC is enabled */
1301 numtc++;
1302 }
1303 if (!numtc) {
1304 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1305 numtc = 1;
1306 }
1307 } else {
1308 /* At least TC0 is enabled in case of non-DCB case */
1309 numtc = 1;
1310 }
1311
1312 vsi->tc_config.numtc = numtc;
1313 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1314 /* Number of queues per enabled TC */
1315 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1316 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1317
1318 /* Setup queue offset/count for all TCs for given VSI */
1319 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1320 /* See if the given TC is enabled for the given VSI */
1321 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1322 int pow, num_qps;
1323
41c445ff
JB		 1324 switch (vsi->type) {
1325 case I40E_VSI_MAIN:
4e3b35b0 1326 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1327 break;
1328 case I40E_VSI_FDIR:
1329 case I40E_VSI_SRIOV:
1330 case I40E_VSI_VMDQ2:
1331 default:
4e3b35b0 1332 qcount = num_tc_qps;
41c445ff
JB		 1333 WARN_ON(i != 0);
1334 break;
1335 }
4e3b35b0
NP		 1336 vsi->tc_config.tc_info[i].qoffset = offset;
1337 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1338
1339 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1340 num_qps = qcount;
41c445ff 1341 pow = 0;
4e3b35b0 1342 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1343 pow++;
1344 num_qps >>= 1;
1345 }
1346
1347 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1348 qmap =
1349 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1350 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1351
4e3b35b0 1352 offset += qcount;
41c445ff
JB		 1353 } else {
1354 /* TC is not enabled so set the offset to
1355 * default queue and allocate one queue
1356 * for the given TC.
1357 */
1358 vsi->tc_config.tc_info[i].qoffset = 0;
1359 vsi->tc_config.tc_info[i].qcount = 1;
1360 vsi->tc_config.tc_info[i].netdev_tc = 0;
1361
1362 qmap = 0;
1363 }
1364 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1365 }
1366
1367 /* Set actual Tx/Rx queue pairs */
1368 vsi->num_queue_pairs = offset;
1369
1370 /* Scheduler section valid can only be set for ADD VSI */
1371 if (is_add) {
1372 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1373
1374 ctxt->info.up_enable_bits = enabled_tc;
1375 }
1376 if (vsi->type == I40E_VSI_SRIOV) {
1377 ctxt->info.mapping_flags |=
1378 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1379 for (i = 0; i < vsi->num_queue_pairs; i++)
1380 ctxt->info.queue_mapping[i] =
1381 cpu_to_le16(vsi->base_queue + i);
1382 } else {
1383 ctxt->info.mapping_flags |=
1384 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1385 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1386 }
1387 ctxt->info.valid_sections |= cpu_to_le16(sections);
1388}
1389
1390/**
1391 * i40e_set_rx_mode - NDO callback to set the netdev filters
1392 * @netdev: network interface device structure
1393 **/
1394static void i40e_set_rx_mode(struct net_device *netdev)
1395{
1396 struct i40e_netdev_priv *np = netdev_priv(netdev);
1397 struct i40e_mac_filter *f, *ftmp;
1398 struct i40e_vsi *vsi = np->vsi;
1399 struct netdev_hw_addr *uca;
1400 struct netdev_hw_addr *mca;
1401 struct netdev_hw_addr *ha;
1402
1403 /* add addr if not already in the filter list */
1404 netdev_for_each_uc_addr(uca, netdev) {
1405 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1406 if (i40e_is_vsi_in_vlan(vsi))
1407 i40e_put_mac_in_vlan(vsi, uca->addr,
1408 false, true);
1409 else
1410 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1411 false, true);
1412 }
1413 }
1414
1415 netdev_for_each_mc_addr(mca, netdev) {
1416 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1417 if (i40e_is_vsi_in_vlan(vsi))
1418 i40e_put_mac_in_vlan(vsi, mca->addr,
1419 false, true);
1420 else
1421 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1422 false, true);
1423 }
1424 }
1425
1426 /* remove filter if not in netdev list */
1427 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1428 bool found = false;
1429
1430 if (!f->is_netdev)
1431 continue;
1432
1433 if (is_multicast_ether_addr(f->macaddr)) {
1434 netdev_for_each_mc_addr(mca, netdev) {
1435 if (ether_addr_equal(mca->addr, f->macaddr)) {
1436 found = true;
1437 break;
1438 }
1439 }
1440 } else {
1441 netdev_for_each_uc_addr(uca, netdev) {
1442 if (ether_addr_equal(uca->addr, f->macaddr)) {
1443 found = true;
1444 break;
1445 }
1446 }
1447
1448 for_each_dev_addr(netdev, ha) {
1449 if (ether_addr_equal(ha->addr, f->macaddr)) {
1450 found = true;
1451 break;
1452 }
1453 }
1454 }
1455 if (!found)
1456 i40e_del_filter(
1457 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1458 }
1459
1460 /* check for other flag changes */
1461 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1462 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1463 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1464 }
1465}
1466
1467/**
1468 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1469 * @vsi: ptr to the VSI
1470 *
1471 * Push any outstanding VSI filter changes through the AdminQ.
1472 *
1473 * Returns 0 or error value
1474 **/
1475int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1476{
1477 struct i40e_mac_filter *f, *ftmp;
1478 bool promisc_forced_on = false;
1479 bool add_happened = false;
1480 int filter_list_len = 0;
1481 u32 changed_flags = 0;
dcae29be 1482 i40e_status aq_ret = 0;
41c445ff
JB		 1483 struct i40e_pf *pf;
1484 int num_add = 0;
1485 int num_del = 0;
1486 u16 cmd_flags;
1487
1488 /* empty array typed pointers, kcalloc later */
1489 struct i40e_aqc_add_macvlan_element_data *add_list;
1490 struct i40e_aqc_remove_macvlan_element_data *del_list;
1491
1492 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1493 usleep_range(1000, 2000);
1494 pf = vsi->back;
1495
1496 if (vsi->netdev) {
1497 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1498 vsi->current_netdev_flags = vsi->netdev->flags;
1499 }
1500
1501 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1502 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1503
1504 filter_list_len = pf->hw.aq.asq_buf_size /
1505 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1506 del_list = kcalloc(filter_list_len,
1507 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1508 GFP_KERNEL);
1509 if (!del_list)
1510 return -ENOMEM;
1511
1512 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1513 if (!f->changed)
1514 continue;
1515
1516 if (f->counter != 0)
1517 continue;
1518 f->changed = false;
1519 cmd_flags = 0;
1520
1521 /* add to delete list */
1522 memcpy(del_list[num_del].mac_addr,
1523 f->macaddr, ETH_ALEN);
1524 del_list[num_del].vlan_tag =
1525 cpu_to_le16((u16)(f->vlan ==
1526 I40E_VLAN_ANY ? 0 : f->vlan));
1527
41c445ff
JB		 1528 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1529 del_list[num_del].flags = cmd_flags;
1530 num_del++;
1531
1532 /* unlink from filter list */
1533 list_del(&f->list);
1534 kfree(f);
1535
1536 /* flush a full buffer */
1537 if (num_del == filter_list_len) {
dcae29be 1538 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1539 vsi->seid, del_list, num_del,
1540 NULL);
1541 num_del = 0;
1542 memset(del_list, 0, sizeof(*del_list));
1543
dcae29be 1544 if (aq_ret)
41c445ff
JB		 1545 dev_info(&pf->pdev->dev,
1546 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1547 aq_ret,
41c445ff
JB		 1548 pf->hw.aq.asq_last_status);
1549 }
1550 }
1551 if (num_del) {
dcae29be 1552 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1553 del_list, num_del, NULL);
1554 num_del = 0;
1555
dcae29be 1556 if (aq_ret)
41c445ff
JB		 1557 dev_info(&pf->pdev->dev,
1558 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1559 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1560 }
1561
1562 kfree(del_list);
1563 del_list = NULL;
1564
1565 /* do all the adds now */
1566 filter_list_len = pf->hw.aq.asq_buf_size /
1567 sizeof(struct i40e_aqc_add_macvlan_element_data),
1568 add_list = kcalloc(filter_list_len,
1569 sizeof(struct i40e_aqc_add_macvlan_element_data),
1570 GFP_KERNEL);
1571 if (!add_list)
1572 return -ENOMEM;
1573
1574 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1575 if (!f->changed)
1576 continue;
1577
1578 if (f->counter == 0)
1579 continue;
1580 f->changed = false;
1581 add_happened = true;
1582 cmd_flags = 0;
1583
1584 /* add to add array */
1585 memcpy(add_list[num_add].mac_addr,
1586 f->macaddr, ETH_ALEN);
1587 add_list[num_add].vlan_tag =
1588 cpu_to_le16(
1589 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1590 add_list[num_add].queue_number = 0;
1591
1592 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1593 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1594 num_add++;
1595
1596 /* flush a full buffer */
1597 if (num_add == filter_list_len) {
dcae29be
JB		 1598 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1599 add_list, num_add,
1600 NULL);
41c445ff
JB		 1601 num_add = 0;
1602
dcae29be 1603 if (aq_ret)
41c445ff
JB		 1604 break;
1605 memset(add_list, 0, sizeof(*add_list));
1606 }
1607 }
1608 if (num_add) {
dcae29be
JB		 1609 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1610 add_list, num_add, NULL);
41c445ff
JB		 1611 num_add = 0;
1612 }
1613 kfree(add_list);
1614 add_list = NULL;
1615
dcae29be 1616 if (add_happened && (!aq_ret)) {
41c445ff 1617 /* do nothing */;
dcae29be 1618 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1619 dev_info(&pf->pdev->dev,
1620 "add filter failed, err %d, aq_err %d\n",
dcae29be 1621 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1622 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1623 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1624 &vsi->state)) {
1625 promisc_forced_on = true;
1626 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1627 &vsi->state);
1628 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1629 }
1630 }
1631 }
1632
1633 /* check for changes in promiscuous modes */
1634 if (changed_flags & IFF_ALLMULTI) {
1635 bool cur_multipromisc;
1636 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1637 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1638 vsi->seid,
1639 cur_multipromisc,
1640 NULL);
1641 if (aq_ret)
41c445ff
JB		 1642 dev_info(&pf->pdev->dev,
1643 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1644 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1645 }
1646 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1647 bool cur_promisc;
1648 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1649 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1650 &vsi->state));
dcae29be
JB		 1651 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1652 vsi->seid,
1653 cur_promisc, NULL);
1654 if (aq_ret)
41c445ff
JB		 1655 dev_info(&pf->pdev->dev,
1656 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1657 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1658 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1659 vsi->seid,
1660 cur_promisc, NULL);
1661 if (aq_ret)
1662 dev_info(&pf->pdev->dev,
1663 "set brdcast promisc failed, err %d, aq_err %d\n",
1664 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1665 }
1666
1667 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1668 return 0;
1669}
1670
1671/**
1672 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1673 * @pf: board private structure
1674 **/
1675static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1676{
1677 int v;
1678
1679 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1680 return;
1681 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1682
1683 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1684 if (pf->vsi[v] &&
1685 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1686 i40e_sync_vsi_filters(pf->vsi[v]);
1687 }
1688}
1689
1690/**
1691 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1692 * @netdev: network interface device structure
1693 * @new_mtu: new value for maximum frame size
1694 *
1695 * Returns 0 on success, negative on failure
1696 **/
1697static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1698{
1699 struct i40e_netdev_priv *np = netdev_priv(netdev);
1700 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1701 struct i40e_vsi *vsi = np->vsi;
1702
1703 /* MTU < 68 is an error and causes problems on some kernels */
1704 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1705 return -EINVAL;
1706
1707 netdev_info(netdev, "changing MTU from %d to %d\n",
1708 netdev->mtu, new_mtu);
1709 netdev->mtu = new_mtu;
1710 if (netif_running(netdev))
1711 i40e_vsi_reinit_locked(vsi);
1712
1713 return 0;
1714}
1715
beb0dff1
JK		 1716/**
1717 * i40e_ioctl - Access the hwtstamp interface
1718 * @netdev: network interface device structure
1719 * @ifr: interface request data
1720 * @cmd: ioctl command
1721 **/
1722int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1723{
1724 struct i40e_netdev_priv *np = netdev_priv(netdev);
1725 struct i40e_pf *pf = np->vsi->back;
1726
1727 switch (cmd) {
1728 case SIOCGHWTSTAMP:
1729 return i40e_ptp_get_ts_config(pf, ifr);
1730 case SIOCSHWTSTAMP:
1731 return i40e_ptp_set_ts_config(pf, ifr);
1732 default:
1733 return -EOPNOTSUPP;
1734 }
1735}
1736
41c445ff
JB		 1737/**
1738 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1739 * @vsi: the vsi being adjusted
1740 **/
1741void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1742{
1743 struct i40e_vsi_context ctxt;
1744 i40e_status ret;
1745
1746 if ((vsi->info.valid_sections &
1747 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1748 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1749 return; /* already enabled */
1750
1751 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1752 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1753 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1754
1755 ctxt.seid = vsi->seid;
1756 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1757 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1758 if (ret) {
1759 dev_info(&vsi->back->pdev->dev,
1760 "%s: update vsi failed, aq_err=%d\n",
1761 __func__, vsi->back->hw.aq.asq_last_status);
1762 }
1763}
1764
1765/**
1766 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1767 * @vsi: the vsi being adjusted
1768 **/
1769void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1770{
1771 struct i40e_vsi_context ctxt;
1772 i40e_status ret;
1773
1774 if ((vsi->info.valid_sections &
1775 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1776 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1777 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1778 return; /* already disabled */
1779
1780 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1781 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1782 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1783
1784 ctxt.seid = vsi->seid;
1785 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1786 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1787 if (ret) {
1788 dev_info(&vsi->back->pdev->dev,
1789 "%s: update vsi failed, aq_err=%d\n",
1790 __func__, vsi->back->hw.aq.asq_last_status);
1791 }
1792}
1793
1794/**
1795 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1796 * @netdev: network interface to be adjusted
1797 * @features: netdev features to test if VLAN offload is enabled or not
1798 **/
1799static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1800{
1801 struct i40e_netdev_priv *np = netdev_priv(netdev);
1802 struct i40e_vsi *vsi = np->vsi;
1803
1804 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1805 i40e_vlan_stripping_enable(vsi);
1806 else
1807 i40e_vlan_stripping_disable(vsi);
1808}
1809
1810/**
1811 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1812 * @vsi: the vsi being configured
1813 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1814 **/
1815int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1816{
1817 struct i40e_mac_filter *f, *add_f;
1818 bool is_netdev, is_vf;
41c445ff
JB		 1819
1820 is_vf = (vsi->type == I40E_VSI_SRIOV);
1821 is_netdev = !!(vsi->netdev);
1822
1823 if (is_netdev) {
1824 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1825 is_vf, is_netdev);
1826 if (!add_f) {
1827 dev_info(&vsi->back->pdev->dev,
1828 "Could not add vlan filter %d for %pM\n",
1829 vid, vsi->netdev->dev_addr);
1830 return -ENOMEM;
1831 }
1832 }
1833
1834 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1835 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1836 if (!add_f) {
1837 dev_info(&vsi->back->pdev->dev,
1838 "Could not add vlan filter %d for %pM\n",
1839 vid, f->macaddr);
1840 return -ENOMEM;
1841 }
1842 }
1843
41c445ff
JB		 1844 /* Now if we add a vlan tag, make sure to check if it is the first
1845 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1846 * with 0, so we now accept untagged and specified tagged traffic
1847 * (and not any taged and untagged)
1848 */
1849 if (vid > 0) {
1850 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1851 I40E_VLAN_ANY,
1852 is_vf, is_netdev)) {
1853 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1854 I40E_VLAN_ANY, is_vf, is_netdev);
1855 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1856 is_vf, is_netdev);
1857 if (!add_f) {
1858 dev_info(&vsi->back->pdev->dev,
1859 "Could not add filter 0 for %pM\n",
1860 vsi->netdev->dev_addr);
1861 return -ENOMEM;
1862 }
1863 }
8d82a7c5 1864 }
41c445ff 1865
8d82a7c5
GR		 1866 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1867 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1868 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1869 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1870 is_vf, is_netdev)) {
1871 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1872 is_vf, is_netdev);
1873 add_f = i40e_add_filter(vsi, f->macaddr,
1874 0, is_vf, is_netdev);
1875 if (!add_f) {
1876 dev_info(&vsi->back->pdev->dev,
1877 "Could not add filter 0 for %pM\n",
1878 f->macaddr);
1879 return -ENOMEM;
1880 }
1881 }
1882 }
41c445ff
JB		 1883 }
1884
80f6428f
ASJ		 1885 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1886 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1887 return 0;
1888
1889 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1890}
1891
1892/**
1893 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1894 * @vsi: the vsi being configured
1895 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1896 *
1897 * Return: 0 on success or negative otherwise
41c445ff
JB		 1898 **/
1899int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1900{
1901 struct net_device *netdev = vsi->netdev;
1902 struct i40e_mac_filter *f, *add_f;
1903 bool is_vf, is_netdev;
1904 int filter_count = 0;
41c445ff
JB		 1905
1906 is_vf = (vsi->type == I40E_VSI_SRIOV);
1907 is_netdev = !!(netdev);
1908
1909 if (is_netdev)
1910 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1911
1912 list_for_each_entry(f, &vsi->mac_filter_list, list)
1913 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1914
41c445ff
JB		 1915 /* go through all the filters for this VSI and if there is only
1916 * vid == 0 it means there are no other filters, so vid 0 must
1917 * be replaced with -1. This signifies that we should from now
1918 * on accept any traffic (with any tag present, or untagged)
1919 */
1920 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1921 if (is_netdev) {
1922 if (f->vlan &&
1923 ether_addr_equal(netdev->dev_addr, f->macaddr))
1924 filter_count++;
1925 }
1926
1927 if (f->vlan)
1928 filter_count++;
1929 }
1930
1931 if (!filter_count && is_netdev) {
1932 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1933 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1934 is_vf, is_netdev);
1935 if (!f) {
1936 dev_info(&vsi->back->pdev->dev,
1937 "Could not add filter %d for %pM\n",
1938 I40E_VLAN_ANY, netdev->dev_addr);
1939 return -ENOMEM;
1940 }
1941 }
1942
1943 if (!filter_count) {
1944 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1945 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1946 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1947 is_vf, is_netdev);
1948 if (!add_f) {
1949 dev_info(&vsi->back->pdev->dev,
1950 "Could not add filter %d for %pM\n",
1951 I40E_VLAN_ANY, f->macaddr);
1952 return -ENOMEM;
1953 }
1954 }
1955 }
1956
80f6428f
ASJ		 1957 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1958 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1959 return 0;
1960
41c445ff
JB		 1961 return i40e_sync_vsi_filters(vsi);
1962}
1963
1964/**
1965 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1966 * @netdev: network interface to be adjusted
1967 * @vid: vlan id to be added
078b5876
JB		 1968 *
1969 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1970 **/
1971static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1972 __always_unused __be16 proto, u16 vid)
1973{
1974 struct i40e_netdev_priv *np = netdev_priv(netdev);
1975 struct i40e_vsi *vsi = np->vsi;
078b5876 1976 int ret = 0;
41c445ff
JB		 1977
1978 if (vid > 4095)
078b5876
JB		 1979 return -EINVAL;
1980
1981 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1982
6982d429
ASJ		 1983 /* If the network stack called us with vid = 0 then
1984 * it is asking to receive priority tagged packets with
1985 * vlan id 0. Our HW receives them by default when configured
1986 * to receive untagged packets so there is no need to add an
1987 * extra filter for vlan 0 tagged packets.
41c445ff 1988 */
6982d429
ASJ		 1989 if (vid)
1990 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 1991
078b5876
JB		 1992 if (!ret && (vid < VLAN_N_VID))
1993 set_bit(vid, vsi->active_vlans);
41c445ff 1994
078b5876 1995 return ret;
41c445ff
JB		 1996}
1997
1998/**
1999 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2000 * @netdev: network interface to be adjusted
2001 * @vid: vlan id to be removed
078b5876 2002 *
fdfd943e 2003 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2004 **/
2005static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2006 __always_unused __be16 proto, u16 vid)
2007{
2008 struct i40e_netdev_priv *np = netdev_priv(netdev);
2009 struct i40e_vsi *vsi = np->vsi;
2010
078b5876
JB		 2011 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2012
41c445ff
JB		 2013 /* return code is ignored as there is nothing a user
2014 * can do about failure to remove and a log message was
078b5876 2015 * already printed from the other function
41c445ff
JB		 2016 */
2017 i40e_vsi_kill_vlan(vsi, vid);
2018
2019 clear_bit(vid, vsi->active_vlans);
078b5876 2020
41c445ff
JB		 2021 return 0;
2022}
2023
2024/**
2025 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2026 * @vsi: the vsi being brought back up
2027 **/
2028static void i40e_restore_vlan(struct i40e_vsi *vsi)
2029{
2030 u16 vid;
2031
2032 if (!vsi->netdev)
2033 return;
2034
2035 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2036
2037 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2038 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2039 vid);
2040}
2041
2042/**
2043 * i40e_vsi_add_pvid - Add pvid for the VSI
2044 * @vsi: the vsi being adjusted
2045 * @vid: the vlan id to set as a PVID
2046 **/
dcae29be 2047int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2048{
2049 struct i40e_vsi_context ctxt;
dcae29be 2050 i40e_status aq_ret;
41c445ff
JB		 2051
2052 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2053 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2054 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2055 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2056 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2057
2058 ctxt.seid = vsi->seid;
2059 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2060 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2061 if (aq_ret) {
41c445ff
JB		 2062 dev_info(&vsi->back->pdev->dev,
2063 "%s: update vsi failed, aq_err=%d\n",
2064 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2065 return -ENOENT;
41c445ff
JB		 2066 }
2067
dcae29be 2068 return 0;
41c445ff
JB		 2069}
2070
2071/**
2072 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2073 * @vsi: the vsi being adjusted
2074 *
2075 * Just use the vlan_rx_register() service to put it back to normal
2076 **/
2077void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2078{
6c12fcbf
GR		 2079 i40e_vlan_stripping_disable(vsi);
2080
41c445ff 2081 vsi->info.pvid = 0;
41c445ff
JB		 2082}
2083
2084/**
2085 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2086 * @vsi: ptr to the VSI
2087 *
2088 * If this function returns with an error, then it's possible one or
2089 * more of the rings is populated (while the rest are not). It is the
2090 * callers duty to clean those orphaned rings.
2091 *
2092 * Return 0 on success, negative on failure
2093 **/
2094static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2095{
2096 int i, err = 0;
2097
2098 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2099 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2100
2101 return err;
2102}
2103
2104/**
2105 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2106 * @vsi: ptr to the VSI
2107 *
2108 * Free VSI's transmit software resources
2109 **/
2110static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2111{
2112 int i;
2113
8e9dca53
GR		 2114 if (!vsi->tx_rings)
2115 return;
2116
41c445ff 2117 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2118 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2119 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2120}
2121
2122/**
2123 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2124 * @vsi: ptr to the VSI
2125 *
2126 * If this function returns with an error, then it's possible one or
2127 * more of the rings is populated (while the rest are not). It is the
2128 * callers duty to clean those orphaned rings.
2129 *
2130 * Return 0 on success, negative on failure
2131 **/
2132static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2133{
2134 int i, err = 0;
2135
2136 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2137 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2138 return err;
2139}
2140
2141/**
2142 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2143 * @vsi: ptr to the VSI
2144 *
2145 * Free all receive software resources
2146 **/
2147static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2148{
2149 int i;
2150
8e9dca53
GR		 2151 if (!vsi->rx_rings)
2152 return;
2153
41c445ff 2154 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2155 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2156 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2157}
2158
2159/**
2160 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2161 * @ring: The Tx ring to configure
2162 *
2163 * Configure the Tx descriptor ring in the HMC context.
2164 **/
2165static int i40e_configure_tx_ring(struct i40e_ring *ring)
2166{
2167 struct i40e_vsi *vsi = ring->vsi;
2168 u16 pf_q = vsi->base_queue + ring->queue_index;
2169 struct i40e_hw *hw = &vsi->back->hw;
2170 struct i40e_hmc_obj_txq tx_ctx;
2171 i40e_status err = 0;
2172 u32 qtx_ctl = 0;
2173
2174 /* some ATR related tx ring init */
60ea5f83 2175 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2176 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2177 ring->atr_count = 0;
2178 } else {
2179 ring->atr_sample_rate = 0;
2180 }
2181
2182 /* initialize XPS */
2183 if (ring->q_vector && ring->netdev &&
4e3b35b0 2184 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2185 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2186 netif_set_xps_queue(ring->netdev,
2187 &ring->q_vector->affinity_mask,
2188 ring->queue_index);
2189
2190 /* clear the context structure first */
2191 memset(&tx_ctx, 0, sizeof(tx_ctx));
2192
2193 tx_ctx.new_context = 1;
2194 tx_ctx.base = (ring->dma / 128);
2195 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2196 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2197 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2198 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2199 /* FDIR VSI tx ring can still use RS bit and writebacks */
2200 if (vsi->type != I40E_VSI_FDIR)
2201 tx_ctx.head_wb_ena = 1;
2202 tx_ctx.head_wb_addr = ring->dma +
2203 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2204
2205 /* As part of VSI creation/update, FW allocates certain
2206 * Tx arbitration queue sets for each TC enabled for
2207 * the VSI. The FW returns the handles to these queue
2208 * sets as part of the response buffer to Add VSI,
2209 * Update VSI, etc. AQ commands. It is expected that
2210 * these queue set handles be associated with the Tx
2211 * queues by the driver as part of the TX queue context
2212 * initialization. This has to be done regardless of
2213 * DCB as by default everything is mapped to TC0.
2214 */
2215 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2216 tx_ctx.rdylist_act = 0;
2217
2218 /* clear the context in the HMC */
2219 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2220 if (err) {
2221 dev_info(&vsi->back->pdev->dev,
2222 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2223 ring->queue_index, pf_q, err);
2224 return -ENOMEM;
2225 }
2226
2227 /* set the context in the HMC */
2228 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2229 if (err) {
2230 dev_info(&vsi->back->pdev->dev,
2231 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2232 ring->queue_index, pf_q, err);
2233 return -ENOMEM;
2234 }
2235
2236 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2237 if (vsi->type == I40E_VSI_VMDQ2)
2238 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2239 else
2240 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2241 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2242 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2243 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2244 i40e_flush(hw);
2245
2246 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2247
2248 /* cache tail off for easier writes later */
2249 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2250
2251 return 0;
2252}
2253
2254/**
2255 * i40e_configure_rx_ring - Configure a receive ring context
2256 * @ring: The Rx ring to configure
2257 *
2258 * Configure the Rx descriptor ring in the HMC context.
2259 **/
2260static int i40e_configure_rx_ring(struct i40e_ring *ring)
2261{
2262 struct i40e_vsi *vsi = ring->vsi;
2263 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2264 u16 pf_q = vsi->base_queue + ring->queue_index;
2265 struct i40e_hw *hw = &vsi->back->hw;
2266 struct i40e_hmc_obj_rxq rx_ctx;
2267 i40e_status err = 0;
2268
2269 ring->state = 0;
2270
2271 /* clear the context structure first */
2272 memset(&rx_ctx, 0, sizeof(rx_ctx));
2273
2274 ring->rx_buf_len = vsi->rx_buf_len;
2275 ring->rx_hdr_len = vsi->rx_hdr_len;
2276
2277 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2278 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2279
2280 rx_ctx.base = (ring->dma / 128);
2281 rx_ctx.qlen = ring->count;
2282
2283 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2284 set_ring_16byte_desc_enabled(ring);
2285 rx_ctx.dsize = 0;
2286 } else {
2287 rx_ctx.dsize = 1;
2288 }
2289
2290 rx_ctx.dtype = vsi->dtype;
2291 if (vsi->dtype) {
2292 set_ring_ps_enabled(ring);
2293 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2294 I40E_RX_SPLIT_IP |
2295 I40E_RX_SPLIT_TCP_UDP |
2296 I40E_RX_SPLIT_SCTP;
2297 } else {
2298 rx_ctx.hsplit_0 = 0;
2299 }
2300
2301 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2302 (chain_len * ring->rx_buf_len));
2303 rx_ctx.tphrdesc_ena = 1;
2304 rx_ctx.tphwdesc_ena = 1;
2305 rx_ctx.tphdata_ena = 1;
2306 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2307 if (hw->revision_id == 0)
2308 rx_ctx.lrxqthresh = 0;
2309 else
2310 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2311 rx_ctx.crcstrip = 1;
2312 rx_ctx.l2tsel = 1;
2313 rx_ctx.showiv = 1;
2314
2315 /* clear the context in the HMC */
2316 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2317 if (err) {
2318 dev_info(&vsi->back->pdev->dev,
2319 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2320 ring->queue_index, pf_q, err);
2321 return -ENOMEM;
2322 }
2323
2324 /* set the context in the HMC */
2325 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2326 if (err) {
2327 dev_info(&vsi->back->pdev->dev,
2328 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2329 ring->queue_index, pf_q, err);
2330 return -ENOMEM;
2331 }
2332
2333 /* cache tail for quicker writes, and clear the reg before use */
2334 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2335 writel(0, ring->tail);
2336
2337 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2338
2339 return 0;
2340}
2341
2342/**
2343 * i40e_vsi_configure_tx - Configure the VSI for Tx
2344 * @vsi: VSI structure describing this set of rings and resources
2345 *
2346 * Configure the Tx VSI for operation.
2347 **/
2348static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2349{
2350 int err = 0;
2351 u16 i;
2352
9f65e15b
AD		 2353 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2354 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2355
2356 return err;
2357}
2358
2359/**
2360 * i40e_vsi_configure_rx - Configure the VSI for Rx
2361 * @vsi: the VSI being configured
2362 *
2363 * Configure the Rx VSI for operation.
2364 **/
2365static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2366{
2367 int err = 0;
2368 u16 i;
2369
2370 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2371 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2372 + ETH_FCS_LEN + VLAN_HLEN;
2373 else
2374 vsi->max_frame = I40E_RXBUFFER_2048;
2375
2376 /* figure out correct receive buffer length */
2377 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2378 I40E_FLAG_RX_PS_ENABLED)) {
2379 case I40E_FLAG_RX_1BUF_ENABLED:
2380 vsi->rx_hdr_len = 0;
2381 vsi->rx_buf_len = vsi->max_frame;
2382 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2383 break;
2384 case I40E_FLAG_RX_PS_ENABLED:
2385 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2386 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2387 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2388 break;
2389 default:
2390 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2391 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2392 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2393 break;
2394 }
2395
2396 /* round up for the chip's needs */
2397 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2398 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2399 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2400 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2401
2402 /* set up individual rings */
2403 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2404 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2405
2406 return err;
2407}
2408
2409/**
2410 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2411 * @vsi: ptr to the VSI
2412 **/
2413static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2414{
2415 u16 qoffset, qcount;
2416 int i, n;
2417
2418 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2419 return;
2420
2421 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2422 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2423 continue;
2424
2425 qoffset = vsi->tc_config.tc_info[n].qoffset;
2426 qcount = vsi->tc_config.tc_info[n].qcount;
2427 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2428 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2429 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2430 rx_ring->dcb_tc = n;
2431 tx_ring->dcb_tc = n;
2432 }
2433 }
2434}
2435
2436/**
2437 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2438 * @vsi: ptr to the VSI
2439 **/
2440static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2441{
2442 if (vsi->netdev)
2443 i40e_set_rx_mode(vsi->netdev);
2444}
2445
17a73f6b
JG		 2446/**
2447 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2448 * @vsi: Pointer to the targeted VSI
2449 *
2450 * This function replays the hlist on the hw where all the SB Flow Director
2451 * filters were saved.
2452 **/
2453static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2454{
2455 struct i40e_fdir_filter *filter;
2456 struct i40e_pf *pf = vsi->back;
2457 struct hlist_node *node;
2458
55a5e60b
ASJ		 2459 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2460 return;
2461
17a73f6b
JG		 2462 hlist_for_each_entry_safe(filter, node,
2463 &pf->fdir_filter_list, fdir_node) {
2464 i40e_add_del_fdir(vsi, filter, true);
2465 }
2466}
2467
41c445ff
JB		 2468/**
2469 * i40e_vsi_configure - Set up the VSI for action
2470 * @vsi: the VSI being configured
2471 **/
2472static int i40e_vsi_configure(struct i40e_vsi *vsi)
2473{
2474 int err;
2475
2476 i40e_set_vsi_rx_mode(vsi);
2477 i40e_restore_vlan(vsi);
2478 i40e_vsi_config_dcb_rings(vsi);
2479 err = i40e_vsi_configure_tx(vsi);
2480 if (!err)
2481 err = i40e_vsi_configure_rx(vsi);
2482
2483 return err;
2484}
2485
2486/**
2487 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2488 * @vsi: the VSI being configured
2489 **/
2490static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2491{
2492 struct i40e_pf *pf = vsi->back;
2493 struct i40e_q_vector *q_vector;
2494 struct i40e_hw *hw = &pf->hw;
2495 u16 vector;
2496 int i, q;
2497 u32 val;
2498 u32 qp;
2499
2500 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2501 * and PFINT_LNKLSTn registers, e.g.:
2502 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2503 */
2504 qp = vsi->base_queue;
2505 vector = vsi->base_vector;
493fb300
AD		 2506 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2507 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2508 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2509 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2510 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2511 q_vector->rx.itr);
2512 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2513 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2514 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2515 q_vector->tx.itr);
2516
2517 /* Linked list for the queuepairs assigned to this vector */
2518 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2519 for (q = 0; q < q_vector->num_ringpairs; q++) {
2520 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2521 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2522 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2523 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2524 (I40E_QUEUE_TYPE_TX
2525 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2526
2527 wr32(hw, I40E_QINT_RQCTL(qp), val);
2528
2529 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2530 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2531 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2532 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2533 (I40E_QUEUE_TYPE_RX
2534 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2535
2536 /* Terminate the linked list */
2537 if (q == (q_vector->num_ringpairs - 1))
2538 val |= (I40E_QUEUE_END_OF_LIST
2539 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2540
2541 wr32(hw, I40E_QINT_TQCTL(qp), val);
2542 qp++;
2543 }
2544 }
2545
2546 i40e_flush(hw);
2547}
2548
2549/**
2550 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2551 * @hw: ptr to the hardware info
2552 **/
2553static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2554{
2555 u32 val;
2556
2557 /* clear things first */
2558 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2559 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2560
2561 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2562 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2563 I40E_PFINT_ICR0_ENA_GRST_MASK |
2564 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2565 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2566 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2567 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2568 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2569 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2570 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2571
2572 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2573
2574 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2575 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2576 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2577
2578 /* OTHER_ITR_IDX = 0 */
2579 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2580}
2581
2582/**
2583 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2584 * @vsi: the VSI being configured
2585 **/
2586static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2587{
493fb300 2588 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2589 struct i40e_pf *pf = vsi->back;
2590 struct i40e_hw *hw = &pf->hw;
2591 u32 val;
2592
2593 /* set the ITR configuration */
2594 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2595 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2596 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2597 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2598 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2599 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2600
2601 i40e_enable_misc_int_causes(hw);
2602
2603 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2604 wr32(hw, I40E_PFINT_LNKLST0, 0);
2605
f29eaa3d 2606 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2607 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2608 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2609 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2610
2611 wr32(hw, I40E_QINT_RQCTL(0), val);
2612
2613 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2614 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2615 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2616
2617 wr32(hw, I40E_QINT_TQCTL(0), val);
2618 i40e_flush(hw);
2619}
2620
2ef28cfb
MW		 2621/**
2622 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2623 * @pf: board private structure
2624 **/
2625void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2626{
2627 struct i40e_hw *hw = &pf->hw;
2628
2629 wr32(hw, I40E_PFINT_DYN_CTL0,
2630 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2631 i40e_flush(hw);
2632}
2633
41c445ff
JB		 2634/**
2635 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2636 * @pf: board private structure
2637 **/
116a57d4 2638void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2639{
2640 struct i40e_hw *hw = &pf->hw;
2641 u32 val;
2642
2643 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2644 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2645 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2646
2647 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2648 i40e_flush(hw);
2649}
2650
2651/**
2652 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2653 * @vsi: pointer to a vsi
2654 * @vector: enable a particular Hw Interrupt vector
2655 **/
2656void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2657{
2658 struct i40e_pf *pf = vsi->back;
2659 struct i40e_hw *hw = &pf->hw;
2660 u32 val;
2661
2662 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2663 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2664 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2665 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2666 /* skip the flush */
41c445ff
JB		 2667}
2668
2669/**
2670 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2671 * @irq: interrupt number
2672 * @data: pointer to a q_vector
2673 **/
2674static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2675{
2676 struct i40e_q_vector *q_vector = data;
2677
cd0b6fa6 2678 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2679 return IRQ_HANDLED;
2680
2681 napi_schedule(&q_vector->napi);
2682
2683 return IRQ_HANDLED;
2684}
2685
41c445ff
JB		 2686/**
2687 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2688 * @vsi: the VSI being configured
2689 * @basename: name for the vector
2690 *
2691 * Allocates MSI-X vectors and requests interrupts from the kernel.
2692 **/
2693static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2694{
2695 int q_vectors = vsi->num_q_vectors;
2696 struct i40e_pf *pf = vsi->back;
2697 int base = vsi->base_vector;
2698 int rx_int_idx = 0;
2699 int tx_int_idx = 0;
2700 int vector, err;
2701
2702 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2703 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2704
cd0b6fa6 2705 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2706 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2707 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2708 tx_int_idx++;
cd0b6fa6 2709 } else if (q_vector->rx.ring) {
41c445ff
JB		 2710 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2711 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2712 } else if (q_vector->tx.ring) {
41c445ff
JB		 2713 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2714 "%s-%s-%d", basename, "tx", tx_int_idx++);
2715 } else {
2716 /* skip this unused q_vector */
2717 continue;
2718 }
2719 err = request_irq(pf->msix_entries[base + vector].vector,
2720 vsi->irq_handler,
2721 0,
2722 q_vector->name,
2723 q_vector);
2724 if (err) {
2725 dev_info(&pf->pdev->dev,
2726 "%s: request_irq failed, error: %d\n",
2727 __func__, err);
2728 goto free_queue_irqs;
2729 }
2730 /* assign the mask for this irq */
2731 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2732 &q_vector->affinity_mask);
2733 }
2734
2735 return 0;
2736
2737free_queue_irqs:
2738 while (vector) {
2739 vector--;
2740 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2741 NULL);
2742 free_irq(pf->msix_entries[base + vector].vector,
2743 &(vsi->q_vectors[vector]));
2744 }
2745 return err;
2746}
2747
2748/**
2749 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2750 * @vsi: the VSI being un-configured
2751 **/
2752static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2753{
2754 struct i40e_pf *pf = vsi->back;
2755 struct i40e_hw *hw = &pf->hw;
2756 int base = vsi->base_vector;
2757 int i;
2758
2759 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2760 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2761 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2762 }
2763
2764 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2765 for (i = vsi->base_vector;
2766 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2767 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2768
2769 i40e_flush(hw);
2770 for (i = 0; i < vsi->num_q_vectors; i++)
2771 synchronize_irq(pf->msix_entries[i + base].vector);
2772 } else {
2773 /* Legacy and MSI mode - this stops all interrupt handling */
2774 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2775 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2776 i40e_flush(hw);
2777 synchronize_irq(pf->pdev->irq);
2778 }
2779}
2780
2781/**
2782 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2783 * @vsi: the VSI being configured
2784 **/
2785static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2786{
2787 struct i40e_pf *pf = vsi->back;
2788 int i;
2789
2790 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2791 for (i = vsi->base_vector;
2792 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2793 i40e_irq_dynamic_enable(vsi, i);
2794 } else {
2795 i40e_irq_dynamic_enable_icr0(pf);
2796 }
2797
1022cb6c 2798 i40e_flush(&pf->hw);
41c445ff
JB		 2799 return 0;
2800}
2801
2802/**
2803 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2804 * @pf: board private structure
2805 **/
2806static void i40e_stop_misc_vector(struct i40e_pf *pf)
2807{
2808 /* Disable ICR 0 */
2809 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2810 i40e_flush(&pf->hw);
2811}
2812
2813/**
2814 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2815 * @irq: interrupt number
2816 * @data: pointer to a q_vector
2817 *
2818 * This is the handler used for all MSI/Legacy interrupts, and deals
2819 * with both queue and non-queue interrupts. This is also used in
2820 * MSIX mode to handle the non-queue interrupts.
2821 **/
2822static irqreturn_t i40e_intr(int irq, void *data)
2823{
2824 struct i40e_pf *pf = (struct i40e_pf *)data;
2825 struct i40e_hw *hw = &pf->hw;
5e823066 2826 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2827 u32 icr0, icr0_remaining;
2828 u32 val, ena_mask;
2829
2830 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2831 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2832
116a57d4
SN		 2833 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2834 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2835 goto enable_intr;
41c445ff 2836
cd92e72f
SN		 2837 /* if interrupt but no bits showing, must be SWINT */
2838 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2839 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2840 pf->sw_int_count++;
2841
41c445ff
JB		 2842 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2843 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2844
2845 /* temporarily disable queue cause for NAPI processing */
2846 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2847 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2848 wr32(hw, I40E_QINT_RQCTL(0), qval);
2849
2850 qval = rd32(hw, I40E_QINT_TQCTL(0));
2851 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2852 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2853
2854 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2855 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2856 }
2857
2858 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2859 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2860 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2861 }
2862
2863 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2864 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2865 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2866 }
2867
2868 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2869 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2870 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2871 }
2872
2873 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2874 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2875 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2876 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2877 val = rd32(hw, I40E_GLGEN_RSTAT);
2878 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2879 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2880 if (val == I40E_RESET_CORER)
41c445ff 2881 pf->corer_count++;
d52cf0a9 2882 else if (val == I40E_RESET_GLOBR)
41c445ff 2883 pf->globr_count++;
d52cf0a9 2884 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2885 pf->empr_count++;
2886 }
2887
9c010ee0
ASJ		 2888 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2889 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2890 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2891 }
2892
beb0dff1
JK		 2893 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2894 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2895
2896 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
2897 ena_mask &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2898 i40e_ptp_tx_hwtstamp(pf);
2899 prttsyn_stat &= ~I40E_PRTTSYN_STAT_0_TXTIME_MASK;
2900 }
2901
2902 wr32(hw, I40E_PRTTSYN_STAT_0, prttsyn_stat);
2903 }
2904
41c445ff
JB		 2905 /* If a critical error is pending we have no choice but to reset the
2906 * device.
2907 * Report and mask out any remaining unexpected interrupts.
2908 */
2909 icr0_remaining = icr0 & ena_mask;
2910 if (icr0_remaining) {
2911 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2912 icr0_remaining);
9c010ee0 2913 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 2914 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 2915 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 2916 dev_info(&pf->pdev->dev, "device will be reset\n");
2917 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2918 i40e_service_event_schedule(pf);
41c445ff
JB		 2919 }
2920 ena_mask &= ~icr0_remaining;
2921 }
5e823066 2922 ret = IRQ_HANDLED;
41c445ff 2923
5e823066 2924enable_intr:
41c445ff
JB		 2925 /* re-enable interrupt causes */
2926 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2927 if (!test_bit(__I40E_DOWN, &pf->state)) {
2928 i40e_service_event_schedule(pf);
2929 i40e_irq_dynamic_enable_icr0(pf);
2930 }
2931
5e823066 2932 return ret;
41c445ff
JB		 2933}
2934
cbf61325
ASJ		 2935/**
2936 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2937 * @tx_ring: tx ring to clean
2938 * @budget: how many cleans we're allowed
2939 *
2940 * Returns true if there's any budget left (e.g. the clean is finished)
2941 **/
2942static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
2943{
2944 struct i40e_vsi *vsi = tx_ring->vsi;
2945 u16 i = tx_ring->next_to_clean;
2946 struct i40e_tx_buffer *tx_buf;
2947 struct i40e_tx_desc *tx_desc;
2948
2949 tx_buf = &tx_ring->tx_bi[i];
2950 tx_desc = I40E_TX_DESC(tx_ring, i);
2951 i -= tx_ring->count;
2952
2953 do {
2954 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
2955
2956 /* if next_to_watch is not set then there is no work pending */
2957 if (!eop_desc)
2958 break;
2959
2960 /* prevent any other reads prior to eop_desc */
2961 read_barrier_depends();
2962
2963 /* if the descriptor isn't done, no work yet to do */
2964 if (!(eop_desc->cmd_type_offset_bsz &
2965 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
2966 break;
2967
2968 /* clear next_to_watch to prevent false hangs */
2969 tx_buf->next_to_watch = NULL;
2970
2971 /* unmap skb header data */
2972 dma_unmap_single(tx_ring->dev,
2973 dma_unmap_addr(tx_buf, dma),
2974 dma_unmap_len(tx_buf, len),
2975 DMA_TO_DEVICE);
2976
2977 dma_unmap_len_set(tx_buf, len, 0);
2978
2979
2980 /* move to the next desc and buffer to clean */
2981 tx_buf++;
2982 tx_desc++;
2983 i++;
2984 if (unlikely(!i)) {
2985 i -= tx_ring->count;
2986 tx_buf = tx_ring->tx_bi;
2987 tx_desc = I40E_TX_DESC(tx_ring, 0);
2988 }
2989
2990 /* update budget accounting */
2991 budget--;
2992 } while (likely(budget));
2993
2994 i += tx_ring->count;
2995 tx_ring->next_to_clean = i;
2996
2997 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
2998 i40e_irq_dynamic_enable(vsi,
2999 tx_ring->q_vector->v_idx + vsi->base_vector);
3000 }
3001 return budget > 0;
3002}
3003
3004/**
3005 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3006 * @irq: interrupt number
3007 * @data: pointer to a q_vector
3008 **/
3009static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3010{
3011 struct i40e_q_vector *q_vector = data;
3012 struct i40e_vsi *vsi;
3013
3014 if (!q_vector->tx.ring)
3015 return IRQ_HANDLED;
3016
3017 vsi = q_vector->tx.ring->vsi;
3018 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3019
3020 return IRQ_HANDLED;
3021}
3022
41c445ff 3023/**
cd0b6fa6 3024 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3025 * @vsi: the VSI being configured
3026 * @v_idx: vector index
cd0b6fa6 3027 * @qp_idx: queue pair index
41c445ff 3028 **/
cd0b6fa6 3029static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3030{
493fb300 3031 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3032 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3033 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3034
3035 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3036 tx_ring->next = q_vector->tx.ring;
3037 q_vector->tx.ring = tx_ring;
41c445ff 3038 q_vector->tx.count++;
cd0b6fa6
AD		 3039
3040 rx_ring->q_vector = q_vector;
3041 rx_ring->next = q_vector->rx.ring;
3042 q_vector->rx.ring = rx_ring;
3043 q_vector->rx.count++;
41c445ff
JB		 3044}
3045
3046/**
3047 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3048 * @vsi: the VSI being configured
3049 *
3050 * This function maps descriptor rings to the queue-specific vectors
3051 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3052 * one vector per queue pair, but on a constrained vector budget, we
3053 * group the queue pairs as "efficiently" as possible.
3054 **/
3055static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3056{
3057 int qp_remaining = vsi->num_queue_pairs;
3058 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3059 int num_ringpairs;
41c445ff
JB		 3060 int v_start = 0;
3061 int qp_idx = 0;
3062
3063 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3064 * group them so there are multiple queues per vector.
3065 */
3066 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3067 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3068
3069 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3070
3071 q_vector->num_ringpairs = num_ringpairs;
3072
3073 q_vector->rx.count = 0;
3074 q_vector->tx.count = 0;
3075 q_vector->rx.ring = NULL;
3076 q_vector->tx.ring = NULL;
3077
3078 while (num_ringpairs--) {
3079 map_vector_to_qp(vsi, v_start, qp_idx);
3080 qp_idx++;
3081 qp_remaining--;
41c445ff
JB		 3082 }
3083 }
3084}
3085
3086/**
3087 * i40e_vsi_request_irq - Request IRQ from the OS
3088 * @vsi: the VSI being configured
3089 * @basename: name for the vector
3090 **/
3091static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3092{
3093 struct i40e_pf *pf = vsi->back;
3094 int err;
3095
3096 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3097 err = i40e_vsi_request_irq_msix(vsi, basename);
3098 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3099 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3100 pf->misc_int_name, pf);
3101 else
3102 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3103 pf->misc_int_name, pf);
3104
3105 if (err)
3106 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3107
3108 return err;
3109}
3110
3111#ifdef CONFIG_NET_POLL_CONTROLLER
3112/**
3113 * i40e_netpoll - A Polling 'interrupt'handler
3114 * @netdev: network interface device structure
3115 *
3116 * This is used by netconsole to send skbs without having to re-enable
3117 * interrupts. It's not called while the normal interrupt routine is executing.
3118 **/
3119static void i40e_netpoll(struct net_device *netdev)
3120{
3121 struct i40e_netdev_priv *np = netdev_priv(netdev);
3122 struct i40e_vsi *vsi = np->vsi;
3123 struct i40e_pf *pf = vsi->back;
3124 int i;
3125
3126 /* if interface is down do nothing */
3127 if (test_bit(__I40E_DOWN, &vsi->state))
3128 return;
3129
3130 pf->flags |= I40E_FLAG_IN_NETPOLL;
3131 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3132 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3133 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3134 } else {
3135 i40e_intr(pf->pdev->irq, netdev);
3136 }
3137 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3138}
3139#endif
3140
3141/**
3142 * i40e_vsi_control_tx - Start or stop a VSI's rings
3143 * @vsi: the VSI being configured
3144 * @enable: start or stop the rings
3145 **/
3146static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3147{
3148 struct i40e_pf *pf = vsi->back;
3149 struct i40e_hw *hw = &pf->hw;
3150 int i, j, pf_q;
3151 u32 tx_reg;
3152
3153 pf_q = vsi->base_queue;
3154 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3155 for (j = 0; j < 50; j++) {
41c445ff 3156 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3157 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3158 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3159 break;
3160 usleep_range(1000, 2000);
3161 }
fda972f6
MW		 3162 /* Skip if the queue is already in the requested state */
3163 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3164 continue;
3165 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3166 continue;
41c445ff
JB		 3167
3168 /* turn on/off the queue */
c5c9eb9e
SN		 3169 if (enable) {
3170 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3171 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3172 } else {
41c445ff 3173 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3174 }
41c445ff
JB		 3175
3176 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3177
3178 /* wait for the change to finish */
3179 for (j = 0; j < 10; j++) {
3180 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3181 if (enable) {
3182 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3183 break;
3184 } else {
3185 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3186 break;
3187 }
3188
3189 udelay(10);
3190 }
3191 if (j >= 10) {
3192 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3193 pf_q, (enable ? "en" : "dis"));
3194 return -ETIMEDOUT;
3195 }
3196 }
3197
7134f9ce
JB		 3198 if (hw->revision_id == 0)
3199 mdelay(50);
3200
41c445ff
JB		 3201 return 0;
3202}
3203
3204/**
3205 * i40e_vsi_control_rx - Start or stop a VSI's rings
3206 * @vsi: the VSI being configured
3207 * @enable: start or stop the rings
3208 **/
3209static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3210{
3211 struct i40e_pf *pf = vsi->back;
3212 struct i40e_hw *hw = &pf->hw;
3213 int i, j, pf_q;
3214 u32 rx_reg;
3215
3216 pf_q = vsi->base_queue;
3217 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3218 for (j = 0; j < 50; j++) {
41c445ff 3219 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3220 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3221 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3222 break;
3223 usleep_range(1000, 2000);
3224 }
41c445ff
JB		 3225
3226 if (enable) {
3227 /* is STAT set ? */
3228 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3229 continue;
3230 } else {
3231 /* is !STAT set ? */
3232 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3233 continue;
3234 }
3235
3236 /* turn on/off the queue */
3237 if (enable)
6c5ef620 3238 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3239 else
6c5ef620 3240 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3241 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3242
3243 /* wait for the change to finish */
3244 for (j = 0; j < 10; j++) {
3245 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3246
3247 if (enable) {
3248 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3249 break;
3250 } else {
3251 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3252 break;
3253 }
3254
3255 udelay(10);
3256 }
3257 if (j >= 10) {
3258 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3259 pf_q, (enable ? "en" : "dis"));
3260 return -ETIMEDOUT;
3261 }
3262 }
3263
3264 return 0;
3265}
3266
3267/**
3268 * i40e_vsi_control_rings - Start or stop a VSI's rings
3269 * @vsi: the VSI being configured
3270 * @enable: start or stop the rings
3271 **/
fc18eaa0 3272int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3273{
3b867b28 3274 int ret = 0;
41c445ff
JB		 3275
3276 /* do rx first for enable and last for disable */
3277 if (request) {
3278 ret = i40e_vsi_control_rx(vsi, request);
3279 if (ret)
3280 return ret;
3281 ret = i40e_vsi_control_tx(vsi, request);
3282 } else {
3b867b28
ASJ		 3283 /* Ignore return value, we need to shutdown whatever we can */
3284 i40e_vsi_control_tx(vsi, request);
3285 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3286 }
3287
3288 return ret;
3289}
3290
3291/**
3292 * i40e_vsi_free_irq - Free the irq association with the OS
3293 * @vsi: the VSI being configured
3294 **/
3295static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3296{
3297 struct i40e_pf *pf = vsi->back;
3298 struct i40e_hw *hw = &pf->hw;
3299 int base = vsi->base_vector;
3300 u32 val, qp;
3301 int i;
3302
3303 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3304 if (!vsi->q_vectors)
3305 return;
3306
3307 for (i = 0; i < vsi->num_q_vectors; i++) {
3308 u16 vector = i + base;
3309
3310 /* free only the irqs that were actually requested */
78681b1f
SN		 3311 if (!vsi->q_vectors[i] ||
3312 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3313 continue;
3314
3315 /* clear the affinity_mask in the IRQ descriptor */
3316 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3317 NULL);
3318 free_irq(pf->msix_entries[vector].vector,
493fb300 3319 vsi->q_vectors[i]);
41c445ff
JB		 3320
3321 /* Tear down the interrupt queue link list
3322 *
3323 * We know that they come in pairs and always
3324 * the Rx first, then the Tx. To clear the
3325 * link list, stick the EOL value into the
3326 * next_q field of the registers.
3327 */
3328 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3329 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3330 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3331 val |= I40E_QUEUE_END_OF_LIST
3332 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3333 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3334
3335 while (qp != I40E_QUEUE_END_OF_LIST) {
3336 u32 next;
3337
3338 val = rd32(hw, I40E_QINT_RQCTL(qp));
3339
3340 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3341 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3342 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3343 I40E_QINT_RQCTL_INTEVENT_MASK);
3344
3345 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3346 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3347
3348 wr32(hw, I40E_QINT_RQCTL(qp), val);
3349
3350 val = rd32(hw, I40E_QINT_TQCTL(qp));
3351
3352 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3353 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3354
3355 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3356 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3357 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3358 I40E_QINT_TQCTL_INTEVENT_MASK);
3359
3360 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3361 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3362
3363 wr32(hw, I40E_QINT_TQCTL(qp), val);
3364 qp = next;
3365 }
3366 }
3367 } else {
3368 free_irq(pf->pdev->irq, pf);
3369
3370 val = rd32(hw, I40E_PFINT_LNKLST0);
3371 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3372 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3373 val |= I40E_QUEUE_END_OF_LIST
3374 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3375 wr32(hw, I40E_PFINT_LNKLST0, val);
3376
3377 val = rd32(hw, I40E_QINT_RQCTL(qp));
3378 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3379 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3380 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3381 I40E_QINT_RQCTL_INTEVENT_MASK);
3382
3383 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3384 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3385
3386 wr32(hw, I40E_QINT_RQCTL(qp), val);
3387
3388 val = rd32(hw, I40E_QINT_TQCTL(qp));
3389
3390 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3391 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3392 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3393 I40E_QINT_TQCTL_INTEVENT_MASK);
3394
3395 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3396 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3397
3398 wr32(hw, I40E_QINT_TQCTL(qp), val);
3399 }
3400}
3401
493fb300
AD		 3402/**
3403 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3404 * @vsi: the VSI being configured
3405 * @v_idx: Index of vector to be freed
3406 *
3407 * This function frees the memory allocated to the q_vector. In addition if
3408 * NAPI is enabled it will delete any references to the NAPI struct prior
3409 * to freeing the q_vector.
3410 **/
3411static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3412{
3413 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3414 struct i40e_ring *ring;
493fb300
AD		 3415
3416 if (!q_vector)
3417 return;
3418
3419 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3420 i40e_for_each_ring(ring, q_vector->tx)
3421 ring->q_vector = NULL;
3422
3423 i40e_for_each_ring(ring, q_vector->rx)
3424 ring->q_vector = NULL;
493fb300
AD		 3425
3426 /* only VSI w/ an associated netdev is set up w/ NAPI */
3427 if (vsi->netdev)
3428 netif_napi_del(&q_vector->napi);
3429
3430 vsi->q_vectors[v_idx] = NULL;
3431
3432 kfree_rcu(q_vector, rcu);
3433}
3434
41c445ff
JB		 3435/**
3436 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3437 * @vsi: the VSI being un-configured
3438 *
3439 * This frees the memory allocated to the q_vectors and
3440 * deletes references to the NAPI struct.
3441 **/
3442static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3443{
3444 int v_idx;
3445
493fb300
AD		 3446 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3447 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3448}
3449
3450/**
3451 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3452 * @pf: board private structure
3453 **/
3454static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3455{
3456 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3457 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3458 pci_disable_msix(pf->pdev);
3459 kfree(pf->msix_entries);
3460 pf->msix_entries = NULL;
3461 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3462 pci_disable_msi(pf->pdev);
3463 }
3464 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3465}
3466
3467/**
3468 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3469 * @pf: board private structure
3470 *
3471 * We go through and clear interrupt specific resources and reset the structure
3472 * to pre-load conditions
3473 **/
3474static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3475{
3476 int i;
3477
3478 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3479 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3480 if (pf->vsi[i])
3481 i40e_vsi_free_q_vectors(pf->vsi[i]);
3482 i40e_reset_interrupt_capability(pf);
3483}
3484
3485/**
3486 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3487 * @vsi: the VSI being configured
3488 **/
3489static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3490{
3491 int q_idx;
3492
3493 if (!vsi->netdev)
3494 return;
3495
3496 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3497 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3498}
3499
3500/**
3501 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3502 * @vsi: the VSI being configured
3503 **/
3504static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3505{
3506 int q_idx;
3507
3508 if (!vsi->netdev)
3509 return;
3510
3511 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3512 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3513}
3514
3515/**
3516 * i40e_quiesce_vsi - Pause a given VSI
3517 * @vsi: the VSI being paused
3518 **/
3519static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3520{
3521 if (test_bit(__I40E_DOWN, &vsi->state))
3522 return;
3523
3524 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3525 if (vsi->netdev && netif_running(vsi->netdev)) {
3526 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3527 } else {
3528 set_bit(__I40E_DOWN, &vsi->state);
3529 i40e_down(vsi);
3530 }
3531}
3532
3533/**
3534 * i40e_unquiesce_vsi - Resume a given VSI
3535 * @vsi: the VSI being resumed
3536 **/
3537static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3538{
3539 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3540 return;
3541
3542 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3543 if (vsi->netdev && netif_running(vsi->netdev))
3544 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3545 else
3546 i40e_up(vsi); /* this clears the DOWN bit */
3547}
3548
3549/**
3550 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3551 * @pf: the PF
3552 **/
3553static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3554{
3555 int v;
3556
3557 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3558 if (pf->vsi[v])
3559 i40e_quiesce_vsi(pf->vsi[v]);
3560 }
3561}
3562
3563/**
3564 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3565 * @pf: the PF
3566 **/
3567static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3568{
3569 int v;
3570
3571 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3572 if (pf->vsi[v])
3573 i40e_unquiesce_vsi(pf->vsi[v]);
3574 }
3575}
3576
3577/**
3578 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3579 * @dcbcfg: the corresponding DCBx configuration structure
3580 *
3581 * Return the number of TCs from given DCBx configuration
3582 **/
3583static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3584{
078b5876
JB		 3585 u8 num_tc = 0;
3586 int i;
41c445ff
JB		 3587
3588 /* Scan the ETS Config Priority Table to find
3589 * traffic class enabled for a given priority
3590 * and use the traffic class index to get the
3591 * number of traffic classes enabled
3592 */
3593 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3594 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3595 num_tc = dcbcfg->etscfg.prioritytable[i];
3596 }
3597
3598 /* Traffic class index starts from zero so
3599 * increment to return the actual count
3600 */
078b5876 3601 return num_tc + 1;
41c445ff
JB		 3602}
3603
3604/**
3605 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3606 * @dcbcfg: the corresponding DCBx configuration structure
3607 *
3608 * Query the current DCB configuration and return the number of
3609 * traffic classes enabled from the given DCBX config
3610 **/
3611static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3612{
3613 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3614 u8 enabled_tc = 1;
3615 u8 i;
3616
3617 for (i = 0; i < num_tc; i++)
3618 enabled_tc |= 1 << i;
3619
3620 return enabled_tc;
3621}
3622
3623/**
3624 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3625 * @pf: PF being queried
3626 *
3627 * Return number of traffic classes enabled for the given PF
3628 **/
3629static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3630{
3631 struct i40e_hw *hw = &pf->hw;
3632 u8 i, enabled_tc;
3633 u8 num_tc = 0;
3634 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3635
3636 /* If DCB is not enabled then always in single TC */
3637 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3638 return 1;
3639
3640 /* MFP mode return count of enabled TCs for this PF */
3641 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3642 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3643 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3644 if (enabled_tc & (1 << i))
3645 num_tc++;
3646 }
3647 return num_tc;
3648 }
3649
3650 /* SFP mode will be enabled for all TCs on port */
3651 return i40e_dcb_get_num_tc(dcbcfg);
3652}
3653
3654/**
3655 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3656 * @pf: PF being queried
3657 *
3658 * Return a bitmap for first enabled traffic class for this PF.
3659 **/
3660static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3661{
3662 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3663 u8 i = 0;
3664
3665 if (!enabled_tc)
3666 return 0x1; /* TC0 */
3667
3668 /* Find the first enabled TC */
3669 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3670 if (enabled_tc & (1 << i))
3671 break;
3672 }
3673
3674 return 1 << i;
3675}
3676
3677/**
3678 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3679 * @pf: PF being queried
3680 *
3681 * Return a bitmap for enabled traffic classes for this PF.
3682 **/
3683static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3684{
3685 /* If DCB is not enabled for this PF then just return default TC */
3686 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3687 return i40e_pf_get_default_tc(pf);
3688
3689 /* MFP mode will have enabled TCs set by FW */
3690 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3691 return pf->hw.func_caps.enabled_tcmap;
3692
3693 /* SFP mode we want PF to be enabled for all TCs */
3694 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3695}
3696
3697/**
3698 * i40e_vsi_get_bw_info - Query VSI BW Information
3699 * @vsi: the VSI being queried
3700 *
3701 * Returns 0 on success, negative value on failure
3702 **/
3703static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3704{
3705 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3706 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3707 struct i40e_pf *pf = vsi->back;
3708 struct i40e_hw *hw = &pf->hw;
dcae29be 3709 i40e_status aq_ret;
41c445ff 3710 u32 tc_bw_max;
41c445ff
JB		 3711 int i;
3712
3713 /* Get the VSI level BW configuration */
dcae29be
JB		 3714 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3715 if (aq_ret) {
41c445ff
JB		 3716 dev_info(&pf->pdev->dev,
3717 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3718 aq_ret, pf->hw.aq.asq_last_status);
3719 return -EINVAL;
41c445ff
JB		 3720 }
3721
3722 /* Get the VSI level BW configuration per TC */
dcae29be 3723 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3724 NULL);
dcae29be 3725 if (aq_ret) {
41c445ff
JB		 3726 dev_info(&pf->pdev->dev,
3727 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3728 aq_ret, pf->hw.aq.asq_last_status);
3729 return -EINVAL;
41c445ff
JB		 3730 }
3731
3732 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3733 dev_info(&pf->pdev->dev,
3734 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3735 bw_config.tc_valid_bits,
3736 bw_ets_config.tc_valid_bits);
3737 /* Still continuing */
3738 }
3739
3740 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3741 vsi->bw_max_quanta = bw_config.max_bw;
3742 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3743 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3744 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3745 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3746 vsi->bw_ets_limit_credits[i] =
3747 le16_to_cpu(bw_ets_config.credits[i]);
3748 /* 3 bits out of 4 for each TC */
3749 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3750 }
078b5876 3751
dcae29be 3752 return 0;
41c445ff
JB		 3753}
3754
3755/**
3756 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3757 * @vsi: the VSI being configured
3758 * @enabled_tc: TC bitmap
3759 * @bw_credits: BW shared credits per TC
3760 *
3761 * Returns 0 on success, negative value on failure
3762 **/
dcae29be 3763static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3764 u8 *bw_share)
3765{
3766 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3767 i40e_status aq_ret;
3768 int i;
41c445ff
JB		 3769
3770 bw_data.tc_valid_bits = enabled_tc;
3771 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3772 bw_data.tc_bw_credits[i] = bw_share[i];
3773
dcae29be
JB		 3774 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3775 NULL);
3776 if (aq_ret) {
41c445ff 3777 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3778 "AQ command Config VSI BW allocation per TC failed = %d\n",
3779 vsi->back->hw.aq.asq_last_status);
dcae29be 3780 return -EINVAL;
41c445ff
JB		 3781 }
3782
3783 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3784 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3785
dcae29be 3786 return 0;
41c445ff
JB		 3787}
3788
3789/**
3790 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3791 * @vsi: the VSI being configured
3792 * @enabled_tc: TC map to be enabled
3793 *
3794 **/
3795static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3796{
3797 struct net_device *netdev = vsi->netdev;
3798 struct i40e_pf *pf = vsi->back;
3799 struct i40e_hw *hw = &pf->hw;
3800 u8 netdev_tc = 0;
3801 int i;
3802 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3803
3804 if (!netdev)
3805 return;
3806
3807 if (!enabled_tc) {
3808 netdev_reset_tc(netdev);
3809 return;
3810 }
3811
3812 /* Set up actual enabled TCs on the VSI */
3813 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3814 return;
3815
3816 /* set per TC queues for the VSI */
3817 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3818 /* Only set TC queues for enabled tcs
3819 *
3820 * e.g. For a VSI that has TC0 and TC3 enabled the
3821 * enabled_tc bitmap would be 0x00001001; the driver
3822 * will set the numtc for netdev as 2 that will be
3823 * referenced by the netdev layer as TC 0 and 1.
3824 */
3825 if (vsi->tc_config.enabled_tc & (1 << i))
3826 netdev_set_tc_queue(netdev,
3827 vsi->tc_config.tc_info[i].netdev_tc,
3828 vsi->tc_config.tc_info[i].qcount,
3829 vsi->tc_config.tc_info[i].qoffset);
3830 }
3831
3832 /* Assign UP2TC map for the VSI */
3833 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3834 /* Get the actual TC# for the UP */
3835 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3836 /* Get the mapped netdev TC# for the UP */
3837 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3838 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3839 }
3840}
3841
3842/**
3843 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3844 * @vsi: the VSI being configured
3845 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3846 **/
3847static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3848 struct i40e_vsi_context *ctxt)
3849{
3850 /* copy just the sections touched not the entire info
3851 * since not all sections are valid as returned by
3852 * update vsi params
3853 */
3854 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3855 memcpy(&vsi->info.queue_mapping,
3856 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3857 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3858 sizeof(vsi->info.tc_mapping));
3859}
3860
3861/**
3862 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3863 * @vsi: VSI to be configured
3864 * @enabled_tc: TC bitmap
3865 *
3866 * This configures a particular VSI for TCs that are mapped to the
3867 * given TC bitmap. It uses default bandwidth share for TCs across
3868 * VSIs to configure TC for a particular VSI.
3869 *
3870 * NOTE:
3871 * It is expected that the VSI queues have been quisced before calling
3872 * this function.
3873 **/
3874static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3875{
3876 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3877 struct i40e_vsi_context ctxt;
3878 int ret = 0;
3879 int i;
3880
3881 /* Check if enabled_tc is same as existing or new TCs */
3882 if (vsi->tc_config.enabled_tc == enabled_tc)
3883 return ret;
3884
3885 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3886 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3887 if (enabled_tc & (1 << i))
3888 bw_share[i] = 1;
3889 }
3890
3891 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3892 if (ret) {
3893 dev_info(&vsi->back->pdev->dev,
3894 "Failed configuring TC map %d for VSI %d\n",
3895 enabled_tc, vsi->seid);
3896 goto out;
3897 }
3898
3899 /* Update Queue Pairs Mapping for currently enabled UPs */
3900 ctxt.seid = vsi->seid;
3901 ctxt.pf_num = vsi->back->hw.pf_id;
3902 ctxt.vf_num = 0;
3903 ctxt.uplink_seid = vsi->uplink_seid;
3904 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3905 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3906
3907 /* Update the VSI after updating the VSI queue-mapping information */
3908 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3909 if (ret) {
3910 dev_info(&vsi->back->pdev->dev,
3911 "update vsi failed, aq_err=%d\n",
3912 vsi->back->hw.aq.asq_last_status);
3913 goto out;
3914 }
3915 /* update the local VSI info with updated queue map */
3916 i40e_vsi_update_queue_map(vsi, &ctxt);
3917 vsi->info.valid_sections = 0;
3918
3919 /* Update current VSI BW information */
3920 ret = i40e_vsi_get_bw_info(vsi);
3921 if (ret) {
3922 dev_info(&vsi->back->pdev->dev,
3923 "Failed updating vsi bw info, aq_err=%d\n",
3924 vsi->back->hw.aq.asq_last_status);
3925 goto out;
3926 }
3927
3928 /* Update the netdev TC setup */
3929 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3930out:
3931 return ret;
3932}
3933
4e3b35b0
NP		 3934/**
3935 * i40e_veb_config_tc - Configure TCs for given VEB
3936 * @veb: given VEB
3937 * @enabled_tc: TC bitmap
3938 *
3939 * Configures given TC bitmap for VEB (switching) element
3940 **/
3941int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
3942{
3943 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
3944 struct i40e_pf *pf = veb->pf;
3945 int ret = 0;
3946 int i;
3947
3948 /* No TCs or already enabled TCs just return */
3949 if (!enabled_tc || veb->enabled_tc == enabled_tc)
3950 return ret;
3951
3952 bw_data.tc_valid_bits = enabled_tc;
3953 /* bw_data.absolute_credits is not set (relative) */
3954
3955 /* Enable ETS TCs with equal BW Share for now */
3956 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3957 if (enabled_tc & (1 << i))
3958 bw_data.tc_bw_share_credits[i] = 1;
3959 }
3960
3961 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
3962 &bw_data, NULL);
3963 if (ret) {
3964 dev_info(&pf->pdev->dev,
3965 "veb bw config failed, aq_err=%d\n",
3966 pf->hw.aq.asq_last_status);
3967 goto out;
3968 }
3969
3970 /* Update the BW information */
3971 ret = i40e_veb_get_bw_info(veb);
3972 if (ret) {
3973 dev_info(&pf->pdev->dev,
3974 "Failed getting veb bw config, aq_err=%d\n",
3975 pf->hw.aq.asq_last_status);
3976 }
3977
3978out:
3979 return ret;
3980}
3981
3982#ifdef CONFIG_I40E_DCB
3983/**
3984 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
3985 * @pf: PF struct
3986 *
3987 * Reconfigure VEB/VSIs on a given PF; it is assumed that
3988 * the caller would've quiesce all the VSIs before calling
3989 * this function
3990 **/
3991static void i40e_dcb_reconfigure(struct i40e_pf *pf)
3992{
3993 u8 tc_map = 0;
3994 int ret;
3995 u8 v;
3996
3997 /* Enable the TCs available on PF to all VEBs */
3998 tc_map = i40e_pf_get_tc_map(pf);
3999 for (v = 0; v < I40E_MAX_VEB; v++) {
4000 if (!pf->veb[v])
4001 continue;
4002 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4003 if (ret) {
4004 dev_info(&pf->pdev->dev,
4005 "Failed configuring TC for VEB seid=%d\n",
4006 pf->veb[v]->seid);
4007 /* Will try to configure as many components */
4008 }
4009 }
4010
4011 /* Update each VSI */
4012 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4013 if (!pf->vsi[v])
4014 continue;
4015
4016 /* - Enable all TCs for the LAN VSI
4017 * - For all others keep them at TC0 for now
4018 */
4019 if (v == pf->lan_vsi)
4020 tc_map = i40e_pf_get_tc_map(pf);
4021 else
4022 tc_map = i40e_pf_get_default_tc(pf);
4023
4024 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4025 if (ret) {
4026 dev_info(&pf->pdev->dev,
4027 "Failed configuring TC for VSI seid=%d\n",
4028 pf->vsi[v]->seid);
4029 /* Will try to configure as many components */
4030 } else {
4031 if (pf->vsi[v]->netdev)
4032 i40e_dcbnl_set_all(pf->vsi[v]);
4033 }
4034 }
4035}
4036
4037/**
4038 * i40e_init_pf_dcb - Initialize DCB configuration
4039 * @pf: PF being configured
4040 *
4041 * Query the current DCB configuration and cache it
4042 * in the hardware structure
4043 **/
4044static int i40e_init_pf_dcb(struct i40e_pf *pf)
4045{
4046 struct i40e_hw *hw = &pf->hw;
4047 int err = 0;
4048
4049 if (pf->hw.func_caps.npar_enable)
4050 goto out;
4051
4052 /* Get the initial DCB configuration */
4053 err = i40e_init_dcb(hw);
4054 if (!err) {
4055 /* Device/Function is not DCBX capable */
4056 if ((!hw->func_caps.dcb) ||
4057 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4058 dev_info(&pf->pdev->dev,
4059 "DCBX offload is not supported or is disabled for this PF.\n");
4060
4061 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4062 goto out;
4063
4064 } else {
4065 /* When status is not DISABLED then DCBX in FW */
4066 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4067 DCB_CAP_DCBX_VER_IEEE;
4068 pf->flags |= I40E_FLAG_DCB_ENABLED;
4069 }
4070 }
4071
4072out:
4073 return err;
4074}
4075#endif /* CONFIG_I40E_DCB */
4076
41c445ff
JB		 4077/**
4078 * i40e_up_complete - Finish the last steps of bringing up a connection
4079 * @vsi: the VSI being configured
4080 **/
4081static int i40e_up_complete(struct i40e_vsi *vsi)
4082{
4083 struct i40e_pf *pf = vsi->back;
4084 int err;
4085
4086 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4087 i40e_vsi_configure_msix(vsi);
4088 else
4089 i40e_configure_msi_and_legacy(vsi);
4090
4091 /* start rings */
4092 err = i40e_vsi_control_rings(vsi, true);
4093 if (err)
4094 return err;
4095
4096 clear_bit(__I40E_DOWN, &vsi->state);
4097 i40e_napi_enable_all(vsi);
4098 i40e_vsi_enable_irq(vsi);
4099
4100 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4101 (vsi->netdev)) {
6d779b41 4102 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 4103 netif_tx_start_all_queues(vsi->netdev);
4104 netif_carrier_on(vsi->netdev);
6d779b41
AS		 4105 } else if (vsi->netdev) {
4106 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff 4107 }
ca64fa4e
ASJ		 4108
4109 /* replay FDIR SB filters */
4110 if (vsi->type == I40E_VSI_FDIR)
4111 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4112 i40e_service_event_schedule(pf);
4113
4114 return 0;
4115}
4116
4117/**
4118 * i40e_vsi_reinit_locked - Reset the VSI
4119 * @vsi: the VSI being configured
4120 *
4121 * Rebuild the ring structs after some configuration
4122 * has changed, e.g. MTU size.
4123 **/
4124static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4125{
4126 struct i40e_pf *pf = vsi->back;
4127
4128 WARN_ON(in_interrupt());
4129 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4130 usleep_range(1000, 2000);
4131 i40e_down(vsi);
4132
4133 /* Give a VF some time to respond to the reset. The
4134 * two second wait is based upon the watchdog cycle in
4135 * the VF driver.
4136 */
4137 if (vsi->type == I40E_VSI_SRIOV)
4138 msleep(2000);
4139 i40e_up(vsi);
4140 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4141}
4142
4143/**
4144 * i40e_up - Bring the connection back up after being down
4145 * @vsi: the VSI being configured
4146 **/
4147int i40e_up(struct i40e_vsi *vsi)
4148{
4149 int err;
4150
4151 err = i40e_vsi_configure(vsi);
4152 if (!err)
4153 err = i40e_up_complete(vsi);
4154
4155 return err;
4156}
4157
4158/**
4159 * i40e_down - Shutdown the connection processing
4160 * @vsi: the VSI being stopped
4161 **/
4162void i40e_down(struct i40e_vsi *vsi)
4163{
4164 int i;
4165
4166 /* It is assumed that the caller of this function
4167 * sets the vsi->state __I40E_DOWN bit.
4168 */
4169 if (vsi->netdev) {
4170 netif_carrier_off(vsi->netdev);
4171 netif_tx_disable(vsi->netdev);
4172 }
4173 i40e_vsi_disable_irq(vsi);
4174 i40e_vsi_control_rings(vsi, false);
4175 i40e_napi_disable_all(vsi);
4176
4177 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4178 i40e_clean_tx_ring(vsi->tx_rings[i]);
4179 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4180 }
4181}
4182
4183/**
4184 * i40e_setup_tc - configure multiple traffic classes
4185 * @netdev: net device to configure
4186 * @tc: number of traffic classes to enable
4187 **/
4188static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4189{
4190 struct i40e_netdev_priv *np = netdev_priv(netdev);
4191 struct i40e_vsi *vsi = np->vsi;
4192 struct i40e_pf *pf = vsi->back;
4193 u8 enabled_tc = 0;
4194 int ret = -EINVAL;
4195 int i;
4196
4197 /* Check if DCB enabled to continue */
4198 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4199 netdev_info(netdev, "DCB is not enabled for adapter\n");
4200 goto exit;
4201 }
4202
4203 /* Check if MFP enabled */
4204 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4205 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4206 goto exit;
4207 }
4208
4209 /* Check whether tc count is within enabled limit */
4210 if (tc > i40e_pf_get_num_tc(pf)) {
4211 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4212 goto exit;
4213 }
4214
4215 /* Generate TC map for number of tc requested */
4216 for (i = 0; i < tc; i++)
4217 enabled_tc |= (1 << i);
4218
4219 /* Requesting same TC configuration as already enabled */
4220 if (enabled_tc == vsi->tc_config.enabled_tc)
4221 return 0;
4222
4223 /* Quiesce VSI queues */
4224 i40e_quiesce_vsi(vsi);
4225
4226 /* Configure VSI for enabled TCs */
4227 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4228 if (ret) {
4229 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4230 vsi->seid);
4231 goto exit;
4232 }
4233
4234 /* Unquiesce VSI */
4235 i40e_unquiesce_vsi(vsi);
4236
4237exit:
4238 return ret;
4239}
4240
4241/**
4242 * i40e_open - Called when a network interface is made active
4243 * @netdev: network interface device structure
4244 *
4245 * The open entry point is called when a network interface is made
4246 * active by the system (IFF_UP). At this point all resources needed
4247 * for transmit and receive operations are allocated, the interrupt
4248 * handler is registered with the OS, the netdev watchdog subtask is
4249 * enabled, and the stack is notified that the interface is ready.
4250 *
4251 * Returns 0 on success, negative value on failure
4252 **/
4253static int i40e_open(struct net_device *netdev)
4254{
4255 struct i40e_netdev_priv *np = netdev_priv(netdev);
4256 struct i40e_vsi *vsi = np->vsi;
4257 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4258 int err;
4259
4260 /* disallow open during test */
4261 if (test_bit(__I40E_TESTING, &pf->state))
4262 return -EBUSY;
4263
4264 netif_carrier_off(netdev);
4265
6c167f58
EK		 4266 err = i40e_vsi_open(vsi);
4267 if (err)
4268 return err;
4269
4270#ifdef CONFIG_I40E_VXLAN
4271 vxlan_get_rx_port(netdev);
4272#endif
4273
4274 return 0;
4275}
4276
4277/**
4278 * i40e_vsi_open -
4279 * @vsi: the VSI to open
4280 *
4281 * Finish initialization of the VSI.
4282 *
4283 * Returns 0 on success, negative value on failure
4284 **/
4285int i40e_vsi_open(struct i40e_vsi *vsi)
4286{
4287 struct i40e_pf *pf = vsi->back;
4288 char int_name[IFNAMSIZ];
4289 int err;
4290
41c445ff
JB		 4291 /* allocate descriptors */
4292 err = i40e_vsi_setup_tx_resources(vsi);
4293 if (err)
4294 goto err_setup_tx;
4295 err = i40e_vsi_setup_rx_resources(vsi);
4296 if (err)
4297 goto err_setup_rx;
4298
4299 err = i40e_vsi_configure(vsi);
4300 if (err)
4301 goto err_setup_rx;
4302
6c167f58
EK		 4303 if (!vsi->netdev) {
4304 err = EINVAL;
4305 goto err_setup_rx;
4306 }
41c445ff 4307 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
6c167f58 4308 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
41c445ff
JB		 4309 err = i40e_vsi_request_irq(vsi, int_name);
4310 if (err)
4311 goto err_setup_rx;
4312
25946ddb 4313 /* Notify the stack of the actual queue counts. */
6c167f58 4314 err = netif_set_real_num_tx_queues(vsi->netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4315 if (err)
4316 goto err_set_queues;
4317
6c167f58 4318 err = netif_set_real_num_rx_queues(vsi->netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4319 if (err)
4320 goto err_set_queues;
4321
41c445ff
JB		 4322 err = i40e_up_complete(vsi);
4323 if (err)
4324 goto err_up_complete;
4325
41c445ff
JB		 4326 return 0;
4327
4328err_up_complete:
4329 i40e_down(vsi);
25946ddb 4330err_set_queues:
41c445ff
JB		 4331 i40e_vsi_free_irq(vsi);
4332err_setup_rx:
4333 i40e_vsi_free_rx_resources(vsi);
4334err_setup_tx:
4335 i40e_vsi_free_tx_resources(vsi);
4336 if (vsi == pf->vsi[pf->lan_vsi])
4337 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4338
4339 return err;
4340}
4341
17a73f6b
JG		 4342/**
4343 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4344 * @pf: Pointer to pf
4345 *
4346 * This function destroys the hlist where all the Flow Director
4347 * filters were saved.
4348 **/
4349static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4350{
4351 struct i40e_fdir_filter *filter;
4352 struct hlist_node *node2;
4353
4354 hlist_for_each_entry_safe(filter, node2,
4355 &pf->fdir_filter_list, fdir_node) {
4356 hlist_del(&filter->fdir_node);
4357 kfree(filter);
4358 }
4359 pf->fdir_pf_active_filters = 0;
4360}
4361
41c445ff
JB		 4362/**
4363 * i40e_close - Disables a network interface
4364 * @netdev: network interface device structure
4365 *
4366 * The close entry point is called when an interface is de-activated
4367 * by the OS. The hardware is still under the driver's control, but
4368 * this netdev interface is disabled.
4369 *
4370 * Returns 0, this is not allowed to fail
4371 **/
4372static int i40e_close(struct net_device *netdev)
4373{
4374 struct i40e_netdev_priv *np = netdev_priv(netdev);
4375 struct i40e_vsi *vsi = np->vsi;
4376
4377 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4378 return 0;
4379
4380 i40e_down(vsi);
4381 i40e_vsi_free_irq(vsi);
4382
4383 i40e_vsi_free_tx_resources(vsi);
4384 i40e_vsi_free_rx_resources(vsi);
4385
4386 return 0;
4387}
4388
4389/**
4390 * i40e_do_reset - Start a PF or Core Reset sequence
4391 * @pf: board private structure
4392 * @reset_flags: which reset is requested
4393 *
4394 * The essential difference in resets is that the PF Reset
4395 * doesn't clear the packet buffers, doesn't reset the PE
4396 * firmware, and doesn't bother the other PFs on the chip.
4397 **/
4398void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4399{
4400 u32 val;
4401
4402 WARN_ON(in_interrupt());
4403
4404 /* do the biggest reset indicated */
4405 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4406
4407 /* Request a Global Reset
4408 *
4409 * This will start the chip's countdown to the actual full
4410 * chip reset event, and a warning interrupt to be sent
4411 * to all PFs, including the requestor. Our handler
4412 * for the warning interrupt will deal with the shutdown
4413 * and recovery of the switch setup.
4414 */
69bfb110 4415 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4416 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4417 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4418 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4419
4420 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4421
4422 /* Request a Core Reset
4423 *
4424 * Same as Global Reset, except does *not* include the MAC/PHY
4425 */
69bfb110 4426 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4427 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4428 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4429 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4430 i40e_flush(&pf->hw);
4431
7823fe34
SN		 4432 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4433
4434 /* Request a Firmware Reset
4435 *
4436 * Same as Global reset, plus restarting the
4437 * embedded firmware engine.
4438 */
4439 /* enable EMP Reset */
4440 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4441 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4442 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4443
4444 /* force the reset */
4445 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4446 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4447 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4448 i40e_flush(&pf->hw);
4449
41c445ff
JB		 4450 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4451
4452 /* Request a PF Reset
4453 *
4454 * Resets only the PF-specific registers
4455 *
4456 * This goes directly to the tear-down and rebuild of
4457 * the switch, since we need to do all the recovery as
4458 * for the Core Reset.
4459 */
69bfb110 4460 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4461 i40e_handle_reset_warning(pf);
4462
4463 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4464 int v;
4465
4466 /* Find the VSI(s) that requested a re-init */
4467 dev_info(&pf->pdev->dev,
4468 "VSI reinit requested\n");
4469 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4470 struct i40e_vsi *vsi = pf->vsi[v];
4471 if (vsi != NULL &&
4472 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4473 i40e_vsi_reinit_locked(pf->vsi[v]);
4474 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4475 }
4476 }
4477
4478 /* no further action needed, so return now */
4479 return;
4480 } else {
4481 dev_info(&pf->pdev->dev,
4482 "bad reset request 0x%08x\n", reset_flags);
4483 return;
4484 }
4485}
4486
4e3b35b0
NP		 4487#ifdef CONFIG_I40E_DCB
4488/**
4489 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4490 * @pf: board private structure
4491 * @old_cfg: current DCB config
4492 * @new_cfg: new DCB config
4493 **/
4494bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4495 struct i40e_dcbx_config *old_cfg,
4496 struct i40e_dcbx_config *new_cfg)
4497{
4498 bool need_reconfig = false;
4499
4500 /* Check if ETS configuration has changed */
4501 if (memcmp(&new_cfg->etscfg,
4502 &old_cfg->etscfg,
4503 sizeof(new_cfg->etscfg))) {
4504 /* If Priority Table has changed reconfig is needed */
4505 if (memcmp(&new_cfg->etscfg.prioritytable,
4506 &old_cfg->etscfg.prioritytable,
4507 sizeof(new_cfg->etscfg.prioritytable))) {
4508 need_reconfig = true;
69bfb110 4509 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4510 }
4511
4512 if (memcmp(&new_cfg->etscfg.tcbwtable,
4513 &old_cfg->etscfg.tcbwtable,
4514 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4515 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4516
4517 if (memcmp(&new_cfg->etscfg.tsatable,
4518 &old_cfg->etscfg.tsatable,
4519 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4520 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4521 }
4522
4523 /* Check if PFC configuration has changed */
4524 if (memcmp(&new_cfg->pfc,
4525 &old_cfg->pfc,
4526 sizeof(new_cfg->pfc))) {
4527 need_reconfig = true;
69bfb110 4528 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4529 }
4530
4531 /* Check if APP Table has changed */
4532 if (memcmp(&new_cfg->app,
4533 &old_cfg->app,
3d9667a9 4534 sizeof(new_cfg->app))) {
4e3b35b0 4535 need_reconfig = true;
69bfb110 4536 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4537 }
4e3b35b0
NP		 4538
4539 return need_reconfig;
4540}
4541
4542/**
4543 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4544 * @pf: board private structure
4545 * @e: event info posted on ARQ
4546 **/
4547static int i40e_handle_lldp_event(struct i40e_pf *pf,
4548 struct i40e_arq_event_info *e)
4549{
4550 struct i40e_aqc_lldp_get_mib *mib =
4551 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4552 struct i40e_hw *hw = &pf->hw;
4553 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4554 struct i40e_dcbx_config tmp_dcbx_cfg;
4555 bool need_reconfig = false;
4556 int ret = 0;
4557 u8 type;
4558
4559 /* Ignore if event is not for Nearest Bridge */
4560 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4561 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4562 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4563 return ret;
4564
4565 /* Check MIB Type and return if event for Remote MIB update */
4566 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4567 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4568 /* Update the remote cached instance and return */
4569 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4570 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4571 &hw->remote_dcbx_config);
4572 goto exit;
4573 }
4574
4575 /* Convert/store the DCBX data from LLDPDU temporarily */
4576 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4577 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4578 if (ret) {
4579 /* Error in LLDPDU parsing return */
4580 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4581 goto exit;
4582 }
4583
4584 /* No change detected in DCBX configs */
4585 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4586 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4587 goto exit;
4588 }
4589
4590 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4591
4592 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4593
4594 /* Overwrite the new configuration */
4595 *dcbx_cfg = tmp_dcbx_cfg;
4596
4597 if (!need_reconfig)
4598 goto exit;
4599
4600 /* Reconfiguration needed quiesce all VSIs */
4601 i40e_pf_quiesce_all_vsi(pf);
4602
4603 /* Changes in configuration update VEB/VSI */
4604 i40e_dcb_reconfigure(pf);
4605
4606 i40e_pf_unquiesce_all_vsi(pf);
4607exit:
4608 return ret;
4609}
4610#endif /* CONFIG_I40E_DCB */
4611
23326186
ASJ		 4612/**
4613 * i40e_do_reset_safe - Protected reset path for userland calls.
4614 * @pf: board private structure
4615 * @reset_flags: which reset is requested
4616 *
4617 **/
4618void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4619{
4620 rtnl_lock();
4621 i40e_do_reset(pf, reset_flags);
4622 rtnl_unlock();
4623}
4624
41c445ff
JB		 4625/**
4626 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4627 * @pf: board private structure
4628 * @e: event info posted on ARQ
4629 *
4630 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4631 * and VF queues
4632 **/
4633static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4634 struct i40e_arq_event_info *e)
4635{
4636 struct i40e_aqc_lan_overflow *data =
4637 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4638 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4639 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4640 struct i40e_hw *hw = &pf->hw;
4641 struct i40e_vf *vf;
4642 u16 vf_id;
4643
69bfb110
JB		 4644 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4645 queue, qtx_ctl);
41c445ff
JB		 4646
4647 /* Queue belongs to VF, find the VF and issue VF reset */
4648 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4649 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4650 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4651 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4652 vf_id -= hw->func_caps.vf_base_id;
4653 vf = &pf->vf[vf_id];
4654 i40e_vc_notify_vf_reset(vf);
4655 /* Allow VF to process pending reset notification */
4656 msleep(20);
4657 i40e_reset_vf(vf, false);
4658 }
4659}
4660
4661/**
4662 * i40e_service_event_complete - Finish up the service event
4663 * @pf: board private structure
4664 **/
4665static void i40e_service_event_complete(struct i40e_pf *pf)
4666{
4667 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4668
4669 /* flush memory to make sure state is correct before next watchog */
4670 smp_mb__before_clear_bit();
4671 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4672}
4673
55a5e60b
ASJ		 4674/**
4675 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4676 * @pf: board private structure
4677 **/
4678int i40e_get_current_fd_count(struct i40e_pf *pf)
4679{
4680 int val, fcnt_prog;
4681 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4682 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4683 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4684 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4685 return fcnt_prog;
4686}
4687
4688/**
4689 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4690 * @pf: board private structure
4691 **/
4692void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4693{
4694 u32 fcnt_prog, fcnt_avail;
4695
4696 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4697 * to re-enable
4698 */
4699 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4700 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4701 return;
4702 fcnt_prog = i40e_get_current_fd_count(pf);
4703 fcnt_avail = pf->hw.fdir_shared_filter_count +
4704 pf->fdir_pf_filter_count;
4705 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4706 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4707 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4708 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4709 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4710 }
4711 }
4712 /* Wait for some more space to be available to turn on ATR */
4713 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4714 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4715 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4716 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4717 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4718 }
4719 }
4720}
4721
41c445ff
JB		 4722/**
4723 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4724 * @pf: board private structure
4725 **/
4726static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4727{
4728 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4729 return;
4730
41c445ff
JB		 4731 /* if interface is down do nothing */
4732 if (test_bit(__I40E_DOWN, &pf->state))
4733 return;
55a5e60b
ASJ		 4734 i40e_fdir_check_and_reenable(pf);
4735
4736 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4737 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4738 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 4739}
4740
4741/**
4742 * i40e_vsi_link_event - notify VSI of a link event
4743 * @vsi: vsi to be notified
4744 * @link_up: link up or down
4745 **/
4746static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4747{
4748 if (!vsi)
4749 return;
4750
4751 switch (vsi->type) {
4752 case I40E_VSI_MAIN:
4753 if (!vsi->netdev || !vsi->netdev_registered)
4754 break;
4755
4756 if (link_up) {
4757 netif_carrier_on(vsi->netdev);
4758 netif_tx_wake_all_queues(vsi->netdev);
4759 } else {
4760 netif_carrier_off(vsi->netdev);
4761 netif_tx_stop_all_queues(vsi->netdev);
4762 }
4763 break;
4764
4765 case I40E_VSI_SRIOV:
4766 break;
4767
4768 case I40E_VSI_VMDQ2:
4769 case I40E_VSI_CTRL:
4770 case I40E_VSI_MIRROR:
4771 default:
4772 /* there is no notification for other VSIs */
4773 break;
4774 }
4775}
4776
4777/**
4778 * i40e_veb_link_event - notify elements on the veb of a link event
4779 * @veb: veb to be notified
4780 * @link_up: link up or down
4781 **/
4782static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4783{
4784 struct i40e_pf *pf;
4785 int i;
4786
4787 if (!veb || !veb->pf)
4788 return;
4789 pf = veb->pf;
4790
4791 /* depth first... */
4792 for (i = 0; i < I40E_MAX_VEB; i++)
4793 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4794 i40e_veb_link_event(pf->veb[i], link_up);
4795
4796 /* ... now the local VSIs */
4797 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4798 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4799 i40e_vsi_link_event(pf->vsi[i], link_up);
4800}
4801
4802/**
4803 * i40e_link_event - Update netif_carrier status
4804 * @pf: board private structure
4805 **/
4806static void i40e_link_event(struct i40e_pf *pf)
4807{
4808 bool new_link, old_link;
4809
4810 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4811 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4812
4813 if (new_link == old_link)
4814 return;
4815
6d779b41
AS		 4816 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4817 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4818 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4819
4820 /* Notify the base of the switch tree connected to
4821 * the link. Floating VEBs are not notified.
4822 */
4823 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4824 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4825 else
4826 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4827
4828 if (pf->vf)
4829 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4830
4831 if (pf->flags & I40E_FLAG_PTP)
4832 i40e_ptp_set_increment(pf);
41c445ff
JB		 4833}
4834
4835/**
4836 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4837 * @pf: board private structure
4838 *
4839 * Set the per-queue flags to request a check for stuck queues in the irq
4840 * clean functions, then force interrupts to be sure the irq clean is called.
4841 **/
4842static void i40e_check_hang_subtask(struct i40e_pf *pf)
4843{
4844 int i, v;
4845
4846 /* If we're down or resetting, just bail */
4847 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4848 return;
4849
4850 /* for each VSI/netdev
4851 * for each Tx queue
4852 * set the check flag
4853 * for each q_vector
4854 * force an interrupt
4855 */
4856 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4857 struct i40e_vsi *vsi = pf->vsi[v];
4858 int armed = 0;
4859
4860 if (!pf->vsi[v] ||
4861 test_bit(__I40E_DOWN, &vsi->state) ||
4862 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4863 continue;
4864
4865 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4866 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4867 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4868 &vsi->tx_rings[i]->state))
41c445ff
JB		 4869 armed++;
4870 }
4871
4872 if (armed) {
4873 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4874 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4875 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4876 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4877 } else {
4878 u16 vec = vsi->base_vector - 1;
4879 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4880 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4881 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4882 wr32(&vsi->back->hw,
4883 I40E_PFINT_DYN_CTLN(vec), val);
4884 }
4885 i40e_flush(&vsi->back->hw);
4886 }
4887 }
4888}
4889
4890/**
4891 * i40e_watchdog_subtask - Check and bring link up
4892 * @pf: board private structure
4893 **/
4894static void i40e_watchdog_subtask(struct i40e_pf *pf)
4895{
4896 int i;
4897
4898 /* if interface is down do nothing */
4899 if (test_bit(__I40E_DOWN, &pf->state) ||
4900 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4901 return;
4902
4903 /* Update the stats for active netdevs so the network stack
4904 * can look at updated numbers whenever it cares to
4905 */
4906 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4907 if (pf->vsi[i] && pf->vsi[i]->netdev)
4908 i40e_update_stats(pf->vsi[i]);
4909
4910 /* Update the stats for the active switching components */
4911 for (i = 0; i < I40E_MAX_VEB; i++)
4912 if (pf->veb[i])
4913 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 4914
4915 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 4916}
4917
4918/**
4919 * i40e_reset_subtask - Set up for resetting the device and driver
4920 * @pf: board private structure
4921 **/
4922static void i40e_reset_subtask(struct i40e_pf *pf)
4923{
4924 u32 reset_flags = 0;
4925
23326186 4926 rtnl_lock();
41c445ff
JB		 4927 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4928 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4929 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4930 }
4931 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4932 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4933 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4934 }
4935 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4936 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4937 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4938 }
4939 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4940 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4941 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4942 }
4943
4944 /* If there's a recovery already waiting, it takes
4945 * precedence before starting a new reset sequence.
4946 */
4947 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4948 i40e_handle_reset_warning(pf);
23326186 4949 goto unlock;
41c445ff
JB		 4950 }
4951
4952 /* If we're already down or resetting, just bail */
4953 if (reset_flags &&
4954 !test_bit(__I40E_DOWN, &pf->state) &&
4955 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4956 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4957
4958unlock:
4959 rtnl_unlock();
41c445ff
JB		 4960}
4961
4962/**
4963 * i40e_handle_link_event - Handle link event
4964 * @pf: board private structure
4965 * @e: event info posted on ARQ
4966 **/
4967static void i40e_handle_link_event(struct i40e_pf *pf,
4968 struct i40e_arq_event_info *e)
4969{
4970 struct i40e_hw *hw = &pf->hw;
4971 struct i40e_aqc_get_link_status *status =
4972 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4973 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4974
4975 /* save off old link status information */
4976 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4977 sizeof(pf->hw.phy.link_info_old));
4978
4979 /* update link status */
4980 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4981 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4982 hw_link_info->link_info = status->link_info;
4983 hw_link_info->an_info = status->an_info;
4984 hw_link_info->ext_info = status->ext_info;
4985 hw_link_info->lse_enable =
4986 le16_to_cpu(status->command_flags) &
4987 I40E_AQ_LSE_ENABLE;
4988
4989 /* process the event */
4990 i40e_link_event(pf);
4991
4992 /* Do a new status request to re-enable LSE reporting
4993 * and load new status information into the hw struct,
4994 * then see if the status changed while processing the
4995 * initial event.
4996 */
4997 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4998 i40e_link_event(pf);
4999}
5000
5001/**
5002 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5003 * @pf: board private structure
5004 **/
5005static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5006{
5007 struct i40e_arq_event_info event;
5008 struct i40e_hw *hw = &pf->hw;
5009 u16 pending, i = 0;
5010 i40e_status ret;
5011 u16 opcode;
5012 u32 val;
5013
5014 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5015 return;
5016
3197ce22 5017 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5018 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5019 if (!event.msg_buf)
5020 return;
5021
5022 do {
2f019123 5023 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5024 ret = i40e_clean_arq_element(hw, &event, &pending);
5025 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5026 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5027 break;
5028 } else if (ret) {
5029 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5030 break;
5031 }
5032
5033 opcode = le16_to_cpu(event.desc.opcode);
5034 switch (opcode) {
5035
5036 case i40e_aqc_opc_get_link_status:
5037 i40e_handle_link_event(pf, &event);
5038 break;
5039 case i40e_aqc_opc_send_msg_to_pf:
5040 ret = i40e_vc_process_vf_msg(pf,
5041 le16_to_cpu(event.desc.retval),
5042 le32_to_cpu(event.desc.cookie_high),
5043 le32_to_cpu(event.desc.cookie_low),
5044 event.msg_buf,
5045 event.msg_size);
5046 break;
5047 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5048 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5049#ifdef CONFIG_I40E_DCB
5050 rtnl_lock();
5051 ret = i40e_handle_lldp_event(pf, &event);
5052 rtnl_unlock();
5053#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5054 break;
5055 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5056 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5057 i40e_handle_lan_overflow_event(pf, &event);
5058 break;
0467bc91
SN		 5059 case i40e_aqc_opc_send_msg_to_peer:
5060 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5061 break;
41c445ff
JB		 5062 default:
5063 dev_info(&pf->pdev->dev,
0467bc91
SN		 5064 "ARQ Error: Unknown event 0x%04x received\n",
5065 opcode);
41c445ff
JB		 5066 break;
5067 }
5068 } while (pending && (i++ < pf->adminq_work_limit));
5069
5070 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5071 /* re-enable Admin queue interrupt cause */
5072 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5073 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5074 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5075 i40e_flush(hw);
5076
5077 kfree(event.msg_buf);
5078}
5079
5080/**
5081 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5082 * @veb: pointer to the VEB instance
5083 *
5084 * This is a recursive function that first builds the attached VSIs then
5085 * recurses in to build the next layer of VEB. We track the connections
5086 * through our own index numbers because the seid's from the HW could
5087 * change across the reset.
5088 **/
5089static int i40e_reconstitute_veb(struct i40e_veb *veb)
5090{
5091 struct i40e_vsi *ctl_vsi = NULL;
5092 struct i40e_pf *pf = veb->pf;
5093 int v, veb_idx;
5094 int ret;
5095
5096 /* build VSI that owns this VEB, temporarily attached to base VEB */
5097 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
5098 if (pf->vsi[v] &&
5099 pf->vsi[v]->veb_idx == veb->idx &&
5100 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5101 ctl_vsi = pf->vsi[v];
5102 break;
5103 }
5104 }
5105 if (!ctl_vsi) {
5106 dev_info(&pf->pdev->dev,
5107 "missing owner VSI for veb_idx %d\n", veb->idx);
5108 ret = -ENOENT;
5109 goto end_reconstitute;
5110 }
5111 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5112 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5113 ret = i40e_add_vsi(ctl_vsi);
5114 if (ret) {
5115 dev_info(&pf->pdev->dev,
5116 "rebuild of owner VSI failed: %d\n", ret);
5117 goto end_reconstitute;
5118 }
5119 i40e_vsi_reset_stats(ctl_vsi);
5120
5121 /* create the VEB in the switch and move the VSI onto the VEB */
5122 ret = i40e_add_veb(veb, ctl_vsi);
5123 if (ret)
5124 goto end_reconstitute;
5125
5126 /* create the remaining VSIs attached to this VEB */
5127 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5128 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5129 continue;
5130
5131 if (pf->vsi[v]->veb_idx == veb->idx) {
5132 struct i40e_vsi *vsi = pf->vsi[v];
5133 vsi->uplink_seid = veb->seid;
5134 ret = i40e_add_vsi(vsi);
5135 if (ret) {
5136 dev_info(&pf->pdev->dev,
5137 "rebuild of vsi_idx %d failed: %d\n",
5138 v, ret);
5139 goto end_reconstitute;
5140 }
5141 i40e_vsi_reset_stats(vsi);
5142 }
5143 }
5144
5145 /* create any VEBs attached to this VEB - RECURSION */
5146 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5147 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5148 pf->veb[veb_idx]->uplink_seid = veb->seid;
5149 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5150 if (ret)
5151 break;
5152 }
5153 }
5154
5155end_reconstitute:
5156 return ret;
5157}
5158
5159/**
5160 * i40e_get_capabilities - get info about the HW
5161 * @pf: the PF struct
5162 **/
5163static int i40e_get_capabilities(struct i40e_pf *pf)
5164{
5165 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5166 u16 data_size;
5167 int buf_len;
5168 int err;
5169
5170 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5171 do {
5172 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5173 if (!cap_buf)
5174 return -ENOMEM;
5175
5176 /* this loads the data into the hw struct for us */
5177 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5178 &data_size,
5179 i40e_aqc_opc_list_func_capabilities,
5180 NULL);
5181 /* data loaded, buffer no longer needed */
5182 kfree(cap_buf);
5183
5184 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5185 /* retry with a larger buffer */
5186 buf_len = data_size;
5187 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5188 dev_info(&pf->pdev->dev,
5189 "capability discovery failed: aq=%d\n",
5190 pf->hw.aq.asq_last_status);
5191 return -ENODEV;
5192 }
5193 } while (err);
5194
d0b10249
JB		 5195 /* increment MSI-X count because current FW skips one */
5196 pf->hw.func_caps.num_msix_vectors++;
7134f9ce 5197
ac71b7ba
ASJ		 5198 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5199 (pf->hw.aq.fw_maj_ver < 2)) {
5200 pf->hw.func_caps.num_msix_vectors++;
5201 pf->hw.func_caps.num_msix_vectors_vf++;
5202 }
5203
41c445ff
JB		 5204 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5205 dev_info(&pf->pdev->dev,
5206 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5207 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5208 pf->hw.func_caps.num_msix_vectors,
5209 pf->hw.func_caps.num_msix_vectors_vf,
5210 pf->hw.func_caps.fd_filters_guaranteed,
5211 pf->hw.func_caps.fd_filters_best_effort,
5212 pf->hw.func_caps.num_tx_qp,
5213 pf->hw.func_caps.num_vsis);
5214
7134f9ce
JB		 5215#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5216 + pf->hw.func_caps.num_vfs)
5217 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5218 dev_info(&pf->pdev->dev,
5219 "got num_vsis %d, setting num_vsis to %d\n",
5220 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5221 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5222 }
5223
41c445ff
JB		 5224 return 0;
5225}
5226
cbf61325
ASJ		 5227static int i40e_vsi_clear(struct i40e_vsi *vsi);
5228
41c445ff 5229/**
cbf61325 5230 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5231 * @pf: board private structure
5232 **/
cbf61325 5233static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5234{
5235 struct i40e_vsi *vsi;
5236 bool new_vsi = false;
5237 int err, i;
5238
cbf61325 5239 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5240 return;
5241
cbf61325 5242 /* find existing VSI and see if it needs configuring */
41c445ff 5243 vsi = NULL;
cbf61325
ASJ		 5244 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5245 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5246 vsi = pf->vsi[i];
cbf61325
ASJ		 5247 break;
5248 }
5249 }
5250
5251 /* create a new VSI if none exists */
41c445ff 5252 if (!vsi) {
cbf61325
ASJ		 5253 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5254 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5255 if (!vsi) {
5256 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
cbf61325 5257 goto err_vsi;
41c445ff
JB		 5258 }
5259 new_vsi = true;
5260 }
cbf61325 5261 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5262
5263 err = i40e_vsi_setup_tx_resources(vsi);
cbf61325
ASJ		 5264 if (err)
5265 goto err_setup_tx;
5266 err = i40e_vsi_setup_rx_resources(vsi);
5267 if (err)
5268 goto err_setup_rx;
5269
5270 if (new_vsi) {
41c445ff 5271 char int_name[IFNAMSIZ + 9];
cbf61325
ASJ		 5272 err = i40e_vsi_configure(vsi);
5273 if (err)
5274 goto err_setup_rx;
41c445ff
JB		 5275 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
5276 dev_driver_string(&pf->pdev->dev));
5277 err = i40e_vsi_request_irq(vsi, int_name);
cbf61325
ASJ		 5278 if (err)
5279 goto err_setup_rx;
41c445ff 5280 err = i40e_up_complete(vsi);
cbf61325
ASJ		 5281 if (err)
5282 goto err_up_complete;
17a73f6b 5283 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
cbf61325 5284 }
41c445ff 5285
cbf61325
ASJ		 5286 return;
5287
5288err_up_complete:
5289 i40e_down(vsi);
5290 i40e_vsi_free_irq(vsi);
5291err_setup_rx:
5292 i40e_vsi_free_rx_resources(vsi);
5293err_setup_tx:
5294 i40e_vsi_free_tx_resources(vsi);
5295err_vsi:
5296 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5297 i40e_vsi_clear(vsi);
41c445ff
JB		 5298}
5299
5300/**
5301 * i40e_fdir_teardown - release the Flow Director resources
5302 * @pf: board private structure
5303 **/
5304static void i40e_fdir_teardown(struct i40e_pf *pf)
5305{
5306 int i;
5307
17a73f6b 5308 i40e_fdir_filter_exit(pf);
41c445ff
JB		 5309 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5310 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5311 i40e_vsi_release(pf->vsi[i]);
5312 break;
5313 }
5314 }
5315}
5316
5317/**
f650a38b 5318 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5319 * @pf: board private structure
5320 *
f650a38b
ASJ		 5321 * Close up the VFs and other things in prep for pf Reset.
5322 **/
5323static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5324{
41c445ff
JB		 5325 struct i40e_hw *hw = &pf->hw;
5326 i40e_status ret;
5327 u32 v;
5328
5329 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5330 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5331 return 0;
41c445ff 5332
69bfb110 5333 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5334
37f0be6d
ASJ		 5335 if (i40e_check_asq_alive(hw))
5336 i40e_vc_notify_reset(pf);
41c445ff
JB		 5337
5338 /* quiesce the VSIs and their queues that are not already DOWN */
5339 i40e_pf_quiesce_all_vsi(pf);
5340
5341 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5342 if (pf->vsi[v])
5343 pf->vsi[v]->seid = 0;
5344 }
5345
5346 i40e_shutdown_adminq(&pf->hw);
5347
f650a38b
ASJ		 5348 /* call shutdown HMC */
5349 ret = i40e_shutdown_lan_hmc(hw);
5350 if (ret) {
5351 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
5352 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5353 }
5354 return ret;
5355}
5356
5357/**
4dda12e6 5358 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5359 * @pf: board private structure
bc7d338f 5360 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5361 **/
bc7d338f 5362static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 5363{
5364 struct i40e_driver_version dv;
5365 struct i40e_hw *hw = &pf->hw;
5366 i40e_status ret;
5367 u32 v;
5368
41c445ff
JB		 5369 /* Now we wait for GRST to settle out.
5370 * We don't have to delete the VEBs or VSIs from the hw switch
5371 * because the reset will make them disappear.
5372 */
5373 ret = i40e_pf_reset(hw);
5374 if (ret)
5375 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
5376 pf->pfr_count++;
5377
5378 if (test_bit(__I40E_DOWN, &pf->state))
5379 goto end_core_reset;
69bfb110 5380 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5381
5382 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5383 ret = i40e_init_adminq(&pf->hw);
5384 if (ret) {
5385 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5386 goto end_core_reset;
5387 }
5388
5389 ret = i40e_get_capabilities(pf);
5390 if (ret) {
5391 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5392 ret);
5393 goto end_core_reset;
5394 }
5395
41c445ff
JB		 5396 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5397 hw->func_caps.num_rx_qp,
5398 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5399 if (ret) {
5400 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5401 goto end_core_reset;
5402 }
5403 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5404 if (ret) {
5405 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5406 goto end_core_reset;
5407 }
5408
4e3b35b0
NP		 5409#ifdef CONFIG_I40E_DCB
5410 ret = i40e_init_pf_dcb(pf);
5411 if (ret) {
5412 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5413 goto end_core_reset;
5414 }
5415#endif /* CONFIG_I40E_DCB */
5416
41c445ff 5417 /* do basic switch setup */
bc7d338f 5418 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5419 if (ret)
5420 goto end_core_reset;
5421
5422 /* Rebuild the VSIs and VEBs that existed before reset.
5423 * They are still in our local switch element arrays, so only
5424 * need to rebuild the switch model in the HW.
5425 *
5426 * If there were VEBs but the reconstitution failed, we'll try
5427 * try to recover minimal use by getting the basic PF VSI working.
5428 */
5429 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5430 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5431 /* find the one VEB connected to the MAC, and find orphans */
5432 for (v = 0; v < I40E_MAX_VEB; v++) {
5433 if (!pf->veb[v])
5434 continue;
5435
5436 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5437 pf->veb[v]->uplink_seid == 0) {
5438 ret = i40e_reconstitute_veb(pf->veb[v]);
5439
5440 if (!ret)
5441 continue;
5442
5443 /* If Main VEB failed, we're in deep doodoo,
5444 * so give up rebuilding the switch and set up
5445 * for minimal rebuild of PF VSI.
5446 * If orphan failed, we'll report the error
5447 * but try to keep going.
5448 */
5449 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5450 dev_info(&pf->pdev->dev,
5451 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5452 ret);
5453 pf->vsi[pf->lan_vsi]->uplink_seid
5454 = pf->mac_seid;
5455 break;
5456 } else if (pf->veb[v]->uplink_seid == 0) {
5457 dev_info(&pf->pdev->dev,
5458 "rebuild of orphan VEB failed: %d\n",
5459 ret);
5460 }
5461 }
5462 }
5463 }
5464
5465 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5466 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5467 /* no VEB, so rebuild only the Main VSI */
5468 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5469 if (ret) {
5470 dev_info(&pf->pdev->dev,
5471 "rebuild of Main VSI failed: %d\n", ret);
5472 goto end_core_reset;
5473 }
5474 }
5475
5476 /* reinit the misc interrupt */
5477 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5478 ret = i40e_setup_misc_vector(pf);
5479
5480 /* restart the VSIs that were rebuilt and running before the reset */
5481 i40e_pf_unquiesce_all_vsi(pf);
5482
69f64b2b
MW		 5483 if (pf->num_alloc_vfs) {
5484 for (v = 0; v < pf->num_alloc_vfs; v++)
5485 i40e_reset_vf(&pf->vf[v], true);
5486 }
5487
41c445ff
JB		 5488 /* tell the firmware that we're starting */
5489 dv.major_version = DRV_VERSION_MAJOR;
5490 dv.minor_version = DRV_VERSION_MINOR;
5491 dv.build_version = DRV_VERSION_BUILD;
5492 dv.subbuild_version = 0;
5493 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5494
69bfb110 5495 dev_info(&pf->pdev->dev, "reset complete\n");
41c445ff
JB		 5496
5497end_core_reset:
5498 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5499}
5500
f650a38b
ASJ		 5501/**
5502 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5503 * @pf: board private structure
5504 *
5505 * Close up the VFs and other things in prep for a Core Reset,
5506 * then get ready to rebuild the world.
5507 **/
5508static void i40e_handle_reset_warning(struct i40e_pf *pf)
5509{
5510 i40e_status ret;
5511
5512 ret = i40e_prep_for_reset(pf);
5513 if (!ret)
bc7d338f 5514 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5515}
5516
41c445ff
JB		 5517/**
5518 * i40e_handle_mdd_event
5519 * @pf: pointer to the pf structure
5520 *
5521 * Called from the MDD irq handler to identify possibly malicious vfs
5522 **/
5523static void i40e_handle_mdd_event(struct i40e_pf *pf)
5524{
5525 struct i40e_hw *hw = &pf->hw;
5526 bool mdd_detected = false;
5527 struct i40e_vf *vf;
5528 u32 reg;
5529 int i;
5530
5531 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5532 return;
5533
5534 /* find what triggered the MDD event */
5535 reg = rd32(hw, I40E_GL_MDET_TX);
5536 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5537 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5538 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5539 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5540 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5541 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5542 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5543 dev_info(&pf->pdev->dev,
f29eaa3d 5544 "Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n",
41c445ff
JB		 5545 event, queue, func);
5546 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5547 mdd_detected = true;
5548 }
5549 reg = rd32(hw, I40E_GL_MDET_RX);
5550 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5551 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5552 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5553 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5554 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5555 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5556 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5557 dev_info(&pf->pdev->dev,
f29eaa3d 5558 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5559 event, queue, func);
5560 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5561 mdd_detected = true;
5562 }
5563
5564 /* see if one of the VFs needs its hand slapped */
5565 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5566 vf = &(pf->vf[i]);
5567 reg = rd32(hw, I40E_VP_MDET_TX(i));
5568 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5569 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5570 vf->num_mdd_events++;
5571 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5572 }
5573
5574 reg = rd32(hw, I40E_VP_MDET_RX(i));
5575 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5576 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5577 vf->num_mdd_events++;
5578 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5579 }
5580
5581 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5582 dev_info(&pf->pdev->dev,
5583 "Too many MDD events on VF %d, disabled\n", i);
5584 dev_info(&pf->pdev->dev,
5585 "Use PF Control I/F to re-enable the VF\n");
5586 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5587 }
5588 }
5589
5590 /* re-enable mdd interrupt cause */
5591 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5592 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5593 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5594 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5595 i40e_flush(hw);
5596}
5597
a1c9a9d9
JK		 5598#ifdef CONFIG_I40E_VXLAN
5599/**
5600 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5601 * @pf: board private structure
5602 **/
5603static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5604{
5605 const int vxlan_hdr_qwords = 4;
5606 struct i40e_hw *hw = &pf->hw;
5607 i40e_status ret;
5608 u8 filter_index;
5609 __be16 port;
5610 int i;
5611
5612 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5613 return;
5614
5615 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5616
5617 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5618 if (pf->pending_vxlan_bitmap & (1 << i)) {
5619 pf->pending_vxlan_bitmap &= ~(1 << i);
5620 port = pf->vxlan_ports[i];
5621 ret = port ?
5622 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5623 vxlan_hdr_qwords,
5624 I40E_AQC_TUNNEL_TYPE_VXLAN,
5625 &filter_index, NULL)
5626 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5627
5628 if (ret) {
5629 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5630 port ? "adding" : "deleting",
5631 ntohs(port), port ? i : i);
5632
5633 pf->vxlan_ports[i] = 0;
5634 } else {
5635 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5636 port ? "Added" : "Deleted",
5637 ntohs(port), port ? i : filter_index);
5638 }
5639 }
5640 }
5641}
5642
5643#endif
41c445ff
JB		 5644/**
5645 * i40e_service_task - Run the driver's async subtasks
5646 * @work: pointer to work_struct containing our data
5647 **/
5648static void i40e_service_task(struct work_struct *work)
5649{
5650 struct i40e_pf *pf = container_of(work,
5651 struct i40e_pf,
5652 service_task);
5653 unsigned long start_time = jiffies;
5654
5655 i40e_reset_subtask(pf);
5656 i40e_handle_mdd_event(pf);
5657 i40e_vc_process_vflr_event(pf);
5658 i40e_watchdog_subtask(pf);
5659 i40e_fdir_reinit_subtask(pf);
5660 i40e_check_hang_subtask(pf);
5661 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5662#ifdef CONFIG_I40E_VXLAN
5663 i40e_sync_vxlan_filters_subtask(pf);
5664#endif
41c445ff
JB		 5665 i40e_clean_adminq_subtask(pf);
5666
5667 i40e_service_event_complete(pf);
5668
5669 /* If the tasks have taken longer than one timer cycle or there
5670 * is more work to be done, reschedule the service task now
5671 * rather than wait for the timer to tick again.
5672 */
5673 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5674 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5675 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5676 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5677 i40e_service_event_schedule(pf);
5678}
5679
5680/**
5681 * i40e_service_timer - timer callback
5682 * @data: pointer to PF struct
5683 **/
5684static void i40e_service_timer(unsigned long data)
5685{
5686 struct i40e_pf *pf = (struct i40e_pf *)data;
5687
5688 mod_timer(&pf->service_timer,
5689 round_jiffies(jiffies + pf->service_timer_period));
5690 i40e_service_event_schedule(pf);
5691}
5692
5693/**
5694 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5695 * @vsi: the VSI being configured
5696 **/
5697static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5698{
5699 struct i40e_pf *pf = vsi->back;
5700
5701 switch (vsi->type) {
5702 case I40E_VSI_MAIN:
5703 vsi->alloc_queue_pairs = pf->num_lan_qps;
5704 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5705 I40E_REQ_DESCRIPTOR_MULTIPLE);
5706 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5707 vsi->num_q_vectors = pf->num_lan_msix;
5708 else
5709 vsi->num_q_vectors = 1;
5710
5711 break;
5712
5713 case I40E_VSI_FDIR:
5714 vsi->alloc_queue_pairs = 1;
5715 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5716 I40E_REQ_DESCRIPTOR_MULTIPLE);
5717 vsi->num_q_vectors = 1;
5718 break;
5719
5720 case I40E_VSI_VMDQ2:
5721 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5722 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5723 I40E_REQ_DESCRIPTOR_MULTIPLE);
5724 vsi->num_q_vectors = pf->num_vmdq_msix;
5725 break;
5726
5727 case I40E_VSI_SRIOV:
5728 vsi->alloc_queue_pairs = pf->num_vf_qps;
5729 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5730 I40E_REQ_DESCRIPTOR_MULTIPLE);
5731 break;
5732
5733 default:
5734 WARN_ON(1);
5735 return -ENODATA;
5736 }
5737
5738 return 0;
5739}
5740
f650a38b
ASJ		 5741/**
5742 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5743 * @type: VSI pointer
bc7d338f 5744 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5745 *
5746 * On error: returns error code (negative)
5747 * On success: returns 0
5748 **/
bc7d338f 5749static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5750{
5751 int size;
5752 int ret = 0;
5753
ac6c5e3d 5754 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5755 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5756 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5757 if (!vsi->tx_rings)
5758 return -ENOMEM;
f650a38b
ASJ		 5759 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5760
bc7d338f
ASJ		 5761 if (alloc_qvectors) {
5762 /* allocate memory for q_vector pointers */
5763 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5764 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5765 if (!vsi->q_vectors) {
5766 ret = -ENOMEM;
5767 goto err_vectors;
5768 }
f650a38b
ASJ		 5769 }
5770 return ret;
5771
5772err_vectors:
5773 kfree(vsi->tx_rings);
5774 return ret;
5775}
5776
41c445ff
JB		 5777/**
5778 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5779 * @pf: board private structure
5780 * @type: type of VSI
5781 *
5782 * On error: returns error code (negative)
5783 * On success: returns vsi index in PF (positive)
5784 **/
5785static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5786{
5787 int ret = -ENODEV;
5788 struct i40e_vsi *vsi;
5789 int vsi_idx;
5790 int i;
5791
5792 /* Need to protect the allocation of the VSIs at the PF level */
5793 mutex_lock(&pf->switch_mutex);
5794
5795 /* VSI list may be fragmented if VSI creation/destruction has
5796 * been happening. We can afford to do a quick scan to look
5797 * for any free VSIs in the list.
5798 *
5799 * find next empty vsi slot, looping back around if necessary
5800 */
5801 i = pf->next_vsi;
5802 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5803 i++;
5804 if (i >= pf->hw.func_caps.num_vsis) {
5805 i = 0;
5806 while (i < pf->next_vsi && pf->vsi[i])
5807 i++;
5808 }
5809
5810 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5811 vsi_idx = i; /* Found one! */
5812 } else {
5813 ret = -ENODEV;
493fb300 5814 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5815 }
5816 pf->next_vsi = ++i;
5817
5818 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5819 if (!vsi) {
5820 ret = -ENOMEM;
493fb300 5821 goto unlock_pf;
41c445ff
JB		 5822 }
5823 vsi->type = type;
5824 vsi->back = pf;
5825 set_bit(__I40E_DOWN, &vsi->state);
5826 vsi->flags = 0;
5827 vsi->idx = vsi_idx;
5828 vsi->rx_itr_setting = pf->rx_itr_default;
5829 vsi->tx_itr_setting = pf->tx_itr_default;
5830 vsi->netdev_registered = false;
5831 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5832 INIT_LIST_HEAD(&vsi->mac_filter_list);
5833
9f65e15b
AD		 5834 ret = i40e_set_num_rings_in_vsi(vsi);
5835 if (ret)
5836 goto err_rings;
5837
bc7d338f 5838 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5839 if (ret)
9f65e15b 5840 goto err_rings;
493fb300 5841
41c445ff
JB		 5842 /* Setup default MSIX irq handler for VSI */
5843 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5844
5845 pf->vsi[vsi_idx] = vsi;
5846 ret = vsi_idx;
493fb300
AD		 5847 goto unlock_pf;
5848
9f65e15b 5849err_rings:
493fb300
AD		 5850 pf->next_vsi = i - 1;
5851 kfree(vsi);
5852unlock_pf:
41c445ff
JB		 5853 mutex_unlock(&pf->switch_mutex);
5854 return ret;
5855}
5856
f650a38b
ASJ		 5857/**
5858 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5859 * @type: VSI pointer
bc7d338f 5860 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5861 *
5862 * On error: returns error code (negative)
5863 * On success: returns 0
5864 **/
bc7d338f 5865static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5866{
5867 /* free the ring and vector containers */
bc7d338f
ASJ		 5868 if (free_qvectors) {
5869 kfree(vsi->q_vectors);
5870 vsi->q_vectors = NULL;
5871 }
f650a38b
ASJ		 5872 kfree(vsi->tx_rings);
5873 vsi->tx_rings = NULL;
5874 vsi->rx_rings = NULL;
5875}
5876
41c445ff
JB		 5877/**
5878 * i40e_vsi_clear - Deallocate the VSI provided
5879 * @vsi: the VSI being un-configured
5880 **/
5881static int i40e_vsi_clear(struct i40e_vsi *vsi)
5882{
5883 struct i40e_pf *pf;
5884
5885 if (!vsi)
5886 return 0;
5887
5888 if (!vsi->back)
5889 goto free_vsi;
5890 pf = vsi->back;
5891
5892 mutex_lock(&pf->switch_mutex);
5893 if (!pf->vsi[vsi->idx]) {
5894 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5895 vsi->idx, vsi->idx, vsi, vsi->type);
5896 goto unlock_vsi;
5897 }
5898
5899 if (pf->vsi[vsi->idx] != vsi) {
5900 dev_err(&pf->pdev->dev,
5901 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5902 pf->vsi[vsi->idx]->idx,
5903 pf->vsi[vsi->idx],
5904 pf->vsi[vsi->idx]->type,
5905 vsi->idx, vsi, vsi->type);
5906 goto unlock_vsi;
5907 }
5908
5909 /* updates the pf for this cleared vsi */
5910 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5911 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5912
bc7d338f 5913 i40e_vsi_free_arrays(vsi, true);
493fb300 5914
41c445ff
JB		 5915 pf->vsi[vsi->idx] = NULL;
5916 if (vsi->idx < pf->next_vsi)
5917 pf->next_vsi = vsi->idx;
5918
5919unlock_vsi:
5920 mutex_unlock(&pf->switch_mutex);
5921free_vsi:
5922 kfree(vsi);
5923
5924 return 0;
5925}
5926
9f65e15b
AD		 5927/**
5928 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5929 * @vsi: the VSI being cleaned
5930 **/
be1d5eea 5931static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5932{
5933 int i;
5934
8e9dca53 5935 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5936 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5937 kfree_rcu(vsi->tx_rings[i], rcu);
5938 vsi->tx_rings[i] = NULL;
5939 vsi->rx_rings[i] = NULL;
5940 }
be1d5eea 5941 }
9f65e15b
AD		 5942}
5943
41c445ff
JB		 5944/**
5945 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5946 * @vsi: the VSI being configured
5947 **/
5948static int i40e_alloc_rings(struct i40e_vsi *vsi)
5949{
5950 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5951 int i;
5952
41c445ff 5953 /* Set basic values in the rings to be used later during open() */
d7397644 5954 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5955 struct i40e_ring *tx_ring;
5956 struct i40e_ring *rx_ring;
5957
ac6c5e3d 5958 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5959 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5960 if (!tx_ring)
5961 goto err_out;
41c445ff
JB		 5962
5963 tx_ring->queue_index = i;
5964 tx_ring->reg_idx = vsi->base_queue + i;
5965 tx_ring->ring_active = false;
5966 tx_ring->vsi = vsi;
5967 tx_ring->netdev = vsi->netdev;
5968 tx_ring->dev = &pf->pdev->dev;
5969 tx_ring->count = vsi->num_desc;
5970 tx_ring->size = 0;
5971 tx_ring->dcb_tc = 0;
9f65e15b 5972 vsi->tx_rings[i] = tx_ring;
41c445ff 5973
9f65e15b 5974 rx_ring = &tx_ring[1];
41c445ff
JB		 5975 rx_ring->queue_index = i;
5976 rx_ring->reg_idx = vsi->base_queue + i;
5977 rx_ring->ring_active = false;
5978 rx_ring->vsi = vsi;
5979 rx_ring->netdev = vsi->netdev;
5980 rx_ring->dev = &pf->pdev->dev;
5981 rx_ring->count = vsi->num_desc;
5982 rx_ring->size = 0;
5983 rx_ring->dcb_tc = 0;
5984 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5985 set_ring_16byte_desc_enabled(rx_ring);
5986 else
5987 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5988 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5989 }
5990
5991 return 0;
9f65e15b
AD		 5992
5993err_out:
5994 i40e_vsi_clear_rings(vsi);
5995 return -ENOMEM;
41c445ff
JB		 5996}
5997
5998/**
5999 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6000 * @pf: board private structure
6001 * @vectors: the number of MSI-X vectors to request
6002 *
6003 * Returns the number of vectors reserved, or error
6004 **/
6005static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6006{
7b37f376
AG		 6007 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6008 I40E_MIN_MSIX, vectors);
6009 if (vectors < 0) {
41c445ff 6010 dev_info(&pf->pdev->dev,
7b37f376 6011 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6012 vectors = 0;
6013 }
6014
7b37f376
AG		 6015 pf->num_msix_entries = vectors;
6016
41c445ff
JB		 6017 return vectors;
6018}
6019
6020/**
6021 * i40e_init_msix - Setup the MSIX capability
6022 * @pf: board private structure
6023 *
6024 * Work with the OS to set up the MSIX vectors needed.
6025 *
6026 * Returns 0 on success, negative on failure
6027 **/
6028static int i40e_init_msix(struct i40e_pf *pf)
6029{
6030 i40e_status err = 0;
6031 struct i40e_hw *hw = &pf->hw;
6032 int v_budget, i;
6033 int vec;
6034
6035 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6036 return -ENODEV;
6037
6038 /* The number of vectors we'll request will be comprised of:
6039 * - Add 1 for "other" cause for Admin Queue events, etc.
6040 * - The number of LAN queue pairs
f8ff1464
ASJ		 6041 * - Queues being used for RSS.
6042 * We don't need as many as max_rss_size vectors.
6043 * use rss_size instead in the calculation since that
6044 * is governed by number of cpus in the system.
6045 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6046 * - The number of VMDq pairs
6047 * Once we count this up, try the request.
6048 *
6049 * If we can't get what we want, we'll simplify to nearly nothing
6050 * and try again. If that still fails, we punt.
6051 */
f8ff1464 6052 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6053 pf->num_vmdq_msix = pf->num_vmdq_qps;
6054 v_budget = 1 + pf->num_lan_msix;
6055 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6056 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6057 v_budget++;
6058
6059 /* Scale down if necessary, and the rings will share vectors */
6060 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6061
6062 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6063 GFP_KERNEL);
6064 if (!pf->msix_entries)
6065 return -ENOMEM;
6066
6067 for (i = 0; i < v_budget; i++)
6068 pf->msix_entries[i].entry = i;
6069 vec = i40e_reserve_msix_vectors(pf, v_budget);
6070 if (vec < I40E_MIN_MSIX) {
6071 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6072 kfree(pf->msix_entries);
6073 pf->msix_entries = NULL;
6074 return -ENODEV;
6075
6076 } else if (vec == I40E_MIN_MSIX) {
6077 /* Adjust for minimal MSIX use */
77fa28be 6078 dev_info(&pf->pdev->dev, "Features disabled, not enough MSI-X vectors\n");
41c445ff
JB		 6079 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6080 pf->num_vmdq_vsis = 0;
6081 pf->num_vmdq_qps = 0;
6082 pf->num_vmdq_msix = 0;
6083 pf->num_lan_qps = 1;
6084 pf->num_lan_msix = 1;
6085
6086 } else if (vec != v_budget) {
6087 /* Scale vector usage down */
6088 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
6089 vec--; /* reserve the misc vector */
6090
6091 /* partition out the remaining vectors */
6092 switch (vec) {
6093 case 2:
6094 pf->num_vmdq_vsis = 1;
6095 pf->num_lan_msix = 1;
6096 break;
6097 case 3:
6098 pf->num_vmdq_vsis = 1;
6099 pf->num_lan_msix = 2;
6100 break;
6101 default:
6102 pf->num_lan_msix = min_t(int, (vec / 2),
6103 pf->num_lan_qps);
6104 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6105 I40E_DEFAULT_NUM_VMDQ_VSI);
6106 break;
6107 }
6108 }
6109
6110 return err;
6111}
6112
493fb300
AD		 6113/**
6114 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
6115 * @vsi: the VSI being configured
6116 * @v_idx: index of the vector in the vsi struct
6117 *
6118 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6119 **/
6120static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
6121{
6122 struct i40e_q_vector *q_vector;
6123
6124 /* allocate q_vector */
6125 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6126 if (!q_vector)
6127 return -ENOMEM;
6128
6129 q_vector->vsi = vsi;
6130 q_vector->v_idx = v_idx;
6131 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6132 if (vsi->netdev)
6133 netif_napi_add(vsi->netdev, &q_vector->napi,
6134 i40e_napi_poll, vsi->work_limit);
6135
cd0b6fa6
AD		 6136 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6137 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6138
493fb300
AD		 6139 /* tie q_vector and vsi together */
6140 vsi->q_vectors[v_idx] = q_vector;
6141
6142 return 0;
6143}
6144
41c445ff
JB		 6145/**
6146 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
6147 * @vsi: the VSI being configured
6148 *
6149 * We allocate one q_vector per queue interrupt. If allocation fails we
6150 * return -ENOMEM.
6151 **/
6152static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
6153{
6154 struct i40e_pf *pf = vsi->back;
6155 int v_idx, num_q_vectors;
493fb300 6156 int err;
41c445ff
JB		 6157
6158 /* if not MSIX, give the one vector only to the LAN VSI */
6159 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6160 num_q_vectors = vsi->num_q_vectors;
6161 else if (vsi == pf->vsi[pf->lan_vsi])
6162 num_q_vectors = 1;
6163 else
6164 return -EINVAL;
6165
41c445ff 6166 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 6167 err = i40e_alloc_q_vector(vsi, v_idx);
6168 if (err)
6169 goto err_out;
41c445ff
JB		 6170 }
6171
6172 return 0;
493fb300
AD		 6173
6174err_out:
6175 while (v_idx--)
6176 i40e_free_q_vector(vsi, v_idx);
6177
6178 return err;
41c445ff
JB		 6179}
6180
6181/**
6182 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6183 * @pf: board private structure to initialize
6184 **/
6185static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6186{
6187 int err = 0;
6188
6189 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6190 err = i40e_init_msix(pf);
6191 if (err) {
60ea5f83
JB		 6192 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6193 I40E_FLAG_RSS_ENABLED |
6194 I40E_FLAG_DCB_ENABLED |
6195 I40E_FLAG_SRIOV_ENABLED |
6196 I40E_FLAG_FD_SB_ENABLED |
6197 I40E_FLAG_FD_ATR_ENABLED |
6198 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6199
6200 /* rework the queue expectations without MSIX */
6201 i40e_determine_queue_usage(pf);
6202 }
6203 }
6204
6205 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6206 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6207 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6208 err = pci_enable_msi(pf->pdev);
6209 if (err) {
958a3e3b 6210 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6211 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6212 }
6213 }
6214
958a3e3b 6215 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6216 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6217
41c445ff
JB		 6218 /* track first vector for misc interrupts */
6219 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6220}
6221
6222/**
6223 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6224 * @pf: board private structure
6225 *
6226 * This sets up the handler for MSIX 0, which is used to manage the
6227 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6228 * when in MSI or Legacy interrupt mode.
6229 **/
6230static int i40e_setup_misc_vector(struct i40e_pf *pf)
6231{
6232 struct i40e_hw *hw = &pf->hw;
6233 int err = 0;
6234
6235 /* Only request the irq if this is the first time through, and
6236 * not when we're rebuilding after a Reset
6237 */
6238 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6239 err = request_irq(pf->msix_entries[0].vector,
6240 i40e_intr, 0, pf->misc_int_name, pf);
6241 if (err) {
6242 dev_info(&pf->pdev->dev,
77fa28be
CS		 6243 "request_irq for %s failed: %d\n",
6244 pf->misc_int_name, err);
41c445ff
JB		 6245 return -EFAULT;
6246 }
6247 }
6248
6249 i40e_enable_misc_int_causes(hw);
6250
6251 /* associate no queues to the misc vector */
6252 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6253 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6254
6255 i40e_flush(hw);
6256
6257 i40e_irq_dynamic_enable_icr0(pf);
6258
6259 return err;
6260}
6261
6262/**
6263 * i40e_config_rss - Prepare for RSS if used
6264 * @pf: board private structure
6265 **/
6266static int i40e_config_rss(struct i40e_pf *pf)
6267{
41c445ff
JB		 6268 /* Set of random keys generated using kernel random number generator */
6269 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6270 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6271 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6272 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6273 struct i40e_hw *hw = &pf->hw;
6274 u32 lut = 0;
6275 int i, j;
6276 u64 hena;
41c445ff
JB		 6277
6278 /* Fill out hash function seed */
6279 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6280 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6281
6282 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6283 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6284 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6285 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6286 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6287 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6288
6289 /* Populate the LUT with max no. of queues in round robin fashion */
6290 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6291
6292 /* The assumption is that lan qp count will be the highest
6293 * qp count for any PF VSI that needs RSS.
6294 * If multiple VSIs need RSS support, all the qp counts
6295 * for those VSIs should be a power of 2 for RSS to work.
6296 * If LAN VSI is the only consumer for RSS then this requirement
6297 * is not necessary.
6298 */
6299 if (j == pf->rss_size)
6300 j = 0;
6301 /* lut = 4-byte sliding window of 4 lut entries */
6302 lut = (lut << 8) | (j &
6303 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6304 /* On i = 3, we have 4 entries in lut; write to the register */
6305 if ((i & 3) == 3)
6306 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6307 }
6308 i40e_flush(hw);
6309
6310 return 0;
6311}
6312
f8ff1464
ASJ		 6313/**
6314 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6315 * @pf: board private structure
6316 * @queue_count: the requested queue count for rss.
6317 *
6318 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6319 * count which may be different from the requested queue count.
6320 **/
6321int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6322{
6323 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6324 return 0;
6325
6326 queue_count = min_t(int, queue_count, pf->rss_size_max);
6327 queue_count = rounddown_pow_of_two(queue_count);
6328
6329 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6330 i40e_prep_for_reset(pf);
6331
f8ff1464
ASJ		 6332 pf->rss_size = queue_count;
6333
6334 i40e_reset_and_rebuild(pf, true);
6335 i40e_config_rss(pf);
6336 }
6337 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6338 return pf->rss_size;
6339}
6340
41c445ff
JB		 6341/**
6342 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6343 * @pf: board private structure to initialize
6344 *
6345 * i40e_sw_init initializes the Adapter private data structure.
6346 * Fields are initialized based on PCI device information and
6347 * OS network device settings (MTU size).
6348 **/
6349static int i40e_sw_init(struct i40e_pf *pf)
6350{
6351 int err = 0;
6352 int size;
6353
6354 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6355 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6356 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6357 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6358 if (I40E_DEBUG_USER & debug)
6359 pf->hw.debug_mask = debug;
6360 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6361 I40E_DEFAULT_MSG_ENABLE);
6362 }
6363
6364 /* Set default capability flags */
6365 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6366 I40E_FLAG_MSI_ENABLED |
6367 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6368 I40E_FLAG_RX_1BUF_ENABLED;
6369
7134f9ce
JB		 6370 /* Depending on PF configurations, it is possible that the RSS
6371 * maximum might end up larger than the available queues
6372 */
41c445ff 6373 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6374 pf->rss_size_max = min_t(int, pf->rss_size_max,
6375 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6376 if (pf->hw.func_caps.rss) {
6377 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6378 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6379 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6380 } else {
6381 pf->rss_size = 1;
6382 }
6383
2050bc65
CS		 6384 /* MFP mode enabled */
6385 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6386 pf->flags |= I40E_FLAG_MFP_ENABLED;
6387 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6388 }
6389
cbf61325
ASJ		 6390 /* FW/NVM is not yet fixed in this regard */
6391 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6392 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6393 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6394 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 6395 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6396 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 6397 } else {
6398 dev_info(&pf->pdev->dev,
0b67584f 6399 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6400 }
cbf61325
ASJ		 6401 pf->fdir_pf_filter_count =
6402 pf->hw.func_caps.fd_filters_guaranteed;
6403 pf->hw.fdir_shared_filter_count =
6404 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6405 }
6406
6407 if (pf->hw.func_caps.vmdq) {
6408 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6409 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6410 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6411 }
6412
41c445ff
JB		 6413#ifdef CONFIG_PCI_IOV
6414 if (pf->hw.func_caps.num_vfs) {
6415 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6416 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6417 pf->num_req_vfs = min_t(int,
6418 pf->hw.func_caps.num_vfs,
6419 I40E_MAX_VF_COUNT);
6420 }
6421#endif /* CONFIG_PCI_IOV */
6422 pf->eeprom_version = 0xDEAD;
6423 pf->lan_veb = I40E_NO_VEB;
6424 pf->lan_vsi = I40E_NO_VSI;
6425
6426 /* set up queue assignment tracking */
6427 size = sizeof(struct i40e_lump_tracking)
6428 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6429 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6430 if (!pf->qp_pile) {
6431 err = -ENOMEM;
6432 goto sw_init_done;
6433 }
6434 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6435 pf->qp_pile->search_hint = 0;
6436
6437 /* set up vector assignment tracking */
6438 size = sizeof(struct i40e_lump_tracking)
6439 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6440 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6441 if (!pf->irq_pile) {
6442 kfree(pf->qp_pile);
6443 err = -ENOMEM;
6444 goto sw_init_done;
6445 }
6446 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6447 pf->irq_pile->search_hint = 0;
6448
6449 mutex_init(&pf->switch_mutex);
6450
6451sw_init_done:
6452 return err;
6453}
6454
7c3c288b
ASJ		 6455/**
6456 * i40e_set_ntuple - set the ntuple feature flag and take action
6457 * @pf: board private structure to initialize
6458 * @features: the feature set that the stack is suggesting
6459 *
6460 * returns a bool to indicate if reset needs to happen
6461 **/
6462bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6463{
6464 bool need_reset = false;
6465
6466 /* Check if Flow Director n-tuple support was enabled or disabled. If
6467 * the state changed, we need to reset.
6468 */
6469 if (features & NETIF_F_NTUPLE) {
6470 /* Enable filters and mark for reset */
6471 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6472 need_reset = true;
6473 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6474 } else {
6475 /* turn off filters, mark for reset and clear SW filter list */
6476 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6477 need_reset = true;
6478 i40e_fdir_filter_exit(pf);
6479 }
6480 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6481 /* if ATR was disabled it can be re-enabled. */
6482 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6483 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6484 }
6485 return need_reset;
6486}
6487
41c445ff
JB		 6488/**
6489 * i40e_set_features - set the netdev feature flags
6490 * @netdev: ptr to the netdev being adjusted
6491 * @features: the feature set that the stack is suggesting
6492 **/
6493static int i40e_set_features(struct net_device *netdev,
6494 netdev_features_t features)
6495{
6496 struct i40e_netdev_priv *np = netdev_priv(netdev);
6497 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6498 struct i40e_pf *pf = vsi->back;
6499 bool need_reset;
41c445ff
JB		 6500
6501 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6502 i40e_vlan_stripping_enable(vsi);
6503 else
6504 i40e_vlan_stripping_disable(vsi);
6505
7c3c288b
ASJ		 6506 need_reset = i40e_set_ntuple(pf, features);
6507
6508 if (need_reset)
6509 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6510
41c445ff
JB		 6511 return 0;
6512}
6513
a1c9a9d9
JK		 6514#ifdef CONFIG_I40E_VXLAN
6515/**
6516 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6517 * @pf: board private structure
6518 * @port: The UDP port to look up
6519 *
6520 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6521 **/
6522static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6523{
6524 u8 i;
6525
6526 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6527 if (pf->vxlan_ports[i] == port)
6528 return i;
6529 }
6530
6531 return i;
6532}
6533
6534/**
6535 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6536 * @netdev: This physical port's netdev
6537 * @sa_family: Socket Family that VXLAN is notifying us about
6538 * @port: New UDP port number that VXLAN started listening to
6539 **/
6540static void i40e_add_vxlan_port(struct net_device *netdev,
6541 sa_family_t sa_family, __be16 port)
6542{
6543 struct i40e_netdev_priv *np = netdev_priv(netdev);
6544 struct i40e_vsi *vsi = np->vsi;
6545 struct i40e_pf *pf = vsi->back;
6546 u8 next_idx;
6547 u8 idx;
6548
6549 if (sa_family == AF_INET6)
6550 return;
6551
6552 idx = i40e_get_vxlan_port_idx(pf, port);
6553
6554 /* Check if port already exists */
6555 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6556 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6557 return;
6558 }
6559
6560 /* Now check if there is space to add the new port */
6561 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6562
6563 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6564 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6565 ntohs(port));
6566 return;
6567 }
6568
6569 /* New port: add it and mark its index in the bitmap */
6570 pf->vxlan_ports[next_idx] = port;
6571 pf->pending_vxlan_bitmap |= (1 << next_idx);
6572
6573 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6574}
6575
6576/**
6577 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6578 * @netdev: This physical port's netdev
6579 * @sa_family: Socket Family that VXLAN is notifying us about
6580 * @port: UDP port number that VXLAN stopped listening to
6581 **/
6582static void i40e_del_vxlan_port(struct net_device *netdev,
6583 sa_family_t sa_family, __be16 port)
6584{
6585 struct i40e_netdev_priv *np = netdev_priv(netdev);
6586 struct i40e_vsi *vsi = np->vsi;
6587 struct i40e_pf *pf = vsi->back;
6588 u8 idx;
6589
6590 if (sa_family == AF_INET6)
6591 return;
6592
6593 idx = i40e_get_vxlan_port_idx(pf, port);
6594
6595 /* Check if port already exists */
6596 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6597 /* if port exists, set it to 0 (mark for deletion)
6598 * and make it pending
6599 */
6600 pf->vxlan_ports[idx] = 0;
6601
6602 pf->pending_vxlan_bitmap |= (1 << idx);
6603
6604 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6605 } else {
6606 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6607 ntohs(port));
6608 }
6609}
6610
6611#endif
41c445ff
JB		 6612static const struct net_device_ops i40e_netdev_ops = {
6613 .ndo_open = i40e_open,
6614 .ndo_stop = i40e_close,
6615 .ndo_start_xmit = i40e_lan_xmit_frame,
6616 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6617 .ndo_set_rx_mode = i40e_set_rx_mode,
6618 .ndo_validate_addr = eth_validate_addr,
6619 .ndo_set_mac_address = i40e_set_mac,
6620 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6621 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6622 .ndo_tx_timeout = i40e_tx_timeout,
6623 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6624 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6625#ifdef CONFIG_NET_POLL_CONTROLLER
6626 .ndo_poll_controller = i40e_netpoll,
6627#endif
6628 .ndo_setup_tc = i40e_setup_tc,
6629 .ndo_set_features = i40e_set_features,
6630 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6631 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6632 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6633 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 6634 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
a1c9a9d9
JK		 6635#ifdef CONFIG_I40E_VXLAN
6636 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6637 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6638#endif
41c445ff
JB		 6639};
6640
6641/**
6642 * i40e_config_netdev - Setup the netdev flags
6643 * @vsi: the VSI being configured
6644 *
6645 * Returns 0 on success, negative value on failure
6646 **/
6647static int i40e_config_netdev(struct i40e_vsi *vsi)
6648{
1a10370a 6649 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6650 struct i40e_pf *pf = vsi->back;
6651 struct i40e_hw *hw = &pf->hw;
6652 struct i40e_netdev_priv *np;
6653 struct net_device *netdev;
6654 u8 mac_addr[ETH_ALEN];
6655 int etherdev_size;
6656
6657 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6658 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6659 if (!netdev)
6660 return -ENOMEM;
6661
6662 vsi->netdev = netdev;
6663 np = netdev_priv(netdev);
6664 np->vsi = vsi;
6665
d70e941b 6666 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 6667 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 6668 NETIF_F_TSO;
41c445ff
JB		 6669
6670 netdev->features = NETIF_F_SG |
6671 NETIF_F_IP_CSUM |
6672 NETIF_F_SCTP_CSUM |
6673 NETIF_F_HIGHDMA |
6674 NETIF_F_GSO_UDP_TUNNEL |
6675 NETIF_F_HW_VLAN_CTAG_TX |
6676 NETIF_F_HW_VLAN_CTAG_RX |
6677 NETIF_F_HW_VLAN_CTAG_FILTER |
6678 NETIF_F_IPV6_CSUM |
6679 NETIF_F_TSO |
6680 NETIF_F_TSO6 |
6681 NETIF_F_RXCSUM |
7c3c288b 6682 NETIF_F_NTUPLE |
41c445ff
JB		 6683 NETIF_F_RXHASH |
6684 0;
6685
6686 /* copy netdev features into list of user selectable features */
6687 netdev->hw_features |= netdev->features;
6688
6689 if (vsi->type == I40E_VSI_MAIN) {
6690 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6691 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6692 } else {
6693 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6694 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6695 pf->vsi[pf->lan_vsi]->netdev->name);
6696 random_ether_addr(mac_addr);
6697 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6698 }
1a10370a 6699 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6700
6701 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6702 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6703 /* vlan gets same features (except vlan offload)
6704 * after any tweaks for specific VSI types
6705 */
6706 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6707 NETIF_F_HW_VLAN_CTAG_RX |
6708 NETIF_F_HW_VLAN_CTAG_FILTER);
6709 netdev->priv_flags |= IFF_UNICAST_FLT;
6710 netdev->priv_flags |= IFF_SUPP_NOFCS;
6711 /* Setup netdev TC information */
6712 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6713
6714 netdev->netdev_ops = &i40e_netdev_ops;
6715 netdev->watchdog_timeo = 5 * HZ;
6716 i40e_set_ethtool_ops(netdev);
6717
6718 return 0;
6719}
6720
6721/**
6722 * i40e_vsi_delete - Delete a VSI from the switch
6723 * @vsi: the VSI being removed
6724 *
6725 * Returns 0 on success, negative value on failure
6726 **/
6727static void i40e_vsi_delete(struct i40e_vsi *vsi)
6728{
6729 /* remove default VSI is not allowed */
6730 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6731 return;
6732
41c445ff
JB		 6733 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6734 return;
6735}
6736
6737/**
6738 * i40e_add_vsi - Add a VSI to the switch
6739 * @vsi: the VSI being configured
6740 *
6741 * This initializes a VSI context depending on the VSI type to be added and
6742 * passes it down to the add_vsi aq command.
6743 **/
6744static int i40e_add_vsi(struct i40e_vsi *vsi)
6745{
6746 int ret = -ENODEV;
6747 struct i40e_mac_filter *f, *ftmp;
6748 struct i40e_pf *pf = vsi->back;
6749 struct i40e_hw *hw = &pf->hw;
6750 struct i40e_vsi_context ctxt;
6751 u8 enabled_tc = 0x1; /* TC0 enabled */
6752 int f_count = 0;
6753
6754 memset(&ctxt, 0, sizeof(ctxt));
6755 switch (vsi->type) {
6756 case I40E_VSI_MAIN:
6757 /* The PF's main VSI is already setup as part of the
6758 * device initialization, so we'll not bother with
6759 * the add_vsi call, but we will retrieve the current
6760 * VSI context.
6761 */
6762 ctxt.seid = pf->main_vsi_seid;
6763 ctxt.pf_num = pf->hw.pf_id;
6764 ctxt.vf_num = 0;
6765 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6766 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6767 if (ret) {
6768 dev_info(&pf->pdev->dev,
6769 "couldn't get pf vsi config, err %d, aq_err %d\n",
6770 ret, pf->hw.aq.asq_last_status);
6771 return -ENOENT;
6772 }
6773 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6774 vsi->info.valid_sections = 0;
6775
6776 vsi->seid = ctxt.seid;
6777 vsi->id = ctxt.vsi_number;
6778
6779 enabled_tc = i40e_pf_get_tc_map(pf);
6780
6781 /* MFP mode setup queue map and update VSI */
6782 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6783 memset(&ctxt, 0, sizeof(ctxt));
6784 ctxt.seid = pf->main_vsi_seid;
6785 ctxt.pf_num = pf->hw.pf_id;
6786 ctxt.vf_num = 0;
6787 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6788 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6789 if (ret) {
6790 dev_info(&pf->pdev->dev,
6791 "update vsi failed, aq_err=%d\n",
6792 pf->hw.aq.asq_last_status);
6793 ret = -ENOENT;
6794 goto err;
6795 }
6796 /* update the local VSI info queue map */
6797 i40e_vsi_update_queue_map(vsi, &ctxt);
6798 vsi->info.valid_sections = 0;
6799 } else {
6800 /* Default/Main VSI is only enabled for TC0
6801 * reconfigure it to enable all TCs that are
6802 * available on the port in SFP mode.
6803 */
6804 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6805 if (ret) {
6806 dev_info(&pf->pdev->dev,
6807 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6808 enabled_tc, ret,
6809 pf->hw.aq.asq_last_status);
6810 ret = -ENOENT;
6811 }
6812 }
6813 break;
6814
6815 case I40E_VSI_FDIR:
cbf61325
ASJ		 6816 ctxt.pf_num = hw->pf_id;
6817 ctxt.vf_num = 0;
6818 ctxt.uplink_seid = vsi->uplink_seid;
6819 ctxt.connection_type = 0x1; /* regular data port */
6820 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 6821 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 6822 break;
6823
6824 case I40E_VSI_VMDQ2:
6825 ctxt.pf_num = hw->pf_id;
6826 ctxt.vf_num = 0;
6827 ctxt.uplink_seid = vsi->uplink_seid;
6828 ctxt.connection_type = 0x1; /* regular data port */
6829 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6830
6831 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6832
6833 /* This VSI is connected to VEB so the switch_id
6834 * should be set to zero by default.
6835 */
6836 ctxt.info.switch_id = 0;
6837 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6838 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6839
6840 /* Setup the VSI tx/rx queue map for TC0 only for now */
6841 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6842 break;
6843
6844 case I40E_VSI_SRIOV:
6845 ctxt.pf_num = hw->pf_id;
6846 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6847 ctxt.uplink_seid = vsi->uplink_seid;
6848 ctxt.connection_type = 0x1; /* regular data port */
6849 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6850
6851 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6852
6853 /* This VSI is connected to VEB so the switch_id
6854 * should be set to zero by default.
6855 */
6856 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6857
6858 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6859 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6860 /* Setup the VSI tx/rx queue map for TC0 only for now */
6861 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6862 break;
6863
6864 default:
6865 return -ENODEV;
6866 }
6867
6868 if (vsi->type != I40E_VSI_MAIN) {
6869 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6870 if (ret) {
6871 dev_info(&vsi->back->pdev->dev,
6872 "add vsi failed, aq_err=%d\n",
6873 vsi->back->hw.aq.asq_last_status);
6874 ret = -ENOENT;
6875 goto err;
6876 }
6877 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6878 vsi->info.valid_sections = 0;
6879 vsi->seid = ctxt.seid;
6880 vsi->id = ctxt.vsi_number;
6881 }
6882
6883 /* If macvlan filters already exist, force them to get loaded */
6884 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6885 f->changed = true;
6886 f_count++;
6887 }
6888 if (f_count) {
6889 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6890 pf->flags |= I40E_FLAG_FILTER_SYNC;
6891 }
6892
6893 /* Update VSI BW information */
6894 ret = i40e_vsi_get_bw_info(vsi);
6895 if (ret) {
6896 dev_info(&pf->pdev->dev,
6897 "couldn't get vsi bw info, err %d, aq_err %d\n",
6898 ret, pf->hw.aq.asq_last_status);
6899 /* VSI is already added so not tearing that up */
6900 ret = 0;
6901 }
6902
6903err:
6904 return ret;
6905}
6906
6907/**
6908 * i40e_vsi_release - Delete a VSI and free its resources
6909 * @vsi: the VSI being removed
6910 *
6911 * Returns 0 on success or < 0 on error
6912 **/
6913int i40e_vsi_release(struct i40e_vsi *vsi)
6914{
6915 struct i40e_mac_filter *f, *ftmp;
6916 struct i40e_veb *veb = NULL;
6917 struct i40e_pf *pf;
6918 u16 uplink_seid;
6919 int i, n;
6920
6921 pf = vsi->back;
6922
6923 /* release of a VEB-owner or last VSI is not allowed */
6924 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6925 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6926 vsi->seid, vsi->uplink_seid);
6927 return -ENODEV;
6928 }
6929 if (vsi == pf->vsi[pf->lan_vsi] &&
6930 !test_bit(__I40E_DOWN, &pf->state)) {
6931 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6932 return -ENODEV;
6933 }
6934
6935 uplink_seid = vsi->uplink_seid;
6936 if (vsi->type != I40E_VSI_SRIOV) {
6937 if (vsi->netdev_registered) {
6938 vsi->netdev_registered = false;
6939 if (vsi->netdev) {
6940 /* results in a call to i40e_close() */
6941 unregister_netdev(vsi->netdev);
41c445ff
JB		 6942 }
6943 } else {
6944 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6945 i40e_down(vsi);
6946 i40e_vsi_free_irq(vsi);
6947 i40e_vsi_free_tx_resources(vsi);
6948 i40e_vsi_free_rx_resources(vsi);
6949 }
6950 i40e_vsi_disable_irq(vsi);
6951 }
6952
6953 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6954 i40e_del_filter(vsi, f->macaddr, f->vlan,
6955 f->is_vf, f->is_netdev);
6956 i40e_sync_vsi_filters(vsi);
6957
6958 i40e_vsi_delete(vsi);
6959 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 6960 if (vsi->netdev) {
6961 free_netdev(vsi->netdev);
6962 vsi->netdev = NULL;
6963 }
41c445ff
JB		 6964 i40e_vsi_clear_rings(vsi);
6965 i40e_vsi_clear(vsi);
6966
6967 /* If this was the last thing on the VEB, except for the
6968 * controlling VSI, remove the VEB, which puts the controlling
6969 * VSI onto the next level down in the switch.
6970 *
6971 * Well, okay, there's one more exception here: don't remove
6972 * the orphan VEBs yet. We'll wait for an explicit remove request
6973 * from up the network stack.
6974 */
6975 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6976 if (pf->vsi[i] &&
6977 pf->vsi[i]->uplink_seid == uplink_seid &&
6978 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6979 n++; /* count the VSIs */
6980 }
6981 }
6982 for (i = 0; i < I40E_MAX_VEB; i++) {
6983 if (!pf->veb[i])
6984 continue;
6985 if (pf->veb[i]->uplink_seid == uplink_seid)
6986 n++; /* count the VEBs */
6987 if (pf->veb[i]->seid == uplink_seid)
6988 veb = pf->veb[i];
6989 }
6990 if (n == 0 && veb && veb->uplink_seid != 0)
6991 i40e_veb_release(veb);
6992
6993 return 0;
6994}
6995
6996/**
6997 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6998 * @vsi: ptr to the VSI
6999 *
7000 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7001 * corresponding SW VSI structure and initializes num_queue_pairs for the
7002 * newly allocated VSI.
7003 *
7004 * Returns 0 on success or negative on failure
7005 **/
7006static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7007{
7008 int ret = -ENOENT;
7009 struct i40e_pf *pf = vsi->back;
7010
493fb300 7011 if (vsi->q_vectors[0]) {
41c445ff
JB		 7012 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7013 vsi->seid);
7014 return -EEXIST;
7015 }
7016
7017 if (vsi->base_vector) {
f29eaa3d 7018 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7019 vsi->seid, vsi->base_vector);
7020 return -EEXIST;
7021 }
7022
7023 ret = i40e_alloc_q_vectors(vsi);
7024 if (ret) {
7025 dev_info(&pf->pdev->dev,
7026 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7027 vsi->num_q_vectors, vsi->seid, ret);
7028 vsi->num_q_vectors = 0;
7029 goto vector_setup_out;
7030 }
7031
958a3e3b
SN		 7032 if (vsi->num_q_vectors)
7033 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7034 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7035 if (vsi->base_vector < 0) {
7036 dev_info(&pf->pdev->dev,
f29eaa3d 7037 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7038 vsi->seid, vsi->base_vector);
7039 i40e_vsi_free_q_vectors(vsi);
7040 ret = -ENOENT;
7041 goto vector_setup_out;
7042 }
7043
7044vector_setup_out:
7045 return ret;
7046}
7047
bc7d338f
ASJ		 7048/**
7049 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7050 * @vsi: pointer to the vsi.
7051 *
7052 * This re-allocates a vsi's queue resources.
7053 *
7054 * Returns pointer to the successfully allocated and configured VSI sw struct
7055 * on success, otherwise returns NULL on failure.
7056 **/
7057static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7058{
7059 struct i40e_pf *pf = vsi->back;
7060 u8 enabled_tc;
7061 int ret;
7062
7063 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7064 i40e_vsi_clear_rings(vsi);
7065
7066 i40e_vsi_free_arrays(vsi, false);
7067 i40e_set_num_rings_in_vsi(vsi);
7068 ret = i40e_vsi_alloc_arrays(vsi, false);
7069 if (ret)
7070 goto err_vsi;
7071
7072 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7073 if (ret < 0) {
7074 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7075 vsi->seid, ret);
7076 goto err_vsi;
7077 }
7078 vsi->base_queue = ret;
7079
7080 /* Update the FW view of the VSI. Force a reset of TC and queue
7081 * layout configurations.
7082 */
7083 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7084 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7085 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7086 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7087
7088 /* assign it some queues */
7089 ret = i40e_alloc_rings(vsi);
7090 if (ret)
7091 goto err_rings;
7092
7093 /* map all of the rings to the q_vectors */
7094 i40e_vsi_map_rings_to_vectors(vsi);
7095 return vsi;
7096
7097err_rings:
7098 i40e_vsi_free_q_vectors(vsi);
7099 if (vsi->netdev_registered) {
7100 vsi->netdev_registered = false;
7101 unregister_netdev(vsi->netdev);
7102 free_netdev(vsi->netdev);
7103 vsi->netdev = NULL;
7104 }
7105 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7106err_vsi:
7107 i40e_vsi_clear(vsi);
7108 return NULL;
7109}
7110
41c445ff
JB		 7111/**
7112 * i40e_vsi_setup - Set up a VSI by a given type
7113 * @pf: board private structure
7114 * @type: VSI type
7115 * @uplink_seid: the switch element to link to
7116 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7117 *
7118 * This allocates the sw VSI structure and its queue resources, then add a VSI
7119 * to the identified VEB.
7120 *
7121 * Returns pointer to the successfully allocated and configure VSI sw struct on
7122 * success, otherwise returns NULL on failure.
7123 **/
7124struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7125 u16 uplink_seid, u32 param1)
7126{
7127 struct i40e_vsi *vsi = NULL;
7128 struct i40e_veb *veb = NULL;
7129 int ret, i;
7130 int v_idx;
7131
7132 /* The requested uplink_seid must be either
7133 * - the PF's port seid
7134 * no VEB is needed because this is the PF
7135 * or this is a Flow Director special case VSI
7136 * - seid of an existing VEB
7137 * - seid of a VSI that owns an existing VEB
7138 * - seid of a VSI that doesn't own a VEB
7139 * a new VEB is created and the VSI becomes the owner
7140 * - seid of the PF VSI, which is what creates the first VEB
7141 * this is a special case of the previous
7142 *
7143 * Find which uplink_seid we were given and create a new VEB if needed
7144 */
7145 for (i = 0; i < I40E_MAX_VEB; i++) {
7146 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7147 veb = pf->veb[i];
7148 break;
7149 }
7150 }
7151
7152 if (!veb && uplink_seid != pf->mac_seid) {
7153
7154 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7155 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7156 vsi = pf->vsi[i];
7157 break;
7158 }
7159 }
7160 if (!vsi) {
7161 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7162 uplink_seid);
7163 return NULL;
7164 }
7165
7166 if (vsi->uplink_seid == pf->mac_seid)
7167 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7168 vsi->tc_config.enabled_tc);
7169 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7170 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7171 vsi->tc_config.enabled_tc);
7172
7173 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7174 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7175 veb = pf->veb[i];
7176 }
7177 if (!veb) {
7178 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7179 return NULL;
7180 }
7181
7182 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7183 uplink_seid = veb->seid;
7184 }
7185
7186 /* get vsi sw struct */
7187 v_idx = i40e_vsi_mem_alloc(pf, type);
7188 if (v_idx < 0)
7189 goto err_alloc;
7190 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7191 if (!vsi)
7192 goto err_alloc;
41c445ff
JB		 7193 vsi->type = type;
7194 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7195
7196 if (type == I40E_VSI_MAIN)
7197 pf->lan_vsi = v_idx;
7198 else if (type == I40E_VSI_SRIOV)
7199 vsi->vf_id = param1;
7200 /* assign it some queues */
cbf61325
ASJ		 7201 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7202 vsi->idx);
41c445ff
JB		 7203 if (ret < 0) {
7204 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7205 vsi->seid, ret);
7206 goto err_vsi;
7207 }
7208 vsi->base_queue = ret;
7209
7210 /* get a VSI from the hardware */
7211 vsi->uplink_seid = uplink_seid;
7212 ret = i40e_add_vsi(vsi);
7213 if (ret)
7214 goto err_vsi;
7215
7216 switch (vsi->type) {
7217 /* setup the netdev if needed */
7218 case I40E_VSI_MAIN:
7219 case I40E_VSI_VMDQ2:
7220 ret = i40e_config_netdev(vsi);
7221 if (ret)
7222 goto err_netdev;
7223 ret = register_netdev(vsi->netdev);
7224 if (ret)
7225 goto err_netdev;
7226 vsi->netdev_registered = true;
7227 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7228#ifdef CONFIG_I40E_DCB
7229 /* Setup DCB netlink interface */
7230 i40e_dcbnl_setup(vsi);
7231#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7232 /* fall through */
7233
7234 case I40E_VSI_FDIR:
7235 /* set up vectors and rings if needed */
7236 ret = i40e_vsi_setup_vectors(vsi);
7237 if (ret)
7238 goto err_msix;
7239
7240 ret = i40e_alloc_rings(vsi);
7241 if (ret)
7242 goto err_rings;
7243
7244 /* map all of the rings to the q_vectors */
7245 i40e_vsi_map_rings_to_vectors(vsi);
7246
7247 i40e_vsi_reset_stats(vsi);
7248 break;
7249
7250 default:
7251 /* no netdev or rings for the other VSI types */
7252 break;
7253 }
7254
7255 return vsi;
7256
7257err_rings:
7258 i40e_vsi_free_q_vectors(vsi);
7259err_msix:
7260 if (vsi->netdev_registered) {
7261 vsi->netdev_registered = false;
7262 unregister_netdev(vsi->netdev);
7263 free_netdev(vsi->netdev);
7264 vsi->netdev = NULL;
7265 }
7266err_netdev:
7267 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7268err_vsi:
7269 i40e_vsi_clear(vsi);
7270err_alloc:
7271 return NULL;
7272}
7273
7274/**
7275 * i40e_veb_get_bw_info - Query VEB BW information
7276 * @veb: the veb to query
7277 *
7278 * Query the Tx scheduler BW configuration data for given VEB
7279 **/
7280static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7281{
7282 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7283 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7284 struct i40e_pf *pf = veb->pf;
7285 struct i40e_hw *hw = &pf->hw;
7286 u32 tc_bw_max;
7287 int ret = 0;
7288 int i;
7289
7290 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7291 &bw_data, NULL);
7292 if (ret) {
7293 dev_info(&pf->pdev->dev,
7294 "query veb bw config failed, aq_err=%d\n",
7295 hw->aq.asq_last_status);
7296 goto out;
7297 }
7298
7299 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7300 &ets_data, NULL);
7301 if (ret) {
7302 dev_info(&pf->pdev->dev,
7303 "query veb bw ets config failed, aq_err=%d\n",
7304 hw->aq.asq_last_status);
7305 goto out;
7306 }
7307
7308 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7309 veb->bw_max_quanta = ets_data.tc_bw_max;
7310 veb->is_abs_credits = bw_data.absolute_credits_enable;
7311 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7312 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7313 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7314 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7315 veb->bw_tc_limit_credits[i] =
7316 le16_to_cpu(bw_data.tc_bw_limits[i]);
7317 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7318 }
7319
7320out:
7321 return ret;
7322}
7323
7324/**
7325 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7326 * @pf: board private structure
7327 *
7328 * On error: returns error code (negative)
7329 * On success: returns vsi index in PF (positive)
7330 **/
7331static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7332{
7333 int ret = -ENOENT;
7334 struct i40e_veb *veb;
7335 int i;
7336
7337 /* Need to protect the allocation of switch elements at the PF level */
7338 mutex_lock(&pf->switch_mutex);
7339
7340 /* VEB list may be fragmented if VEB creation/destruction has
7341 * been happening. We can afford to do a quick scan to look
7342 * for any free slots in the list.
7343 *
7344 * find next empty veb slot, looping back around if necessary
7345 */
7346 i = 0;
7347 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7348 i++;
7349 if (i >= I40E_MAX_VEB) {
7350 ret = -ENOMEM;
7351 goto err_alloc_veb; /* out of VEB slots! */
7352 }
7353
7354 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7355 if (!veb) {
7356 ret = -ENOMEM;
7357 goto err_alloc_veb;
7358 }
7359 veb->pf = pf;
7360 veb->idx = i;
7361 veb->enabled_tc = 1;
7362
7363 pf->veb[i] = veb;
7364 ret = i;
7365err_alloc_veb:
7366 mutex_unlock(&pf->switch_mutex);
7367 return ret;
7368}
7369
7370/**
7371 * i40e_switch_branch_release - Delete a branch of the switch tree
7372 * @branch: where to start deleting
7373 *
7374 * This uses recursion to find the tips of the branch to be
7375 * removed, deleting until we get back to and can delete this VEB.
7376 **/
7377static void i40e_switch_branch_release(struct i40e_veb *branch)
7378{
7379 struct i40e_pf *pf = branch->pf;
7380 u16 branch_seid = branch->seid;
7381 u16 veb_idx = branch->idx;
7382 int i;
7383
7384 /* release any VEBs on this VEB - RECURSION */
7385 for (i = 0; i < I40E_MAX_VEB; i++) {
7386 if (!pf->veb[i])
7387 continue;
7388 if (pf->veb[i]->uplink_seid == branch->seid)
7389 i40e_switch_branch_release(pf->veb[i]);
7390 }
7391
7392 /* Release the VSIs on this VEB, but not the owner VSI.
7393 *
7394 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7395 * the VEB itself, so don't use (*branch) after this loop.
7396 */
7397 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7398 if (!pf->vsi[i])
7399 continue;
7400 if (pf->vsi[i]->uplink_seid == branch_seid &&
7401 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7402 i40e_vsi_release(pf->vsi[i]);
7403 }
7404 }
7405
7406 /* There's one corner case where the VEB might not have been
7407 * removed, so double check it here and remove it if needed.
7408 * This case happens if the veb was created from the debugfs
7409 * commands and no VSIs were added to it.
7410 */
7411 if (pf->veb[veb_idx])
7412 i40e_veb_release(pf->veb[veb_idx]);
7413}
7414
7415/**
7416 * i40e_veb_clear - remove veb struct
7417 * @veb: the veb to remove
7418 **/
7419static void i40e_veb_clear(struct i40e_veb *veb)
7420{
7421 if (!veb)
7422 return;
7423
7424 if (veb->pf) {
7425 struct i40e_pf *pf = veb->pf;
7426
7427 mutex_lock(&pf->switch_mutex);
7428 if (pf->veb[veb->idx] == veb)
7429 pf->veb[veb->idx] = NULL;
7430 mutex_unlock(&pf->switch_mutex);
7431 }
7432
7433 kfree(veb);
7434}
7435
7436/**
7437 * i40e_veb_release - Delete a VEB and free its resources
7438 * @veb: the VEB being removed
7439 **/
7440void i40e_veb_release(struct i40e_veb *veb)
7441{
7442 struct i40e_vsi *vsi = NULL;
7443 struct i40e_pf *pf;
7444 int i, n = 0;
7445
7446 pf = veb->pf;
7447
7448 /* find the remaining VSI and check for extras */
7449 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7450 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7451 n++;
7452 vsi = pf->vsi[i];
7453 }
7454 }
7455 if (n != 1) {
7456 dev_info(&pf->pdev->dev,
7457 "can't remove VEB %d with %d VSIs left\n",
7458 veb->seid, n);
7459 return;
7460 }
7461
7462 /* move the remaining VSI to uplink veb */
7463 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7464 if (veb->uplink_seid) {
7465 vsi->uplink_seid = veb->uplink_seid;
7466 if (veb->uplink_seid == pf->mac_seid)
7467 vsi->veb_idx = I40E_NO_VEB;
7468 else
7469 vsi->veb_idx = veb->veb_idx;
7470 } else {
7471 /* floating VEB */
7472 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7473 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7474 }
7475
7476 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7477 i40e_veb_clear(veb);
7478
7479 return;
7480}
7481
7482/**
7483 * i40e_add_veb - create the VEB in the switch
7484 * @veb: the VEB to be instantiated
7485 * @vsi: the controlling VSI
7486 **/
7487static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7488{
56747264 7489 bool is_default = false;
e1c51b95 7490 bool is_cloud = false;
41c445ff
JB		 7491 int ret;
7492
7493 /* get a VEB from the hardware */
7494 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7495 veb->enabled_tc, is_default,
7496 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7497 if (ret) {
7498 dev_info(&veb->pf->pdev->dev,
7499 "couldn't add VEB, err %d, aq_err %d\n",
7500 ret, veb->pf->hw.aq.asq_last_status);
7501 return -EPERM;
7502 }
7503
7504 /* get statistics counter */
7505 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7506 &veb->stats_idx, NULL, NULL, NULL);
7507 if (ret) {
7508 dev_info(&veb->pf->pdev->dev,
7509 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7510 ret, veb->pf->hw.aq.asq_last_status);
7511 return -EPERM;
7512 }
7513 ret = i40e_veb_get_bw_info(veb);
7514 if (ret) {
7515 dev_info(&veb->pf->pdev->dev,
7516 "couldn't get VEB bw info, err %d, aq_err %d\n",
7517 ret, veb->pf->hw.aq.asq_last_status);
7518 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7519 return -ENOENT;
7520 }
7521
7522 vsi->uplink_seid = veb->seid;
7523 vsi->veb_idx = veb->idx;
7524 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7525
7526 return 0;
7527}
7528
7529/**
7530 * i40e_veb_setup - Set up a VEB
7531 * @pf: board private structure
7532 * @flags: VEB setup flags
7533 * @uplink_seid: the switch element to link to
7534 * @vsi_seid: the initial VSI seid
7535 * @enabled_tc: Enabled TC bit-map
7536 *
7537 * This allocates the sw VEB structure and links it into the switch
7538 * It is possible and legal for this to be a duplicate of an already
7539 * existing VEB. It is also possible for both uplink and vsi seids
7540 * to be zero, in order to create a floating VEB.
7541 *
7542 * Returns pointer to the successfully allocated VEB sw struct on
7543 * success, otherwise returns NULL on failure.
7544 **/
7545struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7546 u16 uplink_seid, u16 vsi_seid,
7547 u8 enabled_tc)
7548{
7549 struct i40e_veb *veb, *uplink_veb = NULL;
7550 int vsi_idx, veb_idx;
7551 int ret;
7552
7553 /* if one seid is 0, the other must be 0 to create a floating relay */
7554 if ((uplink_seid == 0 || vsi_seid == 0) &&
7555 (uplink_seid + vsi_seid != 0)) {
7556 dev_info(&pf->pdev->dev,
7557 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7558 uplink_seid, vsi_seid);
7559 return NULL;
7560 }
7561
7562 /* make sure there is such a vsi and uplink */
7563 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7564 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7565 break;
7566 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7567 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7568 vsi_seid);
7569 return NULL;
7570 }
7571
7572 if (uplink_seid && uplink_seid != pf->mac_seid) {
7573 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7574 if (pf->veb[veb_idx] &&
7575 pf->veb[veb_idx]->seid == uplink_seid) {
7576 uplink_veb = pf->veb[veb_idx];
7577 break;
7578 }
7579 }
7580 if (!uplink_veb) {
7581 dev_info(&pf->pdev->dev,
7582 "uplink seid %d not found\n", uplink_seid);
7583 return NULL;
7584 }
7585 }
7586
7587 /* get veb sw struct */
7588 veb_idx = i40e_veb_mem_alloc(pf);
7589 if (veb_idx < 0)
7590 goto err_alloc;
7591 veb = pf->veb[veb_idx];
7592 veb->flags = flags;
7593 veb->uplink_seid = uplink_seid;
7594 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7595 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7596
7597 /* create the VEB in the switch */
7598 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7599 if (ret)
7600 goto err_veb;
7601
7602 return veb;
7603
7604err_veb:
7605 i40e_veb_clear(veb);
7606err_alloc:
7607 return NULL;
7608}
7609
7610/**
7611 * i40e_setup_pf_switch_element - set pf vars based on switch type
7612 * @pf: board private structure
7613 * @ele: element we are building info from
7614 * @num_reported: total number of elements
7615 * @printconfig: should we print the contents
7616 *
7617 * helper function to assist in extracting a few useful SEID values.
7618 **/
7619static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7620 struct i40e_aqc_switch_config_element_resp *ele,
7621 u16 num_reported, bool printconfig)
7622{
7623 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7624 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7625 u8 element_type = ele->element_type;
7626 u16 seid = le16_to_cpu(ele->seid);
7627
7628 if (printconfig)
7629 dev_info(&pf->pdev->dev,
7630 "type=%d seid=%d uplink=%d downlink=%d\n",
7631 element_type, seid, uplink_seid, downlink_seid);
7632
7633 switch (element_type) {
7634 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7635 pf->mac_seid = seid;
7636 break;
7637 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7638 /* Main VEB? */
7639 if (uplink_seid != pf->mac_seid)
7640 break;
7641 if (pf->lan_veb == I40E_NO_VEB) {
7642 int v;
7643
7644 /* find existing or else empty VEB */
7645 for (v = 0; v < I40E_MAX_VEB; v++) {
7646 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7647 pf->lan_veb = v;
7648 break;
7649 }
7650 }
7651 if (pf->lan_veb == I40E_NO_VEB) {
7652 v = i40e_veb_mem_alloc(pf);
7653 if (v < 0)
7654 break;
7655 pf->lan_veb = v;
7656 }
7657 }
7658
7659 pf->veb[pf->lan_veb]->seid = seid;
7660 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7661 pf->veb[pf->lan_veb]->pf = pf;
7662 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7663 break;
7664 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7665 if (num_reported != 1)
7666 break;
7667 /* This is immediately after a reset so we can assume this is
7668 * the PF's VSI
7669 */
7670 pf->mac_seid = uplink_seid;
7671 pf->pf_seid = downlink_seid;
7672 pf->main_vsi_seid = seid;
7673 if (printconfig)
7674 dev_info(&pf->pdev->dev,
7675 "pf_seid=%d main_vsi_seid=%d\n",
7676 pf->pf_seid, pf->main_vsi_seid);
7677 break;
7678 case I40E_SWITCH_ELEMENT_TYPE_PF:
7679 case I40E_SWITCH_ELEMENT_TYPE_VF:
7680 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7681 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7682 case I40E_SWITCH_ELEMENT_TYPE_PE:
7683 case I40E_SWITCH_ELEMENT_TYPE_PA:
7684 /* ignore these for now */
7685 break;
7686 default:
7687 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7688 element_type, seid);
7689 break;
7690 }
7691}
7692
7693/**
7694 * i40e_fetch_switch_configuration - Get switch config from firmware
7695 * @pf: board private structure
7696 * @printconfig: should we print the contents
7697 *
7698 * Get the current switch configuration from the device and
7699 * extract a few useful SEID values.
7700 **/
7701int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7702{
7703 struct i40e_aqc_get_switch_config_resp *sw_config;
7704 u16 next_seid = 0;
7705 int ret = 0;
7706 u8 *aq_buf;
7707 int i;
7708
7709 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7710 if (!aq_buf)
7711 return -ENOMEM;
7712
7713 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7714 do {
7715 u16 num_reported, num_total;
7716
7717 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7718 I40E_AQ_LARGE_BUF,
7719 &next_seid, NULL);
7720 if (ret) {
7721 dev_info(&pf->pdev->dev,
7722 "get switch config failed %d aq_err=%x\n",
7723 ret, pf->hw.aq.asq_last_status);
7724 kfree(aq_buf);
7725 return -ENOENT;
7726 }
7727
7728 num_reported = le16_to_cpu(sw_config->header.num_reported);
7729 num_total = le16_to_cpu(sw_config->header.num_total);
7730
7731 if (printconfig)
7732 dev_info(&pf->pdev->dev,
7733 "header: %d reported %d total\n",
7734 num_reported, num_total);
7735
7736 if (num_reported) {
7737 int sz = sizeof(*sw_config) * num_reported;
7738
7739 kfree(pf->sw_config);
7740 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7741 if (pf->sw_config)
7742 memcpy(pf->sw_config, sw_config, sz);
7743 }
7744
7745 for (i = 0; i < num_reported; i++) {
7746 struct i40e_aqc_switch_config_element_resp *ele =
7747 &sw_config->element[i];
7748
7749 i40e_setup_pf_switch_element(pf, ele, num_reported,
7750 printconfig);
7751 }
7752 } while (next_seid != 0);
7753
7754 kfree(aq_buf);
7755 return ret;
7756}
7757
7758/**
7759 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7760 * @pf: board private structure
bc7d338f 7761 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7762 *
7763 * Returns 0 on success, negative value on failure
7764 **/
bc7d338f 7765static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7766{
895106a5 7767 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7768 int ret;
7769
7770 /* find out what's out there already */
7771 ret = i40e_fetch_switch_configuration(pf, false);
7772 if (ret) {
7773 dev_info(&pf->pdev->dev,
7774 "couldn't fetch switch config, err %d, aq_err %d\n",
7775 ret, pf->hw.aq.asq_last_status);
7776 return ret;
7777 }
7778 i40e_pf_reset_stats(pf);
7779
41c445ff 7780 /* first time setup */
bc7d338f 7781 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7782 struct i40e_vsi *vsi = NULL;
7783 u16 uplink_seid;
7784
7785 /* Set up the PF VSI associated with the PF's main VSI
7786 * that is already in the HW switch
7787 */
7788 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7789 uplink_seid = pf->veb[pf->lan_veb]->seid;
7790 else
7791 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7792 if (pf->lan_vsi == I40E_NO_VSI)
7793 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7794 else if (reinit)
7795 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7796 if (!vsi) {
7797 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7798 i40e_fdir_teardown(pf);
7799 return -EAGAIN;
7800 }
41c445ff
JB		 7801 } else {
7802 /* force a reset of TC and queue layout configurations */
7803 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7804 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7805 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7806 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7807 }
7808 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7809
cbf61325
ASJ		 7810 i40e_fdir_sb_setup(pf);
7811
41c445ff
JB		 7812 /* Setup static PF queue filter control settings */
7813 ret = i40e_setup_pf_filter_control(pf);
7814 if (ret) {
7815 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7816 ret);
7817 /* Failure here should not stop continuing other steps */
7818 }
7819
7820 /* enable RSS in the HW, even for only one queue, as the stack can use
7821 * the hash
7822 */
7823 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7824 i40e_config_rss(pf);
7825
7826 /* fill in link information and enable LSE reporting */
7827 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7828 i40e_link_event(pf);
7829
d52c20b7 7830 /* Initialize user-specific link properties */
41c445ff
JB		 7831 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7832 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7833 /* requested_mode is set in probe or by ethtool */
7834 if (!pf->fc_autoneg_status)
7835 goto no_autoneg;
7836
7837 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7838 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7839 pf->hw.fc.current_mode = I40E_FC_FULL;
7840 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7841 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7842 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7843 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7844 else
d52c20b7
JB		 7845 pf->hw.fc.current_mode = I40E_FC_NONE;
7846
7847 /* sync the flow control settings with the auto-neg values */
7848 switch (pf->hw.fc.current_mode) {
7849 case I40E_FC_FULL:
7850 txfc = 1;
7851 rxfc = 1;
7852 break;
7853 case I40E_FC_TX_PAUSE:
7854 txfc = 1;
7855 rxfc = 0;
7856 break;
7857 case I40E_FC_RX_PAUSE:
7858 txfc = 0;
7859 rxfc = 1;
7860 break;
7861 case I40E_FC_NONE:
7862 case I40E_FC_DEFAULT:
7863 txfc = 0;
7864 rxfc = 0;
7865 break;
7866 case I40E_FC_PFC:
7867 /* TBD */
7868 break;
7869 /* no default case, we have to handle all possibilities here */
7870 }
7871
7872 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7873
7874 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7875 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7876 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7877
7878 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7879
d52c20b7
JB		 7880 goto fc_complete;
7881
7882no_autoneg:
7883 /* disable L2 flow control, user can turn it on if they wish */
7884 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7885 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7886 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7887
7888fc_complete:
beb0dff1
JK		 7889 i40e_ptp_init(pf);
7890
41c445ff
JB		 7891 return ret;
7892}
7893
41c445ff
JB		 7894/**
7895 * i40e_determine_queue_usage - Work out queue distribution
7896 * @pf: board private structure
7897 **/
7898static void i40e_determine_queue_usage(struct i40e_pf *pf)
7899{
41c445ff
JB		 7900 int queues_left;
7901
7902 pf->num_lan_qps = 0;
41c445ff
JB		 7903
7904 /* Find the max queues to be put into basic use. We'll always be
7905 * using TC0, whether or not DCB is running, and TC0 will get the
7906 * big RSS set.
7907 */
7908 queues_left = pf->hw.func_caps.num_tx_qp;
7909
cbf61325
ASJ		 7910 if ((queues_left == 1) ||
7911 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
7912 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
7913 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 7914 /* one qp for PF, no queues for anything else */
7915 queues_left = 0;
7916 pf->rss_size = pf->num_lan_qps = 1;
7917
7918 /* make sure all the fancies are disabled */
60ea5f83
JB		 7919 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
7920 I40E_FLAG_FD_SB_ENABLED |
7921 I40E_FLAG_FD_ATR_ENABLED |
7922 I40E_FLAG_DCB_ENABLED |
7923 I40E_FLAG_SRIOV_ENABLED |
7924 I40E_FLAG_VMDQ_ENABLED);
41c445ff 7925 } else {
cbf61325
ASJ		 7926 /* Not enough queues for all TCs */
7927 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
7928 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
7929 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
7930 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
7931 }
7932 pf->num_lan_qps = pf->rss_size_max;
7933 queues_left -= pf->num_lan_qps;
7934 }
7935
7936 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7937 if (queues_left > 1) {
7938 queues_left -= 1; /* save 1 queue for FD */
7939 } else {
7940 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7941 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
7942 }
41c445ff
JB		 7943 }
7944
7945 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7946 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 7947 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
7948 (queues_left / pf->num_vf_qps));
41c445ff
JB		 7949 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7950 }
7951
7952 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7953 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7954 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7955 (queues_left / pf->num_vmdq_qps));
7956 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7957 }
7958
f8ff1464 7959 pf->queues_left = queues_left;
41c445ff
JB		 7960 return;
7961}
7962
7963/**
7964 * i40e_setup_pf_filter_control - Setup PF static filter control
7965 * @pf: PF to be setup
7966 *
7967 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7968 * settings. If PE/FCoE are enabled then it will also set the per PF
7969 * based filter sizes required for them. It also enables Flow director,
7970 * ethertype and macvlan type filter settings for the pf.
7971 *
7972 * Returns 0 on success, negative on failure
7973 **/
7974static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7975{
7976 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7977
7978 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7979
7980 /* Flow Director is enabled */
60ea5f83 7981 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 7982 settings->enable_fdir = true;
7983
7984 /* Ethtype and MACVLAN filters enabled for PF */
7985 settings->enable_ethtype = true;
7986 settings->enable_macvlan = true;
7987
7988 if (i40e_set_filter_control(&pf->hw, settings))
7989 return -ENOENT;
7990
7991 return 0;
7992}
7993
0c22b3dd
JB		 7994#define INFO_STRING_LEN 255
7995static void i40e_print_features(struct i40e_pf *pf)
7996{
7997 struct i40e_hw *hw = &pf->hw;
7998 char *buf, *string;
7999
8000 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8001 if (!string) {
8002 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8003 return;
8004 }
8005
8006 buf = string;
8007
8008 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8009#ifdef CONFIG_PCI_IOV
8010 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8011#endif
8012 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8013 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8014
8015 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8016 buf += sprintf(buf, "RSS ");
8017 buf += sprintf(buf, "FDir ");
8018 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
8019 buf += sprintf(buf, "ATR ");
8020 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
8021 buf += sprintf(buf, "NTUPLE ");
8022 if (pf->flags & I40E_FLAG_DCB_ENABLED)
8023 buf += sprintf(buf, "DCB ");
8024 if (pf->flags & I40E_FLAG_PTP)
8025 buf += sprintf(buf, "PTP ");
8026
8027 BUG_ON(buf > (string + INFO_STRING_LEN));
8028 dev_info(&pf->pdev->dev, "%s\n", string);
8029 kfree(string);
8030}
8031
41c445ff
JB		 8032/**
8033 * i40e_probe - Device initialization routine
8034 * @pdev: PCI device information struct
8035 * @ent: entry in i40e_pci_tbl
8036 *
8037 * i40e_probe initializes a pf identified by a pci_dev structure.
8038 * The OS initialization, configuring of the pf private structure,
8039 * and a hardware reset occur.
8040 *
8041 * Returns 0 on success, negative on failure
8042 **/
8043static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8044{
8045 struct i40e_driver_version dv;
8046 struct i40e_pf *pf;
8047 struct i40e_hw *hw;
93cd765b 8048 static u16 pfs_found;
d4dfb81a 8049 u16 link_status;
41c445ff
JB		 8050 int err = 0;
8051 u32 len;
8052
8053 err = pci_enable_device_mem(pdev);
8054 if (err)
8055 return err;
8056
8057 /* set up for high or low dma */
6494294f
MW		 8058 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
8059 if (err)
8060 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8061 if (err) {
8062 dev_err(&pdev->dev,
8063 "DMA configuration failed: 0x%x\n", err);
41c445ff
JB		 8064 goto err_dma;
8065 }
8066
8067 /* set up pci connections */
8068 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8069 IORESOURCE_MEM), i40e_driver_name);
8070 if (err) {
8071 dev_info(&pdev->dev,
8072 "pci_request_selected_regions failed %d\n", err);
8073 goto err_pci_reg;
8074 }
8075
8076 pci_enable_pcie_error_reporting(pdev);
8077 pci_set_master(pdev);
8078
8079 /* Now that we have a PCI connection, we need to do the
8080 * low level device setup. This is primarily setting up
8081 * the Admin Queue structures and then querying for the
8082 * device's current profile information.
8083 */
8084 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8085 if (!pf) {
8086 err = -ENOMEM;
8087 goto err_pf_alloc;
8088 }
8089 pf->next_vsi = 0;
8090 pf->pdev = pdev;
8091 set_bit(__I40E_DOWN, &pf->state);
8092
8093 hw = &pf->hw;
8094 hw->back = pf;
8095 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8096 pci_resource_len(pdev, 0));
8097 if (!hw->hw_addr) {
8098 err = -EIO;
8099 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8100 (unsigned int)pci_resource_start(pdev, 0),
8101 (unsigned int)pci_resource_len(pdev, 0), err);
8102 goto err_ioremap;
8103 }
8104 hw->vendor_id = pdev->vendor;
8105 hw->device_id = pdev->device;
8106 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8107 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8108 hw->subsystem_device_id = pdev->subsystem_device;
8109 hw->bus.device = PCI_SLOT(pdev->devfn);
8110 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8111 pf->instance = pfs_found;
41c445ff 8112
7134f9ce
JB		 8113 /* do a special CORER for clearing PXE mode once at init */
8114 if (hw->revision_id == 0 &&
8115 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8116 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8117 i40e_flush(hw);
8118 msleep(200);
8119 pf->corer_count++;
8120
8121 i40e_clear_pxe_mode(hw);
8122 }
8123
41c445ff
JB		 8124 /* Reset here to make sure all is clean and to define PF 'n' */
8125 err = i40e_pf_reset(hw);
8126 if (err) {
8127 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8128 goto err_pf_reset;
8129 }
8130 pf->pfr_count++;
8131
8132 hw->aq.num_arq_entries = I40E_AQ_LEN;
8133 hw->aq.num_asq_entries = I40E_AQ_LEN;
8134 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8135 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8136 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8137 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8138 "%s-pf%d:misc",
8139 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8140
8141 err = i40e_init_shared_code(hw);
8142 if (err) {
8143 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8144 goto err_pf_reset;
8145 }
8146
d52c20b7
JB		 8147 /* set up a default setting for link flow control */
8148 pf->hw.fc.requested_mode = I40E_FC_NONE;
8149
41c445ff
JB		 8150 err = i40e_init_adminq(hw);
8151 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8152 if (err) {
8153 dev_info(&pdev->dev,
8154 "init_adminq failed: %d expecting API %02x.%02x\n",
8155 err,
8156 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8157 goto err_pf_reset;
8158 }
8159
6ff4ef86 8160 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8161 err = i40e_get_capabilities(pf);
8162 if (err)
8163 goto err_adminq_setup;
8164
8165 err = i40e_sw_init(pf);
8166 if (err) {
8167 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8168 goto err_sw_init;
8169 }
8170
8171 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8172 hw->func_caps.num_rx_qp,
8173 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8174 if (err) {
8175 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8176 goto err_init_lan_hmc;
8177 }
8178
8179 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8180 if (err) {
8181 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8182 err = -ENOENT;
8183 goto err_configure_lan_hmc;
8184 }
8185
8186 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8187 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8188 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8189 err = -EIO;
8190 goto err_mac_addr;
8191 }
8192 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
8193 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
8194
8195 pci_set_drvdata(pdev, pf);
8196 pci_save_state(pdev);
4e3b35b0
NP		 8197#ifdef CONFIG_I40E_DCB
8198 err = i40e_init_pf_dcb(pf);
8199 if (err) {
8200 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
8201 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8202 goto err_init_dcb;
8203 }
8204#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8205
8206 /* set up periodic task facility */
8207 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8208 pf->service_timer_period = HZ;
8209
8210 INIT_WORK(&pf->service_task, i40e_service_task);
8211 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8212 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8213 pf->link_check_timeout = jiffies;
8214
8e2773ae
SN		 8215 /* WoL defaults to disabled */
8216 pf->wol_en = false;
8217 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8218
41c445ff
JB		 8219 /* set up the main switch operations */
8220 i40e_determine_queue_usage(pf);
8221 i40e_init_interrupt_scheme(pf);
8222
8223 /* Set up the *vsi struct based on the number of VSIs in the HW,
8224 * and set up our local tracking of the MAIN PF vsi.
8225 */
8226 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
8227 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8228 if (!pf->vsi) {
8229 err = -ENOMEM;
41c445ff 8230 goto err_switch_setup;
ed87ac09 8231 }
41c445ff 8232
bc7d338f 8233 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8234 if (err) {
8235 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8236 goto err_vsis;
8237 }
8238
8239 /* The main driver is (mostly) up and happy. We need to set this state
8240 * before setting up the misc vector or we get a race and the vector
8241 * ends up disabled forever.
8242 */
8243 clear_bit(__I40E_DOWN, &pf->state);
8244
8245 /* In case of MSIX we are going to setup the misc vector right here
8246 * to handle admin queue events etc. In case of legacy and MSI
8247 * the misc functionality and queue processing is combined in
8248 * the same vector and that gets setup at open.
8249 */
8250 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8251 err = i40e_setup_misc_vector(pf);
8252 if (err) {
8253 dev_info(&pdev->dev,
8254 "setup of misc vector failed: %d\n", err);
8255 goto err_vsis;
8256 }
8257 }
8258
8259 /* prep for VF support */
8260 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8261 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
8262 u32 val;
8263
8264 /* disable link interrupts for VFs */
8265 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8266 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8267 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8268 i40e_flush(hw);
4aeec010
MW		 8269
8270 if (pci_num_vf(pdev)) {
8271 dev_info(&pdev->dev,
8272 "Active VFs found, allocating resources.\n");
8273 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8274 if (err)
8275 dev_info(&pdev->dev,
8276 "Error %d allocating resources for existing VFs\n",
8277 err);
8278 }
41c445ff
JB		 8279 }
8280
93cd765b
ASJ		 8281 pfs_found++;
8282
41c445ff
JB		 8283 i40e_dbg_pf_init(pf);
8284
8285 /* tell the firmware that we're starting */
8286 dv.major_version = DRV_VERSION_MAJOR;
8287 dv.minor_version = DRV_VERSION_MINOR;
8288 dv.build_version = DRV_VERSION_BUILD;
8289 dv.subbuild_version = 0;
8290 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
8291
8292 /* since everything's happy, start the service_task timer */
8293 mod_timer(&pf->service_timer,
8294 round_jiffies(jiffies + pf->service_timer_period));
8295
d4dfb81a
CS		 8296 /* Get the negotiated link width and speed from PCI config space */
8297 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8298
8299 i40e_set_pci_config_data(hw, link_status);
8300
69bfb110 8301 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8302 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8303 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8304 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8305 "Unknown"),
8306 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8307 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8308 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8309 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8310 "Unknown"));
8311
8312 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8313 hw->bus.speed < i40e_bus_speed_8000) {
8314 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8315 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8316 }
8317
0c22b3dd
JB		 8318 /* print a string summarizing features */
8319 i40e_print_features(pf);
8320
41c445ff
JB		 8321 return 0;
8322
8323 /* Unwind what we've done if something failed in the setup */
8324err_vsis:
8325 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8326 i40e_clear_interrupt_scheme(pf);
8327 kfree(pf->vsi);
04b03013
SN		 8328err_switch_setup:
8329 i40e_reset_interrupt_capability(pf);
41c445ff 8330 del_timer_sync(&pf->service_timer);
4e3b35b0
NP		 8331#ifdef CONFIG_I40E_DCB
8332err_init_dcb:
8333#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8334err_mac_addr:
8335err_configure_lan_hmc:
8336 (void)i40e_shutdown_lan_hmc(hw);
8337err_init_lan_hmc:
8338 kfree(pf->qp_pile);
8339 kfree(pf->irq_pile);
8340err_sw_init:
8341err_adminq_setup:
8342 (void)i40e_shutdown_adminq(hw);
8343err_pf_reset:
8344 iounmap(hw->hw_addr);
8345err_ioremap:
8346 kfree(pf);
8347err_pf_alloc:
8348 pci_disable_pcie_error_reporting(pdev);
8349 pci_release_selected_regions(pdev,
8350 pci_select_bars(pdev, IORESOURCE_MEM));
8351err_pci_reg:
8352err_dma:
8353 pci_disable_device(pdev);
8354 return err;
8355}
8356
8357/**
8358 * i40e_remove - Device removal routine
8359 * @pdev: PCI device information struct
8360 *
8361 * i40e_remove is called by the PCI subsystem to alert the driver
8362 * that is should release a PCI device. This could be caused by a
8363 * Hot-Plug event, or because the driver is going to be removed from
8364 * memory.
8365 **/
8366static void i40e_remove(struct pci_dev *pdev)
8367{
8368 struct i40e_pf *pf = pci_get_drvdata(pdev);
8369 i40e_status ret_code;
8370 u32 reg;
8371 int i;
8372
8373 i40e_dbg_pf_exit(pf);
8374
beb0dff1
JK		 8375 i40e_ptp_stop(pf);
8376
41c445ff
JB		 8377 /* no more scheduling of any task */
8378 set_bit(__I40E_DOWN, &pf->state);
8379 del_timer_sync(&pf->service_timer);
8380 cancel_work_sync(&pf->service_task);
8381
eb2d80bc
MW		 8382 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8383 i40e_free_vfs(pf);
8384 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8385 }
8386
41c445ff
JB		 8387 i40e_fdir_teardown(pf);
8388
8389 /* If there is a switch structure or any orphans, remove them.
8390 * This will leave only the PF's VSI remaining.
8391 */
8392 for (i = 0; i < I40E_MAX_VEB; i++) {
8393 if (!pf->veb[i])
8394 continue;
8395
8396 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8397 pf->veb[i]->uplink_seid == 0)
8398 i40e_switch_branch_release(pf->veb[i]);
8399 }
8400
8401 /* Now we can shutdown the PF's VSI, just before we kill
8402 * adminq and hmc.
8403 */
8404 if (pf->vsi[pf->lan_vsi])
8405 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8406
8407 i40e_stop_misc_vector(pf);
8408 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8409 synchronize_irq(pf->msix_entries[0].vector);
8410 free_irq(pf->msix_entries[0].vector, pf);
8411 }
8412
8413 /* shutdown and destroy the HMC */
8414 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8415 if (ret_code)
8416 dev_warn(&pdev->dev,
8417 "Failed to destroy the HMC resources: %d\n", ret_code);
8418
8419 /* shutdown the adminq */
41c445ff
JB		 8420 ret_code = i40e_shutdown_adminq(&pf->hw);
8421 if (ret_code)
8422 dev_warn(&pdev->dev,
8423 "Failed to destroy the Admin Queue resources: %d\n",
8424 ret_code);
8425
8426 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8427 i40e_clear_interrupt_scheme(pf);
8428 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8429 if (pf->vsi[i]) {
8430 i40e_vsi_clear_rings(pf->vsi[i]);
8431 i40e_vsi_clear(pf->vsi[i]);
8432 pf->vsi[i] = NULL;
8433 }
8434 }
8435
8436 for (i = 0; i < I40E_MAX_VEB; i++) {
8437 kfree(pf->veb[i]);
8438 pf->veb[i] = NULL;
8439 }
8440
8441 kfree(pf->qp_pile);
8442 kfree(pf->irq_pile);
8443 kfree(pf->sw_config);
8444 kfree(pf->vsi);
8445
8446 /* force a PF reset to clean anything leftover */
8447 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8448 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8449 i40e_flush(&pf->hw);
8450
8451 iounmap(pf->hw.hw_addr);
8452 kfree(pf);
8453 pci_release_selected_regions(pdev,
8454 pci_select_bars(pdev, IORESOURCE_MEM));
8455
8456 pci_disable_pcie_error_reporting(pdev);
8457 pci_disable_device(pdev);
8458}
8459
8460/**
8461 * i40e_pci_error_detected - warning that something funky happened in PCI land
8462 * @pdev: PCI device information struct
8463 *
8464 * Called to warn that something happened and the error handling steps
8465 * are in progress. Allows the driver to quiesce things, be ready for
8466 * remediation.
8467 **/
8468static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8469 enum pci_channel_state error)
8470{
8471 struct i40e_pf *pf = pci_get_drvdata(pdev);
8472
8473 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8474
8475 /* shutdown all operations */
9007bccd
SN		 8476 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8477 rtnl_lock();
8478 i40e_prep_for_reset(pf);
8479 rtnl_unlock();
8480 }
41c445ff
JB		 8481
8482 /* Request a slot reset */
8483 return PCI_ERS_RESULT_NEED_RESET;
8484}
8485
8486/**
8487 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8488 * @pdev: PCI device information struct
8489 *
8490 * Called to find if the driver can work with the device now that
8491 * the pci slot has been reset. If a basic connection seems good
8492 * (registers are readable and have sane content) then return a
8493 * happy little PCI_ERS_RESULT_xxx.
8494 **/
8495static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8496{
8497 struct i40e_pf *pf = pci_get_drvdata(pdev);
8498 pci_ers_result_t result;
8499 int err;
8500 u32 reg;
8501
8502 dev_info(&pdev->dev, "%s\n", __func__);
8503 if (pci_enable_device_mem(pdev)) {
8504 dev_info(&pdev->dev,
8505 "Cannot re-enable PCI device after reset.\n");
8506 result = PCI_ERS_RESULT_DISCONNECT;
8507 } else {
8508 pci_set_master(pdev);
8509 pci_restore_state(pdev);
8510 pci_save_state(pdev);
8511 pci_wake_from_d3(pdev, false);
8512
8513 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8514 if (reg == 0)
8515 result = PCI_ERS_RESULT_RECOVERED;
8516 else
8517 result = PCI_ERS_RESULT_DISCONNECT;
8518 }
8519
8520 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8521 if (err) {
8522 dev_info(&pdev->dev,
8523 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8524 err);
8525 /* non-fatal, continue */
8526 }
8527
8528 return result;
8529}
8530
8531/**
8532 * i40e_pci_error_resume - restart operations after PCI error recovery
8533 * @pdev: PCI device information struct
8534 *
8535 * Called to allow the driver to bring things back up after PCI error
8536 * and/or reset recovery has finished.
8537 **/
8538static void i40e_pci_error_resume(struct pci_dev *pdev)
8539{
8540 struct i40e_pf *pf = pci_get_drvdata(pdev);
8541
8542 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8543 if (test_bit(__I40E_SUSPENDED, &pf->state))
8544 return;
8545
8546 rtnl_lock();
41c445ff 8547 i40e_handle_reset_warning(pf);
9007bccd
SN		 8548 rtnl_lock();
8549}
8550
8551/**
8552 * i40e_shutdown - PCI callback for shutting down
8553 * @pdev: PCI device information struct
8554 **/
8555static void i40e_shutdown(struct pci_dev *pdev)
8556{
8557 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8558 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8559
8560 set_bit(__I40E_SUSPENDED, &pf->state);
8561 set_bit(__I40E_DOWN, &pf->state);
8562 rtnl_lock();
8563 i40e_prep_for_reset(pf);
8564 rtnl_unlock();
8565
8e2773ae
SN		 8566 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8567 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8568
9007bccd 8569 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8570 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8571 pci_set_power_state(pdev, PCI_D3hot);
8572 }
8573}
8574
8575#ifdef CONFIG_PM
8576/**
8577 * i40e_suspend - PCI callback for moving to D3
8578 * @pdev: PCI device information struct
8579 **/
8580static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8581{
8582 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8583 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8584
8585 set_bit(__I40E_SUSPENDED, &pf->state);
8586 set_bit(__I40E_DOWN, &pf->state);
8587 rtnl_lock();
8588 i40e_prep_for_reset(pf);
8589 rtnl_unlock();
8590
8e2773ae
SN		 8591 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8592 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8593
8594 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8595 pci_set_power_state(pdev, PCI_D3hot);
8596
8597 return 0;
41c445ff
JB		 8598}
8599
9007bccd
SN		 8600/**
8601 * i40e_resume - PCI callback for waking up from D3
8602 * @pdev: PCI device information struct
8603 **/
8604static int i40e_resume(struct pci_dev *pdev)
8605{
8606 struct i40e_pf *pf = pci_get_drvdata(pdev);
8607 u32 err;
8608
8609 pci_set_power_state(pdev, PCI_D0);
8610 pci_restore_state(pdev);
8611 /* pci_restore_state() clears dev->state_saves, so
8612 * call pci_save_state() again to restore it.
8613 */
8614 pci_save_state(pdev);
8615
8616 err = pci_enable_device_mem(pdev);
8617 if (err) {
8618 dev_err(&pdev->dev,
8619 "%s: Cannot enable PCI device from suspend\n",
8620 __func__);
8621 return err;
8622 }
8623 pci_set_master(pdev);
8624
8625 /* no wakeup events while running */
8626 pci_wake_from_d3(pdev, false);
8627
8628 /* handling the reset will rebuild the device state */
8629 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8630 clear_bit(__I40E_DOWN, &pf->state);
8631 rtnl_lock();
8632 i40e_reset_and_rebuild(pf, false);
8633 rtnl_unlock();
8634 }
8635
8636 return 0;
8637}
8638
8639#endif
41c445ff
JB		 8640static const struct pci_error_handlers i40e_err_handler = {
8641 .error_detected = i40e_pci_error_detected,
8642 .slot_reset = i40e_pci_error_slot_reset,
8643 .resume = i40e_pci_error_resume,
8644};
8645
8646static struct pci_driver i40e_driver = {
8647 .name = i40e_driver_name,
8648 .id_table = i40e_pci_tbl,
8649 .probe = i40e_probe,
8650 .remove = i40e_remove,
9007bccd
SN		 8651#ifdef CONFIG_PM
8652 .suspend = i40e_suspend,
8653 .resume = i40e_resume,
8654#endif
8655 .shutdown = i40e_shutdown,
41c445ff
JB		 8656 .err_handler = &i40e_err_handler,
8657 .sriov_configure = i40e_pci_sriov_configure,
8658};
8659
8660/**
8661 * i40e_init_module - Driver registration routine
8662 *
8663 * i40e_init_module is the first routine called when the driver is
8664 * loaded. All it does is register with the PCI subsystem.
8665 **/
8666static int __init i40e_init_module(void)
8667{
8668 pr_info("%s: %s - version %s\n", i40e_driver_name,
8669 i40e_driver_string, i40e_driver_version_str);
8670 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8671 i40e_dbg_init();
8672 return pci_register_driver(&i40e_driver);
8673}
8674module_init(i40e_init_module);
8675
8676/**
8677 * i40e_exit_module - Driver exit cleanup routine
8678 *
8679 * i40e_exit_module is called just before the driver is removed
8680 * from memory.
8681 **/
8682static void __exit i40e_exit_module(void)
8683{
8684 pci_unregister_driver(&i40e_driver);
8685 i40e_dbg_exit();
8686}
8687module_exit(i40e_exit_module);
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