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i40e: Update VEB's enabled_tc after reconfiguration
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
7bda87c7
CS		 41#define DRV_VERSION_MINOR 1
42#define DRV_VERSION_BUILD 23
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
38e00438
VD		 273#ifdef I40E_FCOE
274void i40e_tx_timeout(struct net_device *netdev)
275#else
41c445ff 276static void i40e_tx_timeout(struct net_device *netdev)
38e00438 277#endif
41c445ff
JB		 278{
279 struct i40e_netdev_priv *np = netdev_priv(netdev);
280 struct i40e_vsi *vsi = np->vsi;
281 struct i40e_pf *pf = vsi->back;
282
283 pf->tx_timeout_count++;
284
285 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 286 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 287 pf->tx_timeout_last_recovery = jiffies;
288 netdev_info(netdev, "tx_timeout recovery level %d\n",
289 pf->tx_timeout_recovery_level);
290
291 switch (pf->tx_timeout_recovery_level) {
292 case 0:
293 /* disable and re-enable queues for the VSI */
294 if (in_interrupt()) {
295 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
296 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
297 } else {
298 i40e_vsi_reinit_locked(vsi);
299 }
300 break;
301 case 1:
302 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
303 break;
304 case 2:
305 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
306 break;
307 case 3:
308 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
309 break;
310 default:
311 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 312 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
313 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 314 break;
315 }
316 i40e_service_event_schedule(pf);
317 pf->tx_timeout_recovery_level++;
318}
319
320/**
321 * i40e_release_rx_desc - Store the new tail and head values
322 * @rx_ring: ring to bump
323 * @val: new head index
324 **/
325static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
326{
327 rx_ring->next_to_use = val;
328
329 /* Force memory writes to complete before letting h/w
330 * know there are new descriptors to fetch. (Only
331 * applicable for weak-ordered memory model archs,
332 * such as IA-64).
333 */
334 wmb();
335 writel(val, rx_ring->tail);
336}
337
338/**
339 * i40e_get_vsi_stats_struct - Get System Network Statistics
340 * @vsi: the VSI we care about
341 *
342 * Returns the address of the device statistics structure.
343 * The statistics are actually updated from the service task.
344 **/
345struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
346{
347 return &vsi->net_stats;
348}
349
350/**
351 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
352 * @netdev: network interface device structure
353 *
354 * Returns the address of the device statistics structure.
355 * The statistics are actually updated from the service task.
356 **/
38e00438
VD		 357#ifdef I40E_FCOE
358struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
359 struct net_device *netdev,
360 struct rtnl_link_stats64 *stats)
361#else
41c445ff
JB		 362static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
363 struct net_device *netdev,
980e9b11 364 struct rtnl_link_stats64 *stats)
38e00438 365#endif
41c445ff
JB		 366{
367 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 368 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 369 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 370 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
371 int i;
372
bc7d338f
ASJ		 373 if (test_bit(__I40E_DOWN, &vsi->state))
374 return stats;
375
3c325ced
JB		 376 if (!vsi->tx_rings)
377 return stats;
378
980e9b11
AD		 379 rcu_read_lock();
380 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 381 u64 bytes, packets;
382 unsigned int start;
383
384 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
385 if (!tx_ring)
386 continue;
387
388 do {
57a7744e 389 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 390 packets = tx_ring->stats.packets;
391 bytes = tx_ring->stats.bytes;
57a7744e 392 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 393
394 stats->tx_packets += packets;
395 stats->tx_bytes += bytes;
396 rx_ring = &tx_ring[1];
397
398 do {
57a7744e 399 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 400 packets = rx_ring->stats.packets;
401 bytes = rx_ring->stats.bytes;
57a7744e 402 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 403
980e9b11
AD		 404 stats->rx_packets += packets;
405 stats->rx_bytes += bytes;
406 }
407 rcu_read_unlock();
408
a5282f44 409 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 410 stats->multicast = vsi_stats->multicast;
411 stats->tx_errors = vsi_stats->tx_errors;
412 stats->tx_dropped = vsi_stats->tx_dropped;
413 stats->rx_errors = vsi_stats->rx_errors;
414 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
415 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 416
980e9b11 417 return stats;
41c445ff
JB		 418}
419
420/**
421 * i40e_vsi_reset_stats - Resets all stats of the given vsi
422 * @vsi: the VSI to have its stats reset
423 **/
424void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
425{
426 struct rtnl_link_stats64 *ns;
427 int i;
428
429 if (!vsi)
430 return;
431
432 ns = i40e_get_vsi_stats_struct(vsi);
433 memset(ns, 0, sizeof(*ns));
434 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
435 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
436 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 437 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 438 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 439 memset(&vsi->rx_rings[i]->stats, 0 ,
440 sizeof(vsi->rx_rings[i]->stats));
441 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
442 sizeof(vsi->rx_rings[i]->rx_stats));
443 memset(&vsi->tx_rings[i]->stats, 0 ,
444 sizeof(vsi->tx_rings[i]->stats));
445 memset(&vsi->tx_rings[i]->tx_stats, 0,
446 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 447 }
8e9dca53 448 }
41c445ff
JB		 449 vsi->stat_offsets_loaded = false;
450}
451
452/**
453 * i40e_pf_reset_stats - Reset all of the stats for the given pf
454 * @pf: the PF to be reset
455 **/
456void i40e_pf_reset_stats(struct i40e_pf *pf)
457{
e91fdf76
SN		 458 int i;
459
41c445ff
JB		 460 memset(&pf->stats, 0, sizeof(pf->stats));
461 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
462 pf->stat_offsets_loaded = false;
e91fdf76
SN		 463
464 for (i = 0; i < I40E_MAX_VEB; i++) {
465 if (pf->veb[i]) {
466 memset(&pf->veb[i]->stats, 0,
467 sizeof(pf->veb[i]->stats));
468 memset(&pf->veb[i]->stats_offsets, 0,
469 sizeof(pf->veb[i]->stats_offsets));
470 pf->veb[i]->stat_offsets_loaded = false;
471 }
472 }
41c445ff
JB		 473}
474
475/**
476 * i40e_stat_update48 - read and update a 48 bit stat from the chip
477 * @hw: ptr to the hardware info
478 * @hireg: the high 32 bit reg to read
479 * @loreg: the low 32 bit reg to read
480 * @offset_loaded: has the initial offset been loaded yet
481 * @offset: ptr to current offset value
482 * @stat: ptr to the stat
483 *
484 * Since the device stats are not reset at PFReset, they likely will not
485 * be zeroed when the driver starts. We'll save the first values read
486 * and use them as offsets to be subtracted from the raw values in order
487 * to report stats that count from zero. In the process, we also manage
488 * the potential roll-over.
489 **/
490static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
491 bool offset_loaded, u64 *offset, u64 *stat)
492{
493 u64 new_data;
494
ab60085e 495 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 496 new_data = rd32(hw, loreg);
497 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
498 } else {
499 new_data = rd64(hw, loreg);
500 }
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = new_data - *offset;
505 else
506 *stat = (new_data + ((u64)1 << 48)) - *offset;
507 *stat &= 0xFFFFFFFFFFFFULL;
508}
509
510/**
511 * i40e_stat_update32 - read and update a 32 bit stat from the chip
512 * @hw: ptr to the hardware info
513 * @reg: the hw reg to read
514 * @offset_loaded: has the initial offset been loaded yet
515 * @offset: ptr to current offset value
516 * @stat: ptr to the stat
517 **/
518static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
519 bool offset_loaded, u64 *offset, u64 *stat)
520{
521 u32 new_data;
522
523 new_data = rd32(hw, reg);
524 if (!offset_loaded)
525 *offset = new_data;
526 if (likely(new_data >= *offset))
527 *stat = (u32)(new_data - *offset);
528 else
529 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
530}
531
532/**
533 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
534 * @vsi: the VSI to be updated
535 **/
536void i40e_update_eth_stats(struct i40e_vsi *vsi)
537{
538 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
539 struct i40e_pf *pf = vsi->back;
540 struct i40e_hw *hw = &pf->hw;
541 struct i40e_eth_stats *oes;
542 struct i40e_eth_stats *es; /* device's eth stats */
543
544 es = &vsi->eth_stats;
545 oes = &vsi->eth_stats_offsets;
546
547 /* Gather up the stats that the hw collects */
548 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
549 vsi->stat_offsets_loaded,
550 &oes->tx_errors, &es->tx_errors);
551 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 554 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
555 vsi->stat_offsets_loaded,
556 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
557 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 560
561 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
562 I40E_GLV_GORCL(stat_idx),
563 vsi->stat_offsets_loaded,
564 &oes->rx_bytes, &es->rx_bytes);
565 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
566 I40E_GLV_UPRCL(stat_idx),
567 vsi->stat_offsets_loaded,
568 &oes->rx_unicast, &es->rx_unicast);
569 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
570 I40E_GLV_MPRCL(stat_idx),
571 vsi->stat_offsets_loaded,
572 &oes->rx_multicast, &es->rx_multicast);
573 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
574 I40E_GLV_BPRCL(stat_idx),
575 vsi->stat_offsets_loaded,
576 &oes->rx_broadcast, &es->rx_broadcast);
577
578 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
579 I40E_GLV_GOTCL(stat_idx),
580 vsi->stat_offsets_loaded,
581 &oes->tx_bytes, &es->tx_bytes);
582 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
583 I40E_GLV_UPTCL(stat_idx),
584 vsi->stat_offsets_loaded,
585 &oes->tx_unicast, &es->tx_unicast);
586 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
587 I40E_GLV_MPTCL(stat_idx),
588 vsi->stat_offsets_loaded,
589 &oes->tx_multicast, &es->tx_multicast);
590 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
591 I40E_GLV_BPTCL(stat_idx),
592 vsi->stat_offsets_loaded,
593 &oes->tx_broadcast, &es->tx_broadcast);
594 vsi->stat_offsets_loaded = true;
595}
596
597/**
598 * i40e_update_veb_stats - Update Switch component statistics
599 * @veb: the VEB being updated
600 **/
601static void i40e_update_veb_stats(struct i40e_veb *veb)
602{
603 struct i40e_pf *pf = veb->pf;
604 struct i40e_hw *hw = &pf->hw;
605 struct i40e_eth_stats *oes;
606 struct i40e_eth_stats *es; /* device's eth stats */
607 int idx = 0;
608
609 idx = veb->stats_idx;
610 es = &veb->stats;
611 oes = &veb->stats_offsets;
612
613 /* Gather up the stats that the hw collects */
614 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 617 if (hw->revision_id > 0)
618 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
619 veb->stat_offsets_loaded,
620 &oes->rx_unknown_protocol,
621 &es->rx_unknown_protocol);
41c445ff
JB		 622 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
623 veb->stat_offsets_loaded,
624 &oes->rx_bytes, &es->rx_bytes);
625 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
626 veb->stat_offsets_loaded,
627 &oes->rx_unicast, &es->rx_unicast);
628 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
629 veb->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
632 veb->stat_offsets_loaded,
633 &oes->rx_broadcast, &es->rx_broadcast);
634
635 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
636 veb->stat_offsets_loaded,
637 &oes->tx_bytes, &es->tx_bytes);
638 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
639 veb->stat_offsets_loaded,
640 &oes->tx_unicast, &es->tx_unicast);
641 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
642 veb->stat_offsets_loaded,
643 &oes->tx_multicast, &es->tx_multicast);
644 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
645 veb->stat_offsets_loaded,
646 &oes->tx_broadcast, &es->tx_broadcast);
647 veb->stat_offsets_loaded = true;
648}
649
38e00438
VD		 650#ifdef I40E_FCOE
651/**
652 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
653 * @vsi: the VSI that is capable of doing FCoE
654 **/
655static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
656{
657 struct i40e_pf *pf = vsi->back;
658 struct i40e_hw *hw = &pf->hw;
659 struct i40e_fcoe_stats *ofs;
660 struct i40e_fcoe_stats *fs; /* device's eth stats */
661 int idx;
662
663 if (vsi->type != I40E_VSI_FCOE)
664 return;
665
666 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
667 fs = &vsi->fcoe_stats;
668 ofs = &vsi->fcoe_stats_offsets;
669
670 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
671 vsi->fcoe_stat_offsets_loaded,
672 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
673 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
674 vsi->fcoe_stat_offsets_loaded,
675 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
676 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
677 vsi->fcoe_stat_offsets_loaded,
678 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
679 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
680 vsi->fcoe_stat_offsets_loaded,
681 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
682 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
683 vsi->fcoe_stat_offsets_loaded,
684 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
685 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
686 vsi->fcoe_stat_offsets_loaded,
687 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
688 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
689 vsi->fcoe_stat_offsets_loaded,
690 &ofs->fcoe_last_error, &fs->fcoe_last_error);
691 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
692 vsi->fcoe_stat_offsets_loaded,
693 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
694
695 vsi->fcoe_stat_offsets_loaded = true;
696}
697
698#endif
41c445ff
JB		 699/**
700 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
701 * @pf: the corresponding PF
702 *
703 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
704 **/
705static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
706{
707 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
708 struct i40e_hw_port_stats *nsd = &pf->stats;
709 struct i40e_hw *hw = &pf->hw;
710 u64 xoff = 0;
711 u16 i, v;
712
713 if ((hw->fc.current_mode != I40E_FC_FULL) &&
714 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
715 return;
716
717 xoff = nsd->link_xoff_rx;
718 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
719 pf->stat_offsets_loaded,
720 &osd->link_xoff_rx, &nsd->link_xoff_rx);
721
722 /* No new LFC xoff rx */
723 if (!(nsd->link_xoff_rx - xoff))
724 return;
725
726 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 727 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 728 struct i40e_vsi *vsi = pf->vsi[v];
729
ddfda80f 730 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 731 continue;
732
733 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 734 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 735 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
736 }
737 }
738}
739
740/**
741 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
742 * @pf: the corresponding PF
743 *
744 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
745 **/
746static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
747{
748 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
749 struct i40e_hw_port_stats *nsd = &pf->stats;
750 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
751 struct i40e_dcbx_config *dcb_cfg;
752 struct i40e_hw *hw = &pf->hw;
753 u16 i, v;
754 u8 tc;
755
756 dcb_cfg = &hw->local_dcbx_config;
757
758 /* See if DCB enabled with PFC TC */
759 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
760 !(dcb_cfg->pfc.pfcenable)) {
761 i40e_update_link_xoff_rx(pf);
762 return;
763 }
764
765 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
766 u64 prio_xoff = nsd->priority_xoff_rx[i];
767 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
768 pf->stat_offsets_loaded,
769 &osd->priority_xoff_rx[i],
770 &nsd->priority_xoff_rx[i]);
771
772 /* No new PFC xoff rx */
773 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
774 continue;
775 /* Get the TC for given priority */
776 tc = dcb_cfg->etscfg.prioritytable[i];
777 xoff[tc] = true;
778 }
779
780 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 781 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 782 struct i40e_vsi *vsi = pf->vsi[v];
783
ddfda80f 784 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 785 continue;
786
787 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 788 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 789
790 tc = ring->dcb_tc;
791 if (xoff[tc])
792 clear_bit(__I40E_HANG_CHECK_ARMED,
793 &ring->state);
794 }
795 }
796}
797
798/**
7812fddc 799 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 800 * @vsi: the VSI to be updated
801 *
802 * There are a few instances where we store the same stat in a
803 * couple of different structs. This is partly because we have
804 * the netdev stats that need to be filled out, which is slightly
805 * different from the "eth_stats" defined by the chip and used in
7812fddc 806 * VF communications. We sort it out here.
41c445ff 807 **/
7812fddc 808static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 809{
810 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 811 struct rtnl_link_stats64 *ons;
812 struct rtnl_link_stats64 *ns; /* netdev stats */
813 struct i40e_eth_stats *oes;
814 struct i40e_eth_stats *es; /* device's eth stats */
815 u32 tx_restart, tx_busy;
bf00b376 816 struct i40e_ring *p;
41c445ff 817 u32 rx_page, rx_buf;
bf00b376
AA		 818 u64 bytes, packets;
819 unsigned int start;
41c445ff
JB		 820 u64 rx_p, rx_b;
821 u64 tx_p, tx_b;
41c445ff
JB		 822 u16 q;
823
824 if (test_bit(__I40E_DOWN, &vsi->state) ||
825 test_bit(__I40E_CONFIG_BUSY, &pf->state))
826 return;
827
828 ns = i40e_get_vsi_stats_struct(vsi);
829 ons = &vsi->net_stats_offsets;
830 es = &vsi->eth_stats;
831 oes = &vsi->eth_stats_offsets;
832
833 /* Gather up the netdev and vsi stats that the driver collects
834 * on the fly during packet processing
835 */
836 rx_b = rx_p = 0;
837 tx_b = tx_p = 0;
838 tx_restart = tx_busy = 0;
839 rx_page = 0;
840 rx_buf = 0;
980e9b11 841 rcu_read_lock();
41c445ff 842 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 843 /* locate Tx ring */
844 p = ACCESS_ONCE(vsi->tx_rings[q]);
845
846 do {
57a7744e 847 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 848 packets = p->stats.packets;
849 bytes = p->stats.bytes;
57a7744e 850 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 851 tx_b += bytes;
852 tx_p += packets;
853 tx_restart += p->tx_stats.restart_queue;
854 tx_busy += p->tx_stats.tx_busy;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc
SN		 898/**
899 * i40e_update_pf_stats - Update the pf statistics counters.
900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
922 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->eth.tx_discards,
925 &nsd->eth.tx_discards);
41c445ff 926
532d283d
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
928 I40E_GLPRT_UPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_unicast,
931 &nsd->eth.rx_unicast);
7812fddc
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
933 I40E_GLPRT_MPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_multicast,
936 &nsd->eth.rx_multicast);
532d283d
SN		 937 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
938 I40E_GLPRT_BPRCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.rx_broadcast,
941 &nsd->eth.rx_broadcast);
942 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
943 I40E_GLPRT_UPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_unicast,
946 &nsd->eth.tx_unicast);
947 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
948 I40E_GLPRT_MPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_multicast,
951 &nsd->eth.tx_multicast);
952 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
953 I40E_GLPRT_BPTCL(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->eth.tx_broadcast,
956 &nsd->eth.tx_broadcast);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->tx_dropped_link_down,
961 &nsd->tx_dropped_link_down);
41c445ff 962
7812fddc
SN		 963 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->crc_errors, &nsd->crc_errors);
41c445ff 966
7812fddc
SN		 967 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 970
7812fddc
SN		 971 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->mac_local_faults,
974 &nsd->mac_local_faults);
975 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->mac_remote_faults,
978 &nsd->mac_remote_faults);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->rx_length_errors,
983 &nsd->rx_length_errors);
41c445ff 984
7812fddc
SN		 985 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->link_xon_rx, &nsd->link_xon_rx);
988 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
989 pf->stat_offsets_loaded,
990 &osd->link_xon_tx, &nsd->link_xon_tx);
991 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
992 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 995
7812fddc
SN		 996 for (i = 0; i < 8; i++) {
997 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 998 pf->stat_offsets_loaded,
7812fddc
SN		 999 &osd->priority_xon_rx[i],
1000 &nsd->priority_xon_rx[i]);
1001 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1002 pf->stat_offsets_loaded,
7812fddc
SN		 1003 &osd->priority_xon_tx[i],
1004 &nsd->priority_xon_tx[i]);
1005 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xoff_tx[i],
1008 &nsd->priority_xoff_tx[i]);
1009 i40e_stat_update32(hw,
1010 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1011 pf->stat_offsets_loaded,
7812fddc
SN		 1012 &osd->priority_xon_2_xoff[i],
1013 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1014 }
1015
7812fddc
SN		 1016 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1017 I40E_GLPRT_PRC64L(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->rx_size_64, &nsd->rx_size_64);
1020 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1021 I40E_GLPRT_PRC127L(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_size_127, &nsd->rx_size_127);
1024 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1025 I40E_GLPRT_PRC255L(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->rx_size_255, &nsd->rx_size_255);
1028 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1029 I40E_GLPRT_PRC511L(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->rx_size_511, &nsd->rx_size_511);
1032 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1033 I40E_GLPRT_PRC1023L(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->rx_size_1023, &nsd->rx_size_1023);
1036 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1037 I40E_GLPRT_PRC1522L(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_size_1522, &nsd->rx_size_1522);
1040 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1041 I40E_GLPRT_PRC9522L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->rx_size_big, &nsd->rx_size_big);
1044
1045 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1046 I40E_GLPRT_PTC64L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->tx_size_64, &nsd->tx_size_64);
1049 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1050 I40E_GLPRT_PTC127L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->tx_size_127, &nsd->tx_size_127);
1053 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1054 I40E_GLPRT_PTC255L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->tx_size_255, &nsd->tx_size_255);
1057 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1058 I40E_GLPRT_PTC511L(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_size_511, &nsd->tx_size_511);
1061 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1062 I40E_GLPRT_PTC1023L(hw->port),
1063 pf->stat_offsets_loaded,
1064 &osd->tx_size_1023, &nsd->tx_size_1023);
1065 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1066 I40E_GLPRT_PTC1522L(hw->port),
1067 pf->stat_offsets_loaded,
1068 &osd->tx_size_1522, &nsd->tx_size_1522);
1069 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1070 I40E_GLPRT_PTC9522L(hw->port),
1071 pf->stat_offsets_loaded,
1072 &osd->tx_size_big, &nsd->tx_size_big);
1073
1074 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1075 pf->stat_offsets_loaded,
1076 &osd->rx_undersize, &nsd->rx_undersize);
1077 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1078 pf->stat_offsets_loaded,
1079 &osd->rx_fragments, &nsd->rx_fragments);
1080 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->rx_oversize, &nsd->rx_oversize);
1083 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_jabber, &nsd->rx_jabber);
1086
433c47de
ASJ		 1087 /* FDIR stats */
1088 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1089 pf->stat_offsets_loaded,
1090 &osd->fd_atr_match, &nsd->fd_atr_match);
1091 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1092 pf->stat_offsets_loaded,
1093 &osd->fd_sb_match, &nsd->fd_sb_match);
1094
7812fddc
SN		 1095 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1096 nsd->tx_lpi_status =
1097 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1098 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1099 nsd->rx_lpi_status =
1100 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1101 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1102 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1103 pf->stat_offsets_loaded,
1104 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1105 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1106 pf->stat_offsets_loaded,
1107 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1108
41c445ff
JB		 1109 pf->stat_offsets_loaded = true;
1110}
1111
7812fddc
SN		 1112/**
1113 * i40e_update_stats - Update the various statistics counters.
1114 * @vsi: the VSI to be updated
1115 *
1116 * Update the various stats for this VSI and its related entities.
1117 **/
1118void i40e_update_stats(struct i40e_vsi *vsi)
1119{
1120 struct i40e_pf *pf = vsi->back;
1121
1122 if (vsi == pf->vsi[pf->lan_vsi])
1123 i40e_update_pf_stats(pf);
1124
1125 i40e_update_vsi_stats(vsi);
38e00438
VD		 1126#ifdef I40E_FCOE
1127 i40e_update_fcoe_stats(vsi);
1128#endif
7812fddc
SN		 1129}
1130
41c445ff
JB		 1131/**
1132 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1133 * @vsi: the VSI to be searched
1134 * @macaddr: the MAC address
1135 * @vlan: the vlan
1136 * @is_vf: make sure its a vf filter, else doesn't matter
1137 * @is_netdev: make sure its a netdev filter, else doesn't matter
1138 *
1139 * Returns ptr to the filter object or NULL
1140 **/
1141static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1142 u8 *macaddr, s16 vlan,
1143 bool is_vf, bool is_netdev)
1144{
1145 struct i40e_mac_filter *f;
1146
1147 if (!vsi || !macaddr)
1148 return NULL;
1149
1150 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1151 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1152 (vlan == f->vlan) &&
1153 (!is_vf || f->is_vf) &&
1154 (!is_netdev || f->is_netdev))
1155 return f;
1156 }
1157 return NULL;
1158}
1159
1160/**
1161 * i40e_find_mac - Find a mac addr in the macvlan filters list
1162 * @vsi: the VSI to be searched
1163 * @macaddr: the MAC address we are searching for
1164 * @is_vf: make sure its a vf filter, else doesn't matter
1165 * @is_netdev: make sure its a netdev filter, else doesn't matter
1166 *
1167 * Returns the first filter with the provided MAC address or NULL if
1168 * MAC address was not found
1169 **/
1170struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1171 bool is_vf, bool is_netdev)
1172{
1173 struct i40e_mac_filter *f;
1174
1175 if (!vsi || !macaddr)
1176 return NULL;
1177
1178 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1179 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1180 (!is_vf || f->is_vf) &&
1181 (!is_netdev || f->is_netdev))
1182 return f;
1183 }
1184 return NULL;
1185}
1186
1187/**
1188 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1189 * @vsi: the VSI to be searched
1190 *
1191 * Returns true if VSI is in vlan mode or false otherwise
1192 **/
1193bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1194{
1195 struct i40e_mac_filter *f;
1196
1197 /* Only -1 for all the filters denotes not in vlan mode
1198 * so we have to go through all the list in order to make sure
1199 */
1200 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1201 if (f->vlan >= 0)
1202 return true;
1203 }
1204
1205 return false;
1206}
1207
1208/**
1209 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1210 * @vsi: the VSI to be searched
1211 * @macaddr: the mac address to be filtered
1212 * @is_vf: true if it is a vf
1213 * @is_netdev: true if it is a netdev
1214 *
1215 * Goes through all the macvlan filters and adds a
1216 * macvlan filter for each unique vlan that already exists
1217 *
1218 * Returns first filter found on success, else NULL
1219 **/
1220struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1221 bool is_vf, bool is_netdev)
1222{
1223 struct i40e_mac_filter *f;
1224
1225 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1226 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1227 is_vf, is_netdev)) {
1228 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1229 is_vf, is_netdev))
41c445ff
JB		 1230 return NULL;
1231 }
1232 }
1233
1234 return list_first_entry_or_null(&vsi->mac_filter_list,
1235 struct i40e_mac_filter, list);
1236}
1237
8c27d42e
GR		 1238/**
1239 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1240 * @vsi: the PF Main VSI - inappropriate for any other VSI
1241 * @macaddr: the MAC address
30650cc5
SN		 1242 *
1243 * Some older firmware configurations set up a default promiscuous VLAN
1244 * filter that needs to be removed.
8c27d42e 1245 **/
30650cc5 1246static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1247{
1248 struct i40e_aqc_remove_macvlan_element_data element;
1249 struct i40e_pf *pf = vsi->back;
1250 i40e_status aq_ret;
1251
1252 /* Only appropriate for the PF main VSI */
1253 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1254 return -EINVAL;
8c27d42e 1255
30650cc5 1256 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1257 ether_addr_copy(element.mac_addr, macaddr);
1258 element.vlan_tag = 0;
1259 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1260 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1261 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1262 if (aq_ret)
30650cc5
SN		 1263 return -ENOENT;
1264
1265 return 0;
8c27d42e
GR		 1266}
1267
41c445ff
JB		 1268/**
1269 * i40e_add_filter - Add a mac/vlan filter to the VSI
1270 * @vsi: the VSI to be searched
1271 * @macaddr: the MAC address
1272 * @vlan: the vlan
1273 * @is_vf: make sure its a vf filter, else doesn't matter
1274 * @is_netdev: make sure its a netdev filter, else doesn't matter
1275 *
1276 * Returns ptr to the filter object or NULL when no memory available.
1277 **/
1278struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1279 u8 *macaddr, s16 vlan,
1280 bool is_vf, bool is_netdev)
1281{
1282 struct i40e_mac_filter *f;
1283
1284 if (!vsi || !macaddr)
1285 return NULL;
1286
1287 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1288 if (!f) {
1289 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1290 if (!f)
1291 goto add_filter_out;
1292
9a173901 1293 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1294 f->vlan = vlan;
1295 f->changed = true;
1296
1297 INIT_LIST_HEAD(&f->list);
1298 list_add(&f->list, &vsi->mac_filter_list);
1299 }
1300
1301 /* increment counter and add a new flag if needed */
1302 if (is_vf) {
1303 if (!f->is_vf) {
1304 f->is_vf = true;
1305 f->counter++;
1306 }
1307 } else if (is_netdev) {
1308 if (!f->is_netdev) {
1309 f->is_netdev = true;
1310 f->counter++;
1311 }
1312 } else {
1313 f->counter++;
1314 }
1315
1316 /* changed tells sync_filters_subtask to
1317 * push the filter down to the firmware
1318 */
1319 if (f->changed) {
1320 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1321 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1322 }
1323
1324add_filter_out:
1325 return f;
1326}
1327
1328/**
1329 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1330 * @vsi: the VSI to be searched
1331 * @macaddr: the MAC address
1332 * @vlan: the vlan
1333 * @is_vf: make sure it's a vf filter, else doesn't matter
1334 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1335 **/
1336void i40e_del_filter(struct i40e_vsi *vsi,
1337 u8 *macaddr, s16 vlan,
1338 bool is_vf, bool is_netdev)
1339{
1340 struct i40e_mac_filter *f;
1341
1342 if (!vsi || !macaddr)
1343 return;
1344
1345 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1346 if (!f || f->counter == 0)
1347 return;
1348
1349 if (is_vf) {
1350 if (f->is_vf) {
1351 f->is_vf = false;
1352 f->counter--;
1353 }
1354 } else if (is_netdev) {
1355 if (f->is_netdev) {
1356 f->is_netdev = false;
1357 f->counter--;
1358 }
1359 } else {
1360 /* make sure we don't remove a filter in use by vf or netdev */
1361 int min_f = 0;
1362 min_f += (f->is_vf ? 1 : 0);
1363 min_f += (f->is_netdev ? 1 : 0);
1364
1365 if (f->counter > min_f)
1366 f->counter--;
1367 }
1368
1369 /* counter == 0 tells sync_filters_subtask to
1370 * remove the filter from the firmware's list
1371 */
1372 if (f->counter == 0) {
1373 f->changed = true;
1374 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1375 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1376 }
1377}
1378
1379/**
1380 * i40e_set_mac - NDO callback to set mac address
1381 * @netdev: network interface device structure
1382 * @p: pointer to an address structure
1383 *
1384 * Returns 0 on success, negative on failure
1385 **/
38e00438
VD		 1386#ifdef I40E_FCOE
1387int i40e_set_mac(struct net_device *netdev, void *p)
1388#else
41c445ff 1389static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1390#endif
41c445ff
JB		 1391{
1392 struct i40e_netdev_priv *np = netdev_priv(netdev);
1393 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1394 struct i40e_pf *pf = vsi->back;
1395 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1396 struct sockaddr *addr = p;
1397 struct i40e_mac_filter *f;
1398
1399 if (!is_valid_ether_addr(addr->sa_data))
1400 return -EADDRNOTAVAIL;
1401
30650cc5
SN		 1402 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1403 netdev_info(netdev, "already using mac address %pM\n",
1404 addr->sa_data);
1405 return 0;
1406 }
41c445ff 1407
80f6428f
ASJ		 1408 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1409 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1410 return -EADDRNOTAVAIL;
1411
30650cc5
SN		 1412 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1413 netdev_info(netdev, "returning to hw mac address %pM\n",
1414 hw->mac.addr);
1415 else
1416 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1417
41c445ff
JB		 1418 if (vsi->type == I40E_VSI_MAIN) {
1419 i40e_status ret;
1420 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1421 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1422 addr->sa_data, NULL);
1423 if (ret) {
1424 netdev_info(netdev,
1425 "Addr change for Main VSI failed: %d\n",
1426 ret);
1427 return -EADDRNOTAVAIL;
1428 }
41c445ff
JB		 1429 }
1430
30650cc5
SN		 1431 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1432 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1433
30650cc5
SN		 1434 memset(&element, 0, sizeof(element));
1435 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1436 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1437 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1438 } else {
6c8ad1ba
SN		 1439 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1440 false, false);
6c8ad1ba 1441 }
41c445ff 1442
30650cc5
SN		 1443 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1444 struct i40e_aqc_add_macvlan_element_data element;
1445
1446 memset(&element, 0, sizeof(element));
1447 ether_addr_copy(element.mac_addr, hw->mac.addr);
1448 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1449 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1450 } else {
1451 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1452 false, false);
1453 if (f)
1454 f->is_laa = true;
1455 }
1456
1457 i40e_sync_vsi_filters(vsi);
1458 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1459
1460 return 0;
1461}
1462
1463/**
1464 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1465 * @vsi: the VSI being setup
1466 * @ctxt: VSI context structure
1467 * @enabled_tc: Enabled TCs bitmap
1468 * @is_add: True if called before Add VSI
1469 *
1470 * Setup VSI queue mapping for enabled traffic classes.
1471 **/
38e00438
VD		 1472#ifdef I40E_FCOE
1473void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1474 struct i40e_vsi_context *ctxt,
1475 u8 enabled_tc,
1476 bool is_add)
1477#else
41c445ff
JB		 1478static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1479 struct i40e_vsi_context *ctxt,
1480 u8 enabled_tc,
1481 bool is_add)
38e00438 1482#endif
41c445ff
JB		 1483{
1484 struct i40e_pf *pf = vsi->back;
1485 u16 sections = 0;
1486 u8 netdev_tc = 0;
1487 u16 numtc = 0;
1488 u16 qcount;
1489 u8 offset;
1490 u16 qmap;
1491 int i;
4e3b35b0 1492 u16 num_tc_qps = 0;
41c445ff
JB		 1493
1494 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1495 offset = 0;
1496
1497 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1498 /* Find numtc from enabled TC bitmap */
1499 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1500 if (enabled_tc & (1 << i)) /* TC is enabled */
1501 numtc++;
1502 }
1503 if (!numtc) {
1504 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1505 numtc = 1;
1506 }
1507 } else {
1508 /* At least TC0 is enabled in case of non-DCB case */
1509 numtc = 1;
1510 }
1511
1512 vsi->tc_config.numtc = numtc;
1513 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1514 /* Number of queues per enabled TC */
eb051afe 1515 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1516 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1517
1518 /* Setup queue offset/count for all TCs for given VSI */
1519 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1520 /* See if the given TC is enabled for the given VSI */
1521 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1522 int pow, num_qps;
1523
41c445ff
JB		 1524 switch (vsi->type) {
1525 case I40E_VSI_MAIN:
4e3b35b0 1526 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1527 break;
38e00438
VD		 1528#ifdef I40E_FCOE
1529 case I40E_VSI_FCOE:
1530 qcount = num_tc_qps;
1531 break;
1532#endif
41c445ff
JB		 1533 case I40E_VSI_FDIR:
1534 case I40E_VSI_SRIOV:
1535 case I40E_VSI_VMDQ2:
1536 default:
4e3b35b0 1537 qcount = num_tc_qps;
41c445ff
JB		 1538 WARN_ON(i != 0);
1539 break;
1540 }
4e3b35b0
NP		 1541 vsi->tc_config.tc_info[i].qoffset = offset;
1542 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1543
1544 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1545 num_qps = qcount;
41c445ff 1546 pow = 0;
4e3b35b0 1547 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1548 pow++;
1549 num_qps >>= 1;
1550 }
1551
1552 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1553 qmap =
1554 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1555 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1556
4e3b35b0 1557 offset += qcount;
41c445ff
JB		 1558 } else {
1559 /* TC is not enabled so set the offset to
1560 * default queue and allocate one queue
1561 * for the given TC.
1562 */
1563 vsi->tc_config.tc_info[i].qoffset = 0;
1564 vsi->tc_config.tc_info[i].qcount = 1;
1565 vsi->tc_config.tc_info[i].netdev_tc = 0;
1566
1567 qmap = 0;
1568 }
1569 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1570 }
1571
1572 /* Set actual Tx/Rx queue pairs */
1573 vsi->num_queue_pairs = offset;
1574
1575 /* Scheduler section valid can only be set for ADD VSI */
1576 if (is_add) {
1577 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1578
1579 ctxt->info.up_enable_bits = enabled_tc;
1580 }
1581 if (vsi->type == I40E_VSI_SRIOV) {
1582 ctxt->info.mapping_flags |=
1583 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1584 for (i = 0; i < vsi->num_queue_pairs; i++)
1585 ctxt->info.queue_mapping[i] =
1586 cpu_to_le16(vsi->base_queue + i);
1587 } else {
1588 ctxt->info.mapping_flags |=
1589 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1590 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1591 }
1592 ctxt->info.valid_sections |= cpu_to_le16(sections);
1593}
1594
1595/**
1596 * i40e_set_rx_mode - NDO callback to set the netdev filters
1597 * @netdev: network interface device structure
1598 **/
38e00438
VD		 1599#ifdef I40E_FCOE
1600void i40e_set_rx_mode(struct net_device *netdev)
1601#else
41c445ff 1602static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1603#endif
41c445ff
JB		 1604{
1605 struct i40e_netdev_priv *np = netdev_priv(netdev);
1606 struct i40e_mac_filter *f, *ftmp;
1607 struct i40e_vsi *vsi = np->vsi;
1608 struct netdev_hw_addr *uca;
1609 struct netdev_hw_addr *mca;
1610 struct netdev_hw_addr *ha;
1611
1612 /* add addr if not already in the filter list */
1613 netdev_for_each_uc_addr(uca, netdev) {
1614 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1615 if (i40e_is_vsi_in_vlan(vsi))
1616 i40e_put_mac_in_vlan(vsi, uca->addr,
1617 false, true);
1618 else
1619 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1620 false, true);
1621 }
1622 }
1623
1624 netdev_for_each_mc_addr(mca, netdev) {
1625 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1626 if (i40e_is_vsi_in_vlan(vsi))
1627 i40e_put_mac_in_vlan(vsi, mca->addr,
1628 false, true);
1629 else
1630 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1631 false, true);
1632 }
1633 }
1634
1635 /* remove filter if not in netdev list */
1636 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1637 bool found = false;
1638
1639 if (!f->is_netdev)
1640 continue;
1641
1642 if (is_multicast_ether_addr(f->macaddr)) {
1643 netdev_for_each_mc_addr(mca, netdev) {
1644 if (ether_addr_equal(mca->addr, f->macaddr)) {
1645 found = true;
1646 break;
1647 }
1648 }
1649 } else {
1650 netdev_for_each_uc_addr(uca, netdev) {
1651 if (ether_addr_equal(uca->addr, f->macaddr)) {
1652 found = true;
1653 break;
1654 }
1655 }
1656
1657 for_each_dev_addr(netdev, ha) {
1658 if (ether_addr_equal(ha->addr, f->macaddr)) {
1659 found = true;
1660 break;
1661 }
1662 }
1663 }
1664 if (!found)
1665 i40e_del_filter(
1666 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1667 }
1668
1669 /* check for other flag changes */
1670 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1671 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1672 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1673 }
1674}
1675
1676/**
1677 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1678 * @vsi: ptr to the VSI
1679 *
1680 * Push any outstanding VSI filter changes through the AdminQ.
1681 *
1682 * Returns 0 or error value
1683 **/
1684int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1685{
1686 struct i40e_mac_filter *f, *ftmp;
1687 bool promisc_forced_on = false;
1688 bool add_happened = false;
1689 int filter_list_len = 0;
1690 u32 changed_flags = 0;
dcae29be 1691 i40e_status aq_ret = 0;
41c445ff
JB		 1692 struct i40e_pf *pf;
1693 int num_add = 0;
1694 int num_del = 0;
1695 u16 cmd_flags;
1696
1697 /* empty array typed pointers, kcalloc later */
1698 struct i40e_aqc_add_macvlan_element_data *add_list;
1699 struct i40e_aqc_remove_macvlan_element_data *del_list;
1700
1701 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1702 usleep_range(1000, 2000);
1703 pf = vsi->back;
1704
1705 if (vsi->netdev) {
1706 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1707 vsi->current_netdev_flags = vsi->netdev->flags;
1708 }
1709
1710 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1711 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1712
1713 filter_list_len = pf->hw.aq.asq_buf_size /
1714 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1715 del_list = kcalloc(filter_list_len,
1716 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1717 GFP_KERNEL);
1718 if (!del_list)
1719 return -ENOMEM;
1720
1721 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1722 if (!f->changed)
1723 continue;
1724
1725 if (f->counter != 0)
1726 continue;
1727 f->changed = false;
1728 cmd_flags = 0;
1729
1730 /* add to delete list */
9a173901 1731 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1732 del_list[num_del].vlan_tag =
1733 cpu_to_le16((u16)(f->vlan ==
1734 I40E_VLAN_ANY ? 0 : f->vlan));
1735
41c445ff
JB		 1736 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1737 del_list[num_del].flags = cmd_flags;
1738 num_del++;
1739
1740 /* unlink from filter list */
1741 list_del(&f->list);
1742 kfree(f);
1743
1744 /* flush a full buffer */
1745 if (num_del == filter_list_len) {
dcae29be 1746 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1747 vsi->seid, del_list, num_del,
1748 NULL);
1749 num_del = 0;
1750 memset(del_list, 0, sizeof(*del_list));
1751
fdfe9cbe
SN		 1752 if (aq_ret &&
1753 pf->hw.aq.asq_last_status !=
1754 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1755 dev_info(&pf->pdev->dev,
1756 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1757 aq_ret,
41c445ff
JB		 1758 pf->hw.aq.asq_last_status);
1759 }
1760 }
1761 if (num_del) {
dcae29be 1762 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1763 del_list, num_del, NULL);
1764 num_del = 0;
1765
fdfe9cbe
SN		 1766 if (aq_ret &&
1767 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1768 dev_info(&pf->pdev->dev,
1769 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1770 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1771 }
1772
1773 kfree(del_list);
1774 del_list = NULL;
1775
1776 /* do all the adds now */
1777 filter_list_len = pf->hw.aq.asq_buf_size /
1778 sizeof(struct i40e_aqc_add_macvlan_element_data),
1779 add_list = kcalloc(filter_list_len,
1780 sizeof(struct i40e_aqc_add_macvlan_element_data),
1781 GFP_KERNEL);
1782 if (!add_list)
1783 return -ENOMEM;
1784
1785 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1786 if (!f->changed)
1787 continue;
1788
1789 if (f->counter == 0)
1790 continue;
1791 f->changed = false;
1792 add_happened = true;
1793 cmd_flags = 0;
1794
1795 /* add to add array */
9a173901 1796 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1797 add_list[num_add].vlan_tag =
1798 cpu_to_le16(
1799 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1800 add_list[num_add].queue_number = 0;
1801
1802 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1803 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1804 num_add++;
1805
1806 /* flush a full buffer */
1807 if (num_add == filter_list_len) {
dcae29be
JB		 1808 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1809 add_list, num_add,
1810 NULL);
41c445ff
JB		 1811 num_add = 0;
1812
dcae29be 1813 if (aq_ret)
41c445ff
JB		 1814 break;
1815 memset(add_list, 0, sizeof(*add_list));
1816 }
1817 }
1818 if (num_add) {
dcae29be
JB		 1819 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1820 add_list, num_add, NULL);
41c445ff
JB		 1821 num_add = 0;
1822 }
1823 kfree(add_list);
1824 add_list = NULL;
1825
30650cc5
SN		 1826 if (add_happened && aq_ret &&
1827 pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
41c445ff
JB		 1828 dev_info(&pf->pdev->dev,
1829 "add filter failed, err %d, aq_err %d\n",
dcae29be 1830 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1831 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1832 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1833 &vsi->state)) {
1834 promisc_forced_on = true;
1835 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1836 &vsi->state);
1837 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1838 }
1839 }
1840 }
1841
1842 /* check for changes in promiscuous modes */
1843 if (changed_flags & IFF_ALLMULTI) {
1844 bool cur_multipromisc;
1845 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1846 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1847 vsi->seid,
1848 cur_multipromisc,
1849 NULL);
1850 if (aq_ret)
41c445ff
JB		 1851 dev_info(&pf->pdev->dev,
1852 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1853 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1854 }
1855 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1856 bool cur_promisc;
1857 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1858 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1859 &vsi->state));
dcae29be
JB		 1860 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1861 vsi->seid,
1862 cur_promisc, NULL);
1863 if (aq_ret)
41c445ff
JB		 1864 dev_info(&pf->pdev->dev,
1865 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1866 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1867 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1868 vsi->seid,
1869 cur_promisc, NULL);
1870 if (aq_ret)
1871 dev_info(&pf->pdev->dev,
1872 "set brdcast promisc failed, err %d, aq_err %d\n",
1873 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1874 }
1875
1876 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1877 return 0;
1878}
1879
1880/**
1881 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1882 * @pf: board private structure
1883 **/
1884static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1885{
1886 int v;
1887
1888 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1889 return;
1890 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1891
505682cd 1892 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1893 if (pf->vsi[v] &&
1894 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1895 i40e_sync_vsi_filters(pf->vsi[v]);
1896 }
1897}
1898
1899/**
1900 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1901 * @netdev: network interface device structure
1902 * @new_mtu: new value for maximum frame size
1903 *
1904 * Returns 0 on success, negative on failure
1905 **/
1906static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1907{
1908 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1909 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1910 struct i40e_vsi *vsi = np->vsi;
1911
1912 /* MTU < 68 is an error and causes problems on some kernels */
1913 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1914 return -EINVAL;
1915
1916 netdev_info(netdev, "changing MTU from %d to %d\n",
1917 netdev->mtu, new_mtu);
1918 netdev->mtu = new_mtu;
1919 if (netif_running(netdev))
1920 i40e_vsi_reinit_locked(vsi);
1921
1922 return 0;
1923}
1924
beb0dff1
JK		 1925/**
1926 * i40e_ioctl - Access the hwtstamp interface
1927 * @netdev: network interface device structure
1928 * @ifr: interface request data
1929 * @cmd: ioctl command
1930 **/
1931int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1932{
1933 struct i40e_netdev_priv *np = netdev_priv(netdev);
1934 struct i40e_pf *pf = np->vsi->back;
1935
1936 switch (cmd) {
1937 case SIOCGHWTSTAMP:
1938 return i40e_ptp_get_ts_config(pf, ifr);
1939 case SIOCSHWTSTAMP:
1940 return i40e_ptp_set_ts_config(pf, ifr);
1941 default:
1942 return -EOPNOTSUPP;
1943 }
1944}
1945
41c445ff
JB		 1946/**
1947 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1948 * @vsi: the vsi being adjusted
1949 **/
1950void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1951{
1952 struct i40e_vsi_context ctxt;
1953 i40e_status ret;
1954
1955 if ((vsi->info.valid_sections &
1956 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1957 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1958 return; /* already enabled */
1959
1960 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1961 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1962 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1963
1964 ctxt.seid = vsi->seid;
1965 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1966 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1967 if (ret) {
1968 dev_info(&vsi->back->pdev->dev,
1969 "%s: update vsi failed, aq_err=%d\n",
1970 __func__, vsi->back->hw.aq.asq_last_status);
1971 }
1972}
1973
1974/**
1975 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1976 * @vsi: the vsi being adjusted
1977 **/
1978void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1979{
1980 struct i40e_vsi_context ctxt;
1981 i40e_status ret;
1982
1983 if ((vsi->info.valid_sections &
1984 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1985 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1986 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1987 return; /* already disabled */
1988
1989 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1990 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1991 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1992
1993 ctxt.seid = vsi->seid;
1994 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1995 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1996 if (ret) {
1997 dev_info(&vsi->back->pdev->dev,
1998 "%s: update vsi failed, aq_err=%d\n",
1999 __func__, vsi->back->hw.aq.asq_last_status);
2000 }
2001}
2002
2003/**
2004 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2005 * @netdev: network interface to be adjusted
2006 * @features: netdev features to test if VLAN offload is enabled or not
2007 **/
2008static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2009{
2010 struct i40e_netdev_priv *np = netdev_priv(netdev);
2011 struct i40e_vsi *vsi = np->vsi;
2012
2013 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2014 i40e_vlan_stripping_enable(vsi);
2015 else
2016 i40e_vlan_stripping_disable(vsi);
2017}
2018
2019/**
2020 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2021 * @vsi: the vsi being configured
2022 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2023 **/
2024int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2025{
2026 struct i40e_mac_filter *f, *add_f;
2027 bool is_netdev, is_vf;
41c445ff
JB		 2028
2029 is_vf = (vsi->type == I40E_VSI_SRIOV);
2030 is_netdev = !!(vsi->netdev);
2031
2032 if (is_netdev) {
2033 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2034 is_vf, is_netdev);
2035 if (!add_f) {
2036 dev_info(&vsi->back->pdev->dev,
2037 "Could not add vlan filter %d for %pM\n",
2038 vid, vsi->netdev->dev_addr);
2039 return -ENOMEM;
2040 }
2041 }
2042
2043 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2044 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2045 if (!add_f) {
2046 dev_info(&vsi->back->pdev->dev,
2047 "Could not add vlan filter %d for %pM\n",
2048 vid, f->macaddr);
2049 return -ENOMEM;
2050 }
2051 }
2052
41c445ff
JB		 2053 /* Now if we add a vlan tag, make sure to check if it is the first
2054 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2055 * with 0, so we now accept untagged and specified tagged traffic
2056 * (and not any taged and untagged)
2057 */
2058 if (vid > 0) {
2059 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2060 I40E_VLAN_ANY,
2061 is_vf, is_netdev)) {
2062 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2063 I40E_VLAN_ANY, is_vf, is_netdev);
2064 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2065 is_vf, is_netdev);
2066 if (!add_f) {
2067 dev_info(&vsi->back->pdev->dev,
2068 "Could not add filter 0 for %pM\n",
2069 vsi->netdev->dev_addr);
2070 return -ENOMEM;
2071 }
2072 }
8d82a7c5 2073 }
41c445ff 2074
8d82a7c5
GR		 2075 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2076 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2077 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2078 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2079 is_vf, is_netdev)) {
2080 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2081 is_vf, is_netdev);
2082 add_f = i40e_add_filter(vsi, f->macaddr,
2083 0, is_vf, is_netdev);
2084 if (!add_f) {
2085 dev_info(&vsi->back->pdev->dev,
2086 "Could not add filter 0 for %pM\n",
2087 f->macaddr);
2088 return -ENOMEM;
2089 }
2090 }
2091 }
41c445ff
JB		 2092 }
2093
80f6428f
ASJ		 2094 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2095 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2096 return 0;
2097
2098 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2099}
2100
2101/**
2102 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2103 * @vsi: the vsi being configured
2104 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2105 *
2106 * Return: 0 on success or negative otherwise
41c445ff
JB		 2107 **/
2108int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2109{
2110 struct net_device *netdev = vsi->netdev;
2111 struct i40e_mac_filter *f, *add_f;
2112 bool is_vf, is_netdev;
2113 int filter_count = 0;
41c445ff
JB		 2114
2115 is_vf = (vsi->type == I40E_VSI_SRIOV);
2116 is_netdev = !!(netdev);
2117
2118 if (is_netdev)
2119 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2120
2121 list_for_each_entry(f, &vsi->mac_filter_list, list)
2122 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2123
41c445ff
JB		 2124 /* go through all the filters for this VSI and if there is only
2125 * vid == 0 it means there are no other filters, so vid 0 must
2126 * be replaced with -1. This signifies that we should from now
2127 * on accept any traffic (with any tag present, or untagged)
2128 */
2129 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2130 if (is_netdev) {
2131 if (f->vlan &&
2132 ether_addr_equal(netdev->dev_addr, f->macaddr))
2133 filter_count++;
2134 }
2135
2136 if (f->vlan)
2137 filter_count++;
2138 }
2139
2140 if (!filter_count && is_netdev) {
2141 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2142 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2143 is_vf, is_netdev);
2144 if (!f) {
2145 dev_info(&vsi->back->pdev->dev,
2146 "Could not add filter %d for %pM\n",
2147 I40E_VLAN_ANY, netdev->dev_addr);
2148 return -ENOMEM;
2149 }
2150 }
2151
2152 if (!filter_count) {
2153 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2154 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2155 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2156 is_vf, is_netdev);
2157 if (!add_f) {
2158 dev_info(&vsi->back->pdev->dev,
2159 "Could not add filter %d for %pM\n",
2160 I40E_VLAN_ANY, f->macaddr);
2161 return -ENOMEM;
2162 }
2163 }
2164 }
2165
80f6428f
ASJ		 2166 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2167 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2168 return 0;
2169
41c445ff
JB		 2170 return i40e_sync_vsi_filters(vsi);
2171}
2172
2173/**
2174 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2175 * @netdev: network interface to be adjusted
2176 * @vid: vlan id to be added
078b5876
JB		 2177 *
2178 * net_device_ops implementation for adding vlan ids
41c445ff 2179 **/
38e00438
VD		 2180#ifdef I40E_FCOE
2181int i40e_vlan_rx_add_vid(struct net_device *netdev,
2182 __always_unused __be16 proto, u16 vid)
2183#else
41c445ff
JB		 2184static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2185 __always_unused __be16 proto, u16 vid)
38e00438 2186#endif
41c445ff
JB		 2187{
2188 struct i40e_netdev_priv *np = netdev_priv(netdev);
2189 struct i40e_vsi *vsi = np->vsi;
078b5876 2190 int ret = 0;
41c445ff
JB		 2191
2192 if (vid > 4095)
078b5876
JB		 2193 return -EINVAL;
2194
2195 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2196
6982d429
ASJ		 2197 /* If the network stack called us with vid = 0 then
2198 * it is asking to receive priority tagged packets with
2199 * vlan id 0. Our HW receives them by default when configured
2200 * to receive untagged packets so there is no need to add an
2201 * extra filter for vlan 0 tagged packets.
41c445ff 2202 */
6982d429
ASJ		 2203 if (vid)
2204 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2205
078b5876
JB		 2206 if (!ret && (vid < VLAN_N_VID))
2207 set_bit(vid, vsi->active_vlans);
41c445ff 2208
078b5876 2209 return ret;
41c445ff
JB		 2210}
2211
2212/**
2213 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2214 * @netdev: network interface to be adjusted
2215 * @vid: vlan id to be removed
078b5876 2216 *
fdfd943e 2217 * net_device_ops implementation for removing vlan ids
41c445ff 2218 **/
38e00438
VD		 2219#ifdef I40E_FCOE
2220int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2221 __always_unused __be16 proto, u16 vid)
2222#else
41c445ff
JB		 2223static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2224 __always_unused __be16 proto, u16 vid)
38e00438 2225#endif
41c445ff
JB		 2226{
2227 struct i40e_netdev_priv *np = netdev_priv(netdev);
2228 struct i40e_vsi *vsi = np->vsi;
2229
078b5876
JB		 2230 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2231
41c445ff
JB		 2232 /* return code is ignored as there is nothing a user
2233 * can do about failure to remove and a log message was
078b5876 2234 * already printed from the other function
41c445ff
JB		 2235 */
2236 i40e_vsi_kill_vlan(vsi, vid);
2237
2238 clear_bit(vid, vsi->active_vlans);
078b5876 2239
41c445ff
JB		 2240 return 0;
2241}
2242
2243/**
2244 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2245 * @vsi: the vsi being brought back up
2246 **/
2247static void i40e_restore_vlan(struct i40e_vsi *vsi)
2248{
2249 u16 vid;
2250
2251 if (!vsi->netdev)
2252 return;
2253
2254 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2255
2256 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2257 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2258 vid);
2259}
2260
2261/**
2262 * i40e_vsi_add_pvid - Add pvid for the VSI
2263 * @vsi: the vsi being adjusted
2264 * @vid: the vlan id to set as a PVID
2265 **/
dcae29be 2266int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2267{
2268 struct i40e_vsi_context ctxt;
dcae29be 2269 i40e_status aq_ret;
41c445ff
JB		 2270
2271 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2272 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2273 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2274 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2275 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2276
2277 ctxt.seid = vsi->seid;
2278 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2279 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2280 if (aq_ret) {
41c445ff
JB		 2281 dev_info(&vsi->back->pdev->dev,
2282 "%s: update vsi failed, aq_err=%d\n",
2283 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2284 return -ENOENT;
41c445ff
JB		 2285 }
2286
dcae29be 2287 return 0;
41c445ff
JB		 2288}
2289
2290/**
2291 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2292 * @vsi: the vsi being adjusted
2293 *
2294 * Just use the vlan_rx_register() service to put it back to normal
2295 **/
2296void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2297{
6c12fcbf
GR		 2298 i40e_vlan_stripping_disable(vsi);
2299
41c445ff 2300 vsi->info.pvid = 0;
41c445ff
JB		 2301}
2302
2303/**
2304 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2305 * @vsi: ptr to the VSI
2306 *
2307 * If this function returns with an error, then it's possible one or
2308 * more of the rings is populated (while the rest are not). It is the
2309 * callers duty to clean those orphaned rings.
2310 *
2311 * Return 0 on success, negative on failure
2312 **/
2313static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2314{
2315 int i, err = 0;
2316
2317 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2318 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2319
2320 return err;
2321}
2322
2323/**
2324 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2325 * @vsi: ptr to the VSI
2326 *
2327 * Free VSI's transmit software resources
2328 **/
2329static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2330{
2331 int i;
2332
8e9dca53
GR		 2333 if (!vsi->tx_rings)
2334 return;
2335
41c445ff 2336 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2337 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2338 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2339}
2340
2341/**
2342 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2343 * @vsi: ptr to the VSI
2344 *
2345 * If this function returns with an error, then it's possible one or
2346 * more of the rings is populated (while the rest are not). It is the
2347 * callers duty to clean those orphaned rings.
2348 *
2349 * Return 0 on success, negative on failure
2350 **/
2351static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2352{
2353 int i, err = 0;
2354
2355 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2356 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2357#ifdef I40E_FCOE
2358 i40e_fcoe_setup_ddp_resources(vsi);
2359#endif
41c445ff
JB		 2360 return err;
2361}
2362
2363/**
2364 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2365 * @vsi: ptr to the VSI
2366 *
2367 * Free all receive software resources
2368 **/
2369static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2370{
2371 int i;
2372
8e9dca53
GR		 2373 if (!vsi->rx_rings)
2374 return;
2375
41c445ff 2376 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2377 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2378 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2379#ifdef I40E_FCOE
2380 i40e_fcoe_free_ddp_resources(vsi);
2381#endif
41c445ff
JB		 2382}
2383
2384/**
2385 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2386 * @ring: The Tx ring to configure
2387 *
2388 * Configure the Tx descriptor ring in the HMC context.
2389 **/
2390static int i40e_configure_tx_ring(struct i40e_ring *ring)
2391{
2392 struct i40e_vsi *vsi = ring->vsi;
2393 u16 pf_q = vsi->base_queue + ring->queue_index;
2394 struct i40e_hw *hw = &vsi->back->hw;
2395 struct i40e_hmc_obj_txq tx_ctx;
2396 i40e_status err = 0;
2397 u32 qtx_ctl = 0;
2398
2399 /* some ATR related tx ring init */
60ea5f83 2400 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2401 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2402 ring->atr_count = 0;
2403 } else {
2404 ring->atr_sample_rate = 0;
2405 }
2406
2407 /* initialize XPS */
2408 if (ring->q_vector && ring->netdev &&
4e3b35b0 2409 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2410 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2411 netif_set_xps_queue(ring->netdev,
2412 &ring->q_vector->affinity_mask,
2413 ring->queue_index);
2414
2415 /* clear the context structure first */
2416 memset(&tx_ctx, 0, sizeof(tx_ctx));
2417
2418 tx_ctx.new_context = 1;
2419 tx_ctx.base = (ring->dma / 128);
2420 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2421 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2422 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2423#ifdef I40E_FCOE
2424 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2425#endif
beb0dff1 2426 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2427 /* FDIR VSI tx ring can still use RS bit and writebacks */
2428 if (vsi->type != I40E_VSI_FDIR)
2429 tx_ctx.head_wb_ena = 1;
2430 tx_ctx.head_wb_addr = ring->dma +
2431 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2432
2433 /* As part of VSI creation/update, FW allocates certain
2434 * Tx arbitration queue sets for each TC enabled for
2435 * the VSI. The FW returns the handles to these queue
2436 * sets as part of the response buffer to Add VSI,
2437 * Update VSI, etc. AQ commands. It is expected that
2438 * these queue set handles be associated with the Tx
2439 * queues by the driver as part of the TX queue context
2440 * initialization. This has to be done regardless of
2441 * DCB as by default everything is mapped to TC0.
2442 */
2443 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2444 tx_ctx.rdylist_act = 0;
2445
2446 /* clear the context in the HMC */
2447 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2448 if (err) {
2449 dev_info(&vsi->back->pdev->dev,
2450 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2451 ring->queue_index, pf_q, err);
2452 return -ENOMEM;
2453 }
2454
2455 /* set the context in the HMC */
2456 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2457 if (err) {
2458 dev_info(&vsi->back->pdev->dev,
2459 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2460 ring->queue_index, pf_q, err);
2461 return -ENOMEM;
2462 }
2463
2464 /* Now associate this queue with this PCI function */
7a28d885 2465 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2466 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2467 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2468 I40E_QTX_CTL_VFVM_INDX_MASK;
2469 } else {
9d8bf547 2470 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2471 }
2472
13fd9774
SN		 2473 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2474 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2475 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2476 i40e_flush(hw);
2477
2478 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2479
2480 /* cache tail off for easier writes later */
2481 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2482
2483 return 0;
2484}
2485
2486/**
2487 * i40e_configure_rx_ring - Configure a receive ring context
2488 * @ring: The Rx ring to configure
2489 *
2490 * Configure the Rx descriptor ring in the HMC context.
2491 **/
2492static int i40e_configure_rx_ring(struct i40e_ring *ring)
2493{
2494 struct i40e_vsi *vsi = ring->vsi;
2495 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2496 u16 pf_q = vsi->base_queue + ring->queue_index;
2497 struct i40e_hw *hw = &vsi->back->hw;
2498 struct i40e_hmc_obj_rxq rx_ctx;
2499 i40e_status err = 0;
2500
2501 ring->state = 0;
2502
2503 /* clear the context structure first */
2504 memset(&rx_ctx, 0, sizeof(rx_ctx));
2505
2506 ring->rx_buf_len = vsi->rx_buf_len;
2507 ring->rx_hdr_len = vsi->rx_hdr_len;
2508
2509 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2510 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2511
2512 rx_ctx.base = (ring->dma / 128);
2513 rx_ctx.qlen = ring->count;
2514
2515 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2516 set_ring_16byte_desc_enabled(ring);
2517 rx_ctx.dsize = 0;
2518 } else {
2519 rx_ctx.dsize = 1;
2520 }
2521
2522 rx_ctx.dtype = vsi->dtype;
2523 if (vsi->dtype) {
2524 set_ring_ps_enabled(ring);
2525 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2526 I40E_RX_SPLIT_IP |
2527 I40E_RX_SPLIT_TCP_UDP |
2528 I40E_RX_SPLIT_SCTP;
2529 } else {
2530 rx_ctx.hsplit_0 = 0;
2531 }
2532
2533 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2534 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2535 if (hw->revision_id == 0)
2536 rx_ctx.lrxqthresh = 0;
2537 else
2538 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2539 rx_ctx.crcstrip = 1;
2540 rx_ctx.l2tsel = 1;
2541 rx_ctx.showiv = 1;
38e00438
VD		 2542#ifdef I40E_FCOE
2543 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2544#endif
acb3676b
CS		 2545 /* set the prefena field to 1 because the manual says to */
2546 rx_ctx.prefena = 1;
41c445ff
JB		 2547
2548 /* clear the context in the HMC */
2549 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2550 if (err) {
2551 dev_info(&vsi->back->pdev->dev,
2552 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2553 ring->queue_index, pf_q, err);
2554 return -ENOMEM;
2555 }
2556
2557 /* set the context in the HMC */
2558 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2559 if (err) {
2560 dev_info(&vsi->back->pdev->dev,
2561 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2562 ring->queue_index, pf_q, err);
2563 return -ENOMEM;
2564 }
2565
2566 /* cache tail for quicker writes, and clear the reg before use */
2567 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2568 writel(0, ring->tail);
2569
2570 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2571
2572 return 0;
2573}
2574
2575/**
2576 * i40e_vsi_configure_tx - Configure the VSI for Tx
2577 * @vsi: VSI structure describing this set of rings and resources
2578 *
2579 * Configure the Tx VSI for operation.
2580 **/
2581static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2582{
2583 int err = 0;
2584 u16 i;
2585
9f65e15b
AD		 2586 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2587 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2588
2589 return err;
2590}
2591
2592/**
2593 * i40e_vsi_configure_rx - Configure the VSI for Rx
2594 * @vsi: the VSI being configured
2595 *
2596 * Configure the Rx VSI for operation.
2597 **/
2598static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2599{
2600 int err = 0;
2601 u16 i;
2602
2603 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2604 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2605 + ETH_FCS_LEN + VLAN_HLEN;
2606 else
2607 vsi->max_frame = I40E_RXBUFFER_2048;
2608
2609 /* figure out correct receive buffer length */
2610 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2611 I40E_FLAG_RX_PS_ENABLED)) {
2612 case I40E_FLAG_RX_1BUF_ENABLED:
2613 vsi->rx_hdr_len = 0;
2614 vsi->rx_buf_len = vsi->max_frame;
2615 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2616 break;
2617 case I40E_FLAG_RX_PS_ENABLED:
2618 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2619 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2620 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2621 break;
2622 default:
2623 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2624 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2625 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2626 break;
2627 }
2628
38e00438
VD		 2629#ifdef I40E_FCOE
2630 /* setup rx buffer for FCoE */
2631 if ((vsi->type == I40E_VSI_FCOE) &&
2632 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2633 vsi->rx_hdr_len = 0;
2634 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2635 vsi->max_frame = I40E_RXBUFFER_3072;
2636 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2637 }
2638
2639#endif /* I40E_FCOE */
41c445ff
JB		 2640 /* round up for the chip's needs */
2641 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2642 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2643 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2644 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2645
2646 /* set up individual rings */
2647 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2648 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2649
2650 return err;
2651}
2652
2653/**
2654 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2655 * @vsi: ptr to the VSI
2656 **/
2657static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2658{
e7046ee1 2659 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2660 u16 qoffset, qcount;
2661 int i, n;
2662
2663 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2664 return;
2665
2666 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2667 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2668 continue;
2669
2670 qoffset = vsi->tc_config.tc_info[n].qoffset;
2671 qcount = vsi->tc_config.tc_info[n].qcount;
2672 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2673 rx_ring = vsi->rx_rings[i];
2674 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2675 rx_ring->dcb_tc = n;
2676 tx_ring->dcb_tc = n;
2677 }
2678 }
2679}
2680
2681/**
2682 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2683 * @vsi: ptr to the VSI
2684 **/
2685static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2686{
2687 if (vsi->netdev)
2688 i40e_set_rx_mode(vsi->netdev);
2689}
2690
17a73f6b
JG		 2691/**
2692 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2693 * @vsi: Pointer to the targeted VSI
2694 *
2695 * This function replays the hlist on the hw where all the SB Flow Director
2696 * filters were saved.
2697 **/
2698static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2699{
2700 struct i40e_fdir_filter *filter;
2701 struct i40e_pf *pf = vsi->back;
2702 struct hlist_node *node;
2703
55a5e60b
ASJ		 2704 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2705 return;
2706
17a73f6b
JG		 2707 hlist_for_each_entry_safe(filter, node,
2708 &pf->fdir_filter_list, fdir_node) {
2709 i40e_add_del_fdir(vsi, filter, true);
2710 }
2711}
2712
41c445ff
JB		 2713/**
2714 * i40e_vsi_configure - Set up the VSI for action
2715 * @vsi: the VSI being configured
2716 **/
2717static int i40e_vsi_configure(struct i40e_vsi *vsi)
2718{
2719 int err;
2720
2721 i40e_set_vsi_rx_mode(vsi);
2722 i40e_restore_vlan(vsi);
2723 i40e_vsi_config_dcb_rings(vsi);
2724 err = i40e_vsi_configure_tx(vsi);
2725 if (!err)
2726 err = i40e_vsi_configure_rx(vsi);
2727
2728 return err;
2729}
2730
2731/**
2732 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2733 * @vsi: the VSI being configured
2734 **/
2735static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2736{
2737 struct i40e_pf *pf = vsi->back;
2738 struct i40e_q_vector *q_vector;
2739 struct i40e_hw *hw = &pf->hw;
2740 u16 vector;
2741 int i, q;
2742 u32 val;
2743 u32 qp;
2744
2745 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2746 * and PFINT_LNKLSTn registers, e.g.:
2747 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2748 */
2749 qp = vsi->base_queue;
2750 vector = vsi->base_vector;
493fb300
AD		 2751 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2752 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2753 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2754 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2755 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2756 q_vector->rx.itr);
2757 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2758 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2759 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2760 q_vector->tx.itr);
2761
2762 /* Linked list for the queuepairs assigned to this vector */
2763 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2764 for (q = 0; q < q_vector->num_ringpairs; q++) {
2765 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2766 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2767 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2768 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2769 (I40E_QUEUE_TYPE_TX
2770 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2771
2772 wr32(hw, I40E_QINT_RQCTL(qp), val);
2773
2774 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2775 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2776 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2777 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2778 (I40E_QUEUE_TYPE_RX
2779 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2780
2781 /* Terminate the linked list */
2782 if (q == (q_vector->num_ringpairs - 1))
2783 val |= (I40E_QUEUE_END_OF_LIST
2784 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2785
2786 wr32(hw, I40E_QINT_TQCTL(qp), val);
2787 qp++;
2788 }
2789 }
2790
2791 i40e_flush(hw);
2792}
2793
2794/**
2795 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2796 * @hw: ptr to the hardware info
2797 **/
2798static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2799{
2800 u32 val;
2801
2802 /* clear things first */
2803 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2804 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2805
2806 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2807 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2808 I40E_PFINT_ICR0_ENA_GRST_MASK |
2809 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2810 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2811 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2812 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2813 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2814 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2815
2816 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2817
2818 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2819 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2820 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2821
2822 /* OTHER_ITR_IDX = 0 */
2823 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2824}
2825
2826/**
2827 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2828 * @vsi: the VSI being configured
2829 **/
2830static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2831{
493fb300 2832 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2833 struct i40e_pf *pf = vsi->back;
2834 struct i40e_hw *hw = &pf->hw;
2835 u32 val;
2836
2837 /* set the ITR configuration */
2838 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2839 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2840 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2841 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2842 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2843 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2844
2845 i40e_enable_misc_int_causes(hw);
2846
2847 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2848 wr32(hw, I40E_PFINT_LNKLST0, 0);
2849
f29eaa3d 2850 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2851 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2852 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2853 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2854
2855 wr32(hw, I40E_QINT_RQCTL(0), val);
2856
2857 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2858 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2859 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2860
2861 wr32(hw, I40E_QINT_TQCTL(0), val);
2862 i40e_flush(hw);
2863}
2864
2ef28cfb
MW		 2865/**
2866 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2867 * @pf: board private structure
2868 **/
2869void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2870{
2871 struct i40e_hw *hw = &pf->hw;
2872
2873 wr32(hw, I40E_PFINT_DYN_CTL0,
2874 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2875 i40e_flush(hw);
2876}
2877
41c445ff
JB		 2878/**
2879 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2880 * @pf: board private structure
2881 **/
116a57d4 2882void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2883{
2884 struct i40e_hw *hw = &pf->hw;
2885 u32 val;
2886
2887 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2888 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2889 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2890
2891 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2892 i40e_flush(hw);
2893}
2894
2895/**
2896 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2897 * @vsi: pointer to a vsi
2898 * @vector: enable a particular Hw Interrupt vector
2899 **/
2900void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2901{
2902 struct i40e_pf *pf = vsi->back;
2903 struct i40e_hw *hw = &pf->hw;
2904 u32 val;
2905
2906 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2907 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2908 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2909 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2910 /* skip the flush */
41c445ff
JB		 2911}
2912
5c2cebda
CW		 2913/**
2914 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2915 * @vsi: pointer to a vsi
2916 * @vector: enable a particular Hw Interrupt vector
2917 **/
2918void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2919{
2920 struct i40e_pf *pf = vsi->back;
2921 struct i40e_hw *hw = &pf->hw;
2922 u32 val;
2923
2924 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2925 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2926 i40e_flush(hw);
2927}
2928
41c445ff
JB		 2929/**
2930 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2931 * @irq: interrupt number
2932 * @data: pointer to a q_vector
2933 **/
2934static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2935{
2936 struct i40e_q_vector *q_vector = data;
2937
cd0b6fa6 2938 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2939 return IRQ_HANDLED;
2940
2941 napi_schedule(&q_vector->napi);
2942
2943 return IRQ_HANDLED;
2944}
2945
41c445ff
JB		 2946/**
2947 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2948 * @vsi: the VSI being configured
2949 * @basename: name for the vector
2950 *
2951 * Allocates MSI-X vectors and requests interrupts from the kernel.
2952 **/
2953static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2954{
2955 int q_vectors = vsi->num_q_vectors;
2956 struct i40e_pf *pf = vsi->back;
2957 int base = vsi->base_vector;
2958 int rx_int_idx = 0;
2959 int tx_int_idx = 0;
2960 int vector, err;
2961
2962 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2963 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2964
cd0b6fa6 2965 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2966 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2967 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2968 tx_int_idx++;
cd0b6fa6 2969 } else if (q_vector->rx.ring) {
41c445ff
JB		 2970 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2971 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2972 } else if (q_vector->tx.ring) {
41c445ff
JB		 2973 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2974 "%s-%s-%d", basename, "tx", tx_int_idx++);
2975 } else {
2976 /* skip this unused q_vector */
2977 continue;
2978 }
2979 err = request_irq(pf->msix_entries[base + vector].vector,
2980 vsi->irq_handler,
2981 0,
2982 q_vector->name,
2983 q_vector);
2984 if (err) {
2985 dev_info(&pf->pdev->dev,
2986 "%s: request_irq failed, error: %d\n",
2987 __func__, err);
2988 goto free_queue_irqs;
2989 }
2990 /* assign the mask for this irq */
2991 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2992 &q_vector->affinity_mask);
2993 }
2994
63741846 2995 vsi->irqs_ready = true;
41c445ff
JB		 2996 return 0;
2997
2998free_queue_irqs:
2999 while (vector) {
3000 vector--;
3001 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3002 NULL);
3003 free_irq(pf->msix_entries[base + vector].vector,
3004 &(vsi->q_vectors[vector]));
3005 }
3006 return err;
3007}
3008
3009/**
3010 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3011 * @vsi: the VSI being un-configured
3012 **/
3013static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3014{
3015 struct i40e_pf *pf = vsi->back;
3016 struct i40e_hw *hw = &pf->hw;
3017 int base = vsi->base_vector;
3018 int i;
3019
3020 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3021 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3022 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3023 }
3024
3025 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3026 for (i = vsi->base_vector;
3027 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3028 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3029
3030 i40e_flush(hw);
3031 for (i = 0; i < vsi->num_q_vectors; i++)
3032 synchronize_irq(pf->msix_entries[i + base].vector);
3033 } else {
3034 /* Legacy and MSI mode - this stops all interrupt handling */
3035 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3036 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3037 i40e_flush(hw);
3038 synchronize_irq(pf->pdev->irq);
3039 }
3040}
3041
3042/**
3043 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3044 * @vsi: the VSI being configured
3045 **/
3046static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3047{
3048 struct i40e_pf *pf = vsi->back;
3049 int i;
3050
3051 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3052 for (i = vsi->base_vector;
3053 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3054 i40e_irq_dynamic_enable(vsi, i);
3055 } else {
3056 i40e_irq_dynamic_enable_icr0(pf);
3057 }
3058
1022cb6c 3059 i40e_flush(&pf->hw);
41c445ff
JB		 3060 return 0;
3061}
3062
3063/**
3064 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3065 * @pf: board private structure
3066 **/
3067static void i40e_stop_misc_vector(struct i40e_pf *pf)
3068{
3069 /* Disable ICR 0 */
3070 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3071 i40e_flush(&pf->hw);
3072}
3073
3074/**
3075 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3076 * @irq: interrupt number
3077 * @data: pointer to a q_vector
3078 *
3079 * This is the handler used for all MSI/Legacy interrupts, and deals
3080 * with both queue and non-queue interrupts. This is also used in
3081 * MSIX mode to handle the non-queue interrupts.
3082 **/
3083static irqreturn_t i40e_intr(int irq, void *data)
3084{
3085 struct i40e_pf *pf = (struct i40e_pf *)data;
3086 struct i40e_hw *hw = &pf->hw;
5e823066 3087 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3088 u32 icr0, icr0_remaining;
3089 u32 val, ena_mask;
3090
3091 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3092 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3093
116a57d4
SN		 3094 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3095 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3096 goto enable_intr;
41c445ff 3097
cd92e72f
SN		 3098 /* if interrupt but no bits showing, must be SWINT */
3099 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3100 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3101 pf->sw_int_count++;
3102
41c445ff
JB		 3103 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3104 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3105
3106 /* temporarily disable queue cause for NAPI processing */
3107 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3108 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3109 wr32(hw, I40E_QINT_RQCTL(0), qval);
3110
3111 qval = rd32(hw, I40E_QINT_TQCTL(0));
3112 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3113 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3114
3115 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3116 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3117 }
3118
3119 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3120 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3121 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3122 }
3123
3124 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3125 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3126 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3127 }
3128
3129 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3130 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3131 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3132 }
3133
3134 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3135 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3136 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3137 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3138 val = rd32(hw, I40E_GLGEN_RSTAT);
3139 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3140 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3141 if (val == I40E_RESET_CORER) {
41c445ff 3142 pf->corer_count++;
4eb3f768 3143 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3144 pf->globr_count++;
4eb3f768 3145 } else if (val == I40E_RESET_EMPR) {
41c445ff 3146 pf->empr_count++;
4eb3f768
SN		 3147 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
3148 }
41c445ff
JB		 3149 }
3150
9c010ee0
ASJ		 3151 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3152 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3153 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3154 }
3155
beb0dff1
JK		 3156 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3157 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3158
3159 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3160 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3161 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3162 }
beb0dff1
JK		 3163 }
3164
41c445ff
JB		 3165 /* If a critical error is pending we have no choice but to reset the
3166 * device.
3167 * Report and mask out any remaining unexpected interrupts.
3168 */
3169 icr0_remaining = icr0 & ena_mask;
3170 if (icr0_remaining) {
3171 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3172 icr0_remaining);
9c010ee0 3173 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3174 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3175 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3176 dev_info(&pf->pdev->dev, "device will be reset\n");
3177 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3178 i40e_service_event_schedule(pf);
41c445ff
JB		 3179 }
3180 ena_mask &= ~icr0_remaining;
3181 }
5e823066 3182 ret = IRQ_HANDLED;
41c445ff 3183
5e823066 3184enable_intr:
41c445ff
JB		 3185 /* re-enable interrupt causes */
3186 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3187 if (!test_bit(__I40E_DOWN, &pf->state)) {
3188 i40e_service_event_schedule(pf);
3189 i40e_irq_dynamic_enable_icr0(pf);
3190 }
3191
5e823066 3192 return ret;
41c445ff
JB		 3193}
3194
cbf61325
ASJ		 3195/**
3196 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3197 * @tx_ring: tx ring to clean
3198 * @budget: how many cleans we're allowed
3199 *
3200 * Returns true if there's any budget left (e.g. the clean is finished)
3201 **/
3202static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3203{
3204 struct i40e_vsi *vsi = tx_ring->vsi;
3205 u16 i = tx_ring->next_to_clean;
3206 struct i40e_tx_buffer *tx_buf;
3207 struct i40e_tx_desc *tx_desc;
3208
3209 tx_buf = &tx_ring->tx_bi[i];
3210 tx_desc = I40E_TX_DESC(tx_ring, i);
3211 i -= tx_ring->count;
3212
3213 do {
3214 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3215
3216 /* if next_to_watch is not set then there is no work pending */
3217 if (!eop_desc)
3218 break;
3219
3220 /* prevent any other reads prior to eop_desc */
3221 read_barrier_depends();
3222
3223 /* if the descriptor isn't done, no work yet to do */
3224 if (!(eop_desc->cmd_type_offset_bsz &
3225 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3226 break;
3227
3228 /* clear next_to_watch to prevent false hangs */
3229 tx_buf->next_to_watch = NULL;
3230
49d7d933
ASJ		 3231 tx_desc->buffer_addr = 0;
3232 tx_desc->cmd_type_offset_bsz = 0;
3233 /* move past filter desc */
3234 tx_buf++;
3235 tx_desc++;
3236 i++;
3237 if (unlikely(!i)) {
3238 i -= tx_ring->count;
3239 tx_buf = tx_ring->tx_bi;
3240 tx_desc = I40E_TX_DESC(tx_ring, 0);
3241 }
cbf61325
ASJ		 3242 /* unmap skb header data */
3243 dma_unmap_single(tx_ring->dev,
3244 dma_unmap_addr(tx_buf, dma),
3245 dma_unmap_len(tx_buf, len),
3246 DMA_TO_DEVICE);
49d7d933
ASJ		 3247 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3248 kfree(tx_buf->raw_buf);
cbf61325 3249
49d7d933
ASJ		 3250 tx_buf->raw_buf = NULL;
3251 tx_buf->tx_flags = 0;
3252 tx_buf->next_to_watch = NULL;
cbf61325 3253 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3254 tx_desc->buffer_addr = 0;
3255 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3256
49d7d933 3257 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3258 tx_buf++;
3259 tx_desc++;
3260 i++;
3261 if (unlikely(!i)) {
3262 i -= tx_ring->count;
3263 tx_buf = tx_ring->tx_bi;
3264 tx_desc = I40E_TX_DESC(tx_ring, 0);
3265 }
3266
3267 /* update budget accounting */
3268 budget--;
3269 } while (likely(budget));
3270
3271 i += tx_ring->count;
3272 tx_ring->next_to_clean = i;
3273
3274 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3275 i40e_irq_dynamic_enable(vsi,
3276 tx_ring->q_vector->v_idx + vsi->base_vector);
3277 }
3278 return budget > 0;
3279}
3280
3281/**
3282 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3283 * @irq: interrupt number
3284 * @data: pointer to a q_vector
3285 **/
3286static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3287{
3288 struct i40e_q_vector *q_vector = data;
3289 struct i40e_vsi *vsi;
3290
3291 if (!q_vector->tx.ring)
3292 return IRQ_HANDLED;
3293
3294 vsi = q_vector->tx.ring->vsi;
3295 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3296
3297 return IRQ_HANDLED;
3298}
3299
41c445ff 3300/**
cd0b6fa6 3301 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3302 * @vsi: the VSI being configured
3303 * @v_idx: vector index
cd0b6fa6 3304 * @qp_idx: queue pair index
41c445ff 3305 **/
cd0b6fa6 3306static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3307{
493fb300 3308 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3309 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3310 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3311
3312 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3313 tx_ring->next = q_vector->tx.ring;
3314 q_vector->tx.ring = tx_ring;
41c445ff 3315 q_vector->tx.count++;
cd0b6fa6
AD		 3316
3317 rx_ring->q_vector = q_vector;
3318 rx_ring->next = q_vector->rx.ring;
3319 q_vector->rx.ring = rx_ring;
3320 q_vector->rx.count++;
41c445ff
JB		 3321}
3322
3323/**
3324 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3325 * @vsi: the VSI being configured
3326 *
3327 * This function maps descriptor rings to the queue-specific vectors
3328 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3329 * one vector per queue pair, but on a constrained vector budget, we
3330 * group the queue pairs as "efficiently" as possible.
3331 **/
3332static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3333{
3334 int qp_remaining = vsi->num_queue_pairs;
3335 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3336 int num_ringpairs;
41c445ff
JB		 3337 int v_start = 0;
3338 int qp_idx = 0;
3339
3340 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3341 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3342 * It is also important to go through all the vectors available to be
3343 * sure that if we don't use all the vectors, that the remaining vectors
3344 * are cleared. This is especially important when decreasing the
3345 * number of queues in use.
41c445ff 3346 */
70114ec4 3347 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3348 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3349
3350 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3351
3352 q_vector->num_ringpairs = num_ringpairs;
3353
3354 q_vector->rx.count = 0;
3355 q_vector->tx.count = 0;
3356 q_vector->rx.ring = NULL;
3357 q_vector->tx.ring = NULL;
3358
3359 while (num_ringpairs--) {
3360 map_vector_to_qp(vsi, v_start, qp_idx);
3361 qp_idx++;
3362 qp_remaining--;
41c445ff
JB		 3363 }
3364 }
3365}
3366
3367/**
3368 * i40e_vsi_request_irq - Request IRQ from the OS
3369 * @vsi: the VSI being configured
3370 * @basename: name for the vector
3371 **/
3372static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3373{
3374 struct i40e_pf *pf = vsi->back;
3375 int err;
3376
3377 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3378 err = i40e_vsi_request_irq_msix(vsi, basename);
3379 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3380 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3381 pf->misc_int_name, pf);
3382 else
3383 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3384 pf->misc_int_name, pf);
3385
3386 if (err)
3387 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3388
3389 return err;
3390}
3391
3392#ifdef CONFIG_NET_POLL_CONTROLLER
3393/**
3394 * i40e_netpoll - A Polling 'interrupt'handler
3395 * @netdev: network interface device structure
3396 *
3397 * This is used by netconsole to send skbs without having to re-enable
3398 * interrupts. It's not called while the normal interrupt routine is executing.
3399 **/
38e00438
VD		 3400#ifdef I40E_FCOE
3401void i40e_netpoll(struct net_device *netdev)
3402#else
41c445ff 3403static void i40e_netpoll(struct net_device *netdev)
38e00438 3404#endif
41c445ff
JB		 3405{
3406 struct i40e_netdev_priv *np = netdev_priv(netdev);
3407 struct i40e_vsi *vsi = np->vsi;
3408 struct i40e_pf *pf = vsi->back;
3409 int i;
3410
3411 /* if interface is down do nothing */
3412 if (test_bit(__I40E_DOWN, &vsi->state))
3413 return;
3414
3415 pf->flags |= I40E_FLAG_IN_NETPOLL;
3416 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3417 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3418 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3419 } else {
3420 i40e_intr(pf->pdev->irq, netdev);
3421 }
3422 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3423}
3424#endif
3425
23527308
NP		 3426/**
3427 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3428 * @pf: the PF being configured
3429 * @pf_q: the PF queue
3430 * @enable: enable or disable state of the queue
3431 *
3432 * This routine will wait for the given Tx queue of the PF to reach the
3433 * enabled or disabled state.
3434 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3435 * multiple retries; else will return 0 in case of success.
3436 **/
3437static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3438{
3439 int i;
3440 u32 tx_reg;
3441
3442 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3443 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3444 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3445 break;
3446
f98a2006 3447 usleep_range(10, 20);
23527308
NP		 3448 }
3449 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3450 return -ETIMEDOUT;
3451
3452 return 0;
3453}
3454
41c445ff
JB		 3455/**
3456 * i40e_vsi_control_tx - Start or stop a VSI's rings
3457 * @vsi: the VSI being configured
3458 * @enable: start or stop the rings
3459 **/
3460static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3461{
3462 struct i40e_pf *pf = vsi->back;
3463 struct i40e_hw *hw = &pf->hw;
23527308 3464 int i, j, pf_q, ret = 0;
41c445ff
JB		 3465 u32 tx_reg;
3466
3467 pf_q = vsi->base_queue;
3468 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3469
3470 /* warn the TX unit of coming changes */
3471 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3472 if (!enable)
f98a2006 3473 usleep_range(10, 20);
351499ab 3474
6c5ef620 3475 for (j = 0; j < 50; j++) {
41c445ff 3476 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3477 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3478 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3479 break;
3480 usleep_range(1000, 2000);
3481 }
fda972f6 3482 /* Skip if the queue is already in the requested state */
7c122007 3483 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3484 continue;
41c445ff
JB		 3485
3486 /* turn on/off the queue */
c5c9eb9e
SN		 3487 if (enable) {
3488 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3489 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3490 } else {
41c445ff 3491 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3492 }
41c445ff
JB		 3493
3494 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3495
3496 /* wait for the change to finish */
23527308
NP		 3497 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3498 if (ret) {
3499 dev_info(&pf->pdev->dev,
3500 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3501 __func__, vsi->seid, pf_q,
3502 (enable ? "en" : "dis"));
3503 break;
41c445ff
JB		 3504 }
3505 }
3506
7134f9ce
JB		 3507 if (hw->revision_id == 0)
3508 mdelay(50);
23527308
NP		 3509 return ret;
3510}
3511
3512/**
3513 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3514 * @pf: the PF being configured
3515 * @pf_q: the PF queue
3516 * @enable: enable or disable state of the queue
3517 *
3518 * This routine will wait for the given Rx queue of the PF to reach the
3519 * enabled or disabled state.
3520 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3521 * multiple retries; else will return 0 in case of success.
3522 **/
3523static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3524{
3525 int i;
3526 u32 rx_reg;
3527
3528 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3529 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3530 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3531 break;
3532
f98a2006 3533 usleep_range(10, 20);
23527308
NP		 3534 }
3535 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3536 return -ETIMEDOUT;
7134f9ce 3537
41c445ff
JB		 3538 return 0;
3539}
3540
3541/**
3542 * i40e_vsi_control_rx - Start or stop a VSI's rings
3543 * @vsi: the VSI being configured
3544 * @enable: start or stop the rings
3545 **/
3546static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3547{
3548 struct i40e_pf *pf = vsi->back;
3549 struct i40e_hw *hw = &pf->hw;
23527308 3550 int i, j, pf_q, ret = 0;
41c445ff
JB		 3551 u32 rx_reg;
3552
3553 pf_q = vsi->base_queue;
3554 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3555 for (j = 0; j < 50; j++) {
41c445ff 3556 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3557 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3558 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3559 break;
3560 usleep_range(1000, 2000);
3561 }
41c445ff 3562
7c122007
CS		 3563 /* Skip if the queue is already in the requested state */
3564 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3565 continue;
41c445ff
JB		 3566
3567 /* turn on/off the queue */
3568 if (enable)
6c5ef620 3569 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3570 else
6c5ef620 3571 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3572 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3573
3574 /* wait for the change to finish */
23527308
NP		 3575 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3576 if (ret) {
3577 dev_info(&pf->pdev->dev,
3578 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3579 __func__, vsi->seid, pf_q,
3580 (enable ? "en" : "dis"));
3581 break;
41c445ff
JB		 3582 }
3583 }
3584
23527308 3585 return ret;
41c445ff
JB		 3586}
3587
3588/**
3589 * i40e_vsi_control_rings - Start or stop a VSI's rings
3590 * @vsi: the VSI being configured
3591 * @enable: start or stop the rings
3592 **/
fc18eaa0 3593int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3594{
3b867b28 3595 int ret = 0;
41c445ff
JB		 3596
3597 /* do rx first for enable and last for disable */
3598 if (request) {
3599 ret = i40e_vsi_control_rx(vsi, request);
3600 if (ret)
3601 return ret;
3602 ret = i40e_vsi_control_tx(vsi, request);
3603 } else {
3b867b28
ASJ		 3604 /* Ignore return value, we need to shutdown whatever we can */
3605 i40e_vsi_control_tx(vsi, request);
3606 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3607 }
3608
3609 return ret;
3610}
3611
3612/**
3613 * i40e_vsi_free_irq - Free the irq association with the OS
3614 * @vsi: the VSI being configured
3615 **/
3616static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3617{
3618 struct i40e_pf *pf = vsi->back;
3619 struct i40e_hw *hw = &pf->hw;
3620 int base = vsi->base_vector;
3621 u32 val, qp;
3622 int i;
3623
3624 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3625 if (!vsi->q_vectors)
3626 return;
3627
63741846
SN		 3628 if (!vsi->irqs_ready)
3629 return;
3630
3631 vsi->irqs_ready = false;
41c445ff
JB		 3632 for (i = 0; i < vsi->num_q_vectors; i++) {
3633 u16 vector = i + base;
3634
3635 /* free only the irqs that were actually requested */
78681b1f
SN		 3636 if (!vsi->q_vectors[i] ||
3637 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3638 continue;
3639
3640 /* clear the affinity_mask in the IRQ descriptor */
3641 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3642 NULL);
3643 free_irq(pf->msix_entries[vector].vector,
493fb300 3644 vsi->q_vectors[i]);
41c445ff
JB		 3645
3646 /* Tear down the interrupt queue link list
3647 *
3648 * We know that they come in pairs and always
3649 * the Rx first, then the Tx. To clear the
3650 * link list, stick the EOL value into the
3651 * next_q field of the registers.
3652 */
3653 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3654 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3655 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3656 val |= I40E_QUEUE_END_OF_LIST
3657 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3658 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3659
3660 while (qp != I40E_QUEUE_END_OF_LIST) {
3661 u32 next;
3662
3663 val = rd32(hw, I40E_QINT_RQCTL(qp));
3664
3665 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3666 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3667 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3668 I40E_QINT_RQCTL_INTEVENT_MASK);
3669
3670 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3671 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3672
3673 wr32(hw, I40E_QINT_RQCTL(qp), val);
3674
3675 val = rd32(hw, I40E_QINT_TQCTL(qp));
3676
3677 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3678 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3679
3680 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3681 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3682 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3683 I40E_QINT_TQCTL_INTEVENT_MASK);
3684
3685 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3686 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3687
3688 wr32(hw, I40E_QINT_TQCTL(qp), val);
3689 qp = next;
3690 }
3691 }
3692 } else {
3693 free_irq(pf->pdev->irq, pf);
3694
3695 val = rd32(hw, I40E_PFINT_LNKLST0);
3696 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3697 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3698 val |= I40E_QUEUE_END_OF_LIST
3699 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3700 wr32(hw, I40E_PFINT_LNKLST0, val);
3701
3702 val = rd32(hw, I40E_QINT_RQCTL(qp));
3703 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3704 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3705 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3706 I40E_QINT_RQCTL_INTEVENT_MASK);
3707
3708 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3709 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3710
3711 wr32(hw, I40E_QINT_RQCTL(qp), val);
3712
3713 val = rd32(hw, I40E_QINT_TQCTL(qp));
3714
3715 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3716 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3717 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3718 I40E_QINT_TQCTL_INTEVENT_MASK);
3719
3720 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3721 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3722
3723 wr32(hw, I40E_QINT_TQCTL(qp), val);
3724 }
3725}
3726
493fb300
AD		 3727/**
3728 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3729 * @vsi: the VSI being configured
3730 * @v_idx: Index of vector to be freed
3731 *
3732 * This function frees the memory allocated to the q_vector. In addition if
3733 * NAPI is enabled it will delete any references to the NAPI struct prior
3734 * to freeing the q_vector.
3735 **/
3736static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3737{
3738 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3739 struct i40e_ring *ring;
493fb300
AD		 3740
3741 if (!q_vector)
3742 return;
3743
3744 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3745 i40e_for_each_ring(ring, q_vector->tx)
3746 ring->q_vector = NULL;
3747
3748 i40e_for_each_ring(ring, q_vector->rx)
3749 ring->q_vector = NULL;
493fb300
AD		 3750
3751 /* only VSI w/ an associated netdev is set up w/ NAPI */
3752 if (vsi->netdev)
3753 netif_napi_del(&q_vector->napi);
3754
3755 vsi->q_vectors[v_idx] = NULL;
3756
3757 kfree_rcu(q_vector, rcu);
3758}
3759
41c445ff
JB		 3760/**
3761 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3762 * @vsi: the VSI being un-configured
3763 *
3764 * This frees the memory allocated to the q_vectors and
3765 * deletes references to the NAPI struct.
3766 **/
3767static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3768{
3769 int v_idx;
3770
493fb300
AD		 3771 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3772 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3773}
3774
3775/**
3776 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3777 * @pf: board private structure
3778 **/
3779static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3780{
3781 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3782 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3783 pci_disable_msix(pf->pdev);
3784 kfree(pf->msix_entries);
3785 pf->msix_entries = NULL;
3786 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3787 pci_disable_msi(pf->pdev);
3788 }
3789 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3790}
3791
3792/**
3793 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3794 * @pf: board private structure
3795 *
3796 * We go through and clear interrupt specific resources and reset the structure
3797 * to pre-load conditions
3798 **/
3799static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3800{
3801 int i;
3802
3803 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3804 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3805 if (pf->vsi[i])
3806 i40e_vsi_free_q_vectors(pf->vsi[i]);
3807 i40e_reset_interrupt_capability(pf);
3808}
3809
3810/**
3811 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3812 * @vsi: the VSI being configured
3813 **/
3814static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3815{
3816 int q_idx;
3817
3818 if (!vsi->netdev)
3819 return;
3820
3821 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3822 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3823}
3824
3825/**
3826 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3827 * @vsi: the VSI being configured
3828 **/
3829static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3830{
3831 int q_idx;
3832
3833 if (!vsi->netdev)
3834 return;
3835
3836 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3837 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3838}
3839
90ef8d47
SN		 3840/**
3841 * i40e_vsi_close - Shut down a VSI
3842 * @vsi: the vsi to be quelled
3843 **/
3844static void i40e_vsi_close(struct i40e_vsi *vsi)
3845{
3846 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3847 i40e_down(vsi);
3848 i40e_vsi_free_irq(vsi);
3849 i40e_vsi_free_tx_resources(vsi);
3850 i40e_vsi_free_rx_resources(vsi);
3851}
3852
41c445ff
JB		 3853/**
3854 * i40e_quiesce_vsi - Pause a given VSI
3855 * @vsi: the VSI being paused
3856 **/
3857static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3858{
3859 if (test_bit(__I40E_DOWN, &vsi->state))
3860 return;
3861
3862 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3863 if (vsi->netdev && netif_running(vsi->netdev)) {
3864 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3865 } else {
90ef8d47 3866 i40e_vsi_close(vsi);
41c445ff
JB		 3867 }
3868}
3869
3870/**
3871 * i40e_unquiesce_vsi - Resume a given VSI
3872 * @vsi: the VSI being resumed
3873 **/
3874static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3875{
3876 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3877 return;
3878
3879 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3880 if (vsi->netdev && netif_running(vsi->netdev))
3881 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3882 else
8276f757 3883 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3884}
3885
3886/**
3887 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3888 * @pf: the PF
3889 **/
3890static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3891{
3892 int v;
3893
505682cd 3894 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3895 if (pf->vsi[v])
3896 i40e_quiesce_vsi(pf->vsi[v]);
3897 }
3898}
3899
3900/**
3901 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3902 * @pf: the PF
3903 **/
3904static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3905{
3906 int v;
3907
505682cd 3908 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3909 if (pf->vsi[v])
3910 i40e_unquiesce_vsi(pf->vsi[v]);
3911 }
3912}
3913
3914/**
3915 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3916 * @dcbcfg: the corresponding DCBx configuration structure
3917 *
3918 * Return the number of TCs from given DCBx configuration
3919 **/
3920static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3921{
078b5876
JB		 3922 u8 num_tc = 0;
3923 int i;
41c445ff
JB		 3924
3925 /* Scan the ETS Config Priority Table to find
3926 * traffic class enabled for a given priority
3927 * and use the traffic class index to get the
3928 * number of traffic classes enabled
3929 */
3930 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3931 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3932 num_tc = dcbcfg->etscfg.prioritytable[i];
3933 }
3934
3935 /* Traffic class index starts from zero so
3936 * increment to return the actual count
3937 */
078b5876 3938 return num_tc + 1;
41c445ff
JB		 3939}
3940
3941/**
3942 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3943 * @dcbcfg: the corresponding DCBx configuration structure
3944 *
3945 * Query the current DCB configuration and return the number of
3946 * traffic classes enabled from the given DCBX config
3947 **/
3948static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3949{
3950 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3951 u8 enabled_tc = 1;
3952 u8 i;
3953
3954 for (i = 0; i < num_tc; i++)
3955 enabled_tc |= 1 << i;
3956
3957 return enabled_tc;
3958}
3959
3960/**
3961 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3962 * @pf: PF being queried
3963 *
3964 * Return number of traffic classes enabled for the given PF
3965 **/
3966static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3967{
3968 struct i40e_hw *hw = &pf->hw;
3969 u8 i, enabled_tc;
3970 u8 num_tc = 0;
3971 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3972
3973 /* If DCB is not enabled then always in single TC */
3974 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3975 return 1;
3976
3977 /* MFP mode return count of enabled TCs for this PF */
3978 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3979 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3980 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3981 if (enabled_tc & (1 << i))
3982 num_tc++;
3983 }
3984 return num_tc;
3985 }
3986
3987 /* SFP mode will be enabled for all TCs on port */
3988 return i40e_dcb_get_num_tc(dcbcfg);
3989}
3990
3991/**
3992 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3993 * @pf: PF being queried
3994 *
3995 * Return a bitmap for first enabled traffic class for this PF.
3996 **/
3997static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3998{
3999 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4000 u8 i = 0;
4001
4002 if (!enabled_tc)
4003 return 0x1; /* TC0 */
4004
4005 /* Find the first enabled TC */
4006 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4007 if (enabled_tc & (1 << i))
4008 break;
4009 }
4010
4011 return 1 << i;
4012}
4013
4014/**
4015 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4016 * @pf: PF being queried
4017 *
4018 * Return a bitmap for enabled traffic classes for this PF.
4019 **/
4020static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4021{
4022 /* If DCB is not enabled for this PF then just return default TC */
4023 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4024 return i40e_pf_get_default_tc(pf);
4025
4026 /* MFP mode will have enabled TCs set by FW */
4027 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4028 return pf->hw.func_caps.enabled_tcmap;
4029
4030 /* SFP mode we want PF to be enabled for all TCs */
4031 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4032}
4033
4034/**
4035 * i40e_vsi_get_bw_info - Query VSI BW Information
4036 * @vsi: the VSI being queried
4037 *
4038 * Returns 0 on success, negative value on failure
4039 **/
4040static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4041{
4042 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4043 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4044 struct i40e_pf *pf = vsi->back;
4045 struct i40e_hw *hw = &pf->hw;
dcae29be 4046 i40e_status aq_ret;
41c445ff 4047 u32 tc_bw_max;
41c445ff
JB		 4048 int i;
4049
4050 /* Get the VSI level BW configuration */
dcae29be
JB		 4051 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4052 if (aq_ret) {
41c445ff
JB		 4053 dev_info(&pf->pdev->dev,
4054 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4055 aq_ret, pf->hw.aq.asq_last_status);
4056 return -EINVAL;
41c445ff
JB		 4057 }
4058
4059 /* Get the VSI level BW configuration per TC */
dcae29be 4060 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4061 NULL);
dcae29be 4062 if (aq_ret) {
41c445ff
JB		 4063 dev_info(&pf->pdev->dev,
4064 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4065 aq_ret, pf->hw.aq.asq_last_status);
4066 return -EINVAL;
41c445ff
JB		 4067 }
4068
4069 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4070 dev_info(&pf->pdev->dev,
4071 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4072 bw_config.tc_valid_bits,
4073 bw_ets_config.tc_valid_bits);
4074 /* Still continuing */
4075 }
4076
4077 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4078 vsi->bw_max_quanta = bw_config.max_bw;
4079 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4080 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4081 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4082 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4083 vsi->bw_ets_limit_credits[i] =
4084 le16_to_cpu(bw_ets_config.credits[i]);
4085 /* 3 bits out of 4 for each TC */
4086 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4087 }
078b5876 4088
dcae29be 4089 return 0;
41c445ff
JB		 4090}
4091
4092/**
4093 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4094 * @vsi: the VSI being configured
4095 * @enabled_tc: TC bitmap
4096 * @bw_credits: BW shared credits per TC
4097 *
4098 * Returns 0 on success, negative value on failure
4099 **/
dcae29be 4100static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4101 u8 *bw_share)
4102{
4103 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4104 i40e_status aq_ret;
4105 int i;
41c445ff
JB		 4106
4107 bw_data.tc_valid_bits = enabled_tc;
4108 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4109 bw_data.tc_bw_credits[i] = bw_share[i];
4110
dcae29be
JB		 4111 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4112 NULL);
4113 if (aq_ret) {
41c445ff 4114 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4115 "AQ command Config VSI BW allocation per TC failed = %d\n",
4116 vsi->back->hw.aq.asq_last_status);
dcae29be 4117 return -EINVAL;
41c445ff
JB		 4118 }
4119
4120 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4121 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4122
dcae29be 4123 return 0;
41c445ff
JB		 4124}
4125
4126/**
4127 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4128 * @vsi: the VSI being configured
4129 * @enabled_tc: TC map to be enabled
4130 *
4131 **/
4132static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4133{
4134 struct net_device *netdev = vsi->netdev;
4135 struct i40e_pf *pf = vsi->back;
4136 struct i40e_hw *hw = &pf->hw;
4137 u8 netdev_tc = 0;
4138 int i;
4139 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4140
4141 if (!netdev)
4142 return;
4143
4144 if (!enabled_tc) {
4145 netdev_reset_tc(netdev);
4146 return;
4147 }
4148
4149 /* Set up actual enabled TCs on the VSI */
4150 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4151 return;
4152
4153 /* set per TC queues for the VSI */
4154 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4155 /* Only set TC queues for enabled tcs
4156 *
4157 * e.g. For a VSI that has TC0 and TC3 enabled the
4158 * enabled_tc bitmap would be 0x00001001; the driver
4159 * will set the numtc for netdev as 2 that will be
4160 * referenced by the netdev layer as TC 0 and 1.
4161 */
4162 if (vsi->tc_config.enabled_tc & (1 << i))
4163 netdev_set_tc_queue(netdev,
4164 vsi->tc_config.tc_info[i].netdev_tc,
4165 vsi->tc_config.tc_info[i].qcount,
4166 vsi->tc_config.tc_info[i].qoffset);
4167 }
4168
4169 /* Assign UP2TC map for the VSI */
4170 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4171 /* Get the actual TC# for the UP */
4172 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4173 /* Get the mapped netdev TC# for the UP */
4174 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4175 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4176 }
4177}
4178
4179/**
4180 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4181 * @vsi: the VSI being configured
4182 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4183 **/
4184static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4185 struct i40e_vsi_context *ctxt)
4186{
4187 /* copy just the sections touched not the entire info
4188 * since not all sections are valid as returned by
4189 * update vsi params
4190 */
4191 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4192 memcpy(&vsi->info.queue_mapping,
4193 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4194 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4195 sizeof(vsi->info.tc_mapping));
4196}
4197
4198/**
4199 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4200 * @vsi: VSI to be configured
4201 * @enabled_tc: TC bitmap
4202 *
4203 * This configures a particular VSI for TCs that are mapped to the
4204 * given TC bitmap. It uses default bandwidth share for TCs across
4205 * VSIs to configure TC for a particular VSI.
4206 *
4207 * NOTE:
4208 * It is expected that the VSI queues have been quisced before calling
4209 * this function.
4210 **/
4211static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4212{
4213 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4214 struct i40e_vsi_context ctxt;
4215 int ret = 0;
4216 int i;
4217
4218 /* Check if enabled_tc is same as existing or new TCs */
4219 if (vsi->tc_config.enabled_tc == enabled_tc)
4220 return ret;
4221
4222 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4223 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4224 if (enabled_tc & (1 << i))
4225 bw_share[i] = 1;
4226 }
4227
4228 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4229 if (ret) {
4230 dev_info(&vsi->back->pdev->dev,
4231 "Failed configuring TC map %d for VSI %d\n",
4232 enabled_tc, vsi->seid);
4233 goto out;
4234 }
4235
4236 /* Update Queue Pairs Mapping for currently enabled UPs */
4237 ctxt.seid = vsi->seid;
4238 ctxt.pf_num = vsi->back->hw.pf_id;
4239 ctxt.vf_num = 0;
4240 ctxt.uplink_seid = vsi->uplink_seid;
4241 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4242 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4243
4244 /* Update the VSI after updating the VSI queue-mapping information */
4245 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4246 if (ret) {
4247 dev_info(&vsi->back->pdev->dev,
4248 "update vsi failed, aq_err=%d\n",
4249 vsi->back->hw.aq.asq_last_status);
4250 goto out;
4251 }
4252 /* update the local VSI info with updated queue map */
4253 i40e_vsi_update_queue_map(vsi, &ctxt);
4254 vsi->info.valid_sections = 0;
4255
4256 /* Update current VSI BW information */
4257 ret = i40e_vsi_get_bw_info(vsi);
4258 if (ret) {
4259 dev_info(&vsi->back->pdev->dev,
4260 "Failed updating vsi bw info, aq_err=%d\n",
4261 vsi->back->hw.aq.asq_last_status);
4262 goto out;
4263 }
4264
4265 /* Update the netdev TC setup */
4266 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4267out:
4268 return ret;
4269}
4270
4e3b35b0
NP		 4271/**
4272 * i40e_veb_config_tc - Configure TCs for given VEB
4273 * @veb: given VEB
4274 * @enabled_tc: TC bitmap
4275 *
4276 * Configures given TC bitmap for VEB (switching) element
4277 **/
4278int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4279{
4280 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4281 struct i40e_pf *pf = veb->pf;
4282 int ret = 0;
4283 int i;
4284
4285 /* No TCs or already enabled TCs just return */
4286 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4287 return ret;
4288
4289 bw_data.tc_valid_bits = enabled_tc;
4290 /* bw_data.absolute_credits is not set (relative) */
4291
4292 /* Enable ETS TCs with equal BW Share for now */
4293 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4294 if (enabled_tc & (1 << i))
4295 bw_data.tc_bw_share_credits[i] = 1;
4296 }
4297
4298 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4299 &bw_data, NULL);
4300 if (ret) {
4301 dev_info(&pf->pdev->dev,
4302 "veb bw config failed, aq_err=%d\n",
4303 pf->hw.aq.asq_last_status);
4304 goto out;
4305 }
4306
4307 /* Update the BW information */
4308 ret = i40e_veb_get_bw_info(veb);
4309 if (ret) {
4310 dev_info(&pf->pdev->dev,
4311 "Failed getting veb bw config, aq_err=%d\n",
4312 pf->hw.aq.asq_last_status);
4313 }
4314
4315out:
4316 return ret;
4317}
4318
4319#ifdef CONFIG_I40E_DCB
4320/**
4321 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4322 * @pf: PF struct
4323 *
4324 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4325 * the caller would've quiesce all the VSIs before calling
4326 * this function
4327 **/
4328static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4329{
4330 u8 tc_map = 0;
4331 int ret;
4332 u8 v;
4333
4334 /* Enable the TCs available on PF to all VEBs */
4335 tc_map = i40e_pf_get_tc_map(pf);
4336 for (v = 0; v < I40E_MAX_VEB; v++) {
4337 if (!pf->veb[v])
4338 continue;
4339 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4340 if (ret) {
4341 dev_info(&pf->pdev->dev,
4342 "Failed configuring TC for VEB seid=%d\n",
4343 pf->veb[v]->seid);
4344 /* Will try to configure as many components */
4345 }
4346 }
4347
4348 /* Update each VSI */
505682cd 4349 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4350 if (!pf->vsi[v])
4351 continue;
4352
4353 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4354#ifdef I40E_FCOE
4355 * - For FCoE VSI only enable the TC configured
4356 * as per the APP TLV
4357#endif
4e3b35b0
NP		 4358 * - For all others keep them at TC0 for now
4359 */
4360 if (v == pf->lan_vsi)
4361 tc_map = i40e_pf_get_tc_map(pf);
4362 else
4363 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4364#ifdef I40E_FCOE
4365 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4366 tc_map = i40e_get_fcoe_tc_map(pf);
4367#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4368
4369 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4370 if (ret) {
4371 dev_info(&pf->pdev->dev,
4372 "Failed configuring TC for VSI seid=%d\n",
4373 pf->vsi[v]->seid);
4374 /* Will try to configure as many components */
4375 } else {
0672a091
NP		 4376 /* Re-configure VSI vectors based on updated TC map */
4377 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4378 if (pf->vsi[v]->netdev)
4379 i40e_dcbnl_set_all(pf->vsi[v]);
4380 }
4381 }
4382}
4383
2fd75f31
NP		 4384/**
4385 * i40e_resume_port_tx - Resume port Tx
4386 * @pf: PF struct
4387 *
4388 * Resume a port's Tx and issue a PF reset in case of failure to
4389 * resume.
4390 **/
4391static int i40e_resume_port_tx(struct i40e_pf *pf)
4392{
4393 struct i40e_hw *hw = &pf->hw;
4394 int ret;
4395
4396 ret = i40e_aq_resume_port_tx(hw, NULL);
4397 if (ret) {
4398 dev_info(&pf->pdev->dev,
4399 "AQ command Resume Port Tx failed = %d\n",
4400 pf->hw.aq.asq_last_status);
4401 /* Schedule PF reset to recover */
4402 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4403 i40e_service_event_schedule(pf);
4404 }
4405
4406 return ret;
4407}
4408
4e3b35b0
NP		 4409/**
4410 * i40e_init_pf_dcb - Initialize DCB configuration
4411 * @pf: PF being configured
4412 *
4413 * Query the current DCB configuration and cache it
4414 * in the hardware structure
4415 **/
4416static int i40e_init_pf_dcb(struct i40e_pf *pf)
4417{
4418 struct i40e_hw *hw = &pf->hw;
4419 int err = 0;
4420
4421 if (pf->hw.func_caps.npar_enable)
4422 goto out;
4423
4424 /* Get the initial DCB configuration */
4425 err = i40e_init_dcb(hw);
4426 if (!err) {
4427 /* Device/Function is not DCBX capable */
4428 if ((!hw->func_caps.dcb) ||
4429 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4430 dev_info(&pf->pdev->dev,
4431 "DCBX offload is not supported or is disabled for this PF.\n");
4432
4433 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4434 goto out;
4435
4436 } else {
4437 /* When status is not DISABLED then DCBX in FW */
4438 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4439 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4440
4441 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4442 /* Enable DCB tagging only when more than one TC */
4443 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4444 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4445 dev_dbg(&pf->pdev->dev,
4446 "DCBX offload is supported for this PF.\n");
4e3b35b0 4447 }
014269ff
NP		 4448 } else {
4449 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4450 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4451 }
4452
4453out:
4454 return err;
4455}
4456#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4457#define SPEED_SIZE 14
4458#define FC_SIZE 8
4459/**
4460 * i40e_print_link_message - print link up or down
4461 * @vsi: the VSI for which link needs a message
4462 */
4463static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4464{
4465 char speed[SPEED_SIZE] = "Unknown";
4466 char fc[FC_SIZE] = "RX/TX";
4467
4468 if (!isup) {
4469 netdev_info(vsi->netdev, "NIC Link is Down\n");
4470 return;
4471 }
4472
4473 switch (vsi->back->hw.phy.link_info.link_speed) {
4474 case I40E_LINK_SPEED_40GB:
35a7d804 4475 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08
JB		 4476 break;
4477 case I40E_LINK_SPEED_10GB:
35a7d804 4478 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4479 break;
4480 case I40E_LINK_SPEED_1GB:
35a7d804 4481 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4482 break;
5960d33f
MW		 4483 case I40E_LINK_SPEED_100MB:
4484 strncpy(speed, "100 Mbps", SPEED_SIZE);
4485 break;
cf05ed08
JB		 4486 default:
4487 break;
4488 }
4489
4490 switch (vsi->back->hw.fc.current_mode) {
4491 case I40E_FC_FULL:
35a7d804 4492 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4493 break;
4494 case I40E_FC_TX_PAUSE:
35a7d804 4495 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4496 break;
4497 case I40E_FC_RX_PAUSE:
35a7d804 4498 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4499 break;
4500 default:
35a7d804 4501 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4502 break;
4503 }
4504
4505 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4506 speed, fc);
4507}
4e3b35b0 4508
41c445ff
JB		 4509/**
4510 * i40e_up_complete - Finish the last steps of bringing up a connection
4511 * @vsi: the VSI being configured
4512 **/
4513static int i40e_up_complete(struct i40e_vsi *vsi)
4514{
4515 struct i40e_pf *pf = vsi->back;
4516 int err;
4517
4518 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4519 i40e_vsi_configure_msix(vsi);
4520 else
4521 i40e_configure_msi_and_legacy(vsi);
4522
4523 /* start rings */
4524 err = i40e_vsi_control_rings(vsi, true);
4525 if (err)
4526 return err;
4527
4528 clear_bit(__I40E_DOWN, &vsi->state);
4529 i40e_napi_enable_all(vsi);
4530 i40e_vsi_enable_irq(vsi);
4531
4532 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4533 (vsi->netdev)) {
cf05ed08 4534 i40e_print_link_message(vsi, true);
41c445ff
JB		 4535 netif_tx_start_all_queues(vsi->netdev);
4536 netif_carrier_on(vsi->netdev);
6d779b41 4537 } else if (vsi->netdev) {
cf05ed08 4538 i40e_print_link_message(vsi, false);
7b592f61
CW		 4539 /* need to check for qualified module here*/
4540 if ((pf->hw.phy.link_info.link_info &
4541 I40E_AQ_MEDIA_AVAILABLE) &&
4542 (!(pf->hw.phy.link_info.an_info &
4543 I40E_AQ_QUALIFIED_MODULE)))
4544 netdev_err(vsi->netdev,
4545 "the driver failed to link because an unqualified module was detected.");
41c445ff 4546 }
ca64fa4e
ASJ		 4547
4548 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4549 if (vsi->type == I40E_VSI_FDIR) {
4550 /* reset fd counters */
4551 pf->fd_add_err = pf->fd_atr_cnt = 0;
4552 if (pf->fd_tcp_rule > 0) {
4553 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4554 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4555 pf->fd_tcp_rule = 0;
4556 }
ca64fa4e 4557 i40e_fdir_filter_restore(vsi);
1e1be8f6 4558 }
41c445ff
JB		 4559 i40e_service_event_schedule(pf);
4560
4561 return 0;
4562}
4563
4564/**
4565 * i40e_vsi_reinit_locked - Reset the VSI
4566 * @vsi: the VSI being configured
4567 *
4568 * Rebuild the ring structs after some configuration
4569 * has changed, e.g. MTU size.
4570 **/
4571static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4572{
4573 struct i40e_pf *pf = vsi->back;
4574
4575 WARN_ON(in_interrupt());
4576 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4577 usleep_range(1000, 2000);
4578 i40e_down(vsi);
4579
4580 /* Give a VF some time to respond to the reset. The
4581 * two second wait is based upon the watchdog cycle in
4582 * the VF driver.
4583 */
4584 if (vsi->type == I40E_VSI_SRIOV)
4585 msleep(2000);
4586 i40e_up(vsi);
4587 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4588}
4589
4590/**
4591 * i40e_up - Bring the connection back up after being down
4592 * @vsi: the VSI being configured
4593 **/
4594int i40e_up(struct i40e_vsi *vsi)
4595{
4596 int err;
4597
4598 err = i40e_vsi_configure(vsi);
4599 if (!err)
4600 err = i40e_up_complete(vsi);
4601
4602 return err;
4603}
4604
4605/**
4606 * i40e_down - Shutdown the connection processing
4607 * @vsi: the VSI being stopped
4608 **/
4609void i40e_down(struct i40e_vsi *vsi)
4610{
4611 int i;
4612
4613 /* It is assumed that the caller of this function
4614 * sets the vsi->state __I40E_DOWN bit.
4615 */
4616 if (vsi->netdev) {
4617 netif_carrier_off(vsi->netdev);
4618 netif_tx_disable(vsi->netdev);
4619 }
4620 i40e_vsi_disable_irq(vsi);
4621 i40e_vsi_control_rings(vsi, false);
4622 i40e_napi_disable_all(vsi);
4623
4624 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4625 i40e_clean_tx_ring(vsi->tx_rings[i]);
4626 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4627 }
4628}
4629
4630/**
4631 * i40e_setup_tc - configure multiple traffic classes
4632 * @netdev: net device to configure
4633 * @tc: number of traffic classes to enable
4634 **/
38e00438
VD		 4635#ifdef I40E_FCOE
4636int i40e_setup_tc(struct net_device *netdev, u8 tc)
4637#else
41c445ff 4638static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4639#endif
41c445ff
JB		 4640{
4641 struct i40e_netdev_priv *np = netdev_priv(netdev);
4642 struct i40e_vsi *vsi = np->vsi;
4643 struct i40e_pf *pf = vsi->back;
4644 u8 enabled_tc = 0;
4645 int ret = -EINVAL;
4646 int i;
4647
4648 /* Check if DCB enabled to continue */
4649 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4650 netdev_info(netdev, "DCB is not enabled for adapter\n");
4651 goto exit;
4652 }
4653
4654 /* Check if MFP enabled */
4655 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4656 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4657 goto exit;
4658 }
4659
4660 /* Check whether tc count is within enabled limit */
4661 if (tc > i40e_pf_get_num_tc(pf)) {
4662 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4663 goto exit;
4664 }
4665
4666 /* Generate TC map for number of tc requested */
4667 for (i = 0; i < tc; i++)
4668 enabled_tc |= (1 << i);
4669
4670 /* Requesting same TC configuration as already enabled */
4671 if (enabled_tc == vsi->tc_config.enabled_tc)
4672 return 0;
4673
4674 /* Quiesce VSI queues */
4675 i40e_quiesce_vsi(vsi);
4676
4677 /* Configure VSI for enabled TCs */
4678 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4679 if (ret) {
4680 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4681 vsi->seid);
4682 goto exit;
4683 }
4684
4685 /* Unquiesce VSI */
4686 i40e_unquiesce_vsi(vsi);
4687
4688exit:
4689 return ret;
4690}
4691
4692/**
4693 * i40e_open - Called when a network interface is made active
4694 * @netdev: network interface device structure
4695 *
4696 * The open entry point is called when a network interface is made
4697 * active by the system (IFF_UP). At this point all resources needed
4698 * for transmit and receive operations are allocated, the interrupt
4699 * handler is registered with the OS, the netdev watchdog subtask is
4700 * enabled, and the stack is notified that the interface is ready.
4701 *
4702 * Returns 0 on success, negative value on failure
4703 **/
38e00438
VD		 4704#ifdef I40E_FCOE
4705int i40e_open(struct net_device *netdev)
4706#else
41c445ff 4707static int i40e_open(struct net_device *netdev)
38e00438 4708#endif
41c445ff
JB		 4709{
4710 struct i40e_netdev_priv *np = netdev_priv(netdev);
4711 struct i40e_vsi *vsi = np->vsi;
4712 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4713 int err;
4714
4eb3f768
SN		 4715 /* disallow open during test or if eeprom is broken */
4716 if (test_bit(__I40E_TESTING, &pf->state) ||
4717 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4718 return -EBUSY;
4719
4720 netif_carrier_off(netdev);
4721
6c167f58
EK		 4722 err = i40e_vsi_open(vsi);
4723 if (err)
4724 return err;
4725
059dab69
JB		 4726 /* configure global TSO hardware offload settings */
4727 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4728 TCP_FLAG_FIN) >> 16);
4729 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4730 TCP_FLAG_FIN |
4731 TCP_FLAG_CWR) >> 16);
4732 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4733
6c167f58
EK		 4734#ifdef CONFIG_I40E_VXLAN
4735 vxlan_get_rx_port(netdev);
4736#endif
4737
4738 return 0;
4739}
4740
4741/**
4742 * i40e_vsi_open -
4743 * @vsi: the VSI to open
4744 *
4745 * Finish initialization of the VSI.
4746 *
4747 * Returns 0 on success, negative value on failure
4748 **/
4749int i40e_vsi_open(struct i40e_vsi *vsi)
4750{
4751 struct i40e_pf *pf = vsi->back;
4752 char int_name[IFNAMSIZ];
4753 int err;
4754
41c445ff
JB		 4755 /* allocate descriptors */
4756 err = i40e_vsi_setup_tx_resources(vsi);
4757 if (err)
4758 goto err_setup_tx;
4759 err = i40e_vsi_setup_rx_resources(vsi);
4760 if (err)
4761 goto err_setup_rx;
4762
4763 err = i40e_vsi_configure(vsi);
4764 if (err)
4765 goto err_setup_rx;
4766
c22e3c6c
SN		 4767 if (vsi->netdev) {
4768 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4769 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4770 err = i40e_vsi_request_irq(vsi, int_name);
4771 if (err)
4772 goto err_setup_rx;
41c445ff 4773
c22e3c6c
SN		 4774 /* Notify the stack of the actual queue counts. */
4775 err = netif_set_real_num_tx_queues(vsi->netdev,
4776 vsi->num_queue_pairs);
4777 if (err)
4778 goto err_set_queues;
25946ddb 4779
c22e3c6c
SN		 4780 err = netif_set_real_num_rx_queues(vsi->netdev,
4781 vsi->num_queue_pairs);
4782 if (err)
4783 goto err_set_queues;
8a9eb7d3
SN		 4784
4785 } else if (vsi->type == I40E_VSI_FDIR) {
4786 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4787 dev_driver_string(&pf->pdev->dev));
4788 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4789 } else {
ce9ccb17 4790 err = -EINVAL;
6c167f58
EK		 4791 goto err_setup_rx;
4792 }
25946ddb 4793
41c445ff
JB		 4794 err = i40e_up_complete(vsi);
4795 if (err)
4796 goto err_up_complete;
4797
41c445ff
JB		 4798 return 0;
4799
4800err_up_complete:
4801 i40e_down(vsi);
25946ddb 4802err_set_queues:
41c445ff
JB		 4803 i40e_vsi_free_irq(vsi);
4804err_setup_rx:
4805 i40e_vsi_free_rx_resources(vsi);
4806err_setup_tx:
4807 i40e_vsi_free_tx_resources(vsi);
4808 if (vsi == pf->vsi[pf->lan_vsi])
4809 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4810
4811 return err;
4812}
4813
17a73f6b
JG		 4814/**
4815 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4816 * @pf: Pointer to pf
4817 *
4818 * This function destroys the hlist where all the Flow Director
4819 * filters were saved.
4820 **/
4821static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4822{
4823 struct i40e_fdir_filter *filter;
4824 struct hlist_node *node2;
4825
4826 hlist_for_each_entry_safe(filter, node2,
4827 &pf->fdir_filter_list, fdir_node) {
4828 hlist_del(&filter->fdir_node);
4829 kfree(filter);
4830 }
4831 pf->fdir_pf_active_filters = 0;
4832}
4833
41c445ff
JB		 4834/**
4835 * i40e_close - Disables a network interface
4836 * @netdev: network interface device structure
4837 *
4838 * The close entry point is called when an interface is de-activated
4839 * by the OS. The hardware is still under the driver's control, but
4840 * this netdev interface is disabled.
4841 *
4842 * Returns 0, this is not allowed to fail
4843 **/
38e00438
VD		 4844#ifdef I40E_FCOE
4845int i40e_close(struct net_device *netdev)
4846#else
41c445ff 4847static int i40e_close(struct net_device *netdev)
38e00438 4848#endif
41c445ff
JB		 4849{
4850 struct i40e_netdev_priv *np = netdev_priv(netdev);
4851 struct i40e_vsi *vsi = np->vsi;
4852
90ef8d47 4853 i40e_vsi_close(vsi);
41c445ff
JB		 4854
4855 return 0;
4856}
4857
4858/**
4859 * i40e_do_reset - Start a PF or Core Reset sequence
4860 * @pf: board private structure
4861 * @reset_flags: which reset is requested
4862 *
4863 * The essential difference in resets is that the PF Reset
4864 * doesn't clear the packet buffers, doesn't reset the PE
4865 * firmware, and doesn't bother the other PFs on the chip.
4866 **/
4867void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4868{
4869 u32 val;
4870
4871 WARN_ON(in_interrupt());
4872
263fc48f
MW		 4873 if (i40e_check_asq_alive(&pf->hw))
4874 i40e_vc_notify_reset(pf);
4875
41c445ff
JB		 4876 /* do the biggest reset indicated */
4877 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4878
4879 /* Request a Global Reset
4880 *
4881 * This will start the chip's countdown to the actual full
4882 * chip reset event, and a warning interrupt to be sent
4883 * to all PFs, including the requestor. Our handler
4884 * for the warning interrupt will deal with the shutdown
4885 * and recovery of the switch setup.
4886 */
69bfb110 4887 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4888 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4889 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4890 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4891
4892 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4893
4894 /* Request a Core Reset
4895 *
4896 * Same as Global Reset, except does *not* include the MAC/PHY
4897 */
69bfb110 4898 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4899 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4900 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4901 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4902 i40e_flush(&pf->hw);
4903
7823fe34
SN		 4904 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4905
4906 /* Request a Firmware Reset
4907 *
4908 * Same as Global reset, plus restarting the
4909 * embedded firmware engine.
4910 */
4911 /* enable EMP Reset */
4912 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4913 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4914 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4915
4916 /* force the reset */
4917 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4918 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4919 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4920 i40e_flush(&pf->hw);
4921
41c445ff
JB		 4922 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4923
4924 /* Request a PF Reset
4925 *
4926 * Resets only the PF-specific registers
4927 *
4928 * This goes directly to the tear-down and rebuild of
4929 * the switch, since we need to do all the recovery as
4930 * for the Core Reset.
4931 */
69bfb110 4932 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4933 i40e_handle_reset_warning(pf);
4934
4935 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4936 int v;
4937
4938 /* Find the VSI(s) that requested a re-init */
4939 dev_info(&pf->pdev->dev,
4940 "VSI reinit requested\n");
505682cd 4941 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4942 struct i40e_vsi *vsi = pf->vsi[v];
4943 if (vsi != NULL &&
4944 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4945 i40e_vsi_reinit_locked(pf->vsi[v]);
4946 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4947 }
4948 }
4949
b5d06f05
NP		 4950 /* no further action needed, so return now */
4951 return;
4952 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
4953 int v;
4954
4955 /* Find the VSI(s) that needs to be brought down */
4956 dev_info(&pf->pdev->dev, "VSI down requested\n");
4957 for (v = 0; v < pf->num_alloc_vsi; v++) {
4958 struct i40e_vsi *vsi = pf->vsi[v];
4959 if (vsi != NULL &&
4960 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
4961 set_bit(__I40E_DOWN, &vsi->state);
4962 i40e_down(vsi);
4963 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
4964 }
4965 }
4966
41c445ff
JB		 4967 /* no further action needed, so return now */
4968 return;
4969 } else {
4970 dev_info(&pf->pdev->dev,
4971 "bad reset request 0x%08x\n", reset_flags);
4972 return;
4973 }
4974}
4975
4e3b35b0
NP		 4976#ifdef CONFIG_I40E_DCB
4977/**
4978 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4979 * @pf: board private structure
4980 * @old_cfg: current DCB config
4981 * @new_cfg: new DCB config
4982 **/
4983bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4984 struct i40e_dcbx_config *old_cfg,
4985 struct i40e_dcbx_config *new_cfg)
4986{
4987 bool need_reconfig = false;
4988
4989 /* Check if ETS configuration has changed */
4990 if (memcmp(&new_cfg->etscfg,
4991 &old_cfg->etscfg,
4992 sizeof(new_cfg->etscfg))) {
4993 /* If Priority Table has changed reconfig is needed */
4994 if (memcmp(&new_cfg->etscfg.prioritytable,
4995 &old_cfg->etscfg.prioritytable,
4996 sizeof(new_cfg->etscfg.prioritytable))) {
4997 need_reconfig = true;
69bfb110 4998 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4999 }
5000
5001 if (memcmp(&new_cfg->etscfg.tcbwtable,
5002 &old_cfg->etscfg.tcbwtable,
5003 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5004 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5005
5006 if (memcmp(&new_cfg->etscfg.tsatable,
5007 &old_cfg->etscfg.tsatable,
5008 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5009 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5010 }
5011
5012 /* Check if PFC configuration has changed */
5013 if (memcmp(&new_cfg->pfc,
5014 &old_cfg->pfc,
5015 sizeof(new_cfg->pfc))) {
5016 need_reconfig = true;
69bfb110 5017 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5018 }
5019
5020 /* Check if APP Table has changed */
5021 if (memcmp(&new_cfg->app,
5022 &old_cfg->app,
3d9667a9 5023 sizeof(new_cfg->app))) {
4e3b35b0 5024 need_reconfig = true;
69bfb110 5025 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5026 }
4e3b35b0 5027
9fa61dd2
NP		 5028 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5029 need_reconfig);
4e3b35b0
NP		 5030 return need_reconfig;
5031}
5032
5033/**
5034 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5035 * @pf: board private structure
5036 * @e: event info posted on ARQ
5037 **/
5038static int i40e_handle_lldp_event(struct i40e_pf *pf,
5039 struct i40e_arq_event_info *e)
5040{
5041 struct i40e_aqc_lldp_get_mib *mib =
5042 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5043 struct i40e_hw *hw = &pf->hw;
5044 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
5045 struct i40e_dcbx_config tmp_dcbx_cfg;
5046 bool need_reconfig = false;
5047 int ret = 0;
5048 u8 type;
5049
4d9b6043
NP		 5050 /* Not DCB capable or capability disabled */
5051 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5052 return ret;
5053
4e3b35b0
NP		 5054 /* Ignore if event is not for Nearest Bridge */
5055 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5056 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5057 dev_dbg(&pf->pdev->dev,
5058 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5059 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5060 return ret;
5061
5062 /* Check MIB Type and return if event for Remote MIB update */
5063 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5064 dev_dbg(&pf->pdev->dev,
5065 "%s: LLDP event mib type %s\n", __func__,
5066 type ? "remote" : "local");
4e3b35b0
NP		 5067 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5068 /* Update the remote cached instance and return */
5069 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5070 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5071 &hw->remote_dcbx_config);
5072 goto exit;
5073 }
5074
4e3b35b0 5075 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
9fa61dd2
NP		 5076 /* Store the old configuration */
5077 tmp_dcbx_cfg = *dcbx_cfg;
5078
5079 /* Get updated DCBX data from firmware */
5080 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5081 if (ret) {
9fa61dd2 5082 dev_info(&pf->pdev->dev, "Failed querying DCB configuration data from firmware.\n");
4e3b35b0
NP		 5083 goto exit;
5084 }
5085
5086 /* No change detected in DCBX configs */
5087 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 5088 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5089 goto exit;
5090 }
5091
9fa61dd2 5092 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, dcbx_cfg);
4e3b35b0 5093
9fa61dd2 5094 i40e_dcbnl_flush_apps(pf, dcbx_cfg);
4e3b35b0
NP		 5095
5096 if (!need_reconfig)
5097 goto exit;
5098
4d9b6043
NP		 5099 /* Enable DCB tagging only when more than one TC */
5100 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
5101 pf->flags |= I40E_FLAG_DCB_ENABLED;
5102 else
5103 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5104
4e3b35b0
NP		 5105 /* Reconfiguration needed quiesce all VSIs */
5106 i40e_pf_quiesce_all_vsi(pf);
5107
5108 /* Changes in configuration update VEB/VSI */
5109 i40e_dcb_reconfigure(pf);
5110
2fd75f31
NP		 5111 ret = i40e_resume_port_tx(pf);
5112
5113 /* In case of error no point in resuming VSIs */
5114 if (!ret)
5115 i40e_pf_unquiesce_all_vsi(pf);
4e3b35b0
NP		 5116exit:
5117 return ret;
5118}
5119#endif /* CONFIG_I40E_DCB */
5120
23326186
ASJ		 5121/**
5122 * i40e_do_reset_safe - Protected reset path for userland calls.
5123 * @pf: board private structure
5124 * @reset_flags: which reset is requested
5125 *
5126 **/
5127void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5128{
5129 rtnl_lock();
5130 i40e_do_reset(pf, reset_flags);
5131 rtnl_unlock();
5132}
5133
41c445ff
JB		 5134/**
5135 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5136 * @pf: board private structure
5137 * @e: event info posted on ARQ
5138 *
5139 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5140 * and VF queues
5141 **/
5142static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5143 struct i40e_arq_event_info *e)
5144{
5145 struct i40e_aqc_lan_overflow *data =
5146 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5147 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5148 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5149 struct i40e_hw *hw = &pf->hw;
5150 struct i40e_vf *vf;
5151 u16 vf_id;
5152
69bfb110
JB		 5153 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5154 queue, qtx_ctl);
41c445ff
JB		 5155
5156 /* Queue belongs to VF, find the VF and issue VF reset */
5157 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5158 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5159 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5160 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5161 vf_id -= hw->func_caps.vf_base_id;
5162 vf = &pf->vf[vf_id];
5163 i40e_vc_notify_vf_reset(vf);
5164 /* Allow VF to process pending reset notification */
5165 msleep(20);
5166 i40e_reset_vf(vf, false);
5167 }
5168}
5169
5170/**
5171 * i40e_service_event_complete - Finish up the service event
5172 * @pf: board private structure
5173 **/
5174static void i40e_service_event_complete(struct i40e_pf *pf)
5175{
5176 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5177
5178 /* flush memory to make sure state is correct before next watchog */
4e857c58 5179 smp_mb__before_atomic();
41c445ff
JB		 5180 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5181}
5182
55a5e60b 5183/**
12957388
ASJ		 5184 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5185 * @pf: board private structure
5186 **/
5187int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
5188{
5189 int val, fcnt_prog;
5190
5191 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5192 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5193 return fcnt_prog;
5194}
5195
5196/**
5197 * i40e_get_current_fd_count - Get the count of total FD filters programmed
55a5e60b
ASJ		 5198 * @pf: board private structure
5199 **/
5200int i40e_get_current_fd_count(struct i40e_pf *pf)
5201{
5202 int val, fcnt_prog;
5203 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5204 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5205 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5206 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5207 return fcnt_prog;
5208}
1e1be8f6 5209
55a5e60b
ASJ		 5210/**
5211 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5212 * @pf: board private structure
5213 **/
5214void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5215{
5216 u32 fcnt_prog, fcnt_avail;
5217
1e1be8f6
ASJ		 5218 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5219 return;
5220
55a5e60b
ASJ		 5221 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5222 * to re-enable
5223 */
12957388
ASJ		 5224 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
5225 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5226 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5227 (pf->fd_add_err == 0) ||
5228 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5229 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5230 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5231 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5232 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5233 }
5234 }
5235 /* Wait for some more space to be available to turn on ATR */
5236 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5237 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5238 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5239 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5240 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5241 }
5242 }
5243}
5244
1e1be8f6
ASJ		 5245#define I40E_MIN_FD_FLUSH_INTERVAL 10
5246/**
5247 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5248 * @pf: board private structure
5249 **/
5250static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5251{
5252 int flush_wait_retry = 50;
5253 int reg;
5254
1790ed0c
AA		 5255 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5256 return;
5257
1e1be8f6
ASJ		 5258 if (time_after(jiffies, pf->fd_flush_timestamp +
5259 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
5260 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5261 pf->fd_flush_timestamp = jiffies;
5262 pf->auto_disable_flags |= I40E_FLAG_FD_SB_ENABLED;
5263 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5264 /* flush all filters */
5265 wr32(&pf->hw, I40E_PFQF_CTL_1,
5266 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5267 i40e_flush(&pf->hw);
60793f4a 5268 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5269 pf->fd_add_err = 0;
5270 do {
5271 /* Check FD flush status every 5-6msec */
5272 usleep_range(5000, 6000);
5273 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5274 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5275 break;
5276 } while (flush_wait_retry--);
5277 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5278 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5279 } else {
5280 /* replay sideband filters */
5281 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5282
5283 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5284 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5285 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5286 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5287 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5288 }
5289 }
5290}
5291
5292/**
5293 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5294 * @pf: board private structure
5295 **/
5296int i40e_get_current_atr_cnt(struct i40e_pf *pf)
5297{
5298 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5299}
5300
5301/* We can see up to 256 filter programming desc in transit if the filters are
5302 * being applied really fast; before we see the first
5303 * filter miss error on Rx queue 0. Accumulating enough error messages before
5304 * reacting will make sure we don't cause flush too often.
5305 */
5306#define I40E_MAX_FD_PROGRAM_ERROR 256
5307
41c445ff
JB		 5308/**
5309 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5310 * @pf: board private structure
5311 **/
5312static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5313{
41c445ff 5314
41c445ff
JB		 5315 /* if interface is down do nothing */
5316 if (test_bit(__I40E_DOWN, &pf->state))
5317 return;
1e1be8f6 5318
1790ed0c
AA		 5319 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5320 return;
5321
1e1be8f6
ASJ		 5322 if ((pf->fd_add_err >= I40E_MAX_FD_PROGRAM_ERROR) &&
5323 (i40e_get_current_atr_cnt(pf) >= pf->fd_atr_cnt) &&
5324 (i40e_get_current_atr_cnt(pf) > pf->fdir_pf_filter_count))
5325 i40e_fdir_flush_and_replay(pf);
5326
55a5e60b
ASJ		 5327 i40e_fdir_check_and_reenable(pf);
5328
41c445ff
JB		 5329}
5330
5331/**
5332 * i40e_vsi_link_event - notify VSI of a link event
5333 * @vsi: vsi to be notified
5334 * @link_up: link up or down
5335 **/
5336static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5337{
32b5b811 5338 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5339 return;
5340
5341 switch (vsi->type) {
5342 case I40E_VSI_MAIN:
38e00438
VD		 5343#ifdef I40E_FCOE
5344 case I40E_VSI_FCOE:
5345#endif
41c445ff
JB		 5346 if (!vsi->netdev || !vsi->netdev_registered)
5347 break;
5348
5349 if (link_up) {
5350 netif_carrier_on(vsi->netdev);
5351 netif_tx_wake_all_queues(vsi->netdev);
5352 } else {
5353 netif_carrier_off(vsi->netdev);
5354 netif_tx_stop_all_queues(vsi->netdev);
5355 }
5356 break;
5357
5358 case I40E_VSI_SRIOV:
5359 break;
5360
5361 case I40E_VSI_VMDQ2:
5362 case I40E_VSI_CTRL:
5363 case I40E_VSI_MIRROR:
5364 default:
5365 /* there is no notification for other VSIs */
5366 break;
5367 }
5368}
5369
5370/**
5371 * i40e_veb_link_event - notify elements on the veb of a link event
5372 * @veb: veb to be notified
5373 * @link_up: link up or down
5374 **/
5375static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5376{
5377 struct i40e_pf *pf;
5378 int i;
5379
5380 if (!veb || !veb->pf)
5381 return;
5382 pf = veb->pf;
5383
5384 /* depth first... */
5385 for (i = 0; i < I40E_MAX_VEB; i++)
5386 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5387 i40e_veb_link_event(pf->veb[i], link_up);
5388
5389 /* ... now the local VSIs */
505682cd 5390 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5391 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5392 i40e_vsi_link_event(pf->vsi[i], link_up);
5393}
5394
5395/**
5396 * i40e_link_event - Update netif_carrier status
5397 * @pf: board private structure
5398 **/
5399static void i40e_link_event(struct i40e_pf *pf)
5400{
5401 bool new_link, old_link;
320684cd 5402 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
41c445ff 5403
1e701e09
JB		 5404 /* set this to force the get_link_status call to refresh state */
5405 pf->hw.phy.get_link_info = true;
5406
41c445ff 5407 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5408 new_link = i40e_get_link_status(&pf->hw);
41c445ff 5409
1e701e09 5410 if (new_link == old_link &&
320684cd
MW		 5411 (test_bit(__I40E_DOWN, &vsi->state) ||
5412 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5413 return;
320684cd
MW		 5414
5415 if (!test_bit(__I40E_DOWN, &vsi->state))
5416 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5417
5418 /* Notify the base of the switch tree connected to
5419 * the link. Floating VEBs are not notified.
5420 */
5421 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5422 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5423 else
320684cd 5424 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5425
5426 if (pf->vf)
5427 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5428
5429 if (pf->flags & I40E_FLAG_PTP)
5430 i40e_ptp_set_increment(pf);
41c445ff
JB		 5431}
5432
5433/**
5434 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5435 * @pf: board private structure
5436 *
5437 * Set the per-queue flags to request a check for stuck queues in the irq
5438 * clean functions, then force interrupts to be sure the irq clean is called.
5439 **/
5440static void i40e_check_hang_subtask(struct i40e_pf *pf)
5441{
5442 int i, v;
5443
5444 /* If we're down or resetting, just bail */
5445 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5446 return;
5447
5448 /* for each VSI/netdev
5449 * for each Tx queue
5450 * set the check flag
5451 * for each q_vector
5452 * force an interrupt
5453 */
505682cd 5454 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5455 struct i40e_vsi *vsi = pf->vsi[v];
5456 int armed = 0;
5457
5458 if (!pf->vsi[v] ||
5459 test_bit(__I40E_DOWN, &vsi->state) ||
5460 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5461 continue;
5462
5463 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5464 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5465 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5466 &vsi->tx_rings[i]->state))
41c445ff
JB		 5467 armed++;
5468 }
5469
5470 if (armed) {
5471 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5472 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5473 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5474 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
5475 } else {
5476 u16 vec = vsi->base_vector - 1;
5477 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5478 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5479 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5480 wr32(&vsi->back->hw,
5481 I40E_PFINT_DYN_CTLN(vec), val);
5482 }
5483 i40e_flush(&vsi->back->hw);
5484 }
5485 }
5486}
5487
5488/**
21536717 5489 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5490 * @pf: board private structure
5491 **/
5492static void i40e_watchdog_subtask(struct i40e_pf *pf)
5493{
5494 int i;
5495
5496 /* if interface is down do nothing */
5497 if (test_bit(__I40E_DOWN, &pf->state) ||
5498 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5499 return;
5500
21536717
SN		 5501 /* make sure we don't do these things too often */
5502 if (time_before(jiffies, (pf->service_timer_previous +
5503 pf->service_timer_period)))
5504 return;
5505 pf->service_timer_previous = jiffies;
5506
5507 i40e_check_hang_subtask(pf);
5508 i40e_link_event(pf);
5509
41c445ff
JB		 5510 /* Update the stats for active netdevs so the network stack
5511 * can look at updated numbers whenever it cares to
5512 */
505682cd 5513 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5514 if (pf->vsi[i] && pf->vsi[i]->netdev)
5515 i40e_update_stats(pf->vsi[i]);
5516
5517 /* Update the stats for the active switching components */
5518 for (i = 0; i < I40E_MAX_VEB; i++)
5519 if (pf->veb[i])
5520 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5521
5522 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5523}
5524
5525/**
5526 * i40e_reset_subtask - Set up for resetting the device and driver
5527 * @pf: board private structure
5528 **/
5529static void i40e_reset_subtask(struct i40e_pf *pf)
5530{
5531 u32 reset_flags = 0;
5532
23326186 5533 rtnl_lock();
41c445ff
JB		 5534 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5535 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5536 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5537 }
5538 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5539 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5540 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5541 }
5542 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5543 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5544 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5545 }
5546 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5547 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5548 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5549 }
b5d06f05
NP		 5550 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5551 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5552 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5553 }
41c445ff
JB		 5554
5555 /* If there's a recovery already waiting, it takes
5556 * precedence before starting a new reset sequence.
5557 */
5558 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5559 i40e_handle_reset_warning(pf);
23326186 5560 goto unlock;
41c445ff
JB		 5561 }
5562
5563 /* If we're already down or resetting, just bail */
5564 if (reset_flags &&
5565 !test_bit(__I40E_DOWN, &pf->state) &&
5566 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5567 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5568
5569unlock:
5570 rtnl_unlock();
41c445ff
JB		 5571}
5572
5573/**
5574 * i40e_handle_link_event - Handle link event
5575 * @pf: board private structure
5576 * @e: event info posted on ARQ
5577 **/
5578static void i40e_handle_link_event(struct i40e_pf *pf,
5579 struct i40e_arq_event_info *e)
5580{
5581 struct i40e_hw *hw = &pf->hw;
5582 struct i40e_aqc_get_link_status *status =
5583 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5584 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5585
5586 /* save off old link status information */
5587 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5588 sizeof(pf->hw.phy.link_info_old));
5589
1e701e09
JB		 5590 /* Do a new status request to re-enable LSE reporting
5591 * and load new status information into the hw struct
5592 * This completely ignores any state information
5593 * in the ARQ event info, instead choosing to always
5594 * issue the AQ update link status command.
5595 */
5596 i40e_link_event(pf);
5597
7b592f61
CW		 5598 /* check for unqualified module, if link is down */
5599 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5600 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5601 (!(status->link_info & I40E_AQ_LINK_UP)))
5602 dev_err(&pf->pdev->dev,
5603 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5604}
5605
5606/**
5607 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5608 * @pf: board private structure
5609 **/
5610static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5611{
5612 struct i40e_arq_event_info event;
5613 struct i40e_hw *hw = &pf->hw;
5614 u16 pending, i = 0;
5615 i40e_status ret;
5616 u16 opcode;
86df242b 5617 u32 oldval;
41c445ff
JB		 5618 u32 val;
5619
a316f651
ASJ		 5620 /* Do not run clean AQ when PF reset fails */
5621 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5622 return;
5623
86df242b
SN		 5624 /* check for error indications */
5625 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5626 oldval = val;
5627 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5628 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5629 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5630 }
5631 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5632 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5633 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5634 }
5635 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5636 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5637 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5638 }
5639 if (oldval != val)
5640 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5641
5642 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5643 oldval = val;
5644 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5645 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5646 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5647 }
5648 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5649 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5650 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5651 }
5652 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5653 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5654 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5655 }
5656 if (oldval != val)
5657 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5658
3197ce22 5659 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5660 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5661 if (!event.msg_buf)
5662 return;
5663
5664 do {
2f019123 5665 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff 5666 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5667 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5668 break;
56497978 5669 else if (ret) {
41c445ff
JB		 5670 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5671 break;
5672 }
5673
5674 opcode = le16_to_cpu(event.desc.opcode);
5675 switch (opcode) {
5676
5677 case i40e_aqc_opc_get_link_status:
5678 i40e_handle_link_event(pf, &event);
5679 break;
5680 case i40e_aqc_opc_send_msg_to_pf:
5681 ret = i40e_vc_process_vf_msg(pf,
5682 le16_to_cpu(event.desc.retval),
5683 le32_to_cpu(event.desc.cookie_high),
5684 le32_to_cpu(event.desc.cookie_low),
5685 event.msg_buf,
5686 event.msg_size);
5687 break;
5688 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5689 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5690#ifdef CONFIG_I40E_DCB
5691 rtnl_lock();
5692 ret = i40e_handle_lldp_event(pf, &event);
5693 rtnl_unlock();
5694#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5695 break;
5696 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5697 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5698 i40e_handle_lan_overflow_event(pf, &event);
5699 break;
0467bc91
SN		 5700 case i40e_aqc_opc_send_msg_to_peer:
5701 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5702 break;
41c445ff
JB		 5703 default:
5704 dev_info(&pf->pdev->dev,
0467bc91
SN		 5705 "ARQ Error: Unknown event 0x%04x received\n",
5706 opcode);
41c445ff
JB		 5707 break;
5708 }
5709 } while (pending && (i++ < pf->adminq_work_limit));
5710
5711 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5712 /* re-enable Admin queue interrupt cause */
5713 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5714 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5715 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5716 i40e_flush(hw);
5717
5718 kfree(event.msg_buf);
5719}
5720
4eb3f768
SN		 5721/**
5722 * i40e_verify_eeprom - make sure eeprom is good to use
5723 * @pf: board private structure
5724 **/
5725static void i40e_verify_eeprom(struct i40e_pf *pf)
5726{
5727 int err;
5728
5729 err = i40e_diag_eeprom_test(&pf->hw);
5730 if (err) {
5731 /* retry in case of garbage read */
5732 err = i40e_diag_eeprom_test(&pf->hw);
5733 if (err) {
5734 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5735 err);
5736 set_bit(__I40E_BAD_EEPROM, &pf->state);
5737 }
5738 }
5739
5740 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5741 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5742 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5743 }
5744}
5745
41c445ff
JB		 5746/**
5747 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5748 * @veb: pointer to the VEB instance
5749 *
5750 * This is a recursive function that first builds the attached VSIs then
5751 * recurses in to build the next layer of VEB. We track the connections
5752 * through our own index numbers because the seid's from the HW could
5753 * change across the reset.
5754 **/
5755static int i40e_reconstitute_veb(struct i40e_veb *veb)
5756{
5757 struct i40e_vsi *ctl_vsi = NULL;
5758 struct i40e_pf *pf = veb->pf;
5759 int v, veb_idx;
5760 int ret;
5761
5762 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5763 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5764 if (pf->vsi[v] &&
5765 pf->vsi[v]->veb_idx == veb->idx &&
5766 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5767 ctl_vsi = pf->vsi[v];
5768 break;
5769 }
5770 }
5771 if (!ctl_vsi) {
5772 dev_info(&pf->pdev->dev,
5773 "missing owner VSI for veb_idx %d\n", veb->idx);
5774 ret = -ENOENT;
5775 goto end_reconstitute;
5776 }
5777 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5778 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5779 ret = i40e_add_vsi(ctl_vsi);
5780 if (ret) {
5781 dev_info(&pf->pdev->dev,
5782 "rebuild of owner VSI failed: %d\n", ret);
5783 goto end_reconstitute;
5784 }
5785 i40e_vsi_reset_stats(ctl_vsi);
5786
5787 /* create the VEB in the switch and move the VSI onto the VEB */
5788 ret = i40e_add_veb(veb, ctl_vsi);
5789 if (ret)
5790 goto end_reconstitute;
5791
5792 /* create the remaining VSIs attached to this VEB */
505682cd 5793 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5794 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5795 continue;
5796
5797 if (pf->vsi[v]->veb_idx == veb->idx) {
5798 struct i40e_vsi *vsi = pf->vsi[v];
5799 vsi->uplink_seid = veb->seid;
5800 ret = i40e_add_vsi(vsi);
5801 if (ret) {
5802 dev_info(&pf->pdev->dev,
5803 "rebuild of vsi_idx %d failed: %d\n",
5804 v, ret);
5805 goto end_reconstitute;
5806 }
5807 i40e_vsi_reset_stats(vsi);
5808 }
5809 }
5810
5811 /* create any VEBs attached to this VEB - RECURSION */
5812 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5813 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5814 pf->veb[veb_idx]->uplink_seid = veb->seid;
5815 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5816 if (ret)
5817 break;
5818 }
5819 }
5820
5821end_reconstitute:
5822 return ret;
5823}
5824
5825/**
5826 * i40e_get_capabilities - get info about the HW
5827 * @pf: the PF struct
5828 **/
5829static int i40e_get_capabilities(struct i40e_pf *pf)
5830{
5831 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5832 u16 data_size;
5833 int buf_len;
5834 int err;
5835
5836 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5837 do {
5838 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5839 if (!cap_buf)
5840 return -ENOMEM;
5841
5842 /* this loads the data into the hw struct for us */
5843 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5844 &data_size,
5845 i40e_aqc_opc_list_func_capabilities,
5846 NULL);
5847 /* data loaded, buffer no longer needed */
5848 kfree(cap_buf);
5849
5850 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5851 /* retry with a larger buffer */
5852 buf_len = data_size;
5853 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5854 dev_info(&pf->pdev->dev,
5855 "capability discovery failed: aq=%d\n",
5856 pf->hw.aq.asq_last_status);
5857 return -ENODEV;
5858 }
5859 } while (err);
5860
ac71b7ba
ASJ		 5861 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5862 (pf->hw.aq.fw_maj_ver < 2)) {
5863 pf->hw.func_caps.num_msix_vectors++;
5864 pf->hw.func_caps.num_msix_vectors_vf++;
5865 }
5866
41c445ff
JB		 5867 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5868 dev_info(&pf->pdev->dev,
5869 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5870 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5871 pf->hw.func_caps.num_msix_vectors,
5872 pf->hw.func_caps.num_msix_vectors_vf,
5873 pf->hw.func_caps.fd_filters_guaranteed,
5874 pf->hw.func_caps.fd_filters_best_effort,
5875 pf->hw.func_caps.num_tx_qp,
5876 pf->hw.func_caps.num_vsis);
5877
7134f9ce
JB		 5878#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5879 + pf->hw.func_caps.num_vfs)
5880 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5881 dev_info(&pf->pdev->dev,
5882 "got num_vsis %d, setting num_vsis to %d\n",
5883 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5884 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5885 }
5886
41c445ff
JB		 5887 return 0;
5888}
5889
cbf61325
ASJ		 5890static int i40e_vsi_clear(struct i40e_vsi *vsi);
5891
41c445ff 5892/**
cbf61325 5893 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5894 * @pf: board private structure
5895 **/
cbf61325 5896static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5897{
5898 struct i40e_vsi *vsi;
8a9eb7d3 5899 int i;
41c445ff 5900
407e063c
JB		 5901 /* quick workaround for an NVM issue that leaves a critical register
5902 * uninitialized
5903 */
5904 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
5905 static const u32 hkey[] = {
5906 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
5907 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
5908 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
5909 0x95b3a76d};
5910
5911 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
5912 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
5913 }
5914
cbf61325 5915 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5916 return;
5917
cbf61325 5918 /* find existing VSI and see if it needs configuring */
41c445ff 5919 vsi = NULL;
505682cd 5920 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 5921 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5922 vsi = pf->vsi[i];
cbf61325
ASJ		 5923 break;
5924 }
5925 }
5926
5927 /* create a new VSI if none exists */
41c445ff 5928 if (!vsi) {
cbf61325
ASJ		 5929 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5930 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5931 if (!vsi) {
5932 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5933 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5934 return;
41c445ff 5935 }
cbf61325 5936 }
41c445ff 5937
8a9eb7d3 5938 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5939}
5940
5941/**
5942 * i40e_fdir_teardown - release the Flow Director resources
5943 * @pf: board private structure
5944 **/
5945static void i40e_fdir_teardown(struct i40e_pf *pf)
5946{
5947 int i;
5948
17a73f6b 5949 i40e_fdir_filter_exit(pf);
505682cd 5950 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 5951 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5952 i40e_vsi_release(pf->vsi[i]);
5953 break;
5954 }
5955 }
5956}
5957
5958/**
f650a38b 5959 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5960 * @pf: board private structure
5961 *
f650a38b
ASJ		 5962 * Close up the VFs and other things in prep for pf Reset.
5963 **/
23cfbe07 5964static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5965{
41c445ff 5966 struct i40e_hw *hw = &pf->hw;
60442dea 5967 i40e_status ret = 0;
41c445ff
JB		 5968 u32 v;
5969
5970 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5971 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 5972 return;
41c445ff 5973
69bfb110 5974 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5975
41c445ff
JB		 5976 /* quiesce the VSIs and their queues that are not already DOWN */
5977 i40e_pf_quiesce_all_vsi(pf);
5978
505682cd 5979 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5980 if (pf->vsi[v])
5981 pf->vsi[v]->seid = 0;
5982 }
5983
5984 i40e_shutdown_adminq(&pf->hw);
5985
f650a38b 5986 /* call shutdown HMC */
60442dea
SN		 5987 if (hw->hmc.hmc_obj) {
5988 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 5989 if (ret)
60442dea
SN		 5990 dev_warn(&pf->pdev->dev,
5991 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 5992 }
f650a38b
ASJ		 5993}
5994
44033fac
JB		 5995/**
5996 * i40e_send_version - update firmware with driver version
5997 * @pf: PF struct
5998 */
5999static void i40e_send_version(struct i40e_pf *pf)
6000{
6001 struct i40e_driver_version dv;
6002
6003 dv.major_version = DRV_VERSION_MAJOR;
6004 dv.minor_version = DRV_VERSION_MINOR;
6005 dv.build_version = DRV_VERSION_BUILD;
6006 dv.subbuild_version = 0;
35a7d804 6007 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6008 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6009}
6010
f650a38b 6011/**
4dda12e6 6012 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6013 * @pf: board private structure
bc7d338f 6014 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6015 **/
bc7d338f 6016static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6017{
f650a38b 6018 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6019 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6020 i40e_status ret;
6021 u32 v;
6022
41c445ff
JB		 6023 /* Now we wait for GRST to settle out.
6024 * We don't have to delete the VEBs or VSIs from the hw switch
6025 * because the reset will make them disappear.
6026 */
6027 ret = i40e_pf_reset(hw);
b5565400 6028 if (ret) {
41c445ff 6029 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6030 set_bit(__I40E_RESET_FAILED, &pf->state);
6031 goto clear_recovery;
b5565400 6032 }
41c445ff
JB		 6033 pf->pfr_count++;
6034
6035 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6036 goto clear_recovery;
69bfb110 6037 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6038
6039 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6040 ret = i40e_init_adminq(&pf->hw);
6041 if (ret) {
6042 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
a316f651 6043 goto clear_recovery;
41c445ff
JB		 6044 }
6045
4eb3f768
SN		 6046 /* re-verify the eeprom if we just had an EMP reset */
6047 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
6048 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
6049 i40e_verify_eeprom(pf);
6050 }
6051
e78ac4bf 6052 i40e_clear_pxe_mode(hw);
41c445ff
JB		 6053 ret = i40e_get_capabilities(pf);
6054 if (ret) {
6055 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
6056 ret);
6057 goto end_core_reset;
6058 }
6059
41c445ff
JB		 6060 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6061 hw->func_caps.num_rx_qp,
6062 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6063 if (ret) {
6064 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6065 goto end_core_reset;
6066 }
6067 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6068 if (ret) {
6069 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6070 goto end_core_reset;
6071 }
6072
4e3b35b0
NP		 6073#ifdef CONFIG_I40E_DCB
6074 ret = i40e_init_pf_dcb(pf);
6075 if (ret) {
6076 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
6077 goto end_core_reset;
6078 }
6079#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6080#ifdef I40E_FCOE
6081 ret = i40e_init_pf_fcoe(pf);
6082 if (ret)
6083 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6084
38e00438 6085#endif
41c445ff 6086 /* do basic switch setup */
bc7d338f 6087 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6088 if (ret)
6089 goto end_core_reset;
6090
7e2453fe
JB		 6091 /* driver is only interested in link up/down and module qualification
6092 * reports from firmware
6093 */
6094 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6095 I40E_AQ_EVENT_LINK_UPDOWN |
6096 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6097 if (ret)
6098 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", ret);
6099
cafa2ee6
ASJ		 6100 /* make sure our flow control settings are restored */
6101 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6102 if (ret)
6103 dev_info(&pf->pdev->dev, "set fc fail, aq_err %d\n", ret);
6104
41c445ff
JB		 6105 /* Rebuild the VSIs and VEBs that existed before reset.
6106 * They are still in our local switch element arrays, so only
6107 * need to rebuild the switch model in the HW.
6108 *
6109 * If there were VEBs but the reconstitution failed, we'll try
6110 * try to recover minimal use by getting the basic PF VSI working.
6111 */
6112 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6113 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6114 /* find the one VEB connected to the MAC, and find orphans */
6115 for (v = 0; v < I40E_MAX_VEB; v++) {
6116 if (!pf->veb[v])
6117 continue;
6118
6119 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6120 pf->veb[v]->uplink_seid == 0) {
6121 ret = i40e_reconstitute_veb(pf->veb[v]);
6122
6123 if (!ret)
6124 continue;
6125
6126 /* If Main VEB failed, we're in deep doodoo,
6127 * so give up rebuilding the switch and set up
6128 * for minimal rebuild of PF VSI.
6129 * If orphan failed, we'll report the error
6130 * but try to keep going.
6131 */
6132 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6133 dev_info(&pf->pdev->dev,
6134 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6135 ret);
6136 pf->vsi[pf->lan_vsi]->uplink_seid
6137 = pf->mac_seid;
6138 break;
6139 } else if (pf->veb[v]->uplink_seid == 0) {
6140 dev_info(&pf->pdev->dev,
6141 "rebuild of orphan VEB failed: %d\n",
6142 ret);
6143 }
6144 }
6145 }
6146 }
6147
6148 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6149 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6150 /* no VEB, so rebuild only the Main VSI */
6151 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6152 if (ret) {
6153 dev_info(&pf->pdev->dev,
6154 "rebuild of Main VSI failed: %d\n", ret);
6155 goto end_core_reset;
6156 }
6157 }
6158
cafa2ee6
ASJ		 6159 msleep(75);
6160 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6161 if (ret) {
6162 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
6163 pf->hw.aq.asq_last_status);
6164 }
6165
41c445ff
JB		 6166 /* reinit the misc interrupt */
6167 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6168 ret = i40e_setup_misc_vector(pf);
6169
6170 /* restart the VSIs that were rebuilt and running before the reset */
6171 i40e_pf_unquiesce_all_vsi(pf);
6172
69f64b2b
MW		 6173 if (pf->num_alloc_vfs) {
6174 for (v = 0; v < pf->num_alloc_vfs; v++)
6175 i40e_reset_vf(&pf->vf[v], true);
6176 }
6177
41c445ff 6178 /* tell the firmware that we're starting */
44033fac 6179 i40e_send_version(pf);
41c445ff
JB		 6180
6181end_core_reset:
a316f651
ASJ		 6182 clear_bit(__I40E_RESET_FAILED, &pf->state);
6183clear_recovery:
41c445ff
JB		 6184 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6185}
6186
f650a38b
ASJ		 6187/**
6188 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
6189 * @pf: board private structure
6190 *
6191 * Close up the VFs and other things in prep for a Core Reset,
6192 * then get ready to rebuild the world.
6193 **/
6194static void i40e_handle_reset_warning(struct i40e_pf *pf)
6195{
23cfbe07
SN		 6196 i40e_prep_for_reset(pf);
6197 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6198}
6199
41c445ff
JB		 6200/**
6201 * i40e_handle_mdd_event
6202 * @pf: pointer to the pf structure
6203 *
6204 * Called from the MDD irq handler to identify possibly malicious vfs
6205 **/
6206static void i40e_handle_mdd_event(struct i40e_pf *pf)
6207{
6208 struct i40e_hw *hw = &pf->hw;
6209 bool mdd_detected = false;
df430b12 6210 bool pf_mdd_detected = false;
41c445ff
JB		 6211 struct i40e_vf *vf;
6212 u32 reg;
6213 int i;
6214
6215 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6216 return;
6217
6218 /* find what triggered the MDD event */
6219 reg = rd32(hw, I40E_GL_MDET_TX);
6220 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6221 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6222 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6223 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6224 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6225 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6226 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6227 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6228 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6229 pf->hw.func_caps.base_queue;
faf32978
JB		 6230 if (netif_msg_tx_err(pf))
6231 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
6232 event, queue, pf_num, vf_num);
41c445ff
JB		 6233 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6234 mdd_detected = true;
6235 }
6236 reg = rd32(hw, I40E_GL_MDET_RX);
6237 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6238 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6239 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6240 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6241 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6242 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6243 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6244 pf->hw.func_caps.base_queue;
faf32978
JB		 6245 if (netif_msg_rx_err(pf))
6246 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6247 event, queue, func);
41c445ff
JB		 6248 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6249 mdd_detected = true;
6250 }
6251
df430b12
NP		 6252 if (mdd_detected) {
6253 reg = rd32(hw, I40E_PF_MDET_TX);
6254 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6255 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6256 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6257 pf_mdd_detected = true;
6258 }
6259 reg = rd32(hw, I40E_PF_MDET_RX);
6260 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6261 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6262 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6263 pf_mdd_detected = true;
6264 }
6265 /* Queue belongs to the PF, initiate a reset */
6266 if (pf_mdd_detected) {
6267 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6268 i40e_service_event_schedule(pf);
6269 }
6270 }
6271
41c445ff
JB		 6272 /* see if one of the VFs needs its hand slapped */
6273 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6274 vf = &(pf->vf[i]);
6275 reg = rd32(hw, I40E_VP_MDET_TX(i));
6276 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6277 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6278 vf->num_mdd_events++;
faf32978
JB		 6279 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6280 i);
41c445ff
JB		 6281 }
6282
6283 reg = rd32(hw, I40E_VP_MDET_RX(i));
6284 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6285 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6286 vf->num_mdd_events++;
faf32978
JB		 6287 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6288 i);
41c445ff
JB		 6289 }
6290
6291 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6292 dev_info(&pf->pdev->dev,
6293 "Too many MDD events on VF %d, disabled\n", i);
6294 dev_info(&pf->pdev->dev,
6295 "Use PF Control I/F to re-enable the VF\n");
6296 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6297 }
6298 }
6299
6300 /* re-enable mdd interrupt cause */
6301 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6302 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6303 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6304 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6305 i40e_flush(hw);
6306}
6307
a1c9a9d9
JK		 6308#ifdef CONFIG_I40E_VXLAN
6309/**
6310 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6311 * @pf: board private structure
6312 **/
6313static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6314{
a1c9a9d9
JK		 6315 struct i40e_hw *hw = &pf->hw;
6316 i40e_status ret;
6317 u8 filter_index;
6318 __be16 port;
6319 int i;
6320
6321 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6322 return;
6323
6324 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6325
6326 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6327 if (pf->pending_vxlan_bitmap & (1 << i)) {
6328 pf->pending_vxlan_bitmap &= ~(1 << i);
6329 port = pf->vxlan_ports[i];
6330 ret = port ?
6331 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6332 I40E_AQC_TUNNEL_TYPE_VXLAN,
6333 &filter_index, NULL)
6334 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6335
6336 if (ret) {
6337 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6338 port ? "adding" : "deleting",
6339 ntohs(port), port ? i : i);
6340
6341 pf->vxlan_ports[i] = 0;
6342 } else {
6343 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6344 port ? "Added" : "Deleted",
6345 ntohs(port), port ? i : filter_index);
6346 }
6347 }
6348 }
6349}
6350
6351#endif
41c445ff
JB		 6352/**
6353 * i40e_service_task - Run the driver's async subtasks
6354 * @work: pointer to work_struct containing our data
6355 **/
6356static void i40e_service_task(struct work_struct *work)
6357{
6358 struct i40e_pf *pf = container_of(work,
6359 struct i40e_pf,
6360 service_task);
6361 unsigned long start_time = jiffies;
6362
e57a2fea
SN		 6363 /* don't bother with service tasks if a reset is in progress */
6364 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6365 i40e_service_event_complete(pf);
6366 return;
6367 }
6368
41c445ff
JB		 6369 i40e_reset_subtask(pf);
6370 i40e_handle_mdd_event(pf);
6371 i40e_vc_process_vflr_event(pf);
6372 i40e_watchdog_subtask(pf);
6373 i40e_fdir_reinit_subtask(pf);
41c445ff 6374 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6375#ifdef CONFIG_I40E_VXLAN
6376 i40e_sync_vxlan_filters_subtask(pf);
6377#endif
41c445ff
JB		 6378 i40e_clean_adminq_subtask(pf);
6379
6380 i40e_service_event_complete(pf);
6381
6382 /* If the tasks have taken longer than one timer cycle or there
6383 * is more work to be done, reschedule the service task now
6384 * rather than wait for the timer to tick again.
6385 */
6386 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6387 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6388 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6389 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6390 i40e_service_event_schedule(pf);
6391}
6392
6393/**
6394 * i40e_service_timer - timer callback
6395 * @data: pointer to PF struct
6396 **/
6397static void i40e_service_timer(unsigned long data)
6398{
6399 struct i40e_pf *pf = (struct i40e_pf *)data;
6400
6401 mod_timer(&pf->service_timer,
6402 round_jiffies(jiffies + pf->service_timer_period));
6403 i40e_service_event_schedule(pf);
6404}
6405
6406/**
6407 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6408 * @vsi: the VSI being configured
6409 **/
6410static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6411{
6412 struct i40e_pf *pf = vsi->back;
6413
6414 switch (vsi->type) {
6415 case I40E_VSI_MAIN:
6416 vsi->alloc_queue_pairs = pf->num_lan_qps;
6417 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6418 I40E_REQ_DESCRIPTOR_MULTIPLE);
6419 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6420 vsi->num_q_vectors = pf->num_lan_msix;
6421 else
6422 vsi->num_q_vectors = 1;
6423
6424 break;
6425
6426 case I40E_VSI_FDIR:
6427 vsi->alloc_queue_pairs = 1;
6428 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6429 I40E_REQ_DESCRIPTOR_MULTIPLE);
6430 vsi->num_q_vectors = 1;
6431 break;
6432
6433 case I40E_VSI_VMDQ2:
6434 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6435 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6436 I40E_REQ_DESCRIPTOR_MULTIPLE);
6437 vsi->num_q_vectors = pf->num_vmdq_msix;
6438 break;
6439
6440 case I40E_VSI_SRIOV:
6441 vsi->alloc_queue_pairs = pf->num_vf_qps;
6442 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6443 I40E_REQ_DESCRIPTOR_MULTIPLE);
6444 break;
6445
38e00438
VD		 6446#ifdef I40E_FCOE
6447 case I40E_VSI_FCOE:
6448 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6449 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6450 I40E_REQ_DESCRIPTOR_MULTIPLE);
6451 vsi->num_q_vectors = pf->num_fcoe_msix;
6452 break;
6453
6454#endif /* I40E_FCOE */
41c445ff
JB		 6455 default:
6456 WARN_ON(1);
6457 return -ENODATA;
6458 }
6459
6460 return 0;
6461}
6462
f650a38b
ASJ		 6463/**
6464 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6465 * @type: VSI pointer
bc7d338f 6466 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6467 *
6468 * On error: returns error code (negative)
6469 * On success: returns 0
6470 **/
bc7d338f 6471static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6472{
6473 int size;
6474 int ret = 0;
6475
ac6c5e3d 6476 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6477 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6478 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6479 if (!vsi->tx_rings)
6480 return -ENOMEM;
f650a38b
ASJ		 6481 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6482
bc7d338f
ASJ		 6483 if (alloc_qvectors) {
6484 /* allocate memory for q_vector pointers */
f57e4fbd 6485 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6486 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6487 if (!vsi->q_vectors) {
6488 ret = -ENOMEM;
6489 goto err_vectors;
6490 }
f650a38b
ASJ		 6491 }
6492 return ret;
6493
6494err_vectors:
6495 kfree(vsi->tx_rings);
6496 return ret;
6497}
6498
41c445ff
JB		 6499/**
6500 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6501 * @pf: board private structure
6502 * @type: type of VSI
6503 *
6504 * On error: returns error code (negative)
6505 * On success: returns vsi index in PF (positive)
6506 **/
6507static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6508{
6509 int ret = -ENODEV;
6510 struct i40e_vsi *vsi;
6511 int vsi_idx;
6512 int i;
6513
6514 /* Need to protect the allocation of the VSIs at the PF level */
6515 mutex_lock(&pf->switch_mutex);
6516
6517 /* VSI list may be fragmented if VSI creation/destruction has
6518 * been happening. We can afford to do a quick scan to look
6519 * for any free VSIs in the list.
6520 *
6521 * find next empty vsi slot, looping back around if necessary
6522 */
6523 i = pf->next_vsi;
505682cd 6524 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6525 i++;
505682cd 6526 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6527 i = 0;
6528 while (i < pf->next_vsi && pf->vsi[i])
6529 i++;
6530 }
6531
505682cd 6532 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6533 vsi_idx = i; /* Found one! */
6534 } else {
6535 ret = -ENODEV;
493fb300 6536 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6537 }
6538 pf->next_vsi = ++i;
6539
6540 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6541 if (!vsi) {
6542 ret = -ENOMEM;
493fb300 6543 goto unlock_pf;
41c445ff
JB		 6544 }
6545 vsi->type = type;
6546 vsi->back = pf;
6547 set_bit(__I40E_DOWN, &vsi->state);
6548 vsi->flags = 0;
6549 vsi->idx = vsi_idx;
6550 vsi->rx_itr_setting = pf->rx_itr_default;
6551 vsi->tx_itr_setting = pf->tx_itr_default;
6552 vsi->netdev_registered = false;
6553 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6554 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6555 vsi->irqs_ready = false;
41c445ff 6556
9f65e15b
AD		 6557 ret = i40e_set_num_rings_in_vsi(vsi);
6558 if (ret)
6559 goto err_rings;
6560
bc7d338f 6561 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6562 if (ret)
9f65e15b 6563 goto err_rings;
493fb300 6564
41c445ff
JB		 6565 /* Setup default MSIX irq handler for VSI */
6566 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6567
6568 pf->vsi[vsi_idx] = vsi;
6569 ret = vsi_idx;
493fb300
AD		 6570 goto unlock_pf;
6571
9f65e15b 6572err_rings:
493fb300
AD		 6573 pf->next_vsi = i - 1;
6574 kfree(vsi);
6575unlock_pf:
41c445ff
JB		 6576 mutex_unlock(&pf->switch_mutex);
6577 return ret;
6578}
6579
f650a38b
ASJ		 6580/**
6581 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6582 * @type: VSI pointer
bc7d338f 6583 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6584 *
6585 * On error: returns error code (negative)
6586 * On success: returns 0
6587 **/
bc7d338f 6588static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6589{
6590 /* free the ring and vector containers */
bc7d338f
ASJ		 6591 if (free_qvectors) {
6592 kfree(vsi->q_vectors);
6593 vsi->q_vectors = NULL;
6594 }
f650a38b
ASJ		 6595 kfree(vsi->tx_rings);
6596 vsi->tx_rings = NULL;
6597 vsi->rx_rings = NULL;
6598}
6599
41c445ff
JB		 6600/**
6601 * i40e_vsi_clear - Deallocate the VSI provided
6602 * @vsi: the VSI being un-configured
6603 **/
6604static int i40e_vsi_clear(struct i40e_vsi *vsi)
6605{
6606 struct i40e_pf *pf;
6607
6608 if (!vsi)
6609 return 0;
6610
6611 if (!vsi->back)
6612 goto free_vsi;
6613 pf = vsi->back;
6614
6615 mutex_lock(&pf->switch_mutex);
6616 if (!pf->vsi[vsi->idx]) {
6617 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6618 vsi->idx, vsi->idx, vsi, vsi->type);
6619 goto unlock_vsi;
6620 }
6621
6622 if (pf->vsi[vsi->idx] != vsi) {
6623 dev_err(&pf->pdev->dev,
6624 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6625 pf->vsi[vsi->idx]->idx,
6626 pf->vsi[vsi->idx],
6627 pf->vsi[vsi->idx]->type,
6628 vsi->idx, vsi, vsi->type);
6629 goto unlock_vsi;
6630 }
6631
6632 /* updates the pf for this cleared vsi */
6633 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6634 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6635
bc7d338f 6636 i40e_vsi_free_arrays(vsi, true);
493fb300 6637
41c445ff
JB		 6638 pf->vsi[vsi->idx] = NULL;
6639 if (vsi->idx < pf->next_vsi)
6640 pf->next_vsi = vsi->idx;
6641
6642unlock_vsi:
6643 mutex_unlock(&pf->switch_mutex);
6644free_vsi:
6645 kfree(vsi);
6646
6647 return 0;
6648}
6649
9f65e15b
AD		 6650/**
6651 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6652 * @vsi: the VSI being cleaned
6653 **/
be1d5eea 6654static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6655{
6656 int i;
6657
8e9dca53 6658 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6659 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6660 kfree_rcu(vsi->tx_rings[i], rcu);
6661 vsi->tx_rings[i] = NULL;
6662 vsi->rx_rings[i] = NULL;
6663 }
be1d5eea 6664 }
9f65e15b
AD		 6665}
6666
41c445ff
JB		 6667/**
6668 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6669 * @vsi: the VSI being configured
6670 **/
6671static int i40e_alloc_rings(struct i40e_vsi *vsi)
6672{
e7046ee1 6673 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6674 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6675 int i;
6676
41c445ff 6677 /* Set basic values in the rings to be used later during open() */
d7397644 6678 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6679 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6680 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6681 if (!tx_ring)
6682 goto err_out;
41c445ff
JB		 6683
6684 tx_ring->queue_index = i;
6685 tx_ring->reg_idx = vsi->base_queue + i;
6686 tx_ring->ring_active = false;
6687 tx_ring->vsi = vsi;
6688 tx_ring->netdev = vsi->netdev;
6689 tx_ring->dev = &pf->pdev->dev;
6690 tx_ring->count = vsi->num_desc;
6691 tx_ring->size = 0;
6692 tx_ring->dcb_tc = 0;
9f65e15b 6693 vsi->tx_rings[i] = tx_ring;
41c445ff 6694
9f65e15b 6695 rx_ring = &tx_ring[1];
41c445ff
JB		 6696 rx_ring->queue_index = i;
6697 rx_ring->reg_idx = vsi->base_queue + i;
6698 rx_ring->ring_active = false;
6699 rx_ring->vsi = vsi;
6700 rx_ring->netdev = vsi->netdev;
6701 rx_ring->dev = &pf->pdev->dev;
6702 rx_ring->count = vsi->num_desc;
6703 rx_ring->size = 0;
6704 rx_ring->dcb_tc = 0;
6705 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6706 set_ring_16byte_desc_enabled(rx_ring);
6707 else
6708 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6709 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6710 }
6711
6712 return 0;
9f65e15b
AD		 6713
6714err_out:
6715 i40e_vsi_clear_rings(vsi);
6716 return -ENOMEM;
41c445ff
JB		 6717}
6718
6719/**
6720 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6721 * @pf: board private structure
6722 * @vectors: the number of MSI-X vectors to request
6723 *
6724 * Returns the number of vectors reserved, or error
6725 **/
6726static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6727{
7b37f376
AG		 6728 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6729 I40E_MIN_MSIX, vectors);
6730 if (vectors < 0) {
41c445ff 6731 dev_info(&pf->pdev->dev,
7b37f376 6732 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6733 vectors = 0;
6734 }
6735
6736 return vectors;
6737}
6738
6739/**
6740 * i40e_init_msix - Setup the MSIX capability
6741 * @pf: board private structure
6742 *
6743 * Work with the OS to set up the MSIX vectors needed.
6744 *
6745 * Returns 0 on success, negative on failure
6746 **/
6747static int i40e_init_msix(struct i40e_pf *pf)
6748{
6749 i40e_status err = 0;
6750 struct i40e_hw *hw = &pf->hw;
c135b0de 6751 int other_vecs = 0;
41c445ff
JB		 6752 int v_budget, i;
6753 int vec;
6754
6755 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6756 return -ENODEV;
6757
6758 /* The number of vectors we'll request will be comprised of:
6759 * - Add 1 for "other" cause for Admin Queue events, etc.
6760 * - The number of LAN queue pairs
f8ff1464
ASJ		 6761 * - Queues being used for RSS.
6762 * We don't need as many as max_rss_size vectors.
6763 * use rss_size instead in the calculation since that
6764 * is governed by number of cpus in the system.
6765 * - assumes symmetric Tx/Rx pairing
41c445ff 6766 * - The number of VMDq pairs
38e00438
VD		 6767#ifdef I40E_FCOE
6768 * - The number of FCOE qps.
6769#endif
41c445ff
JB		 6770 * Once we count this up, try the request.
6771 *
6772 * If we can't get what we want, we'll simplify to nearly nothing
6773 * and try again. If that still fails, we punt.
6774 */
f8ff1464 6775 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff 6776 pf->num_vmdq_msix = pf->num_vmdq_qps;
c135b0de
SN		 6777 other_vecs = 1;
6778 other_vecs += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6779 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
c135b0de 6780 other_vecs++;
41c445ff 6781
38e00438
VD		 6782#ifdef I40E_FCOE
6783 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6784 pf->num_fcoe_msix = pf->num_fcoe_qps;
6785 v_budget += pf->num_fcoe_msix;
6786 }
6787
6788#endif
41c445ff 6789 /* Scale down if necessary, and the rings will share vectors */
c135b0de
SN		 6790 pf->num_lan_msix = min_t(int, pf->num_lan_msix,
6791 (hw->func_caps.num_msix_vectors - other_vecs));
6792 v_budget = pf->num_lan_msix + other_vecs;
41c445ff
JB		 6793
6794 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6795 GFP_KERNEL);
6796 if (!pf->msix_entries)
6797 return -ENOMEM;
6798
6799 for (i = 0; i < v_budget; i++)
6800 pf->msix_entries[i].entry = i;
6801 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6802
6803 if (vec != v_budget) {
6804 /* If we have limited resources, we will start with no vectors
6805 * for the special features and then allocate vectors to some
6806 * of these features based on the policy and at the end disable
6807 * the features that did not get any vectors.
6808 */
38e00438
VD		 6809#ifdef I40E_FCOE
6810 pf->num_fcoe_qps = 0;
6811 pf->num_fcoe_msix = 0;
6812#endif
a34977ba
ASJ		 6813 pf->num_vmdq_msix = 0;
6814 }
6815
41c445ff
JB		 6816 if (vec < I40E_MIN_MSIX) {
6817 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6818 kfree(pf->msix_entries);
6819 pf->msix_entries = NULL;
6820 return -ENODEV;
6821
6822 } else if (vec == I40E_MIN_MSIX) {
6823 /* Adjust for minimal MSIX use */
41c445ff
JB		 6824 pf->num_vmdq_vsis = 0;
6825 pf->num_vmdq_qps = 0;
41c445ff
JB		 6826 pf->num_lan_qps = 1;
6827 pf->num_lan_msix = 1;
6828
6829 } else if (vec != v_budget) {
a34977ba
ASJ		 6830 /* reserve the misc vector */
6831 vec--;
6832
41c445ff
JB		 6833 /* Scale vector usage down */
6834 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6835 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6836
6837 /* partition out the remaining vectors */
6838 switch (vec) {
6839 case 2:
41c445ff
JB		 6840 pf->num_lan_msix = 1;
6841 break;
6842 case 3:
38e00438
VD		 6843#ifdef I40E_FCOE
6844 /* give one vector to FCoE */
6845 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6846 pf->num_lan_msix = 1;
6847 pf->num_fcoe_msix = 1;
6848 }
6849#else
41c445ff 6850 pf->num_lan_msix = 2;
38e00438 6851#endif
41c445ff
JB		 6852 break;
6853 default:
38e00438
VD		 6854#ifdef I40E_FCOE
6855 /* give one vector to FCoE */
6856 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6857 pf->num_fcoe_msix = 1;
6858 vec--;
6859 }
6860#endif
41c445ff
JB		 6861 pf->num_lan_msix = min_t(int, (vec / 2),
6862 pf->num_lan_qps);
6863 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6864 I40E_DEFAULT_NUM_VMDQ_VSI);
6865 break;
6866 }
6867 }
6868
a34977ba
ASJ		 6869 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
6870 (pf->num_vmdq_msix == 0)) {
6871 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
6872 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6873 }
38e00438
VD		 6874#ifdef I40E_FCOE
6875
6876 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
6877 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
6878 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
6879 }
6880#endif
41c445ff
JB		 6881 return err;
6882}
6883
493fb300 6884/**
90e04070 6885 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6886 * @vsi: the VSI being configured
6887 * @v_idx: index of the vector in the vsi struct
6888 *
6889 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6890 **/
90e04070 6891static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6892{
6893 struct i40e_q_vector *q_vector;
6894
6895 /* allocate q_vector */
6896 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6897 if (!q_vector)
6898 return -ENOMEM;
6899
6900 q_vector->vsi = vsi;
6901 q_vector->v_idx = v_idx;
6902 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6903 if (vsi->netdev)
6904 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 6905 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 6906
cd0b6fa6
AD		 6907 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6908 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6909
493fb300
AD		 6910 /* tie q_vector and vsi together */
6911 vsi->q_vectors[v_idx] = q_vector;
6912
6913 return 0;
6914}
6915
41c445ff 6916/**
90e04070 6917 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6918 * @vsi: the VSI being configured
6919 *
6920 * We allocate one q_vector per queue interrupt. If allocation fails we
6921 * return -ENOMEM.
6922 **/
90e04070 6923static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6924{
6925 struct i40e_pf *pf = vsi->back;
6926 int v_idx, num_q_vectors;
493fb300 6927 int err;
41c445ff
JB		 6928
6929 /* if not MSIX, give the one vector only to the LAN VSI */
6930 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6931 num_q_vectors = vsi->num_q_vectors;
6932 else if (vsi == pf->vsi[pf->lan_vsi])
6933 num_q_vectors = 1;
6934 else
6935 return -EINVAL;
6936
41c445ff 6937 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6938 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6939 if (err)
6940 goto err_out;
41c445ff
JB		 6941 }
6942
6943 return 0;
493fb300
AD		 6944
6945err_out:
6946 while (v_idx--)
6947 i40e_free_q_vector(vsi, v_idx);
6948
6949 return err;
41c445ff
JB		 6950}
6951
6952/**
6953 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6954 * @pf: board private structure to initialize
6955 **/
6956static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6957{
6958 int err = 0;
6959
6960 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6961 err = i40e_init_msix(pf);
6962 if (err) {
60ea5f83 6963 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 6964#ifdef I40E_FCOE
6965 I40E_FLAG_FCOE_ENABLED |
6966#endif
60ea5f83 6967 I40E_FLAG_RSS_ENABLED |
4d9b6043 6968 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 6969 I40E_FLAG_SRIOV_ENABLED |
6970 I40E_FLAG_FD_SB_ENABLED |
6971 I40E_FLAG_FD_ATR_ENABLED |
6972 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6973
6974 /* rework the queue expectations without MSIX */
6975 i40e_determine_queue_usage(pf);
6976 }
6977 }
6978
6979 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6980 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6981 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6982 err = pci_enable_msi(pf->pdev);
6983 if (err) {
958a3e3b 6984 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6985 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6986 }
6987 }
6988
958a3e3b 6989 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6990 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6991
41c445ff
JB		 6992 /* track first vector for misc interrupts */
6993 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6994}
6995
6996/**
6997 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6998 * @pf: board private structure
6999 *
7000 * This sets up the handler for MSIX 0, which is used to manage the
7001 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7002 * when in MSI or Legacy interrupt mode.
7003 **/
7004static int i40e_setup_misc_vector(struct i40e_pf *pf)
7005{
7006 struct i40e_hw *hw = &pf->hw;
7007 int err = 0;
7008
7009 /* Only request the irq if this is the first time through, and
7010 * not when we're rebuilding after a Reset
7011 */
7012 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7013 err = request_irq(pf->msix_entries[0].vector,
7014 i40e_intr, 0, pf->misc_int_name, pf);
7015 if (err) {
7016 dev_info(&pf->pdev->dev,
77fa28be
CS		 7017 "request_irq for %s failed: %d\n",
7018 pf->misc_int_name, err);
41c445ff
JB		 7019 return -EFAULT;
7020 }
7021 }
7022
7023 i40e_enable_misc_int_causes(hw);
7024
7025 /* associate no queues to the misc vector */
7026 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7027 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7028
7029 i40e_flush(hw);
7030
7031 i40e_irq_dynamic_enable_icr0(pf);
7032
7033 return err;
7034}
7035
7036/**
7037 * i40e_config_rss - Prepare for RSS if used
7038 * @pf: board private structure
7039 **/
7040static int i40e_config_rss(struct i40e_pf *pf)
7041{
22f258a1 7042 u32 rss_key[I40E_PFQF_HKEY_MAX_INDEX + 1];
4617e8c0
ASJ		 7043 struct i40e_hw *hw = &pf->hw;
7044 u32 lut = 0;
7045 int i, j;
7046 u64 hena;
e157ea30 7047 u32 reg_val;
41c445ff 7048
22f258a1 7049 netdev_rss_key_fill(rss_key, sizeof(rss_key));
41c445ff 7050 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
22f258a1 7051 wr32(hw, I40E_PFQF_HKEY(i), rss_key[i]);
41c445ff
JB		 7052
7053 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7054 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7055 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 7056 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 7057 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7058 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7059
e157ea30
CW		 7060 /* Check capability and Set table size and register per hw expectation*/
7061 reg_val = rd32(hw, I40E_PFQF_CTL_0);
7062 if (hw->func_caps.rss_table_size == 512) {
7063 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7064 pf->rss_table_size = 512;
7065 } else {
7066 pf->rss_table_size = 128;
7067 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7068 }
7069 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7070
41c445ff 7071 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7072 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7073
7074 /* The assumption is that lan qp count will be the highest
7075 * qp count for any PF VSI that needs RSS.
7076 * If multiple VSIs need RSS support, all the qp counts
7077 * for those VSIs should be a power of 2 for RSS to work.
7078 * If LAN VSI is the only consumer for RSS then this requirement
7079 * is not necessary.
7080 */
7081 if (j == pf->rss_size)
7082 j = 0;
7083 /* lut = 4-byte sliding window of 4 lut entries */
7084 lut = (lut << 8) | (j &
7085 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
7086 /* On i = 3, we have 4 entries in lut; write to the register */
7087 if ((i & 3) == 3)
7088 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7089 }
7090 i40e_flush(hw);
7091
7092 return 0;
7093}
7094
f8ff1464
ASJ		 7095/**
7096 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7097 * @pf: board private structure
7098 * @queue_count: the requested queue count for rss.
7099 *
7100 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7101 * count which may be different from the requested queue count.
7102 **/
7103int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7104{
7105 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7106 return 0;
7107
7108 queue_count = min_t(int, queue_count, pf->rss_size_max);
f8ff1464
ASJ		 7109
7110 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 7111 i40e_prep_for_reset(pf);
7112
f8ff1464
ASJ		 7113 pf->rss_size = queue_count;
7114
7115 i40e_reset_and_rebuild(pf, true);
7116 i40e_config_rss(pf);
7117 }
7118 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7119 return pf->rss_size;
7120}
7121
41c445ff
JB		 7122/**
7123 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7124 * @pf: board private structure to initialize
7125 *
7126 * i40e_sw_init initializes the Adapter private data structure.
7127 * Fields are initialized based on PCI device information and
7128 * OS network device settings (MTU size).
7129 **/
7130static int i40e_sw_init(struct i40e_pf *pf)
7131{
7132 int err = 0;
7133 int size;
7134
7135 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7136 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7137 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7138 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7139 if (I40E_DEBUG_USER & debug)
7140 pf->hw.debug_mask = debug;
7141 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7142 I40E_DEFAULT_MSG_ENABLE);
7143 }
7144
7145 /* Set default capability flags */
7146 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7147 I40E_FLAG_MSI_ENABLED |
7148 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 7149 I40E_FLAG_RX_1BUF_ENABLED;
7150
ca99eb99
MW		 7151 /* Set default ITR */
7152 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7153 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7154
7134f9ce
JB		 7155 /* Depending on PF configurations, it is possible that the RSS
7156 * maximum might end up larger than the available queues
7157 */
41c445ff 7158 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7159 pf->rss_size = 1;
7134f9ce
JB		 7160 pf->rss_size_max = min_t(int, pf->rss_size_max,
7161 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7162 if (pf->hw.func_caps.rss) {
7163 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7164 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7165 }
7166
2050bc65
CS		 7167 /* MFP mode enabled */
7168 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7169 pf->flags |= I40E_FLAG_MFP_ENABLED;
7170 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
7171 }
7172
cbf61325
ASJ		 7173 /* FW/NVM is not yet fixed in this regard */
7174 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7175 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7176 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7177 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 7178 /* Setup a counter for fd_atr per pf */
7179 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7180 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7181 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 7182 /* Setup a counter for fd_sb per pf */
7183 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7184 } else {
7185 dev_info(&pf->pdev->dev,
0b67584f 7186 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7187 }
cbf61325
ASJ		 7188 pf->fdir_pf_filter_count =
7189 pf->hw.func_caps.fd_filters_guaranteed;
7190 pf->hw.fdir_shared_filter_count =
7191 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7192 }
7193
7194 if (pf->hw.func_caps.vmdq) {
7195 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7196 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7197 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7198 }
7199
38e00438
VD		 7200#ifdef I40E_FCOE
7201 err = i40e_init_pf_fcoe(pf);
7202 if (err)
7203 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7204
7205#endif /* I40E_FCOE */
41c445ff
JB		 7206#ifdef CONFIG_PCI_IOV
7207 if (pf->hw.func_caps.num_vfs) {
7208 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7209 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7210 pf->num_req_vfs = min_t(int,
7211 pf->hw.func_caps.num_vfs,
7212 I40E_MAX_VF_COUNT);
7213 }
7214#endif /* CONFIG_PCI_IOV */
7215 pf->eeprom_version = 0xDEAD;
7216 pf->lan_veb = I40E_NO_VEB;
7217 pf->lan_vsi = I40E_NO_VSI;
7218
7219 /* set up queue assignment tracking */
7220 size = sizeof(struct i40e_lump_tracking)
7221 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7222 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7223 if (!pf->qp_pile) {
7224 err = -ENOMEM;
7225 goto sw_init_done;
7226 }
7227 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7228 pf->qp_pile->search_hint = 0;
7229
7230 /* set up vector assignment tracking */
7231 size = sizeof(struct i40e_lump_tracking)
7232 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
7233 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7234 if (!pf->irq_pile) {
7235 kfree(pf->qp_pile);
7236 err = -ENOMEM;
7237 goto sw_init_done;
7238 }
7239 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
7240 pf->irq_pile->search_hint = 0;
7241
327fe04b
ASJ		 7242 pf->tx_timeout_recovery_level = 1;
7243
41c445ff
JB		 7244 mutex_init(&pf->switch_mutex);
7245
7246sw_init_done:
7247 return err;
7248}
7249
7c3c288b
ASJ		 7250/**
7251 * i40e_set_ntuple - set the ntuple feature flag and take action
7252 * @pf: board private structure to initialize
7253 * @features: the feature set that the stack is suggesting
7254 *
7255 * returns a bool to indicate if reset needs to happen
7256 **/
7257bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7258{
7259 bool need_reset = false;
7260
7261 /* Check if Flow Director n-tuple support was enabled or disabled. If
7262 * the state changed, we need to reset.
7263 */
7264 if (features & NETIF_F_NTUPLE) {
7265 /* Enable filters and mark for reset */
7266 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7267 need_reset = true;
7268 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7269 } else {
7270 /* turn off filters, mark for reset and clear SW filter list */
7271 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7272 need_reset = true;
7273 i40e_fdir_filter_exit(pf);
7274 }
7275 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7276 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7277 /* reset fd counters */
7278 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7279 pf->fdir_pf_active_filters = 0;
7280 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7281 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7282 /* if ATR was auto disabled it can be re-enabled. */
7283 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7284 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7285 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7286 }
7287 return need_reset;
7288}
7289
41c445ff
JB		 7290/**
7291 * i40e_set_features - set the netdev feature flags
7292 * @netdev: ptr to the netdev being adjusted
7293 * @features: the feature set that the stack is suggesting
7294 **/
7295static int i40e_set_features(struct net_device *netdev,
7296 netdev_features_t features)
7297{
7298 struct i40e_netdev_priv *np = netdev_priv(netdev);
7299 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7300 struct i40e_pf *pf = vsi->back;
7301 bool need_reset;
41c445ff
JB		 7302
7303 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7304 i40e_vlan_stripping_enable(vsi);
7305 else
7306 i40e_vlan_stripping_disable(vsi);
7307
7c3c288b
ASJ		 7308 need_reset = i40e_set_ntuple(pf, features);
7309
7310 if (need_reset)
7311 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7312
41c445ff
JB		 7313 return 0;
7314}
7315
a1c9a9d9
JK		 7316#ifdef CONFIG_I40E_VXLAN
7317/**
7318 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7319 * @pf: board private structure
7320 * @port: The UDP port to look up
7321 *
7322 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7323 **/
7324static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7325{
7326 u8 i;
7327
7328 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7329 if (pf->vxlan_ports[i] == port)
7330 return i;
7331 }
7332
7333 return i;
7334}
7335
7336/**
7337 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7338 * @netdev: This physical port's netdev
7339 * @sa_family: Socket Family that VXLAN is notifying us about
7340 * @port: New UDP port number that VXLAN started listening to
7341 **/
7342static void i40e_add_vxlan_port(struct net_device *netdev,
7343 sa_family_t sa_family, __be16 port)
7344{
7345 struct i40e_netdev_priv *np = netdev_priv(netdev);
7346 struct i40e_vsi *vsi = np->vsi;
7347 struct i40e_pf *pf = vsi->back;
7348 u8 next_idx;
7349 u8 idx;
7350
7351 if (sa_family == AF_INET6)
7352 return;
7353
7354 idx = i40e_get_vxlan_port_idx(pf, port);
7355
7356 /* Check if port already exists */
7357 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7358 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7359 return;
7360 }
7361
7362 /* Now check if there is space to add the new port */
7363 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7364
7365 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7366 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7367 ntohs(port));
7368 return;
7369 }
7370
7371 /* New port: add it and mark its index in the bitmap */
7372 pf->vxlan_ports[next_idx] = port;
7373 pf->pending_vxlan_bitmap |= (1 << next_idx);
7374
7375 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7376}
7377
7378/**
7379 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7380 * @netdev: This physical port's netdev
7381 * @sa_family: Socket Family that VXLAN is notifying us about
7382 * @port: UDP port number that VXLAN stopped listening to
7383 **/
7384static void i40e_del_vxlan_port(struct net_device *netdev,
7385 sa_family_t sa_family, __be16 port)
7386{
7387 struct i40e_netdev_priv *np = netdev_priv(netdev);
7388 struct i40e_vsi *vsi = np->vsi;
7389 struct i40e_pf *pf = vsi->back;
7390 u8 idx;
7391
7392 if (sa_family == AF_INET6)
7393 return;
7394
7395 idx = i40e_get_vxlan_port_idx(pf, port);
7396
7397 /* Check if port already exists */
7398 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7399 /* if port exists, set it to 0 (mark for deletion)
7400 * and make it pending
7401 */
7402 pf->vxlan_ports[idx] = 0;
7403
7404 pf->pending_vxlan_bitmap |= (1 << idx);
7405
7406 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7407 } else {
7408 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7409 ntohs(port));
7410 }
7411}
7412
7413#endif
1f224ad2
NP		 7414static int i40e_get_phys_port_id(struct net_device *netdev,
7415 struct netdev_phys_port_id *ppid)
7416{
7417 struct i40e_netdev_priv *np = netdev_priv(netdev);
7418 struct i40e_pf *pf = np->vsi->back;
7419 struct i40e_hw *hw = &pf->hw;
7420
7421 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7422 return -EOPNOTSUPP;
7423
7424 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7425 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7426
7427 return 0;
7428}
7429
4ba0dea5
GR		 7430#ifdef HAVE_FDB_OPS
7431#ifdef USE_CONST_DEV_UC_CHAR
7432static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7433 struct net_device *dev,
7434 const unsigned char *addr,
7435 u16 flags)
7436#else
7437static int i40e_ndo_fdb_add(struct ndmsg *ndm,
7438 struct net_device *dev,
7439 unsigned char *addr,
7440 u16 flags)
7441#endif
7442{
7443 struct i40e_netdev_priv *np = netdev_priv(dev);
7444 struct i40e_pf *pf = np->vsi->back;
7445 int err = 0;
7446
7447 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7448 return -EOPNOTSUPP;
7449
7450 /* Hardware does not support aging addresses so if a
7451 * ndm_state is given only allow permanent addresses
7452 */
7453 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7454 netdev_info(dev, "FDB only supports static addresses\n");
7455 return -EINVAL;
7456 }
7457
7458 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7459 err = dev_uc_add_excl(dev, addr);
7460 else if (is_multicast_ether_addr(addr))
7461 err = dev_mc_add_excl(dev, addr);
7462 else
7463 err = -EINVAL;
7464
7465 /* Only return duplicate errors if NLM_F_EXCL is set */
7466 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7467 err = 0;
7468
7469 return err;
7470}
7471
7472#ifndef USE_DEFAULT_FDB_DEL_DUMP
7473#ifdef USE_CONST_DEV_UC_CHAR
7474static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7475 struct net_device *dev,
7476 const unsigned char *addr)
7477#else
7478static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7479 struct net_device *dev,
7480 unsigned char *addr)
7481#endif
7482{
7483 struct i40e_netdev_priv *np = netdev_priv(dev);
7484 struct i40e_pf *pf = np->vsi->back;
7485 int err = -EOPNOTSUPP;
7486
7487 if (ndm->ndm_state & NUD_PERMANENT) {
7488 netdev_info(dev, "FDB only supports static addresses\n");
7489 return -EINVAL;
7490 }
7491
7492 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7493 if (is_unicast_ether_addr(addr))
7494 err = dev_uc_del(dev, addr);
7495 else if (is_multicast_ether_addr(addr))
7496 err = dev_mc_del(dev, addr);
7497 else
7498 err = -EINVAL;
7499 }
7500
7501 return err;
7502}
7503
7504static int i40e_ndo_fdb_dump(struct sk_buff *skb,
7505 struct netlink_callback *cb,
7506 struct net_device *dev,
5d5eacb3 7507 struct net_device *filter_dev,
4ba0dea5
GR		 7508 int idx)
7509{
7510 struct i40e_netdev_priv *np = netdev_priv(dev);
7511 struct i40e_pf *pf = np->vsi->back;
7512
7513 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
5d5eacb3 7514 idx = ndo_dflt_fdb_dump(skb, cb, dev, filter_dev, idx);
4ba0dea5
GR		 7515
7516 return idx;
7517}
7518
7519#endif /* USE_DEFAULT_FDB_DEL_DUMP */
7520#endif /* HAVE_FDB_OPS */
41c445ff
JB		 7521static const struct net_device_ops i40e_netdev_ops = {
7522 .ndo_open = i40e_open,
7523 .ndo_stop = i40e_close,
7524 .ndo_start_xmit = i40e_lan_xmit_frame,
7525 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7526 .ndo_set_rx_mode = i40e_set_rx_mode,
7527 .ndo_validate_addr = eth_validate_addr,
7528 .ndo_set_mac_address = i40e_set_mac,
7529 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7530 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7531 .ndo_tx_timeout = i40e_tx_timeout,
7532 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7533 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7534#ifdef CONFIG_NET_POLL_CONTROLLER
7535 .ndo_poll_controller = i40e_netpoll,
7536#endif
7537 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 7538#ifdef I40E_FCOE
7539 .ndo_fcoe_enable = i40e_fcoe_enable,
7540 .ndo_fcoe_disable = i40e_fcoe_disable,
7541#endif
41c445ff
JB		 7542 .ndo_set_features = i40e_set_features,
7543 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7544 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7545 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7546 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7547 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 7548 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 7549#ifdef CONFIG_I40E_VXLAN
7550 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7551 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7552#endif
1f224ad2 7553 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5
GR		 7554#ifdef HAVE_FDB_OPS
7555 .ndo_fdb_add = i40e_ndo_fdb_add,
7556#ifndef USE_DEFAULT_FDB_DEL_DUMP
7557 .ndo_fdb_del = i40e_ndo_fdb_del,
7558 .ndo_fdb_dump = i40e_ndo_fdb_dump,
7559#endif
7560#endif
41c445ff
JB		 7561};
7562
7563/**
7564 * i40e_config_netdev - Setup the netdev flags
7565 * @vsi: the VSI being configured
7566 *
7567 * Returns 0 on success, negative value on failure
7568 **/
7569static int i40e_config_netdev(struct i40e_vsi *vsi)
7570{
1a10370a 7571 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7572 struct i40e_pf *pf = vsi->back;
7573 struct i40e_hw *hw = &pf->hw;
7574 struct i40e_netdev_priv *np;
7575 struct net_device *netdev;
7576 u8 mac_addr[ETH_ALEN];
7577 int etherdev_size;
7578
7579 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7580 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7581 if (!netdev)
7582 return -ENOMEM;
7583
7584 vsi->netdev = netdev;
7585 np = netdev_priv(netdev);
7586 np->vsi = vsi;
7587
d70e941b 7588 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7589 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7590 NETIF_F_TSO;
41c445ff
JB		 7591
7592 netdev->features = NETIF_F_SG |
7593 NETIF_F_IP_CSUM |
7594 NETIF_F_SCTP_CSUM |
7595 NETIF_F_HIGHDMA |
7596 NETIF_F_GSO_UDP_TUNNEL |
7597 NETIF_F_HW_VLAN_CTAG_TX |
7598 NETIF_F_HW_VLAN_CTAG_RX |
7599 NETIF_F_HW_VLAN_CTAG_FILTER |
7600 NETIF_F_IPV6_CSUM |
7601 NETIF_F_TSO |
059dab69 7602 NETIF_F_TSO_ECN |
41c445ff
JB		 7603 NETIF_F_TSO6 |
7604 NETIF_F_RXCSUM |
7605 NETIF_F_RXHASH |
7606 0;
7607
2e86a0b6
ASJ		 7608 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7609 netdev->features |= NETIF_F_NTUPLE;
7610
41c445ff
JB		 7611 /* copy netdev features into list of user selectable features */
7612 netdev->hw_features |= netdev->features;
7613
7614 if (vsi->type == I40E_VSI_MAIN) {
7615 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7616 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 7617 /* The following steps are necessary to prevent reception
7618 * of tagged packets - some older NVM configurations load a
7619 * default a MAC-VLAN filter that accepts any tagged packet
7620 * which must be replaced by a normal filter.
8c27d42e 7621 */
30650cc5
SN		 7622 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
7623 i40e_add_filter(vsi, mac_addr,
7624 I40E_VLAN_ANY, false, true);
41c445ff
JB		 7625 } else {
7626 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7627 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7628 pf->vsi[pf->lan_vsi]->netdev->name);
7629 random_ether_addr(mac_addr);
7630 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7631 }
1a10370a 7632 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7633
9a173901
GR		 7634 ether_addr_copy(netdev->dev_addr, mac_addr);
7635 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 7636 /* vlan gets same features (except vlan offload)
7637 * after any tweaks for specific VSI types
7638 */
7639 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
7640 NETIF_F_HW_VLAN_CTAG_RX |
7641 NETIF_F_HW_VLAN_CTAG_FILTER);
7642 netdev->priv_flags |= IFF_UNICAST_FLT;
7643 netdev->priv_flags |= IFF_SUPP_NOFCS;
7644 /* Setup netdev TC information */
7645 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
7646
7647 netdev->netdev_ops = &i40e_netdev_ops;
7648 netdev->watchdog_timeo = 5 * HZ;
7649 i40e_set_ethtool_ops(netdev);
38e00438
VD		 7650#ifdef I40E_FCOE
7651 i40e_fcoe_config_netdev(netdev, vsi);
7652#endif
41c445ff
JB		 7653
7654 return 0;
7655}
7656
7657/**
7658 * i40e_vsi_delete - Delete a VSI from the switch
7659 * @vsi: the VSI being removed
7660 *
7661 * Returns 0 on success, negative value on failure
7662 **/
7663static void i40e_vsi_delete(struct i40e_vsi *vsi)
7664{
7665 /* remove default VSI is not allowed */
7666 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
7667 return;
7668
41c445ff 7669 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 7670}
7671
7672/**
7673 * i40e_add_vsi - Add a VSI to the switch
7674 * @vsi: the VSI being configured
7675 *
7676 * This initializes a VSI context depending on the VSI type to be added and
7677 * passes it down to the add_vsi aq command.
7678 **/
7679static int i40e_add_vsi(struct i40e_vsi *vsi)
7680{
7681 int ret = -ENODEV;
7682 struct i40e_mac_filter *f, *ftmp;
7683 struct i40e_pf *pf = vsi->back;
7684 struct i40e_hw *hw = &pf->hw;
7685 struct i40e_vsi_context ctxt;
7686 u8 enabled_tc = 0x1; /* TC0 enabled */
7687 int f_count = 0;
7688
7689 memset(&ctxt, 0, sizeof(ctxt));
7690 switch (vsi->type) {
7691 case I40E_VSI_MAIN:
7692 /* The PF's main VSI is already setup as part of the
7693 * device initialization, so we'll not bother with
7694 * the add_vsi call, but we will retrieve the current
7695 * VSI context.
7696 */
7697 ctxt.seid = pf->main_vsi_seid;
7698 ctxt.pf_num = pf->hw.pf_id;
7699 ctxt.vf_num = 0;
7700 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7701 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7702 if (ret) {
7703 dev_info(&pf->pdev->dev,
7704 "couldn't get pf vsi config, err %d, aq_err %d\n",
7705 ret, pf->hw.aq.asq_last_status);
7706 return -ENOENT;
7707 }
7708 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7709 vsi->info.valid_sections = 0;
7710
7711 vsi->seid = ctxt.seid;
7712 vsi->id = ctxt.vsi_number;
7713
7714 enabled_tc = i40e_pf_get_tc_map(pf);
7715
7716 /* MFP mode setup queue map and update VSI */
7717 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7718 memset(&ctxt, 0, sizeof(ctxt));
7719 ctxt.seid = pf->main_vsi_seid;
7720 ctxt.pf_num = pf->hw.pf_id;
7721 ctxt.vf_num = 0;
7722 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7723 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7724 if (ret) {
7725 dev_info(&pf->pdev->dev,
7726 "update vsi failed, aq_err=%d\n",
7727 pf->hw.aq.asq_last_status);
7728 ret = -ENOENT;
7729 goto err;
7730 }
7731 /* update the local VSI info queue map */
7732 i40e_vsi_update_queue_map(vsi, &ctxt);
7733 vsi->info.valid_sections = 0;
7734 } else {
7735 /* Default/Main VSI is only enabled for TC0
7736 * reconfigure it to enable all TCs that are
7737 * available on the port in SFP mode.
7738 */
7739 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7740 if (ret) {
7741 dev_info(&pf->pdev->dev,
7742 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7743 enabled_tc, ret,
7744 pf->hw.aq.asq_last_status);
7745 ret = -ENOENT;
7746 }
7747 }
7748 break;
7749
7750 case I40E_VSI_FDIR:
cbf61325
ASJ		 7751 ctxt.pf_num = hw->pf_id;
7752 ctxt.vf_num = 0;
7753 ctxt.uplink_seid = vsi->uplink_seid;
7754 ctxt.connection_type = 0x1; /* regular data port */
7755 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7756 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7757 break;
7758
7759 case I40E_VSI_VMDQ2:
7760 ctxt.pf_num = hw->pf_id;
7761 ctxt.vf_num = 0;
7762 ctxt.uplink_seid = vsi->uplink_seid;
7763 ctxt.connection_type = 0x1; /* regular data port */
7764 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7765
7766 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7767
7768 /* This VSI is connected to VEB so the switch_id
7769 * should be set to zero by default.
7770 */
7771 ctxt.info.switch_id = 0;
41c445ff
JB		 7772 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7773
7774 /* Setup the VSI tx/rx queue map for TC0 only for now */
7775 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7776 break;
7777
7778 case I40E_VSI_SRIOV:
7779 ctxt.pf_num = hw->pf_id;
7780 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7781 ctxt.uplink_seid = vsi->uplink_seid;
7782 ctxt.connection_type = 0x1; /* regular data port */
7783 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7784
7785 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7786
7787 /* This VSI is connected to VEB so the switch_id
7788 * should be set to zero by default.
7789 */
7790 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7791
7792 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7793 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 7794 if (pf->vf[vsi->vf_id].spoofchk) {
7795 ctxt.info.valid_sections |=
7796 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
7797 ctxt.info.sec_flags |=
7798 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
7799 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
7800 }
41c445ff
JB		 7801 /* Setup the VSI tx/rx queue map for TC0 only for now */
7802 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7803 break;
7804
38e00438
VD		 7805#ifdef I40E_FCOE
7806 case I40E_VSI_FCOE:
7807 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
7808 if (ret) {
7809 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
7810 return ret;
7811 }
7812 break;
7813
7814#endif /* I40E_FCOE */
41c445ff
JB		 7815 default:
7816 return -ENODEV;
7817 }
7818
7819 if (vsi->type != I40E_VSI_MAIN) {
7820 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7821 if (ret) {
7822 dev_info(&vsi->back->pdev->dev,
7823 "add vsi failed, aq_err=%d\n",
7824 vsi->back->hw.aq.asq_last_status);
7825 ret = -ENOENT;
7826 goto err;
7827 }
7828 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7829 vsi->info.valid_sections = 0;
7830 vsi->seid = ctxt.seid;
7831 vsi->id = ctxt.vsi_number;
7832 }
7833
7834 /* If macvlan filters already exist, force them to get loaded */
7835 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7836 f->changed = true;
7837 f_count++;
6252c7e4
SN		 7838
7839 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 7840 struct i40e_aqc_remove_macvlan_element_data element;
7841
7842 memset(&element, 0, sizeof(element));
7843 ether_addr_copy(element.mac_addr, f->macaddr);
7844 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7845 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
7846 &element, 1, NULL);
7847 if (ret) {
7848 /* some older FW has a different default */
7849 element.flags |=
7850 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7851 i40e_aq_remove_macvlan(hw, vsi->seid,
7852 &element, 1, NULL);
7853 }
7854
7855 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 7856 I40E_AQC_WRITE_TYPE_LAA_WOL,
7857 f->macaddr, NULL);
7858 }
41c445ff
JB		 7859 }
7860 if (f_count) {
7861 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7862 pf->flags |= I40E_FLAG_FILTER_SYNC;
7863 }
7864
7865 /* Update VSI BW information */
7866 ret = i40e_vsi_get_bw_info(vsi);
7867 if (ret) {
7868 dev_info(&pf->pdev->dev,
7869 "couldn't get vsi bw info, err %d, aq_err %d\n",
7870 ret, pf->hw.aq.asq_last_status);
7871 /* VSI is already added so not tearing that up */
7872 ret = 0;
7873 }
7874
7875err:
7876 return ret;
7877}
7878
7879/**
7880 * i40e_vsi_release - Delete a VSI and free its resources
7881 * @vsi: the VSI being removed
7882 *
7883 * Returns 0 on success or < 0 on error
7884 **/
7885int i40e_vsi_release(struct i40e_vsi *vsi)
7886{
7887 struct i40e_mac_filter *f, *ftmp;
7888 struct i40e_veb *veb = NULL;
7889 struct i40e_pf *pf;
7890 u16 uplink_seid;
7891 int i, n;
7892
7893 pf = vsi->back;
7894
7895 /* release of a VEB-owner or last VSI is not allowed */
7896 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7897 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7898 vsi->seid, vsi->uplink_seid);
7899 return -ENODEV;
7900 }
7901 if (vsi == pf->vsi[pf->lan_vsi] &&
7902 !test_bit(__I40E_DOWN, &pf->state)) {
7903 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7904 return -ENODEV;
7905 }
7906
7907 uplink_seid = vsi->uplink_seid;
7908 if (vsi->type != I40E_VSI_SRIOV) {
7909 if (vsi->netdev_registered) {
7910 vsi->netdev_registered = false;
7911 if (vsi->netdev) {
7912 /* results in a call to i40e_close() */
7913 unregister_netdev(vsi->netdev);
41c445ff
JB		 7914 }
7915 } else {
90ef8d47 7916 i40e_vsi_close(vsi);
41c445ff
JB		 7917 }
7918 i40e_vsi_disable_irq(vsi);
7919 }
7920
7921 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7922 i40e_del_filter(vsi, f->macaddr, f->vlan,
7923 f->is_vf, f->is_netdev);
7924 i40e_sync_vsi_filters(vsi);
7925
7926 i40e_vsi_delete(vsi);
7927 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7928 if (vsi->netdev) {
7929 free_netdev(vsi->netdev);
7930 vsi->netdev = NULL;
7931 }
41c445ff
JB		 7932 i40e_vsi_clear_rings(vsi);
7933 i40e_vsi_clear(vsi);
7934
7935 /* If this was the last thing on the VEB, except for the
7936 * controlling VSI, remove the VEB, which puts the controlling
7937 * VSI onto the next level down in the switch.
7938 *
7939 * Well, okay, there's one more exception here: don't remove
7940 * the orphan VEBs yet. We'll wait for an explicit remove request
7941 * from up the network stack.
7942 */
505682cd 7943 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7944 if (pf->vsi[i] &&
7945 pf->vsi[i]->uplink_seid == uplink_seid &&
7946 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7947 n++; /* count the VSIs */
7948 }
7949 }
7950 for (i = 0; i < I40E_MAX_VEB; i++) {
7951 if (!pf->veb[i])
7952 continue;
7953 if (pf->veb[i]->uplink_seid == uplink_seid)
7954 n++; /* count the VEBs */
7955 if (pf->veb[i]->seid == uplink_seid)
7956 veb = pf->veb[i];
7957 }
7958 if (n == 0 && veb && veb->uplink_seid != 0)
7959 i40e_veb_release(veb);
7960
7961 return 0;
7962}
7963
7964/**
7965 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7966 * @vsi: ptr to the VSI
7967 *
7968 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7969 * corresponding SW VSI structure and initializes num_queue_pairs for the
7970 * newly allocated VSI.
7971 *
7972 * Returns 0 on success or negative on failure
7973 **/
7974static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7975{
7976 int ret = -ENOENT;
7977 struct i40e_pf *pf = vsi->back;
7978
493fb300 7979 if (vsi->q_vectors[0]) {
41c445ff
JB		 7980 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7981 vsi->seid);
7982 return -EEXIST;
7983 }
7984
7985 if (vsi->base_vector) {
f29eaa3d 7986 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7987 vsi->seid, vsi->base_vector);
7988 return -EEXIST;
7989 }
7990
90e04070 7991 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7992 if (ret) {
7993 dev_info(&pf->pdev->dev,
7994 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7995 vsi->num_q_vectors, vsi->seid, ret);
7996 vsi->num_q_vectors = 0;
7997 goto vector_setup_out;
7998 }
7999
958a3e3b
SN		 8000 if (vsi->num_q_vectors)
8001 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8002 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8003 if (vsi->base_vector < 0) {
8004 dev_info(&pf->pdev->dev,
049a2be8
SN		 8005 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8006 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8007 i40e_vsi_free_q_vectors(vsi);
8008 ret = -ENOENT;
8009 goto vector_setup_out;
8010 }
8011
8012vector_setup_out:
8013 return ret;
8014}
8015
bc7d338f
ASJ		 8016/**
8017 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8018 * @vsi: pointer to the vsi.
8019 *
8020 * This re-allocates a vsi's queue resources.
8021 *
8022 * Returns pointer to the successfully allocated and configured VSI sw struct
8023 * on success, otherwise returns NULL on failure.
8024 **/
8025static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8026{
8027 struct i40e_pf *pf = vsi->back;
8028 u8 enabled_tc;
8029 int ret;
8030
8031 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8032 i40e_vsi_clear_rings(vsi);
8033
8034 i40e_vsi_free_arrays(vsi, false);
8035 i40e_set_num_rings_in_vsi(vsi);
8036 ret = i40e_vsi_alloc_arrays(vsi, false);
8037 if (ret)
8038 goto err_vsi;
8039
8040 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8041 if (ret < 0) {
049a2be8
SN		 8042 dev_info(&pf->pdev->dev,
8043 "failed to get tracking for %d queues for VSI %d err=%d\n",
8044 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8045 goto err_vsi;
8046 }
8047 vsi->base_queue = ret;
8048
8049 /* Update the FW view of the VSI. Force a reset of TC and queue
8050 * layout configurations.
8051 */
8052 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8053 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8054 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8055 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8056
8057 /* assign it some queues */
8058 ret = i40e_alloc_rings(vsi);
8059 if (ret)
8060 goto err_rings;
8061
8062 /* map all of the rings to the q_vectors */
8063 i40e_vsi_map_rings_to_vectors(vsi);
8064 return vsi;
8065
8066err_rings:
8067 i40e_vsi_free_q_vectors(vsi);
8068 if (vsi->netdev_registered) {
8069 vsi->netdev_registered = false;
8070 unregister_netdev(vsi->netdev);
8071 free_netdev(vsi->netdev);
8072 vsi->netdev = NULL;
8073 }
8074 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8075err_vsi:
8076 i40e_vsi_clear(vsi);
8077 return NULL;
8078}
8079
41c445ff
JB		 8080/**
8081 * i40e_vsi_setup - Set up a VSI by a given type
8082 * @pf: board private structure
8083 * @type: VSI type
8084 * @uplink_seid: the switch element to link to
8085 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8086 *
8087 * This allocates the sw VSI structure and its queue resources, then add a VSI
8088 * to the identified VEB.
8089 *
8090 * Returns pointer to the successfully allocated and configure VSI sw struct on
8091 * success, otherwise returns NULL on failure.
8092 **/
8093struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8094 u16 uplink_seid, u32 param1)
8095{
8096 struct i40e_vsi *vsi = NULL;
8097 struct i40e_veb *veb = NULL;
8098 int ret, i;
8099 int v_idx;
8100
8101 /* The requested uplink_seid must be either
8102 * - the PF's port seid
8103 * no VEB is needed because this is the PF
8104 * or this is a Flow Director special case VSI
8105 * - seid of an existing VEB
8106 * - seid of a VSI that owns an existing VEB
8107 * - seid of a VSI that doesn't own a VEB
8108 * a new VEB is created and the VSI becomes the owner
8109 * - seid of the PF VSI, which is what creates the first VEB
8110 * this is a special case of the previous
8111 *
8112 * Find which uplink_seid we were given and create a new VEB if needed
8113 */
8114 for (i = 0; i < I40E_MAX_VEB; i++) {
8115 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8116 veb = pf->veb[i];
8117 break;
8118 }
8119 }
8120
8121 if (!veb && uplink_seid != pf->mac_seid) {
8122
505682cd 8123 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8124 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8125 vsi = pf->vsi[i];
8126 break;
8127 }
8128 }
8129 if (!vsi) {
8130 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8131 uplink_seid);
8132 return NULL;
8133 }
8134
8135 if (vsi->uplink_seid == pf->mac_seid)
8136 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8137 vsi->tc_config.enabled_tc);
8138 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8139 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8140 vsi->tc_config.enabled_tc);
8141
8142 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8143 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8144 veb = pf->veb[i];
8145 }
8146 if (!veb) {
8147 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8148 return NULL;
8149 }
8150
8151 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8152 uplink_seid = veb->seid;
8153 }
8154
8155 /* get vsi sw struct */
8156 v_idx = i40e_vsi_mem_alloc(pf, type);
8157 if (v_idx < 0)
8158 goto err_alloc;
8159 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8160 if (!vsi)
8161 goto err_alloc;
41c445ff
JB		 8162 vsi->type = type;
8163 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8164
8165 if (type == I40E_VSI_MAIN)
8166 pf->lan_vsi = v_idx;
8167 else if (type == I40E_VSI_SRIOV)
8168 vsi->vf_id = param1;
8169 /* assign it some queues */
cbf61325
ASJ		 8170 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8171 vsi->idx);
41c445ff 8172 if (ret < 0) {
049a2be8
SN		 8173 dev_info(&pf->pdev->dev,
8174 "failed to get tracking for %d queues for VSI %d err=%d\n",
8175 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 8176 goto err_vsi;
8177 }
8178 vsi->base_queue = ret;
8179
8180 /* get a VSI from the hardware */
8181 vsi->uplink_seid = uplink_seid;
8182 ret = i40e_add_vsi(vsi);
8183 if (ret)
8184 goto err_vsi;
8185
8186 switch (vsi->type) {
8187 /* setup the netdev if needed */
8188 case I40E_VSI_MAIN:
8189 case I40E_VSI_VMDQ2:
38e00438 8190 case I40E_VSI_FCOE:
41c445ff
JB		 8191 ret = i40e_config_netdev(vsi);
8192 if (ret)
8193 goto err_netdev;
8194 ret = register_netdev(vsi->netdev);
8195 if (ret)
8196 goto err_netdev;
8197 vsi->netdev_registered = true;
8198 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8199#ifdef CONFIG_I40E_DCB
8200 /* Setup DCB netlink interface */
8201 i40e_dcbnl_setup(vsi);
8202#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8203 /* fall through */
8204
8205 case I40E_VSI_FDIR:
8206 /* set up vectors and rings if needed */
8207 ret = i40e_vsi_setup_vectors(vsi);
8208 if (ret)
8209 goto err_msix;
8210
8211 ret = i40e_alloc_rings(vsi);
8212 if (ret)
8213 goto err_rings;
8214
8215 /* map all of the rings to the q_vectors */
8216 i40e_vsi_map_rings_to_vectors(vsi);
8217
8218 i40e_vsi_reset_stats(vsi);
8219 break;
8220
8221 default:
8222 /* no netdev or rings for the other VSI types */
8223 break;
8224 }
8225
8226 return vsi;
8227
8228err_rings:
8229 i40e_vsi_free_q_vectors(vsi);
8230err_msix:
8231 if (vsi->netdev_registered) {
8232 vsi->netdev_registered = false;
8233 unregister_netdev(vsi->netdev);
8234 free_netdev(vsi->netdev);
8235 vsi->netdev = NULL;
8236 }
8237err_netdev:
8238 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8239err_vsi:
8240 i40e_vsi_clear(vsi);
8241err_alloc:
8242 return NULL;
8243}
8244
8245/**
8246 * i40e_veb_get_bw_info - Query VEB BW information
8247 * @veb: the veb to query
8248 *
8249 * Query the Tx scheduler BW configuration data for given VEB
8250 **/
8251static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8252{
8253 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8254 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8255 struct i40e_pf *pf = veb->pf;
8256 struct i40e_hw *hw = &pf->hw;
8257 u32 tc_bw_max;
8258 int ret = 0;
8259 int i;
8260
8261 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8262 &bw_data, NULL);
8263 if (ret) {
8264 dev_info(&pf->pdev->dev,
8265 "query veb bw config failed, aq_err=%d\n",
8266 hw->aq.asq_last_status);
8267 goto out;
8268 }
8269
8270 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8271 &ets_data, NULL);
8272 if (ret) {
8273 dev_info(&pf->pdev->dev,
8274 "query veb bw ets config failed, aq_err=%d\n",
8275 hw->aq.asq_last_status);
8276 goto out;
8277 }
8278
8279 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8280 veb->bw_max_quanta = ets_data.tc_bw_max;
8281 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 8282 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 8283 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8284 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8285 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8286 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8287 veb->bw_tc_limit_credits[i] =
8288 le16_to_cpu(bw_data.tc_bw_limits[i]);
8289 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8290 }
8291
8292out:
8293 return ret;
8294}
8295
8296/**
8297 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8298 * @pf: board private structure
8299 *
8300 * On error: returns error code (negative)
8301 * On success: returns vsi index in PF (positive)
8302 **/
8303static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8304{
8305 int ret = -ENOENT;
8306 struct i40e_veb *veb;
8307 int i;
8308
8309 /* Need to protect the allocation of switch elements at the PF level */
8310 mutex_lock(&pf->switch_mutex);
8311
8312 /* VEB list may be fragmented if VEB creation/destruction has
8313 * been happening. We can afford to do a quick scan to look
8314 * for any free slots in the list.
8315 *
8316 * find next empty veb slot, looping back around if necessary
8317 */
8318 i = 0;
8319 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8320 i++;
8321 if (i >= I40E_MAX_VEB) {
8322 ret = -ENOMEM;
8323 goto err_alloc_veb; /* out of VEB slots! */
8324 }
8325
8326 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8327 if (!veb) {
8328 ret = -ENOMEM;
8329 goto err_alloc_veb;
8330 }
8331 veb->pf = pf;
8332 veb->idx = i;
8333 veb->enabled_tc = 1;
8334
8335 pf->veb[i] = veb;
8336 ret = i;
8337err_alloc_veb:
8338 mutex_unlock(&pf->switch_mutex);
8339 return ret;
8340}
8341
8342/**
8343 * i40e_switch_branch_release - Delete a branch of the switch tree
8344 * @branch: where to start deleting
8345 *
8346 * This uses recursion to find the tips of the branch to be
8347 * removed, deleting until we get back to and can delete this VEB.
8348 **/
8349static void i40e_switch_branch_release(struct i40e_veb *branch)
8350{
8351 struct i40e_pf *pf = branch->pf;
8352 u16 branch_seid = branch->seid;
8353 u16 veb_idx = branch->idx;
8354 int i;
8355
8356 /* release any VEBs on this VEB - RECURSION */
8357 for (i = 0; i < I40E_MAX_VEB; i++) {
8358 if (!pf->veb[i])
8359 continue;
8360 if (pf->veb[i]->uplink_seid == branch->seid)
8361 i40e_switch_branch_release(pf->veb[i]);
8362 }
8363
8364 /* Release the VSIs on this VEB, but not the owner VSI.
8365 *
8366 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8367 * the VEB itself, so don't use (*branch) after this loop.
8368 */
505682cd 8369 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8370 if (!pf->vsi[i])
8371 continue;
8372 if (pf->vsi[i]->uplink_seid == branch_seid &&
8373 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8374 i40e_vsi_release(pf->vsi[i]);
8375 }
8376 }
8377
8378 /* There's one corner case where the VEB might not have been
8379 * removed, so double check it here and remove it if needed.
8380 * This case happens if the veb was created from the debugfs
8381 * commands and no VSIs were added to it.
8382 */
8383 if (pf->veb[veb_idx])
8384 i40e_veb_release(pf->veb[veb_idx]);
8385}
8386
8387/**
8388 * i40e_veb_clear - remove veb struct
8389 * @veb: the veb to remove
8390 **/
8391static void i40e_veb_clear(struct i40e_veb *veb)
8392{
8393 if (!veb)
8394 return;
8395
8396 if (veb->pf) {
8397 struct i40e_pf *pf = veb->pf;
8398
8399 mutex_lock(&pf->switch_mutex);
8400 if (pf->veb[veb->idx] == veb)
8401 pf->veb[veb->idx] = NULL;
8402 mutex_unlock(&pf->switch_mutex);
8403 }
8404
8405 kfree(veb);
8406}
8407
8408/**
8409 * i40e_veb_release - Delete a VEB and free its resources
8410 * @veb: the VEB being removed
8411 **/
8412void i40e_veb_release(struct i40e_veb *veb)
8413{
8414 struct i40e_vsi *vsi = NULL;
8415 struct i40e_pf *pf;
8416 int i, n = 0;
8417
8418 pf = veb->pf;
8419
8420 /* find the remaining VSI and check for extras */
505682cd 8421 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8422 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
8423 n++;
8424 vsi = pf->vsi[i];
8425 }
8426 }
8427 if (n != 1) {
8428 dev_info(&pf->pdev->dev,
8429 "can't remove VEB %d with %d VSIs left\n",
8430 veb->seid, n);
8431 return;
8432 }
8433
8434 /* move the remaining VSI to uplink veb */
8435 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
8436 if (veb->uplink_seid) {
8437 vsi->uplink_seid = veb->uplink_seid;
8438 if (veb->uplink_seid == pf->mac_seid)
8439 vsi->veb_idx = I40E_NO_VEB;
8440 else
8441 vsi->veb_idx = veb->veb_idx;
8442 } else {
8443 /* floating VEB */
8444 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8445 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
8446 }
8447
8448 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
8449 i40e_veb_clear(veb);
41c445ff
JB		 8450}
8451
8452/**
8453 * i40e_add_veb - create the VEB in the switch
8454 * @veb: the VEB to be instantiated
8455 * @vsi: the controlling VSI
8456 **/
8457static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
8458{
56747264 8459 bool is_default = false;
e1c51b95 8460 bool is_cloud = false;
41c445ff
JB		 8461 int ret;
8462
8463 /* get a VEB from the hardware */
8464 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 8465 veb->enabled_tc, is_default,
8466 is_cloud, &veb->seid, NULL);
41c445ff
JB		 8467 if (ret) {
8468 dev_info(&veb->pf->pdev->dev,
8469 "couldn't add VEB, err %d, aq_err %d\n",
8470 ret, veb->pf->hw.aq.asq_last_status);
8471 return -EPERM;
8472 }
8473
8474 /* get statistics counter */
8475 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
8476 &veb->stats_idx, NULL, NULL, NULL);
8477 if (ret) {
8478 dev_info(&veb->pf->pdev->dev,
8479 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
8480 ret, veb->pf->hw.aq.asq_last_status);
8481 return -EPERM;
8482 }
8483 ret = i40e_veb_get_bw_info(veb);
8484 if (ret) {
8485 dev_info(&veb->pf->pdev->dev,
8486 "couldn't get VEB bw info, err %d, aq_err %d\n",
8487 ret, veb->pf->hw.aq.asq_last_status);
8488 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8489 return -ENOENT;
8490 }
8491
8492 vsi->uplink_seid = veb->seid;
8493 vsi->veb_idx = veb->idx;
8494 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8495
8496 return 0;
8497}
8498
8499/**
8500 * i40e_veb_setup - Set up a VEB
8501 * @pf: board private structure
8502 * @flags: VEB setup flags
8503 * @uplink_seid: the switch element to link to
8504 * @vsi_seid: the initial VSI seid
8505 * @enabled_tc: Enabled TC bit-map
8506 *
8507 * This allocates the sw VEB structure and links it into the switch
8508 * It is possible and legal for this to be a duplicate of an already
8509 * existing VEB. It is also possible for both uplink and vsi seids
8510 * to be zero, in order to create a floating VEB.
8511 *
8512 * Returns pointer to the successfully allocated VEB sw struct on
8513 * success, otherwise returns NULL on failure.
8514 **/
8515struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8516 u16 uplink_seid, u16 vsi_seid,
8517 u8 enabled_tc)
8518{
8519 struct i40e_veb *veb, *uplink_veb = NULL;
8520 int vsi_idx, veb_idx;
8521 int ret;
8522
8523 /* if one seid is 0, the other must be 0 to create a floating relay */
8524 if ((uplink_seid == 0 || vsi_seid == 0) &&
8525 (uplink_seid + vsi_seid != 0)) {
8526 dev_info(&pf->pdev->dev,
8527 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8528 uplink_seid, vsi_seid);
8529 return NULL;
8530 }
8531
8532 /* make sure there is such a vsi and uplink */
505682cd 8533 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8534 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8535 break;
505682cd 8536 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8537 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8538 vsi_seid);
8539 return NULL;
8540 }
8541
8542 if (uplink_seid && uplink_seid != pf->mac_seid) {
8543 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8544 if (pf->veb[veb_idx] &&
8545 pf->veb[veb_idx]->seid == uplink_seid) {
8546 uplink_veb = pf->veb[veb_idx];
8547 break;
8548 }
8549 }
8550 if (!uplink_veb) {
8551 dev_info(&pf->pdev->dev,
8552 "uplink seid %d not found\n", uplink_seid);
8553 return NULL;
8554 }
8555 }
8556
8557 /* get veb sw struct */
8558 veb_idx = i40e_veb_mem_alloc(pf);
8559 if (veb_idx < 0)
8560 goto err_alloc;
8561 veb = pf->veb[veb_idx];
8562 veb->flags = flags;
8563 veb->uplink_seid = uplink_seid;
8564 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8565 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8566
8567 /* create the VEB in the switch */
8568 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8569 if (ret)
8570 goto err_veb;
1bb8b935
SN		 8571 if (vsi_idx == pf->lan_vsi)
8572 pf->lan_veb = veb->idx;
41c445ff
JB		 8573
8574 return veb;
8575
8576err_veb:
8577 i40e_veb_clear(veb);
8578err_alloc:
8579 return NULL;
8580}
8581
8582/**
8583 * i40e_setup_pf_switch_element - set pf vars based on switch type
8584 * @pf: board private structure
8585 * @ele: element we are building info from
8586 * @num_reported: total number of elements
8587 * @printconfig: should we print the contents
8588 *
8589 * helper function to assist in extracting a few useful SEID values.
8590 **/
8591static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
8592 struct i40e_aqc_switch_config_element_resp *ele,
8593 u16 num_reported, bool printconfig)
8594{
8595 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
8596 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
8597 u8 element_type = ele->element_type;
8598 u16 seid = le16_to_cpu(ele->seid);
8599
8600 if (printconfig)
8601 dev_info(&pf->pdev->dev,
8602 "type=%d seid=%d uplink=%d downlink=%d\n",
8603 element_type, seid, uplink_seid, downlink_seid);
8604
8605 switch (element_type) {
8606 case I40E_SWITCH_ELEMENT_TYPE_MAC:
8607 pf->mac_seid = seid;
8608 break;
8609 case I40E_SWITCH_ELEMENT_TYPE_VEB:
8610 /* Main VEB? */
8611 if (uplink_seid != pf->mac_seid)
8612 break;
8613 if (pf->lan_veb == I40E_NO_VEB) {
8614 int v;
8615
8616 /* find existing or else empty VEB */
8617 for (v = 0; v < I40E_MAX_VEB; v++) {
8618 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
8619 pf->lan_veb = v;
8620 break;
8621 }
8622 }
8623 if (pf->lan_veb == I40E_NO_VEB) {
8624 v = i40e_veb_mem_alloc(pf);
8625 if (v < 0)
8626 break;
8627 pf->lan_veb = v;
8628 }
8629 }
8630
8631 pf->veb[pf->lan_veb]->seid = seid;
8632 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
8633 pf->veb[pf->lan_veb]->pf = pf;
8634 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
8635 break;
8636 case I40E_SWITCH_ELEMENT_TYPE_VSI:
8637 if (num_reported != 1)
8638 break;
8639 /* This is immediately after a reset so we can assume this is
8640 * the PF's VSI
8641 */
8642 pf->mac_seid = uplink_seid;
8643 pf->pf_seid = downlink_seid;
8644 pf->main_vsi_seid = seid;
8645 if (printconfig)
8646 dev_info(&pf->pdev->dev,
8647 "pf_seid=%d main_vsi_seid=%d\n",
8648 pf->pf_seid, pf->main_vsi_seid);
8649 break;
8650 case I40E_SWITCH_ELEMENT_TYPE_PF:
8651 case I40E_SWITCH_ELEMENT_TYPE_VF:
8652 case I40E_SWITCH_ELEMENT_TYPE_EMP:
8653 case I40E_SWITCH_ELEMENT_TYPE_BMC:
8654 case I40E_SWITCH_ELEMENT_TYPE_PE:
8655 case I40E_SWITCH_ELEMENT_TYPE_PA:
8656 /* ignore these for now */
8657 break;
8658 default:
8659 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
8660 element_type, seid);
8661 break;
8662 }
8663}
8664
8665/**
8666 * i40e_fetch_switch_configuration - Get switch config from firmware
8667 * @pf: board private structure
8668 * @printconfig: should we print the contents
8669 *
8670 * Get the current switch configuration from the device and
8671 * extract a few useful SEID values.
8672 **/
8673int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
8674{
8675 struct i40e_aqc_get_switch_config_resp *sw_config;
8676 u16 next_seid = 0;
8677 int ret = 0;
8678 u8 *aq_buf;
8679 int i;
8680
8681 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
8682 if (!aq_buf)
8683 return -ENOMEM;
8684
8685 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
8686 do {
8687 u16 num_reported, num_total;
8688
8689 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
8690 I40E_AQ_LARGE_BUF,
8691 &next_seid, NULL);
8692 if (ret) {
8693 dev_info(&pf->pdev->dev,
8694 "get switch config failed %d aq_err=%x\n",
8695 ret, pf->hw.aq.asq_last_status);
8696 kfree(aq_buf);
8697 return -ENOENT;
8698 }
8699
8700 num_reported = le16_to_cpu(sw_config->header.num_reported);
8701 num_total = le16_to_cpu(sw_config->header.num_total);
8702
8703 if (printconfig)
8704 dev_info(&pf->pdev->dev,
8705 "header: %d reported %d total\n",
8706 num_reported, num_total);
8707
41c445ff
JB		 8708 for (i = 0; i < num_reported; i++) {
8709 struct i40e_aqc_switch_config_element_resp *ele =
8710 &sw_config->element[i];
8711
8712 i40e_setup_pf_switch_element(pf, ele, num_reported,
8713 printconfig);
8714 }
8715 } while (next_seid != 0);
8716
8717 kfree(aq_buf);
8718 return ret;
8719}
8720
8721/**
8722 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8723 * @pf: board private structure
bc7d338f 8724 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8725 *
8726 * Returns 0 on success, negative value on failure
8727 **/
bc7d338f 8728static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 8729{
8730 int ret;
8731
8732 /* find out what's out there already */
8733 ret = i40e_fetch_switch_configuration(pf, false);
8734 if (ret) {
8735 dev_info(&pf->pdev->dev,
8736 "couldn't fetch switch config, err %d, aq_err %d\n",
8737 ret, pf->hw.aq.asq_last_status);
8738 return ret;
8739 }
8740 i40e_pf_reset_stats(pf);
8741
41c445ff 8742 /* first time setup */
bc7d338f 8743 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8744 struct i40e_vsi *vsi = NULL;
8745 u16 uplink_seid;
8746
8747 /* Set up the PF VSI associated with the PF's main VSI
8748 * that is already in the HW switch
8749 */
8750 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8751 uplink_seid = pf->veb[pf->lan_veb]->seid;
8752 else
8753 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8754 if (pf->lan_vsi == I40E_NO_VSI)
8755 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8756 else if (reinit)
8757 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8758 if (!vsi) {
8759 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8760 i40e_fdir_teardown(pf);
8761 return -EAGAIN;
8762 }
41c445ff
JB		 8763 } else {
8764 /* force a reset of TC and queue layout configurations */
8765 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8766 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8767 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8768 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8769 }
8770 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8771
cbf61325
ASJ		 8772 i40e_fdir_sb_setup(pf);
8773
41c445ff
JB		 8774 /* Setup static PF queue filter control settings */
8775 ret = i40e_setup_pf_filter_control(pf);
8776 if (ret) {
8777 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8778 ret);
8779 /* Failure here should not stop continuing other steps */
8780 }
8781
8782 /* enable RSS in the HW, even for only one queue, as the stack can use
8783 * the hash
8784 */
8785 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8786 i40e_config_rss(pf);
8787
8788 /* fill in link information and enable LSE reporting */
a34a6711
MW		 8789 i40e_update_link_info(&pf->hw, true);
8790 i40e_link_event(pf);
8791
8792 /* Initialize user-specific link properties */
8793 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8794 I40E_AQ_AN_COMPLETED) ? true : false);
8795
8796 /* fill in link information and enable LSE reporting */
8109e123 8797 i40e_update_link_info(&pf->hw, true);
41c445ff
JB		 8798 i40e_link_event(pf);
8799
d52c20b7 8800 /* Initialize user-specific link properties */
41c445ff
JB		 8801 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8802 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 8803
beb0dff1
JK		 8804 i40e_ptp_init(pf);
8805
41c445ff
JB		 8806 return ret;
8807}
8808
41c445ff
JB		 8809/**
8810 * i40e_determine_queue_usage - Work out queue distribution
8811 * @pf: board private structure
8812 **/
8813static void i40e_determine_queue_usage(struct i40e_pf *pf)
8814{
41c445ff
JB		 8815 int queues_left;
8816
8817 pf->num_lan_qps = 0;
38e00438
VD		 8818#ifdef I40E_FCOE
8819 pf->num_fcoe_qps = 0;
8820#endif
41c445ff
JB		 8821
8822 /* Find the max queues to be put into basic use. We'll always be
8823 * using TC0, whether or not DCB is running, and TC0 will get the
8824 * big RSS set.
8825 */
8826 queues_left = pf->hw.func_caps.num_tx_qp;
8827
cbf61325 8828 if ((queues_left == 1) ||
9aa7e935 8829 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 8830 /* one qp for PF, no queues for anything else */
8831 queues_left = 0;
8832 pf->rss_size = pf->num_lan_qps = 1;
8833
8834 /* make sure all the fancies are disabled */
60ea5f83 8835 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8836#ifdef I40E_FCOE
8837 I40E_FLAG_FCOE_ENABLED |
8838#endif
60ea5f83
JB		 8839 I40E_FLAG_FD_SB_ENABLED |
8840 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8841 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 8842 I40E_FLAG_SRIOV_ENABLED |
8843 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 8844 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
8845 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 8846 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8847 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 8848 /* one qp for PF */
8849 pf->rss_size = pf->num_lan_qps = 1;
8850 queues_left -= pf->num_lan_qps;
8851
8852 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8853#ifdef I40E_FCOE
8854 I40E_FLAG_FCOE_ENABLED |
8855#endif
9aa7e935
FZ		 8856 I40E_FLAG_FD_SB_ENABLED |
8857 I40E_FLAG_FD_ATR_ENABLED |
8858 I40E_FLAG_DCB_ENABLED |
8859 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8860 } else {
cbf61325 8861 /* Not enough queues for all TCs */
4d9b6043 8862 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 8863 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 8864 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 8865 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8866 }
8867 pf->num_lan_qps = pf->rss_size_max;
8868 queues_left -= pf->num_lan_qps;
8869 }
8870
38e00438
VD		 8871#ifdef I40E_FCOE
8872 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
8873 if (I40E_DEFAULT_FCOE <= queues_left) {
8874 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
8875 } else if (I40E_MINIMUM_FCOE <= queues_left) {
8876 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
8877 } else {
8878 pf->num_fcoe_qps = 0;
8879 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
8880 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
8881 }
8882
8883 queues_left -= pf->num_fcoe_qps;
8884 }
8885
8886#endif
cbf61325
ASJ		 8887 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8888 if (queues_left > 1) {
8889 queues_left -= 1; /* save 1 queue for FD */
8890 } else {
8891 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8892 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8893 }
41c445ff
JB		 8894 }
8895
8896 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8897 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8898 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8899 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8900 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8901 }
8902
8903 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8904 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8905 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8906 (queues_left / pf->num_vmdq_qps));
8907 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8908 }
8909
f8ff1464 8910 pf->queues_left = queues_left;
38e00438
VD		 8911#ifdef I40E_FCOE
8912 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
8913#endif
41c445ff
JB		 8914}
8915
8916/**
8917 * i40e_setup_pf_filter_control - Setup PF static filter control
8918 * @pf: PF to be setup
8919 *
8920 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8921 * settings. If PE/FCoE are enabled then it will also set the per PF
8922 * based filter sizes required for them. It also enables Flow director,
8923 * ethertype and macvlan type filter settings for the pf.
8924 *
8925 * Returns 0 on success, negative on failure
8926 **/
8927static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8928{
8929 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8930
8931 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8932
8933 /* Flow Director is enabled */
60ea5f83 8934 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8935 settings->enable_fdir = true;
8936
8937 /* Ethtype and MACVLAN filters enabled for PF */
8938 settings->enable_ethtype = true;
8939 settings->enable_macvlan = true;
8940
8941 if (i40e_set_filter_control(&pf->hw, settings))
8942 return -ENOENT;
8943
8944 return 0;
8945}
8946
0c22b3dd
JB		 8947#define INFO_STRING_LEN 255
8948static void i40e_print_features(struct i40e_pf *pf)
8949{
8950 struct i40e_hw *hw = &pf->hw;
8951 char *buf, *string;
8952
8953 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8954 if (!string) {
8955 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8956 return;
8957 }
8958
8959 buf = string;
8960
8961 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8962#ifdef CONFIG_PCI_IOV
8963 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8964#endif
8965 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8966 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8967
8968 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8969 buf += sprintf(buf, "RSS ");
0c22b3dd 8970 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 8971 buf += sprintf(buf, "FD_ATR ");
8972 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8973 buf += sprintf(buf, "FD_SB ");
0c22b3dd 8974 buf += sprintf(buf, "NTUPLE ");
c6423ff1 8975 }
4d9b6043 8976 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 8977 buf += sprintf(buf, "DCB ");
8978 if (pf->flags & I40E_FLAG_PTP)
8979 buf += sprintf(buf, "PTP ");
38e00438
VD		 8980#ifdef I40E_FCOE
8981 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
8982 buf += sprintf(buf, "FCOE ");
8983#endif
0c22b3dd
JB		 8984
8985 BUG_ON(buf > (string + INFO_STRING_LEN));
8986 dev_info(&pf->pdev->dev, "%s\n", string);
8987 kfree(string);
8988}
8989
41c445ff
JB		 8990/**
8991 * i40e_probe - Device initialization routine
8992 * @pdev: PCI device information struct
8993 * @ent: entry in i40e_pci_tbl
8994 *
8995 * i40e_probe initializes a pf identified by a pci_dev structure.
8996 * The OS initialization, configuring of the pf private structure,
8997 * and a hardware reset occur.
8998 *
8999 * Returns 0 on success, negative on failure
9000 **/
9001static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9002{
41c445ff
JB		 9003 struct i40e_pf *pf;
9004 struct i40e_hw *hw;
93cd765b 9005 static u16 pfs_found;
d4dfb81a 9006 u16 link_status;
41c445ff
JB		 9007 int err = 0;
9008 u32 len;
8a9eb7d3 9009 u32 i;
41c445ff
JB		 9010
9011 err = pci_enable_device_mem(pdev);
9012 if (err)
9013 return err;
9014
9015 /* set up for high or low dma */
6494294f 9016 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9017 if (err) {
e3e3bfdd
JS		 9018 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9019 if (err) {
9020 dev_err(&pdev->dev,
9021 "DMA configuration failed: 0x%x\n", err);
9022 goto err_dma;
9023 }
41c445ff
JB		 9024 }
9025
9026 /* set up pci connections */
9027 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9028 IORESOURCE_MEM), i40e_driver_name);
9029 if (err) {
9030 dev_info(&pdev->dev,
9031 "pci_request_selected_regions failed %d\n", err);
9032 goto err_pci_reg;
9033 }
9034
9035 pci_enable_pcie_error_reporting(pdev);
9036 pci_set_master(pdev);
9037
9038 /* Now that we have a PCI connection, we need to do the
9039 * low level device setup. This is primarily setting up
9040 * the Admin Queue structures and then querying for the
9041 * device's current profile information.
9042 */
9043 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9044 if (!pf) {
9045 err = -ENOMEM;
9046 goto err_pf_alloc;
9047 }
9048 pf->next_vsi = 0;
9049 pf->pdev = pdev;
9050 set_bit(__I40E_DOWN, &pf->state);
9051
9052 hw = &pf->hw;
9053 hw->back = pf;
9054 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
9055 pci_resource_len(pdev, 0));
9056 if (!hw->hw_addr) {
9057 err = -EIO;
9058 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
9059 (unsigned int)pci_resource_start(pdev, 0),
9060 (unsigned int)pci_resource_len(pdev, 0), err);
9061 goto err_ioremap;
9062 }
9063 hw->vendor_id = pdev->vendor;
9064 hw->device_id = pdev->device;
9065 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9066 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9067 hw->subsystem_device_id = pdev->subsystem_device;
9068 hw->bus.device = PCI_SLOT(pdev->devfn);
9069 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9070 pf->instance = pfs_found;
41c445ff 9071
5b5faa43
SN		 9072 if (debug != -1) {
9073 pf->msg_enable = pf->hw.debug_mask;
9074 pf->msg_enable = debug;
9075 }
9076
7134f9ce
JB		 9077 /* do a special CORER for clearing PXE mode once at init */
9078 if (hw->revision_id == 0 &&
9079 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9080 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9081 i40e_flush(hw);
9082 msleep(200);
9083 pf->corer_count++;
9084
9085 i40e_clear_pxe_mode(hw);
9086 }
9087
41c445ff 9088 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9089 i40e_clear_hw(hw);
41c445ff
JB		 9090 err = i40e_pf_reset(hw);
9091 if (err) {
9092 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9093 goto err_pf_reset;
9094 }
9095 pf->pfr_count++;
9096
9097 hw->aq.num_arq_entries = I40E_AQ_LEN;
9098 hw->aq.num_asq_entries = I40E_AQ_LEN;
9099 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9100 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9101 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
9102 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
9103 "%s-pf%d:misc",
9104 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
9105
9106 err = i40e_init_shared_code(hw);
9107 if (err) {
9108 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
9109 goto err_pf_reset;
9110 }
9111
d52c20b7
JB		 9112 /* set up a default setting for link flow control */
9113 pf->hw.fc.requested_mode = I40E_FC_NONE;
9114
41c445ff
JB		 9115 err = i40e_init_adminq(hw);
9116 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9117 if (err) {
9118 dev_info(&pdev->dev,
7aa67613 9119 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9120 goto err_pf_reset;
9121 }
9122
7aa67613
CS		 9123 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9124 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9125 dev_info(&pdev->dev,
7aa67613
CS		 9126 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9127 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9128 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9129 dev_info(&pdev->dev,
7aa67613 9130 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62
SN		 9131
9132
4eb3f768
SN		 9133 i40e_verify_eeprom(pf);
9134
2c5fe33b
JB		 9135 /* Rev 0 hardware was never productized */
9136 if (hw->revision_id < 1)
9137 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9138
6ff4ef86 9139 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9140 err = i40e_get_capabilities(pf);
9141 if (err)
9142 goto err_adminq_setup;
9143
9144 err = i40e_sw_init(pf);
9145 if (err) {
9146 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9147 goto err_sw_init;
9148 }
9149
9150 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9151 hw->func_caps.num_rx_qp,
9152 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9153 if (err) {
9154 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9155 goto err_init_lan_hmc;
9156 }
9157
9158 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9159 if (err) {
9160 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9161 err = -ENOENT;
9162 goto err_configure_lan_hmc;
9163 }
9164
9165 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9166 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9167 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9168 err = -EIO;
9169 goto err_mac_addr;
9170 }
9171 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9172 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9173 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9174 if (is_valid_ether_addr(hw->mac.port_addr))
9175 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9176#ifdef I40E_FCOE
9177 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9178 if (err)
9179 dev_info(&pdev->dev,
9180 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9181 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9182 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9183 hw->mac.san_addr);
9184 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9185 }
9186 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9187#endif /* I40E_FCOE */
41c445ff
JB		 9188
9189 pci_set_drvdata(pdev, pf);
9190 pci_save_state(pdev);
4e3b35b0
NP		 9191#ifdef CONFIG_I40E_DCB
9192 err = i40e_init_pf_dcb(pf);
9193 if (err) {
9194 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
4d9b6043 9195 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9196 /* Continue without DCB enabled */
4e3b35b0
NP		 9197 }
9198#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9199
9200 /* set up periodic task facility */
9201 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9202 pf->service_timer_period = HZ;
9203
9204 INIT_WORK(&pf->service_task, i40e_service_task);
9205 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9206 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9207 pf->link_check_timeout = jiffies;
9208
8e2773ae
SN		 9209 /* WoL defaults to disabled */
9210 pf->wol_en = false;
9211 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9212
41c445ff
JB		 9213 /* set up the main switch operations */
9214 i40e_determine_queue_usage(pf);
9215 i40e_init_interrupt_scheme(pf);
9216
505682cd
MW		 9217 /* The number of VSIs reported by the FW is the minimum guaranteed
9218 * to us; HW supports far more and we share the remaining pool with
9219 * the other PFs. We allocate space for more than the guarantee with
9220 * the understanding that we might not get them all later.
41c445ff 9221 */
505682cd
MW		 9222 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9223 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9224 else
9225 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9226
9227 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9228 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9229 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9230 if (!pf->vsi) {
9231 err = -ENOMEM;
41c445ff 9232 goto err_switch_setup;
ed87ac09 9233 }
41c445ff 9234
bc7d338f 9235 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9236 if (err) {
9237 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9238 goto err_vsis;
9239 }
8a9eb7d3 9240 /* if FDIR VSI was set up, start it now */
505682cd 9241 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9242 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9243 i40e_vsi_open(pf->vsi[i]);
9244 break;
9245 }
9246 }
41c445ff 9247
7e2453fe
JB		 9248 /* driver is only interested in link up/down and module qualification
9249 * reports from firmware
9250 */
9251 err = i40e_aq_set_phy_int_mask(&pf->hw,
9252 I40E_AQ_EVENT_LINK_UPDOWN |
9253 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
9254 if (err)
9255 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", err);
9256
cafa2ee6
ASJ		 9257 msleep(75);
9258 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9259 if (err) {
9260 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
9261 pf->hw.aq.asq_last_status);
9262 }
9263
41c445ff
JB		 9264 /* The main driver is (mostly) up and happy. We need to set this state
9265 * before setting up the misc vector or we get a race and the vector
9266 * ends up disabled forever.
9267 */
9268 clear_bit(__I40E_DOWN, &pf->state);
9269
9270 /* In case of MSIX we are going to setup the misc vector right here
9271 * to handle admin queue events etc. In case of legacy and MSI
9272 * the misc functionality and queue processing is combined in
9273 * the same vector and that gets setup at open.
9274 */
9275 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9276 err = i40e_setup_misc_vector(pf);
9277 if (err) {
9278 dev_info(&pdev->dev,
9279 "setup of misc vector failed: %d\n", err);
9280 goto err_vsis;
9281 }
9282 }
9283
df805f62 9284#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9285 /* prep for VF support */
9286 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9287 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9288 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9289 u32 val;
9290
9291 /* disable link interrupts for VFs */
9292 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9293 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9294 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9295 i40e_flush(hw);
4aeec010
MW		 9296
9297 if (pci_num_vf(pdev)) {
9298 dev_info(&pdev->dev,
9299 "Active VFs found, allocating resources.\n");
9300 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9301 if (err)
9302 dev_info(&pdev->dev,
9303 "Error %d allocating resources for existing VFs\n",
9304 err);
9305 }
41c445ff 9306 }
df805f62 9307#endif /* CONFIG_PCI_IOV */
41c445ff 9308
93cd765b
ASJ		 9309 pfs_found++;
9310
41c445ff
JB		 9311 i40e_dbg_pf_init(pf);
9312
9313 /* tell the firmware that we're starting */
44033fac 9314 i40e_send_version(pf);
41c445ff
JB		 9315
9316 /* since everything's happy, start the service_task timer */
9317 mod_timer(&pf->service_timer,
9318 round_jiffies(jiffies + pf->service_timer_period));
9319
38e00438
VD		 9320#ifdef I40E_FCOE
9321 /* create FCoE interface */
9322 i40e_fcoe_vsi_setup(pf);
9323
9324#endif
d4dfb81a
CS		 9325 /* Get the negotiated link width and speed from PCI config space */
9326 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9327
9328 i40e_set_pci_config_data(hw, link_status);
9329
69bfb110 9330 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9331 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9332 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9333 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9334 "Unknown"),
9335 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9336 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9337 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9338 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9339 "Unknown"));
9340
9341 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9342 hw->bus.speed < i40e_bus_speed_8000) {
9343 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9344 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9345 }
9346
0c22b3dd
JB		 9347 /* print a string summarizing features */
9348 i40e_print_features(pf);
9349
41c445ff
JB		 9350 return 0;
9351
9352 /* Unwind what we've done if something failed in the setup */
9353err_vsis:
9354 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9355 i40e_clear_interrupt_scheme(pf);
9356 kfree(pf->vsi);
04b03013
SN		 9357err_switch_setup:
9358 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9359 del_timer_sync(&pf->service_timer);
9360err_mac_addr:
9361err_configure_lan_hmc:
9362 (void)i40e_shutdown_lan_hmc(hw);
9363err_init_lan_hmc:
9364 kfree(pf->qp_pile);
9365 kfree(pf->irq_pile);
9366err_sw_init:
9367err_adminq_setup:
9368 (void)i40e_shutdown_adminq(hw);
9369err_pf_reset:
9370 iounmap(hw->hw_addr);
9371err_ioremap:
9372 kfree(pf);
9373err_pf_alloc:
9374 pci_disable_pcie_error_reporting(pdev);
9375 pci_release_selected_regions(pdev,
9376 pci_select_bars(pdev, IORESOURCE_MEM));
9377err_pci_reg:
9378err_dma:
9379 pci_disable_device(pdev);
9380 return err;
9381}
9382
9383/**
9384 * i40e_remove - Device removal routine
9385 * @pdev: PCI device information struct
9386 *
9387 * i40e_remove is called by the PCI subsystem to alert the driver
9388 * that is should release a PCI device. This could be caused by a
9389 * Hot-Plug event, or because the driver is going to be removed from
9390 * memory.
9391 **/
9392static void i40e_remove(struct pci_dev *pdev)
9393{
9394 struct i40e_pf *pf = pci_get_drvdata(pdev);
9395 i40e_status ret_code;
41c445ff
JB		 9396 int i;
9397
9398 i40e_dbg_pf_exit(pf);
9399
beb0dff1
JK		 9400 i40e_ptp_stop(pf);
9401
41c445ff
JB		 9402 /* no more scheduling of any task */
9403 set_bit(__I40E_DOWN, &pf->state);
9404 del_timer_sync(&pf->service_timer);
9405 cancel_work_sync(&pf->service_task);
9406
eb2d80bc
MW		 9407 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
9408 i40e_free_vfs(pf);
9409 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
9410 }
9411
41c445ff
JB		 9412 i40e_fdir_teardown(pf);
9413
9414 /* If there is a switch structure or any orphans, remove them.
9415 * This will leave only the PF's VSI remaining.
9416 */
9417 for (i = 0; i < I40E_MAX_VEB; i++) {
9418 if (!pf->veb[i])
9419 continue;
9420
9421 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
9422 pf->veb[i]->uplink_seid == 0)
9423 i40e_switch_branch_release(pf->veb[i]);
9424 }
9425
9426 /* Now we can shutdown the PF's VSI, just before we kill
9427 * adminq and hmc.
9428 */
9429 if (pf->vsi[pf->lan_vsi])
9430 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
9431
9432 i40e_stop_misc_vector(pf);
9433 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9434 synchronize_irq(pf->msix_entries[0].vector);
9435 free_irq(pf->msix_entries[0].vector, pf);
9436 }
9437
9438 /* shutdown and destroy the HMC */
60442dea
SN		 9439 if (pf->hw.hmc.hmc_obj) {
9440 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
9441 if (ret_code)
9442 dev_warn(&pdev->dev,
9443 "Failed to destroy the HMC resources: %d\n",
9444 ret_code);
9445 }
41c445ff
JB		 9446
9447 /* shutdown the adminq */
41c445ff
JB		 9448 ret_code = i40e_shutdown_adminq(&pf->hw);
9449 if (ret_code)
9450 dev_warn(&pdev->dev,
9451 "Failed to destroy the Admin Queue resources: %d\n",
9452 ret_code);
9453
9454 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
9455 i40e_clear_interrupt_scheme(pf);
505682cd 9456 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9457 if (pf->vsi[i]) {
9458 i40e_vsi_clear_rings(pf->vsi[i]);
9459 i40e_vsi_clear(pf->vsi[i]);
9460 pf->vsi[i] = NULL;
9461 }
9462 }
9463
9464 for (i = 0; i < I40E_MAX_VEB; i++) {
9465 kfree(pf->veb[i]);
9466 pf->veb[i] = NULL;
9467 }
9468
9469 kfree(pf->qp_pile);
9470 kfree(pf->irq_pile);
41c445ff
JB		 9471 kfree(pf->vsi);
9472
41c445ff
JB		 9473 iounmap(pf->hw.hw_addr);
9474 kfree(pf);
9475 pci_release_selected_regions(pdev,
9476 pci_select_bars(pdev, IORESOURCE_MEM));
9477
9478 pci_disable_pcie_error_reporting(pdev);
9479 pci_disable_device(pdev);
9480}
9481
9482/**
9483 * i40e_pci_error_detected - warning that something funky happened in PCI land
9484 * @pdev: PCI device information struct
9485 *
9486 * Called to warn that something happened and the error handling steps
9487 * are in progress. Allows the driver to quiesce things, be ready for
9488 * remediation.
9489 **/
9490static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
9491 enum pci_channel_state error)
9492{
9493 struct i40e_pf *pf = pci_get_drvdata(pdev);
9494
9495 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
9496
9497 /* shutdown all operations */
9007bccd
SN		 9498 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
9499 rtnl_lock();
9500 i40e_prep_for_reset(pf);
9501 rtnl_unlock();
9502 }
41c445ff
JB		 9503
9504 /* Request a slot reset */
9505 return PCI_ERS_RESULT_NEED_RESET;
9506}
9507
9508/**
9509 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9510 * @pdev: PCI device information struct
9511 *
9512 * Called to find if the driver can work with the device now that
9513 * the pci slot has been reset. If a basic connection seems good
9514 * (registers are readable and have sane content) then return a
9515 * happy little PCI_ERS_RESULT_xxx.
9516 **/
9517static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9518{
9519 struct i40e_pf *pf = pci_get_drvdata(pdev);
9520 pci_ers_result_t result;
9521 int err;
9522 u32 reg;
9523
9524 dev_info(&pdev->dev, "%s\n", __func__);
9525 if (pci_enable_device_mem(pdev)) {
9526 dev_info(&pdev->dev,
9527 "Cannot re-enable PCI device after reset.\n");
9528 result = PCI_ERS_RESULT_DISCONNECT;
9529 } else {
9530 pci_set_master(pdev);
9531 pci_restore_state(pdev);
9532 pci_save_state(pdev);
9533 pci_wake_from_d3(pdev, false);
9534
9535 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9536 if (reg == 0)
9537 result = PCI_ERS_RESULT_RECOVERED;
9538 else
9539 result = PCI_ERS_RESULT_DISCONNECT;
9540 }
9541
9542 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9543 if (err) {
9544 dev_info(&pdev->dev,
9545 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9546 err);
9547 /* non-fatal, continue */
9548 }
9549
9550 return result;
9551}
9552
9553/**
9554 * i40e_pci_error_resume - restart operations after PCI error recovery
9555 * @pdev: PCI device information struct
9556 *
9557 * Called to allow the driver to bring things back up after PCI error
9558 * and/or reset recovery has finished.
9559 **/
9560static void i40e_pci_error_resume(struct pci_dev *pdev)
9561{
9562 struct i40e_pf *pf = pci_get_drvdata(pdev);
9563
9564 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 9565 if (test_bit(__I40E_SUSPENDED, &pf->state))
9566 return;
9567
9568 rtnl_lock();
41c445ff 9569 i40e_handle_reset_warning(pf);
9007bccd
SN		 9570 rtnl_lock();
9571}
9572
9573/**
9574 * i40e_shutdown - PCI callback for shutting down
9575 * @pdev: PCI device information struct
9576 **/
9577static void i40e_shutdown(struct pci_dev *pdev)
9578{
9579 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9580 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9581
9582 set_bit(__I40E_SUSPENDED, &pf->state);
9583 set_bit(__I40E_DOWN, &pf->state);
9584 rtnl_lock();
9585 i40e_prep_for_reset(pf);
9586 rtnl_unlock();
9587
8e2773ae
SN		 9588 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9589 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9590
9007bccd 9591 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 9592 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9593 pci_set_power_state(pdev, PCI_D3hot);
9594 }
9595}
9596
9597#ifdef CONFIG_PM
9598/**
9599 * i40e_suspend - PCI callback for moving to D3
9600 * @pdev: PCI device information struct
9601 **/
9602static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
9603{
9604 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9605 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9606
9607 set_bit(__I40E_SUSPENDED, &pf->state);
9608 set_bit(__I40E_DOWN, &pf->state);
9609 rtnl_lock();
9610 i40e_prep_for_reset(pf);
9611 rtnl_unlock();
9612
8e2773ae
SN		 9613 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9614 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9615
9616 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9617 pci_set_power_state(pdev, PCI_D3hot);
9618
9619 return 0;
41c445ff
JB		 9620}
9621
9007bccd
SN		 9622/**
9623 * i40e_resume - PCI callback for waking up from D3
9624 * @pdev: PCI device information struct
9625 **/
9626static int i40e_resume(struct pci_dev *pdev)
9627{
9628 struct i40e_pf *pf = pci_get_drvdata(pdev);
9629 u32 err;
9630
9631 pci_set_power_state(pdev, PCI_D0);
9632 pci_restore_state(pdev);
9633 /* pci_restore_state() clears dev->state_saves, so
9634 * call pci_save_state() again to restore it.
9635 */
9636 pci_save_state(pdev);
9637
9638 err = pci_enable_device_mem(pdev);
9639 if (err) {
9640 dev_err(&pdev->dev,
9641 "%s: Cannot enable PCI device from suspend\n",
9642 __func__);
9643 return err;
9644 }
9645 pci_set_master(pdev);
9646
9647 /* no wakeup events while running */
9648 pci_wake_from_d3(pdev, false);
9649
9650 /* handling the reset will rebuild the device state */
9651 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
9652 clear_bit(__I40E_DOWN, &pf->state);
9653 rtnl_lock();
9654 i40e_reset_and_rebuild(pf, false);
9655 rtnl_unlock();
9656 }
9657
9658 return 0;
9659}
9660
9661#endif
41c445ff
JB		 9662static const struct pci_error_handlers i40e_err_handler = {
9663 .error_detected = i40e_pci_error_detected,
9664 .slot_reset = i40e_pci_error_slot_reset,
9665 .resume = i40e_pci_error_resume,
9666};
9667
9668static struct pci_driver i40e_driver = {
9669 .name = i40e_driver_name,
9670 .id_table = i40e_pci_tbl,
9671 .probe = i40e_probe,
9672 .remove = i40e_remove,
9007bccd
SN		 9673#ifdef CONFIG_PM
9674 .suspend = i40e_suspend,
9675 .resume = i40e_resume,
9676#endif
9677 .shutdown = i40e_shutdown,
41c445ff
JB		 9678 .err_handler = &i40e_err_handler,
9679 .sriov_configure = i40e_pci_sriov_configure,
9680};
9681
9682/**
9683 * i40e_init_module - Driver registration routine
9684 *
9685 * i40e_init_module is the first routine called when the driver is
9686 * loaded. All it does is register with the PCI subsystem.
9687 **/
9688static int __init i40e_init_module(void)
9689{
9690 pr_info("%s: %s - version %s\n", i40e_driver_name,
9691 i40e_driver_string, i40e_driver_version_str);
9692 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
9693 i40e_dbg_init();
9694 return pci_register_driver(&i40e_driver);
9695}
9696module_init(i40e_init_module);
9697
9698/**
9699 * i40e_exit_module - Driver exit cleanup routine
9700 *
9701 * i40e_exit_module is called just before the driver is removed
9702 * from memory.
9703 **/
9704static void __exit i40e_exit_module(void)
9705{
9706 pci_unregister_driver(&i40e_driver);
9707 i40e_dbg_exit();
9708}
9709module_exit(i40e_exit_module);
Linux 6.x block layer and io_uring tree(s)