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i40e: ATR policy change to flush the table to clean stale ATR rules
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
e454d6bf 41#define DRV_VERSION_MINOR 4
4e776381 42#define DRV_VERSION_BUILD 21
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 77 /* required last entry */
78 {0, }
79};
80MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
81
82#define I40E_MAX_VF_COUNT 128
83static int debug = -1;
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
86
87MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
88MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/**
93 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
94 * @hw: pointer to the HW structure
95 * @mem: ptr to mem struct to fill out
96 * @size: size of memory requested
97 * @alignment: what to align the allocation to
98 **/
99int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
100 u64 size, u32 alignment)
101{
102 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
103
104 mem->size = ALIGN(size, alignment);
105 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
106 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 107 if (!mem->va)
108 return -ENOMEM;
41c445ff 109
93bc73b8 110 return 0;
41c445ff
JB		 111}
112
113/**
114 * i40e_free_dma_mem_d - OS specific memory free for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to free
117 **/
118int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
119{
120 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
121
122 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
123 mem->va = NULL;
124 mem->pa = 0;
125 mem->size = 0;
126
127 return 0;
128}
129
130/**
131 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to fill out
134 * @size: size of memory requested
135 **/
136int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
137 u32 size)
138{
139 mem->size = size;
140 mem->va = kzalloc(size, GFP_KERNEL);
141
93bc73b8
JB		 142 if (!mem->va)
143 return -ENOMEM;
41c445ff 144
93bc73b8 145 return 0;
41c445ff
JB		 146}
147
148/**
149 * i40e_free_virt_mem_d - OS specific memory free for shared code
150 * @hw: pointer to the HW structure
151 * @mem: ptr to mem struct to free
152 **/
153int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
154{
155 /* it's ok to kfree a NULL pointer */
156 kfree(mem->va);
157 mem->va = NULL;
158 mem->size = 0;
159
160 return 0;
161}
162
163/**
164 * i40e_get_lump - find a lump of free generic resource
165 * @pf: board private structure
166 * @pile: the pile of resource to search
167 * @needed: the number of items needed
168 * @id: an owner id to stick on the items assigned
169 *
170 * Returns the base item index of the lump, or negative for error
171 *
172 * The search_hint trick and lack of advanced fit-finding only work
173 * because we're highly likely to have all the same size lump requests.
174 * Linear search time and any fragmentation should be minimal.
175 **/
176static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
177 u16 needed, u16 id)
178{
179 int ret = -ENOMEM;
ddf434ac 180 int i, j;
41c445ff
JB		 181
182 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
183 dev_info(&pf->pdev->dev,
184 "param err: pile=%p needed=%d id=0x%04x\n",
185 pile, needed, id);
186 return -EINVAL;
187 }
188
189 /* start the linear search with an imperfect hint */
190 i = pile->search_hint;
ddf434ac 191 while (i < pile->num_entries) {
41c445ff
JB		 192 /* skip already allocated entries */
193 if (pile->list[i] & I40E_PILE_VALID_BIT) {
194 i++;
195 continue;
196 }
197
198 /* do we have enough in this lump? */
199 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
200 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
201 break;
202 }
203
204 if (j == needed) {
205 /* there was enough, so assign it to the requestor */
206 for (j = 0; j < needed; j++)
207 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
208 ret = i;
209 pile->search_hint = i + j;
ddf434ac 210 break;
41c445ff
JB		 211 } else {
212 /* not enough, so skip over it and continue looking */
213 i += j;
214 }
215 }
216
217 return ret;
218}
219
220/**
221 * i40e_put_lump - return a lump of generic resource
222 * @pile: the pile of resource to search
223 * @index: the base item index
224 * @id: the owner id of the items assigned
225 *
226 * Returns the count of items in the lump
227 **/
228static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
229{
230 int valid_id = (id | I40E_PILE_VALID_BIT);
231 int count = 0;
232 int i;
233
234 if (!pile || index >= pile->num_entries)
235 return -EINVAL;
236
237 for (i = index;
238 i < pile->num_entries && pile->list[i] == valid_id;
239 i++) {
240 pile->list[i] = 0;
241 count++;
242 }
243
244 if (count && index < pile->search_hint)
245 pile->search_hint = index;
246
247 return count;
248}
249
250/**
251 * i40e_service_event_schedule - Schedule the service task to wake up
252 * @pf: board private structure
253 *
254 * If not already scheduled, this puts the task into the work queue
255 **/
256static void i40e_service_event_schedule(struct i40e_pf *pf)
257{
258 if (!test_bit(__I40E_DOWN, &pf->state) &&
259 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
260 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
261 schedule_work(&pf->service_task);
262}
263
264/**
265 * i40e_tx_timeout - Respond to a Tx Hang
266 * @netdev: network interface device structure
267 *
268 * If any port has noticed a Tx timeout, it is likely that the whole
269 * device is munged, not just the one netdev port, so go for the full
270 * reset.
271 **/
38e00438
VD		 272#ifdef I40E_FCOE
273void i40e_tx_timeout(struct net_device *netdev)
274#else
41c445ff 275static void i40e_tx_timeout(struct net_device *netdev)
38e00438 276#endif
41c445ff
JB		 277{
278 struct i40e_netdev_priv *np = netdev_priv(netdev);
279 struct i40e_vsi *vsi = np->vsi;
280 struct i40e_pf *pf = vsi->back;
281
282 pf->tx_timeout_count++;
283
284 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 285 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 286 pf->tx_timeout_last_recovery = jiffies;
287 netdev_info(netdev, "tx_timeout recovery level %d\n",
288 pf->tx_timeout_recovery_level);
289
290 switch (pf->tx_timeout_recovery_level) {
291 case 0:
292 /* disable and re-enable queues for the VSI */
293 if (in_interrupt()) {
294 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
295 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
296 } else {
297 i40e_vsi_reinit_locked(vsi);
298 }
299 break;
300 case 1:
301 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
302 break;
303 case 2:
304 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
305 break;
306 case 3:
307 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
308 break;
309 default:
310 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 311 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
312 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 313 break;
314 }
315 i40e_service_event_schedule(pf);
316 pf->tx_timeout_recovery_level++;
317}
318
319/**
320 * i40e_release_rx_desc - Store the new tail and head values
321 * @rx_ring: ring to bump
322 * @val: new head index
323 **/
324static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
325{
326 rx_ring->next_to_use = val;
327
328 /* Force memory writes to complete before letting h/w
329 * know there are new descriptors to fetch. (Only
330 * applicable for weak-ordered memory model archs,
331 * such as IA-64).
332 */
333 wmb();
334 writel(val, rx_ring->tail);
335}
336
337/**
338 * i40e_get_vsi_stats_struct - Get System Network Statistics
339 * @vsi: the VSI we care about
340 *
341 * Returns the address of the device statistics structure.
342 * The statistics are actually updated from the service task.
343 **/
344struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
345{
346 return &vsi->net_stats;
347}
348
349/**
350 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
351 * @netdev: network interface device structure
352 *
353 * Returns the address of the device statistics structure.
354 * The statistics are actually updated from the service task.
355 **/
38e00438
VD		 356#ifdef I40E_FCOE
357struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
358 struct net_device *netdev,
359 struct rtnl_link_stats64 *stats)
360#else
41c445ff
JB		 361static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
362 struct net_device *netdev,
980e9b11 363 struct rtnl_link_stats64 *stats)
38e00438 364#endif
41c445ff
JB		 365{
366 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 367 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 368 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 369 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
370 int i;
371
bc7d338f
ASJ		 372 if (test_bit(__I40E_DOWN, &vsi->state))
373 return stats;
374
3c325ced
JB		 375 if (!vsi->tx_rings)
376 return stats;
377
980e9b11
AD		 378 rcu_read_lock();
379 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 380 u64 bytes, packets;
381 unsigned int start;
382
383 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
384 if (!tx_ring)
385 continue;
386
387 do {
57a7744e 388 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 389 packets = tx_ring->stats.packets;
390 bytes = tx_ring->stats.bytes;
57a7744e 391 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 392
393 stats->tx_packets += packets;
394 stats->tx_bytes += bytes;
395 rx_ring = &tx_ring[1];
396
397 do {
57a7744e 398 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 399 packets = rx_ring->stats.packets;
400 bytes = rx_ring->stats.bytes;
57a7744e 401 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 402
980e9b11
AD		 403 stats->rx_packets += packets;
404 stats->rx_bytes += bytes;
405 }
406 rcu_read_unlock();
407
a5282f44 408 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 409 stats->multicast = vsi_stats->multicast;
410 stats->tx_errors = vsi_stats->tx_errors;
411 stats->tx_dropped = vsi_stats->tx_dropped;
412 stats->rx_errors = vsi_stats->rx_errors;
413 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
414 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 415
980e9b11 416 return stats;
41c445ff
JB		 417}
418
419/**
420 * i40e_vsi_reset_stats - Resets all stats of the given vsi
421 * @vsi: the VSI to have its stats reset
422 **/
423void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
424{
425 struct rtnl_link_stats64 *ns;
426 int i;
427
428 if (!vsi)
429 return;
430
431 ns = i40e_get_vsi_stats_struct(vsi);
432 memset(ns, 0, sizeof(*ns));
433 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
434 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
435 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 436 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 437 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 438 memset(&vsi->rx_rings[i]->stats, 0 ,
439 sizeof(vsi->rx_rings[i]->stats));
440 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
441 sizeof(vsi->rx_rings[i]->rx_stats));
442 memset(&vsi->tx_rings[i]->stats, 0 ,
443 sizeof(vsi->tx_rings[i]->stats));
444 memset(&vsi->tx_rings[i]->tx_stats, 0,
445 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 446 }
8e9dca53 447 }
41c445ff
JB		 448 vsi->stat_offsets_loaded = false;
449}
450
451/**
452 * i40e_pf_reset_stats - Reset all of the stats for the given pf
453 * @pf: the PF to be reset
454 **/
455void i40e_pf_reset_stats(struct i40e_pf *pf)
456{
e91fdf76
SN		 457 int i;
458
41c445ff
JB		 459 memset(&pf->stats, 0, sizeof(pf->stats));
460 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
461 pf->stat_offsets_loaded = false;
e91fdf76
SN		 462
463 for (i = 0; i < I40E_MAX_VEB; i++) {
464 if (pf->veb[i]) {
465 memset(&pf->veb[i]->stats, 0,
466 sizeof(pf->veb[i]->stats));
467 memset(&pf->veb[i]->stats_offsets, 0,
468 sizeof(pf->veb[i]->stats_offsets));
469 pf->veb[i]->stat_offsets_loaded = false;
470 }
471 }
41c445ff
JB		 472}
473
474/**
475 * i40e_stat_update48 - read and update a 48 bit stat from the chip
476 * @hw: ptr to the hardware info
477 * @hireg: the high 32 bit reg to read
478 * @loreg: the low 32 bit reg to read
479 * @offset_loaded: has the initial offset been loaded yet
480 * @offset: ptr to current offset value
481 * @stat: ptr to the stat
482 *
483 * Since the device stats are not reset at PFReset, they likely will not
484 * be zeroed when the driver starts. We'll save the first values read
485 * and use them as offsets to be subtracted from the raw values in order
486 * to report stats that count from zero. In the process, we also manage
487 * the potential roll-over.
488 **/
489static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
490 bool offset_loaded, u64 *offset, u64 *stat)
491{
492 u64 new_data;
493
ab60085e 494 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 495 new_data = rd32(hw, loreg);
496 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
497 } else {
498 new_data = rd64(hw, loreg);
499 }
500 if (!offset_loaded)
501 *offset = new_data;
502 if (likely(new_data >= *offset))
503 *stat = new_data - *offset;
504 else
505 *stat = (new_data + ((u64)1 << 48)) - *offset;
506 *stat &= 0xFFFFFFFFFFFFULL;
507}
508
509/**
510 * i40e_stat_update32 - read and update a 32 bit stat from the chip
511 * @hw: ptr to the hardware info
512 * @reg: the hw reg to read
513 * @offset_loaded: has the initial offset been loaded yet
514 * @offset: ptr to current offset value
515 * @stat: ptr to the stat
516 **/
517static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
518 bool offset_loaded, u64 *offset, u64 *stat)
519{
520 u32 new_data;
521
522 new_data = rd32(hw, reg);
523 if (!offset_loaded)
524 *offset = new_data;
525 if (likely(new_data >= *offset))
526 *stat = (u32)(new_data - *offset);
527 else
528 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
529}
530
531/**
532 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
533 * @vsi: the VSI to be updated
534 **/
535void i40e_update_eth_stats(struct i40e_vsi *vsi)
536{
537 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
538 struct i40e_pf *pf = vsi->back;
539 struct i40e_hw *hw = &pf->hw;
540 struct i40e_eth_stats *oes;
541 struct i40e_eth_stats *es; /* device's eth stats */
542
543 es = &vsi->eth_stats;
544 oes = &vsi->eth_stats_offsets;
545
546 /* Gather up the stats that the hw collects */
547 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->tx_errors, &es->tx_errors);
550 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
551 vsi->stat_offsets_loaded,
552 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 553 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
554 vsi->stat_offsets_loaded,
555 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
556 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 559
560 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
561 I40E_GLV_GORCL(stat_idx),
562 vsi->stat_offsets_loaded,
563 &oes->rx_bytes, &es->rx_bytes);
564 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
565 I40E_GLV_UPRCL(stat_idx),
566 vsi->stat_offsets_loaded,
567 &oes->rx_unicast, &es->rx_unicast);
568 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
569 I40E_GLV_MPRCL(stat_idx),
570 vsi->stat_offsets_loaded,
571 &oes->rx_multicast, &es->rx_multicast);
572 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
573 I40E_GLV_BPRCL(stat_idx),
574 vsi->stat_offsets_loaded,
575 &oes->rx_broadcast, &es->rx_broadcast);
576
577 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
578 I40E_GLV_GOTCL(stat_idx),
579 vsi->stat_offsets_loaded,
580 &oes->tx_bytes, &es->tx_bytes);
581 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
582 I40E_GLV_UPTCL(stat_idx),
583 vsi->stat_offsets_loaded,
584 &oes->tx_unicast, &es->tx_unicast);
585 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
586 I40E_GLV_MPTCL(stat_idx),
587 vsi->stat_offsets_loaded,
588 &oes->tx_multicast, &es->tx_multicast);
589 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
590 I40E_GLV_BPTCL(stat_idx),
591 vsi->stat_offsets_loaded,
592 &oes->tx_broadcast, &es->tx_broadcast);
593 vsi->stat_offsets_loaded = true;
594}
595
596/**
597 * i40e_update_veb_stats - Update Switch component statistics
598 * @veb: the VEB being updated
599 **/
600static void i40e_update_veb_stats(struct i40e_veb *veb)
601{
602 struct i40e_pf *pf = veb->pf;
603 struct i40e_hw *hw = &pf->hw;
604 struct i40e_eth_stats *oes;
605 struct i40e_eth_stats *es; /* device's eth stats */
606 int idx = 0;
607
608 idx = veb->stats_idx;
609 es = &veb->stats;
610 oes = &veb->stats_offsets;
611
612 /* Gather up the stats that the hw collects */
613 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
614 veb->stat_offsets_loaded,
615 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 616 if (hw->revision_id > 0)
617 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
618 veb->stat_offsets_loaded,
619 &oes->rx_unknown_protocol,
620 &es->rx_unknown_protocol);
41c445ff
JB		 621 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
622 veb->stat_offsets_loaded,
623 &oes->rx_bytes, &es->rx_bytes);
624 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
625 veb->stat_offsets_loaded,
626 &oes->rx_unicast, &es->rx_unicast);
627 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
628 veb->stat_offsets_loaded,
629 &oes->rx_multicast, &es->rx_multicast);
630 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
631 veb->stat_offsets_loaded,
632 &oes->rx_broadcast, &es->rx_broadcast);
633
634 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
635 veb->stat_offsets_loaded,
636 &oes->tx_bytes, &es->tx_bytes);
637 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
638 veb->stat_offsets_loaded,
639 &oes->tx_unicast, &es->tx_unicast);
640 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
641 veb->stat_offsets_loaded,
642 &oes->tx_multicast, &es->tx_multicast);
643 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
644 veb->stat_offsets_loaded,
645 &oes->tx_broadcast, &es->tx_broadcast);
646 veb->stat_offsets_loaded = true;
647}
648
38e00438
VD		 649#ifdef I40E_FCOE
650/**
651 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
652 * @vsi: the VSI that is capable of doing FCoE
653 **/
654static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
655{
656 struct i40e_pf *pf = vsi->back;
657 struct i40e_hw *hw = &pf->hw;
658 struct i40e_fcoe_stats *ofs;
659 struct i40e_fcoe_stats *fs; /* device's eth stats */
660 int idx;
661
662 if (vsi->type != I40E_VSI_FCOE)
663 return;
664
665 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
666 fs = &vsi->fcoe_stats;
667 ofs = &vsi->fcoe_stats_offsets;
668
669 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
670 vsi->fcoe_stat_offsets_loaded,
671 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
672 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
673 vsi->fcoe_stat_offsets_loaded,
674 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
675 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
676 vsi->fcoe_stat_offsets_loaded,
677 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
678 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
679 vsi->fcoe_stat_offsets_loaded,
680 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
681 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
682 vsi->fcoe_stat_offsets_loaded,
683 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
684 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
685 vsi->fcoe_stat_offsets_loaded,
686 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
687 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
688 vsi->fcoe_stat_offsets_loaded,
689 &ofs->fcoe_last_error, &fs->fcoe_last_error);
690 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
691 vsi->fcoe_stat_offsets_loaded,
692 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
693
694 vsi->fcoe_stat_offsets_loaded = true;
695}
696
697#endif
41c445ff
JB		 698/**
699 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
700 * @pf: the corresponding PF
701 *
702 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
703 **/
704static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
705{
706 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
707 struct i40e_hw_port_stats *nsd = &pf->stats;
708 struct i40e_hw *hw = &pf->hw;
709 u64 xoff = 0;
710 u16 i, v;
711
712 if ((hw->fc.current_mode != I40E_FC_FULL) &&
713 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
714 return;
715
716 xoff = nsd->link_xoff_rx;
717 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
718 pf->stat_offsets_loaded,
719 &osd->link_xoff_rx, &nsd->link_xoff_rx);
720
721 /* No new LFC xoff rx */
722 if (!(nsd->link_xoff_rx - xoff))
723 return;
724
725 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 726 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 727 struct i40e_vsi *vsi = pf->vsi[v];
728
ddfda80f 729 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 730 continue;
731
732 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 733 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 734 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
735 }
736 }
737}
738
739/**
740 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
741 * @pf: the corresponding PF
742 *
743 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
744 **/
745static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
746{
747 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
748 struct i40e_hw_port_stats *nsd = &pf->stats;
749 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
750 struct i40e_dcbx_config *dcb_cfg;
751 struct i40e_hw *hw = &pf->hw;
752 u16 i, v;
753 u8 tc;
754
755 dcb_cfg = &hw->local_dcbx_config;
756
757 /* See if DCB enabled with PFC TC */
758 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
759 !(dcb_cfg->pfc.pfcenable)) {
760 i40e_update_link_xoff_rx(pf);
761 return;
762 }
763
764 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
765 u64 prio_xoff = nsd->priority_xoff_rx[i];
766 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
767 pf->stat_offsets_loaded,
768 &osd->priority_xoff_rx[i],
769 &nsd->priority_xoff_rx[i]);
770
771 /* No new PFC xoff rx */
772 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
773 continue;
774 /* Get the TC for given priority */
775 tc = dcb_cfg->etscfg.prioritytable[i];
776 xoff[tc] = true;
777 }
778
779 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 780 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 781 struct i40e_vsi *vsi = pf->vsi[v];
782
ddfda80f 783 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 784 continue;
785
786 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 787 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 788
789 tc = ring->dcb_tc;
790 if (xoff[tc])
791 clear_bit(__I40E_HANG_CHECK_ARMED,
792 &ring->state);
793 }
794 }
795}
796
797/**
7812fddc 798 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 799 * @vsi: the VSI to be updated
800 *
801 * There are a few instances where we store the same stat in a
802 * couple of different structs. This is partly because we have
803 * the netdev stats that need to be filled out, which is slightly
804 * different from the "eth_stats" defined by the chip and used in
7812fddc 805 * VF communications. We sort it out here.
41c445ff 806 **/
7812fddc 807static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 808{
809 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 810 struct rtnl_link_stats64 *ons;
811 struct rtnl_link_stats64 *ns; /* netdev stats */
812 struct i40e_eth_stats *oes;
813 struct i40e_eth_stats *es; /* device's eth stats */
814 u32 tx_restart, tx_busy;
815 u32 rx_page, rx_buf;
816 u64 rx_p, rx_b;
817 u64 tx_p, tx_b;
41c445ff
JB		 818 u16 q;
819
820 if (test_bit(__I40E_DOWN, &vsi->state) ||
821 test_bit(__I40E_CONFIG_BUSY, &pf->state))
822 return;
823
824 ns = i40e_get_vsi_stats_struct(vsi);
825 ons = &vsi->net_stats_offsets;
826 es = &vsi->eth_stats;
827 oes = &vsi->eth_stats_offsets;
828
829 /* Gather up the netdev and vsi stats that the driver collects
830 * on the fly during packet processing
831 */
832 rx_b = rx_p = 0;
833 tx_b = tx_p = 0;
834 tx_restart = tx_busy = 0;
835 rx_page = 0;
836 rx_buf = 0;
980e9b11 837 rcu_read_lock();
41c445ff
JB		 838 for (q = 0; q < vsi->num_queue_pairs; q++) {
839 struct i40e_ring *p;
980e9b11
AD		 840 u64 bytes, packets;
841 unsigned int start;
842
843 /* locate Tx ring */
844 p = ACCESS_ONCE(vsi->tx_rings[q]);
845
846 do {
57a7744e 847 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 848 packets = p->stats.packets;
849 bytes = p->stats.bytes;
57a7744e 850 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 851 tx_b += bytes;
852 tx_p += packets;
853 tx_restart += p->tx_stats.restart_queue;
854 tx_busy += p->tx_stats.tx_busy;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc
SN		 898/**
899 * i40e_update_pf_stats - Update the pf statistics counters.
900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
922 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->eth.tx_discards,
925 &nsd->eth.tx_discards);
41c445ff 926
532d283d
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
928 I40E_GLPRT_UPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_unicast,
931 &nsd->eth.rx_unicast);
7812fddc
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
933 I40E_GLPRT_MPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_multicast,
936 &nsd->eth.rx_multicast);
532d283d
SN		 937 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
938 I40E_GLPRT_BPRCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.rx_broadcast,
941 &nsd->eth.rx_broadcast);
942 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
943 I40E_GLPRT_UPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_unicast,
946 &nsd->eth.tx_unicast);
947 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
948 I40E_GLPRT_MPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_multicast,
951 &nsd->eth.tx_multicast);
952 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
953 I40E_GLPRT_BPTCL(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->eth.tx_broadcast,
956 &nsd->eth.tx_broadcast);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->tx_dropped_link_down,
961 &nsd->tx_dropped_link_down);
41c445ff 962
7812fddc
SN		 963 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->crc_errors, &nsd->crc_errors);
41c445ff 966
7812fddc
SN		 967 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 970
7812fddc
SN		 971 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->mac_local_faults,
974 &nsd->mac_local_faults);
975 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->mac_remote_faults,
978 &nsd->mac_remote_faults);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->rx_length_errors,
983 &nsd->rx_length_errors);
41c445ff 984
7812fddc
SN		 985 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->link_xon_rx, &nsd->link_xon_rx);
988 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
989 pf->stat_offsets_loaded,
990 &osd->link_xon_tx, &nsd->link_xon_tx);
991 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
992 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 995
7812fddc
SN		 996 for (i = 0; i < 8; i++) {
997 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 998 pf->stat_offsets_loaded,
7812fddc
SN		 999 &osd->priority_xon_rx[i],
1000 &nsd->priority_xon_rx[i]);
1001 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1002 pf->stat_offsets_loaded,
7812fddc
SN		 1003 &osd->priority_xon_tx[i],
1004 &nsd->priority_xon_tx[i]);
1005 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xoff_tx[i],
1008 &nsd->priority_xoff_tx[i]);
1009 i40e_stat_update32(hw,
1010 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1011 pf->stat_offsets_loaded,
7812fddc
SN		 1012 &osd->priority_xon_2_xoff[i],
1013 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1014 }
1015
7812fddc
SN		 1016 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1017 I40E_GLPRT_PRC64L(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->rx_size_64, &nsd->rx_size_64);
1020 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1021 I40E_GLPRT_PRC127L(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_size_127, &nsd->rx_size_127);
1024 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1025 I40E_GLPRT_PRC255L(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->rx_size_255, &nsd->rx_size_255);
1028 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1029 I40E_GLPRT_PRC511L(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->rx_size_511, &nsd->rx_size_511);
1032 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1033 I40E_GLPRT_PRC1023L(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->rx_size_1023, &nsd->rx_size_1023);
1036 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1037 I40E_GLPRT_PRC1522L(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_size_1522, &nsd->rx_size_1522);
1040 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1041 I40E_GLPRT_PRC9522L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->rx_size_big, &nsd->rx_size_big);
1044
1045 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1046 I40E_GLPRT_PTC64L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->tx_size_64, &nsd->tx_size_64);
1049 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1050 I40E_GLPRT_PTC127L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->tx_size_127, &nsd->tx_size_127);
1053 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1054 I40E_GLPRT_PTC255L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->tx_size_255, &nsd->tx_size_255);
1057 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1058 I40E_GLPRT_PTC511L(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_size_511, &nsd->tx_size_511);
1061 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1062 I40E_GLPRT_PTC1023L(hw->port),
1063 pf->stat_offsets_loaded,
1064 &osd->tx_size_1023, &nsd->tx_size_1023);
1065 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1066 I40E_GLPRT_PTC1522L(hw->port),
1067 pf->stat_offsets_loaded,
1068 &osd->tx_size_1522, &nsd->tx_size_1522);
1069 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1070 I40E_GLPRT_PTC9522L(hw->port),
1071 pf->stat_offsets_loaded,
1072 &osd->tx_size_big, &nsd->tx_size_big);
1073
1074 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1075 pf->stat_offsets_loaded,
1076 &osd->rx_undersize, &nsd->rx_undersize);
1077 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1078 pf->stat_offsets_loaded,
1079 &osd->rx_fragments, &nsd->rx_fragments);
1080 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->rx_oversize, &nsd->rx_oversize);
1083 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_jabber, &nsd->rx_jabber);
1086
433c47de
ASJ		 1087 /* FDIR stats */
1088 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1089 pf->stat_offsets_loaded,
1090 &osd->fd_atr_match, &nsd->fd_atr_match);
1091 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1092 pf->stat_offsets_loaded,
1093 &osd->fd_sb_match, &nsd->fd_sb_match);
1094
7812fddc
SN		 1095 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1096 nsd->tx_lpi_status =
1097 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1098 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1099 nsd->rx_lpi_status =
1100 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1101 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1102 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1103 pf->stat_offsets_loaded,
1104 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1105 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1106 pf->stat_offsets_loaded,
1107 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1108
41c445ff
JB		 1109 pf->stat_offsets_loaded = true;
1110}
1111
7812fddc
SN		 1112/**
1113 * i40e_update_stats - Update the various statistics counters.
1114 * @vsi: the VSI to be updated
1115 *
1116 * Update the various stats for this VSI and its related entities.
1117 **/
1118void i40e_update_stats(struct i40e_vsi *vsi)
1119{
1120 struct i40e_pf *pf = vsi->back;
1121
1122 if (vsi == pf->vsi[pf->lan_vsi])
1123 i40e_update_pf_stats(pf);
1124
1125 i40e_update_vsi_stats(vsi);
38e00438
VD		 1126#ifdef I40E_FCOE
1127 i40e_update_fcoe_stats(vsi);
1128#endif
7812fddc
SN		 1129}
1130
41c445ff
JB		 1131/**
1132 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1133 * @vsi: the VSI to be searched
1134 * @macaddr: the MAC address
1135 * @vlan: the vlan
1136 * @is_vf: make sure its a vf filter, else doesn't matter
1137 * @is_netdev: make sure its a netdev filter, else doesn't matter
1138 *
1139 * Returns ptr to the filter object or NULL
1140 **/
1141static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1142 u8 *macaddr, s16 vlan,
1143 bool is_vf, bool is_netdev)
1144{
1145 struct i40e_mac_filter *f;
1146
1147 if (!vsi || !macaddr)
1148 return NULL;
1149
1150 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1151 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1152 (vlan == f->vlan) &&
1153 (!is_vf || f->is_vf) &&
1154 (!is_netdev || f->is_netdev))
1155 return f;
1156 }
1157 return NULL;
1158}
1159
1160/**
1161 * i40e_find_mac - Find a mac addr in the macvlan filters list
1162 * @vsi: the VSI to be searched
1163 * @macaddr: the MAC address we are searching for
1164 * @is_vf: make sure its a vf filter, else doesn't matter
1165 * @is_netdev: make sure its a netdev filter, else doesn't matter
1166 *
1167 * Returns the first filter with the provided MAC address or NULL if
1168 * MAC address was not found
1169 **/
1170struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1171 bool is_vf, bool is_netdev)
1172{
1173 struct i40e_mac_filter *f;
1174
1175 if (!vsi || !macaddr)
1176 return NULL;
1177
1178 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1179 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1180 (!is_vf || f->is_vf) &&
1181 (!is_netdev || f->is_netdev))
1182 return f;
1183 }
1184 return NULL;
1185}
1186
1187/**
1188 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1189 * @vsi: the VSI to be searched
1190 *
1191 * Returns true if VSI is in vlan mode or false otherwise
1192 **/
1193bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1194{
1195 struct i40e_mac_filter *f;
1196
1197 /* Only -1 for all the filters denotes not in vlan mode
1198 * so we have to go through all the list in order to make sure
1199 */
1200 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1201 if (f->vlan >= 0)
1202 return true;
1203 }
1204
1205 return false;
1206}
1207
1208/**
1209 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1210 * @vsi: the VSI to be searched
1211 * @macaddr: the mac address to be filtered
1212 * @is_vf: true if it is a vf
1213 * @is_netdev: true if it is a netdev
1214 *
1215 * Goes through all the macvlan filters and adds a
1216 * macvlan filter for each unique vlan that already exists
1217 *
1218 * Returns first filter found on success, else NULL
1219 **/
1220struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1221 bool is_vf, bool is_netdev)
1222{
1223 struct i40e_mac_filter *f;
1224
1225 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1226 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1227 is_vf, is_netdev)) {
1228 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1229 is_vf, is_netdev))
41c445ff
JB		 1230 return NULL;
1231 }
1232 }
1233
1234 return list_first_entry_or_null(&vsi->mac_filter_list,
1235 struct i40e_mac_filter, list);
1236}
1237
8c27d42e
GR		 1238/**
1239 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1240 * @vsi: the PF Main VSI - inappropriate for any other VSI
1241 * @macaddr: the MAC address
1242 **/
1243static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
1244{
1245 struct i40e_aqc_remove_macvlan_element_data element;
1246 struct i40e_pf *pf = vsi->back;
1247 i40e_status aq_ret;
1248
1249 /* Only appropriate for the PF main VSI */
1250 if (vsi->type != I40E_VSI_MAIN)
1251 return;
1252
1253 ether_addr_copy(element.mac_addr, macaddr);
1254 element.vlan_tag = 0;
1255 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1256 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1257 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1258 if (aq_ret)
1259 dev_err(&pf->pdev->dev, "Could not remove default MAC-VLAN\n");
1260}
1261
41c445ff
JB		 1262/**
1263 * i40e_add_filter - Add a mac/vlan filter to the VSI
1264 * @vsi: the VSI to be searched
1265 * @macaddr: the MAC address
1266 * @vlan: the vlan
1267 * @is_vf: make sure its a vf filter, else doesn't matter
1268 * @is_netdev: make sure its a netdev filter, else doesn't matter
1269 *
1270 * Returns ptr to the filter object or NULL when no memory available.
1271 **/
1272struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1273 u8 *macaddr, s16 vlan,
1274 bool is_vf, bool is_netdev)
1275{
1276 struct i40e_mac_filter *f;
1277
1278 if (!vsi || !macaddr)
1279 return NULL;
1280
1281 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1282 if (!f) {
1283 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1284 if (!f)
1285 goto add_filter_out;
1286
9a173901 1287 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1288 f->vlan = vlan;
1289 f->changed = true;
1290
1291 INIT_LIST_HEAD(&f->list);
1292 list_add(&f->list, &vsi->mac_filter_list);
1293 }
1294
1295 /* increment counter and add a new flag if needed */
1296 if (is_vf) {
1297 if (!f->is_vf) {
1298 f->is_vf = true;
1299 f->counter++;
1300 }
1301 } else if (is_netdev) {
1302 if (!f->is_netdev) {
1303 f->is_netdev = true;
1304 f->counter++;
1305 }
1306 } else {
1307 f->counter++;
1308 }
1309
1310 /* changed tells sync_filters_subtask to
1311 * push the filter down to the firmware
1312 */
1313 if (f->changed) {
1314 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1315 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1316 }
1317
1318add_filter_out:
1319 return f;
1320}
1321
1322/**
1323 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1324 * @vsi: the VSI to be searched
1325 * @macaddr: the MAC address
1326 * @vlan: the vlan
1327 * @is_vf: make sure it's a vf filter, else doesn't matter
1328 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1329 **/
1330void i40e_del_filter(struct i40e_vsi *vsi,
1331 u8 *macaddr, s16 vlan,
1332 bool is_vf, bool is_netdev)
1333{
1334 struct i40e_mac_filter *f;
1335
1336 if (!vsi || !macaddr)
1337 return;
1338
1339 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1340 if (!f || f->counter == 0)
1341 return;
1342
1343 if (is_vf) {
1344 if (f->is_vf) {
1345 f->is_vf = false;
1346 f->counter--;
1347 }
1348 } else if (is_netdev) {
1349 if (f->is_netdev) {
1350 f->is_netdev = false;
1351 f->counter--;
1352 }
1353 } else {
1354 /* make sure we don't remove a filter in use by vf or netdev */
1355 int min_f = 0;
1356 min_f += (f->is_vf ? 1 : 0);
1357 min_f += (f->is_netdev ? 1 : 0);
1358
1359 if (f->counter > min_f)
1360 f->counter--;
1361 }
1362
1363 /* counter == 0 tells sync_filters_subtask to
1364 * remove the filter from the firmware's list
1365 */
1366 if (f->counter == 0) {
1367 f->changed = true;
1368 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1369 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1370 }
1371}
1372
1373/**
1374 * i40e_set_mac - NDO callback to set mac address
1375 * @netdev: network interface device structure
1376 * @p: pointer to an address structure
1377 *
1378 * Returns 0 on success, negative on failure
1379 **/
38e00438
VD		 1380#ifdef I40E_FCOE
1381int i40e_set_mac(struct net_device *netdev, void *p)
1382#else
41c445ff 1383static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1384#endif
41c445ff
JB		 1385{
1386 struct i40e_netdev_priv *np = netdev_priv(netdev);
1387 struct i40e_vsi *vsi = np->vsi;
1388 struct sockaddr *addr = p;
1389 struct i40e_mac_filter *f;
1390
1391 if (!is_valid_ether_addr(addr->sa_data))
1392 return -EADDRNOTAVAIL;
1393
1394 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1395
80f6428f
ASJ		 1396 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1397 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1398 return -EADDRNOTAVAIL;
1399
41c445ff
JB		 1400 if (vsi->type == I40E_VSI_MAIN) {
1401 i40e_status ret;
1402 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1403 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1404 addr->sa_data, NULL);
1405 if (ret) {
1406 netdev_info(netdev,
1407 "Addr change for Main VSI failed: %d\n",
1408 ret);
1409 return -EADDRNOTAVAIL;
1410 }
41c445ff
JB		 1411 }
1412
6252c7e4
SN		 1413 f = i40e_find_mac(vsi, addr->sa_data, false, true);
1414 if (!f) {
6c8ad1ba
SN		 1415 /* In order to be sure to not drop any packets, add the
1416 * new address first then delete the old one.
1417 */
1418 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1419 false, false);
1420 if (!f)
1421 return -ENOMEM;
1422
1423 i40e_sync_vsi_filters(vsi);
1424 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1425 false, false);
1426 i40e_sync_vsi_filters(vsi);
1427 }
41c445ff 1428
6252c7e4 1429 f->is_laa = true;
6c8ad1ba
SN		 1430 if (!ether_addr_equal(netdev->dev_addr, addr->sa_data))
1431 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1432
1433 return 0;
1434}
1435
1436/**
1437 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1438 * @vsi: the VSI being setup
1439 * @ctxt: VSI context structure
1440 * @enabled_tc: Enabled TCs bitmap
1441 * @is_add: True if called before Add VSI
1442 *
1443 * Setup VSI queue mapping for enabled traffic classes.
1444 **/
38e00438
VD		 1445#ifdef I40E_FCOE
1446void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1447 struct i40e_vsi_context *ctxt,
1448 u8 enabled_tc,
1449 bool is_add)
1450#else
41c445ff
JB		 1451static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1452 struct i40e_vsi_context *ctxt,
1453 u8 enabled_tc,
1454 bool is_add)
38e00438 1455#endif
41c445ff
JB		 1456{
1457 struct i40e_pf *pf = vsi->back;
1458 u16 sections = 0;
1459 u8 netdev_tc = 0;
1460 u16 numtc = 0;
1461 u16 qcount;
1462 u8 offset;
1463 u16 qmap;
1464 int i;
4e3b35b0 1465 u16 num_tc_qps = 0;
41c445ff
JB		 1466
1467 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1468 offset = 0;
1469
1470 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1471 /* Find numtc from enabled TC bitmap */
1472 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1473 if (enabled_tc & (1 << i)) /* TC is enabled */
1474 numtc++;
1475 }
1476 if (!numtc) {
1477 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1478 numtc = 1;
1479 }
1480 } else {
1481 /* At least TC0 is enabled in case of non-DCB case */
1482 numtc = 1;
1483 }
1484
1485 vsi->tc_config.numtc = numtc;
1486 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1487 /* Number of queues per enabled TC */
eb051afe 1488 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1489 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1490
1491 /* Setup queue offset/count for all TCs for given VSI */
1492 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1493 /* See if the given TC is enabled for the given VSI */
1494 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1495 int pow, num_qps;
1496
41c445ff
JB		 1497 switch (vsi->type) {
1498 case I40E_VSI_MAIN:
4e3b35b0 1499 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1500 break;
38e00438
VD		 1501#ifdef I40E_FCOE
1502 case I40E_VSI_FCOE:
1503 qcount = num_tc_qps;
1504 break;
1505#endif
41c445ff
JB		 1506 case I40E_VSI_FDIR:
1507 case I40E_VSI_SRIOV:
1508 case I40E_VSI_VMDQ2:
1509 default:
4e3b35b0 1510 qcount = num_tc_qps;
41c445ff
JB		 1511 WARN_ON(i != 0);
1512 break;
1513 }
4e3b35b0
NP		 1514 vsi->tc_config.tc_info[i].qoffset = offset;
1515 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1516
1517 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1518 num_qps = qcount;
41c445ff 1519 pow = 0;
4e3b35b0 1520 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1521 pow++;
1522 num_qps >>= 1;
1523 }
1524
1525 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1526 qmap =
1527 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1528 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1529
4e3b35b0 1530 offset += qcount;
41c445ff
JB		 1531 } else {
1532 /* TC is not enabled so set the offset to
1533 * default queue and allocate one queue
1534 * for the given TC.
1535 */
1536 vsi->tc_config.tc_info[i].qoffset = 0;
1537 vsi->tc_config.tc_info[i].qcount = 1;
1538 vsi->tc_config.tc_info[i].netdev_tc = 0;
1539
1540 qmap = 0;
1541 }
1542 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1543 }
1544
1545 /* Set actual Tx/Rx queue pairs */
1546 vsi->num_queue_pairs = offset;
1547
1548 /* Scheduler section valid can only be set for ADD VSI */
1549 if (is_add) {
1550 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1551
1552 ctxt->info.up_enable_bits = enabled_tc;
1553 }
1554 if (vsi->type == I40E_VSI_SRIOV) {
1555 ctxt->info.mapping_flags |=
1556 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1557 for (i = 0; i < vsi->num_queue_pairs; i++)
1558 ctxt->info.queue_mapping[i] =
1559 cpu_to_le16(vsi->base_queue + i);
1560 } else {
1561 ctxt->info.mapping_flags |=
1562 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1563 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1564 }
1565 ctxt->info.valid_sections |= cpu_to_le16(sections);
1566}
1567
1568/**
1569 * i40e_set_rx_mode - NDO callback to set the netdev filters
1570 * @netdev: network interface device structure
1571 **/
38e00438
VD		 1572#ifdef I40E_FCOE
1573void i40e_set_rx_mode(struct net_device *netdev)
1574#else
41c445ff 1575static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1576#endif
41c445ff
JB		 1577{
1578 struct i40e_netdev_priv *np = netdev_priv(netdev);
1579 struct i40e_mac_filter *f, *ftmp;
1580 struct i40e_vsi *vsi = np->vsi;
1581 struct netdev_hw_addr *uca;
1582 struct netdev_hw_addr *mca;
1583 struct netdev_hw_addr *ha;
1584
1585 /* add addr if not already in the filter list */
1586 netdev_for_each_uc_addr(uca, netdev) {
1587 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1588 if (i40e_is_vsi_in_vlan(vsi))
1589 i40e_put_mac_in_vlan(vsi, uca->addr,
1590 false, true);
1591 else
1592 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1593 false, true);
1594 }
1595 }
1596
1597 netdev_for_each_mc_addr(mca, netdev) {
1598 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1599 if (i40e_is_vsi_in_vlan(vsi))
1600 i40e_put_mac_in_vlan(vsi, mca->addr,
1601 false, true);
1602 else
1603 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1604 false, true);
1605 }
1606 }
1607
1608 /* remove filter if not in netdev list */
1609 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1610 bool found = false;
1611
1612 if (!f->is_netdev)
1613 continue;
1614
1615 if (is_multicast_ether_addr(f->macaddr)) {
1616 netdev_for_each_mc_addr(mca, netdev) {
1617 if (ether_addr_equal(mca->addr, f->macaddr)) {
1618 found = true;
1619 break;
1620 }
1621 }
1622 } else {
1623 netdev_for_each_uc_addr(uca, netdev) {
1624 if (ether_addr_equal(uca->addr, f->macaddr)) {
1625 found = true;
1626 break;
1627 }
1628 }
1629
1630 for_each_dev_addr(netdev, ha) {
1631 if (ether_addr_equal(ha->addr, f->macaddr)) {
1632 found = true;
1633 break;
1634 }
1635 }
1636 }
1637 if (!found)
1638 i40e_del_filter(
1639 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1640 }
1641
1642 /* check for other flag changes */
1643 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1644 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1645 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1646 }
1647}
1648
1649/**
1650 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1651 * @vsi: ptr to the VSI
1652 *
1653 * Push any outstanding VSI filter changes through the AdminQ.
1654 *
1655 * Returns 0 or error value
1656 **/
1657int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1658{
1659 struct i40e_mac_filter *f, *ftmp;
1660 bool promisc_forced_on = false;
1661 bool add_happened = false;
1662 int filter_list_len = 0;
1663 u32 changed_flags = 0;
dcae29be 1664 i40e_status aq_ret = 0;
41c445ff
JB		 1665 struct i40e_pf *pf;
1666 int num_add = 0;
1667 int num_del = 0;
1668 u16 cmd_flags;
1669
1670 /* empty array typed pointers, kcalloc later */
1671 struct i40e_aqc_add_macvlan_element_data *add_list;
1672 struct i40e_aqc_remove_macvlan_element_data *del_list;
1673
1674 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1675 usleep_range(1000, 2000);
1676 pf = vsi->back;
1677
1678 if (vsi->netdev) {
1679 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1680 vsi->current_netdev_flags = vsi->netdev->flags;
1681 }
1682
1683 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1684 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1685
1686 filter_list_len = pf->hw.aq.asq_buf_size /
1687 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1688 del_list = kcalloc(filter_list_len,
1689 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1690 GFP_KERNEL);
1691 if (!del_list)
1692 return -ENOMEM;
1693
1694 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1695 if (!f->changed)
1696 continue;
1697
1698 if (f->counter != 0)
1699 continue;
1700 f->changed = false;
1701 cmd_flags = 0;
1702
1703 /* add to delete list */
9a173901 1704 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1705 del_list[num_del].vlan_tag =
1706 cpu_to_le16((u16)(f->vlan ==
1707 I40E_VLAN_ANY ? 0 : f->vlan));
1708
41c445ff
JB		 1709 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1710 del_list[num_del].flags = cmd_flags;
1711 num_del++;
1712
1713 /* unlink from filter list */
1714 list_del(&f->list);
1715 kfree(f);
1716
1717 /* flush a full buffer */
1718 if (num_del == filter_list_len) {
dcae29be 1719 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1720 vsi->seid, del_list, num_del,
1721 NULL);
1722 num_del = 0;
1723 memset(del_list, 0, sizeof(*del_list));
1724
fdfe9cbe
SN		 1725 if (aq_ret &&
1726 pf->hw.aq.asq_last_status !=
1727 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1728 dev_info(&pf->pdev->dev,
1729 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1730 aq_ret,
41c445ff
JB		 1731 pf->hw.aq.asq_last_status);
1732 }
1733 }
1734 if (num_del) {
dcae29be 1735 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1736 del_list, num_del, NULL);
1737 num_del = 0;
1738
fdfe9cbe
SN		 1739 if (aq_ret &&
1740 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1741 dev_info(&pf->pdev->dev,
1742 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1743 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1744 }
1745
1746 kfree(del_list);
1747 del_list = NULL;
1748
1749 /* do all the adds now */
1750 filter_list_len = pf->hw.aq.asq_buf_size /
1751 sizeof(struct i40e_aqc_add_macvlan_element_data),
1752 add_list = kcalloc(filter_list_len,
1753 sizeof(struct i40e_aqc_add_macvlan_element_data),
1754 GFP_KERNEL);
1755 if (!add_list)
1756 return -ENOMEM;
1757
1758 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1759 if (!f->changed)
1760 continue;
1761
1762 if (f->counter == 0)
1763 continue;
1764 f->changed = false;
1765 add_happened = true;
1766 cmd_flags = 0;
1767
1768 /* add to add array */
9a173901 1769 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1770 add_list[num_add].vlan_tag =
1771 cpu_to_le16(
1772 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1773 add_list[num_add].queue_number = 0;
1774
1775 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1776 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1777 num_add++;
1778
1779 /* flush a full buffer */
1780 if (num_add == filter_list_len) {
dcae29be
JB		 1781 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1782 add_list, num_add,
1783 NULL);
41c445ff
JB		 1784 num_add = 0;
1785
dcae29be 1786 if (aq_ret)
41c445ff
JB		 1787 break;
1788 memset(add_list, 0, sizeof(*add_list));
1789 }
1790 }
1791 if (num_add) {
dcae29be
JB		 1792 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1793 add_list, num_add, NULL);
41c445ff
JB		 1794 num_add = 0;
1795 }
1796 kfree(add_list);
1797 add_list = NULL;
1798
dcae29be 1799 if (add_happened && (!aq_ret)) {
41c445ff 1800 /* do nothing */;
dcae29be 1801 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1802 dev_info(&pf->pdev->dev,
1803 "add filter failed, err %d, aq_err %d\n",
dcae29be 1804 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1805 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1806 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1807 &vsi->state)) {
1808 promisc_forced_on = true;
1809 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1810 &vsi->state);
1811 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1812 }
1813 }
1814 }
1815
1816 /* check for changes in promiscuous modes */
1817 if (changed_flags & IFF_ALLMULTI) {
1818 bool cur_multipromisc;
1819 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1820 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1821 vsi->seid,
1822 cur_multipromisc,
1823 NULL);
1824 if (aq_ret)
41c445ff
JB		 1825 dev_info(&pf->pdev->dev,
1826 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1827 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1828 }
1829 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1830 bool cur_promisc;
1831 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1832 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1833 &vsi->state));
dcae29be
JB		 1834 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1835 vsi->seid,
1836 cur_promisc, NULL);
1837 if (aq_ret)
41c445ff
JB		 1838 dev_info(&pf->pdev->dev,
1839 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1840 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1841 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1842 vsi->seid,
1843 cur_promisc, NULL);
1844 if (aq_ret)
1845 dev_info(&pf->pdev->dev,
1846 "set brdcast promisc failed, err %d, aq_err %d\n",
1847 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1848 }
1849
1850 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1851 return 0;
1852}
1853
1854/**
1855 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1856 * @pf: board private structure
1857 **/
1858static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1859{
1860 int v;
1861
1862 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1863 return;
1864 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1865
505682cd 1866 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1867 if (pf->vsi[v] &&
1868 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1869 i40e_sync_vsi_filters(pf->vsi[v]);
1870 }
1871}
1872
1873/**
1874 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1875 * @netdev: network interface device structure
1876 * @new_mtu: new value for maximum frame size
1877 *
1878 * Returns 0 on success, negative on failure
1879 **/
1880static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1881{
1882 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1883 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1884 struct i40e_vsi *vsi = np->vsi;
1885
1886 /* MTU < 68 is an error and causes problems on some kernels */
1887 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1888 return -EINVAL;
1889
1890 netdev_info(netdev, "changing MTU from %d to %d\n",
1891 netdev->mtu, new_mtu);
1892 netdev->mtu = new_mtu;
1893 if (netif_running(netdev))
1894 i40e_vsi_reinit_locked(vsi);
1895
1896 return 0;
1897}
1898
beb0dff1
JK		 1899/**
1900 * i40e_ioctl - Access the hwtstamp interface
1901 * @netdev: network interface device structure
1902 * @ifr: interface request data
1903 * @cmd: ioctl command
1904 **/
1905int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1906{
1907 struct i40e_netdev_priv *np = netdev_priv(netdev);
1908 struct i40e_pf *pf = np->vsi->back;
1909
1910 switch (cmd) {
1911 case SIOCGHWTSTAMP:
1912 return i40e_ptp_get_ts_config(pf, ifr);
1913 case SIOCSHWTSTAMP:
1914 return i40e_ptp_set_ts_config(pf, ifr);
1915 default:
1916 return -EOPNOTSUPP;
1917 }
1918}
1919
41c445ff
JB		 1920/**
1921 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1922 * @vsi: the vsi being adjusted
1923 **/
1924void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1925{
1926 struct i40e_vsi_context ctxt;
1927 i40e_status ret;
1928
1929 if ((vsi->info.valid_sections &
1930 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1931 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1932 return; /* already enabled */
1933
1934 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1935 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1936 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1937
1938 ctxt.seid = vsi->seid;
1939 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1940 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1941 if (ret) {
1942 dev_info(&vsi->back->pdev->dev,
1943 "%s: update vsi failed, aq_err=%d\n",
1944 __func__, vsi->back->hw.aq.asq_last_status);
1945 }
1946}
1947
1948/**
1949 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1950 * @vsi: the vsi being adjusted
1951 **/
1952void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1953{
1954 struct i40e_vsi_context ctxt;
1955 i40e_status ret;
1956
1957 if ((vsi->info.valid_sections &
1958 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1959 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1960 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1961 return; /* already disabled */
1962
1963 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1964 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1965 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1966
1967 ctxt.seid = vsi->seid;
1968 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1969 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1970 if (ret) {
1971 dev_info(&vsi->back->pdev->dev,
1972 "%s: update vsi failed, aq_err=%d\n",
1973 __func__, vsi->back->hw.aq.asq_last_status);
1974 }
1975}
1976
1977/**
1978 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1979 * @netdev: network interface to be adjusted
1980 * @features: netdev features to test if VLAN offload is enabled or not
1981 **/
1982static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1983{
1984 struct i40e_netdev_priv *np = netdev_priv(netdev);
1985 struct i40e_vsi *vsi = np->vsi;
1986
1987 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1988 i40e_vlan_stripping_enable(vsi);
1989 else
1990 i40e_vlan_stripping_disable(vsi);
1991}
1992
1993/**
1994 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1995 * @vsi: the vsi being configured
1996 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1997 **/
1998int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1999{
2000 struct i40e_mac_filter *f, *add_f;
2001 bool is_netdev, is_vf;
41c445ff
JB		 2002
2003 is_vf = (vsi->type == I40E_VSI_SRIOV);
2004 is_netdev = !!(vsi->netdev);
2005
2006 if (is_netdev) {
2007 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2008 is_vf, is_netdev);
2009 if (!add_f) {
2010 dev_info(&vsi->back->pdev->dev,
2011 "Could not add vlan filter %d for %pM\n",
2012 vid, vsi->netdev->dev_addr);
2013 return -ENOMEM;
2014 }
2015 }
2016
2017 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2018 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2019 if (!add_f) {
2020 dev_info(&vsi->back->pdev->dev,
2021 "Could not add vlan filter %d for %pM\n",
2022 vid, f->macaddr);
2023 return -ENOMEM;
2024 }
2025 }
2026
41c445ff
JB		 2027 /* Now if we add a vlan tag, make sure to check if it is the first
2028 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2029 * with 0, so we now accept untagged and specified tagged traffic
2030 * (and not any taged and untagged)
2031 */
2032 if (vid > 0) {
2033 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2034 I40E_VLAN_ANY,
2035 is_vf, is_netdev)) {
2036 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2037 I40E_VLAN_ANY, is_vf, is_netdev);
2038 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2039 is_vf, is_netdev);
2040 if (!add_f) {
2041 dev_info(&vsi->back->pdev->dev,
2042 "Could not add filter 0 for %pM\n",
2043 vsi->netdev->dev_addr);
2044 return -ENOMEM;
2045 }
2046 }
8d82a7c5 2047 }
41c445ff 2048
8d82a7c5
GR		 2049 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2050 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2051 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2052 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2053 is_vf, is_netdev)) {
2054 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2055 is_vf, is_netdev);
2056 add_f = i40e_add_filter(vsi, f->macaddr,
2057 0, is_vf, is_netdev);
2058 if (!add_f) {
2059 dev_info(&vsi->back->pdev->dev,
2060 "Could not add filter 0 for %pM\n",
2061 f->macaddr);
2062 return -ENOMEM;
2063 }
2064 }
2065 }
41c445ff
JB		 2066 }
2067
80f6428f
ASJ		 2068 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2069 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2070 return 0;
2071
2072 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2073}
2074
2075/**
2076 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2077 * @vsi: the vsi being configured
2078 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2079 *
2080 * Return: 0 on success or negative otherwise
41c445ff
JB		 2081 **/
2082int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2083{
2084 struct net_device *netdev = vsi->netdev;
2085 struct i40e_mac_filter *f, *add_f;
2086 bool is_vf, is_netdev;
2087 int filter_count = 0;
41c445ff
JB		 2088
2089 is_vf = (vsi->type == I40E_VSI_SRIOV);
2090 is_netdev = !!(netdev);
2091
2092 if (is_netdev)
2093 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2094
2095 list_for_each_entry(f, &vsi->mac_filter_list, list)
2096 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2097
41c445ff
JB		 2098 /* go through all the filters for this VSI and if there is only
2099 * vid == 0 it means there are no other filters, so vid 0 must
2100 * be replaced with -1. This signifies that we should from now
2101 * on accept any traffic (with any tag present, or untagged)
2102 */
2103 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2104 if (is_netdev) {
2105 if (f->vlan &&
2106 ether_addr_equal(netdev->dev_addr, f->macaddr))
2107 filter_count++;
2108 }
2109
2110 if (f->vlan)
2111 filter_count++;
2112 }
2113
2114 if (!filter_count && is_netdev) {
2115 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2116 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2117 is_vf, is_netdev);
2118 if (!f) {
2119 dev_info(&vsi->back->pdev->dev,
2120 "Could not add filter %d for %pM\n",
2121 I40E_VLAN_ANY, netdev->dev_addr);
2122 return -ENOMEM;
2123 }
2124 }
2125
2126 if (!filter_count) {
2127 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2128 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2129 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2130 is_vf, is_netdev);
2131 if (!add_f) {
2132 dev_info(&vsi->back->pdev->dev,
2133 "Could not add filter %d for %pM\n",
2134 I40E_VLAN_ANY, f->macaddr);
2135 return -ENOMEM;
2136 }
2137 }
2138 }
2139
80f6428f
ASJ		 2140 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2141 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2142 return 0;
2143
41c445ff
JB		 2144 return i40e_sync_vsi_filters(vsi);
2145}
2146
2147/**
2148 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2149 * @netdev: network interface to be adjusted
2150 * @vid: vlan id to be added
078b5876
JB		 2151 *
2152 * net_device_ops implementation for adding vlan ids
41c445ff 2153 **/
38e00438
VD		 2154#ifdef I40E_FCOE
2155int i40e_vlan_rx_add_vid(struct net_device *netdev,
2156 __always_unused __be16 proto, u16 vid)
2157#else
41c445ff
JB		 2158static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2159 __always_unused __be16 proto, u16 vid)
38e00438 2160#endif
41c445ff
JB		 2161{
2162 struct i40e_netdev_priv *np = netdev_priv(netdev);
2163 struct i40e_vsi *vsi = np->vsi;
078b5876 2164 int ret = 0;
41c445ff
JB		 2165
2166 if (vid > 4095)
078b5876
JB		 2167 return -EINVAL;
2168
2169 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2170
6982d429
ASJ		 2171 /* If the network stack called us with vid = 0 then
2172 * it is asking to receive priority tagged packets with
2173 * vlan id 0. Our HW receives them by default when configured
2174 * to receive untagged packets so there is no need to add an
2175 * extra filter for vlan 0 tagged packets.
41c445ff 2176 */
6982d429
ASJ		 2177 if (vid)
2178 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2179
078b5876
JB		 2180 if (!ret && (vid < VLAN_N_VID))
2181 set_bit(vid, vsi->active_vlans);
41c445ff 2182
078b5876 2183 return ret;
41c445ff
JB		 2184}
2185
2186/**
2187 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2188 * @netdev: network interface to be adjusted
2189 * @vid: vlan id to be removed
078b5876 2190 *
fdfd943e 2191 * net_device_ops implementation for removing vlan ids
41c445ff 2192 **/
38e00438
VD		 2193#ifdef I40E_FCOE
2194int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2195 __always_unused __be16 proto, u16 vid)
2196#else
41c445ff
JB		 2197static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2198 __always_unused __be16 proto, u16 vid)
38e00438 2199#endif
41c445ff
JB		 2200{
2201 struct i40e_netdev_priv *np = netdev_priv(netdev);
2202 struct i40e_vsi *vsi = np->vsi;
2203
078b5876
JB		 2204 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2205
41c445ff
JB		 2206 /* return code is ignored as there is nothing a user
2207 * can do about failure to remove and a log message was
078b5876 2208 * already printed from the other function
41c445ff
JB		 2209 */
2210 i40e_vsi_kill_vlan(vsi, vid);
2211
2212 clear_bit(vid, vsi->active_vlans);
078b5876 2213
41c445ff
JB		 2214 return 0;
2215}
2216
2217/**
2218 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2219 * @vsi: the vsi being brought back up
2220 **/
2221static void i40e_restore_vlan(struct i40e_vsi *vsi)
2222{
2223 u16 vid;
2224
2225 if (!vsi->netdev)
2226 return;
2227
2228 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2229
2230 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2231 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2232 vid);
2233}
2234
2235/**
2236 * i40e_vsi_add_pvid - Add pvid for the VSI
2237 * @vsi: the vsi being adjusted
2238 * @vid: the vlan id to set as a PVID
2239 **/
dcae29be 2240int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2241{
2242 struct i40e_vsi_context ctxt;
dcae29be 2243 i40e_status aq_ret;
41c445ff
JB		 2244
2245 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2246 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2247 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2248 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2249 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2250
2251 ctxt.seid = vsi->seid;
2252 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2253 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2254 if (aq_ret) {
41c445ff
JB		 2255 dev_info(&vsi->back->pdev->dev,
2256 "%s: update vsi failed, aq_err=%d\n",
2257 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2258 return -ENOENT;
41c445ff
JB		 2259 }
2260
dcae29be 2261 return 0;
41c445ff
JB		 2262}
2263
2264/**
2265 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2266 * @vsi: the vsi being adjusted
2267 *
2268 * Just use the vlan_rx_register() service to put it back to normal
2269 **/
2270void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2271{
6c12fcbf
GR		 2272 i40e_vlan_stripping_disable(vsi);
2273
41c445ff 2274 vsi->info.pvid = 0;
41c445ff
JB		 2275}
2276
2277/**
2278 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2279 * @vsi: ptr to the VSI
2280 *
2281 * If this function returns with an error, then it's possible one or
2282 * more of the rings is populated (while the rest are not). It is the
2283 * callers duty to clean those orphaned rings.
2284 *
2285 * Return 0 on success, negative on failure
2286 **/
2287static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2288{
2289 int i, err = 0;
2290
2291 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2292 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2293
2294 return err;
2295}
2296
2297/**
2298 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2299 * @vsi: ptr to the VSI
2300 *
2301 * Free VSI's transmit software resources
2302 **/
2303static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2304{
2305 int i;
2306
8e9dca53
GR		 2307 if (!vsi->tx_rings)
2308 return;
2309
41c445ff 2310 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2311 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2312 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2313}
2314
2315/**
2316 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2317 * @vsi: ptr to the VSI
2318 *
2319 * If this function returns with an error, then it's possible one or
2320 * more of the rings is populated (while the rest are not). It is the
2321 * callers duty to clean those orphaned rings.
2322 *
2323 * Return 0 on success, negative on failure
2324 **/
2325static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2326{
2327 int i, err = 0;
2328
2329 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2330 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2331#ifdef I40E_FCOE
2332 i40e_fcoe_setup_ddp_resources(vsi);
2333#endif
41c445ff
JB		 2334 return err;
2335}
2336
2337/**
2338 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2339 * @vsi: ptr to the VSI
2340 *
2341 * Free all receive software resources
2342 **/
2343static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2344{
2345 int i;
2346
8e9dca53
GR		 2347 if (!vsi->rx_rings)
2348 return;
2349
41c445ff 2350 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2351 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2352 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2353#ifdef I40E_FCOE
2354 i40e_fcoe_free_ddp_resources(vsi);
2355#endif
41c445ff
JB		 2356}
2357
2358/**
2359 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2360 * @ring: The Tx ring to configure
2361 *
2362 * Configure the Tx descriptor ring in the HMC context.
2363 **/
2364static int i40e_configure_tx_ring(struct i40e_ring *ring)
2365{
2366 struct i40e_vsi *vsi = ring->vsi;
2367 u16 pf_q = vsi->base_queue + ring->queue_index;
2368 struct i40e_hw *hw = &vsi->back->hw;
2369 struct i40e_hmc_obj_txq tx_ctx;
2370 i40e_status err = 0;
2371 u32 qtx_ctl = 0;
2372
2373 /* some ATR related tx ring init */
60ea5f83 2374 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2375 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2376 ring->atr_count = 0;
2377 } else {
2378 ring->atr_sample_rate = 0;
2379 }
2380
2381 /* initialize XPS */
2382 if (ring->q_vector && ring->netdev &&
4e3b35b0 2383 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2384 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2385 netif_set_xps_queue(ring->netdev,
2386 &ring->q_vector->affinity_mask,
2387 ring->queue_index);
2388
2389 /* clear the context structure first */
2390 memset(&tx_ctx, 0, sizeof(tx_ctx));
2391
2392 tx_ctx.new_context = 1;
2393 tx_ctx.base = (ring->dma / 128);
2394 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2395 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2396 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2397#ifdef I40E_FCOE
2398 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2399#endif
beb0dff1 2400 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2401 /* FDIR VSI tx ring can still use RS bit and writebacks */
2402 if (vsi->type != I40E_VSI_FDIR)
2403 tx_ctx.head_wb_ena = 1;
2404 tx_ctx.head_wb_addr = ring->dma +
2405 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2406
2407 /* As part of VSI creation/update, FW allocates certain
2408 * Tx arbitration queue sets for each TC enabled for
2409 * the VSI. The FW returns the handles to these queue
2410 * sets as part of the response buffer to Add VSI,
2411 * Update VSI, etc. AQ commands. It is expected that
2412 * these queue set handles be associated with the Tx
2413 * queues by the driver as part of the TX queue context
2414 * initialization. This has to be done regardless of
2415 * DCB as by default everything is mapped to TC0.
2416 */
2417 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2418 tx_ctx.rdylist_act = 0;
2419
2420 /* clear the context in the HMC */
2421 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2422 if (err) {
2423 dev_info(&vsi->back->pdev->dev,
2424 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2425 ring->queue_index, pf_q, err);
2426 return -ENOMEM;
2427 }
2428
2429 /* set the context in the HMC */
2430 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2431 if (err) {
2432 dev_info(&vsi->back->pdev->dev,
2433 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2434 ring->queue_index, pf_q, err);
2435 return -ENOMEM;
2436 }
2437
2438 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2439 if (vsi->type == I40E_VSI_VMDQ2)
2440 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2441 else
2442 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2443 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2444 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2445 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2446 i40e_flush(hw);
2447
2448 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2449
2450 /* cache tail off for easier writes later */
2451 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2452
2453 return 0;
2454}
2455
2456/**
2457 * i40e_configure_rx_ring - Configure a receive ring context
2458 * @ring: The Rx ring to configure
2459 *
2460 * Configure the Rx descriptor ring in the HMC context.
2461 **/
2462static int i40e_configure_rx_ring(struct i40e_ring *ring)
2463{
2464 struct i40e_vsi *vsi = ring->vsi;
2465 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2466 u16 pf_q = vsi->base_queue + ring->queue_index;
2467 struct i40e_hw *hw = &vsi->back->hw;
2468 struct i40e_hmc_obj_rxq rx_ctx;
2469 i40e_status err = 0;
2470
2471 ring->state = 0;
2472
2473 /* clear the context structure first */
2474 memset(&rx_ctx, 0, sizeof(rx_ctx));
2475
2476 ring->rx_buf_len = vsi->rx_buf_len;
2477 ring->rx_hdr_len = vsi->rx_hdr_len;
2478
2479 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2480 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2481
2482 rx_ctx.base = (ring->dma / 128);
2483 rx_ctx.qlen = ring->count;
2484
2485 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2486 set_ring_16byte_desc_enabled(ring);
2487 rx_ctx.dsize = 0;
2488 } else {
2489 rx_ctx.dsize = 1;
2490 }
2491
2492 rx_ctx.dtype = vsi->dtype;
2493 if (vsi->dtype) {
2494 set_ring_ps_enabled(ring);
2495 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2496 I40E_RX_SPLIT_IP |
2497 I40E_RX_SPLIT_TCP_UDP |
2498 I40E_RX_SPLIT_SCTP;
2499 } else {
2500 rx_ctx.hsplit_0 = 0;
2501 }
2502
2503 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2504 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2505 if (hw->revision_id == 0)
2506 rx_ctx.lrxqthresh = 0;
2507 else
2508 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2509 rx_ctx.crcstrip = 1;
2510 rx_ctx.l2tsel = 1;
2511 rx_ctx.showiv = 1;
38e00438
VD		 2512#ifdef I40E_FCOE
2513 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2514#endif
acb3676b
CS		 2515 /* set the prefena field to 1 because the manual says to */
2516 rx_ctx.prefena = 1;
41c445ff
JB		 2517
2518 /* clear the context in the HMC */
2519 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2520 if (err) {
2521 dev_info(&vsi->back->pdev->dev,
2522 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2523 ring->queue_index, pf_q, err);
2524 return -ENOMEM;
2525 }
2526
2527 /* set the context in the HMC */
2528 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2529 if (err) {
2530 dev_info(&vsi->back->pdev->dev,
2531 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2532 ring->queue_index, pf_q, err);
2533 return -ENOMEM;
2534 }
2535
2536 /* cache tail for quicker writes, and clear the reg before use */
2537 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2538 writel(0, ring->tail);
2539
2540 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2541
2542 return 0;
2543}
2544
2545/**
2546 * i40e_vsi_configure_tx - Configure the VSI for Tx
2547 * @vsi: VSI structure describing this set of rings and resources
2548 *
2549 * Configure the Tx VSI for operation.
2550 **/
2551static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2552{
2553 int err = 0;
2554 u16 i;
2555
9f65e15b
AD		 2556 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2557 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2558
2559 return err;
2560}
2561
2562/**
2563 * i40e_vsi_configure_rx - Configure the VSI for Rx
2564 * @vsi: the VSI being configured
2565 *
2566 * Configure the Rx VSI for operation.
2567 **/
2568static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2569{
2570 int err = 0;
2571 u16 i;
2572
2573 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2574 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2575 + ETH_FCS_LEN + VLAN_HLEN;
2576 else
2577 vsi->max_frame = I40E_RXBUFFER_2048;
2578
2579 /* figure out correct receive buffer length */
2580 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2581 I40E_FLAG_RX_PS_ENABLED)) {
2582 case I40E_FLAG_RX_1BUF_ENABLED:
2583 vsi->rx_hdr_len = 0;
2584 vsi->rx_buf_len = vsi->max_frame;
2585 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2586 break;
2587 case I40E_FLAG_RX_PS_ENABLED:
2588 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2589 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2590 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2591 break;
2592 default:
2593 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2594 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2595 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2596 break;
2597 }
2598
38e00438
VD		 2599#ifdef I40E_FCOE
2600 /* setup rx buffer for FCoE */
2601 if ((vsi->type == I40E_VSI_FCOE) &&
2602 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2603 vsi->rx_hdr_len = 0;
2604 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2605 vsi->max_frame = I40E_RXBUFFER_3072;
2606 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2607 }
2608
2609#endif /* I40E_FCOE */
41c445ff
JB		 2610 /* round up for the chip's needs */
2611 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2612 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2613 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2614 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2615
2616 /* set up individual rings */
2617 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2618 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2619
2620 return err;
2621}
2622
2623/**
2624 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2625 * @vsi: ptr to the VSI
2626 **/
2627static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2628{
e7046ee1 2629 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2630 u16 qoffset, qcount;
2631 int i, n;
2632
2633 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2634 return;
2635
2636 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2637 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2638 continue;
2639
2640 qoffset = vsi->tc_config.tc_info[n].qoffset;
2641 qcount = vsi->tc_config.tc_info[n].qcount;
2642 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2643 rx_ring = vsi->rx_rings[i];
2644 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2645 rx_ring->dcb_tc = n;
2646 tx_ring->dcb_tc = n;
2647 }
2648 }
2649}
2650
2651/**
2652 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2653 * @vsi: ptr to the VSI
2654 **/
2655static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2656{
2657 if (vsi->netdev)
2658 i40e_set_rx_mode(vsi->netdev);
2659}
2660
17a73f6b
JG		 2661/**
2662 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2663 * @vsi: Pointer to the targeted VSI
2664 *
2665 * This function replays the hlist on the hw where all the SB Flow Director
2666 * filters were saved.
2667 **/
2668static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2669{
2670 struct i40e_fdir_filter *filter;
2671 struct i40e_pf *pf = vsi->back;
2672 struct hlist_node *node;
2673
55a5e60b
ASJ		 2674 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2675 return;
2676
17a73f6b
JG		 2677 hlist_for_each_entry_safe(filter, node,
2678 &pf->fdir_filter_list, fdir_node) {
2679 i40e_add_del_fdir(vsi, filter, true);
2680 }
2681}
2682
41c445ff
JB		 2683/**
2684 * i40e_vsi_configure - Set up the VSI for action
2685 * @vsi: the VSI being configured
2686 **/
2687static int i40e_vsi_configure(struct i40e_vsi *vsi)
2688{
2689 int err;
2690
2691 i40e_set_vsi_rx_mode(vsi);
2692 i40e_restore_vlan(vsi);
2693 i40e_vsi_config_dcb_rings(vsi);
2694 err = i40e_vsi_configure_tx(vsi);
2695 if (!err)
2696 err = i40e_vsi_configure_rx(vsi);
2697
2698 return err;
2699}
2700
2701/**
2702 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2703 * @vsi: the VSI being configured
2704 **/
2705static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2706{
2707 struct i40e_pf *pf = vsi->back;
2708 struct i40e_q_vector *q_vector;
2709 struct i40e_hw *hw = &pf->hw;
2710 u16 vector;
2711 int i, q;
2712 u32 val;
2713 u32 qp;
2714
2715 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2716 * and PFINT_LNKLSTn registers, e.g.:
2717 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2718 */
2719 qp = vsi->base_queue;
2720 vector = vsi->base_vector;
493fb300
AD		 2721 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2722 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2723 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2724 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2725 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2726 q_vector->rx.itr);
2727 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2728 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2729 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2730 q_vector->tx.itr);
2731
2732 /* Linked list for the queuepairs assigned to this vector */
2733 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2734 for (q = 0; q < q_vector->num_ringpairs; q++) {
2735 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2736 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2737 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2738 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2739 (I40E_QUEUE_TYPE_TX
2740 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2741
2742 wr32(hw, I40E_QINT_RQCTL(qp), val);
2743
2744 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2745 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2746 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2747 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2748 (I40E_QUEUE_TYPE_RX
2749 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2750
2751 /* Terminate the linked list */
2752 if (q == (q_vector->num_ringpairs - 1))
2753 val |= (I40E_QUEUE_END_OF_LIST
2754 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2755
2756 wr32(hw, I40E_QINT_TQCTL(qp), val);
2757 qp++;
2758 }
2759 }
2760
2761 i40e_flush(hw);
2762}
2763
2764/**
2765 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2766 * @hw: ptr to the hardware info
2767 **/
2768static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2769{
2770 u32 val;
2771
2772 /* clear things first */
2773 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2774 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2775
2776 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2777 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2778 I40E_PFINT_ICR0_ENA_GRST_MASK |
2779 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2780 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2781 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2782 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2783 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2784 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2785
2786 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2787
2788 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2789 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2790 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2791
2792 /* OTHER_ITR_IDX = 0 */
2793 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2794}
2795
2796/**
2797 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2798 * @vsi: the VSI being configured
2799 **/
2800static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2801{
493fb300 2802 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2803 struct i40e_pf *pf = vsi->back;
2804 struct i40e_hw *hw = &pf->hw;
2805 u32 val;
2806
2807 /* set the ITR configuration */
2808 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2809 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2810 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2811 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2812 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2813 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2814
2815 i40e_enable_misc_int_causes(hw);
2816
2817 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2818 wr32(hw, I40E_PFINT_LNKLST0, 0);
2819
f29eaa3d 2820 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2821 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2822 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2823 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2824
2825 wr32(hw, I40E_QINT_RQCTL(0), val);
2826
2827 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2828 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2829 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2830
2831 wr32(hw, I40E_QINT_TQCTL(0), val);
2832 i40e_flush(hw);
2833}
2834
2ef28cfb
MW		 2835/**
2836 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2837 * @pf: board private structure
2838 **/
2839void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2840{
2841 struct i40e_hw *hw = &pf->hw;
2842
2843 wr32(hw, I40E_PFINT_DYN_CTL0,
2844 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2845 i40e_flush(hw);
2846}
2847
41c445ff
JB		 2848/**
2849 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2850 * @pf: board private structure
2851 **/
116a57d4 2852void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2853{
2854 struct i40e_hw *hw = &pf->hw;
2855 u32 val;
2856
2857 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2858 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2859 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2860
2861 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2862 i40e_flush(hw);
2863}
2864
2865/**
2866 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2867 * @vsi: pointer to a vsi
2868 * @vector: enable a particular Hw Interrupt vector
2869 **/
2870void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2871{
2872 struct i40e_pf *pf = vsi->back;
2873 struct i40e_hw *hw = &pf->hw;
2874 u32 val;
2875
2876 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2877 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2878 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2879 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2880 /* skip the flush */
41c445ff
JB		 2881}
2882
5c2cebda
CW		 2883/**
2884 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2885 * @vsi: pointer to a vsi
2886 * @vector: enable a particular Hw Interrupt vector
2887 **/
2888void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2889{
2890 struct i40e_pf *pf = vsi->back;
2891 struct i40e_hw *hw = &pf->hw;
2892 u32 val;
2893
2894 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2895 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2896 i40e_flush(hw);
2897}
2898
41c445ff
JB		 2899/**
2900 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2901 * @irq: interrupt number
2902 * @data: pointer to a q_vector
2903 **/
2904static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2905{
2906 struct i40e_q_vector *q_vector = data;
2907
cd0b6fa6 2908 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2909 return IRQ_HANDLED;
2910
2911 napi_schedule(&q_vector->napi);
2912
2913 return IRQ_HANDLED;
2914}
2915
41c445ff
JB		 2916/**
2917 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2918 * @vsi: the VSI being configured
2919 * @basename: name for the vector
2920 *
2921 * Allocates MSI-X vectors and requests interrupts from the kernel.
2922 **/
2923static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2924{
2925 int q_vectors = vsi->num_q_vectors;
2926 struct i40e_pf *pf = vsi->back;
2927 int base = vsi->base_vector;
2928 int rx_int_idx = 0;
2929 int tx_int_idx = 0;
2930 int vector, err;
2931
2932 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2933 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2934
cd0b6fa6 2935 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2936 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2937 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2938 tx_int_idx++;
cd0b6fa6 2939 } else if (q_vector->rx.ring) {
41c445ff
JB		 2940 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2941 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2942 } else if (q_vector->tx.ring) {
41c445ff
JB		 2943 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2944 "%s-%s-%d", basename, "tx", tx_int_idx++);
2945 } else {
2946 /* skip this unused q_vector */
2947 continue;
2948 }
2949 err = request_irq(pf->msix_entries[base + vector].vector,
2950 vsi->irq_handler,
2951 0,
2952 q_vector->name,
2953 q_vector);
2954 if (err) {
2955 dev_info(&pf->pdev->dev,
2956 "%s: request_irq failed, error: %d\n",
2957 __func__, err);
2958 goto free_queue_irqs;
2959 }
2960 /* assign the mask for this irq */
2961 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2962 &q_vector->affinity_mask);
2963 }
2964
63741846 2965 vsi->irqs_ready = true;
41c445ff
JB		 2966 return 0;
2967
2968free_queue_irqs:
2969 while (vector) {
2970 vector--;
2971 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2972 NULL);
2973 free_irq(pf->msix_entries[base + vector].vector,
2974 &(vsi->q_vectors[vector]));
2975 }
2976 return err;
2977}
2978
2979/**
2980 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2981 * @vsi: the VSI being un-configured
2982 **/
2983static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2984{
2985 struct i40e_pf *pf = vsi->back;
2986 struct i40e_hw *hw = &pf->hw;
2987 int base = vsi->base_vector;
2988 int i;
2989
2990 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2991 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2992 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2993 }
2994
2995 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2996 for (i = vsi->base_vector;
2997 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2998 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2999
3000 i40e_flush(hw);
3001 for (i = 0; i < vsi->num_q_vectors; i++)
3002 synchronize_irq(pf->msix_entries[i + base].vector);
3003 } else {
3004 /* Legacy and MSI mode - this stops all interrupt handling */
3005 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3006 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3007 i40e_flush(hw);
3008 synchronize_irq(pf->pdev->irq);
3009 }
3010}
3011
3012/**
3013 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3014 * @vsi: the VSI being configured
3015 **/
3016static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3017{
3018 struct i40e_pf *pf = vsi->back;
3019 int i;
3020
3021 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3022 for (i = vsi->base_vector;
3023 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3024 i40e_irq_dynamic_enable(vsi, i);
3025 } else {
3026 i40e_irq_dynamic_enable_icr0(pf);
3027 }
3028
1022cb6c 3029 i40e_flush(&pf->hw);
41c445ff
JB		 3030 return 0;
3031}
3032
3033/**
3034 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3035 * @pf: board private structure
3036 **/
3037static void i40e_stop_misc_vector(struct i40e_pf *pf)
3038{
3039 /* Disable ICR 0 */
3040 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3041 i40e_flush(&pf->hw);
3042}
3043
3044/**
3045 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3046 * @irq: interrupt number
3047 * @data: pointer to a q_vector
3048 *
3049 * This is the handler used for all MSI/Legacy interrupts, and deals
3050 * with both queue and non-queue interrupts. This is also used in
3051 * MSIX mode to handle the non-queue interrupts.
3052 **/
3053static irqreturn_t i40e_intr(int irq, void *data)
3054{
3055 struct i40e_pf *pf = (struct i40e_pf *)data;
3056 struct i40e_hw *hw = &pf->hw;
5e823066 3057 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3058 u32 icr0, icr0_remaining;
3059 u32 val, ena_mask;
3060
3061 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3062 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3063
116a57d4
SN		 3064 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3065 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3066 goto enable_intr;
41c445ff 3067
cd92e72f
SN		 3068 /* if interrupt but no bits showing, must be SWINT */
3069 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3070 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3071 pf->sw_int_count++;
3072
41c445ff
JB		 3073 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3074 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3075
3076 /* temporarily disable queue cause for NAPI processing */
3077 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3078 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3079 wr32(hw, I40E_QINT_RQCTL(0), qval);
3080
3081 qval = rd32(hw, I40E_QINT_TQCTL(0));
3082 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3083 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3084
3085 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3086 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3087 }
3088
3089 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3090 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3091 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3092 }
3093
3094 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3095 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3096 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3097 }
3098
3099 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3100 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3101 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3102 }
3103
3104 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3105 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3106 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3107 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3108 val = rd32(hw, I40E_GLGEN_RSTAT);
3109 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3110 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3111 if (val == I40E_RESET_CORER) {
41c445ff 3112 pf->corer_count++;
4eb3f768 3113 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3114 pf->globr_count++;
4eb3f768 3115 } else if (val == I40E_RESET_EMPR) {
41c445ff 3116 pf->empr_count++;
4eb3f768
SN		 3117 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
3118 }
41c445ff
JB		 3119 }
3120
9c010ee0
ASJ		 3121 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3122 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3123 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3124 }
3125
beb0dff1
JK		 3126 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3127 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3128
3129 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3130 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3131 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3132 }
beb0dff1
JK		 3133 }
3134
41c445ff
JB		 3135 /* If a critical error is pending we have no choice but to reset the
3136 * device.
3137 * Report and mask out any remaining unexpected interrupts.
3138 */
3139 icr0_remaining = icr0 & ena_mask;
3140 if (icr0_remaining) {
3141 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3142 icr0_remaining);
9c010ee0 3143 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3144 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3145 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3146 dev_info(&pf->pdev->dev, "device will be reset\n");
3147 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3148 i40e_service_event_schedule(pf);
41c445ff
JB		 3149 }
3150 ena_mask &= ~icr0_remaining;
3151 }
5e823066 3152 ret = IRQ_HANDLED;
41c445ff 3153
5e823066 3154enable_intr:
41c445ff
JB		 3155 /* re-enable interrupt causes */
3156 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3157 if (!test_bit(__I40E_DOWN, &pf->state)) {
3158 i40e_service_event_schedule(pf);
3159 i40e_irq_dynamic_enable_icr0(pf);
3160 }
3161
5e823066 3162 return ret;
41c445ff
JB		 3163}
3164
cbf61325
ASJ		 3165/**
3166 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3167 * @tx_ring: tx ring to clean
3168 * @budget: how many cleans we're allowed
3169 *
3170 * Returns true if there's any budget left (e.g. the clean is finished)
3171 **/
3172static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3173{
3174 struct i40e_vsi *vsi = tx_ring->vsi;
3175 u16 i = tx_ring->next_to_clean;
3176 struct i40e_tx_buffer *tx_buf;
3177 struct i40e_tx_desc *tx_desc;
3178
3179 tx_buf = &tx_ring->tx_bi[i];
3180 tx_desc = I40E_TX_DESC(tx_ring, i);
3181 i -= tx_ring->count;
3182
3183 do {
3184 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3185
3186 /* if next_to_watch is not set then there is no work pending */
3187 if (!eop_desc)
3188 break;
3189
3190 /* prevent any other reads prior to eop_desc */
3191 read_barrier_depends();
3192
3193 /* if the descriptor isn't done, no work yet to do */
3194 if (!(eop_desc->cmd_type_offset_bsz &
3195 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3196 break;
3197
3198 /* clear next_to_watch to prevent false hangs */
3199 tx_buf->next_to_watch = NULL;
3200
49d7d933
ASJ		 3201 tx_desc->buffer_addr = 0;
3202 tx_desc->cmd_type_offset_bsz = 0;
3203 /* move past filter desc */
3204 tx_buf++;
3205 tx_desc++;
3206 i++;
3207 if (unlikely(!i)) {
3208 i -= tx_ring->count;
3209 tx_buf = tx_ring->tx_bi;
3210 tx_desc = I40E_TX_DESC(tx_ring, 0);
3211 }
cbf61325
ASJ		 3212 /* unmap skb header data */
3213 dma_unmap_single(tx_ring->dev,
3214 dma_unmap_addr(tx_buf, dma),
3215 dma_unmap_len(tx_buf, len),
3216 DMA_TO_DEVICE);
49d7d933
ASJ		 3217 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3218 kfree(tx_buf->raw_buf);
cbf61325 3219
49d7d933
ASJ		 3220 tx_buf->raw_buf = NULL;
3221 tx_buf->tx_flags = 0;
3222 tx_buf->next_to_watch = NULL;
cbf61325 3223 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3224 tx_desc->buffer_addr = 0;
3225 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3226
49d7d933 3227 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3228 tx_buf++;
3229 tx_desc++;
3230 i++;
3231 if (unlikely(!i)) {
3232 i -= tx_ring->count;
3233 tx_buf = tx_ring->tx_bi;
3234 tx_desc = I40E_TX_DESC(tx_ring, 0);
3235 }
3236
3237 /* update budget accounting */
3238 budget--;
3239 } while (likely(budget));
3240
3241 i += tx_ring->count;
3242 tx_ring->next_to_clean = i;
3243
3244 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3245 i40e_irq_dynamic_enable(vsi,
3246 tx_ring->q_vector->v_idx + vsi->base_vector);
3247 }
3248 return budget > 0;
3249}
3250
3251/**
3252 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3253 * @irq: interrupt number
3254 * @data: pointer to a q_vector
3255 **/
3256static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3257{
3258 struct i40e_q_vector *q_vector = data;
3259 struct i40e_vsi *vsi;
3260
3261 if (!q_vector->tx.ring)
3262 return IRQ_HANDLED;
3263
3264 vsi = q_vector->tx.ring->vsi;
3265 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3266
3267 return IRQ_HANDLED;
3268}
3269
41c445ff 3270/**
cd0b6fa6 3271 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3272 * @vsi: the VSI being configured
3273 * @v_idx: vector index
cd0b6fa6 3274 * @qp_idx: queue pair index
41c445ff 3275 **/
cd0b6fa6 3276static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3277{
493fb300 3278 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3279 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3280 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3281
3282 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3283 tx_ring->next = q_vector->tx.ring;
3284 q_vector->tx.ring = tx_ring;
41c445ff 3285 q_vector->tx.count++;
cd0b6fa6
AD		 3286
3287 rx_ring->q_vector = q_vector;
3288 rx_ring->next = q_vector->rx.ring;
3289 q_vector->rx.ring = rx_ring;
3290 q_vector->rx.count++;
41c445ff
JB		 3291}
3292
3293/**
3294 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3295 * @vsi: the VSI being configured
3296 *
3297 * This function maps descriptor rings to the queue-specific vectors
3298 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3299 * one vector per queue pair, but on a constrained vector budget, we
3300 * group the queue pairs as "efficiently" as possible.
3301 **/
3302static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3303{
3304 int qp_remaining = vsi->num_queue_pairs;
3305 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3306 int num_ringpairs;
41c445ff
JB		 3307 int v_start = 0;
3308 int qp_idx = 0;
3309
3310 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3311 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3312 * It is also important to go through all the vectors available to be
3313 * sure that if we don't use all the vectors, that the remaining vectors
3314 * are cleared. This is especially important when decreasing the
3315 * number of queues in use.
41c445ff 3316 */
70114ec4 3317 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3318 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3319
3320 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3321
3322 q_vector->num_ringpairs = num_ringpairs;
3323
3324 q_vector->rx.count = 0;
3325 q_vector->tx.count = 0;
3326 q_vector->rx.ring = NULL;
3327 q_vector->tx.ring = NULL;
3328
3329 while (num_ringpairs--) {
3330 map_vector_to_qp(vsi, v_start, qp_idx);
3331 qp_idx++;
3332 qp_remaining--;
41c445ff
JB		 3333 }
3334 }
3335}
3336
3337/**
3338 * i40e_vsi_request_irq - Request IRQ from the OS
3339 * @vsi: the VSI being configured
3340 * @basename: name for the vector
3341 **/
3342static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3343{
3344 struct i40e_pf *pf = vsi->back;
3345 int err;
3346
3347 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3348 err = i40e_vsi_request_irq_msix(vsi, basename);
3349 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3350 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3351 pf->misc_int_name, pf);
3352 else
3353 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3354 pf->misc_int_name, pf);
3355
3356 if (err)
3357 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3358
3359 return err;
3360}
3361
3362#ifdef CONFIG_NET_POLL_CONTROLLER
3363/**
3364 * i40e_netpoll - A Polling 'interrupt'handler
3365 * @netdev: network interface device structure
3366 *
3367 * This is used by netconsole to send skbs without having to re-enable
3368 * interrupts. It's not called while the normal interrupt routine is executing.
3369 **/
38e00438
VD		 3370#ifdef I40E_FCOE
3371void i40e_netpoll(struct net_device *netdev)
3372#else
41c445ff 3373static void i40e_netpoll(struct net_device *netdev)
38e00438 3374#endif
41c445ff
JB		 3375{
3376 struct i40e_netdev_priv *np = netdev_priv(netdev);
3377 struct i40e_vsi *vsi = np->vsi;
3378 struct i40e_pf *pf = vsi->back;
3379 int i;
3380
3381 /* if interface is down do nothing */
3382 if (test_bit(__I40E_DOWN, &vsi->state))
3383 return;
3384
3385 pf->flags |= I40E_FLAG_IN_NETPOLL;
3386 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3387 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3388 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3389 } else {
3390 i40e_intr(pf->pdev->irq, netdev);
3391 }
3392 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3393}
3394#endif
3395
23527308
NP		 3396/**
3397 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3398 * @pf: the PF being configured
3399 * @pf_q: the PF queue
3400 * @enable: enable or disable state of the queue
3401 *
3402 * This routine will wait for the given Tx queue of the PF to reach the
3403 * enabled or disabled state.
3404 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3405 * multiple retries; else will return 0 in case of success.
3406 **/
3407static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3408{
3409 int i;
3410 u32 tx_reg;
3411
3412 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3413 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3414 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3415 break;
3416
3417 udelay(10);
3418 }
3419 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3420 return -ETIMEDOUT;
3421
3422 return 0;
3423}
3424
41c445ff
JB		 3425/**
3426 * i40e_vsi_control_tx - Start or stop a VSI's rings
3427 * @vsi: the VSI being configured
3428 * @enable: start or stop the rings
3429 **/
3430static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3431{
3432 struct i40e_pf *pf = vsi->back;
3433 struct i40e_hw *hw = &pf->hw;
23527308 3434 int i, j, pf_q, ret = 0;
41c445ff
JB		 3435 u32 tx_reg;
3436
3437 pf_q = vsi->base_queue;
3438 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3439
3440 /* warn the TX unit of coming changes */
3441 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3442 if (!enable)
3443 udelay(10);
3444
6c5ef620 3445 for (j = 0; j < 50; j++) {
41c445ff 3446 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3447 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3448 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3449 break;
3450 usleep_range(1000, 2000);
3451 }
fda972f6 3452 /* Skip if the queue is already in the requested state */
7c122007 3453 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3454 continue;
41c445ff
JB		 3455
3456 /* turn on/off the queue */
c5c9eb9e
SN		 3457 if (enable) {
3458 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3459 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3460 } else {
41c445ff 3461 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3462 }
41c445ff
JB		 3463
3464 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3465
3466 /* wait for the change to finish */
23527308
NP		 3467 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3468 if (ret) {
3469 dev_info(&pf->pdev->dev,
3470 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3471 __func__, vsi->seid, pf_q,
3472 (enable ? "en" : "dis"));
3473 break;
41c445ff
JB		 3474 }
3475 }
3476
7134f9ce
JB		 3477 if (hw->revision_id == 0)
3478 mdelay(50);
23527308
NP		 3479 return ret;
3480}
3481
3482/**
3483 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3484 * @pf: the PF being configured
3485 * @pf_q: the PF queue
3486 * @enable: enable or disable state of the queue
3487 *
3488 * This routine will wait for the given Rx queue of the PF to reach the
3489 * enabled or disabled state.
3490 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3491 * multiple retries; else will return 0 in case of success.
3492 **/
3493static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3494{
3495 int i;
3496 u32 rx_reg;
3497
3498 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3499 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3500 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3501 break;
3502
3503 udelay(10);
3504 }
3505 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3506 return -ETIMEDOUT;
7134f9ce 3507
41c445ff
JB		 3508 return 0;
3509}
3510
3511/**
3512 * i40e_vsi_control_rx - Start or stop a VSI's rings
3513 * @vsi: the VSI being configured
3514 * @enable: start or stop the rings
3515 **/
3516static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3517{
3518 struct i40e_pf *pf = vsi->back;
3519 struct i40e_hw *hw = &pf->hw;
23527308 3520 int i, j, pf_q, ret = 0;
41c445ff
JB		 3521 u32 rx_reg;
3522
3523 pf_q = vsi->base_queue;
3524 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3525 for (j = 0; j < 50; j++) {
41c445ff 3526 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3527 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3528 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3529 break;
3530 usleep_range(1000, 2000);
3531 }
41c445ff 3532
7c122007
CS		 3533 /* Skip if the queue is already in the requested state */
3534 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3535 continue;
41c445ff
JB		 3536
3537 /* turn on/off the queue */
3538 if (enable)
6c5ef620 3539 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3540 else
6c5ef620 3541 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3542 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3543
3544 /* wait for the change to finish */
23527308
NP		 3545 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3546 if (ret) {
3547 dev_info(&pf->pdev->dev,
3548 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3549 __func__, vsi->seid, pf_q,
3550 (enable ? "en" : "dis"));
3551 break;
41c445ff
JB		 3552 }
3553 }
3554
23527308 3555 return ret;
41c445ff
JB		 3556}
3557
3558/**
3559 * i40e_vsi_control_rings - Start or stop a VSI's rings
3560 * @vsi: the VSI being configured
3561 * @enable: start or stop the rings
3562 **/
fc18eaa0 3563int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3564{
3b867b28 3565 int ret = 0;
41c445ff
JB		 3566
3567 /* do rx first for enable and last for disable */
3568 if (request) {
3569 ret = i40e_vsi_control_rx(vsi, request);
3570 if (ret)
3571 return ret;
3572 ret = i40e_vsi_control_tx(vsi, request);
3573 } else {
3b867b28
ASJ		 3574 /* Ignore return value, we need to shutdown whatever we can */
3575 i40e_vsi_control_tx(vsi, request);
3576 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3577 }
3578
3579 return ret;
3580}
3581
3582/**
3583 * i40e_vsi_free_irq - Free the irq association with the OS
3584 * @vsi: the VSI being configured
3585 **/
3586static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3587{
3588 struct i40e_pf *pf = vsi->back;
3589 struct i40e_hw *hw = &pf->hw;
3590 int base = vsi->base_vector;
3591 u32 val, qp;
3592 int i;
3593
3594 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3595 if (!vsi->q_vectors)
3596 return;
3597
63741846
SN		 3598 if (!vsi->irqs_ready)
3599 return;
3600
3601 vsi->irqs_ready = false;
41c445ff
JB		 3602 for (i = 0; i < vsi->num_q_vectors; i++) {
3603 u16 vector = i + base;
3604
3605 /* free only the irqs that were actually requested */
78681b1f
SN		 3606 if (!vsi->q_vectors[i] ||
3607 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3608 continue;
3609
3610 /* clear the affinity_mask in the IRQ descriptor */
3611 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3612 NULL);
3613 free_irq(pf->msix_entries[vector].vector,
493fb300 3614 vsi->q_vectors[i]);
41c445ff
JB		 3615
3616 /* Tear down the interrupt queue link list
3617 *
3618 * We know that they come in pairs and always
3619 * the Rx first, then the Tx. To clear the
3620 * link list, stick the EOL value into the
3621 * next_q field of the registers.
3622 */
3623 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3624 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3625 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3626 val |= I40E_QUEUE_END_OF_LIST
3627 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3628 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3629
3630 while (qp != I40E_QUEUE_END_OF_LIST) {
3631 u32 next;
3632
3633 val = rd32(hw, I40E_QINT_RQCTL(qp));
3634
3635 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3636 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3637 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3638 I40E_QINT_RQCTL_INTEVENT_MASK);
3639
3640 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3641 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3642
3643 wr32(hw, I40E_QINT_RQCTL(qp), val);
3644
3645 val = rd32(hw, I40E_QINT_TQCTL(qp));
3646
3647 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3648 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3649
3650 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3651 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3652 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3653 I40E_QINT_TQCTL_INTEVENT_MASK);
3654
3655 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3656 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3657
3658 wr32(hw, I40E_QINT_TQCTL(qp), val);
3659 qp = next;
3660 }
3661 }
3662 } else {
3663 free_irq(pf->pdev->irq, pf);
3664
3665 val = rd32(hw, I40E_PFINT_LNKLST0);
3666 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3667 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3668 val |= I40E_QUEUE_END_OF_LIST
3669 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3670 wr32(hw, I40E_PFINT_LNKLST0, val);
3671
3672 val = rd32(hw, I40E_QINT_RQCTL(qp));
3673 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3674 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3675 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3676 I40E_QINT_RQCTL_INTEVENT_MASK);
3677
3678 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3679 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3680
3681 wr32(hw, I40E_QINT_RQCTL(qp), val);
3682
3683 val = rd32(hw, I40E_QINT_TQCTL(qp));
3684
3685 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3686 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3687 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3688 I40E_QINT_TQCTL_INTEVENT_MASK);
3689
3690 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3691 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3692
3693 wr32(hw, I40E_QINT_TQCTL(qp), val);
3694 }
3695}
3696
493fb300
AD		 3697/**
3698 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3699 * @vsi: the VSI being configured
3700 * @v_idx: Index of vector to be freed
3701 *
3702 * This function frees the memory allocated to the q_vector. In addition if
3703 * NAPI is enabled it will delete any references to the NAPI struct prior
3704 * to freeing the q_vector.
3705 **/
3706static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3707{
3708 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3709 struct i40e_ring *ring;
493fb300
AD		 3710
3711 if (!q_vector)
3712 return;
3713
3714 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3715 i40e_for_each_ring(ring, q_vector->tx)
3716 ring->q_vector = NULL;
3717
3718 i40e_for_each_ring(ring, q_vector->rx)
3719 ring->q_vector = NULL;
493fb300
AD		 3720
3721 /* only VSI w/ an associated netdev is set up w/ NAPI */
3722 if (vsi->netdev)
3723 netif_napi_del(&q_vector->napi);
3724
3725 vsi->q_vectors[v_idx] = NULL;
3726
3727 kfree_rcu(q_vector, rcu);
3728}
3729
41c445ff
JB		 3730/**
3731 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3732 * @vsi: the VSI being un-configured
3733 *
3734 * This frees the memory allocated to the q_vectors and
3735 * deletes references to the NAPI struct.
3736 **/
3737static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3738{
3739 int v_idx;
3740
493fb300
AD		 3741 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3742 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3743}
3744
3745/**
3746 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3747 * @pf: board private structure
3748 **/
3749static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3750{
3751 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3752 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3753 pci_disable_msix(pf->pdev);
3754 kfree(pf->msix_entries);
3755 pf->msix_entries = NULL;
3756 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3757 pci_disable_msi(pf->pdev);
3758 }
3759 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3760}
3761
3762/**
3763 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3764 * @pf: board private structure
3765 *
3766 * We go through and clear interrupt specific resources and reset the structure
3767 * to pre-load conditions
3768 **/
3769static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3770{
3771 int i;
3772
3773 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3774 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3775 if (pf->vsi[i])
3776 i40e_vsi_free_q_vectors(pf->vsi[i]);
3777 i40e_reset_interrupt_capability(pf);
3778}
3779
3780/**
3781 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3782 * @vsi: the VSI being configured
3783 **/
3784static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3785{
3786 int q_idx;
3787
3788 if (!vsi->netdev)
3789 return;
3790
3791 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3792 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3793}
3794
3795/**
3796 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3797 * @vsi: the VSI being configured
3798 **/
3799static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3800{
3801 int q_idx;
3802
3803 if (!vsi->netdev)
3804 return;
3805
3806 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3807 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3808}
3809
90ef8d47
SN		 3810/**
3811 * i40e_vsi_close - Shut down a VSI
3812 * @vsi: the vsi to be quelled
3813 **/
3814static void i40e_vsi_close(struct i40e_vsi *vsi)
3815{
3816 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3817 i40e_down(vsi);
3818 i40e_vsi_free_irq(vsi);
3819 i40e_vsi_free_tx_resources(vsi);
3820 i40e_vsi_free_rx_resources(vsi);
3821}
3822
41c445ff
JB		 3823/**
3824 * i40e_quiesce_vsi - Pause a given VSI
3825 * @vsi: the VSI being paused
3826 **/
3827static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3828{
3829 if (test_bit(__I40E_DOWN, &vsi->state))
3830 return;
3831
3832 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3833 if (vsi->netdev && netif_running(vsi->netdev)) {
3834 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3835 } else {
90ef8d47 3836 i40e_vsi_close(vsi);
41c445ff
JB		 3837 }
3838}
3839
3840/**
3841 * i40e_unquiesce_vsi - Resume a given VSI
3842 * @vsi: the VSI being resumed
3843 **/
3844static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3845{
3846 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3847 return;
3848
3849 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3850 if (vsi->netdev && netif_running(vsi->netdev))
3851 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3852 else
8276f757 3853 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3854}
3855
3856/**
3857 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3858 * @pf: the PF
3859 **/
3860static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3861{
3862 int v;
3863
505682cd 3864 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3865 if (pf->vsi[v])
3866 i40e_quiesce_vsi(pf->vsi[v]);
3867 }
3868}
3869
3870/**
3871 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3872 * @pf: the PF
3873 **/
3874static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3875{
3876 int v;
3877
505682cd 3878 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3879 if (pf->vsi[v])
3880 i40e_unquiesce_vsi(pf->vsi[v]);
3881 }
3882}
3883
3884/**
3885 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3886 * @dcbcfg: the corresponding DCBx configuration structure
3887 *
3888 * Return the number of TCs from given DCBx configuration
3889 **/
3890static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3891{
078b5876
JB		 3892 u8 num_tc = 0;
3893 int i;
41c445ff
JB		 3894
3895 /* Scan the ETS Config Priority Table to find
3896 * traffic class enabled for a given priority
3897 * and use the traffic class index to get the
3898 * number of traffic classes enabled
3899 */
3900 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3901 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3902 num_tc = dcbcfg->etscfg.prioritytable[i];
3903 }
3904
3905 /* Traffic class index starts from zero so
3906 * increment to return the actual count
3907 */
078b5876 3908 return num_tc + 1;
41c445ff
JB		 3909}
3910
3911/**
3912 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3913 * @dcbcfg: the corresponding DCBx configuration structure
3914 *
3915 * Query the current DCB configuration and return the number of
3916 * traffic classes enabled from the given DCBX config
3917 **/
3918static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3919{
3920 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3921 u8 enabled_tc = 1;
3922 u8 i;
3923
3924 for (i = 0; i < num_tc; i++)
3925 enabled_tc |= 1 << i;
3926
3927 return enabled_tc;
3928}
3929
3930/**
3931 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3932 * @pf: PF being queried
3933 *
3934 * Return number of traffic classes enabled for the given PF
3935 **/
3936static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3937{
3938 struct i40e_hw *hw = &pf->hw;
3939 u8 i, enabled_tc;
3940 u8 num_tc = 0;
3941 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3942
3943 /* If DCB is not enabled then always in single TC */
3944 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3945 return 1;
3946
3947 /* MFP mode return count of enabled TCs for this PF */
3948 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3949 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3950 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3951 if (enabled_tc & (1 << i))
3952 num_tc++;
3953 }
3954 return num_tc;
3955 }
3956
3957 /* SFP mode will be enabled for all TCs on port */
3958 return i40e_dcb_get_num_tc(dcbcfg);
3959}
3960
3961/**
3962 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3963 * @pf: PF being queried
3964 *
3965 * Return a bitmap for first enabled traffic class for this PF.
3966 **/
3967static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3968{
3969 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3970 u8 i = 0;
3971
3972 if (!enabled_tc)
3973 return 0x1; /* TC0 */
3974
3975 /* Find the first enabled TC */
3976 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3977 if (enabled_tc & (1 << i))
3978 break;
3979 }
3980
3981 return 1 << i;
3982}
3983
3984/**
3985 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3986 * @pf: PF being queried
3987 *
3988 * Return a bitmap for enabled traffic classes for this PF.
3989 **/
3990static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3991{
3992 /* If DCB is not enabled for this PF then just return default TC */
3993 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3994 return i40e_pf_get_default_tc(pf);
3995
3996 /* MFP mode will have enabled TCs set by FW */
3997 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3998 return pf->hw.func_caps.enabled_tcmap;
3999
4000 /* SFP mode we want PF to be enabled for all TCs */
4001 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4002}
4003
4004/**
4005 * i40e_vsi_get_bw_info - Query VSI BW Information
4006 * @vsi: the VSI being queried
4007 *
4008 * Returns 0 on success, negative value on failure
4009 **/
4010static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4011{
4012 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4013 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4014 struct i40e_pf *pf = vsi->back;
4015 struct i40e_hw *hw = &pf->hw;
dcae29be 4016 i40e_status aq_ret;
41c445ff 4017 u32 tc_bw_max;
41c445ff
JB		 4018 int i;
4019
4020 /* Get the VSI level BW configuration */
dcae29be
JB		 4021 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4022 if (aq_ret) {
41c445ff
JB		 4023 dev_info(&pf->pdev->dev,
4024 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4025 aq_ret, pf->hw.aq.asq_last_status);
4026 return -EINVAL;
41c445ff
JB		 4027 }
4028
4029 /* Get the VSI level BW configuration per TC */
dcae29be 4030 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4031 NULL);
dcae29be 4032 if (aq_ret) {
41c445ff
JB		 4033 dev_info(&pf->pdev->dev,
4034 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4035 aq_ret, pf->hw.aq.asq_last_status);
4036 return -EINVAL;
41c445ff
JB		 4037 }
4038
4039 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4040 dev_info(&pf->pdev->dev,
4041 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4042 bw_config.tc_valid_bits,
4043 bw_ets_config.tc_valid_bits);
4044 /* Still continuing */
4045 }
4046
4047 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4048 vsi->bw_max_quanta = bw_config.max_bw;
4049 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4050 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4051 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4052 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4053 vsi->bw_ets_limit_credits[i] =
4054 le16_to_cpu(bw_ets_config.credits[i]);
4055 /* 3 bits out of 4 for each TC */
4056 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4057 }
078b5876 4058
dcae29be 4059 return 0;
41c445ff
JB		 4060}
4061
4062/**
4063 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4064 * @vsi: the VSI being configured
4065 * @enabled_tc: TC bitmap
4066 * @bw_credits: BW shared credits per TC
4067 *
4068 * Returns 0 on success, negative value on failure
4069 **/
dcae29be 4070static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4071 u8 *bw_share)
4072{
4073 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4074 i40e_status aq_ret;
4075 int i;
41c445ff
JB		 4076
4077 bw_data.tc_valid_bits = enabled_tc;
4078 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4079 bw_data.tc_bw_credits[i] = bw_share[i];
4080
dcae29be
JB		 4081 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4082 NULL);
4083 if (aq_ret) {
41c445ff 4084 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4085 "AQ command Config VSI BW allocation per TC failed = %d\n",
4086 vsi->back->hw.aq.asq_last_status);
dcae29be 4087 return -EINVAL;
41c445ff
JB		 4088 }
4089
4090 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4091 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4092
dcae29be 4093 return 0;
41c445ff
JB		 4094}
4095
4096/**
4097 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4098 * @vsi: the VSI being configured
4099 * @enabled_tc: TC map to be enabled
4100 *
4101 **/
4102static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4103{
4104 struct net_device *netdev = vsi->netdev;
4105 struct i40e_pf *pf = vsi->back;
4106 struct i40e_hw *hw = &pf->hw;
4107 u8 netdev_tc = 0;
4108 int i;
4109 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4110
4111 if (!netdev)
4112 return;
4113
4114 if (!enabled_tc) {
4115 netdev_reset_tc(netdev);
4116 return;
4117 }
4118
4119 /* Set up actual enabled TCs on the VSI */
4120 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4121 return;
4122
4123 /* set per TC queues for the VSI */
4124 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4125 /* Only set TC queues for enabled tcs
4126 *
4127 * e.g. For a VSI that has TC0 and TC3 enabled the
4128 * enabled_tc bitmap would be 0x00001001; the driver
4129 * will set the numtc for netdev as 2 that will be
4130 * referenced by the netdev layer as TC 0 and 1.
4131 */
4132 if (vsi->tc_config.enabled_tc & (1 << i))
4133 netdev_set_tc_queue(netdev,
4134 vsi->tc_config.tc_info[i].netdev_tc,
4135 vsi->tc_config.tc_info[i].qcount,
4136 vsi->tc_config.tc_info[i].qoffset);
4137 }
4138
4139 /* Assign UP2TC map for the VSI */
4140 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4141 /* Get the actual TC# for the UP */
4142 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4143 /* Get the mapped netdev TC# for the UP */
4144 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4145 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4146 }
4147}
4148
4149/**
4150 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4151 * @vsi: the VSI being configured
4152 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4153 **/
4154static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4155 struct i40e_vsi_context *ctxt)
4156{
4157 /* copy just the sections touched not the entire info
4158 * since not all sections are valid as returned by
4159 * update vsi params
4160 */
4161 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4162 memcpy(&vsi->info.queue_mapping,
4163 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4164 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4165 sizeof(vsi->info.tc_mapping));
4166}
4167
4168/**
4169 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4170 * @vsi: VSI to be configured
4171 * @enabled_tc: TC bitmap
4172 *
4173 * This configures a particular VSI for TCs that are mapped to the
4174 * given TC bitmap. It uses default bandwidth share for TCs across
4175 * VSIs to configure TC for a particular VSI.
4176 *
4177 * NOTE:
4178 * It is expected that the VSI queues have been quisced before calling
4179 * this function.
4180 **/
4181static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4182{
4183 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4184 struct i40e_vsi_context ctxt;
4185 int ret = 0;
4186 int i;
4187
4188 /* Check if enabled_tc is same as existing or new TCs */
4189 if (vsi->tc_config.enabled_tc == enabled_tc)
4190 return ret;
4191
4192 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4193 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4194 if (enabled_tc & (1 << i))
4195 bw_share[i] = 1;
4196 }
4197
4198 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4199 if (ret) {
4200 dev_info(&vsi->back->pdev->dev,
4201 "Failed configuring TC map %d for VSI %d\n",
4202 enabled_tc, vsi->seid);
4203 goto out;
4204 }
4205
4206 /* Update Queue Pairs Mapping for currently enabled UPs */
4207 ctxt.seid = vsi->seid;
4208 ctxt.pf_num = vsi->back->hw.pf_id;
4209 ctxt.vf_num = 0;
4210 ctxt.uplink_seid = vsi->uplink_seid;
4211 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4212 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4213
4214 /* Update the VSI after updating the VSI queue-mapping information */
4215 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4216 if (ret) {
4217 dev_info(&vsi->back->pdev->dev,
4218 "update vsi failed, aq_err=%d\n",
4219 vsi->back->hw.aq.asq_last_status);
4220 goto out;
4221 }
4222 /* update the local VSI info with updated queue map */
4223 i40e_vsi_update_queue_map(vsi, &ctxt);
4224 vsi->info.valid_sections = 0;
4225
4226 /* Update current VSI BW information */
4227 ret = i40e_vsi_get_bw_info(vsi);
4228 if (ret) {
4229 dev_info(&vsi->back->pdev->dev,
4230 "Failed updating vsi bw info, aq_err=%d\n",
4231 vsi->back->hw.aq.asq_last_status);
4232 goto out;
4233 }
4234
4235 /* Update the netdev TC setup */
4236 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4237out:
4238 return ret;
4239}
4240
4e3b35b0
NP		 4241/**
4242 * i40e_veb_config_tc - Configure TCs for given VEB
4243 * @veb: given VEB
4244 * @enabled_tc: TC bitmap
4245 *
4246 * Configures given TC bitmap for VEB (switching) element
4247 **/
4248int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4249{
4250 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4251 struct i40e_pf *pf = veb->pf;
4252 int ret = 0;
4253 int i;
4254
4255 /* No TCs or already enabled TCs just return */
4256 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4257 return ret;
4258
4259 bw_data.tc_valid_bits = enabled_tc;
4260 /* bw_data.absolute_credits is not set (relative) */
4261
4262 /* Enable ETS TCs with equal BW Share for now */
4263 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4264 if (enabled_tc & (1 << i))
4265 bw_data.tc_bw_share_credits[i] = 1;
4266 }
4267
4268 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4269 &bw_data, NULL);
4270 if (ret) {
4271 dev_info(&pf->pdev->dev,
4272 "veb bw config failed, aq_err=%d\n",
4273 pf->hw.aq.asq_last_status);
4274 goto out;
4275 }
4276
4277 /* Update the BW information */
4278 ret = i40e_veb_get_bw_info(veb);
4279 if (ret) {
4280 dev_info(&pf->pdev->dev,
4281 "Failed getting veb bw config, aq_err=%d\n",
4282 pf->hw.aq.asq_last_status);
4283 }
4284
4285out:
4286 return ret;
4287}
4288
4289#ifdef CONFIG_I40E_DCB
4290/**
4291 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4292 * @pf: PF struct
4293 *
4294 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4295 * the caller would've quiesce all the VSIs before calling
4296 * this function
4297 **/
4298static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4299{
4300 u8 tc_map = 0;
4301 int ret;
4302 u8 v;
4303
4304 /* Enable the TCs available on PF to all VEBs */
4305 tc_map = i40e_pf_get_tc_map(pf);
4306 for (v = 0; v < I40E_MAX_VEB; v++) {
4307 if (!pf->veb[v])
4308 continue;
4309 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4310 if (ret) {
4311 dev_info(&pf->pdev->dev,
4312 "Failed configuring TC for VEB seid=%d\n",
4313 pf->veb[v]->seid);
4314 /* Will try to configure as many components */
4315 }
4316 }
4317
4318 /* Update each VSI */
505682cd 4319 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4320 if (!pf->vsi[v])
4321 continue;
4322
4323 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4324#ifdef I40E_FCOE
4325 * - For FCoE VSI only enable the TC configured
4326 * as per the APP TLV
4327#endif
4e3b35b0
NP		 4328 * - For all others keep them at TC0 for now
4329 */
4330 if (v == pf->lan_vsi)
4331 tc_map = i40e_pf_get_tc_map(pf);
4332 else
4333 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4334#ifdef I40E_FCOE
4335 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4336 tc_map = i40e_get_fcoe_tc_map(pf);
4337#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4338
4339 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4340 if (ret) {
4341 dev_info(&pf->pdev->dev,
4342 "Failed configuring TC for VSI seid=%d\n",
4343 pf->vsi[v]->seid);
4344 /* Will try to configure as many components */
4345 } else {
0672a091
NP		 4346 /* Re-configure VSI vectors based on updated TC map */
4347 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4348 if (pf->vsi[v]->netdev)
4349 i40e_dcbnl_set_all(pf->vsi[v]);
4350 }
4351 }
4352}
4353
4354/**
4355 * i40e_init_pf_dcb - Initialize DCB configuration
4356 * @pf: PF being configured
4357 *
4358 * Query the current DCB configuration and cache it
4359 * in the hardware structure
4360 **/
4361static int i40e_init_pf_dcb(struct i40e_pf *pf)
4362{
4363 struct i40e_hw *hw = &pf->hw;
4364 int err = 0;
4365
4366 if (pf->hw.func_caps.npar_enable)
4367 goto out;
4368
4369 /* Get the initial DCB configuration */
4370 err = i40e_init_dcb(hw);
4371 if (!err) {
4372 /* Device/Function is not DCBX capable */
4373 if ((!hw->func_caps.dcb) ||
4374 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4375 dev_info(&pf->pdev->dev,
4376 "DCBX offload is not supported or is disabled for this PF.\n");
4377
4378 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4379 goto out;
4380
4381 } else {
4382 /* When status is not DISABLED then DCBX in FW */
4383 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4384 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4385
4386 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4387 /* Enable DCB tagging only when more than one TC */
4388 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4389 pf->flags |= I40E_FLAG_DCB_ENABLED;
4e3b35b0 4390 }
014269ff
NP		 4391 } else {
4392 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4393 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4394 }
4395
4396out:
4397 return err;
4398}
4399#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4400#define SPEED_SIZE 14
4401#define FC_SIZE 8
4402/**
4403 * i40e_print_link_message - print link up or down
4404 * @vsi: the VSI for which link needs a message
4405 */
4406static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4407{
4408 char speed[SPEED_SIZE] = "Unknown";
4409 char fc[FC_SIZE] = "RX/TX";
4410
4411 if (!isup) {
4412 netdev_info(vsi->netdev, "NIC Link is Down\n");
4413 return;
4414 }
4415
4416 switch (vsi->back->hw.phy.link_info.link_speed) {
4417 case I40E_LINK_SPEED_40GB:
35a7d804 4418 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08
JB		 4419 break;
4420 case I40E_LINK_SPEED_10GB:
35a7d804 4421 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4422 break;
4423 case I40E_LINK_SPEED_1GB:
35a7d804 4424 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08
JB		 4425 break;
4426 default:
4427 break;
4428 }
4429
4430 switch (vsi->back->hw.fc.current_mode) {
4431 case I40E_FC_FULL:
35a7d804 4432 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4433 break;
4434 case I40E_FC_TX_PAUSE:
35a7d804 4435 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4436 break;
4437 case I40E_FC_RX_PAUSE:
35a7d804 4438 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4439 break;
4440 default:
35a7d804 4441 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4442 break;
4443 }
4444
4445 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4446 speed, fc);
4447}
4e3b35b0 4448
41c445ff
JB		 4449/**
4450 * i40e_up_complete - Finish the last steps of bringing up a connection
4451 * @vsi: the VSI being configured
4452 **/
4453static int i40e_up_complete(struct i40e_vsi *vsi)
4454{
4455 struct i40e_pf *pf = vsi->back;
c56999f9 4456 u8 set_fc_aq_fail = 0;
41c445ff
JB		 4457 int err;
4458
c56999f9
CS		 4459 /* force flow control off */
4460 i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
4461
41c445ff
JB		 4462 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4463 i40e_vsi_configure_msix(vsi);
4464 else
4465 i40e_configure_msi_and_legacy(vsi);
4466
4467 /* start rings */
4468 err = i40e_vsi_control_rings(vsi, true);
4469 if (err)
4470 return err;
4471
4472 clear_bit(__I40E_DOWN, &vsi->state);
4473 i40e_napi_enable_all(vsi);
4474 i40e_vsi_enable_irq(vsi);
4475
4476 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4477 (vsi->netdev)) {
cf05ed08 4478 i40e_print_link_message(vsi, true);
41c445ff
JB		 4479 netif_tx_start_all_queues(vsi->netdev);
4480 netif_carrier_on(vsi->netdev);
6d779b41 4481 } else if (vsi->netdev) {
cf05ed08 4482 i40e_print_link_message(vsi, false);
41c445ff 4483 }
ca64fa4e
ASJ		 4484
4485 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4486 if (vsi->type == I40E_VSI_FDIR) {
4487 /* reset fd counters */
4488 pf->fd_add_err = pf->fd_atr_cnt = 0;
4489 if (pf->fd_tcp_rule > 0) {
4490 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4491 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4492 pf->fd_tcp_rule = 0;
4493 }
ca64fa4e 4494 i40e_fdir_filter_restore(vsi);
1e1be8f6 4495 }
41c445ff
JB		 4496 i40e_service_event_schedule(pf);
4497
4498 return 0;
4499}
4500
4501/**
4502 * i40e_vsi_reinit_locked - Reset the VSI
4503 * @vsi: the VSI being configured
4504 *
4505 * Rebuild the ring structs after some configuration
4506 * has changed, e.g. MTU size.
4507 **/
4508static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4509{
4510 struct i40e_pf *pf = vsi->back;
4511
4512 WARN_ON(in_interrupt());
4513 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4514 usleep_range(1000, 2000);
4515 i40e_down(vsi);
4516
4517 /* Give a VF some time to respond to the reset. The
4518 * two second wait is based upon the watchdog cycle in
4519 * the VF driver.
4520 */
4521 if (vsi->type == I40E_VSI_SRIOV)
4522 msleep(2000);
4523 i40e_up(vsi);
4524 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4525}
4526
4527/**
4528 * i40e_up - Bring the connection back up after being down
4529 * @vsi: the VSI being configured
4530 **/
4531int i40e_up(struct i40e_vsi *vsi)
4532{
4533 int err;
4534
4535 err = i40e_vsi_configure(vsi);
4536 if (!err)
4537 err = i40e_up_complete(vsi);
4538
4539 return err;
4540}
4541
4542/**
4543 * i40e_down - Shutdown the connection processing
4544 * @vsi: the VSI being stopped
4545 **/
4546void i40e_down(struct i40e_vsi *vsi)
4547{
4548 int i;
4549
4550 /* It is assumed that the caller of this function
4551 * sets the vsi->state __I40E_DOWN bit.
4552 */
4553 if (vsi->netdev) {
4554 netif_carrier_off(vsi->netdev);
4555 netif_tx_disable(vsi->netdev);
4556 }
4557 i40e_vsi_disable_irq(vsi);
4558 i40e_vsi_control_rings(vsi, false);
4559 i40e_napi_disable_all(vsi);
4560
4561 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4562 i40e_clean_tx_ring(vsi->tx_rings[i]);
4563 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4564 }
4565}
4566
4567/**
4568 * i40e_setup_tc - configure multiple traffic classes
4569 * @netdev: net device to configure
4570 * @tc: number of traffic classes to enable
4571 **/
38e00438
VD		 4572#ifdef I40E_FCOE
4573int i40e_setup_tc(struct net_device *netdev, u8 tc)
4574#else
41c445ff 4575static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4576#endif
41c445ff
JB		 4577{
4578 struct i40e_netdev_priv *np = netdev_priv(netdev);
4579 struct i40e_vsi *vsi = np->vsi;
4580 struct i40e_pf *pf = vsi->back;
4581 u8 enabled_tc = 0;
4582 int ret = -EINVAL;
4583 int i;
4584
4585 /* Check if DCB enabled to continue */
4586 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4587 netdev_info(netdev, "DCB is not enabled for adapter\n");
4588 goto exit;
4589 }
4590
4591 /* Check if MFP enabled */
4592 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4593 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4594 goto exit;
4595 }
4596
4597 /* Check whether tc count is within enabled limit */
4598 if (tc > i40e_pf_get_num_tc(pf)) {
4599 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4600 goto exit;
4601 }
4602
4603 /* Generate TC map for number of tc requested */
4604 for (i = 0; i < tc; i++)
4605 enabled_tc |= (1 << i);
4606
4607 /* Requesting same TC configuration as already enabled */
4608 if (enabled_tc == vsi->tc_config.enabled_tc)
4609 return 0;
4610
4611 /* Quiesce VSI queues */
4612 i40e_quiesce_vsi(vsi);
4613
4614 /* Configure VSI for enabled TCs */
4615 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4616 if (ret) {
4617 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4618 vsi->seid);
4619 goto exit;
4620 }
4621
4622 /* Unquiesce VSI */
4623 i40e_unquiesce_vsi(vsi);
4624
4625exit:
4626 return ret;
4627}
4628
4629/**
4630 * i40e_open - Called when a network interface is made active
4631 * @netdev: network interface device structure
4632 *
4633 * The open entry point is called when a network interface is made
4634 * active by the system (IFF_UP). At this point all resources needed
4635 * for transmit and receive operations are allocated, the interrupt
4636 * handler is registered with the OS, the netdev watchdog subtask is
4637 * enabled, and the stack is notified that the interface is ready.
4638 *
4639 * Returns 0 on success, negative value on failure
4640 **/
38e00438
VD		 4641#ifdef I40E_FCOE
4642int i40e_open(struct net_device *netdev)
4643#else
41c445ff 4644static int i40e_open(struct net_device *netdev)
38e00438 4645#endif
41c445ff
JB		 4646{
4647 struct i40e_netdev_priv *np = netdev_priv(netdev);
4648 struct i40e_vsi *vsi = np->vsi;
4649 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4650 int err;
4651
4eb3f768
SN		 4652 /* disallow open during test or if eeprom is broken */
4653 if (test_bit(__I40E_TESTING, &pf->state) ||
4654 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4655 return -EBUSY;
4656
4657 netif_carrier_off(netdev);
4658
6c167f58
EK		 4659 err = i40e_vsi_open(vsi);
4660 if (err)
4661 return err;
4662
059dab69
JB		 4663 /* configure global TSO hardware offload settings */
4664 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4665 TCP_FLAG_FIN) >> 16);
4666 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4667 TCP_FLAG_FIN |
4668 TCP_FLAG_CWR) >> 16);
4669 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4670
6c167f58
EK		 4671#ifdef CONFIG_I40E_VXLAN
4672 vxlan_get_rx_port(netdev);
4673#endif
4674
4675 return 0;
4676}
4677
4678/**
4679 * i40e_vsi_open -
4680 * @vsi: the VSI to open
4681 *
4682 * Finish initialization of the VSI.
4683 *
4684 * Returns 0 on success, negative value on failure
4685 **/
4686int i40e_vsi_open(struct i40e_vsi *vsi)
4687{
4688 struct i40e_pf *pf = vsi->back;
4689 char int_name[IFNAMSIZ];
4690 int err;
4691
41c445ff
JB		 4692 /* allocate descriptors */
4693 err = i40e_vsi_setup_tx_resources(vsi);
4694 if (err)
4695 goto err_setup_tx;
4696 err = i40e_vsi_setup_rx_resources(vsi);
4697 if (err)
4698 goto err_setup_rx;
4699
4700 err = i40e_vsi_configure(vsi);
4701 if (err)
4702 goto err_setup_rx;
4703
c22e3c6c
SN		 4704 if (vsi->netdev) {
4705 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4706 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4707 err = i40e_vsi_request_irq(vsi, int_name);
4708 if (err)
4709 goto err_setup_rx;
41c445ff 4710
c22e3c6c
SN		 4711 /* Notify the stack of the actual queue counts. */
4712 err = netif_set_real_num_tx_queues(vsi->netdev,
4713 vsi->num_queue_pairs);
4714 if (err)
4715 goto err_set_queues;
25946ddb 4716
c22e3c6c
SN		 4717 err = netif_set_real_num_rx_queues(vsi->netdev,
4718 vsi->num_queue_pairs);
4719 if (err)
4720 goto err_set_queues;
8a9eb7d3
SN		 4721
4722 } else if (vsi->type == I40E_VSI_FDIR) {
4723 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4724 dev_driver_string(&pf->pdev->dev));
4725 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4726 } else {
ce9ccb17 4727 err = -EINVAL;
6c167f58
EK		 4728 goto err_setup_rx;
4729 }
25946ddb 4730
41c445ff
JB		 4731 err = i40e_up_complete(vsi);
4732 if (err)
4733 goto err_up_complete;
4734
41c445ff
JB		 4735 return 0;
4736
4737err_up_complete:
4738 i40e_down(vsi);
25946ddb 4739err_set_queues:
41c445ff
JB		 4740 i40e_vsi_free_irq(vsi);
4741err_setup_rx:
4742 i40e_vsi_free_rx_resources(vsi);
4743err_setup_tx:
4744 i40e_vsi_free_tx_resources(vsi);
4745 if (vsi == pf->vsi[pf->lan_vsi])
4746 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4747
4748 return err;
4749}
4750
17a73f6b
JG		 4751/**
4752 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4753 * @pf: Pointer to pf
4754 *
4755 * This function destroys the hlist where all the Flow Director
4756 * filters were saved.
4757 **/
4758static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4759{
4760 struct i40e_fdir_filter *filter;
4761 struct hlist_node *node2;
4762
4763 hlist_for_each_entry_safe(filter, node2,
4764 &pf->fdir_filter_list, fdir_node) {
4765 hlist_del(&filter->fdir_node);
4766 kfree(filter);
4767 }
4768 pf->fdir_pf_active_filters = 0;
4769}
4770
41c445ff
JB		 4771/**
4772 * i40e_close - Disables a network interface
4773 * @netdev: network interface device structure
4774 *
4775 * The close entry point is called when an interface is de-activated
4776 * by the OS. The hardware is still under the driver's control, but
4777 * this netdev interface is disabled.
4778 *
4779 * Returns 0, this is not allowed to fail
4780 **/
38e00438
VD		 4781#ifdef I40E_FCOE
4782int i40e_close(struct net_device *netdev)
4783#else
41c445ff 4784static int i40e_close(struct net_device *netdev)
38e00438 4785#endif
41c445ff
JB		 4786{
4787 struct i40e_netdev_priv *np = netdev_priv(netdev);
4788 struct i40e_vsi *vsi = np->vsi;
4789
90ef8d47 4790 i40e_vsi_close(vsi);
41c445ff
JB		 4791
4792 return 0;
4793}
4794
4795/**
4796 * i40e_do_reset - Start a PF or Core Reset sequence
4797 * @pf: board private structure
4798 * @reset_flags: which reset is requested
4799 *
4800 * The essential difference in resets is that the PF Reset
4801 * doesn't clear the packet buffers, doesn't reset the PE
4802 * firmware, and doesn't bother the other PFs on the chip.
4803 **/
4804void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4805{
4806 u32 val;
4807
4808 WARN_ON(in_interrupt());
4809
263fc48f
MW		 4810 if (i40e_check_asq_alive(&pf->hw))
4811 i40e_vc_notify_reset(pf);
4812
41c445ff
JB		 4813 /* do the biggest reset indicated */
4814 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4815
4816 /* Request a Global Reset
4817 *
4818 * This will start the chip's countdown to the actual full
4819 * chip reset event, and a warning interrupt to be sent
4820 * to all PFs, including the requestor. Our handler
4821 * for the warning interrupt will deal with the shutdown
4822 * and recovery of the switch setup.
4823 */
69bfb110 4824 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4825 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4826 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4827 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4828
4829 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4830
4831 /* Request a Core Reset
4832 *
4833 * Same as Global Reset, except does *not* include the MAC/PHY
4834 */
69bfb110 4835 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4836 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4837 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4838 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4839 i40e_flush(&pf->hw);
4840
7823fe34
SN		 4841 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4842
4843 /* Request a Firmware Reset
4844 *
4845 * Same as Global reset, plus restarting the
4846 * embedded firmware engine.
4847 */
4848 /* enable EMP Reset */
4849 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4850 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4851 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4852
4853 /* force the reset */
4854 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4855 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4856 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4857 i40e_flush(&pf->hw);
4858
41c445ff
JB		 4859 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4860
4861 /* Request a PF Reset
4862 *
4863 * Resets only the PF-specific registers
4864 *
4865 * This goes directly to the tear-down and rebuild of
4866 * the switch, since we need to do all the recovery as
4867 * for the Core Reset.
4868 */
69bfb110 4869 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4870 i40e_handle_reset_warning(pf);
4871
4872 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4873 int v;
4874
4875 /* Find the VSI(s) that requested a re-init */
4876 dev_info(&pf->pdev->dev,
4877 "VSI reinit requested\n");
505682cd 4878 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4879 struct i40e_vsi *vsi = pf->vsi[v];
4880 if (vsi != NULL &&
4881 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4882 i40e_vsi_reinit_locked(pf->vsi[v]);
4883 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4884 }
4885 }
4886
b5d06f05
NP		 4887 /* no further action needed, so return now */
4888 return;
4889 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
4890 int v;
4891
4892 /* Find the VSI(s) that needs to be brought down */
4893 dev_info(&pf->pdev->dev, "VSI down requested\n");
4894 for (v = 0; v < pf->num_alloc_vsi; v++) {
4895 struct i40e_vsi *vsi = pf->vsi[v];
4896 if (vsi != NULL &&
4897 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
4898 set_bit(__I40E_DOWN, &vsi->state);
4899 i40e_down(vsi);
4900 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
4901 }
4902 }
4903
41c445ff
JB		 4904 /* no further action needed, so return now */
4905 return;
4906 } else {
4907 dev_info(&pf->pdev->dev,
4908 "bad reset request 0x%08x\n", reset_flags);
4909 return;
4910 }
4911}
4912
4e3b35b0
NP		 4913#ifdef CONFIG_I40E_DCB
4914/**
4915 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4916 * @pf: board private structure
4917 * @old_cfg: current DCB config
4918 * @new_cfg: new DCB config
4919 **/
4920bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4921 struct i40e_dcbx_config *old_cfg,
4922 struct i40e_dcbx_config *new_cfg)
4923{
4924 bool need_reconfig = false;
4925
4926 /* Check if ETS configuration has changed */
4927 if (memcmp(&new_cfg->etscfg,
4928 &old_cfg->etscfg,
4929 sizeof(new_cfg->etscfg))) {
4930 /* If Priority Table has changed reconfig is needed */
4931 if (memcmp(&new_cfg->etscfg.prioritytable,
4932 &old_cfg->etscfg.prioritytable,
4933 sizeof(new_cfg->etscfg.prioritytable))) {
4934 need_reconfig = true;
69bfb110 4935 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4936 }
4937
4938 if (memcmp(&new_cfg->etscfg.tcbwtable,
4939 &old_cfg->etscfg.tcbwtable,
4940 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4941 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4942
4943 if (memcmp(&new_cfg->etscfg.tsatable,
4944 &old_cfg->etscfg.tsatable,
4945 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4946 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4947 }
4948
4949 /* Check if PFC configuration has changed */
4950 if (memcmp(&new_cfg->pfc,
4951 &old_cfg->pfc,
4952 sizeof(new_cfg->pfc))) {
4953 need_reconfig = true;
69bfb110 4954 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4955 }
4956
4957 /* Check if APP Table has changed */
4958 if (memcmp(&new_cfg->app,
4959 &old_cfg->app,
3d9667a9 4960 sizeof(new_cfg->app))) {
4e3b35b0 4961 need_reconfig = true;
69bfb110 4962 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4963 }
4e3b35b0
NP		 4964
4965 return need_reconfig;
4966}
4967
4968/**
4969 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4970 * @pf: board private structure
4971 * @e: event info posted on ARQ
4972 **/
4973static int i40e_handle_lldp_event(struct i40e_pf *pf,
4974 struct i40e_arq_event_info *e)
4975{
4976 struct i40e_aqc_lldp_get_mib *mib =
4977 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4978 struct i40e_hw *hw = &pf->hw;
4979 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4980 struct i40e_dcbx_config tmp_dcbx_cfg;
4981 bool need_reconfig = false;
4982 int ret = 0;
4983 u8 type;
4984
4d9b6043
NP		 4985 /* Not DCB capable or capability disabled */
4986 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
4987 return ret;
4988
4e3b35b0
NP		 4989 /* Ignore if event is not for Nearest Bridge */
4990 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4991 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4992 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4993 return ret;
4994
4995 /* Check MIB Type and return if event for Remote MIB update */
4996 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4997 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4998 /* Update the remote cached instance and return */
4999 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5000 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5001 &hw->remote_dcbx_config);
5002 goto exit;
5003 }
5004
5005 /* Convert/store the DCBX data from LLDPDU temporarily */
5006 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
5007 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
5008 if (ret) {
5009 /* Error in LLDPDU parsing return */
5010 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
5011 goto exit;
5012 }
5013
5014 /* No change detected in DCBX configs */
5015 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 5016 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5017 goto exit;
5018 }
5019
5020 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
5021
5022 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
5023
5024 /* Overwrite the new configuration */
5025 *dcbx_cfg = tmp_dcbx_cfg;
5026
5027 if (!need_reconfig)
5028 goto exit;
5029
4d9b6043
NP		 5030 /* Enable DCB tagging only when more than one TC */
5031 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
5032 pf->flags |= I40E_FLAG_DCB_ENABLED;
5033 else
5034 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5035
4e3b35b0
NP		 5036 /* Reconfiguration needed quiesce all VSIs */
5037 i40e_pf_quiesce_all_vsi(pf);
5038
5039 /* Changes in configuration update VEB/VSI */
5040 i40e_dcb_reconfigure(pf);
5041
5042 i40e_pf_unquiesce_all_vsi(pf);
5043exit:
5044 return ret;
5045}
5046#endif /* CONFIG_I40E_DCB */
5047
23326186
ASJ		 5048/**
5049 * i40e_do_reset_safe - Protected reset path for userland calls.
5050 * @pf: board private structure
5051 * @reset_flags: which reset is requested
5052 *
5053 **/
5054void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5055{
5056 rtnl_lock();
5057 i40e_do_reset(pf, reset_flags);
5058 rtnl_unlock();
5059}
5060
41c445ff
JB		 5061/**
5062 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5063 * @pf: board private structure
5064 * @e: event info posted on ARQ
5065 *
5066 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5067 * and VF queues
5068 **/
5069static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5070 struct i40e_arq_event_info *e)
5071{
5072 struct i40e_aqc_lan_overflow *data =
5073 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5074 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5075 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5076 struct i40e_hw *hw = &pf->hw;
5077 struct i40e_vf *vf;
5078 u16 vf_id;
5079
69bfb110
JB		 5080 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5081 queue, qtx_ctl);
41c445ff
JB		 5082
5083 /* Queue belongs to VF, find the VF and issue VF reset */
5084 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5085 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5086 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5087 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5088 vf_id -= hw->func_caps.vf_base_id;
5089 vf = &pf->vf[vf_id];
5090 i40e_vc_notify_vf_reset(vf);
5091 /* Allow VF to process pending reset notification */
5092 msleep(20);
5093 i40e_reset_vf(vf, false);
5094 }
5095}
5096
5097/**
5098 * i40e_service_event_complete - Finish up the service event
5099 * @pf: board private structure
5100 **/
5101static void i40e_service_event_complete(struct i40e_pf *pf)
5102{
5103 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5104
5105 /* flush memory to make sure state is correct before next watchog */
4e857c58 5106 smp_mb__before_atomic();
41c445ff
JB		 5107 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5108}
5109
55a5e60b 5110/**
12957388
ASJ		 5111 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5112 * @pf: board private structure
5113 **/
5114int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
5115{
5116 int val, fcnt_prog;
5117
5118 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5119 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5120 return fcnt_prog;
5121}
5122
5123/**
5124 * i40e_get_current_fd_count - Get the count of total FD filters programmed
55a5e60b
ASJ		 5125 * @pf: board private structure
5126 **/
5127int i40e_get_current_fd_count(struct i40e_pf *pf)
5128{
5129 int val, fcnt_prog;
5130 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5131 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5132 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5133 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5134 return fcnt_prog;
5135}
1e1be8f6 5136
55a5e60b
ASJ		 5137/**
5138 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5139 * @pf: board private structure
5140 **/
5141void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5142{
5143 u32 fcnt_prog, fcnt_avail;
5144
1e1be8f6
ASJ		 5145 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5146 return;
5147
55a5e60b
ASJ		 5148 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5149 * to re-enable
5150 */
12957388
ASJ		 5151 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
5152 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5153 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5154 (pf->fd_add_err == 0) ||
5155 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5156 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5157 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5158 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5159 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5160 }
5161 }
5162 /* Wait for some more space to be available to turn on ATR */
5163 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5164 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5165 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5166 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5167 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5168 }
5169 }
5170}
5171
1e1be8f6
ASJ		 5172#define I40E_MIN_FD_FLUSH_INTERVAL 10
5173/**
5174 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5175 * @pf: board private structure
5176 **/
5177static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5178{
5179 int flush_wait_retry = 50;
5180 int reg;
5181
5182 if (time_after(jiffies, pf->fd_flush_timestamp +
5183 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
5184 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5185 pf->fd_flush_timestamp = jiffies;
5186 pf->auto_disable_flags |= I40E_FLAG_FD_SB_ENABLED;
5187 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5188 /* flush all filters */
5189 wr32(&pf->hw, I40E_PFQF_CTL_1,
5190 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5191 i40e_flush(&pf->hw);
5192 pf->fd_add_err = 0;
5193 do {
5194 /* Check FD flush status every 5-6msec */
5195 usleep_range(5000, 6000);
5196 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5197 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5198 break;
5199 } while (flush_wait_retry--);
5200 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5201 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5202 } else {
5203 /* replay sideband filters */
5204 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5205
5206 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5207 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5208 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5209 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5210 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5211 }
5212 }
5213}
5214
5215/**
5216 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5217 * @pf: board private structure
5218 **/
5219int i40e_get_current_atr_cnt(struct i40e_pf *pf)
5220{
5221 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5222}
5223
5224/* We can see up to 256 filter programming desc in transit if the filters are
5225 * being applied really fast; before we see the first
5226 * filter miss error on Rx queue 0. Accumulating enough error messages before
5227 * reacting will make sure we don't cause flush too often.
5228 */
5229#define I40E_MAX_FD_PROGRAM_ERROR 256
5230
41c445ff
JB		 5231/**
5232 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5233 * @pf: board private structure
5234 **/
5235static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5236{
41c445ff 5237
41c445ff
JB		 5238 /* if interface is down do nothing */
5239 if (test_bit(__I40E_DOWN, &pf->state))
5240 return;
1e1be8f6
ASJ		 5241
5242 if ((pf->fd_add_err >= I40E_MAX_FD_PROGRAM_ERROR) &&
5243 (i40e_get_current_atr_cnt(pf) >= pf->fd_atr_cnt) &&
5244 (i40e_get_current_atr_cnt(pf) > pf->fdir_pf_filter_count))
5245 i40e_fdir_flush_and_replay(pf);
5246
55a5e60b
ASJ		 5247 i40e_fdir_check_and_reenable(pf);
5248
41c445ff
JB		 5249}
5250
5251/**
5252 * i40e_vsi_link_event - notify VSI of a link event
5253 * @vsi: vsi to be notified
5254 * @link_up: link up or down
5255 **/
5256static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5257{
5258 if (!vsi)
5259 return;
5260
5261 switch (vsi->type) {
5262 case I40E_VSI_MAIN:
38e00438
VD		 5263#ifdef I40E_FCOE
5264 case I40E_VSI_FCOE:
5265#endif
41c445ff
JB		 5266 if (!vsi->netdev || !vsi->netdev_registered)
5267 break;
5268
5269 if (link_up) {
5270 netif_carrier_on(vsi->netdev);
5271 netif_tx_wake_all_queues(vsi->netdev);
5272 } else {
5273 netif_carrier_off(vsi->netdev);
5274 netif_tx_stop_all_queues(vsi->netdev);
5275 }
5276 break;
5277
5278 case I40E_VSI_SRIOV:
5279 break;
5280
5281 case I40E_VSI_VMDQ2:
5282 case I40E_VSI_CTRL:
5283 case I40E_VSI_MIRROR:
5284 default:
5285 /* there is no notification for other VSIs */
5286 break;
5287 }
5288}
5289
5290/**
5291 * i40e_veb_link_event - notify elements on the veb of a link event
5292 * @veb: veb to be notified
5293 * @link_up: link up or down
5294 **/
5295static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5296{
5297 struct i40e_pf *pf;
5298 int i;
5299
5300 if (!veb || !veb->pf)
5301 return;
5302 pf = veb->pf;
5303
5304 /* depth first... */
5305 for (i = 0; i < I40E_MAX_VEB; i++)
5306 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5307 i40e_veb_link_event(pf->veb[i], link_up);
5308
5309 /* ... now the local VSIs */
505682cd 5310 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5311 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5312 i40e_vsi_link_event(pf->vsi[i], link_up);
5313}
5314
5315/**
5316 * i40e_link_event - Update netif_carrier status
5317 * @pf: board private structure
5318 **/
5319static void i40e_link_event(struct i40e_pf *pf)
5320{
5321 bool new_link, old_link;
5322
5323 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
5324 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
5325
5326 if (new_link == old_link)
5327 return;
6d779b41 5328 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
cf05ed08 5329 i40e_print_link_message(pf->vsi[pf->lan_vsi], new_link);
41c445ff
JB		 5330
5331 /* Notify the base of the switch tree connected to
5332 * the link. Floating VEBs are not notified.
5333 */
5334 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5335 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5336 else
5337 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
5338
5339 if (pf->vf)
5340 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5341
5342 if (pf->flags & I40E_FLAG_PTP)
5343 i40e_ptp_set_increment(pf);
41c445ff
JB		 5344}
5345
5346/**
5347 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5348 * @pf: board private structure
5349 *
5350 * Set the per-queue flags to request a check for stuck queues in the irq
5351 * clean functions, then force interrupts to be sure the irq clean is called.
5352 **/
5353static void i40e_check_hang_subtask(struct i40e_pf *pf)
5354{
5355 int i, v;
5356
5357 /* If we're down or resetting, just bail */
5358 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5359 return;
5360
5361 /* for each VSI/netdev
5362 * for each Tx queue
5363 * set the check flag
5364 * for each q_vector
5365 * force an interrupt
5366 */
505682cd 5367 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5368 struct i40e_vsi *vsi = pf->vsi[v];
5369 int armed = 0;
5370
5371 if (!pf->vsi[v] ||
5372 test_bit(__I40E_DOWN, &vsi->state) ||
5373 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5374 continue;
5375
5376 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5377 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5378 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5379 &vsi->tx_rings[i]->state))
41c445ff
JB		 5380 armed++;
5381 }
5382
5383 if (armed) {
5384 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5385 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5386 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5387 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
5388 } else {
5389 u16 vec = vsi->base_vector - 1;
5390 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5391 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5392 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5393 wr32(&vsi->back->hw,
5394 I40E_PFINT_DYN_CTLN(vec), val);
5395 }
5396 i40e_flush(&vsi->back->hw);
5397 }
5398 }
5399}
5400
5401/**
5402 * i40e_watchdog_subtask - Check and bring link up
5403 * @pf: board private structure
5404 **/
5405static void i40e_watchdog_subtask(struct i40e_pf *pf)
5406{
5407 int i;
5408
5409 /* if interface is down do nothing */
5410 if (test_bit(__I40E_DOWN, &pf->state) ||
5411 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5412 return;
5413
5414 /* Update the stats for active netdevs so the network stack
5415 * can look at updated numbers whenever it cares to
5416 */
505682cd 5417 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5418 if (pf->vsi[i] && pf->vsi[i]->netdev)
5419 i40e_update_stats(pf->vsi[i]);
5420
5421 /* Update the stats for the active switching components */
5422 for (i = 0; i < I40E_MAX_VEB; i++)
5423 if (pf->veb[i])
5424 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5425
5426 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5427}
5428
5429/**
5430 * i40e_reset_subtask - Set up for resetting the device and driver
5431 * @pf: board private structure
5432 **/
5433static void i40e_reset_subtask(struct i40e_pf *pf)
5434{
5435 u32 reset_flags = 0;
5436
23326186 5437 rtnl_lock();
41c445ff
JB		 5438 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5439 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5440 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5441 }
5442 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5443 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5444 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5445 }
5446 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5447 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5448 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5449 }
5450 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5451 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5452 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5453 }
b5d06f05
NP		 5454 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5455 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5456 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5457 }
41c445ff
JB		 5458
5459 /* If there's a recovery already waiting, it takes
5460 * precedence before starting a new reset sequence.
5461 */
5462 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5463 i40e_handle_reset_warning(pf);
23326186 5464 goto unlock;
41c445ff
JB		 5465 }
5466
5467 /* If we're already down or resetting, just bail */
5468 if (reset_flags &&
5469 !test_bit(__I40E_DOWN, &pf->state) &&
5470 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5471 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5472
5473unlock:
5474 rtnl_unlock();
41c445ff
JB		 5475}
5476
5477/**
5478 * i40e_handle_link_event - Handle link event
5479 * @pf: board private structure
5480 * @e: event info posted on ARQ
5481 **/
5482static void i40e_handle_link_event(struct i40e_pf *pf,
5483 struct i40e_arq_event_info *e)
5484{
5485 struct i40e_hw *hw = &pf->hw;
5486 struct i40e_aqc_get_link_status *status =
5487 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5488 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5489
5490 /* save off old link status information */
5491 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5492 sizeof(pf->hw.phy.link_info_old));
5493
5494 /* update link status */
5495 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
5496 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
5497 hw_link_info->link_info = status->link_info;
5498 hw_link_info->an_info = status->an_info;
5499 hw_link_info->ext_info = status->ext_info;
5500 hw_link_info->lse_enable =
5501 le16_to_cpu(status->command_flags) &
5502 I40E_AQ_LSE_ENABLE;
5503
5504 /* process the event */
5505 i40e_link_event(pf);
5506
5507 /* Do a new status request to re-enable LSE reporting
5508 * and load new status information into the hw struct,
5509 * then see if the status changed while processing the
5510 * initial event.
5511 */
8109e123 5512 i40e_update_link_info(&pf->hw, true);
41c445ff
JB		 5513 i40e_link_event(pf);
5514}
5515
5516/**
5517 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5518 * @pf: board private structure
5519 **/
5520static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5521{
5522 struct i40e_arq_event_info event;
5523 struct i40e_hw *hw = &pf->hw;
5524 u16 pending, i = 0;
5525 i40e_status ret;
5526 u16 opcode;
86df242b 5527 u32 oldval;
41c445ff
JB		 5528 u32 val;
5529
86df242b
SN		 5530 /* check for error indications */
5531 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5532 oldval = val;
5533 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5534 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5535 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5536 }
5537 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5538 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5539 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5540 }
5541 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5542 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5543 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5544 }
5545 if (oldval != val)
5546 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5547
5548 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5549 oldval = val;
5550 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5551 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5552 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5553 }
5554 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5555 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5556 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5557 }
5558 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5559 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5560 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5561 }
5562 if (oldval != val)
5563 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5564
3197ce22 5565 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5566 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5567 if (!event.msg_buf)
5568 return;
5569
5570 do {
2f019123 5571 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff 5572 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5573 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5574 break;
56497978 5575 else if (ret) {
41c445ff
JB		 5576 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5577 break;
5578 }
5579
5580 opcode = le16_to_cpu(event.desc.opcode);
5581 switch (opcode) {
5582
5583 case i40e_aqc_opc_get_link_status:
5584 i40e_handle_link_event(pf, &event);
5585 break;
5586 case i40e_aqc_opc_send_msg_to_pf:
5587 ret = i40e_vc_process_vf_msg(pf,
5588 le16_to_cpu(event.desc.retval),
5589 le32_to_cpu(event.desc.cookie_high),
5590 le32_to_cpu(event.desc.cookie_low),
5591 event.msg_buf,
5592 event.msg_size);
5593 break;
5594 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5595 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5596#ifdef CONFIG_I40E_DCB
5597 rtnl_lock();
5598 ret = i40e_handle_lldp_event(pf, &event);
5599 rtnl_unlock();
5600#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5601 break;
5602 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5603 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5604 i40e_handle_lan_overflow_event(pf, &event);
5605 break;
0467bc91
SN		 5606 case i40e_aqc_opc_send_msg_to_peer:
5607 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5608 break;
41c445ff
JB		 5609 default:
5610 dev_info(&pf->pdev->dev,
0467bc91
SN		 5611 "ARQ Error: Unknown event 0x%04x received\n",
5612 opcode);
41c445ff
JB		 5613 break;
5614 }
5615 } while (pending && (i++ < pf->adminq_work_limit));
5616
5617 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5618 /* re-enable Admin queue interrupt cause */
5619 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5620 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5621 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5622 i40e_flush(hw);
5623
5624 kfree(event.msg_buf);
5625}
5626
4eb3f768
SN		 5627/**
5628 * i40e_verify_eeprom - make sure eeprom is good to use
5629 * @pf: board private structure
5630 **/
5631static void i40e_verify_eeprom(struct i40e_pf *pf)
5632{
5633 int err;
5634
5635 err = i40e_diag_eeprom_test(&pf->hw);
5636 if (err) {
5637 /* retry in case of garbage read */
5638 err = i40e_diag_eeprom_test(&pf->hw);
5639 if (err) {
5640 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5641 err);
5642 set_bit(__I40E_BAD_EEPROM, &pf->state);
5643 }
5644 }
5645
5646 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5647 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5648 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5649 }
5650}
5651
41c445ff
JB		 5652/**
5653 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5654 * @veb: pointer to the VEB instance
5655 *
5656 * This is a recursive function that first builds the attached VSIs then
5657 * recurses in to build the next layer of VEB. We track the connections
5658 * through our own index numbers because the seid's from the HW could
5659 * change across the reset.
5660 **/
5661static int i40e_reconstitute_veb(struct i40e_veb *veb)
5662{
5663 struct i40e_vsi *ctl_vsi = NULL;
5664 struct i40e_pf *pf = veb->pf;
5665 int v, veb_idx;
5666 int ret;
5667
5668 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5669 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5670 if (pf->vsi[v] &&
5671 pf->vsi[v]->veb_idx == veb->idx &&
5672 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5673 ctl_vsi = pf->vsi[v];
5674 break;
5675 }
5676 }
5677 if (!ctl_vsi) {
5678 dev_info(&pf->pdev->dev,
5679 "missing owner VSI for veb_idx %d\n", veb->idx);
5680 ret = -ENOENT;
5681 goto end_reconstitute;
5682 }
5683 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5684 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5685 ret = i40e_add_vsi(ctl_vsi);
5686 if (ret) {
5687 dev_info(&pf->pdev->dev,
5688 "rebuild of owner VSI failed: %d\n", ret);
5689 goto end_reconstitute;
5690 }
5691 i40e_vsi_reset_stats(ctl_vsi);
5692
5693 /* create the VEB in the switch and move the VSI onto the VEB */
5694 ret = i40e_add_veb(veb, ctl_vsi);
5695 if (ret)
5696 goto end_reconstitute;
5697
5698 /* create the remaining VSIs attached to this VEB */
505682cd 5699 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5700 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5701 continue;
5702
5703 if (pf->vsi[v]->veb_idx == veb->idx) {
5704 struct i40e_vsi *vsi = pf->vsi[v];
5705 vsi->uplink_seid = veb->seid;
5706 ret = i40e_add_vsi(vsi);
5707 if (ret) {
5708 dev_info(&pf->pdev->dev,
5709 "rebuild of vsi_idx %d failed: %d\n",
5710 v, ret);
5711 goto end_reconstitute;
5712 }
5713 i40e_vsi_reset_stats(vsi);
5714 }
5715 }
5716
5717 /* create any VEBs attached to this VEB - RECURSION */
5718 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5719 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5720 pf->veb[veb_idx]->uplink_seid = veb->seid;
5721 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5722 if (ret)
5723 break;
5724 }
5725 }
5726
5727end_reconstitute:
5728 return ret;
5729}
5730
5731/**
5732 * i40e_get_capabilities - get info about the HW
5733 * @pf: the PF struct
5734 **/
5735static int i40e_get_capabilities(struct i40e_pf *pf)
5736{
5737 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5738 u16 data_size;
5739 int buf_len;
5740 int err;
5741
5742 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5743 do {
5744 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5745 if (!cap_buf)
5746 return -ENOMEM;
5747
5748 /* this loads the data into the hw struct for us */
5749 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5750 &data_size,
5751 i40e_aqc_opc_list_func_capabilities,
5752 NULL);
5753 /* data loaded, buffer no longer needed */
5754 kfree(cap_buf);
5755
5756 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5757 /* retry with a larger buffer */
5758 buf_len = data_size;
5759 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5760 dev_info(&pf->pdev->dev,
5761 "capability discovery failed: aq=%d\n",
5762 pf->hw.aq.asq_last_status);
5763 return -ENODEV;
5764 }
5765 } while (err);
5766
ac71b7ba
ASJ		 5767 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5768 (pf->hw.aq.fw_maj_ver < 2)) {
5769 pf->hw.func_caps.num_msix_vectors++;
5770 pf->hw.func_caps.num_msix_vectors_vf++;
5771 }
5772
41c445ff
JB		 5773 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5774 dev_info(&pf->pdev->dev,
5775 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5776 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5777 pf->hw.func_caps.num_msix_vectors,
5778 pf->hw.func_caps.num_msix_vectors_vf,
5779 pf->hw.func_caps.fd_filters_guaranteed,
5780 pf->hw.func_caps.fd_filters_best_effort,
5781 pf->hw.func_caps.num_tx_qp,
5782 pf->hw.func_caps.num_vsis);
5783
7134f9ce
JB		 5784#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5785 + pf->hw.func_caps.num_vfs)
5786 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5787 dev_info(&pf->pdev->dev,
5788 "got num_vsis %d, setting num_vsis to %d\n",
5789 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5790 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5791 }
5792
41c445ff
JB		 5793 return 0;
5794}
5795
cbf61325
ASJ		 5796static int i40e_vsi_clear(struct i40e_vsi *vsi);
5797
41c445ff 5798/**
cbf61325 5799 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5800 * @pf: board private structure
5801 **/
cbf61325 5802static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5803{
5804 struct i40e_vsi *vsi;
8a9eb7d3 5805 int i;
41c445ff 5806
407e063c
JB		 5807 /* quick workaround for an NVM issue that leaves a critical register
5808 * uninitialized
5809 */
5810 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
5811 static const u32 hkey[] = {
5812 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
5813 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
5814 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
5815 0x95b3a76d};
5816
5817 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
5818 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
5819 }
5820
cbf61325 5821 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5822 return;
5823
cbf61325 5824 /* find existing VSI and see if it needs configuring */
41c445ff 5825 vsi = NULL;
505682cd 5826 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 5827 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5828 vsi = pf->vsi[i];
cbf61325
ASJ		 5829 break;
5830 }
5831 }
5832
5833 /* create a new VSI if none exists */
41c445ff 5834 if (!vsi) {
cbf61325
ASJ		 5835 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5836 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5837 if (!vsi) {
5838 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5839 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5840 return;
41c445ff 5841 }
cbf61325 5842 }
41c445ff 5843
8a9eb7d3 5844 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5845}
5846
5847/**
5848 * i40e_fdir_teardown - release the Flow Director resources
5849 * @pf: board private structure
5850 **/
5851static void i40e_fdir_teardown(struct i40e_pf *pf)
5852{
5853 int i;
5854
17a73f6b 5855 i40e_fdir_filter_exit(pf);
505682cd 5856 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 5857 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5858 i40e_vsi_release(pf->vsi[i]);
5859 break;
5860 }
5861 }
5862}
5863
5864/**
f650a38b 5865 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5866 * @pf: board private structure
5867 *
f650a38b
ASJ		 5868 * Close up the VFs and other things in prep for pf Reset.
5869 **/
23cfbe07 5870static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5871{
41c445ff 5872 struct i40e_hw *hw = &pf->hw;
60442dea 5873 i40e_status ret = 0;
41c445ff
JB		 5874 u32 v;
5875
5876 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5877 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 5878 return;
41c445ff 5879
69bfb110 5880 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5881
41c445ff
JB		 5882 /* quiesce the VSIs and their queues that are not already DOWN */
5883 i40e_pf_quiesce_all_vsi(pf);
5884
505682cd 5885 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5886 if (pf->vsi[v])
5887 pf->vsi[v]->seid = 0;
5888 }
5889
5890 i40e_shutdown_adminq(&pf->hw);
5891
f650a38b 5892 /* call shutdown HMC */
60442dea
SN		 5893 if (hw->hmc.hmc_obj) {
5894 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 5895 if (ret)
60442dea
SN		 5896 dev_warn(&pf->pdev->dev,
5897 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 5898 }
f650a38b
ASJ		 5899}
5900
44033fac
JB		 5901/**
5902 * i40e_send_version - update firmware with driver version
5903 * @pf: PF struct
5904 */
5905static void i40e_send_version(struct i40e_pf *pf)
5906{
5907 struct i40e_driver_version dv;
5908
5909 dv.major_version = DRV_VERSION_MAJOR;
5910 dv.minor_version = DRV_VERSION_MINOR;
5911 dv.build_version = DRV_VERSION_BUILD;
5912 dv.subbuild_version = 0;
35a7d804 5913 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 5914 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5915}
5916
f650a38b 5917/**
4dda12e6 5918 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5919 * @pf: board private structure
bc7d338f 5920 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5921 **/
bc7d338f 5922static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5923{
f650a38b
ASJ		 5924 struct i40e_hw *hw = &pf->hw;
5925 i40e_status ret;
5926 u32 v;
5927
41c445ff
JB		 5928 /* Now we wait for GRST to settle out.
5929 * We don't have to delete the VEBs or VSIs from the hw switch
5930 * because the reset will make them disappear.
5931 */
5932 ret = i40e_pf_reset(hw);
b5565400 5933 if (ret) {
41c445ff 5934 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
b5565400
AA		 5935 goto end_core_reset;
5936 }
41c445ff
JB		 5937 pf->pfr_count++;
5938
5939 if (test_bit(__I40E_DOWN, &pf->state))
5940 goto end_core_reset;
69bfb110 5941 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5942
5943 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5944 ret = i40e_init_adminq(&pf->hw);
5945 if (ret) {
5946 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5947 goto end_core_reset;
5948 }
5949
4eb3f768
SN		 5950 /* re-verify the eeprom if we just had an EMP reset */
5951 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5952 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5953 i40e_verify_eeprom(pf);
5954 }
5955
e78ac4bf 5956 i40e_clear_pxe_mode(hw);
41c445ff
JB		 5957 ret = i40e_get_capabilities(pf);
5958 if (ret) {
5959 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5960 ret);
5961 goto end_core_reset;
5962 }
5963
41c445ff
JB		 5964 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5965 hw->func_caps.num_rx_qp,
5966 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5967 if (ret) {
5968 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5969 goto end_core_reset;
5970 }
5971 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5972 if (ret) {
5973 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5974 goto end_core_reset;
5975 }
5976
4e3b35b0
NP		 5977#ifdef CONFIG_I40E_DCB
5978 ret = i40e_init_pf_dcb(pf);
5979 if (ret) {
5980 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5981 goto end_core_reset;
5982 }
5983#endif /* CONFIG_I40E_DCB */
38e00438
VD		 5984#ifdef I40E_FCOE
5985 ret = i40e_init_pf_fcoe(pf);
5986 if (ret)
5987 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 5988
38e00438 5989#endif
41c445ff 5990 /* do basic switch setup */
bc7d338f 5991 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5992 if (ret)
5993 goto end_core_reset;
5994
5995 /* Rebuild the VSIs and VEBs that existed before reset.
5996 * They are still in our local switch element arrays, so only
5997 * need to rebuild the switch model in the HW.
5998 *
5999 * If there were VEBs but the reconstitution failed, we'll try
6000 * try to recover minimal use by getting the basic PF VSI working.
6001 */
6002 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6003 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6004 /* find the one VEB connected to the MAC, and find orphans */
6005 for (v = 0; v < I40E_MAX_VEB; v++) {
6006 if (!pf->veb[v])
6007 continue;
6008
6009 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6010 pf->veb[v]->uplink_seid == 0) {
6011 ret = i40e_reconstitute_veb(pf->veb[v]);
6012
6013 if (!ret)
6014 continue;
6015
6016 /* If Main VEB failed, we're in deep doodoo,
6017 * so give up rebuilding the switch and set up
6018 * for minimal rebuild of PF VSI.
6019 * If orphan failed, we'll report the error
6020 * but try to keep going.
6021 */
6022 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6023 dev_info(&pf->pdev->dev,
6024 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6025 ret);
6026 pf->vsi[pf->lan_vsi]->uplink_seid
6027 = pf->mac_seid;
6028 break;
6029 } else if (pf->veb[v]->uplink_seid == 0) {
6030 dev_info(&pf->pdev->dev,
6031 "rebuild of orphan VEB failed: %d\n",
6032 ret);
6033 }
6034 }
6035 }
6036 }
6037
6038 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6039 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6040 /* no VEB, so rebuild only the Main VSI */
6041 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6042 if (ret) {
6043 dev_info(&pf->pdev->dev,
6044 "rebuild of Main VSI failed: %d\n", ret);
6045 goto end_core_reset;
6046 }
6047 }
6048
6049 /* reinit the misc interrupt */
6050 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6051 ret = i40e_setup_misc_vector(pf);
6052
6053 /* restart the VSIs that were rebuilt and running before the reset */
6054 i40e_pf_unquiesce_all_vsi(pf);
6055
69f64b2b
MW		 6056 if (pf->num_alloc_vfs) {
6057 for (v = 0; v < pf->num_alloc_vfs; v++)
6058 i40e_reset_vf(&pf->vf[v], true);
6059 }
6060
41c445ff 6061 /* tell the firmware that we're starting */
44033fac 6062 i40e_send_version(pf);
41c445ff
JB		 6063
6064end_core_reset:
6065 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6066}
6067
f650a38b
ASJ		 6068/**
6069 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
6070 * @pf: board private structure
6071 *
6072 * Close up the VFs and other things in prep for a Core Reset,
6073 * then get ready to rebuild the world.
6074 **/
6075static void i40e_handle_reset_warning(struct i40e_pf *pf)
6076{
23cfbe07
SN		 6077 i40e_prep_for_reset(pf);
6078 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6079}
6080
41c445ff
JB		 6081/**
6082 * i40e_handle_mdd_event
6083 * @pf: pointer to the pf structure
6084 *
6085 * Called from the MDD irq handler to identify possibly malicious vfs
6086 **/
6087static void i40e_handle_mdd_event(struct i40e_pf *pf)
6088{
6089 struct i40e_hw *hw = &pf->hw;
6090 bool mdd_detected = false;
df430b12 6091 bool pf_mdd_detected = false;
41c445ff
JB		 6092 struct i40e_vf *vf;
6093 u32 reg;
6094 int i;
6095
6096 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6097 return;
6098
6099 /* find what triggered the MDD event */
6100 reg = rd32(hw, I40E_GL_MDET_TX);
6101 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6102 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6103 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6104 u8 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6105 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6106 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT) >>
6107 I40E_GL_MDET_TX_EVENT_SHIFT;
6108 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6109 I40E_GL_MDET_TX_QUEUE_SHIFT;
41c445ff 6110 dev_info(&pf->pdev->dev,
4c33f83a
ASJ		 6111 "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
6112 event, queue, pf_num, vf_num);
41c445ff
JB		 6113 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6114 mdd_detected = true;
6115 }
6116 reg = rd32(hw, I40E_GL_MDET_RX);
6117 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6118 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6119 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6120 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT) >>
6121 I40E_GL_MDET_RX_EVENT_SHIFT;
6122 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6123 I40E_GL_MDET_RX_QUEUE_SHIFT;
41c445ff 6124 dev_info(&pf->pdev->dev,
f29eaa3d 6125 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 6126 event, queue, func);
6127 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6128 mdd_detected = true;
6129 }
6130
df430b12
NP		 6131 if (mdd_detected) {
6132 reg = rd32(hw, I40E_PF_MDET_TX);
6133 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6134 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
6135 dev_info(&pf->pdev->dev,
6136 "MDD TX event is for this function 0x%08x, requesting PF reset.\n",
6137 reg);
6138 pf_mdd_detected = true;
6139 }
6140 reg = rd32(hw, I40E_PF_MDET_RX);
6141 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6142 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
6143 dev_info(&pf->pdev->dev,
6144 "MDD RX event is for this function 0x%08x, requesting PF reset.\n",
6145 reg);
6146 pf_mdd_detected = true;
6147 }
6148 /* Queue belongs to the PF, initiate a reset */
6149 if (pf_mdd_detected) {
6150 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6151 i40e_service_event_schedule(pf);
6152 }
6153 }
6154
41c445ff
JB		 6155 /* see if one of the VFs needs its hand slapped */
6156 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6157 vf = &(pf->vf[i]);
6158 reg = rd32(hw, I40E_VP_MDET_TX(i));
6159 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6160 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6161 vf->num_mdd_events++;
6162 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
6163 }
6164
6165 reg = rd32(hw, I40E_VP_MDET_RX(i));
6166 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6167 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6168 vf->num_mdd_events++;
6169 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
6170 }
6171
6172 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6173 dev_info(&pf->pdev->dev,
6174 "Too many MDD events on VF %d, disabled\n", i);
6175 dev_info(&pf->pdev->dev,
6176 "Use PF Control I/F to re-enable the VF\n");
6177 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6178 }
6179 }
6180
6181 /* re-enable mdd interrupt cause */
6182 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6183 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6184 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6185 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6186 i40e_flush(hw);
6187}
6188
a1c9a9d9
JK		 6189#ifdef CONFIG_I40E_VXLAN
6190/**
6191 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6192 * @pf: board private structure
6193 **/
6194static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6195{
a1c9a9d9
JK		 6196 struct i40e_hw *hw = &pf->hw;
6197 i40e_status ret;
6198 u8 filter_index;
6199 __be16 port;
6200 int i;
6201
6202 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6203 return;
6204
6205 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6206
6207 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6208 if (pf->pending_vxlan_bitmap & (1 << i)) {
6209 pf->pending_vxlan_bitmap &= ~(1 << i);
6210 port = pf->vxlan_ports[i];
6211 ret = port ?
6212 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6213 I40E_AQC_TUNNEL_TYPE_VXLAN,
6214 &filter_index, NULL)
6215 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6216
6217 if (ret) {
6218 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6219 port ? "adding" : "deleting",
6220 ntohs(port), port ? i : i);
6221
6222 pf->vxlan_ports[i] = 0;
6223 } else {
6224 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6225 port ? "Added" : "Deleted",
6226 ntohs(port), port ? i : filter_index);
6227 }
6228 }
6229 }
6230}
6231
6232#endif
41c445ff
JB		 6233/**
6234 * i40e_service_task - Run the driver's async subtasks
6235 * @work: pointer to work_struct containing our data
6236 **/
6237static void i40e_service_task(struct work_struct *work)
6238{
6239 struct i40e_pf *pf = container_of(work,
6240 struct i40e_pf,
6241 service_task);
6242 unsigned long start_time = jiffies;
6243
e57a2fea
SN		 6244 /* don't bother with service tasks if a reset is in progress */
6245 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6246 i40e_service_event_complete(pf);
6247 return;
6248 }
6249
41c445ff
JB		 6250 i40e_reset_subtask(pf);
6251 i40e_handle_mdd_event(pf);
6252 i40e_vc_process_vflr_event(pf);
6253 i40e_watchdog_subtask(pf);
6254 i40e_fdir_reinit_subtask(pf);
6255 i40e_check_hang_subtask(pf);
6256 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6257#ifdef CONFIG_I40E_VXLAN
6258 i40e_sync_vxlan_filters_subtask(pf);
6259#endif
41c445ff
JB		 6260 i40e_clean_adminq_subtask(pf);
6261
6262 i40e_service_event_complete(pf);
6263
6264 /* If the tasks have taken longer than one timer cycle or there
6265 * is more work to be done, reschedule the service task now
6266 * rather than wait for the timer to tick again.
6267 */
6268 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6269 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6270 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6271 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6272 i40e_service_event_schedule(pf);
6273}
6274
6275/**
6276 * i40e_service_timer - timer callback
6277 * @data: pointer to PF struct
6278 **/
6279static void i40e_service_timer(unsigned long data)
6280{
6281 struct i40e_pf *pf = (struct i40e_pf *)data;
6282
6283 mod_timer(&pf->service_timer,
6284 round_jiffies(jiffies + pf->service_timer_period));
6285 i40e_service_event_schedule(pf);
6286}
6287
6288/**
6289 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6290 * @vsi: the VSI being configured
6291 **/
6292static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6293{
6294 struct i40e_pf *pf = vsi->back;
6295
6296 switch (vsi->type) {
6297 case I40E_VSI_MAIN:
6298 vsi->alloc_queue_pairs = pf->num_lan_qps;
6299 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6300 I40E_REQ_DESCRIPTOR_MULTIPLE);
6301 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6302 vsi->num_q_vectors = pf->num_lan_msix;
6303 else
6304 vsi->num_q_vectors = 1;
6305
6306 break;
6307
6308 case I40E_VSI_FDIR:
6309 vsi->alloc_queue_pairs = 1;
6310 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6311 I40E_REQ_DESCRIPTOR_MULTIPLE);
6312 vsi->num_q_vectors = 1;
6313 break;
6314
6315 case I40E_VSI_VMDQ2:
6316 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6317 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6318 I40E_REQ_DESCRIPTOR_MULTIPLE);
6319 vsi->num_q_vectors = pf->num_vmdq_msix;
6320 break;
6321
6322 case I40E_VSI_SRIOV:
6323 vsi->alloc_queue_pairs = pf->num_vf_qps;
6324 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6325 I40E_REQ_DESCRIPTOR_MULTIPLE);
6326 break;
6327
38e00438
VD		 6328#ifdef I40E_FCOE
6329 case I40E_VSI_FCOE:
6330 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6331 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6332 I40E_REQ_DESCRIPTOR_MULTIPLE);
6333 vsi->num_q_vectors = pf->num_fcoe_msix;
6334 break;
6335
6336#endif /* I40E_FCOE */
41c445ff
JB		 6337 default:
6338 WARN_ON(1);
6339 return -ENODATA;
6340 }
6341
6342 return 0;
6343}
6344
f650a38b
ASJ		 6345/**
6346 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6347 * @type: VSI pointer
bc7d338f 6348 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6349 *
6350 * On error: returns error code (negative)
6351 * On success: returns 0
6352 **/
bc7d338f 6353static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6354{
6355 int size;
6356 int ret = 0;
6357
ac6c5e3d 6358 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6359 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6360 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6361 if (!vsi->tx_rings)
6362 return -ENOMEM;
f650a38b
ASJ		 6363 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6364
bc7d338f
ASJ		 6365 if (alloc_qvectors) {
6366 /* allocate memory for q_vector pointers */
f57e4fbd 6367 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6368 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6369 if (!vsi->q_vectors) {
6370 ret = -ENOMEM;
6371 goto err_vectors;
6372 }
f650a38b
ASJ		 6373 }
6374 return ret;
6375
6376err_vectors:
6377 kfree(vsi->tx_rings);
6378 return ret;
6379}
6380
41c445ff
JB		 6381/**
6382 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6383 * @pf: board private structure
6384 * @type: type of VSI
6385 *
6386 * On error: returns error code (negative)
6387 * On success: returns vsi index in PF (positive)
6388 **/
6389static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6390{
6391 int ret = -ENODEV;
6392 struct i40e_vsi *vsi;
6393 int vsi_idx;
6394 int i;
6395
6396 /* Need to protect the allocation of the VSIs at the PF level */
6397 mutex_lock(&pf->switch_mutex);
6398
6399 /* VSI list may be fragmented if VSI creation/destruction has
6400 * been happening. We can afford to do a quick scan to look
6401 * for any free VSIs in the list.
6402 *
6403 * find next empty vsi slot, looping back around if necessary
6404 */
6405 i = pf->next_vsi;
505682cd 6406 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6407 i++;
505682cd 6408 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6409 i = 0;
6410 while (i < pf->next_vsi && pf->vsi[i])
6411 i++;
6412 }
6413
505682cd 6414 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6415 vsi_idx = i; /* Found one! */
6416 } else {
6417 ret = -ENODEV;
493fb300 6418 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6419 }
6420 pf->next_vsi = ++i;
6421
6422 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6423 if (!vsi) {
6424 ret = -ENOMEM;
493fb300 6425 goto unlock_pf;
41c445ff
JB		 6426 }
6427 vsi->type = type;
6428 vsi->back = pf;
6429 set_bit(__I40E_DOWN, &vsi->state);
6430 vsi->flags = 0;
6431 vsi->idx = vsi_idx;
6432 vsi->rx_itr_setting = pf->rx_itr_default;
6433 vsi->tx_itr_setting = pf->tx_itr_default;
6434 vsi->netdev_registered = false;
6435 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6436 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6437 vsi->irqs_ready = false;
41c445ff 6438
9f65e15b
AD		 6439 ret = i40e_set_num_rings_in_vsi(vsi);
6440 if (ret)
6441 goto err_rings;
6442
bc7d338f 6443 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6444 if (ret)
9f65e15b 6445 goto err_rings;
493fb300 6446
41c445ff
JB		 6447 /* Setup default MSIX irq handler for VSI */
6448 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6449
6450 pf->vsi[vsi_idx] = vsi;
6451 ret = vsi_idx;
493fb300
AD		 6452 goto unlock_pf;
6453
9f65e15b 6454err_rings:
493fb300
AD		 6455 pf->next_vsi = i - 1;
6456 kfree(vsi);
6457unlock_pf:
41c445ff
JB		 6458 mutex_unlock(&pf->switch_mutex);
6459 return ret;
6460}
6461
f650a38b
ASJ		 6462/**
6463 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6464 * @type: VSI pointer
bc7d338f 6465 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6466 *
6467 * On error: returns error code (negative)
6468 * On success: returns 0
6469 **/
bc7d338f 6470static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6471{
6472 /* free the ring and vector containers */
bc7d338f
ASJ		 6473 if (free_qvectors) {
6474 kfree(vsi->q_vectors);
6475 vsi->q_vectors = NULL;
6476 }
f650a38b
ASJ		 6477 kfree(vsi->tx_rings);
6478 vsi->tx_rings = NULL;
6479 vsi->rx_rings = NULL;
6480}
6481
41c445ff
JB		 6482/**
6483 * i40e_vsi_clear - Deallocate the VSI provided
6484 * @vsi: the VSI being un-configured
6485 **/
6486static int i40e_vsi_clear(struct i40e_vsi *vsi)
6487{
6488 struct i40e_pf *pf;
6489
6490 if (!vsi)
6491 return 0;
6492
6493 if (!vsi->back)
6494 goto free_vsi;
6495 pf = vsi->back;
6496
6497 mutex_lock(&pf->switch_mutex);
6498 if (!pf->vsi[vsi->idx]) {
6499 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6500 vsi->idx, vsi->idx, vsi, vsi->type);
6501 goto unlock_vsi;
6502 }
6503
6504 if (pf->vsi[vsi->idx] != vsi) {
6505 dev_err(&pf->pdev->dev,
6506 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6507 pf->vsi[vsi->idx]->idx,
6508 pf->vsi[vsi->idx],
6509 pf->vsi[vsi->idx]->type,
6510 vsi->idx, vsi, vsi->type);
6511 goto unlock_vsi;
6512 }
6513
6514 /* updates the pf for this cleared vsi */
6515 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6516 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6517
bc7d338f 6518 i40e_vsi_free_arrays(vsi, true);
493fb300 6519
41c445ff
JB		 6520 pf->vsi[vsi->idx] = NULL;
6521 if (vsi->idx < pf->next_vsi)
6522 pf->next_vsi = vsi->idx;
6523
6524unlock_vsi:
6525 mutex_unlock(&pf->switch_mutex);
6526free_vsi:
6527 kfree(vsi);
6528
6529 return 0;
6530}
6531
9f65e15b
AD		 6532/**
6533 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6534 * @vsi: the VSI being cleaned
6535 **/
be1d5eea 6536static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6537{
6538 int i;
6539
8e9dca53 6540 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6541 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6542 kfree_rcu(vsi->tx_rings[i], rcu);
6543 vsi->tx_rings[i] = NULL;
6544 vsi->rx_rings[i] = NULL;
6545 }
be1d5eea 6546 }
9f65e15b
AD		 6547}
6548
41c445ff
JB		 6549/**
6550 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6551 * @vsi: the VSI being configured
6552 **/
6553static int i40e_alloc_rings(struct i40e_vsi *vsi)
6554{
e7046ee1 6555 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6556 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6557 int i;
6558
41c445ff 6559 /* Set basic values in the rings to be used later during open() */
d7397644 6560 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6561 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6562 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6563 if (!tx_ring)
6564 goto err_out;
41c445ff
JB		 6565
6566 tx_ring->queue_index = i;
6567 tx_ring->reg_idx = vsi->base_queue + i;
6568 tx_ring->ring_active = false;
6569 tx_ring->vsi = vsi;
6570 tx_ring->netdev = vsi->netdev;
6571 tx_ring->dev = &pf->pdev->dev;
6572 tx_ring->count = vsi->num_desc;
6573 tx_ring->size = 0;
6574 tx_ring->dcb_tc = 0;
9f65e15b 6575 vsi->tx_rings[i] = tx_ring;
41c445ff 6576
9f65e15b 6577 rx_ring = &tx_ring[1];
41c445ff
JB		 6578 rx_ring->queue_index = i;
6579 rx_ring->reg_idx = vsi->base_queue + i;
6580 rx_ring->ring_active = false;
6581 rx_ring->vsi = vsi;
6582 rx_ring->netdev = vsi->netdev;
6583 rx_ring->dev = &pf->pdev->dev;
6584 rx_ring->count = vsi->num_desc;
6585 rx_ring->size = 0;
6586 rx_ring->dcb_tc = 0;
6587 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6588 set_ring_16byte_desc_enabled(rx_ring);
6589 else
6590 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6591 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6592 }
6593
6594 return 0;
9f65e15b
AD		 6595
6596err_out:
6597 i40e_vsi_clear_rings(vsi);
6598 return -ENOMEM;
41c445ff
JB		 6599}
6600
6601/**
6602 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6603 * @pf: board private structure
6604 * @vectors: the number of MSI-X vectors to request
6605 *
6606 * Returns the number of vectors reserved, or error
6607 **/
6608static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6609{
7b37f376
AG		 6610 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6611 I40E_MIN_MSIX, vectors);
6612 if (vectors < 0) {
41c445ff 6613 dev_info(&pf->pdev->dev,
7b37f376 6614 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6615 vectors = 0;
6616 }
6617
6618 return vectors;
6619}
6620
6621/**
6622 * i40e_init_msix - Setup the MSIX capability
6623 * @pf: board private structure
6624 *
6625 * Work with the OS to set up the MSIX vectors needed.
6626 *
6627 * Returns 0 on success, negative on failure
6628 **/
6629static int i40e_init_msix(struct i40e_pf *pf)
6630{
6631 i40e_status err = 0;
6632 struct i40e_hw *hw = &pf->hw;
6633 int v_budget, i;
6634 int vec;
6635
6636 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6637 return -ENODEV;
6638
6639 /* The number of vectors we'll request will be comprised of:
6640 * - Add 1 for "other" cause for Admin Queue events, etc.
6641 * - The number of LAN queue pairs
f8ff1464
ASJ		 6642 * - Queues being used for RSS.
6643 * We don't need as many as max_rss_size vectors.
6644 * use rss_size instead in the calculation since that
6645 * is governed by number of cpus in the system.
6646 * - assumes symmetric Tx/Rx pairing
41c445ff 6647 * - The number of VMDq pairs
38e00438
VD		 6648#ifdef I40E_FCOE
6649 * - The number of FCOE qps.
6650#endif
41c445ff
JB		 6651 * Once we count this up, try the request.
6652 *
6653 * If we can't get what we want, we'll simplify to nearly nothing
6654 * and try again. If that still fails, we punt.
6655 */
f8ff1464 6656 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6657 pf->num_vmdq_msix = pf->num_vmdq_qps;
6658 v_budget = 1 + pf->num_lan_msix;
6659 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6660 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6661 v_budget++;
6662
38e00438
VD		 6663#ifdef I40E_FCOE
6664 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6665 pf->num_fcoe_msix = pf->num_fcoe_qps;
6666 v_budget += pf->num_fcoe_msix;
6667 }
6668
6669#endif
41c445ff
JB		 6670 /* Scale down if necessary, and the rings will share vectors */
6671 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6672
6673 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6674 GFP_KERNEL);
6675 if (!pf->msix_entries)
6676 return -ENOMEM;
6677
6678 for (i = 0; i < v_budget; i++)
6679 pf->msix_entries[i].entry = i;
6680 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6681
6682 if (vec != v_budget) {
6683 /* If we have limited resources, we will start with no vectors
6684 * for the special features and then allocate vectors to some
6685 * of these features based on the policy and at the end disable
6686 * the features that did not get any vectors.
6687 */
38e00438
VD		 6688#ifdef I40E_FCOE
6689 pf->num_fcoe_qps = 0;
6690 pf->num_fcoe_msix = 0;
6691#endif
a34977ba
ASJ		 6692 pf->num_vmdq_msix = 0;
6693 }
6694
41c445ff
JB		 6695 if (vec < I40E_MIN_MSIX) {
6696 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6697 kfree(pf->msix_entries);
6698 pf->msix_entries = NULL;
6699 return -ENODEV;
6700
6701 } else if (vec == I40E_MIN_MSIX) {
6702 /* Adjust for minimal MSIX use */
41c445ff
JB		 6703 pf->num_vmdq_vsis = 0;
6704 pf->num_vmdq_qps = 0;
41c445ff
JB		 6705 pf->num_lan_qps = 1;
6706 pf->num_lan_msix = 1;
6707
6708 } else if (vec != v_budget) {
a34977ba
ASJ		 6709 /* reserve the misc vector */
6710 vec--;
6711
41c445ff
JB		 6712 /* Scale vector usage down */
6713 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6714 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6715
6716 /* partition out the remaining vectors */
6717 switch (vec) {
6718 case 2:
41c445ff
JB		 6719 pf->num_lan_msix = 1;
6720 break;
6721 case 3:
38e00438
VD		 6722#ifdef I40E_FCOE
6723 /* give one vector to FCoE */
6724 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6725 pf->num_lan_msix = 1;
6726 pf->num_fcoe_msix = 1;
6727 }
6728#else
41c445ff 6729 pf->num_lan_msix = 2;
38e00438 6730#endif
41c445ff
JB		 6731 break;
6732 default:
38e00438
VD		 6733#ifdef I40E_FCOE
6734 /* give one vector to FCoE */
6735 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6736 pf->num_fcoe_msix = 1;
6737 vec--;
6738 }
6739#endif
41c445ff
JB		 6740 pf->num_lan_msix = min_t(int, (vec / 2),
6741 pf->num_lan_qps);
6742 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6743 I40E_DEFAULT_NUM_VMDQ_VSI);
6744 break;
6745 }
6746 }
6747
a34977ba
ASJ		 6748 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
6749 (pf->num_vmdq_msix == 0)) {
6750 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
6751 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6752 }
38e00438
VD		 6753#ifdef I40E_FCOE
6754
6755 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
6756 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
6757 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
6758 }
6759#endif
41c445ff
JB		 6760 return err;
6761}
6762
493fb300 6763/**
90e04070 6764 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6765 * @vsi: the VSI being configured
6766 * @v_idx: index of the vector in the vsi struct
6767 *
6768 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6769 **/
90e04070 6770static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6771{
6772 struct i40e_q_vector *q_vector;
6773
6774 /* allocate q_vector */
6775 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6776 if (!q_vector)
6777 return -ENOMEM;
6778
6779 q_vector->vsi = vsi;
6780 q_vector->v_idx = v_idx;
6781 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6782 if (vsi->netdev)
6783 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 6784 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 6785
cd0b6fa6
AD		 6786 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6787 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6788
493fb300
AD		 6789 /* tie q_vector and vsi together */
6790 vsi->q_vectors[v_idx] = q_vector;
6791
6792 return 0;
6793}
6794
41c445ff 6795/**
90e04070 6796 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6797 * @vsi: the VSI being configured
6798 *
6799 * We allocate one q_vector per queue interrupt. If allocation fails we
6800 * return -ENOMEM.
6801 **/
90e04070 6802static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6803{
6804 struct i40e_pf *pf = vsi->back;
6805 int v_idx, num_q_vectors;
493fb300 6806 int err;
41c445ff
JB		 6807
6808 /* if not MSIX, give the one vector only to the LAN VSI */
6809 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6810 num_q_vectors = vsi->num_q_vectors;
6811 else if (vsi == pf->vsi[pf->lan_vsi])
6812 num_q_vectors = 1;
6813 else
6814 return -EINVAL;
6815
41c445ff 6816 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6817 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6818 if (err)
6819 goto err_out;
41c445ff
JB		 6820 }
6821
6822 return 0;
493fb300
AD		 6823
6824err_out:
6825 while (v_idx--)
6826 i40e_free_q_vector(vsi, v_idx);
6827
6828 return err;
41c445ff
JB		 6829}
6830
6831/**
6832 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6833 * @pf: board private structure to initialize
6834 **/
6835static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6836{
6837 int err = 0;
6838
6839 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6840 err = i40e_init_msix(pf);
6841 if (err) {
60ea5f83 6842 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 6843#ifdef I40E_FCOE
6844 I40E_FLAG_FCOE_ENABLED |
6845#endif
60ea5f83 6846 I40E_FLAG_RSS_ENABLED |
4d9b6043 6847 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 6848 I40E_FLAG_SRIOV_ENABLED |
6849 I40E_FLAG_FD_SB_ENABLED |
6850 I40E_FLAG_FD_ATR_ENABLED |
6851 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6852
6853 /* rework the queue expectations without MSIX */
6854 i40e_determine_queue_usage(pf);
6855 }
6856 }
6857
6858 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6859 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6860 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6861 err = pci_enable_msi(pf->pdev);
6862 if (err) {
958a3e3b 6863 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6864 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6865 }
6866 }
6867
958a3e3b 6868 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6869 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6870
41c445ff
JB		 6871 /* track first vector for misc interrupts */
6872 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6873}
6874
6875/**
6876 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6877 * @pf: board private structure
6878 *
6879 * This sets up the handler for MSIX 0, which is used to manage the
6880 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6881 * when in MSI or Legacy interrupt mode.
6882 **/
6883static int i40e_setup_misc_vector(struct i40e_pf *pf)
6884{
6885 struct i40e_hw *hw = &pf->hw;
6886 int err = 0;
6887
6888 /* Only request the irq if this is the first time through, and
6889 * not when we're rebuilding after a Reset
6890 */
6891 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6892 err = request_irq(pf->msix_entries[0].vector,
6893 i40e_intr, 0, pf->misc_int_name, pf);
6894 if (err) {
6895 dev_info(&pf->pdev->dev,
77fa28be
CS		 6896 "request_irq for %s failed: %d\n",
6897 pf->misc_int_name, err);
41c445ff
JB		 6898 return -EFAULT;
6899 }
6900 }
6901
6902 i40e_enable_misc_int_causes(hw);
6903
6904 /* associate no queues to the misc vector */
6905 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6906 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6907
6908 i40e_flush(hw);
6909
6910 i40e_irq_dynamic_enable_icr0(pf);
6911
6912 return err;
6913}
6914
6915/**
6916 * i40e_config_rss - Prepare for RSS if used
6917 * @pf: board private structure
6918 **/
6919static int i40e_config_rss(struct i40e_pf *pf)
6920{
41c445ff
JB		 6921 /* Set of random keys generated using kernel random number generator */
6922 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6923 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6924 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6925 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6926 struct i40e_hw *hw = &pf->hw;
6927 u32 lut = 0;
6928 int i, j;
6929 u64 hena;
e157ea30 6930 u32 reg_val;
41c445ff
JB		 6931
6932 /* Fill out hash function seed */
6933 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6934 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6935
6936 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6937 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6938 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6939 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6940 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6941 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6942
e157ea30
CW		 6943 /* Check capability and Set table size and register per hw expectation*/
6944 reg_val = rd32(hw, I40E_PFQF_CTL_0);
6945 if (hw->func_caps.rss_table_size == 512) {
6946 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
6947 pf->rss_table_size = 512;
6948 } else {
6949 pf->rss_table_size = 128;
6950 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
6951 }
6952 wr32(hw, I40E_PFQF_CTL_0, reg_val);
6953
41c445ff 6954 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 6955 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 6956
6957 /* The assumption is that lan qp count will be the highest
6958 * qp count for any PF VSI that needs RSS.
6959 * If multiple VSIs need RSS support, all the qp counts
6960 * for those VSIs should be a power of 2 for RSS to work.
6961 * If LAN VSI is the only consumer for RSS then this requirement
6962 * is not necessary.
6963 */
6964 if (j == pf->rss_size)
6965 j = 0;
6966 /* lut = 4-byte sliding window of 4 lut entries */
6967 lut = (lut << 8) | (j &
6968 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6969 /* On i = 3, we have 4 entries in lut; write to the register */
6970 if ((i & 3) == 3)
6971 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6972 }
6973 i40e_flush(hw);
6974
6975 return 0;
6976}
6977
f8ff1464
ASJ		 6978/**
6979 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6980 * @pf: board private structure
6981 * @queue_count: the requested queue count for rss.
6982 *
6983 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6984 * count which may be different from the requested queue count.
6985 **/
6986int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6987{
6988 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6989 return 0;
6990
6991 queue_count = min_t(int, queue_count, pf->rss_size_max);
f8ff1464
ASJ		 6992
6993 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6994 i40e_prep_for_reset(pf);
6995
f8ff1464
ASJ		 6996 pf->rss_size = queue_count;
6997
6998 i40e_reset_and_rebuild(pf, true);
6999 i40e_config_rss(pf);
7000 }
7001 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7002 return pf->rss_size;
7003}
7004
41c445ff
JB		 7005/**
7006 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7007 * @pf: board private structure to initialize
7008 *
7009 * i40e_sw_init initializes the Adapter private data structure.
7010 * Fields are initialized based on PCI device information and
7011 * OS network device settings (MTU size).
7012 **/
7013static int i40e_sw_init(struct i40e_pf *pf)
7014{
7015 int err = 0;
7016 int size;
7017
7018 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7019 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7020 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7021 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7022 if (I40E_DEBUG_USER & debug)
7023 pf->hw.debug_mask = debug;
7024 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7025 I40E_DEFAULT_MSG_ENABLE);
7026 }
7027
7028 /* Set default capability flags */
7029 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7030 I40E_FLAG_MSI_ENABLED |
7031 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 7032 I40E_FLAG_RX_1BUF_ENABLED;
7033
ca99eb99
MW		 7034 /* Set default ITR */
7035 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7036 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7037
7134f9ce
JB		 7038 /* Depending on PF configurations, it is possible that the RSS
7039 * maximum might end up larger than the available queues
7040 */
41c445ff 7041 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7042 pf->rss_size = 1;
7134f9ce
JB		 7043 pf->rss_size_max = min_t(int, pf->rss_size_max,
7044 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7045 if (pf->hw.func_caps.rss) {
7046 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7047 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7048 }
7049
2050bc65
CS		 7050 /* MFP mode enabled */
7051 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7052 pf->flags |= I40E_FLAG_MFP_ENABLED;
7053 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
7054 }
7055
cbf61325
ASJ		 7056 /* FW/NVM is not yet fixed in this regard */
7057 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7058 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7059 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7060 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 7061 /* Setup a counter for fd_atr per pf */
7062 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7063 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7064 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 7065 /* Setup a counter for fd_sb per pf */
7066 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7067 } else {
7068 dev_info(&pf->pdev->dev,
0b67584f 7069 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7070 }
cbf61325
ASJ		 7071 pf->fdir_pf_filter_count =
7072 pf->hw.func_caps.fd_filters_guaranteed;
7073 pf->hw.fdir_shared_filter_count =
7074 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7075 }
7076
7077 if (pf->hw.func_caps.vmdq) {
7078 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7079 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7080 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7081 }
7082
38e00438
VD		 7083#ifdef I40E_FCOE
7084 err = i40e_init_pf_fcoe(pf);
7085 if (err)
7086 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7087
7088#endif /* I40E_FCOE */
41c445ff
JB		 7089#ifdef CONFIG_PCI_IOV
7090 if (pf->hw.func_caps.num_vfs) {
7091 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7092 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7093 pf->num_req_vfs = min_t(int,
7094 pf->hw.func_caps.num_vfs,
7095 I40E_MAX_VF_COUNT);
7096 }
7097#endif /* CONFIG_PCI_IOV */
7098 pf->eeprom_version = 0xDEAD;
7099 pf->lan_veb = I40E_NO_VEB;
7100 pf->lan_vsi = I40E_NO_VSI;
7101
7102 /* set up queue assignment tracking */
7103 size = sizeof(struct i40e_lump_tracking)
7104 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7105 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7106 if (!pf->qp_pile) {
7107 err = -ENOMEM;
7108 goto sw_init_done;
7109 }
7110 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7111 pf->qp_pile->search_hint = 0;
7112
7113 /* set up vector assignment tracking */
7114 size = sizeof(struct i40e_lump_tracking)
7115 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
7116 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7117 if (!pf->irq_pile) {
7118 kfree(pf->qp_pile);
7119 err = -ENOMEM;
7120 goto sw_init_done;
7121 }
7122 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
7123 pf->irq_pile->search_hint = 0;
7124
327fe04b
ASJ		 7125 pf->tx_timeout_recovery_level = 1;
7126
41c445ff
JB		 7127 mutex_init(&pf->switch_mutex);
7128
7129sw_init_done:
7130 return err;
7131}
7132
7c3c288b
ASJ		 7133/**
7134 * i40e_set_ntuple - set the ntuple feature flag and take action
7135 * @pf: board private structure to initialize
7136 * @features: the feature set that the stack is suggesting
7137 *
7138 * returns a bool to indicate if reset needs to happen
7139 **/
7140bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7141{
7142 bool need_reset = false;
7143
7144 /* Check if Flow Director n-tuple support was enabled or disabled. If
7145 * the state changed, we need to reset.
7146 */
7147 if (features & NETIF_F_NTUPLE) {
7148 /* Enable filters and mark for reset */
7149 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7150 need_reset = true;
7151 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7152 } else {
7153 /* turn off filters, mark for reset and clear SW filter list */
7154 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7155 need_reset = true;
7156 i40e_fdir_filter_exit(pf);
7157 }
7158 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7159 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7160 /* reset fd counters */
7161 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7162 pf->fdir_pf_active_filters = 0;
7163 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7164 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7165 /* if ATR was auto disabled it can be re-enabled. */
7166 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7167 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7168 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7169 }
7170 return need_reset;
7171}
7172
41c445ff
JB		 7173/**
7174 * i40e_set_features - set the netdev feature flags
7175 * @netdev: ptr to the netdev being adjusted
7176 * @features: the feature set that the stack is suggesting
7177 **/
7178static int i40e_set_features(struct net_device *netdev,
7179 netdev_features_t features)
7180{
7181 struct i40e_netdev_priv *np = netdev_priv(netdev);
7182 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7183 struct i40e_pf *pf = vsi->back;
7184 bool need_reset;
41c445ff
JB		 7185
7186 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7187 i40e_vlan_stripping_enable(vsi);
7188 else
7189 i40e_vlan_stripping_disable(vsi);
7190
7c3c288b
ASJ		 7191 need_reset = i40e_set_ntuple(pf, features);
7192
7193 if (need_reset)
7194 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7195
41c445ff
JB		 7196 return 0;
7197}
7198
a1c9a9d9
JK		 7199#ifdef CONFIG_I40E_VXLAN
7200/**
7201 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7202 * @pf: board private structure
7203 * @port: The UDP port to look up
7204 *
7205 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7206 **/
7207static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7208{
7209 u8 i;
7210
7211 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7212 if (pf->vxlan_ports[i] == port)
7213 return i;
7214 }
7215
7216 return i;
7217}
7218
7219/**
7220 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7221 * @netdev: This physical port's netdev
7222 * @sa_family: Socket Family that VXLAN is notifying us about
7223 * @port: New UDP port number that VXLAN started listening to
7224 **/
7225static void i40e_add_vxlan_port(struct net_device *netdev,
7226 sa_family_t sa_family, __be16 port)
7227{
7228 struct i40e_netdev_priv *np = netdev_priv(netdev);
7229 struct i40e_vsi *vsi = np->vsi;
7230 struct i40e_pf *pf = vsi->back;
7231 u8 next_idx;
7232 u8 idx;
7233
7234 if (sa_family == AF_INET6)
7235 return;
7236
7237 idx = i40e_get_vxlan_port_idx(pf, port);
7238
7239 /* Check if port already exists */
7240 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7241 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7242 return;
7243 }
7244
7245 /* Now check if there is space to add the new port */
7246 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7247
7248 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7249 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7250 ntohs(port));
7251 return;
7252 }
7253
7254 /* New port: add it and mark its index in the bitmap */
7255 pf->vxlan_ports[next_idx] = port;
7256 pf->pending_vxlan_bitmap |= (1 << next_idx);
7257
7258 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7259}
7260
7261/**
7262 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7263 * @netdev: This physical port's netdev
7264 * @sa_family: Socket Family that VXLAN is notifying us about
7265 * @port: UDP port number that VXLAN stopped listening to
7266 **/
7267static void i40e_del_vxlan_port(struct net_device *netdev,
7268 sa_family_t sa_family, __be16 port)
7269{
7270 struct i40e_netdev_priv *np = netdev_priv(netdev);
7271 struct i40e_vsi *vsi = np->vsi;
7272 struct i40e_pf *pf = vsi->back;
7273 u8 idx;
7274
7275 if (sa_family == AF_INET6)
7276 return;
7277
7278 idx = i40e_get_vxlan_port_idx(pf, port);
7279
7280 /* Check if port already exists */
7281 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7282 /* if port exists, set it to 0 (mark for deletion)
7283 * and make it pending
7284 */
7285 pf->vxlan_ports[idx] = 0;
7286
7287 pf->pending_vxlan_bitmap |= (1 << idx);
7288
7289 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7290 } else {
7291 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7292 ntohs(port));
7293 }
7294}
7295
7296#endif
1f224ad2
NP		 7297static int i40e_get_phys_port_id(struct net_device *netdev,
7298 struct netdev_phys_port_id *ppid)
7299{
7300 struct i40e_netdev_priv *np = netdev_priv(netdev);
7301 struct i40e_pf *pf = np->vsi->back;
7302 struct i40e_hw *hw = &pf->hw;
7303
7304 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7305 return -EOPNOTSUPP;
7306
7307 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7308 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7309
7310 return 0;
7311}
7312
4ba0dea5
GR		 7313#ifdef HAVE_FDB_OPS
7314#ifdef USE_CONST_DEV_UC_CHAR
7315static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7316 struct net_device *dev,
7317 const unsigned char *addr,
7318 u16 flags)
7319#else
7320static int i40e_ndo_fdb_add(struct ndmsg *ndm,
7321 struct net_device *dev,
7322 unsigned char *addr,
7323 u16 flags)
7324#endif
7325{
7326 struct i40e_netdev_priv *np = netdev_priv(dev);
7327 struct i40e_pf *pf = np->vsi->back;
7328 int err = 0;
7329
7330 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7331 return -EOPNOTSUPP;
7332
7333 /* Hardware does not support aging addresses so if a
7334 * ndm_state is given only allow permanent addresses
7335 */
7336 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7337 netdev_info(dev, "FDB only supports static addresses\n");
7338 return -EINVAL;
7339 }
7340
7341 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7342 err = dev_uc_add_excl(dev, addr);
7343 else if (is_multicast_ether_addr(addr))
7344 err = dev_mc_add_excl(dev, addr);
7345 else
7346 err = -EINVAL;
7347
7348 /* Only return duplicate errors if NLM_F_EXCL is set */
7349 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7350 err = 0;
7351
7352 return err;
7353}
7354
7355#ifndef USE_DEFAULT_FDB_DEL_DUMP
7356#ifdef USE_CONST_DEV_UC_CHAR
7357static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7358 struct net_device *dev,
7359 const unsigned char *addr)
7360#else
7361static int i40e_ndo_fdb_del(struct ndmsg *ndm,
7362 struct net_device *dev,
7363 unsigned char *addr)
7364#endif
7365{
7366 struct i40e_netdev_priv *np = netdev_priv(dev);
7367 struct i40e_pf *pf = np->vsi->back;
7368 int err = -EOPNOTSUPP;
7369
7370 if (ndm->ndm_state & NUD_PERMANENT) {
7371 netdev_info(dev, "FDB only supports static addresses\n");
7372 return -EINVAL;
7373 }
7374
7375 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7376 if (is_unicast_ether_addr(addr))
7377 err = dev_uc_del(dev, addr);
7378 else if (is_multicast_ether_addr(addr))
7379 err = dev_mc_del(dev, addr);
7380 else
7381 err = -EINVAL;
7382 }
7383
7384 return err;
7385}
7386
7387static int i40e_ndo_fdb_dump(struct sk_buff *skb,
7388 struct netlink_callback *cb,
7389 struct net_device *dev,
5d5eacb3 7390 struct net_device *filter_dev,
4ba0dea5
GR		 7391 int idx)
7392{
7393 struct i40e_netdev_priv *np = netdev_priv(dev);
7394 struct i40e_pf *pf = np->vsi->back;
7395
7396 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
5d5eacb3 7397 idx = ndo_dflt_fdb_dump(skb, cb, dev, filter_dev, idx);
4ba0dea5
GR		 7398
7399 return idx;
7400}
7401
7402#endif /* USE_DEFAULT_FDB_DEL_DUMP */
7403#endif /* HAVE_FDB_OPS */
41c445ff
JB		 7404static const struct net_device_ops i40e_netdev_ops = {
7405 .ndo_open = i40e_open,
7406 .ndo_stop = i40e_close,
7407 .ndo_start_xmit = i40e_lan_xmit_frame,
7408 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7409 .ndo_set_rx_mode = i40e_set_rx_mode,
7410 .ndo_validate_addr = eth_validate_addr,
7411 .ndo_set_mac_address = i40e_set_mac,
7412 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7413 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7414 .ndo_tx_timeout = i40e_tx_timeout,
7415 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7416 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7417#ifdef CONFIG_NET_POLL_CONTROLLER
7418 .ndo_poll_controller = i40e_netpoll,
7419#endif
7420 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 7421#ifdef I40E_FCOE
7422 .ndo_fcoe_enable = i40e_fcoe_enable,
7423 .ndo_fcoe_disable = i40e_fcoe_disable,
7424#endif
41c445ff
JB		 7425 .ndo_set_features = i40e_set_features,
7426 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7427 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7428 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7429 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7430 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
c674d125 7431 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofck,
a1c9a9d9
JK		 7432#ifdef CONFIG_I40E_VXLAN
7433 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7434 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7435#endif
1f224ad2 7436 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5
GR		 7437#ifdef HAVE_FDB_OPS
7438 .ndo_fdb_add = i40e_ndo_fdb_add,
7439#ifndef USE_DEFAULT_FDB_DEL_DUMP
7440 .ndo_fdb_del = i40e_ndo_fdb_del,
7441 .ndo_fdb_dump = i40e_ndo_fdb_dump,
7442#endif
7443#endif
41c445ff
JB		 7444};
7445
7446/**
7447 * i40e_config_netdev - Setup the netdev flags
7448 * @vsi: the VSI being configured
7449 *
7450 * Returns 0 on success, negative value on failure
7451 **/
7452static int i40e_config_netdev(struct i40e_vsi *vsi)
7453{
1a10370a 7454 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7455 struct i40e_pf *pf = vsi->back;
7456 struct i40e_hw *hw = &pf->hw;
7457 struct i40e_netdev_priv *np;
7458 struct net_device *netdev;
7459 u8 mac_addr[ETH_ALEN];
7460 int etherdev_size;
7461
7462 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7463 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7464 if (!netdev)
7465 return -ENOMEM;
7466
7467 vsi->netdev = netdev;
7468 np = netdev_priv(netdev);
7469 np->vsi = vsi;
7470
d70e941b 7471 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7472 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7473 NETIF_F_TSO;
41c445ff
JB		 7474
7475 netdev->features = NETIF_F_SG |
7476 NETIF_F_IP_CSUM |
7477 NETIF_F_SCTP_CSUM |
7478 NETIF_F_HIGHDMA |
7479 NETIF_F_GSO_UDP_TUNNEL |
7480 NETIF_F_HW_VLAN_CTAG_TX |
7481 NETIF_F_HW_VLAN_CTAG_RX |
7482 NETIF_F_HW_VLAN_CTAG_FILTER |
7483 NETIF_F_IPV6_CSUM |
7484 NETIF_F_TSO |
059dab69 7485 NETIF_F_TSO_ECN |
41c445ff
JB		 7486 NETIF_F_TSO6 |
7487 NETIF_F_RXCSUM |
7488 NETIF_F_RXHASH |
7489 0;
7490
2e86a0b6
ASJ		 7491 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7492 netdev->features |= NETIF_F_NTUPLE;
7493
41c445ff
JB		 7494 /* copy netdev features into list of user selectable features */
7495 netdev->hw_features |= netdev->features;
7496
7497 if (vsi->type == I40E_VSI_MAIN) {
7498 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7499 ether_addr_copy(mac_addr, hw->mac.perm_addr);
8c27d42e
GR		 7500 /* The following two steps are necessary to prevent reception
7501 * of tagged packets - by default the NVM loads a MAC-VLAN
7502 * filter that will accept any tagged packet. This is to
7503 * prevent that during normal operations until a specific
7504 * VLAN tag filter has been set.
7505 */
7506 i40e_rm_default_mac_filter(vsi, mac_addr);
7507 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, true);
41c445ff
JB		 7508 } else {
7509 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7510 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7511 pf->vsi[pf->lan_vsi]->netdev->name);
7512 random_ether_addr(mac_addr);
7513 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7514 }
1a10370a 7515 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7516
9a173901
GR		 7517 ether_addr_copy(netdev->dev_addr, mac_addr);
7518 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 7519 /* vlan gets same features (except vlan offload)
7520 * after any tweaks for specific VSI types
7521 */
7522 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
7523 NETIF_F_HW_VLAN_CTAG_RX |
7524 NETIF_F_HW_VLAN_CTAG_FILTER);
7525 netdev->priv_flags |= IFF_UNICAST_FLT;
7526 netdev->priv_flags |= IFF_SUPP_NOFCS;
7527 /* Setup netdev TC information */
7528 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
7529
7530 netdev->netdev_ops = &i40e_netdev_ops;
7531 netdev->watchdog_timeo = 5 * HZ;
7532 i40e_set_ethtool_ops(netdev);
38e00438
VD		 7533#ifdef I40E_FCOE
7534 i40e_fcoe_config_netdev(netdev, vsi);
7535#endif
41c445ff
JB		 7536
7537 return 0;
7538}
7539
7540/**
7541 * i40e_vsi_delete - Delete a VSI from the switch
7542 * @vsi: the VSI being removed
7543 *
7544 * Returns 0 on success, negative value on failure
7545 **/
7546static void i40e_vsi_delete(struct i40e_vsi *vsi)
7547{
7548 /* remove default VSI is not allowed */
7549 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
7550 return;
7551
41c445ff 7552 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 7553}
7554
7555/**
7556 * i40e_add_vsi - Add a VSI to the switch
7557 * @vsi: the VSI being configured
7558 *
7559 * This initializes a VSI context depending on the VSI type to be added and
7560 * passes it down to the add_vsi aq command.
7561 **/
7562static int i40e_add_vsi(struct i40e_vsi *vsi)
7563{
7564 int ret = -ENODEV;
7565 struct i40e_mac_filter *f, *ftmp;
7566 struct i40e_pf *pf = vsi->back;
7567 struct i40e_hw *hw = &pf->hw;
7568 struct i40e_vsi_context ctxt;
7569 u8 enabled_tc = 0x1; /* TC0 enabled */
7570 int f_count = 0;
7571
7572 memset(&ctxt, 0, sizeof(ctxt));
7573 switch (vsi->type) {
7574 case I40E_VSI_MAIN:
7575 /* The PF's main VSI is already setup as part of the
7576 * device initialization, so we'll not bother with
7577 * the add_vsi call, but we will retrieve the current
7578 * VSI context.
7579 */
7580 ctxt.seid = pf->main_vsi_seid;
7581 ctxt.pf_num = pf->hw.pf_id;
7582 ctxt.vf_num = 0;
7583 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7584 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7585 if (ret) {
7586 dev_info(&pf->pdev->dev,
7587 "couldn't get pf vsi config, err %d, aq_err %d\n",
7588 ret, pf->hw.aq.asq_last_status);
7589 return -ENOENT;
7590 }
7591 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7592 vsi->info.valid_sections = 0;
7593
7594 vsi->seid = ctxt.seid;
7595 vsi->id = ctxt.vsi_number;
7596
7597 enabled_tc = i40e_pf_get_tc_map(pf);
7598
7599 /* MFP mode setup queue map and update VSI */
7600 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7601 memset(&ctxt, 0, sizeof(ctxt));
7602 ctxt.seid = pf->main_vsi_seid;
7603 ctxt.pf_num = pf->hw.pf_id;
7604 ctxt.vf_num = 0;
7605 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7606 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7607 if (ret) {
7608 dev_info(&pf->pdev->dev,
7609 "update vsi failed, aq_err=%d\n",
7610 pf->hw.aq.asq_last_status);
7611 ret = -ENOENT;
7612 goto err;
7613 }
7614 /* update the local VSI info queue map */
7615 i40e_vsi_update_queue_map(vsi, &ctxt);
7616 vsi->info.valid_sections = 0;
7617 } else {
7618 /* Default/Main VSI is only enabled for TC0
7619 * reconfigure it to enable all TCs that are
7620 * available on the port in SFP mode.
7621 */
7622 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7623 if (ret) {
7624 dev_info(&pf->pdev->dev,
7625 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7626 enabled_tc, ret,
7627 pf->hw.aq.asq_last_status);
7628 ret = -ENOENT;
7629 }
7630 }
7631 break;
7632
7633 case I40E_VSI_FDIR:
cbf61325
ASJ		 7634 ctxt.pf_num = hw->pf_id;
7635 ctxt.vf_num = 0;
7636 ctxt.uplink_seid = vsi->uplink_seid;
7637 ctxt.connection_type = 0x1; /* regular data port */
7638 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7639 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7640 break;
7641
7642 case I40E_VSI_VMDQ2:
7643 ctxt.pf_num = hw->pf_id;
7644 ctxt.vf_num = 0;
7645 ctxt.uplink_seid = vsi->uplink_seid;
7646 ctxt.connection_type = 0x1; /* regular data port */
7647 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7648
7649 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7650
7651 /* This VSI is connected to VEB so the switch_id
7652 * should be set to zero by default.
7653 */
7654 ctxt.info.switch_id = 0;
41c445ff
JB		 7655 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7656
7657 /* Setup the VSI tx/rx queue map for TC0 only for now */
7658 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7659 break;
7660
7661 case I40E_VSI_SRIOV:
7662 ctxt.pf_num = hw->pf_id;
7663 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7664 ctxt.uplink_seid = vsi->uplink_seid;
7665 ctxt.connection_type = 0x1; /* regular data port */
7666 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7667
7668 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7669
7670 /* This VSI is connected to VEB so the switch_id
7671 * should be set to zero by default.
7672 */
7673 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7674
7675 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7676 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 7677 if (pf->vf[vsi->vf_id].spoofchk) {
7678 ctxt.info.valid_sections |=
7679 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
7680 ctxt.info.sec_flags |=
7681 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
7682 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
7683 }
41c445ff
JB		 7684 /* Setup the VSI tx/rx queue map for TC0 only for now */
7685 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7686 break;
7687
38e00438
VD		 7688#ifdef I40E_FCOE
7689 case I40E_VSI_FCOE:
7690 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
7691 if (ret) {
7692 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
7693 return ret;
7694 }
7695 break;
7696
7697#endif /* I40E_FCOE */
41c445ff
JB		 7698 default:
7699 return -ENODEV;
7700 }
7701
7702 if (vsi->type != I40E_VSI_MAIN) {
7703 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7704 if (ret) {
7705 dev_info(&vsi->back->pdev->dev,
7706 "add vsi failed, aq_err=%d\n",
7707 vsi->back->hw.aq.asq_last_status);
7708 ret = -ENOENT;
7709 goto err;
7710 }
7711 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7712 vsi->info.valid_sections = 0;
7713 vsi->seid = ctxt.seid;
7714 vsi->id = ctxt.vsi_number;
7715 }
7716
7717 /* If macvlan filters already exist, force them to get loaded */
7718 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7719 f->changed = true;
7720 f_count++;
6252c7e4
SN		 7721
7722 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
7723 i40e_aq_mac_address_write(&vsi->back->hw,
7724 I40E_AQC_WRITE_TYPE_LAA_WOL,
7725 f->macaddr, NULL);
7726 }
41c445ff
JB		 7727 }
7728 if (f_count) {
7729 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7730 pf->flags |= I40E_FLAG_FILTER_SYNC;
7731 }
7732
7733 /* Update VSI BW information */
7734 ret = i40e_vsi_get_bw_info(vsi);
7735 if (ret) {
7736 dev_info(&pf->pdev->dev,
7737 "couldn't get vsi bw info, err %d, aq_err %d\n",
7738 ret, pf->hw.aq.asq_last_status);
7739 /* VSI is already added so not tearing that up */
7740 ret = 0;
7741 }
7742
7743err:
7744 return ret;
7745}
7746
7747/**
7748 * i40e_vsi_release - Delete a VSI and free its resources
7749 * @vsi: the VSI being removed
7750 *
7751 * Returns 0 on success or < 0 on error
7752 **/
7753int i40e_vsi_release(struct i40e_vsi *vsi)
7754{
7755 struct i40e_mac_filter *f, *ftmp;
7756 struct i40e_veb *veb = NULL;
7757 struct i40e_pf *pf;
7758 u16 uplink_seid;
7759 int i, n;
7760
7761 pf = vsi->back;
7762
7763 /* release of a VEB-owner or last VSI is not allowed */
7764 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7765 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7766 vsi->seid, vsi->uplink_seid);
7767 return -ENODEV;
7768 }
7769 if (vsi == pf->vsi[pf->lan_vsi] &&
7770 !test_bit(__I40E_DOWN, &pf->state)) {
7771 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7772 return -ENODEV;
7773 }
7774
7775 uplink_seid = vsi->uplink_seid;
7776 if (vsi->type != I40E_VSI_SRIOV) {
7777 if (vsi->netdev_registered) {
7778 vsi->netdev_registered = false;
7779 if (vsi->netdev) {
7780 /* results in a call to i40e_close() */
7781 unregister_netdev(vsi->netdev);
41c445ff
JB		 7782 }
7783 } else {
90ef8d47 7784 i40e_vsi_close(vsi);
41c445ff
JB		 7785 }
7786 i40e_vsi_disable_irq(vsi);
7787 }
7788
7789 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7790 i40e_del_filter(vsi, f->macaddr, f->vlan,
7791 f->is_vf, f->is_netdev);
7792 i40e_sync_vsi_filters(vsi);
7793
7794 i40e_vsi_delete(vsi);
7795 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7796 if (vsi->netdev) {
7797 free_netdev(vsi->netdev);
7798 vsi->netdev = NULL;
7799 }
41c445ff
JB		 7800 i40e_vsi_clear_rings(vsi);
7801 i40e_vsi_clear(vsi);
7802
7803 /* If this was the last thing on the VEB, except for the
7804 * controlling VSI, remove the VEB, which puts the controlling
7805 * VSI onto the next level down in the switch.
7806 *
7807 * Well, okay, there's one more exception here: don't remove
7808 * the orphan VEBs yet. We'll wait for an explicit remove request
7809 * from up the network stack.
7810 */
505682cd 7811 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7812 if (pf->vsi[i] &&
7813 pf->vsi[i]->uplink_seid == uplink_seid &&
7814 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7815 n++; /* count the VSIs */
7816 }
7817 }
7818 for (i = 0; i < I40E_MAX_VEB; i++) {
7819 if (!pf->veb[i])
7820 continue;
7821 if (pf->veb[i]->uplink_seid == uplink_seid)
7822 n++; /* count the VEBs */
7823 if (pf->veb[i]->seid == uplink_seid)
7824 veb = pf->veb[i];
7825 }
7826 if (n == 0 && veb && veb->uplink_seid != 0)
7827 i40e_veb_release(veb);
7828
7829 return 0;
7830}
7831
7832/**
7833 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7834 * @vsi: ptr to the VSI
7835 *
7836 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7837 * corresponding SW VSI structure and initializes num_queue_pairs for the
7838 * newly allocated VSI.
7839 *
7840 * Returns 0 on success or negative on failure
7841 **/
7842static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7843{
7844 int ret = -ENOENT;
7845 struct i40e_pf *pf = vsi->back;
7846
493fb300 7847 if (vsi->q_vectors[0]) {
41c445ff
JB		 7848 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7849 vsi->seid);
7850 return -EEXIST;
7851 }
7852
7853 if (vsi->base_vector) {
f29eaa3d 7854 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7855 vsi->seid, vsi->base_vector);
7856 return -EEXIST;
7857 }
7858
90e04070 7859 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7860 if (ret) {
7861 dev_info(&pf->pdev->dev,
7862 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7863 vsi->num_q_vectors, vsi->seid, ret);
7864 vsi->num_q_vectors = 0;
7865 goto vector_setup_out;
7866 }
7867
958a3e3b
SN		 7868 if (vsi->num_q_vectors)
7869 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7870 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7871 if (vsi->base_vector < 0) {
7872 dev_info(&pf->pdev->dev,
f29eaa3d 7873 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7874 vsi->seid, vsi->base_vector);
7875 i40e_vsi_free_q_vectors(vsi);
7876 ret = -ENOENT;
7877 goto vector_setup_out;
7878 }
7879
7880vector_setup_out:
7881 return ret;
7882}
7883
bc7d338f
ASJ		 7884/**
7885 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7886 * @vsi: pointer to the vsi.
7887 *
7888 * This re-allocates a vsi's queue resources.
7889 *
7890 * Returns pointer to the successfully allocated and configured VSI sw struct
7891 * on success, otherwise returns NULL on failure.
7892 **/
7893static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7894{
7895 struct i40e_pf *pf = vsi->back;
7896 u8 enabled_tc;
7897 int ret;
7898
7899 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7900 i40e_vsi_clear_rings(vsi);
7901
7902 i40e_vsi_free_arrays(vsi, false);
7903 i40e_set_num_rings_in_vsi(vsi);
7904 ret = i40e_vsi_alloc_arrays(vsi, false);
7905 if (ret)
7906 goto err_vsi;
7907
7908 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7909 if (ret < 0) {
7910 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7911 vsi->seid, ret);
7912 goto err_vsi;
7913 }
7914 vsi->base_queue = ret;
7915
7916 /* Update the FW view of the VSI. Force a reset of TC and queue
7917 * layout configurations.
7918 */
7919 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7920 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7921 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7922 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7923
7924 /* assign it some queues */
7925 ret = i40e_alloc_rings(vsi);
7926 if (ret)
7927 goto err_rings;
7928
7929 /* map all of the rings to the q_vectors */
7930 i40e_vsi_map_rings_to_vectors(vsi);
7931 return vsi;
7932
7933err_rings:
7934 i40e_vsi_free_q_vectors(vsi);
7935 if (vsi->netdev_registered) {
7936 vsi->netdev_registered = false;
7937 unregister_netdev(vsi->netdev);
7938 free_netdev(vsi->netdev);
7939 vsi->netdev = NULL;
7940 }
7941 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7942err_vsi:
7943 i40e_vsi_clear(vsi);
7944 return NULL;
7945}
7946
41c445ff
JB		 7947/**
7948 * i40e_vsi_setup - Set up a VSI by a given type
7949 * @pf: board private structure
7950 * @type: VSI type
7951 * @uplink_seid: the switch element to link to
7952 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7953 *
7954 * This allocates the sw VSI structure and its queue resources, then add a VSI
7955 * to the identified VEB.
7956 *
7957 * Returns pointer to the successfully allocated and configure VSI sw struct on
7958 * success, otherwise returns NULL on failure.
7959 **/
7960struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7961 u16 uplink_seid, u32 param1)
7962{
7963 struct i40e_vsi *vsi = NULL;
7964 struct i40e_veb *veb = NULL;
7965 int ret, i;
7966 int v_idx;
7967
7968 /* The requested uplink_seid must be either
7969 * - the PF's port seid
7970 * no VEB is needed because this is the PF
7971 * or this is a Flow Director special case VSI
7972 * - seid of an existing VEB
7973 * - seid of a VSI that owns an existing VEB
7974 * - seid of a VSI that doesn't own a VEB
7975 * a new VEB is created and the VSI becomes the owner
7976 * - seid of the PF VSI, which is what creates the first VEB
7977 * this is a special case of the previous
7978 *
7979 * Find which uplink_seid we were given and create a new VEB if needed
7980 */
7981 for (i = 0; i < I40E_MAX_VEB; i++) {
7982 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7983 veb = pf->veb[i];
7984 break;
7985 }
7986 }
7987
7988 if (!veb && uplink_seid != pf->mac_seid) {
7989
505682cd 7990 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7991 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7992 vsi = pf->vsi[i];
7993 break;
7994 }
7995 }
7996 if (!vsi) {
7997 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7998 uplink_seid);
7999 return NULL;
8000 }
8001
8002 if (vsi->uplink_seid == pf->mac_seid)
8003 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8004 vsi->tc_config.enabled_tc);
8005 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8006 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8007 vsi->tc_config.enabled_tc);
8008
8009 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8010 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8011 veb = pf->veb[i];
8012 }
8013 if (!veb) {
8014 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8015 return NULL;
8016 }
8017
8018 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8019 uplink_seid = veb->seid;
8020 }
8021
8022 /* get vsi sw struct */
8023 v_idx = i40e_vsi_mem_alloc(pf, type);
8024 if (v_idx < 0)
8025 goto err_alloc;
8026 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8027 if (!vsi)
8028 goto err_alloc;
41c445ff
JB		 8029 vsi->type = type;
8030 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8031
8032 if (type == I40E_VSI_MAIN)
8033 pf->lan_vsi = v_idx;
8034 else if (type == I40E_VSI_SRIOV)
8035 vsi->vf_id = param1;
8036 /* assign it some queues */
cbf61325
ASJ		 8037 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8038 vsi->idx);
41c445ff
JB		 8039 if (ret < 0) {
8040 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
8041 vsi->seid, ret);
8042 goto err_vsi;
8043 }
8044 vsi->base_queue = ret;
8045
8046 /* get a VSI from the hardware */
8047 vsi->uplink_seid = uplink_seid;
8048 ret = i40e_add_vsi(vsi);
8049 if (ret)
8050 goto err_vsi;
8051
8052 switch (vsi->type) {
8053 /* setup the netdev if needed */
8054 case I40E_VSI_MAIN:
8055 case I40E_VSI_VMDQ2:
38e00438 8056 case I40E_VSI_FCOE:
41c445ff
JB		 8057 ret = i40e_config_netdev(vsi);
8058 if (ret)
8059 goto err_netdev;
8060 ret = register_netdev(vsi->netdev);
8061 if (ret)
8062 goto err_netdev;
8063 vsi->netdev_registered = true;
8064 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8065#ifdef CONFIG_I40E_DCB
8066 /* Setup DCB netlink interface */
8067 i40e_dcbnl_setup(vsi);
8068#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8069 /* fall through */
8070
8071 case I40E_VSI_FDIR:
8072 /* set up vectors and rings if needed */
8073 ret = i40e_vsi_setup_vectors(vsi);
8074 if (ret)
8075 goto err_msix;
8076
8077 ret = i40e_alloc_rings(vsi);
8078 if (ret)
8079 goto err_rings;
8080
8081 /* map all of the rings to the q_vectors */
8082 i40e_vsi_map_rings_to_vectors(vsi);
8083
8084 i40e_vsi_reset_stats(vsi);
8085 break;
8086
8087 default:
8088 /* no netdev or rings for the other VSI types */
8089 break;
8090 }
8091
8092 return vsi;
8093
8094err_rings:
8095 i40e_vsi_free_q_vectors(vsi);
8096err_msix:
8097 if (vsi->netdev_registered) {
8098 vsi->netdev_registered = false;
8099 unregister_netdev(vsi->netdev);
8100 free_netdev(vsi->netdev);
8101 vsi->netdev = NULL;
8102 }
8103err_netdev:
8104 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8105err_vsi:
8106 i40e_vsi_clear(vsi);
8107err_alloc:
8108 return NULL;
8109}
8110
8111/**
8112 * i40e_veb_get_bw_info - Query VEB BW information
8113 * @veb: the veb to query
8114 *
8115 * Query the Tx scheduler BW configuration data for given VEB
8116 **/
8117static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8118{
8119 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8120 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8121 struct i40e_pf *pf = veb->pf;
8122 struct i40e_hw *hw = &pf->hw;
8123 u32 tc_bw_max;
8124 int ret = 0;
8125 int i;
8126
8127 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8128 &bw_data, NULL);
8129 if (ret) {
8130 dev_info(&pf->pdev->dev,
8131 "query veb bw config failed, aq_err=%d\n",
8132 hw->aq.asq_last_status);
8133 goto out;
8134 }
8135
8136 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8137 &ets_data, NULL);
8138 if (ret) {
8139 dev_info(&pf->pdev->dev,
8140 "query veb bw ets config failed, aq_err=%d\n",
8141 hw->aq.asq_last_status);
8142 goto out;
8143 }
8144
8145 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8146 veb->bw_max_quanta = ets_data.tc_bw_max;
8147 veb->is_abs_credits = bw_data.absolute_credits_enable;
8148 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8149 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8150 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8151 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8152 veb->bw_tc_limit_credits[i] =
8153 le16_to_cpu(bw_data.tc_bw_limits[i]);
8154 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8155 }
8156
8157out:
8158 return ret;
8159}
8160
8161/**
8162 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8163 * @pf: board private structure
8164 *
8165 * On error: returns error code (negative)
8166 * On success: returns vsi index in PF (positive)
8167 **/
8168static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8169{
8170 int ret = -ENOENT;
8171 struct i40e_veb *veb;
8172 int i;
8173
8174 /* Need to protect the allocation of switch elements at the PF level */
8175 mutex_lock(&pf->switch_mutex);
8176
8177 /* VEB list may be fragmented if VEB creation/destruction has
8178 * been happening. We can afford to do a quick scan to look
8179 * for any free slots in the list.
8180 *
8181 * find next empty veb slot, looping back around if necessary
8182 */
8183 i = 0;
8184 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8185 i++;
8186 if (i >= I40E_MAX_VEB) {
8187 ret = -ENOMEM;
8188 goto err_alloc_veb; /* out of VEB slots! */
8189 }
8190
8191 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8192 if (!veb) {
8193 ret = -ENOMEM;
8194 goto err_alloc_veb;
8195 }
8196 veb->pf = pf;
8197 veb->idx = i;
8198 veb->enabled_tc = 1;
8199
8200 pf->veb[i] = veb;
8201 ret = i;
8202err_alloc_veb:
8203 mutex_unlock(&pf->switch_mutex);
8204 return ret;
8205}
8206
8207/**
8208 * i40e_switch_branch_release - Delete a branch of the switch tree
8209 * @branch: where to start deleting
8210 *
8211 * This uses recursion to find the tips of the branch to be
8212 * removed, deleting until we get back to and can delete this VEB.
8213 **/
8214static void i40e_switch_branch_release(struct i40e_veb *branch)
8215{
8216 struct i40e_pf *pf = branch->pf;
8217 u16 branch_seid = branch->seid;
8218 u16 veb_idx = branch->idx;
8219 int i;
8220
8221 /* release any VEBs on this VEB - RECURSION */
8222 for (i = 0; i < I40E_MAX_VEB; i++) {
8223 if (!pf->veb[i])
8224 continue;
8225 if (pf->veb[i]->uplink_seid == branch->seid)
8226 i40e_switch_branch_release(pf->veb[i]);
8227 }
8228
8229 /* Release the VSIs on this VEB, but not the owner VSI.
8230 *
8231 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8232 * the VEB itself, so don't use (*branch) after this loop.
8233 */
505682cd 8234 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8235 if (!pf->vsi[i])
8236 continue;
8237 if (pf->vsi[i]->uplink_seid == branch_seid &&
8238 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8239 i40e_vsi_release(pf->vsi[i]);
8240 }
8241 }
8242
8243 /* There's one corner case where the VEB might not have been
8244 * removed, so double check it here and remove it if needed.
8245 * This case happens if the veb was created from the debugfs
8246 * commands and no VSIs were added to it.
8247 */
8248 if (pf->veb[veb_idx])
8249 i40e_veb_release(pf->veb[veb_idx]);
8250}
8251
8252/**
8253 * i40e_veb_clear - remove veb struct
8254 * @veb: the veb to remove
8255 **/
8256static void i40e_veb_clear(struct i40e_veb *veb)
8257{
8258 if (!veb)
8259 return;
8260
8261 if (veb->pf) {
8262 struct i40e_pf *pf = veb->pf;
8263
8264 mutex_lock(&pf->switch_mutex);
8265 if (pf->veb[veb->idx] == veb)
8266 pf->veb[veb->idx] = NULL;
8267 mutex_unlock(&pf->switch_mutex);
8268 }
8269
8270 kfree(veb);
8271}
8272
8273/**
8274 * i40e_veb_release - Delete a VEB and free its resources
8275 * @veb: the VEB being removed
8276 **/
8277void i40e_veb_release(struct i40e_veb *veb)
8278{
8279 struct i40e_vsi *vsi = NULL;
8280 struct i40e_pf *pf;
8281 int i, n = 0;
8282
8283 pf = veb->pf;
8284
8285 /* find the remaining VSI and check for extras */
505682cd 8286 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8287 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
8288 n++;
8289 vsi = pf->vsi[i];
8290 }
8291 }
8292 if (n != 1) {
8293 dev_info(&pf->pdev->dev,
8294 "can't remove VEB %d with %d VSIs left\n",
8295 veb->seid, n);
8296 return;
8297 }
8298
8299 /* move the remaining VSI to uplink veb */
8300 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
8301 if (veb->uplink_seid) {
8302 vsi->uplink_seid = veb->uplink_seid;
8303 if (veb->uplink_seid == pf->mac_seid)
8304 vsi->veb_idx = I40E_NO_VEB;
8305 else
8306 vsi->veb_idx = veb->veb_idx;
8307 } else {
8308 /* floating VEB */
8309 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8310 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
8311 }
8312
8313 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
8314 i40e_veb_clear(veb);
41c445ff
JB		 8315}
8316
8317/**
8318 * i40e_add_veb - create the VEB in the switch
8319 * @veb: the VEB to be instantiated
8320 * @vsi: the controlling VSI
8321 **/
8322static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
8323{
56747264 8324 bool is_default = false;
e1c51b95 8325 bool is_cloud = false;
41c445ff
JB		 8326 int ret;
8327
8328 /* get a VEB from the hardware */
8329 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 8330 veb->enabled_tc, is_default,
8331 is_cloud, &veb->seid, NULL);
41c445ff
JB		 8332 if (ret) {
8333 dev_info(&veb->pf->pdev->dev,
8334 "couldn't add VEB, err %d, aq_err %d\n",
8335 ret, veb->pf->hw.aq.asq_last_status);
8336 return -EPERM;
8337 }
8338
8339 /* get statistics counter */
8340 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
8341 &veb->stats_idx, NULL, NULL, NULL);
8342 if (ret) {
8343 dev_info(&veb->pf->pdev->dev,
8344 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
8345 ret, veb->pf->hw.aq.asq_last_status);
8346 return -EPERM;
8347 }
8348 ret = i40e_veb_get_bw_info(veb);
8349 if (ret) {
8350 dev_info(&veb->pf->pdev->dev,
8351 "couldn't get VEB bw info, err %d, aq_err %d\n",
8352 ret, veb->pf->hw.aq.asq_last_status);
8353 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8354 return -ENOENT;
8355 }
8356
8357 vsi->uplink_seid = veb->seid;
8358 vsi->veb_idx = veb->idx;
8359 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8360
8361 return 0;
8362}
8363
8364/**
8365 * i40e_veb_setup - Set up a VEB
8366 * @pf: board private structure
8367 * @flags: VEB setup flags
8368 * @uplink_seid: the switch element to link to
8369 * @vsi_seid: the initial VSI seid
8370 * @enabled_tc: Enabled TC bit-map
8371 *
8372 * This allocates the sw VEB structure and links it into the switch
8373 * It is possible and legal for this to be a duplicate of an already
8374 * existing VEB. It is also possible for both uplink and vsi seids
8375 * to be zero, in order to create a floating VEB.
8376 *
8377 * Returns pointer to the successfully allocated VEB sw struct on
8378 * success, otherwise returns NULL on failure.
8379 **/
8380struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8381 u16 uplink_seid, u16 vsi_seid,
8382 u8 enabled_tc)
8383{
8384 struct i40e_veb *veb, *uplink_veb = NULL;
8385 int vsi_idx, veb_idx;
8386 int ret;
8387
8388 /* if one seid is 0, the other must be 0 to create a floating relay */
8389 if ((uplink_seid == 0 || vsi_seid == 0) &&
8390 (uplink_seid + vsi_seid != 0)) {
8391 dev_info(&pf->pdev->dev,
8392 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8393 uplink_seid, vsi_seid);
8394 return NULL;
8395 }
8396
8397 /* make sure there is such a vsi and uplink */
505682cd 8398 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8399 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8400 break;
505682cd 8401 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8402 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8403 vsi_seid);
8404 return NULL;
8405 }
8406
8407 if (uplink_seid && uplink_seid != pf->mac_seid) {
8408 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8409 if (pf->veb[veb_idx] &&
8410 pf->veb[veb_idx]->seid == uplink_seid) {
8411 uplink_veb = pf->veb[veb_idx];
8412 break;
8413 }
8414 }
8415 if (!uplink_veb) {
8416 dev_info(&pf->pdev->dev,
8417 "uplink seid %d not found\n", uplink_seid);
8418 return NULL;
8419 }
8420 }
8421
8422 /* get veb sw struct */
8423 veb_idx = i40e_veb_mem_alloc(pf);
8424 if (veb_idx < 0)
8425 goto err_alloc;
8426 veb = pf->veb[veb_idx];
8427 veb->flags = flags;
8428 veb->uplink_seid = uplink_seid;
8429 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8430 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8431
8432 /* create the VEB in the switch */
8433 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8434 if (ret)
8435 goto err_veb;
1bb8b935
SN		 8436 if (vsi_idx == pf->lan_vsi)
8437 pf->lan_veb = veb->idx;
41c445ff
JB		 8438
8439 return veb;
8440
8441err_veb:
8442 i40e_veb_clear(veb);
8443err_alloc:
8444 return NULL;
8445}
8446
8447/**
8448 * i40e_setup_pf_switch_element - set pf vars based on switch type
8449 * @pf: board private structure
8450 * @ele: element we are building info from
8451 * @num_reported: total number of elements
8452 * @printconfig: should we print the contents
8453 *
8454 * helper function to assist in extracting a few useful SEID values.
8455 **/
8456static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
8457 struct i40e_aqc_switch_config_element_resp *ele,
8458 u16 num_reported, bool printconfig)
8459{
8460 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
8461 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
8462 u8 element_type = ele->element_type;
8463 u16 seid = le16_to_cpu(ele->seid);
8464
8465 if (printconfig)
8466 dev_info(&pf->pdev->dev,
8467 "type=%d seid=%d uplink=%d downlink=%d\n",
8468 element_type, seid, uplink_seid, downlink_seid);
8469
8470 switch (element_type) {
8471 case I40E_SWITCH_ELEMENT_TYPE_MAC:
8472 pf->mac_seid = seid;
8473 break;
8474 case I40E_SWITCH_ELEMENT_TYPE_VEB:
8475 /* Main VEB? */
8476 if (uplink_seid != pf->mac_seid)
8477 break;
8478 if (pf->lan_veb == I40E_NO_VEB) {
8479 int v;
8480
8481 /* find existing or else empty VEB */
8482 for (v = 0; v < I40E_MAX_VEB; v++) {
8483 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
8484 pf->lan_veb = v;
8485 break;
8486 }
8487 }
8488 if (pf->lan_veb == I40E_NO_VEB) {
8489 v = i40e_veb_mem_alloc(pf);
8490 if (v < 0)
8491 break;
8492 pf->lan_veb = v;
8493 }
8494 }
8495
8496 pf->veb[pf->lan_veb]->seid = seid;
8497 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
8498 pf->veb[pf->lan_veb]->pf = pf;
8499 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
8500 break;
8501 case I40E_SWITCH_ELEMENT_TYPE_VSI:
8502 if (num_reported != 1)
8503 break;
8504 /* This is immediately after a reset so we can assume this is
8505 * the PF's VSI
8506 */
8507 pf->mac_seid = uplink_seid;
8508 pf->pf_seid = downlink_seid;
8509 pf->main_vsi_seid = seid;
8510 if (printconfig)
8511 dev_info(&pf->pdev->dev,
8512 "pf_seid=%d main_vsi_seid=%d\n",
8513 pf->pf_seid, pf->main_vsi_seid);
8514 break;
8515 case I40E_SWITCH_ELEMENT_TYPE_PF:
8516 case I40E_SWITCH_ELEMENT_TYPE_VF:
8517 case I40E_SWITCH_ELEMENT_TYPE_EMP:
8518 case I40E_SWITCH_ELEMENT_TYPE_BMC:
8519 case I40E_SWITCH_ELEMENT_TYPE_PE:
8520 case I40E_SWITCH_ELEMENT_TYPE_PA:
8521 /* ignore these for now */
8522 break;
8523 default:
8524 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
8525 element_type, seid);
8526 break;
8527 }
8528}
8529
8530/**
8531 * i40e_fetch_switch_configuration - Get switch config from firmware
8532 * @pf: board private structure
8533 * @printconfig: should we print the contents
8534 *
8535 * Get the current switch configuration from the device and
8536 * extract a few useful SEID values.
8537 **/
8538int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
8539{
8540 struct i40e_aqc_get_switch_config_resp *sw_config;
8541 u16 next_seid = 0;
8542 int ret = 0;
8543 u8 *aq_buf;
8544 int i;
8545
8546 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
8547 if (!aq_buf)
8548 return -ENOMEM;
8549
8550 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
8551 do {
8552 u16 num_reported, num_total;
8553
8554 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
8555 I40E_AQ_LARGE_BUF,
8556 &next_seid, NULL);
8557 if (ret) {
8558 dev_info(&pf->pdev->dev,
8559 "get switch config failed %d aq_err=%x\n",
8560 ret, pf->hw.aq.asq_last_status);
8561 kfree(aq_buf);
8562 return -ENOENT;
8563 }
8564
8565 num_reported = le16_to_cpu(sw_config->header.num_reported);
8566 num_total = le16_to_cpu(sw_config->header.num_total);
8567
8568 if (printconfig)
8569 dev_info(&pf->pdev->dev,
8570 "header: %d reported %d total\n",
8571 num_reported, num_total);
8572
41c445ff
JB		 8573 for (i = 0; i < num_reported; i++) {
8574 struct i40e_aqc_switch_config_element_resp *ele =
8575 &sw_config->element[i];
8576
8577 i40e_setup_pf_switch_element(pf, ele, num_reported,
8578 printconfig);
8579 }
8580 } while (next_seid != 0);
8581
8582 kfree(aq_buf);
8583 return ret;
8584}
8585
8586/**
8587 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8588 * @pf: board private structure
bc7d338f 8589 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8590 *
8591 * Returns 0 on success, negative value on failure
8592 **/
bc7d338f 8593static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 8594{
8595 int ret;
8596
8597 /* find out what's out there already */
8598 ret = i40e_fetch_switch_configuration(pf, false);
8599 if (ret) {
8600 dev_info(&pf->pdev->dev,
8601 "couldn't fetch switch config, err %d, aq_err %d\n",
8602 ret, pf->hw.aq.asq_last_status);
8603 return ret;
8604 }
8605 i40e_pf_reset_stats(pf);
8606
41c445ff 8607 /* first time setup */
bc7d338f 8608 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8609 struct i40e_vsi *vsi = NULL;
8610 u16 uplink_seid;
8611
8612 /* Set up the PF VSI associated with the PF's main VSI
8613 * that is already in the HW switch
8614 */
8615 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8616 uplink_seid = pf->veb[pf->lan_veb]->seid;
8617 else
8618 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8619 if (pf->lan_vsi == I40E_NO_VSI)
8620 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8621 else if (reinit)
8622 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8623 if (!vsi) {
8624 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8625 i40e_fdir_teardown(pf);
8626 return -EAGAIN;
8627 }
41c445ff
JB		 8628 } else {
8629 /* force a reset of TC and queue layout configurations */
8630 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8631 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8632 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8633 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8634 }
8635 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8636
cbf61325
ASJ		 8637 i40e_fdir_sb_setup(pf);
8638
41c445ff
JB		 8639 /* Setup static PF queue filter control settings */
8640 ret = i40e_setup_pf_filter_control(pf);
8641 if (ret) {
8642 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8643 ret);
8644 /* Failure here should not stop continuing other steps */
8645 }
8646
8647 /* enable RSS in the HW, even for only one queue, as the stack can use
8648 * the hash
8649 */
8650 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8651 i40e_config_rss(pf);
8652
8653 /* fill in link information and enable LSE reporting */
8109e123 8654 i40e_update_link_info(&pf->hw, true);
41c445ff
JB		 8655 i40e_link_event(pf);
8656
d52c20b7 8657 /* Initialize user-specific link properties */
41c445ff
JB		 8658 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8659 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 8660
beb0dff1
JK		 8661 i40e_ptp_init(pf);
8662
41c445ff
JB		 8663 return ret;
8664}
8665
41c445ff
JB		 8666/**
8667 * i40e_determine_queue_usage - Work out queue distribution
8668 * @pf: board private structure
8669 **/
8670static void i40e_determine_queue_usage(struct i40e_pf *pf)
8671{
41c445ff
JB		 8672 int queues_left;
8673
8674 pf->num_lan_qps = 0;
38e00438
VD		 8675#ifdef I40E_FCOE
8676 pf->num_fcoe_qps = 0;
8677#endif
41c445ff
JB		 8678
8679 /* Find the max queues to be put into basic use. We'll always be
8680 * using TC0, whether or not DCB is running, and TC0 will get the
8681 * big RSS set.
8682 */
8683 queues_left = pf->hw.func_caps.num_tx_qp;
8684
cbf61325 8685 if ((queues_left == 1) ||
9aa7e935 8686 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 8687 /* one qp for PF, no queues for anything else */
8688 queues_left = 0;
8689 pf->rss_size = pf->num_lan_qps = 1;
8690
8691 /* make sure all the fancies are disabled */
60ea5f83 8692 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8693#ifdef I40E_FCOE
8694 I40E_FLAG_FCOE_ENABLED |
8695#endif
60ea5f83
JB		 8696 I40E_FLAG_FD_SB_ENABLED |
8697 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8698 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 8699 I40E_FLAG_SRIOV_ENABLED |
8700 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 8701 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
8702 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 8703 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8704 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 8705 /* one qp for PF */
8706 pf->rss_size = pf->num_lan_qps = 1;
8707 queues_left -= pf->num_lan_qps;
8708
8709 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8710#ifdef I40E_FCOE
8711 I40E_FLAG_FCOE_ENABLED |
8712#endif
9aa7e935
FZ		 8713 I40E_FLAG_FD_SB_ENABLED |
8714 I40E_FLAG_FD_ATR_ENABLED |
8715 I40E_FLAG_DCB_ENABLED |
8716 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8717 } else {
cbf61325 8718 /* Not enough queues for all TCs */
4d9b6043 8719 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 8720 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 8721 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 8722 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8723 }
8724 pf->num_lan_qps = pf->rss_size_max;
8725 queues_left -= pf->num_lan_qps;
8726 }
8727
38e00438
VD		 8728#ifdef I40E_FCOE
8729 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
8730 if (I40E_DEFAULT_FCOE <= queues_left) {
8731 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
8732 } else if (I40E_MINIMUM_FCOE <= queues_left) {
8733 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
8734 } else {
8735 pf->num_fcoe_qps = 0;
8736 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
8737 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
8738 }
8739
8740 queues_left -= pf->num_fcoe_qps;
8741 }
8742
8743#endif
cbf61325
ASJ		 8744 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8745 if (queues_left > 1) {
8746 queues_left -= 1; /* save 1 queue for FD */
8747 } else {
8748 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8749 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8750 }
41c445ff
JB		 8751 }
8752
8753 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8754 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8755 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8756 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8757 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8758 }
8759
8760 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8761 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8762 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8763 (queues_left / pf->num_vmdq_qps));
8764 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8765 }
8766
f8ff1464 8767 pf->queues_left = queues_left;
38e00438
VD		 8768#ifdef I40E_FCOE
8769 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
8770#endif
41c445ff
JB		 8771}
8772
8773/**
8774 * i40e_setup_pf_filter_control - Setup PF static filter control
8775 * @pf: PF to be setup
8776 *
8777 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8778 * settings. If PE/FCoE are enabled then it will also set the per PF
8779 * based filter sizes required for them. It also enables Flow director,
8780 * ethertype and macvlan type filter settings for the pf.
8781 *
8782 * Returns 0 on success, negative on failure
8783 **/
8784static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8785{
8786 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8787
8788 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8789
8790 /* Flow Director is enabled */
60ea5f83 8791 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8792 settings->enable_fdir = true;
8793
8794 /* Ethtype and MACVLAN filters enabled for PF */
8795 settings->enable_ethtype = true;
8796 settings->enable_macvlan = true;
8797
8798 if (i40e_set_filter_control(&pf->hw, settings))
8799 return -ENOENT;
8800
8801 return 0;
8802}
8803
0c22b3dd
JB		 8804#define INFO_STRING_LEN 255
8805static void i40e_print_features(struct i40e_pf *pf)
8806{
8807 struct i40e_hw *hw = &pf->hw;
8808 char *buf, *string;
8809
8810 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8811 if (!string) {
8812 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8813 return;
8814 }
8815
8816 buf = string;
8817
8818 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8819#ifdef CONFIG_PCI_IOV
8820 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8821#endif
8822 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8823 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8824
8825 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8826 buf += sprintf(buf, "RSS ");
0c22b3dd 8827 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 8828 buf += sprintf(buf, "FD_ATR ");
8829 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8830 buf += sprintf(buf, "FD_SB ");
0c22b3dd 8831 buf += sprintf(buf, "NTUPLE ");
c6423ff1 8832 }
4d9b6043 8833 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 8834 buf += sprintf(buf, "DCB ");
8835 if (pf->flags & I40E_FLAG_PTP)
8836 buf += sprintf(buf, "PTP ");
38e00438
VD		 8837#ifdef I40E_FCOE
8838 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
8839 buf += sprintf(buf, "FCOE ");
8840#endif
0c22b3dd
JB		 8841
8842 BUG_ON(buf > (string + INFO_STRING_LEN));
8843 dev_info(&pf->pdev->dev, "%s\n", string);
8844 kfree(string);
8845}
8846
41c445ff
JB		 8847/**
8848 * i40e_probe - Device initialization routine
8849 * @pdev: PCI device information struct
8850 * @ent: entry in i40e_pci_tbl
8851 *
8852 * i40e_probe initializes a pf identified by a pci_dev structure.
8853 * The OS initialization, configuring of the pf private structure,
8854 * and a hardware reset occur.
8855 *
8856 * Returns 0 on success, negative on failure
8857 **/
8858static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8859{
41c445ff
JB		 8860 struct i40e_pf *pf;
8861 struct i40e_hw *hw;
93cd765b 8862 static u16 pfs_found;
d4dfb81a 8863 u16 link_status;
41c445ff
JB		 8864 int err = 0;
8865 u32 len;
8a9eb7d3 8866 u32 i;
41c445ff
JB		 8867
8868 err = pci_enable_device_mem(pdev);
8869 if (err)
8870 return err;
8871
8872 /* set up for high or low dma */
6494294f 8873 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8874 if (err) {
e3e3bfdd
JS		 8875 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8876 if (err) {
8877 dev_err(&pdev->dev,
8878 "DMA configuration failed: 0x%x\n", err);
8879 goto err_dma;
8880 }
41c445ff
JB		 8881 }
8882
8883 /* set up pci connections */
8884 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8885 IORESOURCE_MEM), i40e_driver_name);
8886 if (err) {
8887 dev_info(&pdev->dev,
8888 "pci_request_selected_regions failed %d\n", err);
8889 goto err_pci_reg;
8890 }
8891
8892 pci_enable_pcie_error_reporting(pdev);
8893 pci_set_master(pdev);
8894
8895 /* Now that we have a PCI connection, we need to do the
8896 * low level device setup. This is primarily setting up
8897 * the Admin Queue structures and then querying for the
8898 * device's current profile information.
8899 */
8900 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8901 if (!pf) {
8902 err = -ENOMEM;
8903 goto err_pf_alloc;
8904 }
8905 pf->next_vsi = 0;
8906 pf->pdev = pdev;
8907 set_bit(__I40E_DOWN, &pf->state);
8908
8909 hw = &pf->hw;
8910 hw->back = pf;
8911 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8912 pci_resource_len(pdev, 0));
8913 if (!hw->hw_addr) {
8914 err = -EIO;
8915 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8916 (unsigned int)pci_resource_start(pdev, 0),
8917 (unsigned int)pci_resource_len(pdev, 0), err);
8918 goto err_ioremap;
8919 }
8920 hw->vendor_id = pdev->vendor;
8921 hw->device_id = pdev->device;
8922 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8923 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8924 hw->subsystem_device_id = pdev->subsystem_device;
8925 hw->bus.device = PCI_SLOT(pdev->devfn);
8926 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8927 pf->instance = pfs_found;
41c445ff 8928
7134f9ce
JB		 8929 /* do a special CORER for clearing PXE mode once at init */
8930 if (hw->revision_id == 0 &&
8931 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8932 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8933 i40e_flush(hw);
8934 msleep(200);
8935 pf->corer_count++;
8936
8937 i40e_clear_pxe_mode(hw);
8938 }
8939
41c445ff 8940 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 8941 i40e_clear_hw(hw);
41c445ff
JB		 8942 err = i40e_pf_reset(hw);
8943 if (err) {
8944 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8945 goto err_pf_reset;
8946 }
8947 pf->pfr_count++;
8948
8949 hw->aq.num_arq_entries = I40E_AQ_LEN;
8950 hw->aq.num_asq_entries = I40E_AQ_LEN;
8951 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8952 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8953 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8954 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8955 "%s-pf%d:misc",
8956 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8957
8958 err = i40e_init_shared_code(hw);
8959 if (err) {
8960 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8961 goto err_pf_reset;
8962 }
8963
d52c20b7
JB		 8964 /* set up a default setting for link flow control */
8965 pf->hw.fc.requested_mode = I40E_FC_NONE;
8966
41c445ff
JB		 8967 err = i40e_init_adminq(hw);
8968 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8969 if (err) {
8970 dev_info(&pdev->dev,
7aa67613 8971 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 8972 goto err_pf_reset;
8973 }
8974
7aa67613
CS		 8975 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
8976 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 8977 dev_info(&pdev->dev,
7aa67613
CS		 8978 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
8979 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
8980 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 8981 dev_info(&pdev->dev,
7aa67613 8982 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62
SN		 8983
8984
4eb3f768
SN		 8985 i40e_verify_eeprom(pf);
8986
2c5fe33b
JB		 8987 /* Rev 0 hardware was never productized */
8988 if (hw->revision_id < 1)
8989 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
8990
6ff4ef86 8991 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8992 err = i40e_get_capabilities(pf);
8993 if (err)
8994 goto err_adminq_setup;
8995
8996 err = i40e_sw_init(pf);
8997 if (err) {
8998 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8999 goto err_sw_init;
9000 }
9001
9002 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9003 hw->func_caps.num_rx_qp,
9004 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9005 if (err) {
9006 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9007 goto err_init_lan_hmc;
9008 }
9009
9010 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9011 if (err) {
9012 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9013 err = -ENOENT;
9014 goto err_configure_lan_hmc;
9015 }
9016
9017 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9018 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9019 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9020 err = -EIO;
9021 goto err_mac_addr;
9022 }
9023 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9024 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9025 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9026 if (is_valid_ether_addr(hw->mac.port_addr))
9027 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9028#ifdef I40E_FCOE
9029 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9030 if (err)
9031 dev_info(&pdev->dev,
9032 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9033 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9034 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9035 hw->mac.san_addr);
9036 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9037 }
9038 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9039#endif /* I40E_FCOE */
41c445ff
JB		 9040
9041 pci_set_drvdata(pdev, pf);
9042 pci_save_state(pdev);
4e3b35b0
NP		 9043#ifdef CONFIG_I40E_DCB
9044 err = i40e_init_pf_dcb(pf);
9045 if (err) {
9046 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
4d9b6043 9047 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9048 /* Continue without DCB enabled */
4e3b35b0
NP		 9049 }
9050#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9051
9052 /* set up periodic task facility */
9053 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9054 pf->service_timer_period = HZ;
9055
9056 INIT_WORK(&pf->service_task, i40e_service_task);
9057 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9058 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9059 pf->link_check_timeout = jiffies;
9060
8e2773ae
SN		 9061 /* WoL defaults to disabled */
9062 pf->wol_en = false;
9063 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9064
41c445ff
JB		 9065 /* set up the main switch operations */
9066 i40e_determine_queue_usage(pf);
9067 i40e_init_interrupt_scheme(pf);
9068
505682cd
MW		 9069 /* The number of VSIs reported by the FW is the minimum guaranteed
9070 * to us; HW supports far more and we share the remaining pool with
9071 * the other PFs. We allocate space for more than the guarantee with
9072 * the understanding that we might not get them all later.
41c445ff 9073 */
505682cd
MW		 9074 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9075 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9076 else
9077 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9078
9079 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9080 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9081 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9082 if (!pf->vsi) {
9083 err = -ENOMEM;
41c445ff 9084 goto err_switch_setup;
ed87ac09 9085 }
41c445ff 9086
bc7d338f 9087 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9088 if (err) {
9089 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9090 goto err_vsis;
9091 }
8a9eb7d3 9092 /* if FDIR VSI was set up, start it now */
505682cd 9093 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9094 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9095 i40e_vsi_open(pf->vsi[i]);
9096 break;
9097 }
9098 }
41c445ff
JB		 9099
9100 /* The main driver is (mostly) up and happy. We need to set this state
9101 * before setting up the misc vector or we get a race and the vector
9102 * ends up disabled forever.
9103 */
9104 clear_bit(__I40E_DOWN, &pf->state);
9105
9106 /* In case of MSIX we are going to setup the misc vector right here
9107 * to handle admin queue events etc. In case of legacy and MSI
9108 * the misc functionality and queue processing is combined in
9109 * the same vector and that gets setup at open.
9110 */
9111 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9112 err = i40e_setup_misc_vector(pf);
9113 if (err) {
9114 dev_info(&pdev->dev,
9115 "setup of misc vector failed: %d\n", err);
9116 goto err_vsis;
9117 }
9118 }
9119
df805f62 9120#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9121 /* prep for VF support */
9122 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9123 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9124 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9125 u32 val;
9126
9127 /* disable link interrupts for VFs */
9128 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9129 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9130 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9131 i40e_flush(hw);
4aeec010
MW		 9132
9133 if (pci_num_vf(pdev)) {
9134 dev_info(&pdev->dev,
9135 "Active VFs found, allocating resources.\n");
9136 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9137 if (err)
9138 dev_info(&pdev->dev,
9139 "Error %d allocating resources for existing VFs\n",
9140 err);
9141 }
41c445ff 9142 }
df805f62 9143#endif /* CONFIG_PCI_IOV */
41c445ff 9144
93cd765b
ASJ		 9145 pfs_found++;
9146
41c445ff
JB		 9147 i40e_dbg_pf_init(pf);
9148
9149 /* tell the firmware that we're starting */
44033fac 9150 i40e_send_version(pf);
41c445ff
JB		 9151
9152 /* since everything's happy, start the service_task timer */
9153 mod_timer(&pf->service_timer,
9154 round_jiffies(jiffies + pf->service_timer_period));
9155
38e00438
VD		 9156#ifdef I40E_FCOE
9157 /* create FCoE interface */
9158 i40e_fcoe_vsi_setup(pf);
9159
9160#endif
d4dfb81a
CS		 9161 /* Get the negotiated link width and speed from PCI config space */
9162 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9163
9164 i40e_set_pci_config_data(hw, link_status);
9165
69bfb110 9166 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9167 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9168 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9169 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9170 "Unknown"),
9171 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9172 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9173 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9174 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9175 "Unknown"));
9176
9177 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9178 hw->bus.speed < i40e_bus_speed_8000) {
9179 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9180 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9181 }
9182
0c22b3dd
JB		 9183 /* print a string summarizing features */
9184 i40e_print_features(pf);
9185
41c445ff
JB		 9186 return 0;
9187
9188 /* Unwind what we've done if something failed in the setup */
9189err_vsis:
9190 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9191 i40e_clear_interrupt_scheme(pf);
9192 kfree(pf->vsi);
04b03013
SN		 9193err_switch_setup:
9194 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9195 del_timer_sync(&pf->service_timer);
9196err_mac_addr:
9197err_configure_lan_hmc:
9198 (void)i40e_shutdown_lan_hmc(hw);
9199err_init_lan_hmc:
9200 kfree(pf->qp_pile);
9201 kfree(pf->irq_pile);
9202err_sw_init:
9203err_adminq_setup:
9204 (void)i40e_shutdown_adminq(hw);
9205err_pf_reset:
9206 iounmap(hw->hw_addr);
9207err_ioremap:
9208 kfree(pf);
9209err_pf_alloc:
9210 pci_disable_pcie_error_reporting(pdev);
9211 pci_release_selected_regions(pdev,
9212 pci_select_bars(pdev, IORESOURCE_MEM));
9213err_pci_reg:
9214err_dma:
9215 pci_disable_device(pdev);
9216 return err;
9217}
9218
9219/**
9220 * i40e_remove - Device removal routine
9221 * @pdev: PCI device information struct
9222 *
9223 * i40e_remove is called by the PCI subsystem to alert the driver
9224 * that is should release a PCI device. This could be caused by a
9225 * Hot-Plug event, or because the driver is going to be removed from
9226 * memory.
9227 **/
9228static void i40e_remove(struct pci_dev *pdev)
9229{
9230 struct i40e_pf *pf = pci_get_drvdata(pdev);
9231 i40e_status ret_code;
41c445ff
JB		 9232 int i;
9233
9234 i40e_dbg_pf_exit(pf);
9235
beb0dff1
JK		 9236 i40e_ptp_stop(pf);
9237
41c445ff
JB		 9238 /* no more scheduling of any task */
9239 set_bit(__I40E_DOWN, &pf->state);
9240 del_timer_sync(&pf->service_timer);
9241 cancel_work_sync(&pf->service_task);
9242
eb2d80bc
MW		 9243 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
9244 i40e_free_vfs(pf);
9245 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
9246 }
9247
41c445ff
JB		 9248 i40e_fdir_teardown(pf);
9249
9250 /* If there is a switch structure or any orphans, remove them.
9251 * This will leave only the PF's VSI remaining.
9252 */
9253 for (i = 0; i < I40E_MAX_VEB; i++) {
9254 if (!pf->veb[i])
9255 continue;
9256
9257 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
9258 pf->veb[i]->uplink_seid == 0)
9259 i40e_switch_branch_release(pf->veb[i]);
9260 }
9261
9262 /* Now we can shutdown the PF's VSI, just before we kill
9263 * adminq and hmc.
9264 */
9265 if (pf->vsi[pf->lan_vsi])
9266 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
9267
9268 i40e_stop_misc_vector(pf);
9269 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9270 synchronize_irq(pf->msix_entries[0].vector);
9271 free_irq(pf->msix_entries[0].vector, pf);
9272 }
9273
9274 /* shutdown and destroy the HMC */
60442dea
SN		 9275 if (pf->hw.hmc.hmc_obj) {
9276 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
9277 if (ret_code)
9278 dev_warn(&pdev->dev,
9279 "Failed to destroy the HMC resources: %d\n",
9280 ret_code);
9281 }
41c445ff
JB		 9282
9283 /* shutdown the adminq */
41c445ff
JB		 9284 ret_code = i40e_shutdown_adminq(&pf->hw);
9285 if (ret_code)
9286 dev_warn(&pdev->dev,
9287 "Failed to destroy the Admin Queue resources: %d\n",
9288 ret_code);
9289
9290 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
9291 i40e_clear_interrupt_scheme(pf);
505682cd 9292 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9293 if (pf->vsi[i]) {
9294 i40e_vsi_clear_rings(pf->vsi[i]);
9295 i40e_vsi_clear(pf->vsi[i]);
9296 pf->vsi[i] = NULL;
9297 }
9298 }
9299
9300 for (i = 0; i < I40E_MAX_VEB; i++) {
9301 kfree(pf->veb[i]);
9302 pf->veb[i] = NULL;
9303 }
9304
9305 kfree(pf->qp_pile);
9306 kfree(pf->irq_pile);
41c445ff
JB		 9307 kfree(pf->vsi);
9308
41c445ff
JB		 9309 iounmap(pf->hw.hw_addr);
9310 kfree(pf);
9311 pci_release_selected_regions(pdev,
9312 pci_select_bars(pdev, IORESOURCE_MEM));
9313
9314 pci_disable_pcie_error_reporting(pdev);
9315 pci_disable_device(pdev);
9316}
9317
9318/**
9319 * i40e_pci_error_detected - warning that something funky happened in PCI land
9320 * @pdev: PCI device information struct
9321 *
9322 * Called to warn that something happened and the error handling steps
9323 * are in progress. Allows the driver to quiesce things, be ready for
9324 * remediation.
9325 **/
9326static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
9327 enum pci_channel_state error)
9328{
9329 struct i40e_pf *pf = pci_get_drvdata(pdev);
9330
9331 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
9332
9333 /* shutdown all operations */
9007bccd
SN		 9334 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
9335 rtnl_lock();
9336 i40e_prep_for_reset(pf);
9337 rtnl_unlock();
9338 }
41c445ff
JB		 9339
9340 /* Request a slot reset */
9341 return PCI_ERS_RESULT_NEED_RESET;
9342}
9343
9344/**
9345 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9346 * @pdev: PCI device information struct
9347 *
9348 * Called to find if the driver can work with the device now that
9349 * the pci slot has been reset. If a basic connection seems good
9350 * (registers are readable and have sane content) then return a
9351 * happy little PCI_ERS_RESULT_xxx.
9352 **/
9353static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9354{
9355 struct i40e_pf *pf = pci_get_drvdata(pdev);
9356 pci_ers_result_t result;
9357 int err;
9358 u32 reg;
9359
9360 dev_info(&pdev->dev, "%s\n", __func__);
9361 if (pci_enable_device_mem(pdev)) {
9362 dev_info(&pdev->dev,
9363 "Cannot re-enable PCI device after reset.\n");
9364 result = PCI_ERS_RESULT_DISCONNECT;
9365 } else {
9366 pci_set_master(pdev);
9367 pci_restore_state(pdev);
9368 pci_save_state(pdev);
9369 pci_wake_from_d3(pdev, false);
9370
9371 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9372 if (reg == 0)
9373 result = PCI_ERS_RESULT_RECOVERED;
9374 else
9375 result = PCI_ERS_RESULT_DISCONNECT;
9376 }
9377
9378 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9379 if (err) {
9380 dev_info(&pdev->dev,
9381 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9382 err);
9383 /* non-fatal, continue */
9384 }
9385
9386 return result;
9387}
9388
9389/**
9390 * i40e_pci_error_resume - restart operations after PCI error recovery
9391 * @pdev: PCI device information struct
9392 *
9393 * Called to allow the driver to bring things back up after PCI error
9394 * and/or reset recovery has finished.
9395 **/
9396static void i40e_pci_error_resume(struct pci_dev *pdev)
9397{
9398 struct i40e_pf *pf = pci_get_drvdata(pdev);
9399
9400 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 9401 if (test_bit(__I40E_SUSPENDED, &pf->state))
9402 return;
9403
9404 rtnl_lock();
41c445ff 9405 i40e_handle_reset_warning(pf);
9007bccd
SN		 9406 rtnl_lock();
9407}
9408
9409/**
9410 * i40e_shutdown - PCI callback for shutting down
9411 * @pdev: PCI device information struct
9412 **/
9413static void i40e_shutdown(struct pci_dev *pdev)
9414{
9415 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9416 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9417
9418 set_bit(__I40E_SUSPENDED, &pf->state);
9419 set_bit(__I40E_DOWN, &pf->state);
9420 rtnl_lock();
9421 i40e_prep_for_reset(pf);
9422 rtnl_unlock();
9423
8e2773ae
SN		 9424 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9425 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9426
9007bccd 9427 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 9428 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9429 pci_set_power_state(pdev, PCI_D3hot);
9430 }
9431}
9432
9433#ifdef CONFIG_PM
9434/**
9435 * i40e_suspend - PCI callback for moving to D3
9436 * @pdev: PCI device information struct
9437 **/
9438static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
9439{
9440 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9441 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9442
9443 set_bit(__I40E_SUSPENDED, &pf->state);
9444 set_bit(__I40E_DOWN, &pf->state);
9445 rtnl_lock();
9446 i40e_prep_for_reset(pf);
9447 rtnl_unlock();
9448
8e2773ae
SN		 9449 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9450 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9451
9452 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9453 pci_set_power_state(pdev, PCI_D3hot);
9454
9455 return 0;
41c445ff
JB		 9456}
9457
9007bccd
SN		 9458/**
9459 * i40e_resume - PCI callback for waking up from D3
9460 * @pdev: PCI device information struct
9461 **/
9462static int i40e_resume(struct pci_dev *pdev)
9463{
9464 struct i40e_pf *pf = pci_get_drvdata(pdev);
9465 u32 err;
9466
9467 pci_set_power_state(pdev, PCI_D0);
9468 pci_restore_state(pdev);
9469 /* pci_restore_state() clears dev->state_saves, so
9470 * call pci_save_state() again to restore it.
9471 */
9472 pci_save_state(pdev);
9473
9474 err = pci_enable_device_mem(pdev);
9475 if (err) {
9476 dev_err(&pdev->dev,
9477 "%s: Cannot enable PCI device from suspend\n",
9478 __func__);
9479 return err;
9480 }
9481 pci_set_master(pdev);
9482
9483 /* no wakeup events while running */
9484 pci_wake_from_d3(pdev, false);
9485
9486 /* handling the reset will rebuild the device state */
9487 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
9488 clear_bit(__I40E_DOWN, &pf->state);
9489 rtnl_lock();
9490 i40e_reset_and_rebuild(pf, false);
9491 rtnl_unlock();
9492 }
9493
9494 return 0;
9495}
9496
9497#endif
41c445ff
JB		 9498static const struct pci_error_handlers i40e_err_handler = {
9499 .error_detected = i40e_pci_error_detected,
9500 .slot_reset = i40e_pci_error_slot_reset,
9501 .resume = i40e_pci_error_resume,
9502};
9503
9504static struct pci_driver i40e_driver = {
9505 .name = i40e_driver_name,
9506 .id_table = i40e_pci_tbl,
9507 .probe = i40e_probe,
9508 .remove = i40e_remove,
9007bccd
SN		 9509#ifdef CONFIG_PM
9510 .suspend = i40e_suspend,
9511 .resume = i40e_resume,
9512#endif
9513 .shutdown = i40e_shutdown,
41c445ff
JB		 9514 .err_handler = &i40e_err_handler,
9515 .sriov_configure = i40e_pci_sriov_configure,
9516};
9517
9518/**
9519 * i40e_init_module - Driver registration routine
9520 *
9521 * i40e_init_module is the first routine called when the driver is
9522 * loaded. All it does is register with the PCI subsystem.
9523 **/
9524static int __init i40e_init_module(void)
9525{
9526 pr_info("%s: %s - version %s\n", i40e_driver_name,
9527 i40e_driver_string, i40e_driver_version_str);
9528 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
9529 i40e_dbg_init();
9530 return pci_register_driver(&i40e_driver);
9531}
9532module_init(i40e_init_module);
9533
9534/**
9535 * i40e_exit_module - Driver exit cleanup routine
9536 *
9537 * i40e_exit_module is called just before the driver is removed
9538 * from memory.
9539 **/
9540static void __exit i40e_exit_module(void)
9541{
9542 pci_unregister_driver(&i40e_driver);
9543 i40e_dbg_exit();
9544}
9545module_exit(i40e_exit_module);
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