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Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next...
[linux-2.6-block.git] / drivers / net / ethernet / intel / fm10k / fm10k_pf.c
CommitLineData
b6fec18f 1/* Intel Ethernet Switch Host Interface Driver
9d4955b4 2 * Copyright(c) 2013 - 2015 Intel Corporation.
b6fec18f
AD		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
19 */
20
21#include "fm10k_pf.h"
c2653865 22#include "fm10k_vf.h"
b6fec18f
AD		 23
24/**
25 * fm10k_reset_hw_pf - PF hardware reset
26 * @hw: pointer to hardware structure
27 *
28 * This function should return the hardware to a state similar to the
29 * one it is in after being powered on.
30 **/
31static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
32{
33 s32 err;
34 u32 reg;
35 u16 i;
36
37 /* Disable interrupts */
38 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
39
40 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */
41 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
42 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
43
44 /* We assume here Tx and Rx queue 0 are owned by the PF */
45
46 /* Shut off VF access to their queues forcing them to queue 0 */
47 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {
48 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
49 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
50 }
51
52 /* shut down all rings */
53 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
54 if (err)
55 return err;
56
57 /* Verify that DMA is no longer active */
58 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL);
59 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))
60 return FM10K_ERR_DMA_PENDING;
61
ac981003
AD		 62 /* verify the switch is ready for reset */
63 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
64 if (!(reg & FM10K_DMA_CTRL2_SWITCH_READY))
65 goto out;
66
b6fec18f
AD		 67 /* Inititate data path reset */
68 reg |= FM10K_DMA_CTRL_DATAPATH_RESET;
69 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg);
70
71 /* Flush write and allow 100us for reset to complete */
72 fm10k_write_flush(hw);
73 udelay(FM10K_RESET_TIMEOUT);
74
75 /* Verify we made it out of reset */
76 reg = fm10k_read_reg(hw, FM10K_IP);
77 if (!(reg & FM10K_IP_NOTINRESET))
78 err = FM10K_ERR_RESET_FAILED;
79
ac981003 80out:
b6fec18f
AD		 81 return err;
82}
83
c2653865
AD		 84/**
85 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
86 * @hw: pointer to hardware structure
87 *
88 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
89 **/
90static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)
91{
92 u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL);
93
94 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);
95}
96
b6fec18f
AD		 97/**
98 * fm10k_init_hw_pf - PF hardware initialization
99 * @hw: pointer to hardware structure
100 *
101 **/
102static s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
103{
104 u32 dma_ctrl, txqctl;
105 u16 i;
106
107 /* Establish default VSI as valid */
108 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
109 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
110 FM10K_DGLORTMAP_ANY);
111
112 /* Invalidate all other GLORT entries */
113 for (i = 1; i < FM10K_DGLORT_COUNT; i++)
114 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
115
116 /* reset ITR2(0) to point to itself */
117 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
118
119 /* reset VF ITR2(0) to point to 0 avoid PF registers */
120 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
121
122 /* loop through all PF ITR2 registers pointing them to the previous */
123 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)
124 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
125
126 /* Enable interrupt moderator if not already enabled */
127 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
128
129 /* compute the default txqctl configuration */
130 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |
131 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);
132
133 for (i = 0; i < FM10K_MAX_QUEUES; i++) {
134 /* configure rings for 256 Queue / 32 Descriptor cache mode */
135 fm10k_write_reg(hw, FM10K_TQDLOC(i),
136 (i * FM10K_TQDLOC_BASE_32_DESC) |
137 FM10K_TQDLOC_SIZE_32_DESC);
138 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
139
140 /* configure rings to provide TPH processing hints */
141 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i),
142 FM10K_TPH_TXCTRL_DESC_TPHEN |
143 FM10K_TPH_TXCTRL_DESC_RROEN |
144 FM10K_TPH_TXCTRL_DESC_WROEN |
145 FM10K_TPH_TXCTRL_DATA_RROEN);
146 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i),
147 FM10K_TPH_RXCTRL_DESC_TPHEN |
148 FM10K_TPH_RXCTRL_DESC_RROEN |
149 FM10K_TPH_RXCTRL_DATA_WROEN |
150 FM10K_TPH_RXCTRL_HDR_WROEN);
151 }
152
20076fa1
JK		 153 /* set max hold interval to align with 1.024 usec in all modes and
154 * store ITR scale
155 */
b6fec18f
AD		 156 switch (hw->bus.speed) {
157 case fm10k_bus_speed_2500:
158 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
20076fa1 159 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1;
b6fec18f
AD		 160 break;
161 case fm10k_bus_speed_5000:
162 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
20076fa1 163 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2;
b6fec18f
AD		 164 break;
165 case fm10k_bus_speed_8000:
166 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
20076fa1 167 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
b6fec18f
AD		 168 break;
169 default:
170 dma_ctrl = 0;
20076fa1
JK		 171 /* just in case, assume Gen3 ITR scale */
172 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
b6fec18f
AD		 173 break;
174 }
175
176 /* Configure TSO flags */
177 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
178 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
179
180 /* Enable DMA engine
181 * Set Rx Descriptor size to 32
182 * Set Minimum MSS to 64
183 * Set Maximum number of Rx queues to 256 / 32 Descriptor
184 */
185 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
186 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |
187 FM10K_DMA_CTRL_32_DESC;
188
189 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl);
190
191 /* record maximum queue count, we limit ourselves to 128 */
192 hw->mac.max_queues = FM10K_MAX_QUEUES_PF;
193
c2653865
AD		 194 /* We support either 64 VFs or 7 VFs depending on if we have ARI */
195 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;
196
b6fec18f
AD		 197 return 0;
198}
199
401b5383
AD		 200/**
201 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
202 * @hw: pointer to hardware structure
203 * @vid: VLAN ID to add to table
204 * @vsi: Index indicating VF ID or PF ID in table
205 * @set: Indicates if this is a set or clear operation
206 *
207 * This function adds or removes the corresponding VLAN ID from the VLAN
208 * filter table for the corresponding function. In addition to the
209 * standard set/clear that supports one bit a multi-bit write is
210 * supported to set 64 bits at a time.
211 **/
212static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
213{
214 u32 vlan_table, reg, mask, bit, len;
215
216 /* verify the VSI index is valid */
217 if (vsi > FM10K_VLAN_TABLE_VSI_MAX)
218 return FM10K_ERR_PARAM;
219
220 /* VLAN multi-bit write:
221 * The multi-bit write has several parts to it.
222 * 3 2 1 0
223 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
225 * | RSVD0 | Length |C|RSVD0| VLAN ID |
226 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
227 *
228 * VLAN ID: Vlan Starting value
229 * RSVD0: Reserved section, must be 0
230 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
231 * Length: Number of times to repeat the bit being set
232 */
233 len = vid >> 16;
234 vid = (vid << 17) >> 17;
235
236 /* verify the reserved 0 fields are 0 */
eca32047 237 if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX)
401b5383
AD		 238 return FM10K_ERR_PARAM;
239
240 /* Loop through the table updating all required VLANs */
241 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;
242 len < FM10K_VLAN_TABLE_VID_MAX;
243 len -= 32 - bit, reg++, bit = 0) {
244 /* record the initial state of the register */
245 vlan_table = fm10k_read_reg(hw, reg);
246
247 /* truncate mask if we are at the start or end of the run */
248 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;
249
250 /* make necessary modifications to the register */
251 mask &= set ? ~vlan_table : vlan_table;
252 if (mask)
253 fm10k_write_reg(hw, reg, vlan_table ^ mask);
254 }
255
256 return 0;
257}
258
b6fec18f
AD		 259/**
260 * fm10k_read_mac_addr_pf - Read device MAC address
261 * @hw: pointer to the HW structure
262 *
263 * Reads the device MAC address from the SM_AREA and stores the value.
264 **/
265static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)
266{
267 u8 perm_addr[ETH_ALEN];
268 u32 serial_num;
269 int i;
270
271 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1));
272
273 /* last byte should be all 1's */
274 if ((~serial_num) << 24)
275 return FM10K_ERR_INVALID_MAC_ADDR;
276
277 perm_addr[0] = (u8)(serial_num >> 24);
278 perm_addr[1] = (u8)(serial_num >> 16);
279 perm_addr[2] = (u8)(serial_num >> 8);
280
281 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0));
282
283 /* first byte should be all 1's */
284 if ((~serial_num) >> 24)
285 return FM10K_ERR_INVALID_MAC_ADDR;
286
287 perm_addr[3] = (u8)(serial_num >> 16);
288 perm_addr[4] = (u8)(serial_num >> 8);
289 perm_addr[5] = (u8)(serial_num);
290
291 for (i = 0; i < ETH_ALEN; i++) {
292 hw->mac.perm_addr[i] = perm_addr[i];
293 hw->mac.addr[i] = perm_addr[i];
294 }
295
296 return 0;
297}
298
401b5383
AD		 299/**
300 * fm10k_glort_valid_pf - Validate that the provided glort is valid
301 * @hw: pointer to the HW structure
302 * @glort: base glort to be validated
303 *
304 * This function will return an error if the provided glort is invalid
305 **/
306bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)
307{
308 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;
309
310 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);
311}
312
313/**
eca32047 314 * fm10k_update_xc_addr_pf - Update device addresses
401b5383
AD		 315 * @hw: pointer to the HW structure
316 * @glort: base resource tag for this request
317 * @mac: MAC address to add/remove from table
318 * @vid: VLAN ID to add/remove from table
319 * @add: Indicates if this is an add or remove operation
320 * @flags: flags field to indicate add and secure
321 *
322 * This function generates a message to the Switch API requesting
323 * that the given logical port add/remove the given L2 MAC/VLAN address.
324 **/
325static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
326 const u8 *mac, u16 vid, bool add, u8 flags)
327{
328 struct fm10k_mbx_info *mbx = &hw->mbx;
329 struct fm10k_mac_update mac_update;
330 u32 msg[5];
331
b32d15b9
JK		 332 /* clear set bit from VLAN ID */
333 vid &= ~FM10K_VLAN_CLEAR;
334
33a44c28
MV		 335 /* if glort or vlan are not valid return error */
336 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)
401b5383
AD		 337 return FM10K_ERR_PARAM;
338
401b5383
AD		 339 /* record fields */
340 mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) |
341 ((u32)mac[3] << 16) |
342 ((u32)mac[4] << 8) |
343 ((u32)mac[5]));
9d4955b4
JK		 344 mac_update.mac_upper = cpu_to_le16(((u16)mac[0] << 8) |
345 ((u16)mac[1]));
401b5383
AD		 346 mac_update.vlan = cpu_to_le16(vid);
347 mac_update.glort = cpu_to_le16(glort);
348 mac_update.action = add ? 0 : 1;
349 mac_update.flags = flags;
350
351 /* populate mac_update fields */
352 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);
353 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,
354 &mac_update, sizeof(mac_update));
355
356 /* load onto outgoing mailbox */
357 return mbx->ops.enqueue_tx(hw, mbx, msg);
358}
359
360/**
eca32047 361 * fm10k_update_uc_addr_pf - Update device unicast addresses
401b5383
AD		 362 * @hw: pointer to the HW structure
363 * @glort: base resource tag for this request
364 * @mac: MAC address to add/remove from table
365 * @vid: VLAN ID to add/remove from table
366 * @add: Indicates if this is an add or remove operation
367 * @flags: flags field to indicate add and secure
368 *
369 * This function is used to add or remove unicast addresses for
370 * the PF.
371 **/
372static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,
373 const u8 *mac, u16 vid, bool add, u8 flags)
374{
375 /* verify MAC address is valid */
376 if (!is_valid_ether_addr(mac))
377 return FM10K_ERR_PARAM;
378
379 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);
380}
381
382/**
383 * fm10k_update_mc_addr_pf - Update device multicast addresses
384 * @hw: pointer to the HW structure
385 * @glort: base resource tag for this request
386 * @mac: MAC address to add/remove from table
387 * @vid: VLAN ID to add/remove from table
388 * @add: Indicates if this is an add or remove operation
389 *
390 * This function is used to add or remove multicast MAC addresses for
391 * the PF.
392 **/
393static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,
394 const u8 *mac, u16 vid, bool add)
395{
396 /* verify multicast address is valid */
397 if (!is_multicast_ether_addr(mac))
398 return FM10K_ERR_PARAM;
399
400 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);
401}
402
403/**
404 * fm10k_update_xcast_mode_pf - Request update of multicast mode
405 * @hw: pointer to hardware structure
406 * @glort: base resource tag for this request
407 * @mode: integer value indicating mode being requested
408 *
409 * This function will attempt to request a higher mode for the port
410 * so that it can enable either multicast, multicast promiscuous, or
411 * promiscuous mode of operation.
412 **/
413static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)
414{
415 struct fm10k_mbx_info *mbx = &hw->mbx;
416 u32 msg[3], xcast_mode;
417
418 if (mode > FM10K_XCAST_MODE_NONE)
419 return FM10K_ERR_PARAM;
420 /* if glort is not valid return error */
421 if (!fm10k_glort_valid_pf(hw, glort))
422 return FM10K_ERR_PARAM;
423
424 /* write xcast mode as a single u32 value,
425 * lower 16 bits: glort
426 * upper 16 bits: mode
427 */
428 xcast_mode = ((u32)mode << 16) | glort;
429
430 /* generate message requesting to change xcast mode */
431 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);
432 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);
433
434 /* load onto outgoing mailbox */
435 return mbx->ops.enqueue_tx(hw, mbx, msg);
436}
437
438/**
439 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list
440 * @hw: pointer to hardware structure
441 *
442 * This function walks through the MSI-X vector table to determine the
443 * number of active interrupts and based on that information updates the
444 * interrupt moderator linked list.
445 **/
446static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)
447{
448 u32 i;
449
450 /* Disable interrupt moderator */
451 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
452
453 /* loop through PF from last to first looking enabled vectors */
454 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {
455 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
456 break;
457 }
458
eca32047 459 /* always reset VFITR2[0] to point to last enabled PF vector */
401b5383
AD		 460 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
461
462 /* reset ITR2[0] to point to last enabled PF vector */
c2653865
AD		 463 if (!hw->iov.num_vfs)
464 fm10k_write_reg(hw, FM10K_ITR2(0), i);
401b5383
AD		 465
466 /* Enable interrupt moderator */
467 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
468}
469
470/**
471 * fm10k_update_lport_state_pf - Notify the switch of a change in port state
472 * @hw: pointer to the HW structure
473 * @glort: base resource tag for this request
474 * @count: number of logical ports being updated
475 * @enable: boolean value indicating enable or disable
476 *
477 * This function is used to add/remove a logical port from the switch.
478 **/
479static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,
480 u16 count, bool enable)
481{
482 struct fm10k_mbx_info *mbx = &hw->mbx;
483 u32 msg[3], lport_msg;
484
485 /* do nothing if we are being asked to create or destroy 0 ports */
486 if (!count)
487 return 0;
488
489 /* if glort is not valid return error */
490 if (!fm10k_glort_valid_pf(hw, glort))
491 return FM10K_ERR_PARAM;
492
493 /* construct the lport message from the 2 pieces of data we have */
494 lport_msg = ((u32)count << 16) | glort;
495
496 /* generate lport create/delete message */
497 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :
498 FM10K_PF_MSG_ID_LPORT_DELETE);
499 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);
500
501 /* load onto outgoing mailbox */
502 return mbx->ops.enqueue_tx(hw, mbx, msg);
503}
504
505/**
506 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
507 * @hw: pointer to hardware structure
508 * @dglort: pointer to dglort configuration structure
509 *
510 * Reads the configuration structure contained in dglort_cfg and uses
511 * that information to then populate a DGLORTMAP/DEC entry and the queues
512 * to which it has been assigned.
513 **/
514static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,
515 struct fm10k_dglort_cfg *dglort)
516{
517 u16 glort, queue_count, vsi_count, pc_count;
518 u16 vsi, queue, pc, q_idx;
519 u32 txqctl, dglortdec, dglortmap;
520
521 /* verify the dglort pointer */
522 if (!dglort)
523 return FM10K_ERR_PARAM;
524
525 /* verify the dglort values */
526 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||
527 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||
528 (dglort->queue_l > 8) || (dglort->queue_b >= 256))
529 return FM10K_ERR_PARAM;
530
531 /* determine count of VSIs and queues */
532 queue_count = 1 << (dglort->rss_l + dglort->pc_l);
533 vsi_count = 1 << (dglort->vsi_l + dglort->queue_l);
534 glort = dglort->glort;
535 q_idx = dglort->queue_b;
536
537 /* configure SGLORT for queues */
538 for (vsi = 0; vsi < vsi_count; vsi++, glort++) {
539 for (queue = 0; queue < queue_count; queue++, q_idx++) {
540 if (q_idx >= FM10K_MAX_QUEUES)
541 break;
542
543 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort);
544 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort);
545 }
546 }
547
548 /* determine count of PCs and queues */
549 queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l);
550 pc_count = 1 << dglort->pc_l;
551
552 /* configure PC for Tx queues */
553 for (pc = 0; pc < pc_count; pc++) {
554 q_idx = pc + dglort->queue_b;
555 for (queue = 0; queue < queue_count; queue++) {
556 if (q_idx >= FM10K_MAX_QUEUES)
557 break;
558
559 txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx));
560 txqctl &= ~FM10K_TXQCTL_PC_MASK;
561 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT;
562 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl);
563
564 q_idx += pc_count;
565 }
566 }
567
568 /* configure DGLORTDEC */
569 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |
570 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |
571 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |
572 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |
573 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |
574 ((u32)(dglort->queue_l));
575 if (dglort->inner_rss)
576 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE;
577
578 /* configure DGLORTMAP */
579 dglortmap = (dglort->idx == fm10k_dglort_default) ?
580 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;
581 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;
582 dglortmap |= dglort->glort;
583
584 /* write values to hardware */
585 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
586 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
587
588 return 0;
589}
590
c2653865
AD		 591u16 fm10k_queues_per_pool(struct fm10k_hw *hw)
592{
593 u16 num_pools = hw->iov.num_pools;
594
595 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?
596 8 : FM10K_MAX_QUEUES_POOL;
597}
598
599u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)
600{
601 u16 num_vfs = hw->iov.num_vfs;
602 u16 vf_q_idx = FM10K_MAX_QUEUES;
603
604 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);
605
606 return vf_q_idx;
607}
608
609static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)
610{
611 u16 num_pools = hw->iov.num_pools;
612
613 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :
614 FM10K_MAX_VECTORS_POOL;
615}
616
617static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)
618{
619 u16 vf_v_idx = FM10K_MAX_VECTORS_PF;
620
621 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;
622
623 return vf_v_idx;
624}
625
626/**
627 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
628 * @hw: pointer to the HW structure
629 * @num_vfs: number of VFs to be allocated
630 * @num_pools: number of virtualization pools to be allocated
631 *
632 * Allocates queues and traffic classes to virtualization entities to prepare
633 * the PF for SR-IOV and VMDq
634 **/
635static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
636 u16 num_pools)
637{
638 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;
639 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;
640 int i, j;
641
642 /* hardware only supports up to 64 pools */
643 if (num_pools > 64)
644 return FM10K_ERR_PARAM;
645
646 /* the number of VFs cannot exceed the number of pools */
647 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))
648 return FM10K_ERR_PARAM;
649
650 /* record number of virtualization entities */
651 hw->iov.num_vfs = num_vfs;
652 hw->iov.num_pools = num_pools;
653
654 /* determine qmap offsets and counts */
655 qmap_stride = (num_vfs > 8) ? 32 : 256;
656 qpp = fm10k_queues_per_pool(hw);
657 vpp = fm10k_vectors_per_pool(hw);
658
659 /* calculate starting index for queues */
660 vf_q_idx = fm10k_vf_queue_index(hw, 0);
661 qmap_idx = 0;
662
663 /* establish TCs with -1 credits and no quanta to prevent transmit */
664 for (i = 0; i < num_vfs; i++) {
665 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0);
666 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0);
667 fm10k_write_reg(hw, FM10K_TC_CREDIT(i),
668 FM10K_TC_CREDIT_CREDIT_MASK);
669 }
670
671 /* zero out all mbmem registers */
672 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)
673 fm10k_write_reg(hw, FM10K_MBMEM(i), 0);
674
675 /* clear event notification of VF FLR */
676 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0);
677 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0);
678
679 /* loop through unallocated rings assigning them back to PF */
680 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
681 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
ded8b20d
JK		 682 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF |
683 FM10K_TXQCTL_UNLIMITED_BW | vid);
c2653865
AD		 684 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
685 }
686
687 /* PF should have already updated VFITR2[0] */
688
689 /* update all ITR registers to flow to VFITR2[0] */
690 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {
691 if (!(i & (vpp - 1)))
692 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp);
693 else
694 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
695 }
696
697 /* update PF ITR2[0] to reference the last vector */
698 fm10k_write_reg(hw, FM10K_ITR2(0),
699 fm10k_vf_vector_index(hw, num_vfs - 1));
700
701 /* loop through rings populating rings and TCs */
702 for (i = 0; i < num_vfs; i++) {
703 /* record index for VF queue 0 for use in end of loop */
704 vf_q_idx0 = vf_q_idx;
705
706 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {
707 /* assign VF and locked TC to queues */
708 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
709 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx),
710 (i << FM10K_TXQCTL_TC_SHIFT) | i |
711 FM10K_TXQCTL_VF | vid);
712 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx),
713 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
714 FM10K_RXDCTL_DROP_ON_EMPTY);
715 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx),
716 FM10K_RXQCTL_VF |
717 (i << FM10K_RXQCTL_VF_SHIFT));
718
719 /* map queue pair to VF */
720 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
721 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
722 }
723
724 /* repeat the first ring for all of the remaining VF rings */
725 for (; j < qmap_stride; j++, qmap_idx++) {
726 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
727 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
728 }
729 }
730
731 /* loop through remaining indexes assigning all to queue 0 */
732 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {
733 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
734 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0);
735 qmap_idx++;
736 }
737
738 return 0;
739}
740
741/**
742 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF
743 * @hw: pointer to the HW structure
744 * @vf_idx: index of VF receiving GLORT
745 * @rate: Rate indicated in Mb/s
746 *
747 * Configured the TC for a given VF to allow only up to a given number
748 * of Mb/s of outgoing Tx throughput.
749 **/
750static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)
751{
752 /* configure defaults */
753 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;
754 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;
755
756 /* verify vf is in range */
757 if (vf_idx >= hw->iov.num_vfs)
758 return FM10K_ERR_PARAM;
759
760 /* set interval to align with 4.096 usec in all modes */
761 switch (hw->bus.speed) {
762 case fm10k_bus_speed_2500:
763 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1;
764 break;
765 case fm10k_bus_speed_5000:
766 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2;
767 break;
768 default:
769 break;
770 }
771
772 if (rate) {
773 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)
774 return FM10K_ERR_PARAM;
775
776 /* The quanta is measured in Bytes per 4.096 or 8.192 usec
777 * The rate is provided in Mbits per second
778 * To tralslate from rate to quanta we need to multiply the
779 * rate by 8.192 usec and divide by 8 bits/byte. To avoid
780 * dealing with floating point we can round the values up
781 * to the nearest whole number ratio which gives us 128 / 125.
782 */
783 tc_rate = (rate * 128) / 125;
784
785 /* try to keep the rate limiting accurate by increasing
786 * the number of credits and interval for rates less than 4Gb/s
787 */
788 if (rate < 4000)
789 interval <<= 1;
790 else
791 tc_rate >>= 1;
792 }
793
794 /* update rate limiter with new values */
795 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
796 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
797 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
798
799 return 0;
800}
801
802/**
803 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
804 * @hw: pointer to the HW structure
805 * @vf_idx: index of VF receiving GLORT
806 *
807 * Update the interrupt moderator linked list to include any MSI-X
808 * interrupts which the VF has enabled in the MSI-X vector table.
809 **/
810static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)
811{
812 u16 vf_v_idx, vf_v_limit, i;
813
814 /* verify vf is in range */
815 if (vf_idx >= hw->iov.num_vfs)
816 return FM10K_ERR_PARAM;
817
eca32047 818 /* determine vector offset and count */
c2653865
AD		 819 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
820 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
821
822 /* search for first vector that is not masked */
823 for (i = vf_v_limit - 1; i > vf_v_idx; i--) {
824 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
825 break;
826 }
827
828 /* reset linked list so it now includes our active vectors */
829 if (vf_idx == (hw->iov.num_vfs - 1))
830 fm10k_write_reg(hw, FM10K_ITR2(0), i);
831 else
832 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i);
833
834 return 0;
835}
836
837/**
838 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
839 * @hw: pointer to the HW structure
840 * @vf_info: pointer to VF information structure
841 *
842 * Assign a MAC address and default VLAN to a VF and notify it of the update
843 **/
844static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
845 struct fm10k_vf_info *vf_info)
846{
847 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;
848 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;
849 s32 err = 0;
850 u16 vf_idx, vf_vid;
851
852 /* verify vf is in range */
853 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)
854 return FM10K_ERR_PARAM;
855
856 /* determine qmap offsets and counts */
857 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
858 queues_per_pool = fm10k_queues_per_pool(hw);
859
860 /* calculate starting index for queues */
861 vf_idx = vf_info->vf_idx;
862 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
863 qmap_idx = qmap_stride * vf_idx;
864
865 /* MAP Tx queue back to 0 temporarily, and disable it */
866 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
867 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
868
869 /* determine correct default VLAN ID */
870 if (vf_info->pf_vid)
871 vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR;
872 else
873 vf_vid = vf_info->sw_vid;
874
875 /* generate MAC_ADDR request */
876 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
877 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,
878 vf_info->mac, vf_vid);
879
880 /* load onto outgoing mailbox, ignore any errors on enqueue */
881 if (vf_info->mbx.ops.enqueue_tx)
882 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
883
884 /* verify ring has disabled before modifying base address registers */
885 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
886 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {
887 /* limit ourselves to a 1ms timeout */
888 if (timeout == 10) {
889 err = FM10K_ERR_DMA_PENDING;
890 goto err_out;
891 }
892
893 usleep_range(100, 200);
894 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
895 }
896
897 /* Update base address registers to contain MAC address */
898 if (is_valid_ether_addr(vf_info->mac)) {
899 tdbal = (((u32)vf_info->mac[3]) << 24) |
900 (((u32)vf_info->mac[4]) << 16) |
901 (((u32)vf_info->mac[5]) << 8);
902
903 tdbah = (((u32)0xFF) << 24) |
904 (((u32)vf_info->mac[0]) << 16) |
905 (((u32)vf_info->mac[1]) << 8) |
906 ((u32)vf_info->mac[2]);
907 }
908
909 /* Record the base address into queue 0 */
910 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal);
911 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah);
912
20076fa1
JK		 913 /* Provide the VF the ITR scale, using software-defined fields in TDLEN
914 * to pass the information during VF initialization. See definition of
915 * FM10K_TDLEN_ITR_SCALE_SHIFT for more details.
916 */
917 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale <<
918 FM10K_TDLEN_ITR_SCALE_SHIFT);
919
c2653865
AD		 920err_out:
921 /* configure Queue control register */
922 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
923 FM10K_TXQCTL_VID_MASK;
924 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
925 FM10K_TXQCTL_VF | vf_idx;
926
927 /* assign VID */
928 for (i = 0; i < queues_per_pool; i++)
929 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
930
931 /* restore the queue back to VF ownership */
932 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
933 return err;
934}
935
936/**
937 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
938 * @hw: pointer to the HW structure
939 * @vf_info: pointer to VF information structure
940 *
941 * Reassign the interrupts and queues to a VF following an FLR
942 **/
943static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
944 struct fm10k_vf_info *vf_info)
945{
946 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;
947 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl;
948 u16 vf_v_idx, vf_v_limit, vf_vid;
949 u8 vf_idx = vf_info->vf_idx;
950 int i;
951
952 /* verify vf is in range */
953 if (vf_idx >= hw->iov.num_vfs)
954 return FM10K_ERR_PARAM;
955
956 /* clear event notification of VF FLR */
957 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32));
958
959 /* force timeout and then disconnect the mailbox */
960 vf_info->mbx.timeout = 0;
961 if (vf_info->mbx.ops.disconnect)
962 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx);
963
eca32047 964 /* determine vector offset and count */
c2653865
AD		 965 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
966 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
967
968 /* determine qmap offsets and counts */
969 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
970 queues_per_pool = fm10k_queues_per_pool(hw);
971 qmap_idx = qmap_stride * vf_idx;
972
973 /* make all the queues inaccessible to the VF */
974 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {
975 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
976 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
977 }
978
979 /* calculate starting index for queues */
980 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
981
982 /* determine correct default VLAN ID */
983 if (vf_info->pf_vid)
984 vf_vid = vf_info->pf_vid;
985 else
986 vf_vid = vf_info->sw_vid;
987
988 /* configure Queue control register */
989 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |
990 (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
991 FM10K_TXQCTL_VF | vf_idx;
992 rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT);
993
994 /* stop further DMA and reset queue ownership back to VF */
995 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {
996 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
997 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
998 fm10k_write_reg(hw, FM10K_RXDCTL(i),
999 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
1000 FM10K_RXDCTL_DROP_ON_EMPTY);
1001 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl);
1002 }
1003
1004 /* reset TC with -1 credits and no quanta to prevent transmit */
1005 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
1006 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0);
1007 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx),
1008 FM10K_TC_CREDIT_CREDIT_MASK);
1009
1010 /* update our first entry in the table based on previous VF */
1011 if (!vf_idx)
1012 hw->mac.ops.update_int_moderator(hw);
1013 else
1014 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1);
1015
1016 /* reset linked list so it now includes our active vectors */
1017 if (vf_idx == (hw->iov.num_vfs - 1))
1018 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx);
1019 else
1020 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
1021
1022 /* link remaining vectors so that next points to previous */
1023 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)
1024 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
1025
1026 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1027 for (i = FM10K_VFMBMEM_LEN; i--;)
1028 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
1029 for (i = FM10K_VLAN_TABLE_SIZE; i--;)
1030 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
1031 for (i = FM10K_RETA_SIZE; i--;)
1032 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0);
1033 for (i = FM10K_RSSRK_SIZE; i--;)
1034 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
1035 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0);
1036
1037 /* Update base address registers to contain MAC address */
1038 if (is_valid_ether_addr(vf_info->mac)) {
1039 tdbal = (((u32)vf_info->mac[3]) << 24) |
1040 (((u32)vf_info->mac[4]) << 16) |
1041 (((u32)vf_info->mac[5]) << 8);
1042 tdbah = (((u32)0xFF) << 24) |
1043 (((u32)vf_info->mac[0]) << 16) |
1044 (((u32)vf_info->mac[1]) << 8) |
1045 ((u32)vf_info->mac[2]);
1046 }
1047
eca32047 1048 /* map queue pairs back to VF from last to first */
c2653865
AD		 1049 for (i = queues_per_pool; i--;) {
1050 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
1051 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
20076fa1
JK		 1052 /* See definition of FM10K_TDLEN_ITR_SCALE_SHIFT for an
1053 * explanation of how TDLEN is used.
1054 */
1055 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx + i),
1056 hw->mac.itr_scale <<
1057 FM10K_TDLEN_ITR_SCALE_SHIFT);
c2653865
AD		 1058 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
1059 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
1060 }
1061
fba341d5
JK		 1062 /* repeat the first ring for all the remaining VF rings */
1063 for (i = queues_per_pool; i < qmap_stride; i++) {
1064 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx);
1065 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx);
1066 }
1067
c2653865
AD		 1068 return 0;
1069}
1070
1071/**
1072 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1073 * @hw: pointer to hardware structure
1074 * @vf_info: pointer to VF information structure
1075 * @lport_idx: Logical port offset from the hardware glort
1076 * @flags: Set of capability flags to extend port beyond basic functionality
1077 *
1078 * This function allows enabling a VF port by assigning it a GLORT and
1079 * setting the flags so that it can enable an Rx mode.
1080 **/
1081static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,
1082 struct fm10k_vf_info *vf_info,
1083 u16 lport_idx, u8 flags)
1084{
1085 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;
1086
1087 /* if glort is not valid return error */
1088 if (!fm10k_glort_valid_pf(hw, glort))
1089 return FM10K_ERR_PARAM;
1090
1091 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;
1092 vf_info->glort = glort;
1093
1094 return 0;
1095}
1096
1097/**
1098 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1099 * @hw: pointer to hardware structure
1100 * @vf_info: pointer to VF information structure
1101 *
1102 * This function disables a VF port by stripping it of a GLORT and
1103 * setting the flags so that it cannot enable any Rx mode.
1104 **/
1105static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,
1106 struct fm10k_vf_info *vf_info)
1107{
1108 u32 msg[1];
1109
1110 /* need to disable the port if it is already enabled */
1111 if (FM10K_VF_FLAG_ENABLED(vf_info)) {
1112 /* notify switch that this port has been disabled */
1113 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);
1114
1115 /* generate port state response to notify VF it is not ready */
1116 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1117 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1118 }
1119
1120 /* clear flags and glort if it exists */
1121 vf_info->vf_flags = 0;
1122 vf_info->glort = 0;
1123}
1124
1125/**
1126 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1127 * @hw: pointer to hardware structure
1128 * @q: stats for all queues of a VF
1129 * @vf_idx: index of VF
1130 *
1131 * This function collects queue stats for VFs.
1132 **/
1133static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,
1134 struct fm10k_hw_stats_q *q,
1135 u16 vf_idx)
1136{
1137 u32 idx, qpp;
1138
1139 /* get stats for all of the queues */
1140 qpp = fm10k_queues_per_pool(hw);
1141 idx = fm10k_vf_queue_index(hw, vf_idx);
1142 fm10k_update_hw_stats_q(hw, q, idx, qpp);
1143}
1144
5f226ddb
AD		 1145static s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw,
1146 struct fm10k_vf_info *vf_info,
1147 u64 timestamp)
1148{
1149 u32 msg[4];
1150
1151 /* generate port state response to notify VF it is not ready */
1152 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588);
1153 fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp);
1154
1155 return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1156}
1157
c2653865
AD		 1158/**
1159 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1160 * @hw: Pointer to hardware structure
1161 * @results: Pointer array to message, results[0] is pointer to message
1162 * @mbx: Pointer to mailbox information structure
1163 *
1164 * This function is a default handler for MSI-X requests from the VF. The
1165 * assumption is that in this case it is acceptable to just directly
eca32047 1166 * hand off the message from the VF to the underlying shared code.
c2653865
AD		 1167 **/
1168s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results,
1169 struct fm10k_mbx_info *mbx)
1170{
1171 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1172 u8 vf_idx = vf_info->vf_idx;
1173
1174 return hw->iov.ops.assign_int_moderator(hw, vf_idx);
1175}
1176
9adbac59
JK		 1177/**
1178 * fm10k_iov_select_vid - Select correct default VID
1179 * @hw: Pointer to hardware structure
1180 * @vid: VID to correct
1181 *
1182 * Will report an error if VID is out of range. For VID = 0, it will return
1183 * either the pf_vid or sw_vid depending on which one is set.
1184 */
1185static inline s32 fm10k_iov_select_vid(struct fm10k_vf_info *vf_info, u16 vid)
1186{
1187 if (!vid)
1188 return vf_info->pf_vid ? vf_info->pf_vid : vf_info->sw_vid;
1189 else if (vf_info->pf_vid && vid != vf_info->pf_vid)
1190 return FM10K_ERR_PARAM;
1191 else
1192 return vid;
1193}
1194
c2653865
AD		 1195/**
1196 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1197 * @hw: Pointer to hardware structure
1198 * @results: Pointer array to message, results[0] is pointer to message
1199 * @mbx: Pointer to mailbox information structure
1200 *
1201 * This function is a default handler for MAC/VLAN requests from the VF.
1202 * The assumption is that in this case it is acceptable to just directly
eca32047 1203 * hand off the message from the VF to the underlying shared code.
c2653865
AD		 1204 **/
1205s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
1206 struct fm10k_mbx_info *mbx)
1207{
1208 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
c2653865
AD		 1209 u8 mac[ETH_ALEN];
1210 u32 *result;
9adbac59
JK		 1211 int err = 0;
1212 bool set;
c2653865
AD		 1213 u16 vlan;
1214 u32 vid;
1215
1216 /* we shouldn't be updating rules on a disabled interface */
1217 if (!FM10K_VF_FLAG_ENABLED(vf_info))
1218 err = FM10K_ERR_PARAM;
1219
1220 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {
1221 result = results[FM10K_MAC_VLAN_MSG_VLAN];
1222
1223 /* record VLAN id requested */
1224 err = fm10k_tlv_attr_get_u32(result, &vid);
1225 if (err)
1226 return err;
1227
9adbac59
JK		 1228 /* verify upper 16 bits are zero */
1229 if (vid >> 16)
c2653865 1230 return FM10K_ERR_PARAM;
9adbac59
JK		 1231
1232 set = !(vid & FM10K_VLAN_CLEAR);
1233 vid &= ~FM10K_VLAN_CLEAR;
1234
cdf32c94 1235 err = fm10k_iov_select_vid(vf_info, (u16)vid);
9adbac59
JK		 1236 if (err < 0)
1237 return err;
1238 else
1239 vid = err;
c2653865
AD		 1240
1241 /* update VSI info for VF in regards to VLAN table */
9adbac59 1242 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, set);
c2653865
AD		 1243 }
1244
1245 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {
1246 result = results[FM10K_MAC_VLAN_MSG_MAC];
1247
1248 /* record unicast MAC address requested */
1249 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1250 if (err)
1251 return err;
1252
1253 /* block attempts to set MAC for a locked device */
1254 if (is_valid_ether_addr(vf_info->mac) &&
1255 memcmp(mac, vf_info->mac, ETH_ALEN))
1256 return FM10K_ERR_PARAM;
1257
9adbac59
JK		 1258 set = !(vlan & FM10K_VLAN_CLEAR);
1259 vlan &= ~FM10K_VLAN_CLEAR;
1260
1261 err = fm10k_iov_select_vid(vf_info, vlan);
1262 if (err < 0)
1263 return err;
1264 else
cdf32c94 1265 vlan = (u16)err;
c2653865
AD		 1266
1267 /* notify switch of request for new unicast address */
9adbac59
JK		 1268 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort,
1269 mac, vlan, set, 0);
c2653865
AD		 1270 }
1271
1272 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {
1273 result = results[FM10K_MAC_VLAN_MSG_MULTICAST];
1274
1275 /* record multicast MAC address requested */
1276 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1277 if (err)
1278 return err;
1279
1280 /* verify that the VF is allowed to request multicast */
1281 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))
1282 return FM10K_ERR_PARAM;
1283
9adbac59
JK		 1284 set = !(vlan & FM10K_VLAN_CLEAR);
1285 vlan &= ~FM10K_VLAN_CLEAR;
1286
1287 err = fm10k_iov_select_vid(vf_info, vlan);
1288 if (err < 0)
1289 return err;
1290 else
cdf32c94 1291 vlan = (u16)err;
c2653865
AD		 1292
1293 /* notify switch of request for new multicast address */
9adbac59
JK		 1294 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort,
1295 mac, vlan, set);
c2653865
AD		 1296 }
1297
1298 return err;
1299}
1300
1301/**
1302 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1303 * @vf_info: VF info structure containing capability flags
1304 * @mode: Requested xcast mode
1305 *
1306 * This function outputs the mode that most closely matches the requested
1307 * mode. If not modes match it will request we disable the port
1308 **/
1309static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,
1310 u8 mode)
1311{
1312 u8 vf_flags = vf_info->vf_flags;
1313
1314 /* match up mode to capabilities as best as possible */
1315 switch (mode) {
1316 case FM10K_XCAST_MODE_PROMISC:
1317 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)
1318 return FM10K_XCAST_MODE_PROMISC;
1319 /* fallthough */
1320 case FM10K_XCAST_MODE_ALLMULTI:
1321 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)
1322 return FM10K_XCAST_MODE_ALLMULTI;
1323 /* fallthough */
1324 case FM10K_XCAST_MODE_MULTI:
1325 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)
1326 return FM10K_XCAST_MODE_MULTI;
1327 /* fallthough */
1328 case FM10K_XCAST_MODE_NONE:
1329 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)
1330 return FM10K_XCAST_MODE_NONE;
1331 /* fallthough */
1332 default:
1333 break;
1334 }
1335
1336 /* disable interface as it should not be able to request any */
1337 return FM10K_XCAST_MODE_DISABLE;
1338}
1339
1340/**
1341 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1342 * @hw: Pointer to hardware structure
1343 * @results: Pointer array to message, results[0] is pointer to message
1344 * @mbx: Pointer to mailbox information structure
1345 *
1346 * This function is a default handler for port state requests. The port
1347 * state requests for now are basic and consist of enabling or disabling
1348 * the port.
1349 **/
1350s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,
1351 struct fm10k_mbx_info *mbx)
1352{
1353 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1354 u32 *result;
1355 s32 err = 0;
1356 u32 msg[2];
1357 u8 mode = 0;
1358
1359 /* verify VF is allowed to enable even minimal mode */
1360 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))
1361 return FM10K_ERR_PARAM;
1362
1363 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {
1364 result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];
1365
1366 /* XCAST mode update requested */
1367 err = fm10k_tlv_attr_get_u8(result, &mode);
1368 if (err)
1369 return FM10K_ERR_PARAM;
1370
1371 /* prep for possible demotion depending on capabilities */
1372 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);
1373
1374 /* if mode is not currently enabled, enable it */
1375 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode)))
1376 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);
1377
1378 /* swap mode back to a bit flag */
1379 mode = FM10K_VF_FLAG_SET_MODE(mode);
1380 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {
1381 /* need to disable the port if it is already enabled */
1382 if (FM10K_VF_FLAG_ENABLED(vf_info))
1383 err = fm10k_update_lport_state_pf(hw, vf_info->glort,
1384 1, false);
1385
ee4373e7
JK		 1386 /* we need to clear VF_FLAG_ENABLED flags in order to ensure
1387 * that we actually re-enable the LPORT state below. Note that
1388 * this has no impact if the VF is already disabled, as the
1389 * flags are already cleared.
1390 */
1391 if (!err)
1392 vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info);
1393
c2653865
AD		 1394 /* when enabling the port we should reset the rate limiters */
1395 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);
1396
1397 /* set mode for minimal functionality */
1398 mode = FM10K_VF_FLAG_SET_MODE_NONE;
1399
1400 /* generate port state response to notify VF it is ready */
1401 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1402 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);
1403 mbx->ops.enqueue_tx(hw, mbx, msg);
1404 }
1405
1406 /* if enable state toggled note the update */
1407 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))
1408 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,
1409 !!mode);
1410
1411 /* if state change succeeded, then update our stored state */
1412 mode |= FM10K_VF_FLAG_CAPABLE(vf_info);
1413 if (!err)
1414 vf_info->vf_flags = mode;
1415
1416 return err;
1417}
1418
1419const struct fm10k_msg_data fm10k_iov_msg_data_pf[] = {
1420 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
1421 FM10K_VF_MSG_MSIX_HANDLER(fm10k_iov_msg_msix_pf),
1422 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_iov_msg_mac_vlan_pf),
1423 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_iov_msg_lport_state_pf),
1424 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1425};
1426
b6fec18f
AD		 1427/**
1428 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF
1429 * @hw: pointer to hardware structure
1430 * @stats: pointer to the stats structure to update
1431 *
1432 * This function collects and aggregates global and per queue hardware
1433 * statistics.
1434 **/
1435static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,
1436 struct fm10k_hw_stats *stats)
1437{
1438 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;
1439 u32 id, id_prev;
1440
1441 /* Use Tx queue 0 as a canary to detect a reset */
1442 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1443
1444 /* Read Global Statistics */
1445 do {
1446 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,
1447 &stats->timeout);
1448 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);
1449 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);
1450 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);
1451 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);
1452 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,
1453 &stats->vlan_drop);
1454 loopback_drop = fm10k_read_hw_stats_32b(hw,
1455 FM10K_STATS_LOOPBACK_DROP,
eca32047 1456 &stats->loopback_drop);
b6fec18f
AD		 1457 nodesc_drop = fm10k_read_hw_stats_32b(hw,
1458 FM10K_STATS_NODESC_DROP,
1459 &stats->nodesc_drop);
1460
1461 /* if value has not changed then we have consistent data */
1462 id_prev = id;
1463 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1464 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);
1465
1466 /* drop non-ID bits and set VALID ID bit */
1467 id &= FM10K_TXQCTL_ID_MASK;
1468 id |= FM10K_STAT_VALID;
1469
1470 /* Update Global Statistics */
1471 if (stats->stats_idx == id) {
1472 stats->timeout.count += timeout;
1473 stats->ur.count += ur;
1474 stats->ca.count += ca;
1475 stats->um.count += um;
1476 stats->xec.count += xec;
1477 stats->vlan_drop.count += vlan_drop;
1478 stats->loopback_drop.count += loopback_drop;
1479 stats->nodesc_drop.count += nodesc_drop;
1480 }
1481
1482 /* Update bases and record current PF id */
1483 fm10k_update_hw_base_32b(&stats->timeout, timeout);
1484 fm10k_update_hw_base_32b(&stats->ur, ur);
1485 fm10k_update_hw_base_32b(&stats->ca, ca);
1486 fm10k_update_hw_base_32b(&stats->um, um);
1487 fm10k_update_hw_base_32b(&stats->xec, xec);
1488 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);
1489 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);
1490 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);
1491 stats->stats_idx = id;
1492
1493 /* Update Queue Statistics */
1494 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
1495}
1496
1497/**
1498 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1499 * @hw: pointer to hardware structure
1500 * @stats: pointer to the stats structure to update
1501 *
1502 * This function resets the base for global and per queue hardware
1503 * statistics.
1504 **/
1505static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,
1506 struct fm10k_hw_stats *stats)
1507{
1508 /* Unbind Global Statistics */
1509 fm10k_unbind_hw_stats_32b(&stats->timeout);
1510 fm10k_unbind_hw_stats_32b(&stats->ur);
1511 fm10k_unbind_hw_stats_32b(&stats->ca);
1512 fm10k_unbind_hw_stats_32b(&stats->um);
1513 fm10k_unbind_hw_stats_32b(&stats->xec);
1514 fm10k_unbind_hw_stats_32b(&stats->vlan_drop);
1515 fm10k_unbind_hw_stats_32b(&stats->loopback_drop);
1516 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop);
1517
1518 /* Unbind Queue Statistics */
1519 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
1520
1521 /* Reinitialize bases for all stats */
1522 fm10k_update_hw_stats_pf(hw, stats);
1523}
1524
401b5383
AD		 1525/**
1526 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1527 * @hw: pointer to hardware structure
1528 * @dma_mask: 64 bit DMA mask required for platform
1529 *
1530 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1531 * to limit the access to memory beyond what is physically in the system.
1532 **/
1533static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)
1534{
1535 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1536 u32 phyaddr = (u32)(dma_mask >> 32);
1537
1538 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr);
1539}
1540
b6fec18f
AD		 1541/**
1542 * fm10k_get_fault_pf - Record a fault in one of the interface units
1543 * @hw: pointer to hardware structure
1544 * @type: pointer to fault type register offset
1545 * @fault: pointer to memory location to record the fault
1546 *
1547 * Record the fault register contents to the fault data structure and
1548 * clear the entry from the register.
1549 *
1550 * Returns ERR_PARAM if invalid register is specified or no error is present.
1551 **/
1552static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,
1553 struct fm10k_fault *fault)
1554{
1555 u32 func;
1556
1557 /* verify the fault register is in range and is aligned */
1558 switch (type) {
1559 case FM10K_PCA_FAULT:
1560 case FM10K_THI_FAULT:
1561 case FM10K_FUM_FAULT:
1562 break;
1563 default:
1564 return FM10K_ERR_PARAM;
1565 }
1566
1567 /* only service faults that are valid */
1568 func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC);
1569 if (!(func & FM10K_FAULT_FUNC_VALID))
1570 return FM10K_ERR_PARAM;
1571
1572 /* read remaining fields */
1573 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI);
1574 fault->address <<= 32;
1575 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO);
1576 fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO);
1577
1578 /* clear valid bit to allow for next error */
1579 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
1580
1581 /* Record which function triggered the error */
1582 if (func & FM10K_FAULT_FUNC_PF)
1583 fault->func = 0;
1584 else
1585 fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >>
1586 FM10K_FAULT_FUNC_VF_SHIFT);
1587
1588 /* record fault type */
1589 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;
1590
1591 return 0;
1592}
1593
401b5383
AD		 1594/**
1595 * fm10k_request_lport_map_pf - Request LPORT map from the switch API
1596 * @hw: pointer to hardware structure
1597 *
1598 **/
1599static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)
1600{
1601 struct fm10k_mbx_info *mbx = &hw->mbx;
1602 u32 msg[1];
1603
1604 /* issue request asking for LPORT map */
1605 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);
1606
1607 /* load onto outgoing mailbox */
1608 return mbx->ops.enqueue_tx(hw, mbx, msg);
1609}
1610
1611/**
1612 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1613 * @hw: pointer to hardware structure
1614 * @switch_ready: pointer to boolean value that will record switch state
1615 *
1616 * This funciton will check the DMA_CTRL2 register and mailbox in order
1617 * to determine if the switch is ready for the PF to begin requesting
1618 * addresses and mapping traffic to the local interface.
1619 **/
1620static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)
1621{
1622 s32 ret_val = 0;
1623 u32 dma_ctrl2;
1624
eca32047 1625 /* verify the switch is ready for interaction */
401b5383
AD		 1626 dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
1627 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))
1628 goto out;
1629
1630 /* retrieve generic host state info */
1631 ret_val = fm10k_get_host_state_generic(hw, switch_ready);
1632 if (ret_val)
1633 goto out;
1634
1635 /* interface cannot receive traffic without logical ports */
1636 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE)
1637 ret_val = fm10k_request_lport_map_pf(hw);
1638
1639out:
1640 return ret_val;
1641}
1642
1643/* This structure defines the attibutes to be parsed below */
1644const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {
1645 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),
1646 FM10K_TLV_ATTR_LAST
1647};
1648
1649/**
1650 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1651 * @hw: Pointer to hardware structure
1652 * @results: pointer array containing parsed data
1653 * @mbx: Pointer to mailbox information structure
1654 *
1655 * This handler configures the lport mapping based on the reply from the
1656 * switch API.
1657 **/
1658s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,
1659 struct fm10k_mbx_info *mbx)
1660{
1661 u16 glort, mask;
1662 u32 dglort_map;
1663 s32 err;
1664
1665 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],
1666 &dglort_map);
1667 if (err)
1668 return err;
1669
1670 /* extract values out of the header */
1671 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);
1672 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);
1673
1674 /* verify mask is set and none of the masked bits in glort are set */
1675 if (!mask || (glort & ~mask))
1676 return FM10K_ERR_PARAM;
1677
1678 /* verify the mask is contiguous, and that it is 1's followed by 0's */
1679 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)
1680 return FM10K_ERR_PARAM;
1681
1682 /* record the glort, mask, and port count */
1683 hw->mac.dglort_map = dglort_map;
1684
1685 return 0;
1686}
1687
1688const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {
1689 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),
1690 FM10K_TLV_ATTR_LAST
1691};
1692
1693/**
1694 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1695 * @hw: Pointer to hardware structure
1696 * @results: pointer array containing parsed data
1697 * @mbx: Pointer to mailbox information structure
1698 *
1699 * This handler configures the default VLAN for the PF
1700 **/
1701s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,
1702 struct fm10k_mbx_info *mbx)
1703{
1704 u16 glort, pvid;
1705 u32 pvid_update;
1706 s32 err;
1707
1708 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1709 &pvid_update);
1710 if (err)
1711 return err;
1712
1713 /* extract values from the pvid update */
1714 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1715 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1716
1717 /* if glort is not valid return error */
1718 if (!fm10k_glort_valid_pf(hw, glort))
1719 return FM10K_ERR_PARAM;
1720
1721 /* verify VID is valid */
1722 if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1723 return FM10K_ERR_PARAM;
1724
1725 /* record the port VLAN ID value */
1726 hw->mac.default_vid = pvid;
1727
1728 return 0;
1729}
1730
1731/**
1732 * fm10k_record_global_table_data - Move global table data to swapi table info
1733 * @from: pointer to source table data structure
1734 * @to: pointer to destination table info structure
1735 *
1736 * This function is will copy table_data to the table_info contained in
1737 * the hw struct.
1738 **/
1739static void fm10k_record_global_table_data(struct fm10k_global_table_data *from,
1740 struct fm10k_swapi_table_info *to)
1741{
1742 /* convert from le32 struct to CPU byte ordered values */
1743 to->used = le32_to_cpu(from->used);
1744 to->avail = le32_to_cpu(from->avail);
1745}
1746
1747const struct fm10k_tlv_attr fm10k_err_msg_attr[] = {
1748 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1749 sizeof(struct fm10k_swapi_error)),
1750 FM10K_TLV_ATTR_LAST
1751};
1752
1753/**
1754 * fm10k_msg_err_pf - Message handler for error reply
1755 * @hw: Pointer to hardware structure
1756 * @results: pointer array containing parsed data
1757 * @mbx: Pointer to mailbox information structure
1758 *
1759 * This handler will capture the data for any error replies to previous
1760 * messages that the PF has sent.
1761 **/
1762s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,
1763 struct fm10k_mbx_info *mbx)
1764{
1765 struct fm10k_swapi_error err_msg;
1766 s32 err;
1767
1768 /* extract structure from message */
1769 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],
1770 &err_msg, sizeof(err_msg));
1771 if (err)
1772 return err;
1773
1774 /* record table status */
1775 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);
1776 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);
1777 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);
1778
1779 /* record SW API status value */
1780 hw->swapi.status = le32_to_cpu(err_msg.status);
1781
1782 return 0;
1783}
1784
5f226ddb
AD		 1785const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = {
1786 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP,
1787 sizeof(struct fm10k_swapi_1588_timestamp)),
1788 FM10K_TLV_ATTR_LAST
1789};
1790
1791/* currently there is no shared 1588 timestamp handler */
1792
1793/**
1794 * fm10k_adjust_systime_pf - Adjust systime frequency
1795 * @hw: pointer to hardware structure
1796 * @ppb: adjustment rate in parts per billion
1797 *
1798 * This function will adjust the SYSTIME_CFG register contained in BAR 4
1799 * if this function is supported for BAR 4 access. The adjustment amount
1800 * is based on the parts per billion value provided and adjusted to a
1801 * value based on parts per 2^48 clock cycles.
1802 *
1803 * If adjustment is not supported or the requested value is too large
1804 * we will return an error.
1805 **/
1806static s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb)
1807{
1808 u64 systime_adjust;
1809
1810 /* if sw_addr is not set we don't have switch register access */
1811 if (!hw->sw_addr)
1812 return ppb ? FM10K_ERR_PARAM : 0;
1813
1814 /* we must convert the value from parts per billion to parts per
1815 * 2^48 cycles. In addition I have opted to only use the 30 most
1816 * significant bits of the adjustment value as the 8 least
1817 * significant bits are located in another register and represent
1818 * a value significantly less than a part per billion, the result
1819 * of dropping the 8 least significant bits is that the adjustment
1820 * value is effectively multiplied by 2^8 when we write it.
1821 *
1822 * As a result of all this the math for this breaks down as follows:
1823 * ppb / 10^9 == adjust * 2^8 / 2^48
1824 * If we solve this for adjust, and simplify it comes out as:
1825 * ppb * 2^31 / 5^9 == adjust
1826 */
1827 systime_adjust = (ppb < 0) ? -ppb : ppb;
1828 systime_adjust <<= 31;
1829 do_div(systime_adjust, 1953125);
1830
1831 /* verify the requested adjustment value is in range */
1832 if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK)
1833 return FM10K_ERR_PARAM;
1834
646725a7
JK		 1835 if (ppb > 0)
1836 systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE;
5f226ddb
AD		 1837
1838 fm10k_write_sw_reg(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust);
1839
1840 return 0;
1841}
1842
1843/**
1844 * fm10k_read_systime_pf - Reads value of systime registers
1845 * @hw: pointer to the hardware structure
1846 *
1847 * Function reads the content of 2 registers, combined to represent a 64 bit
1848 * value measured in nanosecods. In order to guarantee the value is accurate
1849 * we check the 32 most significant bits both before and after reading the
1850 * 32 least significant bits to verify they didn't change as we were reading
1851 * the registers.
1852 **/
1853static u64 fm10k_read_systime_pf(struct fm10k_hw *hw)
1854{
1855 u32 systime_l, systime_h, systime_tmp;
1856
1857 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1858
1859 do {
1860 systime_tmp = systime_h;
1861 systime_l = fm10k_read_reg(hw, FM10K_SYSTIME);
1862 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1863 } while (systime_tmp != systime_h);
1864
1865 return ((u64)systime_h << 32) | systime_l;
1866}
1867
401b5383
AD		 1868static const struct fm10k_msg_data fm10k_msg_data_pf[] = {
1869 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1870 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1871 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),
1872 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1873 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1874 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),
1875 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1876};
1877
b6fec18f
AD		 1878static struct fm10k_mac_ops mac_ops_pf = {
1879 .get_bus_info = &fm10k_get_bus_info_generic,
1880 .reset_hw = &fm10k_reset_hw_pf,
1881 .init_hw = &fm10k_init_hw_pf,
1882 .start_hw = &fm10k_start_hw_generic,
1883 .stop_hw = &fm10k_stop_hw_generic,
401b5383 1884 .update_vlan = &fm10k_update_vlan_pf,
b6fec18f 1885 .read_mac_addr = &fm10k_read_mac_addr_pf,
401b5383
AD		 1886 .update_uc_addr = &fm10k_update_uc_addr_pf,
1887 .update_mc_addr = &fm10k_update_mc_addr_pf,
1888 .update_xcast_mode = &fm10k_update_xcast_mode_pf,
1889 .update_int_moderator = &fm10k_update_int_moderator_pf,
1890 .update_lport_state = &fm10k_update_lport_state_pf,
b6fec18f
AD		 1891 .update_hw_stats = &fm10k_update_hw_stats_pf,
1892 .rebind_hw_stats = &fm10k_rebind_hw_stats_pf,
401b5383
AD		 1893 .configure_dglort_map = &fm10k_configure_dglort_map_pf,
1894 .set_dma_mask = &fm10k_set_dma_mask_pf,
b6fec18f 1895 .get_fault = &fm10k_get_fault_pf,
401b5383 1896 .get_host_state = &fm10k_get_host_state_pf,
5f226ddb
AD		 1897 .adjust_systime = &fm10k_adjust_systime_pf,
1898 .read_systime = &fm10k_read_systime_pf,
b6fec18f
AD		 1899};
1900
c2653865
AD		 1901static struct fm10k_iov_ops iov_ops_pf = {
1902 .assign_resources = &fm10k_iov_assign_resources_pf,
1903 .configure_tc = &fm10k_iov_configure_tc_pf,
1904 .assign_int_moderator = &fm10k_iov_assign_int_moderator_pf,
1905 .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf,
1906 .reset_resources = &fm10k_iov_reset_resources_pf,
1907 .set_lport = &fm10k_iov_set_lport_pf,
1908 .reset_lport = &fm10k_iov_reset_lport_pf,
1909 .update_stats = &fm10k_iov_update_stats_pf,
5f226ddb 1910 .report_timestamp = &fm10k_iov_report_timestamp_pf,
c2653865
AD		 1911};
1912
401b5383
AD		 1913static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw)
1914{
1915 fm10k_get_invariants_generic(hw);
1916
1917 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);
1918}
1919
b6fec18f
AD		 1920struct fm10k_info fm10k_pf_info = {
1921 .mac = fm10k_mac_pf,
401b5383 1922 .get_invariants = &fm10k_get_invariants_pf,
b6fec18f 1923 .mac_ops = &mac_ops_pf,
c2653865 1924 .iov_ops = &iov_ops_pf,
b6fec18f 1925};
Linux 6.x block layer and io_uring tree(s)