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fm10k: Add support for debugfs
[linux-2.6-block.git] / drivers / net / ethernet / intel / fm10k / fm10k_pf.c
CommitLineData
b6fec18f
AD		 1/* Intel Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
19 */
20
21#include "fm10k_pf.h"
c2653865 22#include "fm10k_vf.h"
b6fec18f
AD		 23
24/**
25 * fm10k_reset_hw_pf - PF hardware reset
26 * @hw: pointer to hardware structure
27 *
28 * This function should return the hardware to a state similar to the
29 * one it is in after being powered on.
30 **/
31static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
32{
33 s32 err;
34 u32 reg;
35 u16 i;
36
37 /* Disable interrupts */
38 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
39
40 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */
41 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
42 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
43
44 /* We assume here Tx and Rx queue 0 are owned by the PF */
45
46 /* Shut off VF access to their queues forcing them to queue 0 */
47 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {
48 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
49 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
50 }
51
52 /* shut down all rings */
53 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
54 if (err)
55 return err;
56
57 /* Verify that DMA is no longer active */
58 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL);
59 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))
60 return FM10K_ERR_DMA_PENDING;
61
62 /* Inititate data path reset */
63 reg |= FM10K_DMA_CTRL_DATAPATH_RESET;
64 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg);
65
66 /* Flush write and allow 100us for reset to complete */
67 fm10k_write_flush(hw);
68 udelay(FM10K_RESET_TIMEOUT);
69
70 /* Verify we made it out of reset */
71 reg = fm10k_read_reg(hw, FM10K_IP);
72 if (!(reg & FM10K_IP_NOTINRESET))
73 err = FM10K_ERR_RESET_FAILED;
74
75 return err;
76}
77
c2653865
AD		 78/**
79 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
80 * @hw: pointer to hardware structure
81 *
82 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
83 **/
84static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)
85{
86 u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL);
87
88 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);
89}
90
b6fec18f
AD		 91/**
92 * fm10k_init_hw_pf - PF hardware initialization
93 * @hw: pointer to hardware structure
94 *
95 **/
96static s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
97{
98 u32 dma_ctrl, txqctl;
99 u16 i;
100
101 /* Establish default VSI as valid */
102 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
103 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
104 FM10K_DGLORTMAP_ANY);
105
106 /* Invalidate all other GLORT entries */
107 for (i = 1; i < FM10K_DGLORT_COUNT; i++)
108 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
109
110 /* reset ITR2(0) to point to itself */
111 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
112
113 /* reset VF ITR2(0) to point to 0 avoid PF registers */
114 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
115
116 /* loop through all PF ITR2 registers pointing them to the previous */
117 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)
118 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
119
120 /* Enable interrupt moderator if not already enabled */
121 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
122
123 /* compute the default txqctl configuration */
124 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |
125 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);
126
127 for (i = 0; i < FM10K_MAX_QUEUES; i++) {
128 /* configure rings for 256 Queue / 32 Descriptor cache mode */
129 fm10k_write_reg(hw, FM10K_TQDLOC(i),
130 (i * FM10K_TQDLOC_BASE_32_DESC) |
131 FM10K_TQDLOC_SIZE_32_DESC);
132 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
133
134 /* configure rings to provide TPH processing hints */
135 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i),
136 FM10K_TPH_TXCTRL_DESC_TPHEN |
137 FM10K_TPH_TXCTRL_DESC_RROEN |
138 FM10K_TPH_TXCTRL_DESC_WROEN |
139 FM10K_TPH_TXCTRL_DATA_RROEN);
140 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i),
141 FM10K_TPH_RXCTRL_DESC_TPHEN |
142 FM10K_TPH_RXCTRL_DESC_RROEN |
143 FM10K_TPH_RXCTRL_DATA_WROEN |
144 FM10K_TPH_RXCTRL_HDR_WROEN);
145 }
146
147 /* set max hold interval to align with 1.024 usec in all modes */
148 switch (hw->bus.speed) {
149 case fm10k_bus_speed_2500:
150 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
151 break;
152 case fm10k_bus_speed_5000:
153 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
154 break;
155 case fm10k_bus_speed_8000:
156 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
157 break;
158 default:
159 dma_ctrl = 0;
160 break;
161 }
162
163 /* Configure TSO flags */
164 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
165 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
166
167 /* Enable DMA engine
168 * Set Rx Descriptor size to 32
169 * Set Minimum MSS to 64
170 * Set Maximum number of Rx queues to 256 / 32 Descriptor
171 */
172 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
173 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |
174 FM10K_DMA_CTRL_32_DESC;
175
176 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl);
177
178 /* record maximum queue count, we limit ourselves to 128 */
179 hw->mac.max_queues = FM10K_MAX_QUEUES_PF;
180
c2653865
AD		 181 /* We support either 64 VFs or 7 VFs depending on if we have ARI */
182 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;
183
b6fec18f
AD		 184 return 0;
185}
186
187/**
188 * fm10k_is_slot_appropriate_pf - Indicate appropriate slot for this SKU
189 * @hw: pointer to hardware structure
190 *
191 * Looks at the PCIe bus info to confirm whether or not this slot can support
192 * the necessary bandwidth for this device.
193 **/
194static bool fm10k_is_slot_appropriate_pf(struct fm10k_hw *hw)
195{
196 return (hw->bus.speed == hw->bus_caps.speed) &&
197 (hw->bus.width == hw->bus_caps.width);
198}
199
401b5383
AD		 200/**
201 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
202 * @hw: pointer to hardware structure
203 * @vid: VLAN ID to add to table
204 * @vsi: Index indicating VF ID or PF ID in table
205 * @set: Indicates if this is a set or clear operation
206 *
207 * This function adds or removes the corresponding VLAN ID from the VLAN
208 * filter table for the corresponding function. In addition to the
209 * standard set/clear that supports one bit a multi-bit write is
210 * supported to set 64 bits at a time.
211 **/
212static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
213{
214 u32 vlan_table, reg, mask, bit, len;
215
216 /* verify the VSI index is valid */
217 if (vsi > FM10K_VLAN_TABLE_VSI_MAX)
218 return FM10K_ERR_PARAM;
219
220 /* VLAN multi-bit write:
221 * The multi-bit write has several parts to it.
222 * 3 2 1 0
223 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
225 * | RSVD0 | Length |C|RSVD0| VLAN ID |
226 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
227 *
228 * VLAN ID: Vlan Starting value
229 * RSVD0: Reserved section, must be 0
230 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
231 * Length: Number of times to repeat the bit being set
232 */
233 len = vid >> 16;
234 vid = (vid << 17) >> 17;
235
236 /* verify the reserved 0 fields are 0 */
237 if (len >= FM10K_VLAN_TABLE_VID_MAX ||
238 vid >= FM10K_VLAN_TABLE_VID_MAX)
239 return FM10K_ERR_PARAM;
240
241 /* Loop through the table updating all required VLANs */
242 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;
243 len < FM10K_VLAN_TABLE_VID_MAX;
244 len -= 32 - bit, reg++, bit = 0) {
245 /* record the initial state of the register */
246 vlan_table = fm10k_read_reg(hw, reg);
247
248 /* truncate mask if we are at the start or end of the run */
249 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;
250
251 /* make necessary modifications to the register */
252 mask &= set ? ~vlan_table : vlan_table;
253 if (mask)
254 fm10k_write_reg(hw, reg, vlan_table ^ mask);
255 }
256
257 return 0;
258}
259
b6fec18f
AD		 260/**
261 * fm10k_read_mac_addr_pf - Read device MAC address
262 * @hw: pointer to the HW structure
263 *
264 * Reads the device MAC address from the SM_AREA and stores the value.
265 **/
266static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)
267{
268 u8 perm_addr[ETH_ALEN];
269 u32 serial_num;
270 int i;
271
272 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1));
273
274 /* last byte should be all 1's */
275 if ((~serial_num) << 24)
276 return FM10K_ERR_INVALID_MAC_ADDR;
277
278 perm_addr[0] = (u8)(serial_num >> 24);
279 perm_addr[1] = (u8)(serial_num >> 16);
280 perm_addr[2] = (u8)(serial_num >> 8);
281
282 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0));
283
284 /* first byte should be all 1's */
285 if ((~serial_num) >> 24)
286 return FM10K_ERR_INVALID_MAC_ADDR;
287
288 perm_addr[3] = (u8)(serial_num >> 16);
289 perm_addr[4] = (u8)(serial_num >> 8);
290 perm_addr[5] = (u8)(serial_num);
291
292 for (i = 0; i < ETH_ALEN; i++) {
293 hw->mac.perm_addr[i] = perm_addr[i];
294 hw->mac.addr[i] = perm_addr[i];
295 }
296
297 return 0;
298}
299
401b5383
AD		 300/**
301 * fm10k_glort_valid_pf - Validate that the provided glort is valid
302 * @hw: pointer to the HW structure
303 * @glort: base glort to be validated
304 *
305 * This function will return an error if the provided glort is invalid
306 **/
307bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)
308{
309 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;
310
311 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);
312}
313
314/**
315 * fm10k_update_uc_addr_pf - Update device unicast addresss
316 * @hw: pointer to the HW structure
317 * @glort: base resource tag for this request
318 * @mac: MAC address to add/remove from table
319 * @vid: VLAN ID to add/remove from table
320 * @add: Indicates if this is an add or remove operation
321 * @flags: flags field to indicate add and secure
322 *
323 * This function generates a message to the Switch API requesting
324 * that the given logical port add/remove the given L2 MAC/VLAN address.
325 **/
326static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
327 const u8 *mac, u16 vid, bool add, u8 flags)
328{
329 struct fm10k_mbx_info *mbx = &hw->mbx;
330 struct fm10k_mac_update mac_update;
331 u32 msg[5];
332
333 /* if glort is not valid return error */
334 if (!fm10k_glort_valid_pf(hw, glort))
335 return FM10K_ERR_PARAM;
336
337 /* drop upper 4 bits of VLAN ID */
338 vid = (vid << 4) >> 4;
339
340 /* record fields */
341 mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) |
342 ((u32)mac[3] << 16) |
343 ((u32)mac[4] << 8) |
344 ((u32)mac[5]));
345 mac_update.mac_upper = cpu_to_le16(((u32)mac[0] << 8) |
346 ((u32)mac[1]));
347 mac_update.vlan = cpu_to_le16(vid);
348 mac_update.glort = cpu_to_le16(glort);
349 mac_update.action = add ? 0 : 1;
350 mac_update.flags = flags;
351
352 /* populate mac_update fields */
353 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);
354 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,
355 &mac_update, sizeof(mac_update));
356
357 /* load onto outgoing mailbox */
358 return mbx->ops.enqueue_tx(hw, mbx, msg);
359}
360
361/**
362 * fm10k_update_uc_addr_pf - Update device unicast addresss
363 * @hw: pointer to the HW structure
364 * @glort: base resource tag for this request
365 * @mac: MAC address to add/remove from table
366 * @vid: VLAN ID to add/remove from table
367 * @add: Indicates if this is an add or remove operation
368 * @flags: flags field to indicate add and secure
369 *
370 * This function is used to add or remove unicast addresses for
371 * the PF.
372 **/
373static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,
374 const u8 *mac, u16 vid, bool add, u8 flags)
375{
376 /* verify MAC address is valid */
377 if (!is_valid_ether_addr(mac))
378 return FM10K_ERR_PARAM;
379
380 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);
381}
382
383/**
384 * fm10k_update_mc_addr_pf - Update device multicast addresses
385 * @hw: pointer to the HW structure
386 * @glort: base resource tag for this request
387 * @mac: MAC address to add/remove from table
388 * @vid: VLAN ID to add/remove from table
389 * @add: Indicates if this is an add or remove operation
390 *
391 * This function is used to add or remove multicast MAC addresses for
392 * the PF.
393 **/
394static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,
395 const u8 *mac, u16 vid, bool add)
396{
397 /* verify multicast address is valid */
398 if (!is_multicast_ether_addr(mac))
399 return FM10K_ERR_PARAM;
400
401 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);
402}
403
404/**
405 * fm10k_update_xcast_mode_pf - Request update of multicast mode
406 * @hw: pointer to hardware structure
407 * @glort: base resource tag for this request
408 * @mode: integer value indicating mode being requested
409 *
410 * This function will attempt to request a higher mode for the port
411 * so that it can enable either multicast, multicast promiscuous, or
412 * promiscuous mode of operation.
413 **/
414static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)
415{
416 struct fm10k_mbx_info *mbx = &hw->mbx;
417 u32 msg[3], xcast_mode;
418
419 if (mode > FM10K_XCAST_MODE_NONE)
420 return FM10K_ERR_PARAM;
421 /* if glort is not valid return error */
422 if (!fm10k_glort_valid_pf(hw, glort))
423 return FM10K_ERR_PARAM;
424
425 /* write xcast mode as a single u32 value,
426 * lower 16 bits: glort
427 * upper 16 bits: mode
428 */
429 xcast_mode = ((u32)mode << 16) | glort;
430
431 /* generate message requesting to change xcast mode */
432 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);
433 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);
434
435 /* load onto outgoing mailbox */
436 return mbx->ops.enqueue_tx(hw, mbx, msg);
437}
438
439/**
440 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list
441 * @hw: pointer to hardware structure
442 *
443 * This function walks through the MSI-X vector table to determine the
444 * number of active interrupts and based on that information updates the
445 * interrupt moderator linked list.
446 **/
447static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)
448{
449 u32 i;
450
451 /* Disable interrupt moderator */
452 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
453
454 /* loop through PF from last to first looking enabled vectors */
455 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {
456 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
457 break;
458 }
459
460 /* always reset VFITR2[0] to point to last enabled PF vector*/
461 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
462
463 /* reset ITR2[0] to point to last enabled PF vector */
c2653865
AD		 464 if (!hw->iov.num_vfs)
465 fm10k_write_reg(hw, FM10K_ITR2(0), i);
401b5383
AD		 466
467 /* Enable interrupt moderator */
468 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
469}
470
471/**
472 * fm10k_update_lport_state_pf - Notify the switch of a change in port state
473 * @hw: pointer to the HW structure
474 * @glort: base resource tag for this request
475 * @count: number of logical ports being updated
476 * @enable: boolean value indicating enable or disable
477 *
478 * This function is used to add/remove a logical port from the switch.
479 **/
480static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,
481 u16 count, bool enable)
482{
483 struct fm10k_mbx_info *mbx = &hw->mbx;
484 u32 msg[3], lport_msg;
485
486 /* do nothing if we are being asked to create or destroy 0 ports */
487 if (!count)
488 return 0;
489
490 /* if glort is not valid return error */
491 if (!fm10k_glort_valid_pf(hw, glort))
492 return FM10K_ERR_PARAM;
493
494 /* construct the lport message from the 2 pieces of data we have */
495 lport_msg = ((u32)count << 16) | glort;
496
497 /* generate lport create/delete message */
498 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :
499 FM10K_PF_MSG_ID_LPORT_DELETE);
500 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);
501
502 /* load onto outgoing mailbox */
503 return mbx->ops.enqueue_tx(hw, mbx, msg);
504}
505
506/**
507 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
508 * @hw: pointer to hardware structure
509 * @dglort: pointer to dglort configuration structure
510 *
511 * Reads the configuration structure contained in dglort_cfg and uses
512 * that information to then populate a DGLORTMAP/DEC entry and the queues
513 * to which it has been assigned.
514 **/
515static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,
516 struct fm10k_dglort_cfg *dglort)
517{
518 u16 glort, queue_count, vsi_count, pc_count;
519 u16 vsi, queue, pc, q_idx;
520 u32 txqctl, dglortdec, dglortmap;
521
522 /* verify the dglort pointer */
523 if (!dglort)
524 return FM10K_ERR_PARAM;
525
526 /* verify the dglort values */
527 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||
528 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||
529 (dglort->queue_l > 8) || (dglort->queue_b >= 256))
530 return FM10K_ERR_PARAM;
531
532 /* determine count of VSIs and queues */
533 queue_count = 1 << (dglort->rss_l + dglort->pc_l);
534 vsi_count = 1 << (dglort->vsi_l + dglort->queue_l);
535 glort = dglort->glort;
536 q_idx = dglort->queue_b;
537
538 /* configure SGLORT for queues */
539 for (vsi = 0; vsi < vsi_count; vsi++, glort++) {
540 for (queue = 0; queue < queue_count; queue++, q_idx++) {
541 if (q_idx >= FM10K_MAX_QUEUES)
542 break;
543
544 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort);
545 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort);
546 }
547 }
548
549 /* determine count of PCs and queues */
550 queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l);
551 pc_count = 1 << dglort->pc_l;
552
553 /* configure PC for Tx queues */
554 for (pc = 0; pc < pc_count; pc++) {
555 q_idx = pc + dglort->queue_b;
556 for (queue = 0; queue < queue_count; queue++) {
557 if (q_idx >= FM10K_MAX_QUEUES)
558 break;
559
560 txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx));
561 txqctl &= ~FM10K_TXQCTL_PC_MASK;
562 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT;
563 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl);
564
565 q_idx += pc_count;
566 }
567 }
568
569 /* configure DGLORTDEC */
570 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |
571 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |
572 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |
573 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |
574 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |
575 ((u32)(dglort->queue_l));
576 if (dglort->inner_rss)
577 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE;
578
579 /* configure DGLORTMAP */
580 dglortmap = (dglort->idx == fm10k_dglort_default) ?
581 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;
582 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;
583 dglortmap |= dglort->glort;
584
585 /* write values to hardware */
586 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
587 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
588
589 return 0;
590}
591
c2653865
AD		 592u16 fm10k_queues_per_pool(struct fm10k_hw *hw)
593{
594 u16 num_pools = hw->iov.num_pools;
595
596 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?
597 8 : FM10K_MAX_QUEUES_POOL;
598}
599
600u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)
601{
602 u16 num_vfs = hw->iov.num_vfs;
603 u16 vf_q_idx = FM10K_MAX_QUEUES;
604
605 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);
606
607 return vf_q_idx;
608}
609
610static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)
611{
612 u16 num_pools = hw->iov.num_pools;
613
614 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :
615 FM10K_MAX_VECTORS_POOL;
616}
617
618static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)
619{
620 u16 vf_v_idx = FM10K_MAX_VECTORS_PF;
621
622 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;
623
624 return vf_v_idx;
625}
626
627/**
628 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
629 * @hw: pointer to the HW structure
630 * @num_vfs: number of VFs to be allocated
631 * @num_pools: number of virtualization pools to be allocated
632 *
633 * Allocates queues and traffic classes to virtualization entities to prepare
634 * the PF for SR-IOV and VMDq
635 **/
636static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
637 u16 num_pools)
638{
639 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;
640 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;
641 int i, j;
642
643 /* hardware only supports up to 64 pools */
644 if (num_pools > 64)
645 return FM10K_ERR_PARAM;
646
647 /* the number of VFs cannot exceed the number of pools */
648 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))
649 return FM10K_ERR_PARAM;
650
651 /* record number of virtualization entities */
652 hw->iov.num_vfs = num_vfs;
653 hw->iov.num_pools = num_pools;
654
655 /* determine qmap offsets and counts */
656 qmap_stride = (num_vfs > 8) ? 32 : 256;
657 qpp = fm10k_queues_per_pool(hw);
658 vpp = fm10k_vectors_per_pool(hw);
659
660 /* calculate starting index for queues */
661 vf_q_idx = fm10k_vf_queue_index(hw, 0);
662 qmap_idx = 0;
663
664 /* establish TCs with -1 credits and no quanta to prevent transmit */
665 for (i = 0; i < num_vfs; i++) {
666 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0);
667 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0);
668 fm10k_write_reg(hw, FM10K_TC_CREDIT(i),
669 FM10K_TC_CREDIT_CREDIT_MASK);
670 }
671
672 /* zero out all mbmem registers */
673 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)
674 fm10k_write_reg(hw, FM10K_MBMEM(i), 0);
675
676 /* clear event notification of VF FLR */
677 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0);
678 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0);
679
680 /* loop through unallocated rings assigning them back to PF */
681 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
682 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
683 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | vid);
684 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
685 }
686
687 /* PF should have already updated VFITR2[0] */
688
689 /* update all ITR registers to flow to VFITR2[0] */
690 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {
691 if (!(i & (vpp - 1)))
692 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp);
693 else
694 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
695 }
696
697 /* update PF ITR2[0] to reference the last vector */
698 fm10k_write_reg(hw, FM10K_ITR2(0),
699 fm10k_vf_vector_index(hw, num_vfs - 1));
700
701 /* loop through rings populating rings and TCs */
702 for (i = 0; i < num_vfs; i++) {
703 /* record index for VF queue 0 for use in end of loop */
704 vf_q_idx0 = vf_q_idx;
705
706 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {
707 /* assign VF and locked TC to queues */
708 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
709 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx),
710 (i << FM10K_TXQCTL_TC_SHIFT) | i |
711 FM10K_TXQCTL_VF | vid);
712 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx),
713 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
714 FM10K_RXDCTL_DROP_ON_EMPTY);
715 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx),
716 FM10K_RXQCTL_VF |
717 (i << FM10K_RXQCTL_VF_SHIFT));
718
719 /* map queue pair to VF */
720 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
721 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
722 }
723
724 /* repeat the first ring for all of the remaining VF rings */
725 for (; j < qmap_stride; j++, qmap_idx++) {
726 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
727 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
728 }
729 }
730
731 /* loop through remaining indexes assigning all to queue 0 */
732 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {
733 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
734 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0);
735 qmap_idx++;
736 }
737
738 return 0;
739}
740
741/**
742 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF
743 * @hw: pointer to the HW structure
744 * @vf_idx: index of VF receiving GLORT
745 * @rate: Rate indicated in Mb/s
746 *
747 * Configured the TC for a given VF to allow only up to a given number
748 * of Mb/s of outgoing Tx throughput.
749 **/
750static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)
751{
752 /* configure defaults */
753 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;
754 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;
755
756 /* verify vf is in range */
757 if (vf_idx >= hw->iov.num_vfs)
758 return FM10K_ERR_PARAM;
759
760 /* set interval to align with 4.096 usec in all modes */
761 switch (hw->bus.speed) {
762 case fm10k_bus_speed_2500:
763 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1;
764 break;
765 case fm10k_bus_speed_5000:
766 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2;
767 break;
768 default:
769 break;
770 }
771
772 if (rate) {
773 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)
774 return FM10K_ERR_PARAM;
775
776 /* The quanta is measured in Bytes per 4.096 or 8.192 usec
777 * The rate is provided in Mbits per second
778 * To tralslate from rate to quanta we need to multiply the
779 * rate by 8.192 usec and divide by 8 bits/byte. To avoid
780 * dealing with floating point we can round the values up
781 * to the nearest whole number ratio which gives us 128 / 125.
782 */
783 tc_rate = (rate * 128) / 125;
784
785 /* try to keep the rate limiting accurate by increasing
786 * the number of credits and interval for rates less than 4Gb/s
787 */
788 if (rate < 4000)
789 interval <<= 1;
790 else
791 tc_rate >>= 1;
792 }
793
794 /* update rate limiter with new values */
795 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
796 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
797 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
798
799 return 0;
800}
801
802/**
803 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
804 * @hw: pointer to the HW structure
805 * @vf_idx: index of VF receiving GLORT
806 *
807 * Update the interrupt moderator linked list to include any MSI-X
808 * interrupts which the VF has enabled in the MSI-X vector table.
809 **/
810static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)
811{
812 u16 vf_v_idx, vf_v_limit, i;
813
814 /* verify vf is in range */
815 if (vf_idx >= hw->iov.num_vfs)
816 return FM10K_ERR_PARAM;
817
818 /* determine vector offset and count*/
819 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
820 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
821
822 /* search for first vector that is not masked */
823 for (i = vf_v_limit - 1; i > vf_v_idx; i--) {
824 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
825 break;
826 }
827
828 /* reset linked list so it now includes our active vectors */
829 if (vf_idx == (hw->iov.num_vfs - 1))
830 fm10k_write_reg(hw, FM10K_ITR2(0), i);
831 else
832 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i);
833
834 return 0;
835}
836
837/**
838 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
839 * @hw: pointer to the HW structure
840 * @vf_info: pointer to VF information structure
841 *
842 * Assign a MAC address and default VLAN to a VF and notify it of the update
843 **/
844static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
845 struct fm10k_vf_info *vf_info)
846{
847 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;
848 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;
849 s32 err = 0;
850 u16 vf_idx, vf_vid;
851
852 /* verify vf is in range */
853 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)
854 return FM10K_ERR_PARAM;
855
856 /* determine qmap offsets and counts */
857 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
858 queues_per_pool = fm10k_queues_per_pool(hw);
859
860 /* calculate starting index for queues */
861 vf_idx = vf_info->vf_idx;
862 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
863 qmap_idx = qmap_stride * vf_idx;
864
865 /* MAP Tx queue back to 0 temporarily, and disable it */
866 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
867 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
868
869 /* determine correct default VLAN ID */
870 if (vf_info->pf_vid)
871 vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR;
872 else
873 vf_vid = vf_info->sw_vid;
874
875 /* generate MAC_ADDR request */
876 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
877 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,
878 vf_info->mac, vf_vid);
879
880 /* load onto outgoing mailbox, ignore any errors on enqueue */
881 if (vf_info->mbx.ops.enqueue_tx)
882 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
883
884 /* verify ring has disabled before modifying base address registers */
885 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
886 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {
887 /* limit ourselves to a 1ms timeout */
888 if (timeout == 10) {
889 err = FM10K_ERR_DMA_PENDING;
890 goto err_out;
891 }
892
893 usleep_range(100, 200);
894 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
895 }
896
897 /* Update base address registers to contain MAC address */
898 if (is_valid_ether_addr(vf_info->mac)) {
899 tdbal = (((u32)vf_info->mac[3]) << 24) |
900 (((u32)vf_info->mac[4]) << 16) |
901 (((u32)vf_info->mac[5]) << 8);
902
903 tdbah = (((u32)0xFF) << 24) |
904 (((u32)vf_info->mac[0]) << 16) |
905 (((u32)vf_info->mac[1]) << 8) |
906 ((u32)vf_info->mac[2]);
907 }
908
909 /* Record the base address into queue 0 */
910 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal);
911 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah);
912
913err_out:
914 /* configure Queue control register */
915 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
916 FM10K_TXQCTL_VID_MASK;
917 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
918 FM10K_TXQCTL_VF | vf_idx;
919
920 /* assign VID */
921 for (i = 0; i < queues_per_pool; i++)
922 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
923
924 /* restore the queue back to VF ownership */
925 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
926 return err;
927}
928
929/**
930 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
931 * @hw: pointer to the HW structure
932 * @vf_info: pointer to VF information structure
933 *
934 * Reassign the interrupts and queues to a VF following an FLR
935 **/
936static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
937 struct fm10k_vf_info *vf_info)
938{
939 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;
940 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl;
941 u16 vf_v_idx, vf_v_limit, vf_vid;
942 u8 vf_idx = vf_info->vf_idx;
943 int i;
944
945 /* verify vf is in range */
946 if (vf_idx >= hw->iov.num_vfs)
947 return FM10K_ERR_PARAM;
948
949 /* clear event notification of VF FLR */
950 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32));
951
952 /* force timeout and then disconnect the mailbox */
953 vf_info->mbx.timeout = 0;
954 if (vf_info->mbx.ops.disconnect)
955 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx);
956
957 /* determine vector offset and count*/
958 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
959 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
960
961 /* determine qmap offsets and counts */
962 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
963 queues_per_pool = fm10k_queues_per_pool(hw);
964 qmap_idx = qmap_stride * vf_idx;
965
966 /* make all the queues inaccessible to the VF */
967 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {
968 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
969 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
970 }
971
972 /* calculate starting index for queues */
973 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
974
975 /* determine correct default VLAN ID */
976 if (vf_info->pf_vid)
977 vf_vid = vf_info->pf_vid;
978 else
979 vf_vid = vf_info->sw_vid;
980
981 /* configure Queue control register */
982 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |
983 (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
984 FM10K_TXQCTL_VF | vf_idx;
985 rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT);
986
987 /* stop further DMA and reset queue ownership back to VF */
988 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {
989 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
990 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
991 fm10k_write_reg(hw, FM10K_RXDCTL(i),
992 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
993 FM10K_RXDCTL_DROP_ON_EMPTY);
994 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl);
995 }
996
997 /* reset TC with -1 credits and no quanta to prevent transmit */
998 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
999 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0);
1000 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx),
1001 FM10K_TC_CREDIT_CREDIT_MASK);
1002
1003 /* update our first entry in the table based on previous VF */
1004 if (!vf_idx)
1005 hw->mac.ops.update_int_moderator(hw);
1006 else
1007 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1);
1008
1009 /* reset linked list so it now includes our active vectors */
1010 if (vf_idx == (hw->iov.num_vfs - 1))
1011 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx);
1012 else
1013 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
1014
1015 /* link remaining vectors so that next points to previous */
1016 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)
1017 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
1018
1019 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1020 for (i = FM10K_VFMBMEM_LEN; i--;)
1021 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
1022 for (i = FM10K_VLAN_TABLE_SIZE; i--;)
1023 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
1024 for (i = FM10K_RETA_SIZE; i--;)
1025 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0);
1026 for (i = FM10K_RSSRK_SIZE; i--;)
1027 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
1028 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0);
1029
1030 /* Update base address registers to contain MAC address */
1031 if (is_valid_ether_addr(vf_info->mac)) {
1032 tdbal = (((u32)vf_info->mac[3]) << 24) |
1033 (((u32)vf_info->mac[4]) << 16) |
1034 (((u32)vf_info->mac[5]) << 8);
1035 tdbah = (((u32)0xFF) << 24) |
1036 (((u32)vf_info->mac[0]) << 16) |
1037 (((u32)vf_info->mac[1]) << 8) |
1038 ((u32)vf_info->mac[2]);
1039 }
1040
1041 /* map queue pairs back to VF from last to first*/
1042 for (i = queues_per_pool; i--;) {
1043 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
1044 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
1045 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
1046 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
1047 }
1048
1049 return 0;
1050}
1051
1052/**
1053 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1054 * @hw: pointer to hardware structure
1055 * @vf_info: pointer to VF information structure
1056 * @lport_idx: Logical port offset from the hardware glort
1057 * @flags: Set of capability flags to extend port beyond basic functionality
1058 *
1059 * This function allows enabling a VF port by assigning it a GLORT and
1060 * setting the flags so that it can enable an Rx mode.
1061 **/
1062static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,
1063 struct fm10k_vf_info *vf_info,
1064 u16 lport_idx, u8 flags)
1065{
1066 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;
1067
1068 /* if glort is not valid return error */
1069 if (!fm10k_glort_valid_pf(hw, glort))
1070 return FM10K_ERR_PARAM;
1071
1072 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;
1073 vf_info->glort = glort;
1074
1075 return 0;
1076}
1077
1078/**
1079 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1080 * @hw: pointer to hardware structure
1081 * @vf_info: pointer to VF information structure
1082 *
1083 * This function disables a VF port by stripping it of a GLORT and
1084 * setting the flags so that it cannot enable any Rx mode.
1085 **/
1086static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,
1087 struct fm10k_vf_info *vf_info)
1088{
1089 u32 msg[1];
1090
1091 /* need to disable the port if it is already enabled */
1092 if (FM10K_VF_FLAG_ENABLED(vf_info)) {
1093 /* notify switch that this port has been disabled */
1094 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);
1095
1096 /* generate port state response to notify VF it is not ready */
1097 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1098 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1099 }
1100
1101 /* clear flags and glort if it exists */
1102 vf_info->vf_flags = 0;
1103 vf_info->glort = 0;
1104}
1105
1106/**
1107 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1108 * @hw: pointer to hardware structure
1109 * @q: stats for all queues of a VF
1110 * @vf_idx: index of VF
1111 *
1112 * This function collects queue stats for VFs.
1113 **/
1114static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,
1115 struct fm10k_hw_stats_q *q,
1116 u16 vf_idx)
1117{
1118 u32 idx, qpp;
1119
1120 /* get stats for all of the queues */
1121 qpp = fm10k_queues_per_pool(hw);
1122 idx = fm10k_vf_queue_index(hw, vf_idx);
1123 fm10k_update_hw_stats_q(hw, q, idx, qpp);
1124}
1125
1126/**
1127 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1128 * @hw: Pointer to hardware structure
1129 * @results: Pointer array to message, results[0] is pointer to message
1130 * @mbx: Pointer to mailbox information structure
1131 *
1132 * This function is a default handler for MSI-X requests from the VF. The
1133 * assumption is that in this case it is acceptable to just directly
1134 * hand off the message form the VF to the underlying shared code.
1135 **/
1136s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results,
1137 struct fm10k_mbx_info *mbx)
1138{
1139 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1140 u8 vf_idx = vf_info->vf_idx;
1141
1142 return hw->iov.ops.assign_int_moderator(hw, vf_idx);
1143}
1144
1145/**
1146 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1147 * @hw: Pointer to hardware structure
1148 * @results: Pointer array to message, results[0] is pointer to message
1149 * @mbx: Pointer to mailbox information structure
1150 *
1151 * This function is a default handler for MAC/VLAN requests from the VF.
1152 * The assumption is that in this case it is acceptable to just directly
1153 * hand off the message form the VF to the underlying shared code.
1154 **/
1155s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
1156 struct fm10k_mbx_info *mbx)
1157{
1158 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1159 int err = 0;
1160 u8 mac[ETH_ALEN];
1161 u32 *result;
1162 u16 vlan;
1163 u32 vid;
1164
1165 /* we shouldn't be updating rules on a disabled interface */
1166 if (!FM10K_VF_FLAG_ENABLED(vf_info))
1167 err = FM10K_ERR_PARAM;
1168
1169 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {
1170 result = results[FM10K_MAC_VLAN_MSG_VLAN];
1171
1172 /* record VLAN id requested */
1173 err = fm10k_tlv_attr_get_u32(result, &vid);
1174 if (err)
1175 return err;
1176
1177 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1178 if (!vid || (vid == FM10K_VLAN_CLEAR)) {
1179 if (vf_info->pf_vid)
1180 vid |= vf_info->pf_vid;
1181 else
1182 vid |= vf_info->sw_vid;
1183 } else if (vid != vf_info->pf_vid) {
1184 return FM10K_ERR_PARAM;
1185 }
1186
1187 /* update VSI info for VF in regards to VLAN table */
1188 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi,
1189 !(vid & FM10K_VLAN_CLEAR));
1190 }
1191
1192 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {
1193 result = results[FM10K_MAC_VLAN_MSG_MAC];
1194
1195 /* record unicast MAC address requested */
1196 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1197 if (err)
1198 return err;
1199
1200 /* block attempts to set MAC for a locked device */
1201 if (is_valid_ether_addr(vf_info->mac) &&
1202 memcmp(mac, vf_info->mac, ETH_ALEN))
1203 return FM10K_ERR_PARAM;
1204
1205 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1206 if (!vlan || (vlan == FM10K_VLAN_CLEAR)) {
1207 if (vf_info->pf_vid)
1208 vlan |= vf_info->pf_vid;
1209 else
1210 vlan |= vf_info->sw_vid;
1211 } else if (vf_info->pf_vid) {
1212 return FM10K_ERR_PARAM;
1213 }
1214
1215 /* notify switch of request for new unicast address */
1216 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, mac, vlan,
1217 !(vlan & FM10K_VLAN_CLEAR), 0);
1218 }
1219
1220 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {
1221 result = results[FM10K_MAC_VLAN_MSG_MULTICAST];
1222
1223 /* record multicast MAC address requested */
1224 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1225 if (err)
1226 return err;
1227
1228 /* verify that the VF is allowed to request multicast */
1229 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))
1230 return FM10K_ERR_PARAM;
1231
1232 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1233 if (!vlan || (vlan == FM10K_VLAN_CLEAR)) {
1234 if (vf_info->pf_vid)
1235 vlan |= vf_info->pf_vid;
1236 else
1237 vlan |= vf_info->sw_vid;
1238 } else if (vf_info->pf_vid) {
1239 return FM10K_ERR_PARAM;
1240 }
1241
1242 /* notify switch of request for new multicast address */
1243 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, mac,
1244 !(vlan & FM10K_VLAN_CLEAR), 0);
1245 }
1246
1247 return err;
1248}
1249
1250/**
1251 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1252 * @vf_info: VF info structure containing capability flags
1253 * @mode: Requested xcast mode
1254 *
1255 * This function outputs the mode that most closely matches the requested
1256 * mode. If not modes match it will request we disable the port
1257 **/
1258static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,
1259 u8 mode)
1260{
1261 u8 vf_flags = vf_info->vf_flags;
1262
1263 /* match up mode to capabilities as best as possible */
1264 switch (mode) {
1265 case FM10K_XCAST_MODE_PROMISC:
1266 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)
1267 return FM10K_XCAST_MODE_PROMISC;
1268 /* fallthough */
1269 case FM10K_XCAST_MODE_ALLMULTI:
1270 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)
1271 return FM10K_XCAST_MODE_ALLMULTI;
1272 /* fallthough */
1273 case FM10K_XCAST_MODE_MULTI:
1274 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)
1275 return FM10K_XCAST_MODE_MULTI;
1276 /* fallthough */
1277 case FM10K_XCAST_MODE_NONE:
1278 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)
1279 return FM10K_XCAST_MODE_NONE;
1280 /* fallthough */
1281 default:
1282 break;
1283 }
1284
1285 /* disable interface as it should not be able to request any */
1286 return FM10K_XCAST_MODE_DISABLE;
1287}
1288
1289/**
1290 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1291 * @hw: Pointer to hardware structure
1292 * @results: Pointer array to message, results[0] is pointer to message
1293 * @mbx: Pointer to mailbox information structure
1294 *
1295 * This function is a default handler for port state requests. The port
1296 * state requests for now are basic and consist of enabling or disabling
1297 * the port.
1298 **/
1299s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,
1300 struct fm10k_mbx_info *mbx)
1301{
1302 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1303 u32 *result;
1304 s32 err = 0;
1305 u32 msg[2];
1306 u8 mode = 0;
1307
1308 /* verify VF is allowed to enable even minimal mode */
1309 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))
1310 return FM10K_ERR_PARAM;
1311
1312 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {
1313 result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];
1314
1315 /* XCAST mode update requested */
1316 err = fm10k_tlv_attr_get_u8(result, &mode);
1317 if (err)
1318 return FM10K_ERR_PARAM;
1319
1320 /* prep for possible demotion depending on capabilities */
1321 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);
1322
1323 /* if mode is not currently enabled, enable it */
1324 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode)))
1325 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);
1326
1327 /* swap mode back to a bit flag */
1328 mode = FM10K_VF_FLAG_SET_MODE(mode);
1329 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {
1330 /* need to disable the port if it is already enabled */
1331 if (FM10K_VF_FLAG_ENABLED(vf_info))
1332 err = fm10k_update_lport_state_pf(hw, vf_info->glort,
1333 1, false);
1334
1335 /* when enabling the port we should reset the rate limiters */
1336 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);
1337
1338 /* set mode for minimal functionality */
1339 mode = FM10K_VF_FLAG_SET_MODE_NONE;
1340
1341 /* generate port state response to notify VF it is ready */
1342 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1343 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);
1344 mbx->ops.enqueue_tx(hw, mbx, msg);
1345 }
1346
1347 /* if enable state toggled note the update */
1348 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))
1349 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,
1350 !!mode);
1351
1352 /* if state change succeeded, then update our stored state */
1353 mode |= FM10K_VF_FLAG_CAPABLE(vf_info);
1354 if (!err)
1355 vf_info->vf_flags = mode;
1356
1357 return err;
1358}
1359
1360const struct fm10k_msg_data fm10k_iov_msg_data_pf[] = {
1361 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
1362 FM10K_VF_MSG_MSIX_HANDLER(fm10k_iov_msg_msix_pf),
1363 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_iov_msg_mac_vlan_pf),
1364 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_iov_msg_lport_state_pf),
1365 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1366};
1367
b6fec18f
AD		 1368/**
1369 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF
1370 * @hw: pointer to hardware structure
1371 * @stats: pointer to the stats structure to update
1372 *
1373 * This function collects and aggregates global and per queue hardware
1374 * statistics.
1375 **/
1376static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,
1377 struct fm10k_hw_stats *stats)
1378{
1379 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;
1380 u32 id, id_prev;
1381
1382 /* Use Tx queue 0 as a canary to detect a reset */
1383 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1384
1385 /* Read Global Statistics */
1386 do {
1387 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,
1388 &stats->timeout);
1389 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);
1390 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);
1391 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);
1392 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);
1393 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,
1394 &stats->vlan_drop);
1395 loopback_drop = fm10k_read_hw_stats_32b(hw,
1396 FM10K_STATS_LOOPBACK_DROP,
1397 &stats->loopback_drop);
1398 nodesc_drop = fm10k_read_hw_stats_32b(hw,
1399 FM10K_STATS_NODESC_DROP,
1400 &stats->nodesc_drop);
1401
1402 /* if value has not changed then we have consistent data */
1403 id_prev = id;
1404 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1405 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);
1406
1407 /* drop non-ID bits and set VALID ID bit */
1408 id &= FM10K_TXQCTL_ID_MASK;
1409 id |= FM10K_STAT_VALID;
1410
1411 /* Update Global Statistics */
1412 if (stats->stats_idx == id) {
1413 stats->timeout.count += timeout;
1414 stats->ur.count += ur;
1415 stats->ca.count += ca;
1416 stats->um.count += um;
1417 stats->xec.count += xec;
1418 stats->vlan_drop.count += vlan_drop;
1419 stats->loopback_drop.count += loopback_drop;
1420 stats->nodesc_drop.count += nodesc_drop;
1421 }
1422
1423 /* Update bases and record current PF id */
1424 fm10k_update_hw_base_32b(&stats->timeout, timeout);
1425 fm10k_update_hw_base_32b(&stats->ur, ur);
1426 fm10k_update_hw_base_32b(&stats->ca, ca);
1427 fm10k_update_hw_base_32b(&stats->um, um);
1428 fm10k_update_hw_base_32b(&stats->xec, xec);
1429 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);
1430 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);
1431 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);
1432 stats->stats_idx = id;
1433
1434 /* Update Queue Statistics */
1435 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
1436}
1437
1438/**
1439 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1440 * @hw: pointer to hardware structure
1441 * @stats: pointer to the stats structure to update
1442 *
1443 * This function resets the base for global and per queue hardware
1444 * statistics.
1445 **/
1446static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,
1447 struct fm10k_hw_stats *stats)
1448{
1449 /* Unbind Global Statistics */
1450 fm10k_unbind_hw_stats_32b(&stats->timeout);
1451 fm10k_unbind_hw_stats_32b(&stats->ur);
1452 fm10k_unbind_hw_stats_32b(&stats->ca);
1453 fm10k_unbind_hw_stats_32b(&stats->um);
1454 fm10k_unbind_hw_stats_32b(&stats->xec);
1455 fm10k_unbind_hw_stats_32b(&stats->vlan_drop);
1456 fm10k_unbind_hw_stats_32b(&stats->loopback_drop);
1457 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop);
1458
1459 /* Unbind Queue Statistics */
1460 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
1461
1462 /* Reinitialize bases for all stats */
1463 fm10k_update_hw_stats_pf(hw, stats);
1464}
1465
401b5383
AD		 1466/**
1467 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1468 * @hw: pointer to hardware structure
1469 * @dma_mask: 64 bit DMA mask required for platform
1470 *
1471 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1472 * to limit the access to memory beyond what is physically in the system.
1473 **/
1474static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)
1475{
1476 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1477 u32 phyaddr = (u32)(dma_mask >> 32);
1478
1479 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr);
1480}
1481
b6fec18f
AD		 1482/**
1483 * fm10k_get_fault_pf - Record a fault in one of the interface units
1484 * @hw: pointer to hardware structure
1485 * @type: pointer to fault type register offset
1486 * @fault: pointer to memory location to record the fault
1487 *
1488 * Record the fault register contents to the fault data structure and
1489 * clear the entry from the register.
1490 *
1491 * Returns ERR_PARAM if invalid register is specified or no error is present.
1492 **/
1493static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,
1494 struct fm10k_fault *fault)
1495{
1496 u32 func;
1497
1498 /* verify the fault register is in range and is aligned */
1499 switch (type) {
1500 case FM10K_PCA_FAULT:
1501 case FM10K_THI_FAULT:
1502 case FM10K_FUM_FAULT:
1503 break;
1504 default:
1505 return FM10K_ERR_PARAM;
1506 }
1507
1508 /* only service faults that are valid */
1509 func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC);
1510 if (!(func & FM10K_FAULT_FUNC_VALID))
1511 return FM10K_ERR_PARAM;
1512
1513 /* read remaining fields */
1514 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI);
1515 fault->address <<= 32;
1516 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO);
1517 fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO);
1518
1519 /* clear valid bit to allow for next error */
1520 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
1521
1522 /* Record which function triggered the error */
1523 if (func & FM10K_FAULT_FUNC_PF)
1524 fault->func = 0;
1525 else
1526 fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >>
1527 FM10K_FAULT_FUNC_VF_SHIFT);
1528
1529 /* record fault type */
1530 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;
1531
1532 return 0;
1533}
1534
401b5383
AD		 1535/**
1536 * fm10k_request_lport_map_pf - Request LPORT map from the switch API
1537 * @hw: pointer to hardware structure
1538 *
1539 **/
1540static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)
1541{
1542 struct fm10k_mbx_info *mbx = &hw->mbx;
1543 u32 msg[1];
1544
1545 /* issue request asking for LPORT map */
1546 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);
1547
1548 /* load onto outgoing mailbox */
1549 return mbx->ops.enqueue_tx(hw, mbx, msg);
1550}
1551
1552/**
1553 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1554 * @hw: pointer to hardware structure
1555 * @switch_ready: pointer to boolean value that will record switch state
1556 *
1557 * This funciton will check the DMA_CTRL2 register and mailbox in order
1558 * to determine if the switch is ready for the PF to begin requesting
1559 * addresses and mapping traffic to the local interface.
1560 **/
1561static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)
1562{
1563 s32 ret_val = 0;
1564 u32 dma_ctrl2;
1565
1566 /* verify the switch is ready for interraction */
1567 dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
1568 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))
1569 goto out;
1570
1571 /* retrieve generic host state info */
1572 ret_val = fm10k_get_host_state_generic(hw, switch_ready);
1573 if (ret_val)
1574 goto out;
1575
1576 /* interface cannot receive traffic without logical ports */
1577 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE)
1578 ret_val = fm10k_request_lport_map_pf(hw);
1579
1580out:
1581 return ret_val;
1582}
1583
1584/* This structure defines the attibutes to be parsed below */
1585const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {
1586 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),
1587 FM10K_TLV_ATTR_LAST
1588};
1589
1590/**
1591 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1592 * @hw: Pointer to hardware structure
1593 * @results: pointer array containing parsed data
1594 * @mbx: Pointer to mailbox information structure
1595 *
1596 * This handler configures the lport mapping based on the reply from the
1597 * switch API.
1598 **/
1599s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,
1600 struct fm10k_mbx_info *mbx)
1601{
1602 u16 glort, mask;
1603 u32 dglort_map;
1604 s32 err;
1605
1606 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],
1607 &dglort_map);
1608 if (err)
1609 return err;
1610
1611 /* extract values out of the header */
1612 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);
1613 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);
1614
1615 /* verify mask is set and none of the masked bits in glort are set */
1616 if (!mask || (glort & ~mask))
1617 return FM10K_ERR_PARAM;
1618
1619 /* verify the mask is contiguous, and that it is 1's followed by 0's */
1620 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)
1621 return FM10K_ERR_PARAM;
1622
1623 /* record the glort, mask, and port count */
1624 hw->mac.dglort_map = dglort_map;
1625
1626 return 0;
1627}
1628
1629const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {
1630 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),
1631 FM10K_TLV_ATTR_LAST
1632};
1633
1634/**
1635 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1636 * @hw: Pointer to hardware structure
1637 * @results: pointer array containing parsed data
1638 * @mbx: Pointer to mailbox information structure
1639 *
1640 * This handler configures the default VLAN for the PF
1641 **/
1642s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,
1643 struct fm10k_mbx_info *mbx)
1644{
1645 u16 glort, pvid;
1646 u32 pvid_update;
1647 s32 err;
1648
1649 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1650 &pvid_update);
1651 if (err)
1652 return err;
1653
1654 /* extract values from the pvid update */
1655 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1656 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1657
1658 /* if glort is not valid return error */
1659 if (!fm10k_glort_valid_pf(hw, glort))
1660 return FM10K_ERR_PARAM;
1661
1662 /* verify VID is valid */
1663 if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1664 return FM10K_ERR_PARAM;
1665
1666 /* record the port VLAN ID value */
1667 hw->mac.default_vid = pvid;
1668
1669 return 0;
1670}
1671
1672/**
1673 * fm10k_record_global_table_data - Move global table data to swapi table info
1674 * @from: pointer to source table data structure
1675 * @to: pointer to destination table info structure
1676 *
1677 * This function is will copy table_data to the table_info contained in
1678 * the hw struct.
1679 **/
1680static void fm10k_record_global_table_data(struct fm10k_global_table_data *from,
1681 struct fm10k_swapi_table_info *to)
1682{
1683 /* convert from le32 struct to CPU byte ordered values */
1684 to->used = le32_to_cpu(from->used);
1685 to->avail = le32_to_cpu(from->avail);
1686}
1687
1688const struct fm10k_tlv_attr fm10k_err_msg_attr[] = {
1689 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1690 sizeof(struct fm10k_swapi_error)),
1691 FM10K_TLV_ATTR_LAST
1692};
1693
1694/**
1695 * fm10k_msg_err_pf - Message handler for error reply
1696 * @hw: Pointer to hardware structure
1697 * @results: pointer array containing parsed data
1698 * @mbx: Pointer to mailbox information structure
1699 *
1700 * This handler will capture the data for any error replies to previous
1701 * messages that the PF has sent.
1702 **/
1703s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,
1704 struct fm10k_mbx_info *mbx)
1705{
1706 struct fm10k_swapi_error err_msg;
1707 s32 err;
1708
1709 /* extract structure from message */
1710 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],
1711 &err_msg, sizeof(err_msg));
1712 if (err)
1713 return err;
1714
1715 /* record table status */
1716 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);
1717 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);
1718 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);
1719
1720 /* record SW API status value */
1721 hw->swapi.status = le32_to_cpu(err_msg.status);
1722
1723 return 0;
1724}
1725
1726static const struct fm10k_msg_data fm10k_msg_data_pf[] = {
1727 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1728 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1729 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),
1730 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1731 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1732 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),
1733 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1734};
1735
b6fec18f
AD		 1736static struct fm10k_mac_ops mac_ops_pf = {
1737 .get_bus_info = &fm10k_get_bus_info_generic,
1738 .reset_hw = &fm10k_reset_hw_pf,
1739 .init_hw = &fm10k_init_hw_pf,
1740 .start_hw = &fm10k_start_hw_generic,
1741 .stop_hw = &fm10k_stop_hw_generic,
1742 .is_slot_appropriate = &fm10k_is_slot_appropriate_pf,
401b5383 1743 .update_vlan = &fm10k_update_vlan_pf,
b6fec18f 1744 .read_mac_addr = &fm10k_read_mac_addr_pf,
401b5383
AD		 1745 .update_uc_addr = &fm10k_update_uc_addr_pf,
1746 .update_mc_addr = &fm10k_update_mc_addr_pf,
1747 .update_xcast_mode = &fm10k_update_xcast_mode_pf,
1748 .update_int_moderator = &fm10k_update_int_moderator_pf,
1749 .update_lport_state = &fm10k_update_lport_state_pf,
b6fec18f
AD		 1750 .update_hw_stats = &fm10k_update_hw_stats_pf,
1751 .rebind_hw_stats = &fm10k_rebind_hw_stats_pf,
401b5383
AD		 1752 .configure_dglort_map = &fm10k_configure_dglort_map_pf,
1753 .set_dma_mask = &fm10k_set_dma_mask_pf,
b6fec18f 1754 .get_fault = &fm10k_get_fault_pf,
401b5383 1755 .get_host_state = &fm10k_get_host_state_pf,
b6fec18f
AD		 1756};
1757
c2653865
AD		 1758static struct fm10k_iov_ops iov_ops_pf = {
1759 .assign_resources = &fm10k_iov_assign_resources_pf,
1760 .configure_tc = &fm10k_iov_configure_tc_pf,
1761 .assign_int_moderator = &fm10k_iov_assign_int_moderator_pf,
1762 .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf,
1763 .reset_resources = &fm10k_iov_reset_resources_pf,
1764 .set_lport = &fm10k_iov_set_lport_pf,
1765 .reset_lport = &fm10k_iov_reset_lport_pf,
1766 .update_stats = &fm10k_iov_update_stats_pf,
1767};
1768
401b5383
AD		 1769static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw)
1770{
1771 fm10k_get_invariants_generic(hw);
1772
1773 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);
1774}
1775
b6fec18f
AD		 1776struct fm10k_info fm10k_pf_info = {
1777 .mac = fm10k_mac_pf,
401b5383 1778 .get_invariants = &fm10k_get_invariants_pf,
b6fec18f 1779 .mac_ops = &mac_ops_pf,
c2653865 1780 .iov_ops = &iov_ops_pf,
b6fec18f 1781};
Linux 6.x block layer and io_uring tree(s)