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fm10k: Implement ndo_features_check
[linux-2.6-block.git] / drivers / net / ethernet / intel / fm10k / fm10k_pf.c
CommitLineData
b6fec18f
AD		 1/* Intel Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
19 */
20
21#include "fm10k_pf.h"
c2653865 22#include "fm10k_vf.h"
b6fec18f
AD		 23
24/**
25 * fm10k_reset_hw_pf - PF hardware reset
26 * @hw: pointer to hardware structure
27 *
28 * This function should return the hardware to a state similar to the
29 * one it is in after being powered on.
30 **/
31static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
32{
33 s32 err;
34 u32 reg;
35 u16 i;
36
37 /* Disable interrupts */
38 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
39
40 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */
41 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
42 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
43
44 /* We assume here Tx and Rx queue 0 are owned by the PF */
45
46 /* Shut off VF access to their queues forcing them to queue 0 */
47 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {
48 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
49 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
50 }
51
52 /* shut down all rings */
53 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
54 if (err)
55 return err;
56
57 /* Verify that DMA is no longer active */
58 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL);
59 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))
60 return FM10K_ERR_DMA_PENDING;
61
62 /* Inititate data path reset */
63 reg |= FM10K_DMA_CTRL_DATAPATH_RESET;
64 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg);
65
66 /* Flush write and allow 100us for reset to complete */
67 fm10k_write_flush(hw);
68 udelay(FM10K_RESET_TIMEOUT);
69
70 /* Verify we made it out of reset */
71 reg = fm10k_read_reg(hw, FM10K_IP);
72 if (!(reg & FM10K_IP_NOTINRESET))
73 err = FM10K_ERR_RESET_FAILED;
74
75 return err;
76}
77
c2653865
AD		 78/**
79 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
80 * @hw: pointer to hardware structure
81 *
82 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
83 **/
84static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)
85{
86 u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL);
87
88 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);
89}
90
b6fec18f
AD		 91/**
92 * fm10k_init_hw_pf - PF hardware initialization
93 * @hw: pointer to hardware structure
94 *
95 **/
96static s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
97{
98 u32 dma_ctrl, txqctl;
99 u16 i;
100
101 /* Establish default VSI as valid */
102 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
103 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
104 FM10K_DGLORTMAP_ANY);
105
106 /* Invalidate all other GLORT entries */
107 for (i = 1; i < FM10K_DGLORT_COUNT; i++)
108 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
109
110 /* reset ITR2(0) to point to itself */
111 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
112
113 /* reset VF ITR2(0) to point to 0 avoid PF registers */
114 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
115
116 /* loop through all PF ITR2 registers pointing them to the previous */
117 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)
118 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
119
120 /* Enable interrupt moderator if not already enabled */
121 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
122
123 /* compute the default txqctl configuration */
124 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |
125 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);
126
127 for (i = 0; i < FM10K_MAX_QUEUES; i++) {
128 /* configure rings for 256 Queue / 32 Descriptor cache mode */
129 fm10k_write_reg(hw, FM10K_TQDLOC(i),
130 (i * FM10K_TQDLOC_BASE_32_DESC) |
131 FM10K_TQDLOC_SIZE_32_DESC);
132 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
133
134 /* configure rings to provide TPH processing hints */
135 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i),
136 FM10K_TPH_TXCTRL_DESC_TPHEN |
137 FM10K_TPH_TXCTRL_DESC_RROEN |
138 FM10K_TPH_TXCTRL_DESC_WROEN |
139 FM10K_TPH_TXCTRL_DATA_RROEN);
140 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i),
141 FM10K_TPH_RXCTRL_DESC_TPHEN |
142 FM10K_TPH_RXCTRL_DESC_RROEN |
143 FM10K_TPH_RXCTRL_DATA_WROEN |
144 FM10K_TPH_RXCTRL_HDR_WROEN);
145 }
146
147 /* set max hold interval to align with 1.024 usec in all modes */
148 switch (hw->bus.speed) {
149 case fm10k_bus_speed_2500:
150 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
151 break;
152 case fm10k_bus_speed_5000:
153 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
154 break;
155 case fm10k_bus_speed_8000:
156 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
157 break;
158 default:
159 dma_ctrl = 0;
160 break;
161 }
162
163 /* Configure TSO flags */
164 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
165 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
166
167 /* Enable DMA engine
168 * Set Rx Descriptor size to 32
169 * Set Minimum MSS to 64
170 * Set Maximum number of Rx queues to 256 / 32 Descriptor
171 */
172 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
173 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |
174 FM10K_DMA_CTRL_32_DESC;
175
176 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl);
177
178 /* record maximum queue count, we limit ourselves to 128 */
179 hw->mac.max_queues = FM10K_MAX_QUEUES_PF;
180
c2653865
AD		 181 /* We support either 64 VFs or 7 VFs depending on if we have ARI */
182 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;
183
b6fec18f
AD		 184 return 0;
185}
186
187/**
188 * fm10k_is_slot_appropriate_pf - Indicate appropriate slot for this SKU
189 * @hw: pointer to hardware structure
190 *
191 * Looks at the PCIe bus info to confirm whether or not this slot can support
192 * the necessary bandwidth for this device.
193 **/
194static bool fm10k_is_slot_appropriate_pf(struct fm10k_hw *hw)
195{
196 return (hw->bus.speed == hw->bus_caps.speed) &&
197 (hw->bus.width == hw->bus_caps.width);
198}
199
401b5383
AD		 200/**
201 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
202 * @hw: pointer to hardware structure
203 * @vid: VLAN ID to add to table
204 * @vsi: Index indicating VF ID or PF ID in table
205 * @set: Indicates if this is a set or clear operation
206 *
207 * This function adds or removes the corresponding VLAN ID from the VLAN
208 * filter table for the corresponding function. In addition to the
209 * standard set/clear that supports one bit a multi-bit write is
210 * supported to set 64 bits at a time.
211 **/
212static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
213{
214 u32 vlan_table, reg, mask, bit, len;
215
216 /* verify the VSI index is valid */
217 if (vsi > FM10K_VLAN_TABLE_VSI_MAX)
218 return FM10K_ERR_PARAM;
219
220 /* VLAN multi-bit write:
221 * The multi-bit write has several parts to it.
222 * 3 2 1 0
223 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
225 * | RSVD0 | Length |C|RSVD0| VLAN ID |
226 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
227 *
228 * VLAN ID: Vlan Starting value
229 * RSVD0: Reserved section, must be 0
230 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
231 * Length: Number of times to repeat the bit being set
232 */
233 len = vid >> 16;
234 vid = (vid << 17) >> 17;
235
236 /* verify the reserved 0 fields are 0 */
237 if (len >= FM10K_VLAN_TABLE_VID_MAX ||
238 vid >= FM10K_VLAN_TABLE_VID_MAX)
239 return FM10K_ERR_PARAM;
240
241 /* Loop through the table updating all required VLANs */
242 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;
243 len < FM10K_VLAN_TABLE_VID_MAX;
244 len -= 32 - bit, reg++, bit = 0) {
245 /* record the initial state of the register */
246 vlan_table = fm10k_read_reg(hw, reg);
247
248 /* truncate mask if we are at the start or end of the run */
249 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;
250
251 /* make necessary modifications to the register */
252 mask &= set ? ~vlan_table : vlan_table;
253 if (mask)
254 fm10k_write_reg(hw, reg, vlan_table ^ mask);
255 }
256
257 return 0;
258}
259
b6fec18f
AD		 260/**
261 * fm10k_read_mac_addr_pf - Read device MAC address
262 * @hw: pointer to the HW structure
263 *
264 * Reads the device MAC address from the SM_AREA and stores the value.
265 **/
266static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)
267{
268 u8 perm_addr[ETH_ALEN];
269 u32 serial_num;
270 int i;
271
272 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1));
273
274 /* last byte should be all 1's */
275 if ((~serial_num) << 24)
276 return FM10K_ERR_INVALID_MAC_ADDR;
277
278 perm_addr[0] = (u8)(serial_num >> 24);
279 perm_addr[1] = (u8)(serial_num >> 16);
280 perm_addr[2] = (u8)(serial_num >> 8);
281
282 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0));
283
284 /* first byte should be all 1's */
285 if ((~serial_num) >> 24)
286 return FM10K_ERR_INVALID_MAC_ADDR;
287
288 perm_addr[3] = (u8)(serial_num >> 16);
289 perm_addr[4] = (u8)(serial_num >> 8);
290 perm_addr[5] = (u8)(serial_num);
291
292 for (i = 0; i < ETH_ALEN; i++) {
293 hw->mac.perm_addr[i] = perm_addr[i];
294 hw->mac.addr[i] = perm_addr[i];
295 }
296
297 return 0;
298}
299
401b5383
AD		 300/**
301 * fm10k_glort_valid_pf - Validate that the provided glort is valid
302 * @hw: pointer to the HW structure
303 * @glort: base glort to be validated
304 *
305 * This function will return an error if the provided glort is invalid
306 **/
307bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)
308{
309 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;
310
311 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);
312}
313
314/**
315 * fm10k_update_uc_addr_pf - Update device unicast addresss
316 * @hw: pointer to the HW structure
317 * @glort: base resource tag for this request
318 * @mac: MAC address to add/remove from table
319 * @vid: VLAN ID to add/remove from table
320 * @add: Indicates if this is an add or remove operation
321 * @flags: flags field to indicate add and secure
322 *
323 * This function generates a message to the Switch API requesting
324 * that the given logical port add/remove the given L2 MAC/VLAN address.
325 **/
326static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
327 const u8 *mac, u16 vid, bool add, u8 flags)
328{
329 struct fm10k_mbx_info *mbx = &hw->mbx;
330 struct fm10k_mac_update mac_update;
331 u32 msg[5];
332
33a44c28
MV		 333 /* if glort or vlan are not valid return error */
334 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)
401b5383
AD		 335 return FM10K_ERR_PARAM;
336
401b5383
AD		 337 /* record fields */
338 mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) |
339 ((u32)mac[3] << 16) |
340 ((u32)mac[4] << 8) |
341 ((u32)mac[5]));
342 mac_update.mac_upper = cpu_to_le16(((u32)mac[0] << 8) |
343 ((u32)mac[1]));
344 mac_update.vlan = cpu_to_le16(vid);
345 mac_update.glort = cpu_to_le16(glort);
346 mac_update.action = add ? 0 : 1;
347 mac_update.flags = flags;
348
349 /* populate mac_update fields */
350 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);
351 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,
352 &mac_update, sizeof(mac_update));
353
354 /* load onto outgoing mailbox */
355 return mbx->ops.enqueue_tx(hw, mbx, msg);
356}
357
358/**
359 * fm10k_update_uc_addr_pf - Update device unicast addresss
360 * @hw: pointer to the HW structure
361 * @glort: base resource tag for this request
362 * @mac: MAC address to add/remove from table
363 * @vid: VLAN ID to add/remove from table
364 * @add: Indicates if this is an add or remove operation
365 * @flags: flags field to indicate add and secure
366 *
367 * This function is used to add or remove unicast addresses for
368 * the PF.
369 **/
370static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,
371 const u8 *mac, u16 vid, bool add, u8 flags)
372{
373 /* verify MAC address is valid */
374 if (!is_valid_ether_addr(mac))
375 return FM10K_ERR_PARAM;
376
377 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);
378}
379
380/**
381 * fm10k_update_mc_addr_pf - Update device multicast addresses
382 * @hw: pointer to the HW structure
383 * @glort: base resource tag for this request
384 * @mac: MAC address to add/remove from table
385 * @vid: VLAN ID to add/remove from table
386 * @add: Indicates if this is an add or remove operation
387 *
388 * This function is used to add or remove multicast MAC addresses for
389 * the PF.
390 **/
391static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,
392 const u8 *mac, u16 vid, bool add)
393{
394 /* verify multicast address is valid */
395 if (!is_multicast_ether_addr(mac))
396 return FM10K_ERR_PARAM;
397
398 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);
399}
400
401/**
402 * fm10k_update_xcast_mode_pf - Request update of multicast mode
403 * @hw: pointer to hardware structure
404 * @glort: base resource tag for this request
405 * @mode: integer value indicating mode being requested
406 *
407 * This function will attempt to request a higher mode for the port
408 * so that it can enable either multicast, multicast promiscuous, or
409 * promiscuous mode of operation.
410 **/
411static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)
412{
413 struct fm10k_mbx_info *mbx = &hw->mbx;
414 u32 msg[3], xcast_mode;
415
416 if (mode > FM10K_XCAST_MODE_NONE)
417 return FM10K_ERR_PARAM;
418 /* if glort is not valid return error */
419 if (!fm10k_glort_valid_pf(hw, glort))
420 return FM10K_ERR_PARAM;
421
422 /* write xcast mode as a single u32 value,
423 * lower 16 bits: glort
424 * upper 16 bits: mode
425 */
426 xcast_mode = ((u32)mode << 16) | glort;
427
428 /* generate message requesting to change xcast mode */
429 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);
430 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);
431
432 /* load onto outgoing mailbox */
433 return mbx->ops.enqueue_tx(hw, mbx, msg);
434}
435
436/**
437 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list
438 * @hw: pointer to hardware structure
439 *
440 * This function walks through the MSI-X vector table to determine the
441 * number of active interrupts and based on that information updates the
442 * interrupt moderator linked list.
443 **/
444static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)
445{
446 u32 i;
447
448 /* Disable interrupt moderator */
449 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
450
451 /* loop through PF from last to first looking enabled vectors */
452 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {
453 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
454 break;
455 }
456
457 /* always reset VFITR2[0] to point to last enabled PF vector*/
458 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
459
460 /* reset ITR2[0] to point to last enabled PF vector */
c2653865
AD		 461 if (!hw->iov.num_vfs)
462 fm10k_write_reg(hw, FM10K_ITR2(0), i);
401b5383
AD		 463
464 /* Enable interrupt moderator */
465 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
466}
467
468/**
469 * fm10k_update_lport_state_pf - Notify the switch of a change in port state
470 * @hw: pointer to the HW structure
471 * @glort: base resource tag for this request
472 * @count: number of logical ports being updated
473 * @enable: boolean value indicating enable or disable
474 *
475 * This function is used to add/remove a logical port from the switch.
476 **/
477static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,
478 u16 count, bool enable)
479{
480 struct fm10k_mbx_info *mbx = &hw->mbx;
481 u32 msg[3], lport_msg;
482
483 /* do nothing if we are being asked to create or destroy 0 ports */
484 if (!count)
485 return 0;
486
487 /* if glort is not valid return error */
488 if (!fm10k_glort_valid_pf(hw, glort))
489 return FM10K_ERR_PARAM;
490
491 /* construct the lport message from the 2 pieces of data we have */
492 lport_msg = ((u32)count << 16) | glort;
493
494 /* generate lport create/delete message */
495 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :
496 FM10K_PF_MSG_ID_LPORT_DELETE);
497 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);
498
499 /* load onto outgoing mailbox */
500 return mbx->ops.enqueue_tx(hw, mbx, msg);
501}
502
503/**
504 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
505 * @hw: pointer to hardware structure
506 * @dglort: pointer to dglort configuration structure
507 *
508 * Reads the configuration structure contained in dglort_cfg and uses
509 * that information to then populate a DGLORTMAP/DEC entry and the queues
510 * to which it has been assigned.
511 **/
512static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,
513 struct fm10k_dglort_cfg *dglort)
514{
515 u16 glort, queue_count, vsi_count, pc_count;
516 u16 vsi, queue, pc, q_idx;
517 u32 txqctl, dglortdec, dglortmap;
518
519 /* verify the dglort pointer */
520 if (!dglort)
521 return FM10K_ERR_PARAM;
522
523 /* verify the dglort values */
524 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||
525 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||
526 (dglort->queue_l > 8) || (dglort->queue_b >= 256))
527 return FM10K_ERR_PARAM;
528
529 /* determine count of VSIs and queues */
530 queue_count = 1 << (dglort->rss_l + dglort->pc_l);
531 vsi_count = 1 << (dglort->vsi_l + dglort->queue_l);
532 glort = dglort->glort;
533 q_idx = dglort->queue_b;
534
535 /* configure SGLORT for queues */
536 for (vsi = 0; vsi < vsi_count; vsi++, glort++) {
537 for (queue = 0; queue < queue_count; queue++, q_idx++) {
538 if (q_idx >= FM10K_MAX_QUEUES)
539 break;
540
541 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort);
542 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort);
543 }
544 }
545
546 /* determine count of PCs and queues */
547 queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l);
548 pc_count = 1 << dglort->pc_l;
549
550 /* configure PC for Tx queues */
551 for (pc = 0; pc < pc_count; pc++) {
552 q_idx = pc + dglort->queue_b;
553 for (queue = 0; queue < queue_count; queue++) {
554 if (q_idx >= FM10K_MAX_QUEUES)
555 break;
556
557 txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx));
558 txqctl &= ~FM10K_TXQCTL_PC_MASK;
559 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT;
560 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl);
561
562 q_idx += pc_count;
563 }
564 }
565
566 /* configure DGLORTDEC */
567 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |
568 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |
569 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |
570 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |
571 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |
572 ((u32)(dglort->queue_l));
573 if (dglort->inner_rss)
574 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE;
575
576 /* configure DGLORTMAP */
577 dglortmap = (dglort->idx == fm10k_dglort_default) ?
578 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;
579 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;
580 dglortmap |= dglort->glort;
581
582 /* write values to hardware */
583 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
584 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
585
586 return 0;
587}
588
c2653865
AD		 589u16 fm10k_queues_per_pool(struct fm10k_hw *hw)
590{
591 u16 num_pools = hw->iov.num_pools;
592
593 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?
594 8 : FM10K_MAX_QUEUES_POOL;
595}
596
597u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)
598{
599 u16 num_vfs = hw->iov.num_vfs;
600 u16 vf_q_idx = FM10K_MAX_QUEUES;
601
602 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);
603
604 return vf_q_idx;
605}
606
607static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)
608{
609 u16 num_pools = hw->iov.num_pools;
610
611 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :
612 FM10K_MAX_VECTORS_POOL;
613}
614
615static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)
616{
617 u16 vf_v_idx = FM10K_MAX_VECTORS_PF;
618
619 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;
620
621 return vf_v_idx;
622}
623
624/**
625 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
626 * @hw: pointer to the HW structure
627 * @num_vfs: number of VFs to be allocated
628 * @num_pools: number of virtualization pools to be allocated
629 *
630 * Allocates queues and traffic classes to virtualization entities to prepare
631 * the PF for SR-IOV and VMDq
632 **/
633static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
634 u16 num_pools)
635{
636 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;
637 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;
638 int i, j;
639
640 /* hardware only supports up to 64 pools */
641 if (num_pools > 64)
642 return FM10K_ERR_PARAM;
643
644 /* the number of VFs cannot exceed the number of pools */
645 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))
646 return FM10K_ERR_PARAM;
647
648 /* record number of virtualization entities */
649 hw->iov.num_vfs = num_vfs;
650 hw->iov.num_pools = num_pools;
651
652 /* determine qmap offsets and counts */
653 qmap_stride = (num_vfs > 8) ? 32 : 256;
654 qpp = fm10k_queues_per_pool(hw);
655 vpp = fm10k_vectors_per_pool(hw);
656
657 /* calculate starting index for queues */
658 vf_q_idx = fm10k_vf_queue_index(hw, 0);
659 qmap_idx = 0;
660
661 /* establish TCs with -1 credits and no quanta to prevent transmit */
662 for (i = 0; i < num_vfs; i++) {
663 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0);
664 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0);
665 fm10k_write_reg(hw, FM10K_TC_CREDIT(i),
666 FM10K_TC_CREDIT_CREDIT_MASK);
667 }
668
669 /* zero out all mbmem registers */
670 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)
671 fm10k_write_reg(hw, FM10K_MBMEM(i), 0);
672
673 /* clear event notification of VF FLR */
674 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0);
675 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0);
676
677 /* loop through unallocated rings assigning them back to PF */
678 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
679 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
680 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | vid);
681 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
682 }
683
684 /* PF should have already updated VFITR2[0] */
685
686 /* update all ITR registers to flow to VFITR2[0] */
687 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {
688 if (!(i & (vpp - 1)))
689 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp);
690 else
691 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
692 }
693
694 /* update PF ITR2[0] to reference the last vector */
695 fm10k_write_reg(hw, FM10K_ITR2(0),
696 fm10k_vf_vector_index(hw, num_vfs - 1));
697
698 /* loop through rings populating rings and TCs */
699 for (i = 0; i < num_vfs; i++) {
700 /* record index for VF queue 0 for use in end of loop */
701 vf_q_idx0 = vf_q_idx;
702
703 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {
704 /* assign VF and locked TC to queues */
705 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
706 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx),
707 (i << FM10K_TXQCTL_TC_SHIFT) | i |
708 FM10K_TXQCTL_VF | vid);
709 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx),
710 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
711 FM10K_RXDCTL_DROP_ON_EMPTY);
712 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx),
713 FM10K_RXQCTL_VF |
714 (i << FM10K_RXQCTL_VF_SHIFT));
715
716 /* map queue pair to VF */
717 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
718 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
719 }
720
721 /* repeat the first ring for all of the remaining VF rings */
722 for (; j < qmap_stride; j++, qmap_idx++) {
723 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
724 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
725 }
726 }
727
728 /* loop through remaining indexes assigning all to queue 0 */
729 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {
730 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
731 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0);
732 qmap_idx++;
733 }
734
735 return 0;
736}
737
738/**
739 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF
740 * @hw: pointer to the HW structure
741 * @vf_idx: index of VF receiving GLORT
742 * @rate: Rate indicated in Mb/s
743 *
744 * Configured the TC for a given VF to allow only up to a given number
745 * of Mb/s of outgoing Tx throughput.
746 **/
747static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)
748{
749 /* configure defaults */
750 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;
751 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;
752
753 /* verify vf is in range */
754 if (vf_idx >= hw->iov.num_vfs)
755 return FM10K_ERR_PARAM;
756
757 /* set interval to align with 4.096 usec in all modes */
758 switch (hw->bus.speed) {
759 case fm10k_bus_speed_2500:
760 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1;
761 break;
762 case fm10k_bus_speed_5000:
763 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2;
764 break;
765 default:
766 break;
767 }
768
769 if (rate) {
770 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)
771 return FM10K_ERR_PARAM;
772
773 /* The quanta is measured in Bytes per 4.096 or 8.192 usec
774 * The rate is provided in Mbits per second
775 * To tralslate from rate to quanta we need to multiply the
776 * rate by 8.192 usec and divide by 8 bits/byte. To avoid
777 * dealing with floating point we can round the values up
778 * to the nearest whole number ratio which gives us 128 / 125.
779 */
780 tc_rate = (rate * 128) / 125;
781
782 /* try to keep the rate limiting accurate by increasing
783 * the number of credits and interval for rates less than 4Gb/s
784 */
785 if (rate < 4000)
786 interval <<= 1;
787 else
788 tc_rate >>= 1;
789 }
790
791 /* update rate limiter with new values */
792 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
793 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
794 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
795
796 return 0;
797}
798
799/**
800 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
801 * @hw: pointer to the HW structure
802 * @vf_idx: index of VF receiving GLORT
803 *
804 * Update the interrupt moderator linked list to include any MSI-X
805 * interrupts which the VF has enabled in the MSI-X vector table.
806 **/
807static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)
808{
809 u16 vf_v_idx, vf_v_limit, i;
810
811 /* verify vf is in range */
812 if (vf_idx >= hw->iov.num_vfs)
813 return FM10K_ERR_PARAM;
814
815 /* determine vector offset and count*/
816 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
817 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
818
819 /* search for first vector that is not masked */
820 for (i = vf_v_limit - 1; i > vf_v_idx; i--) {
821 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
822 break;
823 }
824
825 /* reset linked list so it now includes our active vectors */
826 if (vf_idx == (hw->iov.num_vfs - 1))
827 fm10k_write_reg(hw, FM10K_ITR2(0), i);
828 else
829 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i);
830
831 return 0;
832}
833
834/**
835 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
836 * @hw: pointer to the HW structure
837 * @vf_info: pointer to VF information structure
838 *
839 * Assign a MAC address and default VLAN to a VF and notify it of the update
840 **/
841static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
842 struct fm10k_vf_info *vf_info)
843{
844 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;
845 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;
846 s32 err = 0;
847 u16 vf_idx, vf_vid;
848
849 /* verify vf is in range */
850 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)
851 return FM10K_ERR_PARAM;
852
853 /* determine qmap offsets and counts */
854 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
855 queues_per_pool = fm10k_queues_per_pool(hw);
856
857 /* calculate starting index for queues */
858 vf_idx = vf_info->vf_idx;
859 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
860 qmap_idx = qmap_stride * vf_idx;
861
862 /* MAP Tx queue back to 0 temporarily, and disable it */
863 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
864 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
865
866 /* determine correct default VLAN ID */
867 if (vf_info->pf_vid)
868 vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR;
869 else
870 vf_vid = vf_info->sw_vid;
871
872 /* generate MAC_ADDR request */
873 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
874 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,
875 vf_info->mac, vf_vid);
876
877 /* load onto outgoing mailbox, ignore any errors on enqueue */
878 if (vf_info->mbx.ops.enqueue_tx)
879 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
880
881 /* verify ring has disabled before modifying base address registers */
882 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
883 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {
884 /* limit ourselves to a 1ms timeout */
885 if (timeout == 10) {
886 err = FM10K_ERR_DMA_PENDING;
887 goto err_out;
888 }
889
890 usleep_range(100, 200);
891 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
892 }
893
894 /* Update base address registers to contain MAC address */
895 if (is_valid_ether_addr(vf_info->mac)) {
896 tdbal = (((u32)vf_info->mac[3]) << 24) |
897 (((u32)vf_info->mac[4]) << 16) |
898 (((u32)vf_info->mac[5]) << 8);
899
900 tdbah = (((u32)0xFF) << 24) |
901 (((u32)vf_info->mac[0]) << 16) |
902 (((u32)vf_info->mac[1]) << 8) |
903 ((u32)vf_info->mac[2]);
904 }
905
906 /* Record the base address into queue 0 */
907 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal);
908 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah);
909
910err_out:
911 /* configure Queue control register */
912 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
913 FM10K_TXQCTL_VID_MASK;
914 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
915 FM10K_TXQCTL_VF | vf_idx;
916
917 /* assign VID */
918 for (i = 0; i < queues_per_pool; i++)
919 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
920
921 /* restore the queue back to VF ownership */
922 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
923 return err;
924}
925
926/**
927 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
928 * @hw: pointer to the HW structure
929 * @vf_info: pointer to VF information structure
930 *
931 * Reassign the interrupts and queues to a VF following an FLR
932 **/
933static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
934 struct fm10k_vf_info *vf_info)
935{
936 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;
937 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl;
938 u16 vf_v_idx, vf_v_limit, vf_vid;
939 u8 vf_idx = vf_info->vf_idx;
940 int i;
941
942 /* verify vf is in range */
943 if (vf_idx >= hw->iov.num_vfs)
944 return FM10K_ERR_PARAM;
945
946 /* clear event notification of VF FLR */
947 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32));
948
949 /* force timeout and then disconnect the mailbox */
950 vf_info->mbx.timeout = 0;
951 if (vf_info->mbx.ops.disconnect)
952 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx);
953
954 /* determine vector offset and count*/
955 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
956 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
957
958 /* determine qmap offsets and counts */
959 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
960 queues_per_pool = fm10k_queues_per_pool(hw);
961 qmap_idx = qmap_stride * vf_idx;
962
963 /* make all the queues inaccessible to the VF */
964 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {
965 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
966 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
967 }
968
969 /* calculate starting index for queues */
970 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
971
972 /* determine correct default VLAN ID */
973 if (vf_info->pf_vid)
974 vf_vid = vf_info->pf_vid;
975 else
976 vf_vid = vf_info->sw_vid;
977
978 /* configure Queue control register */
979 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |
980 (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
981 FM10K_TXQCTL_VF | vf_idx;
982 rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT);
983
984 /* stop further DMA and reset queue ownership back to VF */
985 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {
986 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
987 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
988 fm10k_write_reg(hw, FM10K_RXDCTL(i),
989 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
990 FM10K_RXDCTL_DROP_ON_EMPTY);
991 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl);
992 }
993
994 /* reset TC with -1 credits and no quanta to prevent transmit */
995 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
996 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0);
997 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx),
998 FM10K_TC_CREDIT_CREDIT_MASK);
999
1000 /* update our first entry in the table based on previous VF */
1001 if (!vf_idx)
1002 hw->mac.ops.update_int_moderator(hw);
1003 else
1004 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1);
1005
1006 /* reset linked list so it now includes our active vectors */
1007 if (vf_idx == (hw->iov.num_vfs - 1))
1008 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx);
1009 else
1010 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
1011
1012 /* link remaining vectors so that next points to previous */
1013 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)
1014 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
1015
1016 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1017 for (i = FM10K_VFMBMEM_LEN; i--;)
1018 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
1019 for (i = FM10K_VLAN_TABLE_SIZE; i--;)
1020 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
1021 for (i = FM10K_RETA_SIZE; i--;)
1022 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0);
1023 for (i = FM10K_RSSRK_SIZE; i--;)
1024 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
1025 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0);
1026
1027 /* Update base address registers to contain MAC address */
1028 if (is_valid_ether_addr(vf_info->mac)) {
1029 tdbal = (((u32)vf_info->mac[3]) << 24) |
1030 (((u32)vf_info->mac[4]) << 16) |
1031 (((u32)vf_info->mac[5]) << 8);
1032 tdbah = (((u32)0xFF) << 24) |
1033 (((u32)vf_info->mac[0]) << 16) |
1034 (((u32)vf_info->mac[1]) << 8) |
1035 ((u32)vf_info->mac[2]);
1036 }
1037
1038 /* map queue pairs back to VF from last to first*/
1039 for (i = queues_per_pool; i--;) {
1040 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
1041 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
1042 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
1043 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
1044 }
1045
1046 return 0;
1047}
1048
1049/**
1050 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1051 * @hw: pointer to hardware structure
1052 * @vf_info: pointer to VF information structure
1053 * @lport_idx: Logical port offset from the hardware glort
1054 * @flags: Set of capability flags to extend port beyond basic functionality
1055 *
1056 * This function allows enabling a VF port by assigning it a GLORT and
1057 * setting the flags so that it can enable an Rx mode.
1058 **/
1059static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,
1060 struct fm10k_vf_info *vf_info,
1061 u16 lport_idx, u8 flags)
1062{
1063 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;
1064
1065 /* if glort is not valid return error */
1066 if (!fm10k_glort_valid_pf(hw, glort))
1067 return FM10K_ERR_PARAM;
1068
1069 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;
1070 vf_info->glort = glort;
1071
1072 return 0;
1073}
1074
1075/**
1076 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1077 * @hw: pointer to hardware structure
1078 * @vf_info: pointer to VF information structure
1079 *
1080 * This function disables a VF port by stripping it of a GLORT and
1081 * setting the flags so that it cannot enable any Rx mode.
1082 **/
1083static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,
1084 struct fm10k_vf_info *vf_info)
1085{
1086 u32 msg[1];
1087
1088 /* need to disable the port if it is already enabled */
1089 if (FM10K_VF_FLAG_ENABLED(vf_info)) {
1090 /* notify switch that this port has been disabled */
1091 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);
1092
1093 /* generate port state response to notify VF it is not ready */
1094 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1095 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1096 }
1097
1098 /* clear flags and glort if it exists */
1099 vf_info->vf_flags = 0;
1100 vf_info->glort = 0;
1101}
1102
1103/**
1104 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1105 * @hw: pointer to hardware structure
1106 * @q: stats for all queues of a VF
1107 * @vf_idx: index of VF
1108 *
1109 * This function collects queue stats for VFs.
1110 **/
1111static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,
1112 struct fm10k_hw_stats_q *q,
1113 u16 vf_idx)
1114{
1115 u32 idx, qpp;
1116
1117 /* get stats for all of the queues */
1118 qpp = fm10k_queues_per_pool(hw);
1119 idx = fm10k_vf_queue_index(hw, vf_idx);
1120 fm10k_update_hw_stats_q(hw, q, idx, qpp);
1121}
1122
5f226ddb
AD		 1123static s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw,
1124 struct fm10k_vf_info *vf_info,
1125 u64 timestamp)
1126{
1127 u32 msg[4];
1128
1129 /* generate port state response to notify VF it is not ready */
1130 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588);
1131 fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp);
1132
1133 return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1134}
1135
c2653865
AD		 1136/**
1137 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1138 * @hw: Pointer to hardware structure
1139 * @results: Pointer array to message, results[0] is pointer to message
1140 * @mbx: Pointer to mailbox information structure
1141 *
1142 * This function is a default handler for MSI-X requests from the VF. The
1143 * assumption is that in this case it is acceptable to just directly
1144 * hand off the message form the VF to the underlying shared code.
1145 **/
1146s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results,
1147 struct fm10k_mbx_info *mbx)
1148{
1149 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1150 u8 vf_idx = vf_info->vf_idx;
1151
1152 return hw->iov.ops.assign_int_moderator(hw, vf_idx);
1153}
1154
1155/**
1156 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1157 * @hw: Pointer to hardware structure
1158 * @results: Pointer array to message, results[0] is pointer to message
1159 * @mbx: Pointer to mailbox information structure
1160 *
1161 * This function is a default handler for MAC/VLAN requests from the VF.
1162 * The assumption is that in this case it is acceptable to just directly
1163 * hand off the message form the VF to the underlying shared code.
1164 **/
1165s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
1166 struct fm10k_mbx_info *mbx)
1167{
1168 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1169 int err = 0;
1170 u8 mac[ETH_ALEN];
1171 u32 *result;
1172 u16 vlan;
1173 u32 vid;
1174
1175 /* we shouldn't be updating rules on a disabled interface */
1176 if (!FM10K_VF_FLAG_ENABLED(vf_info))
1177 err = FM10K_ERR_PARAM;
1178
1179 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {
1180 result = results[FM10K_MAC_VLAN_MSG_VLAN];
1181
1182 /* record VLAN id requested */
1183 err = fm10k_tlv_attr_get_u32(result, &vid);
1184 if (err)
1185 return err;
1186
1187 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1188 if (!vid || (vid == FM10K_VLAN_CLEAR)) {
1189 if (vf_info->pf_vid)
1190 vid |= vf_info->pf_vid;
1191 else
1192 vid |= vf_info->sw_vid;
1193 } else if (vid != vf_info->pf_vid) {
1194 return FM10K_ERR_PARAM;
1195 }
1196
1197 /* update VSI info for VF in regards to VLAN table */
1198 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi,
1199 !(vid & FM10K_VLAN_CLEAR));
1200 }
1201
1202 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {
1203 result = results[FM10K_MAC_VLAN_MSG_MAC];
1204
1205 /* record unicast MAC address requested */
1206 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1207 if (err)
1208 return err;
1209
1210 /* block attempts to set MAC for a locked device */
1211 if (is_valid_ether_addr(vf_info->mac) &&
1212 memcmp(mac, vf_info->mac, ETH_ALEN))
1213 return FM10K_ERR_PARAM;
1214
1215 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1216 if (!vlan || (vlan == FM10K_VLAN_CLEAR)) {
1217 if (vf_info->pf_vid)
1218 vlan |= vf_info->pf_vid;
1219 else
1220 vlan |= vf_info->sw_vid;
1221 } else if (vf_info->pf_vid) {
1222 return FM10K_ERR_PARAM;
1223 }
1224
1225 /* notify switch of request for new unicast address */
1226 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, mac, vlan,
1227 !(vlan & FM10K_VLAN_CLEAR), 0);
1228 }
1229
1230 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {
1231 result = results[FM10K_MAC_VLAN_MSG_MULTICAST];
1232
1233 /* record multicast MAC address requested */
1234 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1235 if (err)
1236 return err;
1237
1238 /* verify that the VF is allowed to request multicast */
1239 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))
1240 return FM10K_ERR_PARAM;
1241
1242 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1243 if (!vlan || (vlan == FM10K_VLAN_CLEAR)) {
1244 if (vf_info->pf_vid)
1245 vlan |= vf_info->pf_vid;
1246 else
1247 vlan |= vf_info->sw_vid;
1248 } else if (vf_info->pf_vid) {
1249 return FM10K_ERR_PARAM;
1250 }
1251
1252 /* notify switch of request for new multicast address */
1253 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, mac,
1254 !(vlan & FM10K_VLAN_CLEAR), 0);
1255 }
1256
1257 return err;
1258}
1259
1260/**
1261 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1262 * @vf_info: VF info structure containing capability flags
1263 * @mode: Requested xcast mode
1264 *
1265 * This function outputs the mode that most closely matches the requested
1266 * mode. If not modes match it will request we disable the port
1267 **/
1268static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,
1269 u8 mode)
1270{
1271 u8 vf_flags = vf_info->vf_flags;
1272
1273 /* match up mode to capabilities as best as possible */
1274 switch (mode) {
1275 case FM10K_XCAST_MODE_PROMISC:
1276 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)
1277 return FM10K_XCAST_MODE_PROMISC;
1278 /* fallthough */
1279 case FM10K_XCAST_MODE_ALLMULTI:
1280 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)
1281 return FM10K_XCAST_MODE_ALLMULTI;
1282 /* fallthough */
1283 case FM10K_XCAST_MODE_MULTI:
1284 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)
1285 return FM10K_XCAST_MODE_MULTI;
1286 /* fallthough */
1287 case FM10K_XCAST_MODE_NONE:
1288 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)
1289 return FM10K_XCAST_MODE_NONE;
1290 /* fallthough */
1291 default:
1292 break;
1293 }
1294
1295 /* disable interface as it should not be able to request any */
1296 return FM10K_XCAST_MODE_DISABLE;
1297}
1298
1299/**
1300 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1301 * @hw: Pointer to hardware structure
1302 * @results: Pointer array to message, results[0] is pointer to message
1303 * @mbx: Pointer to mailbox information structure
1304 *
1305 * This function is a default handler for port state requests. The port
1306 * state requests for now are basic and consist of enabling or disabling
1307 * the port.
1308 **/
1309s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,
1310 struct fm10k_mbx_info *mbx)
1311{
1312 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1313 u32 *result;
1314 s32 err = 0;
1315 u32 msg[2];
1316 u8 mode = 0;
1317
1318 /* verify VF is allowed to enable even minimal mode */
1319 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))
1320 return FM10K_ERR_PARAM;
1321
1322 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {
1323 result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];
1324
1325 /* XCAST mode update requested */
1326 err = fm10k_tlv_attr_get_u8(result, &mode);
1327 if (err)
1328 return FM10K_ERR_PARAM;
1329
1330 /* prep for possible demotion depending on capabilities */
1331 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);
1332
1333 /* if mode is not currently enabled, enable it */
1334 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode)))
1335 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);
1336
1337 /* swap mode back to a bit flag */
1338 mode = FM10K_VF_FLAG_SET_MODE(mode);
1339 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {
1340 /* need to disable the port if it is already enabled */
1341 if (FM10K_VF_FLAG_ENABLED(vf_info))
1342 err = fm10k_update_lport_state_pf(hw, vf_info->glort,
1343 1, false);
1344
1345 /* when enabling the port we should reset the rate limiters */
1346 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);
1347
1348 /* set mode for minimal functionality */
1349 mode = FM10K_VF_FLAG_SET_MODE_NONE;
1350
1351 /* generate port state response to notify VF it is ready */
1352 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1353 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);
1354 mbx->ops.enqueue_tx(hw, mbx, msg);
1355 }
1356
1357 /* if enable state toggled note the update */
1358 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))
1359 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,
1360 !!mode);
1361
1362 /* if state change succeeded, then update our stored state */
1363 mode |= FM10K_VF_FLAG_CAPABLE(vf_info);
1364 if (!err)
1365 vf_info->vf_flags = mode;
1366
1367 return err;
1368}
1369
1370const struct fm10k_msg_data fm10k_iov_msg_data_pf[] = {
1371 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
1372 FM10K_VF_MSG_MSIX_HANDLER(fm10k_iov_msg_msix_pf),
1373 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_iov_msg_mac_vlan_pf),
1374 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_iov_msg_lport_state_pf),
1375 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1376};
1377
b6fec18f
AD		 1378/**
1379 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF
1380 * @hw: pointer to hardware structure
1381 * @stats: pointer to the stats structure to update
1382 *
1383 * This function collects and aggregates global and per queue hardware
1384 * statistics.
1385 **/
1386static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,
1387 struct fm10k_hw_stats *stats)
1388{
1389 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;
1390 u32 id, id_prev;
1391
1392 /* Use Tx queue 0 as a canary to detect a reset */
1393 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1394
1395 /* Read Global Statistics */
1396 do {
1397 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,
1398 &stats->timeout);
1399 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);
1400 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);
1401 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);
1402 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);
1403 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,
1404 &stats->vlan_drop);
1405 loopback_drop = fm10k_read_hw_stats_32b(hw,
1406 FM10K_STATS_LOOPBACK_DROP,
1407 &stats->loopback_drop);
1408 nodesc_drop = fm10k_read_hw_stats_32b(hw,
1409 FM10K_STATS_NODESC_DROP,
1410 &stats->nodesc_drop);
1411
1412 /* if value has not changed then we have consistent data */
1413 id_prev = id;
1414 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1415 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);
1416
1417 /* drop non-ID bits and set VALID ID bit */
1418 id &= FM10K_TXQCTL_ID_MASK;
1419 id |= FM10K_STAT_VALID;
1420
1421 /* Update Global Statistics */
1422 if (stats->stats_idx == id) {
1423 stats->timeout.count += timeout;
1424 stats->ur.count += ur;
1425 stats->ca.count += ca;
1426 stats->um.count += um;
1427 stats->xec.count += xec;
1428 stats->vlan_drop.count += vlan_drop;
1429 stats->loopback_drop.count += loopback_drop;
1430 stats->nodesc_drop.count += nodesc_drop;
1431 }
1432
1433 /* Update bases and record current PF id */
1434 fm10k_update_hw_base_32b(&stats->timeout, timeout);
1435 fm10k_update_hw_base_32b(&stats->ur, ur);
1436 fm10k_update_hw_base_32b(&stats->ca, ca);
1437 fm10k_update_hw_base_32b(&stats->um, um);
1438 fm10k_update_hw_base_32b(&stats->xec, xec);
1439 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);
1440 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);
1441 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);
1442 stats->stats_idx = id;
1443
1444 /* Update Queue Statistics */
1445 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
1446}
1447
1448/**
1449 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1450 * @hw: pointer to hardware structure
1451 * @stats: pointer to the stats structure to update
1452 *
1453 * This function resets the base for global and per queue hardware
1454 * statistics.
1455 **/
1456static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,
1457 struct fm10k_hw_stats *stats)
1458{
1459 /* Unbind Global Statistics */
1460 fm10k_unbind_hw_stats_32b(&stats->timeout);
1461 fm10k_unbind_hw_stats_32b(&stats->ur);
1462 fm10k_unbind_hw_stats_32b(&stats->ca);
1463 fm10k_unbind_hw_stats_32b(&stats->um);
1464 fm10k_unbind_hw_stats_32b(&stats->xec);
1465 fm10k_unbind_hw_stats_32b(&stats->vlan_drop);
1466 fm10k_unbind_hw_stats_32b(&stats->loopback_drop);
1467 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop);
1468
1469 /* Unbind Queue Statistics */
1470 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
1471
1472 /* Reinitialize bases for all stats */
1473 fm10k_update_hw_stats_pf(hw, stats);
1474}
1475
401b5383
AD		 1476/**
1477 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1478 * @hw: pointer to hardware structure
1479 * @dma_mask: 64 bit DMA mask required for platform
1480 *
1481 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1482 * to limit the access to memory beyond what is physically in the system.
1483 **/
1484static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)
1485{
1486 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1487 u32 phyaddr = (u32)(dma_mask >> 32);
1488
1489 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr);
1490}
1491
b6fec18f
AD		 1492/**
1493 * fm10k_get_fault_pf - Record a fault in one of the interface units
1494 * @hw: pointer to hardware structure
1495 * @type: pointer to fault type register offset
1496 * @fault: pointer to memory location to record the fault
1497 *
1498 * Record the fault register contents to the fault data structure and
1499 * clear the entry from the register.
1500 *
1501 * Returns ERR_PARAM if invalid register is specified or no error is present.
1502 **/
1503static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,
1504 struct fm10k_fault *fault)
1505{
1506 u32 func;
1507
1508 /* verify the fault register is in range and is aligned */
1509 switch (type) {
1510 case FM10K_PCA_FAULT:
1511 case FM10K_THI_FAULT:
1512 case FM10K_FUM_FAULT:
1513 break;
1514 default:
1515 return FM10K_ERR_PARAM;
1516 }
1517
1518 /* only service faults that are valid */
1519 func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC);
1520 if (!(func & FM10K_FAULT_FUNC_VALID))
1521 return FM10K_ERR_PARAM;
1522
1523 /* read remaining fields */
1524 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI);
1525 fault->address <<= 32;
1526 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO);
1527 fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO);
1528
1529 /* clear valid bit to allow for next error */
1530 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
1531
1532 /* Record which function triggered the error */
1533 if (func & FM10K_FAULT_FUNC_PF)
1534 fault->func = 0;
1535 else
1536 fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >>
1537 FM10K_FAULT_FUNC_VF_SHIFT);
1538
1539 /* record fault type */
1540 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;
1541
1542 return 0;
1543}
1544
401b5383
AD		 1545/**
1546 * fm10k_request_lport_map_pf - Request LPORT map from the switch API
1547 * @hw: pointer to hardware structure
1548 *
1549 **/
1550static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)
1551{
1552 struct fm10k_mbx_info *mbx = &hw->mbx;
1553 u32 msg[1];
1554
1555 /* issue request asking for LPORT map */
1556 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);
1557
1558 /* load onto outgoing mailbox */
1559 return mbx->ops.enqueue_tx(hw, mbx, msg);
1560}
1561
1562/**
1563 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1564 * @hw: pointer to hardware structure
1565 * @switch_ready: pointer to boolean value that will record switch state
1566 *
1567 * This funciton will check the DMA_CTRL2 register and mailbox in order
1568 * to determine if the switch is ready for the PF to begin requesting
1569 * addresses and mapping traffic to the local interface.
1570 **/
1571static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)
1572{
1573 s32 ret_val = 0;
1574 u32 dma_ctrl2;
1575
1576 /* verify the switch is ready for interraction */
1577 dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
1578 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))
1579 goto out;
1580
1581 /* retrieve generic host state info */
1582 ret_val = fm10k_get_host_state_generic(hw, switch_ready);
1583 if (ret_val)
1584 goto out;
1585
1586 /* interface cannot receive traffic without logical ports */
1587 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE)
1588 ret_val = fm10k_request_lport_map_pf(hw);
1589
1590out:
1591 return ret_val;
1592}
1593
1594/* This structure defines the attibutes to be parsed below */
1595const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {
1596 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),
1597 FM10K_TLV_ATTR_LAST
1598};
1599
1600/**
1601 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1602 * @hw: Pointer to hardware structure
1603 * @results: pointer array containing parsed data
1604 * @mbx: Pointer to mailbox information structure
1605 *
1606 * This handler configures the lport mapping based on the reply from the
1607 * switch API.
1608 **/
1609s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,
1610 struct fm10k_mbx_info *mbx)
1611{
1612 u16 glort, mask;
1613 u32 dglort_map;
1614 s32 err;
1615
1616 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],
1617 &dglort_map);
1618 if (err)
1619 return err;
1620
1621 /* extract values out of the header */
1622 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);
1623 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);
1624
1625 /* verify mask is set and none of the masked bits in glort are set */
1626 if (!mask || (glort & ~mask))
1627 return FM10K_ERR_PARAM;
1628
1629 /* verify the mask is contiguous, and that it is 1's followed by 0's */
1630 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)
1631 return FM10K_ERR_PARAM;
1632
1633 /* record the glort, mask, and port count */
1634 hw->mac.dglort_map = dglort_map;
1635
1636 return 0;
1637}
1638
1639const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {
1640 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),
1641 FM10K_TLV_ATTR_LAST
1642};
1643
1644/**
1645 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1646 * @hw: Pointer to hardware structure
1647 * @results: pointer array containing parsed data
1648 * @mbx: Pointer to mailbox information structure
1649 *
1650 * This handler configures the default VLAN for the PF
1651 **/
1652s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,
1653 struct fm10k_mbx_info *mbx)
1654{
1655 u16 glort, pvid;
1656 u32 pvid_update;
1657 s32 err;
1658
1659 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1660 &pvid_update);
1661 if (err)
1662 return err;
1663
1664 /* extract values from the pvid update */
1665 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1666 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1667
1668 /* if glort is not valid return error */
1669 if (!fm10k_glort_valid_pf(hw, glort))
1670 return FM10K_ERR_PARAM;
1671
1672 /* verify VID is valid */
1673 if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1674 return FM10K_ERR_PARAM;
1675
1676 /* record the port VLAN ID value */
1677 hw->mac.default_vid = pvid;
1678
1679 return 0;
1680}
1681
1682/**
1683 * fm10k_record_global_table_data - Move global table data to swapi table info
1684 * @from: pointer to source table data structure
1685 * @to: pointer to destination table info structure
1686 *
1687 * This function is will copy table_data to the table_info contained in
1688 * the hw struct.
1689 **/
1690static void fm10k_record_global_table_data(struct fm10k_global_table_data *from,
1691 struct fm10k_swapi_table_info *to)
1692{
1693 /* convert from le32 struct to CPU byte ordered values */
1694 to->used = le32_to_cpu(from->used);
1695 to->avail = le32_to_cpu(from->avail);
1696}
1697
1698const struct fm10k_tlv_attr fm10k_err_msg_attr[] = {
1699 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1700 sizeof(struct fm10k_swapi_error)),
1701 FM10K_TLV_ATTR_LAST
1702};
1703
1704/**
1705 * fm10k_msg_err_pf - Message handler for error reply
1706 * @hw: Pointer to hardware structure
1707 * @results: pointer array containing parsed data
1708 * @mbx: Pointer to mailbox information structure
1709 *
1710 * This handler will capture the data for any error replies to previous
1711 * messages that the PF has sent.
1712 **/
1713s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,
1714 struct fm10k_mbx_info *mbx)
1715{
1716 struct fm10k_swapi_error err_msg;
1717 s32 err;
1718
1719 /* extract structure from message */
1720 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],
1721 &err_msg, sizeof(err_msg));
1722 if (err)
1723 return err;
1724
1725 /* record table status */
1726 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);
1727 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);
1728 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);
1729
1730 /* record SW API status value */
1731 hw->swapi.status = le32_to_cpu(err_msg.status);
1732
1733 return 0;
1734}
1735
5f226ddb
AD		 1736const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = {
1737 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP,
1738 sizeof(struct fm10k_swapi_1588_timestamp)),
1739 FM10K_TLV_ATTR_LAST
1740};
1741
1742/* currently there is no shared 1588 timestamp handler */
1743
1744/**
1745 * fm10k_adjust_systime_pf - Adjust systime frequency
1746 * @hw: pointer to hardware structure
1747 * @ppb: adjustment rate in parts per billion
1748 *
1749 * This function will adjust the SYSTIME_CFG register contained in BAR 4
1750 * if this function is supported for BAR 4 access. The adjustment amount
1751 * is based on the parts per billion value provided and adjusted to a
1752 * value based on parts per 2^48 clock cycles.
1753 *
1754 * If adjustment is not supported or the requested value is too large
1755 * we will return an error.
1756 **/
1757static s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb)
1758{
1759 u64 systime_adjust;
1760
1761 /* if sw_addr is not set we don't have switch register access */
1762 if (!hw->sw_addr)
1763 return ppb ? FM10K_ERR_PARAM : 0;
1764
1765 /* we must convert the value from parts per billion to parts per
1766 * 2^48 cycles. In addition I have opted to only use the 30 most
1767 * significant bits of the adjustment value as the 8 least
1768 * significant bits are located in another register and represent
1769 * a value significantly less than a part per billion, the result
1770 * of dropping the 8 least significant bits is that the adjustment
1771 * value is effectively multiplied by 2^8 when we write it.
1772 *
1773 * As a result of all this the math for this breaks down as follows:
1774 * ppb / 10^9 == adjust * 2^8 / 2^48
1775 * If we solve this for adjust, and simplify it comes out as:
1776 * ppb * 2^31 / 5^9 == adjust
1777 */
1778 systime_adjust = (ppb < 0) ? -ppb : ppb;
1779 systime_adjust <<= 31;
1780 do_div(systime_adjust, 1953125);
1781
1782 /* verify the requested adjustment value is in range */
1783 if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK)
1784 return FM10K_ERR_PARAM;
1785
1786 if (ppb < 0)
1787 systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_NEGATIVE;
1788
1789 fm10k_write_sw_reg(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust);
1790
1791 return 0;
1792}
1793
1794/**
1795 * fm10k_read_systime_pf - Reads value of systime registers
1796 * @hw: pointer to the hardware structure
1797 *
1798 * Function reads the content of 2 registers, combined to represent a 64 bit
1799 * value measured in nanosecods. In order to guarantee the value is accurate
1800 * we check the 32 most significant bits both before and after reading the
1801 * 32 least significant bits to verify they didn't change as we were reading
1802 * the registers.
1803 **/
1804static u64 fm10k_read_systime_pf(struct fm10k_hw *hw)
1805{
1806 u32 systime_l, systime_h, systime_tmp;
1807
1808 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1809
1810 do {
1811 systime_tmp = systime_h;
1812 systime_l = fm10k_read_reg(hw, FM10K_SYSTIME);
1813 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1814 } while (systime_tmp != systime_h);
1815
1816 return ((u64)systime_h << 32) | systime_l;
1817}
1818
401b5383
AD		 1819static const struct fm10k_msg_data fm10k_msg_data_pf[] = {
1820 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1821 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1822 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),
1823 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1824 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1825 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),
1826 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1827};
1828
b6fec18f
AD		 1829static struct fm10k_mac_ops mac_ops_pf = {
1830 .get_bus_info = &fm10k_get_bus_info_generic,
1831 .reset_hw = &fm10k_reset_hw_pf,
1832 .init_hw = &fm10k_init_hw_pf,
1833 .start_hw = &fm10k_start_hw_generic,
1834 .stop_hw = &fm10k_stop_hw_generic,
1835 .is_slot_appropriate = &fm10k_is_slot_appropriate_pf,
401b5383 1836 .update_vlan = &fm10k_update_vlan_pf,
b6fec18f 1837 .read_mac_addr = &fm10k_read_mac_addr_pf,
401b5383
AD		 1838 .update_uc_addr = &fm10k_update_uc_addr_pf,
1839 .update_mc_addr = &fm10k_update_mc_addr_pf,
1840 .update_xcast_mode = &fm10k_update_xcast_mode_pf,
1841 .update_int_moderator = &fm10k_update_int_moderator_pf,
1842 .update_lport_state = &fm10k_update_lport_state_pf,
b6fec18f
AD		 1843 .update_hw_stats = &fm10k_update_hw_stats_pf,
1844 .rebind_hw_stats = &fm10k_rebind_hw_stats_pf,
401b5383
AD		 1845 .configure_dglort_map = &fm10k_configure_dglort_map_pf,
1846 .set_dma_mask = &fm10k_set_dma_mask_pf,
b6fec18f 1847 .get_fault = &fm10k_get_fault_pf,
401b5383 1848 .get_host_state = &fm10k_get_host_state_pf,
5f226ddb
AD		 1849 .adjust_systime = &fm10k_adjust_systime_pf,
1850 .read_systime = &fm10k_read_systime_pf,
b6fec18f
AD		 1851};
1852
c2653865
AD		 1853static struct fm10k_iov_ops iov_ops_pf = {
1854 .assign_resources = &fm10k_iov_assign_resources_pf,
1855 .configure_tc = &fm10k_iov_configure_tc_pf,
1856 .assign_int_moderator = &fm10k_iov_assign_int_moderator_pf,
1857 .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf,
1858 .reset_resources = &fm10k_iov_reset_resources_pf,
1859 .set_lport = &fm10k_iov_set_lport_pf,
1860 .reset_lport = &fm10k_iov_reset_lport_pf,
1861 .update_stats = &fm10k_iov_update_stats_pf,
5f226ddb 1862 .report_timestamp = &fm10k_iov_report_timestamp_pf,
c2653865
AD		 1863};
1864
401b5383
AD		 1865static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw)
1866{
1867 fm10k_get_invariants_generic(hw);
1868
1869 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);
1870}
1871
b6fec18f
AD		 1872struct fm10k_info fm10k_pf_info = {
1873 .mac = fm10k_mac_pf,
401b5383 1874 .get_invariants = &fm10k_get_invariants_pf,
b6fec18f 1875 .mac_ops = &mac_ops_pf,
c2653865 1876 .iov_ops = &iov_ops_pf,
b6fec18f 1877};
Linux 6.x block layer and io_uring tree(s)