[linux-2.6-block.git] / drivers / net / ethernet / intel / e1000e / ptp.c

// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 1999 - 2018 Intel Corporation. */

/* PTP 1588 Hardware Clock (PHC)
 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
 */

#include "e1000.h"

#ifdef CONFIG_E1000E_HWTS
#include <linux/clocksource.h>
#include <linux/ktime.h>
#include <asm/tsc.h>
#endif

/**
 * e1000e_phc_adjfreq - adjust the frequency of the hardware clock
 * @ptp: ptp clock structure
 * @delta: Desired frequency change in parts per billion
 *
 * Adjust the frequency of the PHC cycle counter by the indicated delta from
 * the base frequency.
 **/
static int e1000e_phc_adjfreq(struct ptp_clock_info *ptp, s32 delta)
{
	struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
						     ptp_clock_info);
	struct e1000_hw *hw = &adapter->hw;
	bool neg_adj = false;
	unsigned long flags;
	u64 adjustment;
	u32 timinca, incvalue;
	s32 ret_val;

	if ((delta > ptp->max_adj) || (delta <= -1000000000))
		return -EINVAL;

	if (delta < 0) {
		neg_adj = true;
		delta = -delta;
	}

	/* Get the System Time Register SYSTIM base frequency */
	ret_val = e1000e_get_base_timinca(adapter, &timinca);
	if (ret_val)
		return ret_val;

	spin_lock_irqsave(&adapter->systim_lock, flags);

	incvalue = timinca & E1000_TIMINCA_INCVALUE_MASK;

	adjustment = incvalue;
	adjustment *= delta;
	adjustment = div_u64(adjustment, 1000000000);

	incvalue = neg_adj ? (incvalue - adjustment) : (incvalue + adjustment);

	timinca &= ~E1000_TIMINCA_INCVALUE_MASK;
	timinca |= incvalue;

	ew32(TIMINCA, timinca);

	adapter->ptp_delta = delta;

	spin_unlock_irqrestore(&adapter->systim_lock, flags);

	return 0;
}

/**
 * e1000e_phc_adjtime - Shift the time of the hardware clock
 * @ptp: ptp clock structure
 * @delta: Desired change in nanoseconds
 *
 * Adjust the timer by resetting the timecounter structure.
 **/
static int e1000e_phc_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
	struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
						     ptp_clock_info);
	unsigned long flags;

	spin_lock_irqsave(&adapter->systim_lock, flags);
	timecounter_adjtime(&adapter->tc, delta);
	spin_unlock_irqrestore(&adapter->systim_lock, flags);

	return 0;
}

#ifdef CONFIG_E1000E_HWTS
#define MAX_HW_WAIT_COUNT (3)

/**
 * e1000e_phc_get_syncdevicetime - Callback given to timekeeping code reads system/device registers
 * @device: current device time
 * @system: system counter value read synchronously with device time
 * @ctx: context provided by timekeeping code
 *
 * Read device and system (ART) clock simultaneously and return the corrected
 * clock values in ns.
 **/
static int e1000e_phc_get_syncdevicetime(ktime_t *device,
					 struct system_counterval_t *system,
					 void *ctx)
{
	struct e1000_adapter *adapter = (struct e1000_adapter *)ctx;
	struct e1000_hw *hw = &adapter->hw;
	unsigned long flags;
	int i;
	u32 tsync_ctrl;
	u64 dev_cycles;
	u64 sys_cycles;

	tsync_ctrl = er32(TSYNCTXCTL);
	tsync_ctrl |= E1000_TSYNCTXCTL_START_SYNC |
		E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK;
	ew32(TSYNCTXCTL, tsync_ctrl);
	for (i = 0; i < MAX_HW_WAIT_COUNT; ++i) {
		udelay(1);
		tsync_ctrl = er32(TSYNCTXCTL);
		if (tsync_ctrl & E1000_TSYNCTXCTL_SYNC_COMP)
			break;
	}

	if (i == MAX_HW_WAIT_COUNT)
		return -ETIMEDOUT;

	dev_cycles = er32(SYSSTMPH);
	dev_cycles <<= 32;
	dev_cycles |= er32(SYSSTMPL);
	spin_lock_irqsave(&adapter->systim_lock, flags);
	*device = ns_to_ktime(timecounter_cyc2time(&adapter->tc, dev_cycles));
	spin_unlock_irqrestore(&adapter->systim_lock, flags);

	sys_cycles = er32(PLTSTMPH);
	sys_cycles <<= 32;
	sys_cycles |= er32(PLTSTMPL);
	*system = convert_art_to_tsc(sys_cycles);

	return 0;
}

/**
 * e1000e_phc_getsynctime - Reads the current system/device cross timestamp
 * @ptp: ptp clock structure
 * @cts: structure containing timestamp
 *
 * Read device and system (ART) clock simultaneously and return the scaled
 * clock values in ns.
 **/
static int e1000e_phc_getcrosststamp(struct ptp_clock_info *ptp,
				     struct system_device_crosststamp *xtstamp)
{
	struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
						     ptp_clock_info);

	return get_device_system_crosststamp(e1000e_phc_get_syncdevicetime,
						adapter, NULL, xtstamp);
}
#endif/*CONFIG_E1000E_HWTS*/

/**
 * e1000e_phc_gettimex - Reads the current time from the hardware clock and
 *                       system clock
 * @ptp: ptp clock structure
 * @ts: timespec structure to hold the current PHC time
 * @sts: structure to hold the current system time
 *
 * Read the timecounter and return the correct value in ns after converting
 * it into a struct timespec.
 **/
static int e1000e_phc_gettimex(struct ptp_clock_info *ptp,
			       struct timespec64 *ts,
			       struct ptp_system_timestamp *sts)
{
	struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
						     ptp_clock_info);
	unsigned long flags;
	u64 cycles, ns;

	spin_lock_irqsave(&adapter->systim_lock, flags);

	/* NOTE: Non-monotonic SYSTIM readings may be returned */
	cycles = e1000e_read_systim(adapter, sts);
	ns = timecounter_cyc2time(&adapter->tc, cycles);

	spin_unlock_irqrestore(&adapter->systim_lock, flags);

	*ts = ns_to_timespec64(ns);

	return 0;
}

/**
 * e1000e_phc_settime - Set the current time on the hardware clock
 * @ptp: ptp clock structure
 * @ts: timespec containing the new time for the cycle counter
 *
 * Reset the timecounter to use a new base value instead of the kernel
 * wall timer value.
 **/
static int e1000e_phc_settime(struct ptp_clock_info *ptp,
			      const struct timespec64 *ts)
{
	struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
						     ptp_clock_info);
	unsigned long flags;
	u64 ns;

	ns = timespec64_to_ns(ts);

	/* reset the timecounter */
	spin_lock_irqsave(&adapter->systim_lock, flags);
	timecounter_init(&adapter->tc, &adapter->cc, ns);
	spin_unlock_irqrestore(&adapter->systim_lock, flags);

	return 0;
}

/**
 * e1000e_phc_enable - enable or disable an ancillary feature
 * @ptp: ptp clock structure
 * @request: Desired resource to enable or disable
 * @on: Caller passes one to enable or zero to disable
 *
 * Enable (or disable) ancillary features of the PHC subsystem.
 * Currently, no ancillary features are supported.
 **/
static int e1000e_phc_enable(struct ptp_clock_info __always_unused *ptp,
			     struct ptp_clock_request __always_unused *request,
			     int __always_unused on)
{
	return -EOPNOTSUPP;
}

static void e1000e_systim_overflow_work(struct work_struct *work)
{
	struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
						     systim_overflow_work.work);
	struct e1000_hw *hw = &adapter->hw;
	struct timespec64 ts;
	u64 ns;

	/* Update the timecounter */
	ns = timecounter_read(&adapter->tc);

	ts = ns_to_timespec64(ns);
	e_dbg("SYSTIM overflow check at %lld.%09lu\n",
	      (long long) ts.tv_sec, ts.tv_nsec);

	schedule_delayed_work(&adapter->systim_overflow_work,
			      E1000_SYSTIM_OVERFLOW_PERIOD);
}

static const struct ptp_clock_info e1000e_ptp_clock_info = {
	.owner		= THIS_MODULE,
	.n_alarm	= 0,
	.n_ext_ts	= 0,
	.n_per_out	= 0,
	.n_pins		= 0,
	.pps		= 0,
	.adjfreq	= e1000e_phc_adjfreq,
	.adjtime	= e1000e_phc_adjtime,
	.gettimex64	= e1000e_phc_gettimex,
	.settime64	= e1000e_phc_settime,
	.enable		= e1000e_phc_enable,
};

/**
 * e1000e_ptp_init - initialize PTP for devices which support it
 * @adapter: board private structure
 *
 * This function performs the required steps for enabling PTP support.
 * If PTP support has already been loaded it simply calls the cyclecounter
 * init routine and exits.
 **/
void e1000e_ptp_init(struct e1000_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;

	adapter->ptp_clock = NULL;

	if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
		return;

	adapter->ptp_clock_info = e1000e_ptp_clock_info;

	snprintf(adapter->ptp_clock_info.name,
		 sizeof(adapter->ptp_clock_info.name), "%pm",
		 adapter->netdev->perm_addr);

	switch (hw->mac.type) {
	case e1000_pch2lan:
	case e1000_pch_lpt:
	case e1000_pch_spt:
	case e1000_pch_cnp:
		/* fall-through */
	case e1000_pch_tgp:
		if ((hw->mac.type < e1000_pch_lpt) ||
		    (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
			adapter->ptp_clock_info.max_adj = 24000000 - 1;
			break;
		}
		/* fall-through */
	case e1000_82574:
	case e1000_82583:
		adapter->ptp_clock_info.max_adj = 600000000 - 1;
		break;
	default:
		break;
	}

#ifdef CONFIG_E1000E_HWTS
	/* CPU must have ART and GBe must be from Sunrise Point or greater */
	if (hw->mac.type >= e1000_pch_spt && boot_cpu_has(X86_FEATURE_ART))
		adapter->ptp_clock_info.getcrosststamp =
			e1000e_phc_getcrosststamp;
#endif/*CONFIG_E1000E_HWTS*/

	INIT_DELAYED_WORK(&adapter->systim_overflow_work,
			  e1000e_systim_overflow_work);

	schedule_delayed_work(&adapter->systim_overflow_work,
			      E1000_SYSTIM_OVERFLOW_PERIOD);

	adapter->ptp_clock = ptp_clock_register(&adapter->ptp_clock_info,
						&adapter->pdev->dev);
	if (IS_ERR(adapter->ptp_clock)) {
		adapter->ptp_clock = NULL;
		e_err("ptp_clock_register failed\n");
	} else if (adapter->ptp_clock) {
		e_info("registered PHC clock\n");
	}
}

/**
 * e1000e_ptp_remove - disable PTP device and stop the overflow check
 * @adapter: board private structure
 *
 * Stop the PTP support, and cancel the delayed work.
 **/
void e1000e_ptp_remove(struct e1000_adapter *adapter)
{
	if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
		return;

	cancel_delayed_work_sync(&adapter->systim_overflow_work);

	if (adapter->ptp_clock) {
		ptp_clock_unregister(adapter->ptp_clock);
		adapter->ptp_clock = NULL;
		e_info("removed PHC\n");
	}
}
Commit	Line	Data
ae06c70b	1	// SPDX-License-Identifier: GPL-2.0
51dce24b	2	/* Copyright(c) 1999 - 2018 Intel Corporation. */
d89777bf BA	3
	4	/* PTP 1588 Hardware Clock (PHC)
	5	* Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
	6	* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
	7	*/
	8
	9	#include "e1000.h"
	10
01d7ada5 CH	11	#ifdef CONFIG_E1000E_HWTS
	12	#include <linux/clocksource.h>
	13	#include <linux/ktime.h>
	14	#include <asm/tsc.h>
	15	#endif
	16
d89777bf BA	17	/**
	18	* e1000e_phc_adjfreq - adjust the frequency of the hardware clock
	19	* @ptp: ptp clock structure
	20	* @delta: Desired frequency change in parts per billion
	21	*
	22	* Adjust the frequency of the PHC cycle counter by the indicated delta from
	23	* the base frequency.
	24	**/
	25	static int e1000e_phc_adjfreq(struct ptp_clock_info *ptp, s32 delta)
	26	{
	27	struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
	28	ptp_clock_info);
	29	struct e1000_hw *hw = &adapter->hw;
	30	bool neg_adj = false;
6c2ed39c	31	unsigned long flags;
d89777bf BA	32	u64 adjustment;
	33	u32 timinca, incvalue;
	34	s32 ret_val;
	35
	36	if ((delta > ptp->max_adj) \|\| (delta <= -1000000000))
	37	return -EINVAL;
	38
	39	if (delta < 0) {
	40	neg_adj = true;
	41	delta = -delta;
	42	}
	43
	44	/* Get the System Time Register SYSTIM base frequency */
	45	ret_val = e1000e_get_base_timinca(adapter, &timinca);
	46	if (ret_val)
	47	return ret_val;
	48
6c2ed39c TF	49	spin_lock_irqsave(&adapter->systim_lock, flags);
6c2ed39c TF	50
d89777bf BA	51	incvalue = timinca & E1000_TIMINCA_INCVALUE_MASK;
	52
	53	adjustment = incvalue;
	54	adjustment *= delta;
	55	adjustment = div_u64(adjustment, 1000000000);
	56
	57	incvalue = neg_adj ? (incvalue - adjustment) : (incvalue + adjustment);
	58
	59	timinca &= ~E1000_TIMINCA_INCVALUE_MASK;
	60	timinca \|= incvalue;
	61
	62	ew32(TIMINCA, timinca);
	63
aa524b66 JK	64	adapter->ptp_delta = delta;
aa524b66 JK	65
6c2ed39c TF	66	spin_unlock_irqrestore(&adapter->systim_lock, flags);
6c2ed39c TF	67
d89777bf BA	68	return 0;
	69	}
	70
	71	/**
	72	* e1000e_phc_adjtime - Shift the time of the hardware clock
	73	* @ptp: ptp clock structure
	74	* @delta: Desired change in nanoseconds
	75	*
	76	* Adjust the timer by resetting the timecounter structure.
	77	**/
	78	static int e1000e_phc_adjtime(struct ptp_clock_info *ptp, s64 delta)
	79	{
	80	struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
	81	ptp_clock_info);
	82	unsigned long flags;
d89777bf BA	83
d89777bf BA	84	spin_lock_irqsave(&adapter->systim_lock, flags);
f4de2b95	85	timecounter_adjtime(&adapter->tc, delta);
d89777bf BA	86	spin_unlock_irqrestore(&adapter->systim_lock, flags);
	87
	88	return 0;
	89	}
	90
01d7ada5 CH	91	#ifdef CONFIG_E1000E_HWTS
	92	#define MAX_HW_WAIT_COUNT (3)
	93
	94	/**
	95	* e1000e_phc_get_syncdevicetime - Callback given to timekeeping code reads system/device registers
	96	* @device: current device time
	97	* @system: system counter value read synchronously with device time
	98	* @ctx: context provided by timekeeping code
	99	*
	100	* Read device and system (ART) clock simultaneously and return the corrected
	101	* clock values in ns.
	102	**/
	103	static int e1000e_phc_get_syncdevicetime(ktime_t *device,
	104	struct system_counterval_t *system,
	105	void *ctx)
	106	{
	107	struct e1000_adapter adapter = (struct e1000_adapter )ctx;
	108	struct e1000_hw *hw = &adapter->hw;
	109	unsigned long flags;
	110	int i;
	111	u32 tsync_ctrl;
a5a1d1c2 TG	112	u64 dev_cycles;
a5a1d1c2 TG	113	u64 sys_cycles;
01d7ada5 CH	114
	115	tsync_ctrl = er32(TSYNCTXCTL);
	116	tsync_ctrl \|= E1000_TSYNCTXCTL_START_SYNC \|
	117	E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK;
	118	ew32(TSYNCTXCTL, tsync_ctrl);
	119	for (i = 0; i < MAX_HW_WAIT_COUNT; ++i) {
	120	udelay(1);
	121	tsync_ctrl = er32(TSYNCTXCTL);
	122	if (tsync_ctrl & E1000_TSYNCTXCTL_SYNC_COMP)
	123	break;
	124	}
	125
	126	if (i == MAX_HW_WAIT_COUNT)
	127	return -ETIMEDOUT;
	128
	129	dev_cycles = er32(SYSSTMPH);
	130	dev_cycles <<= 32;
	131	dev_cycles \|= er32(SYSSTMPL);
	132	spin_lock_irqsave(&adapter->systim_lock, flags);
	133	*device = ns_to_ktime(timecounter_cyc2time(&adapter->tc, dev_cycles));
	134	spin_unlock_irqrestore(&adapter->systim_lock, flags);
	135
	136	sys_cycles = er32(PLTSTMPH);
	137	sys_cycles <<= 32;
	138	sys_cycles \|= er32(PLTSTMPL);
	139	*system = convert_art_to_tsc(sys_cycles);
	140
	141	return 0;
	142	}
	143
	144	/**
	145	* e1000e_phc_getsynctime - Reads the current system/device cross timestamp
	146	* @ptp: ptp clock structure
	147	* @cts: structure containing timestamp
	148	*
	149	* Read device and system (ART) clock simultaneously and return the scaled
	150	* clock values in ns.
	151	**/
	152	static int e1000e_phc_getcrosststamp(struct ptp_clock_info *ptp,
	153	struct system_device_crosststamp *xtstamp)
	154	{
	155	struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
	156	ptp_clock_info);
	157
	158	return get_device_system_crosststamp(e1000e_phc_get_syncdevicetime,
	159	adapter, NULL, xtstamp);
	160	}
	161	#endif/CONFIG_E1000E_HWTS/
	162
d89777bf	163	/**
98942d70 ML	164	* e1000e_phc_gettimex - Reads the current time from the hardware clock and
98942d70 ML	165	* system clock
d89777bf	166	* @ptp: ptp clock structure
98942d70 ML	167	* @ts: timespec structure to hold the current PHC time
98942d70 ML	168	* @sts: structure to hold the current system time
d89777bf BA	169	*
	170	* Read the timecounter and return the correct value in ns after converting
	171	* it into a struct timespec.
	172	**/
98942d70 ML	173	static int e1000e_phc_gettimex(struct ptp_clock_info *ptp,
	174	struct timespec64 *ts,
	175	struct ptp_system_timestamp *sts)
d89777bf BA	176	{
	177	struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
	178	ptp_clock_info);
	179	unsigned long flags;
e1f65b0d	180	u64 cycles, ns;
d89777bf BA	181
d89777bf BA	182	spin_lock_irqsave(&adapter->systim_lock, flags);
e1f65b0d	183
98942d70 ML	184	/* NOTE: Non-monotonic SYSTIM readings may be returned */
98942d70 ML	185	cycles = e1000e_read_systim(adapter, sts);
e1f65b0d ML	186	ns = timecounter_cyc2time(&adapter->tc, cycles);
e1f65b0d ML	187
d89777bf BA	188	spin_unlock_irqrestore(&adapter->systim_lock, flags);
d89777bf BA	189
bdf36d94	190	*ts = ns_to_timespec64(ns);
d89777bf BA	191
	192	return 0;
	193	}
	194
	195	/**
	196	* e1000e_phc_settime - Set the current time on the hardware clock
	197	* @ptp: ptp clock structure
	198	* @ts: timespec containing the new time for the cycle counter
	199	*
	200	* Reset the timecounter to use a new base value instead of the kernel
	201	* wall timer value.
	202	**/
	203	static int e1000e_phc_settime(struct ptp_clock_info *ptp,
07c74eb7	204	const struct timespec64 *ts)
d89777bf BA	205	{
	206	struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,
	207	ptp_clock_info);
	208	unsigned long flags;
	209	u64 ns;
	210
07c74eb7	211	ns = timespec64_to_ns(ts);
d89777bf BA	212
	213	/* reset the timecounter */
	214	spin_lock_irqsave(&adapter->systim_lock, flags);
	215	timecounter_init(&adapter->tc, &adapter->cc, ns);
	216	spin_unlock_irqrestore(&adapter->systim_lock, flags);
	217
	218	return 0;
	219	}
	220
	221	/**
	222	* e1000e_phc_enable - enable or disable an ancillary feature
	223	* @ptp: ptp clock structure
	224	* @request: Desired resource to enable or disable
	225	* @on: Caller passes one to enable or zero to disable
	226	*
	227	* Enable (or disable) ancillary features of the PHC subsystem.
	228	* Currently, no ancillary features are supported.
	229	**/
8bb62869 BA	230	static int e1000e_phc_enable(struct ptp_clock_info __always_unused *ptp,
	231	struct ptp_clock_request __always_unused *request,
	232	int __always_unused on)
d89777bf BA	233	{
	234	return -EOPNOTSUPP;
	235	}
	236
	237	static void e1000e_systim_overflow_work(struct work_struct *work)
	238	{
	239	struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
	240	systim_overflow_work.work);
	241	struct e1000_hw *hw = &adapter->hw;
07c74eb7	242	struct timespec64 ts;
e1f65b0d	243	u64 ns;
d89777bf	244
e1f65b0d ML	245	/* Update the timecounter */
e1f65b0d ML	246	ns = timecounter_read(&adapter->tc);
d89777bf	247
e1f65b0d	248	ts = ns_to_timespec64(ns);
32eaf120 DM	249	e_dbg("SYSTIM overflow check at %lld.%09lu\n",
32eaf120 DM	250	(long long) ts.tv_sec, ts.tv_nsec);
d89777bf BA	251
	252	schedule_delayed_work(&adapter->systim_overflow_work,
	253	E1000_SYSTIM_OVERFLOW_PERIOD);
	254	}
	255
	256	static const struct ptp_clock_info e1000e_ptp_clock_info = {
	257	.owner = THIS_MODULE,
	258	.n_alarm = 0,
	259	.n_ext_ts = 0,
	260	.n_per_out = 0,
4986b4f0	261	.n_pins = 0,
d89777bf BA	262	.pps = 0,
	263	.adjfreq = e1000e_phc_adjfreq,
	264	.adjtime = e1000e_phc_adjtime,
98942d70	265	.gettimex64 = e1000e_phc_gettimex,
07c74eb7	266	.settime64 = e1000e_phc_settime,
d89777bf BA	267	.enable = e1000e_phc_enable,
	268	};
	269
	270	/**
	271	* e1000e_ptp_init - initialize PTP for devices which support it
	272	* @adapter: board private structure
	273	*
	274	* This function performs the required steps for enabling PTP support.
	275	* If PTP support has already been loaded it simply calls the cyclecounter
	276	* init routine and exits.
	277	**/
	278	void e1000e_ptp_init(struct e1000_adapter *adapter)
	279	{
	280	struct e1000_hw *hw = &adapter->hw;
	281
	282	adapter->ptp_clock = NULL;
	283
	284	if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
	285	return;
	286
	287	adapter->ptp_clock_info = e1000e_ptp_clock_info;
	288
	289	snprintf(adapter->ptp_clock_info.name,
	290	sizeof(adapter->ptp_clock_info.name), "%pm",
	291	adapter->netdev->perm_addr);
	292
	293	switch (hw->mac.type) {
	294	case e1000_pch2lan:
	295	case e1000_pch_lpt:
79849ebc	296	case e1000_pch_spt:
c8744f44	297	case e1000_pch_cnp:
fb776f5d SN	298	/* fall-through */
fb776f5d SN	299	case e1000_pch_tgp:
c8744f44	300	if ((hw->mac.type < e1000_pch_lpt) \|\|
d89777bf BA	301	(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
	302	adapter->ptp_clock_info.max_adj = 24000000 - 1;
	303	break;
	304	}
	305	/* fall-through */
	306	case e1000_82574:
	307	case e1000_82583:
	308	adapter->ptp_clock_info.max_adj = 600000000 - 1;
	309	break;
	310	default:
	311	break;
	312	}
	313
01d7ada5 CH	314	#ifdef CONFIG_E1000E_HWTS
	315	/* CPU must have ART and GBe must be from Sunrise Point or greater */
	316	if (hw->mac.type >= e1000_pch_spt && boot_cpu_has(X86_FEATURE_ART))
	317	adapter->ptp_clock_info.getcrosststamp =
	318	e1000e_phc_getcrosststamp;
	319	#endif/CONFIG_E1000E_HWTS/
	320
d89777bf BA	321	INIT_DELAYED_WORK(&adapter->systim_overflow_work,
	322	e1000e_systim_overflow_work);
	323
	324	schedule_delayed_work(&adapter->systim_overflow_work,
	325	E1000_SYSTIM_OVERFLOW_PERIOD);
	326
	327	adapter->ptp_clock = ptp_clock_register(&adapter->ptp_clock_info,
	328	&adapter->pdev->dev);
	329	if (IS_ERR(adapter->ptp_clock)) {
	330	adapter->ptp_clock = NULL;
	331	e_err("ptp_clock_register failed\n");
efee95f4	332	} else if (adapter->ptp_clock) {
d89777bf BA	333	e_info("registered PHC clock\n");
	334	}
	335	}
	336
	337	/**
	338	* e1000e_ptp_remove - disable PTP device and stop the overflow check
	339	* @adapter: board private structure
	340	*
	341	* Stop the PTP support, and cancel the delayed work.
	342	**/
	343	void e1000e_ptp_remove(struct e1000_adapter *adapter)
	344	{
	345	if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
	346	return;
	347
	348	cancel_delayed_work_sync(&adapter->systim_overflow_work);
	349
	350	if (adapter->ptp_clock) {
	351	ptp_clock_unregister(adapter->ptp_clock);
	352	adapter->ptp_clock = NULL;
	353	e_info("removed PHC\n");
	354	}
	355	}