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e1000e: add support for IEEE-1588 PTP
[linux-2.6-block.git] / drivers / net / ethernet / intel / e1000e / e1000.h
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _E1000_H_
32#define _E1000_H_
33
86d70e53 34#include <linux/bitops.h>
bc7f75fa
AK		 35#include <linux/types.h>
36#include <linux/timer.h>
37#include <linux/workqueue.h>
38#include <linux/io.h>
39#include <linux/netdevice.h>
d8014dbc 40#include <linux/pci.h>
6f461f6c 41#include <linux/pci-aspm.h>
fe46f58f 42#include <linux/crc32.h>
86d70e53 43#include <linux/if_vlan.h>
b67e1913
BA		 44#include <linux/clocksource.h>
45#include <linux/net_tstamp.h>
d89777bf
BA		 46#include <linux/ptp_clock_kernel.h>
47#include <linux/ptp_classify.h>
bc7f75fa
AK		 48#include "hw.h"
49
50struct e1000_info;
51
44defeb3 52#define e_dbg(format, arg...) \
8544b9f7 53 netdev_dbg(hw->adapter->netdev, format, ## arg)
44defeb3 54#define e_err(format, arg...) \
8544b9f7 55 netdev_err(adapter->netdev, format, ## arg)
44defeb3 56#define e_info(format, arg...) \
8544b9f7 57 netdev_info(adapter->netdev, format, ## arg)
44defeb3 58#define e_warn(format, arg...) \
8544b9f7 59 netdev_warn(adapter->netdev, format, ## arg)
44defeb3 60#define e_notice(format, arg...) \
8544b9f7 61 netdev_notice(adapter->netdev, format, ## arg)
bc7f75fa
AK		 62
63
98a1708d 64/* Interrupt modes, as used by the IntMode parameter */
4662e82b
BA		 65#define E1000E_INT_MODE_LEGACY 0
66#define E1000E_INT_MODE_MSI 1
67#define E1000E_INT_MODE_MSIX 2
68
ad68076e 69/* Tx/Rx descriptor defines */
bc7f75fa
AK		 70#define E1000_DEFAULT_TXD 256
71#define E1000_MAX_TXD 4096
7b1be198 72#define E1000_MIN_TXD 64
bc7f75fa
AK		 73
74#define E1000_DEFAULT_RXD 256
75#define E1000_MAX_RXD 4096
7b1be198 76#define E1000_MIN_RXD 64
bc7f75fa 77
de5b3077
AK		 78#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
79#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
80
bc7f75fa
AK		 81/* Early Receive defines */
82#define E1000_ERT_2048 0x100
83
84#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
85
86/* How many Tx Descriptors do we need to call netif_wake_queue ? */
87/* How many Rx Buffers do we bundle into one write to the hardware ? */
88#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
89
90#define AUTO_ALL_MODES 0
91#define E1000_EEPROM_APME 0x0400
92
93#define E1000_MNG_VLAN_NONE (-1)
94
95/* Number of packet split data buffers (not including the header buffer) */
96#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
97
2adc55c9
BA		 98#define DEFAULT_JUMBO 9234
99
a4f58f54
BA		 100/* BM/HV Specific Registers */
101#define BM_PORT_CTRL_PAGE 769
102
103#define PHY_UPPER_SHIFT 21
104#define BM_PHY_REG(page, reg) \
105 (((reg) & MAX_PHY_REG_ADDRESS) |\
106 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
107 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
108
109/* PHY Wakeup Registers and defines */
3ebfc7c9 110#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
a4f58f54
BA		 111#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
112#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
113#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
114#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
115#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
116#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
117#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
118#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
119#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
120
121#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
122#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
123#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
124#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
125#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
126#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
127#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
128
2b6b168d
BA		 129#define HV_STATS_PAGE 778
130#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
131#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
132#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
133#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
134#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
135#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
136#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
137#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
138#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
139#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
140#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
141#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
142#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
143#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
a4f58f54 144
38eb394e
BA		 145#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
146
1d5846b9
BA		 147/* BM PHY Copper Specific Status */
148#define BM_CS_STATUS 17
149#define BM_CS_STATUS_LINK_UP 0x0400
150#define BM_CS_STATUS_RESOLVED 0x0800
151#define BM_CS_STATUS_SPEED_MASK 0xC000
152#define BM_CS_STATUS_SPEED_1000 0x8000
153
154/* 82577 Mobile Phy Status Register */
155#define HV_M_STATUS 26
156#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
157#define HV_M_STATUS_SPEED_MASK 0x0300
158#define HV_M_STATUS_SPEED_1000 0x0200
159#define HV_M_STATUS_LINK_UP 0x0040
160
c6e7f51e
BA		 161#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
162#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
163
23606cf5
RW		 164/* Time to wait before putting the device into D3 if there's no link (in ms). */
165#define LINK_TIMEOUT 100
166
e921eb1a 167/* Count for polling __E1000_RESET condition every 10-20msec.
bb9e44d0
BA		 168 * Experimentation has shown the reset can take approximately 210msec.
169 */
170#define E1000_CHECK_RESET_COUNT 25
171
3a3b7586
JB		 172#define DEFAULT_RDTR 0
173#define DEFAULT_RADV 8
174#define BURST_RDTR 0x20
175#define BURST_RADV 0x20
176
e921eb1a 177/* in the case of WTHRESH, it appears at least the 82571/2 hardware
3a3b7586 178 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
8edc0e62
HS		 179 * WTHRESH=4, so a setting of 5 gives the most efficient bus
180 * utilization but to avoid possible Tx stalls, set it to 1
3a3b7586
JB		 181 */
182#define E1000_TXDCTL_DMA_BURST_ENABLE \
183 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
184 E1000_TXDCTL_COUNT_DESC | \
8edc0e62 185 (1 << 16) | /* wthresh must be +1 more than desired */\
3a3b7586
JB		 186 (1 << 8) | /* hthresh */ \
187 0x1f) /* pthresh */
188
189#define E1000_RXDCTL_DMA_BURST_ENABLE \
190 (0x01000000 | /* set descriptor granularity */ \
191 (4 << 16) | /* set writeback threshold */ \
192 (4 << 8) | /* set prefetch threshold */ \
193 0x20) /* set hthresh */
194
195#define E1000_TIDV_FPD (1 << 31)
196#define E1000_RDTR_FPD (1 << 31)
197
bc7f75fa
AK		 198enum e1000_boards {
199 board_82571,
200 board_82572,
201 board_82573,
4662e82b 202 board_82574,
8c81c9c3 203 board_82583,
bc7f75fa
AK		 204 board_80003es2lan,
205 board_ich8lan,
206 board_ich9lan,
f4187b56 207 board_ich10lan,
a4f58f54 208 board_pchlan,
d3738bb8 209 board_pch2lan,
2fbe4526 210 board_pch_lpt,
bc7f75fa
AK		 211};
212
bc7f75fa
AK		 213struct e1000_ps_page {
214 struct page *page;
215 u64 dma; /* must be u64 - written to hw */
216};
217
e921eb1a 218/* wrappers around a pointer to a socket buffer,
bc7f75fa
AK		 219 * so a DMA handle can be stored along with the buffer
220 */
221struct e1000_buffer {
222 dma_addr_t dma;
223 struct sk_buff *skb;
224 union {
ad68076e 225 /* Tx */
bc7f75fa
AK		 226 struct {
227 unsigned long time_stamp;
228 u16 length;
229 u16 next_to_watch;
9ed318d5
TH		 230 unsigned int segs;
231 unsigned int bytecount;
03b1320d 232 u16 mapped_as_page;
bc7f75fa 233 };
ad68076e 234 /* Rx */
03b1320d
AD		 235 struct {
236 /* arrays of page information for packet split */
237 struct e1000_ps_page *ps_pages;
238 struct page *page;
239 };
bc7f75fa 240 };
bc7f75fa
AK		 241};
242
243struct e1000_ring {
55aa6985 244 struct e1000_adapter *adapter; /* back pointer to adapter */
bc7f75fa
AK		 245 void *desc; /* pointer to ring memory */
246 dma_addr_t dma; /* phys address of ring */
247 unsigned int size; /* length of ring in bytes */
248 unsigned int count; /* number of desc. in ring */
249
250 u16 next_to_use;
251 u16 next_to_clean;
252
c5083cf6
BA		 253 void __iomem *head;
254 void __iomem *tail;
bc7f75fa
AK		 255
256 /* array of buffer information structs */
257 struct e1000_buffer *buffer_info;
258
4662e82b
BA		 259 char name[IFNAMSIZ + 5];
260 u32 ims_val;
261 u32 itr_val;
c5083cf6 262 void __iomem *itr_register;
4662e82b
BA		 263 int set_itr;
264
bc7f75fa 265 struct sk_buff *rx_skb_top;
bc7f75fa
AK		 266};
267
7c25769f
BA		 268/* PHY register snapshot values */
269struct e1000_phy_regs {
270 u16 bmcr; /* basic mode control register */
271 u16 bmsr; /* basic mode status register */
272 u16 advertise; /* auto-negotiation advertisement */
273 u16 lpa; /* link partner ability register */
274 u16 expansion; /* auto-negotiation expansion reg */
275 u16 ctrl1000; /* 1000BASE-T control register */
276 u16 stat1000; /* 1000BASE-T status register */
277 u16 estatus; /* extended status register */
278};
279
bc7f75fa
AK		 280/* board specific private data structure */
281struct e1000_adapter {
282 struct timer_list watchdog_timer;
283 struct timer_list phy_info_timer;
284 struct timer_list blink_timer;
285
286 struct work_struct reset_task;
287 struct work_struct watchdog_task;
288
289 const struct e1000_info *ei;
290
86d70e53 291 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
bc7f75fa
AK		 292 u32 bd_number;
293 u32 rx_buffer_len;
294 u16 mng_vlan_id;
295 u16 link_speed;
296 u16 link_duplex;
84527590 297 u16 eeprom_vers;
bc7f75fa 298
bc7f75fa
AK		 299 /* track device up/down/testing state */
300 unsigned long state;
301
302 /* Interrupt Throttle Rate */
303 u32 itr;
304 u32 itr_setting;
305 u16 tx_itr;
306 u16 rx_itr;
307
e921eb1a 308 /* Tx */
bc7f75fa
AK		 309 struct e1000_ring *tx_ring /* One per active queue */
310 ____cacheline_aligned_in_smp;
d821a4c4 311 u32 tx_fifo_limit;
bc7f75fa
AK		 312
313 struct napi_struct napi;
314
bc7f75fa
AK		 315 unsigned int restart_queue;
316 u32 txd_cmd;
317
318 bool detect_tx_hung;
09357b00 319 bool tx_hang_recheck;
bc7f75fa
AK		 320 u8 tx_timeout_factor;
321
322 u32 tx_int_delay;
323 u32 tx_abs_int_delay;
324
325 unsigned int total_tx_bytes;
326 unsigned int total_tx_packets;
327 unsigned int total_rx_bytes;
328 unsigned int total_rx_packets;
329
ad68076e 330 /* Tx stats */
bc7f75fa
AK		 331 u64 tpt_old;
332 u64 colc_old;
7c25769f
BA		 333 u32 gotc;
334 u64 gotc_old;
bc7f75fa
AK		 335 u32 tx_timeout_count;
336 u32 tx_fifo_head;
337 u32 tx_head_addr;
338 u32 tx_fifo_size;
339 u32 tx_dma_failed;
340
e921eb1a 341 /* Rx */
55aa6985
BA		 342 bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
343 int work_to_do) ____cacheline_aligned_in_smp;
344 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
345 gfp_t gfp);
bc7f75fa
AK		 346 struct e1000_ring *rx_ring;
347
348 u32 rx_int_delay;
349 u32 rx_abs_int_delay;
350
ad68076e 351 /* Rx stats */
bc7f75fa
AK		 352 u64 hw_csum_err;
353 u64 hw_csum_good;
354 u64 rx_hdr_split;
7c25769f
BA		 355 u32 gorc;
356 u64 gorc_old;
bc7f75fa
AK		 357 u32 alloc_rx_buff_failed;
358 u32 rx_dma_failed;
b67e1913 359 u32 rx_hwtstamp_cleared;
bc7f75fa
AK		 360
361 unsigned int rx_ps_pages;
362 u16 rx_ps_bsize0;
318a94d6
JK		 363 u32 max_frame_size;
364 u32 min_frame_size;
bc7f75fa
AK		 365
366 /* OS defined structs */
367 struct net_device *netdev;
368 struct pci_dev *pdev;
bc7f75fa
AK		 369
370 /* structs defined in e1000_hw.h */
371 struct e1000_hw hw;
372
67fd4fcb 373 spinlock_t stats64_lock;
bc7f75fa
AK		 374 struct e1000_hw_stats stats;
375 struct e1000_phy_info phy_info;
376 struct e1000_phy_stats phy_stats;
377
7c25769f
BA		 378 /* Snapshot of PHY registers */
379 struct e1000_phy_regs phy_regs;
380
bc7f75fa
AK		 381 struct e1000_ring test_tx_ring;
382 struct e1000_ring test_rx_ring;
383 u32 test_icr;
384
385 u32 msg_enable;
8e86acd7 386 unsigned int num_vectors;
4662e82b
BA		 387 struct msix_entry *msix_entries;
388 int int_mode;
389 u32 eiac_mask;
bc7f75fa
AK		 390
391 u32 eeprom_wol;
392 u32 wol;
393 u32 pba;
2adc55c9 394 u32 max_hw_frame_size;
bc7f75fa 395
318a94d6 396 bool fc_autoneg;
bc7f75fa 397
bc7f75fa 398 unsigned int flags;
eb7c3adb 399 unsigned int flags2;
a8f88ff5
JB		 400 struct work_struct downshift_task;
401 struct work_struct update_phy_task;
41cec6f1 402 struct work_struct print_hang_task;
23606cf5
RW		 403
404 bool idle_check;
ff10e13c 405 int phy_hang_count;
55aa6985
BA		 406
407 u16 tx_ring_count;
408 u16 rx_ring_count;
b67e1913
BA		 409
410 struct hwtstamp_config hwtstamp_config;
411 struct delayed_work systim_overflow_work;
412 struct sk_buff *tx_hwtstamp_skb;
413 struct work_struct tx_hwtstamp_work;
414 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
415 struct cyclecounter cc;
416 struct timecounter tc;
d89777bf
BA		 417 struct ptp_clock *ptp_clock;
418 struct ptp_clock_info ptp_clock_info;
bc7f75fa
AK		 419};
420
421struct e1000_info {
422 enum e1000_mac_type mac;
423 unsigned int flags;
6f461f6c 424 unsigned int flags2;
bc7f75fa 425 u32 pba;
2adc55c9 426 u32 max_hw_frame_size;
69e3fd8c 427 s32 (*get_variants)(struct e1000_adapter *);
8ce9d6c7
JK		 428 const struct e1000_mac_operations *mac_ops;
429 const struct e1000_phy_operations *phy_ops;
430 const struct e1000_nvm_operations *nvm_ops;
bc7f75fa
AK		 431};
432
d89777bf
BA		 433s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
434
b67e1913
BA		 435/* The system time is maintained by a 64-bit counter comprised of the 32-bit
436 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
437 * its resolution) is based on the contents of the TIMINCA register - it
438 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
439 * For the best accuracy, the incperiod should be as small as possible. The
440 * incvalue is scaled by a factor as large as possible (while still fitting
441 * in bits 23:0) so that relatively small clock corrections can be made.
442 *
443 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
444 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
445 * bits to count nanoseconds leaving the rest for fractional nonseconds.
446 */
447#define INCVALUE_96MHz 125
448#define INCVALUE_SHIFT_96MHz 17
449#define INCPERIOD_SHIFT_96MHz 2
450#define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz)
451
452#define INCVALUE_25MHz 40
453#define INCVALUE_SHIFT_25MHz 18
454#define INCPERIOD_25MHz 1
455
456/* Another drawback of scaling the incvalue by a large factor is the
457 * 64-bit SYSTIM register overflows more quickly. This is dealt with
458 * by simply reading the clock before it overflows.
459 *
460 * Clock ns bits Overflows after
461 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
462 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
463 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
464 */
465#define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
466
bc7f75fa
AK		 467/* hardware capability, feature, and workaround flags */
468#define FLAG_HAS_AMT (1 << 0)
469#define FLAG_HAS_FLASH (1 << 1)
470#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
471#define FLAG_HAS_WOL (1 << 3)
79d4e908 472/* reserved bit4 */
bc7f75fa
AK		 473#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
474#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
475#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
4a770358 476#define FLAG_READ_ONLY_NVM (1 << 8)
97ac8cae 477#define FLAG_IS_ICH (1 << 9)
4662e82b 478#define FLAG_HAS_MSIX (1 << 10)
bc7f75fa
AK		 479#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
480#define FLAG_IS_QUAD_PORT_A (1 << 12)
481#define FLAG_IS_QUAD_PORT (1 << 13)
b67e1913 482#define FLAG_HAS_HW_TIMESTAMP (1 << 14)
bc7f75fa
AK		 483#define FLAG_APME_IN_WUC (1 << 15)
484#define FLAG_APME_IN_CTRL3 (1 << 16)
485#define FLAG_APME_CHECK_PORT_B (1 << 17)
486#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
487#define FLAG_NO_WAKE_UCAST (1 << 19)
488#define FLAG_MNG_PT_ENABLED (1 << 20)
489#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
490#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
491#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
492#define FLAG_RX_NEEDS_RESTART (1 << 24)
493#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
494#define FLAG_SMART_POWER_DOWN (1 << 26)
495#define FLAG_MSI_ENABLED (1 << 27)
dc221294 496/* reserved (1 << 28) */
bc7f75fa 497#define FLAG_TSO_FORCE (1 << 29)
12d43f7d 498#define FLAG_RESTART_NOW (1 << 30)
f8d59f78 499#define FLAG_MSI_TEST_FAILED (1 << 31)
bc7f75fa 500
eb7c3adb 501#define FLAG2_CRC_STRIPPING (1 << 0)
a4f58f54 502#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
b94b5028 503#define FLAG2_IS_DISCARDING (1 << 2)
6f461f6c 504#define FLAG2_DISABLE_ASPM_L1 (1 << 3)
8c7bbb92 505#define FLAG2_HAS_PHY_STATS (1 << 4)
e52997f9 506#define FLAG2_HAS_EEE (1 << 5)
3a3b7586 507#define FLAG2_DMA_BURST (1 << 6)
78cd29d5 508#define FLAG2_DISABLE_ASPM_L0S (1 << 7)
828bac87 509#define FLAG2_DISABLE_AIM (1 << 8)
ff10e13c 510#define FLAG2_CHECK_PHY_HANG (1 << 9)
7f99ae63 511#define FLAG2_NO_DISABLE_RX (1 << 10)
c6e7f51e 512#define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
0184039a 513#define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
b67e1913 514#define FLAG2_CHECK_RX_HWTSTAMP (1 << 13)
eb7c3adb 515
bc7f75fa
AK		 516#define E1000_RX_DESC_PS(R, i) \
517 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
5f450212
BA		 518#define E1000_RX_DESC_EXT(R, i) \
519 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
bc7f75fa 520#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
bc7f75fa
AK		 521#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
522#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
523
524enum e1000_state_t {
525 __E1000_TESTING,
526 __E1000_RESETTING,
a90b412c 527 __E1000_ACCESS_SHARED_RESOURCE,
bc7f75fa
AK		 528 __E1000_DOWN
529};
530
531enum latency_range {
532 lowest_latency = 0,
533 low_latency = 1,
534 bulk_latency = 2,
535 latency_invalid = 255
536};
537
538extern char e1000e_driver_name[];
539extern const char e1000e_driver_version[];
540
541extern void e1000e_check_options(struct e1000_adapter *adapter);
542extern void e1000e_set_ethtool_ops(struct net_device *netdev);
543
544extern int e1000e_up(struct e1000_adapter *adapter);
545extern void e1000e_down(struct e1000_adapter *adapter);
546extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
547extern void e1000e_reset(struct e1000_adapter *adapter);
548extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
55aa6985
BA		 549extern int e1000e_setup_rx_resources(struct e1000_ring *ring);
550extern int e1000e_setup_tx_resources(struct e1000_ring *ring);
551extern void e1000e_free_rx_resources(struct e1000_ring *ring);
552extern void e1000e_free_tx_resources(struct e1000_ring *ring);
67fd4fcb
JK		 553extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
554 struct rtnl_link_stats64
555 *stats);
4662e82b
BA		 556extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
557extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
31dbe5b4
BA		 558extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
559extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
22a4cca2 560extern void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
bc7f75fa
AK		 561
562extern unsigned int copybreak;
563
564extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
565
8ce9d6c7
JK		 566extern const struct e1000_info e1000_82571_info;
567extern const struct e1000_info e1000_82572_info;
568extern const struct e1000_info e1000_82573_info;
569extern const struct e1000_info e1000_82574_info;
570extern const struct e1000_info e1000_82583_info;
571extern const struct e1000_info e1000_ich8_info;
572extern const struct e1000_info e1000_ich9_info;
573extern const struct e1000_info e1000_ich10_info;
574extern const struct e1000_info e1000_pch_info;
575extern const struct e1000_info e1000_pch2_info;
2fbe4526 576extern const struct e1000_info e1000_pch_lpt_info;
8ce9d6c7 577extern const struct e1000_info e1000_es2_info;
bc7f75fa 578
073287c0
BA		 579extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
580 u32 pba_num_size);
bc7f75fa
AK		 581
582extern s32 e1000e_commit_phy(struct e1000_hw *hw);
583
584extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
585
586extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
587extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
588
4a770358 589extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 590extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
591 bool state);
592extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
593extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
99730e4c
BA		 594extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
595extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
bb436b20 596extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
d3738bb8
BA		 597extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
598extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 599
600extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
601extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
602extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
a4f58f54 603extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
bc7f75fa
AK		 604extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
605extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
606extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
607extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
f4d2dd4c
BA		 608extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
609extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
bc7f75fa
AK		 610extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
611extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
612extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
613extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
d1964eb1 614extern s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
bc7f75fa
AK		 615extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
616extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
617extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
618extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
1a46b40f 619extern s32 e1000e_setup_link_generic(struct e1000_hw *hw);
caaddaf8 620extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
bc7f75fa 621extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
e2de3eb6
JK		 622extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
623 u8 *mc_addr_list,
ab8932f3 624 u32 mc_addr_count);
69e1e019 625extern void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
bc7f75fa
AK		 626extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
627extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
628extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
629extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
57cde763 630extern void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
bc7f75fa
AK		 631extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
632extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
dbf80dcb 633extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
caaddaf8 634extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
608f8a0d 635extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
bc7f75fa
AK		 636extern void e1000e_reset_adaptive(struct e1000_hw *hw);
637extern void e1000e_update_adaptive(struct e1000_hw *hw);
638
639extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
640extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
641extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
642extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
643extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
644extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
645extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
2b6b168d 646extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
bc7f75fa 647extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 648extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
649 u16 *data);
bc7f75fa
AK		 650extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
651extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
652extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 653extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
654 u16 data);
bc7f75fa
AK		 655extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
656extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
657extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
658extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
659extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
660extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
661extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
f4187b56 662extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
bc7f75fa 663extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
97ac8cae
BA		 664extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
665extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
666extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
2b6b168d
BA		 667extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
668 u16 *phy_reg);
669extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
670 u16 *phy_reg);
4662e82b
BA		 671extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
672extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa
AK		 673extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
674extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 675extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
676 u16 data);
bc7f75fa 677extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 678extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
679 u16 *data);
bc7f75fa
AK		 680extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
681 u32 usec_interval, bool *success);
682extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
17f208de
BA		 683extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
684extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
2d9498f3
DG		 685extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
686extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa 687extern s32 e1000e_check_downshift(struct e1000_hw *hw);
a4f58f54 688extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 689extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
690 u16 *data);
2b6b168d
BA		 691extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
692 u16 *data);
a4f58f54 693extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 694extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
695 u16 data);
2b6b168d
BA		 696extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
697 u16 data);
a4f58f54
BA		 698extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
699extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
700extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
701extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
702extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
703extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
bc7f75fa 704
0be84010
BA		 705extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
706extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
707extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
708extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
709extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
ff10e13c 710extern bool e1000_check_phy_82574(struct e1000_hw *hw);
203e4151 711extern s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
d89777bf
BA		 712extern void e1000e_ptp_init(struct e1000_adapter *adapter);
713extern void e1000e_ptp_remove(struct e1000_adapter *adapter);
0be84010 714
bc7f75fa
AK		 715static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
716{
94d8186a 717 return hw->phy.ops.reset(hw);
bc7f75fa
AK		 718}
719
bc7f75fa
AK		 720static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
721{
94d8186a 722 return hw->phy.ops.read_reg(hw, offset, data);
bc7f75fa
AK		 723}
724
f1430d69
BA		 725static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
726{
727 return hw->phy.ops.read_reg_locked(hw, offset, data);
728}
729
bc7f75fa
AK		 730static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
731{
94d8186a 732 return hw->phy.ops.write_reg(hw, offset, data);
bc7f75fa
AK		 733}
734
f1430d69
BA		 735static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
736{
737 return hw->phy.ops.write_reg_locked(hw, offset, data);
738}
739
bc7f75fa
AK		 740static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
741{
742 return hw->phy.ops.get_cable_length(hw);
743}
744
745extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
746extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
747extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
748extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
bc7f75fa
AK		 749extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
750extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
751extern void e1000e_release_nvm(struct e1000_hw *hw);
e85e3639 752extern void e1000e_reload_nvm_generic(struct e1000_hw *hw);
608f8a0d
BA		 753extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
754
755static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
756{
757 if (hw->mac.ops.read_mac_addr)
758 return hw->mac.ops.read_mac_addr(hw);
759
760 return e1000_read_mac_addr_generic(hw);
761}
bc7f75fa
AK		 762
763static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
764{
94d8186a 765 return hw->nvm.ops.validate(hw);
bc7f75fa
AK		 766}
767
768static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
769{
94d8186a 770 return hw->nvm.ops.update(hw);
bc7f75fa
AK		 771}
772
773static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
774{
94d8186a 775 return hw->nvm.ops.read(hw, offset, words, data);
bc7f75fa
AK		 776}
777
778static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
779{
94d8186a 780 return hw->nvm.ops.write(hw, offset, words, data);
bc7f75fa
AK		 781}
782
783static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
784{
94d8186a 785 return hw->phy.ops.get_info(hw);
bc7f75fa
AK		 786}
787
4662e82b 788extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
bc7f75fa
AK		 789extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
790extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
791
792static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
793{
794 return readl(hw->hw_addr + reg);
795}
796
bdc125f7
BA		 797#define er32(reg) __er32(hw, E1000_##reg)
798
799/**
800 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
801 * @hw: pointer to the HW structure
802 *
803 * When updating the MAC CSR registers, the Manageability Engine (ME) could
804 * be accessing the registers at the same time. Normally, this is handled in
805 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
806 * accesses later than it should which could result in the register to have
807 * an incorrect value. Workaround this by checking the FWSM register which
808 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
809 * and try again a number of times.
810 **/
811static inline s32 __ew32_prepare(struct e1000_hw *hw)
812{
813 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
814
815 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
816 udelay(50);
817
818 return i;
819}
820
bc7f75fa
AK		 821static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
822{
bdc125f7
BA		 823 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
824 __ew32_prepare(hw);
825
bc7f75fa
AK		 826 writel(val, hw->hw_addr + reg);
827}
828
bdc125f7
BA		 829#define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
830
831#define e1e_flush() er32(STATUS)
832
833#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
834 (__ew32((a), (reg + ((offset) << 2)), (value)))
835
836#define E1000_READ_REG_ARRAY(a, reg, offset) \
837 (readl((a)->hw_addr + reg + ((offset) << 2)))
838
bc7f75fa 839#endif /* _E1000_H_ */
Linux 6.x block layer and io_uring tree(s)