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e1000e: Update driver version number
[linux-2.6-block.git] / drivers / net / ethernet / intel / e1000e / e1000.h
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _E1000_H_
32#define _E1000_H_
33
86d70e53 34#include <linux/bitops.h>
bc7f75fa
AK		 35#include <linux/types.h>
36#include <linux/timer.h>
37#include <linux/workqueue.h>
38#include <linux/io.h>
39#include <linux/netdevice.h>
d8014dbc 40#include <linux/pci.h>
6f461f6c 41#include <linux/pci-aspm.h>
fe46f58f 42#include <linux/crc32.h>
86d70e53 43#include <linux/if_vlan.h>
bc7f75fa
AK		 44
45#include "hw.h"
46
47struct e1000_info;
48
44defeb3 49#define e_dbg(format, arg...) \
8544b9f7 50 netdev_dbg(hw->adapter->netdev, format, ## arg)
44defeb3 51#define e_err(format, arg...) \
8544b9f7 52 netdev_err(adapter->netdev, format, ## arg)
44defeb3 53#define e_info(format, arg...) \
8544b9f7 54 netdev_info(adapter->netdev, format, ## arg)
44defeb3 55#define e_warn(format, arg...) \
8544b9f7 56 netdev_warn(adapter->netdev, format, ## arg)
44defeb3 57#define e_notice(format, arg...) \
8544b9f7 58 netdev_notice(adapter->netdev, format, ## arg)
bc7f75fa
AK		 59
60
98a1708d 61/* Interrupt modes, as used by the IntMode parameter */
4662e82b
BA		 62#define E1000E_INT_MODE_LEGACY 0
63#define E1000E_INT_MODE_MSI 1
64#define E1000E_INT_MODE_MSIX 2
65
ad68076e 66/* Tx/Rx descriptor defines */
bc7f75fa
AK		 67#define E1000_DEFAULT_TXD 256
68#define E1000_MAX_TXD 4096
7b1be198 69#define E1000_MIN_TXD 64
bc7f75fa
AK		 70
71#define E1000_DEFAULT_RXD 256
72#define E1000_MAX_RXD 4096
7b1be198 73#define E1000_MIN_RXD 64
bc7f75fa 74
de5b3077
AK		 75#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
76#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
77
bc7f75fa
AK		 78/* Early Receive defines */
79#define E1000_ERT_2048 0x100
80
81#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
82
83/* How many Tx Descriptors do we need to call netif_wake_queue ? */
84/* How many Rx Buffers do we bundle into one write to the hardware ? */
85#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
86
87#define AUTO_ALL_MODES 0
88#define E1000_EEPROM_APME 0x0400
89
90#define E1000_MNG_VLAN_NONE (-1)
91
92/* Number of packet split data buffers (not including the header buffer) */
93#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
94
2adc55c9
BA		 95#define DEFAULT_JUMBO 9234
96
a4f58f54
BA		 97/* BM/HV Specific Registers */
98#define BM_PORT_CTRL_PAGE 769
99
100#define PHY_UPPER_SHIFT 21
101#define BM_PHY_REG(page, reg) \
102 (((reg) & MAX_PHY_REG_ADDRESS) |\
103 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
104 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
105
106/* PHY Wakeup Registers and defines */
3ebfc7c9 107#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
a4f58f54
BA		 108#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
109#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
110#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
111#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
112#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
113#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
114#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
115#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
116#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
117
118#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
119#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
120#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
121#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
122#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
123#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
124#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
125
2b6b168d
BA		 126#define HV_STATS_PAGE 778
127#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
128#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
129#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
130#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
131#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
132#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
133#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
134#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
135#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
136#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
137#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
138#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
139#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
140#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
a4f58f54 141
38eb394e
BA		 142#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
143
1d5846b9
BA		 144/* BM PHY Copper Specific Status */
145#define BM_CS_STATUS 17
146#define BM_CS_STATUS_LINK_UP 0x0400
147#define BM_CS_STATUS_RESOLVED 0x0800
148#define BM_CS_STATUS_SPEED_MASK 0xC000
149#define BM_CS_STATUS_SPEED_1000 0x8000
150
151/* 82577 Mobile Phy Status Register */
152#define HV_M_STATUS 26
153#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
154#define HV_M_STATUS_SPEED_MASK 0x0300
155#define HV_M_STATUS_SPEED_1000 0x0200
156#define HV_M_STATUS_LINK_UP 0x0040
157
c6e7f51e
BA		 158#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
159#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
160
23606cf5
RW		 161/* Time to wait before putting the device into D3 if there's no link (in ms). */
162#define LINK_TIMEOUT 100
163
bb9e44d0
BA		 164/*
165 * Count for polling __E1000_RESET condition every 10-20msec.
166 * Experimentation has shown the reset can take approximately 210msec.
167 */
168#define E1000_CHECK_RESET_COUNT 25
169
3a3b7586
JB		 170#define DEFAULT_RDTR 0
171#define DEFAULT_RADV 8
172#define BURST_RDTR 0x20
173#define BURST_RADV 0x20
174
175/*
176 * in the case of WTHRESH, it appears at least the 82571/2 hardware
177 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
178 * WTHRESH=4, and since we want 64 bytes at a time written back, set
179 * it to 5
180 */
181#define E1000_TXDCTL_DMA_BURST_ENABLE \
182 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
183 E1000_TXDCTL_COUNT_DESC | \
184 (5 << 16) | /* wthresh must be +1 more than desired */\
185 (1 << 8) | /* hthresh */ \
186 0x1f) /* pthresh */
187
188#define E1000_RXDCTL_DMA_BURST_ENABLE \
189 (0x01000000 | /* set descriptor granularity */ \
190 (4 << 16) | /* set writeback threshold */ \
191 (4 << 8) | /* set prefetch threshold */ \
192 0x20) /* set hthresh */
193
194#define E1000_TIDV_FPD (1 << 31)
195#define E1000_RDTR_FPD (1 << 31)
196
bc7f75fa
AK		 197enum e1000_boards {
198 board_82571,
199 board_82572,
200 board_82573,
4662e82b 201 board_82574,
8c81c9c3 202 board_82583,
bc7f75fa
AK		 203 board_80003es2lan,
204 board_ich8lan,
205 board_ich9lan,
f4187b56 206 board_ich10lan,
a4f58f54 207 board_pchlan,
d3738bb8 208 board_pch2lan,
bc7f75fa
AK		 209};
210
bc7f75fa
AK		 211struct e1000_ps_page {
212 struct page *page;
213 u64 dma; /* must be u64 - written to hw */
214};
215
216/*
217 * wrappers around a pointer to a socket buffer,
218 * so a DMA handle can be stored along with the buffer
219 */
220struct e1000_buffer {
221 dma_addr_t dma;
222 struct sk_buff *skb;
223 union {
ad68076e 224 /* Tx */
bc7f75fa
AK		 225 struct {
226 unsigned long time_stamp;
227 u16 length;
228 u16 next_to_watch;
9ed318d5
TH		 229 unsigned int segs;
230 unsigned int bytecount;
03b1320d 231 u16 mapped_as_page;
bc7f75fa 232 };
ad68076e 233 /* Rx */
03b1320d
AD		 234 struct {
235 /* arrays of page information for packet split */
236 struct e1000_ps_page *ps_pages;
237 struct page *page;
238 };
bc7f75fa 239 };
bc7f75fa
AK		 240};
241
242struct e1000_ring {
55aa6985 243 struct e1000_adapter *adapter; /* back pointer to adapter */
bc7f75fa
AK		 244 void *desc; /* pointer to ring memory */
245 dma_addr_t dma; /* phys address of ring */
246 unsigned int size; /* length of ring in bytes */
247 unsigned int count; /* number of desc. in ring */
248
249 u16 next_to_use;
250 u16 next_to_clean;
251
c5083cf6
BA		 252 void __iomem *head;
253 void __iomem *tail;
bc7f75fa
AK		 254
255 /* array of buffer information structs */
256 struct e1000_buffer *buffer_info;
257
4662e82b
BA		 258 char name[IFNAMSIZ + 5];
259 u32 ims_val;
260 u32 itr_val;
c5083cf6 261 void __iomem *itr_register;
4662e82b
BA		 262 int set_itr;
263
bc7f75fa 264 struct sk_buff *rx_skb_top;
bc7f75fa
AK		 265};
266
7c25769f
BA		 267/* PHY register snapshot values */
268struct e1000_phy_regs {
269 u16 bmcr; /* basic mode control register */
270 u16 bmsr; /* basic mode status register */
271 u16 advertise; /* auto-negotiation advertisement */
272 u16 lpa; /* link partner ability register */
273 u16 expansion; /* auto-negotiation expansion reg */
274 u16 ctrl1000; /* 1000BASE-T control register */
275 u16 stat1000; /* 1000BASE-T status register */
276 u16 estatus; /* extended status register */
277};
278
bc7f75fa
AK		 279/* board specific private data structure */
280struct e1000_adapter {
281 struct timer_list watchdog_timer;
282 struct timer_list phy_info_timer;
283 struct timer_list blink_timer;
284
285 struct work_struct reset_task;
286 struct work_struct watchdog_task;
287
288 const struct e1000_info *ei;
289
86d70e53 290 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
bc7f75fa
AK		 291 u32 bd_number;
292 u32 rx_buffer_len;
293 u16 mng_vlan_id;
294 u16 link_speed;
295 u16 link_duplex;
84527590 296 u16 eeprom_vers;
bc7f75fa 297
bc7f75fa
AK		 298 /* track device up/down/testing state */
299 unsigned long state;
300
301 /* Interrupt Throttle Rate */
302 u32 itr;
303 u32 itr_setting;
304 u16 tx_itr;
305 u16 rx_itr;
306
307 /*
ad68076e 308 * Tx
bc7f75fa
AK		 309 */
310 struct e1000_ring *tx_ring /* One per active queue */
311 ____cacheline_aligned_in_smp;
312
313 struct napi_struct napi;
314
bc7f75fa
AK		 315 unsigned int restart_queue;
316 u32 txd_cmd;
317
318 bool detect_tx_hung;
09357b00 319 bool tx_hang_recheck;
bc7f75fa
AK		 320 u8 tx_timeout_factor;
321
322 u32 tx_int_delay;
323 u32 tx_abs_int_delay;
324
325 unsigned int total_tx_bytes;
326 unsigned int total_tx_packets;
327 unsigned int total_rx_bytes;
328 unsigned int total_rx_packets;
329
ad68076e 330 /* Tx stats */
bc7f75fa
AK		 331 u64 tpt_old;
332 u64 colc_old;
7c25769f
BA		 333 u32 gotc;
334 u64 gotc_old;
bc7f75fa
AK		 335 u32 tx_timeout_count;
336 u32 tx_fifo_head;
337 u32 tx_head_addr;
338 u32 tx_fifo_size;
339 u32 tx_dma_failed;
340
341 /*
ad68076e 342 * Rx
bc7f75fa 343 */
55aa6985
BA		 344 bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
345 int work_to_do) ____cacheline_aligned_in_smp;
346 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
347 gfp_t gfp);
bc7f75fa
AK		 348 struct e1000_ring *rx_ring;
349
350 u32 rx_int_delay;
351 u32 rx_abs_int_delay;
352
ad68076e 353 /* Rx stats */
bc7f75fa
AK		 354 u64 hw_csum_err;
355 u64 hw_csum_good;
356 u64 rx_hdr_split;
7c25769f
BA		 357 u32 gorc;
358 u64 gorc_old;
bc7f75fa
AK		 359 u32 alloc_rx_buff_failed;
360 u32 rx_dma_failed;
361
362 unsigned int rx_ps_pages;
363 u16 rx_ps_bsize0;
318a94d6
JK		 364 u32 max_frame_size;
365 u32 min_frame_size;
bc7f75fa
AK		 366
367 /* OS defined structs */
368 struct net_device *netdev;
369 struct pci_dev *pdev;
bc7f75fa
AK		 370
371 /* structs defined in e1000_hw.h */
372 struct e1000_hw hw;
373
67fd4fcb 374 spinlock_t stats64_lock;
bc7f75fa
AK		 375 struct e1000_hw_stats stats;
376 struct e1000_phy_info phy_info;
377 struct e1000_phy_stats phy_stats;
378
7c25769f
BA		 379 /* Snapshot of PHY registers */
380 struct e1000_phy_regs phy_regs;
381
bc7f75fa
AK		 382 struct e1000_ring test_tx_ring;
383 struct e1000_ring test_rx_ring;
384 u32 test_icr;
385
386 u32 msg_enable;
8e86acd7 387 unsigned int num_vectors;
4662e82b
BA		 388 struct msix_entry *msix_entries;
389 int int_mode;
390 u32 eiac_mask;
bc7f75fa
AK		 391
392 u32 eeprom_wol;
393 u32 wol;
394 u32 pba;
2adc55c9 395 u32 max_hw_frame_size;
bc7f75fa 396
318a94d6 397 bool fc_autoneg;
bc7f75fa 398
bc7f75fa 399 unsigned int flags;
eb7c3adb 400 unsigned int flags2;
a8f88ff5
JB		 401 struct work_struct downshift_task;
402 struct work_struct update_phy_task;
41cec6f1 403 struct work_struct print_hang_task;
23606cf5
RW		 404
405 bool idle_check;
ff10e13c 406 int phy_hang_count;
55aa6985
BA		 407
408 u16 tx_ring_count;
409 u16 rx_ring_count;
bc7f75fa
AK		 410};
411
412struct e1000_info {
413 enum e1000_mac_type mac;
414 unsigned int flags;
6f461f6c 415 unsigned int flags2;
bc7f75fa 416 u32 pba;
2adc55c9 417 u32 max_hw_frame_size;
69e3fd8c 418 s32 (*get_variants)(struct e1000_adapter *);
8ce9d6c7
JK		 419 const struct e1000_mac_operations *mac_ops;
420 const struct e1000_phy_operations *phy_ops;
421 const struct e1000_nvm_operations *nvm_ops;
bc7f75fa
AK		 422};
423
424/* hardware capability, feature, and workaround flags */
425#define FLAG_HAS_AMT (1 << 0)
426#define FLAG_HAS_FLASH (1 << 1)
427#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
428#define FLAG_HAS_WOL (1 << 3)
79d4e908 429/* reserved bit4 */
bc7f75fa
AK		 430#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
431#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
432#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
4a770358 433#define FLAG_READ_ONLY_NVM (1 << 8)
97ac8cae 434#define FLAG_IS_ICH (1 << 9)
4662e82b 435#define FLAG_HAS_MSIX (1 << 10)
bc7f75fa
AK		 436#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
437#define FLAG_IS_QUAD_PORT_A (1 << 12)
438#define FLAG_IS_QUAD_PORT (1 << 13)
6a92f732 439/* reserved bit14 */
bc7f75fa
AK		 440#define FLAG_APME_IN_WUC (1 << 15)
441#define FLAG_APME_IN_CTRL3 (1 << 16)
442#define FLAG_APME_CHECK_PORT_B (1 << 17)
443#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
444#define FLAG_NO_WAKE_UCAST (1 << 19)
445#define FLAG_MNG_PT_ENABLED (1 << 20)
446#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
447#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
448#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
449#define FLAG_RX_NEEDS_RESTART (1 << 24)
450#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
451#define FLAG_SMART_POWER_DOWN (1 << 26)
452#define FLAG_MSI_ENABLED (1 << 27)
dc221294 453/* reserved (1 << 28) */
bc7f75fa 454#define FLAG_TSO_FORCE (1 << 29)
318a94d6 455#define FLAG_RX_RESTART_NOW (1 << 30)
f8d59f78 456#define FLAG_MSI_TEST_FAILED (1 << 31)
bc7f75fa 457
eb7c3adb 458#define FLAG2_CRC_STRIPPING (1 << 0)
a4f58f54 459#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
b94b5028 460#define FLAG2_IS_DISCARDING (1 << 2)
6f461f6c 461#define FLAG2_DISABLE_ASPM_L1 (1 << 3)
8c7bbb92 462#define FLAG2_HAS_PHY_STATS (1 << 4)
e52997f9 463#define FLAG2_HAS_EEE (1 << 5)
3a3b7586 464#define FLAG2_DMA_BURST (1 << 6)
78cd29d5 465#define FLAG2_DISABLE_ASPM_L0S (1 << 7)
828bac87 466#define FLAG2_DISABLE_AIM (1 << 8)
ff10e13c 467#define FLAG2_CHECK_PHY_HANG (1 << 9)
7f99ae63 468#define FLAG2_NO_DISABLE_RX (1 << 10)
c6e7f51e 469#define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
0184039a 470#define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
eb7c3adb 471
bc7f75fa
AK		 472#define E1000_RX_DESC_PS(R, i) \
473 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
5f450212
BA		 474#define E1000_RX_DESC_EXT(R, i) \
475 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
bc7f75fa 476#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
bc7f75fa
AK		 477#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
478#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
479
480enum e1000_state_t {
481 __E1000_TESTING,
482 __E1000_RESETTING,
a90b412c 483 __E1000_ACCESS_SHARED_RESOURCE,
bc7f75fa
AK		 484 __E1000_DOWN
485};
486
487enum latency_range {
488 lowest_latency = 0,
489 low_latency = 1,
490 bulk_latency = 2,
491 latency_invalid = 255
492};
493
494extern char e1000e_driver_name[];
495extern const char e1000e_driver_version[];
496
497extern void e1000e_check_options(struct e1000_adapter *adapter);
498extern void e1000e_set_ethtool_ops(struct net_device *netdev);
499
500extern int e1000e_up(struct e1000_adapter *adapter);
501extern void e1000e_down(struct e1000_adapter *adapter);
502extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
503extern void e1000e_reset(struct e1000_adapter *adapter);
504extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
55aa6985
BA		 505extern int e1000e_setup_rx_resources(struct e1000_ring *ring);
506extern int e1000e_setup_tx_resources(struct e1000_ring *ring);
507extern void e1000e_free_rx_resources(struct e1000_ring *ring);
508extern void e1000e_free_tx_resources(struct e1000_ring *ring);
67fd4fcb
JK		 509extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
510 struct rtnl_link_stats64
511 *stats);
4662e82b
BA		 512extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
513extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
31dbe5b4
BA		 514extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
515extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
bc7f75fa
AK		 516
517extern unsigned int copybreak;
518
519extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
520
8ce9d6c7
JK		 521extern const struct e1000_info e1000_82571_info;
522extern const struct e1000_info e1000_82572_info;
523extern const struct e1000_info e1000_82573_info;
524extern const struct e1000_info e1000_82574_info;
525extern const struct e1000_info e1000_82583_info;
526extern const struct e1000_info e1000_ich8_info;
527extern const struct e1000_info e1000_ich9_info;
528extern const struct e1000_info e1000_ich10_info;
529extern const struct e1000_info e1000_pch_info;
530extern const struct e1000_info e1000_pch2_info;
531extern const struct e1000_info e1000_es2_info;
bc7f75fa 532
073287c0
BA		 533extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
534 u32 pba_num_size);
bc7f75fa
AK		 535
536extern s32 e1000e_commit_phy(struct e1000_hw *hw);
537
538extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
539
540extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
541extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
542
4a770358 543extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 544extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
545 bool state);
546extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
547extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
99730e4c
BA		 548extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
549extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
bb436b20 550extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
d3738bb8
BA		 551extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
552extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 553
554extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
555extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
556extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
a4f58f54 557extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
bc7f75fa
AK		 558extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
559extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
560extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
561extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
f4d2dd4c
BA		 562extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
563extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
bc7f75fa
AK		 564extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
565extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
566extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
567extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
d1964eb1 568extern s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
bc7f75fa
AK		 569extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
570extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
571extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
572extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
1a46b40f 573extern s32 e1000e_setup_link_generic(struct e1000_hw *hw);
caaddaf8 574extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
bc7f75fa 575extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
e2de3eb6
JK		 576extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
577 u8 *mc_addr_list,
ab8932f3 578 u32 mc_addr_count);
69e1e019 579extern void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
bc7f75fa
AK		 580extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
581extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
582extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
583extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
57cde763 584extern void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
bc7f75fa
AK		 585extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
586extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
dbf80dcb 587extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
caaddaf8 588extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
608f8a0d 589extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
bc7f75fa
AK		 590extern void e1000e_reset_adaptive(struct e1000_hw *hw);
591extern void e1000e_update_adaptive(struct e1000_hw *hw);
592
593extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
594extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
595extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
596extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
597extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
598extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
599extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
2b6b168d 600extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
bc7f75fa 601extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 602extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
603 u16 *data);
bc7f75fa
AK		 604extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
605extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
606extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 607extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
608 u16 data);
bc7f75fa
AK		 609extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
610extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
611extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
612extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
613extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
614extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
615extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
f4187b56 616extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
bc7f75fa 617extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
97ac8cae
BA		 618extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
619extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
620extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
2b6b168d
BA		 621extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
622 u16 *phy_reg);
623extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
624 u16 *phy_reg);
4662e82b
BA		 625extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
626extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa
AK		 627extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
628extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 629extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
630 u16 data);
bc7f75fa 631extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 632extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
633 u16 *data);
bc7f75fa
AK		 634extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
635 u32 usec_interval, bool *success);
636extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
17f208de
BA		 637extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
638extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
2d9498f3
DG		 639extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
640extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa 641extern s32 e1000e_check_downshift(struct e1000_hw *hw);
a4f58f54 642extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 643extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
644 u16 *data);
2b6b168d
BA		 645extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
646 u16 *data);
a4f58f54 647extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 648extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
649 u16 data);
2b6b168d
BA		 650extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
651 u16 data);
a4f58f54
BA		 652extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
653extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
654extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
655extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
656extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
657extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
bc7f75fa 658
0be84010
BA		 659extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
660extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
661extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
662extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
663extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
ff10e13c 664extern bool e1000_check_phy_82574(struct e1000_hw *hw);
0be84010 665
bc7f75fa
AK		 666static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
667{
94d8186a 668 return hw->phy.ops.reset(hw);
bc7f75fa
AK		 669}
670
bc7f75fa
AK		 671static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
672{
94d8186a 673 return hw->phy.ops.read_reg(hw, offset, data);
bc7f75fa
AK		 674}
675
f1430d69
BA		 676static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
677{
678 return hw->phy.ops.read_reg_locked(hw, offset, data);
679}
680
bc7f75fa
AK		 681static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
682{
94d8186a 683 return hw->phy.ops.write_reg(hw, offset, data);
bc7f75fa
AK		 684}
685
f1430d69
BA		 686static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
687{
688 return hw->phy.ops.write_reg_locked(hw, offset, data);
689}
690
bc7f75fa
AK		 691static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
692{
693 return hw->phy.ops.get_cable_length(hw);
694}
695
696extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
697extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
698extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
699extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
bc7f75fa
AK		 700extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
701extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
702extern void e1000e_release_nvm(struct e1000_hw *hw);
e85e3639 703extern void e1000e_reload_nvm_generic(struct e1000_hw *hw);
608f8a0d
BA		 704extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
705
706static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
707{
708 if (hw->mac.ops.read_mac_addr)
709 return hw->mac.ops.read_mac_addr(hw);
710
711 return e1000_read_mac_addr_generic(hw);
712}
bc7f75fa
AK		 713
714static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
715{
94d8186a 716 return hw->nvm.ops.validate(hw);
bc7f75fa
AK		 717}
718
719static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
720{
94d8186a 721 return hw->nvm.ops.update(hw);
bc7f75fa
AK		 722}
723
724static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
725{
94d8186a 726 return hw->nvm.ops.read(hw, offset, words, data);
bc7f75fa
AK		 727}
728
729static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
730{
94d8186a 731 return hw->nvm.ops.write(hw, offset, words, data);
bc7f75fa
AK		 732}
733
734static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
735{
94d8186a 736 return hw->phy.ops.get_info(hw);
bc7f75fa
AK		 737}
738
4662e82b 739extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
bc7f75fa
AK		 740extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
741extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
742
743static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
744{
745 return readl(hw->hw_addr + reg);
746}
747
bdc125f7
BA		 748#define er32(reg) __er32(hw, E1000_##reg)
749
750/**
751 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
752 * @hw: pointer to the HW structure
753 *
754 * When updating the MAC CSR registers, the Manageability Engine (ME) could
755 * be accessing the registers at the same time. Normally, this is handled in
756 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
757 * accesses later than it should which could result in the register to have
758 * an incorrect value. Workaround this by checking the FWSM register which
759 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
760 * and try again a number of times.
761 **/
762static inline s32 __ew32_prepare(struct e1000_hw *hw)
763{
764 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
765
766 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
767 udelay(50);
768
769 return i;
770}
771
bc7f75fa
AK		 772static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
773{
bdc125f7
BA		 774 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
775 __ew32_prepare(hw);
776
bc7f75fa
AK		 777 writel(val, hw->hw_addr + reg);
778}
779
bdc125f7
BA		 780#define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
781
782#define e1e_flush() er32(STATUS)
783
784#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
785 (__ew32((a), (reg + ((offset) << 2)), (value)))
786
787#define E1000_READ_REG_ARRAY(a, reg, offset) \
788 (readl((a)->hw_addr + reg + ((offset) << 2)))
789
bc7f75fa 790#endif /* _E1000_H_ */
Linux 6.x block layer and io_uring tree(s)