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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
bf67044b | 4 | Copyright(c) 1999 - 2013 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* Linux PRO/1000 Ethernet Driver main header file */ | |
30 | ||
31 | #ifndef _E1000_H_ | |
32 | #define _E1000_H_ | |
33 | ||
86d70e53 | 34 | #include <linux/bitops.h> |
bc7f75fa AK |
35 | #include <linux/types.h> |
36 | #include <linux/timer.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/io.h> | |
39 | #include <linux/netdevice.h> | |
d8014dbc | 40 | #include <linux/pci.h> |
6f461f6c | 41 | #include <linux/pci-aspm.h> |
fe46f58f | 42 | #include <linux/crc32.h> |
86d70e53 | 43 | #include <linux/if_vlan.h> |
b67e1913 BA |
44 | #include <linux/clocksource.h> |
45 | #include <linux/net_tstamp.h> | |
d89777bf BA |
46 | #include <linux/ptp_clock_kernel.h> |
47 | #include <linux/ptp_classify.h> | |
c2ade1a4 | 48 | #include <linux/mii.h> |
d495bcb8 | 49 | #include <linux/mdio.h> |
bc7f75fa AK |
50 | #include "hw.h" |
51 | ||
52 | struct e1000_info; | |
53 | ||
44defeb3 | 54 | #define e_dbg(format, arg...) \ |
8544b9f7 | 55 | netdev_dbg(hw->adapter->netdev, format, ## arg) |
44defeb3 | 56 | #define e_err(format, arg...) \ |
8544b9f7 | 57 | netdev_err(adapter->netdev, format, ## arg) |
44defeb3 | 58 | #define e_info(format, arg...) \ |
8544b9f7 | 59 | netdev_info(adapter->netdev, format, ## arg) |
44defeb3 | 60 | #define e_warn(format, arg...) \ |
8544b9f7 | 61 | netdev_warn(adapter->netdev, format, ## arg) |
44defeb3 | 62 | #define e_notice(format, arg...) \ |
8544b9f7 | 63 | netdev_notice(adapter->netdev, format, ## arg) |
bc7f75fa | 64 | |
98a1708d | 65 | /* Interrupt modes, as used by the IntMode parameter */ |
4662e82b BA |
66 | #define E1000E_INT_MODE_LEGACY 0 |
67 | #define E1000E_INT_MODE_MSI 1 | |
68 | #define E1000E_INT_MODE_MSIX 2 | |
69 | ||
ad68076e | 70 | /* Tx/Rx descriptor defines */ |
bc7f75fa AK |
71 | #define E1000_DEFAULT_TXD 256 |
72 | #define E1000_MAX_TXD 4096 | |
7b1be198 | 73 | #define E1000_MIN_TXD 64 |
bc7f75fa AK |
74 | |
75 | #define E1000_DEFAULT_RXD 256 | |
76 | #define E1000_MAX_RXD 4096 | |
7b1be198 | 77 | #define E1000_MIN_RXD 64 |
bc7f75fa | 78 | |
de5b3077 AK |
79 | #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ |
80 | #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ | |
81 | ||
bc7f75fa AK |
82 | #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ |
83 | ||
84 | /* How many Tx Descriptors do we need to call netif_wake_queue ? */ | |
85 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | |
86 | #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
87 | ||
88 | #define AUTO_ALL_MODES 0 | |
89 | #define E1000_EEPROM_APME 0x0400 | |
90 | ||
91 | #define E1000_MNG_VLAN_NONE (-1) | |
92 | ||
2adc55c9 BA |
93 | #define DEFAULT_JUMBO 9234 |
94 | ||
23606cf5 RW |
95 | /* Time to wait before putting the device into D3 if there's no link (in ms). */ |
96 | #define LINK_TIMEOUT 100 | |
97 | ||
e921eb1a | 98 | /* Count for polling __E1000_RESET condition every 10-20msec. |
bb9e44d0 BA |
99 | * Experimentation has shown the reset can take approximately 210msec. |
100 | */ | |
101 | #define E1000_CHECK_RESET_COUNT 25 | |
102 | ||
3a3b7586 JB |
103 | #define DEFAULT_RDTR 0 |
104 | #define DEFAULT_RADV 8 | |
105 | #define BURST_RDTR 0x20 | |
106 | #define BURST_RADV 0x20 | |
107 | ||
e921eb1a | 108 | /* in the case of WTHRESH, it appears at least the 82571/2 hardware |
3a3b7586 | 109 | * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when |
8edc0e62 HS |
110 | * WTHRESH=4, so a setting of 5 gives the most efficient bus |
111 | * utilization but to avoid possible Tx stalls, set it to 1 | |
3a3b7586 JB |
112 | */ |
113 | #define E1000_TXDCTL_DMA_BURST_ENABLE \ | |
114 | (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ | |
115 | E1000_TXDCTL_COUNT_DESC | \ | |
8edc0e62 | 116 | (1 << 16) | /* wthresh must be +1 more than desired */\ |
3a3b7586 JB |
117 | (1 << 8) | /* hthresh */ \ |
118 | 0x1f) /* pthresh */ | |
119 | ||
120 | #define E1000_RXDCTL_DMA_BURST_ENABLE \ | |
121 | (0x01000000 | /* set descriptor granularity */ \ | |
122 | (4 << 16) | /* set writeback threshold */ \ | |
123 | (4 << 8) | /* set prefetch threshold */ \ | |
124 | 0x20) /* set hthresh */ | |
125 | ||
126 | #define E1000_TIDV_FPD (1 << 31) | |
127 | #define E1000_RDTR_FPD (1 << 31) | |
128 | ||
bc7f75fa AK |
129 | enum e1000_boards { |
130 | board_82571, | |
131 | board_82572, | |
132 | board_82573, | |
4662e82b | 133 | board_82574, |
8c81c9c3 | 134 | board_82583, |
bc7f75fa AK |
135 | board_80003es2lan, |
136 | board_ich8lan, | |
137 | board_ich9lan, | |
f4187b56 | 138 | board_ich10lan, |
a4f58f54 | 139 | board_pchlan, |
d3738bb8 | 140 | board_pch2lan, |
2fbe4526 | 141 | board_pch_lpt, |
bc7f75fa AK |
142 | }; |
143 | ||
bc7f75fa AK |
144 | struct e1000_ps_page { |
145 | struct page *page; | |
146 | u64 dma; /* must be u64 - written to hw */ | |
147 | }; | |
148 | ||
e921eb1a | 149 | /* wrappers around a pointer to a socket buffer, |
bc7f75fa AK |
150 | * so a DMA handle can be stored along with the buffer |
151 | */ | |
152 | struct e1000_buffer { | |
153 | dma_addr_t dma; | |
154 | struct sk_buff *skb; | |
155 | union { | |
ad68076e | 156 | /* Tx */ |
bc7f75fa AK |
157 | struct { |
158 | unsigned long time_stamp; | |
159 | u16 length; | |
160 | u16 next_to_watch; | |
9ed318d5 TH |
161 | unsigned int segs; |
162 | unsigned int bytecount; | |
03b1320d | 163 | u16 mapped_as_page; |
bc7f75fa | 164 | }; |
ad68076e | 165 | /* Rx */ |
03b1320d AD |
166 | struct { |
167 | /* arrays of page information for packet split */ | |
168 | struct e1000_ps_page *ps_pages; | |
169 | struct page *page; | |
170 | }; | |
bc7f75fa | 171 | }; |
bc7f75fa AK |
172 | }; |
173 | ||
174 | struct e1000_ring { | |
55aa6985 | 175 | struct e1000_adapter *adapter; /* back pointer to adapter */ |
bc7f75fa AK |
176 | void *desc; /* pointer to ring memory */ |
177 | dma_addr_t dma; /* phys address of ring */ | |
178 | unsigned int size; /* length of ring in bytes */ | |
179 | unsigned int count; /* number of desc. in ring */ | |
180 | ||
181 | u16 next_to_use; | |
182 | u16 next_to_clean; | |
183 | ||
c5083cf6 BA |
184 | void __iomem *head; |
185 | void __iomem *tail; | |
bc7f75fa AK |
186 | |
187 | /* array of buffer information structs */ | |
188 | struct e1000_buffer *buffer_info; | |
189 | ||
4662e82b BA |
190 | char name[IFNAMSIZ + 5]; |
191 | u32 ims_val; | |
192 | u32 itr_val; | |
c5083cf6 | 193 | void __iomem *itr_register; |
4662e82b BA |
194 | int set_itr; |
195 | ||
bc7f75fa | 196 | struct sk_buff *rx_skb_top; |
bc7f75fa AK |
197 | }; |
198 | ||
7c25769f BA |
199 | /* PHY register snapshot values */ |
200 | struct e1000_phy_regs { | |
201 | u16 bmcr; /* basic mode control register */ | |
202 | u16 bmsr; /* basic mode status register */ | |
203 | u16 advertise; /* auto-negotiation advertisement */ | |
204 | u16 lpa; /* link partner ability register */ | |
205 | u16 expansion; /* auto-negotiation expansion reg */ | |
206 | u16 ctrl1000; /* 1000BASE-T control register */ | |
207 | u16 stat1000; /* 1000BASE-T status register */ | |
208 | u16 estatus; /* extended status register */ | |
209 | }; | |
210 | ||
bc7f75fa AK |
211 | /* board specific private data structure */ |
212 | struct e1000_adapter { | |
213 | struct timer_list watchdog_timer; | |
214 | struct timer_list phy_info_timer; | |
215 | struct timer_list blink_timer; | |
216 | ||
217 | struct work_struct reset_task; | |
218 | struct work_struct watchdog_task; | |
219 | ||
220 | const struct e1000_info *ei; | |
221 | ||
86d70e53 | 222 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
bc7f75fa AK |
223 | u32 bd_number; |
224 | u32 rx_buffer_len; | |
225 | u16 mng_vlan_id; | |
226 | u16 link_speed; | |
227 | u16 link_duplex; | |
84527590 | 228 | u16 eeprom_vers; |
bc7f75fa | 229 | |
bc7f75fa AK |
230 | /* track device up/down/testing state */ |
231 | unsigned long state; | |
232 | ||
233 | /* Interrupt Throttle Rate */ | |
234 | u32 itr; | |
235 | u32 itr_setting; | |
236 | u16 tx_itr; | |
237 | u16 rx_itr; | |
238 | ||
33550cec BA |
239 | /* Tx - one ring per active queue */ |
240 | struct e1000_ring *tx_ring ____cacheline_aligned_in_smp; | |
d821a4c4 | 241 | u32 tx_fifo_limit; |
bc7f75fa AK |
242 | |
243 | struct napi_struct napi; | |
244 | ||
94fb848b BA |
245 | unsigned int uncorr_errors; /* uncorrectable ECC errors */ |
246 | unsigned int corr_errors; /* correctable ECC errors */ | |
bc7f75fa AK |
247 | unsigned int restart_queue; |
248 | u32 txd_cmd; | |
249 | ||
250 | bool detect_tx_hung; | |
09357b00 | 251 | bool tx_hang_recheck; |
bc7f75fa AK |
252 | u8 tx_timeout_factor; |
253 | ||
254 | u32 tx_int_delay; | |
255 | u32 tx_abs_int_delay; | |
256 | ||
257 | unsigned int total_tx_bytes; | |
258 | unsigned int total_tx_packets; | |
259 | unsigned int total_rx_bytes; | |
260 | unsigned int total_rx_packets; | |
261 | ||
ad68076e | 262 | /* Tx stats */ |
bc7f75fa AK |
263 | u64 tpt_old; |
264 | u64 colc_old; | |
7c25769f BA |
265 | u32 gotc; |
266 | u64 gotc_old; | |
bc7f75fa AK |
267 | u32 tx_timeout_count; |
268 | u32 tx_fifo_head; | |
269 | u32 tx_head_addr; | |
270 | u32 tx_fifo_size; | |
271 | u32 tx_dma_failed; | |
272 | ||
e921eb1a | 273 | /* Rx */ |
55aa6985 BA |
274 | bool (*clean_rx) (struct e1000_ring *ring, int *work_done, |
275 | int work_to_do) ____cacheline_aligned_in_smp; | |
276 | void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count, | |
277 | gfp_t gfp); | |
bc7f75fa AK |
278 | struct e1000_ring *rx_ring; |
279 | ||
280 | u32 rx_int_delay; | |
281 | u32 rx_abs_int_delay; | |
282 | ||
ad68076e | 283 | /* Rx stats */ |
bc7f75fa AK |
284 | u64 hw_csum_err; |
285 | u64 hw_csum_good; | |
286 | u64 rx_hdr_split; | |
7c25769f BA |
287 | u32 gorc; |
288 | u64 gorc_old; | |
bc7f75fa AK |
289 | u32 alloc_rx_buff_failed; |
290 | u32 rx_dma_failed; | |
b67e1913 | 291 | u32 rx_hwtstamp_cleared; |
bc7f75fa AK |
292 | |
293 | unsigned int rx_ps_pages; | |
294 | u16 rx_ps_bsize0; | |
318a94d6 JK |
295 | u32 max_frame_size; |
296 | u32 min_frame_size; | |
bc7f75fa AK |
297 | |
298 | /* OS defined structs */ | |
299 | struct net_device *netdev; | |
300 | struct pci_dev *pdev; | |
bc7f75fa AK |
301 | |
302 | /* structs defined in e1000_hw.h */ | |
303 | struct e1000_hw hw; | |
304 | ||
9d57088b | 305 | spinlock_t stats64_lock; /* protects statistics counters */ |
bc7f75fa AK |
306 | struct e1000_hw_stats stats; |
307 | struct e1000_phy_info phy_info; | |
308 | struct e1000_phy_stats phy_stats; | |
309 | ||
7c25769f BA |
310 | /* Snapshot of PHY registers */ |
311 | struct e1000_phy_regs phy_regs; | |
312 | ||
bc7f75fa AK |
313 | struct e1000_ring test_tx_ring; |
314 | struct e1000_ring test_rx_ring; | |
315 | u32 test_icr; | |
316 | ||
317 | u32 msg_enable; | |
8e86acd7 | 318 | unsigned int num_vectors; |
4662e82b BA |
319 | struct msix_entry *msix_entries; |
320 | int int_mode; | |
321 | u32 eiac_mask; | |
bc7f75fa AK |
322 | |
323 | u32 eeprom_wol; | |
324 | u32 wol; | |
325 | u32 pba; | |
2adc55c9 | 326 | u32 max_hw_frame_size; |
bc7f75fa | 327 | |
318a94d6 | 328 | bool fc_autoneg; |
bc7f75fa | 329 | |
bc7f75fa | 330 | unsigned int flags; |
eb7c3adb | 331 | unsigned int flags2; |
a8f88ff5 JB |
332 | struct work_struct downshift_task; |
333 | struct work_struct update_phy_task; | |
41cec6f1 | 334 | struct work_struct print_hang_task; |
23606cf5 RW |
335 | |
336 | bool idle_check; | |
ff10e13c | 337 | int phy_hang_count; |
55aa6985 BA |
338 | |
339 | u16 tx_ring_count; | |
340 | u16 rx_ring_count; | |
b67e1913 BA |
341 | |
342 | struct hwtstamp_config hwtstamp_config; | |
343 | struct delayed_work systim_overflow_work; | |
344 | struct sk_buff *tx_hwtstamp_skb; | |
345 | struct work_struct tx_hwtstamp_work; | |
346 | spinlock_t systim_lock; /* protects SYSTIML/H regsters */ | |
347 | struct cyclecounter cc; | |
348 | struct timecounter tc; | |
d89777bf BA |
349 | struct ptp_clock *ptp_clock; |
350 | struct ptp_clock_info ptp_clock_info; | |
d495bcb8 BA |
351 | |
352 | u16 eee_advert; | |
bc7f75fa AK |
353 | }; |
354 | ||
355 | struct e1000_info { | |
356 | enum e1000_mac_type mac; | |
357 | unsigned int flags; | |
6f461f6c | 358 | unsigned int flags2; |
bc7f75fa | 359 | u32 pba; |
2adc55c9 | 360 | u32 max_hw_frame_size; |
69e3fd8c | 361 | s32 (*get_variants)(struct e1000_adapter *); |
8ce9d6c7 JK |
362 | const struct e1000_mac_operations *mac_ops; |
363 | const struct e1000_phy_operations *phy_ops; | |
364 | const struct e1000_nvm_operations *nvm_ops; | |
bc7f75fa AK |
365 | }; |
366 | ||
d89777bf BA |
367 | s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); |
368 | ||
b67e1913 BA |
369 | /* The system time is maintained by a 64-bit counter comprised of the 32-bit |
370 | * SYSTIMH and SYSTIML registers. How the counter increments (and therefore | |
371 | * its resolution) is based on the contents of the TIMINCA register - it | |
372 | * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). | |
373 | * For the best accuracy, the incperiod should be as small as possible. The | |
374 | * incvalue is scaled by a factor as large as possible (while still fitting | |
375 | * in bits 23:0) so that relatively small clock corrections can be made. | |
376 | * | |
377 | * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of | |
378 | * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) | |
379 | * bits to count nanoseconds leaving the rest for fractional nonseconds. | |
380 | */ | |
381 | #define INCVALUE_96MHz 125 | |
382 | #define INCVALUE_SHIFT_96MHz 17 | |
383 | #define INCPERIOD_SHIFT_96MHz 2 | |
384 | #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz) | |
385 | ||
386 | #define INCVALUE_25MHz 40 | |
387 | #define INCVALUE_SHIFT_25MHz 18 | |
388 | #define INCPERIOD_25MHz 1 | |
389 | ||
390 | /* Another drawback of scaling the incvalue by a large factor is the | |
391 | * 64-bit SYSTIM register overflows more quickly. This is dealt with | |
392 | * by simply reading the clock before it overflows. | |
393 | * | |
394 | * Clock ns bits Overflows after | |
395 | * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ | |
396 | * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs | |
397 | * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours | |
398 | */ | |
399 | #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) | |
400 | ||
bc7f75fa AK |
401 | /* hardware capability, feature, and workaround flags */ |
402 | #define FLAG_HAS_AMT (1 << 0) | |
403 | #define FLAG_HAS_FLASH (1 << 1) | |
404 | #define FLAG_HAS_HW_VLAN_FILTER (1 << 2) | |
405 | #define FLAG_HAS_WOL (1 << 3) | |
79d4e908 | 406 | /* reserved bit4 */ |
bc7f75fa AK |
407 | #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) |
408 | #define FLAG_HAS_SWSM_ON_LOAD (1 << 6) | |
409 | #define FLAG_HAS_JUMBO_FRAMES (1 << 7) | |
4a770358 | 410 | #define FLAG_READ_ONLY_NVM (1 << 8) |
97ac8cae | 411 | #define FLAG_IS_ICH (1 << 9) |
4662e82b | 412 | #define FLAG_HAS_MSIX (1 << 10) |
bc7f75fa AK |
413 | #define FLAG_HAS_SMART_POWER_DOWN (1 << 11) |
414 | #define FLAG_IS_QUAD_PORT_A (1 << 12) | |
415 | #define FLAG_IS_QUAD_PORT (1 << 13) | |
b67e1913 | 416 | #define FLAG_HAS_HW_TIMESTAMP (1 << 14) |
bc7f75fa AK |
417 | #define FLAG_APME_IN_WUC (1 << 15) |
418 | #define FLAG_APME_IN_CTRL3 (1 << 16) | |
419 | #define FLAG_APME_CHECK_PORT_B (1 << 17) | |
420 | #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) | |
421 | #define FLAG_NO_WAKE_UCAST (1 << 19) | |
422 | #define FLAG_MNG_PT_ENABLED (1 << 20) | |
423 | #define FLAG_RESET_OVERWRITES_LAA (1 << 21) | |
424 | #define FLAG_TARC_SPEED_MODE_BIT (1 << 22) | |
425 | #define FLAG_TARC_SET_BIT_ZERO (1 << 23) | |
426 | #define FLAG_RX_NEEDS_RESTART (1 << 24) | |
427 | #define FLAG_LSC_GIG_SPEED_DROP (1 << 25) | |
428 | #define FLAG_SMART_POWER_DOWN (1 << 26) | |
429 | #define FLAG_MSI_ENABLED (1 << 27) | |
dc221294 | 430 | /* reserved (1 << 28) */ |
bc7f75fa | 431 | #define FLAG_TSO_FORCE (1 << 29) |
12d43f7d | 432 | #define FLAG_RESTART_NOW (1 << 30) |
f8d59f78 | 433 | #define FLAG_MSI_TEST_FAILED (1 << 31) |
bc7f75fa | 434 | |
eb7c3adb | 435 | #define FLAG2_CRC_STRIPPING (1 << 0) |
a4f58f54 | 436 | #define FLAG2_HAS_PHY_WAKEUP (1 << 1) |
b94b5028 | 437 | #define FLAG2_IS_DISCARDING (1 << 2) |
6f461f6c | 438 | #define FLAG2_DISABLE_ASPM_L1 (1 << 3) |
8c7bbb92 | 439 | #define FLAG2_HAS_PHY_STATS (1 << 4) |
e52997f9 | 440 | #define FLAG2_HAS_EEE (1 << 5) |
3a3b7586 | 441 | #define FLAG2_DMA_BURST (1 << 6) |
78cd29d5 | 442 | #define FLAG2_DISABLE_ASPM_L0S (1 << 7) |
828bac87 | 443 | #define FLAG2_DISABLE_AIM (1 << 8) |
ff10e13c | 444 | #define FLAG2_CHECK_PHY_HANG (1 << 9) |
7f99ae63 | 445 | #define FLAG2_NO_DISABLE_RX (1 << 10) |
c6e7f51e | 446 | #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11) |
0184039a | 447 | #define FLAG2_DFLT_CRC_STRIPPING (1 << 12) |
b67e1913 | 448 | #define FLAG2_CHECK_RX_HWTSTAMP (1 << 13) |
eb7c3adb | 449 | |
bc7f75fa AK |
450 | #define E1000_RX_DESC_PS(R, i) \ |
451 | (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) | |
5f450212 BA |
452 | #define E1000_RX_DESC_EXT(R, i) \ |
453 | (&(((union e1000_rx_desc_extended *)((R).desc))[i])) | |
bc7f75fa | 454 | #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) |
bc7f75fa AK |
455 | #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) |
456 | #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) | |
457 | ||
458 | enum e1000_state_t { | |
459 | __E1000_TESTING, | |
460 | __E1000_RESETTING, | |
a90b412c | 461 | __E1000_ACCESS_SHARED_RESOURCE, |
bc7f75fa AK |
462 | __E1000_DOWN |
463 | }; | |
464 | ||
465 | enum latency_range { | |
466 | lowest_latency = 0, | |
467 | low_latency = 1, | |
468 | bulk_latency = 2, | |
469 | latency_invalid = 255 | |
470 | }; | |
471 | ||
472 | extern char e1000e_driver_name[]; | |
473 | extern const char e1000e_driver_version[]; | |
474 | ||
5ccc921a JP |
475 | void e1000e_check_options(struct e1000_adapter *adapter); |
476 | void e1000e_set_ethtool_ops(struct net_device *netdev); | |
477 | ||
478 | int e1000e_up(struct e1000_adapter *adapter); | |
479 | void e1000e_down(struct e1000_adapter *adapter); | |
480 | void e1000e_reinit_locked(struct e1000_adapter *adapter); | |
481 | void e1000e_reset(struct e1000_adapter *adapter); | |
482 | void e1000e_power_up_phy(struct e1000_adapter *adapter); | |
483 | int e1000e_setup_rx_resources(struct e1000_ring *ring); | |
484 | int e1000e_setup_tx_resources(struct e1000_ring *ring); | |
485 | void e1000e_free_rx_resources(struct e1000_ring *ring); | |
486 | void e1000e_free_tx_resources(struct e1000_ring *ring); | |
487 | struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, | |
488 | struct rtnl_link_stats64 *stats); | |
489 | void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); | |
490 | void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); | |
491 | void e1000e_get_hw_control(struct e1000_adapter *adapter); | |
492 | void e1000e_release_hw_control(struct e1000_adapter *adapter); | |
493 | void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); | |
bc7f75fa AK |
494 | |
495 | extern unsigned int copybreak; | |
496 | ||
8ce9d6c7 JK |
497 | extern const struct e1000_info e1000_82571_info; |
498 | extern const struct e1000_info e1000_82572_info; | |
499 | extern const struct e1000_info e1000_82573_info; | |
500 | extern const struct e1000_info e1000_82574_info; | |
501 | extern const struct e1000_info e1000_82583_info; | |
502 | extern const struct e1000_info e1000_ich8_info; | |
503 | extern const struct e1000_info e1000_ich9_info; | |
504 | extern const struct e1000_info e1000_ich10_info; | |
505 | extern const struct e1000_info e1000_pch_info; | |
506 | extern const struct e1000_info e1000_pch2_info; | |
2fbe4526 | 507 | extern const struct e1000_info e1000_pch_lpt_info; |
8ce9d6c7 | 508 | extern const struct e1000_info e1000_es2_info; |
bc7f75fa | 509 | |
5ccc921a JP |
510 | void e1000e_ptp_init(struct e1000_adapter *adapter); |
511 | void e1000e_ptp_remove(struct e1000_adapter *adapter); | |
0be84010 | 512 | |
bc7f75fa AK |
513 | static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) |
514 | { | |
94d8186a | 515 | return hw->phy.ops.reset(hw); |
bc7f75fa AK |
516 | } |
517 | ||
bc7f75fa AK |
518 | static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) |
519 | { | |
94d8186a | 520 | return hw->phy.ops.read_reg(hw, offset, data); |
bc7f75fa AK |
521 | } |
522 | ||
f1430d69 BA |
523 | static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
524 | { | |
525 | return hw->phy.ops.read_reg_locked(hw, offset, data); | |
526 | } | |
527 | ||
bc7f75fa AK |
528 | static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) |
529 | { | |
94d8186a | 530 | return hw->phy.ops.write_reg(hw, offset, data); |
bc7f75fa AK |
531 | } |
532 | ||
f1430d69 BA |
533 | static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) |
534 | { | |
535 | return hw->phy.ops.write_reg_locked(hw, offset, data); | |
536 | } | |
537 | ||
5ccc921a | 538 | void e1000e_reload_nvm_generic(struct e1000_hw *hw); |
608f8a0d BA |
539 | |
540 | static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) | |
541 | { | |
542 | if (hw->mac.ops.read_mac_addr) | |
543 | return hw->mac.ops.read_mac_addr(hw); | |
544 | ||
545 | return e1000_read_mac_addr_generic(hw); | |
546 | } | |
bc7f75fa AK |
547 | |
548 | static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) | |
549 | { | |
94d8186a | 550 | return hw->nvm.ops.validate(hw); |
bc7f75fa AK |
551 | } |
552 | ||
553 | static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) | |
554 | { | |
94d8186a | 555 | return hw->nvm.ops.update(hw); |
bc7f75fa AK |
556 | } |
557 | ||
c29c3ba5 BA |
558 | static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, |
559 | u16 *data) | |
bc7f75fa | 560 | { |
94d8186a | 561 | return hw->nvm.ops.read(hw, offset, words, data); |
bc7f75fa AK |
562 | } |
563 | ||
c29c3ba5 BA |
564 | static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, |
565 | u16 *data) | |
bc7f75fa | 566 | { |
94d8186a | 567 | return hw->nvm.ops.write(hw, offset, words, data); |
bc7f75fa AK |
568 | } |
569 | ||
570 | static inline s32 e1000_get_phy_info(struct e1000_hw *hw) | |
571 | { | |
94d8186a | 572 | return hw->phy.ops.get_info(hw); |
bc7f75fa AK |
573 | } |
574 | ||
bc7f75fa AK |
575 | static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) |
576 | { | |
577 | return readl(hw->hw_addr + reg); | |
578 | } | |
579 | ||
bdc125f7 BA |
580 | #define er32(reg) __er32(hw, E1000_##reg) |
581 | ||
582 | /** | |
583 | * __ew32_prepare - prepare to write to MAC CSR register on certain parts | |
584 | * @hw: pointer to the HW structure | |
585 | * | |
586 | * When updating the MAC CSR registers, the Manageability Engine (ME) could | |
587 | * be accessing the registers at the same time. Normally, this is handled in | |
588 | * h/w by an arbiter but on some parts there is a bug that acknowledges Host | |
589 | * accesses later than it should which could result in the register to have | |
590 | * an incorrect value. Workaround this by checking the FWSM register which | |
591 | * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set | |
592 | * and try again a number of times. | |
593 | **/ | |
594 | static inline s32 __ew32_prepare(struct e1000_hw *hw) | |
595 | { | |
596 | s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; | |
597 | ||
598 | while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) | |
2a437cd3 | 599 | udelay(50); |
bdc125f7 BA |
600 | |
601 | return i; | |
602 | } | |
603 | ||
bc7f75fa AK |
604 | static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) |
605 | { | |
bdc125f7 BA |
606 | if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) |
607 | __ew32_prepare(hw); | |
608 | ||
bc7f75fa AK |
609 | writel(val, hw->hw_addr + reg); |
610 | } | |
611 | ||
bdc125f7 BA |
612 | #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) |
613 | ||
614 | #define e1e_flush() er32(STATUS) | |
615 | ||
616 | #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ | |
617 | (__ew32((a), (reg + ((offset) << 2)), (value))) | |
618 | ||
619 | #define E1000_READ_REG_ARRAY(a, reg, offset) \ | |
620 | (readl((a)->hw_addr + reg + ((offset) << 2))) | |
621 | ||
bc7f75fa | 622 | #endif /* _E1000_H_ */ |