projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
e1000e: re-enable alternate MAC address for all devices which support it
[linux-2.6-block.git] / drivers / net / ethernet / intel / e1000e / e1000.h
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
0d6057e4 4 Copyright(c) 1999 - 2011 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _E1000_H_
32#define _E1000_H_
33
86d70e53 34#include <linux/bitops.h>
bc7f75fa
AK		 35#include <linux/types.h>
36#include <linux/timer.h>
37#include <linux/workqueue.h>
38#include <linux/io.h>
39#include <linux/netdevice.h>
d8014dbc 40#include <linux/pci.h>
6f461f6c 41#include <linux/pci-aspm.h>
fe46f58f 42#include <linux/crc32.h>
86d70e53 43#include <linux/if_vlan.h>
bc7f75fa
AK		 44
45#include "hw.h"
46
47struct e1000_info;
48
44defeb3 49#define e_dbg(format, arg...) \
8544b9f7 50 netdev_dbg(hw->adapter->netdev, format, ## arg)
44defeb3 51#define e_err(format, arg...) \
8544b9f7 52 netdev_err(adapter->netdev, format, ## arg)
44defeb3 53#define e_info(format, arg...) \
8544b9f7 54 netdev_info(adapter->netdev, format, ## arg)
44defeb3 55#define e_warn(format, arg...) \
8544b9f7 56 netdev_warn(adapter->netdev, format, ## arg)
44defeb3 57#define e_notice(format, arg...) \
8544b9f7 58 netdev_notice(adapter->netdev, format, ## arg)
bc7f75fa
AK		 59
60
98a1708d 61/* Interrupt modes, as used by the IntMode parameter */
4662e82b
BA		 62#define E1000E_INT_MODE_LEGACY 0
63#define E1000E_INT_MODE_MSI 1
64#define E1000E_INT_MODE_MSIX 2
65
ad68076e 66/* Tx/Rx descriptor defines */
bc7f75fa
AK		 67#define E1000_DEFAULT_TXD 256
68#define E1000_MAX_TXD 4096
7b1be198 69#define E1000_MIN_TXD 64
bc7f75fa
AK		 70
71#define E1000_DEFAULT_RXD 256
72#define E1000_MAX_RXD 4096
7b1be198 73#define E1000_MIN_RXD 64
bc7f75fa 74
de5b3077
AK		 75#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
76#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
77
bc7f75fa
AK		 78/* Early Receive defines */
79#define E1000_ERT_2048 0x100
80
81#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
82
83/* How many Tx Descriptors do we need to call netif_wake_queue ? */
84/* How many Rx Buffers do we bundle into one write to the hardware ? */
85#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
86
87#define AUTO_ALL_MODES 0
88#define E1000_EEPROM_APME 0x0400
89
90#define E1000_MNG_VLAN_NONE (-1)
91
92/* Number of packet split data buffers (not including the header buffer) */
93#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
94
2adc55c9
BA		 95#define DEFAULT_JUMBO 9234
96
a4f58f54
BA		 97/* BM/HV Specific Registers */
98#define BM_PORT_CTRL_PAGE 769
99
100#define PHY_UPPER_SHIFT 21
101#define BM_PHY_REG(page, reg) \
102 (((reg) & MAX_PHY_REG_ADDRESS) |\
103 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
104 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
105
106/* PHY Wakeup Registers and defines */
3ebfc7c9 107#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
a4f58f54
BA		 108#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
109#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
110#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
111#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
112#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
113#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
114#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
115#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
116#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
117
118#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
119#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
120#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
121#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
122#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
123#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
124#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
125
2b6b168d
BA		 126#define HV_STATS_PAGE 778
127#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
128#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
129#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
130#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
131#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
132#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
133#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
134#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
135#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
136#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
137#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
138#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
139#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
140#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
a4f58f54 141
38eb394e
BA		 142#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
143
1d5846b9
BA		 144/* BM PHY Copper Specific Status */
145#define BM_CS_STATUS 17
146#define BM_CS_STATUS_LINK_UP 0x0400
147#define BM_CS_STATUS_RESOLVED 0x0800
148#define BM_CS_STATUS_SPEED_MASK 0xC000
149#define BM_CS_STATUS_SPEED_1000 0x8000
150
151/* 82577 Mobile Phy Status Register */
152#define HV_M_STATUS 26
153#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
154#define HV_M_STATUS_SPEED_MASK 0x0300
155#define HV_M_STATUS_SPEED_1000 0x0200
156#define HV_M_STATUS_LINK_UP 0x0040
157
c6e7f51e
BA		 158#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
159#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
160
23606cf5
RW		 161/* Time to wait before putting the device into D3 if there's no link (in ms). */
162#define LINK_TIMEOUT 100
163
3a3b7586
JB		 164#define DEFAULT_RDTR 0
165#define DEFAULT_RADV 8
166#define BURST_RDTR 0x20
167#define BURST_RADV 0x20
168
169/*
170 * in the case of WTHRESH, it appears at least the 82571/2 hardware
171 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
172 * WTHRESH=4, and since we want 64 bytes at a time written back, set
173 * it to 5
174 */
175#define E1000_TXDCTL_DMA_BURST_ENABLE \
176 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
177 E1000_TXDCTL_COUNT_DESC | \
178 (5 << 16) | /* wthresh must be +1 more than desired */\
179 (1 << 8) | /* hthresh */ \
180 0x1f) /* pthresh */
181
182#define E1000_RXDCTL_DMA_BURST_ENABLE \
183 (0x01000000 | /* set descriptor granularity */ \
184 (4 << 16) | /* set writeback threshold */ \
185 (4 << 8) | /* set prefetch threshold */ \
186 0x20) /* set hthresh */
187
188#define E1000_TIDV_FPD (1 << 31)
189#define E1000_RDTR_FPD (1 << 31)
190
bc7f75fa
AK		 191enum e1000_boards {
192 board_82571,
193 board_82572,
194 board_82573,
4662e82b 195 board_82574,
8c81c9c3 196 board_82583,
bc7f75fa
AK		 197 board_80003es2lan,
198 board_ich8lan,
199 board_ich9lan,
f4187b56 200 board_ich10lan,
a4f58f54 201 board_pchlan,
d3738bb8 202 board_pch2lan,
bc7f75fa
AK		 203};
204
bc7f75fa
AK		 205struct e1000_ps_page {
206 struct page *page;
207 u64 dma; /* must be u64 - written to hw */
208};
209
210/*
211 * wrappers around a pointer to a socket buffer,
212 * so a DMA handle can be stored along with the buffer
213 */
214struct e1000_buffer {
215 dma_addr_t dma;
216 struct sk_buff *skb;
217 union {
ad68076e 218 /* Tx */
bc7f75fa
AK		 219 struct {
220 unsigned long time_stamp;
221 u16 length;
222 u16 next_to_watch;
9ed318d5
TH		 223 unsigned int segs;
224 unsigned int bytecount;
03b1320d 225 u16 mapped_as_page;
bc7f75fa 226 };
ad68076e 227 /* Rx */
03b1320d
AD		 228 struct {
229 /* arrays of page information for packet split */
230 struct e1000_ps_page *ps_pages;
231 struct page *page;
232 };
bc7f75fa 233 };
bc7f75fa
AK		 234};
235
236struct e1000_ring {
237 void *desc; /* pointer to ring memory */
238 dma_addr_t dma; /* phys address of ring */
239 unsigned int size; /* length of ring in bytes */
240 unsigned int count; /* number of desc. in ring */
241
242 u16 next_to_use;
243 u16 next_to_clean;
244
245 u16 head;
246 u16 tail;
247
248 /* array of buffer information structs */
249 struct e1000_buffer *buffer_info;
250
4662e82b
BA		 251 char name[IFNAMSIZ + 5];
252 u32 ims_val;
253 u32 itr_val;
254 u16 itr_register;
255 int set_itr;
256
bc7f75fa 257 struct sk_buff *rx_skb_top;
bc7f75fa
AK		 258};
259
7c25769f
BA		 260/* PHY register snapshot values */
261struct e1000_phy_regs {
262 u16 bmcr; /* basic mode control register */
263 u16 bmsr; /* basic mode status register */
264 u16 advertise; /* auto-negotiation advertisement */
265 u16 lpa; /* link partner ability register */
266 u16 expansion; /* auto-negotiation expansion reg */
267 u16 ctrl1000; /* 1000BASE-T control register */
268 u16 stat1000; /* 1000BASE-T status register */
269 u16 estatus; /* extended status register */
270};
271
bc7f75fa
AK		 272/* board specific private data structure */
273struct e1000_adapter {
274 struct timer_list watchdog_timer;
275 struct timer_list phy_info_timer;
276 struct timer_list blink_timer;
277
278 struct work_struct reset_task;
279 struct work_struct watchdog_task;
280
281 const struct e1000_info *ei;
282
86d70e53 283 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
bc7f75fa
AK		 284 u32 bd_number;
285 u32 rx_buffer_len;
286 u16 mng_vlan_id;
287 u16 link_speed;
288 u16 link_duplex;
84527590 289 u16 eeprom_vers;
bc7f75fa 290
bc7f75fa
AK		 291 /* track device up/down/testing state */
292 unsigned long state;
293
294 /* Interrupt Throttle Rate */
295 u32 itr;
296 u32 itr_setting;
297 u16 tx_itr;
298 u16 rx_itr;
299
300 /*
ad68076e 301 * Tx
bc7f75fa
AK		 302 */
303 struct e1000_ring *tx_ring /* One per active queue */
304 ____cacheline_aligned_in_smp;
305
306 struct napi_struct napi;
307
bc7f75fa
AK		 308 unsigned int restart_queue;
309 u32 txd_cmd;
310
311 bool detect_tx_hung;
09357b00 312 bool tx_hang_recheck;
bc7f75fa
AK		 313 u8 tx_timeout_factor;
314
315 u32 tx_int_delay;
316 u32 tx_abs_int_delay;
317
318 unsigned int total_tx_bytes;
319 unsigned int total_tx_packets;
320 unsigned int total_rx_bytes;
321 unsigned int total_rx_packets;
322
ad68076e 323 /* Tx stats */
bc7f75fa
AK		 324 u64 tpt_old;
325 u64 colc_old;
7c25769f
BA		 326 u32 gotc;
327 u64 gotc_old;
bc7f75fa
AK		 328 u32 tx_timeout_count;
329 u32 tx_fifo_head;
330 u32 tx_head_addr;
331 u32 tx_fifo_size;
332 u32 tx_dma_failed;
333
334 /*
ad68076e 335 * Rx
bc7f75fa
AK		 336 */
337 bool (*clean_rx) (struct e1000_adapter *adapter,
338 int *work_done, int work_to_do)
339 ____cacheline_aligned_in_smp;
340 void (*alloc_rx_buf) (struct e1000_adapter *adapter,
c2fed996 341 int cleaned_count, gfp_t gfp);
bc7f75fa
AK		 342 struct e1000_ring *rx_ring;
343
344 u32 rx_int_delay;
345 u32 rx_abs_int_delay;
346
ad68076e 347 /* Rx stats */
bc7f75fa
AK		 348 u64 hw_csum_err;
349 u64 hw_csum_good;
350 u64 rx_hdr_split;
7c25769f
BA		 351 u32 gorc;
352 u64 gorc_old;
bc7f75fa
AK		 353 u32 alloc_rx_buff_failed;
354 u32 rx_dma_failed;
355
356 unsigned int rx_ps_pages;
357 u16 rx_ps_bsize0;
318a94d6
JK		 358 u32 max_frame_size;
359 u32 min_frame_size;
bc7f75fa
AK		 360
361 /* OS defined structs */
362 struct net_device *netdev;
363 struct pci_dev *pdev;
bc7f75fa
AK		 364
365 /* structs defined in e1000_hw.h */
366 struct e1000_hw hw;
367
67fd4fcb 368 spinlock_t stats64_lock;
bc7f75fa
AK		 369 struct e1000_hw_stats stats;
370 struct e1000_phy_info phy_info;
371 struct e1000_phy_stats phy_stats;
372
7c25769f
BA		 373 /* Snapshot of PHY registers */
374 struct e1000_phy_regs phy_regs;
375
bc7f75fa
AK		 376 struct e1000_ring test_tx_ring;
377 struct e1000_ring test_rx_ring;
378 u32 test_icr;
379
380 u32 msg_enable;
8e86acd7 381 unsigned int num_vectors;
4662e82b
BA		 382 struct msix_entry *msix_entries;
383 int int_mode;
384 u32 eiac_mask;
bc7f75fa
AK		 385
386 u32 eeprom_wol;
387 u32 wol;
388 u32 pba;
2adc55c9 389 u32 max_hw_frame_size;
bc7f75fa 390
318a94d6 391 bool fc_autoneg;
bc7f75fa 392
bc7f75fa 393 unsigned int flags;
eb7c3adb 394 unsigned int flags2;
a8f88ff5
JB		 395 struct work_struct downshift_task;
396 struct work_struct update_phy_task;
41cec6f1 397 struct work_struct print_hang_task;
23606cf5
RW		 398
399 bool idle_check;
ff10e13c 400 int phy_hang_count;
bc7f75fa
AK		 401};
402
403struct e1000_info {
404 enum e1000_mac_type mac;
405 unsigned int flags;
6f461f6c 406 unsigned int flags2;
bc7f75fa 407 u32 pba;
2adc55c9 408 u32 max_hw_frame_size;
69e3fd8c 409 s32 (*get_variants)(struct e1000_adapter *);
8ce9d6c7
JK		 410 const struct e1000_mac_operations *mac_ops;
411 const struct e1000_phy_operations *phy_ops;
412 const struct e1000_nvm_operations *nvm_ops;
bc7f75fa
AK		 413};
414
415/* hardware capability, feature, and workaround flags */
416#define FLAG_HAS_AMT (1 << 0)
417#define FLAG_HAS_FLASH (1 << 1)
418#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
419#define FLAG_HAS_WOL (1 << 3)
420#define FLAG_HAS_ERT (1 << 4)
421#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
422#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
423#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
4a770358 424#define FLAG_READ_ONLY_NVM (1 << 8)
97ac8cae 425#define FLAG_IS_ICH (1 << 9)
4662e82b 426#define FLAG_HAS_MSIX (1 << 10)
bc7f75fa
AK		 427#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
428#define FLAG_IS_QUAD_PORT_A (1 << 12)
429#define FLAG_IS_QUAD_PORT (1 << 13)
430#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14)
431#define FLAG_APME_IN_WUC (1 << 15)
432#define FLAG_APME_IN_CTRL3 (1 << 16)
433#define FLAG_APME_CHECK_PORT_B (1 << 17)
434#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
435#define FLAG_NO_WAKE_UCAST (1 << 19)
436#define FLAG_MNG_PT_ENABLED (1 << 20)
437#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
438#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
439#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
440#define FLAG_RX_NEEDS_RESTART (1 << 24)
441#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
442#define FLAG_SMART_POWER_DOWN (1 << 26)
443#define FLAG_MSI_ENABLED (1 << 27)
dc221294 444/* reserved (1 << 28) */
bc7f75fa 445#define FLAG_TSO_FORCE (1 << 29)
318a94d6 446#define FLAG_RX_RESTART_NOW (1 << 30)
f8d59f78 447#define FLAG_MSI_TEST_FAILED (1 << 31)
bc7f75fa 448
eb7c3adb 449#define FLAG2_CRC_STRIPPING (1 << 0)
a4f58f54 450#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
b94b5028 451#define FLAG2_IS_DISCARDING (1 << 2)
6f461f6c 452#define FLAG2_DISABLE_ASPM_L1 (1 << 3)
8c7bbb92 453#define FLAG2_HAS_PHY_STATS (1 << 4)
e52997f9 454#define FLAG2_HAS_EEE (1 << 5)
3a3b7586 455#define FLAG2_DMA_BURST (1 << 6)
78cd29d5 456#define FLAG2_DISABLE_ASPM_L0S (1 << 7)
828bac87 457#define FLAG2_DISABLE_AIM (1 << 8)
ff10e13c 458#define FLAG2_CHECK_PHY_HANG (1 << 9)
7f99ae63 459#define FLAG2_NO_DISABLE_RX (1 << 10)
c6e7f51e 460#define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
eb7c3adb 461
bc7f75fa
AK		 462#define E1000_RX_DESC_PS(R, i) \
463 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
5f450212
BA		 464#define E1000_RX_DESC_EXT(R, i) \
465 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
bc7f75fa 466#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
bc7f75fa
AK		 467#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
468#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
469
470enum e1000_state_t {
471 __E1000_TESTING,
472 __E1000_RESETTING,
a90b412c 473 __E1000_ACCESS_SHARED_RESOURCE,
bc7f75fa
AK		 474 __E1000_DOWN
475};
476
477enum latency_range {
478 lowest_latency = 0,
479 low_latency = 1,
480 bulk_latency = 2,
481 latency_invalid = 255
482};
483
484extern char e1000e_driver_name[];
485extern const char e1000e_driver_version[];
486
487extern void e1000e_check_options(struct e1000_adapter *adapter);
488extern void e1000e_set_ethtool_ops(struct net_device *netdev);
489
490extern int e1000e_up(struct e1000_adapter *adapter);
491extern void e1000e_down(struct e1000_adapter *adapter);
492extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
493extern void e1000e_reset(struct e1000_adapter *adapter);
494extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
495extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);
496extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);
497extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);
498extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
67fd4fcb
JK		 499extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
500 struct rtnl_link_stats64
501 *stats);
4662e82b
BA		 502extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
503extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
31dbe5b4
BA		 504extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
505extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
bc7f75fa
AK		 506
507extern unsigned int copybreak;
508
509extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
510
8ce9d6c7
JK		 511extern const struct e1000_info e1000_82571_info;
512extern const struct e1000_info e1000_82572_info;
513extern const struct e1000_info e1000_82573_info;
514extern const struct e1000_info e1000_82574_info;
515extern const struct e1000_info e1000_82583_info;
516extern const struct e1000_info e1000_ich8_info;
517extern const struct e1000_info e1000_ich9_info;
518extern const struct e1000_info e1000_ich10_info;
519extern const struct e1000_info e1000_pch_info;
520extern const struct e1000_info e1000_pch2_info;
521extern const struct e1000_info e1000_es2_info;
bc7f75fa 522
073287c0
BA		 523extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
524 u32 pba_num_size);
bc7f75fa
AK		 525
526extern s32 e1000e_commit_phy(struct e1000_hw *hw);
527
528extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
529
530extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
531extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
532
4a770358 533extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 534extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
535 bool state);
536extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
537extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
99730e4c
BA		 538extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
539extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
bb436b20 540extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
d3738bb8
BA		 541extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
542extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 543
544extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
545extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
546extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
a4f58f54 547extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
bc7f75fa
AK		 548extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
549extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
550extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
551extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
f4d2dd4c
BA		 552extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
553extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
bc7f75fa
AK		 554extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
555extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
556extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
557extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
558extern s32 e1000e_id_led_init(struct e1000_hw *hw);
559extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
560extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
561extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
562extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
563extern s32 e1000e_setup_link(struct e1000_hw *hw);
caaddaf8 564extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
bc7f75fa 565extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
e2de3eb6
JK		 566extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
567 u8 *mc_addr_list,
ab8932f3 568 u32 mc_addr_count);
bc7f75fa
AK		 569extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
570extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
571extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
572extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
573extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
574extern void e1000e_config_collision_dist(struct e1000_hw *hw);
575extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
576extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
dbf80dcb 577extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
caaddaf8 578extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
608f8a0d 579extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
bc7f75fa
AK		 580extern void e1000e_reset_adaptive(struct e1000_hw *hw);
581extern void e1000e_update_adaptive(struct e1000_hw *hw);
582
583extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
584extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
585extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
586extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
587extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
588extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
589extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
2b6b168d 590extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
bc7f75fa 591extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 592extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
593 u16 *data);
bc7f75fa
AK		 594extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
595extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
596extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 597extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
598 u16 data);
bc7f75fa
AK		 599extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
600extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
601extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
602extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
603extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
604extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
605extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
f4187b56 606extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
bc7f75fa 607extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
97ac8cae
BA		 608extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
609extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
610extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
2b6b168d
BA		 611extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
612 u16 *phy_reg);
613extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
614 u16 *phy_reg);
4662e82b
BA		 615extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
616extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa
AK		 617extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
618extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 619extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
620 u16 data);
bc7f75fa 621extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 622extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
623 u16 *data);
bc7f75fa
AK		 624extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
625 u32 usec_interval, bool *success);
626extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
17f208de
BA		 627extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
628extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
2d9498f3
DG		 629extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
630extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa 631extern s32 e1000e_check_downshift(struct e1000_hw *hw);
a4f58f54 632extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 633extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
634 u16 *data);
2b6b168d
BA		 635extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
636 u16 *data);
a4f58f54 637extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 638extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
639 u16 data);
2b6b168d
BA		 640extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
641 u16 data);
a4f58f54
BA		 642extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
643extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
644extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
645extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
646extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
647extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
bc7f75fa 648
0be84010
BA		 649extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
650extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
651extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
652extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
653extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
ff10e13c 654extern bool e1000_check_phy_82574(struct e1000_hw *hw);
0be84010 655
bc7f75fa
AK		 656static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
657{
94d8186a 658 return hw->phy.ops.reset(hw);
bc7f75fa
AK		 659}
660
661static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
662{
663 return hw->phy.ops.check_reset_block(hw);
664}
665
666static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
667{
94d8186a 668 return hw->phy.ops.read_reg(hw, offset, data);
bc7f75fa
AK		 669}
670
671static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
672{
94d8186a 673 return hw->phy.ops.write_reg(hw, offset, data);
bc7f75fa
AK		 674}
675
676static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
677{
678 return hw->phy.ops.get_cable_length(hw);
679}
680
681extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
682extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
683extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
684extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
bc7f75fa
AK		 685extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
686extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
687extern void e1000e_release_nvm(struct e1000_hw *hw);
688extern void e1000e_reload_nvm(struct e1000_hw *hw);
608f8a0d
BA		 689extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
690
691static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
692{
693 if (hw->mac.ops.read_mac_addr)
694 return hw->mac.ops.read_mac_addr(hw);
695
696 return e1000_read_mac_addr_generic(hw);
697}
bc7f75fa
AK		 698
699static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
700{
94d8186a 701 return hw->nvm.ops.validate(hw);
bc7f75fa
AK		 702}
703
704static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
705{
94d8186a 706 return hw->nvm.ops.update(hw);
bc7f75fa
AK		 707}
708
709static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
710{
94d8186a 711 return hw->nvm.ops.read(hw, offset, words, data);
bc7f75fa
AK		 712}
713
714static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
715{
94d8186a 716 return hw->nvm.ops.write(hw, offset, words, data);
bc7f75fa
AK		 717}
718
719static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
720{
94d8186a 721 return hw->phy.ops.get_info(hw);
bc7f75fa
AK		 722}
723
4662e82b
BA		 724static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw)
725{
726 return hw->mac.ops.check_mng_mode(hw);
727}
728
729extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
bc7f75fa
AK		 730extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
731extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
732
733static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
734{
735 return readl(hw->hw_addr + reg);
736}
737
738static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
739{
740 writel(val, hw->hw_addr + reg);
741}
742
743#endif /* _E1000_H_ */
Linux 6.x block layer and io_uring tree(s)