e1000e: Cleanup to fix checkpatch missing blank lines
[linux-2.6-block.git] / drivers / net / ethernet / intel / e1000e / e1000.h
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1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
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21
22/* Linux PRO/1000 Ethernet Driver main header file */
23
24#ifndef _E1000_H_
25#define _E1000_H_
26
86d70e53 27#include <linux/bitops.h>
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28#include <linux/types.h>
29#include <linux/timer.h>
30#include <linux/workqueue.h>
31#include <linux/io.h>
32#include <linux/netdevice.h>
d8014dbc 33#include <linux/pci.h>
6f461f6c 34#include <linux/pci-aspm.h>
fe46f58f 35#include <linux/crc32.h>
86d70e53 36#include <linux/if_vlan.h>
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37#include <linux/clocksource.h>
38#include <linux/net_tstamp.h>
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39#include <linux/ptp_clock_kernel.h>
40#include <linux/ptp_classify.h>
c2ade1a4 41#include <linux/mii.h>
d495bcb8 42#include <linux/mdio.h>
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43#include "hw.h"
44
45struct e1000_info;
46
44defeb3 47#define e_dbg(format, arg...) \
8544b9f7 48 netdev_dbg(hw->adapter->netdev, format, ## arg)
44defeb3 49#define e_err(format, arg...) \
8544b9f7 50 netdev_err(adapter->netdev, format, ## arg)
44defeb3 51#define e_info(format, arg...) \
8544b9f7 52 netdev_info(adapter->netdev, format, ## arg)
44defeb3 53#define e_warn(format, arg...) \
8544b9f7 54 netdev_warn(adapter->netdev, format, ## arg)
44defeb3 55#define e_notice(format, arg...) \
8544b9f7 56 netdev_notice(adapter->netdev, format, ## arg)
bc7f75fa 57
98a1708d 58/* Interrupt modes, as used by the IntMode parameter */
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59#define E1000E_INT_MODE_LEGACY 0
60#define E1000E_INT_MODE_MSI 1
61#define E1000E_INT_MODE_MSIX 2
62
ad68076e 63/* Tx/Rx descriptor defines */
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64#define E1000_DEFAULT_TXD 256
65#define E1000_MAX_TXD 4096
7b1be198 66#define E1000_MIN_TXD 64
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67
68#define E1000_DEFAULT_RXD 256
69#define E1000_MAX_RXD 4096
7b1be198 70#define E1000_MIN_RXD 64
bc7f75fa 71
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72#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
73#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
74
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75#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
76
77/* How many Tx Descriptors do we need to call netif_wake_queue ? */
78/* How many Rx Buffers do we bundle into one write to the hardware ? */
79#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
80
81#define AUTO_ALL_MODES 0
82#define E1000_EEPROM_APME 0x0400
83
84#define E1000_MNG_VLAN_NONE (-1)
85
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86#define DEFAULT_JUMBO 9234
87
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88/* Time to wait before putting the device into D3 if there's no link (in ms). */
89#define LINK_TIMEOUT 100
90
e921eb1a 91/* Count for polling __E1000_RESET condition every 10-20msec.
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92 * Experimentation has shown the reset can take approximately 210msec.
93 */
94#define E1000_CHECK_RESET_COUNT 25
95
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96#define DEFAULT_RDTR 0
97#define DEFAULT_RADV 8
98#define BURST_RDTR 0x20
99#define BURST_RADV 0x20
100
e921eb1a 101/* in the case of WTHRESH, it appears at least the 82571/2 hardware
3a3b7586 102 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
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103 * WTHRESH=4, so a setting of 5 gives the most efficient bus
104 * utilization but to avoid possible Tx stalls, set it to 1
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105 */
106#define E1000_TXDCTL_DMA_BURST_ENABLE \
107 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
108 E1000_TXDCTL_COUNT_DESC | \
8edc0e62 109 (1 << 16) | /* wthresh must be +1 more than desired */\
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110 (1 << 8) | /* hthresh */ \
111 0x1f) /* pthresh */
112
113#define E1000_RXDCTL_DMA_BURST_ENABLE \
114 (0x01000000 | /* set descriptor granularity */ \
115 (4 << 16) | /* set writeback threshold */ \
116 (4 << 8) | /* set prefetch threshold */ \
117 0x20) /* set hthresh */
118
119#define E1000_TIDV_FPD (1 << 31)
120#define E1000_RDTR_FPD (1 << 31)
121
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122enum e1000_boards {
123 board_82571,
124 board_82572,
125 board_82573,
4662e82b 126 board_82574,
8c81c9c3 127 board_82583,
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128 board_80003es2lan,
129 board_ich8lan,
130 board_ich9lan,
f4187b56 131 board_ich10lan,
a4f58f54 132 board_pchlan,
d3738bb8 133 board_pch2lan,
2fbe4526 134 board_pch_lpt,
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135};
136
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137struct e1000_ps_page {
138 struct page *page;
139 u64 dma; /* must be u64 - written to hw */
140};
141
e921eb1a 142/* wrappers around a pointer to a socket buffer,
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143 * so a DMA handle can be stored along with the buffer
144 */
145struct e1000_buffer {
146 dma_addr_t dma;
147 struct sk_buff *skb;
148 union {
ad68076e 149 /* Tx */
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150 struct {
151 unsigned long time_stamp;
152 u16 length;
153 u16 next_to_watch;
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154 unsigned int segs;
155 unsigned int bytecount;
03b1320d 156 u16 mapped_as_page;
bc7f75fa 157 };
ad68076e 158 /* Rx */
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159 struct {
160 /* arrays of page information for packet split */
161 struct e1000_ps_page *ps_pages;
162 struct page *page;
163 };
bc7f75fa 164 };
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165};
166
167struct e1000_ring {
55aa6985 168 struct e1000_adapter *adapter; /* back pointer to adapter */
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169 void *desc; /* pointer to ring memory */
170 dma_addr_t dma; /* phys address of ring */
171 unsigned int size; /* length of ring in bytes */
172 unsigned int count; /* number of desc. in ring */
173
174 u16 next_to_use;
175 u16 next_to_clean;
176
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177 void __iomem *head;
178 void __iomem *tail;
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179
180 /* array of buffer information structs */
181 struct e1000_buffer *buffer_info;
182
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183 char name[IFNAMSIZ + 5];
184 u32 ims_val;
185 u32 itr_val;
c5083cf6 186 void __iomem *itr_register;
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187 int set_itr;
188
bc7f75fa 189 struct sk_buff *rx_skb_top;
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190};
191
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192/* PHY register snapshot values */
193struct e1000_phy_regs {
194 u16 bmcr; /* basic mode control register */
195 u16 bmsr; /* basic mode status register */
196 u16 advertise; /* auto-negotiation advertisement */
197 u16 lpa; /* link partner ability register */
198 u16 expansion; /* auto-negotiation expansion reg */
199 u16 ctrl1000; /* 1000BASE-T control register */
200 u16 stat1000; /* 1000BASE-T status register */
201 u16 estatus; /* extended status register */
202};
203
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204/* board specific private data structure */
205struct e1000_adapter {
206 struct timer_list watchdog_timer;
207 struct timer_list phy_info_timer;
208 struct timer_list blink_timer;
209
210 struct work_struct reset_task;
211 struct work_struct watchdog_task;
212
213 const struct e1000_info *ei;
214
86d70e53 215 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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216 u32 bd_number;
217 u32 rx_buffer_len;
218 u16 mng_vlan_id;
219 u16 link_speed;
220 u16 link_duplex;
84527590 221 u16 eeprom_vers;
bc7f75fa 222
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223 /* track device up/down/testing state */
224 unsigned long state;
225
226 /* Interrupt Throttle Rate */
227 u32 itr;
228 u32 itr_setting;
229 u16 tx_itr;
230 u16 rx_itr;
231
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232 /* Tx - one ring per active queue */
233 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
d821a4c4 234 u32 tx_fifo_limit;
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235
236 struct napi_struct napi;
237
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238 unsigned int uncorr_errors; /* uncorrectable ECC errors */
239 unsigned int corr_errors; /* correctable ECC errors */
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240 unsigned int restart_queue;
241 u32 txd_cmd;
242
243 bool detect_tx_hung;
09357b00 244 bool tx_hang_recheck;
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245 u8 tx_timeout_factor;
246
247 u32 tx_int_delay;
248 u32 tx_abs_int_delay;
249
250 unsigned int total_tx_bytes;
251 unsigned int total_tx_packets;
252 unsigned int total_rx_bytes;
253 unsigned int total_rx_packets;
254
ad68076e 255 /* Tx stats */
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256 u64 tpt_old;
257 u64 colc_old;
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258 u32 gotc;
259 u64 gotc_old;
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260 u32 tx_timeout_count;
261 u32 tx_fifo_head;
262 u32 tx_head_addr;
263 u32 tx_fifo_size;
264 u32 tx_dma_failed;
59c871c5 265 u32 tx_hwtstamp_timeouts;
bc7f75fa 266
e921eb1a 267 /* Rx */
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268 bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
269 int work_to_do) ____cacheline_aligned_in_smp;
270 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
271 gfp_t gfp);
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272 struct e1000_ring *rx_ring;
273
274 u32 rx_int_delay;
275 u32 rx_abs_int_delay;
276
ad68076e 277 /* Rx stats */
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278 u64 hw_csum_err;
279 u64 hw_csum_good;
280 u64 rx_hdr_split;
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281 u32 gorc;
282 u64 gorc_old;
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283 u32 alloc_rx_buff_failed;
284 u32 rx_dma_failed;
b67e1913 285 u32 rx_hwtstamp_cleared;
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286
287 unsigned int rx_ps_pages;
288 u16 rx_ps_bsize0;
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289 u32 max_frame_size;
290 u32 min_frame_size;
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291
292 /* OS defined structs */
293 struct net_device *netdev;
294 struct pci_dev *pdev;
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295
296 /* structs defined in e1000_hw.h */
297 struct e1000_hw hw;
298
9d57088b 299 spinlock_t stats64_lock; /* protects statistics counters */
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300 struct e1000_hw_stats stats;
301 struct e1000_phy_info phy_info;
302 struct e1000_phy_stats phy_stats;
303
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304 /* Snapshot of PHY registers */
305 struct e1000_phy_regs phy_regs;
306
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307 struct e1000_ring test_tx_ring;
308 struct e1000_ring test_rx_ring;
309 u32 test_icr;
310
311 u32 msg_enable;
8e86acd7 312 unsigned int num_vectors;
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313 struct msix_entry *msix_entries;
314 int int_mode;
315 u32 eiac_mask;
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316
317 u32 eeprom_wol;
318 u32 wol;
319 u32 pba;
2adc55c9 320 u32 max_hw_frame_size;
bc7f75fa 321
318a94d6 322 bool fc_autoneg;
bc7f75fa 323
bc7f75fa 324 unsigned int flags;
eb7c3adb 325 unsigned int flags2;
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326 struct work_struct downshift_task;
327 struct work_struct update_phy_task;
41cec6f1 328 struct work_struct print_hang_task;
23606cf5 329
ff10e13c 330 int phy_hang_count;
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331
332 u16 tx_ring_count;
333 u16 rx_ring_count;
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334
335 struct hwtstamp_config hwtstamp_config;
336 struct delayed_work systim_overflow_work;
337 struct sk_buff *tx_hwtstamp_skb;
59c871c5 338 unsigned long tx_hwtstamp_start;
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339 struct work_struct tx_hwtstamp_work;
340 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
341 struct cyclecounter cc;
342 struct timecounter tc;
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343 struct ptp_clock *ptp_clock;
344 struct ptp_clock_info ptp_clock_info;
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345
346 u16 eee_advert;
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347};
348
349struct e1000_info {
350 enum e1000_mac_type mac;
351 unsigned int flags;
6f461f6c 352 unsigned int flags2;
bc7f75fa 353 u32 pba;
2adc55c9 354 u32 max_hw_frame_size;
69e3fd8c 355 s32 (*get_variants)(struct e1000_adapter *);
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356 const struct e1000_mac_operations *mac_ops;
357 const struct e1000_phy_operations *phy_ops;
358 const struct e1000_nvm_operations *nvm_ops;
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359};
360
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361s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
362
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363/* The system time is maintained by a 64-bit counter comprised of the 32-bit
364 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
365 * its resolution) is based on the contents of the TIMINCA register - it
366 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
367 * For the best accuracy, the incperiod should be as small as possible. The
368 * incvalue is scaled by a factor as large as possible (while still fitting
369 * in bits 23:0) so that relatively small clock corrections can be made.
370 *
371 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
372 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
373 * bits to count nanoseconds leaving the rest for fractional nonseconds.
374 */
375#define INCVALUE_96MHz 125
376#define INCVALUE_SHIFT_96MHz 17
377#define INCPERIOD_SHIFT_96MHz 2
378#define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz)
379
380#define INCVALUE_25MHz 40
381#define INCVALUE_SHIFT_25MHz 18
382#define INCPERIOD_25MHz 1
383
384/* Another drawback of scaling the incvalue by a large factor is the
385 * 64-bit SYSTIM register overflows more quickly. This is dealt with
386 * by simply reading the clock before it overflows.
387 *
388 * Clock ns bits Overflows after
389 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
390 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
391 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
392 */
393#define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
394
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395/* hardware capability, feature, and workaround flags */
396#define FLAG_HAS_AMT (1 << 0)
397#define FLAG_HAS_FLASH (1 << 1)
398#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
399#define FLAG_HAS_WOL (1 << 3)
79d4e908 400/* reserved bit4 */
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401#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
402#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
403#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
4a770358 404#define FLAG_READ_ONLY_NVM (1 << 8)
97ac8cae 405#define FLAG_IS_ICH (1 << 9)
4662e82b 406#define FLAG_HAS_MSIX (1 << 10)
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407#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
408#define FLAG_IS_QUAD_PORT_A (1 << 12)
409#define FLAG_IS_QUAD_PORT (1 << 13)
b67e1913 410#define FLAG_HAS_HW_TIMESTAMP (1 << 14)
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411#define FLAG_APME_IN_WUC (1 << 15)
412#define FLAG_APME_IN_CTRL3 (1 << 16)
413#define FLAG_APME_CHECK_PORT_B (1 << 17)
414#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
415#define FLAG_NO_WAKE_UCAST (1 << 19)
416#define FLAG_MNG_PT_ENABLED (1 << 20)
417#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
418#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
419#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
420#define FLAG_RX_NEEDS_RESTART (1 << 24)
421#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
422#define FLAG_SMART_POWER_DOWN (1 << 26)
423#define FLAG_MSI_ENABLED (1 << 27)
dc221294 424/* reserved (1 << 28) */
bc7f75fa 425#define FLAG_TSO_FORCE (1 << 29)
12d43f7d 426#define FLAG_RESTART_NOW (1 << 30)
f8d59f78 427#define FLAG_MSI_TEST_FAILED (1 << 31)
bc7f75fa 428
eb7c3adb 429#define FLAG2_CRC_STRIPPING (1 << 0)
a4f58f54 430#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
b94b5028 431#define FLAG2_IS_DISCARDING (1 << 2)
6f461f6c 432#define FLAG2_DISABLE_ASPM_L1 (1 << 3)
8c7bbb92 433#define FLAG2_HAS_PHY_STATS (1 << 4)
e52997f9 434#define FLAG2_HAS_EEE (1 << 5)
3a3b7586 435#define FLAG2_DMA_BURST (1 << 6)
78cd29d5 436#define FLAG2_DISABLE_ASPM_L0S (1 << 7)
828bac87 437#define FLAG2_DISABLE_AIM (1 << 8)
ff10e13c 438#define FLAG2_CHECK_PHY_HANG (1 << 9)
7f99ae63 439#define FLAG2_NO_DISABLE_RX (1 << 10)
c6e7f51e 440#define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
0184039a 441#define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
b67e1913 442#define FLAG2_CHECK_RX_HWTSTAMP (1 << 13)
eb7c3adb 443
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444#define E1000_RX_DESC_PS(R, i) \
445 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
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446#define E1000_RX_DESC_EXT(R, i) \
447 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
bc7f75fa 448#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
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449#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
450#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
451
452enum e1000_state_t {
453 __E1000_TESTING,
454 __E1000_RESETTING,
a90b412c 455 __E1000_ACCESS_SHARED_RESOURCE,
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456 __E1000_DOWN
457};
458
459enum latency_range {
460 lowest_latency = 0,
461 low_latency = 1,
462 bulk_latency = 2,
463 latency_invalid = 255
464};
465
466extern char e1000e_driver_name[];
467extern const char e1000e_driver_version[];
468
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469void e1000e_check_options(struct e1000_adapter *adapter);
470void e1000e_set_ethtool_ops(struct net_device *netdev);
471
472int e1000e_up(struct e1000_adapter *adapter);
28002099 473void e1000e_down(struct e1000_adapter *adapter, bool reset);
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474void e1000e_reinit_locked(struct e1000_adapter *adapter);
475void e1000e_reset(struct e1000_adapter *adapter);
476void e1000e_power_up_phy(struct e1000_adapter *adapter);
477int e1000e_setup_rx_resources(struct e1000_ring *ring);
478int e1000e_setup_tx_resources(struct e1000_ring *ring);
479void e1000e_free_rx_resources(struct e1000_ring *ring);
480void e1000e_free_tx_resources(struct e1000_ring *ring);
481struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
482 struct rtnl_link_stats64 *stats);
483void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
484void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
485void e1000e_get_hw_control(struct e1000_adapter *adapter);
486void e1000e_release_hw_control(struct e1000_adapter *adapter);
487void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
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488
489extern unsigned int copybreak;
490
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491extern const struct e1000_info e1000_82571_info;
492extern const struct e1000_info e1000_82572_info;
493extern const struct e1000_info e1000_82573_info;
494extern const struct e1000_info e1000_82574_info;
495extern const struct e1000_info e1000_82583_info;
496extern const struct e1000_info e1000_ich8_info;
497extern const struct e1000_info e1000_ich9_info;
498extern const struct e1000_info e1000_ich10_info;
499extern const struct e1000_info e1000_pch_info;
500extern const struct e1000_info e1000_pch2_info;
2fbe4526 501extern const struct e1000_info e1000_pch_lpt_info;
8ce9d6c7 502extern const struct e1000_info e1000_es2_info;
bc7f75fa 503
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504void e1000e_ptp_init(struct e1000_adapter *adapter);
505void e1000e_ptp_remove(struct e1000_adapter *adapter);
0be84010 506
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507static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
508{
94d8186a 509 return hw->phy.ops.reset(hw);
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510}
511
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512static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
513{
94d8186a 514 return hw->phy.ops.read_reg(hw, offset, data);
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515}
516
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517static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
518{
519 return hw->phy.ops.read_reg_locked(hw, offset, data);
520}
521
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522static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
523{
94d8186a 524 return hw->phy.ops.write_reg(hw, offset, data);
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525}
526
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527static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
528{
529 return hw->phy.ops.write_reg_locked(hw, offset, data);
530}
531
5ccc921a 532void e1000e_reload_nvm_generic(struct e1000_hw *hw);
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533
534static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
535{
536 if (hw->mac.ops.read_mac_addr)
537 return hw->mac.ops.read_mac_addr(hw);
538
539 return e1000_read_mac_addr_generic(hw);
540}
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541
542static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
543{
94d8186a 544 return hw->nvm.ops.validate(hw);
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545}
546
547static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
548{
94d8186a 549 return hw->nvm.ops.update(hw);
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550}
551
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552static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
553 u16 *data)
bc7f75fa 554{
94d8186a 555 return hw->nvm.ops.read(hw, offset, words, data);
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556}
557
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558static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
559 u16 *data)
bc7f75fa 560{
94d8186a 561 return hw->nvm.ops.write(hw, offset, words, data);
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562}
563
564static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
565{
94d8186a 566 return hw->phy.ops.get_info(hw);
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567}
568
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569static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
570{
571 return readl(hw->hw_addr + reg);
572}
573
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574#define er32(reg) __er32(hw, E1000_##reg)
575
576/**
577 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
578 * @hw: pointer to the HW structure
579 *
580 * When updating the MAC CSR registers, the Manageability Engine (ME) could
581 * be accessing the registers at the same time. Normally, this is handled in
582 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
583 * accesses later than it should which could result in the register to have
584 * an incorrect value. Workaround this by checking the FWSM register which
585 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
586 * and try again a number of times.
587 **/
588static inline s32 __ew32_prepare(struct e1000_hw *hw)
589{
590 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
591
592 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
2a437cd3 593 udelay(50);
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594
595 return i;
596}
597
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598static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
599{
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600 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
601 __ew32_prepare(hw);
602
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603 writel(val, hw->hw_addr + reg);
604}
605
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606#define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
607
608#define e1e_flush() er32(STATUS)
609
610#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
611 (__ew32((a), (reg + ((offset) << 2)), (value)))
612
613#define E1000_READ_REG_ARRAY(a, reg, offset) \
614 (readl((a)->hw_addr + reg + ((offset) << 2)))
615
bc7f75fa 616#endif /* _E1000_H_ */