[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3vf / hclgevf_main.h

/* SPDX-License-Identifier: GPL-2.0+ */
/* Copyright (c) 2016-2017 Hisilicon Limited. */

#ifndef __HCLGEVF_MAIN_H
#define __HCLGEVF_MAIN_H
#include <linux/fs.h>
#include <linux/if_vlan.h>
#include <linux/types.h>
#include "hclge_mbx.h"
#include "hclgevf_cmd.h"
#include "hnae3.h"

#define HCLGEVF_MOD_VERSION "1.0"
#define HCLGEVF_DRIVER_NAME "hclgevf"

#define HCLGEVF_MAX_VLAN_ID	4095
#define HCLGEVF_MISC_VECTOR_NUM		0

#define HCLGEVF_INVALID_VPORT		0xffff
#define HCLGEVF_GENERAL_TASK_INTERVAL	  5
#define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL  2

/* This number in actual depends upon the total number of VFs
 * created by physical function. But the maximum number of
 * possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
 */
#define HCLGEVF_MAX_VF_VECTOR_NUM	(32 + 1)

#define HCLGEVF_VECTOR_REG_BASE		0x20000
#define HCLGEVF_MISC_VECTOR_REG_BASE	0x20400
#define HCLGEVF_VECTOR_REG_OFFSET	0x4
#define HCLGEVF_VECTOR_VF_OFFSET		0x100000

/* bar registers for cmdq */
#define HCLGEVF_CMDQ_TX_ADDR_L_REG		0x27000
#define HCLGEVF_CMDQ_TX_ADDR_H_REG		0x27004
#define HCLGEVF_CMDQ_TX_DEPTH_REG		0x27008
#define HCLGEVF_CMDQ_TX_TAIL_REG		0x27010
#define HCLGEVF_CMDQ_TX_HEAD_REG		0x27014
#define HCLGEVF_CMDQ_RX_ADDR_L_REG		0x27018
#define HCLGEVF_CMDQ_RX_ADDR_H_REG		0x2701C
#define HCLGEVF_CMDQ_RX_DEPTH_REG		0x27020
#define HCLGEVF_CMDQ_RX_TAIL_REG		0x27024
#define HCLGEVF_CMDQ_RX_HEAD_REG		0x27028
#define HCLGEVF_CMDQ_INTR_SRC_REG		0x27100
#define HCLGEVF_CMDQ_INTR_STS_REG		0x27104
#define HCLGEVF_CMDQ_INTR_EN_REG		0x27108
#define HCLGEVF_CMDQ_INTR_GEN_REG		0x2710C

/* bar registers for common func */
#define HCLGEVF_GRO_EN_REG			0x28000

/* bar registers for rcb */
#define HCLGEVF_RING_RX_ADDR_L_REG		0x80000
#define HCLGEVF_RING_RX_ADDR_H_REG		0x80004
#define HCLGEVF_RING_RX_BD_NUM_REG		0x80008
#define HCLGEVF_RING_RX_BD_LENGTH_REG		0x8000C
#define HCLGEVF_RING_RX_MERGE_EN_REG		0x80014
#define HCLGEVF_RING_RX_TAIL_REG		0x80018
#define HCLGEVF_RING_RX_HEAD_REG		0x8001C
#define HCLGEVF_RING_RX_FBD_NUM_REG		0x80020
#define HCLGEVF_RING_RX_OFFSET_REG		0x80024
#define HCLGEVF_RING_RX_FBD_OFFSET_REG		0x80028
#define HCLGEVF_RING_RX_STASH_REG		0x80030
#define HCLGEVF_RING_RX_BD_ERR_REG		0x80034
#define HCLGEVF_RING_TX_ADDR_L_REG		0x80040
#define HCLGEVF_RING_TX_ADDR_H_REG		0x80044
#define HCLGEVF_RING_TX_BD_NUM_REG		0x80048
#define HCLGEVF_RING_TX_PRIORITY_REG		0x8004C
#define HCLGEVF_RING_TX_TC_REG			0x80050
#define HCLGEVF_RING_TX_MERGE_EN_REG		0x80054
#define HCLGEVF_RING_TX_TAIL_REG		0x80058
#define HCLGEVF_RING_TX_HEAD_REG		0x8005C
#define HCLGEVF_RING_TX_FBD_NUM_REG		0x80060
#define HCLGEVF_RING_TX_OFFSET_REG		0x80064
#define HCLGEVF_RING_TX_EBD_NUM_REG		0x80068
#define HCLGEVF_RING_TX_EBD_OFFSET_REG		0x80070
#define HCLGEVF_RING_TX_BD_ERR_REG		0x80074
#define HCLGEVF_RING_EN_REG			0x80090

/* bar registers for tqp interrupt */
#define HCLGEVF_TQP_INTR_CTRL_REG		0x20000
#define HCLGEVF_TQP_INTR_GL0_REG		0x20100
#define HCLGEVF_TQP_INTR_GL1_REG		0x20200
#define HCLGEVF_TQP_INTR_GL2_REG		0x20300
#define HCLGEVF_TQP_INTR_RL_REG			0x20900

/* Vector0 interrupt CMDQ event source register(RW) */
#define HCLGEVF_VECTOR0_CMDQ_SRC_REG	0x27100
/* Vector0 interrupt CMDQ event status register(RO) */
#define HCLGEVF_VECTOR0_CMDQ_STAT_REG	0x27104
/* CMDQ register bits for RX event(=MBX event) */
#define HCLGEVF_VECTOR0_RX_CMDQ_INT_B	1
/* RST register bits for RESET event */
#define HCLGEVF_VECTOR0_RST_INT_B	2

#define HCLGEVF_TQP_RESET_TRY_TIMES	10
/* Reset related Registers */
#define HCLGEVF_RST_ING			0x20C00
#define HCLGEVF_FUN_RST_ING_BIT		BIT(0)
#define HCLGEVF_GLOBAL_RST_ING_BIT	BIT(5)
#define HCLGEVF_CORE_RST_ING_BIT	BIT(6)
#define HCLGEVF_IMP_RST_ING_BIT		BIT(7)
#define HCLGEVF_RST_ING_BITS \
	(HCLGEVF_FUN_RST_ING_BIT | HCLGEVF_GLOBAL_RST_ING_BIT | \
	 HCLGEVF_CORE_RST_ING_BIT | HCLGEVF_IMP_RST_ING_BIT)

#define HCLGEVF_VF_RST_ING		0x07008
#define HCLGEVF_VF_RST_ING_BIT		BIT(16)

#define HCLGEVF_RSS_IND_TBL_SIZE		512
#define HCLGEVF_RSS_SET_BITMAP_MSK	0xffff
#define HCLGEVF_RSS_KEY_SIZE		40
#define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ	0
#define HCLGEVF_RSS_HASH_ALGO_SIMPLE	1
#define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC	2
#define HCLGEVF_RSS_HASH_ALGO_MASK	0xf
#define HCLGEVF_RSS_CFG_TBL_NUM \
	(HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE)
#define HCLGEVF_RSS_INPUT_TUPLE_OTHER	GENMASK(3, 0)
#define HCLGEVF_RSS_INPUT_TUPLE_SCTP	GENMASK(4, 0)
#define HCLGEVF_D_PORT_BIT		BIT(0)
#define HCLGEVF_S_PORT_BIT		BIT(1)
#define HCLGEVF_D_IP_BIT		BIT(2)
#define HCLGEVF_S_IP_BIT		BIT(3)
#define HCLGEVF_V_TAG_BIT		BIT(4)

#define HCLGEVF_STATS_TIMER_INTERVAL	36U

enum hclgevf_evt_cause {
	HCLGEVF_VECTOR0_EVENT_RST,
	HCLGEVF_VECTOR0_EVENT_MBX,
	HCLGEVF_VECTOR0_EVENT_OTHER,
};

/* states of hclgevf device & tasks */
enum hclgevf_states {
	/* device states */
	HCLGEVF_STATE_DOWN,
	HCLGEVF_STATE_DISABLED,
	HCLGEVF_STATE_IRQ_INITED,
	HCLGEVF_STATE_REMOVING,
	HCLGEVF_STATE_NIC_REGISTERED,
	/* task states */
	HCLGEVF_STATE_SERVICE_SCHED,
	HCLGEVF_STATE_RST_SERVICE_SCHED,
	HCLGEVF_STATE_RST_HANDLING,
	HCLGEVF_STATE_MBX_SERVICE_SCHED,
	HCLGEVF_STATE_MBX_HANDLING,
	HCLGEVF_STATE_CMD_DISABLE,
};

struct hclgevf_mac {
	u8 media_type;
	u8 module_type;
	u8 mac_addr[ETH_ALEN];
	int link;
	u8 duplex;
	u32 speed;
	u64 supported;
	u64 advertising;
};

struct hclgevf_hw {
	void __iomem *io_base;
	int num_vec;
	struct hclgevf_cmq cmq;
	struct hclgevf_mac mac;
	void *hdev; /* hchgevf device it is part of */
};

/* TQP stats */
struct hlcgevf_tqp_stats {
	/* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
	u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
	/* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
	u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
};

struct hclgevf_tqp {
	struct device *dev;	/* device for DMA mapping */
	struct hnae3_queue q;
	struct hlcgevf_tqp_stats tqp_stats;
	u16 index;		/* global index in a NIC controller */

	bool alloced;
};

struct hclgevf_cfg {
	u8 vmdq_vport_num;
	u8 tc_num;
	u16 tqp_desc_num;
	u16 rx_buf_len;
	u8 phy_addr;
	u8 media_type;
	u8 mac_addr[ETH_ALEN];
	u32 numa_node_map;
};

struct hclgevf_rss_tuple_cfg {
	u8 ipv4_tcp_en;
	u8 ipv4_udp_en;
	u8 ipv4_sctp_en;
	u8 ipv4_fragment_en;
	u8 ipv6_tcp_en;
	u8 ipv6_udp_en;
	u8 ipv6_sctp_en;
	u8 ipv6_fragment_en;
};

struct hclgevf_rss_cfg {
	u8  rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */
	u32 hash_algo;
	u32 rss_size;
	u8 hw_tc_map;
	u8  rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */
	struct hclgevf_rss_tuple_cfg rss_tuple_sets;
};

struct hclgevf_misc_vector {
	u8 __iomem *addr;
	int vector_irq;
};

struct hclgevf_rst_stats {
	u32 rst_cnt;			/* the number of reset */
	u32 vf_func_rst_cnt;		/* the number of VF function reset */
	u32 flr_rst_cnt;		/* the number of FLR */
	u32 vf_rst_cnt;			/* the number of VF reset */
	u32 rst_done_cnt;		/* the number of reset completed */
	u32 hw_rst_done_cnt;		/* the number of HW reset completed */
	u32 rst_fail_cnt;		/* the number of VF reset fail */
};

struct hclgevf_dev {
	struct pci_dev *pdev;
	struct hnae3_ae_dev *ae_dev;
	struct hclgevf_hw hw;
	struct hclgevf_misc_vector misc_vector;
	struct hclgevf_rss_cfg rss_cfg;
	unsigned long state;
	unsigned long flr_state;
	unsigned long default_reset_request;
	unsigned long last_reset_time;
	enum hnae3_reset_type reset_level;
	unsigned long reset_pending;
	enum hnae3_reset_type reset_type;

#define HCLGEVF_RESET_REQUESTED		0
#define HCLGEVF_RESET_PENDING		1
	unsigned long reset_state;	/* requested, pending */
	struct hclgevf_rst_stats rst_stats;
	u32 reset_attempts;

	u32 fw_version;
	u16 num_tqps;		/* num task queue pairs of this PF */

	u16 alloc_rss_size;	/* allocated RSS task queue */
	u16 rss_size_max;	/* HW defined max RSS task queue */

	u16 num_alloc_vport;	/* num vports this driver supports */
	u32 numa_node_mask;
	u16 rx_buf_len;
	u16 num_tx_desc;	/* desc num of per tx queue */
	u16 num_rx_desc;	/* desc num of per rx queue */
	u8 hw_tc_map;
	u8 has_pf_mac;

	u16 num_msi;
	u16 num_msi_left;
	u16 num_msi_used;
	u16 num_nic_msix;	/* Num of nic vectors for this VF */
	u16 num_roce_msix;	/* Num of roce vectors for this VF */
	u16 roce_base_msix_offset;
	int roce_base_vector;
	u32 base_msi_vector;
	u16 *vector_status;
	int *vector_irq;

	unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];

	bool mbx_event_pending;
	struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
	struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */

	struct timer_list service_timer;
	struct timer_list keep_alive_timer;
	struct work_struct service_task;
	struct work_struct keep_alive_task;
	struct work_struct rst_service_task;
	struct work_struct mbx_service_task;

	struct hclgevf_tqp *htqp;

	struct hnae3_handle nic;
	struct hnae3_handle roce;

	struct hnae3_client *nic_client;
	struct hnae3_client *roce_client;
	u32 flag;
	u32 stats_timer;
};

static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
{
	return !!hdev->reset_pending;
}

int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode,
			 const u8 *msg_data, u8 msg_len, bool need_resp,
			 u8 *resp_data, u16 resp_len);
void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);

void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
				 u8 duplex);
void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
					u8 *port_base_vlan_info, u8 data_size);
#endif
Commit	Line	Data
e2cb1dec SM	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/* Copyright (c) 2016-2017 Hisilicon Limited. */
	3
	4	#ifndef __HCLGEVF_MAIN_H
	5	#define __HCLGEVF_MAIN_H
	6	#include <linux/fs.h>
fe4144d4	7	#include <linux/if_vlan.h>
e2cb1dec SM	8	#include <linux/types.h>
	9	#include "hclge_mbx.h"
	10	#include "hclgevf_cmd.h"
	11	#include "hnae3.h"
	12
3c7624d8	13	#define HCLGEVF_MOD_VERSION "1.0"
e2cb1dec SM	14	#define HCLGEVF_DRIVER_NAME "hclgevf"
e2cb1dec SM	15
b37ce587	16	#define HCLGEVF_MAX_VLAN_ID 4095
e2cb1dec SM	17	#define HCLGEVF_MISC_VECTOR_NUM 0
	18
	19	#define HCLGEVF_INVALID_VPORT 0xffff
b37ce587 YM	20	#define HCLGEVF_GENERAL_TASK_INTERVAL 5
b37ce587 YM	21	#define HCLGEVF_KEEP_ALIVE_TASK_INTERVAL 2
e2cb1dec SM	22
	23	/* This number in actual depends upon the total number of VFs
	24	* created by physical function. But the maximum number of
	25	* possible vector-per-VF is {VFn(1-32), VECTn(32 + 1)}.
	26	*/
	27	#define HCLGEVF_MAX_VF_VECTOR_NUM (32 + 1)
	28
	29	#define HCLGEVF_VECTOR_REG_BASE 0x20000
	30	#define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400
	31	#define HCLGEVF_VECTOR_REG_OFFSET 0x4
	32	#define HCLGEVF_VECTOR_VF_OFFSET 0x100000
	33
1600c3e5 JS	34	/* bar registers for cmdq */
	35	#define HCLGEVF_CMDQ_TX_ADDR_L_REG 0x27000
	36	#define HCLGEVF_CMDQ_TX_ADDR_H_REG 0x27004
	37	#define HCLGEVF_CMDQ_TX_DEPTH_REG 0x27008
	38	#define HCLGEVF_CMDQ_TX_TAIL_REG 0x27010
	39	#define HCLGEVF_CMDQ_TX_HEAD_REG 0x27014
	40	#define HCLGEVF_CMDQ_RX_ADDR_L_REG 0x27018
	41	#define HCLGEVF_CMDQ_RX_ADDR_H_REG 0x2701C
	42	#define HCLGEVF_CMDQ_RX_DEPTH_REG 0x27020
	43	#define HCLGEVF_CMDQ_RX_TAIL_REG 0x27024
	44	#define HCLGEVF_CMDQ_RX_HEAD_REG 0x27028
	45	#define HCLGEVF_CMDQ_INTR_SRC_REG 0x27100
	46	#define HCLGEVF_CMDQ_INTR_STS_REG 0x27104
	47	#define HCLGEVF_CMDQ_INTR_EN_REG 0x27108
	48	#define HCLGEVF_CMDQ_INTR_GEN_REG 0x2710C
	49
	50	/* bar registers for common func */
	51	#define HCLGEVF_GRO_EN_REG 0x28000
	52
	53	/* bar registers for rcb */
	54	#define HCLGEVF_RING_RX_ADDR_L_REG 0x80000
	55	#define HCLGEVF_RING_RX_ADDR_H_REG 0x80004
	56	#define HCLGEVF_RING_RX_BD_NUM_REG 0x80008
	57	#define HCLGEVF_RING_RX_BD_LENGTH_REG 0x8000C
	58	#define HCLGEVF_RING_RX_MERGE_EN_REG 0x80014
	59	#define HCLGEVF_RING_RX_TAIL_REG 0x80018
	60	#define HCLGEVF_RING_RX_HEAD_REG 0x8001C
	61	#define HCLGEVF_RING_RX_FBD_NUM_REG 0x80020
	62	#define HCLGEVF_RING_RX_OFFSET_REG 0x80024
	63	#define HCLGEVF_RING_RX_FBD_OFFSET_REG 0x80028
	64	#define HCLGEVF_RING_RX_STASH_REG 0x80030
	65	#define HCLGEVF_RING_RX_BD_ERR_REG 0x80034
	66	#define HCLGEVF_RING_TX_ADDR_L_REG 0x80040
	67	#define HCLGEVF_RING_TX_ADDR_H_REG 0x80044
	68	#define HCLGEVF_RING_TX_BD_NUM_REG 0x80048
	69	#define HCLGEVF_RING_TX_PRIORITY_REG 0x8004C
	70	#define HCLGEVF_RING_TX_TC_REG 0x80050
	71	#define HCLGEVF_RING_TX_MERGE_EN_REG 0x80054
	72	#define HCLGEVF_RING_TX_TAIL_REG 0x80058
	73	#define HCLGEVF_RING_TX_HEAD_REG 0x8005C
	74	#define HCLGEVF_RING_TX_FBD_NUM_REG 0x80060
	75	#define HCLGEVF_RING_TX_OFFSET_REG 0x80064
	76	#define HCLGEVF_RING_TX_EBD_NUM_REG 0x80068
	77	#define HCLGEVF_RING_TX_EBD_OFFSET_REG 0x80070
	78	#define HCLGEVF_RING_TX_BD_ERR_REG 0x80074
	79	#define HCLGEVF_RING_EN_REG 0x80090
	80
	81	/* bar registers for tqp interrupt */
	82	#define HCLGEVF_TQP_INTR_CTRL_REG 0x20000
	83	#define HCLGEVF_TQP_INTR_GL0_REG 0x20100
	84	#define HCLGEVF_TQP_INTR_GL1_REG 0x20200
	85	#define HCLGEVF_TQP_INTR_GL2_REG 0x20300
	86	#define HCLGEVF_TQP_INTR_RL_REG 0x20900
	87
e2cb1dec SM	88	/* Vector0 interrupt CMDQ event source register(RW) */
e2cb1dec SM	89	#define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100
13050921 HT	90	/* Vector0 interrupt CMDQ event status register(RO) */
13050921 HT	91	#define HCLGEVF_VECTOR0_CMDQ_STAT_REG 0x27104
e2cb1dec SM	92	/* CMDQ register bits for RX event(=MBX event) */
e2cb1dec SM	93	#define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1
b90fcc5b HT	94	/* RST register bits for RESET event */
b90fcc5b HT	95	#define HCLGEVF_VECTOR0_RST_INT_B 2
e2cb1dec SM	96
e2cb1dec SM	97	#define HCLGEVF_TQP_RESET_TRY_TIMES 10
6988eb2a	98	/* Reset related Registers */
aa5c4f17 HT	99	#define HCLGEVF_RST_ING 0x20C00
	100	#define HCLGEVF_FUN_RST_ING_BIT BIT(0)
	101	#define HCLGEVF_GLOBAL_RST_ING_BIT BIT(5)
	102	#define HCLGEVF_CORE_RST_ING_BIT BIT(6)
	103	#define HCLGEVF_IMP_RST_ING_BIT BIT(7)
	104	#define HCLGEVF_RST_ING_BITS \
	105	(HCLGEVF_FUN_RST_ING_BIT \| HCLGEVF_GLOBAL_RST_ING_BIT \| \
	106	HCLGEVF_CORE_RST_ING_BIT \| HCLGEVF_IMP_RST_ING_BIT)
e2cb1dec	107
72e2fb07 HT	108	#define HCLGEVF_VF_RST_ING 0x07008
	109	#define HCLGEVF_VF_RST_ING_BIT BIT(16)
	110
e2cb1dec SM	111	#define HCLGEVF_RSS_IND_TBL_SIZE 512
	112	#define HCLGEVF_RSS_SET_BITMAP_MSK 0xffff
	113	#define HCLGEVF_RSS_KEY_SIZE 40
	114	#define HCLGEVF_RSS_HASH_ALGO_TOEPLITZ 0
	115	#define HCLGEVF_RSS_HASH_ALGO_SIMPLE 1
	116	#define HCLGEVF_RSS_HASH_ALGO_SYMMETRIC 2
	117	#define HCLGEVF_RSS_HASH_ALGO_MASK 0xf
	118	#define HCLGEVF_RSS_CFG_TBL_NUM \
	119	(HCLGEVF_RSS_IND_TBL_SIZE / HCLGEVF_RSS_CFG_TBL_SIZE)
d97b3072 JS	120	#define HCLGEVF_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
	121	#define HCLGEVF_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
	122	#define HCLGEVF_D_PORT_BIT BIT(0)
	123	#define HCLGEVF_S_PORT_BIT BIT(1)
	124	#define HCLGEVF_D_IP_BIT BIT(2)
	125	#define HCLGEVF_S_IP_BIT BIT(3)
	126	#define HCLGEVF_V_TAG_BIT BIT(4)
e2cb1dec	127
eddd9860	128	#define HCLGEVF_STATS_TIMER_INTERVAL 36U
db01afeb	129
b90fcc5b HT	130	enum hclgevf_evt_cause {
	131	HCLGEVF_VECTOR0_EVENT_RST,
	132	HCLGEVF_VECTOR0_EVENT_MBX,
	133	HCLGEVF_VECTOR0_EVENT_OTHER,
	134	};
	135
e2cb1dec SM	136	/* states of hclgevf device & tasks */
	137	enum hclgevf_states {
	138	/* device states */
	139	HCLGEVF_STATE_DOWN,
	140	HCLGEVF_STATE_DISABLED,
862d969a	141	HCLGEVF_STATE_IRQ_INITED,
acfc3d55	142	HCLGEVF_STATE_REMOVING,
25d1817c	143	HCLGEVF_STATE_NIC_REGISTERED,
e2cb1dec SM	144	/* task states */
e2cb1dec SM	145	HCLGEVF_STATE_SERVICE_SCHED,
35a1e503 SM	146	HCLGEVF_STATE_RST_SERVICE_SCHED,
35a1e503 SM	147	HCLGEVF_STATE_RST_HANDLING,
e2cb1dec SM	148	HCLGEVF_STATE_MBX_SERVICE_SCHED,
e2cb1dec SM	149	HCLGEVF_STATE_MBX_HANDLING,
ef5f8e50	150	HCLGEVF_STATE_CMD_DISABLE,
e2cb1dec SM	151	};
e2cb1dec SM	152
e2cb1dec	153	struct hclgevf_mac {
c136b884	154	u8 media_type;
88d10bd6	155	u8 module_type;
e2cb1dec SM	156	u8 mac_addr[ETH_ALEN];
e2cb1dec SM	157	int link;
4a152de9 FL	158	u8 duplex;
4a152de9 FL	159	u32 speed;
9194d18b	160	u64 supported;
9194d18b	161	u64 advertising;
e2cb1dec SM	162	};
	163
	164	struct hclgevf_hw {
	165	void __iomem *io_base;
	166	int num_vec;
	167	struct hclgevf_cmq cmq;
	168	struct hclgevf_mac mac;
	169	void hdev; / hchgevf device it is part of */
	170	};
	171
	172	/* TQP stats */
	173	struct hlcgevf_tqp_stats {
	174	/* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
	175	u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
	176	/* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
	177	u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
	178	};
	179
	180	struct hclgevf_tqp {
	181	struct device dev; / device for DMA mapping */
	182	struct hnae3_queue q;
	183	struct hlcgevf_tqp_stats tqp_stats;
	184	u16 index; /* global index in a NIC controller */
	185
	186	bool alloced;
	187	};
	188
	189	struct hclgevf_cfg {
	190	u8 vmdq_vport_num;
	191	u8 tc_num;
	192	u16 tqp_desc_num;
	193	u16 rx_buf_len;
	194	u8 phy_addr;
	195	u8 media_type;
	196	u8 mac_addr[ETH_ALEN];
	197	u32 numa_node_map;
	198	};
	199
d97b3072 JS	200	struct hclgevf_rss_tuple_cfg {
	201	u8 ipv4_tcp_en;
	202	u8 ipv4_udp_en;
	203	u8 ipv4_sctp_en;
	204	u8 ipv4_fragment_en;
	205	u8 ipv6_tcp_en;
	206	u8 ipv6_udp_en;
	207	u8 ipv6_sctp_en;
	208	u8 ipv6_fragment_en;
	209	};
	210
e2cb1dec SM	211	struct hclgevf_rss_cfg {
	212	u8 rss_hash_key[HCLGEVF_RSS_KEY_SIZE]; /* user configured hash keys */
	213	u32 hash_algo;
	214	u32 rss_size;
	215	u8 hw_tc_map;
	216	u8 rss_indirection_tbl[HCLGEVF_RSS_IND_TBL_SIZE]; /* shadow table */
d97b3072	217	struct hclgevf_rss_tuple_cfg rss_tuple_sets;
e2cb1dec SM	218	};
	219
	220	struct hclgevf_misc_vector {
	221	u8 __iomem *addr;
	222	int vector_irq;
	223	};
	224
c88a6e7d HT	225	struct hclgevf_rst_stats {
	226	u32 rst_cnt; /* the number of reset */
	227	u32 vf_func_rst_cnt; /* the number of VF function reset */
	228	u32 flr_rst_cnt; /* the number of FLR */
	229	u32 vf_rst_cnt; /* the number of VF reset */
	230	u32 rst_done_cnt; /* the number of reset completed */
	231	u32 hw_rst_done_cnt; /* the number of HW reset completed */
bbe6540e	232	u32 rst_fail_cnt; /* the number of VF reset fail */
c88a6e7d HT	233	};
c88a6e7d HT	234
e2cb1dec SM	235	struct hclgevf_dev {
	236	struct pci_dev *pdev;
	237	struct hnae3_ae_dev *ae_dev;
	238	struct hclgevf_hw hw;
	239	struct hclgevf_misc_vector misc_vector;
	240	struct hclgevf_rss_cfg rss_cfg;
	241	unsigned long state;
6ff3cf07	242	unsigned long flr_state;
720bd583	243	unsigned long default_reset_request;
0742ed7c HT	244	unsigned long last_reset_time;
0742ed7c HT	245	enum hnae3_reset_type reset_level;
dea846e8 HT	246	unsigned long reset_pending;
dea846e8 HT	247	enum hnae3_reset_type reset_type;
e2cb1dec	248
436667d2 SM	249	#define HCLGEVF_RESET_REQUESTED 0
	250	#define HCLGEVF_RESET_PENDING 1
	251	unsigned long reset_state; /* requested, pending */
c88a6e7d	252	struct hclgevf_rst_stats rst_stats;
436667d2 SM	253	u32 reset_attempts;
436667d2 SM	254
e2cb1dec SM	255	u32 fw_version;
	256	u16 num_tqps; /* num task queue pairs of this PF */
	257
	258	u16 alloc_rss_size; /* allocated RSS task queue */
	259	u16 rss_size_max; /* HW defined max RSS task queue */
	260
	261	u16 num_alloc_vport; /* num vports this driver supports */
	262	u32 numa_node_mask;
	263	u16 rx_buf_len;
c0425944 PL	264	u16 num_tx_desc; /* desc num of per tx queue */
c0425944 PL	265	u16 num_rx_desc; /* desc num of per rx queue */
e2cb1dec	266	u8 hw_tc_map;
8e6de441	267	u8 has_pf_mac;
e2cb1dec SM	268
	269	u16 num_msi;
	270	u16 num_msi_left;
	271	u16 num_msi_used;
580a05f9	272	u16 num_nic_msix; /* Num of nic vectors for this VF */
07acf909 JS	273	u16 num_roce_msix; /* Num of roce vectors for this VF */
	274	u16 roce_base_msix_offset;
	275	int roce_base_vector;
e2cb1dec SM	276	u32 base_msi_vector;
	277	u16 *vector_status;
	278	int *vector_irq;
	279
fe4144d4 JS	280	unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
fe4144d4 JS	281
07a0556a	282	bool mbx_event_pending;
e2cb1dec	283	struct hclgevf_mbx_resp_status mbx_resp; /* mailbox response */
07a0556a	284	struct hclgevf_mbx_arq_ring arq; /* mailbox async rx queue */
e2cb1dec SM	285
e2cb1dec SM	286	struct timer_list service_timer;
a6d818e3	287	struct timer_list keep_alive_timer;
e2cb1dec	288	struct work_struct service_task;
a6d818e3	289	struct work_struct keep_alive_task;
35a1e503	290	struct work_struct rst_service_task;
e2cb1dec SM	291	struct work_struct mbx_service_task;
	292
	293	struct hclgevf_tqp *htqp;
	294
	295	struct hnae3_handle nic;
	296	struct hnae3_handle roce;
	297
	298	struct hnae3_client *nic_client;
	299	struct hnae3_client *roce_client;
	300	u32 flag;
db01afeb	301	u32 stats_timer;
e2cb1dec SM	302	};
e2cb1dec SM	303
ef5f8e50 HT	304	static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
	305	{
	306	return !!hdev->reset_pending;
	307	}
	308
e2cb1dec SM	309	int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode,
	310	const u8 *msg_data, u8 msg_len, bool need_resp,
	311	u8 *resp_data, u16 resp_len);
	312	void hclgevf_mbx_handler(struct hclgevf_dev *hdev);
07a0556a SM	313	void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev);
07a0556a SM	314
e2cb1dec	315	void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state);
4a152de9 FL	316	void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
4a152de9 FL	317	u8 duplex);
35a1e503	318	void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev);
07a0556a	319	void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev);
92f11ea1 JS	320	void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
92f11ea1 JS	321	u8 *port_base_vlan_info, u8 data_size);
e2cb1dec	322	#endif