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net: hns3: fix vf id check issue when add flow director rule
[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
46a3df9f
S		 3
4#include <linux/acpi.h>
5#include <linux/device.h>
6#include <linux/etherdevice.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
2866ccb2 14#include <linux/if_vlan.h>
f2f432f2 15#include <net/rtnetlink.h>
46a3df9f 16#include "hclge_cmd.h"
cacde272 17#include "hclge_dcb.h"
46a3df9f 18#include "hclge_main.h"
dde1a86e 19#include "hclge_mbx.h"
46a3df9f
S		 20#include "hclge_mdio.h"
21#include "hclge_tm.h"
5a9f0eac 22#include "hclge_err.h"
46a3df9f
S		 23#include "hnae3.h"
24
25#define HCLGE_NAME "hclge"
26#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
27#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
46a3df9f 28
b9a400ac
YL		 29#define HCLGE_BUF_SIZE_UNIT 256
30
e6d7d79d 31static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
46a3df9f 32static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 33static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
39932473
JS		 34static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
35 u16 *allocated_size, bool is_alloc);
46a3df9f
S		 36
37static struct hnae3_ae_algo ae_algo;
38
39static const struct pci_device_id ae_algo_pci_tbl[] = {
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 47 /* required last entry */
46a3df9f
S		 48 {0, }
49};
50
2f550a46
YL		 51MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
52
ea4750ca
JS		 53static const u32 cmdq_reg_addr_list[] = {HCLGE_CMDQ_TX_ADDR_L_REG,
54 HCLGE_CMDQ_TX_ADDR_H_REG,
55 HCLGE_CMDQ_TX_DEPTH_REG,
56 HCLGE_CMDQ_TX_TAIL_REG,
57 HCLGE_CMDQ_TX_HEAD_REG,
58 HCLGE_CMDQ_RX_ADDR_L_REG,
59 HCLGE_CMDQ_RX_ADDR_H_REG,
60 HCLGE_CMDQ_RX_DEPTH_REG,
61 HCLGE_CMDQ_RX_TAIL_REG,
62 HCLGE_CMDQ_RX_HEAD_REG,
63 HCLGE_VECTOR0_CMDQ_SRC_REG,
64 HCLGE_CMDQ_INTR_STS_REG,
65 HCLGE_CMDQ_INTR_EN_REG,
66 HCLGE_CMDQ_INTR_GEN_REG};
67
68static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
69 HCLGE_VECTOR0_OTER_EN_REG,
70 HCLGE_MISC_RESET_STS_REG,
71 HCLGE_MISC_VECTOR_INT_STS,
72 HCLGE_GLOBAL_RESET_REG,
73 HCLGE_FUN_RST_ING,
74 HCLGE_GRO_EN_REG};
75
76static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG,
77 HCLGE_RING_RX_ADDR_H_REG,
78 HCLGE_RING_RX_BD_NUM_REG,
79 HCLGE_RING_RX_BD_LENGTH_REG,
80 HCLGE_RING_RX_MERGE_EN_REG,
81 HCLGE_RING_RX_TAIL_REG,
82 HCLGE_RING_RX_HEAD_REG,
83 HCLGE_RING_RX_FBD_NUM_REG,
84 HCLGE_RING_RX_OFFSET_REG,
85 HCLGE_RING_RX_FBD_OFFSET_REG,
86 HCLGE_RING_RX_STASH_REG,
87 HCLGE_RING_RX_BD_ERR_REG,
88 HCLGE_RING_TX_ADDR_L_REG,
89 HCLGE_RING_TX_ADDR_H_REG,
90 HCLGE_RING_TX_BD_NUM_REG,
91 HCLGE_RING_TX_PRIORITY_REG,
92 HCLGE_RING_TX_TC_REG,
93 HCLGE_RING_TX_MERGE_EN_REG,
94 HCLGE_RING_TX_TAIL_REG,
95 HCLGE_RING_TX_HEAD_REG,
96 HCLGE_RING_TX_FBD_NUM_REG,
97 HCLGE_RING_TX_OFFSET_REG,
98 HCLGE_RING_TX_EBD_NUM_REG,
99 HCLGE_RING_TX_EBD_OFFSET_REG,
100 HCLGE_RING_TX_BD_ERR_REG,
101 HCLGE_RING_EN_REG};
102
103static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG,
104 HCLGE_TQP_INTR_GL0_REG,
105 HCLGE_TQP_INTR_GL1_REG,
106 HCLGE_TQP_INTR_GL2_REG,
107 HCLGE_TQP_INTR_RL_REG};
108
46a3df9f 109static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
eb66d503 110 "App Loopback test",
4dc13b96
FL		 111 "Serdes serial Loopback test",
112 "Serdes parallel Loopback test",
46a3df9f
S		 113 "Phy Loopback test"
114};
115
46a3df9f
S		 116static const struct hclge_comm_stats_str g_mac_stats_string[] = {
117 {"mac_tx_mac_pause_num",
118 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
119 {"mac_rx_mac_pause_num",
120 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
121 {"mac_tx_pfc_pri0_pkt_num",
122 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
123 {"mac_tx_pfc_pri1_pkt_num",
124 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
125 {"mac_tx_pfc_pri2_pkt_num",
126 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
127 {"mac_tx_pfc_pri3_pkt_num",
128 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
129 {"mac_tx_pfc_pri4_pkt_num",
130 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
131 {"mac_tx_pfc_pri5_pkt_num",
132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
133 {"mac_tx_pfc_pri6_pkt_num",
134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
135 {"mac_tx_pfc_pri7_pkt_num",
136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
137 {"mac_rx_pfc_pri0_pkt_num",
138 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
139 {"mac_rx_pfc_pri1_pkt_num",
140 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
141 {"mac_rx_pfc_pri2_pkt_num",
142 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
143 {"mac_rx_pfc_pri3_pkt_num",
144 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
145 {"mac_rx_pfc_pri4_pkt_num",
146 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
147 {"mac_rx_pfc_pri5_pkt_num",
148 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
149 {"mac_rx_pfc_pri6_pkt_num",
150 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
151 {"mac_rx_pfc_pri7_pkt_num",
152 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
153 {"mac_tx_total_pkt_num",
154 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
155 {"mac_tx_total_oct_num",
156 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
157 {"mac_tx_good_pkt_num",
158 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
159 {"mac_tx_bad_pkt_num",
160 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
161 {"mac_tx_good_oct_num",
162 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
163 {"mac_tx_bad_oct_num",
164 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
165 {"mac_tx_uni_pkt_num",
166 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
167 {"mac_tx_multi_pkt_num",
168 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
169 {"mac_tx_broad_pkt_num",
170 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
171 {"mac_tx_undersize_pkt_num",
172 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
200a88c6
JS		 173 {"mac_tx_oversize_pkt_num",
174 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 175 {"mac_tx_64_oct_pkt_num",
176 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
177 {"mac_tx_65_127_oct_pkt_num",
178 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
179 {"mac_tx_128_255_oct_pkt_num",
180 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
181 {"mac_tx_256_511_oct_pkt_num",
182 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
183 {"mac_tx_512_1023_oct_pkt_num",
184 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
185 {"mac_tx_1024_1518_oct_pkt_num",
186 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
91f384f6
JS		 187 {"mac_tx_1519_2047_oct_pkt_num",
188 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
189 {"mac_tx_2048_4095_oct_pkt_num",
190 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
191 {"mac_tx_4096_8191_oct_pkt_num",
192 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
91f384f6
JS		 193 {"mac_tx_8192_9216_oct_pkt_num",
194 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
195 {"mac_tx_9217_12287_oct_pkt_num",
196 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
197 {"mac_tx_12288_16383_oct_pkt_num",
198 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
199 {"mac_tx_1519_max_good_pkt_num",
200 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
201 {"mac_tx_1519_max_bad_pkt_num",
202 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 203 {"mac_rx_total_pkt_num",
204 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
205 {"mac_rx_total_oct_num",
206 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
207 {"mac_rx_good_pkt_num",
208 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
209 {"mac_rx_bad_pkt_num",
210 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
211 {"mac_rx_good_oct_num",
212 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
213 {"mac_rx_bad_oct_num",
214 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
215 {"mac_rx_uni_pkt_num",
216 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
217 {"mac_rx_multi_pkt_num",
218 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
219 {"mac_rx_broad_pkt_num",
220 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
221 {"mac_rx_undersize_pkt_num",
222 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
200a88c6
JS		 223 {"mac_rx_oversize_pkt_num",
224 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 225 {"mac_rx_64_oct_pkt_num",
226 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
227 {"mac_rx_65_127_oct_pkt_num",
228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
229 {"mac_rx_128_255_oct_pkt_num",
230 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
231 {"mac_rx_256_511_oct_pkt_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
233 {"mac_rx_512_1023_oct_pkt_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
235 {"mac_rx_1024_1518_oct_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
91f384f6
JS		 237 {"mac_rx_1519_2047_oct_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
239 {"mac_rx_2048_4095_oct_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
241 {"mac_rx_4096_8191_oct_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
91f384f6
JS		 243 {"mac_rx_8192_9216_oct_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
245 {"mac_rx_9217_12287_oct_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
247 {"mac_rx_12288_16383_oct_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
249 {"mac_rx_1519_max_good_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
251 {"mac_rx_1519_max_bad_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 253
a6c51c26
JS		 254 {"mac_tx_fragment_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
256 {"mac_tx_undermin_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
258 {"mac_tx_jabber_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
260 {"mac_tx_err_all_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
262 {"mac_tx_from_app_good_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
264 {"mac_tx_from_app_bad_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
266 {"mac_rx_fragment_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
268 {"mac_rx_undermin_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
270 {"mac_rx_jabber_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
272 {"mac_rx_fcs_err_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
274 {"mac_rx_send_app_good_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
276 {"mac_rx_send_app_bad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 278};
279
f5aac71c
FL		 280static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
281 {
282 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
283 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
284 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
285 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
286 .i_port_bitmap = 0x1,
287 },
288};
289
46a3df9f
S		 290static int hclge_mac_update_stats(struct hclge_dev *hdev)
291{
91f384f6 292#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 293#define HCLGE_RTN_DATA_NUM 4
294
295 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
296 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 297 __le64 *desc_data;
46a3df9f
S		 298 int i, k, n;
299 int ret;
300
301 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
302 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
303 if (ret) {
304 dev_err(&hdev->pdev->dev,
305 "Get MAC pkt stats fail, status = %d.\n", ret);
306
307 return ret;
308 }
309
310 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
311 if (unlikely(i == 0)) {
a90bb9a5 312 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 313 n = HCLGE_RTN_DATA_NUM - 2;
314 } else {
a90bb9a5 315 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 316 n = HCLGE_RTN_DATA_NUM;
317 }
318 for (k = 0; k < n; k++) {
a90bb9a5 319 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 320 desc_data++;
321 }
322 }
323
324 return 0;
325}
326
327static int hclge_tqps_update_stats(struct hnae3_handle *handle)
328{
329 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
330 struct hclge_vport *vport = hclge_get_vport(handle);
331 struct hclge_dev *hdev = vport->back;
332 struct hnae3_queue *queue;
333 struct hclge_desc desc[1];
334 struct hclge_tqp *tqp;
335 int ret, i;
336
337 for (i = 0; i < kinfo->num_tqps; i++) {
338 queue = handle->kinfo.tqp[i];
339 tqp = container_of(queue, struct hclge_tqp, q);
340 /* command : HCLGE_OPC_QUERY_IGU_STAT */
341 hclge_cmd_setup_basic_desc(&desc[0],
342 HCLGE_OPC_QUERY_RX_STATUS,
343 true);
344
a90bb9a5 345 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 346 ret = hclge_cmd_send(&hdev->hw, desc, 1);
347 if (ret) {
348 dev_err(&hdev->pdev->dev,
349 "Query tqp stat fail, status = %d,queue = %d\n",
350 ret, i);
351 return ret;
352 }
353 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
cf72fa63 354 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 355 }
356
357 for (i = 0; i < kinfo->num_tqps; i++) {
358 queue = handle->kinfo.tqp[i];
359 tqp = container_of(queue, struct hclge_tqp, q);
360 /* command : HCLGE_OPC_QUERY_IGU_STAT */
361 hclge_cmd_setup_basic_desc(&desc[0],
362 HCLGE_OPC_QUERY_TX_STATUS,
363 true);
364
a90bb9a5 365 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 366 ret = hclge_cmd_send(&hdev->hw, desc, 1);
367 if (ret) {
368 dev_err(&hdev->pdev->dev,
369 "Query tqp stat fail, status = %d,queue = %d\n",
370 ret, i);
371 return ret;
372 }
373 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
cf72fa63 374 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 375 }
376
377 return 0;
378}
379
380static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
381{
382 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
383 struct hclge_tqp *tqp;
384 u64 *buff = data;
385 int i;
386
387 for (i = 0; i < kinfo->num_tqps; i++) {
388 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 389 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 390 }
391
392 for (i = 0; i < kinfo->num_tqps; i++) {
393 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 394 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 395 }
396
397 return buff;
398}
399
400static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
401{
402 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
403
404 return kinfo->num_tqps * (2);
405}
406
407static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
408{
409 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
410 u8 *buff = data;
411 int i = 0;
412
413 for (i = 0; i < kinfo->num_tqps; i++) {
414 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
415 struct hclge_tqp, q);
0c218123 416 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
46a3df9f
S		 417 tqp->index);
418 buff = buff + ETH_GSTRING_LEN;
419 }
420
421 for (i = 0; i < kinfo->num_tqps; i++) {
422 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
423 struct hclge_tqp, q);
0c218123 424 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
46a3df9f
S		 425 tqp->index);
426 buff = buff + ETH_GSTRING_LEN;
427 }
428
429 return buff;
430}
431
432static u64 *hclge_comm_get_stats(void *comm_stats,
433 const struct hclge_comm_stats_str strs[],
434 int size, u64 *data)
435{
436 u64 *buf = data;
437 u32 i;
438
439 for (i = 0; i < size; i++)
440 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
441
442 return buf + size;
443}
444
445static u8 *hclge_comm_get_strings(u32 stringset,
446 const struct hclge_comm_stats_str strs[],
447 int size, u8 *data)
448{
449 char *buff = (char *)data;
450 u32 i;
451
452 if (stringset != ETH_SS_STATS)
453 return buff;
454
455 for (i = 0; i < size; i++) {
456 snprintf(buff, ETH_GSTRING_LEN,
457 strs[i].desc);
458 buff = buff + ETH_GSTRING_LEN;
459 }
460
461 return (u8 *)buff;
462}
463
464static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
465 struct net_device_stats *net_stats)
466{
467 net_stats->tx_dropped = 0;
200a88c6 468 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 469 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
a6c51c26 470 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 471
472 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
473 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
474
a6c51c26 475 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 476 net_stats->rx_length_errors =
477 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
478 net_stats->rx_length_errors +=
200a88c6 479 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 480 net_stats->rx_over_errors =
200a88c6 481 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 482}
483
484static void hclge_update_stats_for_all(struct hclge_dev *hdev)
485{
486 struct hnae3_handle *handle;
487 int status;
488
489 handle = &hdev->vport[0].nic;
490 if (handle->client) {
491 status = hclge_tqps_update_stats(handle);
492 if (status) {
493 dev_err(&hdev->pdev->dev,
494 "Update TQPS stats fail, status = %d.\n",
495 status);
496 }
497 }
498
499 status = hclge_mac_update_stats(hdev);
500 if (status)
501 dev_err(&hdev->pdev->dev,
502 "Update MAC stats fail, status = %d.\n", status);
503
46a3df9f
S		 504 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
505}
506
507static void hclge_update_stats(struct hnae3_handle *handle,
508 struct net_device_stats *net_stats)
509{
510 struct hclge_vport *vport = hclge_get_vport(handle);
511 struct hclge_dev *hdev = vport->back;
512 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
513 int status;
514
c5f65480
JS		 515 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
516 return;
517
46a3df9f
S		 518 status = hclge_mac_update_stats(hdev);
519 if (status)
520 dev_err(&hdev->pdev->dev,
521 "Update MAC stats fail, status = %d.\n",
522 status);
523
46a3df9f
S		 524 status = hclge_tqps_update_stats(handle);
525 if (status)
526 dev_err(&hdev->pdev->dev,
527 "Update TQPS stats fail, status = %d.\n",
528 status);
529
530 hclge_update_netstat(hw_stats, net_stats);
c5f65480
JS		 531
532 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 533}
534
535static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
536{
4dc13b96
FL		 537#define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
538 HNAE3_SUPPORT_PHY_LOOPBACK |\
539 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
540 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
46a3df9f
S		 541
542 struct hclge_vport *vport = hclge_get_vport(handle);
543 struct hclge_dev *hdev = vport->back;
544 int count = 0;
545
546 /* Loopback test support rules:
547 * mac: only GE mode support
548 * serdes: all mac mode will support include GE/XGE/LGE/CGE
549 * phy: only support when phy device exist on board
550 */
551 if (stringset == ETH_SS_TEST) {
552 /* clear loopback bit flags at first */
553 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
3ff6cde8 554 if (hdev->pdev->revision >= 0x21 ||
4dc13b96 555 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
46a3df9f
S		 556 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
557 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
558 count += 1;
eb66d503 559 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
46a3df9f 560 }
5fd50ac3 561
4dc13b96
FL		 562 count += 2;
563 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
564 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
46a3df9f
S		 565 } else if (stringset == ETH_SS_STATS) {
566 count = ARRAY_SIZE(g_mac_stats_string) +
46a3df9f
S		 567 hclge_tqps_get_sset_count(handle, stringset);
568 }
569
570 return count;
571}
572
573static void hclge_get_strings(struct hnae3_handle *handle,
574 u32 stringset,
575 u8 *data)
576{
577 u8 *p = (char *)data;
578 int size;
579
580 if (stringset == ETH_SS_STATS) {
581 size = ARRAY_SIZE(g_mac_stats_string);
582 p = hclge_comm_get_strings(stringset,
583 g_mac_stats_string,
584 size,
585 p);
46a3df9f
S		 586 p = hclge_tqps_get_strings(handle, p);
587 } else if (stringset == ETH_SS_TEST) {
eb66d503 588 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
46a3df9f 589 memcpy(p,
eb66d503 590 hns3_nic_test_strs[HNAE3_LOOP_APP],
46a3df9f
S		 591 ETH_GSTRING_LEN);
592 p += ETH_GSTRING_LEN;
593 }
4dc13b96 594 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
46a3df9f 595 memcpy(p,
4dc13b96
FL		 596 hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
597 ETH_GSTRING_LEN);
598 p += ETH_GSTRING_LEN;
599 }
600 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
601 memcpy(p,
602 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
46a3df9f
S		 603 ETH_GSTRING_LEN);
604 p += ETH_GSTRING_LEN;
605 }
606 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
607 memcpy(p,
a7b687b3 608 hns3_nic_test_strs[HNAE3_LOOP_PHY],
46a3df9f
S		 609 ETH_GSTRING_LEN);
610 p += ETH_GSTRING_LEN;
611 }
612 }
613}
614
615static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
616{
617 struct hclge_vport *vport = hclge_get_vport(handle);
618 struct hclge_dev *hdev = vport->back;
619 u64 *p;
620
621 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
622 g_mac_stats_string,
623 ARRAY_SIZE(g_mac_stats_string),
624 data);
46a3df9f
S		 625 p = hclge_tqps_get_stats(handle, p);
626}
627
628static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 629 struct hclge_func_status_cmd *status)
46a3df9f
S		 630{
631 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
632 return -EINVAL;
633
634 /* Set the pf to main pf */
635 if (status->pf_state & HCLGE_PF_STATE_MAIN)
636 hdev->flag |= HCLGE_FLAG_MAIN;
637 else
638 hdev->flag &= ~HCLGE_FLAG_MAIN;
639
46a3df9f
S		 640 return 0;
641}
642
643static int hclge_query_function_status(struct hclge_dev *hdev)
644{
d44f9b63 645 struct hclge_func_status_cmd *req;
46a3df9f
S		 646 struct hclge_desc desc;
647 int timeout = 0;
648 int ret;
649
650 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 651 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 652
653 do {
654 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
655 if (ret) {
656 dev_err(&hdev->pdev->dev,
657 "query function status failed %d.\n",
658 ret);
659
660 return ret;
661 }
662
663 /* Check pf reset is done */
664 if (req->pf_state)
665 break;
666 usleep_range(1000, 2000);
667 } while (timeout++ < 5);
668
669 ret = hclge_parse_func_status(hdev, req);
670
671 return ret;
672}
673
674static int hclge_query_pf_resource(struct hclge_dev *hdev)
675{
d44f9b63 676 struct hclge_pf_res_cmd *req;
46a3df9f
S		 677 struct hclge_desc desc;
678 int ret;
679
680 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
681 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
682 if (ret) {
683 dev_err(&hdev->pdev->dev,
684 "query pf resource failed %d.\n", ret);
685 return ret;
686 }
687
d44f9b63 688 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 689 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
690 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
691
368686be
YL		 692 if (req->tx_buf_size)
693 hdev->tx_buf_size =
694 __le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S;
695 else
696 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
697
b9a400ac
YL		 698 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT);
699
368686be
YL		 700 if (req->dv_buf_size)
701 hdev->dv_buf_size =
702 __le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S;
703 else
704 hdev->dv_buf_size = HCLGE_DEFAULT_DV;
705
b9a400ac
YL		 706 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT);
707
e92a0843 708 if (hnae3_dev_roce_supported(hdev)) {
375dd5e4
JS		 709 hdev->roce_base_msix_offset =
710 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
711 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
887c3820 712 hdev->num_roce_msi =
e4e87715
PL		 713 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
714 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 715
716 /* PF should have NIC vectors and Roce vectors,
717 * NIC vectors are queued before Roce vectors.
718 */
375dd5e4
JS		 719 hdev->num_msi = hdev->num_roce_msi +
720 hdev->roce_base_msix_offset;
46a3df9f
S		 721 } else {
722 hdev->num_msi =
e4e87715
PL		 723 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
724 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 725 }
726
727 return 0;
728}
729
730static int hclge_parse_speed(int speed_cmd, int *speed)
731{
732 switch (speed_cmd) {
733 case 6:
734 *speed = HCLGE_MAC_SPEED_10M;
735 break;
736 case 7:
737 *speed = HCLGE_MAC_SPEED_100M;
738 break;
739 case 0:
740 *speed = HCLGE_MAC_SPEED_1G;
741 break;
742 case 1:
743 *speed = HCLGE_MAC_SPEED_10G;
744 break;
745 case 2:
746 *speed = HCLGE_MAC_SPEED_25G;
747 break;
748 case 3:
749 *speed = HCLGE_MAC_SPEED_40G;
750 break;
751 case 4:
752 *speed = HCLGE_MAC_SPEED_50G;
753 break;
754 case 5:
755 *speed = HCLGE_MAC_SPEED_100G;
756 break;
757 default:
758 return -EINVAL;
759 }
760
761 return 0;
762}
763
0979aa0b
FL		 764static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
765 u8 speed_ability)
766{
767 unsigned long *supported = hdev->hw.mac.supported;
768
769 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
770 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
771 supported);
772
773 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
774 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
775 supported);
776
777 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
778 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
779 supported);
780
781 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
782 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
783 supported);
784
785 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
786 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
787 supported);
788
789 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
790 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
791}
792
793static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
794{
795 u8 media_type = hdev->hw.mac.media_type;
796
797 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
798 return;
799
800 hclge_parse_fiber_link_mode(hdev, speed_ability);
801}
802
46a3df9f
S		 803static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
804{
d44f9b63 805 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 806 u64 mac_addr_tmp_high;
807 u64 mac_addr_tmp;
808 int i;
809
d44f9b63 810 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 811
812 /* get the configuration */
e4e87715
PL		 813 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
814 HCLGE_CFG_VMDQ_M,
815 HCLGE_CFG_VMDQ_S);
816 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
817 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
818 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
819 HCLGE_CFG_TQP_DESC_N_M,
820 HCLGE_CFG_TQP_DESC_N_S);
821
822 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
823 HCLGE_CFG_PHY_ADDR_M,
824 HCLGE_CFG_PHY_ADDR_S);
825 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
826 HCLGE_CFG_MEDIA_TP_M,
827 HCLGE_CFG_MEDIA_TP_S);
828 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
829 HCLGE_CFG_RX_BUF_LEN_M,
830 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 831 /* get mac_address */
832 mac_addr_tmp = __le32_to_cpu(req->param[2]);
e4e87715
PL		 833 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
834 HCLGE_CFG_MAC_ADDR_H_M,
835 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 836
837 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
838
e4e87715
PL		 839 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
840 HCLGE_CFG_DEFAULT_SPEED_M,
841 HCLGE_CFG_DEFAULT_SPEED_S);
842 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
843 HCLGE_CFG_RSS_SIZE_M,
844 HCLGE_CFG_RSS_SIZE_S);
0e7a40cd 845
46a3df9f
S		 846 for (i = 0; i < ETH_ALEN; i++)
847 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
848
d44f9b63 849 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 850 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
0979aa0b 851
e4e87715
PL		 852 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
853 HCLGE_CFG_SPEED_ABILITY_M,
854 HCLGE_CFG_SPEED_ABILITY_S);
39932473
JS		 855 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
856 HCLGE_CFG_UMV_TBL_SPACE_M,
857 HCLGE_CFG_UMV_TBL_SPACE_S);
858 if (!cfg->umv_space)
859 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
46a3df9f
S		 860}
861
862/* hclge_get_cfg: query the static parameter from flash
863 * @hdev: pointer to struct hclge_dev
864 * @hcfg: the config structure to be getted
865 */
866static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
867{
868 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 869 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 870 int i, ret;
871
872 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 873 u32 offset = 0;
874
d44f9b63 875 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 876 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
877 true);
e4e87715
PL		 878 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
879 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 880 /* Len should be united by 4 bytes when send to hardware */
e4e87715
PL		 881 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
882 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 883 req->offset = cpu_to_le32(offset);
46a3df9f
S		 884 }
885
886 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
887 if (ret) {
3f639907 888 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
46a3df9f
S		 889 return ret;
890 }
891
892 hclge_parse_cfg(hcfg, desc);
3f639907 893
46a3df9f
S		 894 return 0;
895}
896
897static int hclge_get_cap(struct hclge_dev *hdev)
898{
899 int ret;
900
901 ret = hclge_query_function_status(hdev);
902 if (ret) {
903 dev_err(&hdev->pdev->dev,
904 "query function status error %d.\n", ret);
905 return ret;
906 }
907
908 /* get pf resource */
909 ret = hclge_query_pf_resource(hdev);
3f639907
JS		 910 if (ret)
911 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
46a3df9f 912
3f639907 913 return ret;
46a3df9f
S		 914}
915
916static int hclge_configure(struct hclge_dev *hdev)
917{
918 struct hclge_cfg cfg;
919 int ret, i;
920
921 ret = hclge_get_cfg(hdev, &cfg);
922 if (ret) {
923 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
924 return ret;
925 }
926
927 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
928 hdev->base_tqp_pid = 0;
0e7a40cd 929 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 930 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 931 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 932 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 933 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 934 hdev->num_desc = cfg.tqp_desc_num;
935 hdev->tm_info.num_pg = 1;
cacde272 936 hdev->tc_max = cfg.tc_num;
46a3df9f 937 hdev->tm_info.hw_pfc_map = 0;
39932473 938 hdev->wanted_umv_size = cfg.umv_space;
46a3df9f
S		 939
940 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
941 if (ret) {
942 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
943 return ret;
944 }
945
0979aa0b
FL		 946 hclge_parse_link_mode(hdev, cfg.speed_ability);
947
cacde272
YL		 948 if ((hdev->tc_max > HNAE3_MAX_TC) ||
949 (hdev->tc_max < 1)) {
46a3df9f 950 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 951 hdev->tc_max);
952 hdev->tc_max = 1;
46a3df9f
S		 953 }
954
cacde272
YL		 955 /* Dev does not support DCB */
956 if (!hnae3_dev_dcb_supported(hdev)) {
957 hdev->tc_max = 1;
958 hdev->pfc_max = 0;
959 } else {
960 hdev->pfc_max = hdev->tc_max;
961 }
962
a2987975 963 hdev->tm_info.num_tc = 1;
cacde272 964
46a3df9f 965 /* Currently not support uncontiuous tc */
cacde272 966 for (i = 0; i < hdev->tm_info.num_tc; i++)
e4e87715 967 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 968
71b83869 969 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 970
971 return ret;
972}
973
974static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
975 int tso_mss_max)
976{
d44f9b63 977 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 978 struct hclge_desc desc;
a90bb9a5 979 u16 tso_mss;
46a3df9f
S		 980
981 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
982
d44f9b63 983 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 984
985 tso_mss = 0;
e4e87715
PL		 986 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
987 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 988 req->tso_mss_min = cpu_to_le16(tso_mss);
989
990 tso_mss = 0;
e4e87715
PL		 991 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
992 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 993 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 994
995 return hclge_cmd_send(&hdev->hw, &desc, 1);
996}
997
b26a6fea
PL		 998static int hclge_config_gro(struct hclge_dev *hdev, bool en)
999{
1000 struct hclge_cfg_gro_status_cmd *req;
1001 struct hclge_desc desc;
1002 int ret;
1003
1004 if (!hnae3_dev_gro_supported(hdev))
1005 return 0;
1006
1007 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
1008 req = (struct hclge_cfg_gro_status_cmd *)desc.data;
1009
1010 req->gro_en = cpu_to_le16(en ? 1 : 0);
1011
1012 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1013 if (ret)
1014 dev_err(&hdev->pdev->dev,
1015 "GRO hardware config cmd failed, ret = %d\n", ret);
1016
1017 return ret;
1018}
1019
46a3df9f
S		 1020static int hclge_alloc_tqps(struct hclge_dev *hdev)
1021{
1022 struct hclge_tqp *tqp;
1023 int i;
1024
1025 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1026 sizeof(struct hclge_tqp), GFP_KERNEL);
1027 if (!hdev->htqp)
1028 return -ENOMEM;
1029
1030 tqp = hdev->htqp;
1031
1032 for (i = 0; i < hdev->num_tqps; i++) {
1033 tqp->dev = &hdev->pdev->dev;
1034 tqp->index = i;
1035
1036 tqp->q.ae_algo = &ae_algo;
1037 tqp->q.buf_size = hdev->rx_buf_len;
1038 tqp->q.desc_num = hdev->num_desc;
1039 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1040 i * HCLGE_TQP_REG_SIZE;
1041
1042 tqp++;
1043 }
1044
1045 return 0;
1046}
1047
1048static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1049 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1050{
d44f9b63 1051 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1052 struct hclge_desc desc;
1053 int ret;
1054
1055 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1056
d44f9b63 1057 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1058 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1059 req->tqp_vf = func_id;
46a3df9f
S		 1060 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1061 1 << HCLGE_TQP_MAP_EN_B;
1062 req->tqp_vid = cpu_to_le16(tqp_vid);
1063
1064 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907
JS		 1065 if (ret)
1066 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
46a3df9f 1067
3f639907 1068 return ret;
46a3df9f
S		 1069}
1070
128b900d 1071static int hclge_assign_tqp(struct hclge_vport *vport)
46a3df9f 1072{
128b900d 1073 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
46a3df9f 1074 struct hclge_dev *hdev = vport->back;
7df7dad6 1075 int i, alloced;
46a3df9f
S		 1076
1077 for (i = 0, alloced = 0; i < hdev->num_tqps &&
128b900d 1078 alloced < kinfo->num_tqps; i++) {
46a3df9f
S		 1079 if (!hdev->htqp[i].alloced) {
1080 hdev->htqp[i].q.handle = &vport->nic;
1081 hdev->htqp[i].q.tqp_index = alloced;
128b900d
YL		 1082 hdev->htqp[i].q.desc_num = kinfo->num_desc;
1083 kinfo->tqp[alloced] = &hdev->htqp[i].q;
46a3df9f 1084 hdev->htqp[i].alloced = true;
46a3df9f
S		 1085 alloced++;
1086 }
1087 }
128b900d 1088 vport->alloc_tqps = kinfo->num_tqps;
46a3df9f
S		 1089
1090 return 0;
1091}
1092
128b900d
YL		 1093static int hclge_knic_setup(struct hclge_vport *vport,
1094 u16 num_tqps, u16 num_desc)
46a3df9f
S		 1095{
1096 struct hnae3_handle *nic = &vport->nic;
1097 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1098 struct hclge_dev *hdev = vport->back;
1099 int i, ret;
1100
128b900d 1101 kinfo->num_desc = num_desc;
46a3df9f
S		 1102 kinfo->rx_buf_len = hdev->rx_buf_len;
1103 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1104 kinfo->rss_size
1105 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1106 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1107
1108 for (i = 0; i < HNAE3_MAX_TC; i++) {
1109 if (hdev->hw_tc_map & BIT(i)) {
1110 kinfo->tc_info[i].enable = true;
1111 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1112 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1113 kinfo->tc_info[i].tc = i;
1114 } else {
1115 /* Set to default queue if TC is disable */
1116 kinfo->tc_info[i].enable = false;
1117 kinfo->tc_info[i].tqp_offset = 0;
1118 kinfo->tc_info[i].tqp_count = 1;
1119 kinfo->tc_info[i].tc = 0;
1120 }
1121 }
1122
1123 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1124 sizeof(struct hnae3_queue *), GFP_KERNEL);
1125 if (!kinfo->tqp)
1126 return -ENOMEM;
1127
128b900d 1128 ret = hclge_assign_tqp(vport);
3f639907 1129 if (ret)
46a3df9f 1130 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
46a3df9f 1131
3f639907 1132 return ret;
46a3df9f
S		 1133}
1134
7df7dad6
L		 1135static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1136 struct hclge_vport *vport)
1137{
1138 struct hnae3_handle *nic = &vport->nic;
1139 struct hnae3_knic_private_info *kinfo;
1140 u16 i;
1141
1142 kinfo = &nic->kinfo;
1143 for (i = 0; i < kinfo->num_tqps; i++) {
1144 struct hclge_tqp *q =
1145 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1146 bool is_pf;
1147 int ret;
1148
1149 is_pf = !(vport->vport_id);
1150 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1151 i, is_pf);
1152 if (ret)
1153 return ret;
1154 }
1155
1156 return 0;
1157}
1158
1159static int hclge_map_tqp(struct hclge_dev *hdev)
1160{
1161 struct hclge_vport *vport = hdev->vport;
1162 u16 i, num_vport;
1163
1164 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1165 for (i = 0; i < num_vport; i++) {
1166 int ret;
1167
1168 ret = hclge_map_tqp_to_vport(hdev, vport);
1169 if (ret)
1170 return ret;
1171
1172 vport++;
1173 }
1174
1175 return 0;
1176}
1177
46a3df9f
S		 1178static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1179{
1180 /* this would be initialized later */
1181}
1182
1183static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1184{
1185 struct hnae3_handle *nic = &vport->nic;
1186 struct hclge_dev *hdev = vport->back;
1187 int ret;
1188
1189 nic->pdev = hdev->pdev;
1190 nic->ae_algo = &ae_algo;
1191 nic->numa_node_mask = hdev->numa_node_mask;
1192
1193 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
128b900d 1194 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
46a3df9f
S		 1195 if (ret) {
1196 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1197 ret);
1198 return ret;
1199 }
1200 } else {
1201 hclge_unic_setup(vport, num_tqps);
1202 }
1203
1204 return 0;
1205}
1206
1207static int hclge_alloc_vport(struct hclge_dev *hdev)
1208{
1209 struct pci_dev *pdev = hdev->pdev;
1210 struct hclge_vport *vport;
1211 u32 tqp_main_vport;
1212 u32 tqp_per_vport;
1213 int num_vport, i;
1214 int ret;
1215
1216 /* We need to alloc a vport for main NIC of PF */
1217 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1218
38e62046
HT		 1219 if (hdev->num_tqps < num_vport) {
1220 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1221 hdev->num_tqps, num_vport);
1222 return -EINVAL;
1223 }
46a3df9f
S		 1224
1225 /* Alloc the same number of TQPs for every vport */
1226 tqp_per_vport = hdev->num_tqps / num_vport;
1227 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1228
1229 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1230 GFP_KERNEL);
1231 if (!vport)
1232 return -ENOMEM;
1233
1234 hdev->vport = vport;
1235 hdev->num_alloc_vport = num_vport;
1236
2312e050
FL		 1237 if (IS_ENABLED(CONFIG_PCI_IOV))
1238 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1239
1240 for (i = 0; i < num_vport; i++) {
1241 vport->back = hdev;
1242 vport->vport_id = i;
818f1675 1243 vport->mps = HCLGE_MAC_DEFAULT_FRAME;
46a3df9f
S		 1244
1245 if (i == 0)
1246 ret = hclge_vport_setup(vport, tqp_main_vport);
1247 else
1248 ret = hclge_vport_setup(vport, tqp_per_vport);
1249 if (ret) {
1250 dev_err(&pdev->dev,
1251 "vport setup failed for vport %d, %d\n",
1252 i, ret);
1253 return ret;
1254 }
1255
1256 vport++;
1257 }
1258
1259 return 0;
1260}
1261
acf61ecd
YL		 1262static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1263 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1264{
1265/* TX buffer size is unit by 128 byte */
1266#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1267#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1268 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1269 struct hclge_desc desc;
1270 int ret;
1271 u8 i;
1272
d44f9b63 1273 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1274
1275 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1276 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1277 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1278
46a3df9f
S		 1279 req->tx_pkt_buff[i] =
1280 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1281 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1282 }
46a3df9f
S		 1283
1284 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1285 if (ret)
46a3df9f
S		 1286 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1287 ret);
46a3df9f 1288
3f639907 1289 return ret;
46a3df9f
S		 1290}
1291
acf61ecd
YL		 1292static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1293 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1294{
acf61ecd 1295 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1296
3f639907
JS		 1297 if (ret)
1298 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
46a3df9f 1299
3f639907 1300 return ret;
46a3df9f
S		 1301}
1302
1303static int hclge_get_tc_num(struct hclge_dev *hdev)
1304{
1305 int i, cnt = 0;
1306
1307 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1308 if (hdev->hw_tc_map & BIT(i))
1309 cnt++;
1310 return cnt;
1311}
1312
1313static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1314{
1315 int i, cnt = 0;
1316
1317 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1318 if (hdev->hw_tc_map & BIT(i) &&
1319 hdev->tm_info.hw_pfc_map & BIT(i))
1320 cnt++;
1321 return cnt;
1322}
1323
1324/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1325static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1326 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1327{
1328 struct hclge_priv_buf *priv;
1329 int i, cnt = 0;
1330
1331 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1332 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1333 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1334 priv->enable)
1335 cnt++;
1336 }
1337
1338 return cnt;
1339}
1340
1341/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1342static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1343 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1344{
1345 struct hclge_priv_buf *priv;
1346 int i, cnt = 0;
1347
1348 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1349 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1350 if (hdev->hw_tc_map & BIT(i) &&
1351 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1352 priv->enable)
1353 cnt++;
1354 }
1355
1356 return cnt;
1357}
1358
acf61ecd 1359static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1360{
1361 struct hclge_priv_buf *priv;
1362 u32 rx_priv = 0;
1363 int i;
1364
1365 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1366 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1367 if (priv->enable)
1368 rx_priv += priv->buf_size;
1369 }
1370 return rx_priv;
1371}
1372
acf61ecd 1373static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1374{
1375 u32 i, total_tx_size = 0;
1376
1377 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1378 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1379
1380 return total_tx_size;
1381}
1382
acf61ecd
YL		 1383static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1384 struct hclge_pkt_buf_alloc *buf_alloc,
1385 u32 rx_all)
46a3df9f
S		 1386{
1387 u32 shared_buf_min, shared_buf_tc, shared_std;
1388 int tc_num, pfc_enable_num;
b9a400ac 1389 u32 shared_buf, aligned_mps;
46a3df9f
S		 1390 u32 rx_priv;
1391 int i;
1392
1393 tc_num = hclge_get_tc_num(hdev);
1394 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
b9a400ac 1395 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT);
46a3df9f 1396
d221df4e 1397 if (hnae3_dev_dcb_supported(hdev))
b9a400ac 1398 shared_buf_min = 2 * aligned_mps + hdev->dv_buf_size;
d221df4e 1399 else
b9a400ac 1400 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF
368686be 1401 + hdev->dv_buf_size;
d221df4e 1402
b9a400ac
YL		 1403 shared_buf_tc = pfc_enable_num * aligned_mps +
1404 (tc_num - pfc_enable_num) * aligned_mps / 2 +
1405 aligned_mps;
af854724
YL		 1406 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc),
1407 HCLGE_BUF_SIZE_UNIT);
46a3df9f 1408
acf61ecd 1409 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
af854724 1410 if (rx_all < rx_priv + shared_std)
46a3df9f
S		 1411 return false;
1412
b9a400ac 1413 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT);
acf61ecd 1414 buf_alloc->s_buf.buf_size = shared_buf;
368686be
YL		 1415 if (hnae3_dev_dcb_supported(hdev)) {
1416 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size;
1417 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
b9a400ac 1418 - roundup(aligned_mps / 2, HCLGE_BUF_SIZE_UNIT);
368686be 1419 } else {
b9a400ac 1420 buf_alloc->s_buf.self.high = aligned_mps +
368686be 1421 HCLGE_NON_DCB_ADDITIONAL_BUF;
b9a400ac
YL		 1422 buf_alloc->s_buf.self.low =
1423 roundup(aligned_mps / 2, HCLGE_BUF_SIZE_UNIT);
368686be 1424 }
46a3df9f
S		 1425
1426 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1427 if ((hdev->hw_tc_map & BIT(i)) &&
1428 (hdev->tm_info.hw_pfc_map & BIT(i))) {
b9a400ac
YL		 1429 buf_alloc->s_buf.tc_thrd[i].low = aligned_mps;
1430 buf_alloc->s_buf.tc_thrd[i].high = 2 * aligned_mps;
46a3df9f 1431 } else {
acf61ecd 1432 buf_alloc->s_buf.tc_thrd[i].low = 0;
b9a400ac 1433 buf_alloc->s_buf.tc_thrd[i].high = aligned_mps;
46a3df9f
S		 1434 }
1435 }
1436
1437 return true;
1438}
1439
acf61ecd
YL		 1440static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1441 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1442{
1443 u32 i, total_size;
1444
1445 total_size = hdev->pkt_buf_size;
1446
1447 /* alloc tx buffer for all enabled tc */
1448 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1449 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9 1450
368686be 1451 if (total_size < hdev->tx_buf_size)
9ffe79a9
YL		 1452 return -ENOMEM;
1453
1454 if (hdev->hw_tc_map & BIT(i))
368686be 1455 priv->tx_buf_size = hdev->tx_buf_size;
9ffe79a9
YL		 1456 else
1457 priv->tx_buf_size = 0;
1458
1459 total_size -= priv->tx_buf_size;
1460 }
1461
1462 return 0;
1463}
1464
46a3df9f
S		 1465/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1466 * @hdev: pointer to struct hclge_dev
acf61ecd 1467 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1468 * @return: 0: calculate sucessful, negative: fail
1469 */
1db9b1bf
YL		 1470static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1471 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1472{
996ff918 1473 u32 rx_all = hdev->pkt_buf_size, aligned_mps;
46a3df9f
S		 1474 int no_pfc_priv_num, pfc_priv_num;
1475 struct hclge_priv_buf *priv;
1476 int i;
1477
996ff918 1478 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
acf61ecd 1479 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1480
d602a525
YL		 1481 /* When DCB is not supported, rx private
1482 * buffer is not allocated.
1483 */
1484 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1485 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1486 return -ENOMEM;
1487
1488 return 0;
1489 }
1490
46a3df9f
S		 1491 /* step 1, try to alloc private buffer for all enabled tc */
1492 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1493 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1494 if (hdev->hw_tc_map & BIT(i)) {
1495 priv->enable = 1;
1496 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
996ff918 1497 priv->wl.low = aligned_mps;
b9a400ac
YL		 1498 priv->wl.high =
1499 roundup(priv->wl.low + aligned_mps,
1500 HCLGE_BUF_SIZE_UNIT);
46a3df9f 1501 priv->buf_size = priv->wl.high +
b9a400ac 1502 hdev->dv_buf_size;
46a3df9f
S		 1503 } else {
1504 priv->wl.low = 0;
996ff918 1505 priv->wl.high = 2 * aligned_mps;
368686be
YL		 1506 priv->buf_size = priv->wl.high +
1507 hdev->dv_buf_size;
46a3df9f 1508 }
bb1fe9ea
YL		 1509 } else {
1510 priv->enable = 0;
1511 priv->wl.low = 0;
1512 priv->wl.high = 0;
1513 priv->buf_size = 0;
46a3df9f
S		 1514 }
1515 }
1516
acf61ecd 1517 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1518 return 0;
1519
1520 /* step 2, try to decrease the buffer size of
1521 * no pfc TC's private buffer
1522 */
1523 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1524 priv = &buf_alloc->priv_buf[i];
46a3df9f 1525
bb1fe9ea
YL		 1526 priv->enable = 0;
1527 priv->wl.low = 0;
1528 priv->wl.high = 0;
1529 priv->buf_size = 0;
1530
1531 if (!(hdev->hw_tc_map & BIT(i)))
1532 continue;
1533
1534 priv->enable = 1;
46a3df9f
S		 1535
1536 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
b9a400ac 1537 priv->wl.low = 256;
996ff918 1538 priv->wl.high = priv->wl.low + aligned_mps;
368686be 1539 priv->buf_size = priv->wl.high + hdev->dv_buf_size;
46a3df9f
S		 1540 } else {
1541 priv->wl.low = 0;
996ff918 1542 priv->wl.high = aligned_mps;
368686be 1543 priv->buf_size = priv->wl.high + hdev->dv_buf_size;
46a3df9f
S		 1544 }
1545 }
1546
acf61ecd 1547 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1548 return 0;
1549
1550 /* step 3, try to reduce the number of pfc disabled TCs,
1551 * which have private buffer
1552 */
1553 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1554 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1555
1556 /* let the last to be cleared first */
1557 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1558 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1559
1560 if (hdev->hw_tc_map & BIT(i) &&
1561 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1562 /* Clear the no pfc TC private buffer */
1563 priv->wl.low = 0;
1564 priv->wl.high = 0;
1565 priv->buf_size = 0;
1566 priv->enable = 0;
1567 no_pfc_priv_num--;
1568 }
1569
acf61ecd 1570 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1571 no_pfc_priv_num == 0)
1572 break;
1573 }
1574
acf61ecd 1575 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1576 return 0;
1577
1578 /* step 4, try to reduce the number of pfc enabled TCs
1579 * which have private buffer.
1580 */
acf61ecd 1581 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1582
1583 /* let the last to be cleared first */
1584 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1585 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1586
1587 if (hdev->hw_tc_map & BIT(i) &&
1588 hdev->tm_info.hw_pfc_map & BIT(i)) {
1589 /* Reduce the number of pfc TC with private buffer */
1590 priv->wl.low = 0;
1591 priv->enable = 0;
1592 priv->wl.high = 0;
1593 priv->buf_size = 0;
1594 pfc_priv_num--;
1595 }
1596
acf61ecd 1597 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1598 pfc_priv_num == 0)
1599 break;
1600 }
acf61ecd 1601 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1602 return 0;
1603
1604 return -ENOMEM;
1605}
1606
acf61ecd
YL		 1607static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1608 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1609{
d44f9b63 1610 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1611 struct hclge_desc desc;
1612 int ret;
1613 int i;
1614
1615 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1616 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1617
1618 /* Alloc private buffer TCs */
1619 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1620 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1621
1622 req->buf_num[i] =
1623 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1624 req->buf_num[i] |=
5bca3b94 1625 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1626 }
1627
b8c8bf47 1628 req->shared_buf =
acf61ecd 1629 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1630 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1631
46a3df9f 1632 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1633 if (ret)
46a3df9f
S		 1634 dev_err(&hdev->pdev->dev,
1635 "rx private buffer alloc cmd failed %d\n", ret);
46a3df9f 1636
3f639907 1637 return ret;
46a3df9f
S		 1638}
1639
acf61ecd
YL		 1640static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1641 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1642{
1643 struct hclge_rx_priv_wl_buf *req;
1644 struct hclge_priv_buf *priv;
1645 struct hclge_desc desc[2];
1646 int i, j;
1647 int ret;
1648
1649 for (i = 0; i < 2; i++) {
1650 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1651 false);
1652 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1653
1654 /* The first descriptor set the NEXT bit to 1 */
1655 if (i == 0)
1656 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1657 else
1658 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1659
1660 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1661 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1662
1663 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1664 req->tc_wl[j].high =
1665 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1666 req->tc_wl[j].high |=
3738287c 1667 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1668 req->tc_wl[j].low =
1669 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1670 req->tc_wl[j].low |=
3738287c 1671 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1672 }
1673 }
1674
1675 /* Send 2 descriptor at one time */
1676 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3f639907 1677 if (ret)
46a3df9f
S		 1678 dev_err(&hdev->pdev->dev,
1679 "rx private waterline config cmd failed %d\n",
1680 ret);
3f639907 1681 return ret;
46a3df9f
S		 1682}
1683
acf61ecd
YL		 1684static int hclge_common_thrd_config(struct hclge_dev *hdev,
1685 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1686{
acf61ecd 1687 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1688 struct hclge_rx_com_thrd *req;
1689 struct hclge_desc desc[2];
1690 struct hclge_tc_thrd *tc;
1691 int i, j;
1692 int ret;
1693
1694 for (i = 0; i < 2; i++) {
1695 hclge_cmd_setup_basic_desc(&desc[i],
1696 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1697 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1698
1699 /* The first descriptor set the NEXT bit to 1 */
1700 if (i == 0)
1701 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1702 else
1703 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1704
1705 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1706 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1707
1708 req->com_thrd[j].high =
1709 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1710 req->com_thrd[j].high |=
3738287c 1711 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1712 req->com_thrd[j].low =
1713 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1714 req->com_thrd[j].low |=
3738287c 1715 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1716 }
1717 }
1718
1719 /* Send 2 descriptors at one time */
1720 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3f639907 1721 if (ret)
46a3df9f
S		 1722 dev_err(&hdev->pdev->dev,
1723 "common threshold config cmd failed %d\n", ret);
3f639907 1724 return ret;
46a3df9f
S		 1725}
1726
acf61ecd
YL		 1727static int hclge_common_wl_config(struct hclge_dev *hdev,
1728 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1729{
acf61ecd 1730 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1731 struct hclge_rx_com_wl *req;
1732 struct hclge_desc desc;
1733 int ret;
1734
1735 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1736
1737 req = (struct hclge_rx_com_wl *)desc.data;
1738 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
3738287c 1739 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1740
1741 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
3738287c 1742 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1743
1744 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1745 if (ret)
46a3df9f
S		 1746 dev_err(&hdev->pdev->dev,
1747 "common waterline config cmd failed %d\n", ret);
46a3df9f 1748
3f639907 1749 return ret;
46a3df9f
S		 1750}
1751
1752int hclge_buffer_alloc(struct hclge_dev *hdev)
1753{
acf61ecd 1754 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1755 int ret;
1756
acf61ecd
YL		 1757 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1758 if (!pkt_buf)
46a3df9f
S		 1759 return -ENOMEM;
1760
acf61ecd 1761 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1762 if (ret) {
1763 dev_err(&hdev->pdev->dev,
1764 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1765 goto out;
9ffe79a9
YL		 1766 }
1767
acf61ecd 1768 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1769 if (ret) {
1770 dev_err(&hdev->pdev->dev,
1771 "could not alloc tx buffers %d\n", ret);
acf61ecd 1772 goto out;
46a3df9f
S		 1773 }
1774
acf61ecd 1775 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1776 if (ret) {
1777 dev_err(&hdev->pdev->dev,
1778 "could not calc rx priv buffer size for all TCs %d\n",
1779 ret);
acf61ecd 1780 goto out;
46a3df9f
S		 1781 }
1782
acf61ecd 1783 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1784 if (ret) {
1785 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1786 ret);
acf61ecd 1787 goto out;
46a3df9f
S		 1788 }
1789
2daf4a65 1790 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1791 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1792 if (ret) {
1793 dev_err(&hdev->pdev->dev,
1794 "could not configure rx private waterline %d\n",
1795 ret);
acf61ecd 1796 goto out;
2daf4a65 1797 }
46a3df9f 1798
acf61ecd 1799 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1800 if (ret) {
1801 dev_err(&hdev->pdev->dev,
1802 "could not configure common threshold %d\n",
1803 ret);
acf61ecd 1804 goto out;
2daf4a65 1805 }
46a3df9f
S		 1806 }
1807
acf61ecd
YL		 1808 ret = hclge_common_wl_config(hdev, pkt_buf);
1809 if (ret)
46a3df9f
S		 1810 dev_err(&hdev->pdev->dev,
1811 "could not configure common waterline %d\n", ret);
46a3df9f 1812
acf61ecd
YL		 1813out:
1814 kfree(pkt_buf);
1815 return ret;
46a3df9f
S		 1816}
1817
1818static int hclge_init_roce_base_info(struct hclge_vport *vport)
1819{
1820 struct hnae3_handle *roce = &vport->roce;
1821 struct hnae3_handle *nic = &vport->nic;
1822
887c3820 1823 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1824
1825 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1826 vport->back->num_msi_left == 0)
1827 return -EINVAL;
1828
1829 roce->rinfo.base_vector = vport->back->roce_base_vector;
1830
1831 roce->rinfo.netdev = nic->kinfo.netdev;
1832 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1833
1834 roce->pdev = nic->pdev;
1835 roce->ae_algo = nic->ae_algo;
1836 roce->numa_node_mask = nic->numa_node_mask;
1837
1838 return 0;
1839}
1840
887c3820 1841static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1842{
1843 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1844 int vectors;
1845 int i;
46a3df9f 1846
887c3820
SM		 1847 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1848 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1849 if (vectors < 0) {
1850 dev_err(&pdev->dev,
1851 "failed(%d) to allocate MSI/MSI-X vectors\n",
1852 vectors);
1853 return vectors;
46a3df9f 1854 }
887c3820
SM		 1855 if (vectors < hdev->num_msi)
1856 dev_warn(&hdev->pdev->dev,
1857 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1858 hdev->num_msi, vectors);
46a3df9f 1859
887c3820
SM		 1860 hdev->num_msi = vectors;
1861 hdev->num_msi_left = vectors;
1862 hdev->base_msi_vector = pdev->irq;
46a3df9f 1863 hdev->roce_base_vector = hdev->base_msi_vector +
375dd5e4 1864 hdev->roce_base_msix_offset;
46a3df9f 1865
46a3df9f
S		 1866 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1867 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1868 if (!hdev->vector_status) {
1869 pci_free_irq_vectors(pdev);
46a3df9f 1870 return -ENOMEM;
887c3820 1871 }
46a3df9f
S		 1872
1873 for (i = 0; i < hdev->num_msi; i++)
1874 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1875
887c3820
SM		 1876 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1877 sizeof(int), GFP_KERNEL);
1878 if (!hdev->vector_irq) {
1879 pci_free_irq_vectors(pdev);
1880 return -ENOMEM;
46a3df9f 1881 }
46a3df9f
S		 1882
1883 return 0;
1884}
1885
2d03eacc 1886static u8 hclge_check_speed_dup(u8 duplex, int speed)
46a3df9f 1887{
46a3df9f 1888
2d03eacc
YL		 1889 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1890 duplex = HCLGE_MAC_FULL;
46a3df9f 1891
2d03eacc 1892 return duplex;
46a3df9f
S		 1893}
1894
2d03eacc
YL		 1895static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1896 u8 duplex)
46a3df9f 1897{
d44f9b63 1898 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 1899 struct hclge_desc desc;
1900 int ret;
1901
d44f9b63 1902 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 1903
1904 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1905
e4e87715 1906 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 1907
1908 switch (speed) {
1909 case HCLGE_MAC_SPEED_10M:
e4e87715
PL		 1910 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1911 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 1912 break;
1913 case HCLGE_MAC_SPEED_100M:
e4e87715
PL		 1914 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1915 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 1916 break;
1917 case HCLGE_MAC_SPEED_1G:
e4e87715
PL		 1918 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1919 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 1920 break;
1921 case HCLGE_MAC_SPEED_10G:
e4e87715
PL		 1922 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1923 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 1924 break;
1925 case HCLGE_MAC_SPEED_25G:
e4e87715
PL		 1926 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1927 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 1928 break;
1929 case HCLGE_MAC_SPEED_40G:
e4e87715
PL		 1930 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1931 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 1932 break;
1933 case HCLGE_MAC_SPEED_50G:
e4e87715
PL		 1934 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1935 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 1936 break;
1937 case HCLGE_MAC_SPEED_100G:
e4e87715
PL		 1938 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1939 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 1940 break;
1941 default:
d7629e74 1942 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 1943 return -EINVAL;
1944 }
1945
e4e87715
PL		 1946 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1947 1);
46a3df9f
S		 1948
1949 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1950 if (ret) {
1951 dev_err(&hdev->pdev->dev,
1952 "mac speed/duplex config cmd failed %d.\n", ret);
1953 return ret;
1954 }
1955
2d03eacc
YL		 1956 return 0;
1957}
1958
1959int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1960{
1961 int ret;
1962
1963 duplex = hclge_check_speed_dup(duplex, speed);
1964 if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1965 return 0;
1966
1967 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1968 if (ret)
1969 return ret;
1970
1971 hdev->hw.mac.speed = speed;
1972 hdev->hw.mac.duplex = duplex;
46a3df9f
S		 1973
1974 return 0;
1975}
1976
1977static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1978 u8 duplex)
1979{
1980 struct hclge_vport *vport = hclge_get_vport(handle);
1981 struct hclge_dev *hdev = vport->back;
1982
1983 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1984}
1985
46a3df9f
S		 1986static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1987{
d44f9b63 1988 struct hclge_config_auto_neg_cmd *req;
46a3df9f 1989 struct hclge_desc desc;
a90bb9a5 1990 u32 flag = 0;
46a3df9f
S		 1991 int ret;
1992
1993 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1994
d44f9b63 1995 req = (struct hclge_config_auto_neg_cmd *)desc.data;
e4e87715 1996 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 1997 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 1998
1999 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 2000 if (ret)
46a3df9f
S		 2001 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2002 ret);
46a3df9f 2003
3f639907 2004 return ret;
46a3df9f
S		 2005}
2006
2007static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2008{
2009 struct hclge_vport *vport = hclge_get_vport(handle);
2010 struct hclge_dev *hdev = vport->back;
2011
2012 return hclge_set_autoneg_en(hdev, enable);
2013}
2014
2015static int hclge_get_autoneg(struct hnae3_handle *handle)
2016{
2017 struct hclge_vport *vport = hclge_get_vport(handle);
2018 struct hclge_dev *hdev = vport->back;
27b5bf49
FL		 2019 struct phy_device *phydev = hdev->hw.mac.phydev;
2020
2021 if (phydev)
2022 return phydev->autoneg;
46a3df9f
S		 2023
2024 return hdev->hw.mac.autoneg;
2025}
2026
2027static int hclge_mac_init(struct hclge_dev *hdev)
2028{
2029 struct hclge_mac *mac = &hdev->hw.mac;
2030 int ret;
2031
5d497936 2032 hdev->support_sfp_query = true;
2d03eacc
YL		 2033 hdev->hw.mac.duplex = HCLGE_MAC_FULL;
2034 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
2035 hdev->hw.mac.duplex);
46a3df9f
S		 2036 if (ret) {
2037 dev_err(&hdev->pdev->dev,
2038 "Config mac speed dup fail ret=%d\n", ret);
2039 return ret;
2040 }
2041
2042 mac->link = 0;
2043
e6d7d79d
YL		 2044 ret = hclge_set_mac_mtu(hdev, hdev->mps);
2045 if (ret) {
2046 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret);
2047 return ret;
2048 }
f9fd82a9 2049
e6d7d79d 2050 ret = hclge_buffer_alloc(hdev);
3f639907 2051 if (ret)
f9fd82a9 2052 dev_err(&hdev->pdev->dev,
e6d7d79d 2053 "allocate buffer fail, ret=%d\n", ret);
f9fd82a9 2054
3f639907 2055 return ret;
46a3df9f
S		 2056}
2057
c1a81619
SM		 2058static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2059{
2060 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2061 schedule_work(&hdev->mbx_service_task);
2062}
2063
cb1b9f77
SM		 2064static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2065{
2066 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2067 schedule_work(&hdev->rst_service_task);
2068}
2069
46a3df9f
S		 2070static void hclge_task_schedule(struct hclge_dev *hdev)
2071{
2072 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2073 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2074 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2075 (void)schedule_work(&hdev->service_task);
2076}
2077
2078static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2079{
d44f9b63 2080 struct hclge_link_status_cmd *req;
46a3df9f
S		 2081 struct hclge_desc desc;
2082 int link_status;
2083 int ret;
2084
2085 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2086 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2087 if (ret) {
2088 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2089 ret);
2090 return ret;
2091 }
2092
d44f9b63 2093 req = (struct hclge_link_status_cmd *)desc.data;
c79301d8 2094 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
46a3df9f
S		 2095
2096 return !!link_status;
2097}
2098
2099static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2100{
2101 int mac_state;
2102 int link_stat;
2103
582d37bb
PL		 2104 if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2105 return 0;
2106
46a3df9f
S		 2107 mac_state = hclge_get_mac_link_status(hdev);
2108
2109 if (hdev->hw.mac.phydev) {
fd813314 2110 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
46a3df9f
S		 2111 link_stat = mac_state &
2112 hdev->hw.mac.phydev->link;
2113 else
2114 link_stat = 0;
2115
2116 } else {
2117 link_stat = mac_state;
2118 }
2119
2120 return !!link_stat;
2121}
2122
2123static void hclge_update_link_status(struct hclge_dev *hdev)
2124{
2125 struct hnae3_client *client = hdev->nic_client;
2126 struct hnae3_handle *handle;
2127 int state;
2128 int i;
2129
2130 if (!client)
2131 return;
2132 state = hclge_get_mac_phy_link(hdev);
2133 if (state != hdev->hw.mac.link) {
2134 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2135 handle = &hdev->vport[i].nic;
2136 client->ops->link_status_change(handle, state);
2137 }
2138 hdev->hw.mac.link = state;
2139 }
2140}
2141
5d497936
PL		 2142static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed)
2143{
2144 struct hclge_sfp_speed_cmd *resp = NULL;
2145 struct hclge_desc desc;
2146 int ret;
2147
2148 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SFP_GET_SPEED, true);
2149 resp = (struct hclge_sfp_speed_cmd *)desc.data;
2150 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2151 if (ret == -EOPNOTSUPP) {
2152 dev_warn(&hdev->pdev->dev,
2153 "IMP do not support get SFP speed %d\n", ret);
2154 return ret;
2155 } else if (ret) {
2156 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret);
2157 return ret;
2158 }
2159
2160 *speed = resp->sfp_speed;
2161
2162 return 0;
2163}
2164
46a3df9f
S		 2165static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2166{
2167 struct hclge_mac mac = hdev->hw.mac;
46a3df9f
S		 2168 int speed;
2169 int ret;
2170
5d497936 2171 /* get the speed from SFP cmd when phy
46a3df9f
S		 2172 * doesn't exit.
2173 */
5d497936 2174 if (mac.phydev)
46a3df9f
S		 2175 return 0;
2176
5d497936
PL		 2177 /* if IMP does not support get SFP/qSFP speed, return directly */
2178 if (!hdev->support_sfp_query)
2179 return 0;
46a3df9f 2180
5d497936
PL		 2181 ret = hclge_get_sfp_speed(hdev, &speed);
2182 if (ret == -EOPNOTSUPP) {
2183 hdev->support_sfp_query = false;
2184 return ret;
2185 } else if (ret) {
2d03eacc 2186 return ret;
46a3df9f
S		 2187 }
2188
5d497936
PL		 2189 if (speed == HCLGE_MAC_SPEED_UNKNOWN)
2190 return 0; /* do nothing if no SFP */
2191
2192 /* must config full duplex for SFP */
2193 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL);
46a3df9f
S		 2194}
2195
2196static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2197{
2198 struct hclge_vport *vport = hclge_get_vport(handle);
2199 struct hclge_dev *hdev = vport->back;
2200
2201 return hclge_update_speed_duplex(hdev);
2202}
2203
2204static int hclge_get_status(struct hnae3_handle *handle)
2205{
2206 struct hclge_vport *vport = hclge_get_vport(handle);
2207 struct hclge_dev *hdev = vport->back;
2208
2209 hclge_update_link_status(hdev);
2210
2211 return hdev->hw.mac.link;
2212}
2213
d039ef68 2214static void hclge_service_timer(struct timer_list *t)
46a3df9f 2215{
d039ef68 2216 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2217
d039ef68 2218 mod_timer(&hdev->service_timer, jiffies + HZ);
c5f65480 2219 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2220 hclge_task_schedule(hdev);
2221}
2222
2223static void hclge_service_complete(struct hclge_dev *hdev)
2224{
2225 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2226
2227 /* Flush memory before next watchdog */
2228 smp_mb__before_atomic();
2229 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2230}
2231
ca1d7669
SM		 2232static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2233{
f6162d44 2234 u32 rst_src_reg, cmdq_src_reg, msix_src_reg;
ca1d7669
SM		 2235
2236 /* fetch the events from their corresponding regs */
9ca8d1a7 2237 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
c1a81619 2238 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
f6162d44
SM		 2239 msix_src_reg = hclge_read_dev(&hdev->hw,
2240 HCLGE_VECTOR0_PF_OTHER_INT_STS_REG);
c1a81619
SM		 2241
2242 /* Assumption: If by any chance reset and mailbox events are reported
2243 * together then we will only process reset event in this go and will
2244 * defer the processing of the mailbox events. Since, we would have not
2245 * cleared RX CMDQ event this time we would receive again another
2246 * interrupt from H/W just for the mailbox.
2247 */
ca1d7669
SM		 2248
2249 /* check for vector0 reset event sources */
6dd22bbc
HT		 2250 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2251 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
2252 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2253 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2254 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2255 return HCLGE_VECTOR0_EVENT_RST;
2256 }
2257
ca1d7669 2258 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
65e41e7e 2259 dev_info(&hdev->pdev->dev, "global reset interrupt\n");
8d40854f 2260 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ca1d7669
SM		 2261 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2262 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2263 return HCLGE_VECTOR0_EVENT_RST;
2264 }
2265
2266 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
65e41e7e 2267 dev_info(&hdev->pdev->dev, "core reset interrupt\n");
8d40854f 2268 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ca1d7669
SM		 2269 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2270 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2271 return HCLGE_VECTOR0_EVENT_RST;
2272 }
2273
f6162d44
SM		 2274 /* check for vector0 msix event source */
2275 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK)
2276 return HCLGE_VECTOR0_EVENT_ERR;
2277
c1a81619
SM		 2278 /* check for vector0 mailbox(=CMDQ RX) event source */
2279 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2280 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2281 *clearval = cmdq_src_reg;
2282 return HCLGE_VECTOR0_EVENT_MBX;
2283 }
ca1d7669
SM		 2284
2285 return HCLGE_VECTOR0_EVENT_OTHER;
2286}
2287
2288static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2289 u32 regclr)
2290{
c1a81619
SM		 2291 switch (event_type) {
2292 case HCLGE_VECTOR0_EVENT_RST:
ca1d7669 2293 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
c1a81619
SM		 2294 break;
2295 case HCLGE_VECTOR0_EVENT_MBX:
2296 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2297 break;
fa7a4bd5
JS		 2298 default:
2299 break;
c1a81619 2300 }
ca1d7669
SM		 2301}
2302
8e52a602
XW		 2303static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2304{
2305 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2306 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2307 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2308 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2309 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2310}
2311
466b0c00
L		 2312static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2313{
2314 writel(enable ? 1 : 0, vector->addr);
2315}
2316
2317static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2318{
2319 struct hclge_dev *hdev = data;
ca1d7669
SM		 2320 u32 event_cause;
2321 u32 clearval;
466b0c00
L		 2322
2323 hclge_enable_vector(&hdev->misc_vector, false);
ca1d7669
SM		 2324 event_cause = hclge_check_event_cause(hdev, &clearval);
2325
c1a81619 2326 /* vector 0 interrupt is shared with reset and mailbox source events.*/
ca1d7669 2327 switch (event_cause) {
f6162d44
SM		 2328 case HCLGE_VECTOR0_EVENT_ERR:
2329 /* we do not know what type of reset is required now. This could
2330 * only be decided after we fetch the type of errors which
2331 * caused this event. Therefore, we will do below for now:
2332 * 1. Assert HNAE3_UNKNOWN_RESET type of reset. This means we
2333 * have defered type of reset to be used.
2334 * 2. Schedule the reset serivce task.
2335 * 3. When service task receives HNAE3_UNKNOWN_RESET type it
2336 * will fetch the correct type of reset. This would be done
2337 * by first decoding the types of errors.
2338 */
2339 set_bit(HNAE3_UNKNOWN_RESET, &hdev->reset_request);
2340 /* fall through */
ca1d7669 2341 case HCLGE_VECTOR0_EVENT_RST:
cb1b9f77 2342 hclge_reset_task_schedule(hdev);
ca1d7669 2343 break;
c1a81619
SM		 2344 case HCLGE_VECTOR0_EVENT_MBX:
2345 /* If we are here then,
2346 * 1. Either we are not handling any mbx task and we are not
2347 * scheduled as well
2348 * OR
2349 * 2. We could be handling a mbx task but nothing more is
2350 * scheduled.
2351 * In both cases, we should schedule mbx task as there are more
2352 * mbx messages reported by this interrupt.
2353 */
2354 hclge_mbx_task_schedule(hdev);
f0ad97ac 2355 break;
ca1d7669 2356 default:
f0ad97ac
YL		 2357 dev_warn(&hdev->pdev->dev,
2358 "received unknown or unhandled event of vector0\n");
ca1d7669
SM		 2359 break;
2360 }
2361
cd8c5c26 2362 /* clear the source of interrupt if it is not cause by reset */
0d441140 2363 if (event_cause == HCLGE_VECTOR0_EVENT_MBX) {
cd8c5c26
YL		 2364 hclge_clear_event_cause(hdev, event_cause, clearval);
2365 hclge_enable_vector(&hdev->misc_vector, true);
2366 }
466b0c00
L		 2367
2368 return IRQ_HANDLED;
2369}
2370
2371static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2372{
36cbbdf6
PL		 2373 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2374 dev_warn(&hdev->pdev->dev,
2375 "vector(vector_id %d) has been freed.\n", vector_id);
2376 return;
2377 }
2378
466b0c00
L		 2379 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2380 hdev->num_msi_left += 1;
2381 hdev->num_msi_used -= 1;
2382}
2383
2384static void hclge_get_misc_vector(struct hclge_dev *hdev)
2385{
2386 struct hclge_misc_vector *vector = &hdev->misc_vector;
2387
2388 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2389
2390 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2391 hdev->vector_status[0] = 0;
2392
2393 hdev->num_msi_left -= 1;
2394 hdev->num_msi_used += 1;
2395}
2396
2397static int hclge_misc_irq_init(struct hclge_dev *hdev)
2398{
2399 int ret;
2400
2401 hclge_get_misc_vector(hdev);
2402
ca1d7669
SM		 2403 /* this would be explicitly freed in the end */
2404 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2405 0, "hclge_misc", hdev);
466b0c00
L		 2406 if (ret) {
2407 hclge_free_vector(hdev, 0);
2408 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2409 hdev->misc_vector.vector_irq);
2410 }
2411
2412 return ret;
2413}
2414
ca1d7669
SM		 2415static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2416{
2417 free_irq(hdev->misc_vector.vector_irq, hdev);
2418 hclge_free_vector(hdev, 0);
2419}
2420
4ed340ab
L		 2421static int hclge_notify_client(struct hclge_dev *hdev,
2422 enum hnae3_reset_notify_type type)
2423{
2424 struct hnae3_client *client = hdev->nic_client;
2425 u16 i;
2426
2427 if (!client->ops->reset_notify)
2428 return -EOPNOTSUPP;
2429
2430 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2431 struct hnae3_handle *handle = &hdev->vport[i].nic;
2432 int ret;
2433
2434 ret = client->ops->reset_notify(handle, type);
65e41e7e
HT		 2435 if (ret) {
2436 dev_err(&hdev->pdev->dev,
2437 "notify nic client failed %d(%d)\n", type, ret);
4ed340ab 2438 return ret;
65e41e7e 2439 }
4ed340ab
L		 2440 }
2441
2442 return 0;
2443}
2444
f403a84f
HT		 2445static int hclge_notify_roce_client(struct hclge_dev *hdev,
2446 enum hnae3_reset_notify_type type)
2447{
2448 struct hnae3_client *client = hdev->roce_client;
2449 int ret = 0;
2450 u16 i;
2451
2452 if (!client)
2453 return 0;
2454
2455 if (!client->ops->reset_notify)
2456 return -EOPNOTSUPP;
2457
2458 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2459 struct hnae3_handle *handle = &hdev->vport[i].roce;
2460
2461 ret = client->ops->reset_notify(handle, type);
2462 if (ret) {
2463 dev_err(&hdev->pdev->dev,
2464 "notify roce client failed %d(%d)",
2465 type, ret);
2466 return ret;
2467 }
2468 }
2469
2470 return ret;
2471}
2472
4ed340ab
L		 2473static int hclge_reset_wait(struct hclge_dev *hdev)
2474{
2475#define HCLGE_RESET_WATI_MS 100
6dd22bbc 2476#define HCLGE_RESET_WAIT_CNT 200
4ed340ab
L		 2477 u32 val, reg, reg_bit;
2478 u32 cnt = 0;
2479
2480 switch (hdev->reset_type) {
6dd22bbc
HT		 2481 case HNAE3_IMP_RESET:
2482 reg = HCLGE_GLOBAL_RESET_REG;
2483 reg_bit = HCLGE_IMP_RESET_BIT;
2484 break;
4ed340ab
L		 2485 case HNAE3_GLOBAL_RESET:
2486 reg = HCLGE_GLOBAL_RESET_REG;
2487 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2488 break;
2489 case HNAE3_CORE_RESET:
2490 reg = HCLGE_GLOBAL_RESET_REG;
2491 reg_bit = HCLGE_CORE_RESET_BIT;
2492 break;
2493 case HNAE3_FUNC_RESET:
2494 reg = HCLGE_FUN_RST_ING;
2495 reg_bit = HCLGE_FUN_RST_ING_B;
2496 break;
6b9a97ee
HT		 2497 case HNAE3_FLR_RESET:
2498 break;
4ed340ab
L		 2499 default:
2500 dev_err(&hdev->pdev->dev,
2501 "Wait for unsupported reset type: %d\n",
2502 hdev->reset_type);
2503 return -EINVAL;
2504 }
2505
6b9a97ee
HT		 2506 if (hdev->reset_type == HNAE3_FLR_RESET) {
2507 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) &&
2508 cnt++ < HCLGE_RESET_WAIT_CNT)
2509 msleep(HCLGE_RESET_WATI_MS);
2510
2511 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) {
2512 dev_err(&hdev->pdev->dev,
2513 "flr wait timeout: %d\n", cnt);
2514 return -EBUSY;
2515 }
2516
2517 return 0;
2518 }
2519
4ed340ab 2520 val = hclge_read_dev(&hdev->hw, reg);
e4e87715 2521 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
4ed340ab
L		 2522 msleep(HCLGE_RESET_WATI_MS);
2523 val = hclge_read_dev(&hdev->hw, reg);
2524 cnt++;
2525 }
2526
4ed340ab
L		 2527 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2528 dev_warn(&hdev->pdev->dev,
2529 "Wait for reset timeout: %d\n", hdev->reset_type);
2530 return -EBUSY;
2531 }
2532
2533 return 0;
2534}
2535
aa5c4f17
HT		 2536static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
2537{
2538 struct hclge_vf_rst_cmd *req;
2539 struct hclge_desc desc;
2540
2541 req = (struct hclge_vf_rst_cmd *)desc.data;
2542 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
2543 req->dest_vfid = func_id;
2544
2545 if (reset)
2546 req->vf_rst = 0x1;
2547
2548 return hclge_cmd_send(&hdev->hw, &desc, 1);
2549}
2550
2551int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
2552{
2553 int i;
2554
2555 for (i = hdev->num_vmdq_vport + 1; i < hdev->num_alloc_vport; i++) {
2556 struct hclge_vport *vport = &hdev->vport[i];
2557 int ret;
2558
2559 /* Send cmd to set/clear VF's FUNC_RST_ING */
2560 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
2561 if (ret) {
2562 dev_err(&hdev->pdev->dev,
790cd1a8 2563 "set vf(%d) rst failed %d!\n",
aa5c4f17
HT		 2564 vport->vport_id, ret);
2565 return ret;
2566 }
2567
2568 if (!reset)
2569 continue;
2570
2571 /* Inform VF to process the reset.
2572 * hclge_inform_reset_assert_to_vf may fail if VF
2573 * driver is not loaded.
2574 */
2575 ret = hclge_inform_reset_assert_to_vf(vport);
2576 if (ret)
2577 dev_warn(&hdev->pdev->dev,
790cd1a8 2578 "inform reset to vf(%d) failed %d!\n",
aa5c4f17
HT		 2579 vport->vport_id, ret);
2580 }
2581
2582 return 0;
2583}
2584
2bfbd35d 2585int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2586{
2587 struct hclge_desc desc;
2588 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2589 int ret;
2590
2591 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
e4e87715 2592 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2593 req->fun_reset_vfid = func_id;
2594
2595 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2596 if (ret)
2597 dev_err(&hdev->pdev->dev,
2598 "send function reset cmd fail, status =%d\n", ret);
2599
2600 return ret;
2601}
2602
f2f432f2 2603static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2604{
2605 struct pci_dev *pdev = hdev->pdev;
2606 u32 val;
2607
f2f432f2 2608 switch (hdev->reset_type) {
4ed340ab
L		 2609 case HNAE3_GLOBAL_RESET:
2610 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e4e87715 2611 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2612 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2613 dev_info(&pdev->dev, "Global Reset requested\n");
2614 break;
2615 case HNAE3_CORE_RESET:
2616 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e4e87715 2617 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2618 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2619 dev_info(&pdev->dev, "Core Reset requested\n");
2620 break;
2621 case HNAE3_FUNC_RESET:
2622 dev_info(&pdev->dev, "PF Reset requested\n");
cb1b9f77
SM		 2623 /* schedule again to check later */
2624 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2625 hclge_reset_task_schedule(hdev);
4ed340ab 2626 break;
6b9a97ee
HT		 2627 case HNAE3_FLR_RESET:
2628 dev_info(&pdev->dev, "FLR requested\n");
2629 /* schedule again to check later */
2630 set_bit(HNAE3_FLR_RESET, &hdev->reset_pending);
2631 hclge_reset_task_schedule(hdev);
2632 break;
4ed340ab
L		 2633 default:
2634 dev_warn(&pdev->dev,
f2f432f2 2635 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2636 break;
2637 }
2638}
2639
f2f432f2
SM		 2640static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2641 unsigned long *addr)
2642{
2643 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2644
f6162d44
SM		 2645 /* first, resolve any unknown reset type to the known type(s) */
2646 if (test_bit(HNAE3_UNKNOWN_RESET, addr)) {
2647 /* we will intentionally ignore any errors from this function
2648 * as we will end up in *some* reset request in any case
2649 */
2650 hclge_handle_hw_msix_error(hdev, addr);
2651 clear_bit(HNAE3_UNKNOWN_RESET, addr);
2652 /* We defered the clearing of the error event which caused
2653 * interrupt since it was not posssible to do that in
2654 * interrupt context (and this is the reason we introduced
2655 * new UNKNOWN reset type). Now, the errors have been
2656 * handled and cleared in hardware we can safely enable
2657 * interrupts. This is an exception to the norm.
2658 */
2659 hclge_enable_vector(&hdev->misc_vector, true);
2660 }
2661
f2f432f2 2662 /* return the highest priority reset level amongst all */
7cea834d
HT		 2663 if (test_bit(HNAE3_IMP_RESET, addr)) {
2664 rst_level = HNAE3_IMP_RESET;
2665 clear_bit(HNAE3_IMP_RESET, addr);
2666 clear_bit(HNAE3_GLOBAL_RESET, addr);
2667 clear_bit(HNAE3_CORE_RESET, addr);
2668 clear_bit(HNAE3_FUNC_RESET, addr);
2669 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
f2f432f2 2670 rst_level = HNAE3_GLOBAL_RESET;
7cea834d
HT		 2671 clear_bit(HNAE3_GLOBAL_RESET, addr);
2672 clear_bit(HNAE3_CORE_RESET, addr);
2673 clear_bit(HNAE3_FUNC_RESET, addr);
2674 } else if (test_bit(HNAE3_CORE_RESET, addr)) {
f2f432f2 2675 rst_level = HNAE3_CORE_RESET;
7cea834d
HT		 2676 clear_bit(HNAE3_CORE_RESET, addr);
2677 clear_bit(HNAE3_FUNC_RESET, addr);
2678 } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
f2f432f2 2679 rst_level = HNAE3_FUNC_RESET;
7cea834d 2680 clear_bit(HNAE3_FUNC_RESET, addr);
6b9a97ee
HT		 2681 } else if (test_bit(HNAE3_FLR_RESET, addr)) {
2682 rst_level = HNAE3_FLR_RESET;
2683 clear_bit(HNAE3_FLR_RESET, addr);
7cea834d 2684 }
f2f432f2
SM		 2685
2686 return rst_level;
2687}
2688
cd8c5c26
YL		 2689static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2690{
2691 u32 clearval = 0;
2692
2693 switch (hdev->reset_type) {
2694 case HNAE3_IMP_RESET:
2695 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2696 break;
2697 case HNAE3_GLOBAL_RESET:
2698 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2699 break;
2700 case HNAE3_CORE_RESET:
2701 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2702 break;
2703 default:
cd8c5c26
YL		 2704 break;
2705 }
2706
2707 if (!clearval)
2708 return;
2709
2710 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2711 hclge_enable_vector(&hdev->misc_vector, true);
2712}
2713
aa5c4f17
HT		 2714static int hclge_reset_prepare_down(struct hclge_dev *hdev)
2715{
2716 int ret = 0;
2717
2718 switch (hdev->reset_type) {
2719 case HNAE3_FUNC_RESET:
6b9a97ee
HT		 2720 /* fall through */
2721 case HNAE3_FLR_RESET:
aa5c4f17
HT		 2722 ret = hclge_set_all_vf_rst(hdev, true);
2723 break;
2724 default:
2725 break;
2726 }
2727
2728 return ret;
2729}
2730
35d93a30
HT		 2731static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
2732{
6dd22bbc 2733 u32 reg_val;
35d93a30
HT		 2734 int ret = 0;
2735
2736 switch (hdev->reset_type) {
2737 case HNAE3_FUNC_RESET:
aa5c4f17
HT		 2738 /* There is no mechanism for PF to know if VF has stopped IO
2739 * for now, just wait 100 ms for VF to stop IO
2740 */
2741 msleep(100);
35d93a30
HT		 2742 ret = hclge_func_reset_cmd(hdev, 0);
2743 if (ret) {
2744 dev_err(&hdev->pdev->dev,
141b95d5 2745 "asserting function reset fail %d!\n", ret);
35d93a30
HT		 2746 return ret;
2747 }
2748
2749 /* After performaning pf reset, it is not necessary to do the
2750 * mailbox handling or send any command to firmware, because
2751 * any mailbox handling or command to firmware is only valid
2752 * after hclge_cmd_init is called.
2753 */
2754 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2755 break;
6b9a97ee
HT		 2756 case HNAE3_FLR_RESET:
2757 /* There is no mechanism for PF to know if VF has stopped IO
2758 * for now, just wait 100 ms for VF to stop IO
2759 */
2760 msleep(100);
2761 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2762 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
2763 break;
6dd22bbc
HT		 2764 case HNAE3_IMP_RESET:
2765 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
2766 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
2767 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
2768 break;
35d93a30
HT		 2769 default:
2770 break;
2771 }
2772
2773 dev_info(&hdev->pdev->dev, "prepare wait ok\n");
2774
2775 return ret;
2776}
2777
65e41e7e
HT		 2778static bool hclge_reset_err_handle(struct hclge_dev *hdev, bool is_timeout)
2779{
2780#define MAX_RESET_FAIL_CNT 5
2781#define RESET_UPGRADE_DELAY_SEC 10
2782
2783 if (hdev->reset_pending) {
2784 dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
2785 hdev->reset_pending);
2786 return true;
2787 } else if ((hdev->reset_type != HNAE3_IMP_RESET) &&
2788 (hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) &
2789 BIT(HCLGE_IMP_RESET_BIT))) {
2790 dev_info(&hdev->pdev->dev,
2791 "reset failed because IMP Reset is pending\n");
2792 hclge_clear_reset_cause(hdev);
2793 return false;
2794 } else if (hdev->reset_fail_cnt < MAX_RESET_FAIL_CNT) {
2795 hdev->reset_fail_cnt++;
2796 if (is_timeout) {
2797 set_bit(hdev->reset_type, &hdev->reset_pending);
2798 dev_info(&hdev->pdev->dev,
2799 "re-schedule to wait for hw reset done\n");
2800 return true;
2801 }
2802
2803 dev_info(&hdev->pdev->dev, "Upgrade reset level\n");
2804 hclge_clear_reset_cause(hdev);
2805 mod_timer(&hdev->reset_timer,
2806 jiffies + RESET_UPGRADE_DELAY_SEC * HZ);
2807
2808 return false;
2809 }
2810
2811 hclge_clear_reset_cause(hdev);
2812 dev_err(&hdev->pdev->dev, "Reset fail!\n");
2813 return false;
2814}
2815
aa5c4f17
HT		 2816static int hclge_reset_prepare_up(struct hclge_dev *hdev)
2817{
2818 int ret = 0;
2819
2820 switch (hdev->reset_type) {
2821 case HNAE3_FUNC_RESET:
6b9a97ee
HT		 2822 /* fall through */
2823 case HNAE3_FLR_RESET:
aa5c4f17
HT		 2824 ret = hclge_set_all_vf_rst(hdev, false);
2825 break;
2826 default:
2827 break;
2828 }
2829
2830 return ret;
2831}
2832
f2f432f2
SM		 2833static void hclge_reset(struct hclge_dev *hdev)
2834{
6871af29 2835 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
65e41e7e
HT		 2836 bool is_timeout = false;
2837 int ret;
9de0b86f 2838
6871af29
JS		 2839 /* Initialize ae_dev reset status as well, in case enet layer wants to
2840 * know if device is undergoing reset
2841 */
2842 ae_dev->reset_type = hdev->reset_type;
4d60291b 2843 hdev->reset_count++;
f2f432f2 2844 /* perform reset of the stack & ae device for a client */
65e41e7e
HT		 2845 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
2846 if (ret)
2847 goto err_reset;
2848
aa5c4f17
HT		 2849 ret = hclge_reset_prepare_down(hdev);
2850 if (ret)
2851 goto err_reset;
2852
6d4fab39 2853 rtnl_lock();
65e41e7e
HT		 2854 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2855 if (ret)
2856 goto err_reset_lock;
f2f432f2 2857
65e41e7e 2858 rtnl_unlock();
35d93a30 2859
65e41e7e
HT		 2860 ret = hclge_reset_prepare_wait(hdev);
2861 if (ret)
2862 goto err_reset;
cd8c5c26 2863
65e41e7e
HT		 2864 if (hclge_reset_wait(hdev)) {
2865 is_timeout = true;
2866 goto err_reset;
f2f432f2
SM		 2867 }
2868
65e41e7e
HT		 2869 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
2870 if (ret)
2871 goto err_reset;
2872
2873 rtnl_lock();
2874 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2875 if (ret)
2876 goto err_reset_lock;
2877
2878 ret = hclge_reset_ae_dev(hdev->ae_dev);
2879 if (ret)
2880 goto err_reset_lock;
2881
2882 ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2883 if (ret)
2884 goto err_reset_lock;
2885
2886 hclge_clear_reset_cause(hdev);
2887
aa5c4f17
HT		 2888 ret = hclge_reset_prepare_up(hdev);
2889 if (ret)
2890 goto err_reset_lock;
2891
65e41e7e
HT		 2892 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2893 if (ret)
2894 goto err_reset_lock;
2895
6d4fab39 2896 rtnl_unlock();
f403a84f 2897
65e41e7e
HT		 2898 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
2899 if (ret)
2900 goto err_reset;
2901
2902 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
2903 if (ret)
2904 goto err_reset;
2905
b644a8d4
HT		 2906 hdev->last_reset_time = jiffies;
2907 hdev->reset_fail_cnt = 0;
2908 ae_dev->reset_type = HNAE3_NONE_RESET;
2909
65e41e7e
HT		 2910 return;
2911
2912err_reset_lock:
2913 rtnl_unlock();
2914err_reset:
2915 if (hclge_reset_err_handle(hdev, is_timeout))
2916 hclge_reset_task_schedule(hdev);
f2f432f2
SM		 2917}
2918
6ae4e733
SJ		 2919static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
2920{
2921 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2922 struct hclge_dev *hdev = ae_dev->priv;
2923
2924 /* We might end up getting called broadly because of 2 below cases:
2925 * 1. Recoverable error was conveyed through APEI and only way to bring
2926 * normalcy is to reset.
2927 * 2. A new reset request from the stack due to timeout
2928 *
2929 * For the first case,error event might not have ae handle available.
2930 * check if this is a new reset request and we are not here just because
6d4c3981
SM		 2931 * last reset attempt did not succeed and watchdog hit us again. We will
2932 * know this if last reset request did not occur very recently (watchdog
2933 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2934 * In case of new request we reset the "reset level" to PF reset.
9de0b86f
HT		 2935 * And if it is a repeat reset request of the most recent one then we
2936 * want to make sure we throttle the reset request. Therefore, we will
2937 * not allow it again before 3*HZ times.
6d4c3981 2938 */
6ae4e733
SJ		 2939 if (!handle)
2940 handle = &hdev->vport[0].nic;
2941
0742ed7c 2942 if (time_before(jiffies, (hdev->last_reset_time + 3 * HZ)))
9de0b86f 2943 return;
720bd583 2944 else if (hdev->default_reset_request)
0742ed7c 2945 hdev->reset_level =
720bd583
HT		 2946 hclge_get_reset_level(hdev,
2947 &hdev->default_reset_request);
0742ed7c
HT		 2948 else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ)))
2949 hdev->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2950
6d4c3981 2951 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
0742ed7c 2952 hdev->reset_level);
6d4c3981
SM		 2953
2954 /* request reset & schedule reset task */
0742ed7c 2955 set_bit(hdev->reset_level, &hdev->reset_request);
6d4c3981
SM		 2956 hclge_reset_task_schedule(hdev);
2957
0742ed7c
HT		 2958 if (hdev->reset_level < HNAE3_GLOBAL_RESET)
2959 hdev->reset_level++;
4ed340ab
L		 2960}
2961
720bd583
HT		 2962static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2963 enum hnae3_reset_type rst_type)
2964{
2965 struct hclge_dev *hdev = ae_dev->priv;
2966
2967 set_bit(rst_type, &hdev->default_reset_request);
2968}
2969
65e41e7e
HT		 2970static void hclge_reset_timer(struct timer_list *t)
2971{
2972 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
2973
2974 dev_info(&hdev->pdev->dev,
2975 "triggering global reset in reset timer\n");
2976 set_bit(HNAE3_GLOBAL_RESET, &hdev->default_reset_request);
2977 hclge_reset_event(hdev->pdev, NULL);
2978}
2979
4ed340ab
L		 2980static void hclge_reset_subtask(struct hclge_dev *hdev)
2981{
f2f432f2
SM		 2982 /* check if there is any ongoing reset in the hardware. This status can
2983 * be checked from reset_pending. If there is then, we need to wait for
2984 * hardware to complete reset.
2985 * a. If we are able to figure out in reasonable time that hardware
2986 * has fully resetted then, we can proceed with driver, client
2987 * reset.
2988 * b. else, we can come back later to check this status so re-sched
2989 * now.
2990 */
0742ed7c 2991 hdev->last_reset_time = jiffies;
f2f432f2
SM		 2992 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2993 if (hdev->reset_type != HNAE3_NONE_RESET)
2994 hclge_reset(hdev);
4ed340ab 2995
f2f432f2
SM		 2996 /* check if we got any *new* reset requests to be honored */
2997 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2998 if (hdev->reset_type != HNAE3_NONE_RESET)
2999 hclge_do_reset(hdev);
4ed340ab 3000
4ed340ab
L		 3001 hdev->reset_type = HNAE3_NONE_RESET;
3002}
3003
cb1b9f77 3004static void hclge_reset_service_task(struct work_struct *work)
466b0c00 3005{
cb1b9f77
SM		 3006 struct hclge_dev *hdev =
3007 container_of(work, struct hclge_dev, rst_service_task);
3008
3009 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3010 return;
3011
3012 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
3013
4ed340ab 3014 hclge_reset_subtask(hdev);
cb1b9f77
SM		 3015
3016 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 3017}
3018
c1a81619
SM		 3019static void hclge_mailbox_service_task(struct work_struct *work)
3020{
3021 struct hclge_dev *hdev =
3022 container_of(work, struct hclge_dev, mbx_service_task);
3023
3024 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
3025 return;
3026
3027 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
3028
3029 hclge_mbx_handler(hdev);
3030
3031 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
3032}
3033
a6d818e3
YL		 3034static void hclge_update_vport_alive(struct hclge_dev *hdev)
3035{
3036 int i;
3037
3038 /* start from vport 1 for PF is always alive */
3039 for (i = 1; i < hdev->num_alloc_vport; i++) {
3040 struct hclge_vport *vport = &hdev->vport[i];
3041
3042 if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ))
3043 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
818f1675
YL		 3044
3045 /* If vf is not alive, set to default value */
3046 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
3047 vport->mps = HCLGE_MAC_DEFAULT_FRAME;
a6d818e3
YL		 3048 }
3049}
3050
46a3df9f
S		 3051static void hclge_service_task(struct work_struct *work)
3052{
3053 struct hclge_dev *hdev =
3054 container_of(work, struct hclge_dev, service_task);
3055
c5f65480
JS		 3056 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
3057 hclge_update_stats_for_all(hdev);
3058 hdev->hw_stats.stats_timer = 0;
3059 }
3060
46a3df9f
S		 3061 hclge_update_speed_duplex(hdev);
3062 hclge_update_link_status(hdev);
a6d818e3 3063 hclge_update_vport_alive(hdev);
46a3df9f
S		 3064 hclge_service_complete(hdev);
3065}
3066
46a3df9f
S		 3067struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
3068{
3069 /* VF handle has no client */
3070 if (!handle->client)
3071 return container_of(handle, struct hclge_vport, nic);
3072 else if (handle->client->type == HNAE3_CLIENT_ROCE)
3073 return container_of(handle, struct hclge_vport, roce);
3074 else
3075 return container_of(handle, struct hclge_vport, nic);
3076}
3077
3078static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
3079 struct hnae3_vector_info *vector_info)
3080{
3081 struct hclge_vport *vport = hclge_get_vport(handle);
3082 struct hnae3_vector_info *vector = vector_info;
3083 struct hclge_dev *hdev = vport->back;
3084 int alloc = 0;
3085 int i, j;
3086
3087 vector_num = min(hdev->num_msi_left, vector_num);
3088
3089 for (j = 0; j < vector_num; j++) {
3090 for (i = 1; i < hdev->num_msi; i++) {
3091 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
3092 vector->vector = pci_irq_vector(hdev->pdev, i);
3093 vector->io_addr = hdev->hw.io_base +
3094 HCLGE_VECTOR_REG_BASE +
3095 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
3096 vport->vport_id *
3097 HCLGE_VECTOR_VF_OFFSET;
3098 hdev->vector_status[i] = vport->vport_id;
887c3820 3099 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 3100
3101 vector++;
3102 alloc++;
3103
3104 break;
3105 }
3106 }
3107 }
3108 hdev->num_msi_left -= alloc;
3109 hdev->num_msi_used += alloc;
3110
3111 return alloc;
3112}
3113
3114static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
3115{
3116 int i;
3117
887c3820
SM		 3118 for (i = 0; i < hdev->num_msi; i++)
3119 if (vector == hdev->vector_irq[i])
3120 return i;
3121
46a3df9f
S		 3122 return -EINVAL;
3123}
3124
0d3e6631
YL		 3125static int hclge_put_vector(struct hnae3_handle *handle, int vector)
3126{
3127 struct hclge_vport *vport = hclge_get_vport(handle);
3128 struct hclge_dev *hdev = vport->back;
3129 int vector_id;
3130
3131 vector_id = hclge_get_vector_index(hdev, vector);
3132 if (vector_id < 0) {
3133 dev_err(&hdev->pdev->dev,
3134 "Get vector index fail. vector_id =%d\n", vector_id);
3135 return vector_id;
3136 }
3137
3138 hclge_free_vector(hdev, vector_id);
3139
3140 return 0;
3141}
3142
46a3df9f
S		 3143static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
3144{
3145 return HCLGE_RSS_KEY_SIZE;
3146}
3147
3148static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3149{
3150 return HCLGE_RSS_IND_TBL_SIZE;
3151}
3152
46a3df9f
S		 3153static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3154 const u8 hfunc, const u8 *key)
3155{
d44f9b63 3156 struct hclge_rss_config_cmd *req;
46a3df9f
S		 3157 struct hclge_desc desc;
3158 int key_offset;
3159 int key_size;
3160 int ret;
3161
d44f9b63 3162 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 3163
3164 for (key_offset = 0; key_offset < 3; key_offset++) {
3165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3166 false);
3167
3168 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3169 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3170
3171 if (key_offset == 2)
3172 key_size =
3173 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3174 else
3175 key_size = HCLGE_RSS_HASH_KEY_NUM;
3176
3177 memcpy(req->hash_key,
3178 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3179
3180 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3181 if (ret) {
3182 dev_err(&hdev->pdev->dev,
3183 "Configure RSS config fail, status = %d\n",
3184 ret);
3185 return ret;
3186 }
3187 }
3188 return 0;
3189}
3190
89523cfa 3191static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3192{
d44f9b63 3193 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3194 struct hclge_desc desc;
3195 int i, j;
3196 int ret;
3197
d44f9b63 3198 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3199
3200 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3201 hclge_cmd_setup_basic_desc
3202 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3203
a90bb9a5
YL		 3204 req->start_table_index =
3205 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3206 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3207
3208 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3209 req->rss_result[j] =
3210 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3211
3212 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3213 if (ret) {
3214 dev_err(&hdev->pdev->dev,
3215 "Configure rss indir table fail,status = %d\n",
3216 ret);
3217 return ret;
3218 }
3219 }
3220 return 0;
3221}
3222
3223static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3224 u16 *tc_size, u16 *tc_offset)
3225{
d44f9b63 3226 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3227 struct hclge_desc desc;
3228 int ret;
3229 int i;
3230
3231 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3232 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3233
3234 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3235 u16 mode = 0;
3236
e4e87715
PL		 3237 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3238 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3239 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3240 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3241 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3242
3243 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3244 }
3245
3246 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3247 if (ret)
46a3df9f
S		 3248 dev_err(&hdev->pdev->dev,
3249 "Configure rss tc mode fail, status = %d\n", ret);
46a3df9f 3250
3f639907 3251 return ret;
46a3df9f
S		 3252}
3253
232fc64b
PL		 3254static void hclge_get_rss_type(struct hclge_vport *vport)
3255{
3256 if (vport->rss_tuple_sets.ipv4_tcp_en ||
3257 vport->rss_tuple_sets.ipv4_udp_en ||
3258 vport->rss_tuple_sets.ipv4_sctp_en ||
3259 vport->rss_tuple_sets.ipv6_tcp_en ||
3260 vport->rss_tuple_sets.ipv6_udp_en ||
3261 vport->rss_tuple_sets.ipv6_sctp_en)
3262 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4;
3263 else if (vport->rss_tuple_sets.ipv4_fragment_en ||
3264 vport->rss_tuple_sets.ipv6_fragment_en)
3265 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3;
3266 else
3267 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE;
3268}
3269
46a3df9f
S		 3270static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3271{
d44f9b63 3272 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3273 struct hclge_desc desc;
3274 int ret;
3275
3276 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3277
d44f9b63 3278 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429
YL		 3279
3280 /* Get the tuple cfg from pf */
3281 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3282 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3283 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3284 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3285 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3286 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3287 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3288 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
232fc64b 3289 hclge_get_rss_type(&hdev->vport[0]);
46a3df9f 3290 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3291 if (ret)
46a3df9f
S		 3292 dev_err(&hdev->pdev->dev,
3293 "Configure rss input fail, status = %d\n", ret);
3f639907 3294 return ret;
46a3df9f
S		 3295}
3296
3297static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3298 u8 *key, u8 *hfunc)
3299{
3300 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3301 int i;
3302
3303 /* Get hash algorithm */
775501a1
JS		 3304 if (hfunc) {
3305 switch (vport->rss_algo) {
3306 case HCLGE_RSS_HASH_ALGO_TOEPLITZ:
3307 *hfunc = ETH_RSS_HASH_TOP;
3308 break;
3309 case HCLGE_RSS_HASH_ALGO_SIMPLE:
3310 *hfunc = ETH_RSS_HASH_XOR;
3311 break;
3312 default:
3313 *hfunc = ETH_RSS_HASH_UNKNOWN;
3314 break;
3315 }
3316 }
46a3df9f
S		 3317
3318 /* Get the RSS Key required by the user */
3319 if (key)
3320 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3321
3322 /* Get indirect table */
3323 if (indir)
3324 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3325 indir[i] = vport->rss_indirection_tbl[i];
3326
3327 return 0;
3328}
3329
3330static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3331 const u8 *key, const u8 hfunc)
3332{
3333 struct hclge_vport *vport = hclge_get_vport(handle);
3334 struct hclge_dev *hdev = vport->back;
3335 u8 hash_algo;
3336 int ret, i;
3337
3338 /* Set the RSS Hash Key if specififed by the user */
3339 if (key) {
775501a1
JS		 3340 switch (hfunc) {
3341 case ETH_RSS_HASH_TOP:
46a3df9f 3342 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
775501a1
JS		 3343 break;
3344 case ETH_RSS_HASH_XOR:
3345 hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
3346 break;
3347 case ETH_RSS_HASH_NO_CHANGE:
3348 hash_algo = vport->rss_algo;
3349 break;
3350 default:
46a3df9f 3351 return -EINVAL;
775501a1
JS		 3352 }
3353
46a3df9f
S		 3354 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3355 if (ret)
3356 return ret;
89523cfa
YL		 3357
3358 /* Update the shadow RSS key with user specified qids */
3359 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3360 vport->rss_algo = hash_algo;
46a3df9f
S		 3361 }
3362
3363 /* Update the shadow RSS table with user specified qids */
3364 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3365 vport->rss_indirection_tbl[i] = indir[i];
3366
3367 /* Update the hardware */
89523cfa 3368 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3369}
3370
f7db940a
L		 3371static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3372{
3373 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3374
3375 if (nfc->data & RXH_L4_B_2_3)
3376 hash_sets |= HCLGE_D_PORT_BIT;
3377 else
3378 hash_sets &= ~HCLGE_D_PORT_BIT;
3379
3380 if (nfc->data & RXH_IP_SRC)
3381 hash_sets |= HCLGE_S_IP_BIT;
3382 else
3383 hash_sets &= ~HCLGE_S_IP_BIT;
3384
3385 if (nfc->data & RXH_IP_DST)
3386 hash_sets |= HCLGE_D_IP_BIT;
3387 else
3388 hash_sets &= ~HCLGE_D_IP_BIT;
3389
3390 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3391 hash_sets |= HCLGE_V_TAG_BIT;
3392
3393 return hash_sets;
3394}
3395
3396static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3397 struct ethtool_rxnfc *nfc)
3398{
3399 struct hclge_vport *vport = hclge_get_vport(handle);
3400 struct hclge_dev *hdev = vport->back;
3401 struct hclge_rss_input_tuple_cmd *req;
3402 struct hclge_desc desc;
3403 u8 tuple_sets;
3404 int ret;
3405
3406 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3407 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3408 return -EINVAL;
3409
3410 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429 3411 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 3412
6f2af429
YL		 3413 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3414 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3415 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3416 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3417 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3418 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3419 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3420 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 3421
3422 tuple_sets = hclge_get_rss_hash_bits(nfc);
3423 switch (nfc->flow_type) {
3424 case TCP_V4_FLOW:
3425 req->ipv4_tcp_en = tuple_sets;
3426 break;
3427 case TCP_V6_FLOW:
3428 req->ipv6_tcp_en = tuple_sets;
3429 break;
3430 case UDP_V4_FLOW:
3431 req->ipv4_udp_en = tuple_sets;
3432 break;
3433 case UDP_V6_FLOW:
3434 req->ipv6_udp_en = tuple_sets;
3435 break;
3436 case SCTP_V4_FLOW:
3437 req->ipv4_sctp_en = tuple_sets;
3438 break;
3439 case SCTP_V6_FLOW:
3440 if ((nfc->data & RXH_L4_B_0_1) ||
3441 (nfc->data & RXH_L4_B_2_3))
3442 return -EINVAL;
3443
3444 req->ipv6_sctp_en = tuple_sets;
3445 break;
3446 case IPV4_FLOW:
3447 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3448 break;
3449 case IPV6_FLOW:
3450 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3451 break;
3452 default:
3453 return -EINVAL;
3454 }
3455
3456 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6f2af429 3457 if (ret) {
f7db940a
L		 3458 dev_err(&hdev->pdev->dev,
3459 "Set rss tuple fail, status = %d\n", ret);
6f2af429
YL		 3460 return ret;
3461 }
f7db940a 3462
6f2af429
YL		 3463 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3464 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3465 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3466 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3467 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3468 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3469 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3470 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
232fc64b 3471 hclge_get_rss_type(vport);
6f2af429 3472 return 0;
f7db940a
L		 3473}
3474
07d29954
L		 3475static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3476 struct ethtool_rxnfc *nfc)
3477{
3478 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3479 u8 tuple_sets;
07d29954
L		 3480
3481 nfc->data = 0;
3482
07d29954
L		 3483 switch (nfc->flow_type) {
3484 case TCP_V4_FLOW:
6f2af429 3485 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3486 break;
3487 case UDP_V4_FLOW:
6f2af429 3488 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3489 break;
3490 case TCP_V6_FLOW:
6f2af429 3491 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3492 break;
3493 case UDP_V6_FLOW:
6f2af429 3494 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3495 break;
3496 case SCTP_V4_FLOW:
6f2af429 3497 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3498 break;
3499 case SCTP_V6_FLOW:
6f2af429 3500 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3501 break;
3502 case IPV4_FLOW:
3503 case IPV6_FLOW:
3504 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3505 break;
3506 default:
3507 return -EINVAL;
3508 }
3509
3510 if (!tuple_sets)
3511 return 0;
3512
3513 if (tuple_sets & HCLGE_D_PORT_BIT)
3514 nfc->data |= RXH_L4_B_2_3;
3515 if (tuple_sets & HCLGE_S_PORT_BIT)
3516 nfc->data |= RXH_L4_B_0_1;
3517 if (tuple_sets & HCLGE_D_IP_BIT)
3518 nfc->data |= RXH_IP_DST;
3519 if (tuple_sets & HCLGE_S_IP_BIT)
3520 nfc->data |= RXH_IP_SRC;
3521
3522 return 0;
3523}
3524
46a3df9f
S		 3525static int hclge_get_tc_size(struct hnae3_handle *handle)
3526{
3527 struct hclge_vport *vport = hclge_get_vport(handle);
3528 struct hclge_dev *hdev = vport->back;
3529
3530 return hdev->rss_size_max;
3531}
3532
77f255c1 3533int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3534{
46a3df9f 3535 struct hclge_vport *vport = hdev->vport;
268f5dfa
YL		 3536 u8 *rss_indir = vport[0].rss_indirection_tbl;
3537 u16 rss_size = vport[0].alloc_rss_size;
3538 u8 *key = vport[0].rss_hash_key;
3539 u8 hfunc = vport[0].rss_algo;
46a3df9f 3540 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3541 u16 tc_valid[HCLGE_MAX_TC_NUM];
3542 u16 tc_size[HCLGE_MAX_TC_NUM];
268f5dfa
YL		 3543 u16 roundup_size;
3544 int i, ret;
68ece54e 3545
46a3df9f
S		 3546 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3547 if (ret)
268f5dfa 3548 return ret;
46a3df9f 3549
46a3df9f
S		 3550 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3551 if (ret)
268f5dfa 3552 return ret;
46a3df9f
S		 3553
3554 ret = hclge_set_rss_input_tuple(hdev);
3555 if (ret)
268f5dfa 3556 return ret;
46a3df9f 3557
68ece54e
YL		 3558 /* Each TC have the same queue size, and tc_size set to hardware is
3559 * the log2 of roundup power of two of rss_size, the acutal queue
3560 * size is limited by indirection table.
3561 */
3562 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3563 dev_err(&hdev->pdev->dev,
3564 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3565 rss_size);
268f5dfa 3566 return -EINVAL;
68ece54e
YL		 3567 }
3568
3569 roundup_size = roundup_pow_of_two(rss_size);
3570 roundup_size = ilog2(roundup_size);
3571
46a3df9f 3572 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3573 tc_valid[i] = 0;
46a3df9f 3574
68ece54e
YL		 3575 if (!(hdev->hw_tc_map & BIT(i)))
3576 continue;
3577
3578 tc_valid[i] = 1;
3579 tc_size[i] = roundup_size;
3580 tc_offset[i] = rss_size * i;
46a3df9f 3581 }
68ece54e 3582
268f5dfa
YL		 3583 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3584}
46a3df9f 3585
268f5dfa
YL		 3586void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3587{
3588 struct hclge_vport *vport = hdev->vport;
3589 int i, j;
46a3df9f 3590
268f5dfa
YL		 3591 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3592 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3593 vport[j].rss_indirection_tbl[i] =
3594 i % vport[j].alloc_rss_size;
3595 }
3596}
3597
3598static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3599{
3600 struct hclge_vport *vport = hdev->vport;
3601 int i;
3602
268f5dfa
YL		 3603 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3604 vport[i].rss_tuple_sets.ipv4_tcp_en =
3605 HCLGE_RSS_INPUT_TUPLE_OTHER;
3606 vport[i].rss_tuple_sets.ipv4_udp_en =
3607 HCLGE_RSS_INPUT_TUPLE_OTHER;
3608 vport[i].rss_tuple_sets.ipv4_sctp_en =
3609 HCLGE_RSS_INPUT_TUPLE_SCTP;
3610 vport[i].rss_tuple_sets.ipv4_fragment_en =
3611 HCLGE_RSS_INPUT_TUPLE_OTHER;
3612 vport[i].rss_tuple_sets.ipv6_tcp_en =
3613 HCLGE_RSS_INPUT_TUPLE_OTHER;
3614 vport[i].rss_tuple_sets.ipv6_udp_en =
3615 HCLGE_RSS_INPUT_TUPLE_OTHER;
3616 vport[i].rss_tuple_sets.ipv6_sctp_en =
3617 HCLGE_RSS_INPUT_TUPLE_SCTP;
3618 vport[i].rss_tuple_sets.ipv6_fragment_en =
3619 HCLGE_RSS_INPUT_TUPLE_OTHER;
3620
3621 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
ea739c90
FL		 3622
3623 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
268f5dfa
YL		 3624 }
3625
3626 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3627}
3628
84e095d6
SM		 3629int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3630 int vector_id, bool en,
3631 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3632{
3633 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3634 struct hnae3_ring_chain_node *node;
3635 struct hclge_desc desc;
84e095d6
SM		 3636 struct hclge_ctrl_vector_chain_cmd *req
3637 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3638 enum hclge_cmd_status status;
3639 enum hclge_opcode_type op;
3640 u16 tqp_type_and_id;
46a3df9f
S		 3641 int i;
3642
84e095d6
SM		 3643 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3644 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3645 req->int_vector_id = vector_id;
3646
3647 i = 0;
3648 for (node = ring_chain; node; node = node->next) {
84e095d6 3649 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
e4e87715
PL		 3650 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3651 HCLGE_INT_TYPE_S,
3652 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3653 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3654 HCLGE_TQP_ID_S, node->tqp_index);
3655 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3656 HCLGE_INT_GL_IDX_S,
3657 hnae3_get_field(node->int_gl_idx,
3658 HNAE3_RING_GL_IDX_M,
3659 HNAE3_RING_GL_IDX_S));
84e095d6 3660 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3661 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3662 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
84e095d6 3663 req->vfid = vport->vport_id;
46a3df9f 3664
84e095d6
SM		 3665 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3666 if (status) {
46a3df9f
S		 3667 dev_err(&hdev->pdev->dev,
3668 "Map TQP fail, status is %d.\n",
84e095d6
SM		 3669 status);
3670 return -EIO;
46a3df9f
S		 3671 }
3672 i = 0;
3673
3674 hclge_cmd_setup_basic_desc(&desc,
84e095d6 3675 op,
46a3df9f
S		 3676 false);
3677 req->int_vector_id = vector_id;
3678 }
3679 }
3680
3681 if (i > 0) {
3682 req->int_cause_num = i;
84e095d6
SM		 3683 req->vfid = vport->vport_id;
3684 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3685 if (status) {
46a3df9f 3686 dev_err(&hdev->pdev->dev,
84e095d6
SM		 3687 "Map TQP fail, status is %d.\n", status);
3688 return -EIO;
46a3df9f
S		 3689 }
3690 }
3691
3692 return 0;
3693}
3694
84e095d6
SM		 3695static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3696 int vector,
3697 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3698{
3699 struct hclge_vport *vport = hclge_get_vport(handle);
3700 struct hclge_dev *hdev = vport->back;
3701 int vector_id;
3702
3703 vector_id = hclge_get_vector_index(hdev, vector);
3704 if (vector_id < 0) {
3705 dev_err(&hdev->pdev->dev,
84e095d6 3706 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3707 return vector_id;
3708 }
3709
84e095d6 3710 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3711}
3712
84e095d6
SM		 3713static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3714 int vector,
3715 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3716{
3717 struct hclge_vport *vport = hclge_get_vport(handle);
3718 struct hclge_dev *hdev = vport->back;
84e095d6 3719 int vector_id, ret;
46a3df9f 3720
b50ae26c
PL		 3721 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3722 return 0;
3723
46a3df9f
S		 3724 vector_id = hclge_get_vector_index(hdev, vector);
3725 if (vector_id < 0) {
3726 dev_err(&handle->pdev->dev,
3727 "Get vector index fail. ret =%d\n", vector_id);
3728 return vector_id;
3729 }
3730
84e095d6 3731 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
0d3e6631 3732 if (ret)
84e095d6
SM		 3733 dev_err(&handle->pdev->dev,
3734 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3735 vector_id,
3736 ret);
46a3df9f 3737
0d3e6631 3738 return ret;
46a3df9f
S		 3739}
3740
3741int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3742 struct hclge_promisc_param *param)
3743{
d44f9b63 3744 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3745 struct hclge_desc desc;
3746 int ret;
3747
3748 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3749
d44f9b63 3750 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3751 req->vf_id = param->vf_id;
96c0e861
PL		 3752
3753 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3754 * pdev revision(0x20), new revision support them. The
3755 * value of this two fields will not return error when driver
3756 * send command to fireware in revision(0x20).
3757 */
3758 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3759 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3760
3761 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3762 if (ret)
46a3df9f
S		 3763 dev_err(&hdev->pdev->dev,
3764 "Set promisc mode fail, status is %d.\n", ret);
3f639907
JS		 3765
3766 return ret;
46a3df9f
S		 3767}
3768
3769void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3770 bool en_mc, bool en_bc, int vport_id)
3771{
3772 if (!param)
3773 return;
3774
3775 memset(param, 0, sizeof(struct hclge_promisc_param));
3776 if (en_uc)
3777 param->enable = HCLGE_PROMISC_EN_UC;
3778 if (en_mc)
3779 param->enable |= HCLGE_PROMISC_EN_MC;
3780 if (en_bc)
3781 param->enable |= HCLGE_PROMISC_EN_BC;
3782 param->vf_id = vport_id;
3783}
3784
7fa6be4f
HT		 3785static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3786 bool en_mc_pmc)
46a3df9f
S		 3787{
3788 struct hclge_vport *vport = hclge_get_vport(handle);
3789 struct hclge_dev *hdev = vport->back;
3790 struct hclge_promisc_param param;
3791
3b75c3df
PL		 3792 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3793 vport->vport_id);
7fa6be4f 3794 return hclge_cmd_set_promisc_mode(hdev, &param);
46a3df9f
S		 3795}
3796
d695964d
JS		 3797static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
3798{
3799 struct hclge_get_fd_mode_cmd *req;
3800 struct hclge_desc desc;
3801 int ret;
3802
3803 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
3804
3805 req = (struct hclge_get_fd_mode_cmd *)desc.data;
3806
3807 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3808 if (ret) {
3809 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
3810 return ret;
3811 }
3812
3813 *fd_mode = req->mode;
3814
3815 return ret;
3816}
3817
3818static int hclge_get_fd_allocation(struct hclge_dev *hdev,
3819 u32 *stage1_entry_num,
3820 u32 *stage2_entry_num,
3821 u16 *stage1_counter_num,
3822 u16 *stage2_counter_num)
3823{
3824 struct hclge_get_fd_allocation_cmd *req;
3825 struct hclge_desc desc;
3826 int ret;
3827
3828 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
3829
3830 req = (struct hclge_get_fd_allocation_cmd *)desc.data;
3831
3832 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3833 if (ret) {
3834 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
3835 ret);
3836 return ret;
3837 }
3838
3839 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
3840 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
3841 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
3842 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
3843
3844 return ret;
3845}
3846
3847static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num)
3848{
3849 struct hclge_set_fd_key_config_cmd *req;
3850 struct hclge_fd_key_cfg *stage;
3851 struct hclge_desc desc;
3852 int ret;
3853
3854 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
3855
3856 req = (struct hclge_set_fd_key_config_cmd *)desc.data;
3857 stage = &hdev->fd_cfg.key_cfg[stage_num];
3858 req->stage = stage_num;
3859 req->key_select = stage->key_sel;
3860 req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
3861 req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
3862 req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
3863 req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
3864 req->tuple_mask = cpu_to_le32(~stage->tuple_active);
3865 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
3866
3867 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3868 if (ret)
3869 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
3870
3871 return ret;
3872}
3873
3874static int hclge_init_fd_config(struct hclge_dev *hdev)
3875{
3876#define LOW_2_WORDS 0x03
3877 struct hclge_fd_key_cfg *key_cfg;
3878 int ret;
3879
3880 if (!hnae3_dev_fd_supported(hdev))
3881 return 0;
3882
3883 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
3884 if (ret)
3885 return ret;
3886
3887 switch (hdev->fd_cfg.fd_mode) {
3888 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
3889 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
3890 break;
3891 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
3892 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
3893 break;
3894 default:
3895 dev_err(&hdev->pdev->dev,
3896 "Unsupported flow director mode %d\n",
3897 hdev->fd_cfg.fd_mode);
3898 return -EOPNOTSUPP;
3899 }
3900
3901 hdev->fd_cfg.fd_en = true;
3902 hdev->fd_cfg.proto_support =
3903 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW |
3904 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW;
3905 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
3906 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE,
3907 key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
3908 key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
3909 key_cfg->outer_sipv6_word_en = 0;
3910 key_cfg->outer_dipv6_word_en = 0;
3911
3912 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
3913 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
3914 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3915 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3916
3917 /* If use max 400bit key, we can support tuples for ether type */
3918 if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) {
3919 hdev->fd_cfg.proto_support |= ETHER_FLOW;
3920 key_cfg->tuple_active |=
3921 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
3922 }
3923
3924 /* roce_type is used to filter roce frames
3925 * dst_vport is used to specify the rule
3926 */
3927 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
3928
3929 ret = hclge_get_fd_allocation(hdev,
3930 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
3931 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
3932 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
3933 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
3934 if (ret)
3935 return ret;
3936
3937 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
3938}
3939
11732868
JS		 3940static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
3941 int loc, u8 *key, bool is_add)
3942{
3943 struct hclge_fd_tcam_config_1_cmd *req1;
3944 struct hclge_fd_tcam_config_2_cmd *req2;
3945 struct hclge_fd_tcam_config_3_cmd *req3;
3946 struct hclge_desc desc[3];
3947 int ret;
3948
3949 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
3950 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3951 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
3952 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3953 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
3954
3955 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
3956 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
3957 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
3958
3959 req1->stage = stage;
3960 req1->xy_sel = sel_x ? 1 : 0;
3961 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
3962 req1->index = cpu_to_le32(loc);
3963 req1->entry_vld = sel_x ? is_add : 0;
3964
3965 if (key) {
3966 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
3967 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
3968 sizeof(req2->tcam_data));
3969 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
3970 sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
3971 }
3972
3973 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3974 if (ret)
3975 dev_err(&hdev->pdev->dev,
3976 "config tcam key fail, ret=%d\n",
3977 ret);
3978
3979 return ret;
3980}
3981
3982static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
3983 struct hclge_fd_ad_data *action)
3984{
3985 struct hclge_fd_ad_config_cmd *req;
3986 struct hclge_desc desc;
3987 u64 ad_data = 0;
3988 int ret;
3989
3990 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
3991
3992 req = (struct hclge_fd_ad_config_cmd *)desc.data;
3993 req->index = cpu_to_le32(loc);
3994 req->stage = stage;
3995
3996 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
3997 action->write_rule_id_to_bd);
3998 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
3999 action->rule_id);
4000 ad_data <<= 32;
4001 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
4002 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
4003 action->forward_to_direct_queue);
4004 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
4005 action->queue_id);
4006 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
4007 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
4008 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
4009 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
4010 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
4011 action->counter_id);
4012
4013 req->ad_data = cpu_to_le64(ad_data);
4014 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4015 if (ret)
4016 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
4017
4018 return ret;
4019}
4020
4021static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
4022 struct hclge_fd_rule *rule)
4023{
4024 u16 tmp_x_s, tmp_y_s;
4025 u32 tmp_x_l, tmp_y_l;
4026 int i;
4027
4028 if (rule->unused_tuple & tuple_bit)
4029 return true;
4030
4031 switch (tuple_bit) {
4032 case 0:
4033 return false;
4034 case BIT(INNER_DST_MAC):
4035 for (i = 0; i < 6; i++) {
4036 calc_x(key_x[5 - i], rule->tuples.dst_mac[i],
4037 rule->tuples_mask.dst_mac[i]);
4038 calc_y(key_y[5 - i], rule->tuples.dst_mac[i],
4039 rule->tuples_mask.dst_mac[i]);
4040 }
4041
4042 return true;
4043 case BIT(INNER_SRC_MAC):
4044 for (i = 0; i < 6; i++) {
4045 calc_x(key_x[5 - i], rule->tuples.src_mac[i],
4046 rule->tuples.src_mac[i]);
4047 calc_y(key_y[5 - i], rule->tuples.src_mac[i],
4048 rule->tuples.src_mac[i]);
4049 }
4050
4051 return true;
4052 case BIT(INNER_VLAN_TAG_FST):
4053 calc_x(tmp_x_s, rule->tuples.vlan_tag1,
4054 rule->tuples_mask.vlan_tag1);
4055 calc_y(tmp_y_s, rule->tuples.vlan_tag1,
4056 rule->tuples_mask.vlan_tag1);
4057 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4058 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4059
4060 return true;
4061 case BIT(INNER_ETH_TYPE):
4062 calc_x(tmp_x_s, rule->tuples.ether_proto,
4063 rule->tuples_mask.ether_proto);
4064 calc_y(tmp_y_s, rule->tuples.ether_proto,
4065 rule->tuples_mask.ether_proto);
4066 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4067 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4068
4069 return true;
4070 case BIT(INNER_IP_TOS):
4071 calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
4072 calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
4073
4074 return true;
4075 case BIT(INNER_IP_PROTO):
4076 calc_x(*key_x, rule->tuples.ip_proto,
4077 rule->tuples_mask.ip_proto);
4078 calc_y(*key_y, rule->tuples.ip_proto,
4079 rule->tuples_mask.ip_proto);
4080
4081 return true;
4082 case BIT(INNER_SRC_IP):
4083 calc_x(tmp_x_l, rule->tuples.src_ip[3],
4084 rule->tuples_mask.src_ip[3]);
4085 calc_y(tmp_y_l, rule->tuples.src_ip[3],
4086 rule->tuples_mask.src_ip[3]);
4087 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
4088 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
4089
4090 return true;
4091 case BIT(INNER_DST_IP):
4092 calc_x(tmp_x_l, rule->tuples.dst_ip[3],
4093 rule->tuples_mask.dst_ip[3]);
4094 calc_y(tmp_y_l, rule->tuples.dst_ip[3],
4095 rule->tuples_mask.dst_ip[3]);
4096 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
4097 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
4098
4099 return true;
4100 case BIT(INNER_SRC_PORT):
4101 calc_x(tmp_x_s, rule->tuples.src_port,
4102 rule->tuples_mask.src_port);
4103 calc_y(tmp_y_s, rule->tuples.src_port,
4104 rule->tuples_mask.src_port);
4105 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4106 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4107
4108 return true;
4109 case BIT(INNER_DST_PORT):
4110 calc_x(tmp_x_s, rule->tuples.dst_port,
4111 rule->tuples_mask.dst_port);
4112 calc_y(tmp_y_s, rule->tuples.dst_port,
4113 rule->tuples_mask.dst_port);
4114 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4115 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4116
4117 return true;
4118 default:
4119 return false;
4120 }
4121}
4122
4123static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
4124 u8 vf_id, u8 network_port_id)
4125{
4126 u32 port_number = 0;
4127
4128 if (port_type == HOST_PORT) {
4129 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
4130 pf_id);
4131 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
4132 vf_id);
4133 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
4134 } else {
4135 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
4136 HCLGE_NETWORK_PORT_ID_S, network_port_id);
4137 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
4138 }
4139
4140 return port_number;
4141}
4142
4143static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
4144 __le32 *key_x, __le32 *key_y,
4145 struct hclge_fd_rule *rule)
4146{
4147 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
4148 u8 cur_pos = 0, tuple_size, shift_bits;
4149 int i;
4150
4151 for (i = 0; i < MAX_META_DATA; i++) {
4152 tuple_size = meta_data_key_info[i].key_length;
4153 tuple_bit = key_cfg->meta_data_active & BIT(i);
4154
4155 switch (tuple_bit) {
4156 case BIT(ROCE_TYPE):
4157 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
4158 cur_pos += tuple_size;
4159 break;
4160 case BIT(DST_VPORT):
4161 port_number = hclge_get_port_number(HOST_PORT, 0,
4162 rule->vf_id, 0);
4163 hnae3_set_field(meta_data,
4164 GENMASK(cur_pos + tuple_size, cur_pos),
4165 cur_pos, port_number);
4166 cur_pos += tuple_size;
4167 break;
4168 default:
4169 break;
4170 }
4171 }
4172
4173 calc_x(tmp_x, meta_data, 0xFFFFFFFF);
4174 calc_y(tmp_y, meta_data, 0xFFFFFFFF);
4175 shift_bits = sizeof(meta_data) * 8 - cur_pos;
4176
4177 *key_x = cpu_to_le32(tmp_x << shift_bits);
4178 *key_y = cpu_to_le32(tmp_y << shift_bits);
4179}
4180
4181/* A complete key is combined with meta data key and tuple key.
4182 * Meta data key is stored at the MSB region, and tuple key is stored at
4183 * the LSB region, unused bits will be filled 0.
4184 */
4185static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
4186 struct hclge_fd_rule *rule)
4187{
4188 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
4189 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
4190 u8 *cur_key_x, *cur_key_y;
4191 int i, ret, tuple_size;
4192 u8 meta_data_region;
4193
4194 memset(key_x, 0, sizeof(key_x));
4195 memset(key_y, 0, sizeof(key_y));
4196 cur_key_x = key_x;
4197 cur_key_y = key_y;
4198
4199 for (i = 0 ; i < MAX_TUPLE; i++) {
4200 bool tuple_valid;
4201 u32 check_tuple;
4202
4203 tuple_size = tuple_key_info[i].key_length / 8;
4204 check_tuple = key_cfg->tuple_active & BIT(i);
4205
4206 tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
4207 cur_key_y, rule);
4208 if (tuple_valid) {
4209 cur_key_x += tuple_size;
4210 cur_key_y += tuple_size;
4211 }
4212 }
4213
4214 meta_data_region = hdev->fd_cfg.max_key_length / 8 -
4215 MAX_META_DATA_LENGTH / 8;
4216
4217 hclge_fd_convert_meta_data(key_cfg,
4218 (__le32 *)(key_x + meta_data_region),
4219 (__le32 *)(key_y + meta_data_region),
4220 rule);
4221
4222 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
4223 true);
4224 if (ret) {
4225 dev_err(&hdev->pdev->dev,
4226 "fd key_y config fail, loc=%d, ret=%d\n",
4227 rule->queue_id, ret);
4228 return ret;
4229 }
4230
4231 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
4232 true);
4233 if (ret)
4234 dev_err(&hdev->pdev->dev,
4235 "fd key_x config fail, loc=%d, ret=%d\n",
4236 rule->queue_id, ret);
4237 return ret;
4238}
4239
4240static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
4241 struct hclge_fd_rule *rule)
4242{
4243 struct hclge_fd_ad_data ad_data;
4244
4245 ad_data.ad_id = rule->location;
4246
4247 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4248 ad_data.drop_packet = true;
4249 ad_data.forward_to_direct_queue = false;
4250 ad_data.queue_id = 0;
4251 } else {
4252 ad_data.drop_packet = false;
4253 ad_data.forward_to_direct_queue = true;
4254 ad_data.queue_id = rule->queue_id;
4255 }
4256
4257 ad_data.use_counter = false;
4258 ad_data.counter_id = 0;
4259
4260 ad_data.use_next_stage = false;
4261 ad_data.next_input_key = 0;
4262
4263 ad_data.write_rule_id_to_bd = true;
4264 ad_data.rule_id = rule->location;
4265
4266 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
4267}
4268
dd74f815
JS		 4269static int hclge_fd_check_spec(struct hclge_dev *hdev,
4270 struct ethtool_rx_flow_spec *fs, u32 *unused)
4271{
4272 struct ethtool_tcpip4_spec *tcp_ip4_spec;
4273 struct ethtool_usrip4_spec *usr_ip4_spec;
4274 struct ethtool_tcpip6_spec *tcp_ip6_spec;
4275 struct ethtool_usrip6_spec *usr_ip6_spec;
4276 struct ethhdr *ether_spec;
4277
4278 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4279 return -EINVAL;
4280
4281 if (!(fs->flow_type & hdev->fd_cfg.proto_support))
4282 return -EOPNOTSUPP;
4283
4284 if ((fs->flow_type & FLOW_EXT) &&
4285 (fs->h_ext.data[0] != 0 || fs->h_ext.data[1] != 0)) {
4286 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
4287 return -EOPNOTSUPP;
4288 }
4289
4290 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4291 case SCTP_V4_FLOW:
4292 case TCP_V4_FLOW:
4293 case UDP_V4_FLOW:
4294 tcp_ip4_spec = &fs->h_u.tcp_ip4_spec;
4295 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
4296
4297 if (!tcp_ip4_spec->ip4src)
4298 *unused |= BIT(INNER_SRC_IP);
4299
4300 if (!tcp_ip4_spec->ip4dst)
4301 *unused |= BIT(INNER_DST_IP);
4302
4303 if (!tcp_ip4_spec->psrc)
4304 *unused |= BIT(INNER_SRC_PORT);
4305
4306 if (!tcp_ip4_spec->pdst)
4307 *unused |= BIT(INNER_DST_PORT);
4308
4309 if (!tcp_ip4_spec->tos)
4310 *unused |= BIT(INNER_IP_TOS);
4311
4312 break;
4313 case IP_USER_FLOW:
4314 usr_ip4_spec = &fs->h_u.usr_ip4_spec;
4315 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4316 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
4317
4318 if (!usr_ip4_spec->ip4src)
4319 *unused |= BIT(INNER_SRC_IP);
4320
4321 if (!usr_ip4_spec->ip4dst)
4322 *unused |= BIT(INNER_DST_IP);
4323
4324 if (!usr_ip4_spec->tos)
4325 *unused |= BIT(INNER_IP_TOS);
4326
4327 if (!usr_ip4_spec->proto)
4328 *unused |= BIT(INNER_IP_PROTO);
4329
4330 if (usr_ip4_spec->l4_4_bytes)
4331 return -EOPNOTSUPP;
4332
4333 if (usr_ip4_spec->ip_ver != ETH_RX_NFC_IP4)
4334 return -EOPNOTSUPP;
4335
4336 break;
4337 case SCTP_V6_FLOW:
4338 case TCP_V6_FLOW:
4339 case UDP_V6_FLOW:
4340 tcp_ip6_spec = &fs->h_u.tcp_ip6_spec;
4341 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4342 BIT(INNER_IP_TOS);
4343
4344 if (!tcp_ip6_spec->ip6src[0] && !tcp_ip6_spec->ip6src[1] &&
4345 !tcp_ip6_spec->ip6src[2] && !tcp_ip6_spec->ip6src[3])
4346 *unused |= BIT(INNER_SRC_IP);
4347
4348 if (!tcp_ip6_spec->ip6dst[0] && !tcp_ip6_spec->ip6dst[1] &&
4349 !tcp_ip6_spec->ip6dst[2] && !tcp_ip6_spec->ip6dst[3])
4350 *unused |= BIT(INNER_DST_IP);
4351
4352 if (!tcp_ip6_spec->psrc)
4353 *unused |= BIT(INNER_SRC_PORT);
4354
4355 if (!tcp_ip6_spec->pdst)
4356 *unused |= BIT(INNER_DST_PORT);
4357
4358 if (tcp_ip6_spec->tclass)
4359 return -EOPNOTSUPP;
4360
4361 break;
4362 case IPV6_USER_FLOW:
4363 usr_ip6_spec = &fs->h_u.usr_ip6_spec;
4364 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4365 BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) |
4366 BIT(INNER_DST_PORT);
4367
4368 if (!usr_ip6_spec->ip6src[0] && !usr_ip6_spec->ip6src[1] &&
4369 !usr_ip6_spec->ip6src[2] && !usr_ip6_spec->ip6src[3])
4370 *unused |= BIT(INNER_SRC_IP);
4371
4372 if (!usr_ip6_spec->ip6dst[0] && !usr_ip6_spec->ip6dst[1] &&
4373 !usr_ip6_spec->ip6dst[2] && !usr_ip6_spec->ip6dst[3])
4374 *unused |= BIT(INNER_DST_IP);
4375
4376 if (!usr_ip6_spec->l4_proto)
4377 *unused |= BIT(INNER_IP_PROTO);
4378
4379 if (usr_ip6_spec->tclass)
4380 return -EOPNOTSUPP;
4381
4382 if (usr_ip6_spec->l4_4_bytes)
4383 return -EOPNOTSUPP;
4384
4385 break;
4386 case ETHER_FLOW:
4387 ether_spec = &fs->h_u.ether_spec;
4388 *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
4389 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
4390 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
4391
4392 if (is_zero_ether_addr(ether_spec->h_source))
4393 *unused |= BIT(INNER_SRC_MAC);
4394
4395 if (is_zero_ether_addr(ether_spec->h_dest))
4396 *unused |= BIT(INNER_DST_MAC);
4397
4398 if (!ether_spec->h_proto)
4399 *unused |= BIT(INNER_ETH_TYPE);
4400
4401 break;
4402 default:
4403 return -EOPNOTSUPP;
4404 }
4405
4406 if ((fs->flow_type & FLOW_EXT)) {
4407 if (fs->h_ext.vlan_etype)
4408 return -EOPNOTSUPP;
4409 if (!fs->h_ext.vlan_tci)
4410 *unused |= BIT(INNER_VLAN_TAG_FST);
4411
4412 if (fs->m_ext.vlan_tci) {
4413 if (be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID)
4414 return -EINVAL;
4415 }
4416 } else {
4417 *unused |= BIT(INNER_VLAN_TAG_FST);
4418 }
4419
4420 if (fs->flow_type & FLOW_MAC_EXT) {
4421 if (!(hdev->fd_cfg.proto_support & ETHER_FLOW))
4422 return -EOPNOTSUPP;
4423
4424 if (is_zero_ether_addr(fs->h_ext.h_dest))
4425 *unused |= BIT(INNER_DST_MAC);
4426 else
4427 *unused &= ~(BIT(INNER_DST_MAC));
4428 }
4429
4430 return 0;
4431}
4432
4433static bool hclge_fd_rule_exist(struct hclge_dev *hdev, u16 location)
4434{
4435 struct hclge_fd_rule *rule = NULL;
4436 struct hlist_node *node2;
4437
4438 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4439 if (rule->location >= location)
4440 break;
4441 }
4442
4443 return rule && rule->location == location;
4444}
4445
4446static int hclge_fd_update_rule_list(struct hclge_dev *hdev,
4447 struct hclge_fd_rule *new_rule,
4448 u16 location,
4449 bool is_add)
4450{
4451 struct hclge_fd_rule *rule = NULL, *parent = NULL;
4452 struct hlist_node *node2;
4453
4454 if (is_add && !new_rule)
4455 return -EINVAL;
4456
4457 hlist_for_each_entry_safe(rule, node2,
4458 &hdev->fd_rule_list, rule_node) {
4459 if (rule->location >= location)
4460 break;
4461 parent = rule;
4462 }
4463
4464 if (rule && rule->location == location) {
4465 hlist_del(&rule->rule_node);
4466 kfree(rule);
4467 hdev->hclge_fd_rule_num--;
4468
4469 if (!is_add)
4470 return 0;
4471
4472 } else if (!is_add) {
4473 dev_err(&hdev->pdev->dev,
4474 "delete fail, rule %d is inexistent\n",
4475 location);
4476 return -EINVAL;
4477 }
4478
4479 INIT_HLIST_NODE(&new_rule->rule_node);
4480
4481 if (parent)
4482 hlist_add_behind(&new_rule->rule_node, &parent->rule_node);
4483 else
4484 hlist_add_head(&new_rule->rule_node, &hdev->fd_rule_list);
4485
4486 hdev->hclge_fd_rule_num++;
4487
4488 return 0;
4489}
4490
4491static int hclge_fd_get_tuple(struct hclge_dev *hdev,
4492 struct ethtool_rx_flow_spec *fs,
4493 struct hclge_fd_rule *rule)
4494{
4495 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
4496
4497 switch (flow_type) {
4498 case SCTP_V4_FLOW:
4499 case TCP_V4_FLOW:
4500 case UDP_V4_FLOW:
4501 rule->tuples.src_ip[3] =
4502 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
4503 rule->tuples_mask.src_ip[3] =
4504 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
4505
4506 rule->tuples.dst_ip[3] =
4507 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
4508 rule->tuples_mask.dst_ip[3] =
4509 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
4510
4511 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
4512 rule->tuples_mask.src_port =
4513 be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
4514
4515 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
4516 rule->tuples_mask.dst_port =
4517 be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
4518
4519 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
4520 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
4521
4522 rule->tuples.ether_proto = ETH_P_IP;
4523 rule->tuples_mask.ether_proto = 0xFFFF;
4524
4525 break;
4526 case IP_USER_FLOW:
4527 rule->tuples.src_ip[3] =
4528 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
4529 rule->tuples_mask.src_ip[3] =
4530 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
4531
4532 rule->tuples.dst_ip[3] =
4533 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
4534 rule->tuples_mask.dst_ip[3] =
4535 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
4536
4537 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
4538 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
4539
4540 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
4541 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
4542
4543 rule->tuples.ether_proto = ETH_P_IP;
4544 rule->tuples_mask.ether_proto = 0xFFFF;
4545
4546 break;
4547 case SCTP_V6_FLOW:
4548 case TCP_V6_FLOW:
4549 case UDP_V6_FLOW:
4550 be32_to_cpu_array(rule->tuples.src_ip,
4551 fs->h_u.tcp_ip6_spec.ip6src, 4);
4552 be32_to_cpu_array(rule->tuples_mask.src_ip,
4553 fs->m_u.tcp_ip6_spec.ip6src, 4);
4554
4555 be32_to_cpu_array(rule->tuples.dst_ip,
4556 fs->h_u.tcp_ip6_spec.ip6dst, 4);
4557 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4558 fs->m_u.tcp_ip6_spec.ip6dst, 4);
4559
4560 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
4561 rule->tuples_mask.src_port =
4562 be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
4563
4564 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
4565 rule->tuples_mask.dst_port =
4566 be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
4567
4568 rule->tuples.ether_proto = ETH_P_IPV6;
4569 rule->tuples_mask.ether_proto = 0xFFFF;
4570
4571 break;
4572 case IPV6_USER_FLOW:
4573 be32_to_cpu_array(rule->tuples.src_ip,
4574 fs->h_u.usr_ip6_spec.ip6src, 4);
4575 be32_to_cpu_array(rule->tuples_mask.src_ip,
4576 fs->m_u.usr_ip6_spec.ip6src, 4);
4577
4578 be32_to_cpu_array(rule->tuples.dst_ip,
4579 fs->h_u.usr_ip6_spec.ip6dst, 4);
4580 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4581 fs->m_u.usr_ip6_spec.ip6dst, 4);
4582
4583 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
4584 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
4585
4586 rule->tuples.ether_proto = ETH_P_IPV6;
4587 rule->tuples_mask.ether_proto = 0xFFFF;
4588
4589 break;
4590 case ETHER_FLOW:
4591 ether_addr_copy(rule->tuples.src_mac,
4592 fs->h_u.ether_spec.h_source);
4593 ether_addr_copy(rule->tuples_mask.src_mac,
4594 fs->m_u.ether_spec.h_source);
4595
4596 ether_addr_copy(rule->tuples.dst_mac,
4597 fs->h_u.ether_spec.h_dest);
4598 ether_addr_copy(rule->tuples_mask.dst_mac,
4599 fs->m_u.ether_spec.h_dest);
4600
4601 rule->tuples.ether_proto =
4602 be16_to_cpu(fs->h_u.ether_spec.h_proto);
4603 rule->tuples_mask.ether_proto =
4604 be16_to_cpu(fs->m_u.ether_spec.h_proto);
4605
4606 break;
4607 default:
4608 return -EOPNOTSUPP;
4609 }
4610
4611 switch (flow_type) {
4612 case SCTP_V4_FLOW:
4613 case SCTP_V6_FLOW:
4614 rule->tuples.ip_proto = IPPROTO_SCTP;
4615 rule->tuples_mask.ip_proto = 0xFF;
4616 break;
4617 case TCP_V4_FLOW:
4618 case TCP_V6_FLOW:
4619 rule->tuples.ip_proto = IPPROTO_TCP;
4620 rule->tuples_mask.ip_proto = 0xFF;
4621 break;
4622 case UDP_V4_FLOW:
4623 case UDP_V6_FLOW:
4624 rule->tuples.ip_proto = IPPROTO_UDP;
4625 rule->tuples_mask.ip_proto = 0xFF;
4626 break;
4627 default:
4628 break;
4629 }
4630
4631 if ((fs->flow_type & FLOW_EXT)) {
4632 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
4633 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
4634 }
4635
4636 if (fs->flow_type & FLOW_MAC_EXT) {
4637 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
4638 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
4639 }
4640
4641 return 0;
4642}
4643
4644static int hclge_add_fd_entry(struct hnae3_handle *handle,
4645 struct ethtool_rxnfc *cmd)
4646{
4647 struct hclge_vport *vport = hclge_get_vport(handle);
4648 struct hclge_dev *hdev = vport->back;
4649 u16 dst_vport_id = 0, q_index = 0;
4650 struct ethtool_rx_flow_spec *fs;
4651 struct hclge_fd_rule *rule;
4652 u32 unused = 0;
4653 u8 action;
4654 int ret;
4655
4656 if (!hnae3_dev_fd_supported(hdev))
4657 return -EOPNOTSUPP;
4658
4659 if (!hdev->fd_cfg.fd_en) {
4660 dev_warn(&hdev->pdev->dev,
4661 "Please enable flow director first\n");
4662 return -EOPNOTSUPP;
4663 }
4664
4665 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4666
4667 ret = hclge_fd_check_spec(hdev, fs, &unused);
4668 if (ret) {
4669 dev_err(&hdev->pdev->dev, "Check fd spec failed\n");
4670 return ret;
4671 }
4672
4673 if (fs->ring_cookie == RX_CLS_FLOW_DISC) {
4674 action = HCLGE_FD_ACTION_DROP_PACKET;
4675 } else {
4676 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
4677 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
4678 u16 tqps;
4679
0285dbae
JS		 4680 if (vf > hdev->num_req_vfs) {
4681 dev_err(&hdev->pdev->dev,
4682 "Error: vf id (%d) > max vf num (%d)\n",
4683 vf, hdev->num_req_vfs);
4684 return -EINVAL;
4685 }
4686
dd74f815
JS		 4687 dst_vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
4688 tqps = vf ? hdev->vport[vf].alloc_tqps : vport->alloc_tqps;
4689
4690 if (ring >= tqps) {
4691 dev_err(&hdev->pdev->dev,
4692 "Error: queue id (%d) > max tqp num (%d)\n",
4693 ring, tqps - 1);
4694 return -EINVAL;
4695 }
4696
dd74f815
JS		 4697 action = HCLGE_FD_ACTION_ACCEPT_PACKET;
4698 q_index = ring;
4699 }
4700
4701 rule = kzalloc(sizeof(*rule), GFP_KERNEL);
4702 if (!rule)
4703 return -ENOMEM;
4704
4705 ret = hclge_fd_get_tuple(hdev, fs, rule);
4706 if (ret)
4707 goto free_rule;
4708
4709 rule->flow_type = fs->flow_type;
4710
4711 rule->location = fs->location;
4712 rule->unused_tuple = unused;
4713 rule->vf_id = dst_vport_id;
4714 rule->queue_id = q_index;
4715 rule->action = action;
4716
4717 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4718 if (ret)
4719 goto free_rule;
4720
4721 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4722 if (ret)
4723 goto free_rule;
4724
4725 ret = hclge_fd_update_rule_list(hdev, rule, fs->location, true);
4726 if (ret)
4727 goto free_rule;
4728
4729 return ret;
4730
4731free_rule:
4732 kfree(rule);
4733 return ret;
4734}
4735
4736static int hclge_del_fd_entry(struct hnae3_handle *handle,
4737 struct ethtool_rxnfc *cmd)
4738{
4739 struct hclge_vport *vport = hclge_get_vport(handle);
4740 struct hclge_dev *hdev = vport->back;
4741 struct ethtool_rx_flow_spec *fs;
4742 int ret;
4743
4744 if (!hnae3_dev_fd_supported(hdev))
4745 return -EOPNOTSUPP;
4746
4747 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4748
4749 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4750 return -EINVAL;
4751
4752 if (!hclge_fd_rule_exist(hdev, fs->location)) {
4753 dev_err(&hdev->pdev->dev,
4754 "Delete fail, rule %d is inexistent\n",
4755 fs->location);
4756 return -ENOENT;
4757 }
4758
4759 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4760 fs->location, NULL, false);
4761 if (ret)
4762 return ret;
4763
4764 return hclge_fd_update_rule_list(hdev, NULL, fs->location,
4765 false);
4766}
4767
6871af29
JS		 4768static void hclge_del_all_fd_entries(struct hnae3_handle *handle,
4769 bool clear_list)
4770{
4771 struct hclge_vport *vport = hclge_get_vport(handle);
4772 struct hclge_dev *hdev = vport->back;
4773 struct hclge_fd_rule *rule;
4774 struct hlist_node *node;
4775
4776 if (!hnae3_dev_fd_supported(hdev))
4777 return;
4778
4779 if (clear_list) {
4780 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4781 rule_node) {
4782 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4783 rule->location, NULL, false);
4784 hlist_del(&rule->rule_node);
4785 kfree(rule);
4786 hdev->hclge_fd_rule_num--;
4787 }
4788 } else {
4789 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4790 rule_node)
4791 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4792 rule->location, NULL, false);
4793 }
4794}
4795
4796static int hclge_restore_fd_entries(struct hnae3_handle *handle)
4797{
4798 struct hclge_vport *vport = hclge_get_vport(handle);
4799 struct hclge_dev *hdev = vport->back;
4800 struct hclge_fd_rule *rule;
4801 struct hlist_node *node;
4802 int ret;
4803
65e41e7e
HT		 4804 /* Return ok here, because reset error handling will check this
4805 * return value. If error is returned here, the reset process will
4806 * fail.
4807 */
6871af29 4808 if (!hnae3_dev_fd_supported(hdev))
65e41e7e 4809 return 0;
6871af29
JS		 4810
4811 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
4812 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4813 if (!ret)
4814 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4815
4816 if (ret) {
4817 dev_warn(&hdev->pdev->dev,
4818 "Restore rule %d failed, remove it\n",
4819 rule->location);
4820 hlist_del(&rule->rule_node);
4821 kfree(rule);
4822 hdev->hclge_fd_rule_num--;
4823 }
4824 }
4825 return 0;
4826}
4827
05c2314f
JS		 4828static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
4829 struct ethtool_rxnfc *cmd)
4830{
4831 struct hclge_vport *vport = hclge_get_vport(handle);
4832 struct hclge_dev *hdev = vport->back;
4833
4834 if (!hnae3_dev_fd_supported(hdev))
4835 return -EOPNOTSUPP;
4836
4837 cmd->rule_cnt = hdev->hclge_fd_rule_num;
4838 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4839
4840 return 0;
4841}
4842
4843static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
4844 struct ethtool_rxnfc *cmd)
4845{
4846 struct hclge_vport *vport = hclge_get_vport(handle);
4847 struct hclge_fd_rule *rule = NULL;
4848 struct hclge_dev *hdev = vport->back;
4849 struct ethtool_rx_flow_spec *fs;
4850 struct hlist_node *node2;
4851
4852 if (!hnae3_dev_fd_supported(hdev))
4853 return -EOPNOTSUPP;
4854
4855 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4856
4857 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4858 if (rule->location >= fs->location)
4859 break;
4860 }
4861
4862 if (!rule || fs->location != rule->location)
4863 return -ENOENT;
4864
4865 fs->flow_type = rule->flow_type;
4866 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4867 case SCTP_V4_FLOW:
4868 case TCP_V4_FLOW:
4869 case UDP_V4_FLOW:
4870 fs->h_u.tcp_ip4_spec.ip4src =
4871 cpu_to_be32(rule->tuples.src_ip[3]);
4872 fs->m_u.tcp_ip4_spec.ip4src =
4873 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4874 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4875
4876 fs->h_u.tcp_ip4_spec.ip4dst =
4877 cpu_to_be32(rule->tuples.dst_ip[3]);
4878 fs->m_u.tcp_ip4_spec.ip4dst =
4879 rule->unused_tuple & BIT(INNER_DST_IP) ?
4880 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4881
4882 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4883 fs->m_u.tcp_ip4_spec.psrc =
4884 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4885 0 : cpu_to_be16(rule->tuples_mask.src_port);
4886
4887 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4888 fs->m_u.tcp_ip4_spec.pdst =
4889 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4890 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4891
4892 fs->h_u.tcp_ip4_spec.tos = rule->tuples.ip_tos;
4893 fs->m_u.tcp_ip4_spec.tos =
4894 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4895 0 : rule->tuples_mask.ip_tos;
4896
4897 break;
4898 case IP_USER_FLOW:
4899 fs->h_u.usr_ip4_spec.ip4src =
4900 cpu_to_be32(rule->tuples.src_ip[3]);
4901 fs->m_u.tcp_ip4_spec.ip4src =
4902 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4903 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4904
4905 fs->h_u.usr_ip4_spec.ip4dst =
4906 cpu_to_be32(rule->tuples.dst_ip[3]);
4907 fs->m_u.usr_ip4_spec.ip4dst =
4908 rule->unused_tuple & BIT(INNER_DST_IP) ?
4909 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4910
4911 fs->h_u.usr_ip4_spec.tos = rule->tuples.ip_tos;
4912 fs->m_u.usr_ip4_spec.tos =
4913 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4914 0 : rule->tuples_mask.ip_tos;
4915
4916 fs->h_u.usr_ip4_spec.proto = rule->tuples.ip_proto;
4917 fs->m_u.usr_ip4_spec.proto =
4918 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4919 0 : rule->tuples_mask.ip_proto;
4920
4921 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
4922
4923 break;
4924 case SCTP_V6_FLOW:
4925 case TCP_V6_FLOW:
4926 case UDP_V6_FLOW:
4927 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6src,
4928 rule->tuples.src_ip, 4);
4929 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4930 memset(fs->m_u.tcp_ip6_spec.ip6src, 0, sizeof(int) * 4);
4931 else
4932 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6src,
4933 rule->tuples_mask.src_ip, 4);
4934
4935 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6dst,
4936 rule->tuples.dst_ip, 4);
4937 if (rule->unused_tuple & BIT(INNER_DST_IP))
4938 memset(fs->m_u.tcp_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4939 else
4940 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6dst,
4941 rule->tuples_mask.dst_ip, 4);
4942
4943 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4944 fs->m_u.tcp_ip6_spec.psrc =
4945 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4946 0 : cpu_to_be16(rule->tuples_mask.src_port);
4947
4948 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4949 fs->m_u.tcp_ip6_spec.pdst =
4950 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4951 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4952
4953 break;
4954 case IPV6_USER_FLOW:
4955 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6src,
4956 rule->tuples.src_ip, 4);
4957 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4958 memset(fs->m_u.usr_ip6_spec.ip6src, 0, sizeof(int) * 4);
4959 else
4960 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6src,
4961 rule->tuples_mask.src_ip, 4);
4962
4963 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6dst,
4964 rule->tuples.dst_ip, 4);
4965 if (rule->unused_tuple & BIT(INNER_DST_IP))
4966 memset(fs->m_u.usr_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4967 else
4968 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6dst,
4969 rule->tuples_mask.dst_ip, 4);
4970
4971 fs->h_u.usr_ip6_spec.l4_proto = rule->tuples.ip_proto;
4972 fs->m_u.usr_ip6_spec.l4_proto =
4973 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4974 0 : rule->tuples_mask.ip_proto;
4975
4976 break;
4977 case ETHER_FLOW:
4978 ether_addr_copy(fs->h_u.ether_spec.h_source,
4979 rule->tuples.src_mac);
4980 if (rule->unused_tuple & BIT(INNER_SRC_MAC))
4981 eth_zero_addr(fs->m_u.ether_spec.h_source);
4982 else
4983 ether_addr_copy(fs->m_u.ether_spec.h_source,
4984 rule->tuples_mask.src_mac);
4985
4986 ether_addr_copy(fs->h_u.ether_spec.h_dest,
4987 rule->tuples.dst_mac);
4988 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4989 eth_zero_addr(fs->m_u.ether_spec.h_dest);
4990 else
4991 ether_addr_copy(fs->m_u.ether_spec.h_dest,
4992 rule->tuples_mask.dst_mac);
4993
4994 fs->h_u.ether_spec.h_proto =
4995 cpu_to_be16(rule->tuples.ether_proto);
4996 fs->m_u.ether_spec.h_proto =
4997 rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
4998 0 : cpu_to_be16(rule->tuples_mask.ether_proto);
4999
5000 break;
5001 default:
5002 return -EOPNOTSUPP;
5003 }
5004
5005 if (fs->flow_type & FLOW_EXT) {
5006 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
5007 fs->m_ext.vlan_tci =
5008 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
5009 cpu_to_be16(VLAN_VID_MASK) :
5010 cpu_to_be16(rule->tuples_mask.vlan_tag1);
5011 }
5012
5013 if (fs->flow_type & FLOW_MAC_EXT) {
5014 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
5015 if (rule->unused_tuple & BIT(INNER_DST_MAC))
5016 eth_zero_addr(fs->m_u.ether_spec.h_dest);
5017 else
5018 ether_addr_copy(fs->m_u.ether_spec.h_dest,
5019 rule->tuples_mask.dst_mac);
5020 }
5021
5022 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
5023 fs->ring_cookie = RX_CLS_FLOW_DISC;
5024 } else {
5025 u64 vf_id;
5026
5027 fs->ring_cookie = rule->queue_id;
5028 vf_id = rule->vf_id;
5029 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
5030 fs->ring_cookie |= vf_id;
5031 }
5032
5033 return 0;
5034}
5035
5036static int hclge_get_all_rules(struct hnae3_handle *handle,
5037 struct ethtool_rxnfc *cmd, u32 *rule_locs)
5038{
5039 struct hclge_vport *vport = hclge_get_vport(handle);
5040 struct hclge_dev *hdev = vport->back;
5041 struct hclge_fd_rule *rule;
5042 struct hlist_node *node2;
5043 int cnt = 0;
5044
5045 if (!hnae3_dev_fd_supported(hdev))
5046 return -EOPNOTSUPP;
5047
5048 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
5049
5050 hlist_for_each_entry_safe(rule, node2,
5051 &hdev->fd_rule_list, rule_node) {
5052 if (cnt == cmd->rule_cnt)
5053 return -EMSGSIZE;
5054
5055 rule_locs[cnt] = rule->location;
5056 cnt++;
5057 }
5058
5059 cmd->rule_cnt = cnt;
5060
5061 return 0;
5062}
5063
4d60291b
HT		 5064static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
5065{
5066 struct hclge_vport *vport = hclge_get_vport(handle);
5067 struct hclge_dev *hdev = vport->back;
5068
5069 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
5070 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
5071}
5072
5073static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
5074{
5075 struct hclge_vport *vport = hclge_get_vport(handle);
5076 struct hclge_dev *hdev = vport->back;
5077
5078 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5079}
5080
5081static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
5082{
5083 struct hclge_vport *vport = hclge_get_vport(handle);
5084 struct hclge_dev *hdev = vport->back;
5085
5086 return hdev->reset_count;
5087}
5088
c17852a8
JS		 5089static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
5090{
5091 struct hclge_vport *vport = hclge_get_vport(handle);
5092 struct hclge_dev *hdev = vport->back;
5093
5094 hdev->fd_cfg.fd_en = enable;
5095 if (!enable)
5096 hclge_del_all_fd_entries(handle, false);
5097 else
5098 hclge_restore_fd_entries(handle);
5099}
5100
46a3df9f
S		 5101static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
5102{
5103 struct hclge_desc desc;
d44f9b63
YL		 5104 struct hclge_config_mac_mode_cmd *req =
5105 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 5106 u32 loop_en = 0;
46a3df9f
S		 5107 int ret;
5108
5109 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
e4e87715
PL		 5110 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
5111 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
5112 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
5113 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
5114 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
5115 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
5116 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
5117 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
5118 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
5119 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
5120 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
5121 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
5122 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
5123 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 5124 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 5125
5126 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5127 if (ret)
5128 dev_err(&hdev->pdev->dev,
5129 "mac enable fail, ret =%d.\n", ret);
5130}
5131
eb66d503 5132static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 5133{
c39c4d98 5134 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 5135 struct hclge_desc desc;
5136 u32 loop_en;
5137 int ret;
5138
e4d68dae
YL		 5139 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
5140 /* 1 Read out the MAC mode config at first */
5141 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
5142 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5143 if (ret) {
5144 dev_err(&hdev->pdev->dev,
5145 "mac loopback get fail, ret =%d.\n", ret);
5146 return ret;
5147 }
c39c4d98 5148
e4d68dae
YL		 5149 /* 2 Then setup the loopback flag */
5150 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
e4e87715 5151 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
0f29fc23
YL		 5152 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
5153 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
e4d68dae
YL		 5154
5155 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 5156
e4d68dae
YL		 5157 /* 3 Config mac work mode with loopback flag
5158 * and its original configure parameters
5159 */
5160 hclge_cmd_reuse_desc(&desc, false);
5161 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5162 if (ret)
5163 dev_err(&hdev->pdev->dev,
5164 "mac loopback set fail, ret =%d.\n", ret);
5165 return ret;
5166}
c39c4d98 5167
4dc13b96
FL		 5168static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
5169 enum hnae3_loop loop_mode)
5fd50ac3
PL		 5170{
5171#define HCLGE_SERDES_RETRY_MS 10
5172#define HCLGE_SERDES_RETRY_NUM 100
5173 struct hclge_serdes_lb_cmd *req;
5174 struct hclge_desc desc;
5175 int ret, i = 0;
4dc13b96 5176 u8 loop_mode_b;
5fd50ac3 5177
d0d72bac 5178 req = (struct hclge_serdes_lb_cmd *)desc.data;
5fd50ac3
PL		 5179 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
5180
4dc13b96
FL		 5181 switch (loop_mode) {
5182 case HNAE3_LOOP_SERIAL_SERDES:
5183 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
5184 break;
5185 case HNAE3_LOOP_PARALLEL_SERDES:
5186 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
5187 break;
5188 default:
5189 dev_err(&hdev->pdev->dev,
5190 "unsupported serdes loopback mode %d\n", loop_mode);
5191 return -ENOTSUPP;
5192 }
5193
5fd50ac3 5194 if (en) {
4dc13b96
FL		 5195 req->enable = loop_mode_b;
5196 req->mask = loop_mode_b;
5fd50ac3 5197 } else {
4dc13b96 5198 req->mask = loop_mode_b;
5fd50ac3
PL		 5199 }
5200
5201 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5202 if (ret) {
5203 dev_err(&hdev->pdev->dev,
5204 "serdes loopback set fail, ret = %d\n", ret);
5205 return ret;
5206 }
5207
5208 do {
5209 msleep(HCLGE_SERDES_RETRY_MS);
5210 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
5211 true);
5212 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5213 if (ret) {
5214 dev_err(&hdev->pdev->dev,
5215 "serdes loopback get, ret = %d\n", ret);
5216 return ret;
5217 }
5218 } while (++i < HCLGE_SERDES_RETRY_NUM &&
5219 !(req->result & HCLGE_CMD_SERDES_DONE_B));
5220
5221 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
5222 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
5223 return -EBUSY;
5224 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
5225 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
5226 return -EIO;
5227 }
5228
0f29fc23 5229 hclge_cfg_mac_mode(hdev, en);
5fd50ac3
PL		 5230 return 0;
5231}
5232
0f29fc23
YL		 5233static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
5234 int stream_id, bool enable)
5235{
5236 struct hclge_desc desc;
5237 struct hclge_cfg_com_tqp_queue_cmd *req =
5238 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
5239 int ret;
5240
5241 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
5242 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
5243 req->stream_id = cpu_to_le16(stream_id);
5244 req->enable |= enable << HCLGE_TQP_ENABLE_B;
5245
5246 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5247 if (ret)
5248 dev_err(&hdev->pdev->dev,
5249 "Tqp enable fail, status =%d.\n", ret);
5250 return ret;
5251}
5252
e4d68dae
YL		 5253static int hclge_set_loopback(struct hnae3_handle *handle,
5254 enum hnae3_loop loop_mode, bool en)
5255{
5256 struct hclge_vport *vport = hclge_get_vport(handle);
5257 struct hclge_dev *hdev = vport->back;
0f29fc23 5258 int i, ret;
e4d68dae
YL		 5259
5260 switch (loop_mode) {
eb66d503
FL		 5261 case HNAE3_LOOP_APP:
5262 ret = hclge_set_app_loopback(hdev, en);
c39c4d98 5263 break;
4dc13b96
FL		 5264 case HNAE3_LOOP_SERIAL_SERDES:
5265 case HNAE3_LOOP_PARALLEL_SERDES:
5266 ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
5fd50ac3 5267 break;
c39c4d98
YL		 5268 default:
5269 ret = -ENOTSUPP;
5270 dev_err(&hdev->pdev->dev,
5271 "loop_mode %d is not supported\n", loop_mode);
5272 break;
5273 }
5274
0f29fc23
YL		 5275 for (i = 0; i < vport->alloc_tqps; i++) {
5276 ret = hclge_tqp_enable(hdev, i, 0, en);
5277 if (ret)
5278 return ret;
5279 }
46a3df9f 5280
0f29fc23 5281 return 0;
46a3df9f
S		 5282}
5283
5284static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
5285{
5286 struct hclge_vport *vport = hclge_get_vport(handle);
5287 struct hnae3_queue *queue;
5288 struct hclge_tqp *tqp;
5289 int i;
5290
5291 for (i = 0; i < vport->alloc_tqps; i++) {
5292 queue = handle->kinfo.tqp[i];
5293 tqp = container_of(queue, struct hclge_tqp, q);
5294 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
5295 }
5296}
5297
8cdb992f
JS		 5298static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable)
5299{
5300 struct hclge_vport *vport = hclge_get_vport(handle);
5301 struct hclge_dev *hdev = vport->back;
5302
5303 if (enable) {
5304 mod_timer(&hdev->service_timer, jiffies + HZ);
5305 } else {
5306 del_timer_sync(&hdev->service_timer);
5307 cancel_work_sync(&hdev->service_task);
5308 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
5309 }
5310}
5311
46a3df9f
S		 5312static int hclge_ae_start(struct hnae3_handle *handle)
5313{
5314 struct hclge_vport *vport = hclge_get_vport(handle);
5315 struct hclge_dev *hdev = vport->back;
46a3df9f 5316
46a3df9f
S		 5317 /* mac enable */
5318 hclge_cfg_mac_mode(hdev, true);
5319 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
be8d8cdb 5320 hdev->hw.mac.link = 0;
46a3df9f 5321
b50ae26c
PL		 5322 /* reset tqp stats */
5323 hclge_reset_tqp_stats(handle);
5324
b01b7cf1 5325 hclge_mac_start_phy(hdev);
46a3df9f 5326
46a3df9f
S		 5327 return 0;
5328}
5329
5330static void hclge_ae_stop(struct hnae3_handle *handle)
5331{
5332 struct hclge_vport *vport = hclge_get_vport(handle);
5333 struct hclge_dev *hdev = vport->back;
39cfbc9c 5334 int i;
46a3df9f 5335
2f7e4896
FL		 5336 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5337
35d93a30
HT		 5338 /* If it is not PF reset, the firmware will disable the MAC,
5339 * so it only need to stop phy here.
5340 */
5341 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
5342 hdev->reset_type != HNAE3_FUNC_RESET) {
9617f668 5343 hclge_mac_stop_phy(hdev);
b50ae26c 5344 return;
9617f668 5345 }
b50ae26c 5346
39cfbc9c
HT		 5347 for (i = 0; i < handle->kinfo.num_tqps; i++)
5348 hclge_reset_tqp(handle, i);
5349
46a3df9f
S		 5350 /* Mac disable */
5351 hclge_cfg_mac_mode(hdev, false);
5352
5353 hclge_mac_stop_phy(hdev);
5354
5355 /* reset tqp stats */
5356 hclge_reset_tqp_stats(handle);
f30dfddc 5357 hclge_update_link_status(hdev);
46a3df9f
S		 5358}
5359
a6d818e3
YL		 5360int hclge_vport_start(struct hclge_vport *vport)
5361{
5362 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
5363 vport->last_active_jiffies = jiffies;
5364 return 0;
5365}
5366
5367void hclge_vport_stop(struct hclge_vport *vport)
5368{
5369 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
5370}
5371
5372static int hclge_client_start(struct hnae3_handle *handle)
5373{
5374 struct hclge_vport *vport = hclge_get_vport(handle);
5375
5376 return hclge_vport_start(vport);
5377}
5378
5379static void hclge_client_stop(struct hnae3_handle *handle)
5380{
5381 struct hclge_vport *vport = hclge_get_vport(handle);
5382
5383 hclge_vport_stop(vport);
5384}
5385
46a3df9f
S		 5386static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
5387 u16 cmdq_resp, u8 resp_code,
5388 enum hclge_mac_vlan_tbl_opcode op)
5389{
5390 struct hclge_dev *hdev = vport->back;
5391 int return_status = -EIO;
5392
5393 if (cmdq_resp) {
5394 dev_err(&hdev->pdev->dev,
5395 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
5396 cmdq_resp);
5397 return -EIO;
5398 }
5399
5400 if (op == HCLGE_MAC_VLAN_ADD) {
5401 if ((!resp_code) || (resp_code == 1)) {
5402 return_status = 0;
5403 } else if (resp_code == 2) {
eefd00a5 5404 return_status = -ENOSPC;
46a3df9f
S		 5405 dev_err(&hdev->pdev->dev,
5406 "add mac addr failed for uc_overflow.\n");
5407 } else if (resp_code == 3) {
eefd00a5 5408 return_status = -ENOSPC;
46a3df9f
S		 5409 dev_err(&hdev->pdev->dev,
5410 "add mac addr failed for mc_overflow.\n");
5411 } else {
5412 dev_err(&hdev->pdev->dev,
5413 "add mac addr failed for undefined, code=%d.\n",
5414 resp_code);
5415 }
5416 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
5417 if (!resp_code) {
5418 return_status = 0;
5419 } else if (resp_code == 1) {
eefd00a5 5420 return_status = -ENOENT;
46a3df9f
S		 5421 dev_dbg(&hdev->pdev->dev,
5422 "remove mac addr failed for miss.\n");
5423 } else {
5424 dev_err(&hdev->pdev->dev,
5425 "remove mac addr failed for undefined, code=%d.\n",
5426 resp_code);
5427 }
5428 } else if (op == HCLGE_MAC_VLAN_LKUP) {
5429 if (!resp_code) {
5430 return_status = 0;
5431 } else if (resp_code == 1) {
eefd00a5 5432 return_status = -ENOENT;
46a3df9f
S		 5433 dev_dbg(&hdev->pdev->dev,
5434 "lookup mac addr failed for miss.\n");
5435 } else {
5436 dev_err(&hdev->pdev->dev,
5437 "lookup mac addr failed for undefined, code=%d.\n",
5438 resp_code);
5439 }
5440 } else {
eefd00a5 5441 return_status = -EINVAL;
46a3df9f
S		 5442 dev_err(&hdev->pdev->dev,
5443 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
5444 op);
5445 }
5446
5447 return return_status;
5448}
5449
5450static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
5451{
5452 int word_num;
5453 int bit_num;
5454
5455 if (vfid > 255 || vfid < 0)
5456 return -EIO;
5457
5458 if (vfid >= 0 && vfid <= 191) {
5459 word_num = vfid / 32;
5460 bit_num = vfid % 32;
5461 if (clr)
a90bb9a5 5462 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 5463 else
a90bb9a5 5464 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 5465 } else {
5466 word_num = (vfid - 192) / 32;
5467 bit_num = vfid % 32;
5468 if (clr)
a90bb9a5 5469 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 5470 else
a90bb9a5 5471 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 5472 }
5473
5474 return 0;
5475}
5476
5477static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
5478{
5479#define HCLGE_DESC_NUMBER 3
5480#define HCLGE_FUNC_NUMBER_PER_DESC 6
5481 int i, j;
5482
6c39d527 5483 for (i = 1; i < HCLGE_DESC_NUMBER; i++)
46a3df9f
S		 5484 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
5485 if (desc[i].data[j])
5486 return false;
5487
5488 return true;
5489}
5490
d44f9b63 5491static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 5492 const u8 *addr)
5493{
5494 const unsigned char *mac_addr = addr;
5495 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
5496 (mac_addr[0]) | (mac_addr[1] << 8);
5497 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
5498
5499 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
5500 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
5501}
5502
46a3df9f 5503static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5504 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 5505{
5506 struct hclge_dev *hdev = vport->back;
5507 struct hclge_desc desc;
5508 u8 resp_code;
a90bb9a5 5509 u16 retval;
46a3df9f
S		 5510 int ret;
5511
5512 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
5513
d44f9b63 5514 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5515
5516 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5517 if (ret) {
5518 dev_err(&hdev->pdev->dev,
5519 "del mac addr failed for cmd_send, ret =%d.\n",
5520 ret);
5521 return ret;
5522 }
a90bb9a5
YL		 5523 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5524 retval = le16_to_cpu(desc.retval);
46a3df9f 5525
a90bb9a5 5526 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 5527 HCLGE_MAC_VLAN_REMOVE);
5528}
5529
5530static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5531 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 5532 struct hclge_desc *desc,
5533 bool is_mc)
5534{
5535 struct hclge_dev *hdev = vport->back;
5536 u8 resp_code;
a90bb9a5 5537 u16 retval;
46a3df9f
S		 5538 int ret;
5539
5540 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
5541 if (is_mc) {
5542 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5543 memcpy(desc[0].data,
5544 req,
d44f9b63 5545 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5546 hclge_cmd_setup_basic_desc(&desc[1],
5547 HCLGE_OPC_MAC_VLAN_ADD,
5548 true);
5549 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5550 hclge_cmd_setup_basic_desc(&desc[2],
5551 HCLGE_OPC_MAC_VLAN_ADD,
5552 true);
5553 ret = hclge_cmd_send(&hdev->hw, desc, 3);
5554 } else {
5555 memcpy(desc[0].data,
5556 req,
d44f9b63 5557 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5558 ret = hclge_cmd_send(&hdev->hw, desc, 1);
5559 }
5560 if (ret) {
5561 dev_err(&hdev->pdev->dev,
5562 "lookup mac addr failed for cmd_send, ret =%d.\n",
5563 ret);
5564 return ret;
5565 }
a90bb9a5
YL		 5566 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
5567 retval = le16_to_cpu(desc[0].retval);
46a3df9f 5568
a90bb9a5 5569 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 5570 HCLGE_MAC_VLAN_LKUP);
5571}
5572
5573static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5574 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 5575 struct hclge_desc *mc_desc)
5576{
5577 struct hclge_dev *hdev = vport->back;
5578 int cfg_status;
5579 u8 resp_code;
a90bb9a5 5580 u16 retval;
46a3df9f
S		 5581 int ret;
5582
5583 if (!mc_desc) {
5584 struct hclge_desc desc;
5585
5586 hclge_cmd_setup_basic_desc(&desc,
5587 HCLGE_OPC_MAC_VLAN_ADD,
5588 false);
d44f9b63
YL		 5589 memcpy(desc.data, req,
5590 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 5591 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 5592 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5593 retval = le16_to_cpu(desc.retval);
5594
5595 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 5596 resp_code,
5597 HCLGE_MAC_VLAN_ADD);
5598 } else {
c3b6f755 5599 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 5600 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 5601 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 5602 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 5603 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 5604 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
5605 memcpy(mc_desc[0].data, req,
d44f9b63 5606 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 5607 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 5608 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
5609 retval = le16_to_cpu(mc_desc[0].retval);
5610
5611 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 5612 resp_code,
5613 HCLGE_MAC_VLAN_ADD);
5614 }
5615
5616 if (ret) {
5617 dev_err(&hdev->pdev->dev,
5618 "add mac addr failed for cmd_send, ret =%d.\n",
5619 ret);
5620 return ret;
5621 }
5622
5623 return cfg_status;
5624}
5625
39932473
JS		 5626static int hclge_init_umv_space(struct hclge_dev *hdev)
5627{
5628 u16 allocated_size = 0;
5629 int ret;
5630
5631 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size,
5632 true);
5633 if (ret)
5634 return ret;
5635
5636 if (allocated_size < hdev->wanted_umv_size)
5637 dev_warn(&hdev->pdev->dev,
5638 "Alloc umv space failed, want %d, get %d\n",
5639 hdev->wanted_umv_size, allocated_size);
5640
5641 mutex_init(&hdev->umv_mutex);
5642 hdev->max_umv_size = allocated_size;
5643 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_req_vfs + 2);
5644 hdev->share_umv_size = hdev->priv_umv_size +
5645 hdev->max_umv_size % (hdev->num_req_vfs + 2);
5646
5647 return 0;
5648}
5649
5650static int hclge_uninit_umv_space(struct hclge_dev *hdev)
5651{
5652 int ret;
5653
5654 if (hdev->max_umv_size > 0) {
5655 ret = hclge_set_umv_space(hdev, hdev->max_umv_size, NULL,
5656 false);
5657 if (ret)
5658 return ret;
5659 hdev->max_umv_size = 0;
5660 }
5661 mutex_destroy(&hdev->umv_mutex);
5662
5663 return 0;
5664}
5665
5666static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
5667 u16 *allocated_size, bool is_alloc)
5668{
5669 struct hclge_umv_spc_alc_cmd *req;
5670 struct hclge_desc desc;
5671 int ret;
5672
5673 req = (struct hclge_umv_spc_alc_cmd *)desc.data;
5674 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
5675 hnae3_set_bit(req->allocate, HCLGE_UMV_SPC_ALC_B, !is_alloc);
5676 req->space_size = cpu_to_le32(space_size);
5677
5678 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5679 if (ret) {
5680 dev_err(&hdev->pdev->dev,
5681 "%s umv space failed for cmd_send, ret =%d\n",
5682 is_alloc ? "allocate" : "free", ret);
5683 return ret;
5684 }
5685
5686 if (is_alloc && allocated_size)
5687 *allocated_size = le32_to_cpu(desc.data[1]);
5688
5689 return 0;
5690}
5691
5692static void hclge_reset_umv_space(struct hclge_dev *hdev)
5693{
5694 struct hclge_vport *vport;
5695 int i;
5696
5697 for (i = 0; i < hdev->num_alloc_vport; i++) {
5698 vport = &hdev->vport[i];
5699 vport->used_umv_num = 0;
5700 }
5701
5702 mutex_lock(&hdev->umv_mutex);
5703 hdev->share_umv_size = hdev->priv_umv_size +
5704 hdev->max_umv_size % (hdev->num_req_vfs + 2);
5705 mutex_unlock(&hdev->umv_mutex);
5706}
5707
5708static bool hclge_is_umv_space_full(struct hclge_vport *vport)
5709{
5710 struct hclge_dev *hdev = vport->back;
5711 bool is_full;
5712
5713 mutex_lock(&hdev->umv_mutex);
5714 is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
5715 hdev->share_umv_size == 0);
5716 mutex_unlock(&hdev->umv_mutex);
5717
5718 return is_full;
5719}
5720
5721static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
5722{
5723 struct hclge_dev *hdev = vport->back;
5724
5725 mutex_lock(&hdev->umv_mutex);
5726 if (is_free) {
5727 if (vport->used_umv_num > hdev->priv_umv_size)
5728 hdev->share_umv_size++;
5729 vport->used_umv_num--;
5730 } else {
5731 if (vport->used_umv_num >= hdev->priv_umv_size)
5732 hdev->share_umv_size--;
5733 vport->used_umv_num++;
5734 }
5735 mutex_unlock(&hdev->umv_mutex);
5736}
5737
46a3df9f
S		 5738static int hclge_add_uc_addr(struct hnae3_handle *handle,
5739 const unsigned char *addr)
5740{
5741 struct hclge_vport *vport = hclge_get_vport(handle);
5742
5743 return hclge_add_uc_addr_common(vport, addr);
5744}
5745
5746int hclge_add_uc_addr_common(struct hclge_vport *vport,
5747 const unsigned char *addr)
5748{
5749 struct hclge_dev *hdev = vport->back;
d44f9b63 5750 struct hclge_mac_vlan_tbl_entry_cmd req;
d07b6bb4 5751 struct hclge_desc desc;
a90bb9a5 5752 u16 egress_port = 0;
aa7a795e 5753 int ret;
46a3df9f
S		 5754
5755 /* mac addr check */
5756 if (is_zero_ether_addr(addr) ||
5757 is_broadcast_ether_addr(addr) ||
5758 is_multicast_ether_addr(addr)) {
5759 dev_err(&hdev->pdev->dev,
5760 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
5761 addr,
5762 is_zero_ether_addr(addr),
5763 is_broadcast_ether_addr(addr),
5764 is_multicast_ether_addr(addr));
5765 return -EINVAL;
5766 }
5767
5768 memset(&req, 0, sizeof(req));
e4e87715 5769 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 5770
e4e87715
PL		 5771 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
5772 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 5773
5774 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 5775
5776 hclge_prepare_mac_addr(&req, addr);
5777
d07b6bb4
JS		 5778 /* Lookup the mac address in the mac_vlan table, and add
5779 * it if the entry is inexistent. Repeated unicast entry
5780 * is not allowed in the mac vlan table.
5781 */
5782 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
39932473
JS		 5783 if (ret == -ENOENT) {
5784 if (!hclge_is_umv_space_full(vport)) {
5785 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
5786 if (!ret)
5787 hclge_update_umv_space(vport, false);
5788 return ret;
5789 }
5790
5791 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
5792 hdev->priv_umv_size);
5793
5794 return -ENOSPC;
5795 }
d07b6bb4
JS		 5796
5797 /* check if we just hit the duplicate */
5798 if (!ret)
5799 ret = -EINVAL;
5800
5801 dev_err(&hdev->pdev->dev,
5802 "PF failed to add unicast entry(%pM) in the MAC table\n",
5803 addr);
46a3df9f 5804
aa7a795e 5805 return ret;
46a3df9f
S		 5806}
5807
5808static int hclge_rm_uc_addr(struct hnae3_handle *handle,
5809 const unsigned char *addr)
5810{
5811 struct hclge_vport *vport = hclge_get_vport(handle);
5812
5813 return hclge_rm_uc_addr_common(vport, addr);
5814}
5815
5816int hclge_rm_uc_addr_common(struct hclge_vport *vport,
5817 const unsigned char *addr)
5818{
5819 struct hclge_dev *hdev = vport->back;
d44f9b63 5820 struct hclge_mac_vlan_tbl_entry_cmd req;
aa7a795e 5821 int ret;
46a3df9f
S		 5822
5823 /* mac addr check */
5824 if (is_zero_ether_addr(addr) ||
5825 is_broadcast_ether_addr(addr) ||
5826 is_multicast_ether_addr(addr)) {
5827 dev_dbg(&hdev->pdev->dev,
5828 "Remove mac err! invalid mac:%pM.\n",
5829 addr);
5830 return -EINVAL;
5831 }
5832
5833 memset(&req, 0, sizeof(req));
e4e87715
PL		 5834 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5835 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 5836 hclge_prepare_mac_addr(&req, addr);
aa7a795e 5837 ret = hclge_remove_mac_vlan_tbl(vport, &req);
39932473
JS		 5838 if (!ret)
5839 hclge_update_umv_space(vport, true);
46a3df9f 5840
aa7a795e 5841 return ret;
46a3df9f
S		 5842}
5843
5844static int hclge_add_mc_addr(struct hnae3_handle *handle,
5845 const unsigned char *addr)
5846{
5847 struct hclge_vport *vport = hclge_get_vport(handle);
5848
a10829c4 5849 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 5850}
5851
5852int hclge_add_mc_addr_common(struct hclge_vport *vport,
5853 const unsigned char *addr)
5854{
5855 struct hclge_dev *hdev = vport->back;
d44f9b63 5856 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 5857 struct hclge_desc desc[3];
46a3df9f
S		 5858 int status;
5859
5860 /* mac addr check */
5861 if (!is_multicast_ether_addr(addr)) {
5862 dev_err(&hdev->pdev->dev,
5863 "Add mc mac err! invalid mac:%pM.\n",
5864 addr);
5865 return -EINVAL;
5866 }
5867 memset(&req, 0, sizeof(req));
e4e87715
PL		 5868 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5869 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5870 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
fd5f9da3 5871 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 5872 hclge_prepare_mac_addr(&req, addr);
5873 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5874 if (!status) {
5875 /* This mac addr exist, update VFID for it */
5876 hclge_update_desc_vfid(desc, vport->vport_id, false);
5877 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5878 } else {
5879 /* This mac addr do not exist, add new entry for it */
5880 memset(desc[0].data, 0, sizeof(desc[0].data));
5881 memset(desc[1].data, 0, sizeof(desc[0].data));
5882 memset(desc[2].data, 0, sizeof(desc[0].data));
5883 hclge_update_desc_vfid(desc, vport->vport_id, false);
5884 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5885 }
5886
1f6db589
JS		 5887 if (status == -ENOSPC)
5888 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
46a3df9f
S		 5889
5890 return status;
5891}
5892
5893static int hclge_rm_mc_addr(struct hnae3_handle *handle,
5894 const unsigned char *addr)
5895{
5896 struct hclge_vport *vport = hclge_get_vport(handle);
5897
5898 return hclge_rm_mc_addr_common(vport, addr);
5899}
5900
5901int hclge_rm_mc_addr_common(struct hclge_vport *vport,
5902 const unsigned char *addr)
5903{
5904 struct hclge_dev *hdev = vport->back;
d44f9b63 5905 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 5906 enum hclge_cmd_status status;
5907 struct hclge_desc desc[3];
46a3df9f
S		 5908
5909 /* mac addr check */
5910 if (!is_multicast_ether_addr(addr)) {
5911 dev_dbg(&hdev->pdev->dev,
5912 "Remove mc mac err! invalid mac:%pM.\n",
5913 addr);
5914 return -EINVAL;
5915 }
5916
5917 memset(&req, 0, sizeof(req));
e4e87715
PL		 5918 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5919 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5920 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
fd5f9da3 5921 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 5922 hclge_prepare_mac_addr(&req, addr);
5923 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5924 if (!status) {
5925 /* This mac addr exist, remove this handle's VFID for it */
5926 hclge_update_desc_vfid(desc, vport->vport_id, true);
5927
5928 if (hclge_is_all_function_id_zero(desc))
5929 /* All the vfid is zero, so need to delete this entry */
5930 status = hclge_remove_mac_vlan_tbl(vport, &req);
5931 else
5932 /* Not all the vfid is zero, update the vfid */
5933 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5934
5935 } else {
40cca1c5
XW		 5936 /* Maybe this mac address is in mta table, but it cannot be
5937 * deleted here because an entry of mta represents an address
5938 * range rather than a specific address. the delete action to
5939 * all entries will take effect in update_mta_status called by
5940 * hns3_nic_set_rx_mode.
5941 */
5942 status = 0;
46a3df9f
S		 5943 }
5944
46a3df9f
S		 5945 return status;
5946}
5947
f5aac71c
FL		 5948static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
5949 u16 cmdq_resp, u8 resp_code)
5950{
5951#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
5952#define HCLGE_ETHERTYPE_ALREADY_ADD 1
5953#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
5954#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
5955
5956 int return_status;
5957
5958 if (cmdq_resp) {
5959 dev_err(&hdev->pdev->dev,
5960 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
5961 cmdq_resp);
5962 return -EIO;
5963 }
5964
5965 switch (resp_code) {
5966 case HCLGE_ETHERTYPE_SUCCESS_ADD:
5967 case HCLGE_ETHERTYPE_ALREADY_ADD:
5968 return_status = 0;
5969 break;
5970 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
5971 dev_err(&hdev->pdev->dev,
5972 "add mac ethertype failed for manager table overflow.\n");
5973 return_status = -EIO;
5974 break;
5975 case HCLGE_ETHERTYPE_KEY_CONFLICT:
5976 dev_err(&hdev->pdev->dev,
5977 "add mac ethertype failed for key conflict.\n");
5978 return_status = -EIO;
5979 break;
5980 default:
5981 dev_err(&hdev->pdev->dev,
5982 "add mac ethertype failed for undefined, code=%d.\n",
5983 resp_code);
5984 return_status = -EIO;
5985 }
5986
5987 return return_status;
5988}
5989
5990static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
5991 const struct hclge_mac_mgr_tbl_entry_cmd *req)
5992{
5993 struct hclge_desc desc;
5994 u8 resp_code;
5995 u16 retval;
5996 int ret;
5997
5998 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
5999 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
6000
6001 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6002 if (ret) {
6003 dev_err(&hdev->pdev->dev,
6004 "add mac ethertype failed for cmd_send, ret =%d.\n",
6005 ret);
6006 return ret;
6007 }
6008
6009 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
6010 retval = le16_to_cpu(desc.retval);
6011
6012 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
6013}
6014
6015static int init_mgr_tbl(struct hclge_dev *hdev)
6016{
6017 int ret;
6018 int i;
6019
6020 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
6021 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
6022 if (ret) {
6023 dev_err(&hdev->pdev->dev,
6024 "add mac ethertype failed, ret =%d.\n",
6025 ret);
6026 return ret;
6027 }
6028 }
6029
6030 return 0;
6031}
6032
46a3df9f
S		 6033static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
6034{
6035 struct hclge_vport *vport = hclge_get_vport(handle);
6036 struct hclge_dev *hdev = vport->back;
6037
6038 ether_addr_copy(p, hdev->hw.mac.mac_addr);
6039}
6040
59098055
FL		 6041static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
6042 bool is_first)
46a3df9f
S		 6043{
6044 const unsigned char *new_addr = (const unsigned char *)p;
6045 struct hclge_vport *vport = hclge_get_vport(handle);
6046 struct hclge_dev *hdev = vport->back;
18838d0c 6047 int ret;
46a3df9f
S		 6048
6049 /* mac addr check */
6050 if (is_zero_ether_addr(new_addr) ||
6051 is_broadcast_ether_addr(new_addr) ||
6052 is_multicast_ether_addr(new_addr)) {
6053 dev_err(&hdev->pdev->dev,
6054 "Change uc mac err! invalid mac:%p.\n",
6055 new_addr);
6056 return -EINVAL;
6057 }
6058
59098055 6059 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 6060 dev_warn(&hdev->pdev->dev,
59098055 6061 "remove old uc mac address fail.\n");
46a3df9f 6062
18838d0c
FL		 6063 ret = hclge_add_uc_addr(handle, new_addr);
6064 if (ret) {
6065 dev_err(&hdev->pdev->dev,
6066 "add uc mac address fail, ret =%d.\n",
6067 ret);
6068
59098055
FL		 6069 if (!is_first &&
6070 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 6071 dev_err(&hdev->pdev->dev,
59098055 6072 "restore uc mac address fail.\n");
18838d0c
FL		 6073
6074 return -EIO;
46a3df9f
S		 6075 }
6076
e98d7183 6077 ret = hclge_pause_addr_cfg(hdev, new_addr);
18838d0c
FL		 6078 if (ret) {
6079 dev_err(&hdev->pdev->dev,
6080 "configure mac pause address fail, ret =%d.\n",
6081 ret);
6082 return -EIO;
6083 }
6084
6085 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
6086
6087 return 0;
46a3df9f
S		 6088}
6089
26483246
XW		 6090static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
6091 int cmd)
6092{
6093 struct hclge_vport *vport = hclge_get_vport(handle);
6094 struct hclge_dev *hdev = vport->back;
6095
6096 if (!hdev->hw.mac.phydev)
6097 return -EOPNOTSUPP;
6098
6099 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
6100}
6101
46a3df9f 6102static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
64d114f0 6103 u8 fe_type, bool filter_en)
46a3df9f 6104{
d44f9b63 6105 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 6106 struct hclge_desc desc;
6107 int ret;
6108
6109 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
6110
d44f9b63 6111 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f 6112 req->vlan_type = vlan_type;
64d114f0 6113 req->vlan_fe = filter_en ? fe_type : 0;
46a3df9f
S		 6114
6115 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 6116 if (ret)
46a3df9f
S		 6117 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
6118 ret);
46a3df9f 6119
3f639907 6120 return ret;
46a3df9f
S		 6121}
6122
391b5e93
JS		 6123#define HCLGE_FILTER_TYPE_VF 0
6124#define HCLGE_FILTER_TYPE_PORT 1
64d114f0
ZL		 6125#define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0)
6126#define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0)
6127#define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1)
6128#define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2)
6129#define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3)
6130#define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \
6131 | HCLGE_FILTER_FE_ROCE_EGRESS_B)
6132#define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \
6133 | HCLGE_FILTER_FE_ROCE_INGRESS_B)
391b5e93
JS		 6134
6135static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
6136{
6137 struct hclge_vport *vport = hclge_get_vport(handle);
6138 struct hclge_dev *hdev = vport->back;
6139
64d114f0
ZL		 6140 if (hdev->pdev->revision >= 0x21) {
6141 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6142 HCLGE_FILTER_FE_EGRESS, enable);
6143 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
6144 HCLGE_FILTER_FE_INGRESS, enable);
6145 } else {
6146 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6147 HCLGE_FILTER_FE_EGRESS_V1_B, enable);
6148 }
c60edc17
JS		 6149 if (enable)
6150 handle->netdev_flags |= HNAE3_VLAN_FLTR;
6151 else
6152 handle->netdev_flags &= ~HNAE3_VLAN_FLTR;
391b5e93
JS		 6153}
6154
dc8131d8
YL		 6155static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
6156 bool is_kill, u16 vlan, u8 qos,
6157 __be16 proto)
46a3df9f
S		 6158{
6159#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 6160 struct hclge_vlan_filter_vf_cfg_cmd *req0;
6161 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 6162 struct hclge_desc desc[2];
6163 u8 vf_byte_val;
6164 u8 vf_byte_off;
6165 int ret;
6166
6167 hclge_cmd_setup_basic_desc(&desc[0],
6168 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
6169 hclge_cmd_setup_basic_desc(&desc[1],
6170 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
6171
6172 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
6173
6174 vf_byte_off = vfid / 8;
6175 vf_byte_val = 1 << (vfid % 8);
6176
d44f9b63
YL		 6177 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
6178 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 6179
a90bb9a5 6180 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 6181 req0->vlan_cfg = is_kill;
6182
6183 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
6184 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
6185 else
6186 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
6187
6188 ret = hclge_cmd_send(&hdev->hw, desc, 2);
6189 if (ret) {
6190 dev_err(&hdev->pdev->dev,
6191 "Send vf vlan command fail, ret =%d.\n",
6192 ret);
6193 return ret;
6194 }
6195
6196 if (!is_kill) {
6c251711 6197#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 6198 if (!req0->resp_code || req0->resp_code == 1)
6199 return 0;
6200
6c251711
YL		 6201 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
6202 dev_warn(&hdev->pdev->dev,
6203 "vf vlan table is full, vf vlan filter is disabled\n");
6204 return 0;
6205 }
6206
46a3df9f
S		 6207 dev_err(&hdev->pdev->dev,
6208 "Add vf vlan filter fail, ret =%d.\n",
6209 req0->resp_code);
6210 } else {
41dafea2 6211#define HCLGE_VF_VLAN_DEL_NO_FOUND 1
46a3df9f
S		 6212 if (!req0->resp_code)
6213 return 0;
6214
41dafea2
YL		 6215 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
6216 dev_warn(&hdev->pdev->dev,
6217 "vlan %d filter is not in vf vlan table\n",
6218 vlan);
6219 return 0;
6220 }
6221
46a3df9f
S		 6222 dev_err(&hdev->pdev->dev,
6223 "Kill vf vlan filter fail, ret =%d.\n",
6224 req0->resp_code);
6225 }
6226
6227 return -EIO;
6228}
6229
dc8131d8
YL		 6230static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
6231 u16 vlan_id, bool is_kill)
46a3df9f 6232{
d44f9b63 6233 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 6234 struct hclge_desc desc;
6235 u8 vlan_offset_byte_val;
6236 u8 vlan_offset_byte;
6237 u8 vlan_offset_160;
6238 int ret;
6239
6240 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
6241
6242 vlan_offset_160 = vlan_id / 160;
6243 vlan_offset_byte = (vlan_id % 160) / 8;
6244 vlan_offset_byte_val = 1 << (vlan_id % 8);
6245
d44f9b63 6246 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 6247 req->vlan_offset = vlan_offset_160;
6248 req->vlan_cfg = is_kill;
6249 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
6250
6251 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
dc8131d8
YL		 6252 if (ret)
6253 dev_err(&hdev->pdev->dev,
6254 "port vlan command, send fail, ret =%d.\n", ret);
6255 return ret;
6256}
6257
6258static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
6259 u16 vport_id, u16 vlan_id, u8 qos,
6260 bool is_kill)
6261{
6262 u16 vport_idx, vport_num = 0;
6263 int ret;
6264
daaa8521
YL		 6265 if (is_kill && !vlan_id)
6266 return 0;
6267
dc8131d8
YL		 6268 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
6269 0, proto);
46a3df9f
S		 6270 if (ret) {
6271 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 6272 "Set %d vport vlan filter config fail, ret =%d.\n",
6273 vport_id, ret);
46a3df9f
S		 6274 return ret;
6275 }
6276
dc8131d8
YL		 6277 /* vlan 0 may be added twice when 8021q module is enabled */
6278 if (!is_kill && !vlan_id &&
6279 test_bit(vport_id, hdev->vlan_table[vlan_id]))
6280 return 0;
6281
6282 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 6283 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 6284 "Add port vlan failed, vport %d is already in vlan %d\n",
6285 vport_id, vlan_id);
6286 return -EINVAL;
46a3df9f
S		 6287 }
6288
dc8131d8
YL		 6289 if (is_kill &&
6290 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
6291 dev_err(&hdev->pdev->dev,
6292 "Delete port vlan failed, vport %d is not in vlan %d\n",
6293 vport_id, vlan_id);
6294 return -EINVAL;
6295 }
6296
54e97d11 6297 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
dc8131d8
YL		 6298 vport_num++;
6299
6300 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
6301 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
6302 is_kill);
6303
6304 return ret;
6305}
6306
6307int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
6308 u16 vlan_id, bool is_kill)
6309{
6310 struct hclge_vport *vport = hclge_get_vport(handle);
6311 struct hclge_dev *hdev = vport->back;
6312
6313 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
6314 0, is_kill);
46a3df9f
S		 6315}
6316
6317static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
6318 u16 vlan, u8 qos, __be16 proto)
6319{
6320 struct hclge_vport *vport = hclge_get_vport(handle);
6321 struct hclge_dev *hdev = vport->back;
6322
6323 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
6324 return -EINVAL;
6325 if (proto != htons(ETH_P_8021Q))
6326 return -EPROTONOSUPPORT;
6327
dc8131d8 6328 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 6329}
6330
5f6ea83f
PL		 6331static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
6332{
6333 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
6334 struct hclge_vport_vtag_tx_cfg_cmd *req;
6335 struct hclge_dev *hdev = vport->back;
6336 struct hclge_desc desc;
6337 int status;
6338
6339 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
6340
6341 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
6342 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
6343 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
e4e87715
PL		 6344 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
6345 vcfg->accept_tag1 ? 1 : 0);
6346 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
6347 vcfg->accept_untag1 ? 1 : 0);
6348 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
6349 vcfg->accept_tag2 ? 1 : 0);
6350 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
6351 vcfg->accept_untag2 ? 1 : 0);
6352 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
6353 vcfg->insert_tag1_en ? 1 : 0);
6354 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
6355 vcfg->insert_tag2_en ? 1 : 0);
6356 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
5f6ea83f
PL		 6357
6358 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6359 req->vf_bitmap[req->vf_offset] =
6360 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6361
6362 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6363 if (status)
6364 dev_err(&hdev->pdev->dev,
6365 "Send port txvlan cfg command fail, ret =%d\n",
6366 status);
6367
6368 return status;
6369}
6370
6371static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
6372{
6373 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
6374 struct hclge_vport_vtag_rx_cfg_cmd *req;
6375 struct hclge_dev *hdev = vport->back;
6376 struct hclge_desc desc;
6377 int status;
6378
6379 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
6380
6381 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
e4e87715
PL		 6382 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
6383 vcfg->strip_tag1_en ? 1 : 0);
6384 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
6385 vcfg->strip_tag2_en ? 1 : 0);
6386 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
6387 vcfg->vlan1_vlan_prionly ? 1 : 0);
6388 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
6389 vcfg->vlan2_vlan_prionly ? 1 : 0);
5f6ea83f
PL		 6390
6391 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6392 req->vf_bitmap[req->vf_offset] =
6393 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6394
6395 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6396 if (status)
6397 dev_err(&hdev->pdev->dev,
6398 "Send port rxvlan cfg command fail, ret =%d\n",
6399 status);
6400
6401 return status;
6402}
6403
6404static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
6405{
6406 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
6407 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
6408 struct hclge_desc desc;
6409 int status;
6410
6411 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
6412 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
6413 rx_req->ot_fst_vlan_type =
6414 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
6415 rx_req->ot_sec_vlan_type =
6416 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
6417 rx_req->in_fst_vlan_type =
6418 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
6419 rx_req->in_sec_vlan_type =
6420 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
6421
6422 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6423 if (status) {
6424 dev_err(&hdev->pdev->dev,
6425 "Send rxvlan protocol type command fail, ret =%d\n",
6426 status);
6427 return status;
6428 }
6429
6430 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
6431
d0d72bac 6432 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
5f6ea83f
PL		 6433 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
6434 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
6435
6436 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6437 if (status)
6438 dev_err(&hdev->pdev->dev,
6439 "Send txvlan protocol type command fail, ret =%d\n",
6440 status);
6441
6442 return status;
6443}
6444
46a3df9f
S		 6445static int hclge_init_vlan_config(struct hclge_dev *hdev)
6446{
5f6ea83f
PL		 6447#define HCLGE_DEF_VLAN_TYPE 0x8100
6448
c60edc17 6449 struct hnae3_handle *handle = &hdev->vport[0].nic;
5f6ea83f 6450 struct hclge_vport *vport;
46a3df9f 6451 int ret;
5f6ea83f
PL		 6452 int i;
6453
64d114f0
ZL		 6454 if (hdev->pdev->revision >= 0x21) {
6455 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6456 HCLGE_FILTER_FE_EGRESS, true);
6457 if (ret)
6458 return ret;
46a3df9f 6459
64d114f0
ZL		 6460 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
6461 HCLGE_FILTER_FE_INGRESS, true);
6462 if (ret)
6463 return ret;
6464 } else {
6465 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6466 HCLGE_FILTER_FE_EGRESS_V1_B,
6467 true);
6468 if (ret)
6469 return ret;
6470 }
46a3df9f 6471
c60edc17
JS		 6472 handle->netdev_flags |= HNAE3_VLAN_FLTR;
6473
5f6ea83f
PL		 6474 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6475 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6476 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6477 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6478 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
6479 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
6480
6481 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 6482 if (ret)
6483 return ret;
46a3df9f 6484
5f6ea83f
PL		 6485 for (i = 0; i < hdev->num_alloc_vport; i++) {
6486 vport = &hdev->vport[i];
dcb35cce
PL		 6487 vport->txvlan_cfg.accept_tag1 = true;
6488 vport->txvlan_cfg.accept_untag1 = true;
6489
6490 /* accept_tag2 and accept_untag2 are not supported on
6491 * pdev revision(0x20), new revision support them. The
6492 * value of this two fields will not return error when driver
6493 * send command to fireware in revision(0x20).
6494 * This two fields can not configured by user.
6495 */
6496 vport->txvlan_cfg.accept_tag2 = true;
6497 vport->txvlan_cfg.accept_untag2 = true;
6498
5f6ea83f
PL		 6499 vport->txvlan_cfg.insert_tag1_en = false;
6500 vport->txvlan_cfg.insert_tag2_en = false;
6501 vport->txvlan_cfg.default_tag1 = 0;
6502 vport->txvlan_cfg.default_tag2 = 0;
6503
6504 ret = hclge_set_vlan_tx_offload_cfg(vport);
6505 if (ret)
6506 return ret;
6507
6508 vport->rxvlan_cfg.strip_tag1_en = false;
6509 vport->rxvlan_cfg.strip_tag2_en = true;
6510 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6511 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6512
6513 ret = hclge_set_vlan_rx_offload_cfg(vport);
6514 if (ret)
6515 return ret;
6516 }
6517
dc8131d8 6518 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 6519}
6520
b2641e2a 6521int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
052ece6d
PL		 6522{
6523 struct hclge_vport *vport = hclge_get_vport(handle);
6524
6525 vport->rxvlan_cfg.strip_tag1_en = false;
6526 vport->rxvlan_cfg.strip_tag2_en = enable;
6527 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6528 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6529
6530 return hclge_set_vlan_rx_offload_cfg(vport);
6531}
6532
e6d7d79d 6533static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps)
46a3df9f 6534{
d44f9b63 6535 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 6536 struct hclge_desc desc;
46a3df9f 6537
46a3df9f
S		 6538 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
6539
d44f9b63 6540 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
e6d7d79d 6541 req->max_frm_size = cpu_to_le16(new_mps);
8fc7346c 6542 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
46a3df9f 6543
e6d7d79d 6544 return hclge_cmd_send(&hdev->hw, &desc, 1);
46a3df9f
S		 6545}
6546
dd72140c
FL		 6547static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
6548{
6549 struct hclge_vport *vport = hclge_get_vport(handle);
818f1675
YL		 6550
6551 return hclge_set_vport_mtu(vport, new_mtu);
6552}
6553
6554int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu)
6555{
dd72140c 6556 struct hclge_dev *hdev = vport->back;
818f1675 6557 int i, max_frm_size, ret = 0;
dd72140c 6558
e6d7d79d
YL		 6559 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
6560 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
6561 max_frm_size > HCLGE_MAC_MAX_FRAME)
6562 return -EINVAL;
6563
818f1675
YL		 6564 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
6565 mutex_lock(&hdev->vport_lock);
6566 /* VF's mps must fit within hdev->mps */
6567 if (vport->vport_id && max_frm_size > hdev->mps) {
6568 mutex_unlock(&hdev->vport_lock);
6569 return -EINVAL;
6570 } else if (vport->vport_id) {
6571 vport->mps = max_frm_size;
6572 mutex_unlock(&hdev->vport_lock);
6573 return 0;
6574 }
6575
6576 /* PF's mps must be greater then VF's mps */
6577 for (i = 1; i < hdev->num_alloc_vport; i++)
6578 if (max_frm_size < hdev->vport[i].mps) {
6579 mutex_unlock(&hdev->vport_lock);
6580 return -EINVAL;
6581 }
6582
cdca4c48
YL		 6583 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
6584
e6d7d79d 6585 ret = hclge_set_mac_mtu(hdev, max_frm_size);
dd72140c
FL		 6586 if (ret) {
6587 dev_err(&hdev->pdev->dev,
6588 "Change mtu fail, ret =%d\n", ret);
818f1675 6589 goto out;
dd72140c
FL		 6590 }
6591
e6d7d79d 6592 hdev->mps = max_frm_size;
818f1675 6593 vport->mps = max_frm_size;
e6d7d79d 6594
dd72140c
FL		 6595 ret = hclge_buffer_alloc(hdev);
6596 if (ret)
6597 dev_err(&hdev->pdev->dev,
6598 "Allocate buffer fail, ret =%d\n", ret);
6599
818f1675 6600out:
cdca4c48 6601 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
818f1675 6602 mutex_unlock(&hdev->vport_lock);
dd72140c
FL		 6603 return ret;
6604}
6605
46a3df9f
S		 6606static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
6607 bool enable)
6608{
d44f9b63 6609 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 6610 struct hclge_desc desc;
6611 int ret;
6612
6613 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
6614
d44f9b63 6615 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 6616 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
e4e87715 6617 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 6618
6619 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6620 if (ret) {
6621 dev_err(&hdev->pdev->dev,
6622 "Send tqp reset cmd error, status =%d\n", ret);
6623 return ret;
6624 }
6625
6626 return 0;
6627}
6628
6629static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
6630{
d44f9b63 6631 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 6632 struct hclge_desc desc;
6633 int ret;
6634
6635 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
6636
d44f9b63 6637 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 6638 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6639
6640 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6641 if (ret) {
6642 dev_err(&hdev->pdev->dev,
6643 "Get reset status error, status =%d\n", ret);
6644 return ret;
6645 }
6646
e4e87715 6647 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 6648}
6649
0c29d191 6650u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id)
814e0274
PL		 6651{
6652 struct hnae3_queue *queue;
6653 struct hclge_tqp *tqp;
6654
6655 queue = handle->kinfo.tqp[queue_id];
6656 tqp = container_of(queue, struct hclge_tqp, q);
6657
6658 return tqp->index;
6659}
6660
7fa6be4f 6661int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 6662{
6663 struct hclge_vport *vport = hclge_get_vport(handle);
6664 struct hclge_dev *hdev = vport->back;
6665 int reset_try_times = 0;
6666 int reset_status;
814e0274 6667 u16 queue_gid;
7fa6be4f 6668 int ret = 0;
46a3df9f 6669
814e0274
PL		 6670 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
6671
46a3df9f
S		 6672 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
6673 if (ret) {
7fa6be4f
HT		 6674 dev_err(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
6675 return ret;
46a3df9f
S		 6676 }
6677
814e0274 6678 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f 6679 if (ret) {
7fa6be4f
HT		 6680 dev_err(&hdev->pdev->dev,
6681 "Send reset tqp cmd fail, ret = %d\n", ret);
6682 return ret;
46a3df9f
S		 6683 }
6684
6685 reset_try_times = 0;
6686 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6687 /* Wait for tqp hw reset */
6688 msleep(20);
814e0274 6689 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 6690 if (reset_status)
6691 break;
6692 }
6693
6694 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
7fa6be4f
HT		 6695 dev_err(&hdev->pdev->dev, "Reset TQP fail\n");
6696 return ret;
46a3df9f
S		 6697 }
6698
814e0274 6699 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
7fa6be4f
HT		 6700 if (ret)
6701 dev_err(&hdev->pdev->dev,
6702 "Deassert the soft reset fail, ret = %d\n", ret);
6703
6704 return ret;
46a3df9f
S		 6705}
6706
1a426f8b
PL		 6707void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
6708{
6709 struct hclge_dev *hdev = vport->back;
6710 int reset_try_times = 0;
6711 int reset_status;
6712 u16 queue_gid;
6713 int ret;
6714
6715 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
6716
6717 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6718 if (ret) {
6719 dev_warn(&hdev->pdev->dev,
6720 "Send reset tqp cmd fail, ret = %d\n", ret);
6721 return;
6722 }
6723
6724 reset_try_times = 0;
6725 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6726 /* Wait for tqp hw reset */
6727 msleep(20);
6728 reset_status = hclge_get_reset_status(hdev, queue_gid);
6729 if (reset_status)
6730 break;
6731 }
6732
6733 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6734 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
6735 return;
6736 }
6737
6738 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6739 if (ret)
6740 dev_warn(&hdev->pdev->dev,
6741 "Deassert the soft reset fail, ret = %d\n", ret);
6742}
6743
46a3df9f
S		 6744static u32 hclge_get_fw_version(struct hnae3_handle *handle)
6745{
6746 struct hclge_vport *vport = hclge_get_vport(handle);
6747 struct hclge_dev *hdev = vport->back;
6748
6749 return hdev->fw_version;
6750}
6751
61387774
PL		 6752static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6753{
6754 struct phy_device *phydev = hdev->hw.mac.phydev;
6755
6756 if (!phydev)
6757 return;
6758
70814e81 6759 phy_set_asym_pause(phydev, rx_en, tx_en);
61387774
PL		 6760}
6761
6762static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6763{
61387774
PL		 6764 int ret;
6765
6766 if (rx_en && tx_en)
40173a2e 6767 hdev->fc_mode_last_time = HCLGE_FC_FULL;
61387774 6768 else if (rx_en && !tx_en)
40173a2e 6769 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
61387774 6770 else if (!rx_en && tx_en)
40173a2e 6771 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
61387774 6772 else
40173a2e 6773 hdev->fc_mode_last_time = HCLGE_FC_NONE;
61387774 6774
40173a2e 6775 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
61387774 6776 return 0;
61387774
PL		 6777
6778 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
6779 if (ret) {
6780 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
6781 ret);
6782 return ret;
6783 }
6784
40173a2e 6785 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
61387774
PL		 6786
6787 return 0;
6788}
6789
1770a7a3
PL		 6790int hclge_cfg_flowctrl(struct hclge_dev *hdev)
6791{
6792 struct phy_device *phydev = hdev->hw.mac.phydev;
6793 u16 remote_advertising = 0;
6794 u16 local_advertising = 0;
6795 u32 rx_pause, tx_pause;
6796 u8 flowctl;
6797
6798 if (!phydev->link || !phydev->autoneg)
6799 return 0;
6800
3c1bcc86 6801 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising);
1770a7a3
PL		 6802
6803 if (phydev->pause)
6804 remote_advertising = LPA_PAUSE_CAP;
6805
6806 if (phydev->asym_pause)
6807 remote_advertising |= LPA_PAUSE_ASYM;
6808
6809 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
6810 remote_advertising);
6811 tx_pause = flowctl & FLOW_CTRL_TX;
6812 rx_pause = flowctl & FLOW_CTRL_RX;
6813
6814 if (phydev->duplex == HCLGE_MAC_HALF) {
6815 tx_pause = 0;
6816 rx_pause = 0;
6817 }
6818
6819 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
6820}
6821
46a3df9f
S		 6822static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
6823 u32 *rx_en, u32 *tx_en)
6824{
6825 struct hclge_vport *vport = hclge_get_vport(handle);
6826 struct hclge_dev *hdev = vport->back;
6827
6828 *auto_neg = hclge_get_autoneg(handle);
6829
6830 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6831 *rx_en = 0;
6832 *tx_en = 0;
6833 return;
6834 }
6835
6836 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
6837 *rx_en = 1;
6838 *tx_en = 0;
6839 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
6840 *tx_en = 1;
6841 *rx_en = 0;
6842 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
6843 *rx_en = 1;
6844 *tx_en = 1;
6845 } else {
6846 *rx_en = 0;
6847 *tx_en = 0;
6848 }
6849}
6850
61387774
PL		 6851static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
6852 u32 rx_en, u32 tx_en)
6853{
6854 struct hclge_vport *vport = hclge_get_vport(handle);
6855 struct hclge_dev *hdev = vport->back;
6856 struct phy_device *phydev = hdev->hw.mac.phydev;
6857 u32 fc_autoneg;
6858
61387774
PL		 6859 fc_autoneg = hclge_get_autoneg(handle);
6860 if (auto_neg != fc_autoneg) {
6861 dev_info(&hdev->pdev->dev,
6862 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
6863 return -EOPNOTSUPP;
6864 }
6865
6866 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6867 dev_info(&hdev->pdev->dev,
6868 "Priority flow control enabled. Cannot set link flow control.\n");
6869 return -EOPNOTSUPP;
6870 }
6871
6872 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
6873
6874 if (!fc_autoneg)
6875 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
6876
0c963e8c
FL		 6877 /* Only support flow control negotiation for netdev with
6878 * phy attached for now.
6879 */
6880 if (!phydev)
6881 return -EOPNOTSUPP;
6882
61387774
PL		 6883 return phy_start_aneg(phydev);
6884}
6885
46a3df9f
S		 6886static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
6887 u8 *auto_neg, u32 *speed, u8 *duplex)
6888{
6889 struct hclge_vport *vport = hclge_get_vport(handle);
6890 struct hclge_dev *hdev = vport->back;
6891
6892 if (speed)
6893 *speed = hdev->hw.mac.speed;
6894 if (duplex)
6895 *duplex = hdev->hw.mac.duplex;
6896 if (auto_neg)
6897 *auto_neg = hdev->hw.mac.autoneg;
6898}
6899
6900static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
6901{
6902 struct hclge_vport *vport = hclge_get_vport(handle);
6903 struct hclge_dev *hdev = vport->back;
6904
6905 if (media_type)
6906 *media_type = hdev->hw.mac.media_type;
6907}
6908
6909static void hclge_get_mdix_mode(struct hnae3_handle *handle,
6910 u8 *tp_mdix_ctrl, u8 *tp_mdix)
6911{
6912 struct hclge_vport *vport = hclge_get_vport(handle);
6913 struct hclge_dev *hdev = vport->back;
6914 struct phy_device *phydev = hdev->hw.mac.phydev;
6915 int mdix_ctrl, mdix, retval, is_resolved;
6916
6917 if (!phydev) {
6918 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6919 *tp_mdix = ETH_TP_MDI_INVALID;
6920 return;
6921 }
6922
6923 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
6924
6925 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
e4e87715
PL		 6926 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
6927 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 6928
6929 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
e4e87715
PL		 6930 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
6931 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 6932
6933 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
6934
6935 switch (mdix_ctrl) {
6936 case 0x0:
6937 *tp_mdix_ctrl = ETH_TP_MDI;
6938 break;
6939 case 0x1:
6940 *tp_mdix_ctrl = ETH_TP_MDI_X;
6941 break;
6942 case 0x3:
6943 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
6944 break;
6945 default:
6946 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6947 break;
6948 }
6949
6950 if (!is_resolved)
6951 *tp_mdix = ETH_TP_MDI_INVALID;
6952 else if (mdix)
6953 *tp_mdix = ETH_TP_MDI_X;
6954 else
6955 *tp_mdix = ETH_TP_MDI;
6956}
6957
b01b7cf1
FL		 6958static int hclge_init_instance_hw(struct hclge_dev *hdev)
6959{
6960 return hclge_mac_connect_phy(hdev);
6961}
6962
6963static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
6964{
6965 hclge_mac_disconnect_phy(hdev);
6966}
6967
46a3df9f
S		 6968static int hclge_init_client_instance(struct hnae3_client *client,
6969 struct hnae3_ae_dev *ae_dev)
6970{
6971 struct hclge_dev *hdev = ae_dev->priv;
6972 struct hclge_vport *vport;
6973 int i, ret;
6974
6975 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
6976 vport = &hdev->vport[i];
6977
6978 switch (client->type) {
6979 case HNAE3_CLIENT_KNIC:
6980
6981 hdev->nic_client = client;
6982 vport->nic.client = client;
6983 ret = client->ops->init_instance(&vport->nic);
6984 if (ret)
49dd8054 6985 goto clear_nic;
46a3df9f 6986
b01b7cf1
FL		 6987 ret = hclge_init_instance_hw(hdev);
6988 if (ret) {
6989 client->ops->uninit_instance(&vport->nic,
6990 0);
49dd8054 6991 goto clear_nic;
b01b7cf1
FL		 6992 }
6993
d9f28fc2
JS		 6994 hnae3_set_client_init_flag(client, ae_dev, 1);
6995
46a3df9f 6996 if (hdev->roce_client &&
e92a0843 6997 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 6998 struct hnae3_client *rc = hdev->roce_client;
6999
7000 ret = hclge_init_roce_base_info(vport);
7001 if (ret)
49dd8054 7002 goto clear_roce;
46a3df9f
S		 7003
7004 ret = rc->ops->init_instance(&vport->roce);
7005 if (ret)
49dd8054 7006 goto clear_roce;
d9f28fc2
JS		 7007
7008 hnae3_set_client_init_flag(hdev->roce_client,
7009 ae_dev, 1);
46a3df9f
S		 7010 }
7011
7012 break;
7013 case HNAE3_CLIENT_UNIC:
7014 hdev->nic_client = client;
7015 vport->nic.client = client;
7016
7017 ret = client->ops->init_instance(&vport->nic);
7018 if (ret)
49dd8054 7019 goto clear_nic;
46a3df9f 7020
d9f28fc2
JS		 7021 hnae3_set_client_init_flag(client, ae_dev, 1);
7022
46a3df9f
S		 7023 break;
7024 case HNAE3_CLIENT_ROCE:
e92a0843 7025 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 7026 hdev->roce_client = client;
7027 vport->roce.client = client;
7028 }
7029
3a46f34d 7030 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 7031 ret = hclge_init_roce_base_info(vport);
7032 if (ret)
49dd8054 7033 goto clear_roce;
46a3df9f
S		 7034
7035 ret = client->ops->init_instance(&vport->roce);
7036 if (ret)
49dd8054 7037 goto clear_roce;
d9f28fc2
JS		 7038
7039 hnae3_set_client_init_flag(client, ae_dev, 1);
46a3df9f 7040 }
fa7a4bd5
JS		 7041
7042 break;
7043 default:
7044 return -EINVAL;
46a3df9f
S		 7045 }
7046 }
7047
7048 return 0;
49dd8054
JS		 7049
7050clear_nic:
7051 hdev->nic_client = NULL;
7052 vport->nic.client = NULL;
7053 return ret;
7054clear_roce:
7055 hdev->roce_client = NULL;
7056 vport->roce.client = NULL;
7057 return ret;
46a3df9f
S		 7058}
7059
7060static void hclge_uninit_client_instance(struct hnae3_client *client,
7061 struct hnae3_ae_dev *ae_dev)
7062{
7063 struct hclge_dev *hdev = ae_dev->priv;
7064 struct hclge_vport *vport;
7065 int i;
7066
7067 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
7068 vport = &hdev->vport[i];
a17dcf3f 7069 if (hdev->roce_client) {
46a3df9f
S		 7070 hdev->roce_client->ops->uninit_instance(&vport->roce,
7071 0);
a17dcf3f
L		 7072 hdev->roce_client = NULL;
7073 vport->roce.client = NULL;
7074 }
46a3df9f
S		 7075 if (client->type == HNAE3_CLIENT_ROCE)
7076 return;
49dd8054 7077 if (hdev->nic_client && client->ops->uninit_instance) {
b01b7cf1 7078 hclge_uninit_instance_hw(hdev);
46a3df9f 7079 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 7080 hdev->nic_client = NULL;
7081 vport->nic.client = NULL;
7082 }
46a3df9f
S		 7083 }
7084}
7085
7086static int hclge_pci_init(struct hclge_dev *hdev)
7087{
7088 struct pci_dev *pdev = hdev->pdev;
7089 struct hclge_hw *hw;
7090 int ret;
7091
7092 ret = pci_enable_device(pdev);
7093 if (ret) {
7094 dev_err(&pdev->dev, "failed to enable PCI device\n");
3e249d3b 7095 return ret;
46a3df9f
S		 7096 }
7097
7098 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7099 if (ret) {
7100 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7101 if (ret) {
7102 dev_err(&pdev->dev,
7103 "can't set consistent PCI DMA");
7104 goto err_disable_device;
7105 }
7106 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
7107 }
7108
7109 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
7110 if (ret) {
7111 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
7112 goto err_disable_device;
7113 }
7114
7115 pci_set_master(pdev);
7116 hw = &hdev->hw;
46a3df9f
S		 7117 hw->io_base = pcim_iomap(pdev, 2, 0);
7118 if (!hw->io_base) {
7119 dev_err(&pdev->dev, "Can't map configuration register space\n");
7120 ret = -ENOMEM;
7121 goto err_clr_master;
7122 }
7123
709eb41a
L		 7124 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
7125
46a3df9f
S		 7126 return 0;
7127err_clr_master:
7128 pci_clear_master(pdev);
7129 pci_release_regions(pdev);
7130err_disable_device:
7131 pci_disable_device(pdev);
46a3df9f
S		 7132
7133 return ret;
7134}
7135
7136static void hclge_pci_uninit(struct hclge_dev *hdev)
7137{
7138 struct pci_dev *pdev = hdev->pdev;
7139
6a814413 7140 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 7141 pci_free_irq_vectors(pdev);
46a3df9f
S		 7142 pci_clear_master(pdev);
7143 pci_release_mem_regions(pdev);
7144 pci_disable_device(pdev);
7145}
7146
48569cda
PL		 7147static void hclge_state_init(struct hclge_dev *hdev)
7148{
7149 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
7150 set_bit(HCLGE_STATE_DOWN, &hdev->state);
7151 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
7152 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
7153 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
7154 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
7155}
7156
7157static void hclge_state_uninit(struct hclge_dev *hdev)
7158{
7159 set_bit(HCLGE_STATE_DOWN, &hdev->state);
7160
7161 if (hdev->service_timer.function)
7162 del_timer_sync(&hdev->service_timer);
65e41e7e
HT		 7163 if (hdev->reset_timer.function)
7164 del_timer_sync(&hdev->reset_timer);
48569cda
PL		 7165 if (hdev->service_task.func)
7166 cancel_work_sync(&hdev->service_task);
7167 if (hdev->rst_service_task.func)
7168 cancel_work_sync(&hdev->rst_service_task);
7169 if (hdev->mbx_service_task.func)
7170 cancel_work_sync(&hdev->mbx_service_task);
7171}
7172
6b9a97ee
HT		 7173static void hclge_flr_prepare(struct hnae3_ae_dev *ae_dev)
7174{
7175#define HCLGE_FLR_WAIT_MS 100
7176#define HCLGE_FLR_WAIT_CNT 50
7177 struct hclge_dev *hdev = ae_dev->priv;
7178 int cnt = 0;
7179
7180 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
7181 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state);
7182 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request);
7183 hclge_reset_event(hdev->pdev, NULL);
7184
7185 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) &&
7186 cnt++ < HCLGE_FLR_WAIT_CNT)
7187 msleep(HCLGE_FLR_WAIT_MS);
7188
7189 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state))
7190 dev_err(&hdev->pdev->dev,
7191 "flr wait down timeout: %d\n", cnt);
7192}
7193
7194static void hclge_flr_done(struct hnae3_ae_dev *ae_dev)
7195{
7196 struct hclge_dev *hdev = ae_dev->priv;
7197
7198 set_bit(HNAE3_FLR_DONE, &hdev->flr_state);
7199}
7200
46a3df9f
S		 7201static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
7202{
7203 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 7204 struct hclge_dev *hdev;
7205 int ret;
7206
7207 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
7208 if (!hdev) {
7209 ret = -ENOMEM;
ffd5656e 7210 goto out;
46a3df9f
S		 7211 }
7212
46a3df9f
S		 7213 hdev->pdev = pdev;
7214 hdev->ae_dev = ae_dev;
4ed340ab 7215 hdev->reset_type = HNAE3_NONE_RESET;
0742ed7c 7216 hdev->reset_level = HNAE3_FUNC_RESET;
46a3df9f 7217 ae_dev->priv = hdev;
e6d7d79d 7218 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
46a3df9f 7219
818f1675
YL		 7220 mutex_init(&hdev->vport_lock);
7221
46a3df9f
S		 7222 ret = hclge_pci_init(hdev);
7223 if (ret) {
7224 dev_err(&pdev->dev, "PCI init failed\n");
ffd5656e 7225 goto out;
46a3df9f
S		 7226 }
7227
3efb960f
L		 7228 /* Firmware command queue initialize */
7229 ret = hclge_cmd_queue_init(hdev);
7230 if (ret) {
7231 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
ffd5656e 7232 goto err_pci_uninit;
3efb960f
L		 7233 }
7234
7235 /* Firmware command initialize */
46a3df9f
S		 7236 ret = hclge_cmd_init(hdev);
7237 if (ret)
ffd5656e 7238 goto err_cmd_uninit;
46a3df9f
S		 7239
7240 ret = hclge_get_cap(hdev);
7241 if (ret) {
e00e2197
CIK		 7242 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
7243 ret);
ffd5656e 7244 goto err_cmd_uninit;
46a3df9f
S		 7245 }
7246
7247 ret = hclge_configure(hdev);
7248 if (ret) {
7249 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
ffd5656e 7250 goto err_cmd_uninit;
46a3df9f
S		 7251 }
7252
887c3820 7253 ret = hclge_init_msi(hdev);
46a3df9f 7254 if (ret) {
887c3820 7255 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
ffd5656e 7256 goto err_cmd_uninit;
46a3df9f
S		 7257 }
7258
466b0c00
L		 7259 ret = hclge_misc_irq_init(hdev);
7260 if (ret) {
7261 dev_err(&pdev->dev,
7262 "Misc IRQ(vector0) init error, ret = %d.\n",
7263 ret);
ffd5656e 7264 goto err_msi_uninit;
466b0c00
L		 7265 }
7266
46a3df9f
S		 7267 ret = hclge_alloc_tqps(hdev);
7268 if (ret) {
7269 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
ffd5656e 7270 goto err_msi_irq_uninit;
46a3df9f
S		 7271 }
7272
7273 ret = hclge_alloc_vport(hdev);
7274 if (ret) {
7275 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
ffd5656e 7276 goto err_msi_irq_uninit;
46a3df9f
S		 7277 }
7278
7df7dad6
L		 7279 ret = hclge_map_tqp(hdev);
7280 if (ret) {
7281 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
2312e050 7282 goto err_msi_irq_uninit;
7df7dad6
L		 7283 }
7284
c5ef83cb
HT		 7285 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
7286 ret = hclge_mac_mdio_config(hdev);
7287 if (ret) {
7288 dev_err(&hdev->pdev->dev,
7289 "mdio config fail ret=%d\n", ret);
2312e050 7290 goto err_msi_irq_uninit;
c5ef83cb 7291 }
cf9cca2d 7292 }
7293
39932473
JS		 7294 ret = hclge_init_umv_space(hdev);
7295 if (ret) {
7296 dev_err(&pdev->dev, "umv space init error, ret=%d.\n", ret);
7297 goto err_msi_irq_uninit;
7298 }
7299
46a3df9f
S		 7300 ret = hclge_mac_init(hdev);
7301 if (ret) {
7302 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
ffd5656e 7303 goto err_mdiobus_unreg;
46a3df9f 7304 }
46a3df9f
S		 7305
7306 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7307 if (ret) {
7308 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
ffd5656e 7309 goto err_mdiobus_unreg;
46a3df9f
S		 7310 }
7311
b26a6fea
PL		 7312 ret = hclge_config_gro(hdev, true);
7313 if (ret)
7314 goto err_mdiobus_unreg;
7315
46a3df9f
S		 7316 ret = hclge_init_vlan_config(hdev);
7317 if (ret) {
7318 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
ffd5656e 7319 goto err_mdiobus_unreg;
46a3df9f
S		 7320 }
7321
7322 ret = hclge_tm_schd_init(hdev);
7323 if (ret) {
7324 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
ffd5656e 7325 goto err_mdiobus_unreg;
68ece54e
YL		 7326 }
7327
268f5dfa 7328 hclge_rss_init_cfg(hdev);
68ece54e
YL		 7329 ret = hclge_rss_init_hw(hdev);
7330 if (ret) {
7331 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
ffd5656e 7332 goto err_mdiobus_unreg;
46a3df9f
S		 7333 }
7334
f5aac71c
FL		 7335 ret = init_mgr_tbl(hdev);
7336 if (ret) {
7337 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
ffd5656e 7338 goto err_mdiobus_unreg;
f5aac71c
FL		 7339 }
7340
d695964d
JS		 7341 ret = hclge_init_fd_config(hdev);
7342 if (ret) {
7343 dev_err(&pdev->dev,
7344 "fd table init fail, ret=%d\n", ret);
7345 goto err_mdiobus_unreg;
7346 }
7347
99714195
SJ		 7348 ret = hclge_hw_error_set_state(hdev, true);
7349 if (ret) {
7350 dev_err(&pdev->dev,
f3fa4a94 7351 "fail(%d) to enable hw error interrupts\n", ret);
99714195
SJ		 7352 goto err_mdiobus_unreg;
7353 }
7354
cacde272
YL		 7355 hclge_dcb_ops_set(hdev);
7356
d039ef68 7357 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
65e41e7e 7358 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
46a3df9f 7359 INIT_WORK(&hdev->service_task, hclge_service_task);
cb1b9f77 7360 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
c1a81619 7361 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 7362
8e52a602
XW		 7363 hclge_clear_all_event_cause(hdev);
7364
466b0c00
L		 7365 /* Enable MISC vector(vector0) */
7366 hclge_enable_vector(&hdev->misc_vector, true);
7367
48569cda 7368 hclge_state_init(hdev);
0742ed7c 7369 hdev->last_reset_time = jiffies;
46a3df9f
S		 7370
7371 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
7372 return 0;
7373
ffd5656e
HT		 7374err_mdiobus_unreg:
7375 if (hdev->hw.mac.phydev)
7376 mdiobus_unregister(hdev->hw.mac.mdio_bus);
ffd5656e
HT		 7377err_msi_irq_uninit:
7378 hclge_misc_irq_uninit(hdev);
7379err_msi_uninit:
7380 pci_free_irq_vectors(pdev);
7381err_cmd_uninit:
7382 hclge_destroy_cmd_queue(&hdev->hw);
7383err_pci_uninit:
6a814413 7384 pcim_iounmap(pdev, hdev->hw.io_base);
ffd5656e 7385 pci_clear_master(pdev);
46a3df9f 7386 pci_release_regions(pdev);
ffd5656e 7387 pci_disable_device(pdev);
ffd5656e 7388out:
46a3df9f
S		 7389 return ret;
7390}
7391
c6dc5213 7392static void hclge_stats_clear(struct hclge_dev *hdev)
7393{
7394 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
7395}
7396
a6d818e3
YL		 7397static void hclge_reset_vport_state(struct hclge_dev *hdev)
7398{
7399 struct hclge_vport *vport = hdev->vport;
7400 int i;
7401
7402 for (i = 0; i < hdev->num_alloc_vport; i++) {
7403 hclge_vport_start(vport);
7404 vport++;
7405 }
7406}
7407
4ed340ab
L		 7408static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
7409{
7410 struct hclge_dev *hdev = ae_dev->priv;
7411 struct pci_dev *pdev = ae_dev->pdev;
7412 int ret;
7413
7414 set_bit(HCLGE_STATE_DOWN, &hdev->state);
7415
c6dc5213 7416 hclge_stats_clear(hdev);
dc8131d8 7417 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 7418
4ed340ab
L		 7419 ret = hclge_cmd_init(hdev);
7420 if (ret) {
7421 dev_err(&pdev->dev, "Cmd queue init failed\n");
7422 return ret;
7423 }
7424
4ed340ab
L		 7425 ret = hclge_map_tqp(hdev);
7426 if (ret) {
7427 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
7428 return ret;
7429 }
7430
39932473
JS		 7431 hclge_reset_umv_space(hdev);
7432
4ed340ab
L		 7433 ret = hclge_mac_init(hdev);
7434 if (ret) {
7435 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
7436 return ret;
7437 }
7438
4ed340ab
L		 7439 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7440 if (ret) {
7441 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
7442 return ret;
7443 }
7444
b26a6fea
PL		 7445 ret = hclge_config_gro(hdev, true);
7446 if (ret)
7447 return ret;
7448
4ed340ab
L		 7449 ret = hclge_init_vlan_config(hdev);
7450 if (ret) {
7451 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
7452 return ret;
7453 }
7454
f31c1ba6 7455 ret = hclge_tm_init_hw(hdev);
4ed340ab 7456 if (ret) {
f31c1ba6 7457 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 7458 return ret;
7459 }
7460
7461 ret = hclge_rss_init_hw(hdev);
7462 if (ret) {
7463 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
7464 return ret;
7465 }
7466
d695964d
JS		 7467 ret = hclge_init_fd_config(hdev);
7468 if (ret) {
7469 dev_err(&pdev->dev,
7470 "fd table init fail, ret=%d\n", ret);
7471 return ret;
7472 }
7473
f3fa4a94
SJ		 7474 /* Re-enable the hw error interrupts because
7475 * the interrupts get disabled on core/global reset.
01865a50 7476 */
f3fa4a94
SJ		 7477 ret = hclge_hw_error_set_state(hdev, true);
7478 if (ret) {
7479 dev_err(&pdev->dev,
7480 "fail(%d) to re-enable HNS hw error interrupts\n", ret);
7481 return ret;
7482 }
01865a50 7483
a6d818e3
YL		 7484 hclge_reset_vport_state(hdev);
7485
4ed340ab
L		 7486 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
7487 HCLGE_DRIVER_NAME);
7488
7489 return 0;
7490}
7491
46a3df9f
S		 7492static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
7493{
7494 struct hclge_dev *hdev = ae_dev->priv;
7495 struct hclge_mac *mac = &hdev->hw.mac;
7496
48569cda 7497 hclge_state_uninit(hdev);
46a3df9f
S		 7498
7499 if (mac->phydev)
7500 mdiobus_unregister(mac->mdio_bus);
7501
39932473
JS		 7502 hclge_uninit_umv_space(hdev);
7503
466b0c00
L		 7504 /* Disable MISC vector(vector0) */
7505 hclge_enable_vector(&hdev->misc_vector, false);
8e52a602
XW		 7506 synchronize_irq(hdev->misc_vector.vector_irq);
7507
99714195 7508 hclge_hw_error_set_state(hdev, false);
46a3df9f 7509 hclge_destroy_cmd_queue(&hdev->hw);
ca1d7669 7510 hclge_misc_irq_uninit(hdev);
46a3df9f 7511 hclge_pci_uninit(hdev);
818f1675 7512 mutex_destroy(&hdev->vport_lock);
46a3df9f
S		 7513 ae_dev->priv = NULL;
7514}
7515
482d2e9c
PL		 7516static u32 hclge_get_max_channels(struct hnae3_handle *handle)
7517{
7518 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
7519 struct hclge_vport *vport = hclge_get_vport(handle);
7520 struct hclge_dev *hdev = vport->back;
7521
7522 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
7523}
7524
7525static void hclge_get_channels(struct hnae3_handle *handle,
7526 struct ethtool_channels *ch)
7527{
7528 struct hclge_vport *vport = hclge_get_vport(handle);
7529
7530 ch->max_combined = hclge_get_max_channels(handle);
7531 ch->other_count = 1;
7532 ch->max_other = 1;
7533 ch->combined_count = vport->alloc_tqps;
7534}
7535
09f2af64 7536static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
0d43bf45 7537 u16 *alloc_tqps, u16 *max_rss_size)
09f2af64
PL		 7538{
7539 struct hclge_vport *vport = hclge_get_vport(handle);
7540 struct hclge_dev *hdev = vport->back;
09f2af64 7541
0d43bf45 7542 *alloc_tqps = vport->alloc_tqps;
09f2af64
PL		 7543 *max_rss_size = hdev->rss_size_max;
7544}
7545
7546static void hclge_release_tqp(struct hclge_vport *vport)
7547{
7548 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7549 struct hclge_dev *hdev = vport->back;
7550 int i;
7551
7552 for (i = 0; i < kinfo->num_tqps; i++) {
7553 struct hclge_tqp *tqp =
7554 container_of(kinfo->tqp[i], struct hclge_tqp, q);
7555
7556 tqp->q.handle = NULL;
7557 tqp->q.tqp_index = 0;
7558 tqp->alloced = false;
7559 }
7560
7561 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
7562 kinfo->tqp = NULL;
7563}
7564
7565static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
7566{
7567 struct hclge_vport *vport = hclge_get_vport(handle);
7568 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7569 struct hclge_dev *hdev = vport->back;
7570 int cur_rss_size = kinfo->rss_size;
7571 int cur_tqps = kinfo->num_tqps;
7572 u16 tc_offset[HCLGE_MAX_TC_NUM];
7573 u16 tc_valid[HCLGE_MAX_TC_NUM];
7574 u16 tc_size[HCLGE_MAX_TC_NUM];
7575 u16 roundup_size;
7576 u32 *rss_indir;
7577 int ret, i;
7578
fdace1bc 7579 /* Free old tqps, and reallocate with new tqp number when nic setup */
09f2af64
PL		 7580 hclge_release_tqp(vport);
7581
128b900d 7582 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
09f2af64
PL		 7583 if (ret) {
7584 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
7585 return ret;
7586 }
7587
7588 ret = hclge_map_tqp_to_vport(hdev, vport);
7589 if (ret) {
7590 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
7591 return ret;
7592 }
7593
7594 ret = hclge_tm_schd_init(hdev);
7595 if (ret) {
7596 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
7597 return ret;
7598 }
7599
7600 roundup_size = roundup_pow_of_two(kinfo->rss_size);
7601 roundup_size = ilog2(roundup_size);
7602 /* Set the RSS TC mode according to the new RSS size */
7603 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
7604 tc_valid[i] = 0;
7605
7606 if (!(hdev->hw_tc_map & BIT(i)))
7607 continue;
7608
7609 tc_valid[i] = 1;
7610 tc_size[i] = roundup_size;
7611 tc_offset[i] = kinfo->rss_size * i;
7612 }
7613 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
7614 if (ret)
7615 return ret;
7616
7617 /* Reinitializes the rss indirect table according to the new RSS size */
7618 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
7619 if (!rss_indir)
7620 return -ENOMEM;
7621
7622 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
7623 rss_indir[i] = i % kinfo->rss_size;
7624
7625 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
7626 if (ret)
7627 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
7628 ret);
7629
7630 kfree(rss_indir);
7631
7632 if (!ret)
7633 dev_info(&hdev->pdev->dev,
7634 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
7635 cur_rss_size, kinfo->rss_size,
7636 cur_tqps, kinfo->rss_size * kinfo->num_tc);
7637
7638 return ret;
7639}
7640
77b34110
FL		 7641static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
7642 u32 *regs_num_64_bit)
7643{
7644 struct hclge_desc desc;
7645 u32 total_num;
7646 int ret;
7647
7648 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
7649 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7650 if (ret) {
7651 dev_err(&hdev->pdev->dev,
7652 "Query register number cmd failed, ret = %d.\n", ret);
7653 return ret;
7654 }
7655
7656 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
7657 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
7658
7659 total_num = *regs_num_32_bit + *regs_num_64_bit;
7660 if (!total_num)
7661 return -EINVAL;
7662
7663 return 0;
7664}
7665
7666static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7667 void *data)
7668{
7669#define HCLGE_32_BIT_REG_RTN_DATANUM 8
7670
7671 struct hclge_desc *desc;
7672 u32 *reg_val = data;
7673 __le32 *desc_data;
7674 int cmd_num;
7675 int i, k, n;
7676 int ret;
7677
7678 if (regs_num == 0)
7679 return 0;
7680
7681 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
7682 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7683 if (!desc)
7684 return -ENOMEM;
7685
7686 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
7687 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7688 if (ret) {
7689 dev_err(&hdev->pdev->dev,
7690 "Query 32 bit register cmd failed, ret = %d.\n", ret);
7691 kfree(desc);
7692 return ret;
7693 }
7694
7695 for (i = 0; i < cmd_num; i++) {
7696 if (i == 0) {
7697 desc_data = (__le32 *)(&desc[i].data[0]);
7698 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
7699 } else {
7700 desc_data = (__le32 *)(&desc[i]);
7701 n = HCLGE_32_BIT_REG_RTN_DATANUM;
7702 }
7703 for (k = 0; k < n; k++) {
7704 *reg_val++ = le32_to_cpu(*desc_data++);
7705
7706 regs_num--;
7707 if (!regs_num)
7708 break;
7709 }
7710 }
7711
7712 kfree(desc);
7713 return 0;
7714}
7715
7716static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7717 void *data)
7718{
7719#define HCLGE_64_BIT_REG_RTN_DATANUM 4
7720
7721 struct hclge_desc *desc;
7722 u64 *reg_val = data;
7723 __le64 *desc_data;
7724 int cmd_num;
7725 int i, k, n;
7726 int ret;
7727
7728 if (regs_num == 0)
7729 return 0;
7730
7731 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
7732 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7733 if (!desc)
7734 return -ENOMEM;
7735
7736 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
7737 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7738 if (ret) {
7739 dev_err(&hdev->pdev->dev,
7740 "Query 64 bit register cmd failed, ret = %d.\n", ret);
7741 kfree(desc);
7742 return ret;
7743 }
7744
7745 for (i = 0; i < cmd_num; i++) {
7746 if (i == 0) {
7747 desc_data = (__le64 *)(&desc[i].data[0]);
7748 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
7749 } else {
7750 desc_data = (__le64 *)(&desc[i]);
7751 n = HCLGE_64_BIT_REG_RTN_DATANUM;
7752 }
7753 for (k = 0; k < n; k++) {
7754 *reg_val++ = le64_to_cpu(*desc_data++);
7755
7756 regs_num--;
7757 if (!regs_num)
7758 break;
7759 }
7760 }
7761
7762 kfree(desc);
7763 return 0;
7764}
7765
ea4750ca
JS		 7766#define MAX_SEPARATE_NUM 4
7767#define SEPARATOR_VALUE 0xFFFFFFFF
7768#define REG_NUM_PER_LINE 4
7769#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32))
7770
77b34110
FL		 7771static int hclge_get_regs_len(struct hnae3_handle *handle)
7772{
ea4750ca
JS		 7773 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
7774 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
77b34110
FL		 7775 struct hclge_vport *vport = hclge_get_vport(handle);
7776 struct hclge_dev *hdev = vport->back;
7777 u32 regs_num_32_bit, regs_num_64_bit;
7778 int ret;
7779
7780 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7781 if (ret) {
7782 dev_err(&hdev->pdev->dev,
7783 "Get register number failed, ret = %d.\n", ret);
7784 return -EOPNOTSUPP;
7785 }
7786
ea4750ca
JS		 7787 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
7788 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
7789 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
7790 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
7791
7792 return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps +
7793 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE +
7794 regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
77b34110
FL		 7795}
7796
7797static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
7798 void *data)
7799{
ea4750ca 7800 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
77b34110
FL		 7801 struct hclge_vport *vport = hclge_get_vport(handle);
7802 struct hclge_dev *hdev = vport->back;
7803 u32 regs_num_32_bit, regs_num_64_bit;
ea4750ca
JS		 7804 int i, j, reg_um, separator_num;
7805 u32 *reg = data;
77b34110
FL		 7806 int ret;
7807
7808 *version = hdev->fw_version;
7809
7810 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7811 if (ret) {
7812 dev_err(&hdev->pdev->dev,
7813 "Get register number failed, ret = %d.\n", ret);
7814 return;
7815 }
7816
ea4750ca
JS		 7817 /* fetching per-PF registers valus from PF PCIe register space */
7818 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
7819 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7820 for (i = 0; i < reg_um; i++)
7821 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
7822 for (i = 0; i < separator_num; i++)
7823 *reg++ = SEPARATOR_VALUE;
7824
7825 reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
7826 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7827 for (i = 0; i < reg_um; i++)
7828 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]);
7829 for (i = 0; i < separator_num; i++)
7830 *reg++ = SEPARATOR_VALUE;
7831
7832 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
7833 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7834 for (j = 0; j < kinfo->num_tqps; j++) {
7835 for (i = 0; i < reg_um; i++)
7836 *reg++ = hclge_read_dev(&hdev->hw,
7837 ring_reg_addr_list[i] +
7838 0x200 * j);
7839 for (i = 0; i < separator_num; i++)
7840 *reg++ = SEPARATOR_VALUE;
7841 }
7842
7843 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
7844 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7845 for (j = 0; j < hdev->num_msi_used - 1; j++) {
7846 for (i = 0; i < reg_um; i++)
7847 *reg++ = hclge_read_dev(&hdev->hw,
7848 tqp_intr_reg_addr_list[i] +
7849 4 * j);
7850 for (i = 0; i < separator_num; i++)
7851 *reg++ = SEPARATOR_VALUE;
7852 }
7853
7854 /* fetching PF common registers values from firmware */
7855 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg);
77b34110
FL		 7856 if (ret) {
7857 dev_err(&hdev->pdev->dev,
7858 "Get 32 bit register failed, ret = %d.\n", ret);
7859 return;
7860 }
7861
ea4750ca
JS		 7862 reg += regs_num_32_bit;
7863 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg);
77b34110
FL		 7864 if (ret)
7865 dev_err(&hdev->pdev->dev,
7866 "Get 64 bit register failed, ret = %d.\n", ret);
7867}
7868
f6f75abc 7869static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
07f8e940
JS		 7870{
7871 struct hclge_set_led_state_cmd *req;
7872 struct hclge_desc desc;
7873 int ret;
7874
7875 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
7876
7877 req = (struct hclge_set_led_state_cmd *)desc.data;
e4e87715
PL		 7878 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
7879 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
07f8e940
JS		 7880
7881 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7882 if (ret)
7883 dev_err(&hdev->pdev->dev,
7884 "Send set led state cmd error, ret =%d\n", ret);
7885
7886 return ret;
7887}
7888
7889enum hclge_led_status {
7890 HCLGE_LED_OFF,
7891 HCLGE_LED_ON,
7892 HCLGE_LED_NO_CHANGE = 0xFF,
7893};
7894
7895static int hclge_set_led_id(struct hnae3_handle *handle,
7896 enum ethtool_phys_id_state status)
7897{
07f8e940
JS		 7898 struct hclge_vport *vport = hclge_get_vport(handle);
7899 struct hclge_dev *hdev = vport->back;
07f8e940
JS		 7900
7901 switch (status) {
7902 case ETHTOOL_ID_ACTIVE:
f6f75abc 7903 return hclge_set_led_status(hdev, HCLGE_LED_ON);
07f8e940 7904 case ETHTOOL_ID_INACTIVE:
f6f75abc 7905 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
07f8e940 7906 default:
f6f75abc 7907 return -EINVAL;
07f8e940 7908 }
07f8e940
JS		 7909}
7910
0979aa0b
FL		 7911static void hclge_get_link_mode(struct hnae3_handle *handle,
7912 unsigned long *supported,
7913 unsigned long *advertising)
7914{
7915 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
7916 struct hclge_vport *vport = hclge_get_vport(handle);
7917 struct hclge_dev *hdev = vport->back;
7918 unsigned int idx = 0;
7919
7920 for (; idx < size; idx++) {
7921 supported[idx] = hdev->hw.mac.supported[idx];
7922 advertising[idx] = hdev->hw.mac.advertising[idx];
7923 }
7924}
7925
5c9f6b39
PL		 7926static int hclge_gro_en(struct hnae3_handle *handle, int enable)
7927{
7928 struct hclge_vport *vport = hclge_get_vport(handle);
7929 struct hclge_dev *hdev = vport->back;
7930
7931 return hclge_config_gro(hdev, enable);
7932}
7933
46a3df9f
S		 7934static const struct hnae3_ae_ops hclge_ops = {
7935 .init_ae_dev = hclge_init_ae_dev,
7936 .uninit_ae_dev = hclge_uninit_ae_dev,
6b9a97ee
HT		 7937 .flr_prepare = hclge_flr_prepare,
7938 .flr_done = hclge_flr_done,
46a3df9f
S		 7939 .init_client_instance = hclge_init_client_instance,
7940 .uninit_client_instance = hclge_uninit_client_instance,
84e095d6
SM		 7941 .map_ring_to_vector = hclge_map_ring_to_vector,
7942 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 7943 .get_vector = hclge_get_vector,
0d3e6631 7944 .put_vector = hclge_put_vector,
46a3df9f 7945 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 7946 .set_loopback = hclge_set_loopback,
46a3df9f
S		 7947 .start = hclge_ae_start,
7948 .stop = hclge_ae_stop,
a6d818e3
YL		 7949 .client_start = hclge_client_start,
7950 .client_stop = hclge_client_stop,
46a3df9f
S		 7951 .get_status = hclge_get_status,
7952 .get_ksettings_an_result = hclge_get_ksettings_an_result,
7953 .update_speed_duplex_h = hclge_update_speed_duplex_h,
7954 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
7955 .get_media_type = hclge_get_media_type,
7956 .get_rss_key_size = hclge_get_rss_key_size,
7957 .get_rss_indir_size = hclge_get_rss_indir_size,
7958 .get_rss = hclge_get_rss,
7959 .set_rss = hclge_set_rss,
f7db940a 7960 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 7961 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 7962 .get_tc_size = hclge_get_tc_size,
7963 .get_mac_addr = hclge_get_mac_addr,
7964 .set_mac_addr = hclge_set_mac_addr,
26483246 7965 .do_ioctl = hclge_do_ioctl,
46a3df9f
S		 7966 .add_uc_addr = hclge_add_uc_addr,
7967 .rm_uc_addr = hclge_rm_uc_addr,
7968 .add_mc_addr = hclge_add_mc_addr,
7969 .rm_mc_addr = hclge_rm_mc_addr,
7970 .set_autoneg = hclge_set_autoneg,
7971 .get_autoneg = hclge_get_autoneg,
7972 .get_pauseparam = hclge_get_pauseparam,
61387774 7973 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 7974 .set_mtu = hclge_set_mtu,
7975 .reset_queue = hclge_reset_tqp,
7976 .get_stats = hclge_get_stats,
7977 .update_stats = hclge_update_stats,
7978 .get_strings = hclge_get_strings,
7979 .get_sset_count = hclge_get_sset_count,
7980 .get_fw_version = hclge_get_fw_version,
7981 .get_mdix_mode = hclge_get_mdix_mode,
391b5e93 7982 .enable_vlan_filter = hclge_enable_vlan_filter,
dc8131d8 7983 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 7984 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
052ece6d 7985 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 7986 .reset_event = hclge_reset_event,
720bd583 7987 .set_default_reset_request = hclge_set_def_reset_request,
09f2af64
PL		 7988 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
7989 .set_channels = hclge_set_channels,
482d2e9c 7990 .get_channels = hclge_get_channels,
77b34110
FL		 7991 .get_regs_len = hclge_get_regs_len,
7992 .get_regs = hclge_get_regs,
07f8e940 7993 .set_led_id = hclge_set_led_id,
0979aa0b 7994 .get_link_mode = hclge_get_link_mode,
dd74f815
JS		 7995 .add_fd_entry = hclge_add_fd_entry,
7996 .del_fd_entry = hclge_del_fd_entry,
6871af29 7997 .del_all_fd_entries = hclge_del_all_fd_entries,
05c2314f
JS		 7998 .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
7999 .get_fd_rule_info = hclge_get_fd_rule_info,
8000 .get_fd_all_rules = hclge_get_all_rules,
6871af29 8001 .restore_fd_rules = hclge_restore_fd_entries,
c17852a8 8002 .enable_fd = hclge_enable_fd,
3c666b58 8003 .dbg_run_cmd = hclge_dbg_run_cmd,
381c356e 8004 .handle_hw_ras_error = hclge_handle_hw_ras_error,
4d60291b
HT		 8005 .get_hw_reset_stat = hclge_get_hw_reset_stat,
8006 .ae_dev_resetting = hclge_ae_dev_resetting,
8007 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
5c9f6b39 8008 .set_gro_en = hclge_gro_en,
0c29d191 8009 .get_global_queue_id = hclge_covert_handle_qid_global,
8cdb992f 8010 .set_timer_task = hclge_set_timer_task,
46a3df9f
S		 8011};
8012
8013static struct hnae3_ae_algo ae_algo = {
8014 .ops = &hclge_ops,
46a3df9f
S		 8015 .pdev_id_table = ae_algo_pci_tbl,
8016};
8017
8018static int hclge_init(void)
8019{
8020 pr_info("%s is initializing\n", HCLGE_NAME);
8021
854cf33a
FL		 8022 hnae3_register_ae_algo(&ae_algo);
8023
8024 return 0;
46a3df9f
S		 8025}
8026
8027static void hclge_exit(void)
8028{
8029 hnae3_unregister_ae_algo(&ae_algo);
8030}
8031module_init(hclge_init);
8032module_exit(hclge_exit);
8033
8034MODULE_LICENSE("GPL");
8035MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
8036MODULE_DESCRIPTION("HCLGE Driver");
8037MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)