Commit | Line | Data |
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2ef17216 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
d71d8381 | 2 | // Copyright (c) 2016-2017 Hisilicon Limited. |
68c0a5c7 S |
3 | |
4 | #ifndef __HCLGE_CMD_H | |
5 | #define __HCLGE_CMD_H | |
6 | #include <linux/types.h> | |
7 | #include <linux/io.h> | |
0e02a53d | 8 | #include <linux/etherdevice.h> |
68c0a5c7 | 9 | |
d458c815 | 10 | #define HCLGE_CMDQ_TX_TIMEOUT 30000 |
d6ad7c53 | 11 | #define HCLGE_DESC_DATA_LEN 6 |
68c0a5c7 S |
12 | |
13 | struct hclge_dev; | |
14 | struct hclge_desc { | |
15 | __le16 opcode; | |
16 | ||
17 | #define HCLGE_CMDQ_RX_INVLD_B 0 | |
18 | #define HCLGE_CMDQ_RX_OUTVLD_B 1 | |
19 | ||
20 | __le16 flag; | |
21 | __le16 retval; | |
22 | __le16 rsv; | |
d6ad7c53 | 23 | __le32 data[HCLGE_DESC_DATA_LEN]; |
68c0a5c7 S |
24 | }; |
25 | ||
68c0a5c7 S |
26 | struct hclge_cmq_ring { |
27 | dma_addr_t desc_dma_addr; | |
28 | struct hclge_desc *desc; | |
a10829c4 | 29 | struct hclge_dev *dev; |
68c0a5c7 S |
30 | u32 head; |
31 | u32 tail; | |
32 | ||
33 | u16 buf_size; | |
34 | u16 desc_num; | |
35 | int next_to_use; | |
36 | int next_to_clean; | |
ef0c5009 | 37 | u8 ring_type; /* cmq ring type */ |
68c0a5c7 S |
38 | spinlock_t lock; /* Command queue lock */ |
39 | }; | |
40 | ||
41 | enum hclge_cmd_return_status { | |
42 | HCLGE_CMD_EXEC_SUCCESS = 0, | |
43 | HCLGE_CMD_NO_AUTH = 1, | |
4a402f47 | 44 | HCLGE_CMD_NOT_SUPPORTED = 2, |
68c0a5c7 | 45 | HCLGE_CMD_QUEUE_FULL = 3, |
9e1511fb PL |
46 | HCLGE_CMD_NEXT_ERR = 4, |
47 | HCLGE_CMD_UNEXE_ERR = 5, | |
48 | HCLGE_CMD_PARA_ERR = 6, | |
49 | HCLGE_CMD_RESULT_ERR = 7, | |
50 | HCLGE_CMD_TIMEOUT = 8, | |
51 | HCLGE_CMD_HILINK_ERR = 9, | |
52 | HCLGE_CMD_QUEUE_ILLEGAL = 10, | |
53 | HCLGE_CMD_INVALID = 11, | |
68c0a5c7 S |
54 | }; |
55 | ||
56 | enum hclge_cmd_status { | |
57 | HCLGE_STATUS_SUCCESS = 0, | |
58 | HCLGE_ERR_CSQ_FULL = -1, | |
59 | HCLGE_ERR_CSQ_TIMEOUT = -2, | |
60 | HCLGE_ERR_CSQ_ERROR = -3, | |
61 | }; | |
62 | ||
466b0c00 L |
63 | struct hclge_misc_vector { |
64 | u8 __iomem *addr; | |
65 | int vector_irq; | |
66 | }; | |
67 | ||
68c0a5c7 S |
68 | struct hclge_cmq { |
69 | struct hclge_cmq_ring csq; | |
70 | struct hclge_cmq_ring crq; | |
fdace1bc | 71 | u16 tx_timeout; |
68c0a5c7 S |
72 | enum hclge_cmd_status last_status; |
73 | }; | |
74 | ||
c79301d8 JS |
75 | #define HCLGE_CMD_FLAG_IN BIT(0) |
76 | #define HCLGE_CMD_FLAG_OUT BIT(1) | |
77 | #define HCLGE_CMD_FLAG_NEXT BIT(2) | |
78 | #define HCLGE_CMD_FLAG_WR BIT(3) | |
79 | #define HCLGE_CMD_FLAG_NO_INTR BIT(4) | |
80 | #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) | |
68c0a5c7 S |
81 | |
82 | enum hclge_opcode_type { | |
fdace1bc | 83 | /* Generic commands */ |
68c0a5c7 S |
84 | HCLGE_OPC_QUERY_FW_VER = 0x0001, |
85 | HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, | |
86 | HCLGE_OPC_GBL_RST_STATUS = 0x0021, | |
87 | HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, | |
88 | HCLGE_OPC_QUERY_PF_RSRC = 0x0023, | |
89 | HCLGE_OPC_QUERY_VF_RSRC = 0x0024, | |
90 | HCLGE_OPC_GET_CFG_PARAM = 0x0025, | |
72e2fb07 | 91 | HCLGE_OPC_PF_RST_DONE = 0x0026, |
427a7bff | 92 | HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027, |
68c0a5c7 S |
93 | |
94 | HCLGE_OPC_STATS_64_BIT = 0x0030, | |
95 | HCLGE_OPC_STATS_32_BIT = 0x0031, | |
96 | HCLGE_OPC_STATS_MAC = 0x0032, | |
d174ea75 | 97 | HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, |
98 | HCLGE_OPC_STATS_MAC_ALL = 0x0034, | |
77b34110 FL |
99 | |
100 | HCLGE_OPC_QUERY_REG_NUM = 0x0040, | |
101 | HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, | |
102 | HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, | |
27cf979a | 103 | HCLGE_OPC_DFX_BD_NUM = 0x0043, |
104 | HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, | |
105 | HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, | |
106 | HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, | |
107 | HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, | |
108 | HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, | |
109 | HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, | |
110 | HCLGE_OPC_DFX_NCSI_REG = 0x004A, | |
111 | HCLGE_OPC_DFX_RTC_REG = 0x004B, | |
112 | HCLGE_OPC_DFX_PPP_REG = 0x004C, | |
113 | HCLGE_OPC_DFX_RCB_REG = 0x004D, | |
114 | HCLGE_OPC_DFX_TQP_REG = 0x004E, | |
115 | HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, | |
116 | HCLGE_OPC_DFX_QUERY_CHIP_CAP = 0x0050, | |
68c0a5c7 | 117 | |
fdace1bc | 118 | /* MAC command */ |
68c0a5c7 S |
119 | HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, |
120 | HCLGE_OPC_CONFIG_AN_MODE = 0x0304, | |
68c0a5c7 S |
121 | HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, |
122 | HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, | |
123 | HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, | |
a6345787 WL |
124 | HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, |
125 | HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, | |
126 | HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, | |
5fd50ac3 | 127 | HCLGE_OPC_SERDES_LOOPBACK = 0x0315, |
7e6ec914 | 128 | HCLGE_OPC_CONFIG_FEC_MODE = 0x031A, |
68c0a5c7 | 129 | |
fdace1bc | 130 | /* PFC/Pause commands */ |
68c0a5c7 S |
131 | HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, |
132 | HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, | |
133 | HCLGE_OPC_CFG_MAC_PARA = 0x0703, | |
134 | HCLGE_OPC_CFG_PFC_PARA = 0x0704, | |
135 | HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, | |
136 | HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, | |
137 | HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, | |
138 | HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, | |
139 | HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, | |
140 | HCLGE_OPC_QOS_MAP = 0x070A, | |
141 | ||
142 | /* ETS/scheduler commands */ | |
143 | HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, | |
144 | HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, | |
145 | HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, | |
146 | HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, | |
147 | HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, | |
148 | HCLGE_OPC_TM_PG_WEIGHT = 0x0809, | |
149 | HCLGE_OPC_TM_QS_WEIGHT = 0x080A, | |
150 | HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, | |
151 | HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, | |
152 | HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, | |
153 | HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, | |
154 | HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, | |
155 | HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, | |
156 | HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, | |
157 | HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, | |
158 | HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, | |
159 | HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, | |
2849d4e7 | 160 | HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, |
c0ebebb9 | 161 | HCLGE_OPC_QSET_DFX_STS = 0x0844, |
162 | HCLGE_OPC_PRI_DFX_STS = 0x0845, | |
163 | HCLGE_OPC_PG_DFX_STS = 0x0846, | |
164 | HCLGE_OPC_PORT_DFX_STS = 0x0847, | |
165 | HCLGE_OPC_SCH_NQ_CNT = 0x0848, | |
166 | HCLGE_OPC_SCH_RQ_CNT = 0x0849, | |
167 | HCLGE_OPC_TM_INTERNAL_STS = 0x0850, | |
168 | HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, | |
169 | HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, | |
68c0a5c7 | 170 | |
fdace1bc | 171 | /* Packet buffer allocate commands */ |
68c0a5c7 S |
172 | HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, |
173 | HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, | |
174 | HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, | |
175 | HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, | |
176 | HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, | |
177 | HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, | |
178 | ||
68c0a5c7 S |
179 | /* TQP management command */ |
180 | HCLGE_OPC_SET_TQP_MAP = 0x0A01, | |
181 | ||
fdace1bc | 182 | /* TQP commands */ |
68c0a5c7 S |
183 | HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, |
184 | HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, | |
185 | HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, | |
82e00b86 | 186 | HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, |
68c0a5c7 S |
187 | HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, |
188 | HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, | |
189 | HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, | |
190 | HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, | |
191 | HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, | |
192 | HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, | |
193 | HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, | |
194 | ||
0cd86182 WL |
195 | /* PPU commands */ |
196 | HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A, | |
197 | ||
fdace1bc | 198 | /* TSO command */ |
68c0a5c7 | 199 | HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, |
b26a6fea | 200 | HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, |
68c0a5c7 | 201 | |
fdace1bc | 202 | /* RSS commands */ |
68c0a5c7 S |
203 | HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, |
204 | HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, | |
205 | HCLGE_OPC_RSS_TC_MODE = 0x0D08, | |
206 | HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, | |
207 | ||
208 | /* Promisuous mode command */ | |
209 | HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, | |
210 | ||
fdace1bc | 211 | /* Vlan offload commands */ |
5f6ea83f PL |
212 | HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, |
213 | HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, | |
214 | ||
fdace1bc | 215 | /* Interrupts commands */ |
68c0a5c7 S |
216 | HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, |
217 | HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, | |
218 | ||
fdace1bc | 219 | /* MAC commands */ |
68c0a5c7 S |
220 | HCLGE_OPC_MAC_VLAN_ADD = 0x1000, |
221 | HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, | |
222 | HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, | |
223 | HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, | |
39932473 | 224 | HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, |
68c0a5c7 S |
225 | HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, |
226 | HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, | |
227 | ||
dd2956ea YM |
228 | /* MAC VLAN commands */ |
229 | HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033, | |
230 | ||
fdace1bc | 231 | /* VLAN commands */ |
68c0a5c7 S |
232 | HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, |
233 | HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, | |
234 | HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, | |
235 | ||
d695964d JS |
236 | /* Flow Director commands */ |
237 | HCLGE_OPC_FD_MODE_CTRL = 0x1200, | |
238 | HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, | |
239 | HCLGE_OPC_FD_KEY_CONFIG = 0x1202, | |
11732868 JS |
240 | HCLGE_OPC_FD_TCAM_OP = 0x1203, |
241 | HCLGE_OPC_FD_AD_OP = 0x1204, | |
d695964d | 242 | |
68c0a5c7 S |
243 | /* MDIO command */ |
244 | HCLGE_OPC_MDIO_CONFIG = 0x1900, | |
245 | ||
fdace1bc | 246 | /* QCN commands */ |
68c0a5c7 S |
247 | HCLGE_OPC_QCN_MOD_CFG = 0x1A01, |
248 | HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, | |
ee9e4424 | 249 | HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03, |
68c0a5c7 S |
250 | HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, |
251 | HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, | |
252 | HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, | |
253 | HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, | |
254 | HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, | |
255 | ||
fdace1bc | 256 | /* Mailbox command */ |
68c0a5c7 | 257 | HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, |
07f8e940 JS |
258 | |
259 | /* Led command */ | |
260 | HCLGE_OPC_LED_STATUS_CFG = 0xB000, | |
6d67ee9a | 261 | |
ffd140e2 WL |
262 | /* NCL config command */ |
263 | HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, | |
db4d3d55 | 264 | |
33a90e2f ZL |
265 | /* M7 stats command */ |
266 | HCLGE_OPC_M7_STATS_BD = 0x7012, | |
267 | HCLGE_OPC_M7_STATS_INFO = 0x7013, | |
ed8fb4b2 | 268 | HCLGE_OPC_M7_COMPAT_CFG = 0x701A, |
ffd140e2 | 269 | |
5d497936 | 270 | /* SFP command */ |
88d10bd6 | 271 | HCLGE_OPC_GET_SFP_INFO = 0x7104, |
5d497936 | 272 | |
6d67ee9a | 273 | /* Error INT commands */ |
7838f908 | 274 | HCLGE_MAC_COMMON_INT_EN = 0x030E, |
01865a50 | 275 | HCLGE_TM_SCH_ECC_INT_EN = 0x0829, |
c3529177 SJ |
276 | HCLGE_SSU_ECC_INT_CMD = 0x0989, |
277 | HCLGE_SSU_COMMON_INT_CMD = 0x098C, | |
f69b10b3 SJ |
278 | HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, |
279 | HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, | |
280 | HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, | |
6d67ee9a | 281 | HCLGE_COMMON_ECC_INT_CFG = 0x1505, |
332fbf57 SJ |
282 | HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, |
283 | HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, | |
284 | HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, | |
f6162d44 SM |
285 | HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, |
286 | HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, | |
287 | HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, | |
630ba007 SJ |
288 | HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, |
289 | HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, | |
290 | HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, | |
238882c8 XT |
291 | HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585, |
292 | HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586, | |
bf1faf94 | 293 | HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, |
bf1faf94 | 294 | HCLGE_IGU_COMMON_INT_EN = 0x1806, |
01865a50 | 295 | HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, |
da2d072a SJ |
296 | HCLGE_PPP_CMD0_INT_CMD = 0x2100, |
297 | HCLGE_PPP_CMD1_INT_CMD = 0x2101, | |
7737f1fb | 298 | HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, |
bf1faf94 | 299 | HCLGE_NCSI_INT_EN = 0x2401, |
68c0a5c7 S |
300 | }; |
301 | ||
302 | #define HCLGE_TQP_REG_OFFSET 0x80000 | |
303 | #define HCLGE_TQP_REG_SIZE 0x200 | |
304 | ||
305 | #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 | |
306 | #define HCLGE_RCB_INIT_FLAG_EN_B 0 | |
307 | #define HCLGE_RCB_INIT_FLAG_FINI_B 8 | |
d44f9b63 | 308 | struct hclge_config_rcb_init_cmd { |
68c0a5c7 S |
309 | __le16 rcb_init_flag; |
310 | u8 rsv[22]; | |
311 | }; | |
312 | ||
d44f9b63 | 313 | struct hclge_tqp_map_cmd { |
68c0a5c7 S |
314 | __le16 tqp_id; /* Absolute tqp id for in this pf */ |
315 | u8 tqp_vf; /* VF id */ | |
316 | #define HCLGE_TQP_MAP_TYPE_PF 0 | |
317 | #define HCLGE_TQP_MAP_TYPE_VF 1 | |
318 | #define HCLGE_TQP_MAP_TYPE_B 0 | |
319 | #define HCLGE_TQP_MAP_EN_B 1 | |
320 | u8 tqp_flag; /* Indicate it's pf or vf tqp */ | |
321 | __le16 tqp_vid; /* Virtual id in this pf/vf */ | |
322 | u8 rsv[18]; | |
323 | }; | |
324 | ||
0305b443 | 325 | #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 |
68c0a5c7 S |
326 | |
327 | enum hclge_int_type { | |
328 | HCLGE_INT_TX, | |
329 | HCLGE_INT_RX, | |
330 | HCLGE_INT_EVENT, | |
331 | }; | |
332 | ||
d44f9b63 | 333 | struct hclge_ctrl_vector_chain_cmd { |
68c0a5c7 S |
334 | u8 int_vector_id; |
335 | u8 int_cause_num; | |
336 | #define HCLGE_INT_TYPE_S 0 | |
5392902d | 337 | #define HCLGE_INT_TYPE_M GENMASK(1, 0) |
68c0a5c7 | 338 | #define HCLGE_TQP_ID_S 2 |
5392902d | 339 | #define HCLGE_TQP_ID_M GENMASK(12, 2) |
0305b443 | 340 | #define HCLGE_INT_GL_IDX_S 13 |
5392902d | 341 | #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) |
68c0a5c7 | 342 | __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; |
0305b443 L |
343 | u8 vfid; |
344 | u8 rsv; | |
68c0a5c7 S |
345 | }; |
346 | ||
f9f07091 | 347 | #define HCLGE_MAX_TC_NUM 8 |
68c0a5c7 S |
348 | #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ |
349 | #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ | |
d44f9b63 | 350 | struct hclge_tx_buff_alloc_cmd { |
f9f07091 | 351 | __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; |
68c0a5c7 S |
352 | u8 tx_buff_rsv[8]; |
353 | }; | |
354 | ||
d44f9b63 | 355 | struct hclge_rx_priv_buff_cmd { |
f9f07091 | 356 | __le16 buf_num[HCLGE_MAX_TC_NUM]; |
b8c8bf47 YL |
357 | __le16 shared_buf; |
358 | u8 rsv[6]; | |
68c0a5c7 S |
359 | }; |
360 | ||
d44f9b63 | 361 | struct hclge_query_version_cmd { |
68c0a5c7 S |
362 | __le32 firmware; |
363 | __le32 firmware_rsv[5]; | |
364 | }; | |
365 | ||
366 | #define HCLGE_RX_PRIV_EN_B 15 | |
367 | #define HCLGE_TC_NUM_ONE_DESC 4 | |
368 | struct hclge_priv_wl { | |
369 | __le16 high; | |
370 | __le16 low; | |
371 | }; | |
372 | ||
373 | struct hclge_rx_priv_wl_buf { | |
374 | struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; | |
375 | }; | |
376 | ||
377 | struct hclge_rx_com_thrd { | |
378 | struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; | |
379 | }; | |
380 | ||
381 | struct hclge_rx_com_wl { | |
382 | struct hclge_priv_wl com_wl; | |
383 | }; | |
384 | ||
385 | struct hclge_waterline { | |
386 | u32 low; | |
387 | u32 high; | |
388 | }; | |
389 | ||
390 | struct hclge_tc_thrd { | |
391 | u32 low; | |
392 | u32 high; | |
393 | }; | |
394 | ||
395 | struct hclge_priv_buf { | |
396 | struct hclge_waterline wl; /* Waterline for low and high*/ | |
397 | u32 buf_size; /* TC private buffer size */ | |
9ffe79a9 | 398 | u32 tx_buf_size; |
68c0a5c7 S |
399 | u32 enable; /* Enable TC private buffer or not */ |
400 | }; | |
401 | ||
68c0a5c7 S |
402 | struct hclge_shared_buf { |
403 | struct hclge_waterline self; | |
404 | struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; | |
405 | u32 buf_size; | |
406 | }; | |
407 | ||
acf61ecd YL |
408 | struct hclge_pkt_buf_alloc { |
409 | struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; | |
410 | struct hclge_shared_buf s_buf; | |
411 | }; | |
412 | ||
68c0a5c7 | 413 | #define HCLGE_RX_COM_WL_EN_B 15 |
d44f9b63 | 414 | struct hclge_rx_com_wl_buf_cmd { |
68c0a5c7 S |
415 | __le16 high_wl; |
416 | __le16 low_wl; | |
417 | u8 rsv[20]; | |
418 | }; | |
419 | ||
420 | #define HCLGE_RX_PKT_EN_B 15 | |
d44f9b63 | 421 | struct hclge_rx_pkt_buf_cmd { |
68c0a5c7 S |
422 | __le16 high_pkt; |
423 | __le16 low_pkt; | |
424 | u8 rsv[20]; | |
425 | }; | |
426 | ||
427 | #define HCLGE_PF_STATE_DONE_B 0 | |
428 | #define HCLGE_PF_STATE_MAIN_B 1 | |
429 | #define HCLGE_PF_STATE_BOND_B 2 | |
430 | #define HCLGE_PF_STATE_MAC_N_B 6 | |
431 | #define HCLGE_PF_MAC_NUM_MASK 0x3 | |
432 | #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) | |
433 | #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) | |
d6ad7c53 GL |
434 | #define HCLGE_VF_RST_STATUS_CMD 4 |
435 | ||
d44f9b63 | 436 | struct hclge_func_status_cmd { |
d6ad7c53 | 437 | __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD]; |
68c0a5c7 S |
438 | u8 pf_state; |
439 | u8 mac_id; | |
440 | u8 rsv1; | |
441 | u8 pf_cnt_in_mac; | |
442 | u8 pf_num; | |
443 | u8 vf_num; | |
444 | u8 rsv[2]; | |
445 | }; | |
446 | ||
d44f9b63 | 447 | struct hclge_pf_res_cmd { |
68c0a5c7 S |
448 | __le16 tqp_num; |
449 | __le16 buf_size; | |
450 | __le16 msixcap_localid_ba_nic; | |
451 | __le16 msixcap_localid_ba_rocee; | |
375dd5e4 JS |
452 | #define HCLGE_MSIX_OFT_ROCEE_S 0 |
453 | #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) | |
68c0a5c7 | 454 | #define HCLGE_PF_VEC_NUM_S 0 |
c79301d8 | 455 | #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) |
68c0a5c7 S |
456 | __le16 pf_intr_vector_number; |
457 | __le16 pf_own_fun_number; | |
368686be YL |
458 | __le16 tx_buf_size; |
459 | __le16 dv_buf_size; | |
460 | __le32 rsv[2]; | |
68c0a5c7 S |
461 | }; |
462 | ||
463 | #define HCLGE_CFG_OFFSET_S 0 | |
5392902d | 464 | #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) |
68c0a5c7 | 465 | #define HCLGE_CFG_RD_LEN_S 24 |
5392902d | 466 | #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) |
68c0a5c7 S |
467 | #define HCLGE_CFG_RD_LEN_BYTES 16 |
468 | #define HCLGE_CFG_RD_LEN_UNIT 4 | |
469 | ||
470 | #define HCLGE_CFG_VMDQ_S 0 | |
5392902d | 471 | #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) |
68c0a5c7 | 472 | #define HCLGE_CFG_TC_NUM_S 8 |
5392902d | 473 | #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) |
68c0a5c7 | 474 | #define HCLGE_CFG_TQP_DESC_N_S 16 |
5392902d | 475 | #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) |
68c0a5c7 | 476 | #define HCLGE_CFG_PHY_ADDR_S 0 |
39e2151f | 477 | #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) |
68c0a5c7 | 478 | #define HCLGE_CFG_MEDIA_TP_S 8 |
5392902d | 479 | #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) |
68c0a5c7 | 480 | #define HCLGE_CFG_RX_BUF_LEN_S 16 |
5392902d | 481 | #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) |
68c0a5c7 | 482 | #define HCLGE_CFG_MAC_ADDR_H_S 0 |
5392902d | 483 | #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) |
68c0a5c7 | 484 | #define HCLGE_CFG_DEFAULT_SPEED_S 16 |
5392902d | 485 | #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) |
0e7a40cd PL |
486 | #define HCLGE_CFG_RSS_SIZE_S 24 |
487 | #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) | |
0979aa0b FL |
488 | #define HCLGE_CFG_SPEED_ABILITY_S 0 |
489 | #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) | |
39932473 JS |
490 | #define HCLGE_CFG_UMV_TBL_SPACE_S 16 |
491 | #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) | |
68c0a5c7 | 492 | |
d6ad7c53 GL |
493 | #define HCLGE_CFG_CMD_CNT 4 |
494 | ||
d44f9b63 | 495 | struct hclge_cfg_param_cmd { |
68c0a5c7 S |
496 | __le32 offset; |
497 | __le32 rsv; | |
d6ad7c53 | 498 | __le32 param[HCLGE_CFG_CMD_CNT]; |
68c0a5c7 S |
499 | }; |
500 | ||
501 | #define HCLGE_MAC_MODE 0x0 | |
502 | #define HCLGE_DESC_NUM 0x40 | |
503 | ||
504 | #define HCLGE_ALLOC_VALID_B 0 | |
d44f9b63 | 505 | struct hclge_vf_num_cmd { |
68c0a5c7 S |
506 | u8 alloc_valid; |
507 | u8 rsv[23]; | |
508 | }; | |
509 | ||
510 | #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 | |
511 | #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 | |
512 | #define HCLGE_RSS_HASH_KEY_NUM 16 | |
d44f9b63 | 513 | struct hclge_rss_config_cmd { |
68c0a5c7 S |
514 | u8 hash_config; |
515 | u8 rsv[7]; | |
516 | u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; | |
517 | }; | |
518 | ||
d44f9b63 | 519 | struct hclge_rss_input_tuple_cmd { |
68c0a5c7 S |
520 | u8 ipv4_tcp_en; |
521 | u8 ipv4_udp_en; | |
522 | u8 ipv4_sctp_en; | |
523 | u8 ipv4_fragment_en; | |
524 | u8 ipv6_tcp_en; | |
525 | u8 ipv6_udp_en; | |
526 | u8 ipv6_sctp_en; | |
527 | u8 ipv6_fragment_en; | |
528 | u8 rsv[16]; | |
529 | }; | |
530 | ||
531 | #define HCLGE_RSS_CFG_TBL_SIZE 16 | |
532 | ||
d44f9b63 | 533 | struct hclge_rss_indirection_table_cmd { |
a90bb9a5 YL |
534 | __le16 start_table_index; |
535 | __le16 rss_set_bitmap; | |
68c0a5c7 S |
536 | u8 rsv[4]; |
537 | u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; | |
538 | }; | |
539 | ||
540 | #define HCLGE_RSS_TC_OFFSET_S 0 | |
5392902d | 541 | #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) |
68c0a5c7 | 542 | #define HCLGE_RSS_TC_SIZE_S 12 |
5392902d | 543 | #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) |
68c0a5c7 | 544 | #define HCLGE_RSS_TC_VALID_B 15 |
d44f9b63 | 545 | struct hclge_rss_tc_mode_cmd { |
a90bb9a5 | 546 | __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; |
68c0a5c7 S |
547 | u8 rsv[8]; |
548 | }; | |
549 | ||
c79301d8 JS |
550 | #define HCLGE_LINK_STATUS_UP_B 0 |
551 | #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) | |
d44f9b63 | 552 | struct hclge_link_status_cmd { |
68c0a5c7 S |
553 | u8 status; |
554 | u8 rsv[23]; | |
555 | }; | |
556 | ||
557 | struct hclge_promisc_param { | |
558 | u8 vf_id; | |
559 | u8 enable; | |
560 | }; | |
561 | ||
96c0e861 PL |
562 | #define HCLGE_PROMISC_TX_EN_B BIT(4) |
563 | #define HCLGE_PROMISC_RX_EN_B BIT(5) | |
68c0a5c7 S |
564 | #define HCLGE_PROMISC_EN_B 1 |
565 | #define HCLGE_PROMISC_EN_ALL 0x7 | |
566 | #define HCLGE_PROMISC_EN_UC 0x1 | |
567 | #define HCLGE_PROMISC_EN_MC 0x2 | |
568 | #define HCLGE_PROMISC_EN_BC 0x4 | |
d44f9b63 | 569 | struct hclge_promisc_cfg_cmd { |
68c0a5c7 S |
570 | u8 flag; |
571 | u8 vf_id; | |
572 | __le16 rsv0; | |
573 | u8 rsv1[20]; | |
574 | }; | |
575 | ||
576 | enum hclge_promisc_type { | |
577 | HCLGE_UNICAST = 1, | |
578 | HCLGE_MULTICAST = 2, | |
579 | HCLGE_BROADCAST = 3, | |
580 | }; | |
581 | ||
582 | #define HCLGE_MAC_TX_EN_B 6 | |
583 | #define HCLGE_MAC_RX_EN_B 7 | |
584 | #define HCLGE_MAC_PAD_TX_B 11 | |
585 | #define HCLGE_MAC_PAD_RX_B 12 | |
586 | #define HCLGE_MAC_1588_TX_B 13 | |
587 | #define HCLGE_MAC_1588_RX_B 14 | |
588 | #define HCLGE_MAC_APP_LP_B 15 | |
589 | #define HCLGE_MAC_LINE_LP_B 16 | |
590 | #define HCLGE_MAC_FCS_TX_B 17 | |
591 | #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 | |
592 | #define HCLGE_MAC_RX_FCS_STRIP_B 19 | |
593 | #define HCLGE_MAC_RX_FCS_B 20 | |
594 | #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 | |
595 | #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 | |
596 | ||
d44f9b63 | 597 | struct hclge_config_mac_mode_cmd { |
68c0a5c7 S |
598 | __le32 txrx_pad_fcs_loop_en; |
599 | u8 rsv[20]; | |
600 | }; | |
601 | ||
427a7bff HT |
602 | struct hclge_pf_rst_sync_cmd { |
603 | #define HCLGE_PF_RST_ALL_VF_RDY_B 0 | |
604 | u8 all_vf_ready; | |
605 | u8 rsv[23]; | |
606 | }; | |
607 | ||
68c0a5c7 | 608 | #define HCLGE_CFG_SPEED_S 0 |
5392902d | 609 | #define HCLGE_CFG_SPEED_M GENMASK(5, 0) |
68c0a5c7 S |
610 | |
611 | #define HCLGE_CFG_DUPLEX_B 7 | |
612 | #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) | |
613 | ||
d44f9b63 | 614 | struct hclge_config_mac_speed_dup_cmd { |
68c0a5c7 S |
615 | u8 speed_dup; |
616 | ||
617 | #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 | |
618 | u8 mac_change_fec_en; | |
619 | u8 rsv[22]; | |
620 | }; | |
621 | ||
5392902d | 622 | #define HCLGE_RING_ID_MASK GENMASK(9, 0) |
68c0a5c7 S |
623 | #define HCLGE_TQP_ENABLE_B 0 |
624 | ||
625 | #define HCLGE_MAC_CFG_AN_EN_B 0 | |
626 | #define HCLGE_MAC_CFG_AN_INT_EN_B 1 | |
627 | #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 | |
628 | #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 | |
629 | #define HCLGE_MAC_CFG_AN_RST_B 4 | |
630 | ||
631 | #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) | |
632 | ||
d44f9b63 | 633 | struct hclge_config_auto_neg_cmd { |
68c0a5c7 S |
634 | __le32 cfg_an_cmd_flag; |
635 | u8 rsv[20]; | |
636 | }; | |
637 | ||
88d10bd6 JS |
638 | struct hclge_sfp_info_cmd { |
639 | __le32 speed; | |
640 | u8 query_type; /* 0: sfp speed, 1: active speed */ | |
641 | u8 active_fec; | |
642 | u8 autoneg; /* autoneg state */ | |
643 | u8 autoneg_ability; /* whether support autoneg */ | |
644 | __le32 speed_ability; /* speed ability for current media */ | |
645 | __le32 module_type; | |
646 | u8 rsv[8]; | |
5d497936 PL |
647 | }; |
648 | ||
7e6ec914 JS |
649 | #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0 |
650 | #define HCLGE_MAC_CFG_FEC_MODE_S 1 | |
651 | #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1) | |
652 | #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0 | |
653 | #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1 | |
654 | ||
655 | #define HCLGE_MAC_FEC_OFF 0 | |
656 | #define HCLGE_MAC_FEC_BASER 1 | |
657 | #define HCLGE_MAC_FEC_RS 2 | |
658 | struct hclge_config_fec_cmd { | |
659 | u8 fec_mode; | |
660 | u8 default_config; | |
661 | u8 rsv[22]; | |
662 | }; | |
663 | ||
68c0a5c7 S |
664 | #define HCLGE_MAC_UPLINK_PORT 0x100 |
665 | ||
d44f9b63 | 666 | struct hclge_config_max_frm_size_cmd { |
68c0a5c7 | 667 | __le16 max_frm_size; |
8fc7346c JS |
668 | u8 min_frm_size; |
669 | u8 rsv[21]; | |
68c0a5c7 S |
670 | }; |
671 | ||
672 | enum hclge_mac_vlan_tbl_opcode { | |
673 | HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ | |
674 | HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ | |
675 | HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ | |
676 | HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ | |
677 | }; | |
678 | ||
b37ce587 YM |
679 | enum hclge_mac_vlan_add_resp_code { |
680 | HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ | |
681 | HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ | |
682 | }; | |
683 | ||
f8a91784 JS |
684 | #define HCLGE_MAC_VLAN_BIT0_EN_B 0 |
685 | #define HCLGE_MAC_VLAN_BIT1_EN_B 1 | |
686 | #define HCLGE_MAC_EPORT_SW_EN_B 12 | |
687 | #define HCLGE_MAC_EPORT_TYPE_B 11 | |
688 | #define HCLGE_MAC_EPORT_VFID_S 3 | |
5392902d | 689 | #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) |
f8a91784 | 690 | #define HCLGE_MAC_EPORT_PFID_S 0 |
5392902d | 691 | #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) |
d44f9b63 | 692 | struct hclge_mac_vlan_tbl_entry_cmd { |
68c0a5c7 S |
693 | u8 flags; |
694 | u8 resp_code; | |
695 | __le16 vlan_tag; | |
696 | __le32 mac_addr_hi32; | |
697 | __le16 mac_addr_lo16; | |
698 | __le16 rsv1; | |
699 | u8 entry_type; | |
700 | u8 mc_mac_en; | |
701 | __le16 egress_port; | |
702 | __le16 egress_queue; | |
703 | u8 rsv2[6]; | |
704 | }; | |
705 | ||
39932473 JS |
706 | #define HCLGE_UMV_SPC_ALC_B 0 |
707 | struct hclge_umv_spc_alc_cmd { | |
708 | u8 allocate; | |
709 | u8 rsv1[3]; | |
710 | __le32 space_size; | |
711 | u8 rsv2[16]; | |
712 | }; | |
713 | ||
f5aac71c FL |
714 | #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) |
715 | #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) | |
716 | #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) | |
f5aac71c FL |
717 | |
718 | struct hclge_mac_mgr_tbl_entry_cmd { | |
719 | u8 flags; | |
720 | u8 resp_code; | |
721 | __le16 vlan_tag; | |
0e02a53d | 722 | u8 mac_addr[ETH_ALEN]; |
f5aac71c FL |
723 | __le16 rsv1; |
724 | __le16 ethter_type; | |
725 | __le16 egress_port; | |
726 | __le16 egress_queue; | |
727 | u8 sw_port_id_aware; | |
728 | u8 rsv2; | |
729 | u8 i_port_bitmap; | |
730 | u8 i_port_direction; | |
731 | u8 rsv3[2]; | |
732 | }; | |
733 | ||
d44f9b63 | 734 | struct hclge_mac_vlan_add_cmd { |
68c0a5c7 S |
735 | __le16 flags; |
736 | __le16 mac_addr_hi16; | |
737 | __le32 mac_addr_lo32; | |
738 | __le32 mac_addr_msk_hi32; | |
739 | __le16 mac_addr_msk_lo16; | |
740 | __le16 vlan_tag; | |
741 | __le16 ingress_port; | |
742 | __le16 egress_port; | |
743 | u8 rsv[4]; | |
744 | }; | |
745 | ||
746 | #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 | |
d44f9b63 | 747 | struct hclge_mac_vlan_remove_cmd { |
68c0a5c7 S |
748 | __le16 flags; |
749 | __le16 mac_addr_hi16; | |
750 | __le32 mac_addr_lo32; | |
751 | __le32 mac_addr_msk_hi32; | |
752 | __le16 mac_addr_msk_lo16; | |
753 | __le16 vlan_tag; | |
754 | __le16 ingress_port; | |
755 | __le16 egress_port; | |
756 | u8 rsv[4]; | |
757 | }; | |
758 | ||
d44f9b63 | 759 | struct hclge_vlan_filter_ctrl_cmd { |
68c0a5c7 S |
760 | u8 vlan_type; |
761 | u8 vlan_fe; | |
30ebc576 JS |
762 | u8 rsv1[2]; |
763 | u8 vf_id; | |
764 | u8 rsv2[19]; | |
68c0a5c7 S |
765 | }; |
766 | ||
d6ad7c53 GL |
767 | #define HCLGE_VLAN_ID_OFFSET_STEP 160 |
768 | #define HCLGE_VLAN_BYTE_SIZE 8 | |
769 | #define HCLGE_VLAN_OFFSET_BITMAP \ | |
770 | (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE) | |
771 | ||
d44f9b63 | 772 | struct hclge_vlan_filter_pf_cfg_cmd { |
68c0a5c7 S |
773 | u8 vlan_offset; |
774 | u8 vlan_cfg; | |
775 | u8 rsv[2]; | |
d6ad7c53 | 776 | u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP]; |
68c0a5c7 S |
777 | }; |
778 | ||
d6ad7c53 GL |
779 | #define HCLGE_MAX_VF_BYTES 16 |
780 | ||
d44f9b63 | 781 | struct hclge_vlan_filter_vf_cfg_cmd { |
a90bb9a5 | 782 | __le16 vlan_id; |
68c0a5c7 S |
783 | u8 resp_code; |
784 | u8 rsv; | |
785 | u8 vlan_cfg; | |
786 | u8 rsv1[3]; | |
d6ad7c53 | 787 | u8 vf_bitmap[HCLGE_MAX_VF_BYTES]; |
68c0a5c7 S |
788 | }; |
789 | ||
dd2956ea YM |
790 | #define HCLGE_SWITCH_ANTI_SPOOF_B 0U |
791 | #define HCLGE_SWITCH_ALW_LPBK_B 1U | |
792 | #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U | |
793 | #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U | |
794 | #define HCLGE_SWITCH_NO_MASK 0x0 | |
795 | #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE | |
796 | #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD | |
797 | #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB | |
798 | #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7 | |
799 | ||
800 | struct hclge_mac_vlan_switch_cmd { | |
801 | u8 roce_sel; | |
802 | u8 rsv1[3]; | |
803 | __le32 func_id; | |
804 | u8 switch_param; | |
805 | u8 rsv2[3]; | |
806 | u8 param_mask; | |
807 | u8 rsv3[11]; | |
808 | }; | |
809 | ||
810 | enum hclge_mac_vlan_cfg_sel { | |
811 | HCLGE_MAC_VLAN_NIC_SEL = 0, | |
812 | HCLGE_MAC_VLAN_ROCE_SEL, | |
813 | }; | |
814 | ||
dcb35cce PL |
815 | #define HCLGE_ACCEPT_TAG1_B 0 |
816 | #define HCLGE_ACCEPT_UNTAG1_B 1 | |
5f6ea83f PL |
817 | #define HCLGE_PORT_INS_TAG1_EN_B 2 |
818 | #define HCLGE_PORT_INS_TAG2_EN_B 3 | |
819 | #define HCLGE_CFG_NIC_ROCE_SEL_B 4 | |
dcb35cce PL |
820 | #define HCLGE_ACCEPT_TAG2_B 5 |
821 | #define HCLGE_ACCEPT_UNTAG2_B 6 | |
d6ad7c53 | 822 | #define HCLGE_VF_NUM_PER_BYTE 8 |
dcb35cce | 823 | |
5f6ea83f PL |
824 | struct hclge_vport_vtag_tx_cfg_cmd { |
825 | u8 vport_vlan_cfg; | |
826 | u8 vf_offset; | |
827 | u8 rsv1[2]; | |
828 | __le16 def_vlan_tag1; | |
829 | __le16 def_vlan_tag2; | |
d6ad7c53 | 830 | u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; |
5f6ea83f PL |
831 | u8 rsv2[8]; |
832 | }; | |
833 | ||
834 | #define HCLGE_REM_TAG1_EN_B 0 | |
835 | #define HCLGE_REM_TAG2_EN_B 1 | |
836 | #define HCLGE_SHOW_TAG1_EN_B 2 | |
837 | #define HCLGE_SHOW_TAG2_EN_B 3 | |
838 | struct hclge_vport_vtag_rx_cfg_cmd { | |
839 | u8 vport_vlan_cfg; | |
840 | u8 vf_offset; | |
841 | u8 rsv1[6]; | |
d6ad7c53 | 842 | u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; |
5f6ea83f PL |
843 | u8 rsv2[8]; |
844 | }; | |
845 | ||
846 | struct hclge_tx_vlan_type_cfg_cmd { | |
847 | __le16 ot_vlan_type; | |
848 | __le16 in_vlan_type; | |
849 | u8 rsv[20]; | |
850 | }; | |
851 | ||
852 | struct hclge_rx_vlan_type_cfg_cmd { | |
853 | __le16 ot_fst_vlan_type; | |
854 | __le16 ot_sec_vlan_type; | |
855 | __le16 in_fst_vlan_type; | |
856 | __le16 in_sec_vlan_type; | |
857 | u8 rsv[16]; | |
858 | }; | |
859 | ||
d44f9b63 | 860 | struct hclge_cfg_com_tqp_queue_cmd { |
68c0a5c7 S |
861 | __le16 tqp_id; |
862 | __le16 stream_id; | |
863 | u8 enable; | |
864 | u8 rsv[19]; | |
865 | }; | |
866 | ||
d44f9b63 | 867 | struct hclge_cfg_tx_queue_pointer_cmd { |
68c0a5c7 S |
868 | __le16 tqp_id; |
869 | __le16 tx_tail; | |
870 | __le16 tx_head; | |
871 | __le16 fbd_num; | |
872 | __le16 ring_offset; | |
873 | u8 rsv[14]; | |
874 | }; | |
875 | ||
7737f1fb | 876 | #pragma pack(1) |
877 | struct hclge_mac_ethertype_idx_rd_cmd { | |
878 | u8 flags; | |
879 | u8 resp_code; | |
880 | __le16 vlan_tag; | |
d6ad7c53 | 881 | u8 mac_addr[ETH_ALEN]; |
7737f1fb | 882 | __le16 index; |
883 | __le16 ethter_type; | |
884 | __le16 egress_port; | |
885 | __le16 egress_queue; | |
886 | __le16 rev0; | |
887 | u8 i_port_bitmap; | |
888 | u8 i_port_direction; | |
889 | u8 rev1[2]; | |
890 | }; | |
891 | ||
892 | #pragma pack() | |
893 | ||
68c0a5c7 | 894 | #define HCLGE_TSO_MSS_MIN_S 0 |
5392902d | 895 | #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) |
68c0a5c7 S |
896 | |
897 | #define HCLGE_TSO_MSS_MAX_S 16 | |
5392902d | 898 | #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) |
68c0a5c7 | 899 | |
d44f9b63 | 900 | struct hclge_cfg_tso_status_cmd { |
68c0a5c7 S |
901 | __le16 tso_mss_min; |
902 | __le16 tso_mss_max; | |
903 | u8 rsv[20]; | |
904 | }; | |
905 | ||
b26a6fea PL |
906 | #define HCLGE_GRO_EN_B 0 |
907 | struct hclge_cfg_gro_status_cmd { | |
908 | __le16 gro_en; | |
909 | u8 rsv[22]; | |
910 | }; | |
911 | ||
68c0a5c7 S |
912 | #define HCLGE_TSO_MSS_MIN 256 |
913 | #define HCLGE_TSO_MSS_MAX 9668 | |
914 | ||
915 | #define HCLGE_TQP_RESET_B 0 | |
d44f9b63 | 916 | struct hclge_reset_tqp_queue_cmd { |
68c0a5c7 S |
917 | __le16 tqp_id; |
918 | u8 reset_req; | |
919 | u8 ready_to_reset; | |
920 | u8 rsv[20]; | |
921 | }; | |
922 | ||
4ed340ab L |
923 | #define HCLGE_CFG_RESET_MAC_B 3 |
924 | #define HCLGE_CFG_RESET_FUNC_B 7 | |
925 | struct hclge_reset_cmd { | |
926 | u8 mac_func_reset; | |
927 | u8 fun_reset_vfid; | |
928 | u8 rsv[22]; | |
929 | }; | |
5fd50ac3 | 930 | |
72e2fb07 HT |
931 | #define HCLGE_PF_RESET_DONE_BIT BIT(0) |
932 | ||
933 | struct hclge_pf_rst_done_cmd { | |
934 | u8 pf_rst_done; | |
935 | u8 rsv[23]; | |
936 | }; | |
937 | ||
5fd50ac3 | 938 | #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) |
4dc13b96 | 939 | #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) |
5fd50ac3 PL |
940 | #define HCLGE_CMD_SERDES_DONE_B BIT(0) |
941 | #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) | |
942 | struct hclge_serdes_lb_cmd { | |
943 | u8 mask; | |
944 | u8 enable; | |
945 | u8 result; | |
946 | u8 rsv[21]; | |
947 | }; | |
948 | ||
68c0a5c7 S |
949 | #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ |
950 | #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ | |
951 | #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ | |
d221df4e | 952 | #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ |
9e15be90 | 953 | #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ |
68c0a5c7 S |
954 | |
955 | #define HCLGE_TYPE_CRQ 0 | |
956 | #define HCLGE_TYPE_CSQ 1 | |
957 | #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 | |
958 | #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 | |
959 | #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 | |
960 | #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 | |
961 | #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 | |
962 | #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 | |
963 | #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c | |
964 | #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 | |
965 | #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 | |
966 | #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 | |
6b428b4f HT |
967 | |
968 | /* this bit indicates that the driver is ready for hardware reset */ | |
969 | #define HCLGE_NIC_SW_RST_RDY_B 16 | |
970 | #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B) | |
971 | ||
68c0a5c7 S |
972 | #define HCLGE_NIC_CMQ_DESC_NUM 1024 |
973 | #define HCLGE_NIC_CMQ_DESC_NUM_S 3 | |
974 | ||
07f8e940 JS |
975 | #define HCLGE_LED_LOCATE_STATE_S 0 |
976 | #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) | |
977 | ||
978 | struct hclge_set_led_state_cmd { | |
f6f75abc | 979 | u8 rsv1[3]; |
07f8e940 | 980 | u8 locate_led_config; |
f6f75abc | 981 | u8 rsv2[20]; |
07f8e940 JS |
982 | }; |
983 | ||
d695964d JS |
984 | struct hclge_get_fd_mode_cmd { |
985 | u8 mode; | |
986 | u8 enable; | |
987 | u8 rsv[22]; | |
988 | }; | |
989 | ||
990 | struct hclge_get_fd_allocation_cmd { | |
991 | __le32 stage1_entry_num; | |
992 | __le32 stage2_entry_num; | |
993 | __le16 stage1_counter_num; | |
994 | __le16 stage2_counter_num; | |
995 | u8 rsv[12]; | |
996 | }; | |
997 | ||
998 | struct hclge_set_fd_key_config_cmd { | |
999 | u8 stage; | |
1000 | u8 key_select; | |
1001 | u8 inner_sipv6_word_en; | |
1002 | u8 inner_dipv6_word_en; | |
1003 | u8 outer_sipv6_word_en; | |
1004 | u8 outer_dipv6_word_en; | |
1005 | u8 rsv1[2]; | |
1006 | __le32 tuple_mask; | |
1007 | __le32 meta_data_mask; | |
1008 | u8 rsv2[8]; | |
1009 | }; | |
1010 | ||
11732868 JS |
1011 | #define HCLGE_FD_EPORT_SW_EN_B 0 |
1012 | struct hclge_fd_tcam_config_1_cmd { | |
1013 | u8 stage; | |
1014 | u8 xy_sel; | |
1015 | u8 port_info; | |
1016 | u8 rsv1[1]; | |
1017 | __le32 index; | |
1018 | u8 entry_vld; | |
1019 | u8 rsv2[7]; | |
1020 | u8 tcam_data[8]; | |
1021 | }; | |
1022 | ||
1023 | struct hclge_fd_tcam_config_2_cmd { | |
1024 | u8 tcam_data[24]; | |
1025 | }; | |
1026 | ||
1027 | struct hclge_fd_tcam_config_3_cmd { | |
1028 | u8 tcam_data[20]; | |
1029 | u8 rsv[4]; | |
1030 | }; | |
1031 | ||
1032 | #define HCLGE_FD_AD_DROP_B 0 | |
1033 | #define HCLGE_FD_AD_DIRECT_QID_B 1 | |
1034 | #define HCLGE_FD_AD_QID_S 2 | |
1035 | #define HCLGE_FD_AD_QID_M GENMASK(12, 2) | |
1036 | #define HCLGE_FD_AD_USE_COUNTER_B 12 | |
1037 | #define HCLGE_FD_AD_COUNTER_NUM_S 13 | |
1038 | #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) | |
1039 | #define HCLGE_FD_AD_NXT_STEP_B 20 | |
1040 | #define HCLGE_FD_AD_NXT_KEY_S 21 | |
1041 | #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) | |
1042 | #define HCLGE_FD_AD_WR_RULE_ID_B 0 | |
1043 | #define HCLGE_FD_AD_RULE_ID_S 1 | |
1044 | #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) | |
1045 | ||
1046 | struct hclge_fd_ad_config_cmd { | |
1047 | u8 stage; | |
1048 | u8 rsv1[3]; | |
1049 | __le32 index; | |
1050 | __le64 ad_data; | |
1051 | u8 rsv2[8]; | |
1052 | }; | |
1053 | ||
33a90e2f ZL |
1054 | struct hclge_get_m7_bd_cmd { |
1055 | __le32 bd_num; | |
1056 | u8 rsv[20]; | |
1057 | }; | |
1058 | ||
0cd86182 WL |
1059 | struct hclge_query_ppu_pf_other_int_dfx_cmd { |
1060 | __le16 over_8bd_no_fe_qid; | |
1061 | __le16 over_8bd_no_fe_vf_id; | |
1062 | __le16 tso_mss_cmp_min_err_qid; | |
1063 | __le16 tso_mss_cmp_min_err_vf_id; | |
1064 | __le16 tso_mss_cmp_max_err_qid; | |
1065 | __le16 tso_mss_cmp_max_err_vf_id; | |
1066 | __le16 tx_rd_fbd_poison_qid; | |
1067 | __le16 tx_rd_fbd_poison_vf_id; | |
1068 | __le16 rx_rd_fbd_poison_qid; | |
1069 | __le16 rx_rd_fbd_poison_vf_id; | |
1070 | u8 rsv[4]; | |
1071 | }; | |
1072 | ||
ed8fb4b2 | 1073 | #define HCLGE_LINK_EVENT_REPORT_EN_B 0 |
b18bf305 | 1074 | #define HCLGE_NCSI_ERROR_REPORT_EN_B 1 |
ed8fb4b2 JS |
1075 | struct hclge_firmware_compat_cmd { |
1076 | __le32 compat; | |
1077 | u8 rsv[20]; | |
1078 | }; | |
1079 | ||
68c0a5c7 S |
1080 | int hclge_cmd_init(struct hclge_dev *hdev); |
1081 | static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) | |
1082 | { | |
1083 | writel(value, base + reg); | |
1084 | } | |
1085 | ||
1086 | #define hclge_write_dev(a, reg, value) \ | |
1087 | hclge_write_reg((a)->io_base, (reg), (value)) | |
1088 | #define hclge_read_dev(a, reg) \ | |
1089 | hclge_read_reg((a)->io_base, (reg)) | |
1090 | ||
1091 | static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) | |
1092 | { | |
1093 | u8 __iomem *reg_addr = READ_ONCE(base); | |
1094 | ||
1095 | return readl(reg_addr + reg); | |
1096 | } | |
1097 | ||
1098 | #define HCLGE_SEND_SYNC(flag) \ | |
1099 | ((flag) & HCLGE_CMD_FLAG_NO_INTR) | |
1100 | ||
1101 | struct hclge_hw; | |
1102 | int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); | |
1103 | void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, | |
1104 | enum hclge_opcode_type opcode, bool is_read); | |
f7db940a | 1105 | void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); |
68c0a5c7 | 1106 | |
68c0a5c7 S |
1107 | enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, |
1108 | struct hclge_desc *desc); | |
1109 | enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, | |
1110 | struct hclge_desc *desc); | |
1111 | ||
232d0d55 | 1112 | void hclge_cmd_uninit(struct hclge_dev *hdev); |
3efb960f | 1113 | int hclge_cmd_queue_init(struct hclge_dev *hdev); |
68c0a5c7 | 1114 | #endif |