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net: fec: clear all interrupt events to support i.MX6SX
[linux-2.6-block.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
7dd6a2aa 5 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
562d2f8c
GU		 15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 19 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 20 *
230dec61 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 22 */
23
1da177e4
LT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
27#include <linux/ptrace.h>
28#include <linux/errno.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
1da177e4
LT		 32#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
4c09eed9
JB		 36#include <linux/in.h>
37#include <linux/ip.h>
38#include <net/ip.h>
79f33912 39#include <net/tso.h>
4c09eed9
JB		 40#include <linux/tcp.h>
41#include <linux/udp.h>
42#include <linux/icmp.h>
1da177e4
LT		 43#include <linux/spinlock.h>
44#include <linux/workqueue.h>
45#include <linux/bitops.h>
6f501b17
SH		 46#include <linux/io.h>
47#include <linux/irq.h>
196719ec 48#include <linux/clk.h>
ead73183 49#include <linux/platform_device.h>
e6b043d5 50#include <linux/phy.h>
5eb32bd0 51#include <linux/fec.h>
ca2cc333
SG		 52#include <linux/of.h>
53#include <linux/of_device.h>
54#include <linux/of_gpio.h>
407066f8 55#include <linux/of_mdio.h>
ca2cc333 56#include <linux/of_net.h>
5fa9c0fe 57#include <linux/regulator/consumer.h>
cdffcf1b 58#include <linux/if_vlan.h>
a68ab98e 59#include <linux/pinctrl/consumer.h>
c259c132 60#include <linux/prefetch.h>
1da177e4 61
080853af 62#include <asm/cacheflush.h>
196719ec 63
1da177e4 64#include "fec.h"
1da177e4 65
772e42b0 66static void set_multicast_list(struct net_device *ndev);
d851b47b 67static void fec_enet_itr_coal_init(struct net_device *ndev);
772e42b0 68
b5680e0b
SG		 69#define DRIVER_NAME "fec"
70
4d494cdc
FD		 71#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
72
baa70a5c
FL		 73/* Pause frame feild and FIFO threshold */
74#define FEC_ENET_FCE (1 << 5)
75#define FEC_ENET_RSEM_V 0x84
76#define FEC_ENET_RSFL_V 16
77#define FEC_ENET_RAEM_V 0x8
78#define FEC_ENET_RAFL_V 0x8
79#define FEC_ENET_OPD_V 0xFFF0
80
b5680e0b
SG		 81static struct platform_device_id fec_devtype[] = {
82 {
0ca1e290 83 /* keep it for coldfire */
b5680e0b
SG		 84 .name = DRIVER_NAME,
85 .driver_data = 0,
0ca1e290
SG		 86 }, {
87 .name = "imx25-fec",
88 .driver_data = FEC_QUIRK_USE_GASKET,
89 }, {
90 .name = "imx27-fec",
91 .driver_data = 0,
b5680e0b
SG		 92 }, {
93 .name = "imx28-fec",
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
230dec61
SG		 95 }, {
96 .name = "imx6q-fec",
ff43da86 97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 98 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
03191656 99 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
ca7c4a45 100 }, {
36803542 101 .name = "mvf600-fec",
ca7c4a45 102 .driver_data = FEC_QUIRK_ENET_MAC,
95a77470
FD		 103 }, {
104 .name = "imx6sx-fec",
105 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
106 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
f88c7ede 107 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
28b5f058 108 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
0ca1e290
SG		 109 }, {
110 /* sentinel */
111 }
b5680e0b 112};
0ca1e290 113MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 114
ca2cc333 115enum imx_fec_type {
a7dd3219 116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 117 IMX27_FEC, /* runs on i.mx27/35/51 */
118 IMX28_FEC,
230dec61 119 IMX6Q_FEC,
36803542 120 MVF600_FEC,
ba593e00 121 IMX6SX_FEC,
ca2cc333
SG		 122};
123
124static const struct of_device_id fec_dt_ids[] = {
125 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
126 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
127 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 128 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 129 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ba593e00 130 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
ca2cc333
SG		 131 { /* sentinel */ }
132};
133MODULE_DEVICE_TABLE(of, fec_dt_ids);
134
49da97dc
SG		 135static unsigned char macaddr[ETH_ALEN];
136module_param_array(macaddr, byte, NULL, 0);
137MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 138
49da97dc 139#if defined(CONFIG_M5272)
1da177e4
LT		 140/*
141 * Some hardware gets it MAC address out of local flash memory.
142 * if this is non-zero then assume it is the address to get MAC from.
143 */
144#if defined(CONFIG_NETtel)
145#define FEC_FLASHMAC 0xf0006006
146#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
147#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 148#elif defined(CONFIG_CANCam)
149#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 150#elif defined (CONFIG_M5272C3)
151#define FEC_FLASHMAC (0xffe04000 + 4)
152#elif defined(CONFIG_MOD5272)
a7dd3219 153#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 154#else
155#define FEC_FLASHMAC 0
156#endif
43be6366 157#endif /* CONFIG_M5272 */
ead73183 158
cdffcf1b 159/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
1da177e4 160 */
cdffcf1b 161#define PKT_MAXBUF_SIZE 1522
1da177e4 162#define PKT_MINBUF_SIZE 64
cdffcf1b 163#define PKT_MAXBLR_SIZE 1536
1da177e4 164
4c09eed9
JB		 165/* FEC receive acceleration */
166#define FEC_RACC_IPDIS (1 << 1)
167#define FEC_RACC_PRODIS (1 << 2)
168#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
169
1da177e4 170/*
6b265293 171 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 172 * size bits. Other FEC hardware does not, so we need to take that into
173 * account when setting it.
174 */
562d2f8c 175#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
085e79ed 176 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
1da177e4
LT		 177#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
178#else
179#define OPT_FRAME_SIZE 0
180#endif
181
e6b043d5
BW		 182/* FEC MII MMFR bits definition */
183#define FEC_MMFR_ST (1 << 30)
184#define FEC_MMFR_OP_READ (2 << 28)
185#define FEC_MMFR_OP_WRITE (1 << 28)
186#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
187#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
188#define FEC_MMFR_TA (2 << 16)
189#define FEC_MMFR_DATA(v) (v & 0xffff)
1da177e4 190
c3b084c2 191#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 192
22f6b860
SH		 193/* Transmitter timeout */
194#define TX_TIMEOUT (2 * HZ)
1da177e4 195
baa70a5c
FL		 196#define FEC_PAUSE_FLAG_AUTONEG 0x1
197#define FEC_PAUSE_FLAG_ENABLE 0x2
198
1b7bde6d
NA		 199#define COPYBREAK_DEFAULT 256
200
79f33912
NA		 201#define TSO_HEADER_SIZE 128
202/* Max number of allowed TCP segments for software TSO */
203#define FEC_MAX_TSO_SEGS 100
204#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
205
206#define IS_TSO_HEADER(txq, addr) \
207 ((addr >= txq->tso_hdrs_dma) && \
208 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
209
e163cc97
LW		 210static int mii_cnt;
211
36e24e2e 212static inline
4d494cdc
FD		 213struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
214 struct fec_enet_private *fep,
215 int queue_id)
ff43da86 216{
36e24e2e
DFB		 217 struct bufdesc *new_bd = bdp + 1;
218 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
4d494cdc
FD		 219 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
220 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
36e24e2e
DFB		 221 struct bufdesc_ex *ex_base;
222 struct bufdesc *base;
223 int ring_size;
224
4d494cdc
FD		 225 if (bdp >= txq->tx_bd_base) {
226 base = txq->tx_bd_base;
227 ring_size = txq->tx_ring_size;
228 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
36e24e2e 229 } else {
4d494cdc
FD		 230 base = rxq->rx_bd_base;
231 ring_size = rxq->rx_ring_size;
232 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
36e24e2e
DFB		 233 }
234
235 if (fep->bufdesc_ex)
236 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
237 ex_base : ex_new_bd);
ff43da86 238 else
36e24e2e
DFB		 239 return (new_bd >= (base + ring_size)) ?
240 base : new_bd;
ff43da86
FL		 241}
242
36e24e2e 243static inline
4d494cdc
FD		 244struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
245 struct fec_enet_private *fep,
246 int queue_id)
ff43da86 247{
36e24e2e
DFB		 248 struct bufdesc *new_bd = bdp - 1;
249 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
4d494cdc
FD		 250 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
251 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
36e24e2e
DFB		 252 struct bufdesc_ex *ex_base;
253 struct bufdesc *base;
254 int ring_size;
255
4d494cdc
FD		 256 if (bdp >= txq->tx_bd_base) {
257 base = txq->tx_bd_base;
258 ring_size = txq->tx_ring_size;
259 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
36e24e2e 260 } else {
4d494cdc
FD		 261 base = rxq->rx_bd_base;
262 ring_size = rxq->rx_ring_size;
263 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
36e24e2e
DFB		 264 }
265
266 if (fep->bufdesc_ex)
267 return (struct bufdesc *)((ex_new_bd < ex_base) ?
268 (ex_new_bd + ring_size) : ex_new_bd);
ff43da86 269 else
36e24e2e 270 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
ff43da86
FL		 271}
272
61a4427b
NA		 273static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
274 struct fec_enet_private *fep)
275{
276 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
277}
278
4d494cdc
FD		 279static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
280 struct fec_enet_priv_tx_q *txq)
6e909283
NA		 281{
282 int entries;
283
4d494cdc
FD		 284 entries = ((const char *)txq->dirty_tx -
285 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
6e909283 286
4d494cdc 287 return entries > 0 ? entries : entries + txq->tx_ring_size;
6e909283
NA		 288}
289
c20e599b 290static void swap_buffer(void *bufaddr, int len)
b5680e0b
SG		 291{
292 int i;
293 unsigned int *buf = bufaddr;
294
7b487d07 295 for (i = 0; i < len; i += 4, buf++)
e453789a 296 swab32s(buf);
b5680e0b
SG		 297}
298
1310b544
LW		 299static void swap_buffer2(void *dst_buf, void *src_buf, int len)
300{
301 int i;
302 unsigned int *src = src_buf;
303 unsigned int *dst = dst_buf;
304
305 for (i = 0; i < len; i += 4, src++, dst++)
306 *dst = swab32p(src);
307}
308
344756f6
RK		 309static void fec_dump(struct net_device *ndev)
310{
311 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 312 struct bufdesc *bdp;
313 struct fec_enet_priv_tx_q *txq;
314 int index = 0;
344756f6
RK		 315
316 netdev_info(ndev, "TX ring dump\n");
317 pr_info("Nr SC addr len SKB\n");
318
4d494cdc
FD		 319 txq = fep->tx_queue[0];
320 bdp = txq->tx_bd_base;
321
344756f6
RK		 322 do {
323 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
324 index,
4d494cdc
FD		 325 bdp == txq->cur_tx ? 'S' : ' ',
326 bdp == txq->dirty_tx ? 'H' : ' ',
344756f6 327 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
4d494cdc
FD		 328 txq->tx_skbuff[index]);
329 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
344756f6 330 index++;
4d494cdc 331 } while (bdp != txq->tx_bd_base);
344756f6
RK		 332}
333
62a02c98
FD		 334static inline bool is_ipv4_pkt(struct sk_buff *skb)
335{
336 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
337}
338
4c09eed9
JB		 339static int
340fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
341{
342 /* Only run for packets requiring a checksum. */
343 if (skb->ip_summed != CHECKSUM_PARTIAL)
344 return 0;
345
346 if (unlikely(skb_cow_head(skb, 0)))
347 return -1;
348
62a02c98
FD		 349 if (is_ipv4_pkt(skb))
350 ip_hdr(skb)->check = 0;
4c09eed9
JB		 351 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
352
353 return 0;
354}
355
6e909283 356static int
4d494cdc
FD		 357fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
358 struct sk_buff *skb,
359 struct net_device *ndev)
1da177e4 360{
c556167f 361 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 362 struct bufdesc *bdp = txq->cur_tx;
6e909283
NA		 363 struct bufdesc_ex *ebdp;
364 int nr_frags = skb_shinfo(skb)->nr_frags;
4d494cdc 365 unsigned short queue = skb_get_queue_mapping(skb);
6e909283
NA		 366 int frag, frag_len;
367 unsigned short status;
368 unsigned int estatus = 0;
369 skb_frag_t *this_frag;
de5fb0a0 370 unsigned int index;
6e909283 371 void *bufaddr;
d6bf3143 372 dma_addr_t addr;
6e909283 373 int i;
1da177e4 374
6e909283
NA		 375 for (frag = 0; frag < nr_frags; frag++) {
376 this_frag = &skb_shinfo(skb)->frags[frag];
4d494cdc 377 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
6e909283
NA		 378 ebdp = (struct bufdesc_ex *)bdp;
379
380 status = bdp->cbd_sc;
381 status &= ~BD_ENET_TX_STATS;
382 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
383 frag_len = skb_shinfo(skb)->frags[frag].size;
384
385 /* Handle the last BD specially */
386 if (frag == nr_frags - 1) {
387 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
388 if (fep->bufdesc_ex) {
389 estatus |= BD_ENET_TX_INT;
390 if (unlikely(skb_shinfo(skb)->tx_flags &
391 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
392 estatus |= BD_ENET_TX_TS;
393 }
394 }
395
396 if (fep->bufdesc_ex) {
6b7e4008 397 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 398 estatus |= FEC_TX_BD_FTYPE(queue);
6e909283
NA		 399 if (skb->ip_summed == CHECKSUM_PARTIAL)
400 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
401 ebdp->cbd_bdu = 0;
402 ebdp->cbd_esc = estatus;
403 }
404
405 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
406
4d494cdc 407 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
41ef84ce 408 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 409 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 410 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
411 bufaddr = txq->tx_bounce[index];
6e909283 412
6b7e4008 413 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 414 swap_buffer(bufaddr, frag_len);
415 }
416
d6bf3143
RK		 417 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
418 DMA_TO_DEVICE);
419 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 420 dev_kfree_skb_any(skb);
421 if (net_ratelimit())
422 netdev_err(ndev, "Tx DMA memory map failed\n");
423 goto dma_mapping_error;
424 }
425
d6bf3143 426 bdp->cbd_bufaddr = addr;
6e909283
NA		 427 bdp->cbd_datlen = frag_len;
428 bdp->cbd_sc = status;
429 }
430
4d494cdc 431 txq->cur_tx = bdp;
6e909283
NA		 432
433 return 0;
434
435dma_mapping_error:
4d494cdc 436 bdp = txq->cur_tx;
6e909283 437 for (i = 0; i < frag; i++) {
4d494cdc 438 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
6e909283
NA		 439 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
440 bdp->cbd_datlen, DMA_TO_DEVICE);
441 }
442 return NETDEV_TX_OK;
443}
1da177e4 444
4d494cdc
FD		 445static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
446 struct sk_buff *skb, struct net_device *ndev)
6e909283
NA		 447{
448 struct fec_enet_private *fep = netdev_priv(ndev);
6e909283
NA		 449 int nr_frags = skb_shinfo(skb)->nr_frags;
450 struct bufdesc *bdp, *last_bdp;
451 void *bufaddr;
d6bf3143 452 dma_addr_t addr;
6e909283
NA		 453 unsigned short status;
454 unsigned short buflen;
4d494cdc 455 unsigned short queue;
6e909283
NA		 456 unsigned int estatus = 0;
457 unsigned int index;
79f33912 458 int entries_free;
6e909283 459 int ret;
22f6b860 460
4d494cdc 461 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
79f33912
NA		 462 if (entries_free < MAX_SKB_FRAGS + 1) {
463 dev_kfree_skb_any(skb);
464 if (net_ratelimit())
465 netdev_err(ndev, "NOT enough BD for SG!\n");
466 return NETDEV_TX_OK;
467 }
468
4c09eed9
JB		 469 /* Protocol checksum off-load for TCP and UDP. */
470 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 471 dev_kfree_skb_any(skb);
4c09eed9
JB		 472 return NETDEV_TX_OK;
473 }
474
6e909283 475 /* Fill in a Tx ring entry */
4d494cdc 476 bdp = txq->cur_tx;
6e909283 477 status = bdp->cbd_sc;
0e702ab3 478 status &= ~BD_ENET_TX_STATS;
1da177e4 479
22f6b860 480 /* Set buffer length and buffer pointer */
9555b31e 481 bufaddr = skb->data;
6e909283 482 buflen = skb_headlen(skb);
1da177e4 483
4d494cdc
FD		 484 queue = skb_get_queue_mapping(skb);
485 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
41ef84ce 486 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 487 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 488 memcpy(txq->tx_bounce[index], skb->data, buflen);
489 bufaddr = txq->tx_bounce[index];
1da177e4 490
6b7e4008 491 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 492 swap_buffer(bufaddr, buflen);
493 }
6aa20a22 494
d6bf3143
RK		 495 /* Push the data cache so the CPM does not get stale memory data. */
496 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
497 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 498 dev_kfree_skb_any(skb);
499 if (net_ratelimit())
500 netdev_err(ndev, "Tx DMA memory map failed\n");
501 return NETDEV_TX_OK;
502 }
1da177e4 503
6e909283 504 if (nr_frags) {
4d494cdc 505 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
6e909283
NA		 506 if (ret)
507 return ret;
508 } else {
509 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
510 if (fep->bufdesc_ex) {
511 estatus = BD_ENET_TX_INT;
512 if (unlikely(skb_shinfo(skb)->tx_flags &
513 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
514 estatus |= BD_ENET_TX_TS;
515 }
516 }
517
ff43da86
FL		 518 if (fep->bufdesc_ex) {
519
520 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 521
ff43da86 522 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 523 fep->hwts_tx_en))
6605b730 524 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 525
6b7e4008 526 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213
NA		 527 estatus |= FEC_TX_BD_FTYPE(queue);
528
6e909283
NA		 529 if (skb->ip_summed == CHECKSUM_PARTIAL)
530 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
531
532 ebdp->cbd_bdu = 0;
533 ebdp->cbd_esc = estatus;
6605b730 534 }
03191656 535
4d494cdc
FD		 536 last_bdp = txq->cur_tx;
537 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
6e909283 538 /* Save skb pointer */
4d494cdc 539 txq->tx_skbuff[index] = skb;
6e909283
NA		 540
541 bdp->cbd_datlen = buflen;
d6bf3143 542 bdp->cbd_bufaddr = addr;
6e909283 543
fb8ef788
DFB		 544 /* Send it on its way. Tell FEC it's ready, interrupt when done,
545 * it's the last BD of the frame, and to put the CRC on the end.
546 */
6e909283 547 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
fb8ef788
DFB		 548 bdp->cbd_sc = status;
549
22f6b860 550 /* If this was the last BD in the ring, start at the beginning again. */
4d494cdc 551 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
1da177e4 552
7a2a8451
ED		 553 skb_tx_timestamp(skb);
554
4d494cdc 555 txq->cur_tx = bdp;
de5fb0a0 556
de5fb0a0 557 /* Trigger transmission start */
4d494cdc 558 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
1da177e4 559
6e909283 560 return 0;
1da177e4
LT		 561}
562
79f33912 563static int
4d494cdc
FD		 564fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
565 struct net_device *ndev,
566 struct bufdesc *bdp, int index, char *data,
567 int size, bool last_tcp, bool is_last)
61a4427b
NA		 568{
569 struct fec_enet_private *fep = netdev_priv(ndev);
61cd2ebb 570 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
befe8213 571 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 572 unsigned short status;
573 unsigned int estatus = 0;
d6bf3143 574 dma_addr_t addr;
61a4427b
NA		 575
576 status = bdp->cbd_sc;
79f33912 577 status &= ~BD_ENET_TX_STATS;
61a4427b 578
79f33912 579 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912 580
41ef84ce 581 if (((unsigned long) data) & fep->tx_align ||
6b7e4008 582 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 583 memcpy(txq->tx_bounce[index], data, size);
584 data = txq->tx_bounce[index];
79f33912 585
6b7e4008 586 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 587 swap_buffer(data, size);
588 }
589
d6bf3143
RK		 590 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
591 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 592 dev_kfree_skb_any(skb);
6e909283 593 if (net_ratelimit())
79f33912 594 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 595 return NETDEV_TX_BUSY;
596 }
597
d6bf3143
RK		 598 bdp->cbd_datlen = size;
599 bdp->cbd_bufaddr = addr;
600
79f33912 601 if (fep->bufdesc_ex) {
6b7e4008 602 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 603 estatus |= FEC_TX_BD_FTYPE(queue);
79f33912
NA		 604 if (skb->ip_summed == CHECKSUM_PARTIAL)
605 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
606 ebdp->cbd_bdu = 0;
607 ebdp->cbd_esc = estatus;
608 }
609
610 /* Handle the last BD specially */
611 if (last_tcp)
612 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
613 if (is_last) {
614 status |= BD_ENET_TX_INTR;
615 if (fep->bufdesc_ex)
616 ebdp->cbd_esc |= BD_ENET_TX_INT;
617 }
618
619 bdp->cbd_sc = status;
620
621 return 0;
622}
623
624static int
4d494cdc
FD		 625fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
626 struct sk_buff *skb, struct net_device *ndev,
627 struct bufdesc *bdp, int index)
79f33912
NA		 628{
629 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912 630 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
61cd2ebb 631 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
befe8213 632 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 633 void *bufaddr;
634 unsigned long dmabuf;
635 unsigned short status;
636 unsigned int estatus = 0;
637
638 status = bdp->cbd_sc;
639 status &= ~BD_ENET_TX_STATS;
640 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
641
4d494cdc
FD		 642 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
643 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
41ef84ce 644 if (((unsigned long)bufaddr) & fep->tx_align ||
6b7e4008 645 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 646 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
647 bufaddr = txq->tx_bounce[index];
79f33912 648
6b7e4008 649 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 650 swap_buffer(bufaddr, hdr_len);
651
652 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
653 hdr_len, DMA_TO_DEVICE);
654 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
655 dev_kfree_skb_any(skb);
656 if (net_ratelimit())
657 netdev_err(ndev, "Tx DMA memory map failed\n");
658 return NETDEV_TX_BUSY;
659 }
660 }
661
662 bdp->cbd_bufaddr = dmabuf;
663 bdp->cbd_datlen = hdr_len;
664
665 if (fep->bufdesc_ex) {
6b7e4008 666 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 667 estatus |= FEC_TX_BD_FTYPE(queue);
79f33912
NA		 668 if (skb->ip_summed == CHECKSUM_PARTIAL)
669 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
670 ebdp->cbd_bdu = 0;
671 ebdp->cbd_esc = estatus;
672 }
673
674 bdp->cbd_sc = status;
675
676 return 0;
677}
678
4d494cdc
FD		 679static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
680 struct sk_buff *skb,
681 struct net_device *ndev)
79f33912
NA		 682{
683 struct fec_enet_private *fep = netdev_priv(ndev);
684 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
685 int total_len, data_left;
4d494cdc
FD		 686 struct bufdesc *bdp = txq->cur_tx;
687 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 688 struct tso_t tso;
689 unsigned int index = 0;
690 int ret;
691
4d494cdc 692 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
79f33912
NA		 693 dev_kfree_skb_any(skb);
694 if (net_ratelimit())
695 netdev_err(ndev, "NOT enough BD for TSO!\n");
696 return NETDEV_TX_OK;
697 }
698
699 /* Protocol checksum off-load for TCP and UDP. */
700 if (fec_enet_clear_csum(skb, ndev)) {
701 dev_kfree_skb_any(skb);
702 return NETDEV_TX_OK;
703 }
704
705 /* Initialize the TSO handler, and prepare the first payload */
706 tso_start(skb, &tso);
707
708 total_len = skb->len - hdr_len;
709 while (total_len > 0) {
710 char *hdr;
711
4d494cdc 712 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
79f33912
NA		 713 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
714 total_len -= data_left;
715
716 /* prepare packet headers: MAC + IP + TCP */
4d494cdc 717 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
79f33912 718 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
4d494cdc 719 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
79f33912
NA		 720 if (ret)
721 goto err_release;
722
723 while (data_left > 0) {
724 int size;
725
726 size = min_t(int, tso.size, data_left);
4d494cdc
FD		 727 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
728 index = fec_enet_get_bd_index(txq->tx_bd_base,
729 bdp, fep);
730 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
731 bdp, index,
732 tso.data, size,
733 size == data_left,
79f33912
NA		 734 total_len == 0);
735 if (ret)
736 goto err_release;
737
738 data_left -= size;
739 tso_build_data(skb, &tso, size);
740 }
741
4d494cdc 742 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
79f33912
NA		 743 }
744
745 /* Save skb pointer */
4d494cdc 746 txq->tx_skbuff[index] = skb;
79f33912 747
79f33912 748 skb_tx_timestamp(skb);
4d494cdc 749 txq->cur_tx = bdp;
79f33912
NA		 750
751 /* Trigger transmission start */
6b7e4008 752 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
37d6017b
FD		 753 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
754 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
755 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
756 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
757 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
79f33912
NA		 758
759 return 0;
760
761err_release:
762 /* TODO: Release all used data descriptors for TSO */
763 return ret;
764}
765
766static netdev_tx_t
767fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
768{
769 struct fec_enet_private *fep = netdev_priv(ndev);
770 int entries_free;
4d494cdc
FD		 771 unsigned short queue;
772 struct fec_enet_priv_tx_q *txq;
773 struct netdev_queue *nq;
79f33912
NA		 774 int ret;
775
4d494cdc
FD		 776 queue = skb_get_queue_mapping(skb);
777 txq = fep->tx_queue[queue];
778 nq = netdev_get_tx_queue(ndev, queue);
779
79f33912 780 if (skb_is_gso(skb))
4d494cdc 781 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
79f33912 782 else
4d494cdc 783 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
6e909283
NA		 784 if (ret)
785 return ret;
61a4427b 786
4d494cdc
FD		 787 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
788 if (entries_free <= txq->tx_stop_threshold)
789 netif_tx_stop_queue(nq);
61a4427b
NA		 790
791 return NETDEV_TX_OK;
792}
793
14109a59
FL		 794/* Init RX & TX buffer descriptors
795 */
796static void fec_enet_bd_init(struct net_device *dev)
797{
798 struct fec_enet_private *fep = netdev_priv(dev);
4d494cdc
FD		 799 struct fec_enet_priv_tx_q *txq;
800 struct fec_enet_priv_rx_q *rxq;
14109a59
FL		 801 struct bufdesc *bdp;
802 unsigned int i;
59d0f746 803 unsigned int q;
14109a59 804
59d0f746
FL		 805 for (q = 0; q < fep->num_rx_queues; q++) {
806 /* Initialize the receive buffer descriptors. */
807 rxq = fep->rx_queue[q];
808 bdp = rxq->rx_bd_base;
4d494cdc 809
59d0f746 810 for (i = 0; i < rxq->rx_ring_size; i++) {
14109a59 811
59d0f746
FL		 812 /* Initialize the BD for every fragment in the page. */
813 if (bdp->cbd_bufaddr)
814 bdp->cbd_sc = BD_ENET_RX_EMPTY;
815 else
816 bdp->cbd_sc = 0;
817 bdp = fec_enet_get_nextdesc(bdp, fep, q);
818 }
819
820 /* Set the last buffer to wrap */
821 bdp = fec_enet_get_prevdesc(bdp, fep, q);
822 bdp->cbd_sc |= BD_SC_WRAP;
823
824 rxq->cur_rx = rxq->rx_bd_base;
825 }
826
827 for (q = 0; q < fep->num_tx_queues; q++) {
828 /* ...and the same for transmit */
829 txq = fep->tx_queue[q];
830 bdp = txq->tx_bd_base;
831 txq->cur_tx = bdp;
832
833 for (i = 0; i < txq->tx_ring_size; i++) {
834 /* Initialize the BD for every fragment in the page. */
14109a59 835 bdp->cbd_sc = 0;
59d0f746
FL		 836 if (txq->tx_skbuff[i]) {
837 dev_kfree_skb_any(txq->tx_skbuff[i]);
838 txq->tx_skbuff[i] = NULL;
839 }
840 bdp->cbd_bufaddr = 0;
841 bdp = fec_enet_get_nextdesc(bdp, fep, q);
842 }
843
844 /* Set the last buffer to wrap */
845 bdp = fec_enet_get_prevdesc(bdp, fep, q);
846 bdp->cbd_sc |= BD_SC_WRAP;
847 txq->dirty_tx = bdp;
14109a59 848 }
59d0f746 849}
14109a59 850
ce99d0d3
FL		 851static void fec_enet_active_rxring(struct net_device *ndev)
852{
853 struct fec_enet_private *fep = netdev_priv(ndev);
854 int i;
855
856 for (i = 0; i < fep->num_rx_queues; i++)
857 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
858}
859
59d0f746
FL		 860static void fec_enet_enable_ring(struct net_device *ndev)
861{
862 struct fec_enet_private *fep = netdev_priv(ndev);
863 struct fec_enet_priv_tx_q *txq;
864 struct fec_enet_priv_rx_q *rxq;
865 int i;
14109a59 866
59d0f746
FL		 867 for (i = 0; i < fep->num_rx_queues; i++) {
868 rxq = fep->rx_queue[i];
869 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
d543a762 870 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
14109a59 871
59d0f746
FL		 872 /* enable DMA1/2 */
873 if (i)
874 writel(RCMR_MATCHEN | RCMR_CMP(i),
875 fep->hwp + FEC_RCMR(i));
876 }
14109a59 877
59d0f746
FL		 878 for (i = 0; i < fep->num_tx_queues; i++) {
879 txq = fep->tx_queue[i];
880 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
881
882 /* enable DMA1/2 */
883 if (i)
884 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
885 fep->hwp + FEC_DMA_CFG(i));
14109a59 886 }
59d0f746 887}
14109a59 888
59d0f746
FL		 889static void fec_enet_reset_skb(struct net_device *ndev)
890{
891 struct fec_enet_private *fep = netdev_priv(ndev);
892 struct fec_enet_priv_tx_q *txq;
893 int i, j;
894
895 for (i = 0; i < fep->num_tx_queues; i++) {
896 txq = fep->tx_queue[i];
897
898 for (j = 0; j < txq->tx_ring_size; j++) {
899 if (txq->tx_skbuff[j]) {
900 dev_kfree_skb_any(txq->tx_skbuff[j]);
901 txq->tx_skbuff[j] = NULL;
902 }
903 }
904 }
14109a59
FL		 905}
906
dbc64a8e
RK		 907/*
908 * This function is called to start or restart the FEC during a link
909 * change, transmit timeout, or to reconfigure the FEC. The network
910 * packet processing for this device must be stopped before this call.
45993653 911 */
1da177e4 912static void
ef83337d 913fec_restart(struct net_device *ndev)
1da177e4 914{
c556167f 915 struct fec_enet_private *fep = netdev_priv(ndev);
4c09eed9 916 u32 val;
cd1f402c
UKK		 917 u32 temp_mac[2];
918 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 919 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 920
106c314c
FD		 921 /* Whack a reset. We should wait for this.
922 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
923 * instead of reset MAC itself.
924 */
6b7e4008 925 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
106c314c
FD		 926 writel(0, fep->hwp + FEC_ECNTRL);
927 } else {
928 writel(1, fep->hwp + FEC_ECNTRL);
929 udelay(10);
930 }
1da177e4 931
45993653
UKK		 932 /*
933 * enet-mac reset will reset mac address registers too,
934 * so need to reconfigure it.
935 */
6b7e4008 936 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
45993653
UKK		 937 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
938 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
939 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
940 }
1da177e4 941
45993653 942 /* Clear any outstanding interrupt. */
e17f7fec 943 writel(0xffffffff, fep->hwp + FEC_IEVENT);
1da177e4 944
14109a59
FL		 945 fec_enet_bd_init(ndev);
946
59d0f746 947 fec_enet_enable_ring(ndev);
45993653 948
59d0f746
FL		 949 /* Reset tx SKB buffers. */
950 fec_enet_reset_skb(ndev);
97b72e43 951
45993653 952 /* Enable MII mode */
ef83337d 953 if (fep->full_duplex == DUPLEX_FULL) {
cd1f402c 954 /* FD enable */
45993653
UKK		 955 writel(0x04, fep->hwp + FEC_X_CNTRL);
956 } else {
cd1f402c
UKK		 957 /* No Rcv on Xmit */
958 rcntl |= 0x02;
45993653
UKK		 959 writel(0x0, fep->hwp + FEC_X_CNTRL);
960 }
cd1f402c 961
45993653
UKK		 962 /* Set MII speed */
963 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
964
d1391930 965#if !defined(CONFIG_M5272)
4c09eed9
JB		 966 /* set RX checksum */
967 val = readl(fep->hwp + FEC_RACC);
968 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
969 val |= FEC_RACC_OPTIONS;
970 else
971 val &= ~FEC_RACC_OPTIONS;
972 writel(val, fep->hwp + FEC_RACC);
d1391930 973#endif
4c09eed9 974
45993653
UKK		 975 /*
976 * The phy interface and speed need to get configured
977 * differently on enet-mac.
978 */
6b7e4008 979 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 980 /* Enable flow control and length check */
981 rcntl |= 0x40000000 | 0x00000020;
45993653 982
230dec61
SG		 983 /* RGMII, RMII or MII */
984 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
985 rcntl |= (1 << 6);
986 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 987 rcntl |= (1 << 8);
45993653 988 else
cd1f402c 989 rcntl &= ~(1 << 8);
45993653 990
230dec61
SG		 991 /* 1G, 100M or 10M */
992 if (fep->phy_dev) {
993 if (fep->phy_dev->speed == SPEED_1000)
994 ecntl |= (1 << 5);
995 else if (fep->phy_dev->speed == SPEED_100)
996 rcntl &= ~(1 << 9);
997 else
998 rcntl |= (1 << 9);
999 }
45993653
UKK		 1000 } else {
1001#ifdef FEC_MIIGSK_ENR
6b7e4008 1002 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
8d82f219 1003 u32 cfgr;
45993653
UKK		 1004 /* disable the gasket and wait */
1005 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1006 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1007 udelay(1);
1008
1009 /*
1010 * configure the gasket:
1011 * RMII, 50 MHz, no loopback, no echo
0ca1e290 1012 * MII, 25 MHz, no loopback, no echo
45993653 1013 */
8d82f219
EB		 1014 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1015 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1016 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1017 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1018 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 1019
1020 /* re-enable the gasket */
1021 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 1022 }
45993653
UKK		 1023#endif
1024 }
baa70a5c 1025
d1391930 1026#if !defined(CONFIG_M5272)
baa70a5c
FL		 1027 /* enable pause frame*/
1028 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1029 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1030 fep->phy_dev && fep->phy_dev->pause)) {
1031 rcntl |= FEC_ENET_FCE;
1032
4c09eed9 1033 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 1034 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1035 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1036 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1037 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1038
1039 /* OPD */
1040 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1041 } else {
1042 rcntl &= ~FEC_ENET_FCE;
1043 }
d1391930 1044#endif /* !defined(CONFIG_M5272) */
baa70a5c 1045
cd1f402c 1046 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 1047
84fe6182
SW		 1048 /* Setup multicast filter. */
1049 set_multicast_list(ndev);
1050#ifndef CONFIG_M5272
1051 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1052 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1053#endif
1054
6b7e4008 1055 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
230dec61
SG		 1056 /* enable ENET endian swap */
1057 ecntl |= (1 << 8);
1058 /* enable ENET store and forward mode */
1059 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1060 }
1061
ff43da86
FL		 1062 if (fep->bufdesc_ex)
1063 ecntl |= (1 << 4);
6605b730 1064
38ae92dc 1065#ifndef CONFIG_M5272
b9eef55c
JB		 1066 /* Enable the MIB statistic event counters */
1067 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 1068#endif
1069
45993653 1070 /* And last, enable the transmit and receive processing */
230dec61 1071 writel(ecntl, fep->hwp + FEC_ECNTRL);
ce99d0d3 1072 fec_enet_active_rxring(ndev);
45993653 1073
ff43da86
FL		 1074 if (fep->bufdesc_ex)
1075 fec_ptp_start_cyclecounter(ndev);
1076
45993653
UKK		 1077 /* Enable interrupts we wish to service */
1078 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
d851b47b
FD		 1079
1080 /* Init the interrupt coalescing */
1081 fec_enet_itr_coal_init(ndev);
1082
45993653
UKK		 1083}
1084
1085static void
1086fec_stop(struct net_device *ndev)
1087{
1088 struct fec_enet_private *fep = netdev_priv(ndev);
42431dc2 1089 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
45993653
UKK		 1090
1091 /* We cannot expect a graceful transmit stop without link !!! */
1092 if (fep->link) {
1093 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1094 udelay(10);
1095 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 1096 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1097 }
1098
106c314c
FD		 1099 /* Whack a reset. We should wait for this.
1100 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1101 * instead of reset MAC itself.
1102 */
6b7e4008 1103 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
106c314c
FD		 1104 writel(0, fep->hwp + FEC_ECNTRL);
1105 } else {
1106 writel(1, fep->hwp + FEC_ECNTRL);
1107 udelay(10);
1108 }
45993653
UKK		 1109 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1110 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
230dec61
SG		 1111
1112 /* We have to keep ENET enabled to have MII interrupt stay working */
6b7e4008 1113 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
230dec61 1114 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1115 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1116 }
1da177e4
LT		 1117}
1118
1119
45993653
UKK		 1120static void
1121fec_timeout(struct net_device *ndev)
1122{
1123 struct fec_enet_private *fep = netdev_priv(ndev);
1124
344756f6
RK		 1125 fec_dump(ndev);
1126
45993653
UKK		 1127 ndev->stats.tx_errors++;
1128
36cdc743 1129 schedule_work(&fep->tx_timeout_work);
54309fa6
FL		 1130}
1131
36cdc743 1132static void fec_enet_timeout_work(struct work_struct *work)
54309fa6
FL		 1133{
1134 struct fec_enet_private *fep =
36cdc743 1135 container_of(work, struct fec_enet_private, tx_timeout_work);
8ce5624f 1136 struct net_device *ndev = fep->netdev;
54309fa6 1137
36cdc743
RK		 1138 rtnl_lock();
1139 if (netif_device_present(ndev) || netif_running(ndev)) {
1140 napi_disable(&fep->napi);
1141 netif_tx_lock_bh(ndev);
1142 fec_restart(ndev);
1143 netif_wake_queue(ndev);
1144 netif_tx_unlock_bh(ndev);
1145 napi_enable(&fep->napi);
54309fa6 1146 }
36cdc743 1147 rtnl_unlock();
45993653
UKK		 1148}
1149
bfd4ecdd
RK		 1150static void
1151fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1152 struct skb_shared_hwtstamps *hwtstamps)
1153{
1154 unsigned long flags;
1155 u64 ns;
1156
1157 spin_lock_irqsave(&fep->tmreg_lock, flags);
1158 ns = timecounter_cyc2time(&fep->tc, ts);
1159 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1160
1161 memset(hwtstamps, 0, sizeof(*hwtstamps));
1162 hwtstamps->hwtstamp = ns_to_ktime(ns);
1163}
1164
1da177e4 1165static void
4d494cdc 1166fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1da177e4
LT		 1167{
1168 struct fec_enet_private *fep;
2e28532f 1169 struct bufdesc *bdp;
0e702ab3 1170 unsigned short status;
1da177e4 1171 struct sk_buff *skb;
4d494cdc
FD		 1172 struct fec_enet_priv_tx_q *txq;
1173 struct netdev_queue *nq;
de5fb0a0 1174 int index = 0;
79f33912 1175 int entries_free;
1da177e4 1176
c556167f 1177 fep = netdev_priv(ndev);
4d494cdc
FD		 1178
1179 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1180
1181 txq = fep->tx_queue[queue_id];
1182 /* get next bdp of dirty_tx */
1183 nq = netdev_get_tx_queue(ndev, queue_id);
1184 bdp = txq->dirty_tx;
1da177e4 1185
de5fb0a0 1186 /* get next bdp of dirty_tx */
4d494cdc 1187 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
de5fb0a0 1188
0e702ab3 1189 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
de5fb0a0
FL		 1190
1191 /* current queue is empty */
4d494cdc 1192 if (bdp == txq->cur_tx)
f0b3fbea
SH		 1193 break;
1194
4d494cdc 1195 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
de5fb0a0 1196
4d494cdc
FD		 1197 skb = txq->tx_skbuff[index];
1198 txq->tx_skbuff[index] = NULL;
1199 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
79f33912
NA		 1200 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1201 bdp->cbd_datlen, DMA_TO_DEVICE);
2488a54e 1202 bdp->cbd_bufaddr = 0;
6e909283 1203 if (!skb) {
4d494cdc 1204 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
6e909283
NA		 1205 continue;
1206 }
de5fb0a0 1207
1da177e4 1208 /* Check for errors. */
0e702ab3 1209 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1210 BD_ENET_TX_RL | BD_ENET_TX_UN |
1211 BD_ENET_TX_CSL)) {
c556167f 1212 ndev->stats.tx_errors++;
0e702ab3 1213 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1214 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1215 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1216 ndev->stats.tx_window_errors++;
0e702ab3 1217 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1218 ndev->stats.tx_aborted_errors++;
0e702ab3 1219 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1220 ndev->stats.tx_fifo_errors++;
0e702ab3 1221 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1222 ndev->stats.tx_carrier_errors++;
1da177e4 1223 } else {
c556167f 1224 ndev->stats.tx_packets++;
6e909283 1225 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1226 }
1227
ff43da86
FL		 1228 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1229 fep->bufdesc_ex) {
6605b730 1230 struct skb_shared_hwtstamps shhwtstamps;
ff43da86 1231 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730 1232
bfd4ecdd 1233 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
6605b730
FL		 1234 skb_tstamp_tx(skb, &shhwtstamps);
1235 }
ff43da86 1236
1da177e4
LT		 1237 /* Deferred means some collisions occurred during transmit,
1238 * but we eventually sent the packet OK.
1239 */
0e702ab3 1240 if (status & BD_ENET_TX_DEF)
c556167f 1241 ndev->stats.collisions++;
6aa20a22 1242
22f6b860 1243 /* Free the sk buffer associated with this last transmit */
1da177e4 1244 dev_kfree_skb_any(skb);
de5fb0a0 1245
4d494cdc 1246 txq->dirty_tx = bdp;
6aa20a22 1247
22f6b860 1248 /* Update pointer to next buffer descriptor to be transmitted */
4d494cdc 1249 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
6aa20a22 1250
22f6b860 1251 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1252 */
79f33912 1253 if (netif_queue_stopped(ndev)) {
4d494cdc
FD		 1254 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1255 if (entries_free >= txq->tx_wake_threshold)
1256 netif_tx_wake_queue(nq);
79f33912 1257 }
1da177e4 1258 }
ccea2968
RK		 1259
1260 /* ERR006538: Keep the transmitter going */
4d494cdc
FD		 1261 if (bdp != txq->cur_tx &&
1262 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1263 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1264}
1265
1266static void
1267fec_enet_tx(struct net_device *ndev)
1268{
1269 struct fec_enet_private *fep = netdev_priv(ndev);
1270 u16 queue_id;
1271 /* First process class A queue, then Class B and Best Effort queue */
1272 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1273 clear_bit(queue_id, &fep->work_tx);
1274 fec_enet_tx_queue(ndev, queue_id);
1275 }
1276 return;
1da177e4
LT		 1277}
1278
1b7bde6d
NA		 1279static int
1280fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1281{
1282 struct fec_enet_private *fep = netdev_priv(ndev);
1283 int off;
1284
1285 off = ((unsigned long)skb->data) & fep->rx_align;
1286 if (off)
1287 skb_reserve(skb, fep->rx_align + 1 - off);
1288
1289 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1290 FEC_ENET_RX_FRSIZE - fep->rx_align,
1291 DMA_FROM_DEVICE);
1292 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1293 if (net_ratelimit())
1294 netdev_err(ndev, "Rx DMA memory map failed\n");
1295 return -ENOMEM;
1296 }
1297
1298 return 0;
1299}
1300
1301static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1310b544 1302 struct bufdesc *bdp, u32 length, bool swap)
1b7bde6d
NA		 1303{
1304 struct fec_enet_private *fep = netdev_priv(ndev);
1305 struct sk_buff *new_skb;
1306
1307 if (length > fep->rx_copybreak)
1308 return false;
1309
1310 new_skb = netdev_alloc_skb(ndev, length);
1311 if (!new_skb)
1312 return false;
1313
1314 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1315 FEC_ENET_RX_FRSIZE - fep->rx_align,
1316 DMA_FROM_DEVICE);
1310b544
LW		 1317 if (!swap)
1318 memcpy(new_skb->data, (*skb)->data, length);
1319 else
1320 swap_buffer2(new_skb->data, (*skb)->data, length);
1b7bde6d
NA		 1321 *skb = new_skb;
1322
1323 return true;
1324}
1325
1da177e4
LT		 1326/* During a receive, the cur_rx points to the current incoming buffer.
1327 * When we update through the ring, if the next incoming buffer has
1328 * not been given to the system, we just set the empty indicator,
1329 * effectively tossing the packet.
1330 */
dc975382 1331static int
4d494cdc 1332fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1da177e4 1333{
c556167f 1334 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 1335 struct fec_enet_priv_rx_q *rxq;
2e28532f 1336 struct bufdesc *bdp;
0e702ab3 1337 unsigned short status;
1b7bde6d
NA		 1338 struct sk_buff *skb_new = NULL;
1339 struct sk_buff *skb;
1da177e4
LT		 1340 ushort pkt_len;
1341 __u8 *data;
dc975382 1342 int pkt_received = 0;
cdffcf1b
JB		 1343 struct bufdesc_ex *ebdp = NULL;
1344 bool vlan_packet_rcvd = false;
1345 u16 vlan_tag;
d842a31f 1346 int index = 0;
1b7bde6d 1347 bool is_copybreak;
6b7e4008 1348 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
6aa20a22 1349
0e702ab3
GU		 1350#ifdef CONFIG_M532x
1351 flush_cache_all();
6aa20a22 1352#endif
4d494cdc
FD		 1353 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1354 rxq = fep->rx_queue[queue_id];
1da177e4 1355
1da177e4
LT		 1356 /* First, grab all of the stats for the incoming packet.
1357 * These get messed up if we get called due to a busy condition.
1358 */
4d494cdc 1359 bdp = rxq->cur_rx;
1da177e4 1360
22f6b860 1361 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1da177e4 1362
dc975382
FL		 1363 if (pkt_received >= budget)
1364 break;
1365 pkt_received++;
1366
22f6b860
SH		 1367 /* Since we have allocated space to hold a complete frame,
1368 * the last indicator should be set.
1369 */
1370 if ((status & BD_ENET_RX_LAST) == 0)
31b7720c 1371 netdev_err(ndev, "rcv is not +last\n");
1da177e4 1372
db3421c1 1373
22f6b860
SH		 1374 /* Check for errors. */
1375 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1da177e4 1376 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
c556167f 1377 ndev->stats.rx_errors++;
22f6b860
SH		 1378 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1379 /* Frame too long or too short. */
c556167f 1380 ndev->stats.rx_length_errors++;
22f6b860
SH		 1381 }
1382 if (status & BD_ENET_RX_NO) /* Frame alignment */
c556167f 1383 ndev->stats.rx_frame_errors++;
22f6b860 1384 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1385 ndev->stats.rx_crc_errors++;
22f6b860 1386 if (status & BD_ENET_RX_OV) /* FIFO overrun */
c556167f 1387 ndev->stats.rx_fifo_errors++;
1da177e4 1388 }
1da177e4 1389
22f6b860
SH		 1390 /* Report late collisions as a frame error.
1391 * On this error, the BD is closed, but we don't know what we
1392 * have in the buffer. So, just drop this frame on the floor.
1393 */
1394 if (status & BD_ENET_RX_CL) {
c556167f
UKK		 1395 ndev->stats.rx_errors++;
1396 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1397 goto rx_processing_done;
1398 }
1da177e4 1399
22f6b860 1400 /* Process the incoming frame. */
c556167f 1401 ndev->stats.rx_packets++;
22f6b860 1402 pkt_len = bdp->cbd_datlen;
c556167f 1403 ndev->stats.rx_bytes += pkt_len;
1da177e4 1404
4d494cdc 1405 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1b7bde6d 1406 skb = rxq->rx_skbuff[index];
ccdc4f19 1407
1b7bde6d
NA		 1408 /* The packet length includes FCS, but we don't want to
1409 * include that when passing upstream as it messes up
1410 * bridging applications.
1411 */
1310b544
LW		 1412 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1413 need_swap);
1b7bde6d
NA		 1414 if (!is_copybreak) {
1415 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1416 if (unlikely(!skb_new)) {
1417 ndev->stats.rx_dropped++;
1418 goto rx_processing_done;
1419 }
1420 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1421 FEC_ENET_RX_FRSIZE - fep->rx_align,
1422 DMA_FROM_DEVICE);
1423 }
1424
1425 prefetch(skb->data - NET_IP_ALIGN);
1426 skb_put(skb, pkt_len - 4);
1427 data = skb->data;
1310b544 1428 if (!is_copybreak && need_swap)
b5680e0b
SG		 1429 swap_buffer(data, pkt_len);
1430
cdffcf1b
JB		 1431 /* Extract the enhanced buffer descriptor */
1432 ebdp = NULL;
1433 if (fep->bufdesc_ex)
1434 ebdp = (struct bufdesc_ex *)bdp;
1435
1436 /* If this is a VLAN packet remove the VLAN Tag */
1437 vlan_packet_rcvd = false;
1438 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
4d494cdc 1439 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
cdffcf1b
JB		 1440 /* Push and remove the vlan tag */
1441 struct vlan_hdr *vlan_header =
1442 (struct vlan_hdr *) (data + ETH_HLEN);
1443 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
cdffcf1b
JB		 1444
1445 vlan_packet_rcvd = true;
1b7bde6d
NA		 1446
1447 skb_copy_to_linear_data_offset(skb, VLAN_HLEN,
1448 data, (2 * ETH_ALEN));
1449 skb_pull(skb, VLAN_HLEN);
cdffcf1b
JB		 1450 }
1451
1b7bde6d 1452 skb->protocol = eth_type_trans(skb, ndev);
1da177e4 1453
1b7bde6d
NA		 1454 /* Get receive timestamp from the skb */
1455 if (fep->hwts_rx_en && fep->bufdesc_ex)
1456 fec_enet_hwtstamp(fep, ebdp->ts,
1457 skb_hwtstamps(skb));
1458
1459 if (fep->bufdesc_ex &&
1460 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1461 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1462 /* don't check it */
1463 skb->ip_summed = CHECKSUM_UNNECESSARY;
1464 } else {
1465 skb_checksum_none_assert(skb);
4c09eed9 1466 }
1b7bde6d 1467 }
4c09eed9 1468
1b7bde6d
NA		 1469 /* Handle received VLAN packets */
1470 if (vlan_packet_rcvd)
1471 __vlan_hwaccel_put_tag(skb,
1472 htons(ETH_P_8021Q),
1473 vlan_tag);
cdffcf1b 1474
1b7bde6d
NA		 1475 napi_gro_receive(&fep->napi, skb);
1476
1477 if (is_copybreak) {
1478 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1479 FEC_ENET_RX_FRSIZE - fep->rx_align,
1480 DMA_FROM_DEVICE);
1481 } else {
1482 rxq->rx_skbuff[index] = skb_new;
1483 fec_enet_new_rxbdp(ndev, bdp, skb_new);
22f6b860 1484 }
f0b3fbea 1485
22f6b860
SH		 1486rx_processing_done:
1487 /* Clear the status flags for this buffer */
1488 status &= ~BD_ENET_RX_STATS;
1da177e4 1489
22f6b860
SH		 1490 /* Mark the buffer empty */
1491 status |= BD_ENET_RX_EMPTY;
1492 bdp->cbd_sc = status;
6aa20a22 1493
ff43da86
FL		 1494 if (fep->bufdesc_ex) {
1495 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1496
1497 ebdp->cbd_esc = BD_ENET_RX_INT;
1498 ebdp->cbd_prot = 0;
1499 ebdp->cbd_bdu = 0;
1500 }
6605b730 1501
22f6b860 1502 /* Update BD pointer to next entry */
4d494cdc 1503 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
36e24e2e 1504
22f6b860
SH		 1505 /* Doing this here will keep the FEC running while we process
1506 * incoming frames. On a heavily loaded network, we should be
1507 * able to keep up at the expense of system resources.
1508 */
4d494cdc 1509 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
22f6b860 1510 }
4d494cdc
FD		 1511 rxq->cur_rx = bdp;
1512 return pkt_received;
1513}
1da177e4 1514
4d494cdc
FD		 1515static int
1516fec_enet_rx(struct net_device *ndev, int budget)
1517{
1518 int pkt_received = 0;
1519 u16 queue_id;
1520 struct fec_enet_private *fep = netdev_priv(ndev);
1521
1522 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1523 clear_bit(queue_id, &fep->work_rx);
1524 pkt_received += fec_enet_rx_queue(ndev,
1525 budget - pkt_received, queue_id);
1526 }
dc975382 1527 return pkt_received;
1da177e4
LT		 1528}
1529
4d494cdc
FD		 1530static bool
1531fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1532{
1533 if (int_events == 0)
1534 return false;
1535
1536 if (int_events & FEC_ENET_RXF)
1537 fep->work_rx |= (1 << 2);
ce99d0d3
FL		 1538 if (int_events & FEC_ENET_RXF_1)
1539 fep->work_rx |= (1 << 0);
1540 if (int_events & FEC_ENET_RXF_2)
1541 fep->work_rx |= (1 << 1);
4d494cdc
FD		 1542
1543 if (int_events & FEC_ENET_TXF)
1544 fep->work_tx |= (1 << 2);
ce99d0d3
FL		 1545 if (int_events & FEC_ENET_TXF_1)
1546 fep->work_tx |= (1 << 0);
1547 if (int_events & FEC_ENET_TXF_2)
1548 fep->work_tx |= (1 << 1);
4d494cdc
FD		 1549
1550 return true;
1551}
1552
45993653
UKK		 1553static irqreturn_t
1554fec_enet_interrupt(int irq, void *dev_id)
1555{
1556 struct net_device *ndev = dev_id;
1557 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c 1558 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
45993653
UKK		 1559 uint int_events;
1560 irqreturn_t ret = IRQ_NONE;
1561
7a16807c
RK		 1562 int_events = readl(fep->hwp + FEC_IEVENT);
1563 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
4d494cdc 1564 fec_enet_collect_events(fep, int_events);
45993653 1565
7a16807c
RK		 1566 if (int_events & napi_mask) {
1567 ret = IRQ_HANDLED;
dc975382 1568
7a16807c
RK		 1569 /* Disable the NAPI interrupts */
1570 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1571 napi_schedule(&fep->napi);
1572 }
45993653 1573
7a16807c
RK		 1574 if (int_events & FEC_ENET_MII) {
1575 ret = IRQ_HANDLED;
1576 complete(&fep->mdio_done);
1577 }
45993653 1578
81f35ffd
PZ		 1579 if (fep->ptp_clock)
1580 fec_ptp_check_pps_event(fep);
278d2404 1581
45993653
UKK		 1582 return ret;
1583}
1584
dc975382
FL		 1585static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1586{
1587 struct net_device *ndev = napi->dev;
dc975382 1588 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1589 int pkts;
1590
1591 /*
1592 * Clear any pending transmit or receive interrupts before
1593 * processing the rings to avoid racing with the hardware.
1594 */
1595 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1596
1597 pkts = fec_enet_rx(ndev, budget);
45993653 1598
de5fb0a0
FL		 1599 fec_enet_tx(ndev);
1600
dc975382
FL		 1601 if (pkts < budget) {
1602 napi_complete(napi);
1603 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1604 }
1605 return pkts;
1606}
45993653 1607
e6b043d5 1608/* ------------------------------------------------------------------------- */
0c7768a0 1609static void fec_get_mac(struct net_device *ndev)
1da177e4 1610{
c556167f 1611 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1612 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1613 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1614
49da97dc
SG		 1615 /*
1616 * try to get mac address in following order:
1617 *
1618 * 1) module parameter via kernel command line in form
1619 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1620 */
1621 iap = macaddr;
1622
ca2cc333
SG		 1623 /*
1624 * 2) from device tree data
1625 */
1626 if (!is_valid_ether_addr(iap)) {
1627 struct device_node *np = fep->pdev->dev.of_node;
1628 if (np) {
1629 const char *mac = of_get_mac_address(np);
1630 if (mac)
1631 iap = (unsigned char *) mac;
1632 }
1633 }
ca2cc333 1634
49da97dc 1635 /*
ca2cc333 1636 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1637 */
1638 if (!is_valid_ether_addr(iap)) {
1639#ifdef CONFIG_M5272
1640 if (FEC_FLASHMAC)
1641 iap = (unsigned char *)FEC_FLASHMAC;
1642#else
1643 if (pdata)
589efdc7 1644 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1645#endif
1646 }
1647
1648 /*
ca2cc333 1649 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1650 */
1651 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1652 *((__be32 *) &tmpaddr[0]) =
1653 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1654 *((__be16 *) &tmpaddr[4]) =
1655 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1656 iap = &tmpaddr[0];
1da177e4
LT		 1657 }
1658
ff5b2fab
LS		 1659 /*
1660 * 5) random mac address
1661 */
1662 if (!is_valid_ether_addr(iap)) {
1663 /* Report it and use a random ethernet address instead */
1664 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1665 eth_hw_addr_random(ndev);
1666 netdev_info(ndev, "Using random MAC address: %pM\n",
1667 ndev->dev_addr);
1668 return;
1669 }
1670
c556167f 1671 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1672
49da97dc
SG		 1673 /* Adjust MAC if using macaddr */
1674 if (iap == macaddr)
43af940c 1675 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1676}
1677
e6b043d5 1678/* ------------------------------------------------------------------------- */
1da177e4 1679
e6b043d5
BW		 1680/*
1681 * Phy section
1682 */
c556167f 1683static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1684{
c556167f 1685 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1686 struct phy_device *phy_dev = fep->phy_dev;
e6b043d5 1687 int status_change = 0;
1da177e4 1688
e6b043d5
BW		 1689 /* Prevent a state halted on mii error */
1690 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1691 phy_dev->state = PHY_RESUMING;
54309fa6 1692 return;
e6b043d5 1693 }
1da177e4 1694
8ce5624f
RK		 1695 /*
1696 * If the netdev is down, or is going down, we're not interested
1697 * in link state events, so just mark our idea of the link as down
1698 * and ignore the event.
1699 */
1700 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1701 fep->link = 0;
1702 } else if (phy_dev->link) {
d97e7497 1703 if (!fep->link) {
6ea0722f 1704 fep->link = phy_dev->link;
e6b043d5
BW		 1705 status_change = 1;
1706 }
1da177e4 1707
ef83337d
RK		 1708 if (fep->full_duplex != phy_dev->duplex) {
1709 fep->full_duplex = phy_dev->duplex;
d97e7497 1710 status_change = 1;
ef83337d 1711 }
d97e7497
LS		 1712
1713 if (phy_dev->speed != fep->speed) {
1714 fep->speed = phy_dev->speed;
1715 status_change = 1;
1716 }
1717
1718 /* if any of the above changed restart the FEC */
dbc64a8e 1719 if (status_change) {
dbc64a8e 1720 napi_disable(&fep->napi);
dbc64a8e 1721 netif_tx_lock_bh(ndev);
ef83337d 1722 fec_restart(ndev);
dbc64a8e 1723 netif_wake_queue(ndev);
6af42d42 1724 netif_tx_unlock_bh(ndev);
dbc64a8e 1725 napi_enable(&fep->napi);
dbc64a8e 1726 }
d97e7497
LS		 1727 } else {
1728 if (fep->link) {
f208ce10
RK		 1729 napi_disable(&fep->napi);
1730 netif_tx_lock_bh(ndev);
c556167f 1731 fec_stop(ndev);
f208ce10
RK		 1732 netif_tx_unlock_bh(ndev);
1733 napi_enable(&fep->napi);
8d7ed0f0 1734 fep->link = phy_dev->link;
d97e7497
LS		 1735 status_change = 1;
1736 }
1da177e4 1737 }
6aa20a22 1738
e6b043d5
BW		 1739 if (status_change)
1740 phy_print_status(phy_dev);
1741}
1da177e4 1742
e6b043d5 1743static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1744{
e6b043d5 1745 struct fec_enet_private *fep = bus->priv;
97b72e43 1746 unsigned long time_left;
1da177e4 1747
e6b043d5 1748 fep->mii_timeout = 0;
97b72e43 1749 init_completion(&fep->mdio_done);
e6b043d5
BW		 1750
1751 /* start a read op */
1752 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1753 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1754 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1755
1756 /* wait for end of transfer */
97b72e43
BS		 1757 time_left = wait_for_completion_timeout(&fep->mdio_done,
1758 usecs_to_jiffies(FEC_MII_TIMEOUT));
1759 if (time_left == 0) {
1760 fep->mii_timeout = 1;
31b7720c 1761 netdev_err(fep->netdev, "MDIO read timeout\n");
97b72e43 1762 return -ETIMEDOUT;
1da177e4 1763 }
1da177e4 1764
e6b043d5
BW		 1765 /* return value */
1766 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
7dd6a2aa 1767}
6aa20a22 1768
e6b043d5
BW		 1769static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1770 u16 value)
1da177e4 1771{
e6b043d5 1772 struct fec_enet_private *fep = bus->priv;
97b72e43 1773 unsigned long time_left;
1da177e4 1774
e6b043d5 1775 fep->mii_timeout = 0;
97b72e43 1776 init_completion(&fep->mdio_done);
1da177e4 1777
862f0982
SG		 1778 /* start a write op */
1779 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
e6b043d5
BW		 1780 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1781 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1782 fep->hwp + FEC_MII_DATA);
1783
1784 /* wait for end of transfer */
97b72e43
BS		 1785 time_left = wait_for_completion_timeout(&fep->mdio_done,
1786 usecs_to_jiffies(FEC_MII_TIMEOUT));
1787 if (time_left == 0) {
1788 fep->mii_timeout = 1;
31b7720c 1789 netdev_err(fep->netdev, "MDIO write timeout\n");
97b72e43 1790 return -ETIMEDOUT;
e6b043d5 1791 }
1da177e4 1792
e6b043d5
BW		 1793 return 0;
1794}
1da177e4 1795
e8fcfcd5
NA		 1796static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1797{
1798 struct fec_enet_private *fep = netdev_priv(ndev);
1799 int ret;
1800
1801 if (enable) {
1802 ret = clk_prepare_enable(fep->clk_ahb);
1803 if (ret)
1804 return ret;
1805 ret = clk_prepare_enable(fep->clk_ipg);
1806 if (ret)
1807 goto failed_clk_ipg;
1808 if (fep->clk_enet_out) {
1809 ret = clk_prepare_enable(fep->clk_enet_out);
1810 if (ret)
1811 goto failed_clk_enet_out;
1812 }
1813 if (fep->clk_ptp) {
91c0d987 1814 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1815 ret = clk_prepare_enable(fep->clk_ptp);
91c0d987
NA		 1816 if (ret) {
1817 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1818 goto failed_clk_ptp;
91c0d987
NA		 1819 } else {
1820 fep->ptp_clk_on = true;
1821 }
1822 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1823 }
9b5330ed
FD		 1824 if (fep->clk_ref) {
1825 ret = clk_prepare_enable(fep->clk_ref);
1826 if (ret)
1827 goto failed_clk_ref;
1828 }
e8fcfcd5
NA		 1829 } else {
1830 clk_disable_unprepare(fep->clk_ahb);
1831 clk_disable_unprepare(fep->clk_ipg);
1832 if (fep->clk_enet_out)
1833 clk_disable_unprepare(fep->clk_enet_out);
91c0d987
NA		 1834 if (fep->clk_ptp) {
1835 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1836 clk_disable_unprepare(fep->clk_ptp);
91c0d987
NA		 1837 fep->ptp_clk_on = false;
1838 mutex_unlock(&fep->ptp_clk_mutex);
1839 }
9b5330ed
FD		 1840 if (fep->clk_ref)
1841 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1842 }
1843
1844 return 0;
9b5330ed
FD		 1845
1846failed_clk_ref:
1847 if (fep->clk_ref)
1848 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1849failed_clk_ptp:
1850 if (fep->clk_enet_out)
1851 clk_disable_unprepare(fep->clk_enet_out);
1852failed_clk_enet_out:
1853 clk_disable_unprepare(fep->clk_ipg);
1854failed_clk_ipg:
1855 clk_disable_unprepare(fep->clk_ahb);
1856
1857 return ret;
1858}
1859
c556167f 1860static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1861{
c556167f 1862 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1863 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1864 char mdio_bus_id[MII_BUS_ID_SIZE];
1865 char phy_name[MII_BUS_ID_SIZE + 3];
1866 int phy_id;
43af940c 1867 int dev_id = fep->dev_id;
562d2f8c 1868
418bd0d4
BW		 1869 fep->phy_dev = NULL;
1870
407066f8
UKK		 1871 if (fep->phy_node) {
1872 phy_dev = of_phy_connect(ndev, fep->phy_node,
1873 &fec_enet_adjust_link, 0,
1874 fep->phy_interface);
213a9922
NA		 1875 if (!phy_dev)
1876 return -ENODEV;
407066f8
UKK		 1877 } else {
1878 /* check for attached phy */
1879 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1880 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1881 continue;
1882 if (fep->mii_bus->phy_map[phy_id] == NULL)
1883 continue;
1884 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1885 continue;
1886 if (dev_id--)
1887 continue;
949bdd20 1888 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
407066f8
UKK		 1889 break;
1890 }
1da177e4 1891
407066f8
UKK		 1892 if (phy_id >= PHY_MAX_ADDR) {
1893 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
949bdd20 1894 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
407066f8
UKK		 1895 phy_id = 0;
1896 }
1897
1898 snprintf(phy_name, sizeof(phy_name),
1899 PHY_ID_FMT, mdio_bus_id, phy_id);
1900 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1901 fep->phy_interface);
6fcc040f
GU		 1902 }
1903
6fcc040f 1904 if (IS_ERR(phy_dev)) {
31b7720c 1905 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1906 return PTR_ERR(phy_dev);
e6b043d5 1907 }
1da177e4 1908
e6b043d5 1909 /* mask with MAC supported features */
6b7e4008 1910 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
230dec61 1911 phy_dev->supported &= PHY_GBIT_FEATURES;
b44592ff 1912 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
d1391930 1913#if !defined(CONFIG_M5272)
baa70a5c 1914 phy_dev->supported |= SUPPORTED_Pause;
d1391930 1915#endif
baa70a5c 1916 }
230dec61
SG		 1917 else
1918 phy_dev->supported &= PHY_BASIC_FEATURES;
1919
e6b043d5 1920 phy_dev->advertising = phy_dev->supported;
1da177e4 1921
e6b043d5
BW		 1922 fep->phy_dev = phy_dev;
1923 fep->link = 0;
1924 fep->full_duplex = 0;
1da177e4 1925
31b7720c
JP		 1926 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1927 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1928 fep->phy_dev->irq);
418bd0d4 1929
e6b043d5 1930 return 0;
1da177e4
LT		 1931}
1932
e6b043d5 1933static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 1934{
b5680e0b 1935 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 1936 struct net_device *ndev = platform_get_drvdata(pdev);
1937 struct fec_enet_private *fep = netdev_priv(ndev);
407066f8 1938 struct device_node *node;
e6b043d5 1939 int err = -ENXIO, i;
6b265293 1940
b5680e0b
SG		 1941 /*
1942 * The dual fec interfaces are not equivalent with enet-mac.
1943 * Here are the differences:
1944 *
1945 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1946 * - fec0 acts as the 1588 time master while fec1 is slave
1947 * - external phys can only be configured by fec0
1948 *
1949 * That is to say fec1 can not work independently. It only works
1950 * when fec0 is working. The reason behind this design is that the
1951 * second interface is added primarily for Switch mode.
1952 *
1953 * Because of the last point above, both phys are attached on fec0
1954 * mdio interface in board design, and need to be configured by
1955 * fec0 mii_bus.
1956 */
6b7e4008 1957 if ((fep->quirks & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
b5680e0b 1958 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 1959 if (mii_cnt && fec0_mii_bus) {
1960 fep->mii_bus = fec0_mii_bus;
1961 mii_cnt++;
1962 return 0;
1963 }
1964 return -ENOENT;
b5680e0b
SG		 1965 }
1966
e6b043d5 1967 fep->mii_timeout = 0;
1da177e4 1968
e6b043d5
BW		 1969 /*
1970 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 1971 *
1972 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1973 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1974 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1975 * document.
e6b043d5 1976 */
98a6eeb8 1977 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
6b7e4008 1978 if (fep->quirks & FEC_QUIRK_ENET_MAC)
230dec61
SG		 1979 fep->phy_speed--;
1980 fep->phy_speed <<= 1;
e6b043d5 1981 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 1982
e6b043d5
BW		 1983 fep->mii_bus = mdiobus_alloc();
1984 if (fep->mii_bus == NULL) {
1985 err = -ENOMEM;
1986 goto err_out;
1da177e4
LT		 1987 }
1988
e6b043d5
BW		 1989 fep->mii_bus->name = "fec_enet_mii_bus";
1990 fep->mii_bus->read = fec_enet_mdio_read;
1991 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 1992 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1993 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 1994 fep->mii_bus->priv = fep;
1995 fep->mii_bus->parent = &pdev->dev;
1996
1997 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1998 if (!fep->mii_bus->irq) {
1999 err = -ENOMEM;
2000 goto err_out_free_mdiobus;
1da177e4
LT		 2001 }
2002
e6b043d5
BW		 2003 for (i = 0; i < PHY_MAX_ADDR; i++)
2004 fep->mii_bus->irq[i] = PHY_POLL;
1da177e4 2005
407066f8
UKK		 2006 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2007 if (node) {
2008 err = of_mdiobus_register(fep->mii_bus, node);
2009 of_node_put(node);
2010 } else {
2011 err = mdiobus_register(fep->mii_bus);
2012 }
2013
2014 if (err)
e6b043d5 2015 goto err_out_free_mdio_irq;
1da177e4 2016
e163cc97
LW		 2017 mii_cnt++;
2018
b5680e0b 2019 /* save fec0 mii_bus */
6b7e4008 2020 if (fep->quirks & FEC_QUIRK_ENET_MAC)
b5680e0b
SG		 2021 fec0_mii_bus = fep->mii_bus;
2022
e6b043d5 2023 return 0;
1da177e4 2024
e6b043d5
BW		 2025err_out_free_mdio_irq:
2026 kfree(fep->mii_bus->irq);
2027err_out_free_mdiobus:
2028 mdiobus_free(fep->mii_bus);
2029err_out:
2030 return err;
1da177e4
LT		 2031}
2032
e6b043d5 2033static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 2034{
e163cc97
LW		 2035 if (--mii_cnt == 0) {
2036 mdiobus_unregister(fep->mii_bus);
2037 kfree(fep->mii_bus->irq);
2038 mdiobus_free(fep->mii_bus);
2039 }
1da177e4
LT		 2040}
2041
c556167f 2042static int fec_enet_get_settings(struct net_device *ndev,
e6b043d5 2043 struct ethtool_cmd *cmd)
1da177e4 2044{
c556167f 2045 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2046 struct phy_device *phydev = fep->phy_dev;
1da177e4 2047
e6b043d5
BW		 2048 if (!phydev)
2049 return -ENODEV;
1da177e4 2050
e6b043d5 2051 return phy_ethtool_gset(phydev, cmd);
1da177e4
LT		 2052}
2053
c556167f 2054static int fec_enet_set_settings(struct net_device *ndev,
e6b043d5 2055 struct ethtool_cmd *cmd)
1da177e4 2056{
c556167f 2057 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2058 struct phy_device *phydev = fep->phy_dev;
1da177e4 2059
e6b043d5
BW		 2060 if (!phydev)
2061 return -ENODEV;
1da177e4 2062
e6b043d5 2063 return phy_ethtool_sset(phydev, cmd);
1da177e4
LT		 2064}
2065
c556167f 2066static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 2067 struct ethtool_drvinfo *info)
1da177e4 2068{
c556167f 2069 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 2070
7826d43f
JP		 2071 strlcpy(info->driver, fep->pdev->dev.driver->name,
2072 sizeof(info->driver));
2073 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2074 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 2075}
2076
5ebae489
FL		 2077static int fec_enet_get_ts_info(struct net_device *ndev,
2078 struct ethtool_ts_info *info)
2079{
2080 struct fec_enet_private *fep = netdev_priv(ndev);
2081
2082 if (fep->bufdesc_ex) {
2083
2084 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2085 SOF_TIMESTAMPING_RX_SOFTWARE |
2086 SOF_TIMESTAMPING_SOFTWARE |
2087 SOF_TIMESTAMPING_TX_HARDWARE |
2088 SOF_TIMESTAMPING_RX_HARDWARE |
2089 SOF_TIMESTAMPING_RAW_HARDWARE;
2090 if (fep->ptp_clock)
2091 info->phc_index = ptp_clock_index(fep->ptp_clock);
2092 else
2093 info->phc_index = -1;
2094
2095 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2096 (1 << HWTSTAMP_TX_ON);
2097
2098 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2099 (1 << HWTSTAMP_FILTER_ALL);
2100 return 0;
2101 } else {
2102 return ethtool_op_get_ts_info(ndev, info);
2103 }
2104}
2105
d1391930
GR		 2106#if !defined(CONFIG_M5272)
2107
baa70a5c
FL		 2108static void fec_enet_get_pauseparam(struct net_device *ndev,
2109 struct ethtool_pauseparam *pause)
2110{
2111 struct fec_enet_private *fep = netdev_priv(ndev);
2112
2113 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2114 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2115 pause->rx_pause = pause->tx_pause;
2116}
2117
2118static int fec_enet_set_pauseparam(struct net_device *ndev,
2119 struct ethtool_pauseparam *pause)
2120{
2121 struct fec_enet_private *fep = netdev_priv(ndev);
2122
0b146ca8
RK		 2123 if (!fep->phy_dev)
2124 return -ENODEV;
2125
baa70a5c
FL		 2126 if (pause->tx_pause != pause->rx_pause) {
2127 netdev_info(ndev,
2128 "hardware only support enable/disable both tx and rx");
2129 return -EINVAL;
2130 }
2131
2132 fep->pause_flag = 0;
2133
2134 /* tx pause must be same as rx pause */
2135 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2136 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2137
2138 if (pause->rx_pause || pause->autoneg) {
2139 fep->phy_dev->supported |= ADVERTISED_Pause;
2140 fep->phy_dev->advertising |= ADVERTISED_Pause;
2141 } else {
2142 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2143 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2144 }
2145
2146 if (pause->autoneg) {
2147 if (netif_running(ndev))
2148 fec_stop(ndev);
2149 phy_start_aneg(fep->phy_dev);
2150 }
dbc64a8e 2151 if (netif_running(ndev)) {
dbc64a8e 2152 napi_disable(&fep->napi);
dbc64a8e 2153 netif_tx_lock_bh(ndev);
ef83337d 2154 fec_restart(ndev);
dbc64a8e 2155 netif_wake_queue(ndev);
6af42d42 2156 netif_tx_unlock_bh(ndev);
dbc64a8e 2157 napi_enable(&fep->napi);
dbc64a8e 2158 }
baa70a5c
FL		 2159
2160 return 0;
2161}
2162
38ae92dc
CH		 2163static const struct fec_stat {
2164 char name[ETH_GSTRING_LEN];
2165 u16 offset;
2166} fec_stats[] = {
2167 /* RMON TX */
2168 { "tx_dropped", RMON_T_DROP },
2169 { "tx_packets", RMON_T_PACKETS },
2170 { "tx_broadcast", RMON_T_BC_PKT },
2171 { "tx_multicast", RMON_T_MC_PKT },
2172 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2173 { "tx_undersize", RMON_T_UNDERSIZE },
2174 { "tx_oversize", RMON_T_OVERSIZE },
2175 { "tx_fragment", RMON_T_FRAG },
2176 { "tx_jabber", RMON_T_JAB },
2177 { "tx_collision", RMON_T_COL },
2178 { "tx_64byte", RMON_T_P64 },
2179 { "tx_65to127byte", RMON_T_P65TO127 },
2180 { "tx_128to255byte", RMON_T_P128TO255 },
2181 { "tx_256to511byte", RMON_T_P256TO511 },
2182 { "tx_512to1023byte", RMON_T_P512TO1023 },
2183 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2184 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2185 { "tx_octets", RMON_T_OCTETS },
2186
2187 /* IEEE TX */
2188 { "IEEE_tx_drop", IEEE_T_DROP },
2189 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2190 { "IEEE_tx_1col", IEEE_T_1COL },
2191 { "IEEE_tx_mcol", IEEE_T_MCOL },
2192 { "IEEE_tx_def", IEEE_T_DEF },
2193 { "IEEE_tx_lcol", IEEE_T_LCOL },
2194 { "IEEE_tx_excol", IEEE_T_EXCOL },
2195 { "IEEE_tx_macerr", IEEE_T_MACERR },
2196 { "IEEE_tx_cserr", IEEE_T_CSERR },
2197 { "IEEE_tx_sqe", IEEE_T_SQE },
2198 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2199 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2200
2201 /* RMON RX */
2202 { "rx_packets", RMON_R_PACKETS },
2203 { "rx_broadcast", RMON_R_BC_PKT },
2204 { "rx_multicast", RMON_R_MC_PKT },
2205 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2206 { "rx_undersize", RMON_R_UNDERSIZE },
2207 { "rx_oversize", RMON_R_OVERSIZE },
2208 { "rx_fragment", RMON_R_FRAG },
2209 { "rx_jabber", RMON_R_JAB },
2210 { "rx_64byte", RMON_R_P64 },
2211 { "rx_65to127byte", RMON_R_P65TO127 },
2212 { "rx_128to255byte", RMON_R_P128TO255 },
2213 { "rx_256to511byte", RMON_R_P256TO511 },
2214 { "rx_512to1023byte", RMON_R_P512TO1023 },
2215 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2216 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2217 { "rx_octets", RMON_R_OCTETS },
2218
2219 /* IEEE RX */
2220 { "IEEE_rx_drop", IEEE_R_DROP },
2221 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2222 { "IEEE_rx_crc", IEEE_R_CRC },
2223 { "IEEE_rx_align", IEEE_R_ALIGN },
2224 { "IEEE_rx_macerr", IEEE_R_MACERR },
2225 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2226 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2227};
2228
2229static void fec_enet_get_ethtool_stats(struct net_device *dev,
2230 struct ethtool_stats *stats, u64 *data)
2231{
2232 struct fec_enet_private *fep = netdev_priv(dev);
2233 int i;
2234
2235 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2236 data[i] = readl(fep->hwp + fec_stats[i].offset);
2237}
2238
2239static void fec_enet_get_strings(struct net_device *netdev,
2240 u32 stringset, u8 *data)
2241{
2242 int i;
2243 switch (stringset) {
2244 case ETH_SS_STATS:
2245 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2246 memcpy(data + i * ETH_GSTRING_LEN,
2247 fec_stats[i].name, ETH_GSTRING_LEN);
2248 break;
2249 }
2250}
2251
2252static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2253{
2254 switch (sset) {
2255 case ETH_SS_STATS:
2256 return ARRAY_SIZE(fec_stats);
2257 default:
2258 return -EOPNOTSUPP;
2259 }
2260}
d1391930 2261#endif /* !defined(CONFIG_M5272) */
38ae92dc 2262
32bc9b46
CH		 2263static int fec_enet_nway_reset(struct net_device *dev)
2264{
2265 struct fec_enet_private *fep = netdev_priv(dev);
2266 struct phy_device *phydev = fep->phy_dev;
2267
2268 if (!phydev)
2269 return -ENODEV;
2270
2271 return genphy_restart_aneg(phydev);
2272}
2273
d851b47b
FD		 2274/* ITR clock source is enet system clock (clk_ahb).
2275 * TCTT unit is cycle_ns * 64 cycle
2276 * So, the ICTT value = X us / (cycle_ns * 64)
2277 */
2278static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2279{
2280 struct fec_enet_private *fep = netdev_priv(ndev);
2281
2282 return us * (fep->itr_clk_rate / 64000) / 1000;
2283}
2284
2285/* Set threshold for interrupt coalescing */
2286static void fec_enet_itr_coal_set(struct net_device *ndev)
2287{
2288 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2289 int rx_itr, tx_itr;
2290
6b7e4008 2291 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2292 return;
2293
2294 /* Must be greater than zero to avoid unpredictable behavior */
2295 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2296 !fep->tx_time_itr || !fep->tx_pkts_itr)
2297 return;
2298
2299 /* Select enet system clock as Interrupt Coalescing
2300 * timer Clock Source
2301 */
2302 rx_itr = FEC_ITR_CLK_SEL;
2303 tx_itr = FEC_ITR_CLK_SEL;
2304
2305 /* set ICFT and ICTT */
2306 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2307 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2308 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2309 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2310
2311 rx_itr |= FEC_ITR_EN;
2312 tx_itr |= FEC_ITR_EN;
2313
2314 writel(tx_itr, fep->hwp + FEC_TXIC0);
2315 writel(rx_itr, fep->hwp + FEC_RXIC0);
2316 writel(tx_itr, fep->hwp + FEC_TXIC1);
2317 writel(rx_itr, fep->hwp + FEC_RXIC1);
2318 writel(tx_itr, fep->hwp + FEC_TXIC2);
2319 writel(rx_itr, fep->hwp + FEC_RXIC2);
2320}
2321
2322static int
2323fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2324{
2325 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b 2326
6b7e4008 2327 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2328 return -EOPNOTSUPP;
2329
2330 ec->rx_coalesce_usecs = fep->rx_time_itr;
2331 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2332
2333 ec->tx_coalesce_usecs = fep->tx_time_itr;
2334 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2335
2336 return 0;
2337}
2338
2339static int
2340fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2341{
2342 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2343 unsigned int cycle;
2344
6b7e4008 2345 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2346 return -EOPNOTSUPP;
2347
2348 if (ec->rx_max_coalesced_frames > 255) {
2349 pr_err("Rx coalesced frames exceed hardware limiation");
2350 return -EINVAL;
2351 }
2352
2353 if (ec->tx_max_coalesced_frames > 255) {
2354 pr_err("Tx coalesced frame exceed hardware limiation");
2355 return -EINVAL;
2356 }
2357
2358 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2359 if (cycle > 0xFFFF) {
2360 pr_err("Rx coalesed usec exceeed hardware limiation");
2361 return -EINVAL;
2362 }
2363
2364 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2365 if (cycle > 0xFFFF) {
2366 pr_err("Rx coalesed usec exceeed hardware limiation");
2367 return -EINVAL;
2368 }
2369
2370 fep->rx_time_itr = ec->rx_coalesce_usecs;
2371 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2372
2373 fep->tx_time_itr = ec->tx_coalesce_usecs;
2374 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2375
2376 fec_enet_itr_coal_set(ndev);
2377
2378 return 0;
2379}
2380
2381static void fec_enet_itr_coal_init(struct net_device *ndev)
2382{
2383 struct ethtool_coalesce ec;
2384
2385 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2386 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2387
2388 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2389 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2390
2391 fec_enet_set_coalesce(ndev, &ec);
2392}
2393
1b7bde6d
NA		 2394static int fec_enet_get_tunable(struct net_device *netdev,
2395 const struct ethtool_tunable *tuna,
2396 void *data)
2397{
2398 struct fec_enet_private *fep = netdev_priv(netdev);
2399 int ret = 0;
2400
2401 switch (tuna->id) {
2402 case ETHTOOL_RX_COPYBREAK:
2403 *(u32 *)data = fep->rx_copybreak;
2404 break;
2405 default:
2406 ret = -EINVAL;
2407 break;
2408 }
2409
2410 return ret;
2411}
2412
2413static int fec_enet_set_tunable(struct net_device *netdev,
2414 const struct ethtool_tunable *tuna,
2415 const void *data)
2416{
2417 struct fec_enet_private *fep = netdev_priv(netdev);
2418 int ret = 0;
2419
2420 switch (tuna->id) {
2421 case ETHTOOL_RX_COPYBREAK:
2422 fep->rx_copybreak = *(u32 *)data;
2423 break;
2424 default:
2425 ret = -EINVAL;
2426 break;
2427 }
2428
2429 return ret;
2430}
2431
9b07be4b 2432static const struct ethtool_ops fec_enet_ethtool_ops = {
e6b043d5
BW		 2433 .get_settings = fec_enet_get_settings,
2434 .set_settings = fec_enet_set_settings,
2435 .get_drvinfo = fec_enet_get_drvinfo,
32bc9b46 2436 .nway_reset = fec_enet_nway_reset,
c1d7c48f 2437 .get_link = ethtool_op_get_link,
d851b47b
FD		 2438 .get_coalesce = fec_enet_get_coalesce,
2439 .set_coalesce = fec_enet_set_coalesce,
38ae92dc 2440#ifndef CONFIG_M5272
c1d7c48f
RK		 2441 .get_pauseparam = fec_enet_get_pauseparam,
2442 .set_pauseparam = fec_enet_set_pauseparam,
38ae92dc 2443 .get_strings = fec_enet_get_strings,
c1d7c48f 2444 .get_ethtool_stats = fec_enet_get_ethtool_stats,
38ae92dc
CH		 2445 .get_sset_count = fec_enet_get_sset_count,
2446#endif
c1d7c48f 2447 .get_ts_info = fec_enet_get_ts_info,
1b7bde6d
NA		 2448 .get_tunable = fec_enet_get_tunable,
2449 .set_tunable = fec_enet_set_tunable,
e6b043d5 2450};
1da177e4 2451
c556167f 2452static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2453{
c556167f 2454 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2455 struct phy_device *phydev = fep->phy_dev;
1da177e4 2456
c556167f 2457 if (!netif_running(ndev))
e6b043d5 2458 return -EINVAL;
1da177e4 2459
e6b043d5
BW		 2460 if (!phydev)
2461 return -ENODEV;
2462
1d5244d0
BH		 2463 if (fep->bufdesc_ex) {
2464 if (cmd == SIOCSHWTSTAMP)
2465 return fec_ptp_set(ndev, rq);
2466 if (cmd == SIOCGHWTSTAMP)
2467 return fec_ptp_get(ndev, rq);
2468 }
ff43da86 2469
28b04113 2470 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2471}
2472
c556167f 2473static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2474{
c556167f 2475 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2476 unsigned int i;
f0b3fbea
SH		 2477 struct sk_buff *skb;
2478 struct bufdesc *bdp;
4d494cdc
FD		 2479 struct fec_enet_priv_tx_q *txq;
2480 struct fec_enet_priv_rx_q *rxq;
59d0f746
FL		 2481 unsigned int q;
2482
2483 for (q = 0; q < fep->num_rx_queues; q++) {
2484 rxq = fep->rx_queue[q];
2485 bdp = rxq->rx_bd_base;
2486 for (i = 0; i < rxq->rx_ring_size; i++) {
2487 skb = rxq->rx_skbuff[i];
2488 rxq->rx_skbuff[i] = NULL;
2489 if (skb) {
2490 dma_unmap_single(&fep->pdev->dev,
2491 bdp->cbd_bufaddr,
b64bf4b7 2492 FEC_ENET_RX_FRSIZE - fep->rx_align,
59d0f746
FL		 2493 DMA_FROM_DEVICE);
2494 dev_kfree_skb(skb);
2495 }
2496 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2497 }
2498 }
4d494cdc 2499
59d0f746
FL		 2500 for (q = 0; q < fep->num_tx_queues; q++) {
2501 txq = fep->tx_queue[q];
2502 bdp = txq->tx_bd_base;
2503 for (i = 0; i < txq->tx_ring_size; i++) {
2504 kfree(txq->tx_bounce[i]);
2505 txq->tx_bounce[i] = NULL;
2506 skb = txq->tx_skbuff[i];
2507 txq->tx_skbuff[i] = NULL;
f0b3fbea 2508 dev_kfree_skb(skb);
730ee360 2509 }
f0b3fbea 2510 }
59d0f746 2511}
f0b3fbea 2512
59d0f746
FL		 2513static void fec_enet_free_queue(struct net_device *ndev)
2514{
2515 struct fec_enet_private *fep = netdev_priv(ndev);
2516 int i;
2517 struct fec_enet_priv_tx_q *txq;
2518
2519 for (i = 0; i < fep->num_tx_queues; i++)
2520 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2521 txq = fep->tx_queue[i];
2522 dma_free_coherent(NULL,
2523 txq->tx_ring_size * TSO_HEADER_SIZE,
2524 txq->tso_hdrs,
2525 txq->tso_hdrs_dma);
2526 }
2527
2528 for (i = 0; i < fep->num_rx_queues; i++)
2529 if (fep->rx_queue[i])
2530 kfree(fep->rx_queue[i]);
2531
2532 for (i = 0; i < fep->num_tx_queues; i++)
2533 if (fep->tx_queue[i])
2534 kfree(fep->tx_queue[i]);
2535}
2536
2537static int fec_enet_alloc_queue(struct net_device *ndev)
2538{
2539 struct fec_enet_private *fep = netdev_priv(ndev);
2540 int i;
2541 int ret = 0;
2542 struct fec_enet_priv_tx_q *txq;
2543
2544 for (i = 0; i < fep->num_tx_queues; i++) {
2545 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2546 if (!txq) {
2547 ret = -ENOMEM;
2548 goto alloc_failed;
2549 }
2550
2551 fep->tx_queue[i] = txq;
2552 txq->tx_ring_size = TX_RING_SIZE;
2553 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2554
2555 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2556 txq->tx_wake_threshold =
2557 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2558
2559 txq->tso_hdrs = dma_alloc_coherent(NULL,
2560 txq->tx_ring_size * TSO_HEADER_SIZE,
2561 &txq->tso_hdrs_dma,
2562 GFP_KERNEL);
2563 if (!txq->tso_hdrs) {
2564 ret = -ENOMEM;
2565 goto alloc_failed;
2566 }
8b7c9efa 2567 }
59d0f746
FL		 2568
2569 for (i = 0; i < fep->num_rx_queues; i++) {
2570 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2571 GFP_KERNEL);
2572 if (!fep->rx_queue[i]) {
2573 ret = -ENOMEM;
2574 goto alloc_failed;
2575 }
2576
2577 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2578 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2579 }
2580 return ret;
2581
2582alloc_failed:
2583 fec_enet_free_queue(ndev);
2584 return ret;
f0b3fbea
SH		 2585}
2586
59d0f746
FL		 2587static int
2588fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
f0b3fbea 2589{
c556167f 2590 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2591 unsigned int i;
f0b3fbea
SH		 2592 struct sk_buff *skb;
2593 struct bufdesc *bdp;
4d494cdc 2594 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 2595
59d0f746 2596 rxq = fep->rx_queue[queue];
4d494cdc
FD		 2597 bdp = rxq->rx_bd_base;
2598 for (i = 0; i < rxq->rx_ring_size; i++) {
b72061a3 2599 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2600 if (!skb)
2601 goto err_alloc;
f0b3fbea 2602
1b7bde6d 2603 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
730ee360 2604 dev_kfree_skb(skb);
ffdce2cc 2605 goto err_alloc;
d842a31f 2606 }
730ee360 2607
4d494cdc 2608 rxq->rx_skbuff[i] = skb;
f0b3fbea 2609 bdp->cbd_sc = BD_ENET_RX_EMPTY;
ff43da86
FL		 2610
2611 if (fep->bufdesc_ex) {
2612 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2613 ebdp->cbd_esc = BD_ENET_RX_INT;
2614 }
2615
59d0f746 2616 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
f0b3fbea
SH		 2617 }
2618
2619 /* Set the last buffer to wrap. */
59d0f746 2620 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
f0b3fbea 2621 bdp->cbd_sc |= BD_SC_WRAP;
59d0f746 2622 return 0;
f0b3fbea 2623
59d0f746
FL		 2624 err_alloc:
2625 fec_enet_free_buffers(ndev);
2626 return -ENOMEM;
2627}
2628
2629static int
2630fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2631{
2632 struct fec_enet_private *fep = netdev_priv(ndev);
2633 unsigned int i;
2634 struct bufdesc *bdp;
2635 struct fec_enet_priv_tx_q *txq;
2636
2637 txq = fep->tx_queue[queue];
4d494cdc
FD		 2638 bdp = txq->tx_bd_base;
2639 for (i = 0; i < txq->tx_ring_size; i++) {
2640 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2641 if (!txq->tx_bounce[i])
ffdce2cc 2642 goto err_alloc;
f0b3fbea
SH		 2643
2644 bdp->cbd_sc = 0;
2645 bdp->cbd_bufaddr = 0;
6605b730 2646
ff43da86
FL		 2647 if (fep->bufdesc_ex) {
2648 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
96d2222b 2649 ebdp->cbd_esc = BD_ENET_TX_INT;
ff43da86
FL		 2650 }
2651
59d0f746 2652 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
f0b3fbea
SH		 2653 }
2654
2655 /* Set the last buffer to wrap. */
59d0f746 2656 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
f0b3fbea
SH		 2657 bdp->cbd_sc |= BD_SC_WRAP;
2658
2659 return 0;
ffdce2cc
RK		 2660
2661 err_alloc:
2662 fec_enet_free_buffers(ndev);
2663 return -ENOMEM;
f0b3fbea
SH		 2664}
2665
59d0f746
FL		 2666static int fec_enet_alloc_buffers(struct net_device *ndev)
2667{
2668 struct fec_enet_private *fep = netdev_priv(ndev);
2669 unsigned int i;
2670
2671 for (i = 0; i < fep->num_rx_queues; i++)
2672 if (fec_enet_alloc_rxq_buffers(ndev, i))
2673 return -ENOMEM;
2674
2675 for (i = 0; i < fep->num_tx_queues; i++)
2676 if (fec_enet_alloc_txq_buffers(ndev, i))
2677 return -ENOMEM;
2678 return 0;
2679}
2680
1da177e4 2681static int
c556167f 2682fec_enet_open(struct net_device *ndev)
1da177e4 2683{
c556167f 2684 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2685 int ret;
1da177e4 2686
5bbde4d2 2687 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2688 ret = fec_enet_clk_enable(ndev, true);
2689 if (ret)
2690 return ret;
2691
1da177e4
LT		 2692 /* I should reset the ring buffers here, but I don't yet know
2693 * a simple way to do that.
2694 */
1da177e4 2695
c556167f 2696 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea 2697 if (ret)
681d2421 2698 goto err_enet_alloc;
f0b3fbea 2699
418bd0d4 2700 /* Probe and connect to PHY when open the interface */
c556167f 2701 ret = fec_enet_mii_probe(ndev);
681d2421
FE		 2702 if (ret)
2703 goto err_enet_mii_probe;
ce5eaf02 2704
ef83337d 2705 fec_restart(ndev);
ce5eaf02 2706 napi_enable(&fep->napi);
e6b043d5 2707 phy_start(fep->phy_dev);
4d494cdc
FD		 2708 netif_tx_start_all_queues(ndev);
2709
22f6b860 2710 return 0;
681d2421
FE		 2711
2712err_enet_mii_probe:
2713 fec_enet_free_buffers(ndev);
2714err_enet_alloc:
2715 fec_enet_clk_enable(ndev, false);
2716 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2717 return ret;
1da177e4
LT		 2718}
2719
2720static int
c556167f 2721fec_enet_close(struct net_device *ndev)
1da177e4 2722{
c556167f 2723 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2724
d76cfae9
RK		 2725 phy_stop(fep->phy_dev);
2726
31a6de34
RK		 2727 if (netif_device_present(ndev)) {
2728 napi_disable(&fep->napi);
2729 netif_tx_disable(ndev);
8bbbd3c1 2730 fec_stop(ndev);
31a6de34 2731 }
1da177e4 2732
635cf17c 2733 phy_disconnect(fep->phy_dev);
0b146ca8 2734 fep->phy_dev = NULL;
418bd0d4 2735
e8fcfcd5 2736 fec_enet_clk_enable(ndev, false);
5bbde4d2 2737 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
db8880bc 2738 fec_enet_free_buffers(ndev);
f0b3fbea 2739
1da177e4
LT		 2740 return 0;
2741}
2742
1da177e4
LT		 2743/* Set or clear the multicast filter for this adaptor.
2744 * Skeleton taken from sunlance driver.
2745 * The CPM Ethernet implementation allows Multicast as well as individual
2746 * MAC address filtering. Some of the drivers check to make sure it is
2747 * a group multicast address, and discard those that are not. I guess I
2748 * will do the same for now, but just remove the test if you want
2749 * individual filtering as well (do the upper net layers want or support
2750 * this kind of feature?).
2751 */
2752
2753#define HASH_BITS 6 /* #bits in hash */
2754#define CRC32_POLY 0xEDB88320
2755
c556167f 2756static void set_multicast_list(struct net_device *ndev)
1da177e4 2757{
c556167f 2758 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 2759 struct netdev_hw_addr *ha;
48e2f183 2760 unsigned int i, bit, data, crc, tmp;
1da177e4
LT		 2761 unsigned char hash;
2762
c556167f 2763 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 2764 tmp = readl(fep->hwp + FEC_R_CNTRL);
2765 tmp |= 0x8;
2766 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 2767 return;
2768 }
1da177e4 2769
4e831836
SH		 2770 tmp = readl(fep->hwp + FEC_R_CNTRL);
2771 tmp &= ~0x8;
2772 writel(tmp, fep->hwp + FEC_R_CNTRL);
2773
c556167f 2774 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 2775 /* Catch all multicast addresses, so set the
2776 * filter to all 1's
2777 */
2778 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2779 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2780
2781 return;
2782 }
2783
2784 /* Clear filter and add the addresses in hash register
2785 */
2786 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2787 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2788
c556167f 2789 netdev_for_each_mc_addr(ha, ndev) {
4e831836
SH		 2790 /* calculate crc32 value of mac address */
2791 crc = 0xffffffff;
2792
c556167f 2793 for (i = 0; i < ndev->addr_len; i++) {
22bedad3 2794 data = ha->addr[i];
4e831836
SH		 2795 for (bit = 0; bit < 8; bit++, data >>= 1) {
2796 crc = (crc >> 1) ^
2797 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1da177e4
LT		 2798 }
2799 }
4e831836
SH		 2800
2801 /* only upper 6 bits (HASH_BITS) are used
2802 * which point to specific bit in he hash registers
2803 */
2804 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2805
2806 if (hash > 31) {
2807 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2808 tmp |= 1 << (hash - 32);
2809 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2810 } else {
2811 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2812 tmp |= 1 << hash;
2813 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2814 }
1da177e4
LT		 2815 }
2816}
2817
22f6b860 2818/* Set a MAC change in hardware. */
009fda83 2819static int
c556167f 2820fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 2821{
c556167f 2822 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 2823 struct sockaddr *addr = p;
2824
44934fac
LS		 2825 if (addr) {
2826 if (!is_valid_ether_addr(addr->sa_data))
2827 return -EADDRNOTAVAIL;
2828 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2829 }
1da177e4 2830
c556167f
UKK		 2831 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2832 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 2833 fep->hwp + FEC_ADDR_LOW);
c556167f 2834 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 2835 fep->hwp + FEC_ADDR_HIGH);
009fda83 2836 return 0;
1da177e4
LT		 2837}
2838
7f5c6add 2839#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 2840/**
2841 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 2842 * @dev: The FEC network adapter
2843 *
2844 * Polled functionality used by netconsole and others in non interrupt mode
2845 *
2846 */
47a5247f 2847static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 2848{
2849 int i;
2850 struct fec_enet_private *fep = netdev_priv(dev);
2851
2852 for (i = 0; i < FEC_IRQ_NUM; i++) {
2853 if (fep->irq[i] > 0) {
2854 disable_irq(fep->irq[i]);
2855 fec_enet_interrupt(fep->irq[i], dev);
2856 enable_irq(fep->irq[i]);
2857 }
2858 }
2859}
2860#endif
2861
8506fa1d 2862#define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
5bc26726 2863static inline void fec_enet_set_netdev_features(struct net_device *netdev,
4c09eed9
JB		 2864 netdev_features_t features)
2865{
2866 struct fec_enet_private *fep = netdev_priv(netdev);
2867 netdev_features_t changed = features ^ netdev->features;
2868
2869 netdev->features = features;
2870
2871 /* Receive checksum has been changed */
2872 if (changed & NETIF_F_RXCSUM) {
2873 if (features & NETIF_F_RXCSUM)
2874 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2875 else
2876 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
8506fa1d 2877 }
5bc26726
NA		 2878}
2879
2880static int fec_set_features(struct net_device *netdev,
2881 netdev_features_t features)
2882{
2883 struct fec_enet_private *fep = netdev_priv(netdev);
2884 netdev_features_t changed = features ^ netdev->features;
4c09eed9 2885
8506fa1d 2886 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
5bc26726
NA		 2887 napi_disable(&fep->napi);
2888 netif_tx_lock_bh(netdev);
2889 fec_stop(netdev);
2890 fec_enet_set_netdev_features(netdev, features);
ef83337d 2891 fec_restart(netdev);
4d494cdc 2892 netif_tx_wake_all_queues(netdev);
8506fa1d
RK		 2893 netif_tx_unlock_bh(netdev);
2894 napi_enable(&fep->napi);
5bc26726
NA		 2895 } else {
2896 fec_enet_set_netdev_features(netdev, features);
4c09eed9
JB		 2897 }
2898
2899 return 0;
2900}
2901
009fda83
SH		 2902static const struct net_device_ops fec_netdev_ops = {
2903 .ndo_open = fec_enet_open,
2904 .ndo_stop = fec_enet_close,
2905 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 2906 .ndo_set_rx_mode = set_multicast_list,
635ecaa7 2907 .ndo_change_mtu = eth_change_mtu,
009fda83
SH		 2908 .ndo_validate_addr = eth_validate_addr,
2909 .ndo_tx_timeout = fec_timeout,
2910 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 2911 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 2912#ifdef CONFIG_NET_POLL_CONTROLLER
2913 .ndo_poll_controller = fec_poll_controller,
2914#endif
4c09eed9 2915 .ndo_set_features = fec_set_features,
009fda83
SH		 2916};
2917
1da177e4
LT		 2918 /*
2919 * XXX: We need to clean up on failure exits here.
ead73183 2920 *
1da177e4 2921 */
c556167f 2922static int fec_enet_init(struct net_device *ndev)
1da177e4 2923{
c556167f 2924 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 2925 struct fec_enet_priv_tx_q *txq;
2926 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 2927 struct bufdesc *cbd_base;
4d494cdc 2928 dma_addr_t bd_dma;
55d0218a 2929 int bd_size;
59d0f746 2930 unsigned int i;
55d0218a 2931
41ef84ce
FD		 2932#if defined(CONFIG_ARM)
2933 fep->rx_align = 0xf;
2934 fep->tx_align = 0xf;
2935#else
2936 fep->rx_align = 0x3;
2937 fep->tx_align = 0x3;
2938#endif
2939
59d0f746 2940 fec_enet_alloc_queue(ndev);
79f33912 2941
55d0218a
NA		 2942 if (fep->bufdesc_ex)
2943 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2944 else
2945 fep->bufdesc_size = sizeof(struct bufdesc);
4d494cdc 2946 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
55d0218a 2947 fep->bufdesc_size;
1da177e4 2948
8d4dd5cf 2949 /* Allocate memory for buffer descriptors. */
4d494cdc 2950 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
d0320f75 2951 GFP_KERNEL);
4d494cdc 2952 if (!cbd_base) {
79f33912
NA		 2953 return -ENOMEM;
2954 }
2955
4d494cdc 2956 memset(cbd_base, 0, bd_size);
1da177e4 2957
49da97dc 2958 /* Get the Ethernet address */
c556167f 2959 fec_get_mac(ndev);
44934fac
LS		 2960 /* make sure MAC we just acquired is programmed into the hw */
2961 fec_set_mac_address(ndev, NULL);
1da177e4 2962
8d4dd5cf 2963 /* Set receive and transmit descriptor base. */
59d0f746
FL		 2964 for (i = 0; i < fep->num_rx_queues; i++) {
2965 rxq = fep->rx_queue[i];
2966 rxq->index = i;
2967 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
2968 rxq->bd_dma = bd_dma;
2969 if (fep->bufdesc_ex) {
2970 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
2971 cbd_base = (struct bufdesc *)
2972 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
2973 } else {
2974 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
2975 cbd_base += rxq->rx_ring_size;
2976 }
2977 }
2978
2979 for (i = 0; i < fep->num_tx_queues; i++) {
2980 txq = fep->tx_queue[i];
2981 txq->index = i;
2982 txq->tx_bd_base = (struct bufdesc *)cbd_base;
2983 txq->bd_dma = bd_dma;
2984 if (fep->bufdesc_ex) {
2985 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
2986 cbd_base = (struct bufdesc *)
2987 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
2988 } else {
2989 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
2990 cbd_base += txq->tx_ring_size;
2991 }
2992 }
4d494cdc 2993
1da177e4 2994
22f6b860 2995 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 2996 ndev->watchdog_timeo = TX_TIMEOUT;
2997 ndev->netdev_ops = &fec_netdev_ops;
2998 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 2999
dc975382 3000 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 3001 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 3002
6b7e4008 3003 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 3004 /* enable hw VLAN support */
3005 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 3006
6b7e4008 3007 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 3008 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3009
48496255
SG		 3010 /* enable hw accelerator */
3011 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 3012 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 3013 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3014 }
4c09eed9 3015
6b7e4008 3016 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
41ef84ce
FD		 3017 fep->tx_align = 0;
3018 fep->rx_align = 0x3f;
3019 }
3020
09d1e541
NA		 3021 ndev->hw_features = ndev->features;
3022
ef83337d 3023 fec_restart(ndev);
1da177e4 3024
1da177e4
LT		 3025 return 0;
3026}
3027
ca2cc333 3028#ifdef CONFIG_OF
33897cc8 3029static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3030{
3031 int err, phy_reset;
a3caad0a 3032 int msec = 1;
ca2cc333
SG		 3033 struct device_node *np = pdev->dev.of_node;
3034
3035 if (!np)
a9b2c8ef 3036 return;
ca2cc333 3037
a3caad0a
SG		 3038 of_property_read_u32(np, "phy-reset-duration", &msec);
3039 /* A sane reset duration should not be longer than 1s */
3040 if (msec > 1000)
3041 msec = 1;
3042
ca2cc333 3043 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
07dcf8e9
FE		 3044 if (!gpio_is_valid(phy_reset))
3045 return;
3046
119fc007
SG		 3047 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3048 GPIOF_OUT_INIT_LOW, "phy-reset");
ca2cc333 3049 if (err) {
07dcf8e9 3050 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
a9b2c8ef 3051 return;
ca2cc333 3052 }
a3caad0a 3053 msleep(msec);
ca2cc333 3054 gpio_set_value(phy_reset, 1);
ca2cc333
SG		 3055}
3056#else /* CONFIG_OF */
0c7768a0 3057static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3058{
3059 /*
3060 * In case of platform probe, the reset has been done
3061 * by machine code.
3062 */
ca2cc333
SG		 3063}
3064#endif /* CONFIG_OF */
3065
9fc095f1
FD		 3066static void
3067fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3068{
3069 struct device_node *np = pdev->dev.of_node;
3070 int err;
3071
3072 *num_tx = *num_rx = 1;
3073
3074 if (!np || !of_device_is_available(np))
3075 return;
3076
3077 /* parse the num of tx and rx queues */
3078 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
b7bd75cf 3079 if (err)
9fc095f1 3080 *num_tx = 1;
b7bd75cf
FL		 3081
3082 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3083 if (err)
9fc095f1 3084 *num_rx = 1;
9fc095f1
FD		 3085
3086 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
b7bd75cf
FL		 3087 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3088 *num_tx);
9fc095f1
FD		 3089 *num_tx = 1;
3090 return;
3091 }
3092
3093 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
b7bd75cf
FL		 3094 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3095 *num_rx);
9fc095f1
FD		 3096 *num_rx = 1;
3097 return;
3098 }
3099
3100}
3101
33897cc8 3102static int
ead73183
SH		 3103fec_probe(struct platform_device *pdev)
3104{
3105 struct fec_enet_private *fep;
5eb32bd0 3106 struct fec_platform_data *pdata;
ead73183
SH		 3107 struct net_device *ndev;
3108 int i, irq, ret = 0;
3109 struct resource *r;
ca2cc333 3110 const struct of_device_id *of_id;
43af940c 3111 static int dev_id;
407066f8 3112 struct device_node *np = pdev->dev.of_node, *phy_node;
b7bd75cf
FL		 3113 int num_tx_qs;
3114 int num_rx_qs;
ca2cc333 3115
9fc095f1
FD		 3116 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3117
ead73183 3118 /* Init network device */
9fc095f1
FD		 3119 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3120 num_tx_qs, num_rx_qs);
83e519b6
FE		 3121 if (!ndev)
3122 return -ENOMEM;
ead73183
SH		 3123
3124 SET_NETDEV_DEV(ndev, &pdev->dev);
3125
3126 /* setup board info structure */
3127 fep = netdev_priv(ndev);
ead73183 3128
6b7e4008
LW		 3129 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3130 if (of_id)
3131 pdev->id_entry = of_id->data;
3132 fep->quirks = pdev->id_entry->driver_data;
3133
9fc095f1
FD		 3134 fep->num_rx_queues = num_rx_qs;
3135 fep->num_tx_queues = num_tx_qs;
3136
d1391930 3137#if !defined(CONFIG_M5272)
baa70a5c 3138 /* default enable pause frame auto negotiation */
6b7e4008 3139 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
baa70a5c 3140 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 3141#endif
baa70a5c 3142
5bbde4d2
NA		 3143 /* Select default pin state */
3144 pinctrl_pm_select_default_state(&pdev->dev);
3145
399db75b 3146 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941e173a
TB		 3147 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3148 if (IS_ERR(fep->hwp)) {
3149 ret = PTR_ERR(fep->hwp);
3150 goto failed_ioremap;
3151 }
3152
e6b043d5 3153 fep->pdev = pdev;
43af940c 3154 fep->dev_id = dev_id++;
ead73183 3155
ead73183
SH		 3156 platform_set_drvdata(pdev, ndev);
3157
407066f8
UKK		 3158 phy_node = of_parse_phandle(np, "phy-handle", 0);
3159 if (!phy_node && of_phy_is_fixed_link(np)) {
3160 ret = of_phy_register_fixed_link(np);
3161 if (ret < 0) {
3162 dev_err(&pdev->dev,
3163 "broken fixed-link specification\n");
3164 goto failed_phy;
3165 }
3166 phy_node = of_node_get(np);
3167 }
3168 fep->phy_node = phy_node;
3169
6c5f7808 3170 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 3171 if (ret < 0) {
94660ba0 3172 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 3173 if (pdata)
3174 fep->phy_interface = pdata->phy;
3175 else
3176 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3177 } else {
3178 fep->phy_interface = ret;
3179 }
3180
f4d40de3
SH		 3181 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3182 if (IS_ERR(fep->clk_ipg)) {
3183 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 3184 goto failed_clk;
3185 }
f4d40de3
SH		 3186
3187 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3188 if (IS_ERR(fep->clk_ahb)) {
3189 ret = PTR_ERR(fep->clk_ahb);
3190 goto failed_clk;
3191 }
3192
d851b47b
FD		 3193 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3194
daa7d392
WS		 3195 /* enet_out is optional, depends on board */
3196 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3197 if (IS_ERR(fep->clk_enet_out))
3198 fep->clk_enet_out = NULL;
3199
91c0d987
NA		 3200 fep->ptp_clk_on = false;
3201 mutex_init(&fep->ptp_clk_mutex);
9b5330ed
FD		 3202
3203 /* clk_ref is optional, depends on board */
3204 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3205 if (IS_ERR(fep->clk_ref))
3206 fep->clk_ref = NULL;
3207
6b7e4008 3208 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730
FL		 3209 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3210 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 3211 fep->clk_ptp = NULL;
217b5844 3212 fep->bufdesc_ex = false;
6605b730 3213 }
6605b730 3214
e8fcfcd5 3215 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 3216 if (ret)
3217 goto failed_clk;
3218
f4e9f3d2
FE		 3219 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3220 if (!IS_ERR(fep->reg_phy)) {
3221 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 3222 if (ret) {
3223 dev_err(&pdev->dev,
3224 "Failed to enable phy regulator: %d\n", ret);
3225 goto failed_regulator;
3226 }
f6a4d607
FE		 3227 } else {
3228 fep->reg_phy = NULL;
5fa9c0fe
SG		 3229 }
3230
2ca9b2aa
SG		 3231 fec_reset_phy(pdev);
3232
e2f8d555 3233 if (fep->bufdesc_ex)
ca162a82 3234 fec_ptp_init(pdev);
e2f8d555
FE		 3235
3236 ret = fec_enet_init(ndev);
3237 if (ret)
3238 goto failed_init;
3239
3240 for (i = 0; i < FEC_IRQ_NUM; i++) {
3241 irq = platform_get_irq(pdev, i);
3242 if (irq < 0) {
3243 if (i)
3244 break;
3245 ret = irq;
3246 goto failed_irq;
3247 }
0d9b2ab1 3248 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 3249 0, pdev->name, ndev);
0d9b2ab1 3250 if (ret)
e2f8d555 3251 goto failed_irq;
e2f8d555
FE		 3252 }
3253
b4d39b53 3254 init_completion(&fep->mdio_done);
e6b043d5
BW		 3255 ret = fec_enet_mii_init(pdev);
3256 if (ret)
3257 goto failed_mii_init;
3258
03c698c9
OS		 3259 /* Carrier starts down, phylib will bring it up */
3260 netif_carrier_off(ndev);
e8fcfcd5 3261 fec_enet_clk_enable(ndev, false);
5bbde4d2 3262 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 3263
ead73183
SH		 3264 ret = register_netdev(ndev);
3265 if (ret)
3266 goto failed_register;
3267
eb1d0640
FE		 3268 if (fep->bufdesc_ex && fep->ptp_clock)
3269 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3270
1b7bde6d 3271 fep->rx_copybreak = COPYBREAK_DEFAULT;
36cdc743 3272 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
ead73183
SH		 3273 return 0;
3274
3275failed_register:
e6b043d5
BW		 3276 fec_enet_mii_remove(fep);
3277failed_mii_init:
7a2bbd8d 3278failed_irq:
7a2bbd8d 3279failed_init:
f6a4d607
FE		 3280 if (fep->reg_phy)
3281 regulator_disable(fep->reg_phy);
5fa9c0fe 3282failed_regulator:
e8fcfcd5 3283 fec_enet_clk_enable(ndev, false);
ead73183 3284failed_clk:
407066f8
UKK		 3285failed_phy:
3286 of_node_put(phy_node);
ead73183
SH		 3287failed_ioremap:
3288 free_netdev(ndev);
3289
3290 return ret;
3291}
3292
33897cc8 3293static int
ead73183
SH		 3294fec_drv_remove(struct platform_device *pdev)
3295{
3296 struct net_device *ndev = platform_get_drvdata(pdev);
3297 struct fec_enet_private *fep = netdev_priv(ndev);
3298
91c0d987 3299 cancel_delayed_work_sync(&fep->time_keep);
36cdc743 3300 cancel_work_sync(&fep->tx_timeout_work);
e163cc97 3301 unregister_netdev(ndev);
e6b043d5 3302 fec_enet_mii_remove(fep);
f6a4d607
FE		 3303 if (fep->reg_phy)
3304 regulator_disable(fep->reg_phy);
6605b730
FL		 3305 if (fep->ptp_clock)
3306 ptp_clock_unregister(fep->ptp_clock);
e8fcfcd5 3307 fec_enet_clk_enable(ndev, false);
407066f8 3308 of_node_put(fep->phy_node);
ead73183 3309 free_netdev(ndev);
28e2188e 3310
ead73183
SH		 3311 return 0;
3312}
3313
dd66d386 3314static int __maybe_unused fec_suspend(struct device *dev)
ead73183 3315{
87cad5c3 3316 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3317 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 3318
da1774e5 3319 rtnl_lock();
04e5216d 3320 if (netif_running(ndev)) {
d76cfae9 3321 phy_stop(fep->phy_dev);
31a6de34
RK		 3322 napi_disable(&fep->napi);
3323 netif_tx_lock_bh(ndev);
04e5216d 3324 netif_device_detach(ndev);
31a6de34
RK		 3325 netif_tx_unlock_bh(ndev);
3326 fec_stop(ndev);
f4c4a4e0
NA		 3327 fec_enet_clk_enable(ndev, false);
3328 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
ead73183 3329 }
da1774e5
RK		 3330 rtnl_unlock();
3331
238f7bc7
FE		 3332 if (fep->reg_phy)
3333 regulator_disable(fep->reg_phy);
3334
858eeb7d
NA		 3335 /* SOC supply clock to phy, when clock is disabled, phy link down
3336 * SOC control phy regulator, when regulator is disabled, phy link down
3337 */
3338 if (fep->clk_enet_out || fep->reg_phy)
3339 fep->link = 0;
3340
ead73183
SH		 3341 return 0;
3342}
3343
dd66d386 3344static int __maybe_unused fec_resume(struct device *dev)
ead73183 3345{
87cad5c3 3346 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3347 struct fec_enet_private *fep = netdev_priv(ndev);
238f7bc7
FE		 3348 int ret;
3349
3350 if (fep->reg_phy) {
3351 ret = regulator_enable(fep->reg_phy);
3352 if (ret)
3353 return ret;
3354 }
ead73183 3355
da1774e5 3356 rtnl_lock();
04e5216d 3357 if (netif_running(ndev)) {
f4c4a4e0
NA		 3358 pinctrl_pm_select_default_state(&fep->pdev->dev);
3359 ret = fec_enet_clk_enable(ndev, true);
3360 if (ret) {
3361 rtnl_unlock();
3362 goto failed_clk;
3363 }
ef83337d 3364 fec_restart(ndev);
31a6de34 3365 netif_tx_lock_bh(ndev);
6af42d42 3366 netif_device_attach(ndev);
dbc64a8e 3367 netif_tx_unlock_bh(ndev);
6af42d42 3368 napi_enable(&fep->napi);
d76cfae9 3369 phy_start(fep->phy_dev);
ead73183 3370 }
da1774e5 3371 rtnl_unlock();
04e5216d 3372
ead73183 3373 return 0;
13a097bd 3374
e8fcfcd5 3375failed_clk:
13a097bd
FE		 3376 if (fep->reg_phy)
3377 regulator_disable(fep->reg_phy);
3378 return ret;
ead73183
SH		 3379}
3380
bf7bfd7f 3381static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
59d4289b 3382
ead73183
SH		 3383static struct platform_driver fec_driver = {
3384 .driver = {
b5680e0b 3385 .name = DRIVER_NAME,
87cad5c3 3386 .owner = THIS_MODULE,
87cad5c3 3387 .pm = &fec_pm_ops,
ca2cc333 3388 .of_match_table = fec_dt_ids,
ead73183 3389 },
b5680e0b 3390 .id_table = fec_devtype,
87cad5c3 3391 .probe = fec_probe,
33897cc8 3392 .remove = fec_drv_remove,
ead73183
SH		 3393};
3394
aaca2377 3395module_platform_driver(fec_driver);
1da177e4 3396
f8c0aca9 3397MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 3398MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)