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net: fec: add missed clk_disable_unprepare in remove
[linux-2.6-block.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1f508124 1// SPDX-License-Identifier: GPL-2.0+
1da177e4
LT		 2/*
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
7dd6a2aa 6 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
11 * small packets.
12 *
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 *
562d2f8c
GU		 16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 18 *
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 20 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 21 *
230dec61 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/string.h>
8fff755e 28#include <linux/pm_runtime.h>
1da177e4
LT		 29#include <linux/ptrace.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/slab.h>
33#include <linux/interrupt.h>
1da177e4
LT		 34#include <linux/delay.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
4c09eed9
JB		 38#include <linux/in.h>
39#include <linux/ip.h>
40#include <net/ip.h>
79f33912 41#include <net/tso.h>
4c09eed9
JB		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/icmp.h>
1da177e4
LT		 45#include <linux/spinlock.h>
46#include <linux/workqueue.h>
47#include <linux/bitops.h>
6f501b17
SH		 48#include <linux/io.h>
49#include <linux/irq.h>
196719ec 50#include <linux/clk.h>
16f6e983 51#include <linux/crc32.h>
ead73183 52#include <linux/platform_device.h>
7f854420 53#include <linux/mdio.h>
e6b043d5 54#include <linux/phy.h>
5eb32bd0 55#include <linux/fec.h>
ca2cc333
SG		 56#include <linux/of.h>
57#include <linux/of_device.h>
58#include <linux/of_gpio.h>
407066f8 59#include <linux/of_mdio.h>
ca2cc333 60#include <linux/of_net.h>
5fa9c0fe 61#include <linux/regulator/consumer.h>
cdffcf1b 62#include <linux/if_vlan.h>
a68ab98e 63#include <linux/pinctrl/consumer.h>
c259c132 64#include <linux/prefetch.h>
29380905 65#include <soc/imx/cpuidle.h>
1da177e4 66
080853af 67#include <asm/cacheflush.h>
196719ec 68
1da177e4 69#include "fec.h"
1da177e4 70
772e42b0 71static void set_multicast_list(struct net_device *ndev);
d851b47b 72static void fec_enet_itr_coal_init(struct net_device *ndev);
772e42b0 73
b5680e0b
SG		 74#define DRIVER_NAME "fec"
75
4d494cdc
FD		 76#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
77
baa70a5c
FL		 78/* Pause frame feild and FIFO threshold */
79#define FEC_ENET_FCE (1 << 5)
80#define FEC_ENET_RSEM_V 0x84
81#define FEC_ENET_RSFL_V 16
82#define FEC_ENET_RAEM_V 0x8
83#define FEC_ENET_RAFL_V 0x8
84#define FEC_ENET_OPD_V 0xFFF0
8fff755e 85#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
baa70a5c 86
b5680e0b
SG		 87static struct platform_device_id fec_devtype[] = {
88 {
0ca1e290 89 /* keep it for coldfire */
b5680e0b
SG		 90 .name = DRIVER_NAME,
91 .driver_data = 0,
0ca1e290
SG		 92 }, {
93 .name = "imx25-fec",
ec20a63a
FD		 94 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
95 FEC_QUIRK_HAS_FRREG,
0ca1e290
SG		 96 }, {
97 .name = "imx27-fec",
ec20a63a 98 .driver_data = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
b5680e0b
SG		 99 }, {
100 .name = "imx28-fec",
3d125f9c 101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
ec20a63a
FD		 102 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
103 FEC_QUIRK_HAS_FRREG,
230dec61
SG		 104 }, {
105 .name = "imx6q-fec",
ff43da86 106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 107 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
18803495
GU		 108 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
109 FEC_QUIRK_HAS_RACC,
ca7c4a45 110 }, {
36803542 111 .name = "mvf600-fec",
18803495 112 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
95a77470
FD		 113 }, {
114 .name = "imx6sx-fec",
115 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
116 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
f88c7ede 117 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
18803495 118 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
ff7566b8 119 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
a51d3ab5
FD		 120 }, {
121 .name = "imx6ul-fec",
122 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
99492ad4
FD		 124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
125 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
126 FEC_QUIRK_HAS_COALESCE,
0ca1e290
SG		 127 }, {
128 /* sentinel */
129 }
b5680e0b 130};
0ca1e290 131MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 132
ca2cc333 133enum imx_fec_type {
a7dd3219 134 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 135 IMX27_FEC, /* runs on i.mx27/35/51 */
136 IMX28_FEC,
230dec61 137 IMX6Q_FEC,
36803542 138 MVF600_FEC,
ba593e00 139 IMX6SX_FEC,
a51d3ab5 140 IMX6UL_FEC,
ca2cc333
SG		 141};
142
143static const struct of_device_id fec_dt_ids[] = {
144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ba593e00 149 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
a51d3ab5 150 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
ca2cc333
SG		 151 { /* sentinel */ }
152};
153MODULE_DEVICE_TABLE(of, fec_dt_ids);
154
49da97dc
SG		 155static unsigned char macaddr[ETH_ALEN];
156module_param_array(macaddr, byte, NULL, 0);
157MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 158
49da97dc 159#if defined(CONFIG_M5272)
1da177e4
LT		 160/*
161 * Some hardware gets it MAC address out of local flash memory.
162 * if this is non-zero then assume it is the address to get MAC from.
163 */
164#if defined(CONFIG_NETtel)
165#define FEC_FLASHMAC 0xf0006006
166#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
167#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 168#elif defined(CONFIG_CANCam)
169#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 170#elif defined (CONFIG_M5272C3)
171#define FEC_FLASHMAC (0xffe04000 + 4)
172#elif defined(CONFIG_MOD5272)
a7dd3219 173#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 174#else
175#define FEC_FLASHMAC 0
176#endif
43be6366 177#endif /* CONFIG_M5272 */
ead73183 178
cdffcf1b 179/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
fbbeefdd
AL		 180 *
181 * 2048 byte skbufs are allocated. However, alignment requirements
182 * varies between FEC variants. Worst case is 64, so round down by 64.
1da177e4 183 */
fbbeefdd 184#define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
1da177e4 185#define PKT_MINBUF_SIZE 64
1da177e4 186
4c09eed9
JB		 187/* FEC receive acceleration */
188#define FEC_RACC_IPDIS (1 << 1)
189#define FEC_RACC_PRODIS (1 << 2)
3ac72b7b 190#define FEC_RACC_SHIFT16 BIT(7)
4c09eed9
JB		 191#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
192
2b30842b
AL		 193/* MIB Control Register */
194#define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
195
1da177e4 196/*
6b265293 197 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 198 * size bits. Other FEC hardware does not, so we need to take that into
199 * account when setting it.
200 */
562d2f8c 201#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
3f1dcc6a
LS		 202 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
203 defined(CONFIG_ARM64)
1da177e4
LT		 204#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
205#else
206#define OPT_FRAME_SIZE 0
207#endif
208
e6b043d5
BW		 209/* FEC MII MMFR bits definition */
210#define FEC_MMFR_ST (1 << 30)
d3ee8ec7 211#define FEC_MMFR_ST_C45 (0)
e6b043d5 212#define FEC_MMFR_OP_READ (2 << 28)
d3ee8ec7 213#define FEC_MMFR_OP_READ_C45 (3 << 28)
e6b043d5 214#define FEC_MMFR_OP_WRITE (1 << 28)
d3ee8ec7 215#define FEC_MMFR_OP_ADDR_WRITE (0)
e6b043d5
BW		 216#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
217#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
218#define FEC_MMFR_TA (2 << 16)
219#define FEC_MMFR_DATA(v) (v & 0xffff)
de40ed31
NA		 220/* FEC ECR bits definition */
221#define FEC_ECR_MAGICEN (1 << 2)
222#define FEC_ECR_SLEEP (1 << 3)
1da177e4 223
c3b084c2 224#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 225
22f6b860
SH		 226/* Transmitter timeout */
227#define TX_TIMEOUT (2 * HZ)
1da177e4 228
baa70a5c
FL		 229#define FEC_PAUSE_FLAG_AUTONEG 0x1
230#define FEC_PAUSE_FLAG_ENABLE 0x2
de40ed31
NA		 231#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
232#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
233#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
baa70a5c 234
1b7bde6d
NA		 235#define COPYBREAK_DEFAULT 256
236
79f33912
NA		 237/* Max number of allowed TCP segments for software TSO */
238#define FEC_MAX_TSO_SEGS 100
239#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
240
241#define IS_TSO_HEADER(txq, addr) \
242 ((addr >= txq->tso_hdrs_dma) && \
7355f276 243 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
79f33912 244
e163cc97
LW		 245static int mii_cnt;
246
7355f276
TK		 247static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
248 struct bufdesc_prop *bd)
249{
250 return (bdp >= bd->last) ? bd->base
145d6e29 251 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
7355f276 252}
36e24e2e 253
7355f276
TK		 254static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
255 struct bufdesc_prop *bd)
256{
257 return (bdp <= bd->base) ? bd->last
145d6e29 258 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
ff43da86
FL		 259}
260
7355f276
TK		 261static int fec_enet_get_bd_index(struct bufdesc *bdp,
262 struct bufdesc_prop *bd)
61a4427b 263{
7355f276 264 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
61a4427b
NA		 265}
266
7355f276 267static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
6e909283
NA		 268{
269 int entries;
270
7355f276
TK		 271 entries = (((const char *)txq->dirty_tx -
272 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
6e909283 273
7355f276 274 return entries >= 0 ? entries : entries + txq->bd.ring_size;
6e909283
NA		 275}
276
c20e599b 277static void swap_buffer(void *bufaddr, int len)
b5680e0b
SG		 278{
279 int i;
280 unsigned int *buf = bufaddr;
281
7b487d07 282 for (i = 0; i < len; i += 4, buf++)
e453789a 283 swab32s(buf);
b5680e0b
SG		 284}
285
1310b544
LW		 286static void swap_buffer2(void *dst_buf, void *src_buf, int len)
287{
288 int i;
289 unsigned int *src = src_buf;
290 unsigned int *dst = dst_buf;
291
292 for (i = 0; i < len; i += 4, src++, dst++)
293 *dst = swab32p(src);
294}
295
344756f6
RK		 296static void fec_dump(struct net_device *ndev)
297{
298 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 299 struct bufdesc *bdp;
300 struct fec_enet_priv_tx_q *txq;
301 int index = 0;
344756f6
RK		 302
303 netdev_info(ndev, "TX ring dump\n");
304 pr_info("Nr SC addr len SKB\n");
305
4d494cdc 306 txq = fep->tx_queue[0];
7355f276 307 bdp = txq->bd.base;
4d494cdc 308
344756f6 309 do {
5cfa3039 310 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
344756f6 311 index,
7355f276 312 bdp == txq->bd.cur ? 'S' : ' ',
4d494cdc 313 bdp == txq->dirty_tx ? 'H' : ' ',
5cfa3039
JB		 314 fec16_to_cpu(bdp->cbd_sc),
315 fec32_to_cpu(bdp->cbd_bufaddr),
316 fec16_to_cpu(bdp->cbd_datlen),
4d494cdc 317 txq->tx_skbuff[index]);
7355f276 318 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
344756f6 319 index++;
7355f276 320 } while (bdp != txq->bd.base);
344756f6
RK		 321}
322
62a02c98
FD		 323static inline bool is_ipv4_pkt(struct sk_buff *skb)
324{
325 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
326}
327
4c09eed9
JB		 328static int
329fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
330{
331 /* Only run for packets requiring a checksum. */
332 if (skb->ip_summed != CHECKSUM_PARTIAL)
333 return 0;
334
335 if (unlikely(skb_cow_head(skb, 0)))
336 return -1;
337
62a02c98
FD		 338 if (is_ipv4_pkt(skb))
339 ip_hdr(skb)->check = 0;
4c09eed9
JB		 340 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
341
342 return 0;
343}
344
c4bc44c6 345static struct bufdesc *
4d494cdc
FD		 346fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
347 struct sk_buff *skb,
348 struct net_device *ndev)
1da177e4 349{
c556167f 350 struct fec_enet_private *fep = netdev_priv(ndev);
7355f276 351 struct bufdesc *bdp = txq->bd.cur;
6e909283
NA		 352 struct bufdesc_ex *ebdp;
353 int nr_frags = skb_shinfo(skb)->nr_frags;
354 int frag, frag_len;
355 unsigned short status;
356 unsigned int estatus = 0;
357 skb_frag_t *this_frag;
de5fb0a0 358 unsigned int index;
6e909283 359 void *bufaddr;
d6bf3143 360 dma_addr_t addr;
6e909283 361 int i;
1da177e4 362
6e909283
NA		 363 for (frag = 0; frag < nr_frags; frag++) {
364 this_frag = &skb_shinfo(skb)->frags[frag];
7355f276 365 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
6e909283
NA		 366 ebdp = (struct bufdesc_ex *)bdp;
367
5cfa3039 368 status = fec16_to_cpu(bdp->cbd_sc);
6e909283
NA		 369 status &= ~BD_ENET_TX_STATS;
370 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
d7840976 371 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
6e909283
NA		 372
373 /* Handle the last BD specially */
374 if (frag == nr_frags - 1) {
375 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
376 if (fep->bufdesc_ex) {
377 estatus |= BD_ENET_TX_INT;
378 if (unlikely(skb_shinfo(skb)->tx_flags &
379 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
380 estatus |= BD_ENET_TX_TS;
381 }
382 }
383
384 if (fep->bufdesc_ex) {
6b7e4008 385 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 386 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
6e909283
NA		 387 if (skb->ip_summed == CHECKSUM_PARTIAL)
388 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
389 ebdp->cbd_bdu = 0;
5cfa3039 390 ebdp->cbd_esc = cpu_to_fec32(estatus);
6e909283
NA		 391 }
392
d7840976 393 bufaddr = skb_frag_address(this_frag);
6e909283 394
7355f276 395 index = fec_enet_get_bd_index(bdp, &txq->bd);
41ef84ce 396 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 397 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 398 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
399 bufaddr = txq->tx_bounce[index];
6e909283 400
6b7e4008 401 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 402 swap_buffer(bufaddr, frag_len);
403 }
404
d6bf3143
RK		 405 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
406 DMA_TO_DEVICE);
407 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 408 if (net_ratelimit())
409 netdev_err(ndev, "Tx DMA memory map failed\n");
410 goto dma_mapping_error;
411 }
412
5cfa3039
JB		 413 bdp->cbd_bufaddr = cpu_to_fec32(addr);
414 bdp->cbd_datlen = cpu_to_fec16(frag_len);
be293467
TK		 415 /* Make sure the updates to rest of the descriptor are
416 * performed before transferring ownership.
417 */
418 wmb();
5cfa3039 419 bdp->cbd_sc = cpu_to_fec16(status);
6e909283
NA		 420 }
421
c4bc44c6 422 return bdp;
6e909283 423dma_mapping_error:
7355f276 424 bdp = txq->bd.cur;
6e909283 425 for (i = 0; i < frag; i++) {
7355f276 426 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
5cfa3039
JB		 427 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
428 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
6e909283 429 }
c4bc44c6 430 return ERR_PTR(-ENOMEM);
6e909283 431}
1da177e4 432
4d494cdc
FD		 433static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
434 struct sk_buff *skb, struct net_device *ndev)
6e909283
NA		 435{
436 struct fec_enet_private *fep = netdev_priv(ndev);
6e909283
NA		 437 int nr_frags = skb_shinfo(skb)->nr_frags;
438 struct bufdesc *bdp, *last_bdp;
439 void *bufaddr;
d6bf3143 440 dma_addr_t addr;
6e909283
NA		 441 unsigned short status;
442 unsigned short buflen;
443 unsigned int estatus = 0;
444 unsigned int index;
79f33912 445 int entries_free;
22f6b860 446
7355f276 447 entries_free = fec_enet_get_free_txdesc_num(txq);
79f33912
NA		 448 if (entries_free < MAX_SKB_FRAGS + 1) {
449 dev_kfree_skb_any(skb);
450 if (net_ratelimit())
451 netdev_err(ndev, "NOT enough BD for SG!\n");
452 return NETDEV_TX_OK;
453 }
454
4c09eed9
JB		 455 /* Protocol checksum off-load for TCP and UDP. */
456 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 457 dev_kfree_skb_any(skb);
4c09eed9
JB		 458 return NETDEV_TX_OK;
459 }
460
6e909283 461 /* Fill in a Tx ring entry */
7355f276 462 bdp = txq->bd.cur;
c4bc44c6 463 last_bdp = bdp;
5cfa3039 464 status = fec16_to_cpu(bdp->cbd_sc);
0e702ab3 465 status &= ~BD_ENET_TX_STATS;
1da177e4 466
22f6b860 467 /* Set buffer length and buffer pointer */
9555b31e 468 bufaddr = skb->data;
6e909283 469 buflen = skb_headlen(skb);
1da177e4 470
7355f276 471 index = fec_enet_get_bd_index(bdp, &txq->bd);
41ef84ce 472 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 473 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 474 memcpy(txq->tx_bounce[index], skb->data, buflen);
475 bufaddr = txq->tx_bounce[index];
1da177e4 476
6b7e4008 477 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 478 swap_buffer(bufaddr, buflen);
479 }
6aa20a22 480
d6bf3143
RK		 481 /* Push the data cache so the CPM does not get stale memory data. */
482 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
483 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 484 dev_kfree_skb_any(skb);
485 if (net_ratelimit())
486 netdev_err(ndev, "Tx DMA memory map failed\n");
487 return NETDEV_TX_OK;
488 }
1da177e4 489
6e909283 490 if (nr_frags) {
c4bc44c6 491 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
fc75ba51
TK		 492 if (IS_ERR(last_bdp)) {
493 dma_unmap_single(&fep->pdev->dev, addr,
494 buflen, DMA_TO_DEVICE);
495 dev_kfree_skb_any(skb);
c4bc44c6 496 return NETDEV_TX_OK;
fc75ba51 497 }
6e909283
NA		 498 } else {
499 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
500 if (fep->bufdesc_ex) {
501 estatus = BD_ENET_TX_INT;
502 if (unlikely(skb_shinfo(skb)->tx_flags &
503 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
504 estatus |= BD_ENET_TX_TS;
505 }
506 }
fc75ba51
TK		 507 bdp->cbd_bufaddr = cpu_to_fec32(addr);
508 bdp->cbd_datlen = cpu_to_fec16(buflen);
6e909283 509
ff43da86
FL		 510 if (fep->bufdesc_ex) {
511
512 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 513
ff43da86 514 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 515 fep->hwts_tx_en))
6605b730 516 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 517
6b7e4008 518 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 519 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
befe8213 520
6e909283
NA		 521 if (skb->ip_summed == CHECKSUM_PARTIAL)
522 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
523
524 ebdp->cbd_bdu = 0;
5cfa3039 525 ebdp->cbd_esc = cpu_to_fec32(estatus);
6605b730 526 }
03191656 527
7355f276 528 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
6e909283 529 /* Save skb pointer */
4d494cdc 530 txq->tx_skbuff[index] = skb;
6e909283 531
be293467
TK		 532 /* Make sure the updates to rest of the descriptor are performed before
533 * transferring ownership.
534 */
535 wmb();
6e909283 536
fb8ef788
DFB		 537 /* Send it on its way. Tell FEC it's ready, interrupt when done,
538 * it's the last BD of the frame, and to put the CRC on the end.
539 */
6e909283 540 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
5cfa3039 541 bdp->cbd_sc = cpu_to_fec16(status);
fb8ef788 542
22f6b860 543 /* If this was the last BD in the ring, start at the beginning again. */
7355f276 544 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
1da177e4 545
7a2a8451
ED		 546 skb_tx_timestamp(skb);
547
c4bc44c6 548 /* Make sure the update to bdp and tx_skbuff are performed before
7355f276 549 * txq->bd.cur.
c4bc44c6
KH		 550 */
551 wmb();
7355f276 552 txq->bd.cur = bdp;
de5fb0a0 553
de5fb0a0 554 /* Trigger transmission start */
53bb20d1 555 writel(0, txq->bd.reg_desc_active);
1da177e4 556
6e909283 557 return 0;
1da177e4
LT		 558}
559
79f33912 560static int
4d494cdc
FD		 561fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
562 struct net_device *ndev,
563 struct bufdesc *bdp, int index, char *data,
564 int size, bool last_tcp, bool is_last)
61a4427b
NA		 565{
566 struct fec_enet_private *fep = netdev_priv(ndev);
61cd2ebb 567 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
79f33912
NA		 568 unsigned short status;
569 unsigned int estatus = 0;
d6bf3143 570 dma_addr_t addr;
61a4427b 571
5cfa3039 572 status = fec16_to_cpu(bdp->cbd_sc);
79f33912 573 status &= ~BD_ENET_TX_STATS;
61a4427b 574
79f33912 575 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912 576
41ef84ce 577 if (((unsigned long) data) & fep->tx_align ||
6b7e4008 578 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 579 memcpy(txq->tx_bounce[index], data, size);
580 data = txq->tx_bounce[index];
79f33912 581
6b7e4008 582 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 583 swap_buffer(data, size);
584 }
585
d6bf3143
RK		 586 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
587 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 588 dev_kfree_skb_any(skb);
6e909283 589 if (net_ratelimit())
79f33912 590 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 591 return NETDEV_TX_BUSY;
592 }
593
5cfa3039
JB		 594 bdp->cbd_datlen = cpu_to_fec16(size);
595 bdp->cbd_bufaddr = cpu_to_fec32(addr);
d6bf3143 596
79f33912 597 if (fep->bufdesc_ex) {
6b7e4008 598 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 599 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
79f33912
NA		 600 if (skb->ip_summed == CHECKSUM_PARTIAL)
601 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
602 ebdp->cbd_bdu = 0;
5cfa3039 603 ebdp->cbd_esc = cpu_to_fec32(estatus);
79f33912
NA		 604 }
605
606 /* Handle the last BD specially */
607 if (last_tcp)
608 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
609 if (is_last) {
610 status |= BD_ENET_TX_INTR;
611 if (fep->bufdesc_ex)
5cfa3039 612 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
79f33912
NA		 613 }
614
5cfa3039 615 bdp->cbd_sc = cpu_to_fec16(status);
79f33912
NA		 616
617 return 0;
618}
619
620static int
4d494cdc
FD		 621fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
622 struct sk_buff *skb, struct net_device *ndev,
623 struct bufdesc *bdp, int index)
79f33912
NA		 624{
625 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912 626 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
61cd2ebb 627 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
79f33912
NA		 628 void *bufaddr;
629 unsigned long dmabuf;
630 unsigned short status;
631 unsigned int estatus = 0;
632
5cfa3039 633 status = fec16_to_cpu(bdp->cbd_sc);
79f33912
NA		 634 status &= ~BD_ENET_TX_STATS;
635 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
636
4d494cdc
FD		 637 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
638 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
41ef84ce 639 if (((unsigned long)bufaddr) & fep->tx_align ||
6b7e4008 640 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 641 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
642 bufaddr = txq->tx_bounce[index];
79f33912 643
6b7e4008 644 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 645 swap_buffer(bufaddr, hdr_len);
646
647 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
648 hdr_len, DMA_TO_DEVICE);
649 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
650 dev_kfree_skb_any(skb);
651 if (net_ratelimit())
652 netdev_err(ndev, "Tx DMA memory map failed\n");
653 return NETDEV_TX_BUSY;
654 }
655 }
656
5cfa3039
JB		 657 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
658 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
79f33912
NA		 659
660 if (fep->bufdesc_ex) {
6b7e4008 661 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 662 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
79f33912
NA		 663 if (skb->ip_summed == CHECKSUM_PARTIAL)
664 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
665 ebdp->cbd_bdu = 0;
5cfa3039 666 ebdp->cbd_esc = cpu_to_fec32(estatus);
79f33912
NA		 667 }
668
5cfa3039 669 bdp->cbd_sc = cpu_to_fec16(status);
79f33912
NA		 670
671 return 0;
672}
673
4d494cdc
FD		 674static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
675 struct sk_buff *skb,
676 struct net_device *ndev)
79f33912
NA		 677{
678 struct fec_enet_private *fep = netdev_priv(ndev);
679 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
680 int total_len, data_left;
7355f276 681 struct bufdesc *bdp = txq->bd.cur;
79f33912
NA		 682 struct tso_t tso;
683 unsigned int index = 0;
684 int ret;
685
7355f276 686 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
79f33912
NA		 687 dev_kfree_skb_any(skb);
688 if (net_ratelimit())
689 netdev_err(ndev, "NOT enough BD for TSO!\n");
690 return NETDEV_TX_OK;
691 }
692
693 /* Protocol checksum off-load for TCP and UDP. */
694 if (fec_enet_clear_csum(skb, ndev)) {
695 dev_kfree_skb_any(skb);
696 return NETDEV_TX_OK;
697 }
698
699 /* Initialize the TSO handler, and prepare the first payload */
700 tso_start(skb, &tso);
701
702 total_len = skb->len - hdr_len;
703 while (total_len > 0) {
704 char *hdr;
705
7355f276 706 index = fec_enet_get_bd_index(bdp, &txq->bd);
79f33912
NA		 707 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
708 total_len -= data_left;
709
710 /* prepare packet headers: MAC + IP + TCP */
4d494cdc 711 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
79f33912 712 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
4d494cdc 713 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
79f33912
NA		 714 if (ret)
715 goto err_release;
716
717 while (data_left > 0) {
718 int size;
719
720 size = min_t(int, tso.size, data_left);
7355f276
TK		 721 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
722 index = fec_enet_get_bd_index(bdp, &txq->bd);
4d494cdc
FD		 723 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
724 bdp, index,
725 tso.data, size,
726 size == data_left,
79f33912
NA		 727 total_len == 0);
728 if (ret)
729 goto err_release;
730
731 data_left -= size;
732 tso_build_data(skb, &tso, size);
733 }
734
7355f276 735 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
79f33912
NA		 736 }
737
738 /* Save skb pointer */
4d494cdc 739 txq->tx_skbuff[index] = skb;
79f33912 740
79f33912 741 skb_tx_timestamp(skb);
7355f276 742 txq->bd.cur = bdp;
79f33912
NA		 743
744 /* Trigger transmission start */
6b7e4008 745 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
53bb20d1
TK		 746 !readl(txq->bd.reg_desc_active) ||
747 !readl(txq->bd.reg_desc_active) ||
748 !readl(txq->bd.reg_desc_active) ||
749 !readl(txq->bd.reg_desc_active))
750 writel(0, txq->bd.reg_desc_active);
79f33912
NA		 751
752 return 0;
753
754err_release:
755 /* TODO: Release all used data descriptors for TSO */
756 return ret;
757}
758
759static netdev_tx_t
760fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
761{
762 struct fec_enet_private *fep = netdev_priv(ndev);
763 int entries_free;
4d494cdc
FD		 764 unsigned short queue;
765 struct fec_enet_priv_tx_q *txq;
766 struct netdev_queue *nq;
79f33912
NA		 767 int ret;
768
4d494cdc
FD		 769 queue = skb_get_queue_mapping(skb);
770 txq = fep->tx_queue[queue];
771 nq = netdev_get_tx_queue(ndev, queue);
772
79f33912 773 if (skb_is_gso(skb))
4d494cdc 774 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
79f33912 775 else
4d494cdc 776 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
6e909283
NA		 777 if (ret)
778 return ret;
61a4427b 779
7355f276 780 entries_free = fec_enet_get_free_txdesc_num(txq);
4d494cdc
FD		 781 if (entries_free <= txq->tx_stop_threshold)
782 netif_tx_stop_queue(nq);
61a4427b
NA		 783
784 return NETDEV_TX_OK;
785}
786
14109a59
FL		 787/* Init RX & TX buffer descriptors
788 */
789static void fec_enet_bd_init(struct net_device *dev)
790{
791 struct fec_enet_private *fep = netdev_priv(dev);
4d494cdc
FD		 792 struct fec_enet_priv_tx_q *txq;
793 struct fec_enet_priv_rx_q *rxq;
14109a59
FL		 794 struct bufdesc *bdp;
795 unsigned int i;
59d0f746 796 unsigned int q;
14109a59 797
59d0f746
FL		 798 for (q = 0; q < fep->num_rx_queues; q++) {
799 /* Initialize the receive buffer descriptors. */
800 rxq = fep->rx_queue[q];
7355f276 801 bdp = rxq->bd.base;
4d494cdc 802
7355f276 803 for (i = 0; i < rxq->bd.ring_size; i++) {
14109a59 804
59d0f746
FL		 805 /* Initialize the BD for every fragment in the page. */
806 if (bdp->cbd_bufaddr)
5cfa3039 807 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
59d0f746 808 else
5cfa3039 809 bdp->cbd_sc = cpu_to_fec16(0);
7355f276 810 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
59d0f746
FL		 811 }
812
813 /* Set the last buffer to wrap */
7355f276 814 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
5cfa3039 815 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 816
7355f276 817 rxq->bd.cur = rxq->bd.base;
59d0f746
FL		 818 }
819
820 for (q = 0; q < fep->num_tx_queues; q++) {
821 /* ...and the same for transmit */
822 txq = fep->tx_queue[q];
7355f276
TK		 823 bdp = txq->bd.base;
824 txq->bd.cur = bdp;
59d0f746 825
7355f276 826 for (i = 0; i < txq->bd.ring_size; i++) {
59d0f746 827 /* Initialize the BD for every fragment in the page. */
5cfa3039 828 bdp->cbd_sc = cpu_to_fec16(0);
178e5f57
FD		 829 if (bdp->cbd_bufaddr &&
830 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
831 dma_unmap_single(&fep->pdev->dev,
832 fec32_to_cpu(bdp->cbd_bufaddr),
833 fec16_to_cpu(bdp->cbd_datlen),
834 DMA_TO_DEVICE);
59d0f746
FL		 835 if (txq->tx_skbuff[i]) {
836 dev_kfree_skb_any(txq->tx_skbuff[i]);
837 txq->tx_skbuff[i] = NULL;
838 }
5cfa3039 839 bdp->cbd_bufaddr = cpu_to_fec32(0);
7355f276 840 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
59d0f746
FL		 841 }
842
843 /* Set the last buffer to wrap */
7355f276 844 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
5cfa3039 845 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 846 txq->dirty_tx = bdp;
14109a59 847 }
59d0f746 848}
14109a59 849
ce99d0d3
FL		 850static void fec_enet_active_rxring(struct net_device *ndev)
851{
852 struct fec_enet_private *fep = netdev_priv(ndev);
853 int i;
854
855 for (i = 0; i < fep->num_rx_queues; i++)
53bb20d1 856 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
ce99d0d3
FL		 857}
858
59d0f746
FL		 859static void fec_enet_enable_ring(struct net_device *ndev)
860{
861 struct fec_enet_private *fep = netdev_priv(ndev);
862 struct fec_enet_priv_tx_q *txq;
863 struct fec_enet_priv_rx_q *rxq;
864 int i;
14109a59 865
59d0f746
FL		 866 for (i = 0; i < fep->num_rx_queues; i++) {
867 rxq = fep->rx_queue[i];
7355f276 868 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
fbbeefdd 869 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
14109a59 870
59d0f746
FL		 871 /* enable DMA1/2 */
872 if (i)
873 writel(RCMR_MATCHEN | RCMR_CMP(i),
874 fep->hwp + FEC_RCMR(i));
875 }
14109a59 876
59d0f746
FL		 877 for (i = 0; i < fep->num_tx_queues; i++) {
878 txq = fep->tx_queue[i];
7355f276 879 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
59d0f746
FL		 880
881 /* enable DMA1/2 */
882 if (i)
883 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
884 fep->hwp + FEC_DMA_CFG(i));
14109a59 885 }
59d0f746 886}
14109a59 887
59d0f746
FL		 888static void fec_enet_reset_skb(struct net_device *ndev)
889{
890 struct fec_enet_private *fep = netdev_priv(ndev);
891 struct fec_enet_priv_tx_q *txq;
892 int i, j;
893
894 for (i = 0; i < fep->num_tx_queues; i++) {
895 txq = fep->tx_queue[i];
896
7355f276 897 for (j = 0; j < txq->bd.ring_size; j++) {
59d0f746
FL		 898 if (txq->tx_skbuff[j]) {
899 dev_kfree_skb_any(txq->tx_skbuff[j]);
900 txq->tx_skbuff[j] = NULL;
901 }
902 }
903 }
14109a59
FL		 904}
905
dbc64a8e
RK		 906/*
907 * This function is called to start or restart the FEC during a link
908 * change, transmit timeout, or to reconfigure the FEC. The network
909 * packet processing for this device must be stopped before this call.
45993653 910 */
1da177e4 911static void
ef83337d 912fec_restart(struct net_device *ndev)
1da177e4 913{
c556167f 914 struct fec_enet_private *fep = netdev_priv(ndev);
4c09eed9 915 u32 val;
cd1f402c
UKK		 916 u32 temp_mac[2];
917 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 918 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 919
106c314c
FD		 920 /* Whack a reset. We should wait for this.
921 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
922 * instead of reset MAC itself.
923 */
6b7e4008 924 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
106c314c
FD		 925 writel(0, fep->hwp + FEC_ECNTRL);
926 } else {
927 writel(1, fep->hwp + FEC_ECNTRL);
928 udelay(10);
929 }
1da177e4 930
45993653
UKK		 931 /*
932 * enet-mac reset will reset mac address registers too,
933 * so need to reconfigure it.
934 */
b82d44d7
GS		 935 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
936 writel((__force u32)cpu_to_be32(temp_mac[0]),
937 fep->hwp + FEC_ADDR_LOW);
938 writel((__force u32)cpu_to_be32(temp_mac[1]),
939 fep->hwp + FEC_ADDR_HIGH);
1da177e4 940
45993653 941 /* Clear any outstanding interrupt. */
e17f7fec 942 writel(0xffffffff, fep->hwp + FEC_IEVENT);
1da177e4 943
14109a59
FL		 944 fec_enet_bd_init(ndev);
945
59d0f746 946 fec_enet_enable_ring(ndev);
45993653 947
59d0f746
FL		 948 /* Reset tx SKB buffers. */
949 fec_enet_reset_skb(ndev);
97b72e43 950
45993653 951 /* Enable MII mode */
ef83337d 952 if (fep->full_duplex == DUPLEX_FULL) {
cd1f402c 953 /* FD enable */
45993653
UKK		 954 writel(0x04, fep->hwp + FEC_X_CNTRL);
955 } else {
cd1f402c
UKK		 956 /* No Rcv on Xmit */
957 rcntl |= 0x02;
45993653
UKK		 958 writel(0x0, fep->hwp + FEC_X_CNTRL);
959 }
cd1f402c 960
45993653
UKK		 961 /* Set MII speed */
962 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
963
d1391930 964#if !defined(CONFIG_M5272)
18803495 965 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
18803495 966 val = readl(fep->hwp + FEC_RACC);
3ac72b7b
EN		 967 /* align IP header */
968 val |= FEC_RACC_SHIFT16;
18803495 969 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
3ac72b7b 970 /* set RX checksum */
18803495
GU		 971 val |= FEC_RACC_OPTIONS;
972 else
973 val &= ~FEC_RACC_OPTIONS;
974 writel(val, fep->hwp + FEC_RACC);
32867fcc 975 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
18803495 976 }
d1391930 977#endif
4c09eed9 978
45993653
UKK		 979 /*
980 * The phy interface and speed need to get configured
981 * differently on enet-mac.
982 */
6b7e4008 983 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 984 /* Enable flow control and length check */
985 rcntl |= 0x40000000 | 0x00000020;
45993653 986
230dec61 987 /* RGMII, RMII or MII */
e813bb2b
MP		 988 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
989 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
990 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
991 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
230dec61
SG		 992 rcntl |= (1 << 6);
993 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 994 rcntl |= (1 << 8);
45993653 995 else
cd1f402c 996 rcntl &= ~(1 << 8);
45993653 997
230dec61 998 /* 1G, 100M or 10M */
45f5c327
PR		 999 if (ndev->phydev) {
1000 if (ndev->phydev->speed == SPEED_1000)
230dec61 1001 ecntl |= (1 << 5);
45f5c327 1002 else if (ndev->phydev->speed == SPEED_100)
230dec61
SG		 1003 rcntl &= ~(1 << 9);
1004 else
1005 rcntl |= (1 << 9);
1006 }
45993653
UKK		 1007 } else {
1008#ifdef FEC_MIIGSK_ENR
6b7e4008 1009 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
8d82f219 1010 u32 cfgr;
45993653
UKK		 1011 /* disable the gasket and wait */
1012 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1013 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1014 udelay(1);
1015
1016 /*
1017 * configure the gasket:
1018 * RMII, 50 MHz, no loopback, no echo
0ca1e290 1019 * MII, 25 MHz, no loopback, no echo
45993653 1020 */
8d82f219
EB		 1021 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1022 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
45f5c327 1023 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
8d82f219
EB		 1024 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1025 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 1026
1027 /* re-enable the gasket */
1028 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 1029 }
45993653
UKK		 1030#endif
1031 }
baa70a5c 1032
d1391930 1033#if !defined(CONFIG_M5272)
baa70a5c
FL		 1034 /* enable pause frame*/
1035 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1036 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
45f5c327 1037 ndev->phydev && ndev->phydev->pause)) {
baa70a5c
FL		 1038 rcntl |= FEC_ENET_FCE;
1039
4c09eed9 1040 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 1041 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1042 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1043 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1044 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1045
1046 /* OPD */
1047 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1048 } else {
1049 rcntl &= ~FEC_ENET_FCE;
1050 }
d1391930 1051#endif /* !defined(CONFIG_M5272) */
baa70a5c 1052
cd1f402c 1053 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 1054
84fe6182
SW		 1055 /* Setup multicast filter. */
1056 set_multicast_list(ndev);
1057#ifndef CONFIG_M5272
1058 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1059 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1060#endif
1061
6b7e4008 1062 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
230dec61
SG		 1063 /* enable ENET endian swap */
1064 ecntl |= (1 << 8);
1065 /* enable ENET store and forward mode */
1066 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1067 }
1068
ff43da86
FL		 1069 if (fep->bufdesc_ex)
1070 ecntl |= (1 << 4);
6605b730 1071
38ae92dc 1072#ifndef CONFIG_M5272
b9eef55c
JB		 1073 /* Enable the MIB statistic event counters */
1074 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 1075#endif
1076
45993653 1077 /* And last, enable the transmit and receive processing */
230dec61 1078 writel(ecntl, fep->hwp + FEC_ECNTRL);
ce99d0d3 1079 fec_enet_active_rxring(ndev);
45993653 1080
ff43da86
FL		 1081 if (fep->bufdesc_ex)
1082 fec_ptp_start_cyclecounter(ndev);
1083
45993653 1084 /* Enable interrupts we wish to service */
0c5a3aef
NA		 1085 if (fep->link)
1086 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1087 else
1088 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
d851b47b
FD		 1089
1090 /* Init the interrupt coalescing */
1091 fec_enet_itr_coal_init(ndev);
1092
45993653
UKK		 1093}
1094
1095static void
1096fec_stop(struct net_device *ndev)
1097{
1098 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 1099 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
42431dc2 1100 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
de40ed31 1101 u32 val;
45993653
UKK		 1102
1103 /* We cannot expect a graceful transmit stop without link !!! */
1104 if (fep->link) {
1105 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1106 udelay(10);
1107 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 1108 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1109 }
1110
106c314c
FD		 1111 /* Whack a reset. We should wait for this.
1112 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1113 * instead of reset MAC itself.
1114 */
de40ed31
NA		 1115 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1116 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1117 writel(0, fep->hwp + FEC_ECNTRL);
1118 } else {
1119 writel(1, fep->hwp + FEC_ECNTRL);
1120 udelay(10);
1121 }
1122 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
106c314c 1123 } else {
de40ed31
NA		 1124 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1125 val = readl(fep->hwp + FEC_ECNTRL);
1126 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1127 writel(val, fep->hwp + FEC_ECNTRL);
1128
1129 if (pdata && pdata->sleep_mode_enable)
1130 pdata->sleep_mode_enable(true);
106c314c 1131 }
45993653 1132 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
230dec61
SG		 1133
1134 /* We have to keep ENET enabled to have MII interrupt stay working */
de40ed31
NA		 1135 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1136 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
230dec61 1137 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1138 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1139 }
1da177e4
LT		 1140}
1141
1142
45993653
UKK		 1143static void
1144fec_timeout(struct net_device *ndev)
1145{
1146 struct fec_enet_private *fep = netdev_priv(ndev);
1147
344756f6
RK		 1148 fec_dump(ndev);
1149
45993653
UKK		 1150 ndev->stats.tx_errors++;
1151
36cdc743 1152 schedule_work(&fep->tx_timeout_work);
54309fa6
FL		 1153}
1154
36cdc743 1155static void fec_enet_timeout_work(struct work_struct *work)
54309fa6
FL		 1156{
1157 struct fec_enet_private *fep =
36cdc743 1158 container_of(work, struct fec_enet_private, tx_timeout_work);
8ce5624f 1159 struct net_device *ndev = fep->netdev;
54309fa6 1160
36cdc743
RK		 1161 rtnl_lock();
1162 if (netif_device_present(ndev) || netif_running(ndev)) {
1163 napi_disable(&fep->napi);
1164 netif_tx_lock_bh(ndev);
1165 fec_restart(ndev);
657ade07 1166 netif_tx_wake_all_queues(ndev);
36cdc743
RK		 1167 netif_tx_unlock_bh(ndev);
1168 napi_enable(&fep->napi);
54309fa6 1169 }
36cdc743 1170 rtnl_unlock();
45993653
UKK		 1171}
1172
bfd4ecdd
RK		 1173static void
1174fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1175 struct skb_shared_hwtstamps *hwtstamps)
1176{
1177 unsigned long flags;
1178 u64 ns;
1179
1180 spin_lock_irqsave(&fep->tmreg_lock, flags);
1181 ns = timecounter_cyc2time(&fep->tc, ts);
1182 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1183
1184 memset(hwtstamps, 0, sizeof(*hwtstamps));
1185 hwtstamps->hwtstamp = ns_to_ktime(ns);
1186}
1187
1da177e4 1188static void
4d494cdc 1189fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1da177e4
LT		 1190{
1191 struct fec_enet_private *fep;
a2fe37b6 1192 struct bufdesc *bdp;
0e702ab3 1193 unsigned short status;
1da177e4 1194 struct sk_buff *skb;
4d494cdc
FD		 1195 struct fec_enet_priv_tx_q *txq;
1196 struct netdev_queue *nq;
de5fb0a0 1197 int index = 0;
79f33912 1198 int entries_free;
1da177e4 1199
c556167f 1200 fep = netdev_priv(ndev);
4d494cdc
FD		 1201
1202 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1203
1204 txq = fep->tx_queue[queue_id];
1205 /* get next bdp of dirty_tx */
1206 nq = netdev_get_tx_queue(ndev, queue_id);
1207 bdp = txq->dirty_tx;
1da177e4 1208
de5fb0a0 1209 /* get next bdp of dirty_tx */
7355f276 1210 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
de5fb0a0 1211
7355f276
TK		 1212 while (bdp != READ_ONCE(txq->bd.cur)) {
1213 /* Order the load of bd.cur and cbd_sc */
c4bc44c6 1214 rmb();
5cfa3039 1215 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
c4bc44c6 1216 if (status & BD_ENET_TX_READY)
f0b3fbea
SH		 1217 break;
1218
7355f276 1219 index = fec_enet_get_bd_index(bdp, &txq->bd);
2b995f63 1220
a2fe37b6 1221 skb = txq->tx_skbuff[index];
2b995f63 1222 txq->tx_skbuff[index] = NULL;
5cfa3039
JB		 1223 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1224 dma_unmap_single(&fep->pdev->dev,
1225 fec32_to_cpu(bdp->cbd_bufaddr),
1226 fec16_to_cpu(bdp->cbd_datlen),
1227 DMA_TO_DEVICE);
1228 bdp->cbd_bufaddr = cpu_to_fec32(0);
7fafe803
TK		 1229 if (!skb)
1230 goto skb_done;
de5fb0a0 1231
1da177e4 1232 /* Check for errors. */
0e702ab3 1233 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1234 BD_ENET_TX_RL | BD_ENET_TX_UN |
1235 BD_ENET_TX_CSL)) {
c556167f 1236 ndev->stats.tx_errors++;
0e702ab3 1237 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1238 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1239 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1240 ndev->stats.tx_window_errors++;
0e702ab3 1241 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1242 ndev->stats.tx_aborted_errors++;
0e702ab3 1243 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1244 ndev->stats.tx_fifo_errors++;
0e702ab3 1245 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1246 ndev->stats.tx_carrier_errors++;
1da177e4 1247 } else {
c556167f 1248 ndev->stats.tx_packets++;
6e909283 1249 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1250 }
1251
ff43da86
FL		 1252 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1253 fep->bufdesc_ex) {
6605b730 1254 struct skb_shared_hwtstamps shhwtstamps;
ff43da86 1255 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730 1256
5cfa3039 1257 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
6605b730
FL		 1258 skb_tstamp_tx(skb, &shhwtstamps);
1259 }
ff43da86 1260
1da177e4
LT		 1261 /* Deferred means some collisions occurred during transmit,
1262 * but we eventually sent the packet OK.
1263 */
0e702ab3 1264 if (status & BD_ENET_TX_DEF)
c556167f 1265 ndev->stats.collisions++;
6aa20a22 1266
22f6b860 1267 /* Free the sk buffer associated with this last transmit */
1da177e4 1268 dev_kfree_skb_any(skb);
7fafe803 1269skb_done:
c4bc44c6
KH		 1270 /* Make sure the update to bdp and tx_skbuff are performed
1271 * before dirty_tx
1272 */
1273 wmb();
4d494cdc 1274 txq->dirty_tx = bdp;
6aa20a22 1275
22f6b860 1276 /* Update pointer to next buffer descriptor to be transmitted */
7355f276 1277 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
6aa20a22 1278
22f6b860 1279 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1280 */
657ade07 1281 if (netif_tx_queue_stopped(nq)) {
7355f276 1282 entries_free = fec_enet_get_free_txdesc_num(txq);
4d494cdc
FD		 1283 if (entries_free >= txq->tx_wake_threshold)
1284 netif_tx_wake_queue(nq);
79f33912 1285 }
1da177e4 1286 }
ccea2968 1287
c10bc0e7 1288 /* ERR006358: Keep the transmitter going */
7355f276 1289 if (bdp != txq->bd.cur &&
53bb20d1
TK		 1290 readl(txq->bd.reg_desc_active) == 0)
1291 writel(0, txq->bd.reg_desc_active);
4d494cdc
FD		 1292}
1293
1294static void
1295fec_enet_tx(struct net_device *ndev)
1296{
1297 struct fec_enet_private *fep = netdev_priv(ndev);
1298 u16 queue_id;
1299 /* First process class A queue, then Class B and Best Effort queue */
1300 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1301 clear_bit(queue_id, &fep->work_tx);
1302 fec_enet_tx_queue(ndev, queue_id);
1303 }
1304 return;
1da177e4
LT		 1305}
1306
1b7bde6d
NA		 1307static int
1308fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1309{
1310 struct fec_enet_private *fep = netdev_priv(ndev);
1311 int off;
1312
1313 off = ((unsigned long)skb->data) & fep->rx_align;
1314 if (off)
1315 skb_reserve(skb, fep->rx_align + 1 - off);
1316
5cfa3039
JB		 1317 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1318 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1b7bde6d
NA		 1319 if (net_ratelimit())
1320 netdev_err(ndev, "Rx DMA memory map failed\n");
1321 return -ENOMEM;
1322 }
1323
1324 return 0;
1325}
1326
1327static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1310b544 1328 struct bufdesc *bdp, u32 length, bool swap)
1b7bde6d
NA		 1329{
1330 struct fec_enet_private *fep = netdev_priv(ndev);
1331 struct sk_buff *new_skb;
1332
1333 if (length > fep->rx_copybreak)
1334 return false;
1335
1336 new_skb = netdev_alloc_skb(ndev, length);
1337 if (!new_skb)
1338 return false;
1339
5cfa3039
JB		 1340 dma_sync_single_for_cpu(&fep->pdev->dev,
1341 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1342 FEC_ENET_RX_FRSIZE - fep->rx_align,
1343 DMA_FROM_DEVICE);
1310b544
LW		 1344 if (!swap)
1345 memcpy(new_skb->data, (*skb)->data, length);
1346 else
1347 swap_buffer2(new_skb->data, (*skb)->data, length);
1b7bde6d
NA		 1348 *skb = new_skb;
1349
1350 return true;
1351}
1352
7355f276 1353/* During a receive, the bd_rx.cur points to the current incoming buffer.
1da177e4
LT		 1354 * When we update through the ring, if the next incoming buffer has
1355 * not been given to the system, we just set the empty indicator,
1356 * effectively tossing the packet.
1357 */
dc975382 1358static int
4d494cdc 1359fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1da177e4 1360{
c556167f 1361 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 1362 struct fec_enet_priv_rx_q *rxq;
2e28532f 1363 struct bufdesc *bdp;
0e702ab3 1364 unsigned short status;
1b7bde6d
NA		 1365 struct sk_buff *skb_new = NULL;
1366 struct sk_buff *skb;
1da177e4
LT		 1367 ushort pkt_len;
1368 __u8 *data;
dc975382 1369 int pkt_received = 0;
cdffcf1b
JB		 1370 struct bufdesc_ex *ebdp = NULL;
1371 bool vlan_packet_rcvd = false;
1372 u16 vlan_tag;
d842a31f 1373 int index = 0;
1b7bde6d 1374 bool is_copybreak;
6b7e4008 1375 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
6aa20a22 1376
0e702ab3
GU		 1377#ifdef CONFIG_M532x
1378 flush_cache_all();
6aa20a22 1379#endif
4d494cdc
FD		 1380 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1381 rxq = fep->rx_queue[queue_id];
1da177e4 1382
1da177e4
LT		 1383 /* First, grab all of the stats for the incoming packet.
1384 * These get messed up if we get called due to a busy condition.
1385 */
7355f276 1386 bdp = rxq->bd.cur;
1da177e4 1387
5cfa3039 1388 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1da177e4 1389
dc975382
FL		 1390 if (pkt_received >= budget)
1391 break;
1392 pkt_received++;
1393
ed63f1dc 1394 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
db3421c1 1395
22f6b860 1396 /* Check for errors. */
095098e1 1397 status ^= BD_ENET_RX_LAST;
22f6b860 1398 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
095098e1
TK		 1399 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1400 BD_ENET_RX_CL)) {
c556167f 1401 ndev->stats.rx_errors++;
095098e1
TK		 1402 if (status & BD_ENET_RX_OV) {
1403 /* FIFO overrun */
1404 ndev->stats.rx_fifo_errors++;
1405 goto rx_processing_done;
1406 }
1407 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1408 | BD_ENET_RX_LAST)) {
22f6b860 1409 /* Frame too long or too short. */
c556167f 1410 ndev->stats.rx_length_errors++;
095098e1
TK		 1411 if (status & BD_ENET_RX_LAST)
1412 netdev_err(ndev, "rcv is not +last\n");
22f6b860 1413 }
22f6b860 1414 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1415 ndev->stats.rx_crc_errors++;
095098e1
TK		 1416 /* Report late collisions as a frame error. */
1417 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1418 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1419 goto rx_processing_done;
1420 }
1da177e4 1421
22f6b860 1422 /* Process the incoming frame. */
c556167f 1423 ndev->stats.rx_packets++;
5cfa3039 1424 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
c556167f 1425 ndev->stats.rx_bytes += pkt_len;
1da177e4 1426
7355f276 1427 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1b7bde6d 1428 skb = rxq->rx_skbuff[index];
ccdc4f19 1429
1b7bde6d
NA		 1430 /* The packet length includes FCS, but we don't want to
1431 * include that when passing upstream as it messes up
1432 * bridging applications.
1433 */
1310b544
LW		 1434 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1435 need_swap);
1b7bde6d
NA		 1436 if (!is_copybreak) {
1437 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1438 if (unlikely(!skb_new)) {
1439 ndev->stats.rx_dropped++;
1440 goto rx_processing_done;
1441 }
5cfa3039
JB		 1442 dma_unmap_single(&fep->pdev->dev,
1443 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1444 FEC_ENET_RX_FRSIZE - fep->rx_align,
1445 DMA_FROM_DEVICE);
1446 }
1447
1448 prefetch(skb->data - NET_IP_ALIGN);
1449 skb_put(skb, pkt_len - 4);
1450 data = skb->data;
3ac72b7b 1451
235bde1e
FE		 1452 if (!is_copybreak && need_swap)
1453 swap_buffer(data, pkt_len);
1454
3ac72b7b
EN		 1455#if !defined(CONFIG_M5272)
1456 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1457 data = skb_pull_inline(skb, 2);
1458#endif
1459
cdffcf1b
JB		 1460 /* Extract the enhanced buffer descriptor */
1461 ebdp = NULL;
1462 if (fep->bufdesc_ex)
1463 ebdp = (struct bufdesc_ex *)bdp;
1464
1465 /* If this is a VLAN packet remove the VLAN Tag */
1466 vlan_packet_rcvd = false;
1467 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
5cfa3039
JB		 1468 fep->bufdesc_ex &&
1469 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
cdffcf1b
JB		 1470 /* Push and remove the vlan tag */
1471 struct vlan_hdr *vlan_header =
1472 (struct vlan_hdr *) (data + ETH_HLEN);
1473 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
cdffcf1b
JB		 1474
1475 vlan_packet_rcvd = true;
1b7bde6d 1476
af5cbc98 1477 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1b7bde6d 1478 skb_pull(skb, VLAN_HLEN);
cdffcf1b
JB		 1479 }
1480
1b7bde6d 1481 skb->protocol = eth_type_trans(skb, ndev);
1da177e4 1482
1b7bde6d
NA		 1483 /* Get receive timestamp from the skb */
1484 if (fep->hwts_rx_en && fep->bufdesc_ex)
5cfa3039 1485 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1b7bde6d
NA		 1486 skb_hwtstamps(skb));
1487
1488 if (fep->bufdesc_ex &&
1489 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
5cfa3039 1490 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1b7bde6d
NA		 1491 /* don't check it */
1492 skb->ip_summed = CHECKSUM_UNNECESSARY;
1493 } else {
1494 skb_checksum_none_assert(skb);
4c09eed9 1495 }
1b7bde6d 1496 }
4c09eed9 1497
1b7bde6d
NA		 1498 /* Handle received VLAN packets */
1499 if (vlan_packet_rcvd)
1500 __vlan_hwaccel_put_tag(skb,
1501 htons(ETH_P_8021Q),
1502 vlan_tag);
cdffcf1b 1503
1b7bde6d
NA		 1504 napi_gro_receive(&fep->napi, skb);
1505
1506 if (is_copybreak) {
5cfa3039
JB		 1507 dma_sync_single_for_device(&fep->pdev->dev,
1508 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1509 FEC_ENET_RX_FRSIZE - fep->rx_align,
1510 DMA_FROM_DEVICE);
1511 } else {
1512 rxq->rx_skbuff[index] = skb_new;
1513 fec_enet_new_rxbdp(ndev, bdp, skb_new);
22f6b860 1514 }
f0b3fbea 1515
22f6b860
SH		 1516rx_processing_done:
1517 /* Clear the status flags for this buffer */
1518 status &= ~BD_ENET_RX_STATS;
1da177e4 1519
22f6b860
SH		 1520 /* Mark the buffer empty */
1521 status |= BD_ENET_RX_EMPTY;
6aa20a22 1522
ff43da86
FL		 1523 if (fep->bufdesc_ex) {
1524 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1525
5cfa3039 1526 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
ff43da86
FL		 1527 ebdp->cbd_prot = 0;
1528 ebdp->cbd_bdu = 0;
1529 }
be293467
TK		 1530 /* Make sure the updates to rest of the descriptor are
1531 * performed before transferring ownership.
1532 */
1533 wmb();
1534 bdp->cbd_sc = cpu_to_fec16(status);
6605b730 1535
22f6b860 1536 /* Update BD pointer to next entry */
7355f276 1537 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
36e24e2e 1538
22f6b860
SH		 1539 /* Doing this here will keep the FEC running while we process
1540 * incoming frames. On a heavily loaded network, we should be
1541 * able to keep up at the expense of system resources.
1542 */
53bb20d1 1543 writel(0, rxq->bd.reg_desc_active);
22f6b860 1544 }
7355f276 1545 rxq->bd.cur = bdp;
4d494cdc
FD		 1546 return pkt_received;
1547}
1da177e4 1548
4d494cdc
FD		 1549static int
1550fec_enet_rx(struct net_device *ndev, int budget)
1551{
1552 int pkt_received = 0;
1553 u16 queue_id;
1554 struct fec_enet_private *fep = netdev_priv(ndev);
1555
1556 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1c021bb7
UKK		 1557 int ret;
1558
1559 ret = fec_enet_rx_queue(ndev,
4d494cdc 1560 budget - pkt_received, queue_id);
1c021bb7
UKK		 1561
1562 if (ret < budget - pkt_received)
1563 clear_bit(queue_id, &fep->work_rx);
1564
1565 pkt_received += ret;
4d494cdc 1566 }
dc975382 1567 return pkt_received;
1da177e4
LT		 1568}
1569
4d494cdc
FD		 1570static bool
1571fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1572{
1573 if (int_events == 0)
1574 return false;
1575
5e62d98c 1576 if (int_events & FEC_ENET_RXF_0)
4d494cdc 1577 fep->work_rx |= (1 << 2);
ce99d0d3
FL		 1578 if (int_events & FEC_ENET_RXF_1)
1579 fep->work_rx |= (1 << 0);
1580 if (int_events & FEC_ENET_RXF_2)
1581 fep->work_rx |= (1 << 1);
4d494cdc 1582
5e62d98c 1583 if (int_events & FEC_ENET_TXF_0)
4d494cdc 1584 fep->work_tx |= (1 << 2);
ce99d0d3
FL		 1585 if (int_events & FEC_ENET_TXF_1)
1586 fep->work_tx |= (1 << 0);
1587 if (int_events & FEC_ENET_TXF_2)
1588 fep->work_tx |= (1 << 1);
4d494cdc
FD		 1589
1590 return true;
1591}
1592
45993653
UKK		 1593static irqreturn_t
1594fec_enet_interrupt(int irq, void *dev_id)
1595{
1596 struct net_device *ndev = dev_id;
1597 struct fec_enet_private *fep = netdev_priv(ndev);
1598 uint int_events;
1599 irqreturn_t ret = IRQ_NONE;
1600
7a16807c 1601 int_events = readl(fep->hwp + FEC_IEVENT);
94191fd6 1602 writel(int_events, fep->hwp + FEC_IEVENT);
4d494cdc 1603 fec_enet_collect_events(fep, int_events);
45993653 1604
61615cd2 1605 if ((fep->work_tx || fep->work_rx) && fep->link) {
7a16807c 1606 ret = IRQ_HANDLED;
dc975382 1607
94191fd6
NA		 1608 if (napi_schedule_prep(&fep->napi)) {
1609 /* Disable the NAPI interrupts */
80dc6a9f 1610 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
94191fd6
NA		 1611 __napi_schedule(&fep->napi);
1612 }
7a16807c 1613 }
45993653 1614
7a16807c
RK		 1615 if (int_events & FEC_ENET_MII) {
1616 ret = IRQ_HANDLED;
1617 complete(&fep->mdio_done);
1618 }
45993653
UKK		 1619 return ret;
1620}
1621
dc975382
FL		 1622static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1623{
1624 struct net_device *ndev = napi->dev;
dc975382 1625 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1626 int pkts;
1627
7a16807c 1628 pkts = fec_enet_rx(ndev, budget);
45993653 1629
de5fb0a0
FL		 1630 fec_enet_tx(ndev);
1631
dc975382 1632 if (pkts < budget) {
6ad20165 1633 napi_complete_done(napi, pkts);
dc975382
FL		 1634 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1635 }
1636 return pkts;
1637}
45993653 1638
e6b043d5 1639/* ------------------------------------------------------------------------- */
0c7768a0 1640static void fec_get_mac(struct net_device *ndev)
1da177e4 1641{
c556167f 1642 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1643 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1644 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1645
49da97dc
SG		 1646 /*
1647 * try to get mac address in following order:
1648 *
1649 * 1) module parameter via kernel command line in form
1650 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1651 */
1652 iap = macaddr;
1653
ca2cc333
SG		 1654 /*
1655 * 2) from device tree data
1656 */
1657 if (!is_valid_ether_addr(iap)) {
1658 struct device_node *np = fep->pdev->dev.of_node;
1659 if (np) {
1660 const char *mac = of_get_mac_address(np);
a51645f7 1661 if (!IS_ERR(mac))
ca2cc333
SG		 1662 iap = (unsigned char *) mac;
1663 }
1664 }
ca2cc333 1665
49da97dc 1666 /*
ca2cc333 1667 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1668 */
1669 if (!is_valid_ether_addr(iap)) {
1670#ifdef CONFIG_M5272
1671 if (FEC_FLASHMAC)
1672 iap = (unsigned char *)FEC_FLASHMAC;
1673#else
1674 if (pdata)
589efdc7 1675 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1676#endif
1677 }
1678
1679 /*
ca2cc333 1680 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1681 */
1682 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1683 *((__be32 *) &tmpaddr[0]) =
1684 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1685 *((__be16 *) &tmpaddr[4]) =
1686 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1687 iap = &tmpaddr[0];
1da177e4
LT		 1688 }
1689
ff5b2fab
LS		 1690 /*
1691 * 5) random mac address
1692 */
1693 if (!is_valid_ether_addr(iap)) {
1694 /* Report it and use a random ethernet address instead */
a19a0582 1695 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
ff5b2fab 1696 eth_hw_addr_random(ndev);
a19a0582
FE		 1697 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1698 ndev->dev_addr);
ff5b2fab
LS		 1699 return;
1700 }
1701
c556167f 1702 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1703
49da97dc
SG		 1704 /* Adjust MAC if using macaddr */
1705 if (iap == macaddr)
43af940c 1706 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1707}
1708
e6b043d5 1709/* ------------------------------------------------------------------------- */
1da177e4 1710
e6b043d5
BW		 1711/*
1712 * Phy section
1713 */
c556167f 1714static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1715{
c556167f 1716 struct fec_enet_private *fep = netdev_priv(ndev);
45f5c327 1717 struct phy_device *phy_dev = ndev->phydev;
e6b043d5 1718 int status_change = 0;
1da177e4 1719
8ce5624f
RK		 1720 /*
1721 * If the netdev is down, or is going down, we're not interested
1722 * in link state events, so just mark our idea of the link as down
1723 * and ignore the event.
1724 */
1725 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1726 fep->link = 0;
1727 } else if (phy_dev->link) {
d97e7497 1728 if (!fep->link) {
6ea0722f 1729 fep->link = phy_dev->link;
e6b043d5
BW		 1730 status_change = 1;
1731 }
1da177e4 1732
ef83337d
RK		 1733 if (fep->full_duplex != phy_dev->duplex) {
1734 fep->full_duplex = phy_dev->duplex;
d97e7497 1735 status_change = 1;
ef83337d 1736 }
d97e7497
LS		 1737
1738 if (phy_dev->speed != fep->speed) {
1739 fep->speed = phy_dev->speed;
1740 status_change = 1;
1741 }
1742
1743 /* if any of the above changed restart the FEC */
dbc64a8e 1744 if (status_change) {
dbc64a8e 1745 napi_disable(&fep->napi);
dbc64a8e 1746 netif_tx_lock_bh(ndev);
ef83337d 1747 fec_restart(ndev);
657ade07 1748 netif_tx_wake_all_queues(ndev);
6af42d42 1749 netif_tx_unlock_bh(ndev);
dbc64a8e 1750 napi_enable(&fep->napi);
dbc64a8e 1751 }
d97e7497
LS		 1752 } else {
1753 if (fep->link) {
f208ce10
RK		 1754 napi_disable(&fep->napi);
1755 netif_tx_lock_bh(ndev);
c556167f 1756 fec_stop(ndev);
f208ce10
RK		 1757 netif_tx_unlock_bh(ndev);
1758 napi_enable(&fep->napi);
8d7ed0f0 1759 fep->link = phy_dev->link;
d97e7497
LS		 1760 status_change = 1;
1761 }
1da177e4 1762 }
6aa20a22 1763
e6b043d5
BW		 1764 if (status_change)
1765 phy_print_status(phy_dev);
1766}
1da177e4 1767
e6b043d5 1768static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1769{
e6b043d5 1770 struct fec_enet_private *fep = bus->priv;
8fff755e 1771 struct device *dev = &fep->pdev->dev;
97b72e43 1772 unsigned long time_left;
d3ee8ec7
MH		 1773 int ret = 0, frame_start, frame_addr, frame_op;
1774 bool is_c45 = !!(regnum & MII_ADDR_C45);
8fff755e
AL		 1775
1776 ret = pm_runtime_get_sync(dev);
b0c6ce24 1777 if (ret < 0)
8fff755e 1778 return ret;
1da177e4 1779
aac27c7a 1780 reinit_completion(&fep->mdio_done);
e6b043d5 1781
d3ee8ec7
MH		 1782 if (is_c45) {
1783 frame_start = FEC_MMFR_ST_C45;
1784
1785 /* write address */
1786 frame_addr = (regnum >> 16);
1787 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1788 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1789 FEC_MMFR_TA | (regnum & 0xFFFF),
1790 fep->hwp + FEC_MII_DATA);
1791
1792 /* wait for end of transfer */
1793 time_left = wait_for_completion_timeout(&fep->mdio_done,
1794 usecs_to_jiffies(FEC_MII_TIMEOUT));
1795 if (time_left == 0) {
1796 netdev_err(fep->netdev, "MDIO address write timeout\n");
1797 ret = -ETIMEDOUT;
1798 goto out;
1799 }
1800
1801 frame_op = FEC_MMFR_OP_READ_C45;
1802
1803 } else {
1804 /* C22 read */
1805 frame_op = FEC_MMFR_OP_READ;
1806 frame_start = FEC_MMFR_ST;
1807 frame_addr = regnum;
1808 }
1809
e6b043d5 1810 /* start a read op */
d3ee8ec7
MH		 1811 writel(frame_start | frame_op |
1812 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
e6b043d5
BW		 1813 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1814
1815 /* wait for end of transfer */
97b72e43
BS		 1816 time_left = wait_for_completion_timeout(&fep->mdio_done,
1817 usecs_to_jiffies(FEC_MII_TIMEOUT));
1818 if (time_left == 0) {
31b7720c 1819 netdev_err(fep->netdev, "MDIO read timeout\n");
8fff755e
AL		 1820 ret = -ETIMEDOUT;
1821 goto out;
1da177e4 1822 }
1da177e4 1823
8fff755e
AL		 1824 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1825
1826out:
1827 pm_runtime_mark_last_busy(dev);
1828 pm_runtime_put_autosuspend(dev);
1829
1830 return ret;
7dd6a2aa 1831}
6aa20a22 1832
e6b043d5
BW		 1833static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1834 u16 value)
1da177e4 1835{
e6b043d5 1836 struct fec_enet_private *fep = bus->priv;
8fff755e 1837 struct device *dev = &fep->pdev->dev;
97b72e43 1838 unsigned long time_left;
d3ee8ec7
MH		 1839 int ret, frame_start, frame_addr;
1840 bool is_c45 = !!(regnum & MII_ADDR_C45);
8fff755e
AL		 1841
1842 ret = pm_runtime_get_sync(dev);
b0c6ce24 1843 if (ret < 0)
8fff755e 1844 return ret;
42ea4457
MS		 1845 else
1846 ret = 0;
1da177e4 1847
aac27c7a 1848 reinit_completion(&fep->mdio_done);
1da177e4 1849
d3ee8ec7
MH		 1850 if (is_c45) {
1851 frame_start = FEC_MMFR_ST_C45;
1852
1853 /* write address */
1854 frame_addr = (regnum >> 16);
1855 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1856 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1857 FEC_MMFR_TA | (regnum & 0xFFFF),
1858 fep->hwp + FEC_MII_DATA);
1859
1860 /* wait for end of transfer */
1861 time_left = wait_for_completion_timeout(&fep->mdio_done,
1862 usecs_to_jiffies(FEC_MII_TIMEOUT));
1863 if (time_left == 0) {
1864 netdev_err(fep->netdev, "MDIO address write timeout\n");
1865 ret = -ETIMEDOUT;
1866 goto out;
1867 }
1868 } else {
1869 /* C22 write */
1870 frame_start = FEC_MMFR_ST;
1871 frame_addr = regnum;
1872 }
1873
862f0982 1874 /* start a write op */
d3ee8ec7
MH		 1875 writel(frame_start | FEC_MMFR_OP_WRITE |
1876 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
e6b043d5
BW		 1877 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1878 fep->hwp + FEC_MII_DATA);
1879
1880 /* wait for end of transfer */
97b72e43
BS		 1881 time_left = wait_for_completion_timeout(&fep->mdio_done,
1882 usecs_to_jiffies(FEC_MII_TIMEOUT));
1883 if (time_left == 0) {
31b7720c 1884 netdev_err(fep->netdev, "MDIO write timeout\n");
8fff755e 1885 ret = -ETIMEDOUT;
e6b043d5 1886 }
1da177e4 1887
d3ee8ec7 1888out:
8fff755e
AL		 1889 pm_runtime_mark_last_busy(dev);
1890 pm_runtime_put_autosuspend(dev);
1891
1892 return ret;
e6b043d5 1893}
1da177e4 1894
e8fcfcd5
NA		 1895static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1896{
1897 struct fec_enet_private *fep = netdev_priv(ndev);
1898 int ret;
1899
1900 if (enable) {
01e5943a
UKK		 1901 ret = clk_prepare_enable(fep->clk_enet_out);
1902 if (ret)
d7c3a206 1903 return ret;
01e5943a 1904
e8fcfcd5 1905 if (fep->clk_ptp) {
91c0d987 1906 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1907 ret = clk_prepare_enable(fep->clk_ptp);
91c0d987
NA		 1908 if (ret) {
1909 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1910 goto failed_clk_ptp;
91c0d987
NA		 1911 } else {
1912 fep->ptp_clk_on = true;
1913 }
1914 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1915 }
01e5943a
UKK		 1916
1917 ret = clk_prepare_enable(fep->clk_ref);
1918 if (ret)
1919 goto failed_clk_ref;
1b0a83ac
RL		 1920
1921 phy_reset_after_clk_enable(ndev->phydev);
e8fcfcd5 1922 } else {
01e5943a 1923 clk_disable_unprepare(fep->clk_enet_out);
91c0d987
NA		 1924 if (fep->clk_ptp) {
1925 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1926 clk_disable_unprepare(fep->clk_ptp);
91c0d987
NA		 1927 fep->ptp_clk_on = false;
1928 mutex_unlock(&fep->ptp_clk_mutex);
1929 }
01e5943a 1930 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1931 }
1932
1933 return 0;
9b5330ed
FD		 1934
1935failed_clk_ref:
1936 if (fep->clk_ref)
1937 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1938failed_clk_ptp:
1939 if (fep->clk_enet_out)
1940 clk_disable_unprepare(fep->clk_enet_out);
e8fcfcd5
NA		 1941
1942 return ret;
1943}
1944
c556167f 1945static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1946{
c556167f 1947 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1948 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1949 char mdio_bus_id[MII_BUS_ID_SIZE];
1950 char phy_name[MII_BUS_ID_SIZE + 3];
1951 int phy_id;
43af940c 1952 int dev_id = fep->dev_id;
562d2f8c 1953
407066f8
UKK		 1954 if (fep->phy_node) {
1955 phy_dev = of_phy_connect(ndev, fep->phy_node,
1956 &fec_enet_adjust_link, 0,
1957 fep->phy_interface);
9558df3a
AL		 1958 if (!phy_dev) {
1959 netdev_err(ndev, "Unable to connect to phy\n");
213a9922 1960 return -ENODEV;
9558df3a 1961 }
407066f8
UKK		 1962 } else {
1963 /* check for attached phy */
1964 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
7f854420 1965 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
407066f8
UKK		 1966 continue;
1967 if (dev_id--)
1968 continue;
949bdd20 1969 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
407066f8
UKK		 1970 break;
1971 }
1da177e4 1972
407066f8
UKK		 1973 if (phy_id >= PHY_MAX_ADDR) {
1974 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
949bdd20 1975 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
407066f8
UKK		 1976 phy_id = 0;
1977 }
1978
1979 snprintf(phy_name, sizeof(phy_name),
1980 PHY_ID_FMT, mdio_bus_id, phy_id);
1981 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1982 fep->phy_interface);
6fcc040f
GU		 1983 }
1984
6fcc040f 1985 if (IS_ERR(phy_dev)) {
31b7720c 1986 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1987 return PTR_ERR(phy_dev);
e6b043d5 1988 }
1da177e4 1989
e6b043d5 1990 /* mask with MAC supported features */
6b7e4008 1991 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
58056c1e 1992 phy_set_max_speed(phy_dev, 1000);
41124fa6
AL		 1993 phy_remove_link_mode(phy_dev,
1994 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
d1391930 1995#if !defined(CONFIG_M5272)
c306ad36 1996 phy_support_sym_pause(phy_dev);
d1391930 1997#endif
baa70a5c 1998 }
230dec61 1999 else
58056c1e 2000 phy_set_max_speed(phy_dev, 100);
230dec61 2001
e6b043d5
BW		 2002 fep->link = 0;
2003 fep->full_duplex = 0;
1da177e4 2004
2220943a 2005 phy_attached_info(phy_dev);
418bd0d4 2006
e6b043d5 2007 return 0;
1da177e4
LT		 2008}
2009
e6b043d5 2010static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 2011{
b5680e0b 2012 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 2013 struct net_device *ndev = platform_get_drvdata(pdev);
2014 struct fec_enet_private *fep = netdev_priv(ndev);
407066f8 2015 struct device_node *node;
e7f4dc35 2016 int err = -ENXIO;
63c60732 2017 u32 mii_speed, holdtime;
6b265293 2018
b5680e0b 2019 /*
3d125f9c 2020 * The i.MX28 dual fec interfaces are not equal.
b5680e0b
SG		 2021 * Here are the differences:
2022 *
2023 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2024 * - fec0 acts as the 1588 time master while fec1 is slave
2025 * - external phys can only be configured by fec0
2026 *
2027 * That is to say fec1 can not work independently. It only works
2028 * when fec0 is working. The reason behind this design is that the
2029 * second interface is added primarily for Switch mode.
2030 *
2031 * Because of the last point above, both phys are attached on fec0
2032 * mdio interface in board design, and need to be configured by
2033 * fec0 mii_bus.
2034 */
3d125f9c 2035 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
b5680e0b 2036 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 2037 if (mii_cnt && fec0_mii_bus) {
2038 fep->mii_bus = fec0_mii_bus;
2039 mii_cnt++;
2040 return 0;
2041 }
2042 return -ENOENT;
b5680e0b
SG		 2043 }
2044
e6b043d5
BW		 2045 /*
2046 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 2047 *
2048 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2049 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2050 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2051 * document.
e6b043d5 2052 */
63c60732 2053 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
6b7e4008 2054 if (fep->quirks & FEC_QUIRK_ENET_MAC)
63c60732
UKK		 2055 mii_speed--;
2056 if (mii_speed > 63) {
2057 dev_err(&pdev->dev,
981a0547 2058 "fec clock (%lu) too fast to get right mii speed\n",
63c60732
UKK		 2059 clk_get_rate(fep->clk_ipg));
2060 err = -EINVAL;
2061 goto err_out;
2062 }
2063
2064 /*
2065 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2066 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2067 * versions are RAZ there, so just ignore the difference and write the
2068 * register always.
2069 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2070 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2071 * output.
2072 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2073 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2074 * holdtime cannot result in a value greater than 3.
2075 */
2076 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2077
2078 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2079
e6b043d5 2080 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 2081
e6b043d5
BW		 2082 fep->mii_bus = mdiobus_alloc();
2083 if (fep->mii_bus == NULL) {
2084 err = -ENOMEM;
2085 goto err_out;
1da177e4
LT		 2086 }
2087
e6b043d5
BW		 2088 fep->mii_bus->name = "fec_enet_mii_bus";
2089 fep->mii_bus->read = fec_enet_mdio_read;
2090 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 2091 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2092 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 2093 fep->mii_bus->priv = fep;
2094 fep->mii_bus->parent = &pdev->dev;
2095
407066f8 2096 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
00e798c7 2097 err = of_mdiobus_register(fep->mii_bus, node);
a4ebec03 2098 of_node_put(node);
407066f8 2099 if (err)
e7f4dc35 2100 goto err_out_free_mdiobus;
1da177e4 2101
e163cc97
LW		 2102 mii_cnt++;
2103
b5680e0b 2104 /* save fec0 mii_bus */
3d125f9c 2105 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
b5680e0b
SG		 2106 fec0_mii_bus = fep->mii_bus;
2107
e6b043d5 2108 return 0;
1da177e4 2109
e6b043d5
BW		 2110err_out_free_mdiobus:
2111 mdiobus_free(fep->mii_bus);
2112err_out:
2113 return err;
1da177e4
LT		 2114}
2115
e6b043d5 2116static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 2117{
e163cc97
LW		 2118 if (--mii_cnt == 0) {
2119 mdiobus_unregister(fep->mii_bus);
e163cc97
LW		 2120 mdiobus_free(fep->mii_bus);
2121 }
1da177e4
LT		 2122}
2123
c556167f 2124static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 2125 struct ethtool_drvinfo *info)
1da177e4 2126{
c556167f 2127 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 2128
7826d43f
JP		 2129 strlcpy(info->driver, fep->pdev->dev.driver->name,
2130 sizeof(info->driver));
2131 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2132 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 2133}
2134
db65f35f
PR		 2135static int fec_enet_get_regs_len(struct net_device *ndev)
2136{
2137 struct fec_enet_private *fep = netdev_priv(ndev);
2138 struct resource *r;
2139 int s = 0;
2140
2141 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2142 if (r)
2143 s = resource_size(r);
2144
2145 return s;
2146}
2147
2148/* List of registers that can be safety be read to dump them with ethtool */
2149#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
3f1dcc6a 2150 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
78cc6e7e 2151 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
f9bcc9f3 2152static __u32 fec_enet_register_version = 2;
db65f35f
PR		 2153static u32 fec_enet_register_offset[] = {
2154 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2155 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2156 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2157 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2158 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2159 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2160 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2161 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2162 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2163 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2164 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2165 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2166 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2167 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2168 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2169 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2170 RMON_T_P_GTE2048, RMON_T_OCTETS,
2171 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2172 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2173 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2174 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2175 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2176 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2177 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2178 RMON_R_P_GTE2048, RMON_R_OCTETS,
2179 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2180 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2181};
2182#else
f9bcc9f3 2183static __u32 fec_enet_register_version = 1;
db65f35f
PR		 2184static u32 fec_enet_register_offset[] = {
2185 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2186 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2187 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2188 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2189 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2190 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2191 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2192 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2193 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2194};
2195#endif
2196
2197static void fec_enet_get_regs(struct net_device *ndev,
2198 struct ethtool_regs *regs, void *regbuf)
2199{
2200 struct fec_enet_private *fep = netdev_priv(ndev);
2201 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2202 u32 *buf = (u32 *)regbuf;
2203 u32 i, off;
2204
f9bcc9f3
VD		 2205 regs->version = fec_enet_register_version;
2206
db65f35f
PR		 2207 memset(buf, 0, regs->len);
2208
2209 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
ec20a63a
FD		 2210 off = fec_enet_register_offset[i];
2211
2212 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2213 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2214 continue;
2215
2216 off >>= 2;
db65f35f
PR		 2217 buf[off] = readl(&theregs[off]);
2218 }
2219}
2220
5ebae489
FL		 2221static int fec_enet_get_ts_info(struct net_device *ndev,
2222 struct ethtool_ts_info *info)
2223{
2224 struct fec_enet_private *fep = netdev_priv(ndev);
2225
2226 if (fep->bufdesc_ex) {
2227
2228 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2229 SOF_TIMESTAMPING_RX_SOFTWARE |
2230 SOF_TIMESTAMPING_SOFTWARE |
2231 SOF_TIMESTAMPING_TX_HARDWARE |
2232 SOF_TIMESTAMPING_RX_HARDWARE |
2233 SOF_TIMESTAMPING_RAW_HARDWARE;
2234 if (fep->ptp_clock)
2235 info->phc_index = ptp_clock_index(fep->ptp_clock);
2236 else
2237 info->phc_index = -1;
2238
2239 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2240 (1 << HWTSTAMP_TX_ON);
2241
2242 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2243 (1 << HWTSTAMP_FILTER_ALL);
2244 return 0;
2245 } else {
2246 return ethtool_op_get_ts_info(ndev, info);
2247 }
2248}
2249
d1391930
GR		 2250#if !defined(CONFIG_M5272)
2251
baa70a5c
FL		 2252static void fec_enet_get_pauseparam(struct net_device *ndev,
2253 struct ethtool_pauseparam *pause)
2254{
2255 struct fec_enet_private *fep = netdev_priv(ndev);
2256
2257 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2258 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2259 pause->rx_pause = pause->tx_pause;
2260}
2261
2262static int fec_enet_set_pauseparam(struct net_device *ndev,
2263 struct ethtool_pauseparam *pause)
2264{
2265 struct fec_enet_private *fep = netdev_priv(ndev);
2266
45f5c327 2267 if (!ndev->phydev)
0b146ca8
RK		 2268 return -ENODEV;
2269
baa70a5c
FL		 2270 if (pause->tx_pause != pause->rx_pause) {
2271 netdev_info(ndev,
2272 "hardware only support enable/disable both tx and rx");
2273 return -EINVAL;
2274 }
2275
2276 fep->pause_flag = 0;
2277
2278 /* tx pause must be same as rx pause */
2279 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2280 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2281
0c122405
AL		 2282 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2283 pause->autoneg);
baa70a5c
FL		 2284
2285 if (pause->autoneg) {
2286 if (netif_running(ndev))
2287 fec_stop(ndev);
45f5c327 2288 phy_start_aneg(ndev->phydev);
baa70a5c 2289 }
dbc64a8e 2290 if (netif_running(ndev)) {
dbc64a8e 2291 napi_disable(&fep->napi);
dbc64a8e 2292 netif_tx_lock_bh(ndev);
ef83337d 2293 fec_restart(ndev);
657ade07 2294 netif_tx_wake_all_queues(ndev);
6af42d42 2295 netif_tx_unlock_bh(ndev);
dbc64a8e 2296 napi_enable(&fep->napi);
dbc64a8e 2297 }
baa70a5c
FL		 2298
2299 return 0;
2300}
2301
38ae92dc
CH		 2302static const struct fec_stat {
2303 char name[ETH_GSTRING_LEN];
2304 u16 offset;
2305} fec_stats[] = {
2306 /* RMON TX */
2307 { "tx_dropped", RMON_T_DROP },
2308 { "tx_packets", RMON_T_PACKETS },
2309 { "tx_broadcast", RMON_T_BC_PKT },
2310 { "tx_multicast", RMON_T_MC_PKT },
2311 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2312 { "tx_undersize", RMON_T_UNDERSIZE },
2313 { "tx_oversize", RMON_T_OVERSIZE },
2314 { "tx_fragment", RMON_T_FRAG },
2315 { "tx_jabber", RMON_T_JAB },
2316 { "tx_collision", RMON_T_COL },
2317 { "tx_64byte", RMON_T_P64 },
2318 { "tx_65to127byte", RMON_T_P65TO127 },
2319 { "tx_128to255byte", RMON_T_P128TO255 },
2320 { "tx_256to511byte", RMON_T_P256TO511 },
2321 { "tx_512to1023byte", RMON_T_P512TO1023 },
2322 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2323 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2324 { "tx_octets", RMON_T_OCTETS },
2325
2326 /* IEEE TX */
2327 { "IEEE_tx_drop", IEEE_T_DROP },
2328 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2329 { "IEEE_tx_1col", IEEE_T_1COL },
2330 { "IEEE_tx_mcol", IEEE_T_MCOL },
2331 { "IEEE_tx_def", IEEE_T_DEF },
2332 { "IEEE_tx_lcol", IEEE_T_LCOL },
2333 { "IEEE_tx_excol", IEEE_T_EXCOL },
2334 { "IEEE_tx_macerr", IEEE_T_MACERR },
2335 { "IEEE_tx_cserr", IEEE_T_CSERR },
2336 { "IEEE_tx_sqe", IEEE_T_SQE },
2337 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2338 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2339
2340 /* RMON RX */
2341 { "rx_packets", RMON_R_PACKETS },
2342 { "rx_broadcast", RMON_R_BC_PKT },
2343 { "rx_multicast", RMON_R_MC_PKT },
2344 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2345 { "rx_undersize", RMON_R_UNDERSIZE },
2346 { "rx_oversize", RMON_R_OVERSIZE },
2347 { "rx_fragment", RMON_R_FRAG },
2348 { "rx_jabber", RMON_R_JAB },
2349 { "rx_64byte", RMON_R_P64 },
2350 { "rx_65to127byte", RMON_R_P65TO127 },
2351 { "rx_128to255byte", RMON_R_P128TO255 },
2352 { "rx_256to511byte", RMON_R_P256TO511 },
2353 { "rx_512to1023byte", RMON_R_P512TO1023 },
2354 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2355 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2356 { "rx_octets", RMON_R_OCTETS },
2357
2358 /* IEEE RX */
2359 { "IEEE_rx_drop", IEEE_R_DROP },
2360 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2361 { "IEEE_rx_crc", IEEE_R_CRC },
2362 { "IEEE_rx_align", IEEE_R_ALIGN },
2363 { "IEEE_rx_macerr", IEEE_R_MACERR },
2364 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2365 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2366};
2367
f85de666
NY		 2368#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2369
80cca775 2370static void fec_enet_update_ethtool_stats(struct net_device *dev)
38ae92dc
CH		 2371{
2372 struct fec_enet_private *fep = netdev_priv(dev);
2373 int i;
2374
2375 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
80cca775
NY		 2376 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2377}
2378
2379static void fec_enet_get_ethtool_stats(struct net_device *dev,
2380 struct ethtool_stats *stats, u64 *data)
2381{
2382 struct fec_enet_private *fep = netdev_priv(dev);
2383
2384 if (netif_running(dev))
2385 fec_enet_update_ethtool_stats(dev);
2386
f85de666 2387 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
38ae92dc
CH		 2388}
2389
2390static void fec_enet_get_strings(struct net_device *netdev,
2391 u32 stringset, u8 *data)
2392{
2393 int i;
2394 switch (stringset) {
2395 case ETH_SS_STATS:
2396 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2397 memcpy(data + i * ETH_GSTRING_LEN,
2398 fec_stats[i].name, ETH_GSTRING_LEN);
2399 break;
2400 }
2401}
2402
2403static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2404{
2405 switch (sset) {
2406 case ETH_SS_STATS:
2407 return ARRAY_SIZE(fec_stats);
2408 default:
2409 return -EOPNOTSUPP;
2410 }
2411}
f85de666 2412
2b30842b
AL		 2413static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2414{
2415 struct fec_enet_private *fep = netdev_priv(dev);
2416 int i;
2417
2418 /* Disable MIB statistics counters */
2419 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2420
2421 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2422 writel(0, fep->hwp + fec_stats[i].offset);
2423
2424 /* Don't disable MIB statistics counters */
2425 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2426}
2427
f85de666
NY		 2428#else /* !defined(CONFIG_M5272) */
2429#define FEC_STATS_SIZE 0
2430static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2431{
2432}
41e8e404
FE		 2433
2434static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2435{
2436}
d1391930 2437#endif /* !defined(CONFIG_M5272) */
38ae92dc 2438
d851b47b
FD		 2439/* ITR clock source is enet system clock (clk_ahb).
2440 * TCTT unit is cycle_ns * 64 cycle
2441 * So, the ICTT value = X us / (cycle_ns * 64)
2442 */
2443static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2444{
2445 struct fec_enet_private *fep = netdev_priv(ndev);
2446
2447 return us * (fep->itr_clk_rate / 64000) / 1000;
2448}
2449
2450/* Set threshold for interrupt coalescing */
2451static void fec_enet_itr_coal_set(struct net_device *ndev)
2452{
2453 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2454 int rx_itr, tx_itr;
2455
d851b47b
FD		 2456 /* Must be greater than zero to avoid unpredictable behavior */
2457 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2458 !fep->tx_time_itr || !fep->tx_pkts_itr)
2459 return;
2460
2461 /* Select enet system clock as Interrupt Coalescing
2462 * timer Clock Source
2463 */
2464 rx_itr = FEC_ITR_CLK_SEL;
2465 tx_itr = FEC_ITR_CLK_SEL;
2466
2467 /* set ICFT and ICTT */
2468 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2469 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2470 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2471 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2472
2473 rx_itr |= FEC_ITR_EN;
2474 tx_itr |= FEC_ITR_EN;
2475
2476 writel(tx_itr, fep->hwp + FEC_TXIC0);
2477 writel(rx_itr, fep->hwp + FEC_RXIC0);
ff7566b8
FD		 2478 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2479 writel(tx_itr, fep->hwp + FEC_TXIC1);
2480 writel(rx_itr, fep->hwp + FEC_RXIC1);
2481 writel(tx_itr, fep->hwp + FEC_TXIC2);
2482 writel(rx_itr, fep->hwp + FEC_RXIC2);
2483 }
d851b47b
FD		 2484}
2485
2486static int
2487fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2488{
2489 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b 2490
ff7566b8 2491 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
d851b47b
FD		 2492 return -EOPNOTSUPP;
2493
2494 ec->rx_coalesce_usecs = fep->rx_time_itr;
2495 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2496
2497 ec->tx_coalesce_usecs = fep->tx_time_itr;
2498 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2499
2500 return 0;
2501}
2502
2503static int
2504fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2505{
2506 struct fec_enet_private *fep = netdev_priv(ndev);
517a772c 2507 struct device *dev = &fep->pdev->dev;
d851b47b
FD		 2508 unsigned int cycle;
2509
ff7566b8 2510 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
d851b47b
FD		 2511 return -EOPNOTSUPP;
2512
2513 if (ec->rx_max_coalesced_frames > 255) {
517a772c 2514 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
d851b47b
FD		 2515 return -EINVAL;
2516 }
2517
2518 if (ec->tx_max_coalesced_frames > 255) {
517a772c 2519 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
d851b47b
FD		 2520 return -EINVAL;
2521 }
2522
2523 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2524 if (cycle > 0xFFFF) {
517a772c 2525 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
d851b47b
FD		 2526 return -EINVAL;
2527 }
2528
2529 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2530 if (cycle > 0xFFFF) {
517a772c 2531 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
d851b47b
FD		 2532 return -EINVAL;
2533 }
2534
2535 fep->rx_time_itr = ec->rx_coalesce_usecs;
2536 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2537
2538 fep->tx_time_itr = ec->tx_coalesce_usecs;
2539 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2540
2541 fec_enet_itr_coal_set(ndev);
2542
2543 return 0;
2544}
2545
2546static void fec_enet_itr_coal_init(struct net_device *ndev)
2547{
2548 struct ethtool_coalesce ec;
2549
2550 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2551 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2552
2553 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2554 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2555
2556 fec_enet_set_coalesce(ndev, &ec);
2557}
2558
1b7bde6d
NA		 2559static int fec_enet_get_tunable(struct net_device *netdev,
2560 const struct ethtool_tunable *tuna,
2561 void *data)
2562{
2563 struct fec_enet_private *fep = netdev_priv(netdev);
2564 int ret = 0;
2565
2566 switch (tuna->id) {
2567 case ETHTOOL_RX_COPYBREAK:
2568 *(u32 *)data = fep->rx_copybreak;
2569 break;
2570 default:
2571 ret = -EINVAL;
2572 break;
2573 }
2574
2575 return ret;
2576}
2577
2578static int fec_enet_set_tunable(struct net_device *netdev,
2579 const struct ethtool_tunable *tuna,
2580 const void *data)
2581{
2582 struct fec_enet_private *fep = netdev_priv(netdev);
2583 int ret = 0;
2584
2585 switch (tuna->id) {
2586 case ETHTOOL_RX_COPYBREAK:
2587 fep->rx_copybreak = *(u32 *)data;
2588 break;
2589 default:
2590 ret = -EINVAL;
2591 break;
2592 }
2593
2594 return ret;
2595}
2596
de40ed31
NA		 2597static void
2598fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2599{
2600 struct fec_enet_private *fep = netdev_priv(ndev);
2601
2602 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2603 wol->supported = WAKE_MAGIC;
2604 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2605 } else {
2606 wol->supported = wol->wolopts = 0;
2607 }
2608}
2609
2610static int
2611fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2612{
2613 struct fec_enet_private *fep = netdev_priv(ndev);
2614
2615 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2616 return -EINVAL;
2617
2618 if (wol->wolopts & ~WAKE_MAGIC)
2619 return -EINVAL;
2620
2621 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2622 if (device_may_wakeup(&ndev->dev)) {
2623 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2624 if (fep->irq[0] > 0)
2625 enable_irq_wake(fep->irq[0]);
2626 } else {
2627 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2628 if (fep->irq[0] > 0)
2629 disable_irq_wake(fep->irq[0]);
2630 }
2631
2632 return 0;
2633}
2634
9b07be4b 2635static const struct ethtool_ops fec_enet_ethtool_ops = {
e6b043d5 2636 .get_drvinfo = fec_enet_get_drvinfo,
db65f35f
PR		 2637 .get_regs_len = fec_enet_get_regs_len,
2638 .get_regs = fec_enet_get_regs,
11d59289 2639 .nway_reset = phy_ethtool_nway_reset,
c1d7c48f 2640 .get_link = ethtool_op_get_link,
d851b47b
FD		 2641 .get_coalesce = fec_enet_get_coalesce,
2642 .set_coalesce = fec_enet_set_coalesce,
38ae92dc 2643#ifndef CONFIG_M5272
c1d7c48f
RK		 2644 .get_pauseparam = fec_enet_get_pauseparam,
2645 .set_pauseparam = fec_enet_set_pauseparam,
38ae92dc 2646 .get_strings = fec_enet_get_strings,
c1d7c48f 2647 .get_ethtool_stats = fec_enet_get_ethtool_stats,
38ae92dc
CH		 2648 .get_sset_count = fec_enet_get_sset_count,
2649#endif
c1d7c48f 2650 .get_ts_info = fec_enet_get_ts_info,
1b7bde6d
NA		 2651 .get_tunable = fec_enet_get_tunable,
2652 .set_tunable = fec_enet_set_tunable,
de40ed31
NA		 2653 .get_wol = fec_enet_get_wol,
2654 .set_wol = fec_enet_set_wol,
9365fbf5
PR		 2655 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2656 .set_link_ksettings = phy_ethtool_set_link_ksettings,
e6b043d5 2657};
1da177e4 2658
c556167f 2659static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2660{
c556167f 2661 struct fec_enet_private *fep = netdev_priv(ndev);
45f5c327 2662 struct phy_device *phydev = ndev->phydev;
1da177e4 2663
c556167f 2664 if (!netif_running(ndev))
e6b043d5 2665 return -EINVAL;
1da177e4 2666
e6b043d5
BW		 2667 if (!phydev)
2668 return -ENODEV;
2669
1d5244d0
BH		 2670 if (fep->bufdesc_ex) {
2671 if (cmd == SIOCSHWTSTAMP)
2672 return fec_ptp_set(ndev, rq);
2673 if (cmd == SIOCGHWTSTAMP)
2674 return fec_ptp_get(ndev, rq);
2675 }
ff43da86 2676
28b04113 2677 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2678}
2679
c556167f 2680static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2681{
c556167f 2682 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2683 unsigned int i;
f0b3fbea
SH		 2684 struct sk_buff *skb;
2685 struct bufdesc *bdp;
4d494cdc
FD		 2686 struct fec_enet_priv_tx_q *txq;
2687 struct fec_enet_priv_rx_q *rxq;
59d0f746
FL		 2688 unsigned int q;
2689
2690 for (q = 0; q < fep->num_rx_queues; q++) {
2691 rxq = fep->rx_queue[q];
7355f276
TK		 2692 bdp = rxq->bd.base;
2693 for (i = 0; i < rxq->bd.ring_size; i++) {
59d0f746
FL		 2694 skb = rxq->rx_skbuff[i];
2695 rxq->rx_skbuff[i] = NULL;
2696 if (skb) {
2697 dma_unmap_single(&fep->pdev->dev,
5cfa3039 2698 fec32_to_cpu(bdp->cbd_bufaddr),
b64bf4b7 2699 FEC_ENET_RX_FRSIZE - fep->rx_align,
59d0f746
FL		 2700 DMA_FROM_DEVICE);
2701 dev_kfree_skb(skb);
2702 }
7355f276 2703 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
59d0f746
FL		 2704 }
2705 }
4d494cdc 2706
59d0f746
FL		 2707 for (q = 0; q < fep->num_tx_queues; q++) {
2708 txq = fep->tx_queue[q];
7355f276
TK		 2709 bdp = txq->bd.base;
2710 for (i = 0; i < txq->bd.ring_size; i++) {
59d0f746
FL		 2711 kfree(txq->tx_bounce[i]);
2712 txq->tx_bounce[i] = NULL;
2713 skb = txq->tx_skbuff[i];
2714 txq->tx_skbuff[i] = NULL;
f0b3fbea 2715 dev_kfree_skb(skb);
730ee360 2716 }
f0b3fbea 2717 }
59d0f746 2718}
f0b3fbea 2719
59d0f746
FL		 2720static void fec_enet_free_queue(struct net_device *ndev)
2721{
2722 struct fec_enet_private *fep = netdev_priv(ndev);
2723 int i;
2724 struct fec_enet_priv_tx_q *txq;
2725
2726 for (i = 0; i < fep->num_tx_queues; i++)
2727 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2728 txq = fep->tx_queue[i];
94920128 2729 dma_free_coherent(&fep->pdev->dev,
7355f276 2730 txq->bd.ring_size * TSO_HEADER_SIZE,
59d0f746
FL		 2731 txq->tso_hdrs,
2732 txq->tso_hdrs_dma);
2733 }
2734
2735 for (i = 0; i < fep->num_rx_queues; i++)
1b4b32c6 2736 kfree(fep->rx_queue[i]);
59d0f746 2737 for (i = 0; i < fep->num_tx_queues; i++)
1b4b32c6 2738 kfree(fep->tx_queue[i]);
59d0f746
FL		 2739}
2740
2741static int fec_enet_alloc_queue(struct net_device *ndev)
2742{
2743 struct fec_enet_private *fep = netdev_priv(ndev);
2744 int i;
2745 int ret = 0;
2746 struct fec_enet_priv_tx_q *txq;
2747
2748 for (i = 0; i < fep->num_tx_queues; i++) {
2749 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2750 if (!txq) {
2751 ret = -ENOMEM;
2752 goto alloc_failed;
2753 }
2754
2755 fep->tx_queue[i] = txq;
7355f276
TK		 2756 txq->bd.ring_size = TX_RING_SIZE;
2757 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
59d0f746
FL		 2758
2759 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2760 txq->tx_wake_threshold =
7355f276 2761 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
59d0f746 2762
94920128 2763 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
7355f276 2764 txq->bd.ring_size * TSO_HEADER_SIZE,
59d0f746
FL		 2765 &txq->tso_hdrs_dma,
2766 GFP_KERNEL);
2767 if (!txq->tso_hdrs) {
2768 ret = -ENOMEM;
2769 goto alloc_failed;
2770 }
8b7c9efa 2771 }
59d0f746
FL		 2772
2773 for (i = 0; i < fep->num_rx_queues; i++) {
2774 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2775 GFP_KERNEL);
2776 if (!fep->rx_queue[i]) {
2777 ret = -ENOMEM;
2778 goto alloc_failed;
2779 }
2780
7355f276
TK		 2781 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2782 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
59d0f746
FL		 2783 }
2784 return ret;
2785
2786alloc_failed:
2787 fec_enet_free_queue(ndev);
2788 return ret;
f0b3fbea
SH		 2789}
2790
59d0f746
FL		 2791static int
2792fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
f0b3fbea 2793{
c556167f 2794 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2795 unsigned int i;
f0b3fbea
SH		 2796 struct sk_buff *skb;
2797 struct bufdesc *bdp;
4d494cdc 2798 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 2799
59d0f746 2800 rxq = fep->rx_queue[queue];
7355f276
TK		 2801 bdp = rxq->bd.base;
2802 for (i = 0; i < rxq->bd.ring_size; i++) {
b72061a3 2803 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2804 if (!skb)
2805 goto err_alloc;
f0b3fbea 2806
1b7bde6d 2807 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
730ee360 2808 dev_kfree_skb(skb);
ffdce2cc 2809 goto err_alloc;
d842a31f 2810 }
730ee360 2811
4d494cdc 2812 rxq->rx_skbuff[i] = skb;
5cfa3039 2813 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
ff43da86
FL		 2814
2815 if (fep->bufdesc_ex) {
2816 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
5cfa3039 2817 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
ff43da86
FL		 2818 }
2819
7355f276 2820 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
f0b3fbea
SH		 2821 }
2822
2823 /* Set the last buffer to wrap. */
7355f276 2824 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
5cfa3039 2825 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 2826 return 0;
f0b3fbea 2827
59d0f746
FL		 2828 err_alloc:
2829 fec_enet_free_buffers(ndev);
2830 return -ENOMEM;
2831}
2832
2833static int
2834fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2835{
2836 struct fec_enet_private *fep = netdev_priv(ndev);
2837 unsigned int i;
2838 struct bufdesc *bdp;
2839 struct fec_enet_priv_tx_q *txq;
2840
2841 txq = fep->tx_queue[queue];
7355f276
TK		 2842 bdp = txq->bd.base;
2843 for (i = 0; i < txq->bd.ring_size; i++) {
4d494cdc
FD		 2844 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2845 if (!txq->tx_bounce[i])
ffdce2cc 2846 goto err_alloc;
f0b3fbea 2847
5cfa3039
JB		 2848 bdp->cbd_sc = cpu_to_fec16(0);
2849 bdp->cbd_bufaddr = cpu_to_fec32(0);
6605b730 2850
ff43da86
FL		 2851 if (fep->bufdesc_ex) {
2852 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
5cfa3039 2853 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
ff43da86
FL		 2854 }
2855
7355f276 2856 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
f0b3fbea
SH		 2857 }
2858
2859 /* Set the last buffer to wrap. */
7355f276 2860 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
5cfa3039 2861 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
f0b3fbea
SH		 2862
2863 return 0;
ffdce2cc
RK		 2864
2865 err_alloc:
2866 fec_enet_free_buffers(ndev);
2867 return -ENOMEM;
f0b3fbea
SH		 2868}
2869
59d0f746
FL		 2870static int fec_enet_alloc_buffers(struct net_device *ndev)
2871{
2872 struct fec_enet_private *fep = netdev_priv(ndev);
2873 unsigned int i;
2874
2875 for (i = 0; i < fep->num_rx_queues; i++)
2876 if (fec_enet_alloc_rxq_buffers(ndev, i))
2877 return -ENOMEM;
2878
2879 for (i = 0; i < fep->num_tx_queues; i++)
2880 if (fec_enet_alloc_txq_buffers(ndev, i))
2881 return -ENOMEM;
2882 return 0;
2883}
2884
1da177e4 2885static int
c556167f 2886fec_enet_open(struct net_device *ndev)
1da177e4 2887{
c556167f 2888 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2889 int ret;
1b0a83ac 2890 bool reset_again;
1da177e4 2891
8fff755e 2892 ret = pm_runtime_get_sync(&fep->pdev->dev);
b0c6ce24 2893 if (ret < 0)
8fff755e
AL		 2894 return ret;
2895
5bbde4d2 2896 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2897 ret = fec_enet_clk_enable(ndev, true);
2898 if (ret)
8fff755e 2899 goto clk_enable;
e8fcfcd5 2900
1b0a83ac
RL		 2901 /* During the first fec_enet_open call the PHY isn't probed at this
2902 * point. Therefore the phy_reset_after_clk_enable() call within
2903 * fec_enet_clk_enable() fails. As we need this reset in order to be
2904 * sure the PHY is working correctly we check if we need to reset again
2905 * later when the PHY is probed
2906 */
2907 if (ndev->phydev && ndev->phydev->drv)
2908 reset_again = false;
2909 else
2910 reset_again = true;
2911
1da177e4
LT		 2912 /* I should reset the ring buffers here, but I don't yet know
2913 * a simple way to do that.
2914 */
1da177e4 2915
c556167f 2916 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea 2917 if (ret)
681d2421 2918 goto err_enet_alloc;
f0b3fbea 2919
55dd2753
NA		 2920 /* Init MAC prior to mii bus probe */
2921 fec_restart(ndev);
2922
418bd0d4 2923 /* Probe and connect to PHY when open the interface */
c556167f 2924 ret = fec_enet_mii_probe(ndev);
681d2421
FE		 2925 if (ret)
2926 goto err_enet_mii_probe;
ce5eaf02 2927
1b0a83ac
RL		 2928 /* Call phy_reset_after_clk_enable() again if it failed during
2929 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
2930 */
2931 if (reset_again)
2932 phy_reset_after_clk_enable(ndev->phydev);
2933
29380905
LS		 2934 if (fep->quirks & FEC_QUIRK_ERR006687)
2935 imx6q_cpuidle_fec_irqs_used();
2936
ce5eaf02 2937 napi_enable(&fep->napi);
45f5c327 2938 phy_start(ndev->phydev);
4d494cdc
FD		 2939 netif_tx_start_all_queues(ndev);
2940
de40ed31
NA		 2941 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2942 FEC_WOL_FLAG_ENABLE);
2943
22f6b860 2944 return 0;
681d2421
FE		 2945
2946err_enet_mii_probe:
2947 fec_enet_free_buffers(ndev);
2948err_enet_alloc:
2949 fec_enet_clk_enable(ndev, false);
8fff755e
AL		 2950clk_enable:
2951 pm_runtime_mark_last_busy(&fep->pdev->dev);
2952 pm_runtime_put_autosuspend(&fep->pdev->dev);
681d2421
FE		 2953 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2954 return ret;
1da177e4
LT		 2955}
2956
2957static int
c556167f 2958fec_enet_close(struct net_device *ndev)
1da177e4 2959{
c556167f 2960 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2961
45f5c327 2962 phy_stop(ndev->phydev);
d76cfae9 2963
31a6de34
RK		 2964 if (netif_device_present(ndev)) {
2965 napi_disable(&fep->napi);
2966 netif_tx_disable(ndev);
8bbbd3c1 2967 fec_stop(ndev);
31a6de34 2968 }
1da177e4 2969
45f5c327 2970 phy_disconnect(ndev->phydev);
418bd0d4 2971
29380905
LS		 2972 if (fep->quirks & FEC_QUIRK_ERR006687)
2973 imx6q_cpuidle_fec_irqs_unused();
2974
80cca775
NY		 2975 fec_enet_update_ethtool_stats(ndev);
2976
e8fcfcd5 2977 fec_enet_clk_enable(ndev, false);
5bbde4d2 2978 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
8fff755e
AL		 2979 pm_runtime_mark_last_busy(&fep->pdev->dev);
2980 pm_runtime_put_autosuspend(&fep->pdev->dev);
2981
db8880bc 2982 fec_enet_free_buffers(ndev);
f0b3fbea 2983
1da177e4
LT		 2984 return 0;
2985}
2986
1da177e4
LT		 2987/* Set or clear the multicast filter for this adaptor.
2988 * Skeleton taken from sunlance driver.
2989 * The CPM Ethernet implementation allows Multicast as well as individual
2990 * MAC address filtering. Some of the drivers check to make sure it is
2991 * a group multicast address, and discard those that are not. I guess I
2992 * will do the same for now, but just remove the test if you want
2993 * individual filtering as well (do the upper net layers want or support
2994 * this kind of feature?).
2995 */
2996
6176e89c 2997#define FEC_HASH_BITS 6 /* #bits in hash */
1da177e4 2998
c556167f 2999static void set_multicast_list(struct net_device *ndev)
1da177e4 3000{
c556167f 3001 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 3002 struct netdev_hw_addr *ha;
16f6e983 3003 unsigned int crc, tmp;
1da177e4 3004 unsigned char hash;
01f8902b 3005 unsigned int hash_high = 0, hash_low = 0;
1da177e4 3006
c556167f 3007 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 3008 tmp = readl(fep->hwp + FEC_R_CNTRL);
3009 tmp |= 0x8;
3010 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 3011 return;
3012 }
1da177e4 3013
4e831836
SH		 3014 tmp = readl(fep->hwp + FEC_R_CNTRL);
3015 tmp &= ~0x8;
3016 writel(tmp, fep->hwp + FEC_R_CNTRL);
3017
c556167f 3018 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 3019 /* Catch all multicast addresses, so set the
3020 * filter to all 1's
3021 */
3022 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3023 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3024
3025 return;
3026 }
3027
01f8902b 3028 /* Add the addresses in hash register */
c556167f 3029 netdev_for_each_mc_addr(ha, ndev) {
4e831836 3030 /* calculate crc32 value of mac address */
16f6e983 3031 crc = ether_crc_le(ndev->addr_len, ha->addr);
4e831836 3032
6176e89c 3033 /* only upper 6 bits (FEC_HASH_BITS) are used
981a0547 3034 * which point to specific bit in the hash registers
4e831836 3035 */
6176e89c 3036 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
4e831836 3037
01f8902b
RS		 3038 if (hash > 31)
3039 hash_high |= 1 << (hash - 32);
3040 else
3041 hash_low |= 1 << hash;
1da177e4 3042 }
01f8902b
RS		 3043
3044 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3045 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1da177e4
LT		 3046}
3047
22f6b860 3048/* Set a MAC change in hardware. */
009fda83 3049static int
c556167f 3050fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 3051{
c556167f 3052 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 3053 struct sockaddr *addr = p;
3054
44934fac
LS		 3055 if (addr) {
3056 if (!is_valid_ether_addr(addr->sa_data))
3057 return -EADDRNOTAVAIL;
3058 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3059 }
1da177e4 3060
9638d19e
NA		 3061 /* Add netif status check here to avoid system hang in below case:
3062 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3063 * After ethx down, fec all clocks are gated off and then register
3064 * access causes system hang.
3065 */
3066 if (!netif_running(ndev))
3067 return 0;
3068
c556167f
UKK		 3069 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3070 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 3071 fep->hwp + FEC_ADDR_LOW);
c556167f 3072 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 3073 fep->hwp + FEC_ADDR_HIGH);
009fda83 3074 return 0;
1da177e4
LT		 3075}
3076
7f5c6add 3077#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 3078/**
3079 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 3080 * @dev: The FEC network adapter
3081 *
3082 * Polled functionality used by netconsole and others in non interrupt mode
3083 *
3084 */
47a5247f 3085static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 3086{
3087 int i;
3088 struct fec_enet_private *fep = netdev_priv(dev);
3089
3090 for (i = 0; i < FEC_IRQ_NUM; i++) {
3091 if (fep->irq[i] > 0) {
3092 disable_irq(fep->irq[i]);
3093 fec_enet_interrupt(fep->irq[i], dev);
3094 enable_irq(fep->irq[i]);
3095 }
3096 }
3097}
3098#endif
3099
5bc26726 3100static inline void fec_enet_set_netdev_features(struct net_device *netdev,
4c09eed9
JB		 3101 netdev_features_t features)
3102{
3103 struct fec_enet_private *fep = netdev_priv(netdev);
3104 netdev_features_t changed = features ^ netdev->features;
3105
3106 netdev->features = features;
3107
3108 /* Receive checksum has been changed */
3109 if (changed & NETIF_F_RXCSUM) {
3110 if (features & NETIF_F_RXCSUM)
3111 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3112 else
3113 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
8506fa1d 3114 }
5bc26726
NA		 3115}
3116
3117static int fec_set_features(struct net_device *netdev,
3118 netdev_features_t features)
3119{
3120 struct fec_enet_private *fep = netdev_priv(netdev);
3121 netdev_features_t changed = features ^ netdev->features;
4c09eed9 3122
5b40f709 3123 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
5bc26726
NA		 3124 napi_disable(&fep->napi);
3125 netif_tx_lock_bh(netdev);
3126 fec_stop(netdev);
3127 fec_enet_set_netdev_features(netdev, features);
ef83337d 3128 fec_restart(netdev);
4d494cdc 3129 netif_tx_wake_all_queues(netdev);
8506fa1d
RK		 3130 netif_tx_unlock_bh(netdev);
3131 napi_enable(&fep->napi);
5bc26726
NA		 3132 } else {
3133 fec_enet_set_netdev_features(netdev, features);
4c09eed9
JB		 3134 }
3135
3136 return 0;
3137}
3138
009fda83
SH		 3139static const struct net_device_ops fec_netdev_ops = {
3140 .ndo_open = fec_enet_open,
3141 .ndo_stop = fec_enet_close,
3142 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 3143 .ndo_set_rx_mode = set_multicast_list,
009fda83
SH		 3144 .ndo_validate_addr = eth_validate_addr,
3145 .ndo_tx_timeout = fec_timeout,
3146 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 3147 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 3148#ifdef CONFIG_NET_POLL_CONTROLLER
3149 .ndo_poll_controller = fec_poll_controller,
3150#endif
4c09eed9 3151 .ndo_set_features = fec_set_features,
009fda83
SH		 3152};
3153
53bb20d1
TK		 3154static const unsigned short offset_des_active_rxq[] = {
3155 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3156};
3157
3158static const unsigned short offset_des_active_txq[] = {
3159 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3160};
3161
1da177e4
LT		 3162 /*
3163 * XXX: We need to clean up on failure exits here.
ead73183 3164 *
1da177e4 3165 */
c556167f 3166static int fec_enet_init(struct net_device *ndev)
1da177e4 3167{
c556167f 3168 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 3169 struct bufdesc *cbd_base;
4d494cdc 3170 dma_addr_t bd_dma;
55d0218a 3171 int bd_size;
59d0f746 3172 unsigned int i;
7355f276
TK		 3173 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3174 sizeof(struct bufdesc);
3175 unsigned dsize_log2 = __fls(dsize);
453e9dc4 3176 int ret;
55d0218a 3177
7355f276 3178 WARN_ON(dsize != (1 << dsize_log2));
3f1dcc6a 3179#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
41ef84ce
FD		 3180 fep->rx_align = 0xf;
3181 fep->tx_align = 0xf;
3182#else
3183 fep->rx_align = 0x3;
3184 fep->tx_align = 0x3;
3185#endif
3186
453e9dc4
SA		 3187 /* Check mask of the streaming and coherent API */
3188 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3189 if (ret < 0) {
3190 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3191 return ret;
3192 }
3193
59d0f746 3194 fec_enet_alloc_queue(ndev);
79f33912 3195
7355f276 3196 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
1da177e4 3197
8d4dd5cf 3198 /* Allocate memory for buffer descriptors. */
c0a1a0a6
LS		 3199 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3200 GFP_KERNEL);
4d494cdc 3201 if (!cbd_base) {
79f33912
NA		 3202 return -ENOMEM;
3203 }
3204
49da97dc 3205 /* Get the Ethernet address */
c556167f 3206 fec_get_mac(ndev);
44934fac
LS		 3207 /* make sure MAC we just acquired is programmed into the hw */
3208 fec_set_mac_address(ndev, NULL);
1da177e4 3209
8d4dd5cf 3210 /* Set receive and transmit descriptor base. */
59d0f746 3211 for (i = 0; i < fep->num_rx_queues; i++) {
7355f276
TK		 3212 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3213 unsigned size = dsize * rxq->bd.ring_size;
3214
3215 rxq->bd.qid = i;
3216 rxq->bd.base = cbd_base;
3217 rxq->bd.cur = cbd_base;
3218 rxq->bd.dma = bd_dma;
3219 rxq->bd.dsize = dsize;
3220 rxq->bd.dsize_log2 = dsize_log2;
53bb20d1 3221 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
7355f276
TK		 3222 bd_dma += size;
3223 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3224 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
59d0f746
FL		 3225 }
3226
3227 for (i = 0; i < fep->num_tx_queues; i++) {
7355f276
TK		 3228 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3229 unsigned size = dsize * txq->bd.ring_size;
3230
3231 txq->bd.qid = i;
3232 txq->bd.base = cbd_base;
3233 txq->bd.cur = cbd_base;
3234 txq->bd.dma = bd_dma;
3235 txq->bd.dsize = dsize;
3236 txq->bd.dsize_log2 = dsize_log2;
53bb20d1 3237 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
7355f276
TK		 3238 bd_dma += size;
3239 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3240 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
59d0f746 3241 }
4d494cdc 3242
1da177e4 3243
22f6b860 3244 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 3245 ndev->watchdog_timeo = TX_TIMEOUT;
3246 ndev->netdev_ops = &fec_netdev_ops;
3247 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 3248
dc975382 3249 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 3250 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 3251
6b7e4008 3252 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 3253 /* enable hw VLAN support */
3254 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 3255
6b7e4008 3256 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 3257 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3258
48496255
SG		 3259 /* enable hw accelerator */
3260 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 3261 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 3262 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3263 }
4c09eed9 3264
6b7e4008 3265 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
41ef84ce
FD		 3266 fep->tx_align = 0;
3267 fep->rx_align = 0x3f;
3268 }
3269
09d1e541
NA		 3270 ndev->hw_features = ndev->features;
3271
ef83337d 3272 fec_restart(ndev);
1da177e4 3273
2b30842b
AL		 3274 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3275 fec_enet_clear_ethtool_stats(ndev);
3276 else
3277 fec_enet_update_ethtool_stats(ndev);
80cca775 3278
1da177e4
LT		 3279 return 0;
3280}
3281
ca2cc333 3282#ifdef CONFIG_OF
9269e556 3283static int fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3284{
3285 int err, phy_reset;
962d8cdc 3286 bool active_high = false;
159a0760 3287 int msec = 1, phy_post_delay = 0;
ca2cc333
SG		 3288 struct device_node *np = pdev->dev.of_node;
3289
3290 if (!np)
9269e556 3291 return 0;
ca2cc333 3292
61e04ccb 3293 err = of_property_read_u32(np, "phy-reset-duration", &msec);
a3caad0a 3294 /* A sane reset duration should not be longer than 1s */
61e04ccb 3295 if (!err && msec > 1000)
a3caad0a
SG		 3296 msec = 1;
3297
ca2cc333 3298 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
9269e556
FD		 3299 if (phy_reset == -EPROBE_DEFER)
3300 return phy_reset;
3301 else if (!gpio_is_valid(phy_reset))
3302 return 0;
07dcf8e9 3303
159a0760
QS		 3304 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3305 /* valid reset duration should be less than 1s */
3306 if (!err && phy_post_delay > 1000)
3307 return -EINVAL;
3308
962d8cdc 3309 active_high = of_property_read_bool(np, "phy-reset-active-high");
64f10f6e 3310
119fc007 3311 err = devm_gpio_request_one(&pdev->dev, phy_reset,
962d8cdc 3312 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
64f10f6e 3313 "phy-reset");
ca2cc333 3314 if (err) {
07dcf8e9 3315 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
9269e556 3316 return err;
ca2cc333 3317 }
eb37c563
SW		 3318
3319 if (msec > 20)
3320 msleep(msec);
3321 else
3322 usleep_range(msec * 1000, msec * 1000 + 1000);
3323
962d8cdc 3324 gpio_set_value_cansleep(phy_reset, !active_high);
9269e556 3325
159a0760
QS		 3326 if (!phy_post_delay)
3327 return 0;
3328
3329 if (phy_post_delay > 20)
3330 msleep(phy_post_delay);
3331 else
3332 usleep_range(phy_post_delay * 1000,
3333 phy_post_delay * 1000 + 1000);
3334
9269e556 3335 return 0;
ca2cc333
SG		 3336}
3337#else /* CONFIG_OF */
9269e556 3338static int fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3339{
3340 /*
3341 * In case of platform probe, the reset has been done
3342 * by machine code.
3343 */
9269e556 3344 return 0;
ca2cc333
SG		 3345}
3346#endif /* CONFIG_OF */
3347
9fc095f1
FD		 3348static void
3349fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3350{
3351 struct device_node *np = pdev->dev.of_node;
9fc095f1
FD		 3352
3353 *num_tx = *num_rx = 1;
3354
3355 if (!np || !of_device_is_available(np))
3356 return;
3357
3358 /* parse the num of tx and rx queues */
73b1c90d 3359 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
b7bd75cf 3360
73b1c90d 3361 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
9fc095f1
FD		 3362
3363 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
b7bd75cf
FL		 3364 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3365 *num_tx);
9fc095f1
FD		 3366 *num_tx = 1;
3367 return;
3368 }
3369
3370 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
b7bd75cf
FL		 3371 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3372 *num_rx);
9fc095f1
FD		 3373 *num_rx = 1;
3374 return;
3375 }
3376
3377}
3378
4ad1ceec
TK		 3379static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3380{
3381 int irq_cnt = platform_irq_count(pdev);
3382
3383 if (irq_cnt > FEC_IRQ_NUM)
3384 irq_cnt = FEC_IRQ_NUM; /* last for pps */
3385 else if (irq_cnt == 2)
3386 irq_cnt = 1; /* last for pps */
3387 else if (irq_cnt <= 0)
3388 irq_cnt = 1; /* At least 1 irq is needed */
3389 return irq_cnt;
3390}
3391
33897cc8 3392static int
ead73183
SH		 3393fec_probe(struct platform_device *pdev)
3394{
3395 struct fec_enet_private *fep;
5eb32bd0 3396 struct fec_platform_data *pdata;
ead73183
SH		 3397 struct net_device *ndev;
3398 int i, irq, ret = 0;
ca2cc333 3399 const struct of_device_id *of_id;
43af940c 3400 static int dev_id;
407066f8 3401 struct device_node *np = pdev->dev.of_node, *phy_node;
b7bd75cf
FL		 3402 int num_tx_qs;
3403 int num_rx_qs;
4ad1ceec
TK		 3404 char irq_name[8];
3405 int irq_cnt;
ca2cc333 3406
9fc095f1
FD		 3407 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3408
ead73183 3409 /* Init network device */
80cca775 3410 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
f85de666 3411 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
83e519b6
FE		 3412 if (!ndev)
3413 return -ENOMEM;
ead73183
SH		 3414
3415 SET_NETDEV_DEV(ndev, &pdev->dev);
3416
3417 /* setup board info structure */
3418 fep = netdev_priv(ndev);
ead73183 3419
6b7e4008
LW		 3420 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3421 if (of_id)
3422 pdev->id_entry = of_id->data;
3423 fep->quirks = pdev->id_entry->driver_data;
3424
0c818594 3425 fep->netdev = ndev;
9fc095f1
FD		 3426 fep->num_rx_queues = num_rx_qs;
3427 fep->num_tx_queues = num_tx_qs;
3428
d1391930 3429#if !defined(CONFIG_M5272)
baa70a5c 3430 /* default enable pause frame auto negotiation */
6b7e4008 3431 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
baa70a5c 3432 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 3433#endif
baa70a5c 3434
5bbde4d2
NA		 3435 /* Select default pin state */
3436 pinctrl_pm_select_default_state(&pdev->dev);
3437
4f830a5a 3438 fep->hwp = devm_platform_ioremap_resource(pdev, 0);
941e173a
TB		 3439 if (IS_ERR(fep->hwp)) {
3440 ret = PTR_ERR(fep->hwp);
3441 goto failed_ioremap;
3442 }
3443
e6b043d5 3444 fep->pdev = pdev;
43af940c 3445 fep->dev_id = dev_id++;
ead73183 3446
ead73183
SH		 3447 platform_set_drvdata(pdev, ndev);
3448
29380905
LS		 3449 if ((of_machine_is_compatible("fsl,imx6q") ||
3450 of_machine_is_compatible("fsl,imx6dl")) &&
3451 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3452 fep->quirks |= FEC_QUIRK_ERR006687;
3453
de40ed31
NA		 3454 if (of_get_property(np, "fsl,magic-packet", NULL))
3455 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3456
407066f8
UKK		 3457 phy_node = of_parse_phandle(np, "phy-handle", 0);
3458 if (!phy_node && of_phy_is_fixed_link(np)) {
3459 ret = of_phy_register_fixed_link(np);
3460 if (ret < 0) {
3461 dev_err(&pdev->dev,
3462 "broken fixed-link specification\n");
3463 goto failed_phy;
3464 }
3465 phy_node = of_node_get(np);
3466 }
3467 fep->phy_node = phy_node;
3468
6c5f7808 3469 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 3470 if (ret < 0) {
94660ba0 3471 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 3472 if (pdata)
3473 fep->phy_interface = pdata->phy;
3474 else
3475 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3476 } else {
3477 fep->phy_interface = ret;
3478 }
3479
f4d40de3
SH		 3480 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3481 if (IS_ERR(fep->clk_ipg)) {
3482 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 3483 goto failed_clk;
3484 }
f4d40de3
SH		 3485
3486 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3487 if (IS_ERR(fep->clk_ahb)) {
3488 ret = PTR_ERR(fep->clk_ahb);
3489 goto failed_clk;
3490 }
3491
d851b47b
FD		 3492 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3493
daa7d392
WS		 3494 /* enet_out is optional, depends on board */
3495 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3496 if (IS_ERR(fep->clk_enet_out))
3497 fep->clk_enet_out = NULL;
3498
91c0d987
NA		 3499 fep->ptp_clk_on = false;
3500 mutex_init(&fep->ptp_clk_mutex);
9b5330ed
FD		 3501
3502 /* clk_ref is optional, depends on board */
3503 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3504 if (IS_ERR(fep->clk_ref))
3505 fep->clk_ref = NULL;
3506
6b7e4008 3507 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730
FL		 3508 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3509 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 3510 fep->clk_ptp = NULL;
217b5844 3511 fep->bufdesc_ex = false;
6605b730 3512 }
6605b730 3513
e8fcfcd5 3514 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 3515 if (ret)
3516 goto failed_clk;
3517
8fff755e
AL		 3518 ret = clk_prepare_enable(fep->clk_ipg);
3519 if (ret)
3520 goto failed_clk_ipg;
d7c3a206
AD		 3521 ret = clk_prepare_enable(fep->clk_ahb);
3522 if (ret)
3523 goto failed_clk_ahb;
8fff755e 3524
25974d8a 3525 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
f4e9f3d2
FE		 3526 if (!IS_ERR(fep->reg_phy)) {
3527 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 3528 if (ret) {
3529 dev_err(&pdev->dev,
3530 "Failed to enable phy regulator: %d\n", ret);
3531 goto failed_regulator;
3532 }
f6a4d607 3533 } else {
3f38c683
FD		 3534 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3535 ret = -EPROBE_DEFER;
3536 goto failed_regulator;
3537 }
f6a4d607 3538 fep->reg_phy = NULL;
5fa9c0fe
SG		 3539 }
3540
8fff755e
AL		 3541 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3542 pm_runtime_use_autosuspend(&pdev->dev);
14d2b7c1 3543 pm_runtime_get_noresume(&pdev->dev);
8fff755e
AL		 3544 pm_runtime_set_active(&pdev->dev);
3545 pm_runtime_enable(&pdev->dev);
3546
9269e556
FD		 3547 ret = fec_reset_phy(pdev);
3548 if (ret)
3549 goto failed_reset;
2ca9b2aa 3550
4ad1ceec 3551 irq_cnt = fec_enet_get_irq_cnt(pdev);
e2f8d555 3552 if (fep->bufdesc_ex)
4ad1ceec 3553 fec_ptp_init(pdev, irq_cnt);
e2f8d555
FE		 3554
3555 ret = fec_enet_init(ndev);
3556 if (ret)
3557 goto failed_init;
3558
4ad1ceec 3559 for (i = 0; i < irq_cnt; i++) {
3ded9f2b 3560 snprintf(irq_name, sizeof(irq_name), "int%d", i);
3b56be21 3561 irq = platform_get_irq_byname_optional(pdev, irq_name);
4ad1ceec
TK		 3562 if (irq < 0)
3563 irq = platform_get_irq(pdev, i);
e2f8d555 3564 if (irq < 0) {
e2f8d555
FE		 3565 ret = irq;
3566 goto failed_irq;
3567 }
0d9b2ab1 3568 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 3569 0, pdev->name, ndev);
0d9b2ab1 3570 if (ret)
e2f8d555 3571 goto failed_irq;
de40ed31
NA		 3572
3573 fep->irq[i] = irq;
e2f8d555
FE		 3574 }
3575
b4d39b53 3576 init_completion(&fep->mdio_done);
e6b043d5
BW		 3577 ret = fec_enet_mii_init(pdev);
3578 if (ret)
3579 goto failed_mii_init;
3580
03c698c9
OS		 3581 /* Carrier starts down, phylib will bring it up */
3582 netif_carrier_off(ndev);
e8fcfcd5 3583 fec_enet_clk_enable(ndev, false);
5bbde4d2 3584 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 3585
ead73183
SH		 3586 ret = register_netdev(ndev);
3587 if (ret)
3588 goto failed_register;
3589
de40ed31
NA		 3590 device_init_wakeup(&ndev->dev, fep->wol_flag &
3591 FEC_WOL_HAS_MAGIC_PACKET);
3592
eb1d0640
FE		 3593 if (fep->bufdesc_ex && fep->ptp_clock)
3594 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3595
1b7bde6d 3596 fep->rx_copybreak = COPYBREAK_DEFAULT;
36cdc743 3597 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
8fff755e
AL		 3598
3599 pm_runtime_mark_last_busy(&pdev->dev);
3600 pm_runtime_put_autosuspend(&pdev->dev);
3601
ead73183
SH		 3602 return 0;
3603
3604failed_register:
e6b043d5
BW		 3605 fec_enet_mii_remove(fep);
3606failed_mii_init:
7a2bbd8d 3607failed_irq:
7a2bbd8d 3608failed_init:
32cba57b 3609 fec_ptp_stop(pdev);
f6a4d607
FE		 3610 if (fep->reg_phy)
3611 regulator_disable(fep->reg_phy);
9269e556 3612failed_reset:
ce8d24f9 3613 pm_runtime_put_noidle(&pdev->dev);
9269e556 3614 pm_runtime_disable(&pdev->dev);
5fa9c0fe 3615failed_regulator:
d7c3a206
AD		 3616 clk_disable_unprepare(fep->clk_ahb);
3617failed_clk_ahb:
3618 clk_disable_unprepare(fep->clk_ipg);
8fff755e 3619failed_clk_ipg:
e8fcfcd5 3620 fec_enet_clk_enable(ndev, false);
ead73183 3621failed_clk:
82005b1c
JH		 3622 if (of_phy_is_fixed_link(np))
3623 of_phy_deregister_fixed_link(np);
407066f8 3624 of_node_put(phy_node);
d1616f07
FD		 3625failed_phy:
3626 dev_id--;
ead73183
SH		 3627failed_ioremap:
3628 free_netdev(ndev);
3629
3630 return ret;
3631}
3632
33897cc8 3633static int
ead73183
SH		 3634fec_drv_remove(struct platform_device *pdev)
3635{
3636 struct net_device *ndev = platform_get_drvdata(pdev);
3637 struct fec_enet_private *fep = netdev_priv(ndev);
82005b1c 3638 struct device_node *np = pdev->dev.of_node;
ead73183 3639
36cdc743 3640 cancel_work_sync(&fep->tx_timeout_work);
32cba57b 3641 fec_ptp_stop(pdev);
e163cc97 3642 unregister_netdev(ndev);
e6b043d5 3643 fec_enet_mii_remove(fep);
f6a4d607
FE		 3644 if (fep->reg_phy)
3645 regulator_disable(fep->reg_phy);
a069215c
FF		 3646 pm_runtime_put(&pdev->dev);
3647 pm_runtime_disable(&pdev->dev);
c43eab3e
CY		 3648 clk_disable_unprepare(fep->clk_ahb);
3649 clk_disable_unprepare(fep->clk_ipg);
82005b1c
JH		 3650 if (of_phy_is_fixed_link(np))
3651 of_phy_deregister_fixed_link(np);
407066f8 3652 of_node_put(fep->phy_node);
ead73183 3653 free_netdev(ndev);
28e2188e 3654
ead73183
SH		 3655 return 0;
3656}
3657
dd66d386 3658static int __maybe_unused fec_suspend(struct device *dev)
ead73183 3659{
87cad5c3 3660 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3661 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 3662
da1774e5 3663 rtnl_lock();
04e5216d 3664 if (netif_running(ndev)) {
de40ed31
NA		 3665 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3666 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
45f5c327 3667 phy_stop(ndev->phydev);
31a6de34
RK		 3668 napi_disable(&fep->napi);
3669 netif_tx_lock_bh(ndev);
04e5216d 3670 netif_device_detach(ndev);
31a6de34
RK		 3671 netif_tx_unlock_bh(ndev);
3672 fec_stop(ndev);
f4c4a4e0 3673 fec_enet_clk_enable(ndev, false);
de40ed31
NA		 3674 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3675 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
ead73183 3676 }
da1774e5
RK		 3677 rtnl_unlock();
3678
de40ed31 3679 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
238f7bc7
FE		 3680 regulator_disable(fep->reg_phy);
3681
858eeb7d
NA		 3682 /* SOC supply clock to phy, when clock is disabled, phy link down
3683 * SOC control phy regulator, when regulator is disabled, phy link down
3684 */
3685 if (fep->clk_enet_out || fep->reg_phy)
3686 fep->link = 0;
3687
ead73183
SH		 3688 return 0;
3689}
3690
dd66d386 3691static int __maybe_unused fec_resume(struct device *dev)
ead73183 3692{
87cad5c3 3693 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3694 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 3695 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
238f7bc7 3696 int ret;
de40ed31 3697 int val;
238f7bc7 3698
de40ed31 3699 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
238f7bc7
FE		 3700 ret = regulator_enable(fep->reg_phy);
3701 if (ret)
3702 return ret;
3703 }
ead73183 3704
da1774e5 3705 rtnl_lock();
04e5216d 3706 if (netif_running(ndev)) {
f4c4a4e0
NA		 3707 ret = fec_enet_clk_enable(ndev, true);
3708 if (ret) {
3709 rtnl_unlock();
3710 goto failed_clk;
3711 }
de40ed31
NA		 3712 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3713 if (pdata && pdata->sleep_mode_enable)
3714 pdata->sleep_mode_enable(false);
3715 val = readl(fep->hwp + FEC_ECNTRL);
3716 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3717 writel(val, fep->hwp + FEC_ECNTRL);
3718 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3719 } else {
3720 pinctrl_pm_select_default_state(&fep->pdev->dev);
3721 }
ef83337d 3722 fec_restart(ndev);
31a6de34 3723 netif_tx_lock_bh(ndev);
6af42d42 3724 netif_device_attach(ndev);
dbc64a8e 3725 netif_tx_unlock_bh(ndev);
6af42d42 3726 napi_enable(&fep->napi);
45f5c327 3727 phy_start(ndev->phydev);
ead73183 3728 }
da1774e5 3729 rtnl_unlock();
04e5216d 3730
ead73183 3731 return 0;
13a097bd 3732
e8fcfcd5 3733failed_clk:
13a097bd
FE		 3734 if (fep->reg_phy)
3735 regulator_disable(fep->reg_phy);
3736 return ret;
ead73183
SH		 3737}
3738
8fff755e
AL		 3739static int __maybe_unused fec_runtime_suspend(struct device *dev)
3740{
3741 struct net_device *ndev = dev_get_drvdata(dev);
3742 struct fec_enet_private *fep = netdev_priv(ndev);
3743
d7c3a206 3744 clk_disable_unprepare(fep->clk_ahb);
8fff755e
AL		 3745 clk_disable_unprepare(fep->clk_ipg);
3746
3747 return 0;
3748}
3749
3750static int __maybe_unused fec_runtime_resume(struct device *dev)
3751{
3752 struct net_device *ndev = dev_get_drvdata(dev);
3753 struct fec_enet_private *fep = netdev_priv(ndev);
d7c3a206 3754 int ret;
8fff755e 3755
d7c3a206
AD		 3756 ret = clk_prepare_enable(fep->clk_ahb);
3757 if (ret)
3758 return ret;
3759 ret = clk_prepare_enable(fep->clk_ipg);
3760 if (ret)
3761 goto failed_clk_ipg;
3762
3763 return 0;
3764
3765failed_clk_ipg:
3766 clk_disable_unprepare(fep->clk_ahb);
3767 return ret;
8fff755e
AL		 3768}
3769
3770static const struct dev_pm_ops fec_pm_ops = {
3771 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3772 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3773};
59d4289b 3774
ead73183
SH		 3775static struct platform_driver fec_driver = {
3776 .driver = {
b5680e0b 3777 .name = DRIVER_NAME,
87cad5c3 3778 .pm = &fec_pm_ops,
ca2cc333 3779 .of_match_table = fec_dt_ids,
ead73183 3780 },
b5680e0b 3781 .id_table = fec_devtype,
87cad5c3 3782 .probe = fec_probe,
33897cc8 3783 .remove = fec_drv_remove,
ead73183
SH		 3784};
3785
aaca2377 3786module_platform_driver(fec_driver);
1da177e4 3787
f8c0aca9 3788MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 3789MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)