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net: fec: improve access to quirk flags by copying them into fec_enet_private struct
[linux-2.6-block.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
7dd6a2aa 5 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
562d2f8c
GU		 15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 19 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 20 *
230dec61 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 22 */
23
1da177e4
LT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
27#include <linux/ptrace.h>
28#include <linux/errno.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
1da177e4
LT		 32#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
4c09eed9
JB		 36#include <linux/in.h>
37#include <linux/ip.h>
38#include <net/ip.h>
79f33912 39#include <net/tso.h>
4c09eed9
JB		 40#include <linux/tcp.h>
41#include <linux/udp.h>
42#include <linux/icmp.h>
1da177e4
LT		 43#include <linux/spinlock.h>
44#include <linux/workqueue.h>
45#include <linux/bitops.h>
6f501b17
SH		 46#include <linux/io.h>
47#include <linux/irq.h>
196719ec 48#include <linux/clk.h>
ead73183 49#include <linux/platform_device.h>
e6b043d5 50#include <linux/phy.h>
5eb32bd0 51#include <linux/fec.h>
ca2cc333
SG		 52#include <linux/of.h>
53#include <linux/of_device.h>
54#include <linux/of_gpio.h>
407066f8 55#include <linux/of_mdio.h>
ca2cc333 56#include <linux/of_net.h>
5fa9c0fe 57#include <linux/regulator/consumer.h>
cdffcf1b 58#include <linux/if_vlan.h>
a68ab98e 59#include <linux/pinctrl/consumer.h>
c259c132 60#include <linux/prefetch.h>
1da177e4 61
080853af 62#include <asm/cacheflush.h>
196719ec 63
1da177e4 64#include "fec.h"
1da177e4 65
772e42b0 66static void set_multicast_list(struct net_device *ndev);
d851b47b 67static void fec_enet_itr_coal_init(struct net_device *ndev);
772e42b0 68
b5680e0b
SG		 69#define DRIVER_NAME "fec"
70
4d494cdc
FD		 71#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
72
baa70a5c
FL		 73/* Pause frame feild and FIFO threshold */
74#define FEC_ENET_FCE (1 << 5)
75#define FEC_ENET_RSEM_V 0x84
76#define FEC_ENET_RSFL_V 16
77#define FEC_ENET_RAEM_V 0x8
78#define FEC_ENET_RAFL_V 0x8
79#define FEC_ENET_OPD_V 0xFFF0
80
b5680e0b
SG		 81static struct platform_device_id fec_devtype[] = {
82 {
0ca1e290 83 /* keep it for coldfire */
b5680e0b
SG		 84 .name = DRIVER_NAME,
85 .driver_data = 0,
0ca1e290
SG		 86 }, {
87 .name = "imx25-fec",
88 .driver_data = FEC_QUIRK_USE_GASKET,
89 }, {
90 .name = "imx27-fec",
91 .driver_data = 0,
b5680e0b
SG		 92 }, {
93 .name = "imx28-fec",
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
230dec61
SG		 95 }, {
96 .name = "imx6q-fec",
ff43da86 97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 98 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
03191656 99 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
ca7c4a45 100 }, {
36803542 101 .name = "mvf600-fec",
ca7c4a45 102 .driver_data = FEC_QUIRK_ENET_MAC,
95a77470
FD		 103 }, {
104 .name = "imx6sx-fec",
105 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
106 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
f88c7ede 107 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
28b5f058 108 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
0ca1e290
SG		 109 }, {
110 /* sentinel */
111 }
b5680e0b 112};
0ca1e290 113MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 114
ca2cc333 115enum imx_fec_type {
a7dd3219 116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 117 IMX27_FEC, /* runs on i.mx27/35/51 */
118 IMX28_FEC,
230dec61 119 IMX6Q_FEC,
36803542 120 MVF600_FEC,
ba593e00 121 IMX6SX_FEC,
ca2cc333
SG		 122};
123
124static const struct of_device_id fec_dt_ids[] = {
125 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
126 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
127 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 128 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 129 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ba593e00 130 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
ca2cc333
SG		 131 { /* sentinel */ }
132};
133MODULE_DEVICE_TABLE(of, fec_dt_ids);
134
49da97dc
SG		 135static unsigned char macaddr[ETH_ALEN];
136module_param_array(macaddr, byte, NULL, 0);
137MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 138
49da97dc 139#if defined(CONFIG_M5272)
1da177e4
LT		 140/*
141 * Some hardware gets it MAC address out of local flash memory.
142 * if this is non-zero then assume it is the address to get MAC from.
143 */
144#if defined(CONFIG_NETtel)
145#define FEC_FLASHMAC 0xf0006006
146#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
147#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 148#elif defined(CONFIG_CANCam)
149#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 150#elif defined (CONFIG_M5272C3)
151#define FEC_FLASHMAC (0xffe04000 + 4)
152#elif defined(CONFIG_MOD5272)
a7dd3219 153#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 154#else
155#define FEC_FLASHMAC 0
156#endif
43be6366 157#endif /* CONFIG_M5272 */
ead73183 158
cdffcf1b 159/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
1da177e4 160 */
cdffcf1b 161#define PKT_MAXBUF_SIZE 1522
1da177e4 162#define PKT_MINBUF_SIZE 64
cdffcf1b 163#define PKT_MAXBLR_SIZE 1536
1da177e4 164
4c09eed9
JB		 165/* FEC receive acceleration */
166#define FEC_RACC_IPDIS (1 << 1)
167#define FEC_RACC_PRODIS (1 << 2)
168#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
169
1da177e4 170/*
6b265293 171 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 172 * size bits. Other FEC hardware does not, so we need to take that into
173 * account when setting it.
174 */
562d2f8c 175#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
085e79ed 176 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
1da177e4
LT		 177#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
178#else
179#define OPT_FRAME_SIZE 0
180#endif
181
e6b043d5
BW		 182/* FEC MII MMFR bits definition */
183#define FEC_MMFR_ST (1 << 30)
184#define FEC_MMFR_OP_READ (2 << 28)
185#define FEC_MMFR_OP_WRITE (1 << 28)
186#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
187#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
188#define FEC_MMFR_TA (2 << 16)
189#define FEC_MMFR_DATA(v) (v & 0xffff)
1da177e4 190
c3b084c2 191#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 192
22f6b860
SH		 193/* Transmitter timeout */
194#define TX_TIMEOUT (2 * HZ)
1da177e4 195
baa70a5c
FL		 196#define FEC_PAUSE_FLAG_AUTONEG 0x1
197#define FEC_PAUSE_FLAG_ENABLE 0x2
198
1b7bde6d
NA		 199#define COPYBREAK_DEFAULT 256
200
79f33912
NA		 201#define TSO_HEADER_SIZE 128
202/* Max number of allowed TCP segments for software TSO */
203#define FEC_MAX_TSO_SEGS 100
204#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
205
206#define IS_TSO_HEADER(txq, addr) \
207 ((addr >= txq->tso_hdrs_dma) && \
208 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
209
e163cc97
LW		 210static int mii_cnt;
211
36e24e2e 212static inline
4d494cdc
FD		 213struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
214 struct fec_enet_private *fep,
215 int queue_id)
ff43da86 216{
36e24e2e
DFB		 217 struct bufdesc *new_bd = bdp + 1;
218 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
4d494cdc
FD		 219 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
220 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
36e24e2e
DFB		 221 struct bufdesc_ex *ex_base;
222 struct bufdesc *base;
223 int ring_size;
224
4d494cdc
FD		 225 if (bdp >= txq->tx_bd_base) {
226 base = txq->tx_bd_base;
227 ring_size = txq->tx_ring_size;
228 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
36e24e2e 229 } else {
4d494cdc
FD		 230 base = rxq->rx_bd_base;
231 ring_size = rxq->rx_ring_size;
232 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
36e24e2e
DFB		 233 }
234
235 if (fep->bufdesc_ex)
236 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
237 ex_base : ex_new_bd);
ff43da86 238 else
36e24e2e
DFB		 239 return (new_bd >= (base + ring_size)) ?
240 base : new_bd;
ff43da86
FL		 241}
242
36e24e2e 243static inline
4d494cdc
FD		 244struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
245 struct fec_enet_private *fep,
246 int queue_id)
ff43da86 247{
36e24e2e
DFB		 248 struct bufdesc *new_bd = bdp - 1;
249 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
4d494cdc
FD		 250 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
251 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
36e24e2e
DFB		 252 struct bufdesc_ex *ex_base;
253 struct bufdesc *base;
254 int ring_size;
255
4d494cdc
FD		 256 if (bdp >= txq->tx_bd_base) {
257 base = txq->tx_bd_base;
258 ring_size = txq->tx_ring_size;
259 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
36e24e2e 260 } else {
4d494cdc
FD		 261 base = rxq->rx_bd_base;
262 ring_size = rxq->rx_ring_size;
263 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
36e24e2e
DFB		 264 }
265
266 if (fep->bufdesc_ex)
267 return (struct bufdesc *)((ex_new_bd < ex_base) ?
268 (ex_new_bd + ring_size) : ex_new_bd);
ff43da86 269 else
36e24e2e 270 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
ff43da86
FL		 271}
272
61a4427b
NA		 273static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
274 struct fec_enet_private *fep)
275{
276 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
277}
278
4d494cdc
FD		 279static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
280 struct fec_enet_priv_tx_q *txq)
6e909283
NA		 281{
282 int entries;
283
4d494cdc
FD		 284 entries = ((const char *)txq->dirty_tx -
285 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
6e909283 286
4d494cdc 287 return entries > 0 ? entries : entries + txq->tx_ring_size;
6e909283
NA		 288}
289
b5680e0b
SG		 290static void *swap_buffer(void *bufaddr, int len)
291{
292 int i;
293 unsigned int *buf = bufaddr;
294
ffed61e6 295 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
b5680e0b
SG		 296 *buf = cpu_to_be32(*buf);
297
298 return bufaddr;
299}
300
1310b544
LW		 301static void swap_buffer2(void *dst_buf, void *src_buf, int len)
302{
303 int i;
304 unsigned int *src = src_buf;
305 unsigned int *dst = dst_buf;
306
307 for (i = 0; i < len; i += 4, src++, dst++)
308 *dst = swab32p(src);
309}
310
344756f6
RK		 311static void fec_dump(struct net_device *ndev)
312{
313 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 314 struct bufdesc *bdp;
315 struct fec_enet_priv_tx_q *txq;
316 int index = 0;
344756f6
RK		 317
318 netdev_info(ndev, "TX ring dump\n");
319 pr_info("Nr SC addr len SKB\n");
320
4d494cdc
FD		 321 txq = fep->tx_queue[0];
322 bdp = txq->tx_bd_base;
323
344756f6
RK		 324 do {
325 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
326 index,
4d494cdc
FD		 327 bdp == txq->cur_tx ? 'S' : ' ',
328 bdp == txq->dirty_tx ? 'H' : ' ',
344756f6 329 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
4d494cdc
FD		 330 txq->tx_skbuff[index]);
331 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
344756f6 332 index++;
4d494cdc 333 } while (bdp != txq->tx_bd_base);
344756f6
RK		 334}
335
62a02c98
FD		 336static inline bool is_ipv4_pkt(struct sk_buff *skb)
337{
338 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
339}
340
4c09eed9
JB		 341static int
342fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
343{
344 /* Only run for packets requiring a checksum. */
345 if (skb->ip_summed != CHECKSUM_PARTIAL)
346 return 0;
347
348 if (unlikely(skb_cow_head(skb, 0)))
349 return -1;
350
62a02c98
FD		 351 if (is_ipv4_pkt(skb))
352 ip_hdr(skb)->check = 0;
4c09eed9
JB		 353 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
354
355 return 0;
356}
357
6e909283 358static int
4d494cdc
FD		 359fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
360 struct sk_buff *skb,
361 struct net_device *ndev)
1da177e4 362{
c556167f 363 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 364 struct bufdesc *bdp = txq->cur_tx;
6e909283
NA		 365 struct bufdesc_ex *ebdp;
366 int nr_frags = skb_shinfo(skb)->nr_frags;
4d494cdc 367 unsigned short queue = skb_get_queue_mapping(skb);
6e909283
NA		 368 int frag, frag_len;
369 unsigned short status;
370 unsigned int estatus = 0;
371 skb_frag_t *this_frag;
de5fb0a0 372 unsigned int index;
6e909283 373 void *bufaddr;
d6bf3143 374 dma_addr_t addr;
6e909283 375 int i;
1da177e4 376
6e909283
NA		 377 for (frag = 0; frag < nr_frags; frag++) {
378 this_frag = &skb_shinfo(skb)->frags[frag];
4d494cdc 379 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
6e909283
NA		 380 ebdp = (struct bufdesc_ex *)bdp;
381
382 status = bdp->cbd_sc;
383 status &= ~BD_ENET_TX_STATS;
384 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
385 frag_len = skb_shinfo(skb)->frags[frag].size;
386
387 /* Handle the last BD specially */
388 if (frag == nr_frags - 1) {
389 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
390 if (fep->bufdesc_ex) {
391 estatus |= BD_ENET_TX_INT;
392 if (unlikely(skb_shinfo(skb)->tx_flags &
393 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
394 estatus |= BD_ENET_TX_TS;
395 }
396 }
397
398 if (fep->bufdesc_ex) {
6b7e4008 399 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 400 estatus |= FEC_TX_BD_FTYPE(queue);
6e909283
NA		 401 if (skb->ip_summed == CHECKSUM_PARTIAL)
402 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
403 ebdp->cbd_bdu = 0;
404 ebdp->cbd_esc = estatus;
405 }
406
407 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
408
4d494cdc 409 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
41ef84ce 410 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 411 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 412 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
413 bufaddr = txq->tx_bounce[index];
6e909283 414
6b7e4008 415 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 416 swap_buffer(bufaddr, frag_len);
417 }
418
d6bf3143
RK		 419 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
420 DMA_TO_DEVICE);
421 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 422 dev_kfree_skb_any(skb);
423 if (net_ratelimit())
424 netdev_err(ndev, "Tx DMA memory map failed\n");
425 goto dma_mapping_error;
426 }
427
d6bf3143 428 bdp->cbd_bufaddr = addr;
6e909283
NA		 429 bdp->cbd_datlen = frag_len;
430 bdp->cbd_sc = status;
431 }
432
4d494cdc 433 txq->cur_tx = bdp;
6e909283
NA		 434
435 return 0;
436
437dma_mapping_error:
4d494cdc 438 bdp = txq->cur_tx;
6e909283 439 for (i = 0; i < frag; i++) {
4d494cdc 440 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
6e909283
NA		 441 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
442 bdp->cbd_datlen, DMA_TO_DEVICE);
443 }
444 return NETDEV_TX_OK;
445}
1da177e4 446
4d494cdc
FD		 447static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
448 struct sk_buff *skb, struct net_device *ndev)
6e909283
NA		 449{
450 struct fec_enet_private *fep = netdev_priv(ndev);
6e909283
NA		 451 int nr_frags = skb_shinfo(skb)->nr_frags;
452 struct bufdesc *bdp, *last_bdp;
453 void *bufaddr;
d6bf3143 454 dma_addr_t addr;
6e909283
NA		 455 unsigned short status;
456 unsigned short buflen;
4d494cdc 457 unsigned short queue;
6e909283
NA		 458 unsigned int estatus = 0;
459 unsigned int index;
79f33912 460 int entries_free;
6e909283 461 int ret;
22f6b860 462
4d494cdc 463 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
79f33912
NA		 464 if (entries_free < MAX_SKB_FRAGS + 1) {
465 dev_kfree_skb_any(skb);
466 if (net_ratelimit())
467 netdev_err(ndev, "NOT enough BD for SG!\n");
468 return NETDEV_TX_OK;
469 }
470
4c09eed9
JB		 471 /* Protocol checksum off-load for TCP and UDP. */
472 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 473 dev_kfree_skb_any(skb);
4c09eed9
JB		 474 return NETDEV_TX_OK;
475 }
476
6e909283 477 /* Fill in a Tx ring entry */
4d494cdc 478 bdp = txq->cur_tx;
6e909283 479 status = bdp->cbd_sc;
0e702ab3 480 status &= ~BD_ENET_TX_STATS;
1da177e4 481
22f6b860 482 /* Set buffer length and buffer pointer */
9555b31e 483 bufaddr = skb->data;
6e909283 484 buflen = skb_headlen(skb);
1da177e4 485
4d494cdc
FD		 486 queue = skb_get_queue_mapping(skb);
487 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
41ef84ce 488 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 489 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 490 memcpy(txq->tx_bounce[index], skb->data, buflen);
491 bufaddr = txq->tx_bounce[index];
1da177e4 492
6b7e4008 493 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 494 swap_buffer(bufaddr, buflen);
495 }
6aa20a22 496
d6bf3143
RK		 497 /* Push the data cache so the CPM does not get stale memory data. */
498 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
499 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 500 dev_kfree_skb_any(skb);
501 if (net_ratelimit())
502 netdev_err(ndev, "Tx DMA memory map failed\n");
503 return NETDEV_TX_OK;
504 }
1da177e4 505
6e909283 506 if (nr_frags) {
4d494cdc 507 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
6e909283
NA		 508 if (ret)
509 return ret;
510 } else {
511 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
512 if (fep->bufdesc_ex) {
513 estatus = BD_ENET_TX_INT;
514 if (unlikely(skb_shinfo(skb)->tx_flags &
515 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
516 estatus |= BD_ENET_TX_TS;
517 }
518 }
519
ff43da86
FL		 520 if (fep->bufdesc_ex) {
521
522 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 523
ff43da86 524 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 525 fep->hwts_tx_en))
6605b730 526 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 527
6b7e4008 528 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213
NA		 529 estatus |= FEC_TX_BD_FTYPE(queue);
530
6e909283
NA		 531 if (skb->ip_summed == CHECKSUM_PARTIAL)
532 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
533
534 ebdp->cbd_bdu = 0;
535 ebdp->cbd_esc = estatus;
6605b730 536 }
03191656 537
4d494cdc
FD		 538 last_bdp = txq->cur_tx;
539 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
6e909283 540 /* Save skb pointer */
4d494cdc 541 txq->tx_skbuff[index] = skb;
6e909283
NA		 542
543 bdp->cbd_datlen = buflen;
d6bf3143 544 bdp->cbd_bufaddr = addr;
6e909283 545
fb8ef788
DFB		 546 /* Send it on its way. Tell FEC it's ready, interrupt when done,
547 * it's the last BD of the frame, and to put the CRC on the end.
548 */
6e909283 549 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
fb8ef788
DFB		 550 bdp->cbd_sc = status;
551
22f6b860 552 /* If this was the last BD in the ring, start at the beginning again. */
4d494cdc 553 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
1da177e4 554
7a2a8451
ED		 555 skb_tx_timestamp(skb);
556
4d494cdc 557 txq->cur_tx = bdp;
de5fb0a0 558
de5fb0a0 559 /* Trigger transmission start */
4d494cdc 560 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
1da177e4 561
6e909283 562 return 0;
1da177e4
LT		 563}
564
79f33912 565static int
4d494cdc
FD		 566fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
567 struct net_device *ndev,
568 struct bufdesc *bdp, int index, char *data,
569 int size, bool last_tcp, bool is_last)
61a4427b
NA		 570{
571 struct fec_enet_private *fep = netdev_priv(ndev);
61cd2ebb 572 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
befe8213 573 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 574 unsigned short status;
575 unsigned int estatus = 0;
d6bf3143 576 dma_addr_t addr;
61a4427b
NA		 577
578 status = bdp->cbd_sc;
79f33912 579 status &= ~BD_ENET_TX_STATS;
61a4427b 580
79f33912 581 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912 582
41ef84ce 583 if (((unsigned long) data) & fep->tx_align ||
6b7e4008 584 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 585 memcpy(txq->tx_bounce[index], data, size);
586 data = txq->tx_bounce[index];
79f33912 587
6b7e4008 588 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 589 swap_buffer(data, size);
590 }
591
d6bf3143
RK		 592 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
593 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 594 dev_kfree_skb_any(skb);
6e909283 595 if (net_ratelimit())
79f33912 596 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 597 return NETDEV_TX_BUSY;
598 }
599
d6bf3143
RK		 600 bdp->cbd_datlen = size;
601 bdp->cbd_bufaddr = addr;
602
79f33912 603 if (fep->bufdesc_ex) {
6b7e4008 604 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 605 estatus |= FEC_TX_BD_FTYPE(queue);
79f33912
NA		 606 if (skb->ip_summed == CHECKSUM_PARTIAL)
607 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
608 ebdp->cbd_bdu = 0;
609 ebdp->cbd_esc = estatus;
610 }
611
612 /* Handle the last BD specially */
613 if (last_tcp)
614 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
615 if (is_last) {
616 status |= BD_ENET_TX_INTR;
617 if (fep->bufdesc_ex)
618 ebdp->cbd_esc |= BD_ENET_TX_INT;
619 }
620
621 bdp->cbd_sc = status;
622
623 return 0;
624}
625
626static int
4d494cdc
FD		 627fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
628 struct sk_buff *skb, struct net_device *ndev,
629 struct bufdesc *bdp, int index)
79f33912
NA		 630{
631 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912 632 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
61cd2ebb 633 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
befe8213 634 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 635 void *bufaddr;
636 unsigned long dmabuf;
637 unsigned short status;
638 unsigned int estatus = 0;
639
640 status = bdp->cbd_sc;
641 status &= ~BD_ENET_TX_STATS;
642 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
643
4d494cdc
FD		 644 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
645 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
41ef84ce 646 if (((unsigned long)bufaddr) & fep->tx_align ||
6b7e4008 647 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 648 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
649 bufaddr = txq->tx_bounce[index];
79f33912 650
6b7e4008 651 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 652 swap_buffer(bufaddr, hdr_len);
653
654 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
655 hdr_len, DMA_TO_DEVICE);
656 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
657 dev_kfree_skb_any(skb);
658 if (net_ratelimit())
659 netdev_err(ndev, "Tx DMA memory map failed\n");
660 return NETDEV_TX_BUSY;
661 }
662 }
663
664 bdp->cbd_bufaddr = dmabuf;
665 bdp->cbd_datlen = hdr_len;
666
667 if (fep->bufdesc_ex) {
6b7e4008 668 if (fep->quirks & FEC_QUIRK_HAS_AVB)
befe8213 669 estatus |= FEC_TX_BD_FTYPE(queue);
79f33912
NA		 670 if (skb->ip_summed == CHECKSUM_PARTIAL)
671 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
672 ebdp->cbd_bdu = 0;
673 ebdp->cbd_esc = estatus;
674 }
675
676 bdp->cbd_sc = status;
677
678 return 0;
679}
680
4d494cdc
FD		 681static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
682 struct sk_buff *skb,
683 struct net_device *ndev)
79f33912
NA		 684{
685 struct fec_enet_private *fep = netdev_priv(ndev);
686 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
687 int total_len, data_left;
4d494cdc
FD		 688 struct bufdesc *bdp = txq->cur_tx;
689 unsigned short queue = skb_get_queue_mapping(skb);
79f33912
NA		 690 struct tso_t tso;
691 unsigned int index = 0;
692 int ret;
693
4d494cdc 694 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
79f33912
NA		 695 dev_kfree_skb_any(skb);
696 if (net_ratelimit())
697 netdev_err(ndev, "NOT enough BD for TSO!\n");
698 return NETDEV_TX_OK;
699 }
700
701 /* Protocol checksum off-load for TCP and UDP. */
702 if (fec_enet_clear_csum(skb, ndev)) {
703 dev_kfree_skb_any(skb);
704 return NETDEV_TX_OK;
705 }
706
707 /* Initialize the TSO handler, and prepare the first payload */
708 tso_start(skb, &tso);
709
710 total_len = skb->len - hdr_len;
711 while (total_len > 0) {
712 char *hdr;
713
4d494cdc 714 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
79f33912
NA		 715 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
716 total_len -= data_left;
717
718 /* prepare packet headers: MAC + IP + TCP */
4d494cdc 719 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
79f33912 720 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
4d494cdc 721 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
79f33912
NA		 722 if (ret)
723 goto err_release;
724
725 while (data_left > 0) {
726 int size;
727
728 size = min_t(int, tso.size, data_left);
4d494cdc
FD		 729 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
730 index = fec_enet_get_bd_index(txq->tx_bd_base,
731 bdp, fep);
732 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
733 bdp, index,
734 tso.data, size,
735 size == data_left,
79f33912
NA		 736 total_len == 0);
737 if (ret)
738 goto err_release;
739
740 data_left -= size;
741 tso_build_data(skb, &tso, size);
742 }
743
4d494cdc 744 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
79f33912
NA		 745 }
746
747 /* Save skb pointer */
4d494cdc 748 txq->tx_skbuff[index] = skb;
79f33912 749
79f33912 750 skb_tx_timestamp(skb);
4d494cdc 751 txq->cur_tx = bdp;
79f33912
NA		 752
753 /* Trigger transmission start */
6b7e4008 754 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
37d6017b
FD		 755 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
756 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
757 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
758 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
759 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
79f33912
NA		 760
761 return 0;
762
763err_release:
764 /* TODO: Release all used data descriptors for TSO */
765 return ret;
766}
767
768static netdev_tx_t
769fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
770{
771 struct fec_enet_private *fep = netdev_priv(ndev);
772 int entries_free;
4d494cdc
FD		 773 unsigned short queue;
774 struct fec_enet_priv_tx_q *txq;
775 struct netdev_queue *nq;
79f33912
NA		 776 int ret;
777
4d494cdc
FD		 778 queue = skb_get_queue_mapping(skb);
779 txq = fep->tx_queue[queue];
780 nq = netdev_get_tx_queue(ndev, queue);
781
79f33912 782 if (skb_is_gso(skb))
4d494cdc 783 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
79f33912 784 else
4d494cdc 785 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
6e909283
NA		 786 if (ret)
787 return ret;
61a4427b 788
4d494cdc
FD		 789 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
790 if (entries_free <= txq->tx_stop_threshold)
791 netif_tx_stop_queue(nq);
61a4427b
NA		 792
793 return NETDEV_TX_OK;
794}
795
14109a59
FL		 796/* Init RX & TX buffer descriptors
797 */
798static void fec_enet_bd_init(struct net_device *dev)
799{
800 struct fec_enet_private *fep = netdev_priv(dev);
4d494cdc
FD		 801 struct fec_enet_priv_tx_q *txq;
802 struct fec_enet_priv_rx_q *rxq;
14109a59
FL		 803 struct bufdesc *bdp;
804 unsigned int i;
59d0f746 805 unsigned int q;
14109a59 806
59d0f746
FL		 807 for (q = 0; q < fep->num_rx_queues; q++) {
808 /* Initialize the receive buffer descriptors. */
809 rxq = fep->rx_queue[q];
810 bdp = rxq->rx_bd_base;
4d494cdc 811
59d0f746 812 for (i = 0; i < rxq->rx_ring_size; i++) {
14109a59 813
59d0f746
FL		 814 /* Initialize the BD for every fragment in the page. */
815 if (bdp->cbd_bufaddr)
816 bdp->cbd_sc = BD_ENET_RX_EMPTY;
817 else
818 bdp->cbd_sc = 0;
819 bdp = fec_enet_get_nextdesc(bdp, fep, q);
820 }
821
822 /* Set the last buffer to wrap */
823 bdp = fec_enet_get_prevdesc(bdp, fep, q);
824 bdp->cbd_sc |= BD_SC_WRAP;
825
826 rxq->cur_rx = rxq->rx_bd_base;
827 }
828
829 for (q = 0; q < fep->num_tx_queues; q++) {
830 /* ...and the same for transmit */
831 txq = fep->tx_queue[q];
832 bdp = txq->tx_bd_base;
833 txq->cur_tx = bdp;
834
835 for (i = 0; i < txq->tx_ring_size; i++) {
836 /* Initialize the BD for every fragment in the page. */
14109a59 837 bdp->cbd_sc = 0;
59d0f746
FL		 838 if (txq->tx_skbuff[i]) {
839 dev_kfree_skb_any(txq->tx_skbuff[i]);
840 txq->tx_skbuff[i] = NULL;
841 }
842 bdp->cbd_bufaddr = 0;
843 bdp = fec_enet_get_nextdesc(bdp, fep, q);
844 }
845
846 /* Set the last buffer to wrap */
847 bdp = fec_enet_get_prevdesc(bdp, fep, q);
848 bdp->cbd_sc |= BD_SC_WRAP;
849 txq->dirty_tx = bdp;
14109a59 850 }
59d0f746 851}
14109a59 852
ce99d0d3
FL		 853static void fec_enet_active_rxring(struct net_device *ndev)
854{
855 struct fec_enet_private *fep = netdev_priv(ndev);
856 int i;
857
858 for (i = 0; i < fep->num_rx_queues; i++)
859 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
860}
861
59d0f746
FL		 862static void fec_enet_enable_ring(struct net_device *ndev)
863{
864 struct fec_enet_private *fep = netdev_priv(ndev);
865 struct fec_enet_priv_tx_q *txq;
866 struct fec_enet_priv_rx_q *rxq;
867 int i;
14109a59 868
59d0f746
FL		 869 for (i = 0; i < fep->num_rx_queues; i++) {
870 rxq = fep->rx_queue[i];
871 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
14109a59 872
59d0f746
FL		 873 /* enable DMA1/2 */
874 if (i)
875 writel(RCMR_MATCHEN | RCMR_CMP(i),
876 fep->hwp + FEC_RCMR(i));
877 }
14109a59 878
59d0f746
FL		 879 for (i = 0; i < fep->num_tx_queues; i++) {
880 txq = fep->tx_queue[i];
881 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
882
883 /* enable DMA1/2 */
884 if (i)
885 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
886 fep->hwp + FEC_DMA_CFG(i));
14109a59 887 }
59d0f746 888}
14109a59 889
59d0f746
FL		 890static void fec_enet_reset_skb(struct net_device *ndev)
891{
892 struct fec_enet_private *fep = netdev_priv(ndev);
893 struct fec_enet_priv_tx_q *txq;
894 int i, j;
895
896 for (i = 0; i < fep->num_tx_queues; i++) {
897 txq = fep->tx_queue[i];
898
899 for (j = 0; j < txq->tx_ring_size; j++) {
900 if (txq->tx_skbuff[j]) {
901 dev_kfree_skb_any(txq->tx_skbuff[j]);
902 txq->tx_skbuff[j] = NULL;
903 }
904 }
905 }
14109a59
FL		 906}
907
dbc64a8e
RK		 908/*
909 * This function is called to start or restart the FEC during a link
910 * change, transmit timeout, or to reconfigure the FEC. The network
911 * packet processing for this device must be stopped before this call.
45993653 912 */
1da177e4 913static void
ef83337d 914fec_restart(struct net_device *ndev)
1da177e4 915{
c556167f 916 struct fec_enet_private *fep = netdev_priv(ndev);
4c09eed9 917 u32 val;
cd1f402c
UKK		 918 u32 temp_mac[2];
919 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 920 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 921
106c314c
FD		 922 /* Whack a reset. We should wait for this.
923 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
924 * instead of reset MAC itself.
925 */
6b7e4008 926 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
106c314c
FD		 927 writel(0, fep->hwp + FEC_ECNTRL);
928 } else {
929 writel(1, fep->hwp + FEC_ECNTRL);
930 udelay(10);
931 }
1da177e4 932
45993653
UKK		 933 /*
934 * enet-mac reset will reset mac address registers too,
935 * so need to reconfigure it.
936 */
6b7e4008 937 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
45993653
UKK		 938 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
939 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
940 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
941 }
1da177e4 942
45993653
UKK		 943 /* Clear any outstanding interrupt. */
944 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1da177e4 945
45993653
UKK		 946 /* Set maximum receive buffer size. */
947 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1da177e4 948
14109a59
FL		 949 fec_enet_bd_init(ndev);
950
59d0f746 951 fec_enet_enable_ring(ndev);
45993653 952
59d0f746
FL		 953 /* Reset tx SKB buffers. */
954 fec_enet_reset_skb(ndev);
97b72e43 955
45993653 956 /* Enable MII mode */
ef83337d 957 if (fep->full_duplex == DUPLEX_FULL) {
cd1f402c 958 /* FD enable */
45993653
UKK		 959 writel(0x04, fep->hwp + FEC_X_CNTRL);
960 } else {
cd1f402c
UKK		 961 /* No Rcv on Xmit */
962 rcntl |= 0x02;
45993653
UKK		 963 writel(0x0, fep->hwp + FEC_X_CNTRL);
964 }
cd1f402c 965
45993653
UKK		 966 /* Set MII speed */
967 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
968
d1391930 969#if !defined(CONFIG_M5272)
4c09eed9
JB		 970 /* set RX checksum */
971 val = readl(fep->hwp + FEC_RACC);
972 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
973 val |= FEC_RACC_OPTIONS;
974 else
975 val &= ~FEC_RACC_OPTIONS;
976 writel(val, fep->hwp + FEC_RACC);
d1391930 977#endif
4c09eed9 978
45993653
UKK		 979 /*
980 * The phy interface and speed need to get configured
981 * differently on enet-mac.
982 */
6b7e4008 983 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 984 /* Enable flow control and length check */
985 rcntl |= 0x40000000 | 0x00000020;
45993653 986
230dec61
SG		 987 /* RGMII, RMII or MII */
988 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
989 rcntl |= (1 << 6);
990 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 991 rcntl |= (1 << 8);
45993653 992 else
cd1f402c 993 rcntl &= ~(1 << 8);
45993653 994
230dec61
SG		 995 /* 1G, 100M or 10M */
996 if (fep->phy_dev) {
997 if (fep->phy_dev->speed == SPEED_1000)
998 ecntl |= (1 << 5);
999 else if (fep->phy_dev->speed == SPEED_100)
1000 rcntl &= ~(1 << 9);
1001 else
1002 rcntl |= (1 << 9);
1003 }
45993653
UKK		 1004 } else {
1005#ifdef FEC_MIIGSK_ENR
6b7e4008 1006 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
8d82f219 1007 u32 cfgr;
45993653
UKK		 1008 /* disable the gasket and wait */
1009 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1010 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1011 udelay(1);
1012
1013 /*
1014 * configure the gasket:
1015 * RMII, 50 MHz, no loopback, no echo
0ca1e290 1016 * MII, 25 MHz, no loopback, no echo
45993653 1017 */
8d82f219
EB		 1018 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1019 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1020 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1021 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1022 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 1023
1024 /* re-enable the gasket */
1025 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 1026 }
45993653
UKK		 1027#endif
1028 }
baa70a5c 1029
d1391930 1030#if !defined(CONFIG_M5272)
baa70a5c
FL		 1031 /* enable pause frame*/
1032 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1033 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1034 fep->phy_dev && fep->phy_dev->pause)) {
1035 rcntl |= FEC_ENET_FCE;
1036
4c09eed9 1037 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 1038 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1039 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1040 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1041 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1042
1043 /* OPD */
1044 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1045 } else {
1046 rcntl &= ~FEC_ENET_FCE;
1047 }
d1391930 1048#endif /* !defined(CONFIG_M5272) */
baa70a5c 1049
cd1f402c 1050 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 1051
84fe6182
SW		 1052 /* Setup multicast filter. */
1053 set_multicast_list(ndev);
1054#ifndef CONFIG_M5272
1055 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1056 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1057#endif
1058
6b7e4008 1059 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
230dec61
SG		 1060 /* enable ENET endian swap */
1061 ecntl |= (1 << 8);
1062 /* enable ENET store and forward mode */
1063 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1064 }
1065
ff43da86
FL		 1066 if (fep->bufdesc_ex)
1067 ecntl |= (1 << 4);
6605b730 1068
38ae92dc 1069#ifndef CONFIG_M5272
b9eef55c
JB		 1070 /* Enable the MIB statistic event counters */
1071 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 1072#endif
1073
45993653 1074 /* And last, enable the transmit and receive processing */
230dec61 1075 writel(ecntl, fep->hwp + FEC_ECNTRL);
ce99d0d3 1076 fec_enet_active_rxring(ndev);
45993653 1077
ff43da86
FL		 1078 if (fep->bufdesc_ex)
1079 fec_ptp_start_cyclecounter(ndev);
1080
45993653
UKK		 1081 /* Enable interrupts we wish to service */
1082 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
d851b47b
FD		 1083
1084 /* Init the interrupt coalescing */
1085 fec_enet_itr_coal_init(ndev);
1086
45993653
UKK		 1087}
1088
1089static void
1090fec_stop(struct net_device *ndev)
1091{
1092 struct fec_enet_private *fep = netdev_priv(ndev);
42431dc2 1093 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
45993653
UKK		 1094
1095 /* We cannot expect a graceful transmit stop without link !!! */
1096 if (fep->link) {
1097 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1098 udelay(10);
1099 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 1100 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1101 }
1102
106c314c
FD		 1103 /* Whack a reset. We should wait for this.
1104 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1105 * instead of reset MAC itself.
1106 */
6b7e4008 1107 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
106c314c
FD		 1108 writel(0, fep->hwp + FEC_ECNTRL);
1109 } else {
1110 writel(1, fep->hwp + FEC_ECNTRL);
1111 udelay(10);
1112 }
45993653
UKK		 1113 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1114 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
230dec61
SG		 1115
1116 /* We have to keep ENET enabled to have MII interrupt stay working */
6b7e4008 1117 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
230dec61 1118 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1119 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1120 }
1da177e4
LT		 1121}
1122
1123
45993653
UKK		 1124static void
1125fec_timeout(struct net_device *ndev)
1126{
1127 struct fec_enet_private *fep = netdev_priv(ndev);
1128
344756f6
RK		 1129 fec_dump(ndev);
1130
45993653
UKK		 1131 ndev->stats.tx_errors++;
1132
36cdc743 1133 schedule_work(&fep->tx_timeout_work);
54309fa6
FL		 1134}
1135
36cdc743 1136static void fec_enet_timeout_work(struct work_struct *work)
54309fa6
FL		 1137{
1138 struct fec_enet_private *fep =
36cdc743 1139 container_of(work, struct fec_enet_private, tx_timeout_work);
8ce5624f 1140 struct net_device *ndev = fep->netdev;
54309fa6 1141
36cdc743
RK		 1142 rtnl_lock();
1143 if (netif_device_present(ndev) || netif_running(ndev)) {
1144 napi_disable(&fep->napi);
1145 netif_tx_lock_bh(ndev);
1146 fec_restart(ndev);
1147 netif_wake_queue(ndev);
1148 netif_tx_unlock_bh(ndev);
1149 napi_enable(&fep->napi);
54309fa6 1150 }
36cdc743 1151 rtnl_unlock();
45993653
UKK		 1152}
1153
bfd4ecdd
RK		 1154static void
1155fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1156 struct skb_shared_hwtstamps *hwtstamps)
1157{
1158 unsigned long flags;
1159 u64 ns;
1160
1161 spin_lock_irqsave(&fep->tmreg_lock, flags);
1162 ns = timecounter_cyc2time(&fep->tc, ts);
1163 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1164
1165 memset(hwtstamps, 0, sizeof(*hwtstamps));
1166 hwtstamps->hwtstamp = ns_to_ktime(ns);
1167}
1168
1da177e4 1169static void
4d494cdc 1170fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1da177e4
LT		 1171{
1172 struct fec_enet_private *fep;
2e28532f 1173 struct bufdesc *bdp;
0e702ab3 1174 unsigned short status;
1da177e4 1175 struct sk_buff *skb;
4d494cdc
FD		 1176 struct fec_enet_priv_tx_q *txq;
1177 struct netdev_queue *nq;
de5fb0a0 1178 int index = 0;
79f33912 1179 int entries_free;
1da177e4 1180
c556167f 1181 fep = netdev_priv(ndev);
4d494cdc
FD		 1182
1183 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1184
1185 txq = fep->tx_queue[queue_id];
1186 /* get next bdp of dirty_tx */
1187 nq = netdev_get_tx_queue(ndev, queue_id);
1188 bdp = txq->dirty_tx;
1da177e4 1189
de5fb0a0 1190 /* get next bdp of dirty_tx */
4d494cdc 1191 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
de5fb0a0 1192
0e702ab3 1193 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
de5fb0a0
FL		 1194
1195 /* current queue is empty */
4d494cdc 1196 if (bdp == txq->cur_tx)
f0b3fbea
SH		 1197 break;
1198
4d494cdc 1199 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
de5fb0a0 1200
4d494cdc
FD		 1201 skb = txq->tx_skbuff[index];
1202 txq->tx_skbuff[index] = NULL;
1203 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
79f33912
NA		 1204 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1205 bdp->cbd_datlen, DMA_TO_DEVICE);
2488a54e 1206 bdp->cbd_bufaddr = 0;
6e909283 1207 if (!skb) {
4d494cdc 1208 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
6e909283
NA		 1209 continue;
1210 }
de5fb0a0 1211
1da177e4 1212 /* Check for errors. */
0e702ab3 1213 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1214 BD_ENET_TX_RL | BD_ENET_TX_UN |
1215 BD_ENET_TX_CSL)) {
c556167f 1216 ndev->stats.tx_errors++;
0e702ab3 1217 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1218 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1219 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1220 ndev->stats.tx_window_errors++;
0e702ab3 1221 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1222 ndev->stats.tx_aborted_errors++;
0e702ab3 1223 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1224 ndev->stats.tx_fifo_errors++;
0e702ab3 1225 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1226 ndev->stats.tx_carrier_errors++;
1da177e4 1227 } else {
c556167f 1228 ndev->stats.tx_packets++;
6e909283 1229 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1230 }
1231
ff43da86
FL		 1232 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1233 fep->bufdesc_ex) {
6605b730 1234 struct skb_shared_hwtstamps shhwtstamps;
ff43da86 1235 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730 1236
bfd4ecdd 1237 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
6605b730
FL		 1238 skb_tstamp_tx(skb, &shhwtstamps);
1239 }
ff43da86 1240
1da177e4
LT		 1241 /* Deferred means some collisions occurred during transmit,
1242 * but we eventually sent the packet OK.
1243 */
0e702ab3 1244 if (status & BD_ENET_TX_DEF)
c556167f 1245 ndev->stats.collisions++;
6aa20a22 1246
22f6b860 1247 /* Free the sk buffer associated with this last transmit */
1da177e4 1248 dev_kfree_skb_any(skb);
de5fb0a0 1249
4d494cdc 1250 txq->dirty_tx = bdp;
6aa20a22 1251
22f6b860 1252 /* Update pointer to next buffer descriptor to be transmitted */
4d494cdc 1253 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
6aa20a22 1254
22f6b860 1255 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1256 */
79f33912 1257 if (netif_queue_stopped(ndev)) {
4d494cdc
FD		 1258 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1259 if (entries_free >= txq->tx_wake_threshold)
1260 netif_tx_wake_queue(nq);
79f33912 1261 }
1da177e4 1262 }
ccea2968
RK		 1263
1264 /* ERR006538: Keep the transmitter going */
4d494cdc
FD		 1265 if (bdp != txq->cur_tx &&
1266 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1267 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1268}
1269
1270static void
1271fec_enet_tx(struct net_device *ndev)
1272{
1273 struct fec_enet_private *fep = netdev_priv(ndev);
1274 u16 queue_id;
1275 /* First process class A queue, then Class B and Best Effort queue */
1276 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1277 clear_bit(queue_id, &fep->work_tx);
1278 fec_enet_tx_queue(ndev, queue_id);
1279 }
1280 return;
1da177e4
LT		 1281}
1282
1b7bde6d
NA		 1283static int
1284fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1285{
1286 struct fec_enet_private *fep = netdev_priv(ndev);
1287 int off;
1288
1289 off = ((unsigned long)skb->data) & fep->rx_align;
1290 if (off)
1291 skb_reserve(skb, fep->rx_align + 1 - off);
1292
1293 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1294 FEC_ENET_RX_FRSIZE - fep->rx_align,
1295 DMA_FROM_DEVICE);
1296 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1297 if (net_ratelimit())
1298 netdev_err(ndev, "Rx DMA memory map failed\n");
1299 return -ENOMEM;
1300 }
1301
1302 return 0;
1303}
1304
1305static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1310b544 1306 struct bufdesc *bdp, u32 length, bool swap)
1b7bde6d
NA		 1307{
1308 struct fec_enet_private *fep = netdev_priv(ndev);
1309 struct sk_buff *new_skb;
1310
1311 if (length > fep->rx_copybreak)
1312 return false;
1313
1314 new_skb = netdev_alloc_skb(ndev, length);
1315 if (!new_skb)
1316 return false;
1317
1318 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1319 FEC_ENET_RX_FRSIZE - fep->rx_align,
1320 DMA_FROM_DEVICE);
1310b544
LW		 1321 if (!swap)
1322 memcpy(new_skb->data, (*skb)->data, length);
1323 else
1324 swap_buffer2(new_skb->data, (*skb)->data, length);
1b7bde6d
NA		 1325 *skb = new_skb;
1326
1327 return true;
1328}
1329
1da177e4
LT		 1330/* During a receive, the cur_rx points to the current incoming buffer.
1331 * When we update through the ring, if the next incoming buffer has
1332 * not been given to the system, we just set the empty indicator,
1333 * effectively tossing the packet.
1334 */
dc975382 1335static int
4d494cdc 1336fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1da177e4 1337{
c556167f 1338 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 1339 struct fec_enet_priv_rx_q *rxq;
2e28532f 1340 struct bufdesc *bdp;
0e702ab3 1341 unsigned short status;
1b7bde6d
NA		 1342 struct sk_buff *skb_new = NULL;
1343 struct sk_buff *skb;
1da177e4
LT		 1344 ushort pkt_len;
1345 __u8 *data;
dc975382 1346 int pkt_received = 0;
cdffcf1b
JB		 1347 struct bufdesc_ex *ebdp = NULL;
1348 bool vlan_packet_rcvd = false;
1349 u16 vlan_tag;
d842a31f 1350 int index = 0;
1b7bde6d 1351 bool is_copybreak;
6b7e4008 1352 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
6aa20a22 1353
0e702ab3
GU		 1354#ifdef CONFIG_M532x
1355 flush_cache_all();
6aa20a22 1356#endif
4d494cdc
FD		 1357 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1358 rxq = fep->rx_queue[queue_id];
1da177e4 1359
1da177e4
LT		 1360 /* First, grab all of the stats for the incoming packet.
1361 * These get messed up if we get called due to a busy condition.
1362 */
4d494cdc 1363 bdp = rxq->cur_rx;
1da177e4 1364
22f6b860 1365 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1da177e4 1366
dc975382
FL		 1367 if (pkt_received >= budget)
1368 break;
1369 pkt_received++;
1370
22f6b860
SH		 1371 /* Since we have allocated space to hold a complete frame,
1372 * the last indicator should be set.
1373 */
1374 if ((status & BD_ENET_RX_LAST) == 0)
31b7720c 1375 netdev_err(ndev, "rcv is not +last\n");
1da177e4 1376
db3421c1 1377
22f6b860
SH		 1378 /* Check for errors. */
1379 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1da177e4 1380 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
c556167f 1381 ndev->stats.rx_errors++;
22f6b860
SH		 1382 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1383 /* Frame too long or too short. */
c556167f 1384 ndev->stats.rx_length_errors++;
22f6b860
SH		 1385 }
1386 if (status & BD_ENET_RX_NO) /* Frame alignment */
c556167f 1387 ndev->stats.rx_frame_errors++;
22f6b860 1388 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1389 ndev->stats.rx_crc_errors++;
22f6b860 1390 if (status & BD_ENET_RX_OV) /* FIFO overrun */
c556167f 1391 ndev->stats.rx_fifo_errors++;
1da177e4 1392 }
1da177e4 1393
22f6b860
SH		 1394 /* Report late collisions as a frame error.
1395 * On this error, the BD is closed, but we don't know what we
1396 * have in the buffer. So, just drop this frame on the floor.
1397 */
1398 if (status & BD_ENET_RX_CL) {
c556167f
UKK		 1399 ndev->stats.rx_errors++;
1400 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1401 goto rx_processing_done;
1402 }
1da177e4 1403
22f6b860 1404 /* Process the incoming frame. */
c556167f 1405 ndev->stats.rx_packets++;
22f6b860 1406 pkt_len = bdp->cbd_datlen;
c556167f 1407 ndev->stats.rx_bytes += pkt_len;
1da177e4 1408
4d494cdc 1409 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1b7bde6d 1410 skb = rxq->rx_skbuff[index];
ccdc4f19 1411
1b7bde6d
NA		 1412 /* The packet length includes FCS, but we don't want to
1413 * include that when passing upstream as it messes up
1414 * bridging applications.
1415 */
1310b544
LW		 1416 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1417 need_swap);
1b7bde6d
NA		 1418 if (!is_copybreak) {
1419 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1420 if (unlikely(!skb_new)) {
1421 ndev->stats.rx_dropped++;
1422 goto rx_processing_done;
1423 }
1424 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1425 FEC_ENET_RX_FRSIZE - fep->rx_align,
1426 DMA_FROM_DEVICE);
1427 }
1428
1429 prefetch(skb->data - NET_IP_ALIGN);
1430 skb_put(skb, pkt_len - 4);
1431 data = skb->data;
1310b544 1432 if (!is_copybreak && need_swap)
b5680e0b
SG		 1433 swap_buffer(data, pkt_len);
1434
cdffcf1b
JB		 1435 /* Extract the enhanced buffer descriptor */
1436 ebdp = NULL;
1437 if (fep->bufdesc_ex)
1438 ebdp = (struct bufdesc_ex *)bdp;
1439
1440 /* If this is a VLAN packet remove the VLAN Tag */
1441 vlan_packet_rcvd = false;
1442 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
4d494cdc 1443 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
cdffcf1b
JB		 1444 /* Push and remove the vlan tag */
1445 struct vlan_hdr *vlan_header =
1446 (struct vlan_hdr *) (data + ETH_HLEN);
1447 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
cdffcf1b
JB		 1448
1449 vlan_packet_rcvd = true;
1b7bde6d
NA		 1450
1451 skb_copy_to_linear_data_offset(skb, VLAN_HLEN,
1452 data, (2 * ETH_ALEN));
1453 skb_pull(skb, VLAN_HLEN);
cdffcf1b
JB		 1454 }
1455
1b7bde6d 1456 skb->protocol = eth_type_trans(skb, ndev);
1da177e4 1457
1b7bde6d
NA		 1458 /* Get receive timestamp from the skb */
1459 if (fep->hwts_rx_en && fep->bufdesc_ex)
1460 fec_enet_hwtstamp(fep, ebdp->ts,
1461 skb_hwtstamps(skb));
1462
1463 if (fep->bufdesc_ex &&
1464 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1465 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1466 /* don't check it */
1467 skb->ip_summed = CHECKSUM_UNNECESSARY;
1468 } else {
1469 skb_checksum_none_assert(skb);
4c09eed9 1470 }
1b7bde6d 1471 }
4c09eed9 1472
1b7bde6d
NA		 1473 /* Handle received VLAN packets */
1474 if (vlan_packet_rcvd)
1475 __vlan_hwaccel_put_tag(skb,
1476 htons(ETH_P_8021Q),
1477 vlan_tag);
cdffcf1b 1478
1b7bde6d
NA		 1479 napi_gro_receive(&fep->napi, skb);
1480
1481 if (is_copybreak) {
1482 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1483 FEC_ENET_RX_FRSIZE - fep->rx_align,
1484 DMA_FROM_DEVICE);
1485 } else {
1486 rxq->rx_skbuff[index] = skb_new;
1487 fec_enet_new_rxbdp(ndev, bdp, skb_new);
22f6b860 1488 }
f0b3fbea 1489
22f6b860
SH		 1490rx_processing_done:
1491 /* Clear the status flags for this buffer */
1492 status &= ~BD_ENET_RX_STATS;
1da177e4 1493
22f6b860
SH		 1494 /* Mark the buffer empty */
1495 status |= BD_ENET_RX_EMPTY;
1496 bdp->cbd_sc = status;
6aa20a22 1497
ff43da86
FL		 1498 if (fep->bufdesc_ex) {
1499 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1500
1501 ebdp->cbd_esc = BD_ENET_RX_INT;
1502 ebdp->cbd_prot = 0;
1503 ebdp->cbd_bdu = 0;
1504 }
6605b730 1505
22f6b860 1506 /* Update BD pointer to next entry */
4d494cdc 1507 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
36e24e2e 1508
22f6b860
SH		 1509 /* Doing this here will keep the FEC running while we process
1510 * incoming frames. On a heavily loaded network, we should be
1511 * able to keep up at the expense of system resources.
1512 */
4d494cdc 1513 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
22f6b860 1514 }
4d494cdc
FD		 1515 rxq->cur_rx = bdp;
1516 return pkt_received;
1517}
1da177e4 1518
4d494cdc
FD		 1519static int
1520fec_enet_rx(struct net_device *ndev, int budget)
1521{
1522 int pkt_received = 0;
1523 u16 queue_id;
1524 struct fec_enet_private *fep = netdev_priv(ndev);
1525
1526 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1527 clear_bit(queue_id, &fep->work_rx);
1528 pkt_received += fec_enet_rx_queue(ndev,
1529 budget - pkt_received, queue_id);
1530 }
dc975382 1531 return pkt_received;
1da177e4
LT		 1532}
1533
4d494cdc
FD		 1534static bool
1535fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1536{
1537 if (int_events == 0)
1538 return false;
1539
1540 if (int_events & FEC_ENET_RXF)
1541 fep->work_rx |= (1 << 2);
ce99d0d3
FL		 1542 if (int_events & FEC_ENET_RXF_1)
1543 fep->work_rx |= (1 << 0);
1544 if (int_events & FEC_ENET_RXF_2)
1545 fep->work_rx |= (1 << 1);
4d494cdc
FD		 1546
1547 if (int_events & FEC_ENET_TXF)
1548 fep->work_tx |= (1 << 2);
ce99d0d3
FL		 1549 if (int_events & FEC_ENET_TXF_1)
1550 fep->work_tx |= (1 << 0);
1551 if (int_events & FEC_ENET_TXF_2)
1552 fep->work_tx |= (1 << 1);
4d494cdc
FD		 1553
1554 return true;
1555}
1556
45993653
UKK		 1557static irqreturn_t
1558fec_enet_interrupt(int irq, void *dev_id)
1559{
1560 struct net_device *ndev = dev_id;
1561 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c 1562 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
45993653
UKK		 1563 uint int_events;
1564 irqreturn_t ret = IRQ_NONE;
1565
7a16807c
RK		 1566 int_events = readl(fep->hwp + FEC_IEVENT);
1567 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
4d494cdc 1568 fec_enet_collect_events(fep, int_events);
45993653 1569
7a16807c
RK		 1570 if (int_events & napi_mask) {
1571 ret = IRQ_HANDLED;
dc975382 1572
7a16807c
RK		 1573 /* Disable the NAPI interrupts */
1574 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1575 napi_schedule(&fep->napi);
1576 }
45993653 1577
7a16807c
RK		 1578 if (int_events & FEC_ENET_MII) {
1579 ret = IRQ_HANDLED;
1580 complete(&fep->mdio_done);
1581 }
45993653 1582
81f35ffd
PZ		 1583 if (fep->ptp_clock)
1584 fec_ptp_check_pps_event(fep);
278d2404 1585
45993653
UKK		 1586 return ret;
1587}
1588
dc975382
FL		 1589static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1590{
1591 struct net_device *ndev = napi->dev;
dc975382 1592 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1593 int pkts;
1594
1595 /*
1596 * Clear any pending transmit or receive interrupts before
1597 * processing the rings to avoid racing with the hardware.
1598 */
1599 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1600
1601 pkts = fec_enet_rx(ndev, budget);
45993653 1602
de5fb0a0
FL		 1603 fec_enet_tx(ndev);
1604
dc975382
FL		 1605 if (pkts < budget) {
1606 napi_complete(napi);
1607 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1608 }
1609 return pkts;
1610}
45993653 1611
e6b043d5 1612/* ------------------------------------------------------------------------- */
0c7768a0 1613static void fec_get_mac(struct net_device *ndev)
1da177e4 1614{
c556167f 1615 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1616 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1617 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1618
49da97dc
SG		 1619 /*
1620 * try to get mac address in following order:
1621 *
1622 * 1) module parameter via kernel command line in form
1623 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1624 */
1625 iap = macaddr;
1626
ca2cc333
SG		 1627 /*
1628 * 2) from device tree data
1629 */
1630 if (!is_valid_ether_addr(iap)) {
1631 struct device_node *np = fep->pdev->dev.of_node;
1632 if (np) {
1633 const char *mac = of_get_mac_address(np);
1634 if (mac)
1635 iap = (unsigned char *) mac;
1636 }
1637 }
ca2cc333 1638
49da97dc 1639 /*
ca2cc333 1640 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1641 */
1642 if (!is_valid_ether_addr(iap)) {
1643#ifdef CONFIG_M5272
1644 if (FEC_FLASHMAC)
1645 iap = (unsigned char *)FEC_FLASHMAC;
1646#else
1647 if (pdata)
589efdc7 1648 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1649#endif
1650 }
1651
1652 /*
ca2cc333 1653 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1654 */
1655 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1656 *((__be32 *) &tmpaddr[0]) =
1657 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1658 *((__be16 *) &tmpaddr[4]) =
1659 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1660 iap = &tmpaddr[0];
1da177e4
LT		 1661 }
1662
ff5b2fab
LS		 1663 /*
1664 * 5) random mac address
1665 */
1666 if (!is_valid_ether_addr(iap)) {
1667 /* Report it and use a random ethernet address instead */
1668 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1669 eth_hw_addr_random(ndev);
1670 netdev_info(ndev, "Using random MAC address: %pM\n",
1671 ndev->dev_addr);
1672 return;
1673 }
1674
c556167f 1675 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1676
49da97dc
SG		 1677 /* Adjust MAC if using macaddr */
1678 if (iap == macaddr)
43af940c 1679 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1680}
1681
e6b043d5 1682/* ------------------------------------------------------------------------- */
1da177e4 1683
e6b043d5
BW		 1684/*
1685 * Phy section
1686 */
c556167f 1687static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1688{
c556167f 1689 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1690 struct phy_device *phy_dev = fep->phy_dev;
e6b043d5 1691 int status_change = 0;
1da177e4 1692
e6b043d5
BW		 1693 /* Prevent a state halted on mii error */
1694 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1695 phy_dev->state = PHY_RESUMING;
54309fa6 1696 return;
e6b043d5 1697 }
1da177e4 1698
8ce5624f
RK		 1699 /*
1700 * If the netdev is down, or is going down, we're not interested
1701 * in link state events, so just mark our idea of the link as down
1702 * and ignore the event.
1703 */
1704 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1705 fep->link = 0;
1706 } else if (phy_dev->link) {
d97e7497 1707 if (!fep->link) {
6ea0722f 1708 fep->link = phy_dev->link;
e6b043d5
BW		 1709 status_change = 1;
1710 }
1da177e4 1711
ef83337d
RK		 1712 if (fep->full_duplex != phy_dev->duplex) {
1713 fep->full_duplex = phy_dev->duplex;
d97e7497 1714 status_change = 1;
ef83337d 1715 }
d97e7497
LS		 1716
1717 if (phy_dev->speed != fep->speed) {
1718 fep->speed = phy_dev->speed;
1719 status_change = 1;
1720 }
1721
1722 /* if any of the above changed restart the FEC */
dbc64a8e 1723 if (status_change) {
dbc64a8e 1724 napi_disable(&fep->napi);
dbc64a8e 1725 netif_tx_lock_bh(ndev);
ef83337d 1726 fec_restart(ndev);
dbc64a8e 1727 netif_wake_queue(ndev);
6af42d42 1728 netif_tx_unlock_bh(ndev);
dbc64a8e 1729 napi_enable(&fep->napi);
dbc64a8e 1730 }
d97e7497
LS		 1731 } else {
1732 if (fep->link) {
f208ce10
RK		 1733 napi_disable(&fep->napi);
1734 netif_tx_lock_bh(ndev);
c556167f 1735 fec_stop(ndev);
f208ce10
RK		 1736 netif_tx_unlock_bh(ndev);
1737 napi_enable(&fep->napi);
8d7ed0f0 1738 fep->link = phy_dev->link;
d97e7497
LS		 1739 status_change = 1;
1740 }
1da177e4 1741 }
6aa20a22 1742
e6b043d5
BW		 1743 if (status_change)
1744 phy_print_status(phy_dev);
1745}
1da177e4 1746
e6b043d5 1747static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1748{
e6b043d5 1749 struct fec_enet_private *fep = bus->priv;
97b72e43 1750 unsigned long time_left;
1da177e4 1751
e6b043d5 1752 fep->mii_timeout = 0;
97b72e43 1753 init_completion(&fep->mdio_done);
e6b043d5
BW		 1754
1755 /* start a read op */
1756 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1757 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1758 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1759
1760 /* wait for end of transfer */
97b72e43
BS		 1761 time_left = wait_for_completion_timeout(&fep->mdio_done,
1762 usecs_to_jiffies(FEC_MII_TIMEOUT));
1763 if (time_left == 0) {
1764 fep->mii_timeout = 1;
31b7720c 1765 netdev_err(fep->netdev, "MDIO read timeout\n");
97b72e43 1766 return -ETIMEDOUT;
1da177e4 1767 }
1da177e4 1768
e6b043d5
BW		 1769 /* return value */
1770 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
7dd6a2aa 1771}
6aa20a22 1772
e6b043d5
BW		 1773static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1774 u16 value)
1da177e4 1775{
e6b043d5 1776 struct fec_enet_private *fep = bus->priv;
97b72e43 1777 unsigned long time_left;
1da177e4 1778
e6b043d5 1779 fep->mii_timeout = 0;
97b72e43 1780 init_completion(&fep->mdio_done);
1da177e4 1781
862f0982
SG		 1782 /* start a write op */
1783 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
e6b043d5
BW		 1784 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1785 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1786 fep->hwp + FEC_MII_DATA);
1787
1788 /* wait for end of transfer */
97b72e43
BS		 1789 time_left = wait_for_completion_timeout(&fep->mdio_done,
1790 usecs_to_jiffies(FEC_MII_TIMEOUT));
1791 if (time_left == 0) {
1792 fep->mii_timeout = 1;
31b7720c 1793 netdev_err(fep->netdev, "MDIO write timeout\n");
97b72e43 1794 return -ETIMEDOUT;
e6b043d5 1795 }
1da177e4 1796
e6b043d5
BW		 1797 return 0;
1798}
1da177e4 1799
e8fcfcd5
NA		 1800static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1801{
1802 struct fec_enet_private *fep = netdev_priv(ndev);
1803 int ret;
1804
1805 if (enable) {
1806 ret = clk_prepare_enable(fep->clk_ahb);
1807 if (ret)
1808 return ret;
1809 ret = clk_prepare_enable(fep->clk_ipg);
1810 if (ret)
1811 goto failed_clk_ipg;
1812 if (fep->clk_enet_out) {
1813 ret = clk_prepare_enable(fep->clk_enet_out);
1814 if (ret)
1815 goto failed_clk_enet_out;
1816 }
1817 if (fep->clk_ptp) {
91c0d987 1818 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1819 ret = clk_prepare_enable(fep->clk_ptp);
91c0d987
NA		 1820 if (ret) {
1821 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1822 goto failed_clk_ptp;
91c0d987
NA		 1823 } else {
1824 fep->ptp_clk_on = true;
1825 }
1826 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1827 }
9b5330ed
FD		 1828 if (fep->clk_ref) {
1829 ret = clk_prepare_enable(fep->clk_ref);
1830 if (ret)
1831 goto failed_clk_ref;
1832 }
e8fcfcd5
NA		 1833 } else {
1834 clk_disable_unprepare(fep->clk_ahb);
1835 clk_disable_unprepare(fep->clk_ipg);
1836 if (fep->clk_enet_out)
1837 clk_disable_unprepare(fep->clk_enet_out);
91c0d987
NA		 1838 if (fep->clk_ptp) {
1839 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1840 clk_disable_unprepare(fep->clk_ptp);
91c0d987
NA		 1841 fep->ptp_clk_on = false;
1842 mutex_unlock(&fep->ptp_clk_mutex);
1843 }
9b5330ed
FD		 1844 if (fep->clk_ref)
1845 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1846 }
1847
1848 return 0;
9b5330ed
FD		 1849
1850failed_clk_ref:
1851 if (fep->clk_ref)
1852 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1853failed_clk_ptp:
1854 if (fep->clk_enet_out)
1855 clk_disable_unprepare(fep->clk_enet_out);
1856failed_clk_enet_out:
1857 clk_disable_unprepare(fep->clk_ipg);
1858failed_clk_ipg:
1859 clk_disable_unprepare(fep->clk_ahb);
1860
1861 return ret;
1862}
1863
c556167f 1864static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1865{
c556167f 1866 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1867 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1868 char mdio_bus_id[MII_BUS_ID_SIZE];
1869 char phy_name[MII_BUS_ID_SIZE + 3];
1870 int phy_id;
43af940c 1871 int dev_id = fep->dev_id;
562d2f8c 1872
418bd0d4
BW		 1873 fep->phy_dev = NULL;
1874
407066f8
UKK		 1875 if (fep->phy_node) {
1876 phy_dev = of_phy_connect(ndev, fep->phy_node,
1877 &fec_enet_adjust_link, 0,
1878 fep->phy_interface);
1879 } else {
1880 /* check for attached phy */
1881 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1882 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1883 continue;
1884 if (fep->mii_bus->phy_map[phy_id] == NULL)
1885 continue;
1886 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1887 continue;
1888 if (dev_id--)
1889 continue;
949bdd20 1890 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
407066f8
UKK		 1891 break;
1892 }
1da177e4 1893
407066f8
UKK		 1894 if (phy_id >= PHY_MAX_ADDR) {
1895 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
949bdd20 1896 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
407066f8
UKK		 1897 phy_id = 0;
1898 }
1899
1900 snprintf(phy_name, sizeof(phy_name),
1901 PHY_ID_FMT, mdio_bus_id, phy_id);
1902 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1903 fep->phy_interface);
6fcc040f
GU		 1904 }
1905
6fcc040f 1906 if (IS_ERR(phy_dev)) {
31b7720c 1907 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1908 return PTR_ERR(phy_dev);
e6b043d5 1909 }
1da177e4 1910
e6b043d5 1911 /* mask with MAC supported features */
6b7e4008 1912 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
230dec61 1913 phy_dev->supported &= PHY_GBIT_FEATURES;
b44592ff 1914 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
d1391930 1915#if !defined(CONFIG_M5272)
baa70a5c 1916 phy_dev->supported |= SUPPORTED_Pause;
d1391930 1917#endif
baa70a5c 1918 }
230dec61
SG		 1919 else
1920 phy_dev->supported &= PHY_BASIC_FEATURES;
1921
e6b043d5 1922 phy_dev->advertising = phy_dev->supported;
1da177e4 1923
e6b043d5
BW		 1924 fep->phy_dev = phy_dev;
1925 fep->link = 0;
1926 fep->full_duplex = 0;
1da177e4 1927
31b7720c
JP		 1928 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1929 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1930 fep->phy_dev->irq);
418bd0d4 1931
e6b043d5 1932 return 0;
1da177e4
LT		 1933}
1934
e6b043d5 1935static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 1936{
b5680e0b 1937 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 1938 struct net_device *ndev = platform_get_drvdata(pdev);
1939 struct fec_enet_private *fep = netdev_priv(ndev);
407066f8 1940 struct device_node *node;
e6b043d5 1941 int err = -ENXIO, i;
6b265293 1942
b5680e0b
SG		 1943 /*
1944 * The dual fec interfaces are not equivalent with enet-mac.
1945 * Here are the differences:
1946 *
1947 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1948 * - fec0 acts as the 1588 time master while fec1 is slave
1949 * - external phys can only be configured by fec0
1950 *
1951 * That is to say fec1 can not work independently. It only works
1952 * when fec0 is working. The reason behind this design is that the
1953 * second interface is added primarily for Switch mode.
1954 *
1955 * Because of the last point above, both phys are attached on fec0
1956 * mdio interface in board design, and need to be configured by
1957 * fec0 mii_bus.
1958 */
6b7e4008 1959 if ((fep->quirks & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
b5680e0b 1960 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 1961 if (mii_cnt && fec0_mii_bus) {
1962 fep->mii_bus = fec0_mii_bus;
1963 mii_cnt++;
1964 return 0;
1965 }
1966 return -ENOENT;
b5680e0b
SG		 1967 }
1968
e6b043d5 1969 fep->mii_timeout = 0;
1da177e4 1970
e6b043d5
BW		 1971 /*
1972 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 1973 *
1974 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1975 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1976 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1977 * document.
e6b043d5 1978 */
98a6eeb8 1979 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
6b7e4008 1980 if (fep->quirks & FEC_QUIRK_ENET_MAC)
230dec61
SG		 1981 fep->phy_speed--;
1982 fep->phy_speed <<= 1;
e6b043d5 1983 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 1984
e6b043d5
BW		 1985 fep->mii_bus = mdiobus_alloc();
1986 if (fep->mii_bus == NULL) {
1987 err = -ENOMEM;
1988 goto err_out;
1da177e4
LT		 1989 }
1990
e6b043d5
BW		 1991 fep->mii_bus->name = "fec_enet_mii_bus";
1992 fep->mii_bus->read = fec_enet_mdio_read;
1993 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 1994 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1995 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 1996 fep->mii_bus->priv = fep;
1997 fep->mii_bus->parent = &pdev->dev;
1998
1999 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2000 if (!fep->mii_bus->irq) {
2001 err = -ENOMEM;
2002 goto err_out_free_mdiobus;
1da177e4
LT		 2003 }
2004
e6b043d5
BW		 2005 for (i = 0; i < PHY_MAX_ADDR; i++)
2006 fep->mii_bus->irq[i] = PHY_POLL;
1da177e4 2007
407066f8
UKK		 2008 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2009 if (node) {
2010 err = of_mdiobus_register(fep->mii_bus, node);
2011 of_node_put(node);
2012 } else {
2013 err = mdiobus_register(fep->mii_bus);
2014 }
2015
2016 if (err)
e6b043d5 2017 goto err_out_free_mdio_irq;
1da177e4 2018
e163cc97
LW		 2019 mii_cnt++;
2020
b5680e0b 2021 /* save fec0 mii_bus */
6b7e4008 2022 if (fep->quirks & FEC_QUIRK_ENET_MAC)
b5680e0b
SG		 2023 fec0_mii_bus = fep->mii_bus;
2024
e6b043d5 2025 return 0;
1da177e4 2026
e6b043d5
BW		 2027err_out_free_mdio_irq:
2028 kfree(fep->mii_bus->irq);
2029err_out_free_mdiobus:
2030 mdiobus_free(fep->mii_bus);
2031err_out:
2032 return err;
1da177e4
LT		 2033}
2034
e6b043d5 2035static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 2036{
e163cc97
LW		 2037 if (--mii_cnt == 0) {
2038 mdiobus_unregister(fep->mii_bus);
2039 kfree(fep->mii_bus->irq);
2040 mdiobus_free(fep->mii_bus);
2041 }
1da177e4
LT		 2042}
2043
c556167f 2044static int fec_enet_get_settings(struct net_device *ndev,
e6b043d5 2045 struct ethtool_cmd *cmd)
1da177e4 2046{
c556167f 2047 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2048 struct phy_device *phydev = fep->phy_dev;
1da177e4 2049
e6b043d5
BW		 2050 if (!phydev)
2051 return -ENODEV;
1da177e4 2052
e6b043d5 2053 return phy_ethtool_gset(phydev, cmd);
1da177e4
LT		 2054}
2055
c556167f 2056static int fec_enet_set_settings(struct net_device *ndev,
e6b043d5 2057 struct ethtool_cmd *cmd)
1da177e4 2058{
c556167f 2059 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2060 struct phy_device *phydev = fep->phy_dev;
1da177e4 2061
e6b043d5
BW		 2062 if (!phydev)
2063 return -ENODEV;
1da177e4 2064
e6b043d5 2065 return phy_ethtool_sset(phydev, cmd);
1da177e4
LT		 2066}
2067
c556167f 2068static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 2069 struct ethtool_drvinfo *info)
1da177e4 2070{
c556167f 2071 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 2072
7826d43f
JP		 2073 strlcpy(info->driver, fep->pdev->dev.driver->name,
2074 sizeof(info->driver));
2075 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2076 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 2077}
2078
5ebae489
FL		 2079static int fec_enet_get_ts_info(struct net_device *ndev,
2080 struct ethtool_ts_info *info)
2081{
2082 struct fec_enet_private *fep = netdev_priv(ndev);
2083
2084 if (fep->bufdesc_ex) {
2085
2086 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2087 SOF_TIMESTAMPING_RX_SOFTWARE |
2088 SOF_TIMESTAMPING_SOFTWARE |
2089 SOF_TIMESTAMPING_TX_HARDWARE |
2090 SOF_TIMESTAMPING_RX_HARDWARE |
2091 SOF_TIMESTAMPING_RAW_HARDWARE;
2092 if (fep->ptp_clock)
2093 info->phc_index = ptp_clock_index(fep->ptp_clock);
2094 else
2095 info->phc_index = -1;
2096
2097 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2098 (1 << HWTSTAMP_TX_ON);
2099
2100 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2101 (1 << HWTSTAMP_FILTER_ALL);
2102 return 0;
2103 } else {
2104 return ethtool_op_get_ts_info(ndev, info);
2105 }
2106}
2107
d1391930
GR		 2108#if !defined(CONFIG_M5272)
2109
baa70a5c
FL		 2110static void fec_enet_get_pauseparam(struct net_device *ndev,
2111 struct ethtool_pauseparam *pause)
2112{
2113 struct fec_enet_private *fep = netdev_priv(ndev);
2114
2115 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2116 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2117 pause->rx_pause = pause->tx_pause;
2118}
2119
2120static int fec_enet_set_pauseparam(struct net_device *ndev,
2121 struct ethtool_pauseparam *pause)
2122{
2123 struct fec_enet_private *fep = netdev_priv(ndev);
2124
0b146ca8
RK		 2125 if (!fep->phy_dev)
2126 return -ENODEV;
2127
baa70a5c
FL		 2128 if (pause->tx_pause != pause->rx_pause) {
2129 netdev_info(ndev,
2130 "hardware only support enable/disable both tx and rx");
2131 return -EINVAL;
2132 }
2133
2134 fep->pause_flag = 0;
2135
2136 /* tx pause must be same as rx pause */
2137 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2138 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2139
2140 if (pause->rx_pause || pause->autoneg) {
2141 fep->phy_dev->supported |= ADVERTISED_Pause;
2142 fep->phy_dev->advertising |= ADVERTISED_Pause;
2143 } else {
2144 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2145 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2146 }
2147
2148 if (pause->autoneg) {
2149 if (netif_running(ndev))
2150 fec_stop(ndev);
2151 phy_start_aneg(fep->phy_dev);
2152 }
dbc64a8e 2153 if (netif_running(ndev)) {
dbc64a8e 2154 napi_disable(&fep->napi);
dbc64a8e 2155 netif_tx_lock_bh(ndev);
ef83337d 2156 fec_restart(ndev);
dbc64a8e 2157 netif_wake_queue(ndev);
6af42d42 2158 netif_tx_unlock_bh(ndev);
dbc64a8e 2159 napi_enable(&fep->napi);
dbc64a8e 2160 }
baa70a5c
FL		 2161
2162 return 0;
2163}
2164
38ae92dc
CH		 2165static const struct fec_stat {
2166 char name[ETH_GSTRING_LEN];
2167 u16 offset;
2168} fec_stats[] = {
2169 /* RMON TX */
2170 { "tx_dropped", RMON_T_DROP },
2171 { "tx_packets", RMON_T_PACKETS },
2172 { "tx_broadcast", RMON_T_BC_PKT },
2173 { "tx_multicast", RMON_T_MC_PKT },
2174 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2175 { "tx_undersize", RMON_T_UNDERSIZE },
2176 { "tx_oversize", RMON_T_OVERSIZE },
2177 { "tx_fragment", RMON_T_FRAG },
2178 { "tx_jabber", RMON_T_JAB },
2179 { "tx_collision", RMON_T_COL },
2180 { "tx_64byte", RMON_T_P64 },
2181 { "tx_65to127byte", RMON_T_P65TO127 },
2182 { "tx_128to255byte", RMON_T_P128TO255 },
2183 { "tx_256to511byte", RMON_T_P256TO511 },
2184 { "tx_512to1023byte", RMON_T_P512TO1023 },
2185 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2186 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2187 { "tx_octets", RMON_T_OCTETS },
2188
2189 /* IEEE TX */
2190 { "IEEE_tx_drop", IEEE_T_DROP },
2191 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2192 { "IEEE_tx_1col", IEEE_T_1COL },
2193 { "IEEE_tx_mcol", IEEE_T_MCOL },
2194 { "IEEE_tx_def", IEEE_T_DEF },
2195 { "IEEE_tx_lcol", IEEE_T_LCOL },
2196 { "IEEE_tx_excol", IEEE_T_EXCOL },
2197 { "IEEE_tx_macerr", IEEE_T_MACERR },
2198 { "IEEE_tx_cserr", IEEE_T_CSERR },
2199 { "IEEE_tx_sqe", IEEE_T_SQE },
2200 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2201 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2202
2203 /* RMON RX */
2204 { "rx_packets", RMON_R_PACKETS },
2205 { "rx_broadcast", RMON_R_BC_PKT },
2206 { "rx_multicast", RMON_R_MC_PKT },
2207 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2208 { "rx_undersize", RMON_R_UNDERSIZE },
2209 { "rx_oversize", RMON_R_OVERSIZE },
2210 { "rx_fragment", RMON_R_FRAG },
2211 { "rx_jabber", RMON_R_JAB },
2212 { "rx_64byte", RMON_R_P64 },
2213 { "rx_65to127byte", RMON_R_P65TO127 },
2214 { "rx_128to255byte", RMON_R_P128TO255 },
2215 { "rx_256to511byte", RMON_R_P256TO511 },
2216 { "rx_512to1023byte", RMON_R_P512TO1023 },
2217 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2218 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2219 { "rx_octets", RMON_R_OCTETS },
2220
2221 /* IEEE RX */
2222 { "IEEE_rx_drop", IEEE_R_DROP },
2223 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2224 { "IEEE_rx_crc", IEEE_R_CRC },
2225 { "IEEE_rx_align", IEEE_R_ALIGN },
2226 { "IEEE_rx_macerr", IEEE_R_MACERR },
2227 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2228 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2229};
2230
2231static void fec_enet_get_ethtool_stats(struct net_device *dev,
2232 struct ethtool_stats *stats, u64 *data)
2233{
2234 struct fec_enet_private *fep = netdev_priv(dev);
2235 int i;
2236
2237 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2238 data[i] = readl(fep->hwp + fec_stats[i].offset);
2239}
2240
2241static void fec_enet_get_strings(struct net_device *netdev,
2242 u32 stringset, u8 *data)
2243{
2244 int i;
2245 switch (stringset) {
2246 case ETH_SS_STATS:
2247 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2248 memcpy(data + i * ETH_GSTRING_LEN,
2249 fec_stats[i].name, ETH_GSTRING_LEN);
2250 break;
2251 }
2252}
2253
2254static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2255{
2256 switch (sset) {
2257 case ETH_SS_STATS:
2258 return ARRAY_SIZE(fec_stats);
2259 default:
2260 return -EOPNOTSUPP;
2261 }
2262}
d1391930 2263#endif /* !defined(CONFIG_M5272) */
38ae92dc 2264
32bc9b46
CH		 2265static int fec_enet_nway_reset(struct net_device *dev)
2266{
2267 struct fec_enet_private *fep = netdev_priv(dev);
2268 struct phy_device *phydev = fep->phy_dev;
2269
2270 if (!phydev)
2271 return -ENODEV;
2272
2273 return genphy_restart_aneg(phydev);
2274}
2275
d851b47b
FD		 2276/* ITR clock source is enet system clock (clk_ahb).
2277 * TCTT unit is cycle_ns * 64 cycle
2278 * So, the ICTT value = X us / (cycle_ns * 64)
2279 */
2280static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2281{
2282 struct fec_enet_private *fep = netdev_priv(ndev);
2283
2284 return us * (fep->itr_clk_rate / 64000) / 1000;
2285}
2286
2287/* Set threshold for interrupt coalescing */
2288static void fec_enet_itr_coal_set(struct net_device *ndev)
2289{
2290 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2291 int rx_itr, tx_itr;
2292
6b7e4008 2293 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2294 return;
2295
2296 /* Must be greater than zero to avoid unpredictable behavior */
2297 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2298 !fep->tx_time_itr || !fep->tx_pkts_itr)
2299 return;
2300
2301 /* Select enet system clock as Interrupt Coalescing
2302 * timer Clock Source
2303 */
2304 rx_itr = FEC_ITR_CLK_SEL;
2305 tx_itr = FEC_ITR_CLK_SEL;
2306
2307 /* set ICFT and ICTT */
2308 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2309 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2310 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2311 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2312
2313 rx_itr |= FEC_ITR_EN;
2314 tx_itr |= FEC_ITR_EN;
2315
2316 writel(tx_itr, fep->hwp + FEC_TXIC0);
2317 writel(rx_itr, fep->hwp + FEC_RXIC0);
2318 writel(tx_itr, fep->hwp + FEC_TXIC1);
2319 writel(rx_itr, fep->hwp + FEC_RXIC1);
2320 writel(tx_itr, fep->hwp + FEC_TXIC2);
2321 writel(rx_itr, fep->hwp + FEC_RXIC2);
2322}
2323
2324static int
2325fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2326{
2327 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b 2328
6b7e4008 2329 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2330 return -EOPNOTSUPP;
2331
2332 ec->rx_coalesce_usecs = fep->rx_time_itr;
2333 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2334
2335 ec->tx_coalesce_usecs = fep->tx_time_itr;
2336 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2337
2338 return 0;
2339}
2340
2341static int
2342fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2343{
2344 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2345 unsigned int cycle;
2346
6b7e4008 2347 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2348 return -EOPNOTSUPP;
2349
2350 if (ec->rx_max_coalesced_frames > 255) {
2351 pr_err("Rx coalesced frames exceed hardware limiation");
2352 return -EINVAL;
2353 }
2354
2355 if (ec->tx_max_coalesced_frames > 255) {
2356 pr_err("Tx coalesced frame exceed hardware limiation");
2357 return -EINVAL;
2358 }
2359
2360 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2361 if (cycle > 0xFFFF) {
2362 pr_err("Rx coalesed usec exceeed hardware limiation");
2363 return -EINVAL;
2364 }
2365
2366 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2367 if (cycle > 0xFFFF) {
2368 pr_err("Rx coalesed usec exceeed hardware limiation");
2369 return -EINVAL;
2370 }
2371
2372 fep->rx_time_itr = ec->rx_coalesce_usecs;
2373 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2374
2375 fep->tx_time_itr = ec->tx_coalesce_usecs;
2376 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2377
2378 fec_enet_itr_coal_set(ndev);
2379
2380 return 0;
2381}
2382
2383static void fec_enet_itr_coal_init(struct net_device *ndev)
2384{
2385 struct ethtool_coalesce ec;
2386
2387 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2388 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2389
2390 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2391 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2392
2393 fec_enet_set_coalesce(ndev, &ec);
2394}
2395
1b7bde6d
NA		 2396static int fec_enet_get_tunable(struct net_device *netdev,
2397 const struct ethtool_tunable *tuna,
2398 void *data)
2399{
2400 struct fec_enet_private *fep = netdev_priv(netdev);
2401 int ret = 0;
2402
2403 switch (tuna->id) {
2404 case ETHTOOL_RX_COPYBREAK:
2405 *(u32 *)data = fep->rx_copybreak;
2406 break;
2407 default:
2408 ret = -EINVAL;
2409 break;
2410 }
2411
2412 return ret;
2413}
2414
2415static int fec_enet_set_tunable(struct net_device *netdev,
2416 const struct ethtool_tunable *tuna,
2417 const void *data)
2418{
2419 struct fec_enet_private *fep = netdev_priv(netdev);
2420 int ret = 0;
2421
2422 switch (tuna->id) {
2423 case ETHTOOL_RX_COPYBREAK:
2424 fep->rx_copybreak = *(u32 *)data;
2425 break;
2426 default:
2427 ret = -EINVAL;
2428 break;
2429 }
2430
2431 return ret;
2432}
2433
9b07be4b 2434static const struct ethtool_ops fec_enet_ethtool_ops = {
e6b043d5
BW		 2435 .get_settings = fec_enet_get_settings,
2436 .set_settings = fec_enet_set_settings,
2437 .get_drvinfo = fec_enet_get_drvinfo,
32bc9b46 2438 .nway_reset = fec_enet_nway_reset,
c1d7c48f 2439 .get_link = ethtool_op_get_link,
d851b47b
FD		 2440 .get_coalesce = fec_enet_get_coalesce,
2441 .set_coalesce = fec_enet_set_coalesce,
38ae92dc 2442#ifndef CONFIG_M5272
c1d7c48f
RK		 2443 .get_pauseparam = fec_enet_get_pauseparam,
2444 .set_pauseparam = fec_enet_set_pauseparam,
38ae92dc 2445 .get_strings = fec_enet_get_strings,
c1d7c48f 2446 .get_ethtool_stats = fec_enet_get_ethtool_stats,
38ae92dc
CH		 2447 .get_sset_count = fec_enet_get_sset_count,
2448#endif
c1d7c48f 2449 .get_ts_info = fec_enet_get_ts_info,
1b7bde6d
NA		 2450 .get_tunable = fec_enet_get_tunable,
2451 .set_tunable = fec_enet_set_tunable,
e6b043d5 2452};
1da177e4 2453
c556167f 2454static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2455{
c556167f 2456 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2457 struct phy_device *phydev = fep->phy_dev;
1da177e4 2458
c556167f 2459 if (!netif_running(ndev))
e6b043d5 2460 return -EINVAL;
1da177e4 2461
e6b043d5
BW		 2462 if (!phydev)
2463 return -ENODEV;
2464
1d5244d0
BH		 2465 if (fep->bufdesc_ex) {
2466 if (cmd == SIOCSHWTSTAMP)
2467 return fec_ptp_set(ndev, rq);
2468 if (cmd == SIOCGHWTSTAMP)
2469 return fec_ptp_get(ndev, rq);
2470 }
ff43da86 2471
28b04113 2472 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2473}
2474
c556167f 2475static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2476{
c556167f 2477 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2478 unsigned int i;
f0b3fbea
SH		 2479 struct sk_buff *skb;
2480 struct bufdesc *bdp;
4d494cdc
FD		 2481 struct fec_enet_priv_tx_q *txq;
2482 struct fec_enet_priv_rx_q *rxq;
59d0f746
FL		 2483 unsigned int q;
2484
2485 for (q = 0; q < fep->num_rx_queues; q++) {
2486 rxq = fep->rx_queue[q];
2487 bdp = rxq->rx_bd_base;
2488 for (i = 0; i < rxq->rx_ring_size; i++) {
2489 skb = rxq->rx_skbuff[i];
2490 rxq->rx_skbuff[i] = NULL;
2491 if (skb) {
2492 dma_unmap_single(&fep->pdev->dev,
2493 bdp->cbd_bufaddr,
b64bf4b7 2494 FEC_ENET_RX_FRSIZE - fep->rx_align,
59d0f746
FL		 2495 DMA_FROM_DEVICE);
2496 dev_kfree_skb(skb);
2497 }
2498 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2499 }
2500 }
4d494cdc 2501
59d0f746
FL		 2502 for (q = 0; q < fep->num_tx_queues; q++) {
2503 txq = fep->tx_queue[q];
2504 bdp = txq->tx_bd_base;
2505 for (i = 0; i < txq->tx_ring_size; i++) {
2506 kfree(txq->tx_bounce[i]);
2507 txq->tx_bounce[i] = NULL;
2508 skb = txq->tx_skbuff[i];
2509 txq->tx_skbuff[i] = NULL;
f0b3fbea 2510 dev_kfree_skb(skb);
730ee360 2511 }
f0b3fbea 2512 }
59d0f746 2513}
f0b3fbea 2514
59d0f746
FL		 2515static void fec_enet_free_queue(struct net_device *ndev)
2516{
2517 struct fec_enet_private *fep = netdev_priv(ndev);
2518 int i;
2519 struct fec_enet_priv_tx_q *txq;
2520
2521 for (i = 0; i < fep->num_tx_queues; i++)
2522 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2523 txq = fep->tx_queue[i];
2524 dma_free_coherent(NULL,
2525 txq->tx_ring_size * TSO_HEADER_SIZE,
2526 txq->tso_hdrs,
2527 txq->tso_hdrs_dma);
2528 }
2529
2530 for (i = 0; i < fep->num_rx_queues; i++)
2531 if (fep->rx_queue[i])
2532 kfree(fep->rx_queue[i]);
2533
2534 for (i = 0; i < fep->num_tx_queues; i++)
2535 if (fep->tx_queue[i])
2536 kfree(fep->tx_queue[i]);
2537}
2538
2539static int fec_enet_alloc_queue(struct net_device *ndev)
2540{
2541 struct fec_enet_private *fep = netdev_priv(ndev);
2542 int i;
2543 int ret = 0;
2544 struct fec_enet_priv_tx_q *txq;
2545
2546 for (i = 0; i < fep->num_tx_queues; i++) {
2547 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2548 if (!txq) {
2549 ret = -ENOMEM;
2550 goto alloc_failed;
2551 }
2552
2553 fep->tx_queue[i] = txq;
2554 txq->tx_ring_size = TX_RING_SIZE;
2555 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2556
2557 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2558 txq->tx_wake_threshold =
2559 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2560
2561 txq->tso_hdrs = dma_alloc_coherent(NULL,
2562 txq->tx_ring_size * TSO_HEADER_SIZE,
2563 &txq->tso_hdrs_dma,
2564 GFP_KERNEL);
2565 if (!txq->tso_hdrs) {
2566 ret = -ENOMEM;
2567 goto alloc_failed;
2568 }
8b7c9efa 2569 }
59d0f746
FL		 2570
2571 for (i = 0; i < fep->num_rx_queues; i++) {
2572 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2573 GFP_KERNEL);
2574 if (!fep->rx_queue[i]) {
2575 ret = -ENOMEM;
2576 goto alloc_failed;
2577 }
2578
2579 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2580 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2581 }
2582 return ret;
2583
2584alloc_failed:
2585 fec_enet_free_queue(ndev);
2586 return ret;
f0b3fbea
SH		 2587}
2588
59d0f746
FL		 2589static int
2590fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
f0b3fbea 2591{
c556167f 2592 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2593 unsigned int i;
f0b3fbea
SH		 2594 struct sk_buff *skb;
2595 struct bufdesc *bdp;
4d494cdc 2596 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 2597
59d0f746 2598 rxq = fep->rx_queue[queue];
4d494cdc
FD		 2599 bdp = rxq->rx_bd_base;
2600 for (i = 0; i < rxq->rx_ring_size; i++) {
b72061a3 2601 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2602 if (!skb)
2603 goto err_alloc;
f0b3fbea 2604
1b7bde6d 2605 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
730ee360 2606 dev_kfree_skb(skb);
ffdce2cc 2607 goto err_alloc;
d842a31f 2608 }
730ee360 2609
4d494cdc 2610 rxq->rx_skbuff[i] = skb;
f0b3fbea 2611 bdp->cbd_sc = BD_ENET_RX_EMPTY;
ff43da86
FL		 2612
2613 if (fep->bufdesc_ex) {
2614 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2615 ebdp->cbd_esc = BD_ENET_RX_INT;
2616 }
2617
59d0f746 2618 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
f0b3fbea
SH		 2619 }
2620
2621 /* Set the last buffer to wrap. */
59d0f746 2622 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
f0b3fbea 2623 bdp->cbd_sc |= BD_SC_WRAP;
59d0f746 2624 return 0;
f0b3fbea 2625
59d0f746
FL		 2626 err_alloc:
2627 fec_enet_free_buffers(ndev);
2628 return -ENOMEM;
2629}
2630
2631static int
2632fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2633{
2634 struct fec_enet_private *fep = netdev_priv(ndev);
2635 unsigned int i;
2636 struct bufdesc *bdp;
2637 struct fec_enet_priv_tx_q *txq;
2638
2639 txq = fep->tx_queue[queue];
4d494cdc
FD		 2640 bdp = txq->tx_bd_base;
2641 for (i = 0; i < txq->tx_ring_size; i++) {
2642 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2643 if (!txq->tx_bounce[i])
ffdce2cc 2644 goto err_alloc;
f0b3fbea
SH		 2645
2646 bdp->cbd_sc = 0;
2647 bdp->cbd_bufaddr = 0;
6605b730 2648
ff43da86
FL		 2649 if (fep->bufdesc_ex) {
2650 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
96d2222b 2651 ebdp->cbd_esc = BD_ENET_TX_INT;
ff43da86
FL		 2652 }
2653
59d0f746 2654 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
f0b3fbea
SH		 2655 }
2656
2657 /* Set the last buffer to wrap. */
59d0f746 2658 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
f0b3fbea
SH		 2659 bdp->cbd_sc |= BD_SC_WRAP;
2660
2661 return 0;
ffdce2cc
RK		 2662
2663 err_alloc:
2664 fec_enet_free_buffers(ndev);
2665 return -ENOMEM;
f0b3fbea
SH		 2666}
2667
59d0f746
FL		 2668static int fec_enet_alloc_buffers(struct net_device *ndev)
2669{
2670 struct fec_enet_private *fep = netdev_priv(ndev);
2671 unsigned int i;
2672
2673 for (i = 0; i < fep->num_rx_queues; i++)
2674 if (fec_enet_alloc_rxq_buffers(ndev, i))
2675 return -ENOMEM;
2676
2677 for (i = 0; i < fep->num_tx_queues; i++)
2678 if (fec_enet_alloc_txq_buffers(ndev, i))
2679 return -ENOMEM;
2680 return 0;
2681}
2682
1da177e4 2683static int
c556167f 2684fec_enet_open(struct net_device *ndev)
1da177e4 2685{
c556167f 2686 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2687 int ret;
1da177e4 2688
5bbde4d2 2689 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2690 ret = fec_enet_clk_enable(ndev, true);
2691 if (ret)
2692 return ret;
2693
1da177e4
LT		 2694 /* I should reset the ring buffers here, but I don't yet know
2695 * a simple way to do that.
2696 */
1da177e4 2697
c556167f 2698 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea 2699 if (ret)
681d2421 2700 goto err_enet_alloc;
f0b3fbea 2701
418bd0d4 2702 /* Probe and connect to PHY when open the interface */
c556167f 2703 ret = fec_enet_mii_probe(ndev);
681d2421
FE		 2704 if (ret)
2705 goto err_enet_mii_probe;
ce5eaf02 2706
ef83337d 2707 fec_restart(ndev);
ce5eaf02 2708 napi_enable(&fep->napi);
e6b043d5 2709 phy_start(fep->phy_dev);
4d494cdc
FD		 2710 netif_tx_start_all_queues(ndev);
2711
22f6b860 2712 return 0;
681d2421
FE		 2713
2714err_enet_mii_probe:
2715 fec_enet_free_buffers(ndev);
2716err_enet_alloc:
2717 fec_enet_clk_enable(ndev, false);
2718 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2719 return ret;
1da177e4
LT		 2720}
2721
2722static int
c556167f 2723fec_enet_close(struct net_device *ndev)
1da177e4 2724{
c556167f 2725 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2726
d76cfae9
RK		 2727 phy_stop(fep->phy_dev);
2728
31a6de34
RK		 2729 if (netif_device_present(ndev)) {
2730 napi_disable(&fep->napi);
2731 netif_tx_disable(ndev);
8bbbd3c1 2732 fec_stop(ndev);
31a6de34 2733 }
1da177e4 2734
635cf17c 2735 phy_disconnect(fep->phy_dev);
0b146ca8 2736 fep->phy_dev = NULL;
418bd0d4 2737
e8fcfcd5 2738 fec_enet_clk_enable(ndev, false);
5bbde4d2 2739 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
db8880bc 2740 fec_enet_free_buffers(ndev);
f0b3fbea 2741
1da177e4
LT		 2742 return 0;
2743}
2744
1da177e4
LT		 2745/* Set or clear the multicast filter for this adaptor.
2746 * Skeleton taken from sunlance driver.
2747 * The CPM Ethernet implementation allows Multicast as well as individual
2748 * MAC address filtering. Some of the drivers check to make sure it is
2749 * a group multicast address, and discard those that are not. I guess I
2750 * will do the same for now, but just remove the test if you want
2751 * individual filtering as well (do the upper net layers want or support
2752 * this kind of feature?).
2753 */
2754
2755#define HASH_BITS 6 /* #bits in hash */
2756#define CRC32_POLY 0xEDB88320
2757
c556167f 2758static void set_multicast_list(struct net_device *ndev)
1da177e4 2759{
c556167f 2760 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 2761 struct netdev_hw_addr *ha;
48e2f183 2762 unsigned int i, bit, data, crc, tmp;
1da177e4
LT		 2763 unsigned char hash;
2764
c556167f 2765 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 2766 tmp = readl(fep->hwp + FEC_R_CNTRL);
2767 tmp |= 0x8;
2768 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 2769 return;
2770 }
1da177e4 2771
4e831836
SH		 2772 tmp = readl(fep->hwp + FEC_R_CNTRL);
2773 tmp &= ~0x8;
2774 writel(tmp, fep->hwp + FEC_R_CNTRL);
2775
c556167f 2776 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 2777 /* Catch all multicast addresses, so set the
2778 * filter to all 1's
2779 */
2780 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2781 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2782
2783 return;
2784 }
2785
2786 /* Clear filter and add the addresses in hash register
2787 */
2788 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2789 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2790
c556167f 2791 netdev_for_each_mc_addr(ha, ndev) {
4e831836
SH		 2792 /* calculate crc32 value of mac address */
2793 crc = 0xffffffff;
2794
c556167f 2795 for (i = 0; i < ndev->addr_len; i++) {
22bedad3 2796 data = ha->addr[i];
4e831836
SH		 2797 for (bit = 0; bit < 8; bit++, data >>= 1) {
2798 crc = (crc >> 1) ^
2799 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1da177e4
LT		 2800 }
2801 }
4e831836
SH		 2802
2803 /* only upper 6 bits (HASH_BITS) are used
2804 * which point to specific bit in he hash registers
2805 */
2806 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2807
2808 if (hash > 31) {
2809 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2810 tmp |= 1 << (hash - 32);
2811 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2812 } else {
2813 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2814 tmp |= 1 << hash;
2815 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2816 }
1da177e4
LT		 2817 }
2818}
2819
22f6b860 2820/* Set a MAC change in hardware. */
009fda83 2821static int
c556167f 2822fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 2823{
c556167f 2824 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 2825 struct sockaddr *addr = p;
2826
44934fac
LS		 2827 if (addr) {
2828 if (!is_valid_ether_addr(addr->sa_data))
2829 return -EADDRNOTAVAIL;
2830 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2831 }
1da177e4 2832
c556167f
UKK		 2833 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2834 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 2835 fep->hwp + FEC_ADDR_LOW);
c556167f 2836 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 2837 fep->hwp + FEC_ADDR_HIGH);
009fda83 2838 return 0;
1da177e4
LT		 2839}
2840
7f5c6add 2841#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 2842/**
2843 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 2844 * @dev: The FEC network adapter
2845 *
2846 * Polled functionality used by netconsole and others in non interrupt mode
2847 *
2848 */
47a5247f 2849static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 2850{
2851 int i;
2852 struct fec_enet_private *fep = netdev_priv(dev);
2853
2854 for (i = 0; i < FEC_IRQ_NUM; i++) {
2855 if (fep->irq[i] > 0) {
2856 disable_irq(fep->irq[i]);
2857 fec_enet_interrupt(fep->irq[i], dev);
2858 enable_irq(fep->irq[i]);
2859 }
2860 }
2861}
2862#endif
2863
8506fa1d 2864#define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
5bc26726 2865static inline void fec_enet_set_netdev_features(struct net_device *netdev,
4c09eed9
JB		 2866 netdev_features_t features)
2867{
2868 struct fec_enet_private *fep = netdev_priv(netdev);
2869 netdev_features_t changed = features ^ netdev->features;
2870
2871 netdev->features = features;
2872
2873 /* Receive checksum has been changed */
2874 if (changed & NETIF_F_RXCSUM) {
2875 if (features & NETIF_F_RXCSUM)
2876 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2877 else
2878 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
8506fa1d 2879 }
5bc26726
NA		 2880}
2881
2882static int fec_set_features(struct net_device *netdev,
2883 netdev_features_t features)
2884{
2885 struct fec_enet_private *fep = netdev_priv(netdev);
2886 netdev_features_t changed = features ^ netdev->features;
4c09eed9 2887
8506fa1d 2888 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
5bc26726
NA		 2889 napi_disable(&fep->napi);
2890 netif_tx_lock_bh(netdev);
2891 fec_stop(netdev);
2892 fec_enet_set_netdev_features(netdev, features);
ef83337d 2893 fec_restart(netdev);
4d494cdc 2894 netif_tx_wake_all_queues(netdev);
8506fa1d
RK		 2895 netif_tx_unlock_bh(netdev);
2896 napi_enable(&fep->napi);
5bc26726
NA		 2897 } else {
2898 fec_enet_set_netdev_features(netdev, features);
4c09eed9
JB		 2899 }
2900
2901 return 0;
2902}
2903
009fda83
SH		 2904static const struct net_device_ops fec_netdev_ops = {
2905 .ndo_open = fec_enet_open,
2906 .ndo_stop = fec_enet_close,
2907 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 2908 .ndo_set_rx_mode = set_multicast_list,
635ecaa7 2909 .ndo_change_mtu = eth_change_mtu,
009fda83
SH		 2910 .ndo_validate_addr = eth_validate_addr,
2911 .ndo_tx_timeout = fec_timeout,
2912 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 2913 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 2914#ifdef CONFIG_NET_POLL_CONTROLLER
2915 .ndo_poll_controller = fec_poll_controller,
2916#endif
4c09eed9 2917 .ndo_set_features = fec_set_features,
009fda83
SH		 2918};
2919
1da177e4
LT		 2920 /*
2921 * XXX: We need to clean up on failure exits here.
ead73183 2922 *
1da177e4 2923 */
c556167f 2924static int fec_enet_init(struct net_device *ndev)
1da177e4 2925{
c556167f 2926 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 2927 struct fec_enet_priv_tx_q *txq;
2928 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 2929 struct bufdesc *cbd_base;
4d494cdc 2930 dma_addr_t bd_dma;
55d0218a 2931 int bd_size;
59d0f746 2932 unsigned int i;
55d0218a 2933
41ef84ce
FD		 2934#if defined(CONFIG_ARM)
2935 fep->rx_align = 0xf;
2936 fep->tx_align = 0xf;
2937#else
2938 fep->rx_align = 0x3;
2939 fep->tx_align = 0x3;
2940#endif
2941
59d0f746 2942 fec_enet_alloc_queue(ndev);
79f33912 2943
55d0218a
NA		 2944 if (fep->bufdesc_ex)
2945 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2946 else
2947 fep->bufdesc_size = sizeof(struct bufdesc);
4d494cdc 2948 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
55d0218a 2949 fep->bufdesc_size;
1da177e4 2950
8d4dd5cf 2951 /* Allocate memory for buffer descriptors. */
4d494cdc 2952 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
d0320f75 2953 GFP_KERNEL);
4d494cdc 2954 if (!cbd_base) {
79f33912
NA		 2955 return -ENOMEM;
2956 }
2957
4d494cdc 2958 memset(cbd_base, 0, bd_size);
1da177e4 2959
49da97dc 2960 /* Get the Ethernet address */
c556167f 2961 fec_get_mac(ndev);
44934fac
LS		 2962 /* make sure MAC we just acquired is programmed into the hw */
2963 fec_set_mac_address(ndev, NULL);
1da177e4 2964
8d4dd5cf 2965 /* Set receive and transmit descriptor base. */
59d0f746
FL		 2966 for (i = 0; i < fep->num_rx_queues; i++) {
2967 rxq = fep->rx_queue[i];
2968 rxq->index = i;
2969 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
2970 rxq->bd_dma = bd_dma;
2971 if (fep->bufdesc_ex) {
2972 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
2973 cbd_base = (struct bufdesc *)
2974 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
2975 } else {
2976 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
2977 cbd_base += rxq->rx_ring_size;
2978 }
2979 }
2980
2981 for (i = 0; i < fep->num_tx_queues; i++) {
2982 txq = fep->tx_queue[i];
2983 txq->index = i;
2984 txq->tx_bd_base = (struct bufdesc *)cbd_base;
2985 txq->bd_dma = bd_dma;
2986 if (fep->bufdesc_ex) {
2987 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
2988 cbd_base = (struct bufdesc *)
2989 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
2990 } else {
2991 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
2992 cbd_base += txq->tx_ring_size;
2993 }
2994 }
4d494cdc 2995
1da177e4 2996
22f6b860 2997 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 2998 ndev->watchdog_timeo = TX_TIMEOUT;
2999 ndev->netdev_ops = &fec_netdev_ops;
3000 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 3001
dc975382 3002 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 3003 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 3004
6b7e4008 3005 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 3006 /* enable hw VLAN support */
3007 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 3008
6b7e4008 3009 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 3010 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3011
48496255
SG		 3012 /* enable hw accelerator */
3013 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 3014 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 3015 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3016 }
4c09eed9 3017
6b7e4008 3018 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
41ef84ce
FD		 3019 fep->tx_align = 0;
3020 fep->rx_align = 0x3f;
3021 }
3022
09d1e541
NA		 3023 ndev->hw_features = ndev->features;
3024
ef83337d 3025 fec_restart(ndev);
1da177e4 3026
1da177e4
LT		 3027 return 0;
3028}
3029
ca2cc333 3030#ifdef CONFIG_OF
33897cc8 3031static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3032{
3033 int err, phy_reset;
a3caad0a 3034 int msec = 1;
ca2cc333
SG		 3035 struct device_node *np = pdev->dev.of_node;
3036
3037 if (!np)
a9b2c8ef 3038 return;
ca2cc333 3039
a3caad0a
SG		 3040 of_property_read_u32(np, "phy-reset-duration", &msec);
3041 /* A sane reset duration should not be longer than 1s */
3042 if (msec > 1000)
3043 msec = 1;
3044
ca2cc333 3045 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
07dcf8e9
FE		 3046 if (!gpio_is_valid(phy_reset))
3047 return;
3048
119fc007
SG		 3049 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3050 GPIOF_OUT_INIT_LOW, "phy-reset");
ca2cc333 3051 if (err) {
07dcf8e9 3052 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
a9b2c8ef 3053 return;
ca2cc333 3054 }
a3caad0a 3055 msleep(msec);
ca2cc333 3056 gpio_set_value(phy_reset, 1);
ca2cc333
SG		 3057}
3058#else /* CONFIG_OF */
0c7768a0 3059static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3060{
3061 /*
3062 * In case of platform probe, the reset has been done
3063 * by machine code.
3064 */
ca2cc333
SG		 3065}
3066#endif /* CONFIG_OF */
3067
9fc095f1
FD		 3068static void
3069fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3070{
3071 struct device_node *np = pdev->dev.of_node;
3072 int err;
3073
3074 *num_tx = *num_rx = 1;
3075
3076 if (!np || !of_device_is_available(np))
3077 return;
3078
3079 /* parse the num of tx and rx queues */
3080 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
b7bd75cf 3081 if (err)
9fc095f1 3082 *num_tx = 1;
b7bd75cf
FL		 3083
3084 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3085 if (err)
9fc095f1 3086 *num_rx = 1;
9fc095f1
FD		 3087
3088 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
b7bd75cf
FL		 3089 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3090 *num_tx);
9fc095f1
FD		 3091 *num_tx = 1;
3092 return;
3093 }
3094
3095 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
b7bd75cf
FL		 3096 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3097 *num_rx);
9fc095f1
FD		 3098 *num_rx = 1;
3099 return;
3100 }
3101
3102}
3103
33897cc8 3104static int
ead73183
SH		 3105fec_probe(struct platform_device *pdev)
3106{
3107 struct fec_enet_private *fep;
5eb32bd0 3108 struct fec_platform_data *pdata;
ead73183
SH		 3109 struct net_device *ndev;
3110 int i, irq, ret = 0;
3111 struct resource *r;
ca2cc333 3112 const struct of_device_id *of_id;
43af940c 3113 static int dev_id;
407066f8 3114 struct device_node *np = pdev->dev.of_node, *phy_node;
b7bd75cf
FL		 3115 int num_tx_qs;
3116 int num_rx_qs;
ca2cc333 3117
9fc095f1
FD		 3118 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3119
ead73183 3120 /* Init network device */
9fc095f1
FD		 3121 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3122 num_tx_qs, num_rx_qs);
83e519b6
FE		 3123 if (!ndev)
3124 return -ENOMEM;
ead73183
SH		 3125
3126 SET_NETDEV_DEV(ndev, &pdev->dev);
3127
3128 /* setup board info structure */
3129 fep = netdev_priv(ndev);
ead73183 3130
6b7e4008
LW		 3131 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3132 if (of_id)
3133 pdev->id_entry = of_id->data;
3134 fep->quirks = pdev->id_entry->driver_data;
3135
9fc095f1
FD		 3136 fep->num_rx_queues = num_rx_qs;
3137 fep->num_tx_queues = num_tx_qs;
3138
d1391930 3139#if !defined(CONFIG_M5272)
baa70a5c 3140 /* default enable pause frame auto negotiation */
6b7e4008 3141 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
baa70a5c 3142 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 3143#endif
baa70a5c 3144
5bbde4d2
NA		 3145 /* Select default pin state */
3146 pinctrl_pm_select_default_state(&pdev->dev);
3147
399db75b 3148 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941e173a
TB		 3149 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3150 if (IS_ERR(fep->hwp)) {
3151 ret = PTR_ERR(fep->hwp);
3152 goto failed_ioremap;
3153 }
3154
e6b043d5 3155 fep->pdev = pdev;
43af940c 3156 fep->dev_id = dev_id++;
ead73183 3157
ead73183
SH		 3158 platform_set_drvdata(pdev, ndev);
3159
407066f8
UKK		 3160 phy_node = of_parse_phandle(np, "phy-handle", 0);
3161 if (!phy_node && of_phy_is_fixed_link(np)) {
3162 ret = of_phy_register_fixed_link(np);
3163 if (ret < 0) {
3164 dev_err(&pdev->dev,
3165 "broken fixed-link specification\n");
3166 goto failed_phy;
3167 }
3168 phy_node = of_node_get(np);
3169 }
3170 fep->phy_node = phy_node;
3171
6c5f7808 3172 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 3173 if (ret < 0) {
94660ba0 3174 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 3175 if (pdata)
3176 fep->phy_interface = pdata->phy;
3177 else
3178 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3179 } else {
3180 fep->phy_interface = ret;
3181 }
3182
f4d40de3
SH		 3183 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3184 if (IS_ERR(fep->clk_ipg)) {
3185 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 3186 goto failed_clk;
3187 }
f4d40de3
SH		 3188
3189 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3190 if (IS_ERR(fep->clk_ahb)) {
3191 ret = PTR_ERR(fep->clk_ahb);
3192 goto failed_clk;
3193 }
3194
d851b47b
FD		 3195 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3196
daa7d392
WS		 3197 /* enet_out is optional, depends on board */
3198 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3199 if (IS_ERR(fep->clk_enet_out))
3200 fep->clk_enet_out = NULL;
3201
91c0d987
NA		 3202 fep->ptp_clk_on = false;
3203 mutex_init(&fep->ptp_clk_mutex);
9b5330ed
FD		 3204
3205 /* clk_ref is optional, depends on board */
3206 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3207 if (IS_ERR(fep->clk_ref))
3208 fep->clk_ref = NULL;
3209
6b7e4008 3210 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730
FL		 3211 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3212 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 3213 fep->clk_ptp = NULL;
217b5844 3214 fep->bufdesc_ex = false;
6605b730 3215 }
6605b730 3216
e8fcfcd5 3217 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 3218 if (ret)
3219 goto failed_clk;
3220
f4e9f3d2
FE		 3221 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3222 if (!IS_ERR(fep->reg_phy)) {
3223 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 3224 if (ret) {
3225 dev_err(&pdev->dev,
3226 "Failed to enable phy regulator: %d\n", ret);
3227 goto failed_regulator;
3228 }
f6a4d607
FE		 3229 } else {
3230 fep->reg_phy = NULL;
5fa9c0fe
SG		 3231 }
3232
2ca9b2aa
SG		 3233 fec_reset_phy(pdev);
3234
e2f8d555 3235 if (fep->bufdesc_ex)
ca162a82 3236 fec_ptp_init(pdev);
e2f8d555
FE		 3237
3238 ret = fec_enet_init(ndev);
3239 if (ret)
3240 goto failed_init;
3241
3242 for (i = 0; i < FEC_IRQ_NUM; i++) {
3243 irq = platform_get_irq(pdev, i);
3244 if (irq < 0) {
3245 if (i)
3246 break;
3247 ret = irq;
3248 goto failed_irq;
3249 }
0d9b2ab1 3250 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 3251 0, pdev->name, ndev);
0d9b2ab1 3252 if (ret)
e2f8d555 3253 goto failed_irq;
e2f8d555
FE		 3254 }
3255
b4d39b53 3256 init_completion(&fep->mdio_done);
e6b043d5
BW		 3257 ret = fec_enet_mii_init(pdev);
3258 if (ret)
3259 goto failed_mii_init;
3260
03c698c9
OS		 3261 /* Carrier starts down, phylib will bring it up */
3262 netif_carrier_off(ndev);
e8fcfcd5 3263 fec_enet_clk_enable(ndev, false);
5bbde4d2 3264 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 3265
ead73183
SH		 3266 ret = register_netdev(ndev);
3267 if (ret)
3268 goto failed_register;
3269
eb1d0640
FE		 3270 if (fep->bufdesc_ex && fep->ptp_clock)
3271 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3272
1b7bde6d 3273 fep->rx_copybreak = COPYBREAK_DEFAULT;
36cdc743 3274 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
ead73183
SH		 3275 return 0;
3276
3277failed_register:
e6b043d5
BW		 3278 fec_enet_mii_remove(fep);
3279failed_mii_init:
7a2bbd8d 3280failed_irq:
7a2bbd8d 3281failed_init:
f6a4d607
FE		 3282 if (fep->reg_phy)
3283 regulator_disable(fep->reg_phy);
5fa9c0fe 3284failed_regulator:
e8fcfcd5 3285 fec_enet_clk_enable(ndev, false);
ead73183 3286failed_clk:
407066f8
UKK		 3287failed_phy:
3288 of_node_put(phy_node);
ead73183
SH		 3289failed_ioremap:
3290 free_netdev(ndev);
3291
3292 return ret;
3293}
3294
33897cc8 3295static int
ead73183
SH		 3296fec_drv_remove(struct platform_device *pdev)
3297{
3298 struct net_device *ndev = platform_get_drvdata(pdev);
3299 struct fec_enet_private *fep = netdev_priv(ndev);
3300
91c0d987 3301 cancel_delayed_work_sync(&fep->time_keep);
36cdc743 3302 cancel_work_sync(&fep->tx_timeout_work);
e163cc97 3303 unregister_netdev(ndev);
e6b043d5 3304 fec_enet_mii_remove(fep);
f6a4d607
FE		 3305 if (fep->reg_phy)
3306 regulator_disable(fep->reg_phy);
6605b730
FL		 3307 if (fep->ptp_clock)
3308 ptp_clock_unregister(fep->ptp_clock);
e8fcfcd5 3309 fec_enet_clk_enable(ndev, false);
407066f8 3310 of_node_put(fep->phy_node);
ead73183 3311 free_netdev(ndev);
28e2188e 3312
ead73183
SH		 3313 return 0;
3314}
3315
dd66d386 3316static int __maybe_unused fec_suspend(struct device *dev)
ead73183 3317{
87cad5c3 3318 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3319 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 3320
da1774e5 3321 rtnl_lock();
04e5216d 3322 if (netif_running(ndev)) {
d76cfae9 3323 phy_stop(fep->phy_dev);
31a6de34
RK		 3324 napi_disable(&fep->napi);
3325 netif_tx_lock_bh(ndev);
04e5216d 3326 netif_device_detach(ndev);
31a6de34
RK		 3327 netif_tx_unlock_bh(ndev);
3328 fec_stop(ndev);
f4c4a4e0
NA		 3329 fec_enet_clk_enable(ndev, false);
3330 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
ead73183 3331 }
da1774e5
RK		 3332 rtnl_unlock();
3333
238f7bc7
FE		 3334 if (fep->reg_phy)
3335 regulator_disable(fep->reg_phy);
3336
ead73183
SH		 3337 return 0;
3338}
3339
dd66d386 3340static int __maybe_unused fec_resume(struct device *dev)
ead73183 3341{
87cad5c3 3342 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3343 struct fec_enet_private *fep = netdev_priv(ndev);
238f7bc7
FE		 3344 int ret;
3345
3346 if (fep->reg_phy) {
3347 ret = regulator_enable(fep->reg_phy);
3348 if (ret)
3349 return ret;
3350 }
ead73183 3351
da1774e5 3352 rtnl_lock();
04e5216d 3353 if (netif_running(ndev)) {
f4c4a4e0
NA		 3354 pinctrl_pm_select_default_state(&fep->pdev->dev);
3355 ret = fec_enet_clk_enable(ndev, true);
3356 if (ret) {
3357 rtnl_unlock();
3358 goto failed_clk;
3359 }
ef83337d 3360 fec_restart(ndev);
31a6de34 3361 netif_tx_lock_bh(ndev);
6af42d42 3362 netif_device_attach(ndev);
dbc64a8e 3363 netif_tx_unlock_bh(ndev);
6af42d42 3364 napi_enable(&fep->napi);
d76cfae9 3365 phy_start(fep->phy_dev);
ead73183 3366 }
da1774e5 3367 rtnl_unlock();
04e5216d 3368
ead73183 3369 return 0;
13a097bd 3370
e8fcfcd5 3371failed_clk:
13a097bd
FE		 3372 if (fep->reg_phy)
3373 regulator_disable(fep->reg_phy);
3374 return ret;
ead73183
SH		 3375}
3376
bf7bfd7f 3377static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
59d4289b 3378
ead73183
SH		 3379static struct platform_driver fec_driver = {
3380 .driver = {
b5680e0b 3381 .name = DRIVER_NAME,
87cad5c3 3382 .owner = THIS_MODULE,
87cad5c3 3383 .pm = &fec_pm_ops,
ca2cc333 3384 .of_match_table = fec_dt_ids,
ead73183 3385 },
b5680e0b 3386 .id_table = fec_devtype,
87cad5c3 3387 .probe = fec_probe,
33897cc8 3388 .remove = fec_drv_remove,
ead73183
SH		 3389};
3390
aaca2377 3391module_platform_driver(fec_driver);
1da177e4 3392
f8c0aca9 3393MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 3394MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)