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be2net: enable IFACE filters only after creating RXQs
[linux-2.6-block.git] / drivers / net / ethernet / emulex / benet / be_cmds.h
CommitLineData
6b7c5b94 1/*
d19261b8 2 * Copyright (C) 2005 - 2015 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
83b06116
VV		 47#define CQE_FLAGS_VALID_MASK BIT(31)
48#define CQE_FLAGS_ASYNC_MASK BIT(30)
49#define CQE_FLAGS_COMPLETED_MASK BIT(28)
50#define CQE_FLAGS_CONSUMED_MASK BIT(27)
6b7c5b94
SP		 51
52/* Completion Status */
4c60005f 53enum mcc_base_status {
2b3f291b
SP		 54 MCC_STATUS_SUCCESS = 0,
55 MCC_STATUS_FAILED = 1,
56 MCC_STATUS_ILLEGAL_REQUEST = 2,
57 MCC_STATUS_ILLEGAL_FIELD = 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
b29812c1
SR		 60 MCC_STATUS_NOT_SUPPORTED = 66,
61 MCC_STATUS_FEATURE_NOT_SUPPORTED = 68
6b7c5b94
SP		 62};
63
4c60005f
KA		 64/* Additional status */
65enum mcc_addl_status {
66 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16,
67 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d,
77be8c1c
KA		 68 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a,
69 MCC_ADDL_STATUS_INSUFFICIENT_VLANS = 0xab
4c60005f
KA		 70};
71
72#define CQE_BASE_STATUS_MASK 0xFFFF
73#define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */
74#define CQE_ADDL_STATUS_MASK 0xFF
75#define CQE_ADDL_STATUS_SHIFT 16 /* bits 16 - 31 */
d9d604f8 76
4c60005f
KA		 77#define base_status(status) \
78 ((enum mcc_base_status) \
79 (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0))
80#define addl_status(status) \
81 ((enum mcc_addl_status) \
82 (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \
83 CQE_ADDL_STATUS_MASK : 0))
6b7c5b94 84
efd2e40a 85struct be_mcc_compl {
6b7c5b94
SP		 86 u32 status; /* dword 0 */
87 u32 tag0; /* dword 1 */
88 u32 tag1; /* dword 2 */
89 u32 flags; /* dword 3 */
90};
91
3acf19d9
SP		 92/* When the async bit of mcc_compl flags is set, flags
93 * is interpreted as follows:
a8f447bd 94 */
3acf19d9
SP		 95#define ASYNC_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
96#define ASYNC_EVENT_CODE_MASK 0xFF
97#define ASYNC_EVENT_TYPE_SHIFT 16
98#define ASYNC_EVENT_TYPE_MASK 0xFF
a8f447bd 99#define ASYNC_EVENT_CODE_LINK_STATE 0x1
cc4ce020
SK		 100#define ASYNC_EVENT_CODE_GRP_5 0x5
101#define ASYNC_EVENT_QOS_SPEED 0x1
102#define ASYNC_EVENT_COS_PRIORITY 0x2
3968fa1e 103#define ASYNC_EVENT_PVID_STATE 0x3
bc0c3405
AK		 104#define ASYNC_EVENT_CODE_QNQ 0x6
105#define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
21252377
VV		 106#define ASYNC_EVENT_CODE_SLIPORT 0x11
107#define ASYNC_EVENT_PORT_MISCONFIG 0x9
760c295e 108#define ASYNC_EVENT_FW_CONTROL 0x5
bc0c3405 109
a8f447bd 110enum {
ea172a01
SP		 111 LINK_DOWN = 0x0,
112 LINK_UP = 0x1
a8f447bd 113};
ea172a01 114#define LINK_STATUS_MASK 0x1
2e177a5c 115#define LOGICAL_LINK_STATUS_MASK 0x2
a8f447bd 116
3acf19d9 117/* When the event code of compl->flags is link-state, the mcc_compl
a8f447bd
SP		 118 * must be interpreted as follows
119 */
120struct be_async_event_link_state {
121 u8 physical_port;
122 u8 port_link_status;
123 u8 port_duplex;
124 u8 port_speed;
125 u8 port_fault;
126 u8 rsvd0[7];
3acf19d9 127 u32 flags;
a8f447bd
SP		 128} __packed;
129
3acf19d9 130/* When the event code of compl->flags is GRP-5 and event_type is QOS_SPEED
cc4ce020
SK		 131 * the mcc_compl must be interpreted as follows
132 */
133struct be_async_event_grp5_qos_link_speed {
134 u8 physical_port;
135 u8 rsvd[5];
136 u16 qos_link_speed;
137 u32 event_tag;
3acf19d9 138 u32 flags;
cc4ce020
SK		 139} __packed;
140
3acf19d9 141/* When the event code of compl->flags is GRP5 and event type is
cc4ce020
SK		 142 * CoS-Priority, the mcc_compl must be interpreted as follows
143 */
144struct be_async_event_grp5_cos_priority {
145 u8 physical_port;
146 u8 available_priority_bmap;
147 u8 reco_default_priority;
148 u8 valid;
149 u8 rsvd0;
150 u8 event_tag;
3acf19d9 151 u32 flags;
cc4ce020
SK		 152} __packed;
153
3acf19d9 154/* When the event code of compl->flags is GRP5 and event type is
3968fa1e
AK		 155 * PVID state, the mcc_compl must be interpreted as follows
156 */
157struct be_async_event_grp5_pvid_state {
158 u8 enabled;
159 u8 rsvd0;
160 u16 tag;
161 u32 event_tag;
162 u32 rsvd1;
3acf19d9 163 u32 flags;
3968fa1e
AK		 164} __packed;
165
bc0c3405
AK		 166/* async event indicating outer VLAN tag in QnQ */
167struct be_async_event_qnq {
168 u8 valid; /* Indicates if outer VLAN is valid */
169 u8 rsvd0;
170 u16 vlan_tag;
171 u32 event_tag;
172 u8 rsvd1[4];
3acf19d9 173 u32 flags;
bc0c3405
AK		 174} __packed;
175
21252377
VV		 176#define INCOMPATIBLE_SFP 0x3
177/* async event indicating misconfigured port */
178struct be_async_event_misconfig_port {
179 u32 event_data_word1;
180 u32 event_data_word2;
181 u32 rsvd0;
182 u32 flags;
183} __packed;
184
760c295e
VD		 185#define BMC_FILT_BROADCAST_ARP BIT(0)
186#define BMC_FILT_BROADCAST_DHCP_CLIENT BIT(1)
187#define BMC_FILT_BROADCAST_DHCP_SERVER BIT(2)
188#define BMC_FILT_BROADCAST_NET_BIOS BIT(3)
189#define BMC_FILT_BROADCAST BIT(7)
190#define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER BIT(8)
191#define BMC_FILT_MULTICAST_IPV6_RA BIT(9)
192#define BMC_FILT_MULTICAST_IPV6_RAS BIT(10)
193#define BMC_FILT_MULTICAST BIT(15)
194struct be_async_fw_control {
195 u32 event_data_word1;
196 u32 event_data_word2;
197 u32 evt_tag;
198 u32 event_data_word4;
199} __packed;
200
6b7c5b94
SP		 201struct be_mcc_mailbox {
202 struct be_mcc_wrb wrb;
efd2e40a 203 struct be_mcc_compl compl;
6b7c5b94
SP		 204};
205
206#define CMD_SUBSYSTEM_COMMON 0x1
207#define CMD_SUBSYSTEM_ETH 0x3
ff33a6e2 208#define CMD_SUBSYSTEM_LOWLEVEL 0xb
6b7c5b94
SP		 209
210#define OPCODE_COMMON_NTWK_MAC_QUERY 1
211#define OPCODE_COMMON_NTWK_MAC_SET 2
212#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
213#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
214#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
fa9a6fed 215#define OPCODE_COMMON_READ_FLASHROM 6
84517482 216#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 217#define OPCODE_COMMON_CQ_CREATE 12
218#define OPCODE_COMMON_EQ_CREATE 13
cc4ce020 219#define OPCODE_COMMON_MCC_CREATE 21
e1d18735 220#define OPCODE_COMMON_SET_QOS 28
cc4ce020 221#define OPCODE_COMMON_MCC_CREATE_EXT 90
368c0ca2 222#define OPCODE_COMMON_SEEPROM_READ 30
9e1453c5 223#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
6b7c5b94
SP		 224#define OPCODE_COMMON_NTWK_RX_FILTER 34
225#define OPCODE_COMMON_GET_FW_VERSION 35
226#define OPCODE_COMMON_SET_FLOW_CONTROL 36
227#define OPCODE_COMMON_GET_FLOW_CONTROL 37
228#define OPCODE_COMMON_SET_FRAME_SIZE 39
229#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
230#define OPCODE_COMMON_FIRMWARE_CONFIG 42
231#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
232#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 233#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 234#define OPCODE_COMMON_CQ_DESTROY 54
235#define OPCODE_COMMON_EQ_DESTROY 55
236#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
237#define OPCODE_COMMON_NTWK_PMAC_ADD 59
238#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 239#define OPCODE_COMMON_FUNCTION_RESET 61
311fddc7 240#define OPCODE_COMMON_MANAGE_FAT 68
fad9ab2c
SB		 241#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
242#define OPCODE_COMMON_GET_BEACON_STATE 70
0388f251 243#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
b4e32a71 244#define OPCODE_COMMON_GET_PORT_NAME 77
bdce2ad7 245#define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80
68c45a2d 246#define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
04a06028 247#define OPCODE_COMMON_SET_FN_PRIVILEGES 100
ee3cb629 248#define OPCODE_COMMON_GET_PHY_DETAILS 102
2e588f84 249#define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
609ff3bb 250#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
941a77d5
SK		 251#define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
252#define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
590c391d
PR		 253#define OPCODE_COMMON_GET_MAC_LIST 147
254#define OPCODE_COMMON_SET_MAC_LIST 148
f1f3ee1b 255#define OPCODE_COMMON_GET_HSW_CONFIG 152
abb93951
PR		 256#define OPCODE_COMMON_GET_FUNC_CONFIG 160
257#define OPCODE_COMMON_GET_PROFILE_CONFIG 164
d5c18473 258#define OPCODE_COMMON_SET_PROFILE_CONFIG 165
542963b7 259#define OPCODE_COMMON_GET_ACTIVE_PROFILE 167
f1f3ee1b 260#define OPCODE_COMMON_SET_HSW_CONFIG 153
f25b119c 261#define OPCODE_COMMON_GET_FN_PRIVILEGES 170
de49bd5a 262#define OPCODE_COMMON_READ_OBJECT 171
485bf569 263#define OPCODE_COMMON_WRITE_OBJECT 172
f0613380 264#define OPCODE_COMMON_DELETE_OBJECT 174
a401801c 265#define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193
4c876616 266#define OPCODE_COMMON_GET_IFACE_LIST 194
dcf7ebba 267#define OPCODE_COMMON_ENABLE_DISABLE_VF 196
6b7c5b94 268
3abcdeda 269#define OPCODE_ETH_RSS_CONFIG 1
6b7c5b94
SP		 270#define OPCODE_ETH_ACPI_CONFIG 2
271#define OPCODE_ETH_PROMISCUOUS 3
272#define OPCODE_ETH_GET_STATISTICS 4
273#define OPCODE_ETH_TX_CREATE 7
274#define OPCODE_ETH_RX_CREATE 8
275#define OPCODE_ETH_TX_DESTROY 9
276#define OPCODE_ETH_RX_DESTROY 10
71d8d1b5 277#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
005d5696 278#define OPCODE_ETH_GET_PPORT_STATS 18
6b7c5b94 279
ff33a6e2
S		 280#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
281#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
fced9999 282#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
ff33a6e2 283
6b7c5b94
SP		 284struct be_cmd_req_hdr {
285 u8 opcode; /* dword 0 */
286 u8 subsystem; /* dword 0 */
287 u8 port_number; /* dword 0 */
288 u8 domain; /* dword 0 */
289 u32 timeout; /* dword 1 */
290 u32 request_length; /* dword 2 */
7b139c83
AK		 291 u8 version; /* dword 3 */
292 u8 rsvd[3]; /* dword 3 */
6b7c5b94
SP		 293};
294
295#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
296#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
297struct be_cmd_resp_hdr {
652bf646
PR		 298 u8 opcode; /* dword 0 */
299 u8 subsystem; /* dword 0 */
300 u8 rsvd[2]; /* dword 0 */
4c60005f
KA		 301 u8 base_status; /* dword 1 */
302 u8 addl_status; /* dword 1 */
652bf646 303 u8 rsvd1[2]; /* dword 1 */
6b7c5b94
SP		 304 u32 response_length; /* dword 2 */
305 u32 actual_resp_len; /* dword 3 */
306};
307
308struct phys_addr {
309 u32 lo;
310 u32 hi;
311};
312
313/**************************
314 * BE Command definitions *
315 **************************/
316
317/* Pseudo amap definition in which each bit of the actual structure is defined
318 * as a byte: used to calculate offset/shift/mask of each field */
319struct amap_eq_context {
320 u8 cidx[13]; /* dword 0*/
321 u8 rsvd0[3]; /* dword 0*/
322 u8 epidx[13]; /* dword 0*/
323 u8 valid; /* dword 0*/
324 u8 rsvd1; /* dword 0*/
325 u8 size; /* dword 0*/
326 u8 pidx[13]; /* dword 1*/
327 u8 rsvd2[3]; /* dword 1*/
328 u8 pd[10]; /* dword 1*/
329 u8 count[3]; /* dword 1*/
330 u8 solevent; /* dword 1*/
331 u8 stalled; /* dword 1*/
332 u8 armed; /* dword 1*/
333 u8 rsvd3[4]; /* dword 2*/
334 u8 func[8]; /* dword 2*/
335 u8 rsvd4; /* dword 2*/
336 u8 delaymult[10]; /* dword 2*/
337 u8 rsvd5[2]; /* dword 2*/
338 u8 phase[2]; /* dword 2*/
339 u8 nodelay; /* dword 2*/
340 u8 rsvd6[4]; /* dword 2*/
341 u8 rsvd7[32]; /* dword 3*/
342} __packed;
343
344struct be_cmd_req_eq_create {
345 struct be_cmd_req_hdr hdr;
346 u16 num_pages; /* sword */
347 u16 rsvd0; /* sword */
348 u8 context[sizeof(struct amap_eq_context) / 8];
349 struct phys_addr pages[8];
350} __packed;
351
352struct be_cmd_resp_eq_create {
353 struct be_cmd_resp_hdr resp_hdr;
354 u16 eq_id; /* sword */
f2f781a7 355 u16 msix_idx; /* available only in v2 */
6b7c5b94
SP		 356} __packed;
357
358/******************** Mac query ***************************/
359enum {
360 MAC_ADDRESS_TYPE_STORAGE = 0x0,
361 MAC_ADDRESS_TYPE_NETWORK = 0x1,
362 MAC_ADDRESS_TYPE_PD = 0x2,
363 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
364};
365
366struct mac_addr {
367 u16 size_of_struct;
368 u8 addr[ETH_ALEN];
369} __packed;
370
371struct be_cmd_req_mac_query {
372 struct be_cmd_req_hdr hdr;
373 u8 type;
374 u8 permanent;
375 u16 if_id;
590c391d 376 u32 pmac_id;
6b7c5b94
SP		 377} __packed;
378
379struct be_cmd_resp_mac_query {
380 struct be_cmd_resp_hdr hdr;
381 struct mac_addr mac;
382};
383
384/******************** PMac Add ***************************/
385struct be_cmd_req_pmac_add {
386 struct be_cmd_req_hdr hdr;
387 u32 if_id;
388 u8 mac_address[ETH_ALEN];
389 u8 rsvd0[2];
390} __packed;
391
392struct be_cmd_resp_pmac_add {
393 struct be_cmd_resp_hdr hdr;
394 u32 pmac_id;
395};
396
397/******************** PMac Del ***************************/
398struct be_cmd_req_pmac_del {
399 struct be_cmd_req_hdr hdr;
400 u32 if_id;
401 u32 pmac_id;
402};
403
404/******************** Create CQ ***************************/
405/* Pseudo amap definition in which each bit of the actual structure is defined
406 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 407struct amap_cq_context_be {
6b7c5b94
SP		 408 u8 cidx[11]; /* dword 0*/
409 u8 rsvd0; /* dword 0*/
410 u8 coalescwm[2]; /* dword 0*/
411 u8 nodelay; /* dword 0*/
412 u8 epidx[11]; /* dword 0*/
413 u8 rsvd1; /* dword 0*/
414 u8 count[2]; /* dword 0*/
415 u8 valid; /* dword 0*/
416 u8 solevent; /* dword 0*/
417 u8 eventable; /* dword 0*/
418 u8 pidx[11]; /* dword 1*/
419 u8 rsvd2; /* dword 1*/
420 u8 pd[10]; /* dword 1*/
421 u8 eqid[8]; /* dword 1*/
422 u8 stalled; /* dword 1*/
423 u8 armed; /* dword 1*/
424 u8 rsvd3[4]; /* dword 2*/
425 u8 func[8]; /* dword 2*/
426 u8 rsvd4[20]; /* dword 2*/
427 u8 rsvd5[32]; /* dword 3*/
428} __packed;
429
bbdc42f8 430struct amap_cq_context_v2 {
fe6d2a38
SP		 431 u8 rsvd0[12]; /* dword 0*/
432 u8 coalescwm[2]; /* dword 0*/
433 u8 nodelay; /* dword 0*/
434 u8 rsvd1[12]; /* dword 0*/
435 u8 count[2]; /* dword 0*/
436 u8 valid; /* dword 0*/
437 u8 rsvd2; /* dword 0*/
438 u8 eventable; /* dword 0*/
439 u8 eqid[16]; /* dword 1*/
440 u8 rsvd3[15]; /* dword 1*/
441 u8 armed; /* dword 1*/
442 u8 rsvd4[32]; /* dword 2*/
443 u8 rsvd5[32]; /* dword 3*/
444} __packed;
445
6b7c5b94
SP		 446struct be_cmd_req_cq_create {
447 struct be_cmd_req_hdr hdr;
448 u16 num_pages;
fe6d2a38
SP		 449 u8 page_size;
450 u8 rsvd0;
451 u8 context[sizeof(struct amap_cq_context_be) / 8];
6b7c5b94
SP		 452 struct phys_addr pages[8];
453} __packed;
454
fe6d2a38 455
6b7c5b94
SP		 456struct be_cmd_resp_cq_create {
457 struct be_cmd_resp_hdr hdr;
458 u16 cq_id;
459 u16 rsvd0;
460} __packed;
461
311fddc7
SK		 462struct be_cmd_req_get_fat {
463 struct be_cmd_req_hdr hdr;
464 u32 fat_operation;
465 u32 read_log_offset;
466 u32 read_log_length;
467 u32 data_buffer_size;
468 u32 data_buffer[1];
469} __packed;
470
471struct be_cmd_resp_get_fat {
472 struct be_cmd_resp_hdr hdr;
473 u32 log_size;
474 u32 read_log_length;
475 u32 rsvd[2];
476 u32 data_buffer[1];
477} __packed;
478
479
5fb379ee
SP		 480/******************** Create MCCQ ***************************/
481/* Pseudo amap definition in which each bit of the actual structure is defined
482 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 483struct amap_mcc_context_be {
5fb379ee
SP		 484 u8 con_index[14];
485 u8 rsvd0[2];
486 u8 ring_size[4];
487 u8 fetch_wrb;
488 u8 fetch_r2t;
489 u8 cq_id[10];
490 u8 prod_index[14];
491 u8 fid[8];
492 u8 pdid[9];
493 u8 valid;
494 u8 rsvd1[32];
495 u8 rsvd2[32];
496} __packed;
497
666d39c7 498struct amap_mcc_context_v1 {
fe6d2a38
SP		 499 u8 async_cq_id[16];
500 u8 ring_size[4];
501 u8 rsvd0[12];
502 u8 rsvd1[31];
503 u8 valid;
504 u8 async_cq_valid[1];
505 u8 rsvd2[31];
506 u8 rsvd3[32];
507} __packed;
508
5fb379ee 509struct be_cmd_req_mcc_create {
34b1ef04
SK		 510 struct be_cmd_req_hdr hdr;
511 u16 num_pages;
512 u16 cq_id;
513 u8 context[sizeof(struct amap_mcc_context_be) / 8];
514 struct phys_addr pages[8];
515} __packed;
516
517struct be_cmd_req_mcc_ext_create {
5fb379ee
SP		 518 struct be_cmd_req_hdr hdr;
519 u16 num_pages;
fe6d2a38 520 u16 cq_id;
cc4ce020 521 u32 async_event_bitmap[1];
666d39c7 522 u8 context[sizeof(struct amap_mcc_context_v1) / 8];
5fb379ee
SP		 523 struct phys_addr pages[8];
524} __packed;
525
526struct be_cmd_resp_mcc_create {
527 struct be_cmd_resp_hdr hdr;
528 u16 id;
529 u16 rsvd0;
530} __packed;
531
6b7c5b94
SP		 532/******************** Create TxQ ***************************/
533#define BE_ETH_TX_RING_TYPE_STANDARD 2
534#define BE_ULP1_NUM 1
535
6b7c5b94
SP		 536struct be_cmd_req_eth_tx_create {
537 struct be_cmd_req_hdr hdr;
538 u8 num_pages;
539 u8 ulp_num;
94d73aaa
VV		 540 u16 type;
541 u16 if_id;
542 u8 queue_size;
543 u8 rsvd0;
544 u32 rsvd1;
545 u16 cq_id;
546 u16 rsvd2;
547 u32 rsvd3[13];
6b7c5b94
SP		 548 struct phys_addr pages[8];
549} __packed;
550
551struct be_cmd_resp_eth_tx_create {
552 struct be_cmd_resp_hdr hdr;
553 u16 cid;
94d73aaa
VV		 554 u16 rid;
555 u32 db_offset;
556 u32 rsvd0[4];
6b7c5b94
SP		 557} __packed;
558
559/******************** Create RxQ ***************************/
560struct be_cmd_req_eth_rx_create {
561 struct be_cmd_req_hdr hdr;
562 u16 cq_id;
563 u8 frag_size;
564 u8 num_pages;
565 struct phys_addr pages[2];
566 u32 interface_id;
567 u16 max_frame_size;
568 u16 rsvd0;
569 u32 rss_queue;
570} __packed;
571
572struct be_cmd_resp_eth_rx_create {
573 struct be_cmd_resp_hdr hdr;
574 u16 id;
3abcdeda 575 u8 rss_id;
6b7c5b94
SP		 576 u8 rsvd0;
577} __packed;
578
579/******************** Q Destroy ***************************/
580/* Type of Queue to be destroyed */
581enum {
582 QTYPE_EQ = 1,
583 QTYPE_CQ,
584 QTYPE_TXQ,
5fb379ee
SP		 585 QTYPE_RXQ,
586 QTYPE_MCCQ
6b7c5b94
SP		 587};
588
589struct be_cmd_req_q_destroy {
590 struct be_cmd_req_hdr hdr;
591 u16 id;
592 u16 bypass_flush; /* valid only for rx q destroy */
593} __packed;
594
595/************ I/f Create (it's actually I/f Config Create)**********/
596
597/* Capability flags for the i/f */
598enum be_if_flags {
599 BE_IF_FLAGS_RSS = 0x4,
600 BE_IF_FLAGS_PROMISCUOUS = 0x8,
601 BE_IF_FLAGS_BROADCAST = 0x10,
602 BE_IF_FLAGS_UNTAGGED = 0x20,
603 BE_IF_FLAGS_ULP = 0x40,
604 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
605 BE_IF_FLAGS_VLAN = 0x100,
606 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
607 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
f21b538c 608 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
71bb8bd0
VV		 609 BE_IF_FLAGS_MULTICAST = 0x1000,
610 BE_IF_FLAGS_DEFQ_RSS = 0x1000000
6b7c5b94
SP		 611};
612
3da988c9
SB		 613#define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\
614 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\
615 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\
616 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\
71bb8bd0 617 BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_DEFQ_RSS)
3da988c9 618
ac34b743
SP		 619#define BE_IF_FLAGS_ALL_PROMISCUOUS (BE_IF_FLAGS_PROMISCUOUS | \
620 BE_IF_FLAGS_VLAN_PROMISCUOUS |\
621 BE_IF_FLAGS_MCAST_PROMISCUOUS)
622
bcc84140
KA		 623#define BE_IF_EN_FLAGS (BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_PASS_L3L4_ERRORS |\
624 BE_IF_FLAGS_MULTICAST | BE_IF_FLAGS_UNTAGGED)
625
626#define BE_IF_ALL_FILT_FLAGS (BE_IF_EN_FLAGS | BE_IF_FLAGS_ALL_PROMISCUOUS)
627
6b7c5b94
SP		 628/* An RX interface is an object with one or more MAC addresses and
629 * filtering capabilities. */
630struct be_cmd_req_if_create {
631 struct be_cmd_req_hdr hdr;
af901ca1 632 u32 version; /* ignore currently */
6b7c5b94
SP		 633 u32 capability_flags;
634 u32 enable_flags;
635 u8 mac_addr[ETH_ALEN];
636 u8 rsvd0;
637 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
638 u32 vlan_tag; /* not used currently */
639} __packed;
640
641struct be_cmd_resp_if_create {
642 struct be_cmd_resp_hdr hdr;
643 u32 interface_id;
644 u32 pmac_id;
645};
646
647/****** I/f Destroy(it's actually I/f Config Destroy )**********/
648struct be_cmd_req_if_destroy {
649 struct be_cmd_req_hdr hdr;
650 u32 interface_id;
651};
652
653/*************** HW Stats Get **********************************/
89a88ab8 654struct be_port_rxf_stats_v0 {
6b7c5b94
SP		 655 u32 rx_bytes_lsd; /* dword 0*/
656 u32 rx_bytes_msd; /* dword 1*/
657 u32 rx_total_frames; /* dword 2*/
658 u32 rx_unicast_frames; /* dword 3*/
659 u32 rx_multicast_frames; /* dword 4*/
660 u32 rx_broadcast_frames; /* dword 5*/
661 u32 rx_crc_errors; /* dword 6*/
662 u32 rx_alignment_symbol_errors; /* dword 7*/
663 u32 rx_pause_frames; /* dword 8*/
664 u32 rx_control_frames; /* dword 9*/
665 u32 rx_in_range_errors; /* dword 10*/
666 u32 rx_out_range_errors; /* dword 11*/
667 u32 rx_frame_too_long; /* dword 12*/
18fb06a1
SR		 668 u32 rx_address_filtered; /* dword 13*/
669 u32 rx_vlan_filtered; /* dword 14*/
6b7c5b94
SP		 670 u32 rx_dropped_too_small; /* dword 15*/
671 u32 rx_dropped_too_short; /* dword 16*/
672 u32 rx_dropped_header_too_small; /* dword 17*/
673 u32 rx_dropped_tcp_length; /* dword 18*/
674 u32 rx_dropped_runt; /* dword 19*/
675 u32 rx_64_byte_packets; /* dword 20*/
676 u32 rx_65_127_byte_packets; /* dword 21*/
677 u32 rx_128_256_byte_packets; /* dword 22*/
678 u32 rx_256_511_byte_packets; /* dword 23*/
679 u32 rx_512_1023_byte_packets; /* dword 24*/
680 u32 rx_1024_1518_byte_packets; /* dword 25*/
681 u32 rx_1519_2047_byte_packets; /* dword 26*/
682 u32 rx_2048_4095_byte_packets; /* dword 27*/
683 u32 rx_4096_8191_byte_packets; /* dword 28*/
684 u32 rx_8192_9216_byte_packets; /* dword 29*/
685 u32 rx_ip_checksum_errs; /* dword 30*/
686 u32 rx_tcp_checksum_errs; /* dword 31*/
687 u32 rx_udp_checksum_errs; /* dword 32*/
688 u32 rx_non_rss_packets; /* dword 33*/
689 u32 rx_ipv4_packets; /* dword 34*/
690 u32 rx_ipv6_packets; /* dword 35*/
691 u32 rx_ipv4_bytes_lsd; /* dword 36*/
692 u32 rx_ipv4_bytes_msd; /* dword 37*/
693 u32 rx_ipv6_bytes_lsd; /* dword 38*/
694 u32 rx_ipv6_bytes_msd; /* dword 39*/
695 u32 rx_chute1_packets; /* dword 40*/
696 u32 rx_chute2_packets; /* dword 41*/
697 u32 rx_chute3_packets; /* dword 42*/
698 u32 rx_management_packets; /* dword 43*/
699 u32 rx_switched_unicast_packets; /* dword 44*/
700 u32 rx_switched_multicast_packets; /* dword 45*/
701 u32 rx_switched_broadcast_packets; /* dword 46*/
702 u32 tx_bytes_lsd; /* dword 47*/
703 u32 tx_bytes_msd; /* dword 48*/
704 u32 tx_unicastframes; /* dword 49*/
705 u32 tx_multicastframes; /* dword 50*/
706 u32 tx_broadcastframes; /* dword 51*/
707 u32 tx_pauseframes; /* dword 52*/
708 u32 tx_controlframes; /* dword 53*/
709 u32 tx_64_byte_packets; /* dword 54*/
710 u32 tx_65_127_byte_packets; /* dword 55*/
711 u32 tx_128_256_byte_packets; /* dword 56*/
712 u32 tx_256_511_byte_packets; /* dword 57*/
713 u32 tx_512_1023_byte_packets; /* dword 58*/
714 u32 tx_1024_1518_byte_packets; /* dword 59*/
715 u32 tx_1519_2047_byte_packets; /* dword 60*/
716 u32 tx_2048_4095_byte_packets; /* dword 61*/
717 u32 tx_4096_8191_byte_packets; /* dword 62*/
718 u32 tx_8192_9216_byte_packets; /* dword 63*/
719 u32 rx_fifo_overflow; /* dword 64*/
720 u32 rx_input_fifo_overflow; /* dword 65*/
721};
722
89a88ab8
AK		 723struct be_rxf_stats_v0 {
724 struct be_port_rxf_stats_v0 port[2];
6b7c5b94
SP		 725 u32 rx_drops_no_pbuf; /* dword 132*/
726 u32 rx_drops_no_txpb; /* dword 133*/
727 u32 rx_drops_no_erx_descr; /* dword 134*/
728 u32 rx_drops_no_tpre_descr; /* dword 135*/
729 u32 management_rx_port_packets; /* dword 136*/
730 u32 management_rx_port_bytes; /* dword 137*/
731 u32 management_rx_port_pause_frames; /* dword 138*/
732 u32 management_rx_port_errors; /* dword 139*/
733 u32 management_tx_port_packets; /* dword 140*/
734 u32 management_tx_port_bytes; /* dword 141*/
735 u32 management_tx_port_pause; /* dword 142*/
736 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
737 u32 rx_drops_too_many_frags; /* dword 144*/
738 u32 rx_drops_invalid_ring; /* dword 145*/
739 u32 forwarded_packets; /* dword 146*/
740 u32 rx_drops_mtu; /* dword 147*/
f6c4bf3e
AK		 741 u32 rsvd0[7];
742 u32 port0_jabber_events;
743 u32 port1_jabber_events;
744 u32 rsvd1[6];
6b7c5b94
SP		 745};
746
89a88ab8 747struct be_erx_stats_v0 {
6b7c5b94 748 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
89a88ab8 749 u32 rsvd[4];
6b7c5b94
SP		 750};
751
f6c4bf3e
AK		 752struct be_pmem_stats {
753 u32 eth_red_drops;
89a88ab8 754 u32 rsvd[5];
f6c4bf3e
AK		 755};
756
89a88ab8
AK		 757struct be_hw_stats_v0 {
758 struct be_rxf_stats_v0 rxf;
6b7c5b94 759 u32 rsvd[48];
89a88ab8 760 struct be_erx_stats_v0 erx;
f6c4bf3e 761 struct be_pmem_stats pmem;
6b7c5b94
SP		 762};
763
89a88ab8 764struct be_cmd_req_get_stats_v0 {
6b7c5b94 765 struct be_cmd_req_hdr hdr;
89a88ab8 766 u8 rsvd[sizeof(struct be_hw_stats_v0)];
6b7c5b94
SP		 767};
768
89a88ab8 769struct be_cmd_resp_get_stats_v0 {
6b7c5b94 770 struct be_cmd_resp_hdr hdr;
89a88ab8 771 struct be_hw_stats_v0 hw_stats;
6b7c5b94
SP		 772};
773
ac124ff9 774struct lancer_pport_stats {
005d5696
SX		 775 u32 tx_packets_lo;
776 u32 tx_packets_hi;
777 u32 tx_unicast_packets_lo;
778 u32 tx_unicast_packets_hi;
779 u32 tx_multicast_packets_lo;
780 u32 tx_multicast_packets_hi;
781 u32 tx_broadcast_packets_lo;
782 u32 tx_broadcast_packets_hi;
783 u32 tx_bytes_lo;
784 u32 tx_bytes_hi;
785 u32 tx_unicast_bytes_lo;
786 u32 tx_unicast_bytes_hi;
787 u32 tx_multicast_bytes_lo;
788 u32 tx_multicast_bytes_hi;
789 u32 tx_broadcast_bytes_lo;
790 u32 tx_broadcast_bytes_hi;
791 u32 tx_discards_lo;
792 u32 tx_discards_hi;
793 u32 tx_errors_lo;
794 u32 tx_errors_hi;
795 u32 tx_pause_frames_lo;
796 u32 tx_pause_frames_hi;
797 u32 tx_pause_on_frames_lo;
798 u32 tx_pause_on_frames_hi;
799 u32 tx_pause_off_frames_lo;
800 u32 tx_pause_off_frames_hi;
801 u32 tx_internal_mac_errors_lo;
802 u32 tx_internal_mac_errors_hi;
803 u32 tx_control_frames_lo;
804 u32 tx_control_frames_hi;
805 u32 tx_packets_64_bytes_lo;
806 u32 tx_packets_64_bytes_hi;
807 u32 tx_packets_65_to_127_bytes_lo;
808 u32 tx_packets_65_to_127_bytes_hi;
809 u32 tx_packets_128_to_255_bytes_lo;
810 u32 tx_packets_128_to_255_bytes_hi;
811 u32 tx_packets_256_to_511_bytes_lo;
812 u32 tx_packets_256_to_511_bytes_hi;
813 u32 tx_packets_512_to_1023_bytes_lo;
814 u32 tx_packets_512_to_1023_bytes_hi;
815 u32 tx_packets_1024_to_1518_bytes_lo;
816 u32 tx_packets_1024_to_1518_bytes_hi;
817 u32 tx_packets_1519_to_2047_bytes_lo;
818 u32 tx_packets_1519_to_2047_bytes_hi;
819 u32 tx_packets_2048_to_4095_bytes_lo;
820 u32 tx_packets_2048_to_4095_bytes_hi;
821 u32 tx_packets_4096_to_8191_bytes_lo;
822 u32 tx_packets_4096_to_8191_bytes_hi;
823 u32 tx_packets_8192_to_9216_bytes_lo;
824 u32 tx_packets_8192_to_9216_bytes_hi;
825 u32 tx_lso_packets_lo;
826 u32 tx_lso_packets_hi;
827 u32 rx_packets_lo;
828 u32 rx_packets_hi;
829 u32 rx_unicast_packets_lo;
830 u32 rx_unicast_packets_hi;
831 u32 rx_multicast_packets_lo;
832 u32 rx_multicast_packets_hi;
833 u32 rx_broadcast_packets_lo;
834 u32 rx_broadcast_packets_hi;
835 u32 rx_bytes_lo;
836 u32 rx_bytes_hi;
837 u32 rx_unicast_bytes_lo;
838 u32 rx_unicast_bytes_hi;
839 u32 rx_multicast_bytes_lo;
840 u32 rx_multicast_bytes_hi;
841 u32 rx_broadcast_bytes_lo;
842 u32 rx_broadcast_bytes_hi;
843 u32 rx_unknown_protos;
844 u32 rsvd_69; /* Word 69 is reserved */
845 u32 rx_discards_lo;
846 u32 rx_discards_hi;
847 u32 rx_errors_lo;
848 u32 rx_errors_hi;
849 u32 rx_crc_errors_lo;
850 u32 rx_crc_errors_hi;
851 u32 rx_alignment_errors_lo;
852 u32 rx_alignment_errors_hi;
853 u32 rx_symbol_errors_lo;
854 u32 rx_symbol_errors_hi;
855 u32 rx_pause_frames_lo;
856 u32 rx_pause_frames_hi;
857 u32 rx_pause_on_frames_lo;
858 u32 rx_pause_on_frames_hi;
859 u32 rx_pause_off_frames_lo;
860 u32 rx_pause_off_frames_hi;
861 u32 rx_frames_too_long_lo;
862 u32 rx_frames_too_long_hi;
863 u32 rx_internal_mac_errors_lo;
864 u32 rx_internal_mac_errors_hi;
865 u32 rx_undersize_packets;
866 u32 rx_oversize_packets;
867 u32 rx_fragment_packets;
868 u32 rx_jabbers;
869 u32 rx_control_frames_lo;
870 u32 rx_control_frames_hi;
871 u32 rx_control_frames_unknown_opcode_lo;
872 u32 rx_control_frames_unknown_opcode_hi;
873 u32 rx_in_range_errors;
874 u32 rx_out_of_range_errors;
18fb06a1
SR		 875 u32 rx_address_filtered;
876 u32 rx_vlan_filtered;
005d5696
SX		 877 u32 rx_dropped_too_small;
878 u32 rx_dropped_too_short;
879 u32 rx_dropped_header_too_small;
880 u32 rx_dropped_invalid_tcp_length;
881 u32 rx_dropped_runt;
882 u32 rx_ip_checksum_errors;
883 u32 rx_tcp_checksum_errors;
884 u32 rx_udp_checksum_errors;
885 u32 rx_non_rss_packets;
886 u32 rsvd_111;
887 u32 rx_ipv4_packets_lo;
888 u32 rx_ipv4_packets_hi;
889 u32 rx_ipv6_packets_lo;
890 u32 rx_ipv6_packets_hi;
891 u32 rx_ipv4_bytes_lo;
892 u32 rx_ipv4_bytes_hi;
893 u32 rx_ipv6_bytes_lo;
894 u32 rx_ipv6_bytes_hi;
895 u32 rx_nic_packets_lo;
896 u32 rx_nic_packets_hi;
897 u32 rx_tcp_packets_lo;
898 u32 rx_tcp_packets_hi;
899 u32 rx_iscsi_packets_lo;
900 u32 rx_iscsi_packets_hi;
901 u32 rx_management_packets_lo;
902 u32 rx_management_packets_hi;
903 u32 rx_switched_unicast_packets_lo;
904 u32 rx_switched_unicast_packets_hi;
905 u32 rx_switched_multicast_packets_lo;
906 u32 rx_switched_multicast_packets_hi;
907 u32 rx_switched_broadcast_packets_lo;
908 u32 rx_switched_broadcast_packets_hi;
909 u32 num_forwards_lo;
910 u32 num_forwards_hi;
911 u32 rx_fifo_overflow;
912 u32 rx_input_fifo_overflow;
913 u32 rx_drops_too_many_frags_lo;
914 u32 rx_drops_too_many_frags_hi;
915 u32 rx_drops_invalid_queue;
916 u32 rsvd_141;
917 u32 rx_drops_mtu_lo;
918 u32 rx_drops_mtu_hi;
919 u32 rx_packets_64_bytes_lo;
920 u32 rx_packets_64_bytes_hi;
921 u32 rx_packets_65_to_127_bytes_lo;
922 u32 rx_packets_65_to_127_bytes_hi;
923 u32 rx_packets_128_to_255_bytes_lo;
924 u32 rx_packets_128_to_255_bytes_hi;
925 u32 rx_packets_256_to_511_bytes_lo;
926 u32 rx_packets_256_to_511_bytes_hi;
927 u32 rx_packets_512_to_1023_bytes_lo;
928 u32 rx_packets_512_to_1023_bytes_hi;
929 u32 rx_packets_1024_to_1518_bytes_lo;
930 u32 rx_packets_1024_to_1518_bytes_hi;
931 u32 rx_packets_1519_to_2047_bytes_lo;
932 u32 rx_packets_1519_to_2047_bytes_hi;
933 u32 rx_packets_2048_to_4095_bytes_lo;
934 u32 rx_packets_2048_to_4095_bytes_hi;
935 u32 rx_packets_4096_to_8191_bytes_lo;
936 u32 rx_packets_4096_to_8191_bytes_hi;
937 u32 rx_packets_8192_to_9216_bytes_lo;
938 u32 rx_packets_8192_to_9216_bytes_hi;
939};
940
941struct pport_stats_params {
942 u16 pport_num;
943 u8 rsvd;
944 u8 reset_stats;
945};
946
947struct lancer_cmd_req_pport_stats {
948 struct be_cmd_req_hdr hdr;
949 union {
950 struct pport_stats_params params;
ac124ff9 951 u8 rsvd[sizeof(struct lancer_pport_stats)];
005d5696
SX		 952 } cmd_params;
953};
954
955struct lancer_cmd_resp_pport_stats {
956 struct be_cmd_resp_hdr hdr;
ac124ff9 957 struct lancer_pport_stats pport_stats;
005d5696
SX		 958};
959
ac124ff9 960static inline struct lancer_pport_stats*
005d5696
SX		 961 pport_stats_from_cmd(struct be_adapter *adapter)
962{
963 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
964 return &cmd->pport_stats;
965}
966
609ff3bb
AK		 967struct be_cmd_req_get_cntl_addnl_attribs {
968 struct be_cmd_req_hdr hdr;
969 u8 rsvd[8];
970};
971
972struct be_cmd_resp_get_cntl_addnl_attribs {
973 struct be_cmd_resp_hdr hdr;
974 u16 ipl_file_number;
975 u8 ipl_file_version;
976 u8 rsvd0;
977 u8 on_die_temperature; /* in degrees centigrade*/
978 u8 rsvd1[3];
979};
980
6b7c5b94
SP		 981struct be_cmd_req_vlan_config {
982 struct be_cmd_req_hdr hdr;
983 u8 interface_id;
984 u8 promiscuous;
985 u8 untagged;
986 u8 num_vlan;
987 u16 normal_vlan[64];
988} __packed;
989
5b8821b7 990/******************* RX FILTER ******************************/
e7b909a6 991#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
6b7c5b94
SP		 992struct macaddr {
993 u8 byte[ETH_ALEN];
994};
995
ecd0bf0f
PR		 996struct be_cmd_req_rx_filter {
997 struct be_cmd_req_hdr hdr;
998 u32 global_flags_mask;
999 u32 global_flags;
1000 u32 if_flags_mask;
1001 u32 if_flags;
1002 u32 if_id;
5b8821b7
SP		 1003 u32 mcast_num;
1004 struct macaddr mcast_mac[BE_MAX_MC];
ecd0bf0f
PR		 1005};
1006
6b7c5b94
SP		 1007/******************** Link Status Query *******************/
1008struct be_cmd_req_link_status {
1009 struct be_cmd_req_hdr hdr;
1010 u32 rsvd;
1011};
1012
6b7c5b94
SP		 1013enum {
1014 PHY_LINK_DUPLEX_NONE = 0x0,
1015 PHY_LINK_DUPLEX_HALF = 0x1,
1016 PHY_LINK_DUPLEX_FULL = 0x2
1017};
1018
1019enum {
1020 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
1021 PHY_LINK_SPEED_10MBPS = 0x1,
1022 PHY_LINK_SPEED_100MBPS = 0x2,
1023 PHY_LINK_SPEED_1GBPS = 0x3,
b971f847
VV		 1024 PHY_LINK_SPEED_10GBPS = 0x4,
1025 PHY_LINK_SPEED_20GBPS = 0x5,
1026 PHY_LINK_SPEED_25GBPS = 0x6,
1027 PHY_LINK_SPEED_40GBPS = 0x7
6b7c5b94
SP		 1028};
1029
1030struct be_cmd_resp_link_status {
1031 struct be_cmd_resp_hdr hdr;
1032 u8 physical_port;
1033 u8 mac_duplex;
1034 u8 mac_speed;
1035 u8 mac_fault;
1036 u8 mgmt_mac_duplex;
1037 u8 mgmt_mac_speed;
0388f251 1038 u16 link_speed;
b236916a
AK		 1039 u8 logical_link_status;
1040 u8 rsvd1[3];
6b7c5b94
SP		 1041} __packed;
1042
0388f251
SB		 1043/******************** Port Identification ***************************/
1044/* Identifies the type of port attached to NIC */
1045struct be_cmd_req_port_type {
1046 struct be_cmd_req_hdr hdr;
72d7e2bf
SR		 1047 __le32 page_num;
1048 __le32 port;
0388f251
SB		 1049};
1050
1051enum {
1052 TR_PAGE_A0 = 0xa0,
1053 TR_PAGE_A2 = 0xa2
1054};
1055
6809cee0
RN		 1056/* From SFF-8436 QSFP+ spec */
1057#define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83
1058#define QSFP_PLUS_CR4_CABLE 0x8
1059#define QSFP_PLUS_SR4_CABLE 0x4
1060#define QSFP_PLUS_LR4_CABLE 0x2
1061
e36edd9d 1062/* From SFF-8472 spec */
6809cee0
RN		 1063#define SFP_PLUS_SFF_8472_COMP 0x5E
1064#define SFP_PLUS_CABLE_TYPE_OFFSET 0x8
1065#define SFP_PLUS_COPPER_CABLE 0x4
21252377
VV		 1066#define SFP_VENDOR_NAME_OFFSET 0x14
1067#define SFP_VENDOR_PN_OFFSET 0x28
e36edd9d
ML		 1068
1069#define PAGE_DATA_LEN 256
0388f251
SB		 1070struct be_cmd_resp_port_type {
1071 struct be_cmd_resp_hdr hdr;
1072 u32 page_num;
1073 u32 port;
e36edd9d 1074 u8 page_data[PAGE_DATA_LEN];
0388f251
SB		 1075};
1076
6b7c5b94 1077/******************** Get FW Version *******************/
6b7c5b94
SP		 1078struct be_cmd_req_get_fw_version {
1079 struct be_cmd_req_hdr hdr;
1080 u8 rsvd0[FW_VER_LEN];
1081 u8 rsvd1[FW_VER_LEN];
1082} __packed;
1083
1084struct be_cmd_resp_get_fw_version {
1085 struct be_cmd_resp_hdr hdr;
1086 u8 firmware_version_string[FW_VER_LEN];
1087 u8 fw_on_flash_version_string[FW_VER_LEN];
1088} __packed;
1089
1090/******************** Set Flow Contrl *******************/
1091struct be_cmd_req_set_flow_control {
1092 struct be_cmd_req_hdr hdr;
1093 u16 tx_flow_control;
1094 u16 rx_flow_control;
1095} __packed;
1096
1097/******************** Get Flow Contrl *******************/
1098struct be_cmd_req_get_flow_control {
1099 struct be_cmd_req_hdr hdr;
1100 u32 rsvd;
1101};
1102
1103struct be_cmd_resp_get_flow_control {
1104 struct be_cmd_resp_hdr hdr;
1105 u16 tx_flow_control;
1106 u16 rx_flow_control;
1107} __packed;
1108
1109/******************** Modify EQ Delay *******************/
2632bafd
SP		 1110struct be_set_eqd {
1111 u32 eq_id;
1112 u32 phase;
1113 u32 delay_multiplier;
1114};
1115
6b7c5b94
SP		 1116struct be_cmd_req_modify_eq_delay {
1117 struct be_cmd_req_hdr hdr;
1118 u32 num_eq;
2632bafd 1119 struct be_set_eqd set_eqd[MAX_EVT_QS];
6b7c5b94
SP		 1120} __packed;
1121
6b7c5b94 1122/******************** Get FW Config *******************/
752961a1
SP		 1123/* The HW can come up in either of the following multi-channel modes
1124 * based on the skew/IPL.
1125 */
045508a8 1126#define RDMA_ENABLED 0x4
66064dbc 1127#define QNQ_MODE 0x400
752961a1
SP		 1128#define VNIC_MODE 0x20000
1129#define UMC_ENABLED 0x1000000
6b7c5b94
SP		 1130struct be_cmd_req_query_fw_cfg {
1131 struct be_cmd_req_hdr hdr;
3abcdeda 1132 u32 rsvd[31];
6b7c5b94
SP		 1133};
1134
1135struct be_cmd_resp_query_fw_cfg {
1136 struct be_cmd_resp_hdr hdr;
1137 u32 be_config_number;
1138 u32 asic_revision;
1139 u32 phys_port;
3486be29 1140 u32 function_mode;
6b7c5b94 1141 u32 rsvd[26];
3abcdeda
SP		 1142 u32 function_caps;
1143};
1144
73dea398
PR		 1145/******************** RSS Config ****************************************/
1146/* RSS type Input parameters used to compute RX hash
1147 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1148 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1149 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1150 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1151 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1152 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1153 *
1154 * When multiple RSS types are enabled, HW picks the best hash policy
1155 * based on the type of the received packet.
1156 */
3abcdeda
SP		 1157#define RSS_ENABLE_NONE 0x0
1158#define RSS_ENABLE_IPV4 0x1
1159#define RSS_ENABLE_TCP_IPV4 0x2
1160#define RSS_ENABLE_IPV6 0x4
1161#define RSS_ENABLE_TCP_IPV6 0x8
d3bd3a5e
PR		 1162#define RSS_ENABLE_UDP_IPV4 0x10
1163#define RSS_ENABLE_UDP_IPV6 0x20
3abcdeda 1164
594ad54a
SR		 1165#define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC)
1166#define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3)
1167
3abcdeda
SP		 1168struct be_cmd_req_rss_config {
1169 struct be_cmd_req_hdr hdr;
1170 u32 if_id;
1171 u16 enable_rss;
1172 u16 cpu_table_size_log2;
1173 u32 hash[10];
1174 u8 cpu_table[128];
1175 u8 flush;
1176 u8 rsvd0[3];
6b7c5b94
SP		 1177};
1178
fad9ab2c
SB		 1179/******************** Port Beacon ***************************/
1180
1181#define BEACON_STATE_ENABLED 0x1
1182#define BEACON_STATE_DISABLED 0x0
1183
1184struct be_cmd_req_enable_disable_beacon {
1185 struct be_cmd_req_hdr hdr;
1186 u8 port_num;
1187 u8 beacon_state;
1188 u8 beacon_duration;
1189 u8 status_duration;
1190} __packed;
1191
fad9ab2c
SB		 1192struct be_cmd_req_get_beacon_state {
1193 struct be_cmd_req_hdr hdr;
1194 u8 port_num;
1195 u8 rsvd0;
1196 u16 rsvd1;
1197} __packed;
1198
1199struct be_cmd_resp_get_beacon_state {
1200 struct be_cmd_resp_hdr resp_hdr;
1201 u8 beacon_state;
1202 u8 rsvd0[3];
1203} __packed;
1204
e02cfd96
VV		 1205/* Flashrom related descriptors */
1206#define MAX_FLASH_COMP 32
1207
1208#define OPTYPE_ISCSI_ACTIVE 0
1209#define OPTYPE_REDBOOT 1
1210#define OPTYPE_BIOS 2
1211#define OPTYPE_PXE_BIOS 3
70a7b525 1212#define OPTYPE_OFFSET_SPECIFIED 7
e02cfd96
VV		 1213#define OPTYPE_FCOE_BIOS 8
1214#define OPTYPE_ISCSI_BACKUP 9
1215#define OPTYPE_FCOE_FW_ACTIVE 10
1216#define OPTYPE_FCOE_FW_BACKUP 11
1217#define OPTYPE_NCSI_FW 13
1218#define OPTYPE_REDBOOT_DIR 18
1219#define OPTYPE_REDBOOT_CONFIG 19
1220#define OPTYPE_SH_PHY_FW 21
1221#define OPTYPE_FLASHISM_JUMPVECTOR 22
1222#define OPTYPE_UFI_DIR 23
1223#define OPTYPE_PHY_FW 99
1224
1225#define FLASH_BIOS_IMAGE_MAX_SIZE_g2 262144 /* Max OPTION ROM image sz */
1226#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 262144 /* Max Redboot image sz */
1227#define FLASH_IMAGE_MAX_SIZE_g2 1310720 /* Max firmware image size */
1228
1229#define FLASH_NCSI_IMAGE_MAX_SIZE_g3 262144
1230#define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144
1231#define FLASH_BIOS_IMAGE_MAX_SIZE_g3 524288 /* Max OPTION ROM image sz */
1232#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 1048576 /* Max Redboot image sz */
1233#define FLASH_IMAGE_MAX_SIZE_g3 2097152 /* Max firmware image size */
1234
1235/* Offsets for components on Flash. */
1236#define FLASH_REDBOOT_START_g2 0
1237#define FLASH_FCoE_BIOS_START_g2 524288
1238#define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 1048576
1239#define FLASH_iSCSI_BACKUP_IMAGE_START_g2 2359296
1240#define FLASH_FCoE_PRIMARY_IMAGE_START_g2 3670016
1241#define FLASH_FCoE_BACKUP_IMAGE_START_g2 4980736
1242#define FLASH_iSCSI_BIOS_START_g2 7340032
1243#define FLASH_PXE_BIOS_START_g2 7864320
1244
1245#define FLASH_REDBOOT_START_g3 262144
1246#define FLASH_PHY_FW_START_g3 1310720
1247#define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 2097152
1248#define FLASH_iSCSI_BACKUP_IMAGE_START_g3 4194304
1249#define FLASH_FCoE_PRIMARY_IMAGE_START_g3 6291456
1250#define FLASH_FCoE_BACKUP_IMAGE_START_g3 8388608
1251#define FLASH_iSCSI_BIOS_START_g3 12582912
1252#define FLASH_PXE_BIOS_START_g3 13107200
1253#define FLASH_FCoE_BIOS_START_g3 13631488
1254#define FLASH_NCSI_START_g3 15990784
1255
1256#define IMAGE_NCSI 16
1257#define IMAGE_OPTION_ROM_PXE 32
1258#define IMAGE_OPTION_ROM_FCoE 33
1259#define IMAGE_OPTION_ROM_ISCSI 34
1260#define IMAGE_FLASHISM_JUMPVECTOR 48
1261#define IMAGE_FIRMWARE_iSCSI 160
1262#define IMAGE_FIRMWARE_FCoE 162
1263#define IMAGE_FIRMWARE_BACKUP_iSCSI 176
1264#define IMAGE_FIRMWARE_BACKUP_FCoE 178
1265#define IMAGE_FIRMWARE_PHY 192
1266#define IMAGE_REDBOOT_DIR 208
1267#define IMAGE_REDBOOT_CONFIG 209
1268#define IMAGE_UFI_DIR 210
1269#define IMAGE_BOOT_CODE 224
1270
1271struct controller_id {
1272 u32 vendor;
1273 u32 device;
1274 u32 subvendor;
1275 u32 subdevice;
1276};
1277
1278struct flash_comp {
1279 unsigned long offset;
1280 int optype;
1281 int size;
1282 int img_type;
1283};
1284
1285struct image_hdr {
1286 u32 imageid;
1287 u32 imageoffset;
1288 u32 imagelength;
1289 u32 image_checksum;
1290 u8 image_version[32];
1291};
1292
1293struct flash_file_hdr_g2 {
1294 u8 sign[32];
1295 u32 cksum;
1296 u32 antidote;
1297 struct controller_id cont_id;
1298 u32 file_len;
1299 u32 chunk_num;
1300 u32 total_chunks;
1301 u32 num_imgs;
1302 u8 build[24];
1303};
1304
5d3acd0d
VV		 1305/* First letter of the build version of the image */
1306#define BLD_STR_UFI_TYPE_BE2 '2'
1307#define BLD_STR_UFI_TYPE_BE3 '3'
1308#define BLD_STR_UFI_TYPE_SH '4'
1309
e02cfd96
VV		 1310struct flash_file_hdr_g3 {
1311 u8 sign[52];
1312 u8 ufi_version[4];
1313 u32 file_len;
1314 u32 cksum;
1315 u32 antidote;
1316 u32 num_imgs;
1317 u8 build[24];
1318 u8 asic_type_rev;
1319 u8 rsvd[31];
1320};
1321
1322struct flash_section_hdr {
1323 u32 format_rev;
1324 u32 cksum;
1325 u32 antidote;
1326 u32 num_images;
1327 u8 id_string[128];
1328 u32 rsvd[4];
1329} __packed;
1330
1331struct flash_section_hdr_g2 {
1332 u32 format_rev;
1333 u32 cksum;
1334 u32 antidote;
1335 u32 build_num;
1336 u8 id_string[128];
1337 u32 rsvd[8];
1338} __packed;
1339
1340struct flash_section_entry {
1341 u32 type;
1342 u32 offset;
1343 u32 pad_size;
1344 u32 image_size;
1345 u32 cksum;
1346 u32 entry_point;
1347 u16 optype;
1348 u16 rsvd0;
1349 u32 rsvd1;
1350 u8 ver_data[32];
1351} __packed;
1352
1353struct flash_section_info {
1354 u8 cookie[32];
1355 struct flash_section_hdr fsec_hdr;
1356 struct flash_section_entry fsec_entry[32];
1357} __packed;
1358
1359struct flash_section_info_g2 {
1360 u8 cookie[32];
1361 struct flash_section_hdr_g2 fsec_hdr;
1362 struct flash_section_entry fsec_entry[32];
1363} __packed;
1364
84517482 1365/****************** Firmware Flash ******************/
e02cfd96
VV		 1366#define FLASHROM_OPER_FLASH 1
1367#define FLASHROM_OPER_SAVE 2
1368#define FLASHROM_OPER_REPORT 4
1369#define FLASHROM_OPER_PHY_FLASH 9
1370#define FLASHROM_OPER_PHY_SAVE 10
1371
84517482
AK		 1372struct flashrom_params {
1373 u32 op_code;
1374 u32 op_type;
1375 u32 data_buf_size;
1376 u32 offset;
84517482
AK		 1377};
1378
1379struct be_cmd_write_flashrom {
1380 struct be_cmd_req_hdr hdr;
1381 struct flashrom_params params;
be716446
PR		 1382 u8 data_buf[32768];
1383 u8 rsvd[4];
1384} __packed;
84517482 1385
be716446
PR		 1386/* cmd to read flash crc */
1387struct be_cmd_read_flash_crc {
1388 struct be_cmd_req_hdr hdr;
1389 struct flashrom_params params;
1390 u8 crc[4];
1391 u8 rsvd[4];
96c9b2e4
VV		 1392} __packed;
1393
485bf569
SN		 1394/**************** Lancer Firmware Flash ************/
1395struct amap_lancer_write_obj_context {
1396 u8 write_length[24];
1397 u8 reserved1[7];
1398 u8 eof;
1399} __packed;
1400
1401struct lancer_cmd_req_write_object {
1402 struct be_cmd_req_hdr hdr;
1403 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1404 u32 write_offset;
1405 u8 object_name[104];
1406 u32 descriptor_count;
1407 u32 buf_len;
1408 u32 addr_low;
1409 u32 addr_high;
1410};
1411
f67ef7ba
PR		 1412#define LANCER_NO_RESET_NEEDED 0x00
1413#define LANCER_FW_RESET_NEEDED 0x02
485bf569
SN		 1414struct lancer_cmd_resp_write_object {
1415 u8 opcode;
1416 u8 subsystem;
1417 u8 rsvd1[2];
1418 u8 status;
1419 u8 additional_status;
1420 u8 rsvd2[2];
1421 u32 resp_len;
1422 u32 actual_resp_len;
1423 u32 actual_write_len;
f67ef7ba
PR		 1424 u8 change_status;
1425 u8 rsvd3[3];
485bf569
SN		 1426};
1427
de49bd5a
PR		 1428/************************ Lancer Read FW info **************/
1429#define LANCER_READ_FILE_CHUNK (32*1024)
1430#define LANCER_READ_FILE_EOF_MASK 0x80000000
1431
1432#define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
af5875bd
PR		 1433#define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1434#define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
de49bd5a
PR		 1435
1436struct lancer_cmd_req_read_object {
1437 struct be_cmd_req_hdr hdr;
1438 u32 desired_read_len;
1439 u32 read_offset;
1440 u8 object_name[104];
1441 u32 descriptor_count;
1442 u32 buf_len;
1443 u32 addr_low;
1444 u32 addr_high;
1445};
1446
1447struct lancer_cmd_resp_read_object {
1448 u8 opcode;
1449 u8 subsystem;
1450 u8 rsvd1[2];
1451 u8 status;
1452 u8 additional_status;
1453 u8 rsvd2[2];
1454 u32 resp_len;
1455 u32 actual_resp_len;
1456 u32 actual_read_len;
1457 u32 eof;
1458};
1459
f0613380
KA		 1460struct lancer_cmd_req_delete_object {
1461 struct be_cmd_req_hdr hdr;
1462 u32 rsvd1;
1463 u32 rsvd2;
1464 u8 object_name[104];
1465};
1466
71d8d1b5
AK		 1467/************************ WOL *******************************/
1468struct be_cmd_req_acpi_wol_magic_config{
1469 struct be_cmd_req_hdr hdr;
1470 u32 rsvd0[145];
1471 u8 magic_mac[6];
1472 u8 rsvd2[2];
1473} __packed;
1474
4762f6ce
AK		 1475struct be_cmd_req_acpi_wol_magic_config_v1 {
1476 struct be_cmd_req_hdr hdr;
1477 u8 rsvd0[2];
1478 u8 query_options;
1479 u8 rsvd1[5];
1480 u32 rsvd2[288];
1481 u8 magic_mac[6];
1482 u8 rsvd3[22];
1483} __packed;
1484
1485struct be_cmd_resp_acpi_wol_magic_config_v1 {
1486 struct be_cmd_resp_hdr hdr;
1487 u8 rsvd0[2];
1488 u8 wol_settings;
1489 u8 rsvd1[5];
1490 u32 rsvd2[295];
1491} __packed;
1492
1493#define BE_GET_WOL_CAP 2
1494
1495#define BE_WOL_CAP 0x1
1496#define BE_PME_D0_CAP 0x8
1497#define BE_PME_D1_CAP 0x10
1498#define BE_PME_D2_CAP 0x20
1499#define BE_PME_D3HOT_CAP 0x40
1500#define BE_PME_D3COLD_CAP 0x80
1501
ff33a6e2
S		 1502/********************** LoopBack test *********************/
1503struct be_cmd_req_loopback_test {
1504 struct be_cmd_req_hdr hdr;
1505 u32 loopback_type;
1506 u32 num_pkts;
1507 u64 pattern;
1508 u32 src_port;
1509 u32 dest_port;
1510 u32 pkt_size;
1511};
1512
1513struct be_cmd_resp_loopback_test {
1514 struct be_cmd_resp_hdr resp_hdr;
1515 u32 status;
1516 u32 num_txfer;
1517 u32 num_rx;
1518 u32 miscomp_off;
1519 u32 ticks_compl;
1520};
1521
fced9999
SB		 1522struct be_cmd_req_set_lmode {
1523 struct be_cmd_req_hdr hdr;
1524 u8 src_port;
1525 u8 dest_port;
1526 u8 loopback_type;
1527 u8 loopback_state;
1528};
1529
ff33a6e2
S		 1530/********************** DDR DMA test *********************/
1531struct be_cmd_req_ddrdma_test {
1532 struct be_cmd_req_hdr hdr;
1533 u64 pattern;
1534 u32 byte_count;
1535 u32 rsvd0;
1536 u8 snd_buff[4096];
1537 u8 rsvd1[4096];
1538};
1539
1540struct be_cmd_resp_ddrdma_test {
1541 struct be_cmd_resp_hdr hdr;
1542 u64 pattern;
1543 u32 byte_cnt;
1544 u32 snd_err;
1545 u8 rsvd0[4096];
1546 u8 rcv_buff[4096];
1547};
1548
368c0ca2
SB		 1549/*********************** SEEPROM Read ***********************/
1550
1551#define BE_READ_SEEPROM_LEN 1024
1552struct be_cmd_req_seeprom_read {
1553 struct be_cmd_req_hdr hdr;
1554 u8 rsvd0[BE_READ_SEEPROM_LEN];
1555};
1556
1557struct be_cmd_resp_seeprom_read {
1558 struct be_cmd_req_hdr hdr;
1559 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1560};
1561
ee3cb629
AK		 1562enum {
1563 PHY_TYPE_CX4_10GB = 0,
1564 PHY_TYPE_XFP_10GB,
1565 PHY_TYPE_SFP_1GB,
1566 PHY_TYPE_SFP_PLUS_10GB,
1567 PHY_TYPE_KR_10GB,
1568 PHY_TYPE_KX4_10GB,
1569 PHY_TYPE_BASET_10GB,
1570 PHY_TYPE_BASET_1GB,
42f11cf2
AK		 1571 PHY_TYPE_BASEX_1GB,
1572 PHY_TYPE_SGMII,
6809cee0
RN		 1573 PHY_TYPE_QSFP,
1574 PHY_TYPE_KR4_40GB,
1575 PHY_TYPE_KR2_20GB,
e02cfd96 1576 PHY_TYPE_TN_8022,
ee3cb629
AK		 1577 PHY_TYPE_DISABLED = 255
1578};
1579
42f11cf2
AK		 1580#define BE_SUPPORTED_SPEED_NONE 0
1581#define BE_SUPPORTED_SPEED_10MBPS 1
1582#define BE_SUPPORTED_SPEED_100MBPS 2
1583#define BE_SUPPORTED_SPEED_1GBPS 4
1584#define BE_SUPPORTED_SPEED_10GBPS 8
d6b7a9b7 1585#define BE_SUPPORTED_SPEED_20GBPS 0x10
6809cee0 1586#define BE_SUPPORTED_SPEED_40GBPS 0x20
42f11cf2
AK		 1587
1588#define BE_AN_EN 0x2
1589#define BE_PAUSE_SYM_EN 0x80
1590
1591/* MAC speed valid values */
1592#define SPEED_DEFAULT 0x0
1593#define SPEED_FORCED_10GB 0x1
1594#define SPEED_FORCED_1GB 0x2
1595#define SPEED_AUTONEG_10GB 0x3
1596#define SPEED_AUTONEG_1GB 0x4
1597#define SPEED_AUTONEG_100MB 0x5
1598#define SPEED_AUTONEG_10GB_1GB 0x6
1599#define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1600#define SPEED_AUTONEG_1GB_100MB 0x8
1601#define SPEED_AUTONEG_10MB 0x9
1602#define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1603#define SPEED_AUTONEG_100MB_10MB 0xb
1604#define SPEED_FORCED_100MB 0xc
1605#define SPEED_FORCED_10MB 0xd
1606
ee3cb629
AK		 1607struct be_cmd_req_get_phy_info {
1608 struct be_cmd_req_hdr hdr;
1609 u8 rsvd0[24];
1610};
306f1348
SP		 1611
1612struct be_phy_info {
ee3cb629
AK		 1613 u16 phy_type;
1614 u16 interface_type;
1615 u32 misc_params;
42f11cf2
AK		 1616 u16 ext_phy_details;
1617 u16 rsvd;
1618 u16 auto_speeds_supported;
1619 u16 fixed_speeds_supported;
1620 u32 future_use[2];
ee3cb629
AK		 1621};
1622
306f1348
SP		 1623struct be_cmd_resp_get_phy_info {
1624 struct be_cmd_req_hdr hdr;
1625 struct be_phy_info phy_info;
1626};
1627
e1d18735
AK		 1628/*********************** Set QOS ***********************/
1629
1630#define BE_QOS_BITS_NIC 1
1631
1632struct be_cmd_req_set_qos {
1633 struct be_cmd_req_hdr hdr;
1634 u32 valid_bits;
1635 u32 max_bps_nic;
1636 u32 rsvd[7];
1637};
1638
9e1453c5 1639/*********************** Controller Attributes ***********************/
e02cfd96
VV		 1640struct mgmt_hba_attribs {
1641 u32 rsvd0[24];
1642 u8 controller_model_number[32];
1643 u32 rsvd1[79];
1644 u8 rsvd2[3];
1645 u8 phy_port;
1646 u32 rsvd3[13];
1647} __packed;
1648
1649struct mgmt_controller_attrib {
1650 struct mgmt_hba_attribs hba_attribs;
1651 u32 rsvd0[10];
1652} __packed;
1653
9e1453c5
AK		 1654struct be_cmd_req_cntl_attribs {
1655 struct be_cmd_req_hdr hdr;
1656};
1657
1658struct be_cmd_resp_cntl_attribs {
1659 struct be_cmd_resp_hdr hdr;
1660 struct mgmt_controller_attrib attribs;
1661};
1662
2e588f84
SP		 1663/*********************** Set driver function ***********************/
1664#define CAPABILITY_SW_TIMESTAMPS 2
1665#define CAPABILITY_BE3_NATIVE_ERX_API 4
1666
1667struct be_cmd_req_set_func_cap {
1668 struct be_cmd_req_hdr hdr;
1669 u32 valid_cap_flags;
1670 u32 cap_flags;
1671 u8 rsvd[212];
1672};
1673
1674struct be_cmd_resp_set_func_cap {
1675 struct be_cmd_resp_hdr hdr;
1676 u32 valid_cap_flags;
1677 u32 cap_flags;
1678 u8 rsvd[212];
1679};
1680
f25b119c
PR		 1681/*********************** Function Privileges ***********************/
1682enum {
1683 BE_PRIV_DEFAULT = 0x1,
1684 BE_PRIV_LNKQUERY = 0x2,
1685 BE_PRIV_LNKSTATS = 0x4,
1686 BE_PRIV_LNKMGMT = 0x8,
1687 BE_PRIV_LNKDIAG = 0x10,
1688 BE_PRIV_UTILQUERY = 0x20,
1689 BE_PRIV_FILTMGMT = 0x40,
1690 BE_PRIV_IFACEMGMT = 0x80,
1691 BE_PRIV_VHADM = 0x100,
1692 BE_PRIV_DEVCFG = 0x200,
1693 BE_PRIV_DEVSEC = 0x400
1694};
1695#define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1696 BE_PRIV_DEVSEC)
1697#define MIN_PRIVILEGES BE_PRIV_DEFAULT
1698
1699struct be_cmd_priv_map {
1700 u8 opcode;
1701 u8 subsystem;
1702 u32 priv_mask;
1703};
1704
1705struct be_cmd_req_get_fn_privileges {
1706 struct be_cmd_req_hdr hdr;
1707 u32 rsvd;
1708};
1709
1710struct be_cmd_resp_get_fn_privileges {
1711 struct be_cmd_resp_hdr hdr;
1712 u32 privilege_mask;
1713};
1714
04a06028
SP		 1715struct be_cmd_req_set_fn_privileges {
1716 struct be_cmd_req_hdr hdr;
1717 u32 privileges; /* Used by BE3, SH-R */
1718 u32 privileges_lancer; /* Used by Lancer */
1719};
f25b119c 1720
590c391d
PR		 1721/******************** GET/SET_MACLIST **************************/
1722#define BE_MAX_MAC 64
590c391d
PR		 1723struct be_cmd_req_get_mac_list {
1724 struct be_cmd_req_hdr hdr;
e5e1ee89
PR		 1725 u8 mac_type;
1726 u8 perm_override;
1727 u16 iface_id;
1728 u32 mac_id;
1729 u32 rsvd[3];
1730} __packed;
1731
1732struct get_list_macaddr {
1733 u16 mac_addr_size;
1734 union {
1735 u8 macaddr[6];
1736 struct {
1737 u8 rsvd[2];
1738 u32 mac_id;
1739 } __packed s_mac_id;
1740 } __packed mac_addr_id;
590c391d
PR		 1741} __packed;
1742
1743struct be_cmd_resp_get_mac_list {
1744 struct be_cmd_resp_hdr hdr;
e5e1ee89
PR		 1745 struct get_list_macaddr fd_macaddr; /* Factory default mac */
1746 struct get_list_macaddr macid_macaddr; /* soft mac */
1747 u8 true_mac_count;
1748 u8 pseudo_mac_count;
1749 u8 mac_list_size;
1750 u8 rsvd;
1751 /* perm override mac */
1752 struct get_list_macaddr macaddr_list[BE_MAX_MAC];
590c391d
PR		 1753} __packed;
1754
1755struct be_cmd_req_set_mac_list {
1756 struct be_cmd_req_hdr hdr;
1757 u8 mac_count;
1758 u8 rsvd1;
1759 u16 rsvd2;
1760 struct macaddr mac[BE_MAX_MAC];
1761} __packed;
1762
f1f3ee1b 1763/*********************** HSW Config ***********************/
a77dcb8c
AK		 1764#define PORT_FWD_TYPE_VEPA 0x3
1765#define PORT_FWD_TYPE_VEB 0x2
1766
e7bcbd7b
KA		 1767#define ENABLE_MAC_SPOOFCHK 0x2
1768#define DISABLE_MAC_SPOOFCHK 0x3
1769
f1f3ee1b
AK		 1770struct amap_set_hsw_context {
1771 u8 interface_id[16];
e7bcbd7b
KA		 1772 u8 rsvd0[8];
1773 u8 mac_spoofchk[2];
1774 u8 rsvd1[4];
f1f3ee1b 1775 u8 pvid_valid;
a77dcb8c 1776 u8 pport;
e7bcbd7b 1777 u8 rsvd2[6];
a77dcb8c 1778 u8 port_fwd_type[3];
e7bcbd7b
KA		 1779 u8 rsvd3[5];
1780 u8 vlan_spoofchk[2];
f1f3ee1b 1781 u8 pvid[16];
f1f3ee1b
AK		 1782 u8 rsvd4[32];
1783 u8 rsvd5[32];
e7bcbd7b 1784 u8 rsvd6[32];
f1f3ee1b
AK		 1785} __packed;
1786
1787struct be_cmd_req_set_hsw_config {
1788 struct be_cmd_req_hdr hdr;
1789 u8 context[sizeof(struct amap_set_hsw_context) / 8];
1790} __packed;
1791
f1f3ee1b
AK		 1792struct amap_get_hsw_req_context {
1793 u8 interface_id[16];
1794 u8 rsvd0[14];
1795 u8 pvid_valid;
1796 u8 pport;
1797} __packed;
1798
1799struct amap_get_hsw_resp_context {
a77dcb8c
AK		 1800 u8 rsvd0[6];
1801 u8 port_fwd_type[3];
e7bcbd7b
KA		 1802 u8 rsvd1[5];
1803 u8 spoofchk;
1804 u8 rsvd2;
f1f3ee1b 1805 u8 pvid[16];
f1f3ee1b
AK		 1806 u8 rsvd3[32];
1807 u8 rsvd4[32];
e7bcbd7b 1808 u8 rsvd5[32];
f1f3ee1b
AK		 1809} __packed;
1810
1811struct be_cmd_req_get_hsw_config {
1812 struct be_cmd_req_hdr hdr;
1813 u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1814} __packed;
1815
1816struct be_cmd_resp_get_hsw_config {
1817 struct be_cmd_resp_hdr hdr;
1818 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1819 u32 rsvd;
1820};
1821
b4e32a71
PR		 1822/******************* get port names ***************/
1823struct be_cmd_req_get_port_name {
1824 struct be_cmd_req_hdr hdr;
1825 u32 rsvd0;
1826};
1827
1828struct be_cmd_resp_get_port_name {
1829 struct be_cmd_req_hdr hdr;
1830 u8 port_name[4];
1831};
1832
89a88ab8
AK		 1833/*************** HW Stats Get v1 **********************************/
1834#define BE_TXP_SW_SZ 48
1835struct be_port_rxf_stats_v1 {
1836 u32 rsvd0[12];
1837 u32 rx_crc_errors;
1838 u32 rx_alignment_symbol_errors;
1839 u32 rx_pause_frames;
1840 u32 rx_priority_pause_frames;
1841 u32 rx_control_frames;
1842 u32 rx_in_range_errors;
1843 u32 rx_out_range_errors;
1844 u32 rx_frame_too_long;
18fb06a1 1845 u32 rx_address_filtered;
89a88ab8
AK		 1846 u32 rx_dropped_too_small;
1847 u32 rx_dropped_too_short;
1848 u32 rx_dropped_header_too_small;
1849 u32 rx_dropped_tcp_length;
1850 u32 rx_dropped_runt;
1851 u32 rsvd1[10];
1852 u32 rx_ip_checksum_errs;
1853 u32 rx_tcp_checksum_errs;
1854 u32 rx_udp_checksum_errs;
1855 u32 rsvd2[7];
1856 u32 rx_switched_unicast_packets;
1857 u32 rx_switched_multicast_packets;
1858 u32 rx_switched_broadcast_packets;
1859 u32 rsvd3[3];
1860 u32 tx_pauseframes;
1861 u32 tx_priority_pauseframes;
1862 u32 tx_controlframes;
1863 u32 rsvd4[10];
1864 u32 rxpp_fifo_overflow_drop;
1865 u32 rx_input_fifo_overflow_drop;
1866 u32 pmem_fifo_overflow_drop;
1867 u32 jabber_events;
1868 u32 rsvd5[3];
1869};
1870
1871
1872struct be_rxf_stats_v1 {
1873 struct be_port_rxf_stats_v1 port[4];
1874 u32 rsvd0[2];
1875 u32 rx_drops_no_pbuf;
1876 u32 rx_drops_no_txpb;
1877 u32 rx_drops_no_erx_descr;
1878 u32 rx_drops_no_tpre_descr;
1879 u32 rsvd1[6];
1880 u32 rx_drops_too_many_frags;
1881 u32 rx_drops_invalid_ring;
1882 u32 forwarded_packets;
1883 u32 rx_drops_mtu;
1884 u32 rsvd2[14];
1885};
1886
1887struct be_erx_stats_v1 {
1888 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1889 u32 rsvd[4];
1890};
1891
61000861
AK		 1892struct be_port_rxf_stats_v2 {
1893 u32 rsvd0[10];
1894 u32 roce_bytes_received_lsd;
1895 u32 roce_bytes_received_msd;
1896 u32 rsvd1[5];
1897 u32 roce_frames_received;
1898 u32 rx_crc_errors;
1899 u32 rx_alignment_symbol_errors;
1900 u32 rx_pause_frames;
1901 u32 rx_priority_pause_frames;
1902 u32 rx_control_frames;
1903 u32 rx_in_range_errors;
1904 u32 rx_out_range_errors;
1905 u32 rx_frame_too_long;
1906 u32 rx_address_filtered;
1907 u32 rx_dropped_too_small;
1908 u32 rx_dropped_too_short;
1909 u32 rx_dropped_header_too_small;
1910 u32 rx_dropped_tcp_length;
1911 u32 rx_dropped_runt;
1912 u32 rsvd2[10];
1913 u32 rx_ip_checksum_errs;
1914 u32 rx_tcp_checksum_errs;
1915 u32 rx_udp_checksum_errs;
1916 u32 rsvd3[7];
1917 u32 rx_switched_unicast_packets;
1918 u32 rx_switched_multicast_packets;
1919 u32 rx_switched_broadcast_packets;
1920 u32 rsvd4[3];
1921 u32 tx_pauseframes;
1922 u32 tx_priority_pauseframes;
1923 u32 tx_controlframes;
1924 u32 rsvd5[10];
1925 u32 rxpp_fifo_overflow_drop;
1926 u32 rx_input_fifo_overflow_drop;
1927 u32 pmem_fifo_overflow_drop;
1928 u32 jabber_events;
1929 u32 rsvd6[3];
1930 u32 rx_drops_payload_size;
1931 u32 rx_drops_clipped_header;
1932 u32 rx_drops_crc;
1933 u32 roce_drops_payload_len;
1934 u32 roce_drops_crc;
1935 u32 rsvd7[19];
1936};
1937
1938struct be_rxf_stats_v2 {
1939 struct be_port_rxf_stats_v2 port[4];
1940 u32 rsvd0[2];
1941 u32 rx_drops_no_pbuf;
1942 u32 rx_drops_no_txpb;
1943 u32 rx_drops_no_erx_descr;
1944 u32 rx_drops_no_tpre_descr;
1945 u32 rsvd1[6];
1946 u32 rx_drops_too_many_frags;
1947 u32 rx_drops_invalid_ring;
1948 u32 forwarded_packets;
1949 u32 rx_drops_mtu;
1950 u32 rsvd2[35];
1951};
1952
89a88ab8
AK		 1953struct be_hw_stats_v1 {
1954 struct be_rxf_stats_v1 rxf;
1955 u32 rsvd0[BE_TXP_SW_SZ];
1956 struct be_erx_stats_v1 erx;
1957 struct be_pmem_stats pmem;
0b3f0e7a 1958 u32 rsvd1[18];
89a88ab8
AK		 1959};
1960
1961struct be_cmd_req_get_stats_v1 {
1962 struct be_cmd_req_hdr hdr;
1963 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1964};
1965
1966struct be_cmd_resp_get_stats_v1 {
1967 struct be_cmd_resp_hdr hdr;
1968 struct be_hw_stats_v1 hw_stats;
1969};
1970
61000861
AK		 1971struct be_erx_stats_v2 {
1972 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/
1973 u32 rsvd[3];
1974};
1975
1976struct be_hw_stats_v2 {
1977 struct be_rxf_stats_v2 rxf;
1978 u32 rsvd0[BE_TXP_SW_SZ];
1979 struct be_erx_stats_v2 erx;
1980 struct be_pmem_stats pmem;
1981 u32 rsvd1[18];
1982};
1983
1984struct be_cmd_req_get_stats_v2 {
1985 struct be_cmd_req_hdr hdr;
1986 u8 rsvd[sizeof(struct be_hw_stats_v2)];
1987};
1988
1989struct be_cmd_resp_get_stats_v2 {
1990 struct be_cmd_resp_hdr hdr;
1991 struct be_hw_stats_v2 hw_stats;
1992};
1993
941a77d5
SK		 1994/************** get fat capabilites *******************/
1995#define MAX_MODULES 27
1996#define MAX_MODES 4
1997#define MODE_UART 0
1998#define FW_LOG_LEVEL_DEFAULT 48
1999#define FW_LOG_LEVEL_FATAL 64
2000
2001struct ext_fat_mode {
2002 u8 mode;
2003 u8 rsvd0;
2004 u16 port_mask;
2005 u32 dbg_lvl;
2006 u64 fun_mask;
2007} __packed;
2008
2009struct ext_fat_modules {
2010 u8 modules_str[32];
2011 u32 modules_id;
2012 u32 num_modes;
2013 struct ext_fat_mode trace_lvl[MAX_MODES];
2014} __packed;
2015
2016struct be_fat_conf_params {
2017 u32 max_log_entries;
2018 u32 log_entry_size;
2019 u8 log_type;
2020 u8 max_log_funs;
2021 u8 max_log_ports;
2022 u8 rsvd0;
2023 u32 supp_modes;
2024 u32 num_modules;
2025 struct ext_fat_modules module[MAX_MODULES];
2026} __packed;
2027
2028struct be_cmd_req_get_ext_fat_caps {
2029 struct be_cmd_req_hdr hdr;
2030 u32 parameter_type;
2031};
2032
2033struct be_cmd_resp_get_ext_fat_caps {
2034 struct be_cmd_resp_hdr hdr;
2035 struct be_fat_conf_params get_params;
2036};
2037
2038struct be_cmd_req_set_ext_fat_caps {
2039 struct be_cmd_req_hdr hdr;
2040 struct be_fat_conf_params set_params;
2041};
2042
150d58c7
VV		 2043#define RESOURCE_DESC_SIZE_V0 72
2044#define RESOURCE_DESC_SIZE_V1 88
2045#define PCIE_RESOURCE_DESC_TYPE_V0 0x40
a05f99db 2046#define NIC_RESOURCE_DESC_TYPE_V0 0x41
150d58c7 2047#define PCIE_RESOURCE_DESC_TYPE_V1 0x50
a05f99db 2048#define NIC_RESOURCE_DESC_TYPE_V1 0x51
f93f160b 2049#define PORT_RESOURCE_DESC_TYPE_V1 0x55
150d58c7 2050#define MAX_RESOURCE_DESC 264
d5c18473 2051
f2858738 2052#define IF_CAPS_FLAGS_VALID_SHIFT 0 /* IF caps valid */
10cccf60 2053#define VFT_SHIFT 3 /* VF template */
a401801c
SP		 2054#define IMM_SHIFT 6 /* Immediate */
2055#define NOSV_SHIFT 7 /* No save */
d5c18473 2056
150d58c7 2057struct be_res_desc_hdr {
abb93951
PR		 2058 u8 desc_type;
2059 u8 desc_len;
150d58c7
VV		 2060} __packed;
2061
a401801c
SP		 2062struct be_port_res_desc {
2063 struct be_res_desc_hdr hdr;
2064 u8 rsvd0;
2065 u8 flags;
2066 u8 link_num;
2067 u8 mc_type;
2068 u16 rsvd1;
2069
2070#define NV_TYPE_MASK 0x3 /* bits 0-1 */
2071#define NV_TYPE_DISABLED 1
2072#define NV_TYPE_VXLAN 3
2073#define SOCVID_SHIFT 2 /* Strip outer vlan */
2074#define RCVID_SHIFT 4 /* Report vlan */
2075 u8 nv_flags;
2076 u8 rsvd2;
2077 __le16 nv_port; /* vxlan/gre port */
2078 u32 rsvd3[19];
2079} __packed;
2080
150d58c7
VV		 2081struct be_pcie_res_desc {
2082 struct be_res_desc_hdr hdr;
2083 u8 rsvd0;
2084 u8 flags;
2085 u16 rsvd1;
2086 u8 pf_num;
2087 u8 rsvd2;
2088 u32 rsvd3;
2089 u8 sriov_state;
2090 u8 pf_state;
2091 u8 pf_type;
2092 u8 rsvd4;
2093 u16 num_vfs;
2094 u16 rsvd5;
2095 u32 rsvd6[17];
2096} __packed;
2097
2098struct be_nic_res_desc {
2099 struct be_res_desc_hdr hdr;
abb93951 2100 u8 rsvd1;
a401801c
SP		 2101
2102#define QUN_SHIFT 4 /* QoS is in absolute units */
abb93951
PR		 2103 u8 flags;
2104 u8 vf_num;
2105 u8 rsvd2;
2106 u8 pf_num;
2107 u8 rsvd3;
2108 u16 unicast_mac_count;
2109 u8 rsvd4[6];
2110 u16 mcc_count;
2111 u16 vlan_count;
2112 u16 mcast_mac_count;
2113 u16 txq_count;
2114 u16 rq_count;
2115 u16 rssq_count;
2116 u16 lro_count;
2117 u16 cq_count;
2118 u16 toe_conn_count;
2119 u16 eq_count;
0f77ba73
RN		 2120 u16 vlan_id;
2121 u16 iface_count;
abb93951
PR		 2122 u32 cap_flags;
2123 u8 link_param;
0f77ba73
RN		 2124 u8 rsvd6;
2125 u16 channel_id_param;
abb93951
PR		 2126 u32 bw_min;
2127 u32 bw_max;
2128 u8 acpi_params;
2129 u8 wol_param;
2130 u16 rsvd7;
0f77ba73
RN		 2131 u16 tunnel_iface_count;
2132 u16 direct_tenant_iface_count;
2133 u32 rsvd8[6];
150d58c7 2134} __packed;
abb93951 2135
f93f160b
VV		 2136/************ Multi-Channel type ***********/
2137enum mc_type {
2138 MC_NONE = 0x01,
2139 UMC = 0x02,
2140 FLEX10 = 0x03,
2141 vNIC1 = 0x04,
2142 nPAR = 0x05,
2143 UFP = 0x06,
2144 vNIC2 = 0x07
2145};
2146
f93f160b
VV		 2147/* Is BE in a multi-channel mode */
2148static inline bool be_is_mc(struct be_adapter *adapter)
2149{
2150 return adapter->mc_type > MC_NONE;
2151}
2152
abb93951
PR		 2153struct be_cmd_req_get_func_config {
2154 struct be_cmd_req_hdr hdr;
2155};
2156
2157struct be_cmd_resp_get_func_config {
28710c55 2158 struct be_cmd_resp_hdr hdr;
abb93951 2159 u32 desc_count;
150d58c7 2160 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
abb93951
PR		 2161};
2162
f2858738
VV		 2163enum {
2164 RESOURCE_LIMITS,
2165 RESOURCE_MODIFIABLE
2166};
2167
abb93951
PR		 2168struct be_cmd_req_get_profile_config {
2169 struct be_cmd_req_hdr hdr;
2170 u8 rsvd;
f2858738
VV		 2171#define ACTIVE_PROFILE_TYPE 0x2
2172#define QUERY_MODIFIABLE_FIELDS_TYPE BIT(3)
abb93951
PR		 2173 u8 type;
2174 u16 rsvd1;
2175};
2176
2177struct be_cmd_resp_get_profile_config {
150d58c7 2178 struct be_cmd_resp_hdr hdr;
f2858738
VV		 2179 __le16 desc_count;
2180 u16 rsvd;
150d58c7 2181 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
a05f99db
VV		 2182};
2183
f2858738 2184#define FIELD_MODIFIABLE 0xFFFF
d5c18473
PR		 2185struct be_cmd_req_set_profile_config {
2186 struct be_cmd_req_hdr hdr;
2187 u32 rsvd;
2188 u32 desc_count;
bec84e6b
VV		 2189 u8 desc[2 * RESOURCE_DESC_SIZE_V1];
2190} __packed;
d5c18473 2191
542963b7
VV		 2192struct be_cmd_req_get_active_profile {
2193 struct be_cmd_req_hdr hdr;
2194 u32 rsvd;
2195} __packed;
2196
2197struct be_cmd_resp_get_active_profile {
2198 struct be_cmd_resp_hdr hdr;
2199 u16 active_profile_id;
2200 u16 next_profile_id;
2201} __packed;
2202
dcf7ebba
PR		 2203struct be_cmd_enable_disable_vf {
2204 struct be_cmd_req_hdr hdr;
2205 u8 enable;
2206 u8 rsvd[3];
2207};
2208
68c45a2d
SK		 2209struct be_cmd_req_intr_set {
2210 struct be_cmd_req_hdr hdr;
2211 u8 intr_enabled;
2212 u8 rsvd[3];
2213};
2214
f25b119c
PR		 2215static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
2216{
2217 return flags & adapter->cmd_privileges ? true : false;
2218}
2219
4c876616
SP		 2220/************** Get IFACE LIST *******************/
2221struct be_if_desc {
2222 u32 if_id;
2223 u32 cap_flags;
2224 u32 en_flags;
2225};
2226
2227struct be_cmd_req_get_iface_list {
2228 struct be_cmd_req_hdr hdr;
2229};
2230
2231struct be_cmd_resp_get_iface_list {
2232 struct be_cmd_req_hdr hdr;
2233 u32 if_cnt;
2234 struct be_if_desc if_desc;
2235};
2236
bdce2ad7
SR		 2237/*************** Set logical link ********************/
2238#define PLINK_TRACK_SHIFT 8
2239struct be_cmd_req_set_ll_link {
2240 struct be_cmd_req_hdr hdr;
2241 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */
2242};
2243
a401801c
SP		 2244/************** Manage IFACE Filters *******************/
2245#define OP_CONVERT_NORMAL_TO_TUNNEL 0
2246#define OP_CONVERT_TUNNEL_TO_NORMAL 1
2247
2248struct be_cmd_req_manage_iface_filters {
2249 struct be_cmd_req_hdr hdr;
2250 u8 op;
2251 u8 rsvd0;
2252 u8 flags;
2253 u8 rsvd1;
2254 u32 tunnel_iface_id;
2255 u32 target_iface_id;
2256 u8 mac[6];
2257 u16 vlan_tag;
2258 u32 tenant_id;
2259 u32 filter_id;
2260 u32 cap_flags;
2261 u32 cap_control_flags;
2262} __packed;
2263
31886e87
JP		 2264int be_pci_fnum_get(struct be_adapter *adapter);
2265int be_fw_wait_ready(struct be_adapter *adapter);
2266int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
2267 bool permanent, u32 if_handle, u32 pmac_id);
2268int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id,
2269 u32 *pmac_id, u32 domain);
2270int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id,
2271 u32 domain);
2272int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
2273 u32 *if_handle, u32 domain);
2274int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain);
2275int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo);
2276int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
2277 struct be_queue_info *eq, bool no_delay,
2278 int num_cqe_dma_coalesce);
2279int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq,
2280 struct be_queue_info *cq);
2281int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo);
2282int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq,
2283 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
2284int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
2285 int type);
2286int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q);
2287int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
2288 u8 *link_status, u32 dom);
2289int be_cmd_reset(struct be_adapter *adapter);
2290int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd);
2291int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
2292 struct be_dma_mem *nonemb_cmd);
e97e3cda 2293int be_cmd_get_fw_ver(struct be_adapter *adapter);
2632bafd 2294int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num);
31886e87 2295int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
435452aa 2296 u32 num, u32 domain);
31886e87
JP		 2297int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
2298int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc);
2299int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc);
e97e3cda 2300int be_cmd_query_fw_cfg(struct be_adapter *adapter);
31886e87
JP		 2301int be_cmd_reset_function(struct be_adapter *adapter);
2302int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
33cb0fa7 2303 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey);
31886e87
JP		 2304int be_process_mcc(struct be_adapter *adapter);
2305int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon,
2306 u8 status, u8 state);
2307int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num,
2308 u32 *state);
e36edd9d
ML		 2309int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2310 u8 page_num, u8 *data);
6809cee0 2311int be_cmd_query_cable_type(struct be_adapter *adapter);
21252377 2312int be_cmd_query_sfp_info(struct be_adapter *adapter);
31886e87 2313int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
70a7b525
VV		 2314 u32 flash_oper, u32 flash_opcode, u32 img_offset,
2315 u32 buf_size);
31886e87
JP		 2316int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2317 u32 data_size, u32 data_offset,
2318 const char *obj_name, u32 *data_written,
2319 u8 *change_status, u8 *addn_status);
de49bd5a 2320int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
31886e87
JP		 2321 u32 data_size, u32 data_offset, const char *obj_name,
2322 u32 *data_read, u32 *eof, u8 *addn_status);
f0613380 2323int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name);
3f0d4560 2324int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
70a7b525 2325 u16 img_optype, u32 img_offset, u32 crc_offset);
31886e87
JP		 2326int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2327 struct be_dma_mem *nonemb_cmd);
2328int be_cmd_fw_init(struct be_adapter *adapter);
2329int be_cmd_fw_clean(struct be_adapter *adapter);
2330void be_async_mcc_enable(struct be_adapter *adapter);
2331void be_async_mcc_disable(struct be_adapter *adapter);
2332int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2333 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2334 u64 pattern);
2335int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt,
2336 struct be_dma_mem *cmd);
2337int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2338 struct be_dma_mem *nonemb_cmd);
2339int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2340 u8 loopback_type, u8 enable);
2341int be_cmd_get_phy_info(struct be_adapter *adapter);
0f77ba73
RN		 2342int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate,
2343 u16 link_speed, u8 domain);
31886e87
JP		 2344void be_detect_error(struct be_adapter *adapter);
2345int be_cmd_get_die_temperature(struct be_adapter *adapter);
2346int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
2347int be_cmd_req_native_mode(struct be_adapter *adapter);
2348int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
c5f156de 2349int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
31886e87
JP		 2350int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2351 u32 domain);
2352int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2353 u32 vf_num);
2354int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
b188f090
SR		 2355 bool *pmac_id_active, u32 *pmac_id,
2356 u32 if_handle, u8 domain);
2357int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac,
2358 u32 if_handle, bool active, u32 domain);
31886e87
JP		 2359int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac);
2360int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count,
2361 u32 domain);
2362int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom);
2363int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain,
e7bcbd7b 2364 u16 intf_id, u16 hsw_mode, u8 spoofchk);
31886e87 2365int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain,
e7bcbd7b 2366 u16 intf_id, u8 *mode, bool *spoofchk);
31886e87 2367int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
baaa08d1
VV		 2368int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level);
2369int be_cmd_get_fw_log_level(struct be_adapter *adapter);
31886e87
JP		 2370int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2371 struct be_dma_mem *cmd);
2372int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2373 struct be_dma_mem *cmd,
2374 struct be_fat_conf_params *cfgs);
31886e87
JP		 2375int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask);
2376int lancer_initiate_dump(struct be_adapter *adapter);
f0613380 2377int lancer_delete_dump(struct be_adapter *adapter);
31886e87
JP		 2378bool dump_present(struct be_adapter *adapter);
2379int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
21252377 2380int be_cmd_query_port_name(struct be_adapter *adapter);
92bf14ab
SP		 2381int be_cmd_get_func_config(struct be_adapter *adapter,
2382 struct be_resources *res);
2383int be_cmd_get_profile_config(struct be_adapter *adapter,
f2858738 2384 struct be_resources *res, u8 query, u8 domain);
542963b7 2385int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile);
31886e87
JP		 2386int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
2387 int vf_num);
2388int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
2389int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);
bdce2ad7
SR		 2390int be_cmd_set_logical_link_config(struct be_adapter *adapter,
2391 int link_state, u8 domain);
a401801c
SP		 2392int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port);
2393int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op);
bec84e6b 2394int be_cmd_set_sriov_config(struct be_adapter *adapter,
f2858738
VV		 2395 struct be_resources res, u16 num_vfs,
2396 u16 num_vf_qs);
Linux 6.x block layer and io_uring tree(s)