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tg3: tg3_reset_task() needs to use rtnl_lock to synchronize
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
de750e4c 7 * Copyright (C) 2005-2014 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
a6b7a407 28#include <linux/interrupt.h>
1da177e4
LT		 29#include <linux/ioport.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ethtool.h>
3110f5f5 35#include <linux/mdio.h>
1da177e4 36#include <linux/mii.h>
158d7abd 37#include <linux/phy.h>
a9daf367 38#include <linux/brcmphy.h>
e565eec3 39#include <linux/if.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
de750e4c 97#define TG3_MIN_NUM 137
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
de750e4c 100#define DRV_MODULE_RELDATE "May 11, 2014"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
e565eec3
MC		 211#define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212#define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
213
c6cdf436 214#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 215#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 216
077f849d 217#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 218#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 219#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
221
229b1ad1 222static char version[] =
05dbe005 223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 224
225MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227MODULE_LICENSE("GPL");
228MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 229MODULE_FIRMWARE(FIRMWARE_TG3);
230MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
232
1da177e4
LT		 233static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234module_param(tg3_debug, int, 0);
235MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
236
3d567e0e
NNS		 237#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
239
9baa3c34 240static const struct pci_device_id tg3_pci_tbl[] = {
13185217
HK		 241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
68273712
NS		 343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
13185217
HK		 348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 356 {}
1da177e4
LT		 357};
358
359MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
360
50da859d 361static const struct {
1da177e4 362 const char string[ETH_GSTRING_LEN];
48fa55a0 363} ethtool_stats_keys[] = {
1da177e4
LT		 364 { "rx_octets" },
365 { "rx_fragments" },
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
369 { "rx_fcs_errors" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
376 { "rx_jabbers" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
390
391 { "tx_octets" },
392 { "tx_collisions" },
393
394 { "tx_xon_sent" },
395 { "tx_xoff_sent" },
396 { "tx_flow_control" },
397 { "tx_mac_errors" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
400 { "tx_deferred" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
421 { "tx_discards" },
422 { "tx_errors" },
423
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
426 { "rxbds_empty" },
427 { "rx_discards" },
428 { "rx_errors" },
429 { "rx_threshold_hit" },
430
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
434
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
437 { "nic_irqs" },
438 { "nic_avoided_irqs" },
4452d099
MC		 439 { "nic_tx_threshold_hit" },
440
441 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 442};
443
48fa55a0 444#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 445#define TG3_NVRAM_TEST 0
446#define TG3_LINK_TEST 1
447#define TG3_REGISTER_TEST 2
448#define TG3_MEMORY_TEST 3
449#define TG3_MAC_LOOPB_TEST 4
450#define TG3_PHY_LOOPB_TEST 5
451#define TG3_EXT_LOOPB_TEST 6
452#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 453
454
50da859d 455static const struct {
4cafd3f5 456 const char string[ETH_GSTRING_LEN];
48fa55a0 457} ethtool_test_keys[] = {
93df8b8f
NNS		 458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 466};
467
48fa55a0
MC		 468#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
469
470
b401e9e2
MC		 471static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
472{
473 writel(val, tp->regs + off);
474}
475
476static u32 tg3_read32(struct tg3 *tp, u32 off)
477{
de6f31eb 478 return readl(tp->regs + off);
b401e9e2
MC		 479}
480
0d3031d9
MC		 481static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
482{
483 writel(val, tp->aperegs + off);
484}
485
486static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
487{
de6f31eb 488 return readl(tp->aperegs + off);
0d3031d9
MC		 489}
490
1da177e4
LT		 491static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
492{
6892914f
MC		 493 unsigned long flags;
494
495 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 499}
500
501static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
502{
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
1da177e4
LT		 505}
506
6892914f 507static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 508{
6892914f
MC		 509 unsigned long flags;
510 u32 val;
511
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 return val;
517}
518
519static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
520{
521 unsigned long flags;
522
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
526 return;
527 }
66711e66 528 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
531 return;
1da177e4 532 }
6892914f
MC		 533
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
538
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
541 */
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
543 (val == 0x1)) {
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
546 }
547}
548
549static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
550{
551 unsigned long flags;
552 u32 val;
553
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 return val;
559}
560
b401e9e2
MC		 561/* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
565 */
566static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 567{
63c3a66f 568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 569 /* Non-posted methods */
570 tp->write32(tp, off, val);
571 else {
572 /* Posted method */
573 tg3_write32(tp, off, val);
574 if (usec_wait)
575 udelay(usec_wait);
576 tp->read32(tp, off);
577 }
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
580 */
581 if (usec_wait)
582 udelay(usec_wait);
1da177e4
LT		 583}
584
09ee929c
MC		 585static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
586{
587 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 591 tp->read32_mbox(tp, off);
09ee929c
MC		 592}
593
20094930 594static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 595{
596 void __iomem *mbox = tp->regs + off;
597 writel(val, mbox);
63c3a66f 598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 599 writel(val, mbox);
7e6c63f0
HM		 600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 602 readl(mbox);
603}
604
b5d3772c
MC		 605static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
606{
de6f31eb 607 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 608}
609
610static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
611{
612 writel(val, tp->regs + off + GRCMBOX_BASE);
613}
614
c6cdf436 615#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 616#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 617#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 620
c6cdf436
MC		 621#define tw32(reg, val) tp->write32(tp, reg, val)
622#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 625
626static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
627{
6892914f
MC		 628 unsigned long flags;
629
4153577a 630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
632 return;
633
6892914f 634 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 638
bbadf503
MC		 639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
641 } else {
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 644
bbadf503
MC		 645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
647 }
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 649}
650
1da177e4
LT		 651static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
652{
6892914f
MC		 653 unsigned long flags;
654
4153577a 655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
657 *val = 0;
658 return;
659 }
660
6892914f 661 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 665
bbadf503
MC		 666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
668 } else {
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
671
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
674 }
6892914f 675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 676}
677
0d3031d9
MC		 678static void tg3_ape_lock_init(struct tg3 *tp)
679{
680 int i;
6f5c8f83 681 u32 regbase, bit;
f92d9dc1 682
4153577a 683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 684 regbase = TG3_APE_LOCK_GRANT;
685 else
686 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 687
688 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
690 switch (i) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
696 break;
697 default:
698 if (!tp->pci_fn)
699 bit = APE_LOCK_GRANT_DRIVER;
700 else
701 bit = 1 << tp->pci_fn;
702 }
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 704 }
705
0d3031d9
MC		 706}
707
708static int tg3_ape_lock(struct tg3 *tp, int locknum)
709{
710 int i, off;
711 int ret = 0;
6f5c8f83 712 u32 status, req, gnt, bit;
0d3031d9 713
63c3a66f 714 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 715 return 0;
716
717 switch (locknum) {
6f5c8f83 718 case TG3_APE_LOCK_GPIO:
4153577a 719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 720 return 0;
33f401ae
MC		 721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 723 if (!tp->pci_fn)
724 bit = APE_LOCK_REQ_DRIVER;
725 else
726 bit = 1 << tp->pci_fn;
33f401ae 727 break;
8151ad57
MC		 728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
733 break;
33f401ae
MC		 734 default:
735 return -EINVAL;
0d3031d9
MC		 736 }
737
4153577a 738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
741 } else {
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
744 }
745
0d3031d9
MC		 746 off = 4 * locknum;
747
6f5c8f83 748 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 749
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
f92d9dc1 752 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 753 if (status == bit)
0d3031d9 754 break;
6d446ec3
GS		 755 if (pci_channel_offline(tp->pdev))
756 break;
757
0d3031d9
MC		 758 udelay(10);
759 }
760
6f5c8f83 761 if (status != bit) {
0d3031d9 762 /* Revoke the lock request. */
6f5c8f83 763 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 764 ret = -EBUSY;
765 }
766
767 return ret;
768}
769
770static void tg3_ape_unlock(struct tg3 *tp, int locknum)
771{
6f5c8f83 772 u32 gnt, bit;
0d3031d9 773
63c3a66f 774 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 775 return;
776
777 switch (locknum) {
6f5c8f83 778 case TG3_APE_LOCK_GPIO:
4153577a 779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 780 return;
33f401ae
MC		 781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 783 if (!tp->pci_fn)
784 bit = APE_LOCK_GRANT_DRIVER;
785 else
786 bit = 1 << tp->pci_fn;
33f401ae 787 break;
8151ad57
MC		 788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
793 break;
33f401ae
MC		 794 default:
795 return;
0d3031d9
MC		 796 }
797
4153577a 798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 799 gnt = TG3_APE_LOCK_GRANT;
800 else
801 gnt = TG3_APE_PER_LOCK_GRANT;
802
6f5c8f83 803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 804}
805
b65a372b 806static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 807{
fd6d3f0e
MC		 808 u32 apedata;
809
b65a372b
MC		 810 while (timeout_us) {
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
812 return -EBUSY;
813
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
816 break;
817
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
819
820 udelay(10);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
822 }
823
824 return timeout_us ? 0 : -EBUSY;
825}
826
cf8d55ae
MC		 827static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
828{
829 u32 i, apedata;
830
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
833
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
835 break;
836
837 udelay(10);
838 }
839
840 return i == timeout_us / 10;
841}
842
86449944
MC		 843static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
844 u32 len)
cf8d55ae
MC		 845{
846 int err;
847 u32 i, bufoff, msgoff, maxlen, apedata;
848
849 if (!tg3_flag(tp, APE_HAS_NCSI))
850 return 0;
851
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
854 return -ENODEV;
855
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
858 return -EAGAIN;
859
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
861 TG3_APE_SHMEM_BASE;
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
864
865 while (len) {
866 u32 length;
867
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
870 len -= length;
871
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
874 return -EAGAIN;
875
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
878 if (err)
879 return err;
880
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
885
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
888
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
891
892 base_off += length;
893
894 if (tg3_ape_wait_for_event(tp, 30000))
895 return -EAGAIN;
896
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
900 data++;
901 }
902 }
903
904 return 0;
905}
906
b65a372b
MC		 907static int tg3_ape_send_event(struct tg3 *tp, u32 event)
908{
909 int err;
910 u32 apedata;
fd6d3f0e
MC		 911
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 914 return -EAGAIN;
fd6d3f0e
MC		 915
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 918 return -EAGAIN;
fd6d3f0e
MC		 919
920 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 921 err = tg3_ape_event_lock(tp, 1000);
922 if (err)
923 return err;
fd6d3f0e 924
b65a372b
MC		 925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 927
b65a372b
MC		 928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 930
b65a372b 931 return 0;
fd6d3f0e
MC		 932}
933
934static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
935{
936 u32 event;
937 u32 apedata;
938
939 if (!tg3_flag(tp, ENABLE_APE))
940 return;
941
942 switch (kind) {
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
956
957 event = APE_EVENT_STATUS_STATE_START;
958 break;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
964 */
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
966
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
972 } else
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
974
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
976
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
978 break;
fd6d3f0e
MC		 979 default:
980 return;
981 }
982
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
984
985 tg3_ape_send_event(tp, event);
986}
987
1da177e4
LT		 988static void tg3_disable_ints(struct tg3 *tp)
989{
89aeb3bc
MC		 990 int i;
991
1da177e4
LT		 992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 996}
997
1da177e4
LT		 998static void tg3_enable_ints(struct tg3 *tp)
999{
89aeb3bc 1000 int i;
89aeb3bc 1001
bbe832c0
MC		 1002 tp->irq_sync = 0;
1003 wmb();
1004
1da177e4
LT		 1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 1007
f89f38b8 1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1011
898a56f8 1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1013 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1015
f89f38b8 1016 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1017 }
f19af9c2
MC		 1018
1019 /* Force an initial interrupt */
63c3a66f 1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1023 else
f89f38b8
MC		 1024 tw32(HOSTCC_MODE, tp->coal_now);
1025
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1027}
1028
17375d25 1029static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1030{
17375d25 1031 struct tg3 *tp = tnapi->tp;
898a56f8 1032 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1033 unsigned int work_exists = 0;
1034
1035 /* check for phy events */
63c3a66f 1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1037 if (sblk->status & SD_STATUS_LINK_CHG)
1038 work_exists = 1;
1039 }
f891ea16
MC		 1040
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1043 work_exists = 1;
1044
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1048 work_exists = 1;
1049
1050 return work_exists;
1051}
1052
17375d25 1053/* tg3_int_reenable
04237ddd
MC		 1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
6aa20a22 1056 * which reenables interrupts
1da177e4 1057 */
17375d25 1058static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1059{
17375d25
MC		 1060 struct tg3 *tp = tnapi->tp;
1061
898a56f8 1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1063 mmiowb();
1064
fac9b83e
DM		 1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1068 */
63c3a66f 1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1072}
1073
1da177e4
LT		 1074static void tg3_switch_clocks(struct tg3 *tp)
1075{
f6eb9b1f 1076 u32 clock_ctrl;
1da177e4
LT		 1077 u32 orig_clock_ctrl;
1078
63c3a66f 1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1080 return;
1081
f6eb9b1f
MC		 1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1083
1da177e4
LT		 1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1087 0x1f);
1088 tp->pci_clock_ctrl = clock_ctrl;
1089
63c3a66f 1090 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1094 }
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1097 clock_ctrl |
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1099 40);
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1102 40);
1da177e4 1103 }
b401e9e2 1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1105}
1106
1107#define PHY_BUSY_LOOPS 5000
1108
5c358045
HM		 1109static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1110 u32 *val)
1da177e4
LT		 1111{
1112 u32 frame_val;
1113 unsigned int loops;
1114 int ret;
1115
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1117 tw32_f(MAC_MI_MODE,
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1119 udelay(80);
1120 }
1121
8151ad57
MC		 1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1123
1da177e4
LT		 1124 *val = 0x0;
1125
5c358045 1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1131
1da177e4
LT		 1132 tw32_f(MAC_MI_COM, frame_val);
1133
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1136 udelay(10);
1137 frame_val = tr32(MAC_MI_COM);
1138
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1140 udelay(5);
1141 frame_val = tr32(MAC_MI_COM);
1142 break;
1143 }
1144 loops -= 1;
1145 }
1146
1147 ret = -EBUSY;
1148 if (loops != 0) {
1149 *val = frame_val & MI_COM_DATA_MASK;
1150 ret = 0;
1151 }
1152
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1155 udelay(80);
1156 }
1157
8151ad57
MC		 1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1159
1da177e4
LT		 1160 return ret;
1161}
1162
5c358045
HM		 1163static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1164{
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1166}
1167
1168static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1169 u32 val)
1da177e4
LT		 1170{
1171 u32 frame_val;
1172 unsigned int loops;
1173 int ret;
1174
f07e9af3 1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1177 return 0;
1178
1da177e4
LT		 1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1180 tw32_f(MAC_MI_MODE,
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1182 udelay(80);
1183 }
1184
8151ad57
MC		 1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1186
5c358045 1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1193
1da177e4
LT		 1194 tw32_f(MAC_MI_COM, frame_val);
1195
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1198 udelay(10);
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1201 udelay(5);
1202 frame_val = tr32(MAC_MI_COM);
1203 break;
1204 }
1205 loops -= 1;
1206 }
1207
1208 ret = -EBUSY;
1209 if (loops != 0)
1210 ret = 0;
1211
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1214 udelay(80);
1215 }
1216
8151ad57
MC		 1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1218
1da177e4
LT		 1219 return ret;
1220}
1221
5c358045
HM		 1222static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1223{
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1225}
1226
b0988c15
MC		 1227static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1228{
1229 int err;
1230
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1232 if (err)
1233 goto done;
1234
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1236 if (err)
1237 goto done;
1238
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1241 if (err)
1242 goto done;
1243
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1245
1246done:
1247 return err;
1248}
1249
1250static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1251{
1252 int err;
1253
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1255 if (err)
1256 goto done;
1257
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1259 if (err)
1260 goto done;
1261
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1264 if (err)
1265 goto done;
1266
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1268
1269done:
1270 return err;
1271}
1272
1273static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1274{
1275 int err;
1276
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1278 if (!err)
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1280
1281 return err;
1282}
1283
1284static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1285{
1286 int err;
1287
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1289 if (!err)
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1291
1292 return err;
1293}
1294
15ee95c3
MC		 1295static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1296{
1297 int err;
1298
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1302 if (!err)
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1304
1305 return err;
1306}
1307
b4bd2929
MC		 1308static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1309{
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1312
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1314}
1315
daf3ec68
NNS		 1316static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1317{
1318 u32 val;
1319 int err;
1d36ba45 1320
daf3ec68 1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1322
daf3ec68
NNS		 1323 if (err)
1324 return err;
daf3ec68 1325
7c10ee32 1326 if (enable)
daf3ec68
NNS		 1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1328 else
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1330
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1333
1334 return err;
1335}
1d36ba45 1336
3ab71071
NS		 1337static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1338{
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1341}
1342
95e2869a
MC		 1343static int tg3_bmcr_reset(struct tg3 *tp)
1344{
1345 u32 phy_control;
1346 int limit, err;
1347
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1350 */
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1353 if (err != 0)
1354 return -EBUSY;
1355
1356 limit = 5000;
1357 while (limit--) {
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1359 if (err != 0)
1360 return -EBUSY;
1361
1362 if ((phy_control & BMCR_RESET) == 0) {
1363 udelay(40);
1364 break;
1365 }
1366 udelay(10);
1367 }
d4675b52 1368 if (limit < 0)
95e2869a
MC		 1369 return -EBUSY;
1370
1371 return 0;
1372}
1373
158d7abd
MC		 1374static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1375{
3d16543d 1376 struct tg3 *tp = bp->priv;
158d7abd
MC		 1377 u32 val;
1378
24bb4fb6 1379 spin_lock_bh(&tp->lock);
158d7abd 1380
ead2402c 1381 if (__tg3_readphy(tp, mii_id, reg, &val))
24bb4fb6
MC		 1382 val = -EIO;
1383
1384 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1385
1386 return val;
1387}
1388
1389static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1390{
3d16543d 1391 struct tg3 *tp = bp->priv;
24bb4fb6 1392 u32 ret = 0;
158d7abd 1393
24bb4fb6 1394 spin_lock_bh(&tp->lock);
158d7abd 1395
ead2402c 1396 if (__tg3_writephy(tp, mii_id, reg, val))
24bb4fb6 1397 ret = -EIO;
158d7abd 1398
24bb4fb6
MC		 1399 spin_unlock_bh(&tp->lock);
1400
1401 return ret;
158d7abd
MC		 1402}
1403
9c61d6bc 1404static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1405{
1406 u32 val;
fcb389df 1407 struct phy_device *phydev;
a9daf367 1408
ead2402c 1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
fcb389df 1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
fcb389df
MC		 1413 val = MAC_PHYCFG2_50610_LED_MODES;
1414 break;
6a443a0f 1415 case PHY_ID_BCMAC131:
fcb389df
MC		 1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1417 break;
6a443a0f 1418 case PHY_ID_RTL8211C:
fcb389df
MC		 1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1420 break;
6a443a0f 1421 case PHY_ID_RTL8201E:
fcb389df
MC		 1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1423 break;
1424 default:
a9daf367 1425 return;
fcb389df
MC		 1426 }
1427
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1430
1431 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1435 tw32(MAC_PHYCFG1, val);
1436
1437 return;
1438 }
1439
63c3a66f 1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1447
1448 tw32(MAC_PHYCFG2, val);
a9daf367 1449
bb85fbb6
MC		 1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1458 }
bb85fbb6
MC		 1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
a9daf367 1462
a9daf367
MC		 1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1481 }
1482 tw32(MAC_EXT_RGMII_MODE, val);
1483}
1484
158d7abd
MC		 1485static void tg3_mdio_start(struct tg3 *tp)
1486{
158d7abd
MC		 1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1489 udelay(80);
a9daf367 1490
63c3a66f 1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1492 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1493 tg3_mdio_config_5785(tp);
1494}
1495
1496static int tg3_mdio_init(struct tg3 *tp)
1497{
1498 int i;
1499 u32 reg;
1500 struct phy_device *phydev;
1501
63c3a66f 1502 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1503 u32 is_serdes;
882e9793 1504
69f11c99 1505 tp->phy_addr = tp->pci_fn + 1;
882e9793 1506
4153577a 1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1509 else
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1512 if (is_serdes)
1513 tp->phy_addr += 7;
ee002b64
HM		 1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1515 int addr;
1516
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1518 if (addr < 0)
1519 return addr;
1520 tp->phy_addr = addr;
882e9793 1521 } else
3f0e3ad7 1522 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1523
158d7abd
MC		 1524 tg3_mdio_start(tp);
1525
63c3a66f 1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1527 return 0;
1528
298cf9be
LB		 1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1531 return -ENOMEM;
158d7abd 1532
298cf9be
LB		 1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
ead2402c 1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
298cf9be 1541 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1542
1543 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1544 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1545
1546 /* The bus registration will look for all the PHYs on the mdio bus.
1547 * Unfortunately, it does not ensure the PHY is powered up before
1548 * accessing the PHY ID registers. A chip reset is the
1549 * quickest way to bring the device back to an operational state..
1550 */
1551 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1552 tg3_bmcr_reset(tp);
1553
298cf9be 1554 i = mdiobus_register(tp->mdio_bus);
a9daf367 1555 if (i) {
ab96b241 1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1557 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1558 return i;
1559 }
158d7abd 1560
ead2402c 1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
a9daf367 1562
9c61d6bc 1563 if (!phydev || !phydev->drv) {
ab96b241 1564 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1565 mdiobus_unregister(tp->mdio_bus);
1566 mdiobus_free(tp->mdio_bus);
1567 return -ENODEV;
1568 }
1569
1570 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1571 case PHY_ID_BCM57780:
321d32a0 1572 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1573 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1574 break;
6a443a0f
MC		 1575 case PHY_ID_BCM50610:
1576 case PHY_ID_BCM50610M:
32e5a8d6 1577 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1578 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1579 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1580 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1582 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1584 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1587 /* fallthru */
6a443a0f 1588 case PHY_ID_RTL8211C:
fcb389df 1589 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1590 break;
6a443a0f
MC		 1591 case PHY_ID_RTL8201E:
1592 case PHY_ID_BCMAC131:
a9daf367 1593 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1594 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1595 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1596 break;
1597 }
1598
63c3a66f 1599 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1600
4153577a 1601 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1602 tg3_mdio_config_5785(tp);
a9daf367
MC		 1603
1604 return 0;
158d7abd
MC		 1605}
1606
1607static void tg3_mdio_fini(struct tg3 *tp)
1608{
63c3a66f
JP		 1609 if (tg3_flag(tp, MDIOBUS_INITED)) {
1610 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1611 mdiobus_unregister(tp->mdio_bus);
1612 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1613 }
1614}
1615
4ba526ce
MC		 1616/* tp->lock is held. */
1617static inline void tg3_generate_fw_event(struct tg3 *tp)
1618{
1619 u32 val;
1620
1621 val = tr32(GRC_RX_CPU_EVENT);
1622 val |= GRC_RX_CPU_DRIVER_EVENT;
1623 tw32_f(GRC_RX_CPU_EVENT, val);
1624
1625 tp->last_event_jiffies = jiffies;
1626}
1627
1628#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1629
95e2869a
MC		 1630/* tp->lock is held. */
1631static void tg3_wait_for_event_ack(struct tg3 *tp)
1632{
1633 int i;
4ba526ce
MC		 1634 unsigned int delay_cnt;
1635 long time_remain;
1636
1637 /* If enough time has passed, no wait is necessary. */
1638 time_remain = (long)(tp->last_event_jiffies + 1 +
1639 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1640 (long)jiffies;
1641 if (time_remain < 0)
1642 return;
1643
1644 /* Check if we can shorten the wait time. */
1645 delay_cnt = jiffies_to_usecs(time_remain);
1646 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1647 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1648 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1649
4ba526ce 1650 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1652 break;
6d446ec3
GS		 1653 if (pci_channel_offline(tp->pdev))
1654 break;
1655
4ba526ce 1656 udelay(8);
95e2869a
MC		 1657 }
1658}
1659
1660/* tp->lock is held. */
b28f389d 1661static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1662{
b28f389d 1663 u32 reg, val;
95e2869a
MC		 1664
1665 val = 0;
1666 if (!tg3_readphy(tp, MII_BMCR, &reg))
1667 val = reg << 16;
1668 if (!tg3_readphy(tp, MII_BMSR, &reg))
1669 val |= (reg & 0xffff);
b28f389d 1670 *data++ = val;
95e2869a
MC		 1671
1672 val = 0;
1673 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1674 val = reg << 16;
1675 if (!tg3_readphy(tp, MII_LPA, &reg))
1676 val |= (reg & 0xffff);
b28f389d 1677 *data++ = val;
95e2869a
MC		 1678
1679 val = 0;
f07e9af3 1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1681 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1682 val = reg << 16;
1683 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1684 val |= (reg & 0xffff);
1685 }
b28f389d 1686 *data++ = val;
95e2869a
MC		 1687
1688 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1689 val = reg << 16;
1690 else
1691 val = 0;
b28f389d
MC		 1692 *data++ = val;
1693}
1694
1695/* tp->lock is held. */
1696static void tg3_ump_link_report(struct tg3 *tp)
1697{
1698 u32 data[4];
1699
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1701 return;
1702
1703 tg3_phy_gather_ump_data(tp, data);
1704
1705 tg3_wait_for_event_ack(tp);
1706
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1713
4ba526ce 1714 tg3_generate_fw_event(tp);
95e2869a
MC		 1715}
1716
8d5a89b3
MC		 1717/* tp->lock is held. */
1718static void tg3_stop_fw(struct tg3 *tp)
1719{
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1721 /* Wait for RX cpu to ACK the previous event. */
1722 tg3_wait_for_event_ack(tp);
1723
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1725
1726 tg3_generate_fw_event(tp);
1727
1728 /* Wait for RX cpu to ACK this event. */
1729 tg3_wait_for_event_ack(tp);
1730 }
1731}
1732
fd6d3f0e
MC		 1733/* tp->lock is held. */
1734static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1735{
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1737 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1738
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1740 switch (kind) {
1741 case RESET_KIND_INIT:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1743 DRV_STATE_START);
1744 break;
1745
1746 case RESET_KIND_SHUTDOWN:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1748 DRV_STATE_UNLOAD);
1749 break;
1750
1751 case RESET_KIND_SUSPEND:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1753 DRV_STATE_SUSPEND);
1754 break;
1755
1756 default:
1757 break;
1758 }
1759 }
fd6d3f0e
MC		 1760}
1761
1762/* tp->lock is held. */
1763static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1764{
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1766 switch (kind) {
1767 case RESET_KIND_INIT:
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1769 DRV_STATE_START_DONE);
1770 break;
1771
1772 case RESET_KIND_SHUTDOWN:
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1774 DRV_STATE_UNLOAD_DONE);
1775 break;
1776
1777 default:
1778 break;
1779 }
1780 }
fd6d3f0e
MC		 1781}
1782
1783/* tp->lock is held. */
1784static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1785{
1786 if (tg3_flag(tp, ENABLE_ASF)) {
1787 switch (kind) {
1788 case RESET_KIND_INIT:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1790 DRV_STATE_START);
1791 break;
1792
1793 case RESET_KIND_SHUTDOWN:
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1795 DRV_STATE_UNLOAD);
1796 break;
1797
1798 case RESET_KIND_SUSPEND:
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1800 DRV_STATE_SUSPEND);
1801 break;
1802
1803 default:
1804 break;
1805 }
1806 }
1807}
1808
1809static int tg3_poll_fw(struct tg3 *tp)
1810{
1811 int i;
1812 u32 val;
1813
df465abf
NS		 1814 if (tg3_flag(tp, NO_FWARE_REPORTED))
1815 return 0;
1816
7e6c63f0
HM		 1817 if (tg3_flag(tp, IS_SSB_CORE)) {
1818 /* We don't use firmware. */
1819 return 0;
1820 }
1821
4153577a 1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1823 /* Wait up to 20ms for init done. */
1824 for (i = 0; i < 200; i++) {
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1826 return 0;
6d446ec3
GS		 1827 if (pci_channel_offline(tp->pdev))
1828 return -ENODEV;
1829
fd6d3f0e
MC		 1830 udelay(100);
1831 }
1832 return -ENODEV;
1833 }
1834
1835 /* Wait for firmware initialization to complete. */
1836 for (i = 0; i < 100000; i++) {
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1838 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1839 break;
6d446ec3
GS		 1840 if (pci_channel_offline(tp->pdev)) {
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1842 tg3_flag_set(tp, NO_FWARE_REPORTED);
1843 netdev_info(tp->dev, "No firmware running\n");
1844 }
1845
1846 break;
1847 }
1848
fd6d3f0e
MC		 1849 udelay(10);
1850 }
1851
1852 /* Chip might not be fitted with firmware. Some Sun onboard
1853 * parts are configured like that. So don't signal the timeout
1854 * of the above loop as an error, but do report the lack of
1855 * running firmware once.
1856 */
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1858 tg3_flag_set(tp, NO_FWARE_REPORTED);
1859
1860 netdev_info(tp->dev, "No firmware running\n");
1861 }
1862
4153577a 1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1864 /* The 57765 A0 needs a little more
1865 * time to do some important work.
1866 */
1867 mdelay(10);
1868 }
1869
1870 return 0;
1871}
1872
95e2869a
MC		 1873static void tg3_link_report(struct tg3 *tp)
1874{
1875 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1876 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1877 tg3_ump_link_report(tp);
1878 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1880 (tp->link_config.active_speed == SPEED_1000 ?
1881 1000 :
1882 (tp->link_config.active_speed == SPEED_100 ?
1883 100 : 10)),
1884 (tp->link_config.active_duplex == DUPLEX_FULL ?
1885 "full" : "half"));
1886
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1889 "on" : "off",
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1891 "on" : "off");
47007831
MC		 1892
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1894 netdev_info(tp->dev, "EEE is %s\n",
1895 tp->setlpicnt ? "enabled" : "disabled");
1896
95e2869a
MC		 1897 tg3_ump_link_report(tp);
1898 }
84421b99
NS		 1899
1900 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1901}
1902
fdad8de4
NS		 1903static u32 tg3_decode_flowctrl_1000T(u32 adv)
1904{
1905 u32 flowctrl = 0;
1906
1907 if (adv & ADVERTISE_PAUSE_CAP) {
1908 flowctrl |= FLOW_CTRL_RX;
1909 if (!(adv & ADVERTISE_PAUSE_ASYM))
1910 flowctrl |= FLOW_CTRL_TX;
1911 } else if (adv & ADVERTISE_PAUSE_ASYM)
1912 flowctrl |= FLOW_CTRL_TX;
1913
1914 return flowctrl;
1915}
1916
95e2869a
MC		 1917static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1918{
1919 u16 miireg;
1920
e18ce346 1921 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1922 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1923 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1924 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1925 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1926 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1927 else
1928 miireg = 0;
1929
1930 return miireg;
1931}
1932
fdad8de4
NS		 1933static u32 tg3_decode_flowctrl_1000X(u32 adv)
1934{
1935 u32 flowctrl = 0;
1936
1937 if (adv & ADVERTISE_1000XPAUSE) {
1938 flowctrl |= FLOW_CTRL_RX;
1939 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1940 flowctrl |= FLOW_CTRL_TX;
1941 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1942 flowctrl |= FLOW_CTRL_TX;
1943
1944 return flowctrl;
1945}
1946
95e2869a
MC		 1947static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1948{
1949 u8 cap = 0;
1950
f3791cdf
MC		 1951 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1952 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1953 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1954 if (lcladv & ADVERTISE_1000XPAUSE)
1955 cap = FLOW_CTRL_RX;
1956 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1957 cap = FLOW_CTRL_TX;
95e2869a
MC		 1958 }
1959
1960 return cap;
1961}
1962
f51f3562 1963static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1964{
b02fd9e3 1965 u8 autoneg;
f51f3562 1966 u8 flowctrl = 0;
95e2869a
MC		 1967 u32 old_rx_mode = tp->rx_mode;
1968 u32 old_tx_mode = tp->tx_mode;
1969
63c3a66f 1970 if (tg3_flag(tp, USE_PHYLIB))
ead2402c 1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
b02fd9e3
MC		 1972 else
1973 autoneg = tp->link_config.autoneg;
1974
63c3a66f 1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1977 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1978 else
bc02ff95 1979 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1980 } else
1981 flowctrl = tp->link_config.flowctrl;
95e2869a 1982
f51f3562 1983 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1984
e18ce346 1985 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1987 else
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1989
f51f3562 1990 if (old_rx_mode != tp->rx_mode)
95e2869a 1991 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1992
e18ce346 1993 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1995 else
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1997
f51f3562 1998 if (old_tx_mode != tp->tx_mode)
95e2869a 1999 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 2000}
2001
b02fd9e3
MC		 2002static void tg3_adjust_link(struct net_device *dev)
2003{
2004 u8 oldflowctrl, linkmesg = 0;
2005 u32 mac_mode, lcl_adv, rmt_adv;
2006 struct tg3 *tp = netdev_priv(dev);
ead2402c 2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2008
24bb4fb6 2009 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 2010
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2012 MAC_MODE_HALF_DUPLEX);
2013
2014 oldflowctrl = tp->link_config.active_flowctrl;
2015
2016 if (phydev->link) {
2017 lcl_adv = 0;
2018 rmt_adv = 0;
2019
2020 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2021 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2022 else if (phydev->speed == SPEED_1000 ||
4153577a 2023 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2024 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2025 else
2026 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2027
2028 if (phydev->duplex == DUPLEX_HALF)
2029 mac_mode |= MAC_MODE_HALF_DUPLEX;
2030 else {
f88788f0 2031 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2032 tp->link_config.flowctrl);
2033
2034 if (phydev->pause)
2035 rmt_adv = LPA_PAUSE_CAP;
2036 if (phydev->asym_pause)
2037 rmt_adv |= LPA_PAUSE_ASYM;
2038 }
2039
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2041 } else
2042 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2043
2044 if (mac_mode != tp->mac_mode) {
2045 tp->mac_mode = mac_mode;
2046 tw32_f(MAC_MODE, tp->mac_mode);
2047 udelay(40);
2048 }
2049
4153577a 2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2051 if (phydev->speed == SPEED_10)
2052 tw32(MAC_MI_STAT,
2053 MAC_MI_STAT_10MBPS_MODE |
2054 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2055 else
2056 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2057 }
2058
b02fd9e3
MC		 2059 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2060 tw32(MAC_TX_LENGTHS,
2061 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2062 (6 << TX_LENGTHS_IPG_SHIFT) |
2063 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2064 else
2065 tw32(MAC_TX_LENGTHS,
2066 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2067 (6 << TX_LENGTHS_IPG_SHIFT) |
2068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2069
34655ad6 2070 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2071 phydev->speed != tp->link_config.active_speed ||
2072 phydev->duplex != tp->link_config.active_duplex ||
2073 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2074 linkmesg = 1;
b02fd9e3 2075
34655ad6 2076 tp->old_link = phydev->link;
b02fd9e3
MC		 2077 tp->link_config.active_speed = phydev->speed;
2078 tp->link_config.active_duplex = phydev->duplex;
2079
24bb4fb6 2080 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2081
2082 if (linkmesg)
2083 tg3_link_report(tp);
2084}
2085
2086static int tg3_phy_init(struct tg3 *tp)
2087{
2088 struct phy_device *phydev;
2089
f07e9af3 2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2091 return 0;
2092
2093 /* Bring the PHY back to a known state. */
2094 tg3_bmcr_reset(tp);
2095
ead2402c 2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3
MC		 2097
2098 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2100 tg3_adjust_link, phydev->interface);
b02fd9e3 2101 if (IS_ERR(phydev)) {
ab96b241 2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2103 return PTR_ERR(phydev);
2104 }
2105
b02fd9e3 2106 /* Mask with MAC supported features. */
9c61d6bc
MC		 2107 switch (phydev->interface) {
2108 case PHY_INTERFACE_MODE_GMII:
2109 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2111 phydev->supported &= (PHY_GBIT_FEATURES |
2112 SUPPORTED_Pause |
2113 SUPPORTED_Asym_Pause);
2114 break;
2115 }
2116 /* fallthru */
9c61d6bc
MC		 2117 case PHY_INTERFACE_MODE_MII:
2118 phydev->supported &= (PHY_BASIC_FEATURES |
2119 SUPPORTED_Pause |
2120 SUPPORTED_Asym_Pause);
2121 break;
2122 default:
ead2402c 2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
9c61d6bc
MC		 2124 return -EINVAL;
2125 }
2126
f07e9af3 2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2128
2129 phydev->advertising = phydev->supported;
2130
b02fd9e3
MC		 2131 return 0;
2132}
2133
2134static void tg3_phy_start(struct tg3 *tp)
2135{
2136 struct phy_device *phydev;
2137
f07e9af3 2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2139 return;
2140
ead2402c 2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2142
80096068
MC		 2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2145 phydev->speed = tp->link_config.speed;
2146 phydev->duplex = tp->link_config.duplex;
2147 phydev->autoneg = tp->link_config.autoneg;
2148 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2149 }
2150
2151 phy_start(phydev);
2152
2153 phy_start_aneg(phydev);
2154}
2155
2156static void tg3_phy_stop(struct tg3 *tp)
2157{
f07e9af3 2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2159 return;
2160
ead2402c 2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 2162}
2163
2164static void tg3_phy_fini(struct tg3 *tp)
2165{
f07e9af3 2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
ead2402c 2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
f07e9af3 2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2169 }
2170}
2171
941ec90f
MC		 2172static int tg3_phy_set_extloopbk(struct tg3 *tp)
2173{
2174 int err;
2175 u32 val;
2176
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2178 return 0;
2179
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2181 /* Cannot do read-modify-write on 5401 */
2182 err = tg3_phy_auxctl_write(tp,
2183 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2184 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2185 0x4c20);
2186 goto done;
2187 }
2188
2189 err = tg3_phy_auxctl_read(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2191 if (err)
2192 return err;
2193
2194 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2195 err = tg3_phy_auxctl_write(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2197
2198done:
2199 return err;
2200}
2201
7f97a4bd
MC		 2202static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2203{
2204 u32 phytest;
2205
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2207 u32 phy;
2208
2209 tg3_writephy(tp, MII_TG3_FET_TEST,
2210 phytest | MII_TG3_FET_SHADOW_EN);
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2212 if (enable)
2213 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2214 else
2215 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2217 }
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2219 }
2220}
2221
6833c043
MC		 2222static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2223{
2224 u32 reg;
2225
63c3a66f
JP		 2226 if (!tg3_flag(tp, 5705_PLUS) ||
2227 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2229 return;
2230
f07e9af3 2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2232 tg3_phy_fet_toggle_apd(tp, enable);
2233 return;
2234 }
2235
3ab71071 2236 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
6833c043
MC		 2237 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2238 MII_TG3_MISC_SHDW_SCR5_SDTL |
2239 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2241 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2242
3ab71071 2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
6833c043
MC		 2244
2245
3ab71071 2246 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
6833c043
MC		 2247 if (enable)
2248 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2249
3ab71071 2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
6833c043
MC		 2251}
2252
953c96e0 2253static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2254{
2255 u32 phy;
2256
63c3a66f 2257 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2259 return;
2260
f07e9af3 2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2262 u32 ephy;
2263
535ef6e1
MC		 2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2265 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2266
2267 tg3_writephy(tp, MII_TG3_FET_TEST,
2268 ephy | MII_TG3_FET_SHADOW_EN);
2269 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2270 if (enable)
535ef6e1 2271 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2272 else
535ef6e1
MC		 2273 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2274 tg3_writephy(tp, reg, phy);
9ef8ca99 2275 }
535ef6e1 2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2277 }
2278 } else {
15ee95c3
MC		 2279 int ret;
2280
2281 ret = tg3_phy_auxctl_read(tp,
2282 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2283 if (!ret) {
9ef8ca99
MC		 2284 if (enable)
2285 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2286 else
2287 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2288 tg3_phy_auxctl_write(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2290 }
2291 }
2292}
2293
1da177e4
LT		 2294static void tg3_phy_set_wirespeed(struct tg3 *tp)
2295{
15ee95c3 2296 int ret;
1da177e4
LT		 2297 u32 val;
2298
f07e9af3 2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2300 return;
2301
15ee95c3
MC		 2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2303 if (!ret)
b4bd2929
MC		 2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2305 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2306}
2307
b2a5c19c
MC		 2308static void tg3_phy_apply_otp(struct tg3 *tp)
2309{
2310 u32 otp, phy;
2311
2312 if (!tp->phy_otp)
2313 return;
2314
2315 otp = tp->phy_otp;
2316
daf3ec68 2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2318 return;
b2a5c19c
MC		 2319
2320 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2321 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2323
2324 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2325 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2327
2328 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2329 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2331
2332 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2334
2335 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2337
2338 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2339 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2341
daf3ec68 2342 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2343}
2344
400dfbaa
NS		 2345static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2346{
2347 u32 val;
2348 struct ethtool_eee *dest = &tp->eee;
2349
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2351 return;
2352
2353 if (eee)
2354 dest = eee;
2355
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2357 return;
2358
2359 /* Pull eee_active */
2360 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2361 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2362 dest->eee_active = 1;
2363 } else
2364 dest->eee_active = 0;
2365
2366 /* Pull lp advertised settings */
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2368 return;
2369 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2370
2371 /* Pull advertised and eee_enabled settings */
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2373 return;
2374 dest->eee_enabled = !!val;
2375 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2376
2377 /* Pull tx_lpi_enabled */
2378 val = tr32(TG3_CPMU_EEE_MODE);
2379 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2380
2381 /* Pull lpi timer value */
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2383}
2384
953c96e0 2385static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2386{
2387 u32 val;
2388
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2390 return;
2391
2392 tp->setlpicnt = 0;
2393
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2395 current_link_up &&
a6b68dab
MC		 2396 tp->link_config.active_duplex == DUPLEX_FULL &&
2397 (tp->link_config.active_speed == SPEED_100 ||
2398 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2399 u32 eeectl;
2400
2401 if (tp->link_config.active_speed == SPEED_1000)
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2403 else
2404 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2405
2406 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2407
400dfbaa
NS		 2408 tg3_eee_pull_config(tp, NULL);
2409 if (tp->eee.eee_active)
52b02d04
MC		 2410 tp->setlpicnt = 2;
2411 }
2412
2413 if (!tp->setlpicnt) {
953c96e0 2414 if (current_link_up &&
daf3ec68 2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2417 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2418 }
2419
52b02d04
MC		 2420 val = tr32(TG3_CPMU_EEE_MODE);
2421 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2422 }
2423}
2424
b0c5943f
MC		 2425static void tg3_phy_eee_enable(struct tg3 *tp)
2426{
2427 u32 val;
2428
2429 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2430 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2431 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2432 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2434 val = MII_TG3_DSP_TAP26_ALNOKO |
2435 MII_TG3_DSP_TAP26_RMRXSTO;
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2437 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2438 }
2439
2440 val = tr32(TG3_CPMU_EEE_MODE);
2441 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2442}
2443
1da177e4
LT		 2444static int tg3_wait_macro_done(struct tg3 *tp)
2445{
2446 int limit = 100;
2447
2448 while (limit--) {
2449 u32 tmp32;
2450
f08aa1a8 2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2452 if ((tmp32 & 0x1000) == 0)
2453 break;
2454 }
2455 }
d4675b52 2456 if (limit < 0)
1da177e4
LT		 2457 return -EBUSY;
2458
2459 return 0;
2460}
2461
2462static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2463{
2464 static const u32 test_pat[4][6] = {
2465 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2466 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2467 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2468 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2469 };
2470 int chan;
2471
2472 for (chan = 0; chan < 4; chan++) {
2473 int i;
2474
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2476 (chan * 0x2000) | 0x0200);
f08aa1a8 2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2478
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2481 test_pat[chan][i]);
2482
f08aa1a8 2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2484 if (tg3_wait_macro_done(tp)) {
2485 *resetp = 1;
2486 return -EBUSY;
2487 }
2488
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2490 (chan * 0x2000) | 0x0200);
f08aa1a8 2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2492 if (tg3_wait_macro_done(tp)) {
2493 *resetp = 1;
2494 return -EBUSY;
2495 }
2496
f08aa1a8 2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2498 if (tg3_wait_macro_done(tp)) {
2499 *resetp = 1;
2500 return -EBUSY;
2501 }
2502
2503 for (i = 0; i < 6; i += 2) {
2504 u32 low, high;
2505
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2508 tg3_wait_macro_done(tp)) {
2509 *resetp = 1;
2510 return -EBUSY;
2511 }
2512 low &= 0x7fff;
2513 high &= 0x000f;
2514 if (low != test_pat[chan][i] ||
2515 high != test_pat[chan][i+1]) {
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2519
2520 return -EBUSY;
2521 }
2522 }
2523 }
2524
2525 return 0;
2526}
2527
2528static int tg3_phy_reset_chanpat(struct tg3 *tp)
2529{
2530 int chan;
2531
2532 for (chan = 0; chan < 4; chan++) {
2533 int i;
2534
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2536 (chan * 0x2000) | 0x0200);
f08aa1a8 2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2538 for (i = 0; i < 6; i++)
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2541 if (tg3_wait_macro_done(tp))
2542 return -EBUSY;
2543 }
2544
2545 return 0;
2546}
2547
2548static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2549{
2550 u32 reg32, phy9_orig;
2551 int retries, do_phy_reset, err;
2552
2553 retries = 10;
2554 do_phy_reset = 1;
2555 do {
2556 if (do_phy_reset) {
2557 err = tg3_bmcr_reset(tp);
2558 if (err)
2559 return err;
2560 do_phy_reset = 0;
2561 }
2562
2563 /* Disable transmitter and interrupt. */
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2565 continue;
2566
2567 reg32 |= 0x3000;
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2569
2570 /* Set full-duplex, 1000 mbps. */
2571 tg3_writephy(tp, MII_BMCR,
221c5637 2572 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2573
2574 /* Set to master mode. */
221c5637 2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2576 continue;
2577
221c5637
MC		 2578 tg3_writephy(tp, MII_CTRL1000,
2579 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2580
daf3ec68 2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2582 if (err)
2583 return err;
1da177e4
LT		 2584
2585 /* Block the PHY control access. */
6ee7c0a0 2586 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2587
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2589 if (!err)
2590 break;
2591 } while (--retries);
2592
2593 err = tg3_phy_reset_chanpat(tp);
2594 if (err)
2595 return err;
2596
6ee7c0a0 2597 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2598
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2601
daf3ec68 2602 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2603
221c5637 2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4 2605
c6e27f2f
DC		 2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
2607 if (err)
2608 return err;
1da177e4 2609
c6e27f2f
DC		 2610 reg32 &= ~0x3000;
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2612
2613 return 0;
1da177e4
LT		 2614}
2615
f4a46d1f
NNS		 2616static void tg3_carrier_off(struct tg3 *tp)
2617{
2618 netif_carrier_off(tp->dev);
2619 tp->link_up = false;
2620}
2621
ce20f161
NS		 2622static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2623{
2624 if (tg3_flag(tp, ENABLE_ASF))
2625 netdev_warn(tp->dev,
2626 "Management side-band traffic will be interrupted during phy settings change\n");
2627}
2628
1da177e4
LT		 2629/* This will reset the tigon3 PHY if there is no valid
2630 * link unless the FORCE argument is non-zero.
2631 */
2632static int tg3_phy_reset(struct tg3 *tp)
2633{
f833c4c1 2634 u32 val, cpmuctrl;
1da177e4
LT		 2635 int err;
2636
4153577a 2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2638 val = tr32(GRC_MISC_CFG);
2639 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2640 udelay(40);
2641 }
f833c4c1
MC		 2642 err = tg3_readphy(tp, MII_BMSR, &val);
2643 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2644 if (err != 0)
2645 return -EBUSY;
2646
f4a46d1f 2647 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2648 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2649 tg3_link_report(tp);
2650 }
2651
4153577a
JP		 2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2653 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2654 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2655 err = tg3_phy_reset_5703_4_5(tp);
2656 if (err)
2657 return err;
2658 goto out;
2659 }
2660
b2a5c19c 2661 cpmuctrl = 0;
4153577a
JP		 2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2664 cpmuctrl = tr32(TG3_CPMU_CTRL);
2665 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2666 tw32(TG3_CPMU_CTRL,
2667 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2668 }
2669
1da177e4
LT		 2670 err = tg3_bmcr_reset(tp);
2671 if (err)
2672 return err;
2673
b2a5c19c 2674 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2675 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2677
2678 tw32(TG3_CPMU_CTRL, cpmuctrl);
2679 }
2680
4153577a
JP		 2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2684 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2685 CPMU_LSPD_1000MB_MACCLK_12_5) {
2686 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2687 udelay(40);
2688 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2689 }
2690 }
2691
63c3a66f 2692 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2694 return 0;
2695
b2a5c19c
MC		 2696 tg3_phy_apply_otp(tp);
2697
f07e9af3 2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2699 tg3_phy_toggle_apd(tp, true);
2700 else
2701 tg3_phy_toggle_apd(tp, false);
2702
1da177e4 2703out:
1d36ba45 2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2707 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2708 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2709 }
1d36ba45 2710
f07e9af3 2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2714 }
1d36ba45 2715
f07e9af3 2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2718 tg3_phydsp_write(tp, 0x000a, 0x310b);
2719 tg3_phydsp_write(tp, 0x201f, 0x9506);
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2722 }
f07e9af3 2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2728 tg3_writephy(tp, MII_TG3_TEST1,
2729 MII_TG3_TEST1_TRIM_EN | 0x4);
2730 } else
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2732
daf3ec68 2733 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2734 }
c424cb24 2735 }
1d36ba45 2736
1da177e4
LT		 2737 /* Set Extended packet length bit (bit 14) on all chips that */
2738 /* support jumbo frames */
79eb6904 2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2740 /* Cannot do read-modify-write on 5401 */
b4bd2929 2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2743 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2744 err = tg3_phy_auxctl_read(tp,
2745 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2746 if (!err)
b4bd2929
MC		 2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2748 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2749 }
2750
2751 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2752 * jumbo frames transmission.
2753 */
63c3a66f 2754 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2757 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2758 }
2759
4153577a 2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2761 /* adjust output voltage */
535ef6e1 2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2763 }
2764
4153577a 2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2766 tg3_phydsp_write(tp, 0xffb, 0x4000);
2767
953c96e0 2768 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2769 tg3_phy_set_wirespeed(tp);
2770 return 0;
2771}
2772
3a1e19d3
MC		 2773#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2774#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2776 TG3_GPIO_MSG_NEED_VAUX)
2777#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2778 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 12))
2782
2783#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2784 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 12))
2788
2789static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2790{
2791 u32 status, shift;
2792
4153577a
JP		 2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2796 else
2797 status = tr32(TG3_CPMU_DRV_STATUS);
2798
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2800 status &= ~(TG3_GPIO_MSG_MASK << shift);
2801 status |= (newstat << shift);
2802
4153577a
JP		 2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2804 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2806 else
2807 tw32(TG3_CPMU_DRV_STATUS, status);
2808
2809 return status >> TG3_APE_GPIO_MSG_SHIFT;
2810}
2811
520b2756
MC		 2812static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2813{
2814 if (!tg3_flag(tp, IS_NIC))
2815 return 0;
2816
4153577a
JP		 2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2818 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2821 return -EIO;
520b2756 2822
3a1e19d3
MC		 2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2824
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2827
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2829 } else {
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY);
2832 }
6f5c8f83 2833
520b2756
MC		 2834 return 0;
2835}
2836
2837static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2838{
2839 u32 grc_local_ctrl;
2840
2841 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2842 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2843 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2844 return;
2845
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2847
2848 tw32_wait_f(GRC_LOCAL_CTRL,
2849 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2850 TG3_GRC_LCLCTL_PWRSW_DELAY);
2851
2852 tw32_wait_f(GRC_LOCAL_CTRL,
2853 grc_local_ctrl,
2854 TG3_GRC_LCLCTL_PWRSW_DELAY);
2855
2856 tw32_wait_f(GRC_LOCAL_CTRL,
2857 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2858 TG3_GRC_LCLCTL_PWRSW_DELAY);
2859}
2860
2861static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2862{
2863 if (!tg3_flag(tp, IS_NIC))
2864 return;
2865
4153577a
JP		 2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2867 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2869 (GRC_LCLCTRL_GPIO_OE0 |
2870 GRC_LCLCTRL_GPIO_OE1 |
2871 GRC_LCLCTRL_GPIO_OE2 |
2872 GRC_LCLCTRL_GPIO_OUTPUT0 |
2873 GRC_LCLCTRL_GPIO_OUTPUT1),
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2877 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2878 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2879 GRC_LCLCTRL_GPIO_OE1 |
2880 GRC_LCLCTRL_GPIO_OE2 |
2881 GRC_LCLCTRL_GPIO_OUTPUT0 |
2882 GRC_LCLCTRL_GPIO_OUTPUT1 |
2883 tp->grc_local_ctrl;
2884 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2885 TG3_GRC_LCLCTL_PWRSW_DELAY);
2886
2887 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2888 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2890
2891 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2892 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2894 } else {
2895 u32 no_gpio2;
2896 u32 grc_local_ctrl = 0;
2897
2898 /* Workaround to prevent overdrawing Amps. */
4153577a 2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2902 grc_local_ctrl,
2903 TG3_GRC_LCLCTL_PWRSW_DELAY);
2904 }
2905
2906 /* On 5753 and variants, GPIO2 cannot be used. */
2907 no_gpio2 = tp->nic_sram_data_cfg &
2908 NIC_SRAM_DATA_CFG_NO_GPIO2;
2909
2910 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2911 GRC_LCLCTRL_GPIO_OE1 |
2912 GRC_LCLCTRL_GPIO_OE2 |
2913 GRC_LCLCTRL_GPIO_OUTPUT1 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2;
2915 if (no_gpio2) {
2916 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2917 GRC_LCLCTRL_GPIO_OUTPUT2);
2918 }
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2922
2923 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2924
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2928
2929 if (!no_gpio2) {
2930 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2934 }
2935 }
3a1e19d3
MC		 2936}
2937
cd0d7228 2938static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2939{
2940 u32 msg = 0;
2941
2942 /* Serialize power state transitions */
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2944 return;
2945
cd0d7228 2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2947 msg = TG3_GPIO_MSG_NEED_VAUX;
2948
2949 msg = tg3_set_function_status(tp, msg);
2950
2951 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2952 goto done;
6f5c8f83 2953
3a1e19d3
MC		 2954 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2955 tg3_pwrsrc_switch_to_vaux(tp);
2956 else
2957 tg3_pwrsrc_die_with_vmain(tp);
2958
2959done:
6f5c8f83 2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2961}
2962
cd0d7228 2963static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2964{
683644b7 2965 bool need_vaux = false;
1da177e4 2966
334355aa 2967 /* The GPIOs do something completely different on 57765. */
55086ad9 2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2969 return;
2970
4153577a
JP		 2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2972 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2973 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2974 tg3_frob_aux_power_5717(tp, include_wol ?
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2976 return;
2977 }
2978
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2980 struct net_device *dev_peer;
2981
2982 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2983
bc1c7567 2984 /* remove_one() may have been run on the peer. */
683644b7
MC		 2985 if (dev_peer) {
2986 struct tg3 *tp_peer = netdev_priv(dev_peer);
2987
63c3a66f 2988 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2989 return;
2990
cd0d7228 2991 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2992 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2993 need_vaux = true;
2994 }
1da177e4
LT		 2995 }
2996
cd0d7228
MC		 2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2998 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 2999 need_vaux = true;
3000
520b2756
MC		 3001 if (need_vaux)
3002 tg3_pwrsrc_switch_to_vaux(tp);
3003 else
3004 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 3005}
3006
e8f3f6ca
MC		 3007static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3008{
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3010 return 1;
79eb6904 3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3012 if (speed != SPEED_10)
3013 return 1;
3014 } else if (speed == SPEED_10)
3015 return 1;
3016
3017 return 0;
3018}
3019
44f3b503
NS		 3020static bool tg3_phy_power_bug(struct tg3 *tp)
3021{
3022 switch (tg3_asic_rev(tp)) {
3023 case ASIC_REV_5700:
3024 case ASIC_REV_5704:
3025 return true;
3026 case ASIC_REV_5780:
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3028 return true;
3029 return false;
3030 case ASIC_REV_5717:
3031 if (!tp->pci_fn)
3032 return true;
3033 return false;
3034 case ASIC_REV_5719:
3035 case ASIC_REV_5720:
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3037 !tp->pci_fn)
3038 return true;
3039 return false;
3040 }
3041
3042 return false;
3043}
3044
989038e2
NS		 3045static bool tg3_phy_led_bug(struct tg3 *tp)
3046{
3047 switch (tg3_asic_rev(tp)) {
3048 case ASIC_REV_5719:
300cf9b9 3049 case ASIC_REV_5720:
989038e2
NS		 3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3051 !tp->pci_fn)
3052 return true;
3053 return false;
3054 }
3055
3056 return false;
3057}
3058
0a459aac 3059static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3060{
ce057f01
MC		 3061 u32 val;
3062
942d1af0
NS		 3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3064 return;
3065
f07e9af3 3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3070
3071 sg_dig_ctrl |=
3072 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3073 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3074 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3075 }
3f7045c1 3076 return;
5129724a 3077 }
3f7045c1 3078
4153577a 3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3080 tg3_bmcr_reset(tp);
3081 val = tr32(GRC_MISC_CFG);
3082 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3083 udelay(40);
3084 return;
f07e9af3 3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3086 u32 phytest;
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3088 u32 phy;
3089
3090 tg3_writephy(tp, MII_ADVERTISE, 0);
3091 tg3_writephy(tp, MII_BMCR,
3092 BMCR_ANENABLE | BMCR_ANRESTART);
3093
3094 tg3_writephy(tp, MII_TG3_FET_TEST,
3095 phytest | MII_TG3_FET_SHADOW_EN);
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3097 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3098 tg3_writephy(tp,
3099 MII_TG3_FET_SHDW_AUXMODE4,
3100 phy);
3101 }
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3103 }
3104 return;
0a459aac 3105 } else if (do_low_power) {
989038e2
NS		 3106 if (!tg3_phy_led_bug(tp))
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3109
b4bd2929
MC		 3110 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3111 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3112 MII_TG3_AUXCTL_PCTL_VREG_11V;
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3114 }
3f7045c1 3115
15c3b696
MC		 3116 /* The PHY should not be powered down on some chips because
3117 * of bugs.
3118 */
44f3b503 3119 if (tg3_phy_power_bug(tp))
15c3b696 3120 return;
ce057f01 3121
4153577a
JP		 3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3125 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3126 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3127 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3128 }
3129
15c3b696
MC		 3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3131}
3132
ffbcfed4
MC		 3133/* tp->lock is held. */
3134static int tg3_nvram_lock(struct tg3 *tp)
3135{
63c3a66f 3136 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3137 int i;
3138
3139 if (tp->nvram_lock_cnt == 0) {
3140 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3141 for (i = 0; i < 8000; i++) {
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3143 break;
3144 udelay(20);
3145 }
3146 if (i == 8000) {
3147 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3148 return -ENODEV;
3149 }
3150 }
3151 tp->nvram_lock_cnt++;
3152 }
3153 return 0;
3154}
3155
3156/* tp->lock is held. */
3157static void tg3_nvram_unlock(struct tg3 *tp)
3158{
63c3a66f 3159 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3160 if (tp->nvram_lock_cnt > 0)
3161 tp->nvram_lock_cnt--;
3162 if (tp->nvram_lock_cnt == 0)
3163 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3164 }
3165}
3166
3167/* tp->lock is held. */
3168static void tg3_enable_nvram_access(struct tg3 *tp)
3169{
63c3a66f 3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3172
3173 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3174 }
3175}
3176
3177/* tp->lock is held. */
3178static void tg3_disable_nvram_access(struct tg3 *tp)
3179{
63c3a66f 3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3181 u32 nvaccess = tr32(NVRAM_ACCESS);
3182
3183 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3184 }
3185}
3186
3187static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3188 u32 offset, u32 *val)
3189{
3190 u32 tmp;
3191 int i;
3192
3193 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3194 return -EINVAL;
3195
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3197 EEPROM_ADDR_DEVID_MASK |
3198 EEPROM_ADDR_READ);
3199 tw32(GRC_EEPROM_ADDR,
3200 tmp |
3201 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3202 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3203 EEPROM_ADDR_ADDR_MASK) |
3204 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3205
3206 for (i = 0; i < 1000; i++) {
3207 tmp = tr32(GRC_EEPROM_ADDR);
3208
3209 if (tmp & EEPROM_ADDR_COMPLETE)
3210 break;
3211 msleep(1);
3212 }
3213 if (!(tmp & EEPROM_ADDR_COMPLETE))
3214 return -EBUSY;
3215
62cedd11
MC		 3216 tmp = tr32(GRC_EEPROM_DATA);
3217
3218 /*
3219 * The data will always be opposite the native endian
3220 * format. Perform a blind byteswap to compensate.
3221 */
3222 *val = swab32(tmp);
3223
ffbcfed4
MC		 3224 return 0;
3225}
3226
66c965f5 3227#define NVRAM_CMD_TIMEOUT 5000
ffbcfed4
MC		 3228
3229static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3230{
3231 int i;
3232
3233 tw32(NVRAM_CMD, nvram_cmd);
3234 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
66c965f5 3235 usleep_range(10, 40);
ffbcfed4
MC		 3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3237 udelay(10);
3238 break;
3239 }
3240 }
3241
3242 if (i == NVRAM_CMD_TIMEOUT)
3243 return -EBUSY;
3244
3245 return 0;
3246}
3247
3248static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3249{
63c3a66f
JP		 3250 if (tg3_flag(tp, NVRAM) &&
3251 tg3_flag(tp, NVRAM_BUFFERED) &&
3252 tg3_flag(tp, FLASH) &&
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3254 (tp->nvram_jedecnum == JEDEC_ATMEL))
3255
3256 addr = ((addr / tp->nvram_pagesize) <<
3257 ATMEL_AT45DB0X1B_PAGE_POS) +
3258 (addr % tp->nvram_pagesize);
3259
3260 return addr;
3261}
3262
3263static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3264{
63c3a66f
JP		 3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3270
3271 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3272 tp->nvram_pagesize) +
3273 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3274
3275 return addr;
3276}
3277
e4f34110
MC		 3278/* NOTE: Data read in from NVRAM is byteswapped according to
3279 * the byteswapping settings for all other register accesses.
3280 * tg3 devices are BE devices, so on a BE machine, the data
3281 * returned will be exactly as it is seen in NVRAM. On a LE
3282 * machine, the 32-bit value will be byteswapped.
3283 */
ffbcfed4
MC		 3284static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3285{
3286 int ret;
3287
63c3a66f 3288 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3289 return tg3_nvram_read_using_eeprom(tp, offset, val);
3290
3291 offset = tg3_nvram_phys_addr(tp, offset);
3292
3293 if (offset > NVRAM_ADDR_MSK)
3294 return -EINVAL;
3295
3296 ret = tg3_nvram_lock(tp);
3297 if (ret)
3298 return ret;
3299
3300 tg3_enable_nvram_access(tp);
3301
3302 tw32(NVRAM_ADDR, offset);
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3304 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3305
3306 if (ret == 0)
e4f34110 3307 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3308
3309 tg3_disable_nvram_access(tp);
3310
3311 tg3_nvram_unlock(tp);
3312
3313 return ret;
3314}
3315
a9dc529d
MC		 3316/* Ensures NVRAM data is in bytestream format. */
3317static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3318{
3319 u32 v;
a9dc529d 3320 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3321 if (!res)
a9dc529d 3322 *val = cpu_to_be32(v);
ffbcfed4
MC		 3323 return res;
3324}
3325
dbe9b92a
MC		 3326static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3327 u32 offset, u32 len, u8 *buf)
3328{
3329 int i, j, rc = 0;
3330 u32 val;
3331
3332 for (i = 0; i < len; i += 4) {
3333 u32 addr;
3334 __be32 data;
3335
3336 addr = offset + i;
3337
3338 memcpy(&data, buf + i, 4);
3339
3340 /*
3341 * The SEEPROM interface expects the data to always be opposite
3342 * the native endian format. We accomplish this by reversing
3343 * all the operations that would have been performed on the
3344 * data from a call to tg3_nvram_read_be32().
3345 */
3346 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3347
3348 val = tr32(GRC_EEPROM_ADDR);
3349 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3350
3351 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3352 EEPROM_ADDR_READ);
3353 tw32(GRC_EEPROM_ADDR, val |
3354 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3355 (addr & EEPROM_ADDR_ADDR_MASK) |
3356 EEPROM_ADDR_START |
3357 EEPROM_ADDR_WRITE);
3358
3359 for (j = 0; j < 1000; j++) {
3360 val = tr32(GRC_EEPROM_ADDR);
3361
3362 if (val & EEPROM_ADDR_COMPLETE)
3363 break;
3364 msleep(1);
3365 }
3366 if (!(val & EEPROM_ADDR_COMPLETE)) {
3367 rc = -EBUSY;
3368 break;
3369 }
3370 }
3371
3372 return rc;
3373}
3374
3375/* offset and length are dword aligned */
3376static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3377 u8 *buf)
3378{
3379 int ret = 0;
3380 u32 pagesize = tp->nvram_pagesize;
3381 u32 pagemask = pagesize - 1;
3382 u32 nvram_cmd;
3383 u8 *tmp;
3384
3385 tmp = kmalloc(pagesize, GFP_KERNEL);
3386 if (tmp == NULL)
3387 return -ENOMEM;
3388
3389 while (len) {
3390 int j;
3391 u32 phy_addr, page_off, size;
3392
3393 phy_addr = offset & ~pagemask;
3394
3395 for (j = 0; j < pagesize; j += 4) {
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3397 (__be32 *) (tmp + j));
3398 if (ret)
3399 break;
3400 }
3401 if (ret)
3402 break;
3403
3404 page_off = offset & pagemask;
3405 size = pagesize;
3406 if (len < size)
3407 size = len;
3408
3409 len -= size;
3410
3411 memcpy(tmp + page_off, buf, size);
3412
3413 offset = offset + (pagesize - page_off);
3414
3415 tg3_enable_nvram_access(tp);
3416
3417 /*
3418 * Before we can erase the flash page, we need
3419 * to issue a special "write enable" command.
3420 */
3421 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3422
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3424 break;
3425
3426 /* Erase the target page */
3427 tw32(NVRAM_ADDR, phy_addr);
3428
3429 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3430 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3431
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3433 break;
3434
3435 /* Issue another write enable to start the write. */
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3437
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3439 break;
3440
3441 for (j = 0; j < pagesize; j += 4) {
3442 __be32 data;
3443
3444 data = *((__be32 *) (tmp + j));
3445
3446 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3447
3448 tw32(NVRAM_ADDR, phy_addr + j);
3449
3450 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3451 NVRAM_CMD_WR;
3452
3453 if (j == 0)
3454 nvram_cmd |= NVRAM_CMD_FIRST;
3455 else if (j == (pagesize - 4))
3456 nvram_cmd |= NVRAM_CMD_LAST;
3457
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3459 if (ret)
3460 break;
3461 }
3462 if (ret)
3463 break;
3464 }
3465
3466 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3467 tg3_nvram_exec_cmd(tp, nvram_cmd);
3468
3469 kfree(tmp);
3470
3471 return ret;
3472}
3473
3474/* offset and length are dword aligned */
3475static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3476 u8 *buf)
3477{
3478 int i, ret = 0;
3479
3480 for (i = 0; i < len; i += 4, offset += 4) {
3481 u32 page_off, phy_addr, nvram_cmd;
3482 __be32 data;
3483
3484 memcpy(&data, buf + i, 4);
3485 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3486
3487 page_off = offset % tp->nvram_pagesize;
3488
3489 phy_addr = tg3_nvram_phys_addr(tp, offset);
3490
dbe9b92a
MC		 3491 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3492
3493 if (page_off == 0 || i == 0)
3494 nvram_cmd |= NVRAM_CMD_FIRST;
3495 if (page_off == (tp->nvram_pagesize - 4))
3496 nvram_cmd |= NVRAM_CMD_LAST;
3497
3498 if (i == (len - 4))
3499 nvram_cmd |= NVRAM_CMD_LAST;
3500
42278224
MC		 3501 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3502 !tg3_flag(tp, FLASH) ||
3503 !tg3_flag(tp, 57765_PLUS))
3504 tw32(NVRAM_ADDR, phy_addr);
3505
4153577a 3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3507 !tg3_flag(tp, 5755_PLUS) &&
3508 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 (nvram_cmd & NVRAM_CMD_FIRST)) {
3510 u32 cmd;
3511
3512 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3513 ret = tg3_nvram_exec_cmd(tp, cmd);
3514 if (ret)
3515 break;
3516 }
3517 if (!tg3_flag(tp, FLASH)) {
3518 /* We always do complete word writes to eeprom. */
3519 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3520 }
3521
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3523 if (ret)
3524 break;
3525 }
3526 return ret;
3527}
3528
3529/* offset and length are dword aligned */
3530static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3531{
3532 int ret;
3533
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3537 udelay(40);
3538 }
3539
3540 if (!tg3_flag(tp, NVRAM)) {
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3542 } else {
3543 u32 grc_mode;
3544
3545 ret = tg3_nvram_lock(tp);
3546 if (ret)
3547 return ret;
3548
3549 tg3_enable_nvram_access(tp);
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3551 tw32(NVRAM_WRITE1, 0x406);
3552
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3555
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3558 buf);
3559 } else {
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3561 buf);
3562 }
3563
3564 grc_mode = tr32(GRC_MODE);
3565 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3566
3567 tg3_disable_nvram_access(tp);
3568 tg3_nvram_unlock(tp);
3569 }
3570
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3573 udelay(40);
3574 }
3575
3576 return ret;
3577}
3578
997b4f13
MC		 3579#define RX_CPU_SCRATCH_BASE 0x30000
3580#define RX_CPU_SCRATCH_SIZE 0x04000
3581#define TX_CPU_SCRATCH_BASE 0x34000
3582#define TX_CPU_SCRATCH_SIZE 0x04000
3583
3584/* tp->lock is held. */
837c45bb 3585static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3586{
3587 int i;
837c45bb 3588 const int iters = 10000;
997b4f13 3589
837c45bb
NS		 3590 for (i = 0; i < iters; i++) {
3591 tw32(cpu_base + CPU_STATE, 0xffffffff);
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3594 break;
6d446ec3
GS		 3595 if (pci_channel_offline(tp->pdev))
3596 return -EBUSY;
837c45bb
NS		 3597 }
3598
3599 return (i == iters) ? -EBUSY : 0;
3600}
3601
3602/* tp->lock is held. */
3603static int tg3_rxcpu_pause(struct tg3 *tp)
3604{
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3606
3607 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3608 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3609 udelay(10);
3610
3611 return rc;
3612}
3613
3614/* tp->lock is held. */
3615static int tg3_txcpu_pause(struct tg3 *tp)
3616{
3617 return tg3_pause_cpu(tp, TX_CPU_BASE);
3618}
3619
3620/* tp->lock is held. */
3621static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3622{
3623 tw32(cpu_base + CPU_STATE, 0xffffffff);
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3625}
3626
3627/* tp->lock is held. */
3628static void tg3_rxcpu_resume(struct tg3 *tp)
3629{
3630 tg3_resume_cpu(tp, RX_CPU_BASE);
3631}
3632
3633/* tp->lock is held. */
3634static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3635{
3636 int rc;
3637
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3639
4153577a 3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3641 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3642
3643 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3644 return 0;
3645 }
837c45bb
NS		 3646 if (cpu_base == RX_CPU_BASE) {
3647 rc = tg3_rxcpu_pause(tp);
997b4f13 3648 } else {
7e6c63f0
HM		 3649 /*
3650 * There is only an Rx CPU for the 5750 derivative in the
3651 * BCM4785.
3652 */
3653 if (tg3_flag(tp, IS_SSB_CORE))
3654 return 0;
3655
837c45bb 3656 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3657 }
3658
837c45bb 3659 if (rc) {
997b4f13 3660 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3662 return -ENODEV;
3663 }
3664
3665 /* Clear firmware's nvram arbitration. */
3666 if (tg3_flag(tp, NVRAM))
3667 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3668 return 0;
3669}
3670
31f11a95
NS		 3671static int tg3_fw_data_len(struct tg3 *tp,
3672 const struct tg3_firmware_hdr *fw_hdr)
3673{
3674 int fw_len;
3675
3676 /* Non fragmented firmware have one firmware header followed by a
3677 * contiguous chunk of data to be written. The length field in that
3678 * header is not the length of data to be written but the complete
3679 * length of the bss. The data length is determined based on
3680 * tp->fw->size minus headers.
3681 *
3682 * Fragmented firmware have a main header followed by multiple
3683 * fragments. Each fragment is identical to non fragmented firmware
3684 * with a firmware header followed by a contiguous chunk of data. In
3685 * the main header, the length field is unused and set to 0xffffffff.
3686 * In each fragment header the length is the entire size of that
3687 * fragment i.e. fragment data + header length. Data length is
3688 * therefore length field in the header minus TG3_FW_HDR_LEN.
3689 */
3690 if (tp->fw_len == 0xffffffff)
3691 fw_len = be32_to_cpu(fw_hdr->len);
3692 else
3693 fw_len = tp->fw->size;
3694
3695 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3696}
3697
997b4f13
MC		 3698/* tp->lock is held. */
3699static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3700 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3701 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3702{
c4dab506 3703 int err, i;
997b4f13 3704 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3705 int total_len = tp->fw->size;
997b4f13
MC		 3706
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3708 netdev_err(tp->dev,
3709 "%s: Trying to load TX cpu firmware which is 5705\n",
3710 __func__);
3711 return -EINVAL;
3712 }
3713
c4dab506 3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3715 write_op = tg3_write_mem;
3716 else
3717 write_op = tg3_write_indirect_reg32;
3718
c4dab506
NS		 3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3720 /* It is possible that bootcode is still loading at this point.
3721 * Get the nvram lock first before halting the cpu.
3722 */
3723 int lock_err = tg3_nvram_lock(tp);
3724 err = tg3_halt_cpu(tp, cpu_base);
3725 if (!lock_err)
3726 tg3_nvram_unlock(tp);
3727 if (err)
3728 goto out;
997b4f13 3729
c4dab506
NS		 3730 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3731 write_op(tp, cpu_scratch_base + i, 0);
3732 tw32(cpu_base + CPU_STATE, 0xffffffff);
3733 tw32(cpu_base + CPU_MODE,
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3735 } else {
3736 /* Subtract additional main header for fragmented firmware and
3737 * advance to the first fragment
3738 */
3739 total_len -= TG3_FW_HDR_LEN;
3740 fw_hdr++;
3741 }
77997ea3 3742
31f11a95
NS		 3743 do {
3744 u32 *fw_data = (u32 *)(fw_hdr + 1);
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3746 write_op(tp, cpu_scratch_base +
3747 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3748 (i * sizeof(u32)),
3749 be32_to_cpu(fw_data[i]));
3750
3751 total_len -= be32_to_cpu(fw_hdr->len);
3752
3753 /* Advance to next fragment */
3754 fw_hdr = (struct tg3_firmware_hdr *)
3755 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3756 } while (total_len > 0);
997b4f13
MC		 3757
3758 err = 0;
3759
3760out:
3761 return err;
3762}
3763
f4bffb28
NS		 3764/* tp->lock is held. */
3765static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3766{
3767 int i;
3768 const int iters = 5;
3769
3770 tw32(cpu_base + CPU_STATE, 0xffffffff);
3771 tw32_f(cpu_base + CPU_PC, pc);
3772
3773 for (i = 0; i < iters; i++) {
3774 if (tr32(cpu_base + CPU_PC) == pc)
3775 break;
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3778 tw32_f(cpu_base + CPU_PC, pc);
3779 udelay(1000);
3780 }
3781
3782 return (i == iters) ? -EBUSY : 0;
3783}
3784
997b4f13
MC		 3785/* tp->lock is held. */
3786static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3787{
77997ea3 3788 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3789 int err;
997b4f13 3790
77997ea3 3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3792
3793 /* Firmware blob starts with version numbers, followed by
3794 start address and length. We are setting complete length.
3795 length = end_address_of_bss - start_address_of_text.
3796 Remainder is the blob to be loaded contiguously
3797 from start address. */
3798
997b4f13
MC		 3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3800 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3801 fw_hdr);
997b4f13
MC		 3802 if (err)
3803 return err;
3804
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3806 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3807 fw_hdr);
997b4f13
MC		 3808 if (err)
3809 return err;
3810
3811 /* Now startup only the RX cpu. */
77997ea3
NS		 3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3813 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3814 if (err) {
997b4f13
MC		 3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3816 "should be %08x\n", __func__,
77997ea3
NS		 3817 tr32(RX_CPU_BASE + CPU_PC),
3818 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3819 return -ENODEV;
3820 }
837c45bb
NS		 3821
3822 tg3_rxcpu_resume(tp);
997b4f13
MC		 3823
3824 return 0;
3825}
3826
c4dab506
NS		 3827static int tg3_validate_rxcpu_state(struct tg3 *tp)
3828{
3829 const int iters = 1000;
3830 int i;
3831 u32 val;
3832
3833 /* Wait for boot code to complete initialization and enter service
3834 * loop. It is then safe to download service patches
3835 */
3836 for (i = 0; i < iters; i++) {
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3838 break;
3839
3840 udelay(10);
3841 }
3842
3843 if (i == iters) {
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3845 return -EBUSY;
3846 }
3847
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3849 if (val & 0xff) {
3850 netdev_warn(tp->dev,
3851 "Other patches exist. Not downloading EEE patch\n");
3852 return -EEXIST;
3853 }
3854
3855 return 0;
3856}
3857
3858/* tp->lock is held. */
3859static void tg3_load_57766_firmware(struct tg3 *tp)
3860{
3861 struct tg3_firmware_hdr *fw_hdr;
3862
3863 if (!tg3_flag(tp, NO_NVRAM))
3864 return;
3865
3866 if (tg3_validate_rxcpu_state(tp))
3867 return;
3868
3869 if (!tp->fw)
3870 return;
3871
3872 /* This firmware blob has a different format than older firmware
3873 * releases as given below. The main difference is we have fragmented
3874 * data to be written to non-contiguous locations.
3875 *
3876 * In the beginning we have a firmware header identical to other
3877 * firmware which consists of version, base addr and length. The length
3878 * here is unused and set to 0xffffffff.
3879 *
3880 * This is followed by a series of firmware fragments which are
3881 * individually identical to previous firmware. i.e. they have the
3882 * firmware header and followed by data for that fragment. The version
3883 * field of the individual fragment header is unused.
3884 */
3885
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3887 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3888 return;
3889
3890 if (tg3_rxcpu_pause(tp))
3891 return;
3892
3893 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3895
3896 tg3_rxcpu_resume(tp);
3897}
3898
997b4f13
MC		 3899/* tp->lock is held. */
3900static int tg3_load_tso_firmware(struct tg3 *tp)
3901{
77997ea3 3902 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3904 int err;
997b4f13 3905
1caf13eb 3906 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3907 return 0;
3908
77997ea3 3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3910
3911 /* Firmware blob starts with version numbers, followed by
3912 start address and length. We are setting complete length.
3913 length = end_address_of_bss - start_address_of_text.
3914 Remainder is the blob to be loaded contiguously
3915 from start address. */
3916
997b4f13 3917 cpu_scratch_size = tp->fw_len;
997b4f13 3918
4153577a 3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3920 cpu_base = RX_CPU_BASE;
3921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3922 } else {
3923 cpu_base = TX_CPU_BASE;
3924 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3925 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3926 }
3927
3928 err = tg3_load_firmware_cpu(tp, cpu_base,
3929 cpu_scratch_base, cpu_scratch_size,
77997ea3 3930 fw_hdr);
997b4f13
MC		 3931 if (err)
3932 return err;
3933
3934 /* Now startup the cpu. */
77997ea3
NS		 3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3936 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3937 if (err) {
997b4f13
MC		 3938 netdev_err(tp->dev,
3939 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3940 __func__, tr32(cpu_base + CPU_PC),
3941 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3942 return -ENODEV;
3943 }
837c45bb
NS		 3944
3945 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3946 return 0;
3947}
3948
f022ae62
MC		 3949/* tp->lock is held. */
3950static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3951{
3952 u32 addr_high, addr_low;
3953
3954 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3955 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3956 (mac_addr[4] << 8) | mac_addr[5]);
3957
3958 if (index < 4) {
3959 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3960 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3961 } else {
3962 index -= 4;
3963 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3964 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3965 }
3966}
997b4f13 3967
3f007891 3968/* tp->lock is held. */
953c96e0 3969static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891 3970{
f022ae62 3971 u32 addr_high;
3f007891
MC		 3972 int i;
3973
3f007891
MC		 3974 for (i = 0; i < 4; i++) {
3975 if (i == 1 && skip_mac_1)
3976 continue;
f022ae62 3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3978 }
3979
4153577a
JP		 3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3981 tg3_asic_rev(tp) == ASIC_REV_5704) {
f022ae62
MC		 3982 for (i = 4; i < 16; i++)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3984 }
3985
3986 addr_high = (tp->dev->dev_addr[0] +
3987 tp->dev->dev_addr[1] +
3988 tp->dev->dev_addr[2] +
3989 tp->dev->dev_addr[3] +
3990 tp->dev->dev_addr[4] +
3991 tp->dev->dev_addr[5]) &
3992 TX_BACKOFF_SEED_MASK;
3993 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3994}
3995
c866b7ea 3996static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 3997{
c866b7ea
RW		 3998 /*
3999 * Make sure register accesses (indirect or otherwise) will function
4000 * correctly.
1da177e4
LT		 4001 */
4002 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4004}
1da177e4 4005
c866b7ea
RW		 4006static int tg3_power_up(struct tg3 *tp)
4007{
bed9829f 4008 int err;
8c6bda1a 4009
bed9829f 4010 tg3_enable_register_access(tp);
1da177e4 4011
bed9829f
MC		 4012 err = pci_set_power_state(tp->pdev, PCI_D0);
4013 if (!err) {
4014 /* Switch out of Vaux if it is a NIC */
4015 tg3_pwrsrc_switch_to_vmain(tp);
4016 } else {
4017 netdev_err(tp->dev, "Transition to D0 failed\n");
4018 }
1da177e4 4019
bed9829f 4020 return err;
c866b7ea 4021}
1da177e4 4022
953c96e0 4023static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4024
c866b7ea
RW		 4025static int tg3_power_down_prepare(struct tg3 *tp)
4026{
4027 u32 misc_host_ctrl;
4028 bool device_should_wake, do_low_power;
4029
4030 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4031
4032 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4033 if (tg3_flag(tp, CLKREQ_BUG))
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4035 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4036
1da177e4
LT		 4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4038 tw32(TG3PCI_MISC_HOST_CTRL,
4039 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4040
c866b7ea 4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4042 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4043
63c3a66f 4044 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4045 do_low_power = false;
f07e9af3 4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4048 struct phy_device *phydev;
0a459aac 4049 u32 phyid, advertising;
b02fd9e3 4050
ead2402c 4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 4052
80096068 4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4054
c6700ce2
MC		 4055 tp->link_config.speed = phydev->speed;
4056 tp->link_config.duplex = phydev->duplex;
4057 tp->link_config.autoneg = phydev->autoneg;
4058 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4059
4060 advertising = ADVERTISED_TP |
4061 ADVERTISED_Pause |
4062 ADVERTISED_Autoneg |
4063 ADVERTISED_10baseT_Half;
4064
63c3a66f
JP		 4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4066 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4067 advertising |=
4068 ADVERTISED_100baseT_Half |
4069 ADVERTISED_100baseT_Full |
4070 ADVERTISED_10baseT_Full;
4071 else
4072 advertising |= ADVERTISED_10baseT_Full;
4073 }
4074
4075 phydev->advertising = advertising;
4076
4077 phy_start_aneg(phydev);
0a459aac
MC		 4078
4079 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4080 if (phyid != PHY_ID_BCMAC131) {
4081 phyid &= PHY_BCM_OUI_MASK;
4082 if (phyid == PHY_BCM_OUI_1 ||
4083 phyid == PHY_BCM_OUI_2 ||
4084 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4085 do_low_power = true;
4086 }
b02fd9e3 4087 }
dd477003 4088 } else {
2023276e 4089 do_low_power = true;
0a459aac 4090
c6700ce2 4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4093
2855b9fe 4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4095 tg3_setup_phy(tp, false);
1da177e4
LT		 4096 }
4097
4153577a 4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4099 u32 val;
4100
4101 val = tr32(GRC_VCPU_EXT_CTRL);
4102 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4103 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4104 int i;
4105 u32 val;
4106
4107 for (i = 0; i < 200; i++) {
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4109 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4110 break;
4111 msleep(1);
4112 }
4113 }
63c3a66f 4114 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4116 WOL_DRV_STATE_SHUTDOWN |
4117 WOL_DRV_WOL |
4118 WOL_SET_MAGIC_PKT);
6921d201 4119
05ac4cb7 4120 if (device_should_wake) {
1da177e4
LT		 4121 u32 mac_mode;
4122
f07e9af3 4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4124 if (do_low_power &&
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4126 tg3_phy_auxctl_write(tp,
4127 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4128 MII_TG3_AUXCTL_PCTL_WOL_EN |
4129 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4130 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4131 udelay(40);
4132 }
1da177e4 4133
f07e9af3 4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4135 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4136 else if (tp->phy_flags &
4137 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4138 if (tp->link_config.active_speed == SPEED_1000)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4140 else
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4142 } else
3f7045c1 4143 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4144
e8f3f6ca 4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4148 SPEED_100 : SPEED_10;
4149 if (tg3_5700_link_polarity(tp, speed))
4150 mac_mode |= MAC_MODE_LINK_POLARITY;
4151 else
4152 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4153 }
1da177e4
LT		 4154 } else {
4155 mac_mode = MAC_MODE_PORT_MODE_TBI;
4156 }
4157
63c3a66f 4158 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4159 tw32(MAC_LED_CTRL, tp->led_ctrl);
4160
05ac4cb7 4161 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4164 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4165
63c3a66f 4166 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4167 mac_mode |= MAC_MODE_APE_TX_EN |
4168 MAC_MODE_APE_RX_EN |
4169 MAC_MODE_TDE_ENABLE;
3bda1258 4170
1da177e4
LT		 4171 tw32_f(MAC_MODE, mac_mode);
4172 udelay(100);
4173
4174 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4175 udelay(10);
4176 }
4177
63c3a66f 4178 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4179 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4181 u32 base_val;
4182
4183 base_val = tp->pci_clock_ctrl;
4184 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE);
4186
b401e9e2
MC		 4187 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4188 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4189 } else if (tg3_flag(tp, 5780_CLASS) ||
4190 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4191 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4192 /* do nothing */
63c3a66f 4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4194 u32 newbits1, newbits2;
4195
4153577a
JP		 4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4197 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4198 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4199 CLOCK_CTRL_TXCLK_DISABLE |
4200 CLOCK_CTRL_ALTCLK);
4201 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4202 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4203 newbits1 = CLOCK_CTRL_625_CORE;
4204 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4205 } else {
4206 newbits1 = CLOCK_CTRL_ALTCLK;
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4208 }
4209
b401e9e2
MC		 4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4211 40);
1da177e4 4212
b401e9e2
MC		 4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4214 40);
1da177e4 4215
63c3a66f 4216 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4217 u32 newbits3;
4218
4153577a
JP		 4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4220 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4221 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4222 CLOCK_CTRL_TXCLK_DISABLE |
4223 CLOCK_CTRL_44MHZ_CORE);
4224 } else {
4225 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4226 }
4227
b401e9e2
MC		 4228 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4229 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4230 }
4231 }
4232
63c3a66f 4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4234 tg3_power_down_phy(tp, do_low_power);
6921d201 4235
cd0d7228 4236 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4237
4238 /* Workaround for unstable PLL clock */
7e6c63f0 4239 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4242 u32 val = tr32(0x7d00);
4243
4244 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4245 tw32(0x7d00, val);
63c3a66f 4246 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4247 int err;
4248
4249 err = tg3_nvram_lock(tp);
1da177e4 4250 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4251 if (!err)
4252 tg3_nvram_unlock(tp);
6921d201 4253 }
1da177e4
LT		 4254 }
4255
bbadf503
MC		 4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4257
2e460fc0
NS		 4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4259
c866b7ea
RW		 4260 return 0;
4261}
12dac075 4262
c866b7ea
RW		 4263static void tg3_power_down(struct tg3 *tp)
4264{
63c3a66f 4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4266 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4267}
4268
1da177e4
LT		 4269static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4270{
4271 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4272 case MII_TG3_AUX_STAT_10HALF:
4273 *speed = SPEED_10;
4274 *duplex = DUPLEX_HALF;
4275 break;
4276
4277 case MII_TG3_AUX_STAT_10FULL:
4278 *speed = SPEED_10;
4279 *duplex = DUPLEX_FULL;
4280 break;
4281
4282 case MII_TG3_AUX_STAT_100HALF:
4283 *speed = SPEED_100;
4284 *duplex = DUPLEX_HALF;
4285 break;
4286
4287 case MII_TG3_AUX_STAT_100FULL:
4288 *speed = SPEED_100;
4289 *duplex = DUPLEX_FULL;
4290 break;
4291
4292 case MII_TG3_AUX_STAT_1000HALF:
4293 *speed = SPEED_1000;
4294 *duplex = DUPLEX_HALF;
4295 break;
4296
4297 case MII_TG3_AUX_STAT_1000FULL:
4298 *speed = SPEED_1000;
4299 *duplex = DUPLEX_FULL;
4300 break;
4301
4302 default:
f07e9af3 4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4304 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4305 SPEED_10;
4306 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4307 DUPLEX_HALF;
4308 break;
4309 }
e740522e
MC		 4310 *speed = SPEED_UNKNOWN;
4311 *duplex = DUPLEX_UNKNOWN;
1da177e4 4312 break;
855e1111 4313 }
1da177e4
LT		 4314}
4315
42b64a45 4316static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4317{
42b64a45
MC		 4318 int err = 0;
4319 u32 val, new_adv;
1da177e4 4320
42b64a45 4321 new_adv = ADVERTISE_CSMA;
202ff1c2 4322 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4323 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4324
42b64a45
MC		 4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4326 if (err)
4327 goto done;
ba4d07a8 4328
4f272096
MC		 4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4330 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4331
4153577a
JP		 4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4334 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4335
4f272096
MC		 4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4337 if (err)
4338 goto done;
4339 }
1da177e4 4340
42b64a45
MC		 4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4342 goto done;
52b02d04 4343
42b64a45
MC		 4344 tw32(TG3_CPMU_EEE_MODE,
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4346
daf3ec68 4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4348 if (!err) {
4349 u32 err2;
52b02d04 4350
b715ce94
MC		 4351 val = 0;
4352 /* Advertise 100-BaseTX EEE ability */
4353 if (advertise & ADVERTISED_100baseT_Full)
4354 val |= MDIO_AN_EEE_ADV_100TX;
4355 /* Advertise 1000-BaseT EEE ability */
4356 if (advertise & ADVERTISED_1000baseT_Full)
4357 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4358
4359 if (!tp->eee.eee_enabled) {
4360 val = 0;
4361 tp->eee.advertised = 0;
4362 } else {
4363 tp->eee.advertised = advertise &
4364 (ADVERTISED_100baseT_Full |
4365 ADVERTISED_1000baseT_Full);
4366 }
4367
b715ce94
MC		 4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4369 if (err)
4370 val = 0;
4371
4153577a 4372 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4373 case ASIC_REV_5717:
4374 case ASIC_REV_57765:
55086ad9 4375 case ASIC_REV_57766:
21a00ab2 4376 case ASIC_REV_5719:
b715ce94
MC		 4377 /* If we advertised any eee advertisements above... */
4378 if (val)
4379 val = MII_TG3_DSP_TAP26_ALNOKO |
4380 MII_TG3_DSP_TAP26_RMRXSTO |
4381 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4383 /* Fall through */
4384 case ASIC_REV_5720:
c65a17f4 4385 case ASIC_REV_5762:
be671947
MC		 4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4388 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4389 }
52b02d04 4390
daf3ec68 4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4392 if (!err)
4393 err = err2;
4394 }
4395
4396done:
4397 return err;
4398}
4399
4400static void tg3_phy_copper_begin(struct tg3 *tp)
4401{
d13ba512
MC		 4402 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4404 u32 adv, fc;
4405
942d1af0
NS		 4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4408 adv = ADVERTISED_10baseT_Half |
4409 ADVERTISED_10baseT_Full;
4410 if (tg3_flag(tp, WOL_SPEED_100MB))
4411 adv |= ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full;
7c786065
NS		 4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4414 if (!(tp->phy_flags &
4415 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4416 adv |= ADVERTISED_1000baseT_Half;
4417 adv |= ADVERTISED_1000baseT_Full;
4418 }
d13ba512
MC		 4419
4420 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4421 } else {
d13ba512
MC		 4422 adv = tp->link_config.advertising;
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4424 adv &= ~(ADVERTISED_1000baseT_Half |
4425 ADVERTISED_1000baseT_Full);
4426
4427 fc = tp->link_config.flowctrl;
52b02d04 4428 }
52b02d04 4429
d13ba512 4430 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4431
942d1af0
NS		 4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4434 /* Normally during power down we want to autonegotiate
4435 * the lowest possible speed for WOL. However, to avoid
4436 * link flap, we leave it untouched.
4437 */
4438 return;
4439 }
4440
d13ba512
MC		 4441 tg3_writephy(tp, MII_BMCR,
4442 BMCR_ANENABLE | BMCR_ANRESTART);
4443 } else {
4444 int i;
1da177e4
LT		 4445 u32 bmcr, orig_bmcr;
4446
4447 tp->link_config.active_speed = tp->link_config.speed;
4448 tp->link_config.active_duplex = tp->link_config.duplex;
4449
7c6cdead
NS		 4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4451 /* With autoneg disabled, 5715 only links up when the
4452 * advertisement register has the configured speed
4453 * enabled.
4454 */
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4456 }
4457
1da177e4
LT		 4458 bmcr = 0;
4459 switch (tp->link_config.speed) {
4460 default:
4461 case SPEED_10:
4462 break;
4463
4464 case SPEED_100:
4465 bmcr |= BMCR_SPEED100;
4466 break;
4467
4468 case SPEED_1000:
221c5637 4469 bmcr |= BMCR_SPEED1000;
1da177e4 4470 break;
855e1111 4471 }
1da177e4
LT		 4472
4473 if (tp->link_config.duplex == DUPLEX_FULL)
4474 bmcr |= BMCR_FULLDPLX;
4475
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4477 (bmcr != orig_bmcr)) {
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4479 for (i = 0; i < 1500; i++) {
4480 u32 tmp;
4481
4482 udelay(10);
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4484 tg3_readphy(tp, MII_BMSR, &tmp))
4485 continue;
4486 if (!(tmp & BMSR_LSTATUS)) {
4487 udelay(40);
4488 break;
4489 }
4490 }
4491 tg3_writephy(tp, MII_BMCR, bmcr);
4492 udelay(40);
4493 }
1da177e4
LT		 4494 }
4495}
4496
fdad8de4
NS		 4497static int tg3_phy_pull_config(struct tg3 *tp)
4498{
4499 int err;
4500 u32 val;
4501
4502 err = tg3_readphy(tp, MII_BMCR, &val);
4503 if (err)
4504 goto done;
4505
4506 if (!(val & BMCR_ANENABLE)) {
4507 tp->link_config.autoneg = AUTONEG_DISABLE;
4508 tp->link_config.advertising = 0;
4509 tg3_flag_clear(tp, PAUSE_AUTONEG);
4510
4511 err = -EIO;
4512
4513 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4514 case 0:
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4516 goto done;
4517
4518 tp->link_config.speed = SPEED_10;
4519 break;
4520 case BMCR_SPEED100:
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4522 goto done;
4523
4524 tp->link_config.speed = SPEED_100;
4525 break;
4526 case BMCR_SPEED1000:
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 tp->link_config.speed = SPEED_1000;
4529 break;
4530 }
4531 /* Fall through */
4532 default:
4533 goto done;
4534 }
4535
4536 if (val & BMCR_FULLDPLX)
4537 tp->link_config.duplex = DUPLEX_FULL;
4538 else
4539 tp->link_config.duplex = DUPLEX_HALF;
4540
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4542
4543 err = 0;
4544 goto done;
4545 }
4546
4547 tp->link_config.autoneg = AUTONEG_ENABLE;
4548 tp->link_config.advertising = ADVERTISED_Autoneg;
4549 tg3_flag_set(tp, PAUSE_AUTONEG);
4550
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4552 u32 adv;
4553
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4555 if (err)
4556 goto done;
4557
4558 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4559 tp->link_config.advertising |= adv | ADVERTISED_TP;
4560
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4562 } else {
4563 tp->link_config.advertising |= ADVERTISED_FIBRE;
4564 }
4565
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4567 u32 adv;
4568
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4570 err = tg3_readphy(tp, MII_CTRL1000, &val);
4571 if (err)
4572 goto done;
4573
4574 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4575 } else {
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4577 if (err)
4578 goto done;
4579
4580 adv = tg3_decode_flowctrl_1000X(val);
4581 tp->link_config.flowctrl = adv;
4582
4583 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4584 adv = mii_adv_to_ethtool_adv_x(val);
4585 }
4586
4587 tp->link_config.advertising |= adv;
4588 }
4589
4590done:
4591 return err;
4592}
4593
1da177e4
LT		 4594static int tg3_init_5401phy_dsp(struct tg3 *tp)
4595{
4596 int err;
4597
4598 /* Turn off tap power management. */
4599 /* Set Extended packet length bit */
b4bd2929 4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4601
6ee7c0a0
MC		 4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4607
4608 udelay(40);
4609
4610 return err;
4611}
4612
ed1ff5c3
NS		 4613static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4614{
5b6c273a 4615 struct ethtool_eee eee;
ed1ff5c3
NS		 4616
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4618 return true;
4619
5b6c273a 4620 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4621
5b6c273a
NS		 4622 if (tp->eee.eee_enabled) {
4623 if (tp->eee.advertised != eee.advertised ||
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4626 return false;
4627 } else {
4628 /* EEE is disabled but we're advertising */
4629 if (eee.advertised)
4630 return false;
4631 }
ed1ff5c3
NS		 4632
4633 return true;
4634}
4635
e2bf73e7 4636static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4637{
e2bf73e7 4638 u32 advmsk, tgtadv, advertising;
3600d918 4639
e2bf73e7
MC		 4640 advertising = tp->link_config.advertising;
4641 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4642
e2bf73e7
MC		 4643 advmsk = ADVERTISE_ALL;
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4646 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4647 }
1da177e4 4648
e2bf73e7
MC		 4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4650 return false;
4651
4652 if ((*lcladv & advmsk) != tgtadv)
4653 return false;
b99d2a57 4654
f07e9af3 4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4656 u32 tg3_ctrl;
4657
e2bf73e7 4658 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4659
221c5637 4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4661 return false;
1da177e4 4662
3198e07f 4663 if (tgtadv &&
4153577a
JP		 4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4666 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4667 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4668 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4669 } else {
4670 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4671 }
4672
e2bf73e7
MC		 4673 if (tg3_ctrl != tgtadv)
4674 return false;
ef167e27
MC		 4675 }
4676
e2bf73e7 4677 return true;
ef167e27
MC		 4678}
4679
859edb26
MC		 4680static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4681{
4682 u32 lpeth = 0;
4683
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4685 u32 val;
4686
4687 if (tg3_readphy(tp, MII_STAT1000, &val))
4688 return false;
4689
4690 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4691 }
4692
4693 if (tg3_readphy(tp, MII_LPA, rmtadv))
4694 return false;
4695
4696 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4697 tp->link_config.rmt_adv = lpeth;
4698
4699 return true;
4700}
4701
953c96e0 4702static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4703{
4704 if (curr_link_up != tp->link_up) {
4705 if (curr_link_up) {
84421b99 4706 netif_carrier_on(tp->dev);
f4a46d1f 4707 } else {
84421b99 4708 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4711 }
4712
4713 tg3_link_report(tp);
4714 return true;
4715 }
4716
4717 return false;
4718}
4719
3310e248
MC		 4720static void tg3_clear_mac_status(struct tg3 *tp)
4721{
4722 tw32(MAC_EVENT, 0);
4723
4724 tw32_f(MAC_STATUS,
4725 MAC_STATUS_SYNC_CHANGED |
4726 MAC_STATUS_CFG_CHANGED |
4727 MAC_STATUS_MI_COMPLETION |
4728 MAC_STATUS_LNKSTATE_CHANGED);
4729 udelay(40);
4730}
4731
9e2ecbeb
NS		 4732static void tg3_setup_eee(struct tg3 *tp)
4733{
4734 u32 val;
4735
4736 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4737 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4739 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4740
4741 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4742
4743 tw32_f(TG3_CPMU_EEE_CTRL,
4744 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4745
4746 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4748 TG3_CPMU_EEEMD_LPI_IN_RX |
4749 TG3_CPMU_EEEMD_EEE_ENABLE;
4750
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4752 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4753
4754 if (tg3_flag(tp, ENABLE_APE))
4755 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4756
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4758
4759 tw32_f(TG3_CPMU_EEE_DBTMR1,
4760 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4761 (tp->eee.tx_lpi_timer & 0xffff));
4762
4763 tw32_f(TG3_CPMU_EEE_DBTMR2,
4764 TG3_CPMU_DBTMR2_APE_TX_2047US |
4765 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4766}
4767
953c96e0 4768static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4769{
953c96e0 4770 bool current_link_up;
f833c4c1 4771 u32 bmsr, val;
ef167e27 4772 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4773 u16 current_speed;
4774 u8 current_duplex;
4775 int i, err;
4776
3310e248 4777 tg3_clear_mac_status(tp);
1da177e4 4778
8ef21428
MC		 4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4780 tw32_f(MAC_MI_MODE,
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4782 udelay(80);
4783 }
1da177e4 4784
b4bd2929 4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4786
4787 /* Some third-party PHYs need to be reset on link going
4788 * down.
4789 */
4153577a
JP		 4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4791 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4792 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4793 tp->link_up) {
1da177e4
LT		 4794 tg3_readphy(tp, MII_BMSR, &bmsr);
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4796 !(bmsr & BMSR_LSTATUS))
953c96e0 4797 force_reset = true;
1da177e4
LT		 4798 }
4799 if (force_reset)
4800 tg3_phy_reset(tp);
4801
79eb6904 4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4805 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4806 bmsr = 0;
4807
4808 if (!(bmsr & BMSR_LSTATUS)) {
4809 err = tg3_init_5401phy_dsp(tp);
4810 if (err)
4811 return err;
4812
4813 tg3_readphy(tp, MII_BMSR, &bmsr);
4814 for (i = 0; i < 1000; i++) {
4815 udelay(10);
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4817 (bmsr & BMSR_LSTATUS)) {
4818 udelay(40);
4819 break;
4820 }
4821 }
4822
79eb6904
MC		 4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4824 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4825 !(bmsr & BMSR_LSTATUS) &&
4826 tp->link_config.active_speed == SPEED_1000) {
4827 err = tg3_phy_reset(tp);
4828 if (!err)
4829 err = tg3_init_5401phy_dsp(tp);
4830 if (err)
4831 return err;
4832 }
4833 }
4153577a
JP		 4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4836 /* 5701 {A0,B0} CRC bug workaround */
4837 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4841 }
4842
4843 /* Clear pending interrupts... */
f833c4c1
MC		 4844 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4846
f07e9af3 4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4850 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4851
4153577a
JP		 4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4853 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4857 else
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4859 }
4860
953c96e0 4861 current_link_up = false;
e740522e
MC		 4862 current_speed = SPEED_UNKNOWN;
4863 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4865 tp->link_config.rmt_adv = 0;
1da177e4 4866
f07e9af3 4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4868 err = tg3_phy_auxctl_read(tp,
4869 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4870 &val);
4871 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4872 tg3_phy_auxctl_write(tp,
4873 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4874 val | (1 << 10));
1da177e4
LT		 4875 goto relink;
4876 }
4877 }
4878
4879 bmsr = 0;
4880 for (i = 0; i < 100; i++) {
4881 tg3_readphy(tp, MII_BMSR, &bmsr);
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4883 (bmsr & BMSR_LSTATUS))
4884 break;
4885 udelay(40);
4886 }
4887
4888 if (bmsr & BMSR_LSTATUS) {
4889 u32 aux_stat, bmcr;
4890
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4892 for (i = 0; i < 2000; i++) {
4893 udelay(10);
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4895 aux_stat)
4896 break;
4897 }
4898
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4900 &current_speed,
4901 &current_duplex);
4902
4903 bmcr = 0;
4904 for (i = 0; i < 200; i++) {
4905 tg3_readphy(tp, MII_BMCR, &bmcr);
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4907 continue;
4908 if (bmcr && bmcr != 0x7fff)
4909 break;
4910 udelay(10);
4911 }
4912
ef167e27
MC		 4913 lcl_adv = 0;
4914 rmt_adv = 0;
1da177e4 4915
ef167e27
MC		 4916 tp->link_config.active_speed = current_speed;
4917 tp->link_config.active_duplex = current_duplex;
4918
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4921
ef167e27 4922 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4923 eee_config_ok &&
e2bf73e7 4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4926 current_link_up = true;
ed1ff5c3
NS		 4927
4928 /* EEE settings changes take effect only after a phy
4929 * reset. If we have skipped a reset due to Link Flap
4930 * Avoidance being enabled, do it now.
4931 */
4932 if (!eee_config_ok &&
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4934 !force_reset) {
4935 tg3_setup_eee(tp);
ed1ff5c3 4936 tg3_phy_reset(tp);
5b6c273a 4937 }
1da177e4
LT		 4938 } else {
4939 if (!(bmcr & BMCR_ANENABLE) &&
4940 tp->link_config.speed == current_speed &&
f0fcd7a9 4941 tp->link_config.duplex == current_duplex) {
953c96e0 4942 current_link_up = true;
1da177e4
LT		 4943 }
4944 }
4945
953c96e0 4946 if (current_link_up &&
e348c5e7
MC		 4947 tp->link_config.active_duplex == DUPLEX_FULL) {
4948 u32 reg, bit;
4949
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4951 reg = MII_TG3_FET_GEN_STAT;
4952 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4953 } else {
4954 reg = MII_TG3_EXT_STAT;
4955 bit = MII_TG3_EXT_STAT_MDIX;
4956 }
4957
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4960
ef167e27 4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4962 }
1da177e4
LT		 4963 }
4964
1da177e4 4965relink:
953c96e0 4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4967 tg3_phy_copper_begin(tp);
4968
7e6c63f0 4969 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4970 current_link_up = true;
7e6c63f0
HM		 4971 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4972 current_speed = SPEED_1000;
4973 current_duplex = DUPLEX_FULL;
4974 tp->link_config.active_speed = current_speed;
4975 tp->link_config.active_duplex = current_duplex;
4976 }
4977
f833c4c1 4978 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4981 current_link_up = true;
1da177e4
LT		 4982 }
4983
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4985 if (current_link_up) {
1da177e4
LT		 4986 if (tp->link_config.active_speed == SPEED_100 ||
4987 tp->link_config.active_speed == SPEED_10)
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4989 else
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4993 else
1da177e4
LT		 4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4995
7e6c63f0
HM		 4996 /* In order for the 5750 core in BCM4785 chip to work properly
4997 * in RGMII mode, the Led Control Register must be set up.
4998 */
4999 if (tg3_flag(tp, RGMII_MODE)) {
5000 u32 led_ctrl = tr32(MAC_LED_CTRL);
5001 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5002
5003 if (tp->link_config.active_speed == SPEED_10)
5004 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5005 else if (tp->link_config.active_speed == SPEED_100)
5006 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5007 LED_CTRL_100MBPS_ON);
5008 else if (tp->link_config.active_speed == SPEED_1000)
5009 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5010 LED_CTRL_1000MBPS_ON);
5011
5012 tw32(MAC_LED_CTRL, led_ctrl);
5013 udelay(40);
5014 }
5015
1da177e4
LT		 5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5017 if (tp->link_config.active_duplex == DUPLEX_HALF)
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5019
4153577a 5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 5021 if (current_link_up &&
e8f3f6ca 5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5024 else
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5026 }
5027
5028 /* ??? Without this setting Netgear GA302T PHY does not
5029 * ??? send/receive packets...
5030 */
79eb6904 5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5034 tw32_f(MAC_MI_MODE, tp->mi_mode);
5035 udelay(80);
5036 }
5037
5038 tw32_f(MAC_MODE, tp->mac_mode);
5039 udelay(40);
5040
52b02d04
MC		 5041 tg3_phy_eee_adjust(tp, current_link_up);
5042
63c3a66f 5043 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5044 /* Polled via timer. */
5045 tw32_f(MAC_EVENT, 0);
5046 } else {
5047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5048 }
5049 udelay(40);
5050
4153577a 5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5052 current_link_up &&
1da177e4 5053 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5055 udelay(120);
5056 tw32_f(MAC_STATUS,
5057 (MAC_STATUS_SYNC_CHANGED |
5058 MAC_STATUS_CFG_CHANGED));
5059 udelay(40);
5060 tg3_write_mem(tp,
5061 NIC_SRAM_FIRMWARE_MBOX,
5062 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5063 }
5064
5e7dfd0f 5065 /* Prevent send BD corruption. */
63c3a66f 5066 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5067 if (tp->link_config.active_speed == SPEED_100 ||
5068 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5070 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5071 else
0f49bfbd
JL		 5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5073 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5074 }
5075
f4a46d1f 5076 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5077
5078 return 0;
5079}
5080
5081struct tg3_fiber_aneginfo {
5082 int state;
5083#define ANEG_STATE_UNKNOWN 0
5084#define ANEG_STATE_AN_ENABLE 1
5085#define ANEG_STATE_RESTART_INIT 2
5086#define ANEG_STATE_RESTART 3
5087#define ANEG_STATE_DISABLE_LINK_OK 4
5088#define ANEG_STATE_ABILITY_DETECT_INIT 5
5089#define ANEG_STATE_ABILITY_DETECT 6
5090#define ANEG_STATE_ACK_DETECT_INIT 7
5091#define ANEG_STATE_ACK_DETECT 8
5092#define ANEG_STATE_COMPLETE_ACK_INIT 9
5093#define ANEG_STATE_COMPLETE_ACK 10
5094#define ANEG_STATE_IDLE_DETECT_INIT 11
5095#define ANEG_STATE_IDLE_DETECT 12
5096#define ANEG_STATE_LINK_OK 13
5097#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5098#define ANEG_STATE_NEXT_PAGE_WAIT 15
5099
5100 u32 flags;
5101#define MR_AN_ENABLE 0x00000001
5102#define MR_RESTART_AN 0x00000002
5103#define MR_AN_COMPLETE 0x00000004
5104#define MR_PAGE_RX 0x00000008
5105#define MR_NP_LOADED 0x00000010
5106#define MR_TOGGLE_TX 0x00000020
5107#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5108#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5109#define MR_LP_ADV_SYM_PAUSE 0x00000100
5110#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5111#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5112#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5113#define MR_LP_ADV_NEXT_PAGE 0x00001000
5114#define MR_TOGGLE_RX 0x00002000
5115#define MR_NP_RX 0x00004000
5116
5117#define MR_LINK_OK 0x80000000
5118
5119 unsigned long link_time, cur_time;
5120
5121 u32 ability_match_cfg;
5122 int ability_match_count;
5123
5124 char ability_match, idle_match, ack_match;
5125
5126 u32 txconfig, rxconfig;
5127#define ANEG_CFG_NP 0x00000080
5128#define ANEG_CFG_ACK 0x00000040
5129#define ANEG_CFG_RF2 0x00000020
5130#define ANEG_CFG_RF1 0x00000010
5131#define ANEG_CFG_PS2 0x00000001
5132#define ANEG_CFG_PS1 0x00008000
5133#define ANEG_CFG_HD 0x00004000
5134#define ANEG_CFG_FD 0x00002000
5135#define ANEG_CFG_INVAL 0x00001f06
5136
5137};
5138#define ANEG_OK 0
5139#define ANEG_DONE 1
5140#define ANEG_TIMER_ENAB 2
5141#define ANEG_FAILED -1
5142
5143#define ANEG_STATE_SETTLE_TIME 10000
5144
5145static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5146 struct tg3_fiber_aneginfo *ap)
5147{
5be73b47 5148 u16 flowctrl;
1da177e4
LT		 5149 unsigned long delta;
5150 u32 rx_cfg_reg;
5151 int ret;
5152
5153 if (ap->state == ANEG_STATE_UNKNOWN) {
5154 ap->rxconfig = 0;
5155 ap->link_time = 0;
5156 ap->cur_time = 0;
5157 ap->ability_match_cfg = 0;
5158 ap->ability_match_count = 0;
5159 ap->ability_match = 0;
5160 ap->idle_match = 0;
5161 ap->ack_match = 0;
5162 }
5163 ap->cur_time++;
5164
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5167
5168 if (rx_cfg_reg != ap->ability_match_cfg) {
5169 ap->ability_match_cfg = rx_cfg_reg;
5170 ap->ability_match = 0;
5171 ap->ability_match_count = 0;
5172 } else {
5173 if (++ap->ability_match_count > 1) {
5174 ap->ability_match = 1;
5175 ap->ability_match_cfg = rx_cfg_reg;
5176 }
5177 }
5178 if (rx_cfg_reg & ANEG_CFG_ACK)
5179 ap->ack_match = 1;
5180 else
5181 ap->ack_match = 0;
5182
5183 ap->idle_match = 0;
5184 } else {
5185 ap->idle_match = 1;
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5189 ap->ack_match = 0;
5190
5191 rx_cfg_reg = 0;
5192 }
5193
5194 ap->rxconfig = rx_cfg_reg;
5195 ret = ANEG_OK;
5196
33f401ae 5197 switch (ap->state) {
1da177e4
LT		 5198 case ANEG_STATE_UNKNOWN:
5199 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5200 ap->state = ANEG_STATE_AN_ENABLE;
5201
5202 /* fallthru */
5203 case ANEG_STATE_AN_ENABLE:
5204 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5205 if (ap->flags & MR_AN_ENABLE) {
5206 ap->link_time = 0;
5207 ap->cur_time = 0;
5208 ap->ability_match_cfg = 0;
5209 ap->ability_match_count = 0;
5210 ap->ability_match = 0;
5211 ap->idle_match = 0;
5212 ap->ack_match = 0;
5213
5214 ap->state = ANEG_STATE_RESTART_INIT;
5215 } else {
5216 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5217 }
5218 break;
5219
5220 case ANEG_STATE_RESTART_INIT:
5221 ap->link_time = ap->cur_time;
5222 ap->flags &= ~(MR_NP_LOADED);
5223 ap->txconfig = 0;
5224 tw32(MAC_TX_AUTO_NEG, 0);
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5226 tw32_f(MAC_MODE, tp->mac_mode);
5227 udelay(40);
5228
5229 ret = ANEG_TIMER_ENAB;
5230 ap->state = ANEG_STATE_RESTART;
5231
5232 /* fallthru */
5233 case ANEG_STATE_RESTART:
5234 delta = ap->cur_time - ap->link_time;
859a5887 5235 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5236 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5237 else
1da177e4 5238 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5239 break;
5240
5241 case ANEG_STATE_DISABLE_LINK_OK:
5242 ret = ANEG_DONE;
5243 break;
5244
5245 case ANEG_STATE_ABILITY_DETECT_INIT:
5246 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5247 ap->txconfig = ANEG_CFG_FD;
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5249 if (flowctrl & ADVERTISE_1000XPAUSE)
5250 ap->txconfig |= ANEG_CFG_PS1;
5251 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5252 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5253 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5255 tw32_f(MAC_MODE, tp->mac_mode);
5256 udelay(40);
5257
5258 ap->state = ANEG_STATE_ABILITY_DETECT;
5259 break;
5260
5261 case ANEG_STATE_ABILITY_DETECT:
859a5887 5262 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5263 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5264 break;
5265
5266 case ANEG_STATE_ACK_DETECT_INIT:
5267 ap->txconfig |= ANEG_CFG_ACK;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5271 udelay(40);
5272
5273 ap->state = ANEG_STATE_ACK_DETECT;
5274
5275 /* fallthru */
5276 case ANEG_STATE_ACK_DETECT:
5277 if (ap->ack_match != 0) {
5278 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5279 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5280 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5281 } else {
5282 ap->state = ANEG_STATE_AN_ENABLE;
5283 }
5284 } else if (ap->ability_match != 0 &&
5285 ap->rxconfig == 0) {
5286 ap->state = ANEG_STATE_AN_ENABLE;
5287 }
5288 break;
5289
5290 case ANEG_STATE_COMPLETE_ACK_INIT:
5291 if (ap->rxconfig & ANEG_CFG_INVAL) {
5292 ret = ANEG_FAILED;
5293 break;
5294 }
5295 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5296 MR_LP_ADV_HALF_DUPLEX |
5297 MR_LP_ADV_SYM_PAUSE |
5298 MR_LP_ADV_ASYM_PAUSE |
5299 MR_LP_ADV_REMOTE_FAULT1 |
5300 MR_LP_ADV_REMOTE_FAULT2 |
5301 MR_LP_ADV_NEXT_PAGE |
5302 MR_TOGGLE_RX |
5303 MR_NP_RX);
5304 if (ap->rxconfig & ANEG_CFG_FD)
5305 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_HD)
5307 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5308 if (ap->rxconfig & ANEG_CFG_PS1)
5309 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_PS2)
5311 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5312 if (ap->rxconfig & ANEG_CFG_RF1)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5314 if (ap->rxconfig & ANEG_CFG_RF2)
5315 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5316 if (ap->rxconfig & ANEG_CFG_NP)
5317 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5318
5319 ap->link_time = ap->cur_time;
5320
5321 ap->flags ^= (MR_TOGGLE_TX);
5322 if (ap->rxconfig & 0x0008)
5323 ap->flags |= MR_TOGGLE_RX;
5324 if (ap->rxconfig & ANEG_CFG_NP)
5325 ap->flags |= MR_NP_RX;
5326 ap->flags |= MR_PAGE_RX;
5327
5328 ap->state = ANEG_STATE_COMPLETE_ACK;
5329 ret = ANEG_TIMER_ENAB;
5330 break;
5331
5332 case ANEG_STATE_COMPLETE_ACK:
5333 if (ap->ability_match != 0 &&
5334 ap->rxconfig == 0) {
5335 ap->state = ANEG_STATE_AN_ENABLE;
5336 break;
5337 }
5338 delta = ap->cur_time - ap->link_time;
5339 if (delta > ANEG_STATE_SETTLE_TIME) {
5340 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5342 } else {
5343 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5344 !(ap->flags & MR_NP_RX)) {
5345 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5346 } else {
5347 ret = ANEG_FAILED;
5348 }
5349 }
5350 }
5351 break;
5352
5353 case ANEG_STATE_IDLE_DETECT_INIT:
5354 ap->link_time = ap->cur_time;
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5356 tw32_f(MAC_MODE, tp->mac_mode);
5357 udelay(40);
5358
5359 ap->state = ANEG_STATE_IDLE_DETECT;
5360 ret = ANEG_TIMER_ENAB;
5361 break;
5362
5363 case ANEG_STATE_IDLE_DETECT:
5364 if (ap->ability_match != 0 &&
5365 ap->rxconfig == 0) {
5366 ap->state = ANEG_STATE_AN_ENABLE;
5367 break;
5368 }
5369 delta = ap->cur_time - ap->link_time;
5370 if (delta > ANEG_STATE_SETTLE_TIME) {
5371 /* XXX another gem from the Broadcom driver :( */
5372 ap->state = ANEG_STATE_LINK_OK;
5373 }
5374 break;
5375
5376 case ANEG_STATE_LINK_OK:
5377 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5378 ret = ANEG_DONE;
5379 break;
5380
5381 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5382 /* ??? unimplemented */
5383 break;
5384
5385 case ANEG_STATE_NEXT_PAGE_WAIT:
5386 /* ??? unimplemented */
5387 break;
5388
5389 default:
5390 ret = ANEG_FAILED;
5391 break;
855e1111 5392 }
1da177e4
LT		 5393
5394 return ret;
5395}
5396
5be73b47 5397static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5398{
5399 int res = 0;
5400 struct tg3_fiber_aneginfo aninfo;
5401 int status = ANEG_FAILED;
5402 unsigned int tick;
5403 u32 tmp;
5404
5405 tw32_f(MAC_TX_AUTO_NEG, 0);
5406
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5408 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5409 udelay(40);
5410
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5412 udelay(40);
5413
5414 memset(&aninfo, 0, sizeof(aninfo));
5415 aninfo.flags |= MR_AN_ENABLE;
5416 aninfo.state = ANEG_STATE_UNKNOWN;
5417 aninfo.cur_time = 0;
5418 tick = 0;
5419 while (++tick < 195000) {
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5421 if (status == ANEG_DONE || status == ANEG_FAILED)
5422 break;
5423
5424 udelay(1);
5425 }
5426
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5428 tw32_f(MAC_MODE, tp->mac_mode);
5429 udelay(40);
5430
5be73b47
MC		 5431 *txflags = aninfo.txconfig;
5432 *rxflags = aninfo.flags;
1da177e4
LT		 5433
5434 if (status == ANEG_DONE &&
5435 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5436 MR_LP_ADV_FULL_DUPLEX)))
5437 res = 1;
5438
5439 return res;
5440}
5441
5442static void tg3_init_bcm8002(struct tg3 *tp)
5443{
5444 u32 mac_status = tr32(MAC_STATUS);
5445 int i;
5446
5447 /* Reset when initting first time or we have a link. */
63c3a66f 5448 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5449 !(mac_status & MAC_STATUS_PCS_SYNCED))
5450 return;
5451
5452 /* Set PLL lock range. */
5453 tg3_writephy(tp, 0x16, 0x8007);
5454
5455 /* SW reset */
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5457
5458 /* Wait for reset to complete. */
5459 /* XXX schedule_timeout() ... */
5460 for (i = 0; i < 500; i++)
5461 udelay(10);
5462
5463 /* Config mode; select PMA/Ch 1 regs. */
5464 tg3_writephy(tp, 0x10, 0x8411);
5465
5466 /* Enable auto-lock and comdet, select txclk for tx. */
5467 tg3_writephy(tp, 0x11, 0x0a10);
5468
5469 tg3_writephy(tp, 0x18, 0x00a0);
5470 tg3_writephy(tp, 0x16, 0x41ff);
5471
5472 /* Assert and deassert POR. */
5473 tg3_writephy(tp, 0x13, 0x0400);
5474 udelay(40);
5475 tg3_writephy(tp, 0x13, 0x0000);
5476
5477 tg3_writephy(tp, 0x11, 0x0a50);
5478 udelay(40);
5479 tg3_writephy(tp, 0x11, 0x0a10);
5480
5481 /* Wait for signal to stabilize */
5482 /* XXX schedule_timeout() ... */
5483 for (i = 0; i < 15000; i++)
5484 udelay(10);
5485
5486 /* Deselect the channel register so we can read the PHYID
5487 * later.
5488 */
5489 tg3_writephy(tp, 0x10, 0x8011);
5490}
5491
953c96e0 5492static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5493{
82cd3d11 5494 u16 flowctrl;
953c96e0 5495 bool current_link_up;
1da177e4
LT		 5496 u32 sg_dig_ctrl, sg_dig_status;
5497 u32 serdes_cfg, expected_sg_dig_ctrl;
5498 int workaround, port_a;
1da177e4
LT		 5499
5500 serdes_cfg = 0;
5501 expected_sg_dig_ctrl = 0;
5502 workaround = 0;
5503 port_a = 1;
953c96e0 5504 current_link_up = false;
1da177e4 5505
4153577a
JP		 5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5508 workaround = 1;
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5510 port_a = 0;
5511
5512 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5513 /* preserve bits 20-23 for voltage regulator */
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5515 }
5516
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5518
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5520 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5521 if (workaround) {
5522 u32 val = serdes_cfg;
5523
5524 if (port_a)
5525 val |= 0xc010000;
5526 else
5527 val |= 0x4010000;
5528 tw32_f(MAC_SERDES_CFG, val);
5529 }
c98f6e3b
MC		 5530
5531 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5532 }
5533 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5534 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5535 current_link_up = true;
1da177e4
LT		 5536 }
5537 goto out;
5538 }
5539
5540 /* Want auto-negotiation. */
c98f6e3b 5541 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5542
82cd3d11
MC		 5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5544 if (flowctrl & ADVERTISE_1000XPAUSE)
5545 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5546 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5547 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5548
5549 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5551 tp->serdes_counter &&
5552 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5553 MAC_STATUS_RCVD_CFG)) ==
5554 MAC_STATUS_PCS_SYNCED)) {
5555 tp->serdes_counter--;
953c96e0 5556 current_link_up = true;
3d3ebe74
MC		 5557 goto out;
5558 }
5559restart_autoneg:
1da177e4
LT		 5560 if (workaround)
5561 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5563 udelay(5);
5564 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5565
3d3ebe74 5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5568 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5569 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5570 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5571 mac_status = tr32(MAC_STATUS);
5572
c98f6e3b 5573 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5574 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5575 u32 local_adv = 0, remote_adv = 0;
5576
5577 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5578 local_adv |= ADVERTISE_1000XPAUSE;
5579 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5580 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5581
c98f6e3b 5582 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5583 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5584 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5585 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5586
859edb26
MC		 5587 tp->link_config.rmt_adv =
5588 mii_adv_to_ethtool_adv_x(remote_adv);
5589
1da177e4 5590 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5591 current_link_up = true;
3d3ebe74 5592 tp->serdes_counter = 0;
f07e9af3 5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5594 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5595 if (tp->serdes_counter)
5596 tp->serdes_counter--;
1da177e4
LT		 5597 else {
5598 if (workaround) {
5599 u32 val = serdes_cfg;
5600
5601 if (port_a)
5602 val |= 0xc010000;
5603 else
5604 val |= 0x4010000;
5605
5606 tw32_f(MAC_SERDES_CFG, val);
5607 }
5608
c98f6e3b 5609 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5610 udelay(40);
5611
5612 /* Link parallel detection - link is up */
5613 /* only if we have PCS_SYNC and not */
5614 /* receiving config code words */
5615 mac_status = tr32(MAC_STATUS);
5616 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5617 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5618 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5619 current_link_up = true;
f07e9af3
MC		 5620 tp->phy_flags |=
5621 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5622 tp->serdes_counter =
5623 SERDES_PARALLEL_DET_TIMEOUT;
5624 } else
5625 goto restart_autoneg;
1da177e4
LT		 5626 }
5627 }
3d3ebe74
MC		 5628 } else {
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5631 }
5632
5633out:
5634 return current_link_up;
5635}
5636
953c96e0 5637static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5638{
953c96e0 5639 bool current_link_up = false;
1da177e4 5640
5cf64b8a 5641 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5642 goto out;
1da177e4
LT		 5643
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5645 u32 txflags, rxflags;
1da177e4 5646 int i;
6aa20a22 5647
5be73b47
MC		 5648 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5649 u32 local_adv = 0, remote_adv = 0;
1da177e4 5650
5be73b47
MC		 5651 if (txflags & ANEG_CFG_PS1)
5652 local_adv |= ADVERTISE_1000XPAUSE;
5653 if (txflags & ANEG_CFG_PS2)
5654 local_adv |= ADVERTISE_1000XPSE_ASYM;
5655
5656 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE;
5658 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5659 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5660
859edb26
MC		 5661 tp->link_config.rmt_adv =
5662 mii_adv_to_ethtool_adv_x(remote_adv);
5663
1da177e4
LT		 5664 tg3_setup_flow_control(tp, local_adv, remote_adv);
5665
953c96e0 5666 current_link_up = true;
1da177e4
LT		 5667 }
5668 for (i = 0; i < 30; i++) {
5669 udelay(20);
5670 tw32_f(MAC_STATUS,
5671 (MAC_STATUS_SYNC_CHANGED |
5672 MAC_STATUS_CFG_CHANGED));
5673 udelay(40);
5674 if ((tr32(MAC_STATUS) &
5675 (MAC_STATUS_SYNC_CHANGED |
5676 MAC_STATUS_CFG_CHANGED)) == 0)
5677 break;
5678 }
5679
5680 mac_status = tr32(MAC_STATUS);
953c96e0 5681 if (!current_link_up &&
1da177e4
LT		 5682 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5683 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5684 current_link_up = true;
1da177e4 5685 } else {
5be73b47
MC		 5686 tg3_setup_flow_control(tp, 0, 0);
5687
1da177e4 5688 /* Forcing 1000FD link up. */
953c96e0 5689 current_link_up = true;
1da177e4
LT		 5690
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5692 udelay(40);
e8f3f6ca
MC		 5693
5694 tw32_f(MAC_MODE, tp->mac_mode);
5695 udelay(40);
1da177e4
LT		 5696 }
5697
5698out:
5699 return current_link_up;
5700}
5701
953c96e0 5702static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5703{
5704 u32 orig_pause_cfg;
5705 u16 orig_active_speed;
5706 u8 orig_active_duplex;
5707 u32 mac_status;
953c96e0 5708 bool current_link_up;
1da177e4
LT		 5709 int i;
5710
8d018621 5711 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5712 orig_active_speed = tp->link_config.active_speed;
5713 orig_active_duplex = tp->link_config.active_duplex;
5714
63c3a66f 5715 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5716 tp->link_up &&
63c3a66f 5717 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5718 mac_status = tr32(MAC_STATUS);
5719 mac_status &= (MAC_STATUS_PCS_SYNCED |
5720 MAC_STATUS_SIGNAL_DET |
5721 MAC_STATUS_CFG_CHANGED |
5722 MAC_STATUS_RCVD_CFG);
5723 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5724 MAC_STATUS_SIGNAL_DET)) {
5725 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5726 MAC_STATUS_CFG_CHANGED));
5727 return 0;
5728 }
5729 }
5730
5731 tw32_f(MAC_TX_AUTO_NEG, 0);
5732
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5735 tw32_f(MAC_MODE, tp->mac_mode);
5736 udelay(40);
5737
79eb6904 5738 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5739 tg3_init_bcm8002(tp);
5740
5741 /* Enable link change event even when serdes polling. */
5742 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5743 udelay(40);
5744
953c96e0 5745 current_link_up = false;
859edb26 5746 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5747 mac_status = tr32(MAC_STATUS);
5748
63c3a66f 5749 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5751 else
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5753
898a56f8 5754 tp->napi[0].hw_status->status =
1da177e4 5755 (SD_STATUS_UPDATED |
898a56f8 5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5757
5758 for (i = 0; i < 100; i++) {
5759 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5760 MAC_STATUS_CFG_CHANGED));
5761 udelay(5);
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5763 MAC_STATUS_CFG_CHANGED |
5764 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5765 break;
5766 }
5767
5768 mac_status = tr32(MAC_STATUS);
5769 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5770 current_link_up = false;
3d3ebe74
MC		 5771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5772 tp->serdes_counter == 0) {
1da177e4
LT		 5773 tw32_f(MAC_MODE, (tp->mac_mode |
5774 MAC_MODE_SEND_CONFIGS));
5775 udelay(1);
5776 tw32_f(MAC_MODE, tp->mac_mode);
5777 }
5778 }
5779
953c96e0 5780 if (current_link_up) {
1da177e4
LT		 5781 tp->link_config.active_speed = SPEED_1000;
5782 tp->link_config.active_duplex = DUPLEX_FULL;
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5784 LED_CTRL_LNKLED_OVERRIDE |
5785 LED_CTRL_1000MBPS_ON));
5786 } else {
e740522e
MC		 5787 tp->link_config.active_speed = SPEED_UNKNOWN;
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_TRAFFIC_OVERRIDE));
5792 }
5793
f4a46d1f 5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5795 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5796 if (orig_pause_cfg != now_pause_cfg ||
5797 orig_active_speed != tp->link_config.active_speed ||
5798 orig_active_duplex != tp->link_config.active_duplex)
5799 tg3_link_report(tp);
5800 }
5801
5802 return 0;
5803}
5804
953c96e0 5805static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5806{
953c96e0 5807 int err = 0;
747e8f8b 5808 u32 bmsr, bmcr;
85730a63
MC		 5809 u16 current_speed = SPEED_UNKNOWN;
5810 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5811 bool current_link_up = false;
85730a63
MC		 5812 u32 local_adv, remote_adv, sgsr;
5813
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5815 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5817 (sgsr & SERDES_TG3_SGMII_MODE)) {
5818
5819 if (force_reset)
5820 tg3_phy_reset(tp);
5821
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5823
5824 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5826 } else {
953c96e0 5827 current_link_up = true;
85730a63
MC		 5828 if (sgsr & SERDES_TG3_SPEED_1000) {
5829 current_speed = SPEED_1000;
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5831 } else if (sgsr & SERDES_TG3_SPEED_100) {
5832 current_speed = SPEED_100;
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5834 } else {
5835 current_speed = SPEED_10;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5837 }
5838
5839 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5840 current_duplex = DUPLEX_FULL;
5841 else
5842 current_duplex = DUPLEX_HALF;
5843 }
5844
5845 tw32_f(MAC_MODE, tp->mac_mode);
5846 udelay(40);
5847
5848 tg3_clear_mac_status(tp);
5849
5850 goto fiber_setup_done;
5851 }
747e8f8b
MC		 5852
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5854 tw32_f(MAC_MODE, tp->mac_mode);
5855 udelay(40);
5856
3310e248 5857 tg3_clear_mac_status(tp);
747e8f8b
MC		 5858
5859 if (force_reset)
5860 tg3_phy_reset(tp);
5861
859edb26 5862 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5863
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5868 bmsr |= BMSR_LSTATUS;
5869 else
5870 bmsr &= ~BMSR_LSTATUS;
5871 }
747e8f8b
MC		 5872
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5874
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5877 /* do nothing, just check for link up at the end */
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5879 u32 adv, newadv;
747e8f8b
MC		 5880
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5882 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5883 ADVERTISE_1000XPAUSE |
5884 ADVERTISE_1000XPSE_ASYM |
5885 ADVERTISE_SLCT);
747e8f8b 5886
28011cf1 5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5889
28011cf1
MC		 5890 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5891 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5892 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5893 tg3_writephy(tp, MII_BMCR, bmcr);
5894
5895 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5898
5899 return err;
5900 }
5901 } else {
5902 u32 new_bmcr;
5903
5904 bmcr &= ~BMCR_SPEED1000;
5905 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5906
5907 if (tp->link_config.duplex == DUPLEX_FULL)
5908 new_bmcr |= BMCR_FULLDPLX;
5909
5910 if (new_bmcr != bmcr) {
5911 /* BMCR_SPEED1000 is a reserved bit that needs
5912 * to be set on write.
5913 */
5914 new_bmcr |= BMCR_SPEED1000;
5915
5916 /* Force a linkdown */
f4a46d1f 5917 if (tp->link_up) {
747e8f8b
MC		 5918 u32 adv;
5919
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5921 adv &= ~(ADVERTISE_1000XFULL |
5922 ADVERTISE_1000XHALF |
5923 ADVERTISE_SLCT);
5924 tg3_writephy(tp, MII_ADVERTISE, adv);
5925 tg3_writephy(tp, MII_BMCR, bmcr |
5926 BMCR_ANRESTART |
5927 BMCR_ANENABLE);
5928 udelay(10);
f4a46d1f 5929 tg3_carrier_off(tp);
747e8f8b
MC		 5930 }
5931 tg3_writephy(tp, MII_BMCR, new_bmcr);
5932 bmcr = new_bmcr;
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5937 bmsr |= BMSR_LSTATUS;
5938 else
5939 bmsr &= ~BMSR_LSTATUS;
5940 }
f07e9af3 5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5942 }
5943 }
5944
5945 if (bmsr & BMSR_LSTATUS) {
5946 current_speed = SPEED_1000;
953c96e0 5947 current_link_up = true;
747e8f8b
MC		 5948 if (bmcr & BMCR_FULLDPLX)
5949 current_duplex = DUPLEX_FULL;
5950 else
5951 current_duplex = DUPLEX_HALF;
5952
ef167e27
MC		 5953 local_adv = 0;
5954 remote_adv = 0;
5955
747e8f8b 5956 if (bmcr & BMCR_ANENABLE) {
ef167e27 5957 u32 common;
747e8f8b
MC		 5958
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5961 common = local_adv & remote_adv;
5962 if (common & (ADVERTISE_1000XHALF |
5963 ADVERTISE_1000XFULL)) {
5964 if (common & ADVERTISE_1000XFULL)
5965 current_duplex = DUPLEX_FULL;
5966 else
5967 current_duplex = DUPLEX_HALF;
859edb26
MC		 5968
5969 tp->link_config.rmt_adv =
5970 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5971 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5972 /* Link is up via parallel detect */
859a5887 5973 } else {
953c96e0 5974 current_link_up = false;
859a5887 5975 }
747e8f8b
MC		 5976 }
5977 }
5978
85730a63 5979fiber_setup_done:
953c96e0 5980 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5981 tg3_setup_flow_control(tp, local_adv, remote_adv);
5982
747e8f8b
MC		 5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5984 if (tp->link_config.active_duplex == DUPLEX_HALF)
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5986
5987 tw32_f(MAC_MODE, tp->mac_mode);
5988 udelay(40);
5989
5990 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5991
5992 tp->link_config.active_speed = current_speed;
5993 tp->link_config.active_duplex = current_duplex;
5994
f4a46d1f 5995 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 5996 return err;
5997}
5998
5999static void tg3_serdes_parallel_detect(struct tg3 *tp)
6000{
3d3ebe74 6001 if (tp->serdes_counter) {
747e8f8b 6002 /* Give autoneg time to complete. */
3d3ebe74 6003 tp->serdes_counter--;
747e8f8b
MC		 6004 return;
6005 }
c6cdf436 6006
f4a46d1f 6007 if (!tp->link_up &&
747e8f8b
MC		 6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6009 u32 bmcr;
6010
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 if (bmcr & BMCR_ANENABLE) {
6013 u32 phy1, phy2;
6014
6015 /* Select shadow register 0x1f */
f08aa1a8
MC		 6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 6018
6019 /* Select expansion interrupt status register */
f08aa1a8
MC		 6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6021 MII_TG3_DSP_EXP1_INT_STAT);
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6024
6025 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6026 /* We have signal detect and not receiving
6027 * config code words, link is up by parallel
6028 * detection.
6029 */
6030
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6035 }
6036 }
f4a46d1f 6037 } else if (tp->link_up &&
859a5887 6038 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6040 u32 phy2;
6041
6042 /* Select expansion interrupt status register */
f08aa1a8
MC		 6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 MII_TG3_DSP_EXP1_INT_STAT);
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6046 if (phy2 & 0x20) {
6047 u32 bmcr;
6048
6049 /* Config code words received, turn on autoneg. */
6050 tg3_readphy(tp, MII_BMCR, &bmcr);
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6052
f07e9af3 6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6054
6055 }
6056 }
6057}
6058
953c96e0 6059static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6060{
f2096f94 6061 u32 val;
1da177e4
LT		 6062 int err;
6063
f07e9af3 6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6065 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6067 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6068 else
1da177e4 6069 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6070
4153577a 6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6072 u32 scale;
aa6c91fe
MC		 6073
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6075 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6076 scale = 65;
6077 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6078 scale = 6;
6079 else
6080 scale = 12;
6081
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6083 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6084 tw32(GRC_MISC_CFG, val);
6085 }
6086
f2096f94
MC		 6087 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6088 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6090 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6091 val |= tr32(MAC_TX_LENGTHS) &
6092 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6093 TX_LENGTHS_CNT_DWN_VAL_MSK);
6094
1da177e4
LT		 6095 if (tp->link_config.active_speed == SPEED_1000 &&
6096 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6097 tw32(MAC_TX_LENGTHS, val |
6098 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6099 else
f2096f94
MC		 6100 tw32(MAC_TX_LENGTHS, val |
6101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6102
63c3a66f 6103 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6104 if (tp->link_up) {
1da177e4 6105 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6106 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6107 } else {
6108 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6109 }
6110 }
6111
63c3a66f 6112 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6113 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6114 if (!tp->link_up)
8ed5d97e
MC		 6115 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6116 tp->pwrmgmt_thresh;
6117 else
6118 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6119 tw32(PCIE_PWR_MGMT_THRESH, val);
6120 }
6121
1da177e4
LT		 6122 return err;
6123}
6124
7d41e49a
MC		 6125/* tp->lock must be held */
6126static u64 tg3_refclk_read(struct tg3 *tp)
6127{
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6130}
6131
be947307
MC		 6132/* tp->lock must be held */
6133static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6134{
92e6457d
NS		 6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6136
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6141}
6142
7d41e49a
MC		 6143static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144static inline void tg3_full_unlock(struct tg3 *tp);
6145static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6146{
6147 struct tg3 *tp = netdev_priv(dev);
6148
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6150 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6151 SOF_TIMESTAMPING_SOFTWARE;
6152
6153 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6154 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6155 SOF_TIMESTAMPING_RX_HARDWARE |
6156 SOF_TIMESTAMPING_RAW_HARDWARE;
6157 }
7d41e49a
MC		 6158
6159 if (tp->ptp_clock)
6160 info->phc_index = ptp_clock_index(tp->ptp_clock);
6161 else
6162 info->phc_index = -1;
6163
6164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6165
6166 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6168 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6170 return 0;
6171}
6172
6173static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6174{
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6176 bool neg_adj = false;
6177 u32 correction = 0;
6178
6179 if (ppb < 0) {
6180 neg_adj = true;
6181 ppb = -ppb;
6182 }
6183
6184 /* Frequency adjustment is performed using hardware with a 24 bit
6185 * accumulator and a programmable correction value. On each clk, the
6186 * correction value gets added to the accumulator and when it
6187 * overflows, the time counter is incremented/decremented.
6188 *
6189 * So conversion from ppb to correction value is
6190 * ppb * (1 << 24) / 1000000000
6191 */
6192 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6193 TG3_EAV_REF_CLK_CORRECT_MASK;
6194
6195 tg3_full_lock(tp, 0);
6196
6197 if (correction)
6198 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6199 TG3_EAV_REF_CLK_CORRECT_EN |
6200 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6201 else
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6203
6204 tg3_full_unlock(tp);
6205
6206 return 0;
6207}
6208
6209static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6210{
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6212
6213 tg3_full_lock(tp, 0);
6214 tp->ptp_adjust += delta;
6215 tg3_full_unlock(tp);
6216
6217 return 0;
6218}
6219
6220static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6221{
6222 u64 ns;
6223 u32 remainder;
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6225
6226 tg3_full_lock(tp, 0);
6227 ns = tg3_refclk_read(tp);
6228 ns += tp->ptp_adjust;
6229 tg3_full_unlock(tp);
6230
6231 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6232 ts->tv_nsec = remainder;
6233
6234 return 0;
6235}
6236
6237static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6238 const struct timespec *ts)
6239{
6240 u64 ns;
6241 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6242
6243 ns = timespec_to_ns(ts);
6244
6245 tg3_full_lock(tp, 0);
6246 tg3_refclk_write(tp, ns);
6247 tp->ptp_adjust = 0;
6248 tg3_full_unlock(tp);
6249
6250 return 0;
6251}
6252
6253static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6254 struct ptp_clock_request *rq, int on)
6255{
92e6457d
NS		 6256 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6257 u32 clock_ctl;
6258 int rval = 0;
6259
6260 switch (rq->type) {
6261 case PTP_CLK_REQ_PEROUT:
6262 if (rq->perout.index != 0)
6263 return -EINVAL;
6264
6265 tg3_full_lock(tp, 0);
6266 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6267 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6268
6269 if (on) {
6270 u64 nsec;
6271
6272 nsec = rq->perout.start.sec * 1000000000ULL +
6273 rq->perout.start.nsec;
6274
6275 if (rq->perout.period.sec || rq->perout.period.nsec) {
6276 netdev_warn(tp->dev,
6277 "Device supports only a one-shot timesync output, period must be 0\n");
6278 rval = -EINVAL;
6279 goto err_out;
6280 }
6281
6282 if (nsec & (1ULL << 63)) {
6283 netdev_warn(tp->dev,
6284 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6285 rval = -EINVAL;
6286 goto err_out;
6287 }
6288
6289 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6290 tw32(TG3_EAV_WATCHDOG0_MSB,
6291 TG3_EAV_WATCHDOG0_EN |
6292 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6293
6294 tw32(TG3_EAV_REF_CLCK_CTL,
6295 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6296 } else {
6297 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6298 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6299 }
6300
6301err_out:
6302 tg3_full_unlock(tp);
6303 return rval;
6304
6305 default:
6306 break;
6307 }
6308
7d41e49a
MC		 6309 return -EOPNOTSUPP;
6310}
6311
6312static const struct ptp_clock_info tg3_ptp_caps = {
6313 .owner = THIS_MODULE,
6314 .name = "tg3 clock",
6315 .max_adj = 250000000,
6316 .n_alarm = 0,
6317 .n_ext_ts = 0,
92e6457d 6318 .n_per_out = 1,
4986b4f0 6319 .n_pins = 0,
7d41e49a
MC		 6320 .pps = 0,
6321 .adjfreq = tg3_ptp_adjfreq,
6322 .adjtime = tg3_ptp_adjtime,
6323 .gettime = tg3_ptp_gettime,
6324 .settime = tg3_ptp_settime,
6325 .enable = tg3_ptp_enable,
6326};
6327
fb4ce8ad
MC		 6328static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6329 struct skb_shared_hwtstamps *timestamp)
6330{
6331 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6332 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6333 tp->ptp_adjust);
6334}
6335
be947307
MC		 6336/* tp->lock must be held */
6337static void tg3_ptp_init(struct tg3 *tp)
6338{
6339 if (!tg3_flag(tp, PTP_CAPABLE))
6340 return;
6341
6342 /* Initialize the hardware clock to the system time. */
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6344 tp->ptp_adjust = 0;
7d41e49a 6345 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6346}
6347
6348/* tp->lock must be held */
6349static void tg3_ptp_resume(struct tg3 *tp)
6350{
6351 if (!tg3_flag(tp, PTP_CAPABLE))
6352 return;
6353
6354 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6355 tp->ptp_adjust = 0;
6356}
6357
6358static void tg3_ptp_fini(struct tg3 *tp)
6359{
6360 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6361 return;
6362
7d41e49a 6363 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6364 tp->ptp_clock = NULL;
6365 tp->ptp_adjust = 0;
6366}
6367
66cfd1bd
MC		 6368static inline int tg3_irq_sync(struct tg3 *tp)
6369{
6370 return tp->irq_sync;
6371}
6372
97bd8e49
MC		 6373static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6374{
6375 int i;
6376
6377 dst = (u32 *)((u8 *)dst + off);
6378 for (i = 0; i < len; i += sizeof(u32))
6379 *dst++ = tr32(off + i);
6380}
6381
6382static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6383{
6384 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6385 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6386 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6387 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6388 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6389 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6390 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6391 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6392 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6393 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6394 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6395 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6396 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6397 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6398 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6399 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6400 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6401 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6402 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6403
63c3a66f 6404 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6405 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6406
6407 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6408 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6409 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6410 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6411 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6412 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6413 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6414 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6415
63c3a66f 6416 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6417 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6419 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6420 }
6421
6422 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6423 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6424 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6425 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6426 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6427
63c3a66f 6428 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6429 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6430}
6431
6432static void tg3_dump_state(struct tg3 *tp)
6433{
6434 int i;
6435 u32 *regs;
6436
6437 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6438 if (!regs)
97bd8e49 6439 return;
97bd8e49 6440
63c3a66f 6441 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6442 /* Read up to but not including private PCI registers */
6443 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6444 regs[i / sizeof(u32)] = tr32(i);
6445 } else
6446 tg3_dump_legacy_regs(tp, regs);
6447
6448 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6449 if (!regs[i + 0] && !regs[i + 1] &&
6450 !regs[i + 2] && !regs[i + 3])
6451 continue;
6452
6453 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6454 i * 4,
6455 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6456 }
6457
6458 kfree(regs);
6459
6460 for (i = 0; i < tp->irq_cnt; i++) {
6461 struct tg3_napi *tnapi = &tp->napi[i];
6462
6463 /* SW status block */
6464 netdev_err(tp->dev,
6465 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6466 i,
6467 tnapi->hw_status->status,
6468 tnapi->hw_status->status_tag,
6469 tnapi->hw_status->rx_jumbo_consumer,
6470 tnapi->hw_status->rx_consumer,
6471 tnapi->hw_status->rx_mini_consumer,
6472 tnapi->hw_status->idx[0].rx_producer,
6473 tnapi->hw_status->idx[0].tx_consumer);
6474
6475 netdev_err(tp->dev,
6476 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6477 i,
6478 tnapi->last_tag, tnapi->last_irq_tag,
6479 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6480 tnapi->rx_rcb_ptr,
6481 tnapi->prodring.rx_std_prod_idx,
6482 tnapi->prodring.rx_std_cons_idx,
6483 tnapi->prodring.rx_jmb_prod_idx,
6484 tnapi->prodring.rx_jmb_cons_idx);
6485 }
6486}
6487
df3e6548
MC		 6488/* This is called whenever we suspect that the system chipset is re-
6489 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6490 * is bogus tx completions. We try to recover by setting the
6491 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6492 * in the workqueue.
6493 */
6494static void tg3_tx_recover(struct tg3 *tp)
6495{
63c3a66f 6496 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6497 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6498
5129c3a3
MC		 6499 netdev_warn(tp->dev,
6500 "The system may be re-ordering memory-mapped I/O "
6501 "cycles to the network device, attempting to recover. "
6502 "Please report the problem to the driver maintainer "
6503 "and include system chipset information.\n");
df3e6548 6504
63c3a66f 6505 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6506}
6507
f3f3f27e 6508static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6509{
f65aac16
MC		 6510 /* Tell compiler to fetch tx indices from memory. */
6511 barrier();
f3f3f27e
MC		 6512 return tnapi->tx_pending -
6513 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6514}
6515
1da177e4
LT		 6516/* Tigon3 never reports partial packet sends. So we do not
6517 * need special logic to handle SKBs that have not had all
6518 * of their frags sent yet, like SunGEM does.
6519 */
17375d25 6520static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6521{
17375d25 6522 struct tg3 *tp = tnapi->tp;
898a56f8 6523 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6524 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6525 struct netdev_queue *txq;
6526 int index = tnapi - tp->napi;
298376d3 6527 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6528
63c3a66f 6529 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6530 index--;
6531
6532 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6533
6534 while (sw_idx != hw_idx) {
df8944cf 6535 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6536 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6537 int i, tx_bug = 0;
6538
6539 if (unlikely(skb == NULL)) {
6540 tg3_tx_recover(tp);
6541 return;
6542 }
1da177e4 6543
fb4ce8ad
MC		 6544 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6545 struct skb_shared_hwtstamps timestamp;
6546 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6547 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6548
6549 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6550
6551 skb_tstamp_tx(skb, &timestamp);
6552 }
6553
f4188d8a 6554 pci_unmap_single(tp->pdev,
4e5e4f0d 6555 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6556 skb_headlen(skb),
6557 PCI_DMA_TODEVICE);
1da177e4
LT		 6558
6559 ri->skb = NULL;
6560
e01ee14d
MC		 6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6565 }
6566
1da177e4
LT		 6567 sw_idx = NEXT_TX(sw_idx);
6568
6569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6570 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6571 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6572 tx_bug = 1;
f4188d8a
AD		 6573
6574 pci_unmap_page(tp->pdev,
4e5e4f0d 6575 dma_unmap_addr(ri, mapping),
9e903e08 6576 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6577 PCI_DMA_TODEVICE);
e01ee14d
MC		 6578
6579 while (ri->fragmented) {
6580 ri->fragmented = false;
6581 sw_idx = NEXT_TX(sw_idx);
6582 ri = &tnapi->tx_buffers[sw_idx];
6583 }
6584
1da177e4
LT		 6585 sw_idx = NEXT_TX(sw_idx);
6586 }
6587
298376d3
TH		 6588 pkts_compl++;
6589 bytes_compl += skb->len;
6590
497a27b9 6591 dev_kfree_skb_any(skb);
df3e6548
MC		 6592
6593 if (unlikely(tx_bug)) {
6594 tg3_tx_recover(tp);
6595 return;
6596 }
1da177e4
LT		 6597 }
6598
5cb917bc 6599 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6600
f3f3f27e 6601 tnapi->tx_cons = sw_idx;
1da177e4 6602
1b2a7205
MC		 6603 /* Need to make the tx_cons update visible to tg3_start_xmit()
6604 * before checking for netif_queue_stopped(). Without the
6605 * memory barrier, there is a small possibility that tg3_start_xmit()
6606 * will miss it and cause the queue to be stopped forever.
6607 */
6608 smp_mb();
6609
fe5f5787 6610 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6611 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6612 __netif_tx_lock(txq, smp_processor_id());
6613 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6614 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6615 netif_tx_wake_queue(txq);
6616 __netif_tx_unlock(txq);
51b91468 6617 }
1da177e4
LT		 6618}
6619
8d4057a9
ED		 6620static void tg3_frag_free(bool is_frag, void *data)
6621{
6622 if (is_frag)
6623 put_page(virt_to_head_page(data));
6624 else
6625 kfree(data);
6626}
6627
9205fd9c 6628static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6629{
8d4057a9
ED		 6630 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6632
9205fd9c 6633 if (!ri->data)
2b2cdb65
MC		 6634 return;
6635
4e5e4f0d 6636 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6637 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6638 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6639 ri->data = NULL;
2b2cdb65
MC		 6640}
6641
8d4057a9 6642
1da177e4
LT		 6643/* Returns size of skb allocated or < 0 on error.
6644 *
6645 * We only need to fill in the address because the other members
6646 * of the RX descriptor are invariant, see tg3_init_rings.
6647 *
6648 * Note the purposeful assymetry of cpu vs. chip accesses. For
6649 * posting buffers we only dirty the first cache line of the RX
6650 * descriptor (containing the address). Whereas for the RX status
6651 * buffers the cpu only reads the last cacheline of the RX descriptor
6652 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6653 */
9205fd9c 6654static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6655 u32 opaque_key, u32 dest_idx_unmasked,
6656 unsigned int *frag_size)
1da177e4
LT		 6657{
6658 struct tg3_rx_buffer_desc *desc;
f94e290e 6659 struct ring_info *map;
9205fd9c 6660 u8 *data;
1da177e4 6661 dma_addr_t mapping;
9205fd9c 6662 int skb_size, data_size, dest_idx;
1da177e4 6663
1da177e4
LT		 6664 switch (opaque_key) {
6665 case RXD_OPAQUE_RING_STD:
2c49a44d 6666 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6667 desc = &tpr->rx_std[dest_idx];
6668 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6669 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6670 break;
6671
6672 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6673 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6674 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6675 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6676 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6677 break;
6678
6679 default:
6680 return -EINVAL;
855e1111 6681 }
1da177e4
LT		 6682
6683 /* Do not overwrite any of the map or rp information
6684 * until we are sure we can commit to a new buffer.
6685 *
6686 * Callers depend upon this behavior and assume that
6687 * we leave everything unchanged if we fail.
6688 */
9205fd9c
ED		 6689 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6690 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6691 if (skb_size <= PAGE_SIZE) {
6692 data = netdev_alloc_frag(skb_size);
6693 *frag_size = skb_size;
8d4057a9
ED		 6694 } else {
6695 data = kmalloc(skb_size, GFP_ATOMIC);
6696 *frag_size = 0;
6697 }
9205fd9c 6698 if (!data)
1da177e4
LT		 6699 return -ENOMEM;
6700
9205fd9c
ED		 6701 mapping = pci_map_single(tp->pdev,
6702 data + TG3_RX_OFFSET(tp),
6703 data_size,
1da177e4 6704 PCI_DMA_FROMDEVICE);
8d4057a9 6705 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6706 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6707 return -EIO;
6708 }
1da177e4 6709
9205fd9c 6710 map->data = data;
4e5e4f0d 6711 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6712
1da177e4
LT		 6713 desc->addr_hi = ((u64)mapping >> 32);
6714 desc->addr_lo = ((u64)mapping & 0xffffffff);
6715
9205fd9c 6716 return data_size;
1da177e4
LT		 6717}
6718
6719/* We only need to move over in the address because the other
6720 * members of the RX descriptor are invariant. See notes above
9205fd9c 6721 * tg3_alloc_rx_data for full details.
1da177e4 6722 */
a3896167
MC		 6723static void tg3_recycle_rx(struct tg3_napi *tnapi,
6724 struct tg3_rx_prodring_set *dpr,
6725 u32 opaque_key, int src_idx,
6726 u32 dest_idx_unmasked)
1da177e4 6727{
17375d25 6728 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6729 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6730 struct ring_info *src_map, *dest_map;
8fea32b9 6731 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6732 int dest_idx;
1da177e4
LT		 6733
6734 switch (opaque_key) {
6735 case RXD_OPAQUE_RING_STD:
2c49a44d 6736 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6737 dest_desc = &dpr->rx_std[dest_idx];
6738 dest_map = &dpr->rx_std_buffers[dest_idx];
6739 src_desc = &spr->rx_std[src_idx];
6740 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6741 break;
6742
6743 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6744 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6745 dest_desc = &dpr->rx_jmb[dest_idx].std;
6746 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6747 src_desc = &spr->rx_jmb[src_idx].std;
6748 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6749 break;
6750
6751 default:
6752 return;
855e1111 6753 }
1da177e4 6754
9205fd9c 6755 dest_map->data = src_map->data;
4e5e4f0d
FT		 6756 dma_unmap_addr_set(dest_map, mapping,
6757 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6758 dest_desc->addr_hi = src_desc->addr_hi;
6759 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6760
6761 /* Ensure that the update to the skb happens after the physical
6762 * addresses have been transferred to the new BD location.
6763 */
6764 smp_wmb();
6765
9205fd9c 6766 src_map->data = NULL;
1da177e4
LT		 6767}
6768
1da177e4
LT		 6769/* The RX ring scheme is composed of multiple rings which post fresh
6770 * buffers to the chip, and one special ring the chip uses to report
6771 * status back to the host.
6772 *
6773 * The special ring reports the status of received packets to the
6774 * host. The chip does not write into the original descriptor the
6775 * RX buffer was obtained from. The chip simply takes the original
6776 * descriptor as provided by the host, updates the status and length
6777 * field, then writes this into the next status ring entry.
6778 *
6779 * Each ring the host uses to post buffers to the chip is described
6780 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6781 * it is first placed into the on-chip ram. When the packet's length
6782 * is known, it walks down the TG3_BDINFO entries to select the ring.
6783 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6784 * which is within the range of the new packet's length is chosen.
6785 *
6786 * The "separate ring for rx status" scheme may sound queer, but it makes
6787 * sense from a cache coherency perspective. If only the host writes
6788 * to the buffer post rings, and only the chip writes to the rx status
6789 * rings, then cache lines never move beyond shared-modified state.
6790 * If both the host and chip were to write into the same ring, cache line
6791 * eviction could occur since both entities want it in an exclusive state.
6792 */
17375d25 6793static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6794{
17375d25 6795 struct tg3 *tp = tnapi->tp;
f92905de 6796 u32 work_mask, rx_std_posted = 0;
4361935a 6797 u32 std_prod_idx, jmb_prod_idx;
72334482 6798 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6799 u16 hw_idx;
1da177e4 6800 int received;
8fea32b9 6801 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6802
8d9d7cfc 6803 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6804 /*
6805 * We need to order the read of hw_idx and the read of
6806 * the opaque cookie.
6807 */
6808 rmb();
1da177e4
LT		 6809 work_mask = 0;
6810 received = 0;
4361935a
MC		 6811 std_prod_idx = tpr->rx_std_prod_idx;
6812 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6813 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6814 struct ring_info *ri;
72334482 6815 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6816 unsigned int len;
6817 struct sk_buff *skb;
6818 dma_addr_t dma_addr;
6819 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6820 u8 *data;
fb4ce8ad 6821 u64 tstamp = 0;
1da177e4
LT		 6822
6823 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6824 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6825 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6826 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6827 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6828 data = ri->data;
4361935a 6829 post_ptr = &std_prod_idx;
f92905de 6830 rx_std_posted++;
1da177e4 6831 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6832 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6833 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6834 data = ri->data;
4361935a 6835 post_ptr = &jmb_prod_idx;
21f581a5 6836 } else
1da177e4 6837 goto next_pkt_nopost;
1da177e4
LT		 6838
6839 work_mask |= opaque_key;
6840
d7b95315 6841 if (desc->err_vlan & RXD_ERR_MASK) {
1da177e4 6842 drop_it:
a3896167 6843 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6844 desc_idx, *post_ptr);
6845 drop_it_no_recycle:
6846 /* Other statistics kept track of by card. */
b0057c51 6847 tp->rx_dropped++;
1da177e4
LT		 6848 goto next_pkt;
6849 }
6850
9205fd9c 6851 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6852 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6853 ETH_FCS_LEN;
1da177e4 6854
fb4ce8ad
MC		 6855 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6856 RXD_FLAG_PTPSTAT_PTPV1 ||
6857 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6858 RXD_FLAG_PTPSTAT_PTPV2) {
6859 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6860 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6861 }
6862
d2757fc4 6863 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6864 int skb_size;
8d4057a9 6865 unsigned int frag_size;
1da177e4 6866
9205fd9c 6867 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6868 *post_ptr, &frag_size);
1da177e4
LT		 6869 if (skb_size < 0)
6870 goto drop_it;
6871
287be12e 6872 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6873 PCI_DMA_FROMDEVICE);
6874
9205fd9c 6875 /* Ensure that the update to the data happens
61e800cf
MC		 6876 * after the usage of the old DMA mapping.
6877 */
6878 smp_wmb();
6879
9205fd9c 6880 ri->data = NULL;
61e800cf 6881
85aec73d
IV		 6882 skb = build_skb(data, frag_size);
6883 if (!skb) {
6884 tg3_frag_free(frag_size != 0, data);
6885 goto drop_it_no_recycle;
6886 }
6887 skb_reserve(skb, TG3_RX_OFFSET(tp));
1da177e4 6888 } else {
a3896167 6889 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6890 desc_idx, *post_ptr);
6891
9205fd9c
ED		 6892 skb = netdev_alloc_skb(tp->dev,
6893 len + TG3_RAW_IP_ALIGN);
6894 if (skb == NULL)
1da177e4
LT		 6895 goto drop_it_no_recycle;
6896
9205fd9c 6897 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6898 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6899 memcpy(skb->data,
6900 data + TG3_RX_OFFSET(tp),
6901 len);
1da177e4 6902 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6903 }
6904
9205fd9c 6905 skb_put(skb, len);
fb4ce8ad
MC		 6906 if (tstamp)
6907 tg3_hwclock_to_timestamp(tp, tstamp,
6908 skb_hwtstamps(skb));
6909
dc668910 6910 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6911 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6912 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6913 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6914 skb->ip_summed = CHECKSUM_UNNECESSARY;
6915 else
bc8acf2c 6916 skb_checksum_none_assert(skb);
1da177e4
LT		 6917
6918 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6919
6920 if (len > (tp->dev->mtu + ETH_HLEN) &&
7d3083ee
VY		 6921 skb->protocol != htons(ETH_P_8021Q) &&
6922 skb->protocol != htons(ETH_P_8021AD)) {
497a27b9 6923 dev_kfree_skb_any(skb);
b0057c51 6924 goto drop_it_no_recycle;
f7b493e0
MC		 6925 }
6926
9dc7a113 6927 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6928 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6929 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6930 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6931
bf933c80 6932 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6933
1da177e4
LT		 6934 received++;
6935 budget--;
6936
6937next_pkt:
6938 (*post_ptr)++;
f92905de
MC		 6939
6940 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6941 tpr->rx_std_prod_idx = std_prod_idx &
6942 tp->rx_std_ring_mask;
86cfe4ff
MC		 6943 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6944 tpr->rx_std_prod_idx);
f92905de
MC		 6945 work_mask &= ~RXD_OPAQUE_RING_STD;
6946 rx_std_posted = 0;
6947 }
1da177e4 6948next_pkt_nopost:
483ba50b 6949 sw_idx++;
7cb32cf2 6950 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6951
6952 /* Refresh hw_idx to see if there is new work */
6953 if (sw_idx == hw_idx) {
8d9d7cfc 6954 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6955 rmb();
6956 }
1da177e4
LT		 6957 }
6958
6959 /* ACK the status ring. */
72334482
MC		 6960 tnapi->rx_rcb_ptr = sw_idx;
6961 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6962
6963 /* Refill RX ring(s). */
63c3a66f 6964 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6965 /* Sync BD data before updating mailbox */
6966 wmb();
6967
b196c7e4 6968 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6969 tpr->rx_std_prod_idx = std_prod_idx &
6970 tp->rx_std_ring_mask;
b196c7e4
MC		 6971 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6972 tpr->rx_std_prod_idx);
6973 }
6974 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6975 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6976 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6977 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6978 tpr->rx_jmb_prod_idx);
6979 }
6980 mmiowb();
6981 } else if (work_mask) {
6982 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6983 * updated before the producer indices can be updated.
6984 */
6985 smp_wmb();
6986
2c49a44d
MC		 6987 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6988 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6989
7ae52890
MC		 6990 if (tnapi != &tp->napi[1]) {
6991 tp->rx_refill = true;
e4af1af9 6992 napi_schedule(&tp->napi[1].napi);
7ae52890 6993 }
1da177e4 6994 }
1da177e4
LT		 6995
6996 return received;
6997}
6998
35f2d7d0 6999static void tg3_poll_link(struct tg3 *tp)
1da177e4 7000{
1da177e4 7001 /* handle link change and other phy events */
63c3a66f 7002 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 7003 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7004
1da177e4
LT		 7005 if (sblk->status & SD_STATUS_LINK_CHG) {
7006 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 7007 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 7008 spin_lock(&tp->lock);
63c3a66f 7009 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 7010 tw32_f(MAC_STATUS,
7011 (MAC_STATUS_SYNC_CHANGED |
7012 MAC_STATUS_CFG_CHANGED |
7013 MAC_STATUS_MI_COMPLETION |
7014 MAC_STATUS_LNKSTATE_CHANGED));
7015 udelay(40);
7016 } else
953c96e0 7017 tg3_setup_phy(tp, false);
f47c11ee 7018 spin_unlock(&tp->lock);
1da177e4
LT		 7019 }
7020 }
35f2d7d0
MC		 7021}
7022
f89f38b8
MC		 7023static int tg3_rx_prodring_xfer(struct tg3 *tp,
7024 struct tg3_rx_prodring_set *dpr,
7025 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7026{
7027 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7028 int i, err = 0;
b196c7e4
MC		 7029
7030 while (1) {
7031 src_prod_idx = spr->rx_std_prod_idx;
7032
7033 /* Make sure updates to the rx_std_buffers[] entries and the
7034 * standard producer index are seen in the correct order.
7035 */
7036 smp_rmb();
7037
7038 if (spr->rx_std_cons_idx == src_prod_idx)
7039 break;
7040
7041 if (spr->rx_std_cons_idx < src_prod_idx)
7042 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7043 else
2c49a44d
MC		 7044 cpycnt = tp->rx_std_ring_mask + 1 -
7045 spr->rx_std_cons_idx;
b196c7e4 7046
2c49a44d
MC		 7047 cpycnt = min(cpycnt,
7048 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7049
7050 si = spr->rx_std_cons_idx;
7051 di = dpr->rx_std_prod_idx;
7052
e92967bf 7053 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7054 if (dpr->rx_std_buffers[i].data) {
e92967bf 7055 cpycnt = i - di;
f89f38b8 7056 err = -ENOSPC;
e92967bf
MC		 7057 break;
7058 }
7059 }
7060
7061 if (!cpycnt)
7062 break;
7063
7064 /* Ensure that updates to the rx_std_buffers ring and the
7065 * shadowed hardware producer ring from tg3_recycle_skb() are
7066 * ordered correctly WRT the skb check above.
7067 */
7068 smp_rmb();
7069
b196c7e4
MC		 7070 memcpy(&dpr->rx_std_buffers[di],
7071 &spr->rx_std_buffers[si],
7072 cpycnt * sizeof(struct ring_info));
7073
7074 for (i = 0; i < cpycnt; i++, di++, si++) {
7075 struct tg3_rx_buffer_desc *sbd, *dbd;
7076 sbd = &spr->rx_std[si];
7077 dbd = &dpr->rx_std[di];
7078 dbd->addr_hi = sbd->addr_hi;
7079 dbd->addr_lo = sbd->addr_lo;
7080 }
7081
2c49a44d
MC		 7082 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7083 tp->rx_std_ring_mask;
7084 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7085 tp->rx_std_ring_mask;
b196c7e4
MC		 7086 }
7087
7088 while (1) {
7089 src_prod_idx = spr->rx_jmb_prod_idx;
7090
7091 /* Make sure updates to the rx_jmb_buffers[] entries and
7092 * the jumbo producer index are seen in the correct order.
7093 */
7094 smp_rmb();
7095
7096 if (spr->rx_jmb_cons_idx == src_prod_idx)
7097 break;
7098
7099 if (spr->rx_jmb_cons_idx < src_prod_idx)
7100 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7101 else
2c49a44d
MC		 7102 cpycnt = tp->rx_jmb_ring_mask + 1 -
7103 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7104
7105 cpycnt = min(cpycnt,
2c49a44d 7106 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7107
7108 si = spr->rx_jmb_cons_idx;
7109 di = dpr->rx_jmb_prod_idx;
7110
e92967bf 7111 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7112 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7113 cpycnt = i - di;
f89f38b8 7114 err = -ENOSPC;
e92967bf
MC		 7115 break;
7116 }
7117 }
7118
7119 if (!cpycnt)
7120 break;
7121
7122 /* Ensure that updates to the rx_jmb_buffers ring and the
7123 * shadowed hardware producer ring from tg3_recycle_skb() are
7124 * ordered correctly WRT the skb check above.
7125 */
7126 smp_rmb();
7127
b196c7e4
MC		 7128 memcpy(&dpr->rx_jmb_buffers[di],
7129 &spr->rx_jmb_buffers[si],
7130 cpycnt * sizeof(struct ring_info));
7131
7132 for (i = 0; i < cpycnt; i++, di++, si++) {
7133 struct tg3_rx_buffer_desc *sbd, *dbd;
7134 sbd = &spr->rx_jmb[si].std;
7135 dbd = &dpr->rx_jmb[di].std;
7136 dbd->addr_hi = sbd->addr_hi;
7137 dbd->addr_lo = sbd->addr_lo;
7138 }
7139
2c49a44d
MC		 7140 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7141 tp->rx_jmb_ring_mask;
7142 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7143 tp->rx_jmb_ring_mask;
b196c7e4 7144 }
f89f38b8
MC		 7145
7146 return err;
b196c7e4
MC		 7147}
7148
35f2d7d0
MC		 7149static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7150{
7151 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7152
7153 /* run TX completion thread */
f3f3f27e 7154 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7155 tg3_tx(tnapi);
63c3a66f 7156 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7157 return work_done;
1da177e4
LT		 7158 }
7159
f891ea16
MC		 7160 if (!tnapi->rx_rcb_prod_idx)
7161 return work_done;
7162
1da177e4
LT		 7163 /* run RX thread, within the bounds set by NAPI.
7164 * All RX "locking" is done by ensuring outside
bea3348e 7165 * code synchronizes with tg3->napi.poll()
1da177e4 7166 */
8d9d7cfc 7167 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7168 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7169
63c3a66f 7170 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7171 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7172 int i, err = 0;
e4af1af9
MC		 7173 u32 std_prod_idx = dpr->rx_std_prod_idx;
7174 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7175
7ae52890 7176 tp->rx_refill = false;
9102426a 7177 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7178 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7179 &tp->napi[i].prodring);
b196c7e4
MC		 7180
7181 wmb();
7182
e4af1af9
MC		 7183 if (std_prod_idx != dpr->rx_std_prod_idx)
7184 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7185 dpr->rx_std_prod_idx);
b196c7e4 7186
e4af1af9
MC		 7187 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7188 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7189 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7190
7191 mmiowb();
f89f38b8
MC		 7192
7193 if (err)
7194 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7195 }
7196
6f535763
DM		 7197 return work_done;
7198}
7199
db219973
MC		 7200static inline void tg3_reset_task_schedule(struct tg3 *tp)
7201{
7202 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7203 schedule_work(&tp->reset_task);
7204}
7205
7206static inline void tg3_reset_task_cancel(struct tg3 *tp)
7207{
7208 cancel_work_sync(&tp->reset_task);
7209 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7210 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7211}
7212
35f2d7d0
MC		 7213static int tg3_poll_msix(struct napi_struct *napi, int budget)
7214{
7215 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7216 struct tg3 *tp = tnapi->tp;
7217 int work_done = 0;
7218 struct tg3_hw_status *sblk = tnapi->hw_status;
7219
7220 while (1) {
7221 work_done = tg3_poll_work(tnapi, work_done, budget);
7222
63c3a66f 7223 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7224 goto tx_recovery;
7225
7226 if (unlikely(work_done >= budget))
7227 break;
7228
c6cdf436 7229 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7230 * to tell the hw how much work has been processed,
7231 * so we must read it before checking for more work.
7232 */
7233 tnapi->last_tag = sblk->status_tag;
7234 tnapi->last_irq_tag = tnapi->last_tag;
7235 rmb();
7236
7237 /* check for RX/TX work to do */
6d40db7b
MC		 7238 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7239 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7240
7241 /* This test here is not race free, but will reduce
7242 * the number of interrupts by looping again.
7243 */
7244 if (tnapi == &tp->napi[1] && tp->rx_refill)
7245 continue;
7246
35f2d7d0
MC		 7247 napi_complete(napi);
7248 /* Reenable interrupts. */
7249 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7250
7251 /* This test here is synchronized by napi_schedule()
7252 * and napi_complete() to close the race condition.
7253 */
7254 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7255 tw32(HOSTCC_MODE, tp->coalesce_mode |
7256 HOSTCC_MODE_ENABLE |
7257 tnapi->coal_now);
7258 }
35f2d7d0
MC		 7259 mmiowb();
7260 break;
7261 }
7262 }
7263
7264 return work_done;
7265
7266tx_recovery:
7267 /* work_done is guaranteed to be less than budget. */
7268 napi_complete(napi);
db219973 7269 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7270 return work_done;
7271}
7272
e64de4e6
MC		 7273static void tg3_process_error(struct tg3 *tp)
7274{
7275 u32 val;
7276 bool real_error = false;
7277
63c3a66f 7278 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7279 return;
7280
7281 /* Check Flow Attention register */
7282 val = tr32(HOSTCC_FLOW_ATTN);
7283 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7284 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7285 real_error = true;
7286 }
7287
7288 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7289 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7290 real_error = true;
7291 }
7292
7293 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7294 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7295 real_error = true;
7296 }
7297
7298 if (!real_error)
7299 return;
7300
7301 tg3_dump_state(tp);
7302
63c3a66f 7303 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7304 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7305}
7306
6f535763
DM		 7307static int tg3_poll(struct napi_struct *napi, int budget)
7308{
8ef0442f
MC		 7309 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7310 struct tg3 *tp = tnapi->tp;
6f535763 7311 int work_done = 0;
898a56f8 7312 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7313
7314 while (1) {
e64de4e6
MC		 7315 if (sblk->status & SD_STATUS_ERROR)
7316 tg3_process_error(tp);
7317
35f2d7d0
MC		 7318 tg3_poll_link(tp);
7319
17375d25 7320 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7321
63c3a66f 7322 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7323 goto tx_recovery;
7324
7325 if (unlikely(work_done >= budget))
7326 break;
7327
63c3a66f 7328 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7329 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7330 * to tell the hw how much work has been processed,
7331 * so we must read it before checking for more work.
7332 */
898a56f8
MC		 7333 tnapi->last_tag = sblk->status_tag;
7334 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7335 rmb();
7336 } else
7337 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7338
17375d25 7339 if (likely(!tg3_has_work(tnapi))) {
288379f0 7340 napi_complete(napi);
17375d25 7341 tg3_int_reenable(tnapi);
6f535763
DM		 7342 break;
7343 }
1da177e4
LT		 7344 }
7345
bea3348e 7346 return work_done;
6f535763
DM		 7347
7348tx_recovery:
4fd7ab59 7349 /* work_done is guaranteed to be less than budget. */
288379f0 7350 napi_complete(napi);
db219973 7351 tg3_reset_task_schedule(tp);
4fd7ab59 7352 return work_done;
1da177e4
LT		 7353}
7354
66cfd1bd
MC		 7355static void tg3_napi_disable(struct tg3 *tp)
7356{
7357 int i;
7358
7359 for (i = tp->irq_cnt - 1; i >= 0; i--)
7360 napi_disable(&tp->napi[i].napi);
7361}
7362
7363static void tg3_napi_enable(struct tg3 *tp)
7364{
7365 int i;
7366
7367 for (i = 0; i < tp->irq_cnt; i++)
7368 napi_enable(&tp->napi[i].napi);
7369}
7370
7371static void tg3_napi_init(struct tg3 *tp)
7372{
7373 int i;
7374
7375 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7376 for (i = 1; i < tp->irq_cnt; i++)
7377 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7378}
7379
7380static void tg3_napi_fini(struct tg3 *tp)
7381{
7382 int i;
7383
7384 for (i = 0; i < tp->irq_cnt; i++)
7385 netif_napi_del(&tp->napi[i].napi);
7386}
7387
7388static inline void tg3_netif_stop(struct tg3 *tp)
7389{
7390 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7391 tg3_napi_disable(tp);
f4a46d1f 7392 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7393 netif_tx_disable(tp->dev);
7394}
7395
35763066 7396/* tp->lock must be held */
66cfd1bd
MC		 7397static inline void tg3_netif_start(struct tg3 *tp)
7398{
be947307
MC		 7399 tg3_ptp_resume(tp);
7400
66cfd1bd
MC		 7401 /* NOTE: unconditional netif_tx_wake_all_queues is only
7402 * appropriate so long as all callers are assured to
7403 * have free tx slots (such as after tg3_init_hw)
7404 */
7405 netif_tx_wake_all_queues(tp->dev);
7406
f4a46d1f
NNS		 7407 if (tp->link_up)
7408 netif_carrier_on(tp->dev);
7409
66cfd1bd
MC		 7410 tg3_napi_enable(tp);
7411 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7412 tg3_enable_ints(tp);
7413}
7414
f47c11ee
DM		 7415static void tg3_irq_quiesce(struct tg3 *tp)
7416{
4f125f42
MC		 7417 int i;
7418
f47c11ee
DM		 7419 BUG_ON(tp->irq_sync);
7420
7421 tp->irq_sync = 1;
7422 smp_mb();
7423
4f125f42
MC		 7424 for (i = 0; i < tp->irq_cnt; i++)
7425 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7426}
7427
f47c11ee
DM		 7428/* Fully shutdown all tg3 driver activity elsewhere in the system.
7429 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7430 * with as well. Most of the time, this is not necessary except when
7431 * shutting down the device.
7432 */
7433static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7434{
46966545 7435 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7436 if (irq_sync)
7437 tg3_irq_quiesce(tp);
f47c11ee
DM		 7438}
7439
7440static inline void tg3_full_unlock(struct tg3 *tp)
7441{
f47c11ee
DM		 7442 spin_unlock_bh(&tp->lock);
7443}
7444
fcfa0a32
MC		 7445/* One-shot MSI handler - Chip automatically disables interrupt
7446 * after sending MSI so driver doesn't have to do it.
7447 */
7d12e780 7448static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7449{
09943a18
MC		 7450 struct tg3_napi *tnapi = dev_id;
7451 struct tg3 *tp = tnapi->tp;
fcfa0a32 7452
898a56f8 7453 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7454 if (tnapi->rx_rcb)
7455 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7456
7457 if (likely(!tg3_irq_sync(tp)))
09943a18 7458 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7459
7460 return IRQ_HANDLED;
7461}
7462
88b06bc2
MC		 7463/* MSI ISR - No need to check for interrupt sharing and no need to
7464 * flush status block and interrupt mailbox. PCI ordering rules
7465 * guarantee that MSI will arrive after the status block.
7466 */
7d12e780 7467static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7468{
09943a18
MC		 7469 struct tg3_napi *tnapi = dev_id;
7470 struct tg3 *tp = tnapi->tp;
88b06bc2 7471
898a56f8 7472 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7473 if (tnapi->rx_rcb)
7474 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7475 /*
fac9b83e 7476 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7477 * chip-internal interrupt pending events.
fac9b83e 7478 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7479 * NIC to stop sending us irqs, engaging "in-intr-handler"
7480 * event coalescing.
7481 */
5b39de91 7482 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7483 if (likely(!tg3_irq_sync(tp)))
09943a18 7484 napi_schedule(&tnapi->napi);
61487480 7485
88b06bc2
MC		 7486 return IRQ_RETVAL(1);
7487}
7488
7d12e780 7489static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7490{
09943a18
MC		 7491 struct tg3_napi *tnapi = dev_id;
7492 struct tg3 *tp = tnapi->tp;
898a56f8 7493 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7494 unsigned int handled = 1;
7495
1da177e4
LT		 7496 /* In INTx mode, it is possible for the interrupt to arrive at
7497 * the CPU before the status block posted prior to the interrupt.
7498 * Reading the PCI State register will confirm whether the
7499 * interrupt is ours and will flush the status block.
7500 */
d18edcb2 7501 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7502 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7503 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7504 handled = 0;
f47c11ee 7505 goto out;
fac9b83e 7506 }
d18edcb2
MC		 7507 }
7508
7509 /*
7510 * Writing any value to intr-mbox-0 clears PCI INTA# and
7511 * chip-internal interrupt pending events.
7512 * Writing non-zero to intr-mbox-0 additional tells the
7513 * NIC to stop sending us irqs, engaging "in-intr-handler"
7514 * event coalescing.
c04cb347
MC		 7515 *
7516 * Flush the mailbox to de-assert the IRQ immediately to prevent
7517 * spurious interrupts. The flush impacts performance but
7518 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7519 */
c04cb347 7520 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7521 if (tg3_irq_sync(tp))
7522 goto out;
7523 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7524 if (likely(tg3_has_work(tnapi))) {
72334482 7525 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7526 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7527 } else {
7528 /* No work, shared interrupt perhaps? re-enable
7529 * interrupts, and flush that PCI write
7530 */
7531 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7532 0x00000000);
fac9b83e 7533 }
f47c11ee 7534out:
fac9b83e
DM		 7535 return IRQ_RETVAL(handled);
7536}
7537
7d12e780 7538static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7539{
09943a18
MC		 7540 struct tg3_napi *tnapi = dev_id;
7541 struct tg3 *tp = tnapi->tp;
898a56f8 7542 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7543 unsigned int handled = 1;
7544
fac9b83e
DM		 7545 /* In INTx mode, it is possible for the interrupt to arrive at
7546 * the CPU before the status block posted prior to the interrupt.
7547 * Reading the PCI State register will confirm whether the
7548 * interrupt is ours and will flush the status block.
7549 */
898a56f8 7550 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7551 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7552 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7553 handled = 0;
f47c11ee 7554 goto out;
1da177e4 7555 }
d18edcb2
MC		 7556 }
7557
7558 /*
7559 * writing any value to intr-mbox-0 clears PCI INTA# and
7560 * chip-internal interrupt pending events.
7561 * writing non-zero to intr-mbox-0 additional tells the
7562 * NIC to stop sending us irqs, engaging "in-intr-handler"
7563 * event coalescing.
c04cb347
MC		 7564 *
7565 * Flush the mailbox to de-assert the IRQ immediately to prevent
7566 * spurious interrupts. The flush impacts performance but
7567 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7568 */
c04cb347 7569 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7570
7571 /*
7572 * In a shared interrupt configuration, sometimes other devices'
7573 * interrupts will scream. We record the current status tag here
7574 * so that the above check can report that the screaming interrupts
7575 * are unhandled. Eventually they will be silenced.
7576 */
898a56f8 7577 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7578
d18edcb2
MC		 7579 if (tg3_irq_sync(tp))
7580 goto out;
624f8e50 7581
72334482 7582 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7583
09943a18 7584 napi_schedule(&tnapi->napi);
624f8e50 7585
f47c11ee 7586out:
1da177e4
LT		 7587 return IRQ_RETVAL(handled);
7588}
7589
7938109f 7590/* ISR for interrupt test */
7d12e780 7591static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7592{
09943a18
MC		 7593 struct tg3_napi *tnapi = dev_id;
7594 struct tg3 *tp = tnapi->tp;
898a56f8 7595 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7596
f9804ddb
MC		 7597 if ((sblk->status & SD_STATUS_UPDATED) ||
7598 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7599 tg3_disable_ints(tp);
7938109f
MC		 7600 return IRQ_RETVAL(1);
7601 }
7602 return IRQ_RETVAL(0);
7603}
7604
1da177e4
LT		 7605#ifdef CONFIG_NET_POLL_CONTROLLER
7606static void tg3_poll_controller(struct net_device *dev)
7607{
4f125f42 7608 int i;
88b06bc2
MC		 7609 struct tg3 *tp = netdev_priv(dev);
7610
9c13cb8b
NNS		 7611 if (tg3_irq_sync(tp))
7612 return;
7613
4f125f42 7614 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7615 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7616}
7617#endif
7618
1da177e4
LT		 7619static void tg3_tx_timeout(struct net_device *dev)
7620{
7621 struct tg3 *tp = netdev_priv(dev);
7622
b0408751 7623 if (netif_msg_tx_err(tp)) {
05dbe005 7624 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7625 tg3_dump_state(tp);
b0408751 7626 }
1da177e4 7627
db219973 7628 tg3_reset_task_schedule(tp);
1da177e4
LT		 7629}
7630
c58ec932
MC		 7631/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7632static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7633{
7634 u32 base = (u32) mapping & 0xffffffff;
7635
37567910 7636 return base + len + 8 < base;
c58ec932
MC		 7637}
7638
0f0d1510
MC		 7639/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7640 * of any 4GB boundaries: 4G, 8G, etc
7641 */
7642static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7643 u32 len, u32 mss)
7644{
7645 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7646 u32 base = (u32) mapping & 0xffffffff;
7647
7648 return ((base + len + (mss & 0x3fff)) < base);
7649 }
7650 return 0;
7651}
7652
72f2afb8
MC		 7653/* Test for DMA addresses > 40-bit */
7654static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7655 int len)
7656{
7657#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7658 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7659 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7660 return 0;
7661#else
7662 return 0;
7663#endif
7664}
7665
d1a3b737 7666static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7667 dma_addr_t mapping, u32 len, u32 flags,
7668 u32 mss, u32 vlan)
2ffcc981 7669{
92cd3a17
MC		 7670 txbd->addr_hi = ((u64) mapping >> 32);
7671 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7672 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7673 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7674}
1da177e4 7675
84b67b27 7676static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7677 dma_addr_t map, u32 len, u32 flags,
7678 u32 mss, u32 vlan)
7679{
7680 struct tg3 *tp = tnapi->tp;
7681 bool hwbug = false;
7682
7683 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7684 hwbug = true;
d1a3b737
MC		 7685
7686 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7687 hwbug = true;
d1a3b737 7688
0f0d1510
MC		 7689 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7690 hwbug = true;
7691
d1a3b737 7692 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7693 hwbug = true;
d1a3b737 7694
a4cb428d 7695 if (tp->dma_limit) {
b9e45482 7696 u32 prvidx = *entry;
e31aa987 7697 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7698 while (len > tp->dma_limit && *budget) {
7699 u32 frag_len = tp->dma_limit;
7700 len -= tp->dma_limit;
e31aa987 7701
b9e45482
MC		 7702 /* Avoid the 8byte DMA problem */
7703 if (len <= 8) {
a4cb428d
MC		 7704 len += tp->dma_limit / 2;
7705 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7706 }
7707
b9e45482
MC		 7708 tnapi->tx_buffers[*entry].fragmented = true;
7709
7710 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7711 frag_len, tmp_flag, mss, vlan);
7712 *budget -= 1;
7713 prvidx = *entry;
7714 *entry = NEXT_TX(*entry);
7715
e31aa987
MC		 7716 map += frag_len;
7717 }
7718
7719 if (len) {
7720 if (*budget) {
7721 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7722 len, flags, mss, vlan);
b9e45482 7723 *budget -= 1;
e31aa987
MC		 7724 *entry = NEXT_TX(*entry);
7725 } else {
3db1cd5c 7726 hwbug = true;
b9e45482 7727 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7728 }
7729 }
7730 } else {
84b67b27
MC		 7731 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7732 len, flags, mss, vlan);
e31aa987
MC		 7733 *entry = NEXT_TX(*entry);
7734 }
d1a3b737
MC		 7735
7736 return hwbug;
7737}
7738
0d681b27 7739static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7740{
7741 int i;
0d681b27 7742 struct sk_buff *skb;
df8944cf 7743 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7744
0d681b27
MC		 7745 skb = txb->skb;
7746 txb->skb = NULL;
7747
432aa7ed
MC		 7748 pci_unmap_single(tnapi->tp->pdev,
7749 dma_unmap_addr(txb, mapping),
7750 skb_headlen(skb),
7751 PCI_DMA_TODEVICE);
e01ee14d
MC		 7752
7753 while (txb->fragmented) {
7754 txb->fragmented = false;
7755 entry = NEXT_TX(entry);
7756 txb = &tnapi->tx_buffers[entry];
7757 }
7758
ba1142e4 7759 for (i = 0; i <= last; i++) {
9e903e08 7760 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7761
7762 entry = NEXT_TX(entry);
7763 txb = &tnapi->tx_buffers[entry];
7764
7765 pci_unmap_page(tnapi->tp->pdev,
7766 dma_unmap_addr(txb, mapping),
9e903e08 7767 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7768
7769 while (txb->fragmented) {
7770 txb->fragmented = false;
7771 entry = NEXT_TX(entry);
7772 txb = &tnapi->tx_buffers[entry];
7773 }
432aa7ed
MC		 7774 }
7775}
7776
72f2afb8 7777/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7778static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7779 struct sk_buff **pskb,
84b67b27 7780 u32 *entry, u32 *budget,
92cd3a17 7781 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7782{
24f4efd4 7783 struct tg3 *tp = tnapi->tp;
f7ff1987 7784 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7785 dma_addr_t new_addr = 0;
432aa7ed 7786 int ret = 0;
1da177e4 7787
4153577a 7788 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7789 new_skb = skb_copy(skb, GFP_ATOMIC);
7790 else {
7791 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7792
7793 new_skb = skb_copy_expand(skb,
7794 skb_headroom(skb) + more_headroom,
7795 skb_tailroom(skb), GFP_ATOMIC);
7796 }
7797
1da177e4 7798 if (!new_skb) {
c58ec932
MC		 7799 ret = -1;
7800 } else {
7801 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7802 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7803 PCI_DMA_TODEVICE);
7804 /* Make sure the mapping succeeded */
7805 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
497a27b9 7806 dev_kfree_skb_any(new_skb);
c58ec932 7807 ret = -1;
c58ec932 7808 } else {
b9e45482
MC		 7809 u32 save_entry = *entry;
7810
92cd3a17
MC		 7811 base_flags |= TXD_FLAG_END;
7812
84b67b27
MC		 7813 tnapi->tx_buffers[*entry].skb = new_skb;
7814 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7815 mapping, new_addr);
7816
84b67b27 7817 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7818 new_skb->len, base_flags,
7819 mss, vlan)) {
ba1142e4 7820 tg3_tx_skb_unmap(tnapi, save_entry, -1);
497a27b9 7821 dev_kfree_skb_any(new_skb);
d1a3b737
MC		 7822 ret = -1;
7823 }
f4188d8a 7824 }
1da177e4
LT		 7825 }
7826
497a27b9 7827 dev_kfree_skb_any(skb);
f7ff1987 7828 *pskb = new_skb;
c58ec932 7829 return ret;
1da177e4
LT		 7830}
7831
2ffcc981 7832static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83 7833
4d8fdc95
PS		 7834/* Use GSO to workaround all TSO packets that meet HW bug conditions
7835 * indicated in tg3_tx_frag_set()
52c0fd83 7836 */
4d8fdc95
PS		 7837static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7838 struct netdev_queue *txq, struct sk_buff *skb)
52c0fd83
MC		 7839{
7840 struct sk_buff *segs, *nskb;
f3f3f27e 7841 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7842
7843 /* Estimate the number of fragments in the worst case */
4d8fdc95
PS		 7844 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7845 netif_tx_stop_queue(txq);
f65aac16
MC		 7846
7847 /* netif_tx_stop_queue() must be done before checking
7848 * checking tx index in tg3_tx_avail() below, because in
7849 * tg3_tx(), we update tx index before checking for
7850 * netif_tx_queue_stopped().
7851 */
7852 smp_mb();
4d8fdc95 7853 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7f62ad5d
MC		 7854 return NETDEV_TX_BUSY;
7855
4d8fdc95 7856 netif_tx_wake_queue(txq);
52c0fd83
MC		 7857 }
7858
4d8fdc95
PS		 7859 segs = skb_gso_segment(skb, tp->dev->features &
7860 ~(NETIF_F_TSO | NETIF_F_TSO6));
40c1deaf 7861 if (IS_ERR(segs) || !segs)
52c0fd83
MC		 7862 goto tg3_tso_bug_end;
7863
7864 do {
7865 nskb = segs;
7866 segs = segs->next;
7867 nskb->next = NULL;
2ffcc981 7868 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7869 } while (segs);
7870
7871tg3_tso_bug_end:
497a27b9 7872 dev_kfree_skb_any(skb);
52c0fd83
MC		 7873
7874 return NETDEV_TX_OK;
7875}
52c0fd83 7876
d71c0dc4 7877/* hard_start_xmit for all devices */
2ffcc981 7878static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7879{
7880 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7881 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7882 u32 budget;
432aa7ed 7883 int i = -1, would_hit_hwbug;
90079ce8 7884 dma_addr_t mapping;
24f4efd4
MC		 7885 struct tg3_napi *tnapi;
7886 struct netdev_queue *txq;
432aa7ed 7887 unsigned int last;
d3f6f3a1
MC		 7888 struct iphdr *iph = NULL;
7889 struct tcphdr *tcph = NULL;
7890 __sum16 tcp_csum = 0, ip_csum = 0;
7891 __be16 ip_tot_len = 0;
f4188d8a 7892
24f4efd4
MC		 7893 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7894 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7895 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7896 tnapi++;
1da177e4 7897
84b67b27
MC		 7898 budget = tg3_tx_avail(tnapi);
7899
00b70504 7900 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7901 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7902 * interrupt. Furthermore, IRQ processing runs lockless so we have
7903 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7904 */
84b67b27 7905 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7906 if (!netif_tx_queue_stopped(txq)) {
7907 netif_tx_stop_queue(txq);
1f064a87
SH		 7908
7909 /* This is a hard error, log it. */
5129c3a3
MC		 7910 netdev_err(dev,
7911 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7912 }
1da177e4
LT		 7913 return NETDEV_TX_BUSY;
7914 }
7915
f3f3f27e 7916 entry = tnapi->tx_prod;
1da177e4 7917 base_flags = 0;
24f4efd4 7918
be98da6a
MC		 7919 mss = skb_shinfo(skb)->gso_size;
7920 if (mss) {
34195c3d 7921 u32 tcp_opt_len, hdr_len;
1da177e4 7922
105dcb59 7923 if (skb_cow_head(skb, 0))
48855432 7924 goto drop;
1da177e4 7925
34195c3d 7926 iph = ip_hdr(skb);
ab6a5bb6 7927 tcp_opt_len = tcp_optlen(skb);
1da177e4 7928
a5a11955 7929 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7930
476c1885
VY		 7931 /* HW/FW can not correctly segment packets that have been
7932 * vlan encapsulated.
7933 */
7934 if (skb->protocol == htons(ETH_P_8021Q) ||
7935 skb->protocol == htons(ETH_P_8021AD))
7936 return tg3_tso_bug(tp, tnapi, txq, skb);
7937
a5a11955 7938 if (!skb_is_gso_v6(skb)) {
d71c0dc4
MC		 7939 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7940 tg3_flag(tp, TSO_BUG))
4d8fdc95 7941 return tg3_tso_bug(tp, tnapi, txq, skb);
d71c0dc4 7942
d3f6f3a1
MC		 7943 ip_csum = iph->check;
7944 ip_tot_len = iph->tot_len;
34195c3d
MC		 7945 iph->check = 0;
7946 iph->tot_len = htons(mss + hdr_len);
7947 }
7948
1da177e4
LT		 7949 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7950 TXD_FLAG_CPU_POST_DMA);
7951
d3f6f3a1
MC		 7952 tcph = tcp_hdr(skb);
7953 tcp_csum = tcph->check;
7954
63c3a66f
JP		 7955 if (tg3_flag(tp, HW_TSO_1) ||
7956 tg3_flag(tp, HW_TSO_2) ||
7957 tg3_flag(tp, HW_TSO_3)) {
d3f6f3a1 7958 tcph->check = 0;
1da177e4 7959 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
d3f6f3a1
MC		 7960 } else {
7961 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7962 0, IPPROTO_TCP, 0);
7963 }
1da177e4 7964
63c3a66f 7965 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7966 mss |= (hdr_len & 0xc) << 12;
7967 if (hdr_len & 0x10)
7968 base_flags |= 0x00000010;
7969 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7970 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7971 mss |= hdr_len << 9;
63c3a66f 7972 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7973 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7974 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7975 int tsflags;
7976
eddc9ec5 7977 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7978 mss |= (tsflags << 11);
7979 }
7980 } else {
eddc9ec5 7981 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7982 int tsflags;
7983
eddc9ec5 7984 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7985 base_flags |= tsflags << 12;
7986 }
7987 }
476c1885
VY		 7988 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7989 /* HW/FW can not correctly checksum packets that have been
7990 * vlan encapsulated.
7991 */
7992 if (skb->protocol == htons(ETH_P_8021Q) ||
7993 skb->protocol == htons(ETH_P_8021AD)) {
7994 if (skb_checksum_help(skb))
7995 goto drop;
7996 } else {
7997 base_flags |= TXD_FLAG_TCPUDP_CSUM;
7998 }
1da177e4 7999 }
bf933c80 8000
93a700a9
MC		 8001 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8002 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8003 base_flags |= TXD_FLAG_JMB_PKT;
8004
92cd3a17
MC		 8005 if (vlan_tx_tag_present(skb)) {
8006 base_flags |= TXD_FLAG_VLAN;
8007 vlan = vlan_tx_tag_get(skb);
8008 }
1da177e4 8009
fb4ce8ad
MC		 8010 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8011 tg3_flag(tp, TX_TSTAMP_EN)) {
8012 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8013 base_flags |= TXD_FLAG_HWTSTAMP;
8014 }
8015
f4188d8a
AD		 8016 len = skb_headlen(skb);
8017
8018 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 8019 if (pci_dma_mapping_error(tp->pdev, mapping))
8020 goto drop;
8021
90079ce8 8022
f3f3f27e 8023 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 8024 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 8025
8026 would_hit_hwbug = 0;
8027
63c3a66f 8028 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 8029 would_hit_hwbug = 1;
1da177e4 8030
84b67b27 8031 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 8032 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 8033 mss, vlan)) {
d1a3b737 8034 would_hit_hwbug = 1;
ba1142e4 8035 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 8036 u32 tmp_mss = mss;
8037
8038 if (!tg3_flag(tp, HW_TSO_1) &&
8039 !tg3_flag(tp, HW_TSO_2) &&
8040 !tg3_flag(tp, HW_TSO_3))
8041 tmp_mss = 0;
8042
c5665a53
MC		 8043 /* Now loop through additional data
8044 * fragments, and queue them.
8045 */
1da177e4
LT		 8046 last = skb_shinfo(skb)->nr_frags - 1;
8047 for (i = 0; i <= last; i++) {
8048 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8049
9e903e08 8050 len = skb_frag_size(frag);
dc234d0b 8051 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8052 len, DMA_TO_DEVICE);
1da177e4 8053
f3f3f27e 8054 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8055 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8056 mapping);
5d6bcdfe 8057 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8058 goto dma_error;
1da177e4 8059
b9e45482
MC		 8060 if (!budget ||
8061 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8062 len, base_flags |
8063 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8064 tmp_mss, vlan)) {
72f2afb8 8065 would_hit_hwbug = 1;
b9e45482
MC		 8066 break;
8067 }
1da177e4
LT		 8068 }
8069 }
8070
8071 if (would_hit_hwbug) {
0d681b27 8072 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4 8073
d3f6f3a1
MC		 8074 if (mss) {
8075 /* If it's a TSO packet, do GSO instead of
8076 * allocating and copying to a large linear SKB
8077 */
8078 if (ip_tot_len) {
8079 iph->check = ip_csum;
8080 iph->tot_len = ip_tot_len;
8081 }
8082 tcph->check = tcp_csum;
4d8fdc95 8083 return tg3_tso_bug(tp, tnapi, txq, skb);
d3f6f3a1
MC		 8084 }
8085
1da177e4
LT		 8086 /* If the workaround fails due to memory/mapping
8087 * failure, silently drop this packet.
8088 */
84b67b27
MC		 8089 entry = tnapi->tx_prod;
8090 budget = tg3_tx_avail(tnapi);
f7ff1987 8091 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8092 base_flags, mss, vlan))
48855432 8093 goto drop_nofree;
1da177e4
LT		 8094 }
8095
d515b450 8096 skb_tx_timestamp(skb);
5cb917bc 8097 netdev_tx_sent_queue(txq, skb->len);
d515b450 8098
6541b806
MC		 8099 /* Sync BD data before updating mailbox */
8100 wmb();
8101
f3f3f27e
MC		 8102 tnapi->tx_prod = entry;
8103 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8104 netif_tx_stop_queue(txq);
f65aac16
MC		 8105
8106 /* netif_tx_stop_queue() must be done before checking
8107 * checking tx index in tg3_tx_avail() below, because in
8108 * tg3_tx(), we update tx index before checking for
8109 * netif_tx_queue_stopped().
8110 */
8111 smp_mb();
f3f3f27e 8112 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8113 netif_tx_wake_queue(txq);
51b91468 8114 }
1da177e4 8115
2c7c9ea4
PS		 8116 if (!skb->xmit_more || netif_xmit_stopped(txq)) {
8117 /* Packets are ready, update Tx producer idx on card. */
8118 tw32_tx_mbox(tnapi->prodmbox, entry);
8119 mmiowb();
8120 }
8121
1da177e4 8122 return NETDEV_TX_OK;
f4188d8a
AD		 8123
8124dma_error:
ba1142e4 8125 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8126 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432 8127drop:
497a27b9 8128 dev_kfree_skb_any(skb);
48855432
ED		 8129drop_nofree:
8130 tp->tx_dropped++;
f4188d8a 8131 return NETDEV_TX_OK;
1da177e4
LT		 8132}
8133
6e01b20b
MC		 8134static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8135{
8136 if (enable) {
8137 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8138 MAC_MODE_PORT_MODE_MASK);
8139
8140 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8141
8142 if (!tg3_flag(tp, 5705_PLUS))
8143 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8144
8145 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8146 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8147 else
8148 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8149 } else {
8150 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8151
8152 if (tg3_flag(tp, 5705_PLUS) ||
8153 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8154 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8155 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8156 }
8157
8158 tw32(MAC_MODE, tp->mac_mode);
8159 udelay(40);
8160}
8161
941ec90f 8162static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8163{
941ec90f 8164 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8165
8166 tg3_phy_toggle_apd(tp, false);
953c96e0 8167 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8168
941ec90f
MC		 8169 if (extlpbk && tg3_phy_set_extloopbk(tp))
8170 return -EIO;
8171
8172 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8173 switch (speed) {
8174 case SPEED_10:
8175 break;
8176 case SPEED_100:
8177 bmcr |= BMCR_SPEED100;
8178 break;
8179 case SPEED_1000:
8180 default:
8181 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8182 speed = SPEED_100;
8183 bmcr |= BMCR_SPEED100;
8184 } else {
8185 speed = SPEED_1000;
8186 bmcr |= BMCR_SPEED1000;
8187 }
8188 }
8189
941ec90f
MC		 8190 if (extlpbk) {
8191 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8192 tg3_readphy(tp, MII_CTRL1000, &val);
8193 val |= CTL1000_AS_MASTER |
8194 CTL1000_ENABLE_MASTER;
8195 tg3_writephy(tp, MII_CTRL1000, val);
8196 } else {
8197 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8198 MII_TG3_FET_PTEST_TRIM_2;
8199 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8200 }
8201 } else
8202 bmcr |= BMCR_LOOPBACK;
8203
5e5a7f37
MC		 8204 tg3_writephy(tp, MII_BMCR, bmcr);
8205
8206 /* The write needs to be flushed for the FETs */
8207 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8208 tg3_readphy(tp, MII_BMCR, &bmcr);
8209
8210 udelay(40);
8211
8212 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8213 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8214 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8215 MII_TG3_FET_PTEST_FRC_TX_LINK |
8216 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8217
8218 /* The write needs to be flushed for the AC131 */
8219 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8220 }
8221
8222 /* Reset to prevent losing 1st rx packet intermittently */
8223 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8224 tg3_flag(tp, 5780_CLASS)) {
8225 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8226 udelay(10);
8227 tw32_f(MAC_RX_MODE, tp->rx_mode);
8228 }
8229
8230 mac_mode = tp->mac_mode &
8231 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8232 if (speed == SPEED_1000)
8233 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8234 else
8235 mac_mode |= MAC_MODE_PORT_MODE_MII;
8236
4153577a 8237 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8238 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8239
8240 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8241 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8242 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8243 mac_mode |= MAC_MODE_LINK_POLARITY;
8244
8245 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8246 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8247 }
8248
8249 tw32(MAC_MODE, mac_mode);
8250 udelay(40);
941ec90f
MC		 8251
8252 return 0;
5e5a7f37
MC		 8253}
8254
c8f44aff 8255static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8256{
8257 struct tg3 *tp = netdev_priv(dev);
8258
8259 if (features & NETIF_F_LOOPBACK) {
8260 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8261 return;
8262
06c03c02 8263 spin_lock_bh(&tp->lock);
6e01b20b 8264 tg3_mac_loopback(tp, true);
06c03c02
MB		 8265 netif_carrier_on(tp->dev);
8266 spin_unlock_bh(&tp->lock);
8267 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8268 } else {
8269 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8270 return;
8271
06c03c02 8272 spin_lock_bh(&tp->lock);
6e01b20b 8273 tg3_mac_loopback(tp, false);
06c03c02 8274 /* Force link status check */
953c96e0 8275 tg3_setup_phy(tp, true);
06c03c02
MB		 8276 spin_unlock_bh(&tp->lock);
8277 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8278 }
8279}
8280
c8f44aff
MM		 8281static netdev_features_t tg3_fix_features(struct net_device *dev,
8282 netdev_features_t features)
dc668910
MM		 8283{
8284 struct tg3 *tp = netdev_priv(dev);
8285
63c3a66f 8286 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8287 features &= ~NETIF_F_ALL_TSO;
8288
8289 return features;
8290}
8291
c8f44aff 8292static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8293{
c8f44aff 8294 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8295
8296 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8297 tg3_set_loopback(dev, features);
8298
8299 return 0;
8300}
8301
21f581a5
MC		 8302static void tg3_rx_prodring_free(struct tg3 *tp,
8303 struct tg3_rx_prodring_set *tpr)
1da177e4 8304{
1da177e4
LT		 8305 int i;
8306
8fea32b9 8307 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8308 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8309 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8310 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8311 tp->rx_pkt_map_sz);
8312
63c3a66f 8313 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8314 for (i = tpr->rx_jmb_cons_idx;
8315 i != tpr->rx_jmb_prod_idx;
2c49a44d 8316 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8317 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8318 TG3_RX_JMB_MAP_SZ);
8319 }
8320 }
8321
2b2cdb65 8322 return;
b196c7e4 8323 }
1da177e4 8324
2c49a44d 8325 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8326 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8327 tp->rx_pkt_map_sz);
1da177e4 8328
63c3a66f 8329 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8330 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8331 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8332 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8333 }
8334}
8335
c6cdf436 8336/* Initialize rx rings for packet processing.
1da177e4
LT		 8337 *
8338 * The chip has been shut down and the driver detached from
8339 * the networking, so no interrupts or new tx packets will
8340 * end up in the driver. tp->{tx,}lock are held and thus
8341 * we may not sleep.
8342 */
21f581a5
MC		 8343static int tg3_rx_prodring_alloc(struct tg3 *tp,
8344 struct tg3_rx_prodring_set *tpr)
1da177e4 8345{
287be12e 8346 u32 i, rx_pkt_dma_sz;
1da177e4 8347
b196c7e4
MC		 8348 tpr->rx_std_cons_idx = 0;
8349 tpr->rx_std_prod_idx = 0;
8350 tpr->rx_jmb_cons_idx = 0;
8351 tpr->rx_jmb_prod_idx = 0;
8352
8fea32b9 8353 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8354 memset(&tpr->rx_std_buffers[0], 0,
8355 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8356 if (tpr->rx_jmb_buffers)
2b2cdb65 8357 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8358 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8359 goto done;
8360 }
8361
1da177e4 8362 /* Zero out all descriptors. */
2c49a44d 8363 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8364
287be12e 8365 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8366 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8367 tp->dev->mtu > ETH_DATA_LEN)
8368 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8369 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8370
1da177e4
LT		 8371 /* Initialize invariants of the rings, we only set this
8372 * stuff once. This works because the card does not
8373 * write into the rx buffer posting rings.
8374 */
2c49a44d 8375 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8376 struct tg3_rx_buffer_desc *rxd;
8377
21f581a5 8378 rxd = &tpr->rx_std[i];
287be12e 8379 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8380 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8381 rxd->opaque = (RXD_OPAQUE_RING_STD |
8382 (i << RXD_OPAQUE_INDEX_SHIFT));
8383 }
8384
1da177e4
LT		 8385 /* Now allocate fresh SKBs for each rx ring. */
8386 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8387 unsigned int frag_size;
8388
8389 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8390 &frag_size) < 0) {
5129c3a3
MC		 8391 netdev_warn(tp->dev,
8392 "Using a smaller RX standard ring. Only "
8393 "%d out of %d buffers were allocated "
8394 "successfully\n", i, tp->rx_pending);
32d8c572 8395 if (i == 0)
cf7a7298 8396 goto initfail;
32d8c572 8397 tp->rx_pending = i;
1da177e4 8398 break;
32d8c572 8399 }
1da177e4
LT		 8400 }
8401
63c3a66f 8402 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8403 goto done;
8404
2c49a44d 8405 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8406
63c3a66f 8407 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8408 goto done;
cf7a7298 8409
2c49a44d 8410 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8411 struct tg3_rx_buffer_desc *rxd;
8412
8413 rxd = &tpr->rx_jmb[i].std;
8414 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8415 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8416 RXD_FLAG_JUMBO;
8417 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8418 (i << RXD_OPAQUE_INDEX_SHIFT));
8419 }
8420
8421 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8422 unsigned int frag_size;
8423
8424 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8425 &frag_size) < 0) {
5129c3a3
MC		 8426 netdev_warn(tp->dev,
8427 "Using a smaller RX jumbo ring. Only %d "
8428 "out of %d buffers were allocated "
8429 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8430 if (i == 0)
8431 goto initfail;
8432 tp->rx_jumbo_pending = i;
8433 break;
1da177e4
LT		 8434 }
8435 }
cf7a7298
MC		 8436
8437done:
32d8c572 8438 return 0;
cf7a7298
MC		 8439
8440initfail:
21f581a5 8441 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8442 return -ENOMEM;
1da177e4
LT		 8443}
8444
21f581a5
MC		 8445static void tg3_rx_prodring_fini(struct tg3 *tp,
8446 struct tg3_rx_prodring_set *tpr)
1da177e4 8447{
21f581a5
MC		 8448 kfree(tpr->rx_std_buffers);
8449 tpr->rx_std_buffers = NULL;
8450 kfree(tpr->rx_jmb_buffers);
8451 tpr->rx_jmb_buffers = NULL;
8452 if (tpr->rx_std) {
4bae65c8
MC		 8453 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8454 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8455 tpr->rx_std = NULL;
1da177e4 8456 }
21f581a5 8457 if (tpr->rx_jmb) {
4bae65c8
MC		 8458 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8459 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8460 tpr->rx_jmb = NULL;
1da177e4 8461 }
cf7a7298
MC		 8462}
8463
21f581a5
MC		 8464static int tg3_rx_prodring_init(struct tg3 *tp,
8465 struct tg3_rx_prodring_set *tpr)
cf7a7298 8466{
2c49a44d
MC		 8467 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8468 GFP_KERNEL);
21f581a5 8469 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8470 return -ENOMEM;
8471
4bae65c8
MC		 8472 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8473 TG3_RX_STD_RING_BYTES(tp),
8474 &tpr->rx_std_mapping,
8475 GFP_KERNEL);
21f581a5 8476 if (!tpr->rx_std)
cf7a7298
MC		 8477 goto err_out;
8478
63c3a66f 8479 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8480 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8481 GFP_KERNEL);
8482 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8483 goto err_out;
8484
4bae65c8
MC		 8485 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8486 TG3_RX_JMB_RING_BYTES(tp),
8487 &tpr->rx_jmb_mapping,
8488 GFP_KERNEL);
21f581a5 8489 if (!tpr->rx_jmb)
cf7a7298
MC		 8490 goto err_out;
8491 }
8492
8493 return 0;
8494
8495err_out:
21f581a5 8496 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8497 return -ENOMEM;
8498}
8499
8500/* Free up pending packets in all rx/tx rings.
8501 *
8502 * The chip has been shut down and the driver detached from
8503 * the networking, so no interrupts or new tx packets will
8504 * end up in the driver. tp->{tx,}lock is not held and we are not
8505 * in an interrupt context and thus may sleep.
8506 */
8507static void tg3_free_rings(struct tg3 *tp)
8508{
f77a6a8e 8509 int i, j;
cf7a7298 8510
f77a6a8e
MC		 8511 for (j = 0; j < tp->irq_cnt; j++) {
8512 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8513
8fea32b9 8514 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8515
0c1d0e2b
MC		 8516 if (!tnapi->tx_buffers)
8517 continue;
8518
0d681b27
MC		 8519 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8520 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8521
0d681b27 8522 if (!skb)
f77a6a8e 8523 continue;
cf7a7298 8524
ba1142e4
MC		 8525 tg3_tx_skb_unmap(tnapi, i,
8526 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8527
8528 dev_kfree_skb_any(skb);
8529 }
5cb917bc 8530 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8531 }
cf7a7298
MC		 8532}
8533
8534/* Initialize tx/rx rings for packet processing.
8535 *
8536 * The chip has been shut down and the driver detached from
8537 * the networking, so no interrupts or new tx packets will
8538 * end up in the driver. tp->{tx,}lock are held and thus
8539 * we may not sleep.
8540 */
8541static int tg3_init_rings(struct tg3 *tp)
8542{
f77a6a8e 8543 int i;
72334482 8544
cf7a7298
MC		 8545 /* Free up all the SKBs. */
8546 tg3_free_rings(tp);
8547
f77a6a8e
MC		 8548 for (i = 0; i < tp->irq_cnt; i++) {
8549 struct tg3_napi *tnapi = &tp->napi[i];
8550
8551 tnapi->last_tag = 0;
8552 tnapi->last_irq_tag = 0;
8553 tnapi->hw_status->status = 0;
8554 tnapi->hw_status->status_tag = 0;
8555 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8556
f77a6a8e
MC		 8557 tnapi->tx_prod = 0;
8558 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8559 if (tnapi->tx_ring)
8560 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8561
8562 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8563 if (tnapi->rx_rcb)
8564 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8565
a620a6bc
TLSC		 8566 if (tnapi->prodring.rx_std &&
8567 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8568 tg3_free_rings(tp);
2b2cdb65 8569 return -ENOMEM;
e4af1af9 8570 }
f77a6a8e 8571 }
72334482 8572
2b2cdb65 8573 return 0;
cf7a7298
MC		 8574}
8575
49a359e3 8576static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8577{
f77a6a8e 8578 int i;
898a56f8 8579
49a359e3 8580 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8581 struct tg3_napi *tnapi = &tp->napi[i];
8582
8583 if (tnapi->tx_ring) {
4bae65c8 8584 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8585 tnapi->tx_ring, tnapi->tx_desc_mapping);
8586 tnapi->tx_ring = NULL;
8587 }
8588
8589 kfree(tnapi->tx_buffers);
8590 tnapi->tx_buffers = NULL;
49a359e3
MC		 8591 }
8592}
f77a6a8e 8593
49a359e3
MC		 8594static int tg3_mem_tx_acquire(struct tg3 *tp)
8595{
8596 int i;
8597 struct tg3_napi *tnapi = &tp->napi[0];
8598
8599 /* If multivector TSS is enabled, vector 0 does not handle
8600 * tx interrupts. Don't allocate any resources for it.
8601 */
8602 if (tg3_flag(tp, ENABLE_TSS))
8603 tnapi++;
8604
8605 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8606 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8607 TG3_TX_RING_SIZE, GFP_KERNEL);
8608 if (!tnapi->tx_buffers)
8609 goto err_out;
8610
8611 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8612 TG3_TX_RING_BYTES,
8613 &tnapi->tx_desc_mapping,
8614 GFP_KERNEL);
8615 if (!tnapi->tx_ring)
8616 goto err_out;
8617 }
8618
8619 return 0;
8620
8621err_out:
8622 tg3_mem_tx_release(tp);
8623 return -ENOMEM;
8624}
8625
8626static void tg3_mem_rx_release(struct tg3 *tp)
8627{
8628 int i;
8629
8630 for (i = 0; i < tp->irq_max; i++) {
8631 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8632
8fea32b9
MC		 8633 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8634
49a359e3
MC		 8635 if (!tnapi->rx_rcb)
8636 continue;
8637
8638 dma_free_coherent(&tp->pdev->dev,
8639 TG3_RX_RCB_RING_BYTES(tp),
8640 tnapi->rx_rcb,
8641 tnapi->rx_rcb_mapping);
8642 tnapi->rx_rcb = NULL;
8643 }
8644}
8645
8646static int tg3_mem_rx_acquire(struct tg3 *tp)
8647{
8648 unsigned int i, limit;
8649
8650 limit = tp->rxq_cnt;
8651
8652 /* If RSS is enabled, we need a (dummy) producer ring
8653 * set on vector zero. This is the true hw prodring.
8654 */
8655 if (tg3_flag(tp, ENABLE_RSS))
8656 limit++;
8657
8658 for (i = 0; i < limit; i++) {
8659 struct tg3_napi *tnapi = &tp->napi[i];
8660
8661 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8662 goto err_out;
8663
8664 /* If multivector RSS is enabled, vector 0
8665 * does not handle rx or tx interrupts.
8666 * Don't allocate any resources for it.
8667 */
8668 if (!i && tg3_flag(tp, ENABLE_RSS))
8669 continue;
8670
ede23fa8
JP		 8671 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8672 TG3_RX_RCB_RING_BYTES(tp),
8673 &tnapi->rx_rcb_mapping,
8674 GFP_KERNEL);
49a359e3
MC		 8675 if (!tnapi->rx_rcb)
8676 goto err_out;
49a359e3
MC		 8677 }
8678
8679 return 0;
8680
8681err_out:
8682 tg3_mem_rx_release(tp);
8683 return -ENOMEM;
8684}
8685
8686/*
8687 * Must not be invoked with interrupt sources disabled and
8688 * the hardware shutdown down.
8689 */
8690static void tg3_free_consistent(struct tg3 *tp)
8691{
8692 int i;
8693
8694 for (i = 0; i < tp->irq_cnt; i++) {
8695 struct tg3_napi *tnapi = &tp->napi[i];
8696
f77a6a8e 8697 if (tnapi->hw_status) {
4bae65c8
MC		 8698 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8699 tnapi->hw_status,
8700 tnapi->status_mapping);
f77a6a8e
MC		 8701 tnapi->hw_status = NULL;
8702 }
1da177e4 8703 }
f77a6a8e 8704
49a359e3
MC		 8705 tg3_mem_rx_release(tp);
8706 tg3_mem_tx_release(tp);
8707
1da177e4 8708 if (tp->hw_stats) {
4bae65c8
MC		 8709 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8710 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8711 tp->hw_stats = NULL;
8712 }
8713}
8714
8715/*
8716 * Must not be invoked with interrupt sources disabled and
8717 * the hardware shutdown down. Can sleep.
8718 */
8719static int tg3_alloc_consistent(struct tg3 *tp)
8720{
f77a6a8e 8721 int i;
898a56f8 8722
ede23fa8
JP		 8723 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8724 sizeof(struct tg3_hw_stats),
8725 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8726 if (!tp->hw_stats)
1da177e4
LT		 8727 goto err_out;
8728
f77a6a8e
MC		 8729 for (i = 0; i < tp->irq_cnt; i++) {
8730 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8731 struct tg3_hw_status *sblk;
1da177e4 8732
ede23fa8
JP		 8733 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8734 TG3_HW_STATUS_SIZE,
8735 &tnapi->status_mapping,
8736 GFP_KERNEL);
f77a6a8e
MC		 8737 if (!tnapi->hw_status)
8738 goto err_out;
898a56f8 8739
8d9d7cfc
MC		 8740 sblk = tnapi->hw_status;
8741
49a359e3 8742 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8743 u16 *prodptr = NULL;
8fea32b9 8744
49a359e3
MC		 8745 /*
8746 * When RSS is enabled, the status block format changes
8747 * slightly. The "rx_jumbo_consumer", "reserved",
8748 * and "rx_mini_consumer" members get mapped to the
8749 * other three rx return ring producer indexes.
8750 */
8751 switch (i) {
8752 case 1:
8753 prodptr = &sblk->idx[0].rx_producer;
8754 break;
8755 case 2:
8756 prodptr = &sblk->rx_jumbo_consumer;
8757 break;
8758 case 3:
8759 prodptr = &sblk->reserved;
8760 break;
8761 case 4:
8762 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8763 break;
8764 }
49a359e3
MC		 8765 tnapi->rx_rcb_prod_idx = prodptr;
8766 } else {
8d9d7cfc 8767 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8768 }
f77a6a8e 8769 }
1da177e4 8770
49a359e3
MC		 8771 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8772 goto err_out;
8773
1da177e4
LT		 8774 return 0;
8775
8776err_out:
8777 tg3_free_consistent(tp);
8778 return -ENOMEM;
8779}
8780
8781#define MAX_WAIT_CNT 1000
8782
8783/* To stop a block, clear the enable bit and poll till it
8784 * clears. tp->lock is held.
8785 */
953c96e0 8786static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8787{
8788 unsigned int i;
8789 u32 val;
8790
63c3a66f 8791 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8792 switch (ofs) {
8793 case RCVLSC_MODE:
8794 case DMAC_MODE:
8795 case MBFREE_MODE:
8796 case BUFMGR_MODE:
8797 case MEMARB_MODE:
8798 /* We can't enable/disable these bits of the
8799 * 5705/5750, just say success.
8800 */
8801 return 0;
8802
8803 default:
8804 break;
855e1111 8805 }
1da177e4
LT		 8806 }
8807
8808 val = tr32(ofs);
8809 val &= ~enable_bit;
8810 tw32_f(ofs, val);
8811
8812 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8813 if (pci_channel_offline(tp->pdev)) {
8814 dev_err(&tp->pdev->dev,
8815 "tg3_stop_block device offline, "
8816 "ofs=%lx enable_bit=%x\n",
8817 ofs, enable_bit);
8818 return -ENODEV;
8819 }
8820
1da177e4
LT		 8821 udelay(100);
8822 val = tr32(ofs);
8823 if ((val & enable_bit) == 0)
8824 break;
8825 }
8826
b3b7d6be 8827 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8828 dev_err(&tp->pdev->dev,
8829 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8830 ofs, enable_bit);
1da177e4
LT		 8831 return -ENODEV;
8832 }
8833
8834 return 0;
8835}
8836
8837/* tp->lock is held. */
953c96e0 8838static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8839{
8840 int i, err;
8841
8842 tg3_disable_ints(tp);
8843
6d446ec3
GS		 8844 if (pci_channel_offline(tp->pdev)) {
8845 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8846 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8847 err = -ENODEV;
8848 goto err_no_dev;
8849 }
8850
1da177e4
LT		 8851 tp->rx_mode &= ~RX_MODE_ENABLE;
8852 tw32_f(MAC_RX_MODE, tp->rx_mode);
8853 udelay(10);
8854
b3b7d6be
DM		 8855 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8856 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8857 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8858 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8859 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8860 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8861
8862 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8863 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8864 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8865 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8866 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8867 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8868 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8869
8870 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8871 tw32_f(MAC_MODE, tp->mac_mode);
8872 udelay(40);
8873
8874 tp->tx_mode &= ~TX_MODE_ENABLE;
8875 tw32_f(MAC_TX_MODE, tp->tx_mode);
8876
8877 for (i = 0; i < MAX_WAIT_CNT; i++) {
8878 udelay(100);
8879 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8880 break;
8881 }
8882 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8883 dev_err(&tp->pdev->dev,
8884 "%s timed out, TX_MODE_ENABLE will not clear "
8885 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8886 err |= -ENODEV;
1da177e4
LT		 8887 }
8888
e6de8ad1 8889 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8890 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8891 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8892
8893 tw32(FTQ_RESET, 0xffffffff);
8894 tw32(FTQ_RESET, 0x00000000);
8895
b3b7d6be
DM		 8896 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8897 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8898
6d446ec3 8899err_no_dev:
f77a6a8e
MC		 8900 for (i = 0; i < tp->irq_cnt; i++) {
8901 struct tg3_napi *tnapi = &tp->napi[i];
8902 if (tnapi->hw_status)
8903 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8904 }
1da177e4 8905
1da177e4
LT		 8906 return err;
8907}
8908
ee6a99b5
MC		 8909/* Save PCI command register before chip reset */
8910static void tg3_save_pci_state(struct tg3 *tp)
8911{
8a6eac90 8912 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8913}
8914
8915/* Restore PCI state after chip reset */
8916static void tg3_restore_pci_state(struct tg3 *tp)
8917{
8918 u32 val;
8919
8920 /* Re-enable indirect register accesses. */
8921 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8922 tp->misc_host_ctrl);
8923
8924 /* Set MAX PCI retry to zero. */
8925 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8926 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8927 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8928 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8929 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8930 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8931 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8932 PCISTATE_ALLOW_APE_SHMEM_WR |
8933 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8934 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8935
8a6eac90 8936 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8937
2c55a3d0
MC		 8938 if (!tg3_flag(tp, PCI_EXPRESS)) {
8939 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8940 tp->pci_cacheline_sz);
8941 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8942 tp->pci_lat_timer);
114342f2 8943 }
5f5c51e3 8944
ee6a99b5 8945 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8946 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8947 u16 pcix_cmd;
8948
8949 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8950 &pcix_cmd);
8951 pcix_cmd &= ~PCI_X_CMD_ERO;
8952 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8953 pcix_cmd);
8954 }
ee6a99b5 8955
63c3a66f 8956 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8957
8958 /* Chip reset on 5780 will reset MSI enable bit,
8959 * so need to restore it.
8960 */
63c3a66f 8961 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8962 u16 ctrl;
8963
8964 pci_read_config_word(tp->pdev,
8965 tp->msi_cap + PCI_MSI_FLAGS,
8966 &ctrl);
8967 pci_write_config_word(tp->pdev,
8968 tp->msi_cap + PCI_MSI_FLAGS,
8969 ctrl | PCI_MSI_FLAGS_ENABLE);
8970 val = tr32(MSGINT_MODE);
8971 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8972 }
8973 }
8974}
8975
f82995b6
NS		 8976static void tg3_override_clk(struct tg3 *tp)
8977{
8978 u32 val;
8979
8980 switch (tg3_asic_rev(tp)) {
8981 case ASIC_REV_5717:
8982 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8983 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8984 TG3_CPMU_MAC_ORIDE_ENABLE);
8985 break;
8986
8987 case ASIC_REV_5719:
8988 case ASIC_REV_5720:
8989 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8990 break;
8991
8992 default:
8993 return;
8994 }
8995}
8996
8997static void tg3_restore_clk(struct tg3 *tp)
8998{
8999 u32 val;
9000
9001 switch (tg3_asic_rev(tp)) {
9002 case ASIC_REV_5717:
9003 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9004 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9005 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9006 break;
9007
9008 case ASIC_REV_5719:
9009 case ASIC_REV_5720:
9010 val = tr32(TG3_CPMU_CLCK_ORIDE);
9011 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9012 break;
9013
9014 default:
9015 return;
9016 }
9017}
9018
1da177e4
LT		 9019/* tp->lock is held. */
9020static int tg3_chip_reset(struct tg3 *tp)
9021{
9022 u32 val;
1ee582d8 9023 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 9024 int i, err;
1da177e4 9025
8496e85c
RW		 9026 if (!pci_device_is_present(tp->pdev))
9027 return -ENODEV;
9028
f49639e6
DM		 9029 tg3_nvram_lock(tp);
9030
77b483f1
MC		 9031 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9032
f49639e6
DM		 9033 /* No matching tg3_nvram_unlock() after this because
9034 * chip reset below will undo the nvram lock.
9035 */
9036 tp->nvram_lock_cnt = 0;
1da177e4 9037
ee6a99b5
MC		 9038 /* GRC_MISC_CFG core clock reset will clear the memory
9039 * enable bit in PCI register 4 and the MSI enable bit
9040 * on some chips, so we save relevant registers here.
9041 */
9042 tg3_save_pci_state(tp);
9043
4153577a 9044 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 9045 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 9046 tw32(GRC_FASTBOOT_PC, 0);
9047
1da177e4
LT		 9048 /*
9049 * We must avoid the readl() that normally takes place.
9050 * It locks machines, causes machine checks, and other
9051 * fun things. So, temporarily disable the 5701
9052 * hardware workaround, while we do the reset.
9053 */
1ee582d8
MC		 9054 write_op = tp->write32;
9055 if (write_op == tg3_write_flush_reg32)
9056 tp->write32 = tg3_write32;
1da177e4 9057
d18edcb2
MC		 9058 /* Prevent the irq handler from reading or writing PCI registers
9059 * during chip reset when the memory enable bit in the PCI command
9060 * register may be cleared. The chip does not generate interrupt
9061 * at this time, but the irq handler may still be called due to irq
9062 * sharing or irqpoll.
9063 */
63c3a66f 9064 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 9065 for (i = 0; i < tp->irq_cnt; i++) {
9066 struct tg3_napi *tnapi = &tp->napi[i];
9067 if (tnapi->hw_status) {
9068 tnapi->hw_status->status = 0;
9069 tnapi->hw_status->status_tag = 0;
9070 }
9071 tnapi->last_tag = 0;
9072 tnapi->last_irq_tag = 0;
b8fa2f3a 9073 }
d18edcb2 9074 smp_mb();
4f125f42
MC		 9075
9076 for (i = 0; i < tp->irq_cnt; i++)
9077 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 9078
4153577a 9079 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 9080 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9081 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9082 }
9083
1da177e4
LT		 9084 /* do the reset */
9085 val = GRC_MISC_CFG_CORECLK_RESET;
9086
63c3a66f 9087 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 9088 /* Force PCIe 1.0a mode */
4153577a 9089 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9090 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 9091 tr32(TG3_PCIE_PHY_TSTCTL) ==
9092 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9093 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9094
4153577a 9095 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 9096 tw32(GRC_MISC_CFG, (1 << 29));
9097 val |= (1 << 29);
9098 }
9099 }
9100
4153577a 9101 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 9102 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9103 tw32(GRC_VCPU_EXT_CTRL,
9104 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9105 }
9106
f82995b6
NS		 9107 /* Set the clock to the highest frequency to avoid timeouts. With link
9108 * aware mode, the clock speed could be slow and bootcode does not
9109 * complete within the expected time. Override the clock to allow the
9110 * bootcode to finish sooner and then restore it.
9111 */
9112 tg3_override_clk(tp);
9113
f37500d3 9114 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9115 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9116 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9117
1da177e4
LT		 9118 tw32(GRC_MISC_CFG, val);
9119
1ee582d8
MC		 9120 /* restore 5701 hardware bug workaround write method */
9121 tp->write32 = write_op;
1da177e4
LT		 9122
9123 /* Unfortunately, we have to delay before the PCI read back.
9124 * Some 575X chips even will not respond to a PCI cfg access
9125 * when the reset command is given to the chip.
9126 *
9127 * How do these hardware designers expect things to work
9128 * properly if the PCI write is posted for a long period
9129 * of time? It is always necessary to have some method by
9130 * which a register read back can occur to push the write
9131 * out which does the reset.
9132 *
9133 * For most tg3 variants the trick below was working.
9134 * Ho hum...
9135 */
9136 udelay(120);
9137
9138 /* Flush PCI posted writes. The normal MMIO registers
9139 * are inaccessible at this time so this is the only
9140 * way to make this reliably (actually, this is no longer
9141 * the case, see above). I tried to use indirect
9142 * register read/write but this upset some 5701 variants.
9143 */
9144 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9145
9146 udelay(120);
9147
0f49bfbd 9148 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9149 u16 val16;
9150
4153577a 9151 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9152 int j;
1da177e4
LT		 9153 u32 cfg_val;
9154
9155 /* Wait for link training to complete. */
86449944 9156 for (j = 0; j < 5000; j++)
1da177e4
LT		 9157 udelay(100);
9158
9159 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9160 pci_write_config_dword(tp->pdev, 0xc4,
9161 cfg_val | (1 << 15));
9162 }
5e7dfd0f 9163
e7126997 9164 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9165 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9166 /*
9167 * Older PCIe devices only support the 128 byte
9168 * MPS setting. Enforce the restriction.
5e7dfd0f 9169 */
63c3a66f 9170 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9171 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9172 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9173
5e7dfd0f 9174 /* Clear error status */
0f49bfbd 9175 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9176 PCI_EXP_DEVSTA_CED |
9177 PCI_EXP_DEVSTA_NFED |
9178 PCI_EXP_DEVSTA_FED |
9179 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9180 }
9181
ee6a99b5 9182 tg3_restore_pci_state(tp);
1da177e4 9183
63c3a66f
JP		 9184 tg3_flag_clear(tp, CHIP_RESETTING);
9185 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9186
ee6a99b5 9187 val = 0;
63c3a66f 9188 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9189 val = tr32(MEMARB_MODE);
ee6a99b5 9190 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9191
4153577a 9192 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9193 tg3_stop_fw(tp);
9194 tw32(0x5000, 0x400);
9195 }
9196
7e6c63f0
HM		 9197 if (tg3_flag(tp, IS_SSB_CORE)) {
9198 /*
9199 * BCM4785: In order to avoid repercussions from using
9200 * potentially defective internal ROM, stop the Rx RISC CPU,
9201 * which is not required.
9202 */
9203 tg3_stop_fw(tp);
9204 tg3_halt_cpu(tp, RX_CPU_BASE);
9205 }
9206
fb03a43f
NS		 9207 err = tg3_poll_fw(tp);
9208 if (err)
9209 return err;
9210
1da177e4
LT		 9211 tw32(GRC_MODE, tp->grc_mode);
9212
4153577a 9213 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9214 val = tr32(0xc4);
1da177e4
LT		 9215
9216 tw32(0xc4, val | (1 << 15));
9217 }
9218
9219 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9220 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9221 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9222 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9223 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9224 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9225 }
9226
f07e9af3 9227 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9228 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9229 val = tp->mac_mode;
f07e9af3 9230 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9231 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9232 val = tp->mac_mode;
1da177e4 9233 } else
d2394e6b
MC		 9234 val = 0;
9235
9236 tw32_f(MAC_MODE, val);
1da177e4
LT		 9237 udelay(40);
9238
77b483f1
MC		 9239 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9240
0a9140cf
MC		 9241 tg3_mdio_start(tp);
9242
63c3a66f 9243 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9244 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9245 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9246 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9247 val = tr32(0x7c00);
1da177e4
LT		 9248
9249 tw32(0x7c00, val | (1 << 25));
9250 }
9251
f82995b6 9252 tg3_restore_clk(tp);
d78b59f5 9253
1da177e4 9254 /* Reprobe ASF enable state. */
63c3a66f 9255 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9256 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9257 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9258
63c3a66f 9259 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9260 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9261 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9262 u32 nic_cfg;
9263
9264 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9265 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9266 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9267 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9268 if (tg3_flag(tp, 5750_PLUS))
9269 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9270
9271 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9272 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9273 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9274 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9275 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9276 }
9277 }
9278
9279 return 0;
9280}
9281
65ec698d
MC		 9282static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9283static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
e565eec3 9284static void __tg3_set_rx_mode(struct net_device *);
92feeabf 9285
1da177e4 9286/* tp->lock is held. */
953c96e0 9287static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9288{
9289 int err;
9290
9291 tg3_stop_fw(tp);
9292
944d980e 9293 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9294
b3b7d6be 9295 tg3_abort_hw(tp, silent);
1da177e4
LT		 9296 err = tg3_chip_reset(tp);
9297
953c96e0 9298 __tg3_set_mac_addr(tp, false);
daba2a63 9299
944d980e
MC		 9300 tg3_write_sig_legacy(tp, kind);
9301 tg3_write_sig_post_reset(tp, kind);
1da177e4 9302
92feeabf
MC		 9303 if (tp->hw_stats) {
9304 /* Save the stats across chip resets... */
b4017c53 9305 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9306 tg3_get_estats(tp, &tp->estats_prev);
9307
9308 /* And make sure the next sample is new data */
9309 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9310 }
9311
4bc814ab 9312 return err;
1da177e4
LT		 9313}
9314
1da177e4
LT		 9315static int tg3_set_mac_addr(struct net_device *dev, void *p)
9316{
9317 struct tg3 *tp = netdev_priv(dev);
9318 struct sockaddr *addr = p;
953c96e0
JP		 9319 int err = 0;
9320 bool skip_mac_1 = false;
1da177e4 9321
f9804ddb 9322 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9323 return -EADDRNOTAVAIL;
f9804ddb 9324
1da177e4
LT		 9325 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9326
e75f7c90
MC		 9327 if (!netif_running(dev))
9328 return 0;
9329
63c3a66f 9330 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9331 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9332
986e0aeb
MC		 9333 addr0_high = tr32(MAC_ADDR_0_HIGH);
9334 addr0_low = tr32(MAC_ADDR_0_LOW);
9335 addr1_high = tr32(MAC_ADDR_1_HIGH);
9336 addr1_low = tr32(MAC_ADDR_1_LOW);
9337
9338 /* Skip MAC addr 1 if ASF is using it. */
9339 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9340 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9341 skip_mac_1 = true;
58712ef9 9342 }
986e0aeb
MC		 9343 spin_lock_bh(&tp->lock);
9344 __tg3_set_mac_addr(tp, skip_mac_1);
e565eec3 9345 __tg3_set_rx_mode(dev);
986e0aeb 9346 spin_unlock_bh(&tp->lock);
1da177e4 9347
b9ec6c1b 9348 return err;
1da177e4
LT		 9349}
9350
9351/* tp->lock is held. */
9352static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9353 dma_addr_t mapping, u32 maxlen_flags,
9354 u32 nic_addr)
9355{
9356 tg3_write_mem(tp,
9357 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9358 ((u64) mapping >> 32));
9359 tg3_write_mem(tp,
9360 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9361 ((u64) mapping & 0xffffffff));
9362 tg3_write_mem(tp,
9363 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9364 maxlen_flags);
9365
63c3a66f 9366 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9367 tg3_write_mem(tp,
9368 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9369 nic_addr);
9370}
9371
a489b6d9
MC		 9372
9373static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9374{
a489b6d9 9375 int i = 0;
b6080e12 9376
63c3a66f 9377 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9378 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9379 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9380 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9381 } else {
9382 tw32(HOSTCC_TXCOL_TICKS, 0);
9383 tw32(HOSTCC_TXMAX_FRAMES, 0);
9384 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9385
9386 for (; i < tp->txq_cnt; i++) {
9387 u32 reg;
9388
9389 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9390 tw32(reg, ec->tx_coalesce_usecs);
9391 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9392 tw32(reg, ec->tx_max_coalesced_frames);
9393 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9394 tw32(reg, ec->tx_max_coalesced_frames_irq);
9395 }
19cfaecc 9396 }
b6080e12 9397
a489b6d9
MC		 9398 for (; i < tp->irq_max - 1; i++) {
9399 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9400 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9401 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9402 }
9403}
9404
9405static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9406{
9407 int i = 0;
9408 u32 limit = tp->rxq_cnt;
9409
63c3a66f 9410 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9411 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9412 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9413 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9414 limit--;
19cfaecc 9415 } else {
b6080e12
MC		 9416 tw32(HOSTCC_RXCOL_TICKS, 0);
9417 tw32(HOSTCC_RXMAX_FRAMES, 0);
9418 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9419 }
b6080e12 9420
a489b6d9 9421 for (; i < limit; i++) {
b6080e12
MC		 9422 u32 reg;
9423
9424 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9425 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9426 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9427 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9428 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9429 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9430 }
9431
9432 for (; i < tp->irq_max - 1; i++) {
9433 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9434 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9435 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9436 }
9437}
19cfaecc 9438
a489b6d9
MC		 9439static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9440{
9441 tg3_coal_tx_init(tp, ec);
9442 tg3_coal_rx_init(tp, ec);
9443
9444 if (!tg3_flag(tp, 5705_PLUS)) {
9445 u32 val = ec->stats_block_coalesce_usecs;
9446
9447 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9448 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9449
f4a46d1f 9450 if (!tp->link_up)
a489b6d9
MC		 9451 val = 0;
9452
9453 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9454 }
15f9850d 9455}
1da177e4 9456
328947ff
NS		 9457/* tp->lock is held. */
9458static void tg3_tx_rcbs_disable(struct tg3 *tp)
9459{
9460 u32 txrcb, limit;
9461
9462 /* Disable all transmit rings but the first. */
9463 if (!tg3_flag(tp, 5705_PLUS))
9464 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9465 else if (tg3_flag(tp, 5717_PLUS))
9466 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9467 else if (tg3_flag(tp, 57765_CLASS) ||
9468 tg3_asic_rev(tp) == ASIC_REV_5762)
9469 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9470 else
9471 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9472
9473 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9474 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9475 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9476 BDINFO_FLAGS_DISABLED);
9477}
9478
32ba19ef
NS		 9479/* tp->lock is held. */
9480static void tg3_tx_rcbs_init(struct tg3 *tp)
9481{
9482 int i = 0;
9483 u32 txrcb = NIC_SRAM_SEND_RCB;
9484
9485 if (tg3_flag(tp, ENABLE_TSS))
9486 i++;
9487
9488 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9489 struct tg3_napi *tnapi = &tp->napi[i];
9490
9491 if (!tnapi->tx_ring)
9492 continue;
9493
9494 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9495 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9496 NIC_SRAM_TX_BUFFER_DESC);
9497 }
9498}
9499
328947ff
NS		 9500/* tp->lock is held. */
9501static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9502{
9503 u32 rxrcb, limit;
9504
9505 /* Disable all receive return rings but the first. */
9506 if (tg3_flag(tp, 5717_PLUS))
9507 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9508 else if (!tg3_flag(tp, 5705_PLUS))
9509 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9510 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9511 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9512 tg3_flag(tp, 57765_CLASS))
9513 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9514 else
9515 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9516
9517 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9518 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9519 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9520 BDINFO_FLAGS_DISABLED);
9521}
9522
32ba19ef
NS		 9523/* tp->lock is held. */
9524static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9525{
9526 int i = 0;
9527 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9528
9529 if (tg3_flag(tp, ENABLE_RSS))
9530 i++;
9531
9532 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9533 struct tg3_napi *tnapi = &tp->napi[i];
9534
9535 if (!tnapi->rx_rcb)
9536 continue;
9537
9538 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9539 (tp->rx_ret_ring_mask + 1) <<
9540 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9541 }
9542}
9543
2d31ecaf
MC		 9544/* tp->lock is held. */
9545static void tg3_rings_reset(struct tg3 *tp)
9546{
9547 int i;
328947ff 9548 u32 stblk;
2d31ecaf
MC		 9549 struct tg3_napi *tnapi = &tp->napi[0];
9550
328947ff 9551 tg3_tx_rcbs_disable(tp);
2d31ecaf 9552
328947ff 9553 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9554
9555 /* Disable interrupts */
9556 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9557 tp->napi[0].chk_msi_cnt = 0;
9558 tp->napi[0].last_rx_cons = 0;
9559 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9560
9561 /* Zero mailbox registers. */
63c3a66f 9562 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9563 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9564 tp->napi[i].tx_prod = 0;
9565 tp->napi[i].tx_cons = 0;
63c3a66f 9566 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9567 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9568 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9569 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9570 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9571 tp->napi[i].last_rx_cons = 0;
9572 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9573 }
63c3a66f 9574 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9575 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9576 } else {
9577 tp->napi[0].tx_prod = 0;
9578 tp->napi[0].tx_cons = 0;
9579 tw32_mailbox(tp->napi[0].prodmbox, 0);
9580 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9581 }
2d31ecaf
MC		 9582
9583 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9584 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9585 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9586 for (i = 0; i < 16; i++)
9587 tw32_tx_mbox(mbox + i * 8, 0);
9588 }
9589
2d31ecaf
MC		 9590 /* Clear status block in ram. */
9591 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9592
9593 /* Set status block DMA address */
9594 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9595 ((u64) tnapi->status_mapping >> 32));
9596 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9597 ((u64) tnapi->status_mapping & 0xffffffff));
9598
f77a6a8e 9599 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9600
f77a6a8e
MC		 9601 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9602 u64 mapping = (u64)tnapi->status_mapping;
9603 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9604 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9605 stblk += 8;
f77a6a8e
MC		 9606
9607 /* Clear status block in ram. */
9608 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9609 }
32ba19ef
NS		 9610
9611 tg3_tx_rcbs_init(tp);
9612 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9613}
9614
eb07a940
MC		 9615static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9616{
9617 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9618
63c3a66f
JP		 9619 if (!tg3_flag(tp, 5750_PLUS) ||
9620 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9621 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9622 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9623 tg3_flag(tp, 57765_PLUS))
eb07a940 9624 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9625 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9626 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9627 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9628 else
9629 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9630
9631 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9632 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9633
9634 val = min(nic_rep_thresh, host_rep_thresh);
9635 tw32(RCVBDI_STD_THRESH, val);
9636
63c3a66f 9637 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9638 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9639
63c3a66f 9640 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9641 return;
9642
513aa6ea 9643 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9644
9645 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9646
9647 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9648 tw32(RCVBDI_JUMBO_THRESH, val);
9649
63c3a66f 9650 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9651 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9652}
9653
ccd5ba9d
MC		 9654static inline u32 calc_crc(unsigned char *buf, int len)
9655{
9656 u32 reg;
9657 u32 tmp;
9658 int j, k;
9659
9660 reg = 0xffffffff;
9661
9662 for (j = 0; j < len; j++) {
9663 reg ^= buf[j];
9664
9665 for (k = 0; k < 8; k++) {
9666 tmp = reg & 0x01;
9667
9668 reg >>= 1;
9669
9670 if (tmp)
9671 reg ^= 0xedb88320;
9672 }
9673 }
9674
9675 return ~reg;
9676}
9677
9678static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9679{
9680 /* accept or reject all multicast frames */
9681 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9682 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9683 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9684 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9685}
9686
9687static void __tg3_set_rx_mode(struct net_device *dev)
9688{
9689 struct tg3 *tp = netdev_priv(dev);
9690 u32 rx_mode;
9691
9692 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9693 RX_MODE_KEEP_VLAN_TAG);
9694
9695#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9696 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9697 * flag clear.
9698 */
9699 if (!tg3_flag(tp, ENABLE_ASF))
9700 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9701#endif
9702
9703 if (dev->flags & IFF_PROMISC) {
9704 /* Promiscuous mode. */
9705 rx_mode |= RX_MODE_PROMISC;
9706 } else if (dev->flags & IFF_ALLMULTI) {
9707 /* Accept all multicast. */
9708 tg3_set_multi(tp, 1);
9709 } else if (netdev_mc_empty(dev)) {
9710 /* Reject all multicast. */
9711 tg3_set_multi(tp, 0);
9712 } else {
9713 /* Accept one or more multicast(s). */
9714 struct netdev_hw_addr *ha;
9715 u32 mc_filter[4] = { 0, };
9716 u32 regidx;
9717 u32 bit;
9718 u32 crc;
9719
9720 netdev_for_each_mc_addr(ha, dev) {
9721 crc = calc_crc(ha->addr, ETH_ALEN);
9722 bit = ~crc & 0x7f;
9723 regidx = (bit & 0x60) >> 5;
9724 bit &= 0x1f;
9725 mc_filter[regidx] |= (1 << bit);
9726 }
9727
9728 tw32(MAC_HASH_REG_0, mc_filter[0]);
9729 tw32(MAC_HASH_REG_1, mc_filter[1]);
9730 tw32(MAC_HASH_REG_2, mc_filter[2]);
9731 tw32(MAC_HASH_REG_3, mc_filter[3]);
9732 }
9733
e565eec3
MC		 9734 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9735 rx_mode |= RX_MODE_PROMISC;
9736 } else if (!(dev->flags & IFF_PROMISC)) {
9737 /* Add all entries into to the mac addr filter list */
9738 int i = 0;
9739 struct netdev_hw_addr *ha;
9740
9741 netdev_for_each_uc_addr(ha, dev) {
9742 __tg3_set_one_mac_addr(tp, ha->addr,
9743 i + TG3_UCAST_ADDR_IDX(tp));
9744 i++;
9745 }
9746 }
9747
ccd5ba9d
MC		 9748 if (rx_mode != tp->rx_mode) {
9749 tp->rx_mode = rx_mode;
9750 tw32_f(MAC_RX_MODE, rx_mode);
9751 udelay(10);
9752 }
9753}
9754
9102426a 9755static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9756{
9757 int i;
9758
9759 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9760 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9761}
9762
9763static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9764{
9765 int i;
9766
9767 if (!tg3_flag(tp, SUPPORT_MSIX))
9768 return;
9769
0b3ba055 9770 if (tp->rxq_cnt == 1) {
bcebcc46 9771 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9772 return;
9773 }
9774
9775 /* Validate table against current IRQ count */
9776 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9777 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9778 break;
9779 }
9780
9781 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9782 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9783}
9784
90415477 9785static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9786{
9787 int i = 0;
9788 u32 reg = MAC_RSS_INDIR_TBL_0;
9789
9790 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9791 u32 val = tp->rss_ind_tbl[i];
9792 i++;
9793 for (; i % 8; i++) {
9794 val <<= 4;
9795 val |= tp->rss_ind_tbl[i];
9796 }
9797 tw32(reg, val);
9798 reg += 4;
9799 }
9800}
9801
9bc297ea
NS		 9802static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9803{
9804 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9805 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9806 else
9807 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9808}
9809
1da177e4 9810/* tp->lock is held. */
953c96e0 9811static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9812{
9813 u32 val, rdmac_mode;
9814 int i, err, limit;
8fea32b9 9815 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9816
9817 tg3_disable_ints(tp);
9818
9819 tg3_stop_fw(tp);
9820
9821 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9822
63c3a66f 9823 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9824 tg3_abort_hw(tp, 1);
1da177e4 9825
fdad8de4
NS		 9826 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9827 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9828 tg3_phy_pull_config(tp);
400dfbaa 9829 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9830 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9831 }
9832
400dfbaa
NS		 9833 /* Enable MAC control of LPI */
9834 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9835 tg3_setup_eee(tp);
9836
603f1173 9837 if (reset_phy)
d4d2c558
MC		 9838 tg3_phy_reset(tp);
9839
1da177e4
LT		 9840 err = tg3_chip_reset(tp);
9841 if (err)
9842 return err;
9843
9844 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9845
4153577a 9846 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9847 val = tr32(TG3_CPMU_CTRL);
9848 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9849 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9850
9851 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9852 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9853 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9854 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9855
9856 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9857 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9858 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9859 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9860
9861 val = tr32(TG3_CPMU_HST_ACC);
9862 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9863 val |= CPMU_HST_ACC_MACCLK_6_25;
9864 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9865 }
9866
4153577a 9867 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9868 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9869 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9870 PCIE_PWR_MGMT_L1_THRESH_4MS;
9871 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9872
9873 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9874 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9875
9876 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9877
f40386c8
MC		 9878 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9879 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9880 }
9881
63c3a66f 9882 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9883 u32 grc_mode = tr32(GRC_MODE);
9884
9885 /* Access the lower 1K of PL PCIE block registers. */
9886 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9887 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9888
9889 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9890 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9891 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9892
9893 tw32(GRC_MODE, grc_mode);
9894 }
9895
55086ad9 9896 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9897 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9898 u32 grc_mode = tr32(GRC_MODE);
cea46462 9899
5093eedc
MC		 9900 /* Access the lower 1K of PL PCIE block registers. */
9901 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9902 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9903
5093eedc
MC		 9904 val = tr32(TG3_PCIE_TLDLPL_PORT +
9905 TG3_PCIE_PL_LO_PHYCTL5);
9906 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9907 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9908
5093eedc
MC		 9909 tw32(GRC_MODE, grc_mode);
9910 }
a977dbe8 9911
4153577a 9912 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9913 u32 grc_mode;
9914
9915 /* Fix transmit hangs */
9916 val = tr32(TG3_CPMU_PADRNG_CTL);
9917 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9918 tw32(TG3_CPMU_PADRNG_CTL, val);
9919
9920 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9921
9922 /* Access the lower 1K of DL PCIE block registers. */
9923 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9924 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9925
9926 val = tr32(TG3_PCIE_TLDLPL_PORT +
9927 TG3_PCIE_DL_LO_FTSMAX);
9928 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9929 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9930 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9931
9932 tw32(GRC_MODE, grc_mode);
9933 }
9934
a977dbe8
MC		 9935 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9936 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9937 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9938 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9939 }
9940
1da177e4
LT		 9941 /* This works around an issue with Athlon chipsets on
9942 * B3 tigon3 silicon. This bit has no effect on any
9943 * other revision. But do not set this on PCI Express
795d01c5 9944 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9945 */
63c3a66f
JP		 9946 if (!tg3_flag(tp, CPMU_PRESENT)) {
9947 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9948 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9949 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9950 }
1da177e4 9951
4153577a 9952 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9953 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9954 val = tr32(TG3PCI_PCISTATE);
9955 val |= PCISTATE_RETRY_SAME_DMA;
9956 tw32(TG3PCI_PCISTATE, val);
9957 }
9958
63c3a66f 9959 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9960 /* Allow reads and writes to the
9961 * APE register and memory space.
9962 */
9963 val = tr32(TG3PCI_PCISTATE);
9964 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9965 PCISTATE_ALLOW_APE_SHMEM_WR |
9966 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9967 tw32(TG3PCI_PCISTATE, val);
9968 }
9969
4153577a 9970 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9971 /* Enable some hw fixes. */
9972 val = tr32(TG3PCI_MSI_DATA);
9973 val |= (1 << 26) | (1 << 28) | (1 << 29);
9974 tw32(TG3PCI_MSI_DATA, val);
9975 }
9976
9977 /* Descriptor ring init may make accesses to the
9978 * NIC SRAM area to setup the TX descriptors, so we
9979 * can only do this after the hardware has been
9980 * successfully reset.
9981 */
32d8c572
MC		 9982 err = tg3_init_rings(tp);
9983 if (err)
9984 return err;
1da177e4 9985
63c3a66f 9986 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9987 val = tr32(TG3PCI_DMA_RW_CTRL) &
9988 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9989 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9990 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9991 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9992 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9993 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9994 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9995 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9996 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9997 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9998 /* This value is determined during the probe time DMA
9999 * engine test, tg3_test_dma.
10000 */
10001 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10002 }
1da177e4
LT		 10003
10004 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10005 GRC_MODE_4X_NIC_SEND_RINGS |
10006 GRC_MODE_NO_TX_PHDR_CSUM |
10007 GRC_MODE_NO_RX_PHDR_CSUM);
10008 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 10009
10010 /* Pseudo-header checksum is done by hardware logic and not
10011 * the offload processers, so make the chip do the pseudo-
10012 * header checksums on receive. For transmit it is more
10013 * convenient to do the pseudo-header checksum in software
10014 * as Linux does that on transmit for us in all cases.
10015 */
10016 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 10017
fb4ce8ad
MC		 10018 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10019 if (tp->rxptpctl)
10020 tw32(TG3_RX_PTP_CTL,
10021 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10022
10023 if (tg3_flag(tp, PTP_CAPABLE))
10024 val |= GRC_MODE_TIME_SYNC_ENABLE;
10025
10026 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 10027
10028 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10029 val = tr32(GRC_MISC_CFG);
10030 val &= ~0xff;
10031 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10032 tw32(GRC_MISC_CFG, val);
10033
10034 /* Initialize MBUF/DESC pool. */
63c3a66f 10035 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 10036 /* Do nothing. */
4153577a 10037 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 10038 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 10039 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 10040 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10041 else
10042 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10043 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10044 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 10045 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10046 int fw_len;
10047
077f849d 10048 fw_len = tp->fw_len;
1da177e4
LT		 10049 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10050 tw32(BUFMGR_MB_POOL_ADDR,
10051 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10052 tw32(BUFMGR_MB_POOL_SIZE,
10053 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10054 }
1da177e4 10055
0f893dc6 10056 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 10057 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10058 tp->bufmgr_config.mbuf_read_dma_low_water);
10059 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10060 tp->bufmgr_config.mbuf_mac_rx_low_water);
10061 tw32(BUFMGR_MB_HIGH_WATER,
10062 tp->bufmgr_config.mbuf_high_water);
10063 } else {
10064 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10065 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10066 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10067 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10068 tw32(BUFMGR_MB_HIGH_WATER,
10069 tp->bufmgr_config.mbuf_high_water_jumbo);
10070 }
10071 tw32(BUFMGR_DMA_LOW_WATER,
10072 tp->bufmgr_config.dma_low_water);
10073 tw32(BUFMGR_DMA_HIGH_WATER,
10074 tp->bufmgr_config.dma_high_water);
10075
d309a46e 10076 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 10077 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 10078 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a 10079 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 10080 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 10081 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10082 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 10083 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 10084 tw32(BUFMGR_MODE, val);
1da177e4
LT		 10085 for (i = 0; i < 2000; i++) {
10086 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10087 break;
10088 udelay(10);
10089 }
10090 if (i >= 2000) {
05dbe005 10091 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 10092 return -ENODEV;
10093 }
10094
4153577a 10095 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 10096 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 10097
eb07a940 10098 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 10099
10100 /* Initialize TG3_BDINFO's at:
10101 * RCVDBDI_STD_BD: standard eth size rx ring
10102 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10103 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10104 *
10105 * like so:
10106 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10107 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10108 * ring attribute flags
10109 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10110 *
10111 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10112 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10113 *
10114 * The size of each ring is fixed in the firmware, but the location is
10115 * configurable.
10116 */
10117 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10118 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 10119 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10120 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 10121 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 10122 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10123 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 10124
fdb72b38 10125 /* Disable the mini ring */
63c3a66f 10126 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10127 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10128 BDINFO_FLAGS_DISABLED);
10129
fdb72b38
MC		 10130 /* Program the jumbo buffer descriptor ring control
10131 * blocks on those devices that have them.
10132 */
4153577a 10133 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10134 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10135
63c3a66f 10136 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10137 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10138 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10139 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10140 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10141 val = TG3_RX_JMB_RING_SIZE(tp) <<
10142 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10143 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10144 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10145 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10146 tg3_flag(tp, 57765_CLASS) ||
4153577a 10147 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10148 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10149 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10150 } else {
10151 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10152 BDINFO_FLAGS_DISABLED);
10153 }
10154
63c3a66f 10155 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10156 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10157 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10158 val |= (TG3_RX_STD_DMA_SZ << 2);
10159 } else
04380d40 10160 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10161 } else
de9f5230 10162 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10163
10164 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10165
411da640 10166 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10167 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10168
63c3a66f
JP		 10169 tpr->rx_jmb_prod_idx =
10170 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10171 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10172
2d31ecaf
MC		 10173 tg3_rings_reset(tp);
10174
1da177e4 10175 /* Initialize MAC address and backoff seed. */
953c96e0 10176 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10177
10178 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10179 tw32(MAC_RX_MTU_SIZE,
10180 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10181
10182 /* The slot time is changed by tg3_setup_phy if we
10183 * run at gigabit with half duplex.
10184 */
f2096f94
MC		 10185 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10186 (6 << TX_LENGTHS_IPG_SHIFT) |
10187 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10188
4153577a
JP		 10189 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10190 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10191 val |= tr32(MAC_TX_LENGTHS) &
10192 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10193 TX_LENGTHS_CNT_DWN_VAL_MSK);
10194
10195 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10196
10197 /* Receive rules. */
10198 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10199 tw32(RCVLPC_CONFIG, 0x0181);
10200
10201 /* Calculate RDMAC_MODE setting early, we need it to determine
10202 * the RCVLPC_STATE_ENABLE mask.
10203 */
10204 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10205 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10206 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10207 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10208 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10209
4153577a 10210 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10211 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10212
4153577a
JP		 10213 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10214 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10215 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10216 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10217 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10218 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10219
4153577a
JP		 10220 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10221 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10222 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10223 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10224 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10225 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10226 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10227 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10228 }
10229 }
10230
63c3a66f 10231 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10232 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10233
4153577a 10234 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10235 tp->dma_limit = 0;
10236 if (tp->dev->mtu <= ETH_DATA_LEN) {
10237 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10238 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10239 }
10240 }
10241
63c3a66f
JP		 10242 if (tg3_flag(tp, HW_TSO_1) ||
10243 tg3_flag(tp, HW_TSO_2) ||
10244 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10245 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10246
108a6c16 10247 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10248 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10249 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10250 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10251
4153577a
JP		 10252 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10253 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10254 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10255
4153577a
JP		 10256 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10257 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10258 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10259 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10260 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10261 u32 tgtreg;
10262
4153577a 10263 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10264 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10265 else
10266 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10267
10268 val = tr32(tgtreg);
4153577a
JP		 10269 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10270 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10271 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10272 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10273 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10274 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10275 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10276 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10277 }
c65a17f4 10278 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10279 }
10280
4153577a
JP		 10281 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10282 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10283 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10284 u32 tgtreg;
10285
4153577a 10286 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10287 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10288 else
10289 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10290
10291 val = tr32(tgtreg);
10292 tw32(tgtreg, val |
d309a46e
MC		 10293 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10294 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10295 }
10296
1da177e4 10297 /* Receive/send statistics. */
63c3a66f 10298 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10299 val = tr32(RCVLPC_STATS_ENABLE);
10300 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10301 tw32(RCVLPC_STATS_ENABLE, val);
10302 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10303 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10304 val = tr32(RCVLPC_STATS_ENABLE);
10305 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10306 tw32(RCVLPC_STATS_ENABLE, val);
10307 } else {
10308 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10309 }
10310 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10311 tw32(SNDDATAI_STATSENAB, 0xffffff);
10312 tw32(SNDDATAI_STATSCTRL,
10313 (SNDDATAI_SCTRL_ENABLE |
10314 SNDDATAI_SCTRL_FASTUPD));
10315
10316 /* Setup host coalescing engine. */
10317 tw32(HOSTCC_MODE, 0);
10318 for (i = 0; i < 2000; i++) {
10319 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10320 break;
10321 udelay(10);
10322 }
10323
d244c892 10324 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10325
63c3a66f 10326 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10327 /* Status/statistics block address. See tg3_timer,
10328 * the tg3_periodic_fetch_stats call there, and
10329 * tg3_get_stats to see how this works for 5705/5750 chips.
10330 */
1da177e4
LT		 10331 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10332 ((u64) tp->stats_mapping >> 32));
10333 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10334 ((u64) tp->stats_mapping & 0xffffffff));
10335 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10336
1da177e4 10337 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10338
10339 /* Clear statistics and status block memory areas */
10340 for (i = NIC_SRAM_STATS_BLK;
10341 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10342 i += sizeof(u32)) {
10343 tg3_write_mem(tp, i, 0);
10344 udelay(40);
10345 }
1da177e4
LT		 10346 }
10347
10348 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10349
10350 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10351 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10352 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10353 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10354
f07e9af3
MC		 10355 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10356 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10357 /* reset to prevent losing 1st rx packet intermittently */
10358 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10359 udelay(10);
10360 }
10361
3bda1258 10362 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10363 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10364 MAC_MODE_FHDE_ENABLE;
10365 if (tg3_flag(tp, ENABLE_APE))
10366 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10367 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10368 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10369 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10370 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10371 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10372 udelay(40);
10373
314fba34 10374 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10375 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10376 * register to preserve the GPIO settings for LOMs. The GPIOs,
10377 * whether used as inputs or outputs, are set by boot code after
10378 * reset.
10379 */
63c3a66f 10380 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10381 u32 gpio_mask;
10382
9d26e213
MC		 10383 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10384 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10385 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10386
4153577a 10387 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10388 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10389 GRC_LCLCTRL_GPIO_OUTPUT3;
10390
4153577a 10391 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10392 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10393
aaf84465 10394 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10395 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10396
10397 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10398 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10399 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10400 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10401 }
1da177e4
LT		 10402 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10403 udelay(100);
10404
c3b5003b 10405 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10406 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10407 val |= MSGINT_MODE_ENABLE;
10408 if (tp->irq_cnt > 1)
10409 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10410 if (!tg3_flag(tp, 1SHOT_MSI))
10411 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10412 tw32(MSGINT_MODE, val);
10413 }
10414
63c3a66f 10415 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10416 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10417 udelay(40);
10418 }
10419
10420 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10421 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10422 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10423 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10424 WDMAC_MODE_LNGREAD_ENAB);
10425
4153577a
JP		 10426 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10427 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10428 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10429 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10430 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10431 /* nothing */
10432 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10433 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10434 val |= WDMAC_MODE_RX_ACCEL;
10435 }
10436 }
10437
d9ab5ad1 10438 /* Enable host coalescing bug fix */
63c3a66f 10439 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10440 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10441
4153577a 10442 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10443 val |= WDMAC_MODE_BURST_ALL_DATA;
10444
1da177e4
LT		 10445 tw32_f(WDMAC_MODE, val);
10446 udelay(40);
10447
63c3a66f 10448 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10449 u16 pcix_cmd;
10450
10451 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10452 &pcix_cmd);
4153577a 10453 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10454 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10455 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10456 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10457 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10458 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10459 }
9974a356
MC		 10460 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10461 pcix_cmd);
1da177e4
LT		 10462 }
10463
10464 tw32_f(RDMAC_MODE, rdmac_mode);
10465 udelay(40);
10466
9bc297ea
NS		 10467 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10468 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10469 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10470 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10471 break;
10472 }
10473 if (i < TG3_NUM_RDMA_CHANNELS) {
10474 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10475 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10476 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10477 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10478 }
10479 }
10480
1da177e4 10481 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10482 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10483 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10484
4153577a 10485 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10486 tw32(SNDDATAC_MODE,
10487 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10488 else
10489 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10490
1da177e4
LT		 10491 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10492 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10493 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10494 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10495 val |= RCVDBDI_MODE_LRG_RING_SZ;
10496 tw32(RCVDBDI_MODE, val);
1da177e4 10497 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10498 if (tg3_flag(tp, HW_TSO_1) ||
10499 tg3_flag(tp, HW_TSO_2) ||
10500 tg3_flag(tp, HW_TSO_3))
1da177e4 10501 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10502 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10503 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10504 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10505 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10506 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10507
4153577a 10508 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10509 err = tg3_load_5701_a0_firmware_fix(tp);
10510 if (err)
10511 return err;
10512 }
10513
c4dab506
NS		 10514 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10515 /* Ignore any errors for the firmware download. If download
10516 * fails, the device will operate with EEE disabled
10517 */
10518 tg3_load_57766_firmware(tp);
10519 }
10520
63c3a66f 10521 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10522 err = tg3_load_tso_firmware(tp);
10523 if (err)
10524 return err;
10525 }
1da177e4
LT		 10526
10527 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10528
63c3a66f 10529 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10530 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10531 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10532
4153577a
JP		 10533 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10534 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10535 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10536 tp->tx_mode &= ~val;
10537 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10538 }
10539
1da177e4
LT		 10540 tw32_f(MAC_TX_MODE, tp->tx_mode);
10541 udelay(100);
10542
63c3a66f 10543 if (tg3_flag(tp, ENABLE_RSS)) {
39648356
ED		 10544 u32 rss_key[10];
10545
bcebcc46 10546 tg3_rss_write_indir_tbl(tp);
baf8a94a 10547
39648356
ED		 10548 netdev_rss_key_fill(rss_key, 10 * sizeof(u32));
10549
10550 for (i = 0; i < 10 ; i++)
10551 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);
baf8a94a
MC		 10552 }
10553
1da177e4 10554 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10555 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10556 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10557
378b72c8
NS		 10558 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10559 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10560
63c3a66f 10561 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10562 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10563 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10564 RX_MODE_RSS_IPV6_HASH_EN |
10565 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10566 RX_MODE_RSS_IPV4_HASH_EN |
10567 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10568
1da177e4
LT		 10569 tw32_f(MAC_RX_MODE, tp->rx_mode);
10570 udelay(10);
10571
1da177e4
LT		 10572 tw32(MAC_LED_CTRL, tp->led_ctrl);
10573
10574 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10575 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10576 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10577 udelay(10);
10578 }
10579 tw32_f(MAC_RX_MODE, tp->rx_mode);
10580 udelay(10);
10581
f07e9af3 10582 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10583 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10584 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10585 /* Set drive transmission level to 1.2V */
10586 /* only if the signal pre-emphasis bit is not set */
10587 val = tr32(MAC_SERDES_CFG);
10588 val &= 0xfffff000;
10589 val |= 0x880;
10590 tw32(MAC_SERDES_CFG, val);
10591 }
4153577a 10592 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10593 tw32(MAC_SERDES_CFG, 0x616000);
10594 }
10595
10596 /* Prevent chip from dropping frames when flow control
10597 * is enabled.
10598 */
55086ad9 10599 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10600 val = 1;
10601 else
10602 val = 2;
10603 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10604
4153577a 10605 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10606 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10607 /* Use hardware link auto-negotiation */
63c3a66f 10608 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10609 }
10610
f07e9af3 10611 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10612 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10613 u32 tmp;
10614
10615 tmp = tr32(SERDES_RX_CTRL);
10616 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10617 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10618 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10619 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10620 }
10621
63c3a66f 10622 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10623 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10624 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10625
953c96e0 10626 err = tg3_setup_phy(tp, false);
dd477003
MC		 10627 if (err)
10628 return err;
1da177e4 10629
f07e9af3
MC		 10630 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10631 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10632 u32 tmp;
10633
10634 /* Clear CRC stats. */
10635 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10636 tg3_writephy(tp, MII_TG3_TEST1,
10637 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10638 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10639 }
1da177e4
LT		 10640 }
10641 }
10642
10643 __tg3_set_rx_mode(tp->dev);
10644
10645 /* Initialize receive rules. */
10646 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10647 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10648 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10649 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10650
63c3a66f 10651 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10652 limit = 8;
10653 else
10654 limit = 16;
63c3a66f 10655 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10656 limit -= 4;
10657 switch (limit) {
10658 case 16:
10659 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10660 case 15:
10661 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10662 case 14:
10663 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10664 case 13:
10665 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10666 case 12:
10667 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10668 case 11:
10669 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10670 case 10:
10671 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10672 case 9:
10673 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10674 case 8:
10675 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10676 case 7:
10677 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10678 case 6:
10679 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10680 case 5:
10681 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10682 case 4:
10683 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10684 case 3:
10685 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10686 case 2:
10687 case 1:
10688
10689 default:
10690 break;
855e1111 10691 }
1da177e4 10692
63c3a66f 10693 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10694 /* Write our heartbeat update interval to APE. */
10695 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10696 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10697
1da177e4
LT		 10698 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10699
1da177e4
LT		 10700 return 0;
10701}
10702
10703/* Called at device open time to get the chip ready for
10704 * packet processing. Invoked with tp->lock held.
10705 */
953c96e0 10706static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10707{
df465abf
NS		 10708 /* Chip may have been just powered on. If so, the boot code may still
10709 * be running initialization. Wait for it to finish to avoid races in
10710 * accessing the hardware.
10711 */
10712 tg3_enable_register_access(tp);
10713 tg3_poll_fw(tp);
10714
1da177e4
LT		 10715 tg3_switch_clocks(tp);
10716
10717 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10718
2f751b67 10719 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10720}
10721
aed93e0b
MC		 10722static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10723{
10724 int i;
10725
10726 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10727 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10728
10729 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10730 off += len;
10731
10732 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10733 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10734 memset(ocir, 0, TG3_OCIR_LEN);
10735 }
10736}
10737
10738/* sysfs attributes for hwmon */
10739static ssize_t tg3_show_temp(struct device *dev,
10740 struct device_attribute *devattr, char *buf)
10741{
aed93e0b 10742 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
a2f4dfba 10743 struct tg3 *tp = dev_get_drvdata(dev);
aed93e0b
MC		 10744 u32 temperature;
10745
10746 spin_lock_bh(&tp->lock);
10747 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10748 sizeof(temperature));
10749 spin_unlock_bh(&tp->lock);
10750 return sprintf(buf, "%u\n", temperature);
10751}
10752
10753
10754static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10755 TG3_TEMP_SENSOR_OFFSET);
10756static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10757 TG3_TEMP_CAUTION_OFFSET);
10758static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10759 TG3_TEMP_MAX_OFFSET);
10760
a2f4dfba 10761static struct attribute *tg3_attrs[] = {
aed93e0b
MC		 10762 &sensor_dev_attr_temp1_input.dev_attr.attr,
10763 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10764 &sensor_dev_attr_temp1_max.dev_attr.attr,
10765 NULL
10766};
a2f4dfba 10767ATTRIBUTE_GROUPS(tg3);
aed93e0b 10768
aed93e0b
MC		 10769static void tg3_hwmon_close(struct tg3 *tp)
10770{
aed93e0b
MC		 10771 if (tp->hwmon_dev) {
10772 hwmon_device_unregister(tp->hwmon_dev);
10773 tp->hwmon_dev = NULL;
aed93e0b 10774 }
aed93e0b
MC		 10775}
10776
10777static void tg3_hwmon_open(struct tg3 *tp)
10778{
a2f4dfba 10779 int i;
aed93e0b
MC		 10780 u32 size = 0;
10781 struct pci_dev *pdev = tp->pdev;
10782 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10783
10784 tg3_sd_scan_scratchpad(tp, ocirs);
10785
10786 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10787 if (!ocirs[i].src_data_length)
10788 continue;
10789
10790 size += ocirs[i].src_hdr_length;
10791 size += ocirs[i].src_data_length;
10792 }
10793
10794 if (!size)
10795 return;
10796
a2f4dfba
GR		 10797 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10798 tp, tg3_groups);
aed93e0b
MC		 10799 if (IS_ERR(tp->hwmon_dev)) {
10800 tp->hwmon_dev = NULL;
10801 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
aed93e0b 10802 }
aed93e0b
MC		 10803}
10804
10805
1da177e4
LT		 10806#define TG3_STAT_ADD32(PSTAT, REG) \
10807do { u32 __val = tr32(REG); \
10808 (PSTAT)->low += __val; \
10809 if ((PSTAT)->low < __val) \
10810 (PSTAT)->high += 1; \
10811} while (0)
10812
10813static void tg3_periodic_fetch_stats(struct tg3 *tp)
10814{
10815 struct tg3_hw_stats *sp = tp->hw_stats;
10816
f4a46d1f 10817 if (!tp->link_up)
1da177e4
LT		 10818 return;
10819
10820 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10821 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10822 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10823 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10824 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10825 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10826 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10827 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10828 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10829 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10830 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10831 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10832 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10833 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10834 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10835 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10836 u32 val;
10837
10838 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10839 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10840 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10841 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10842 }
1da177e4
LT		 10843
10844 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10845 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10846 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10847 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10848 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10849 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10850 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10851 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10852 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10853 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10854 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10855 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10856 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10857 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10858
10859 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a 10860 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
94962f7f 10861 tg3_asic_rev(tp) != ASIC_REV_5762 &&
4153577a
JP		 10862 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10863 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10864 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10865 } else {
10866 u32 val = tr32(HOSTCC_FLOW_ATTN);
10867 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10868 if (val) {
10869 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10870 sp->rx_discards.low += val;
10871 if (sp->rx_discards.low < val)
10872 sp->rx_discards.high += 1;
10873 }
10874 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10875 }
463d305b 10876 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10877}
10878
0e6cf6a9
MC		 10879static void tg3_chk_missed_msi(struct tg3 *tp)
10880{
10881 u32 i;
10882
10883 for (i = 0; i < tp->irq_cnt; i++) {
10884 struct tg3_napi *tnapi = &tp->napi[i];
10885
10886 if (tg3_has_work(tnapi)) {
10887 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10888 tnapi->last_tx_cons == tnapi->tx_cons) {
10889 if (tnapi->chk_msi_cnt < 1) {
10890 tnapi->chk_msi_cnt++;
10891 return;
10892 }
7f230735 10893 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10894 }
10895 }
10896 tnapi->chk_msi_cnt = 0;
10897 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10898 tnapi->last_tx_cons = tnapi->tx_cons;
10899 }
10900}
10901
1da177e4
LT		 10902static void tg3_timer(unsigned long __opaque)
10903{
10904 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10905
f47c11ee 10906 spin_lock(&tp->lock);
1da177e4 10907
4fd190a9
PS		 10908 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {
10909 spin_unlock(&tp->lock);
10910 goto restart_timer;
10911 }
10912
4153577a 10913 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10914 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10915 tg3_chk_missed_msi(tp);
10916
7e6c63f0
HM		 10917 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10918 /* BCM4785: Flush posted writes from GbE to host memory. */
10919 tr32(HOSTCC_MODE);
10920 }
10921
63c3a66f 10922 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10923 /* All of this garbage is because when using non-tagged
10924 * IRQ status the mailbox/status_block protocol the chip
10925 * uses with the cpu is race prone.
10926 */
898a56f8 10927 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10928 tw32(GRC_LOCAL_CTRL,
10929 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10930 } else {
10931 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10932 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10933 }
1da177e4 10934
fac9b83e 10935 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10936 spin_unlock(&tp->lock);
db219973 10937 tg3_reset_task_schedule(tp);
5b190624 10938 goto restart_timer;
fac9b83e 10939 }
1da177e4
LT		 10940 }
10941
1da177e4
LT		 10942 /* This part only runs once per second. */
10943 if (!--tp->timer_counter) {
63c3a66f 10944 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10945 tg3_periodic_fetch_stats(tp);
10946
b0c5943f
MC		 10947 if (tp->setlpicnt && !--tp->setlpicnt)
10948 tg3_phy_eee_enable(tp);
52b02d04 10949
63c3a66f 10950 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10951 u32 mac_stat;
10952 int phy_event;
10953
10954 mac_stat = tr32(MAC_STATUS);
10955
10956 phy_event = 0;
f07e9af3 10957 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10958 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10959 phy_event = 1;
10960 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10961 phy_event = 1;
10962
10963 if (phy_event)
953c96e0 10964 tg3_setup_phy(tp, false);
63c3a66f 10965 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10966 u32 mac_stat = tr32(MAC_STATUS);
10967 int need_setup = 0;
10968
f4a46d1f 10969 if (tp->link_up &&
1da177e4
LT		 10970 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10971 need_setup = 1;
10972 }
f4a46d1f 10973 if (!tp->link_up &&
1da177e4
LT		 10974 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10975 MAC_STATUS_SIGNAL_DET))) {
10976 need_setup = 1;
10977 }
10978 if (need_setup) {
3d3ebe74
MC		 10979 if (!tp->serdes_counter) {
10980 tw32_f(MAC_MODE,
10981 (tp->mac_mode &
10982 ~MAC_MODE_PORT_MODE_MASK));
10983 udelay(40);
10984 tw32_f(MAC_MODE, tp->mac_mode);
10985 udelay(40);
10986 }
953c96e0 10987 tg3_setup_phy(tp, false);
1da177e4 10988 }
f07e9af3 10989 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10990 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10991 tg3_serdes_parallel_detect(tp);
1743b83c
NS		 10992 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10993 u32 cpmu = tr32(TG3_CPMU_STATUS);
10994 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10995 TG3_CPMU_STATUS_LINK_MASK);
10996
10997 if (link_up != tp->link_up)
10998 tg3_setup_phy(tp, false);
57d8b880 10999 }
1da177e4
LT		 11000
11001 tp->timer_counter = tp->timer_multiplier;
11002 }
11003
130b8e4d
MC		 11004 /* Heartbeat is only sent once every 2 seconds.
11005 *
11006 * The heartbeat is to tell the ASF firmware that the host
11007 * driver is still alive. In the event that the OS crashes,
11008 * ASF needs to reset the hardware to free up the FIFO space
11009 * that may be filled with rx packets destined for the host.
11010 * If the FIFO is full, ASF will no longer function properly.
11011 *
11012 * Unintended resets have been reported on real time kernels
11013 * where the timer doesn't run on time. Netpoll will also have
11014 * same problem.
11015 *
11016 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11017 * to check the ring condition when the heartbeat is expiring
11018 * before doing the reset. This will prevent most unintended
11019 * resets.
11020 */
1da177e4 11021 if (!--tp->asf_counter) {
63c3a66f 11022 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 11023 tg3_wait_for_event_ack(tp);
11024
bbadf503 11025 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 11026 FWCMD_NICDRV_ALIVE3);
bbadf503 11027 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 11028 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11029 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 11030
11031 tg3_generate_fw_event(tp);
1da177e4
LT		 11032 }
11033 tp->asf_counter = tp->asf_multiplier;
11034 }
11035
f47c11ee 11036 spin_unlock(&tp->lock);
1da177e4 11037
f475f163 11038restart_timer:
1da177e4
LT		 11039 tp->timer.expires = jiffies + tp->timer_offset;
11040 add_timer(&tp->timer);
11041}
11042
229b1ad1 11043static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 11044{
11045 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 11046 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 11047 !tg3_flag(tp, 57765_CLASS))
11048 tp->timer_offset = HZ;
11049 else
11050 tp->timer_offset = HZ / 10;
11051
11052 BUG_ON(tp->timer_offset > HZ);
11053
11054 tp->timer_multiplier = (HZ / tp->timer_offset);
11055 tp->asf_multiplier = (HZ / tp->timer_offset) *
11056 TG3_FW_UPDATE_FREQ_SEC;
11057
11058 init_timer(&tp->timer);
11059 tp->timer.data = (unsigned long) tp;
11060 tp->timer.function = tg3_timer;
11061}
11062
11063static void tg3_timer_start(struct tg3 *tp)
11064{
11065 tp->asf_counter = tp->asf_multiplier;
11066 tp->timer_counter = tp->timer_multiplier;
11067
11068 tp->timer.expires = jiffies + tp->timer_offset;
11069 add_timer(&tp->timer);
11070}
11071
11072static void tg3_timer_stop(struct tg3 *tp)
11073{
11074 del_timer_sync(&tp->timer);
11075}
11076
11077/* Restart hardware after configuration changes, self-test, etc.
11078 * Invoked with tp->lock held.
11079 */
953c96e0 11080static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 11081 __releases(tp->lock)
11082 __acquires(tp->lock)
11083{
11084 int err;
11085
11086 err = tg3_init_hw(tp, reset_phy);
11087 if (err) {
11088 netdev_err(tp->dev,
11089 "Failed to re-initialize device, aborting\n");
11090 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11091 tg3_full_unlock(tp);
11092 tg3_timer_stop(tp);
11093 tp->irq_sync = 0;
11094 tg3_napi_enable(tp);
11095 dev_close(tp->dev);
11096 tg3_full_lock(tp, 0);
11097 }
11098 return err;
11099}
11100
11101static void tg3_reset_task(struct work_struct *work)
11102{
11103 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11104 int err;
11105
db84bf43 11106 rtnl_lock();
21f7638e
MC		 11107 tg3_full_lock(tp, 0);
11108
11109 if (!netif_running(tp->dev)) {
11110 tg3_flag_clear(tp, RESET_TASK_PENDING);
11111 tg3_full_unlock(tp);
db84bf43 11112 rtnl_unlock();
21f7638e
MC		 11113 return;
11114 }
11115
11116 tg3_full_unlock(tp);
11117
11118 tg3_phy_stop(tp);
11119
11120 tg3_netif_stop(tp);
11121
11122 tg3_full_lock(tp, 1);
11123
11124 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11125 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11126 tp->write32_rx_mbox = tg3_write_flush_reg32;
11127 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11128 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11129 }
11130
11131 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11132 err = tg3_init_hw(tp, true);
21f7638e
MC		 11133 if (err)
11134 goto out;
11135
11136 tg3_netif_start(tp);
11137
11138out:
11139 tg3_full_unlock(tp);
11140
11141 if (!err)
11142 tg3_phy_start(tp);
11143
11144 tg3_flag_clear(tp, RESET_TASK_PENDING);
db84bf43 11145 rtnl_unlock();
21f7638e
MC		 11146}
11147
4f125f42 11148static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11149{
7d12e780 11150 irq_handler_t fn;
fcfa0a32 11151 unsigned long flags;
4f125f42
MC		 11152 char *name;
11153 struct tg3_napi *tnapi = &tp->napi[irq_num];
11154
11155 if (tp->irq_cnt == 1)
11156 name = tp->dev->name;
11157 else {
11158 name = &tnapi->irq_lbl[0];
21e315e1
NS		 11159 if (tnapi->tx_buffers && tnapi->rx_rcb)
11160 snprintf(name, IFNAMSIZ,
11161 "%s-txrx-%d", tp->dev->name, irq_num);
11162 else if (tnapi->tx_buffers)
11163 snprintf(name, IFNAMSIZ,
11164 "%s-tx-%d", tp->dev->name, irq_num);
11165 else if (tnapi->rx_rcb)
11166 snprintf(name, IFNAMSIZ,
11167 "%s-rx-%d", tp->dev->name, irq_num);
11168 else
11169 snprintf(name, IFNAMSIZ,
11170 "%s-%d", tp->dev->name, irq_num);
4f125f42
MC		 11171 name[IFNAMSIZ-1] = 0;
11172 }
fcfa0a32 11173
63c3a66f 11174 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11175 fn = tg3_msi;
63c3a66f 11176 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11177 fn = tg3_msi_1shot;
ab392d2d 11178 flags = 0;
fcfa0a32
MC		 11179 } else {
11180 fn = tg3_interrupt;
63c3a66f 11181 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11182 fn = tg3_interrupt_tagged;
ab392d2d 11183 flags = IRQF_SHARED;
fcfa0a32 11184 }
4f125f42
MC		 11185
11186 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11187}
11188
7938109f
MC		 11189static int tg3_test_interrupt(struct tg3 *tp)
11190{
09943a18 11191 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11192 struct net_device *dev = tp->dev;
b16250e3 11193 int err, i, intr_ok = 0;
f6eb9b1f 11194 u32 val;
7938109f 11195
d4bc3927
MC		 11196 if (!netif_running(dev))
11197 return -ENODEV;
11198
7938109f
MC		 11199 tg3_disable_ints(tp);
11200
4f125f42 11201 free_irq(tnapi->irq_vec, tnapi);
7938109f 11202
f6eb9b1f
MC		 11203 /*
11204 * Turn off MSI one shot mode. Otherwise this test has no
11205 * observable way to know whether the interrupt was delivered.
11206 */
3aa1cdf8 11207 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11208 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11209 tw32(MSGINT_MODE, val);
11210 }
11211
4f125f42 11212 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11213 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11214 if (err)
11215 return err;
11216
898a56f8 11217 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11218 tg3_enable_ints(tp);
11219
11220 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11221 tnapi->coal_now);
7938109f
MC		 11222
11223 for (i = 0; i < 5; i++) {
b16250e3
MC		 11224 u32 int_mbox, misc_host_ctrl;
11225
898a56f8 11226 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11227 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11228
11229 if ((int_mbox != 0) ||
11230 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11231 intr_ok = 1;
7938109f 11232 break;
b16250e3
MC		 11233 }
11234
3aa1cdf8
MC		 11235 if (tg3_flag(tp, 57765_PLUS) &&
11236 tnapi->hw_status->status_tag != tnapi->last_tag)
11237 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11238
7938109f
MC		 11239 msleep(10);
11240 }
11241
11242 tg3_disable_ints(tp);
11243
4f125f42 11244 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11245
4f125f42 11246 err = tg3_request_irq(tp, 0);
7938109f
MC		 11247
11248 if (err)
11249 return err;
11250
f6eb9b1f
MC		 11251 if (intr_ok) {
11252 /* Reenable MSI one shot mode. */
5b39de91 11253 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11254 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11255 tw32(MSGINT_MODE, val);
11256 }
7938109f 11257 return 0;
f6eb9b1f 11258 }
7938109f
MC		 11259
11260 return -EIO;
11261}
11262
11263/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11264 * successfully restored
11265 */
11266static int tg3_test_msi(struct tg3 *tp)
11267{
7938109f
MC		 11268 int err;
11269 u16 pci_cmd;
11270
63c3a66f 11271 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11272 return 0;
11273
11274 /* Turn off SERR reporting in case MSI terminates with Master
11275 * Abort.
11276 */
11277 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11278 pci_write_config_word(tp->pdev, PCI_COMMAND,
11279 pci_cmd & ~PCI_COMMAND_SERR);
11280
11281 err = tg3_test_interrupt(tp);
11282
11283 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11284
11285 if (!err)
11286 return 0;
11287
11288 /* other failures */
11289 if (err != -EIO)
11290 return err;
11291
11292 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11293 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11294 "to INTx mode. Please report this failure to the PCI "
11295 "maintainer and include system chipset information\n");
7938109f 11296
4f125f42 11297 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11298
7938109f
MC		 11299 pci_disable_msi(tp->pdev);
11300
63c3a66f 11301 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11302 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11303
4f125f42 11304 err = tg3_request_irq(tp, 0);
7938109f
MC		 11305 if (err)
11306 return err;
11307
11308 /* Need to reset the chip because the MSI cycle may have terminated
11309 * with Master Abort.
11310 */
f47c11ee 11311 tg3_full_lock(tp, 1);
7938109f 11312
944d980e 11313 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11314 err = tg3_init_hw(tp, true);
7938109f 11315
f47c11ee 11316 tg3_full_unlock(tp);
7938109f
MC		 11317
11318 if (err)
4f125f42 11319 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11320
11321 return err;
11322}
11323
9e9fd12d
MC		 11324static int tg3_request_firmware(struct tg3 *tp)
11325{
77997ea3 11326 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11327
11328 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11329 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11330 tp->fw_needed);
9e9fd12d
MC		 11331 return -ENOENT;
11332 }
11333
77997ea3 11334 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11335
11336 /* Firmware blob starts with version numbers, followed by
11337 * start address and _full_ length including BSS sections
11338 * (which must be longer than the actual data, of course
11339 */
11340
77997ea3
NS		 11341 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11342 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11343 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11344 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11345 release_firmware(tp->fw);
11346 tp->fw = NULL;
11347 return -EINVAL;
11348 }
11349
11350 /* We no longer need firmware; we have it. */
11351 tp->fw_needed = NULL;
11352 return 0;
11353}
11354
9102426a 11355static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11356{
9102426a 11357 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11358
9102426a 11359 if (irq_cnt > 1) {
c3b5003b
MC		 11360 /* We want as many rx rings enabled as there are cpus.
11361 * In multiqueue MSI-X mode, the first MSI-X vector
11362 * only deals with link interrupts, etc, so we add
11363 * one to the number of vectors we are requesting.
11364 */
9102426a 11365 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11366 }
679563f4 11367
9102426a
MC		 11368 return irq_cnt;
11369}
11370
11371static bool tg3_enable_msix(struct tg3 *tp)
11372{
11373 int i, rc;
86449944 11374 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11375
0968169c
MC		 11376 tp->txq_cnt = tp->txq_req;
11377 tp->rxq_cnt = tp->rxq_req;
11378 if (!tp->rxq_cnt)
11379 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11380 if (tp->rxq_cnt > tp->rxq_max)
11381 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11382
11383 /* Disable multiple TX rings by default. Simple round-robin hardware
11384 * scheduling of the TX rings can cause starvation of rings with
11385 * small packets when other rings have TSO or jumbo packets.
11386 */
11387 if (!tp->txq_req)
11388 tp->txq_cnt = 1;
9102426a
MC		 11389
11390 tp->irq_cnt = tg3_irq_count(tp);
11391
679563f4
MC		 11392 for (i = 0; i < tp->irq_max; i++) {
11393 msix_ent[i].entry = i;
11394 msix_ent[i].vector = 0;
11395 }
11396
6f1f411a 11397 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
2430b031
MC		 11398 if (rc < 0) {
11399 return false;
6f1f411a 11400 } else if (rc < tp->irq_cnt) {
05dbe005
JP		 11401 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11402 tp->irq_cnt, rc);
679563f4 11403 tp->irq_cnt = rc;
49a359e3 11404 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11405 if (tp->txq_cnt)
11406 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11407 }
11408
11409 for (i = 0; i < tp->irq_max; i++)
11410 tp->napi[i].irq_vec = msix_ent[i].vector;
11411
49a359e3 11412 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11413 pci_disable_msix(tp->pdev);
11414 return false;
11415 }
b92b9040 11416
9102426a
MC		 11417 if (tp->irq_cnt == 1)
11418 return true;
d78b59f5 11419
9102426a
MC		 11420 tg3_flag_set(tp, ENABLE_RSS);
11421
11422 if (tp->txq_cnt > 1)
11423 tg3_flag_set(tp, ENABLE_TSS);
11424
11425 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11426
679563f4
MC		 11427 return true;
11428}
11429
07b0173c
MC		 11430static void tg3_ints_init(struct tg3 *tp)
11431{
63c3a66f
JP		 11432 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11433 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11434 /* All MSI supporting chips should support tagged
11435 * status. Assert that this is the case.
11436 */
5129c3a3
MC		 11437 netdev_warn(tp->dev,
11438 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11439 goto defcfg;
07b0173c 11440 }
4f125f42 11441
63c3a66f
JP		 11442 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11443 tg3_flag_set(tp, USING_MSIX);
11444 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11445 tg3_flag_set(tp, USING_MSI);
679563f4 11446
63c3a66f 11447 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11448 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11449 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11450 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11451 if (!tg3_flag(tp, 1SHOT_MSI))
11452 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11453 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11454 }
11455defcfg:
63c3a66f 11456 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11457 tp->irq_cnt = 1;
11458 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11459 }
11460
11461 if (tp->irq_cnt == 1) {
11462 tp->txq_cnt = 1;
11463 tp->rxq_cnt = 1;
2ddaad39 11464 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11465 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11466 }
07b0173c
MC		 11467}
11468
11469static void tg3_ints_fini(struct tg3 *tp)
11470{
63c3a66f 11471 if (tg3_flag(tp, USING_MSIX))
679563f4 11472 pci_disable_msix(tp->pdev);
63c3a66f 11473 else if (tg3_flag(tp, USING_MSI))
679563f4 11474 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11475 tg3_flag_clear(tp, USING_MSI);
11476 tg3_flag_clear(tp, USING_MSIX);
11477 tg3_flag_clear(tp, ENABLE_RSS);
11478 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11479}
11480
be947307
MC		 11481static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11482 bool init)
1da177e4 11483{
d8f4cd38 11484 struct net_device *dev = tp->dev;
4f125f42 11485 int i, err;
1da177e4 11486
679563f4
MC		 11487 /*
11488 * Setup interrupts first so we know how
11489 * many NAPI resources to allocate
11490 */
11491 tg3_ints_init(tp);
11492
90415477 11493 tg3_rss_check_indir_tbl(tp);
bcebcc46 11494
1da177e4
LT		 11495 /* The placement of this call is tied
11496 * to the setup and use of Host TX descriptors.
11497 */
11498 err = tg3_alloc_consistent(tp);
11499 if (err)
4a5f46f2 11500 goto out_ints_fini;
88b06bc2 11501
66cfd1bd
MC		 11502 tg3_napi_init(tp);
11503
fed97810 11504 tg3_napi_enable(tp);
1da177e4 11505
4f125f42
MC		 11506 for (i = 0; i < tp->irq_cnt; i++) {
11507 struct tg3_napi *tnapi = &tp->napi[i];
11508 err = tg3_request_irq(tp, i);
11509 if (err) {
5bc09186
MC		 11510 for (i--; i >= 0; i--) {
11511 tnapi = &tp->napi[i];
4f125f42 11512 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11513 }
4a5f46f2 11514 goto out_napi_fini;
4f125f42
MC		 11515 }
11516 }
1da177e4 11517
f47c11ee 11518 tg3_full_lock(tp, 0);
1da177e4 11519
2e460fc0
NS		 11520 if (init)
11521 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11522
d8f4cd38 11523 err = tg3_init_hw(tp, reset_phy);
1da177e4 11524 if (err) {
944d980e 11525 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11526 tg3_free_rings(tp);
1da177e4
LT		 11527 }
11528
f47c11ee 11529 tg3_full_unlock(tp);
1da177e4 11530
07b0173c 11531 if (err)
4a5f46f2 11532 goto out_free_irq;
1da177e4 11533
d8f4cd38 11534 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11535 err = tg3_test_msi(tp);
fac9b83e 11536
7938109f 11537 if (err) {
f47c11ee 11538 tg3_full_lock(tp, 0);
944d980e 11539 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11540 tg3_free_rings(tp);
f47c11ee 11541 tg3_full_unlock(tp);
7938109f 11542
4a5f46f2 11543 goto out_napi_fini;
7938109f 11544 }
fcfa0a32 11545
63c3a66f 11546 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11547 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11548
f6eb9b1f
MC		 11549 tw32(PCIE_TRANSACTION_CFG,
11550 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11551 }
7938109f
MC		 11552 }
11553
b02fd9e3
MC		 11554 tg3_phy_start(tp);
11555
aed93e0b
MC		 11556 tg3_hwmon_open(tp);
11557
f47c11ee 11558 tg3_full_lock(tp, 0);
1da177e4 11559
21f7638e 11560 tg3_timer_start(tp);
63c3a66f 11561 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11562 tg3_enable_ints(tp);
11563
be947307
MC		 11564 if (init)
11565 tg3_ptp_init(tp);
11566 else
11567 tg3_ptp_resume(tp);
11568
11569
f47c11ee 11570 tg3_full_unlock(tp);
1da177e4 11571
fe5f5787 11572 netif_tx_start_all_queues(dev);
1da177e4 11573
06c03c02
MB		 11574 /*
11575 * Reset loopback feature if it was turned on while the device was down
11576 * make sure that it's installed properly now.
11577 */
11578 if (dev->features & NETIF_F_LOOPBACK)
11579 tg3_set_loopback(dev, dev->features);
11580
1da177e4 11581 return 0;
07b0173c 11582
4a5f46f2 11583out_free_irq:
4f125f42
MC		 11584 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11585 struct tg3_napi *tnapi = &tp->napi[i];
11586 free_irq(tnapi->irq_vec, tnapi);
11587 }
07b0173c 11588
4a5f46f2 11589out_napi_fini:
fed97810 11590 tg3_napi_disable(tp);
66cfd1bd 11591 tg3_napi_fini(tp);
07b0173c 11592 tg3_free_consistent(tp);
679563f4 11593
4a5f46f2 11594out_ints_fini:
679563f4 11595 tg3_ints_fini(tp);
d8f4cd38 11596
07b0173c 11597 return err;
1da177e4
LT		 11598}
11599
65138594 11600static void tg3_stop(struct tg3 *tp)
1da177e4 11601{
4f125f42 11602 int i;
1da177e4 11603
db219973 11604 tg3_reset_task_cancel(tp);
bd473da3 11605 tg3_netif_stop(tp);
1da177e4 11606
21f7638e 11607 tg3_timer_stop(tp);
1da177e4 11608
aed93e0b
MC		 11609 tg3_hwmon_close(tp);
11610
24bb4fb6
MC		 11611 tg3_phy_stop(tp);
11612
f47c11ee 11613 tg3_full_lock(tp, 1);
1da177e4
LT		 11614
11615 tg3_disable_ints(tp);
11616
944d980e 11617 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11618 tg3_free_rings(tp);
63c3a66f 11619 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11620
f47c11ee 11621 tg3_full_unlock(tp);
1da177e4 11622
4f125f42
MC		 11623 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11624 struct tg3_napi *tnapi = &tp->napi[i];
11625 free_irq(tnapi->irq_vec, tnapi);
11626 }
07b0173c
MC		 11627
11628 tg3_ints_fini(tp);
1da177e4 11629
66cfd1bd
MC		 11630 tg3_napi_fini(tp);
11631
1da177e4 11632 tg3_free_consistent(tp);
65138594
MC		 11633}
11634
d8f4cd38
MC		 11635static int tg3_open(struct net_device *dev)
11636{
11637 struct tg3 *tp = netdev_priv(dev);
11638 int err;
11639
0486a063
IV		 11640 if (tp->pcierr_recovery) {
11641 netdev_err(dev, "Failed to open device. PCI error recovery "
11642 "in progress\n");
11643 return -EAGAIN;
11644 }
11645
d8f4cd38
MC		 11646 if (tp->fw_needed) {
11647 err = tg3_request_firmware(tp);
c4dab506
NS		 11648 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11649 if (err) {
11650 netdev_warn(tp->dev, "EEE capability disabled\n");
11651 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11652 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11653 netdev_warn(tp->dev, "EEE capability restored\n");
11654 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11655 }
11656 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11657 if (err)
11658 return err;
11659 } else if (err) {
11660 netdev_warn(tp->dev, "TSO capability disabled\n");
11661 tg3_flag_clear(tp, TSO_CAPABLE);
11662 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11663 netdev_notice(tp->dev, "TSO capability restored\n");
11664 tg3_flag_set(tp, TSO_CAPABLE);
11665 }
11666 }
11667
f4a46d1f 11668 tg3_carrier_off(tp);
d8f4cd38
MC		 11669
11670 err = tg3_power_up(tp);
11671 if (err)
11672 return err;
11673
11674 tg3_full_lock(tp, 0);
11675
11676 tg3_disable_ints(tp);
11677 tg3_flag_clear(tp, INIT_COMPLETE);
11678
11679 tg3_full_unlock(tp);
11680
942d1af0
NS		 11681 err = tg3_start(tp,
11682 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11683 true, true);
d8f4cd38
MC		 11684 if (err) {
11685 tg3_frob_aux_power(tp, false);
11686 pci_set_power_state(tp->pdev, PCI_D3hot);
11687 }
be947307 11688
7d41e49a
MC		 11689 if (tg3_flag(tp, PTP_CAPABLE)) {
11690 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11691 &tp->pdev->dev);
11692 if (IS_ERR(tp->ptp_clock))
11693 tp->ptp_clock = NULL;
11694 }
11695
07b0173c 11696 return err;
1da177e4
LT		 11697}
11698
1da177e4
LT		 11699static int tg3_close(struct net_device *dev)
11700{
11701 struct tg3 *tp = netdev_priv(dev);
11702
0486a063
IV		 11703 if (tp->pcierr_recovery) {
11704 netdev_err(dev, "Failed to close device. PCI error recovery "
11705 "in progress\n");
11706 return -EAGAIN;
11707 }
11708
be947307
MC		 11709 tg3_ptp_fini(tp);
11710
65138594 11711 tg3_stop(tp);
1da177e4 11712
92feeabf
MC		 11713 /* Clear stats across close / open calls */
11714 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11715 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11716
8496e85c
RW		 11717 if (pci_device_is_present(tp->pdev)) {
11718 tg3_power_down_prepare(tp);
bc1c7567 11719
8496e85c
RW		 11720 tg3_carrier_off(tp);
11721 }
1da177e4
LT		 11722 return 0;
11723}
11724
511d2224 11725static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11726{
11727 return ((u64)val->high << 32) | ((u64)val->low);
11728}
11729
65ec698d 11730static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11731{
11732 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11733
f07e9af3 11734 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11735 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11736 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11737 u32 val;
11738
569a5df8
MC		 11739 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11740 tg3_writephy(tp, MII_TG3_TEST1,
11741 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11742 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11743 } else
11744 val = 0;
1da177e4
LT		 11745
11746 tp->phy_crc_errors += val;
11747
11748 return tp->phy_crc_errors;
11749 }
11750
11751 return get_stat64(&hw_stats->rx_fcs_errors);
11752}
11753
11754#define ESTAT_ADD(member) \
11755 estats->member = old_estats->member + \
511d2224 11756 get_stat64(&hw_stats->member)
1da177e4 11757
65ec698d 11758static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11759{
1da177e4
LT		 11760 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11761 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11762
1da177e4
LT		 11763 ESTAT_ADD(rx_octets);
11764 ESTAT_ADD(rx_fragments);
11765 ESTAT_ADD(rx_ucast_packets);
11766 ESTAT_ADD(rx_mcast_packets);
11767 ESTAT_ADD(rx_bcast_packets);
11768 ESTAT_ADD(rx_fcs_errors);
11769 ESTAT_ADD(rx_align_errors);
11770 ESTAT_ADD(rx_xon_pause_rcvd);
11771 ESTAT_ADD(rx_xoff_pause_rcvd);
11772 ESTAT_ADD(rx_mac_ctrl_rcvd);
11773 ESTAT_ADD(rx_xoff_entered);
11774 ESTAT_ADD(rx_frame_too_long_errors);
11775 ESTAT_ADD(rx_jabbers);
11776 ESTAT_ADD(rx_undersize_packets);
11777 ESTAT_ADD(rx_in_length_errors);
11778 ESTAT_ADD(rx_out_length_errors);
11779 ESTAT_ADD(rx_64_or_less_octet_packets);
11780 ESTAT_ADD(rx_65_to_127_octet_packets);
11781 ESTAT_ADD(rx_128_to_255_octet_packets);
11782 ESTAT_ADD(rx_256_to_511_octet_packets);
11783 ESTAT_ADD(rx_512_to_1023_octet_packets);
11784 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11785 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11786 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11787 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11788 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11789
11790 ESTAT_ADD(tx_octets);
11791 ESTAT_ADD(tx_collisions);
11792 ESTAT_ADD(tx_xon_sent);
11793 ESTAT_ADD(tx_xoff_sent);
11794 ESTAT_ADD(tx_flow_control);
11795 ESTAT_ADD(tx_mac_errors);
11796 ESTAT_ADD(tx_single_collisions);
11797 ESTAT_ADD(tx_mult_collisions);
11798 ESTAT_ADD(tx_deferred);
11799 ESTAT_ADD(tx_excessive_collisions);
11800 ESTAT_ADD(tx_late_collisions);
11801 ESTAT_ADD(tx_collide_2times);
11802 ESTAT_ADD(tx_collide_3times);
11803 ESTAT_ADD(tx_collide_4times);
11804 ESTAT_ADD(tx_collide_5times);
11805 ESTAT_ADD(tx_collide_6times);
11806 ESTAT_ADD(tx_collide_7times);
11807 ESTAT_ADD(tx_collide_8times);
11808 ESTAT_ADD(tx_collide_9times);
11809 ESTAT_ADD(tx_collide_10times);
11810 ESTAT_ADD(tx_collide_11times);
11811 ESTAT_ADD(tx_collide_12times);
11812 ESTAT_ADD(tx_collide_13times);
11813 ESTAT_ADD(tx_collide_14times);
11814 ESTAT_ADD(tx_collide_15times);
11815 ESTAT_ADD(tx_ucast_packets);
11816 ESTAT_ADD(tx_mcast_packets);
11817 ESTAT_ADD(tx_bcast_packets);
11818 ESTAT_ADD(tx_carrier_sense_errors);
11819 ESTAT_ADD(tx_discards);
11820 ESTAT_ADD(tx_errors);
11821
11822 ESTAT_ADD(dma_writeq_full);
11823 ESTAT_ADD(dma_write_prioq_full);
11824 ESTAT_ADD(rxbds_empty);
11825 ESTAT_ADD(rx_discards);
11826 ESTAT_ADD(rx_errors);
11827 ESTAT_ADD(rx_threshold_hit);
11828
11829 ESTAT_ADD(dma_readq_full);
11830 ESTAT_ADD(dma_read_prioq_full);
11831 ESTAT_ADD(tx_comp_queue_full);
11832
11833 ESTAT_ADD(ring_set_send_prod_index);
11834 ESTAT_ADD(ring_status_update);
11835 ESTAT_ADD(nic_irqs);
11836 ESTAT_ADD(nic_avoided_irqs);
11837 ESTAT_ADD(nic_tx_threshold_hit);
11838
4452d099 11839 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11840}
11841
65ec698d 11842static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11843{
511d2224 11844 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11845 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11846
1da177e4
LT		 11847 stats->rx_packets = old_stats->rx_packets +
11848 get_stat64(&hw_stats->rx_ucast_packets) +
11849 get_stat64(&hw_stats->rx_mcast_packets) +
11850 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11851
1da177e4
LT		 11852 stats->tx_packets = old_stats->tx_packets +
11853 get_stat64(&hw_stats->tx_ucast_packets) +
11854 get_stat64(&hw_stats->tx_mcast_packets) +
11855 get_stat64(&hw_stats->tx_bcast_packets);
11856
11857 stats->rx_bytes = old_stats->rx_bytes +
11858 get_stat64(&hw_stats->rx_octets);
11859 stats->tx_bytes = old_stats->tx_bytes +
11860 get_stat64(&hw_stats->tx_octets);
11861
11862 stats->rx_errors = old_stats->rx_errors +
4f63b877 11863 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11864 stats->tx_errors = old_stats->tx_errors +
11865 get_stat64(&hw_stats->tx_errors) +
11866 get_stat64(&hw_stats->tx_mac_errors) +
11867 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11868 get_stat64(&hw_stats->tx_discards);
11869
11870 stats->multicast = old_stats->multicast +
11871 get_stat64(&hw_stats->rx_mcast_packets);
11872 stats->collisions = old_stats->collisions +
11873 get_stat64(&hw_stats->tx_collisions);
11874
11875 stats->rx_length_errors = old_stats->rx_length_errors +
11876 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11877 get_stat64(&hw_stats->rx_undersize_packets);
11878
1da177e4
LT		 11879 stats->rx_frame_errors = old_stats->rx_frame_errors +
11880 get_stat64(&hw_stats->rx_align_errors);
11881 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11882 get_stat64(&hw_stats->tx_discards);
11883 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11884 get_stat64(&hw_stats->tx_carrier_sense_errors);
11885
11886 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11887 tg3_calc_crc_errors(tp);
1da177e4 11888
4f63b877
JL		 11889 stats->rx_missed_errors = old_stats->rx_missed_errors +
11890 get_stat64(&hw_stats->rx_discards);
11891
b0057c51 11892 stats->rx_dropped = tp->rx_dropped;
48855432 11893 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11894}
11895
1da177e4
LT		 11896static int tg3_get_regs_len(struct net_device *dev)
11897{
97bd8e49 11898 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11899}
11900
11901static void tg3_get_regs(struct net_device *dev,
11902 struct ethtool_regs *regs, void *_p)
11903{
1da177e4 11904 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11905
11906 regs->version = 0;
11907
97bd8e49 11908 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11909
80096068 11910 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11911 return;
11912
f47c11ee 11913 tg3_full_lock(tp, 0);
1da177e4 11914
97bd8e49 11915 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11916
f47c11ee 11917 tg3_full_unlock(tp);
1da177e4
LT		 11918}
11919
11920static int tg3_get_eeprom_len(struct net_device *dev)
11921{
11922 struct tg3 *tp = netdev_priv(dev);
11923
11924 return tp->nvram_size;
11925}
11926
1da177e4
LT		 11927static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11928{
11929 struct tg3 *tp = netdev_priv(dev);
506724c4 11930 int ret, cpmu_restore = 0;
1da177e4 11931 u8 *pd;
506724c4 11932 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
a9dc529d 11933 __be32 val;
1da177e4 11934
63c3a66f 11935 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11936 return -EINVAL;
11937
1da177e4
LT		 11938 offset = eeprom->offset;
11939 len = eeprom->len;
11940 eeprom->len = 0;
11941
11942 eeprom->magic = TG3_EEPROM_MAGIC;
11943
506724c4
PS		 11944 /* Override clock, link aware and link idle modes */
11945 if (tg3_flag(tp, CPMU_PRESENT)) {
11946 cpmu_val = tr32(TG3_CPMU_CTRL);
11947 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
11948 CPMU_CTRL_LINK_IDLE_MODE)) {
11949 tw32(TG3_CPMU_CTRL, cpmu_val &
11950 ~(CPMU_CTRL_LINK_AWARE_MODE |
11951 CPMU_CTRL_LINK_IDLE_MODE));
11952 cpmu_restore = 1;
11953 }
11954 }
11955 tg3_override_clk(tp);
11956
1da177e4
LT		 11957 if (offset & 3) {
11958 /* adjustments to start on required 4 byte boundary */
11959 b_offset = offset & 3;
11960 b_count = 4 - b_offset;
11961 if (b_count > len) {
11962 /* i.e. offset=1 len=2 */
11963 b_count = len;
11964 }
a9dc529d 11965 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4 11966 if (ret)
506724c4 11967 goto eeprom_done;
be98da6a 11968 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11969 len -= b_count;
11970 offset += b_count;
c6cdf436 11971 eeprom->len += b_count;
1da177e4
LT		 11972 }
11973
25985edc 11974 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11975 pd = &data[eeprom->len];
11976 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11977 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4 11978 if (ret) {
506724c4
PS		 11979 if (i)
11980 i -= 4;
1da177e4 11981 eeprom->len += i;
506724c4 11982 goto eeprom_done;
1da177e4 11983 }
1da177e4 11984 memcpy(pd + i, &val, 4);
506724c4
PS		 11985 if (need_resched()) {
11986 if (signal_pending(current)) {
11987 eeprom->len += i;
11988 ret = -EINTR;
11989 goto eeprom_done;
11990 }
11991 cond_resched();
11992 }
1da177e4
LT		 11993 }
11994 eeprom->len += i;
11995
11996 if (len & 3) {
11997 /* read last bytes not ending on 4 byte boundary */
11998 pd = &data[eeprom->len];
11999 b_count = len & 3;
12000 b_offset = offset + len - b_count;
a9dc529d 12001 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4 12002 if (ret)
506724c4 12003 goto eeprom_done;
b9fc7dc5 12004 memcpy(pd, &val, b_count);
1da177e4
LT		 12005 eeprom->len += b_count;
12006 }
506724c4
PS		 12007 ret = 0;
12008
12009eeprom_done:
12010 /* Restore clock, link aware and link idle modes */
12011 tg3_restore_clk(tp);
12012 if (cpmu_restore)
12013 tw32(TG3_CPMU_CTRL, cpmu_val);
12014
12015 return ret;
1da177e4
LT		 12016}
12017
1da177e4
LT		 12018static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12019{
12020 struct tg3 *tp = netdev_priv(dev);
12021 int ret;
b9fc7dc5 12022 u32 offset, len, b_offset, odd_len;
1da177e4 12023 u8 *buf;
a9dc529d 12024 __be32 start, end;
1da177e4 12025
63c3a66f 12026 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 12027 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 12028 return -EINVAL;
12029
12030 offset = eeprom->offset;
12031 len = eeprom->len;
12032
12033 if ((b_offset = (offset & 3))) {
12034 /* adjustments to start on required 4 byte boundary */
a9dc529d 12035 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 12036 if (ret)
12037 return ret;
1da177e4
LT		 12038 len += b_offset;
12039 offset &= ~3;
1c8594b4
MC		 12040 if (len < 4)
12041 len = 4;
1da177e4
LT		 12042 }
12043
12044 odd_len = 0;
1c8594b4 12045 if (len & 3) {
1da177e4
LT		 12046 /* adjustments to end on required 4 byte boundary */
12047 odd_len = 1;
12048 len = (len + 3) & ~3;
a9dc529d 12049 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 12050 if (ret)
12051 return ret;
1da177e4
LT		 12052 }
12053
12054 buf = data;
12055 if (b_offset || odd_len) {
12056 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 12057 if (!buf)
1da177e4
LT		 12058 return -ENOMEM;
12059 if (b_offset)
12060 memcpy(buf, &start, 4);
12061 if (odd_len)
12062 memcpy(buf+len-4, &end, 4);
12063 memcpy(buf + b_offset, data, eeprom->len);
12064 }
12065
12066 ret = tg3_nvram_write_block(tp, offset, len, buf);
12067
12068 if (buf != data)
12069 kfree(buf);
12070
12071 return ret;
12072}
12073
12074static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12075{
b02fd9e3
MC		 12076 struct tg3 *tp = netdev_priv(dev);
12077
63c3a66f 12078 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12079 struct phy_device *phydev;
f07e9af3 12080 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12081 return -EAGAIN;
ead2402c 12082 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12083 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 12084 }
6aa20a22 12085
1da177e4
LT		 12086 cmd->supported = (SUPPORTED_Autoneg);
12087
f07e9af3 12088 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 12089 cmd->supported |= (SUPPORTED_1000baseT_Half |
12090 SUPPORTED_1000baseT_Full);
12091
f07e9af3 12092 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 12093 cmd->supported |= (SUPPORTED_100baseT_Half |
12094 SUPPORTED_100baseT_Full |
12095 SUPPORTED_10baseT_Half |
12096 SUPPORTED_10baseT_Full |
3bebab59 12097 SUPPORTED_TP);
ef348144
KK		 12098 cmd->port = PORT_TP;
12099 } else {
1da177e4 12100 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 12101 cmd->port = PORT_FIBRE;
12102 }
6aa20a22 12103
1da177e4 12104 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 12105 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12106 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12107 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12108 cmd->advertising |= ADVERTISED_Pause;
12109 } else {
12110 cmd->advertising |= ADVERTISED_Pause |
12111 ADVERTISED_Asym_Pause;
12112 }
12113 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12114 cmd->advertising |= ADVERTISED_Asym_Pause;
12115 }
12116 }
f4a46d1f 12117 if (netif_running(dev) && tp->link_up) {
70739497 12118 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 12119 cmd->duplex = tp->link_config.active_duplex;
859edb26 12120 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 12121 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12122 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12123 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12124 else
12125 cmd->eth_tp_mdix = ETH_TP_MDI;
12126 }
64c22182 12127 } else {
e740522e
MC		 12128 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12129 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 12130 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 12131 }
882e9793 12132 cmd->phy_address = tp->phy_addr;
7e5856bd 12133 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 12134 cmd->autoneg = tp->link_config.autoneg;
12135 cmd->maxtxpkt = 0;
12136 cmd->maxrxpkt = 0;
12137 return 0;
12138}
6aa20a22 12139
1da177e4
LT		 12140static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12141{
12142 struct tg3 *tp = netdev_priv(dev);
25db0338 12143 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 12144
63c3a66f 12145 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12146 struct phy_device *phydev;
f07e9af3 12147 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12148 return -EAGAIN;
ead2402c 12149 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12150 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 12151 }
12152
7e5856bd
MC		 12153 if (cmd->autoneg != AUTONEG_ENABLE &&
12154 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 12155 return -EINVAL;
7e5856bd
MC		 12156
12157 if (cmd->autoneg == AUTONEG_DISABLE &&
12158 cmd->duplex != DUPLEX_FULL &&
12159 cmd->duplex != DUPLEX_HALF)
37ff238d 12160 return -EINVAL;
1da177e4 12161
7e5856bd
MC		 12162 if (cmd->autoneg == AUTONEG_ENABLE) {
12163 u32 mask = ADVERTISED_Autoneg |
12164 ADVERTISED_Pause |
12165 ADVERTISED_Asym_Pause;
12166
f07e9af3 12167 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 12168 mask |= ADVERTISED_1000baseT_Half |
12169 ADVERTISED_1000baseT_Full;
12170
f07e9af3 12171 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12172 mask |= ADVERTISED_100baseT_Half |
12173 ADVERTISED_100baseT_Full |
12174 ADVERTISED_10baseT_Half |
12175 ADVERTISED_10baseT_Full |
12176 ADVERTISED_TP;
12177 else
12178 mask |= ADVERTISED_FIBRE;
12179
12180 if (cmd->advertising & ~mask)
12181 return -EINVAL;
12182
12183 mask &= (ADVERTISED_1000baseT_Half |
12184 ADVERTISED_1000baseT_Full |
12185 ADVERTISED_100baseT_Half |
12186 ADVERTISED_100baseT_Full |
12187 ADVERTISED_10baseT_Half |
12188 ADVERTISED_10baseT_Full);
12189
12190 cmd->advertising &= mask;
12191 } else {
f07e9af3 12192 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12193 if (speed != SPEED_1000)
7e5856bd
MC		 12194 return -EINVAL;
12195
12196 if (cmd->duplex != DUPLEX_FULL)
12197 return -EINVAL;
12198 } else {
25db0338
DD		 12199 if (speed != SPEED_100 &&
12200 speed != SPEED_10)
7e5856bd
MC		 12201 return -EINVAL;
12202 }
12203 }
12204
f47c11ee 12205 tg3_full_lock(tp, 0);
1da177e4
LT		 12206
12207 tp->link_config.autoneg = cmd->autoneg;
12208 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12209 tp->link_config.advertising = (cmd->advertising |
12210 ADVERTISED_Autoneg);
e740522e
MC		 12211 tp->link_config.speed = SPEED_UNKNOWN;
12212 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12213 } else {
12214 tp->link_config.advertising = 0;
25db0338 12215 tp->link_config.speed = speed;
1da177e4 12216 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12217 }
6aa20a22 12218
fdad8de4
NS		 12219 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12220
ce20f161
NS		 12221 tg3_warn_mgmt_link_flap(tp);
12222
1da177e4 12223 if (netif_running(dev))
953c96e0 12224 tg3_setup_phy(tp, true);
1da177e4 12225
f47c11ee 12226 tg3_full_unlock(tp);
6aa20a22 12227
1da177e4
LT		 12228 return 0;
12229}
6aa20a22 12230
1da177e4
LT		 12231static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12232{
12233 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12234
68aad78c
RJ		 12235 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12236 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12237 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12238 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12239}
6aa20a22 12240
1da177e4
LT		 12241static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12242{
12243 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12244
63c3a66f 12245 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12246 wol->supported = WAKE_MAGIC;
12247 else
12248 wol->supported = 0;
1da177e4 12249 wol->wolopts = 0;
63c3a66f 12250 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12251 wol->wolopts = WAKE_MAGIC;
12252 memset(&wol->sopass, 0, sizeof(wol->sopass));
12253}
6aa20a22 12254
1da177e4
LT		 12255static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12256{
12257 struct tg3 *tp = netdev_priv(dev);
12dac075 12258 struct device *dp = &tp->pdev->dev;
6aa20a22 12259
1da177e4
LT		 12260 if (wol->wolopts & ~WAKE_MAGIC)
12261 return -EINVAL;
12262 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12263 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12264 return -EINVAL;
6aa20a22 12265
f2dc0d18
RW		 12266 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12267
f2dc0d18 12268 if (device_may_wakeup(dp))
63c3a66f 12269 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12270 else
63c3a66f 12271 tg3_flag_clear(tp, WOL_ENABLE);
6aa20a22 12272
1da177e4
LT		 12273 return 0;
12274}
6aa20a22 12275
1da177e4
LT		 12276static u32 tg3_get_msglevel(struct net_device *dev)
12277{
12278 struct tg3 *tp = netdev_priv(dev);
12279 return tp->msg_enable;
12280}
6aa20a22 12281
1da177e4
LT		 12282static void tg3_set_msglevel(struct net_device *dev, u32 value)
12283{
12284 struct tg3 *tp = netdev_priv(dev);
12285 tp->msg_enable = value;
12286}
6aa20a22 12287
1da177e4
LT		 12288static int tg3_nway_reset(struct net_device *dev)
12289{
12290 struct tg3 *tp = netdev_priv(dev);
1da177e4 12291 int r;
6aa20a22 12292
1da177e4
LT		 12293 if (!netif_running(dev))
12294 return -EAGAIN;
12295
f07e9af3 12296 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12297 return -EINVAL;
12298
ce20f161
NS		 12299 tg3_warn_mgmt_link_flap(tp);
12300
63c3a66f 12301 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12302 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12303 return -EAGAIN;
ead2402c 12304 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 12305 } else {
12306 u32 bmcr;
12307
12308 spin_lock_bh(&tp->lock);
12309 r = -EINVAL;
12310 tg3_readphy(tp, MII_BMCR, &bmcr);
12311 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12312 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12313 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12314 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12315 BMCR_ANENABLE);
12316 r = 0;
12317 }
12318 spin_unlock_bh(&tp->lock);
1da177e4 12319 }
6aa20a22 12320
1da177e4
LT		 12321 return r;
12322}
6aa20a22 12323
1da177e4
LT		 12324static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12325{
12326 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12327
2c49a44d 12328 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12329 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12330 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12331 else
12332 ering->rx_jumbo_max_pending = 0;
12333
12334 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12335
12336 ering->rx_pending = tp->rx_pending;
63c3a66f 12337 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12338 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12339 else
12340 ering->rx_jumbo_pending = 0;
12341
f3f3f27e 12342 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12343}
6aa20a22 12344
1da177e4
LT		 12345static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12346{
12347 struct tg3 *tp = netdev_priv(dev);
646c9edd 12348 int i, irq_sync = 0, err = 0;
6aa20a22 12349
2c49a44d
MC		 12350 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12351 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12352 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12353 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12354 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12355 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12356 return -EINVAL;
6aa20a22 12357
bbe832c0 12358 if (netif_running(dev)) {
b02fd9e3 12359 tg3_phy_stop(tp);
1da177e4 12360 tg3_netif_stop(tp);
bbe832c0
MC		 12361 irq_sync = 1;
12362 }
1da177e4 12363
bbe832c0 12364 tg3_full_lock(tp, irq_sync);
6aa20a22 12365
1da177e4
LT		 12366 tp->rx_pending = ering->rx_pending;
12367
63c3a66f 12368 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12369 tp->rx_pending > 63)
12370 tp->rx_pending = 63;
ba67b510
IV		 12371
12372 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12373 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12374
6fd45cb8 12375 for (i = 0; i < tp->irq_max; i++)
646c9edd 12376 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12377
12378 if (netif_running(dev)) {
944d980e 12379 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12380 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12381 if (!err)
12382 tg3_netif_start(tp);
1da177e4
LT		 12383 }
12384
f47c11ee 12385 tg3_full_unlock(tp);
6aa20a22 12386
b02fd9e3
MC		 12387 if (irq_sync && !err)
12388 tg3_phy_start(tp);
12389
b9ec6c1b 12390 return err;
1da177e4 12391}
6aa20a22 12392
1da177e4
LT		 12393static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12394{
12395 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12396
63c3a66f 12397 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12398
4a2db503 12399 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12400 epause->rx_pause = 1;
12401 else
12402 epause->rx_pause = 0;
12403
4a2db503 12404 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12405 epause->tx_pause = 1;
12406 else
12407 epause->tx_pause = 0;
1da177e4 12408}
6aa20a22 12409
1da177e4
LT		 12410static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12411{
12412 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12413 int err = 0;
6aa20a22 12414
ce20f161
NS		 12415 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12416 tg3_warn_mgmt_link_flap(tp);
12417
63c3a66f 12418 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12419 u32 newadv;
12420 struct phy_device *phydev;
1da177e4 12421
ead2402c 12422 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
f47c11ee 12423
2712168f
MC		 12424 if (!(phydev->supported & SUPPORTED_Pause) ||
12425 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12426 (epause->rx_pause != epause->tx_pause)))
2712168f 12427 return -EINVAL;
1da177e4 12428
2712168f
MC		 12429 tp->link_config.flowctrl = 0;
12430 if (epause->rx_pause) {
12431 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12432
12433 if (epause->tx_pause) {
12434 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12435 newadv = ADVERTISED_Pause;
b02fd9e3 12436 } else
2712168f
MC		 12437 newadv = ADVERTISED_Pause |
12438 ADVERTISED_Asym_Pause;
12439 } else if (epause->tx_pause) {
12440 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12441 newadv = ADVERTISED_Asym_Pause;
12442 } else
12443 newadv = 0;
12444
12445 if (epause->autoneg)
63c3a66f 12446 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12447 else
63c3a66f 12448 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12449
f07e9af3 12450 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12451 u32 oldadv = phydev->advertising &
12452 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12453 if (oldadv != newadv) {
12454 phydev->advertising &=
12455 ~(ADVERTISED_Pause |
12456 ADVERTISED_Asym_Pause);
12457 phydev->advertising |= newadv;
12458 if (phydev->autoneg) {
12459 /*
12460 * Always renegotiate the link to
12461 * inform our link partner of our
12462 * flow control settings, even if the
12463 * flow control is forced. Let
12464 * tg3_adjust_link() do the final
12465 * flow control setup.
12466 */
12467 return phy_start_aneg(phydev);
b02fd9e3 12468 }
b02fd9e3 12469 }
b02fd9e3 12470
2712168f 12471 if (!epause->autoneg)
b02fd9e3 12472 tg3_setup_flow_control(tp, 0, 0);
2712168f 12473 } else {
c6700ce2 12474 tp->link_config.advertising &=
2712168f
MC		 12475 ~(ADVERTISED_Pause |
12476 ADVERTISED_Asym_Pause);
c6700ce2 12477 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12478 }
12479 } else {
12480 int irq_sync = 0;
12481
12482 if (netif_running(dev)) {
12483 tg3_netif_stop(tp);
12484 irq_sync = 1;
12485 }
12486
12487 tg3_full_lock(tp, irq_sync);
12488
12489 if (epause->autoneg)
63c3a66f 12490 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12491 else
63c3a66f 12492 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12493 if (epause->rx_pause)
e18ce346 12494 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12495 else
e18ce346 12496 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12497 if (epause->tx_pause)
e18ce346 12498 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12499 else
e18ce346 12500 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12501
12502 if (netif_running(dev)) {
12503 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12504 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12505 if (!err)
12506 tg3_netif_start(tp);
12507 }
12508
12509 tg3_full_unlock(tp);
12510 }
6aa20a22 12511
fdad8de4
NS		 12512 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12513
b9ec6c1b 12514 return err;
1da177e4 12515}
6aa20a22 12516
de6f31eb 12517static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12518{
b9f2c044
JG		 12519 switch (sset) {
12520 case ETH_SS_TEST:
12521 return TG3_NUM_TEST;
12522 case ETH_SS_STATS:
12523 return TG3_NUM_STATS;
12524 default:
12525 return -EOPNOTSUPP;
12526 }
4cafd3f5
MC		 12527}
12528
90415477
MC		 12529static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12530 u32 *rules __always_unused)
12531{
12532 struct tg3 *tp = netdev_priv(dev);
12533
12534 if (!tg3_flag(tp, SUPPORT_MSIX))
12535 return -EOPNOTSUPP;
12536
12537 switch (info->cmd) {
12538 case ETHTOOL_GRXRINGS:
12539 if (netif_running(tp->dev))
9102426a 12540 info->data = tp->rxq_cnt;
90415477
MC		 12541 else {
12542 info->data = num_online_cpus();
9102426a
MC		 12543 if (info->data > TG3_RSS_MAX_NUM_QS)
12544 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12545 }
12546
12547 /* The first interrupt vector only
12548 * handles link interrupts.
12549 */
12550 info->data -= 1;
12551 return 0;
12552
12553 default:
12554 return -EOPNOTSUPP;
12555 }
12556}
12557
12558static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12559{
12560 u32 size = 0;
12561 struct tg3 *tp = netdev_priv(dev);
12562
12563 if (tg3_flag(tp, SUPPORT_MSIX))
12564 size = TG3_RSS_INDIR_TBL_SIZE;
12565
12566 return size;
12567}
12568
892311f6 12569static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, u8 *hfunc)
90415477
MC		 12570{
12571 struct tg3 *tp = netdev_priv(dev);
12572 int i;
12573
892311f6
EP		 12574 if (hfunc)
12575 *hfunc = ETH_RSS_HASH_TOP;
12576 if (!indir)
12577 return 0;
12578
90415477
MC		 12579 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12580 indir[i] = tp->rss_ind_tbl[i];
12581
12582 return 0;
12583}
12584
892311f6
EP		 12585static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
12586 const u8 hfunc)
90415477
MC		 12587{
12588 struct tg3 *tp = netdev_priv(dev);
12589 size_t i;
12590
892311f6
EP		 12591 /* We require at least one supported parameter to be changed and no
12592 * change in any of the unsupported parameters
12593 */
12594 if (key ||
12595 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
12596 return -EOPNOTSUPP;
12597
12598 if (!indir)
12599 return 0;
12600
90415477
MC		 12601 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12602 tp->rss_ind_tbl[i] = indir[i];
12603
12604 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12605 return 0;
12606
12607 /* It is legal to write the indirection
12608 * table while the device is running.
12609 */
12610 tg3_full_lock(tp, 0);
12611 tg3_rss_write_indir_tbl(tp);
12612 tg3_full_unlock(tp);
12613
12614 return 0;
12615}
12616
0968169c
MC		 12617static void tg3_get_channels(struct net_device *dev,
12618 struct ethtool_channels *channel)
12619{
12620 struct tg3 *tp = netdev_priv(dev);
12621 u32 deflt_qs = netif_get_num_default_rss_queues();
12622
12623 channel->max_rx = tp->rxq_max;
12624 channel->max_tx = tp->txq_max;
12625
12626 if (netif_running(dev)) {
12627 channel->rx_count = tp->rxq_cnt;
12628 channel->tx_count = tp->txq_cnt;
12629 } else {
12630 if (tp->rxq_req)
12631 channel->rx_count = tp->rxq_req;
12632 else
12633 channel->rx_count = min(deflt_qs, tp->rxq_max);
12634
12635 if (tp->txq_req)
12636 channel->tx_count = tp->txq_req;
12637 else
12638 channel->tx_count = min(deflt_qs, tp->txq_max);
12639 }
12640}
12641
12642static int tg3_set_channels(struct net_device *dev,
12643 struct ethtool_channels *channel)
12644{
12645 struct tg3 *tp = netdev_priv(dev);
12646
12647 if (!tg3_flag(tp, SUPPORT_MSIX))
12648 return -EOPNOTSUPP;
12649
12650 if (channel->rx_count > tp->rxq_max ||
12651 channel->tx_count > tp->txq_max)
12652 return -EINVAL;
12653
12654 tp->rxq_req = channel->rx_count;
12655 tp->txq_req = channel->tx_count;
12656
12657 if (!netif_running(dev))
12658 return 0;
12659
12660 tg3_stop(tp);
12661
f4a46d1f 12662 tg3_carrier_off(tp);
0968169c 12663
be947307 12664 tg3_start(tp, true, false, false);
0968169c
MC		 12665
12666 return 0;
12667}
12668
de6f31eb 12669static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12670{
12671 switch (stringset) {
12672 case ETH_SS_STATS:
12673 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12674 break;
4cafd3f5
MC		 12675 case ETH_SS_TEST:
12676 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12677 break;
1da177e4
LT		 12678 default:
12679 WARN_ON(1); /* we need a WARN() */
12680 break;
12681 }
12682}
12683
81b8709c 12684static int tg3_set_phys_id(struct net_device *dev,
12685 enum ethtool_phys_id_state state)
4009a93d
MC		 12686{
12687 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12688
12689 if (!netif_running(tp->dev))
12690 return -EAGAIN;
12691
81b8709c 12692 switch (state) {
12693 case ETHTOOL_ID_ACTIVE:
fce55922 12694 return 1; /* cycle on/off once per second */
4009a93d 12695
81b8709c 12696 case ETHTOOL_ID_ON:
12697 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12698 LED_CTRL_1000MBPS_ON |
12699 LED_CTRL_100MBPS_ON |
12700 LED_CTRL_10MBPS_ON |
12701 LED_CTRL_TRAFFIC_OVERRIDE |
12702 LED_CTRL_TRAFFIC_BLINK |
12703 LED_CTRL_TRAFFIC_LED);
12704 break;
6aa20a22 12705
81b8709c 12706 case ETHTOOL_ID_OFF:
12707 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12708 LED_CTRL_TRAFFIC_OVERRIDE);
12709 break;
4009a93d 12710
81b8709c 12711 case ETHTOOL_ID_INACTIVE:
12712 tw32(MAC_LED_CTRL, tp->led_ctrl);
12713 break;
4009a93d 12714 }
81b8709c 12715
4009a93d
MC		 12716 return 0;
12717}
12718
de6f31eb 12719static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12720 struct ethtool_stats *estats, u64 *tmp_stats)
12721{
12722 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12723
b546e46f
MC		 12724 if (tp->hw_stats)
12725 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12726 else
12727 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12728}
12729
535a490e 12730static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12731{
12732 int i;
12733 __be32 *buf;
12734 u32 offset = 0, len = 0;
12735 u32 magic, val;
12736
63c3a66f 12737 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12738 return NULL;
12739
12740 if (magic == TG3_EEPROM_MAGIC) {
12741 for (offset = TG3_NVM_DIR_START;
12742 offset < TG3_NVM_DIR_END;
12743 offset += TG3_NVM_DIRENT_SIZE) {
12744 if (tg3_nvram_read(tp, offset, &val))
12745 return NULL;
12746
12747 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12748 TG3_NVM_DIRTYPE_EXTVPD)
12749 break;
12750 }
12751
12752 if (offset != TG3_NVM_DIR_END) {
12753 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12754 if (tg3_nvram_read(tp, offset + 4, &offset))
12755 return NULL;
12756
12757 offset = tg3_nvram_logical_addr(tp, offset);
12758 }
12759 }
12760
12761 if (!offset || !len) {
12762 offset = TG3_NVM_VPD_OFF;
12763 len = TG3_NVM_VPD_LEN;
12764 }
12765
12766 buf = kmalloc(len, GFP_KERNEL);
12767 if (buf == NULL)
12768 return NULL;
12769
12770 if (magic == TG3_EEPROM_MAGIC) {
12771 for (i = 0; i < len; i += 4) {
12772 /* The data is in little-endian format in NVRAM.
12773 * Use the big-endian read routines to preserve
12774 * the byte order as it exists in NVRAM.
12775 */
12776 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12777 goto error;
12778 }
12779 } else {
12780 u8 *ptr;
12781 ssize_t cnt;
12782 unsigned int pos = 0;
12783
12784 ptr = (u8 *)&buf[0];
12785 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12786 cnt = pci_read_vpd(tp->pdev, pos,
12787 len - pos, ptr);
12788 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12789 cnt = 0;
12790 else if (cnt < 0)
12791 goto error;
12792 }
12793 if (pos != len)
12794 goto error;
12795 }
12796
535a490e
MC		 12797 *vpdlen = len;
12798
c3e94500
MC		 12799 return buf;
12800
12801error:
12802 kfree(buf);
12803 return NULL;
12804}
12805
566f86ad 12806#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12807#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12808#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12809#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12810#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12811#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12812#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12813#define NVRAM_SELFBOOT_HW_SIZE 0x20
12814#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12815
12816static int tg3_test_nvram(struct tg3 *tp)
12817{
535a490e 12818 u32 csum, magic, len;
a9dc529d 12819 __be32 *buf;
ab0049b4 12820 int i, j, k, err = 0, size;
566f86ad 12821
63c3a66f 12822 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12823 return 0;
12824
e4f34110 12825 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12826 return -EIO;
12827
1b27777a
MC		 12828 if (magic == TG3_EEPROM_MAGIC)
12829 size = NVRAM_TEST_SIZE;
b16250e3 12830 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12831 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12832 TG3_EEPROM_SB_FORMAT_1) {
12833 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12834 case TG3_EEPROM_SB_REVISION_0:
12835 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12836 break;
12837 case TG3_EEPROM_SB_REVISION_2:
12838 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12839 break;
12840 case TG3_EEPROM_SB_REVISION_3:
12841 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12842 break;
727a6d9f
MC		 12843 case TG3_EEPROM_SB_REVISION_4:
12844 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12845 break;
12846 case TG3_EEPROM_SB_REVISION_5:
12847 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12848 break;
12849 case TG3_EEPROM_SB_REVISION_6:
12850 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12851 break;
a5767dec 12852 default:
727a6d9f 12853 return -EIO;
a5767dec
MC		 12854 }
12855 } else
1b27777a 12856 return 0;
b16250e3
MC		 12857 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12858 size = NVRAM_SELFBOOT_HW_SIZE;
12859 else
1b27777a
MC		 12860 return -EIO;
12861
12862 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12863 if (buf == NULL)
12864 return -ENOMEM;
12865
1b27777a
MC		 12866 err = -EIO;
12867 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12868 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12869 if (err)
566f86ad 12870 break;
566f86ad 12871 }
1b27777a 12872 if (i < size)
566f86ad
MC		 12873 goto out;
12874
1b27777a 12875 /* Selfboot format */
a9dc529d 12876 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12877 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12878 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12879 u8 *buf8 = (u8 *) buf, csum8 = 0;
12880
b9fc7dc5 12881 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12882 TG3_EEPROM_SB_REVISION_2) {
12883 /* For rev 2, the csum doesn't include the MBA. */
12884 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12885 csum8 += buf8[i];
12886 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12887 csum8 += buf8[i];
12888 } else {
12889 for (i = 0; i < size; i++)
12890 csum8 += buf8[i];
12891 }
1b27777a 12892
ad96b485
AB		 12893 if (csum8 == 0) {
12894 err = 0;
12895 goto out;
12896 }
12897
12898 err = -EIO;
12899 goto out;
1b27777a 12900 }
566f86ad 12901
b9fc7dc5 12902 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12903 TG3_EEPROM_MAGIC_HW) {
12904 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12905 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12906 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12907
12908 /* Separate the parity bits and the data bytes. */
12909 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12910 if ((i == 0) || (i == 8)) {
12911 int l;
12912 u8 msk;
12913
12914 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12915 parity[k++] = buf8[i] & msk;
12916 i++;
859a5887 12917 } else if (i == 16) {
b16250e3
MC		 12918 int l;
12919 u8 msk;
12920
12921 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12922 parity[k++] = buf8[i] & msk;
12923 i++;
12924
12925 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12926 parity[k++] = buf8[i] & msk;
12927 i++;
12928 }
12929 data[j++] = buf8[i];
12930 }
12931
12932 err = -EIO;
12933 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12934 u8 hw8 = hweight8(data[i]);
12935
12936 if ((hw8 & 0x1) && parity[i])
12937 goto out;
12938 else if (!(hw8 & 0x1) && !parity[i])
12939 goto out;
12940 }
12941 err = 0;
12942 goto out;
12943 }
12944
01c3a392
MC		 12945 err = -EIO;
12946
566f86ad
MC		 12947 /* Bootstrap checksum at offset 0x10 */
12948 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12949 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12950 goto out;
12951
12952 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12953 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12954 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12955 goto out;
566f86ad 12956
c3e94500
MC		 12957 kfree(buf);
12958
535a490e 12959 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12960 if (!buf)
12961 return -ENOMEM;
d4894f3e 12962
535a490e 12963 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12964 if (i > 0) {
12965 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12966 if (j < 0)
12967 goto out;
12968
535a490e 12969 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12970 goto out;
12971
12972 i += PCI_VPD_LRDT_TAG_SIZE;
12973 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12974 PCI_VPD_RO_KEYWORD_CHKSUM);
12975 if (j > 0) {
12976 u8 csum8 = 0;
12977
12978 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12979
12980 for (i = 0; i <= j; i++)
12981 csum8 += ((u8 *)buf)[i];
12982
12983 if (csum8)
12984 goto out;
12985 }
12986 }
12987
566f86ad
MC		 12988 err = 0;
12989
12990out:
12991 kfree(buf);
12992 return err;
12993}
12994
ca43007a
MC		 12995#define TG3_SERDES_TIMEOUT_SEC 2
12996#define TG3_COPPER_TIMEOUT_SEC 6
12997
12998static int tg3_test_link(struct tg3 *tp)
12999{
13000 int i, max;
13001
13002 if (!netif_running(tp->dev))
13003 return -ENODEV;
13004
f07e9af3 13005 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 13006 max = TG3_SERDES_TIMEOUT_SEC;
13007 else
13008 max = TG3_COPPER_TIMEOUT_SEC;
13009
13010 for (i = 0; i < max; i++) {
f4a46d1f 13011 if (tp->link_up)
ca43007a
MC		 13012 return 0;
13013
13014 if (msleep_interruptible(1000))
13015 break;
13016 }
13017
13018 return -EIO;
13019}
13020
a71116d1 13021/* Only test the commonly used registers */
30ca3e37 13022static int tg3_test_registers(struct tg3 *tp)
a71116d1 13023{
b16250e3 13024 int i, is_5705, is_5750;
a71116d1
MC		 13025 u32 offset, read_mask, write_mask, val, save_val, read_val;
13026 static struct {
13027 u16 offset;
13028 u16 flags;
13029#define TG3_FL_5705 0x1
13030#define TG3_FL_NOT_5705 0x2
13031#define TG3_FL_NOT_5788 0x4
b16250e3 13032#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 13033 u32 read_mask;
13034 u32 write_mask;
13035 } reg_tbl[] = {
13036 /* MAC Control Registers */
13037 { MAC_MODE, TG3_FL_NOT_5705,
13038 0x00000000, 0x00ef6f8c },
13039 { MAC_MODE, TG3_FL_5705,
13040 0x00000000, 0x01ef6b8c },
13041 { MAC_STATUS, TG3_FL_NOT_5705,
13042 0x03800107, 0x00000000 },
13043 { MAC_STATUS, TG3_FL_5705,
13044 0x03800100, 0x00000000 },
13045 { MAC_ADDR_0_HIGH, 0x0000,
13046 0x00000000, 0x0000ffff },
13047 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 13048 0x00000000, 0xffffffff },
a71116d1
MC		 13049 { MAC_RX_MTU_SIZE, 0x0000,
13050 0x00000000, 0x0000ffff },
13051 { MAC_TX_MODE, 0x0000,
13052 0x00000000, 0x00000070 },
13053 { MAC_TX_LENGTHS, 0x0000,
13054 0x00000000, 0x00003fff },
13055 { MAC_RX_MODE, TG3_FL_NOT_5705,
13056 0x00000000, 0x000007fc },
13057 { MAC_RX_MODE, TG3_FL_5705,
13058 0x00000000, 0x000007dc },
13059 { MAC_HASH_REG_0, 0x0000,
13060 0x00000000, 0xffffffff },
13061 { MAC_HASH_REG_1, 0x0000,
13062 0x00000000, 0xffffffff },
13063 { MAC_HASH_REG_2, 0x0000,
13064 0x00000000, 0xffffffff },
13065 { MAC_HASH_REG_3, 0x0000,
13066 0x00000000, 0xffffffff },
13067
13068 /* Receive Data and Receive BD Initiator Control Registers. */
13069 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13070 0x00000000, 0xffffffff },
13071 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13072 0x00000000, 0xffffffff },
13073 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13074 0x00000000, 0x00000003 },
13075 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13076 0x00000000, 0xffffffff },
13077 { RCVDBDI_STD_BD+0, 0x0000,
13078 0x00000000, 0xffffffff },
13079 { RCVDBDI_STD_BD+4, 0x0000,
13080 0x00000000, 0xffffffff },
13081 { RCVDBDI_STD_BD+8, 0x0000,
13082 0x00000000, 0xffff0002 },
13083 { RCVDBDI_STD_BD+0xc, 0x0000,
13084 0x00000000, 0xffffffff },
6aa20a22 13085
a71116d1
MC		 13086 /* Receive BD Initiator Control Registers. */
13087 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13088 0x00000000, 0xffffffff },
13089 { RCVBDI_STD_THRESH, TG3_FL_5705,
13090 0x00000000, 0x000003ff },
13091 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13092 0x00000000, 0xffffffff },
6aa20a22 13093
a71116d1
MC		 13094 /* Host Coalescing Control Registers. */
13095 { HOSTCC_MODE, TG3_FL_NOT_5705,
13096 0x00000000, 0x00000004 },
13097 { HOSTCC_MODE, TG3_FL_5705,
13098 0x00000000, 0x000000f6 },
13099 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13100 0x00000000, 0xffffffff },
13101 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13102 0x00000000, 0x000003ff },
13103 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13104 0x00000000, 0xffffffff },
13105 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13106 0x00000000, 0x000003ff },
13107 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13108 0x00000000, 0xffffffff },
13109 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13110 0x00000000, 0x000000ff },
13111 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13112 0x00000000, 0xffffffff },
13113 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13114 0x00000000, 0x000000ff },
13115 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13116 0x00000000, 0xffffffff },
13117 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13118 0x00000000, 0xffffffff },
13119 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13120 0x00000000, 0xffffffff },
13121 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13122 0x00000000, 0x000000ff },
13123 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13124 0x00000000, 0xffffffff },
13125 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13126 0x00000000, 0x000000ff },
13127 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13128 0x00000000, 0xffffffff },
13129 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13130 0x00000000, 0xffffffff },
13131 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13132 0x00000000, 0xffffffff },
13133 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13134 0x00000000, 0xffffffff },
13135 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13136 0x00000000, 0xffffffff },
13137 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13138 0xffffffff, 0x00000000 },
13139 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13140 0xffffffff, 0x00000000 },
13141
13142 /* Buffer Manager Control Registers. */
b16250e3 13143 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 13144 0x00000000, 0x007fff80 },
b16250e3 13145 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 13146 0x00000000, 0x007fffff },
13147 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13148 0x00000000, 0x0000003f },
13149 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13150 0x00000000, 0x000001ff },
13151 { BUFMGR_MB_HIGH_WATER, 0x0000,
13152 0x00000000, 0x000001ff },
13153 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13154 0xffffffff, 0x00000000 },
13155 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13156 0xffffffff, 0x00000000 },
6aa20a22 13157
a71116d1
MC		 13158 /* Mailbox Registers */
13159 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13160 0x00000000, 0x000001ff },
13161 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13162 0x00000000, 0x000001ff },
13163 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13164 0x00000000, 0x000007ff },
13165 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13166 0x00000000, 0x000001ff },
13167
13168 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13169 };
13170
b16250e3 13171 is_5705 = is_5750 = 0;
63c3a66f 13172 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 13173 is_5705 = 1;
63c3a66f 13174 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 13175 is_5750 = 1;
13176 }
a71116d1
MC		 13177
13178 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13179 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13180 continue;
13181
13182 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13183 continue;
13184
63c3a66f 13185 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 13186 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13187 continue;
13188
b16250e3
MC		 13189 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13190 continue;
13191
a71116d1
MC		 13192 offset = (u32) reg_tbl[i].offset;
13193 read_mask = reg_tbl[i].read_mask;
13194 write_mask = reg_tbl[i].write_mask;
13195
13196 /* Save the original register content */
13197 save_val = tr32(offset);
13198
13199 /* Determine the read-only value. */
13200 read_val = save_val & read_mask;
13201
13202 /* Write zero to the register, then make sure the read-only bits
13203 * are not changed and the read/write bits are all zeros.
13204 */
13205 tw32(offset, 0);
13206
13207 val = tr32(offset);
13208
13209 /* Test the read-only and read/write bits. */
13210 if (((val & read_mask) != read_val) || (val & write_mask))
13211 goto out;
13212
13213 /* Write ones to all the bits defined by RdMask and WrMask, then
13214 * make sure the read-only bits are not changed and the
13215 * read/write bits are all ones.
13216 */
13217 tw32(offset, read_mask | write_mask);
13218
13219 val = tr32(offset);
13220
13221 /* Test the read-only bits. */
13222 if ((val & read_mask) != read_val)
13223 goto out;
13224
13225 /* Test the read/write bits. */
13226 if ((val & write_mask) != write_mask)
13227 goto out;
13228
13229 tw32(offset, save_val);
13230 }
13231
13232 return 0;
13233
13234out:
9f88f29f 13235 if (netif_msg_hw(tp))
2445e461
MC		 13236 netdev_err(tp->dev,
13237 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13238 tw32(offset, save_val);
13239 return -EIO;
13240}
13241
7942e1db
MC		 13242static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13243{
f71e1309 13244 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13245 int i;
13246 u32 j;
13247
e9edda69 13248 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13249 for (j = 0; j < len; j += 4) {
13250 u32 val;
13251
13252 tg3_write_mem(tp, offset + j, test_pattern[i]);
13253 tg3_read_mem(tp, offset + j, &val);
13254 if (val != test_pattern[i])
13255 return -EIO;
13256 }
13257 }
13258 return 0;
13259}
13260
13261static int tg3_test_memory(struct tg3 *tp)
13262{
13263 static struct mem_entry {
13264 u32 offset;
13265 u32 len;
13266 } mem_tbl_570x[] = {
38690194 13267 { 0x00000000, 0x00b50},
7942e1db
MC		 13268 { 0x00002000, 0x1c000},
13269 { 0xffffffff, 0x00000}
13270 }, mem_tbl_5705[] = {
13271 { 0x00000100, 0x0000c},
13272 { 0x00000200, 0x00008},
7942e1db
MC		 13273 { 0x00004000, 0x00800},
13274 { 0x00006000, 0x01000},
13275 { 0x00008000, 0x02000},
13276 { 0x00010000, 0x0e000},
13277 { 0xffffffff, 0x00000}
79f4d13a
MC		 13278 }, mem_tbl_5755[] = {
13279 { 0x00000200, 0x00008},
13280 { 0x00004000, 0x00800},
13281 { 0x00006000, 0x00800},
13282 { 0x00008000, 0x02000},
13283 { 0x00010000, 0x0c000},
13284 { 0xffffffff, 0x00000}
b16250e3
MC		 13285 }, mem_tbl_5906[] = {
13286 { 0x00000200, 0x00008},
13287 { 0x00004000, 0x00400},
13288 { 0x00006000, 0x00400},
13289 { 0x00008000, 0x01000},
13290 { 0x00010000, 0x01000},
13291 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13292 }, mem_tbl_5717[] = {
13293 { 0x00000200, 0x00008},
13294 { 0x00010000, 0x0a000},
13295 { 0x00020000, 0x13c00},
13296 { 0xffffffff, 0x00000}
13297 }, mem_tbl_57765[] = {
13298 { 0x00000200, 0x00008},
13299 { 0x00004000, 0x00800},
13300 { 0x00006000, 0x09800},
13301 { 0x00010000, 0x0a000},
13302 { 0xffffffff, 0x00000}
7942e1db
MC		 13303 };
13304 struct mem_entry *mem_tbl;
13305 int err = 0;
13306 int i;
13307
63c3a66f 13308 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13309 mem_tbl = mem_tbl_5717;
c65a17f4 13310 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13311 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13312 mem_tbl = mem_tbl_57765;
63c3a66f 13313 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13314 mem_tbl = mem_tbl_5755;
4153577a 13315 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13316 mem_tbl = mem_tbl_5906;
63c3a66f 13317 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13318 mem_tbl = mem_tbl_5705;
13319 else
7942e1db
MC		 13320 mem_tbl = mem_tbl_570x;
13321
13322 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13323 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13324 if (err)
7942e1db
MC		 13325 break;
13326 }
6aa20a22 13327
7942e1db
MC		 13328 return err;
13329}
13330
bb158d69
MC		 13331#define TG3_TSO_MSS 500
13332
13333#define TG3_TSO_IP_HDR_LEN 20
13334#define TG3_TSO_TCP_HDR_LEN 20
13335#define TG3_TSO_TCP_OPT_LEN 12
13336
13337static const u8 tg3_tso_header[] = {
133380x08, 0x00,
133390x45, 0x00, 0x00, 0x00,
133400x00, 0x00, 0x40, 0x00,
133410x40, 0x06, 0x00, 0x00,
133420x0a, 0x00, 0x00, 0x01,
133430x0a, 0x00, 0x00, 0x02,
133440x0d, 0x00, 0xe0, 0x00,
133450x00, 0x00, 0x01, 0x00,
133460x00, 0x00, 0x02, 0x00,
133470x80, 0x10, 0x10, 0x00,
133480x14, 0x09, 0x00, 0x00,
133490x01, 0x01, 0x08, 0x0a,
133500x11, 0x11, 0x11, 0x11,
133510x11, 0x11, 0x11, 0x11,
13352};
9f40dead 13353
28a45957 13354static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13355{
5e5a7f37 13356 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13357 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13358 u32 budget;
9205fd9c
ED		 13359 struct sk_buff *skb;
13360 u8 *tx_data, *rx_data;
c76949a6
MC		 13361 dma_addr_t map;
13362 int num_pkts, tx_len, rx_len, i, err;
13363 struct tg3_rx_buffer_desc *desc;
898a56f8 13364 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13365 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13366
c8873405
MC		 13367 tnapi = &tp->napi[0];
13368 rnapi = &tp->napi[0];
0c1d0e2b 13369 if (tp->irq_cnt > 1) {
63c3a66f 13370 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13371 rnapi = &tp->napi[1];
63c3a66f 13372 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13373 tnapi = &tp->napi[1];
0c1d0e2b 13374 }
fd2ce37f 13375 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13376
c76949a6
MC		 13377 err = -EIO;
13378
4852a861 13379 tx_len = pktsz;
a20e9c62 13380 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13381 if (!skb)
13382 return -ENOMEM;
13383
c76949a6 13384 tx_data = skb_put(skb, tx_len);
d458cdf7
JP		 13385 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13386 memset(tx_data + ETH_ALEN, 0x0, 8);
c76949a6 13387
4852a861 13388 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13389
28a45957 13390 if (tso_loopback) {
bb158d69
MC		 13391 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13392
13393 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13394 TG3_TSO_TCP_OPT_LEN;
13395
13396 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13397 sizeof(tg3_tso_header));
13398 mss = TG3_TSO_MSS;
13399
13400 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13401 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13402
13403 /* Set the total length field in the IP header */
13404 iph->tot_len = htons((u16)(mss + hdr_len));
13405
13406 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13407 TXD_FLAG_CPU_POST_DMA);
13408
63c3a66f
JP		 13409 if (tg3_flag(tp, HW_TSO_1) ||
13410 tg3_flag(tp, HW_TSO_2) ||
13411 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13412 struct tcphdr *th;
13413 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13414 th = (struct tcphdr *)&tx_data[val];
13415 th->check = 0;
13416 } else
13417 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13418
63c3a66f 13419 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13420 mss |= (hdr_len & 0xc) << 12;
13421 if (hdr_len & 0x10)
13422 base_flags |= 0x00000010;
13423 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13424 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13425 mss |= hdr_len << 9;
63c3a66f 13426 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13427 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13428 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13429 } else {
13430 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13431 }
13432
13433 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13434 } else {
13435 num_pkts = 1;
13436 data_off = ETH_HLEN;
c441b456
MC		 13437
13438 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13439 tx_len > VLAN_ETH_FRAME_LEN)
13440 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13441 }
13442
13443 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13444 tx_data[i] = (u8) (i & 0xff);
13445
f4188d8a
AD		 13446 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13447 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13448 dev_kfree_skb(skb);
13449 return -EIO;
13450 }
c76949a6 13451
0d681b27
MC		 13452 val = tnapi->tx_prod;
13453 tnapi->tx_buffers[val].skb = skb;
13454 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13455
c76949a6 13456 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13457 rnapi->coal_now);
c76949a6
MC		 13458
13459 udelay(10);
13460
898a56f8 13461 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13462
84b67b27
MC		 13463 budget = tg3_tx_avail(tnapi);
13464 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13465 base_flags | TXD_FLAG_END, mss, 0)) {
13466 tnapi->tx_buffers[val].skb = NULL;
13467 dev_kfree_skb(skb);
13468 return -EIO;
13469 }
c76949a6 13470
f3f3f27e 13471 tnapi->tx_prod++;
c76949a6 13472
6541b806
MC		 13473 /* Sync BD data before updating mailbox */
13474 wmb();
13475
f3f3f27e
MC		 13476 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13477 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13478
13479 udelay(10);
13480
303fc921
MC		 13481 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13482 for (i = 0; i < 35; i++) {
c76949a6 13483 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13484 coal_now);
c76949a6
MC		 13485
13486 udelay(10);
13487
898a56f8
MC		 13488 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13489 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13490 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13491 (rx_idx == (rx_start_idx + num_pkts)))
13492 break;
13493 }
13494
ba1142e4 13495 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13496 dev_kfree_skb(skb);
13497
f3f3f27e 13498 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13499 goto out;
13500
13501 if (rx_idx != rx_start_idx + num_pkts)
13502 goto out;
13503
bb158d69
MC		 13504 val = data_off;
13505 while (rx_idx != rx_start_idx) {
13506 desc = &rnapi->rx_rcb[rx_start_idx++];
13507 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13508 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13509
bb158d69
MC		 13510 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13511 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13512 goto out;
c76949a6 13513
bb158d69
MC		 13514 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13515 - ETH_FCS_LEN;
c76949a6 13516
28a45957 13517 if (!tso_loopback) {
bb158d69
MC		 13518 if (rx_len != tx_len)
13519 goto out;
4852a861 13520
bb158d69
MC		 13521 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13522 if (opaque_key != RXD_OPAQUE_RING_STD)
13523 goto out;
13524 } else {
13525 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13526 goto out;
13527 }
13528 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13529 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13530 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13531 goto out;
bb158d69 13532 }
4852a861 13533
bb158d69 13534 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13535 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13536 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13537 mapping);
13538 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13539 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13540 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13541 mapping);
13542 } else
13543 goto out;
c76949a6 13544
bb158d69
MC		 13545 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13546 PCI_DMA_FROMDEVICE);
c76949a6 13547
9205fd9c 13548 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13549 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13550 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13551 goto out;
13552 }
c76949a6 13553 }
bb158d69 13554
c76949a6 13555 err = 0;
6aa20a22 13556
9205fd9c 13557 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13558out:
13559 return err;
13560}
13561
00c266b7
MC		 13562#define TG3_STD_LOOPBACK_FAILED 1
13563#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13564#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13565#define TG3_LOOPBACK_FAILED \
13566 (TG3_STD_LOOPBACK_FAILED | \
13567 TG3_JMB_LOOPBACK_FAILED | \
13568 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13569
941ec90f 13570static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13571{
28a45957 13572 int err = -EIO;
2215e24c 13573 u32 eee_cap;
c441b456
MC		 13574 u32 jmb_pkt_sz = 9000;
13575
13576 if (tp->dma_limit)
13577 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13578
ab789046
MC		 13579 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13580 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13581
28a45957 13582 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13583 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13584 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13585 if (do_extlpbk)
93df8b8f 13586 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13587 goto done;
13588 }
13589
953c96e0 13590 err = tg3_reset_hw(tp, true);
ab789046 13591 if (err) {
93df8b8f
NNS		 13592 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13593 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13594 if (do_extlpbk)
93df8b8f 13595 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13596 goto done;
13597 }
9f40dead 13598
63c3a66f 13599 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13600 int i;
13601
13602 /* Reroute all rx packets to the 1st queue */
13603 for (i = MAC_RSS_INDIR_TBL_0;
13604 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13605 tw32(i, 0x0);
13606 }
13607
6e01b20b
MC		 13608 /* HW errata - mac loopback fails in some cases on 5780.
13609 * Normal traffic and PHY loopback are not affected by
13610 * errata. Also, the MAC loopback test is deprecated for
13611 * all newer ASIC revisions.
13612 */
4153577a 13613 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13614 !tg3_flag(tp, CPMU_PRESENT)) {
13615 tg3_mac_loopback(tp, true);
9936bcf6 13616
28a45957 13617 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13618 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13619
13620 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13621 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13622 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13623
13624 tg3_mac_loopback(tp, false);
13625 }
4852a861 13626
f07e9af3 13627 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13628 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13629 int i;
13630
941ec90f 13631 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13632
13633 /* Wait for link */
13634 for (i = 0; i < 100; i++) {
13635 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13636 break;
13637 mdelay(1);
13638 }
13639
28a45957 13640 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13641 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13642 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13643 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13644 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13645 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13646 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13647 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13648
941ec90f
MC		 13649 if (do_extlpbk) {
13650 tg3_phy_lpbk_set(tp, 0, true);
13651
13652 /* All link indications report up, but the hardware
13653 * isn't really ready for about 20 msec. Double it
13654 * to be sure.
13655 */
13656 mdelay(40);
13657
13658 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13659 data[TG3_EXT_LOOPB_TEST] |=
13660 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13661 if (tg3_flag(tp, TSO_CAPABLE) &&
13662 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13663 data[TG3_EXT_LOOPB_TEST] |=
13664 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13665 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13666 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13667 data[TG3_EXT_LOOPB_TEST] |=
13668 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13669 }
13670
5e5a7f37
MC		 13671 /* Re-enable gphy autopowerdown. */
13672 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13673 tg3_phy_toggle_apd(tp, true);
13674 }
6833c043 13675
93df8b8f
NNS		 13676 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13677 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13678
ab789046
MC		 13679done:
13680 tp->phy_flags |= eee_cap;
13681
9f40dead
MC		 13682 return err;
13683}
13684
4cafd3f5
MC		 13685static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13686 u64 *data)
13687{
566f86ad 13688 struct tg3 *tp = netdev_priv(dev);
941ec90f 13689 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13690
2e460fc0
NS		 13691 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13692 if (tg3_power_up(tp)) {
13693 etest->flags |= ETH_TEST_FL_FAILED;
13694 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13695 return;
13696 }
13697 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13698 }
bc1c7567 13699
566f86ad
MC		 13700 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13701
13702 if (tg3_test_nvram(tp) != 0) {
13703 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13704 data[TG3_NVRAM_TEST] = 1;
566f86ad 13705 }
941ec90f 13706 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13707 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13708 data[TG3_LINK_TEST] = 1;
ca43007a 13709 }
a71116d1 13710 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13711 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13712
13713 if (netif_running(dev)) {
b02fd9e3 13714 tg3_phy_stop(tp);
a71116d1 13715 tg3_netif_stop(tp);
bbe832c0
MC		 13716 irq_sync = 1;
13717 }
a71116d1 13718
bbe832c0 13719 tg3_full_lock(tp, irq_sync);
a71116d1 13720 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13721 err = tg3_nvram_lock(tp);
a71116d1 13722 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13723 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13724 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13725 if (!err)
13726 tg3_nvram_unlock(tp);
a71116d1 13727
f07e9af3 13728 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13729 tg3_phy_reset(tp);
13730
a71116d1
MC		 13731 if (tg3_test_registers(tp) != 0) {
13732 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13733 data[TG3_REGISTER_TEST] = 1;
a71116d1 13734 }
28a45957 13735
7942e1db
MC		 13736 if (tg3_test_memory(tp) != 0) {
13737 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13738 data[TG3_MEMORY_TEST] = 1;
7942e1db 13739 }
28a45957 13740
941ec90f
MC		 13741 if (doextlpbk)
13742 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13743
93df8b8f 13744 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13745 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13746
f47c11ee
DM		 13747 tg3_full_unlock(tp);
13748
d4bc3927
MC		 13749 if (tg3_test_interrupt(tp) != 0) {
13750 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13751 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13752 }
f47c11ee
DM		 13753
13754 tg3_full_lock(tp, 0);
d4bc3927 13755
a71116d1
MC		 13756 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13757 if (netif_running(dev)) {
63c3a66f 13758 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13759 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13760 if (!err2)
b9ec6c1b 13761 tg3_netif_start(tp);
a71116d1 13762 }
f47c11ee
DM		 13763
13764 tg3_full_unlock(tp);
b02fd9e3
MC		 13765
13766 if (irq_sync && !err2)
13767 tg3_phy_start(tp);
a71116d1 13768 }
80096068 13769 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13770 tg3_power_down_prepare(tp);
bc1c7567 13771
4cafd3f5
MC		 13772}
13773
7260899b 13774static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
0a633ac2
MC		 13775{
13776 struct tg3 *tp = netdev_priv(dev);
13777 struct hwtstamp_config stmpconf;
13778
13779 if (!tg3_flag(tp, PTP_CAPABLE))
7260899b 13780 return -EOPNOTSUPP;
0a633ac2
MC		 13781
13782 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13783 return -EFAULT;
13784
13785 if (stmpconf.flags)
13786 return -EINVAL;
13787
58b187c6
BH		 13788 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13789 stmpconf.tx_type != HWTSTAMP_TX_OFF)
0a633ac2 13790 return -ERANGE;
0a633ac2
MC		 13791
13792 switch (stmpconf.rx_filter) {
13793 case HWTSTAMP_FILTER_NONE:
13794 tp->rxptpctl = 0;
13795 break;
13796 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13797 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13798 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13799 break;
13800 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13801 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13802 TG3_RX_PTP_CTL_SYNC_EVNT;
13803 break;
13804 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13805 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13806 TG3_RX_PTP_CTL_DELAY_REQ;
13807 break;
13808 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13809 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13810 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13811 break;
13812 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13813 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13814 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13815 break;
13816 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13817 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13818 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13819 break;
13820 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13821 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13822 TG3_RX_PTP_CTL_SYNC_EVNT;
13823 break;
13824 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13825 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13826 TG3_RX_PTP_CTL_SYNC_EVNT;
13827 break;
13828 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13829 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13830 TG3_RX_PTP_CTL_SYNC_EVNT;
13831 break;
13832 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13833 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13834 TG3_RX_PTP_CTL_DELAY_REQ;
13835 break;
13836 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13837 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13838 TG3_RX_PTP_CTL_DELAY_REQ;
13839 break;
13840 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13841 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13842 TG3_RX_PTP_CTL_DELAY_REQ;
13843 break;
13844 default:
13845 return -ERANGE;
13846 }
13847
13848 if (netif_running(dev) && tp->rxptpctl)
13849 tw32(TG3_RX_PTP_CTL,
13850 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13851
58b187c6
BH		 13852 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13853 tg3_flag_set(tp, TX_TSTAMP_EN);
13854 else
13855 tg3_flag_clear(tp, TX_TSTAMP_EN);
13856
0a633ac2
MC		 13857 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13858 -EFAULT : 0;
13859}
13860
7260899b
BH		 13861static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13862{
13863 struct tg3 *tp = netdev_priv(dev);
13864 struct hwtstamp_config stmpconf;
13865
13866 if (!tg3_flag(tp, PTP_CAPABLE))
13867 return -EOPNOTSUPP;
13868
13869 stmpconf.flags = 0;
13870 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13871 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13872
13873 switch (tp->rxptpctl) {
13874 case 0:
13875 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13876 break;
13877 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13878 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13879 break;
13880 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13881 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13882 break;
13883 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13884 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13885 break;
13886 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13887 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13888 break;
13889 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13890 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13891 break;
13892 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13893 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13894 break;
13895 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13896 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13897 break;
13898 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13899 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13900 break;
13901 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13902 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13903 break;
13904 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13905 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13906 break;
13907 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13908 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13909 break;
13910 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13911 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13912 break;
13913 default:
13914 WARN_ON_ONCE(1);
13915 return -ERANGE;
13916 }
13917
13918 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13919 -EFAULT : 0;
13920}
13921
1da177e4
LT		 13922static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13923{
13924 struct mii_ioctl_data *data = if_mii(ifr);
13925 struct tg3 *tp = netdev_priv(dev);
13926 int err;
13927
63c3a66f 13928 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13929 struct phy_device *phydev;
f07e9af3 13930 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13931 return -EAGAIN;
ead2402c 13932 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
28b04113 13933 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13934 }
13935
33f401ae 13936 switch (cmd) {
1da177e4 13937 case SIOCGMIIPHY:
882e9793 13938 data->phy_id = tp->phy_addr;
1da177e4
LT		 13939
13940 /* fallthru */
13941 case SIOCGMIIREG: {
13942 u32 mii_regval;
13943
f07e9af3 13944 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13945 break; /* We have no PHY */
13946
34eea5ac 13947 if (!netif_running(dev))
bc1c7567
MC		 13948 return -EAGAIN;
13949
f47c11ee 13950 spin_lock_bh(&tp->lock);
5c358045
HM		 13951 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13952 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13953 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13954
13955 data->val_out = mii_regval;
13956
13957 return err;
13958 }
13959
13960 case SIOCSMIIREG:
f07e9af3 13961 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13962 break; /* We have no PHY */
13963
34eea5ac 13964 if (!netif_running(dev))
bc1c7567
MC		 13965 return -EAGAIN;
13966
f47c11ee 13967 spin_lock_bh(&tp->lock);
5c358045
HM		 13968 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13969 data->reg_num & 0x1f, data->val_in);
f47c11ee 13970 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13971
13972 return err;
13973
0a633ac2 13974 case SIOCSHWTSTAMP:
7260899b
BH		 13975 return tg3_hwtstamp_set(dev, ifr);
13976
13977 case SIOCGHWTSTAMP:
13978 return tg3_hwtstamp_get(dev, ifr);
0a633ac2 13979
1da177e4
LT		 13980 default:
13981 /* do nothing */
13982 break;
13983 }
13984 return -EOPNOTSUPP;
13985}
13986
15f9850d
DM		 13987static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13988{
13989 struct tg3 *tp = netdev_priv(dev);
13990
13991 memcpy(ec, &tp->coal, sizeof(*ec));
13992 return 0;
13993}
13994
d244c892
MC		 13995static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13996{
13997 struct tg3 *tp = netdev_priv(dev);
13998 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13999 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
14000
63c3a66f 14001 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 14002 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
14003 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
14004 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
14005 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
14006 }
14007
14008 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
14009 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
14010 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
14011 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
14012 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
14013 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
14014 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
14015 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
14016 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
14017 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
14018 return -EINVAL;
14019
14020 /* No rx interrupts will be generated if both are zero */
14021 if ((ec->rx_coalesce_usecs == 0) &&
14022 (ec->rx_max_coalesced_frames == 0))
14023 return -EINVAL;
14024
14025 /* No tx interrupts will be generated if both are zero */
14026 if ((ec->tx_coalesce_usecs == 0) &&
14027 (ec->tx_max_coalesced_frames == 0))
14028 return -EINVAL;
14029
14030 /* Only copy relevant parameters, ignore all others. */
14031 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14032 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14033 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14034 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14035 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14036 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14037 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14038 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14039 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14040
14041 if (netif_running(dev)) {
14042 tg3_full_lock(tp, 0);
14043 __tg3_set_coalesce(tp, &tp->coal);
14044 tg3_full_unlock(tp);
14045 }
14046 return 0;
14047}
14048
1cbf9eb8
NS		 14049static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14050{
14051 struct tg3 *tp = netdev_priv(dev);
14052
14053 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14054 netdev_warn(tp->dev, "Board does not support EEE!\n");
14055 return -EOPNOTSUPP;
14056 }
14057
14058 if (edata->advertised != tp->eee.advertised) {
14059 netdev_warn(tp->dev,
14060 "Direct manipulation of EEE advertisement is not supported\n");
14061 return -EINVAL;
14062 }
14063
14064 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14065 netdev_warn(tp->dev,
14066 "Maximal Tx Lpi timer supported is %#x(u)\n",
14067 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14068 return -EINVAL;
14069 }
14070
14071 tp->eee = *edata;
14072
14073 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14074 tg3_warn_mgmt_link_flap(tp);
14075
14076 if (netif_running(tp->dev)) {
14077 tg3_full_lock(tp, 0);
14078 tg3_setup_eee(tp);
14079 tg3_phy_reset(tp);
14080 tg3_full_unlock(tp);
14081 }
14082
14083 return 0;
14084}
14085
14086static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14087{
14088 struct tg3 *tp = netdev_priv(dev);
14089
14090 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14091 netdev_warn(tp->dev,
14092 "Board does not support EEE!\n");
14093 return -EOPNOTSUPP;
14094 }
14095
14096 *edata = tp->eee;
14097 return 0;
14098}
14099
7282d491 14100static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 14101 .get_settings = tg3_get_settings,
14102 .set_settings = tg3_set_settings,
14103 .get_drvinfo = tg3_get_drvinfo,
14104 .get_regs_len = tg3_get_regs_len,
14105 .get_regs = tg3_get_regs,
14106 .get_wol = tg3_get_wol,
14107 .set_wol = tg3_set_wol,
14108 .get_msglevel = tg3_get_msglevel,
14109 .set_msglevel = tg3_set_msglevel,
14110 .nway_reset = tg3_nway_reset,
14111 .get_link = ethtool_op_get_link,
14112 .get_eeprom_len = tg3_get_eeprom_len,
14113 .get_eeprom = tg3_get_eeprom,
14114 .set_eeprom = tg3_set_eeprom,
14115 .get_ringparam = tg3_get_ringparam,
14116 .set_ringparam = tg3_set_ringparam,
14117 .get_pauseparam = tg3_get_pauseparam,
14118 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 14119 .self_test = tg3_self_test,
1da177e4 14120 .get_strings = tg3_get_strings,
81b8709c 14121 .set_phys_id = tg3_set_phys_id,
1da177e4 14122 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 14123 .get_coalesce = tg3_get_coalesce,
d244c892 14124 .set_coalesce = tg3_set_coalesce,
b9f2c044 14125 .get_sset_count = tg3_get_sset_count,
90415477
MC		 14126 .get_rxnfc = tg3_get_rxnfc,
14127 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
fe62d001
BH		 14128 .get_rxfh = tg3_get_rxfh,
14129 .set_rxfh = tg3_set_rxfh,
0968169c
MC		 14130 .get_channels = tg3_get_channels,
14131 .set_channels = tg3_set_channels,
7d41e49a 14132 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 14133 .get_eee = tg3_get_eee,
14134 .set_eee = tg3_set_eee,
1da177e4
LT		 14135};
14136
b4017c53
DM		 14137static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14138 struct rtnl_link_stats64 *stats)
14139{
14140 struct tg3 *tp = netdev_priv(dev);
14141
0f566b20
MC		 14142 spin_lock_bh(&tp->lock);
14143 if (!tp->hw_stats) {
7b31b4de 14144 *stats = tp->net_stats_prev;
0f566b20 14145 spin_unlock_bh(&tp->lock);
7b31b4de 14146 return stats;
0f566b20 14147 }
b4017c53 14148
b4017c53
DM		 14149 tg3_get_nstats(tp, stats);
14150 spin_unlock_bh(&tp->lock);
14151
14152 return stats;
14153}
14154
ccd5ba9d
MC		 14155static void tg3_set_rx_mode(struct net_device *dev)
14156{
14157 struct tg3 *tp = netdev_priv(dev);
14158
14159 if (!netif_running(dev))
14160 return;
14161
14162 tg3_full_lock(tp, 0);
14163 __tg3_set_rx_mode(dev);
14164 tg3_full_unlock(tp);
14165}
14166
faf1627a
MC		 14167static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14168 int new_mtu)
14169{
14170 dev->mtu = new_mtu;
14171
14172 if (new_mtu > ETH_DATA_LEN) {
14173 if (tg3_flag(tp, 5780_CLASS)) {
14174 netdev_update_features(dev);
14175 tg3_flag_clear(tp, TSO_CAPABLE);
14176 } else {
14177 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14178 }
14179 } else {
14180 if (tg3_flag(tp, 5780_CLASS)) {
14181 tg3_flag_set(tp, TSO_CAPABLE);
14182 netdev_update_features(dev);
14183 }
14184 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14185 }
14186}
14187
14188static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14189{
14190 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 14191 int err;
14192 bool reset_phy = false;
faf1627a
MC		 14193
14194 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14195 return -EINVAL;
14196
14197 if (!netif_running(dev)) {
14198 /* We'll just catch it later when the
14199 * device is up'd.
14200 */
14201 tg3_set_mtu(dev, tp, new_mtu);
14202 return 0;
14203 }
14204
14205 tg3_phy_stop(tp);
14206
14207 tg3_netif_stop(tp);
14208
c6993dfd
NS		 14209 tg3_set_mtu(dev, tp, new_mtu);
14210
faf1627a
MC		 14211 tg3_full_lock(tp, 1);
14212
14213 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14214
2fae5e36
MC		 14215 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14216 * breaks all requests to 256 bytes.
14217 */
4153577a 14218 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 14219 reset_phy = true;
2fae5e36
MC		 14220
14221 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 14222
14223 if (!err)
14224 tg3_netif_start(tp);
14225
14226 tg3_full_unlock(tp);
14227
14228 if (!err)
14229 tg3_phy_start(tp);
14230
14231 return err;
14232}
14233
14234static const struct net_device_ops tg3_netdev_ops = {
14235 .ndo_open = tg3_open,
14236 .ndo_stop = tg3_close,
14237 .ndo_start_xmit = tg3_start_xmit,
14238 .ndo_get_stats64 = tg3_get_stats64,
14239 .ndo_validate_addr = eth_validate_addr,
14240 .ndo_set_rx_mode = tg3_set_rx_mode,
14241 .ndo_set_mac_address = tg3_set_mac_addr,
14242 .ndo_do_ioctl = tg3_ioctl,
14243 .ndo_tx_timeout = tg3_tx_timeout,
14244 .ndo_change_mtu = tg3_change_mtu,
14245 .ndo_fix_features = tg3_fix_features,
14246 .ndo_set_features = tg3_set_features,
14247#ifdef CONFIG_NET_POLL_CONTROLLER
14248 .ndo_poll_controller = tg3_poll_controller,
14249#endif
14250};
14251
229b1ad1 14252static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14253{
1b27777a 14254 u32 cursize, val, magic;
1da177e4
LT		 14255
14256 tp->nvram_size = EEPROM_CHIP_SIZE;
14257
e4f34110 14258 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14259 return;
14260
b16250e3
MC		 14261 if ((magic != TG3_EEPROM_MAGIC) &&
14262 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14263 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14264 return;
14265
14266 /*
14267 * Size the chip by reading offsets at increasing powers of two.
14268 * When we encounter our validation signature, we know the addressing
14269 * has wrapped around, and thus have our chip size.
14270 */
1b27777a 14271 cursize = 0x10;
1da177e4
LT		 14272
14273 while (cursize < tp->nvram_size) {
e4f34110 14274 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14275 return;
14276
1820180b 14277 if (val == magic)
1da177e4
LT		 14278 break;
14279
14280 cursize <<= 1;
14281 }
14282
14283 tp->nvram_size = cursize;
14284}
6aa20a22 14285
229b1ad1 14286static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14287{
14288 u32 val;
14289
63c3a66f 14290 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14291 return;
14292
14293 /* Selfboot format */
1820180b 14294 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14295 tg3_get_eeprom_size(tp);
14296 return;
14297 }
14298
6d348f2c 14299 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14300 if (val != 0) {
6d348f2c
MC		 14301 /* This is confusing. We want to operate on the
14302 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14303 * call will read from NVRAM and byteswap the data
14304 * according to the byteswapping settings for all
14305 * other register accesses. This ensures the data we
14306 * want will always reside in the lower 16-bits.
14307 * However, the data in NVRAM is in LE format, which
14308 * means the data from the NVRAM read will always be
14309 * opposite the endianness of the CPU. The 16-bit
14310 * byteswap then brings the data to CPU endianness.
14311 */
14312 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14313 return;
14314 }
14315 }
fd1122a2 14316 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14317}
14318
229b1ad1 14319static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14320{
14321 u32 nvcfg1;
14322
14323 nvcfg1 = tr32(NVRAM_CFG1);
14324 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14325 tg3_flag_set(tp, FLASH);
8590a603 14326 } else {
1da177e4
LT		 14327 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14328 tw32(NVRAM_CFG1, nvcfg1);
14329 }
14330
4153577a 14331 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14332 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14333 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14334 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14335 tp->nvram_jedecnum = JEDEC_ATMEL;
14336 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14337 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14338 break;
14339 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14340 tp->nvram_jedecnum = JEDEC_ATMEL;
14341 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14342 break;
14343 case FLASH_VENDOR_ATMEL_EEPROM:
14344 tp->nvram_jedecnum = JEDEC_ATMEL;
14345 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14346 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14347 break;
14348 case FLASH_VENDOR_ST:
14349 tp->nvram_jedecnum = JEDEC_ST;
14350 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14351 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14352 break;
14353 case FLASH_VENDOR_SAIFUN:
14354 tp->nvram_jedecnum = JEDEC_SAIFUN;
14355 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14356 break;
14357 case FLASH_VENDOR_SST_SMALL:
14358 case FLASH_VENDOR_SST_LARGE:
14359 tp->nvram_jedecnum = JEDEC_SST;
14360 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14361 break;
1da177e4 14362 }
8590a603 14363 } else {
1da177e4
LT		 14364 tp->nvram_jedecnum = JEDEC_ATMEL;
14365 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14366 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14367 }
14368}
14369
229b1ad1 14370static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14371{
14372 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14373 case FLASH_5752PAGE_SIZE_256:
14374 tp->nvram_pagesize = 256;
14375 break;
14376 case FLASH_5752PAGE_SIZE_512:
14377 tp->nvram_pagesize = 512;
14378 break;
14379 case FLASH_5752PAGE_SIZE_1K:
14380 tp->nvram_pagesize = 1024;
14381 break;
14382 case FLASH_5752PAGE_SIZE_2K:
14383 tp->nvram_pagesize = 2048;
14384 break;
14385 case FLASH_5752PAGE_SIZE_4K:
14386 tp->nvram_pagesize = 4096;
14387 break;
14388 case FLASH_5752PAGE_SIZE_264:
14389 tp->nvram_pagesize = 264;
14390 break;
14391 case FLASH_5752PAGE_SIZE_528:
14392 tp->nvram_pagesize = 528;
14393 break;
14394 }
14395}
14396
229b1ad1 14397static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14398{
14399 u32 nvcfg1;
14400
14401 nvcfg1 = tr32(NVRAM_CFG1);
14402
e6af301b
MC		 14403 /* NVRAM protection for TPM */
14404 if (nvcfg1 & (1 << 27))
63c3a66f 14405 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14406
361b4ac2 14407 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14408 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14409 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14410 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14411 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14412 break;
14413 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14414 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14415 tg3_flag_set(tp, NVRAM_BUFFERED);
14416 tg3_flag_set(tp, FLASH);
8590a603
MC		 14417 break;
14418 case FLASH_5752VENDOR_ST_M45PE10:
14419 case FLASH_5752VENDOR_ST_M45PE20:
14420 case FLASH_5752VENDOR_ST_M45PE40:
14421 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14422 tg3_flag_set(tp, NVRAM_BUFFERED);
14423 tg3_flag_set(tp, FLASH);
8590a603 14424 break;
361b4ac2
MC		 14425 }
14426
63c3a66f 14427 if (tg3_flag(tp, FLASH)) {
a1b950d5 14428 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14429 } else {
361b4ac2
MC		 14430 /* For eeprom, set pagesize to maximum eeprom size */
14431 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14432
14433 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14434 tw32(NVRAM_CFG1, nvcfg1);
14435 }
14436}
14437
229b1ad1 14438static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14439{
989a9d23 14440 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14441
14442 nvcfg1 = tr32(NVRAM_CFG1);
14443
14444 /* NVRAM protection for TPM */
989a9d23 14445 if (nvcfg1 & (1 << 27)) {
63c3a66f 14446 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14447 protect = 1;
14448 }
d3c7b886 14449
989a9d23
MC		 14450 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14451 switch (nvcfg1) {
8590a603
MC		 14452 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14453 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14454 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14455 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14456 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14457 tg3_flag_set(tp, NVRAM_BUFFERED);
14458 tg3_flag_set(tp, FLASH);
8590a603
MC		 14459 tp->nvram_pagesize = 264;
14460 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14461 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14462 tp->nvram_size = (protect ? 0x3e200 :
14463 TG3_NVRAM_SIZE_512KB);
14464 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14465 tp->nvram_size = (protect ? 0x1f200 :
14466 TG3_NVRAM_SIZE_256KB);
14467 else
14468 tp->nvram_size = (protect ? 0x1f200 :
14469 TG3_NVRAM_SIZE_128KB);
14470 break;
14471 case FLASH_5752VENDOR_ST_M45PE10:
14472 case FLASH_5752VENDOR_ST_M45PE20:
14473 case FLASH_5752VENDOR_ST_M45PE40:
14474 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14475 tg3_flag_set(tp, NVRAM_BUFFERED);
14476 tg3_flag_set(tp, FLASH);
8590a603
MC		 14477 tp->nvram_pagesize = 256;
14478 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14479 tp->nvram_size = (protect ?
14480 TG3_NVRAM_SIZE_64KB :
14481 TG3_NVRAM_SIZE_128KB);
14482 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14483 tp->nvram_size = (protect ?
14484 TG3_NVRAM_SIZE_64KB :
14485 TG3_NVRAM_SIZE_256KB);
14486 else
14487 tp->nvram_size = (protect ?
14488 TG3_NVRAM_SIZE_128KB :
14489 TG3_NVRAM_SIZE_512KB);
14490 break;
d3c7b886
MC		 14491 }
14492}
14493
229b1ad1 14494static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14495{
14496 u32 nvcfg1;
14497
14498 nvcfg1 = tr32(NVRAM_CFG1);
14499
14500 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14501 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14502 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14503 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14504 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14505 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14506 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14507 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14508
8590a603
MC		 14509 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14510 tw32(NVRAM_CFG1, nvcfg1);
14511 break;
14512 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14513 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14514 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14515 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14516 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14517 tg3_flag_set(tp, NVRAM_BUFFERED);
14518 tg3_flag_set(tp, FLASH);
8590a603
MC		 14519 tp->nvram_pagesize = 264;
14520 break;
14521 case FLASH_5752VENDOR_ST_M45PE10:
14522 case FLASH_5752VENDOR_ST_M45PE20:
14523 case FLASH_5752VENDOR_ST_M45PE40:
14524 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14525 tg3_flag_set(tp, NVRAM_BUFFERED);
14526 tg3_flag_set(tp, FLASH);
8590a603
MC		 14527 tp->nvram_pagesize = 256;
14528 break;
1b27777a
MC		 14529 }
14530}
14531
229b1ad1 14532static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14533{
14534 u32 nvcfg1, protect = 0;
14535
14536 nvcfg1 = tr32(NVRAM_CFG1);
14537
14538 /* NVRAM protection for TPM */
14539 if (nvcfg1 & (1 << 27)) {
63c3a66f 14540 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14541 protect = 1;
14542 }
14543
14544 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14545 switch (nvcfg1) {
8590a603
MC		 14546 case FLASH_5761VENDOR_ATMEL_ADB021D:
14547 case FLASH_5761VENDOR_ATMEL_ADB041D:
14548 case FLASH_5761VENDOR_ATMEL_ADB081D:
14549 case FLASH_5761VENDOR_ATMEL_ADB161D:
14550 case FLASH_5761VENDOR_ATMEL_MDB021D:
14551 case FLASH_5761VENDOR_ATMEL_MDB041D:
14552 case FLASH_5761VENDOR_ATMEL_MDB081D:
14553 case FLASH_5761VENDOR_ATMEL_MDB161D:
14554 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14555 tg3_flag_set(tp, NVRAM_BUFFERED);
14556 tg3_flag_set(tp, FLASH);
14557 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14558 tp->nvram_pagesize = 256;
14559 break;
14560 case FLASH_5761VENDOR_ST_A_M45PE20:
14561 case FLASH_5761VENDOR_ST_A_M45PE40:
14562 case FLASH_5761VENDOR_ST_A_M45PE80:
14563 case FLASH_5761VENDOR_ST_A_M45PE16:
14564 case FLASH_5761VENDOR_ST_M_M45PE20:
14565 case FLASH_5761VENDOR_ST_M_M45PE40:
14566 case FLASH_5761VENDOR_ST_M_M45PE80:
14567 case FLASH_5761VENDOR_ST_M_M45PE16:
14568 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14569 tg3_flag_set(tp, NVRAM_BUFFERED);
14570 tg3_flag_set(tp, FLASH);
8590a603
MC		 14571 tp->nvram_pagesize = 256;
14572 break;
6b91fa02
MC		 14573 }
14574
14575 if (protect) {
14576 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14577 } else {
14578 switch (nvcfg1) {
8590a603
MC		 14579 case FLASH_5761VENDOR_ATMEL_ADB161D:
14580 case FLASH_5761VENDOR_ATMEL_MDB161D:
14581 case FLASH_5761VENDOR_ST_A_M45PE16:
14582 case FLASH_5761VENDOR_ST_M_M45PE16:
14583 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14584 break;
14585 case FLASH_5761VENDOR_ATMEL_ADB081D:
14586 case FLASH_5761VENDOR_ATMEL_MDB081D:
14587 case FLASH_5761VENDOR_ST_A_M45PE80:
14588 case FLASH_5761VENDOR_ST_M_M45PE80:
14589 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14590 break;
14591 case FLASH_5761VENDOR_ATMEL_ADB041D:
14592 case FLASH_5761VENDOR_ATMEL_MDB041D:
14593 case FLASH_5761VENDOR_ST_A_M45PE40:
14594 case FLASH_5761VENDOR_ST_M_M45PE40:
14595 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14596 break;
14597 case FLASH_5761VENDOR_ATMEL_ADB021D:
14598 case FLASH_5761VENDOR_ATMEL_MDB021D:
14599 case FLASH_5761VENDOR_ST_A_M45PE20:
14600 case FLASH_5761VENDOR_ST_M_M45PE20:
14601 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14602 break;
6b91fa02
MC		 14603 }
14604 }
14605}
14606
229b1ad1 14607static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14608{
14609 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14610 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14611 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14612}
14613
229b1ad1 14614static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14615{
14616 u32 nvcfg1;
14617
14618 nvcfg1 = tr32(NVRAM_CFG1);
14619
14620 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14621 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14622 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14623 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14624 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14625 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14626
14627 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14628 tw32(NVRAM_CFG1, nvcfg1);
14629 return;
14630 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14631 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14632 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14633 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14634 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14635 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14636 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14637 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14638 tg3_flag_set(tp, NVRAM_BUFFERED);
14639 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14640
14641 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14642 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14643 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14644 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14645 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14646 break;
14647 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14648 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14649 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14650 break;
14651 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14652 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14653 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14654 break;
14655 }
14656 break;
14657 case FLASH_5752VENDOR_ST_M45PE10:
14658 case FLASH_5752VENDOR_ST_M45PE20:
14659 case FLASH_5752VENDOR_ST_M45PE40:
14660 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14661 tg3_flag_set(tp, NVRAM_BUFFERED);
14662 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14663
14664 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14665 case FLASH_5752VENDOR_ST_M45PE10:
14666 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14667 break;
14668 case FLASH_5752VENDOR_ST_M45PE20:
14669 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14670 break;
14671 case FLASH_5752VENDOR_ST_M45PE40:
14672 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14673 break;
14674 }
14675 break;
14676 default:
63c3a66f 14677 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14678 return;
14679 }
14680
a1b950d5
MC		 14681 tg3_nvram_get_pagesize(tp, nvcfg1);
14682 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14683 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14684}
14685
14686
229b1ad1 14687static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14688{
14689 u32 nvcfg1;
14690
14691 nvcfg1 = tr32(NVRAM_CFG1);
14692
14693 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14694 case FLASH_5717VENDOR_ATMEL_EEPROM:
14695 case FLASH_5717VENDOR_MICRO_EEPROM:
14696 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14697 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14698 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14699
14700 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14701 tw32(NVRAM_CFG1, nvcfg1);
14702 return;
14703 case FLASH_5717VENDOR_ATMEL_MDB011D:
14704 case FLASH_5717VENDOR_ATMEL_ADB011B:
14705 case FLASH_5717VENDOR_ATMEL_ADB011D:
14706 case FLASH_5717VENDOR_ATMEL_MDB021D:
14707 case FLASH_5717VENDOR_ATMEL_ADB021B:
14708 case FLASH_5717VENDOR_ATMEL_ADB021D:
14709 case FLASH_5717VENDOR_ATMEL_45USPT:
14710 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14711 tg3_flag_set(tp, NVRAM_BUFFERED);
14712 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14713
14714 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14715 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14716 /* Detect size with tg3_nvram_get_size() */
14717 break;
a1b950d5
MC		 14718 case FLASH_5717VENDOR_ATMEL_ADB021B:
14719 case FLASH_5717VENDOR_ATMEL_ADB021D:
14720 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14721 break;
14722 default:
14723 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14724 break;
14725 }
321d32a0 14726 break;
a1b950d5
MC		 14727 case FLASH_5717VENDOR_ST_M_M25PE10:
14728 case FLASH_5717VENDOR_ST_A_M25PE10:
14729 case FLASH_5717VENDOR_ST_M_M45PE10:
14730 case FLASH_5717VENDOR_ST_A_M45PE10:
14731 case FLASH_5717VENDOR_ST_M_M25PE20:
14732 case FLASH_5717VENDOR_ST_A_M25PE20:
14733 case FLASH_5717VENDOR_ST_M_M45PE20:
14734 case FLASH_5717VENDOR_ST_A_M45PE20:
14735 case FLASH_5717VENDOR_ST_25USPT:
14736 case FLASH_5717VENDOR_ST_45USPT:
14737 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14738 tg3_flag_set(tp, NVRAM_BUFFERED);
14739 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14740
14741 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14742 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14743 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14744 /* Detect size with tg3_nvram_get_size() */
14745 break;
14746 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14747 case FLASH_5717VENDOR_ST_A_M45PE20:
14748 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14749 break;
14750 default:
14751 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14752 break;
14753 }
321d32a0 14754 break;
a1b950d5 14755 default:
63c3a66f 14756 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14757 return;
321d32a0 14758 }
a1b950d5
MC		 14759
14760 tg3_nvram_get_pagesize(tp, nvcfg1);
14761 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14762 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14763}
14764
229b1ad1 14765static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14766{
14767 u32 nvcfg1, nvmpinstrp;
14768
14769 nvcfg1 = tr32(NVRAM_CFG1);
14770 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14771
4153577a 14772 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14773 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14774 tg3_flag_set(tp, NO_NVRAM);
14775 return;
14776 }
14777
14778 switch (nvmpinstrp) {
14779 case FLASH_5762_EEPROM_HD:
14780 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14781 break;
c86a8560
MC		 14782 case FLASH_5762_EEPROM_LD:
14783 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14784 break;
f6334bb8
MC		 14785 case FLASH_5720VENDOR_M_ST_M45PE20:
14786 /* This pinstrap supports multiple sizes, so force it
14787 * to read the actual size from location 0xf0.
14788 */
14789 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14790 break;
c86a8560
MC		 14791 }
14792 }
14793
9b91b5f1
MC		 14794 switch (nvmpinstrp) {
14795 case FLASH_5720_EEPROM_HD:
14796 case FLASH_5720_EEPROM_LD:
14797 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14798 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14799
14800 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14801 tw32(NVRAM_CFG1, nvcfg1);
14802 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14803 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14804 else
14805 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14806 return;
14807 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14808 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14809 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14810 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14811 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14812 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14813 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14814 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14815 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14816 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14817 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14818 case FLASH_5720VENDOR_ATMEL_45USPT:
14819 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14820 tg3_flag_set(tp, NVRAM_BUFFERED);
14821 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14822
14823 switch (nvmpinstrp) {
14824 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14825 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14826 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14827 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14828 break;
14829 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14830 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14831 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14832 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14833 break;
14834 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14835 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14836 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14837 break;
14838 default:
4153577a 14839 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14840 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14841 break;
14842 }
14843 break;
14844 case FLASH_5720VENDOR_M_ST_M25PE10:
14845 case FLASH_5720VENDOR_M_ST_M45PE10:
14846 case FLASH_5720VENDOR_A_ST_M25PE10:
14847 case FLASH_5720VENDOR_A_ST_M45PE10:
14848 case FLASH_5720VENDOR_M_ST_M25PE20:
14849 case FLASH_5720VENDOR_M_ST_M45PE20:
14850 case FLASH_5720VENDOR_A_ST_M25PE20:
14851 case FLASH_5720VENDOR_A_ST_M45PE20:
14852 case FLASH_5720VENDOR_M_ST_M25PE40:
14853 case FLASH_5720VENDOR_M_ST_M45PE40:
14854 case FLASH_5720VENDOR_A_ST_M25PE40:
14855 case FLASH_5720VENDOR_A_ST_M45PE40:
14856 case FLASH_5720VENDOR_M_ST_M25PE80:
14857 case FLASH_5720VENDOR_M_ST_M45PE80:
14858 case FLASH_5720VENDOR_A_ST_M25PE80:
14859 case FLASH_5720VENDOR_A_ST_M45PE80:
14860 case FLASH_5720VENDOR_ST_25USPT:
14861 case FLASH_5720VENDOR_ST_45USPT:
14862 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14863 tg3_flag_set(tp, NVRAM_BUFFERED);
14864 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14865
14866 switch (nvmpinstrp) {
14867 case FLASH_5720VENDOR_M_ST_M25PE20:
14868 case FLASH_5720VENDOR_M_ST_M45PE20:
14869 case FLASH_5720VENDOR_A_ST_M25PE20:
14870 case FLASH_5720VENDOR_A_ST_M45PE20:
14871 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14872 break;
14873 case FLASH_5720VENDOR_M_ST_M25PE40:
14874 case FLASH_5720VENDOR_M_ST_M45PE40:
14875 case FLASH_5720VENDOR_A_ST_M25PE40:
14876 case FLASH_5720VENDOR_A_ST_M45PE40:
14877 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14878 break;
14879 case FLASH_5720VENDOR_M_ST_M25PE80:
14880 case FLASH_5720VENDOR_M_ST_M45PE80:
14881 case FLASH_5720VENDOR_A_ST_M25PE80:
14882 case FLASH_5720VENDOR_A_ST_M45PE80:
14883 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14884 break;
14885 default:
4153577a 14886 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14887 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14888 break;
14889 }
14890 break;
14891 default:
63c3a66f 14892 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14893 return;
14894 }
14895
14896 tg3_nvram_get_pagesize(tp, nvcfg1);
14897 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14898 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14899
4153577a 14900 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14901 u32 val;
14902
14903 if (tg3_nvram_read(tp, 0, &val))
14904 return;
14905
14906 if (val != TG3_EEPROM_MAGIC &&
14907 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14908 tg3_flag_set(tp, NO_NVRAM);
14909 }
9b91b5f1
MC		 14910}
14911
1da177e4 14912/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14913static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14914{
7e6c63f0
HM		 14915 if (tg3_flag(tp, IS_SSB_CORE)) {
14916 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14917 tg3_flag_clear(tp, NVRAM);
14918 tg3_flag_clear(tp, NVRAM_BUFFERED);
14919 tg3_flag_set(tp, NO_NVRAM);
14920 return;
14921 }
14922
1da177e4
LT		 14923 tw32_f(GRC_EEPROM_ADDR,
14924 (EEPROM_ADDR_FSM_RESET |
14925 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14926 EEPROM_ADDR_CLKPERD_SHIFT)));
14927
9d57f01c 14928 msleep(1);
1da177e4
LT		 14929
14930 /* Enable seeprom accesses. */
14931 tw32_f(GRC_LOCAL_CTRL,
14932 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14933 udelay(100);
14934
4153577a
JP		 14935 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14936 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14937 tg3_flag_set(tp, NVRAM);
1da177e4 14938
ec41c7df 14939 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14940 netdev_warn(tp->dev,
14941 "Cannot get nvram lock, %s failed\n",
05dbe005 14942 __func__);
ec41c7df
MC		 14943 return;
14944 }
e6af301b 14945 tg3_enable_nvram_access(tp);
1da177e4 14946
989a9d23
MC		 14947 tp->nvram_size = 0;
14948
4153577a 14949 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14950 tg3_get_5752_nvram_info(tp);
4153577a 14951 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14952 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14953 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14954 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14955 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14956 tg3_get_5787_nvram_info(tp);
4153577a 14957 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14958 tg3_get_5761_nvram_info(tp);
4153577a 14959 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14960 tg3_get_5906_nvram_info(tp);
4153577a 14961 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14962 tg3_flag(tp, 57765_CLASS))
321d32a0 14963 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14964 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14965 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14966 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14967 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14968 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14969 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14970 else
14971 tg3_get_nvram_info(tp);
14972
989a9d23
MC		 14973 if (tp->nvram_size == 0)
14974 tg3_get_nvram_size(tp);
1da177e4 14975
e6af301b 14976 tg3_disable_nvram_access(tp);
381291b7 14977 tg3_nvram_unlock(tp);
1da177e4
LT		 14978
14979 } else {
63c3a66f
JP		 14980 tg3_flag_clear(tp, NVRAM);
14981 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14982
14983 tg3_get_eeprom_size(tp);
14984 }
14985}
14986
1da177e4
LT		 14987struct subsys_tbl_ent {
14988 u16 subsys_vendor, subsys_devid;
14989 u32 phy_id;
14990};
14991
229b1ad1 14992static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14993 /* Broadcom boards. */
24daf2b0 14994 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14995 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14996 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14997 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14998 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14999 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 15000 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15001 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
15002 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 15003 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 15004 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 15005 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 15006 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15007 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
15008 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 15009 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 15010 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 15011 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 15012 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 15013 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 15014 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 15015 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 15016
15017 /* 3com boards. */
24daf2b0 15018 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15019 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 15020 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15021 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 15022 { TG3PCI_SUBVENDOR_ID_3COM,
15023 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15024 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15025 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 15026 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 15027 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 15028
15029 /* DELL boards. */
24daf2b0 15030 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15031 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 15032 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15033 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 15034 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15035 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 15036 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 15037 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 15038
15039 /* Compaq boards. */
24daf2b0 15040 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15041 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 15042 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15043 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 15044 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15045 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15046 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15047 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 15048 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 15049 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 15050
15051 /* IBM boards. */
24daf2b0
MC		 15052 { TG3PCI_SUBVENDOR_ID_IBM,
15053 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 15054};
15055
229b1ad1 15056static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 15057{
15058 int i;
15059
15060 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15061 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15062 tp->pdev->subsystem_vendor) &&
15063 (subsys_id_to_phy_id[i].subsys_devid ==
15064 tp->pdev->subsystem_device))
15065 return &subsys_id_to_phy_id[i];
15066 }
15067 return NULL;
15068}
15069
229b1ad1 15070static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 15071{
1da177e4 15072 u32 val;
f49639e6 15073
79eb6904 15074 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 15075 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15076
a85feb8c 15077 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 15078 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15079 tg3_flag_set(tp, WOL_CAP);
72b845e0 15080
4153577a 15081 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 15082 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 15083 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15084 tg3_flag_set(tp, IS_NIC);
9d26e213 15085 }
0527ba35
MC		 15086 val = tr32(VCPU_CFGSHDW);
15087 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 15088 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 15089 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 15090 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 15091 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15092 device_set_wakeup_enable(&tp->pdev->dev, true);
15093 }
05ac4cb7 15094 goto done;
b5d3772c
MC		 15095 }
15096
1da177e4
LT		 15097 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15098 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15099 u32 nic_cfg, led_cfg;
7c786065
NS		 15100 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15101 u32 nic_phy_id, ver, eeprom_phy_id;
7d0c41ef 15102 int eeprom_phy_serdes = 0;
1da177e4
LT		 15103
15104 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15105 tp->nic_sram_data_cfg = nic_cfg;
15106
15107 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15108 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 15109 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15110 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15111 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 15112 (ver > 0) && (ver < 0x100))
15113 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15114
4153577a 15115 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 15116 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15117
7c786065
NS		 15118 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15119 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15120 tg3_asic_rev(tp) == ASIC_REV_5720)
15121 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15122
1da177e4
LT		 15123 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15124 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15125 eeprom_phy_serdes = 1;
15126
15127 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15128 if (nic_phy_id != 0) {
15129 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15130 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15131
15132 eeprom_phy_id = (id1 >> 16) << 10;
15133 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15134 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15135 } else
15136 eeprom_phy_id = 0;
15137
7d0c41ef 15138 tp->phy_id = eeprom_phy_id;
747e8f8b 15139 if (eeprom_phy_serdes) {
63c3a66f 15140 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 15141 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 15142 else
f07e9af3 15143 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 15144 }
7d0c41ef 15145
63c3a66f 15146 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 15147 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15148 SHASTA_EXT_LED_MODE_MASK);
cbf46853 15149 else
1da177e4
LT		 15150 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15151
15152 switch (led_cfg) {
15153 default:
15154 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15155 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15156 break;
15157
15158 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15159 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15160 break;
15161
15162 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15163 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 15164
15165 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15166 * read on some older 5700/5701 bootcode.
15167 */
4153577a
JP		 15168 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15169 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 15170 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15171
1da177e4
LT		 15172 break;
15173
15174 case SHASTA_EXT_LED_SHARED:
15175 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 15176 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15177 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 15178 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15179 LED_CTRL_MODE_PHY_2);
89f67978
NS		 15180
15181 if (tg3_flag(tp, 5717_PLUS) ||
15182 tg3_asic_rev(tp) == ASIC_REV_5762)
15183 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15184 LED_CTRL_BLINK_RATE_MASK;
15185
1da177e4
LT		 15186 break;
15187
15188 case SHASTA_EXT_LED_MAC:
15189 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15190 break;
15191
15192 case SHASTA_EXT_LED_COMBO:
15193 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 15194 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 15195 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15196 LED_CTRL_MODE_PHY_2);
15197 break;
15198
855e1111 15199 }
1da177e4 15200
4153577a
JP		 15201 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15202 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 15203 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15204 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15205
4153577a 15206 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 15207 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 15208
9d26e213 15209 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 15210 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 15211 if ((tp->pdev->subsystem_vendor ==
15212 PCI_VENDOR_ID_ARIMA) &&
15213 (tp->pdev->subsystem_device == 0x205a ||
15214 tp->pdev->subsystem_device == 0x2063))
63c3a66f 15215 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 15216 } else {
63c3a66f
JP		 15217 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15218 tg3_flag_set(tp, IS_NIC);
9d26e213 15219 }
1da177e4
LT		 15220
15221 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 15222 tg3_flag_set(tp, ENABLE_ASF);
15223 if (tg3_flag(tp, 5750_PLUS))
15224 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 15225 }
b2b98d4a
MC		 15226
15227 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 15228 tg3_flag(tp, 5750_PLUS))
15229 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 15230
f07e9af3 15231 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 15232 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 15233 tg3_flag_clear(tp, WOL_CAP);
1da177e4 15234
63c3a66f 15235 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 15236 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 15237 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15238 device_set_wakeup_enable(&tp->pdev->dev, true);
15239 }
0527ba35 15240
1da177e4 15241 if (cfg2 & (1 << 17))
f07e9af3 15242 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 15243
15244 /* serdes signal pre-emphasis in register 0x590 set by */
15245 /* bootcode if bit 18 is set */
15246 if (cfg2 & (1 << 18))
f07e9af3 15247 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 15248
63c3a66f 15249 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 15250 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15251 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 15252 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 15253 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 15254
942d1af0 15255 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 15256 u32 cfg3;
15257
15258 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 15259 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15260 !tg3_flag(tp, 57765_PLUS) &&
15261 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15262 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15263 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15264 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15265 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15266 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15267 }
a9daf367 15268
14417063 15269 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15270 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15271 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15272 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15273 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15274 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
7c786065
NS		 15275
15276 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15277 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
1da177e4 15278 }
05ac4cb7 15279done:
63c3a66f 15280 if (tg3_flag(tp, WOL_CAP))
43067ed8 15281 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15282 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15283 else
15284 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15285}
15286
c86a8560
MC		 15287static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15288{
15289 int i, err;
15290 u32 val2, off = offset * 8;
15291
15292 err = tg3_nvram_lock(tp);
15293 if (err)
15294 return err;
15295
15296 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15297 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15298 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15299 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15300 udelay(10);
15301
15302 for (i = 0; i < 100; i++) {
15303 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15304 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15305 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15306 break;
15307 }
15308 udelay(10);
15309 }
15310
15311 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15312
15313 tg3_nvram_unlock(tp);
15314 if (val2 & APE_OTP_STATUS_CMD_DONE)
15315 return 0;
15316
15317 return -EBUSY;
15318}
15319
229b1ad1 15320static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15321{
15322 int i;
15323 u32 val;
15324
15325 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15326 tw32(OTP_CTRL, cmd);
15327
15328 /* Wait for up to 1 ms for command to execute. */
15329 for (i = 0; i < 100; i++) {
15330 val = tr32(OTP_STATUS);
15331 if (val & OTP_STATUS_CMD_DONE)
15332 break;
15333 udelay(10);
15334 }
15335
15336 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15337}
15338
15339/* Read the gphy configuration from the OTP region of the chip. The gphy
15340 * configuration is a 32-bit value that straddles the alignment boundary.
15341 * We do two 32-bit reads and then shift and merge the results.
15342 */
229b1ad1 15343static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15344{
15345 u32 bhalf_otp, thalf_otp;
15346
15347 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15348
15349 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15350 return 0;
15351
15352 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15353
15354 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15355 return 0;
15356
15357 thalf_otp = tr32(OTP_READ_DATA);
15358
15359 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15360
15361 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15362 return 0;
15363
15364 bhalf_otp = tr32(OTP_READ_DATA);
15365
15366 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15367}
15368
229b1ad1 15369static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15370{
202ff1c2 15371 u32 adv = ADVERTISED_Autoneg;
e256f8a3 15372
7c786065
NS		 15373 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15374 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15375 adv |= ADVERTISED_1000baseT_Half;
15376 adv |= ADVERTISED_1000baseT_Full;
15377 }
e256f8a3
MC		 15378
15379 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15380 adv |= ADVERTISED_100baseT_Half |
15381 ADVERTISED_100baseT_Full |
15382 ADVERTISED_10baseT_Half |
15383 ADVERTISED_10baseT_Full |
15384 ADVERTISED_TP;
15385 else
15386 adv |= ADVERTISED_FIBRE;
15387
15388 tp->link_config.advertising = adv;
e740522e
MC		 15389 tp->link_config.speed = SPEED_UNKNOWN;
15390 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15391 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15392 tp->link_config.active_speed = SPEED_UNKNOWN;
15393 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15394
15395 tp->old_link = -1;
e256f8a3
MC		 15396}
15397
229b1ad1 15398static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15399{
15400 u32 hw_phy_id_1, hw_phy_id_2;
15401 u32 hw_phy_id, hw_phy_id_masked;
15402 int err;
1da177e4 15403
e256f8a3 15404 /* flow control autonegotiation is default behavior */
63c3a66f 15405 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15406 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15407
8151ad57
MC		 15408 if (tg3_flag(tp, ENABLE_APE)) {
15409 switch (tp->pci_fn) {
15410 case 0:
15411 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15412 break;
15413 case 1:
15414 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15415 break;
15416 case 2:
15417 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15418 break;
15419 case 3:
15420 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15421 break;
15422 }
15423 }
15424
942d1af0
NS		 15425 if (!tg3_flag(tp, ENABLE_ASF) &&
15426 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15427 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15428 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15429 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15430
63c3a66f 15431 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15432 return tg3_phy_init(tp);
15433
1da177e4 15434 /* Reading the PHY ID register can conflict with ASF
877d0310 15435 * firmware access to the PHY hardware.
1da177e4
LT		 15436 */
15437 err = 0;
63c3a66f 15438 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15439 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15440 } else {
15441 /* Now read the physical PHY_ID from the chip and verify
15442 * that it is sane. If it doesn't look good, we fall back
15443 * to either the hard-coded table based PHY_ID and failing
15444 * that the value found in the eeprom area.
15445 */
15446 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15447 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15448
15449 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15450 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15451 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15452
79eb6904 15453 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15454 }
15455
79eb6904 15456 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15457 tp->phy_id = hw_phy_id;
79eb6904 15458 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15459 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15460 else
f07e9af3 15461 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15462 } else {
79eb6904 15463 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15464 /* Do nothing, phy ID already set up in
15465 * tg3_get_eeprom_hw_cfg().
15466 */
1da177e4
LT		 15467 } else {
15468 struct subsys_tbl_ent *p;
15469
15470 /* No eeprom signature? Try the hardcoded
15471 * subsys device table.
15472 */
24daf2b0 15473 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15474 if (p) {
15475 tp->phy_id = p->phy_id;
15476 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15477 /* For now we saw the IDs 0xbc050cd0,
15478 * 0xbc050f80 and 0xbc050c30 on devices
15479 * connected to an BCM4785 and there are
15480 * probably more. Just assume that the phy is
15481 * supported when it is connected to a SSB core
15482 * for now.
15483 */
1da177e4 15484 return -ENODEV;
7e6c63f0 15485 }
1da177e4 15486
1da177e4 15487 if (!tp->phy_id ||
79eb6904 15488 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15489 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15490 }
15491 }
15492
a6b68dab 15493 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15494 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15495 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15496 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15497 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15498 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15499 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15500 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15501 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15502 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15503
9e2ecbeb
NS		 15504 tp->eee.supported = SUPPORTED_100baseT_Full |
15505 SUPPORTED_1000baseT_Full;
15506 tp->eee.advertised = ADVERTISED_100baseT_Full |
15507 ADVERTISED_1000baseT_Full;
15508 tp->eee.eee_enabled = 1;
15509 tp->eee.tx_lpi_enabled = 1;
15510 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15511 }
15512
e256f8a3
MC		 15513 tg3_phy_init_link_config(tp);
15514
942d1af0
NS		 15515 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15516 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15517 !tg3_flag(tp, ENABLE_APE) &&
15518 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15519 u32 bmsr, dummy;
1da177e4
LT		 15520
15521 tg3_readphy(tp, MII_BMSR, &bmsr);
15522 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15523 (bmsr & BMSR_LSTATUS))
15524 goto skip_phy_reset;
6aa20a22 15525
1da177e4
LT		 15526 err = tg3_phy_reset(tp);
15527 if (err)
15528 return err;
15529
42b64a45 15530 tg3_phy_set_wirespeed(tp);
1da177e4 15531
e2bf73e7 15532 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15533 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15534 tp->link_config.flowctrl);
1da177e4
LT		 15535
15536 tg3_writephy(tp, MII_BMCR,
15537 BMCR_ANENABLE | BMCR_ANRESTART);
15538 }
1da177e4
LT		 15539 }
15540
15541skip_phy_reset:
79eb6904 15542 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15543 err = tg3_init_5401phy_dsp(tp);
15544 if (err)
15545 return err;
1da177e4 15546
1da177e4
LT		 15547 err = tg3_init_5401phy_dsp(tp);
15548 }
15549
1da177e4
LT		 15550 return err;
15551}
15552
229b1ad1 15553static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15554{
a4a8bb15 15555 u8 *vpd_data;
4181b2c8 15556 unsigned int block_end, rosize, len;
535a490e 15557 u32 vpdlen;
184b8904 15558 int j, i = 0;
a4a8bb15 15559
535a490e 15560 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15561 if (!vpd_data)
15562 goto out_no_vpd;
1da177e4 15563
535a490e 15564 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15565 if (i < 0)
15566 goto out_not_found;
1da177e4 15567
4181b2c8
MC		 15568 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15569 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15570 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15571
535a490e 15572 if (block_end > vpdlen)
4181b2c8 15573 goto out_not_found;
af2c6a4a 15574
184b8904
MC		 15575 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15576 PCI_VPD_RO_KEYWORD_MFR_ID);
15577 if (j > 0) {
15578 len = pci_vpd_info_field_size(&vpd_data[j]);
15579
15580 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15581 if (j + len > block_end || len != 4 ||
15582 memcmp(&vpd_data[j], "1028", 4))
15583 goto partno;
15584
15585 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15586 PCI_VPD_RO_KEYWORD_VENDOR0);
15587 if (j < 0)
15588 goto partno;
15589
15590 len = pci_vpd_info_field_size(&vpd_data[j]);
15591
15592 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15593 if (j + len > block_end)
15594 goto partno;
15595
715230a4
KC		 15596 if (len >= sizeof(tp->fw_ver))
15597 len = sizeof(tp->fw_ver) - 1;
15598 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15599 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15600 &vpd_data[j]);
184b8904
MC		 15601 }
15602
15603partno:
4181b2c8
MC		 15604 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15605 PCI_VPD_RO_KEYWORD_PARTNO);
15606 if (i < 0)
15607 goto out_not_found;
af2c6a4a 15608
4181b2c8 15609 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15610
4181b2c8
MC		 15611 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15612 if (len > TG3_BPN_SIZE ||
535a490e 15613 (len + i) > vpdlen)
4181b2c8 15614 goto out_not_found;
1da177e4 15615
4181b2c8 15616 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15617
1da177e4 15618out_not_found:
a4a8bb15 15619 kfree(vpd_data);
37a949c5 15620 if (tp->board_part_number[0])
a4a8bb15
MC		 15621 return;
15622
15623out_no_vpd:
4153577a 15624 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15625 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15626 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15627 strcpy(tp->board_part_number, "BCM5717");
15628 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15629 strcpy(tp->board_part_number, "BCM5718");
15630 else
15631 goto nomatch;
4153577a 15632 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15633 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15634 strcpy(tp->board_part_number, "BCM57780");
15635 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15636 strcpy(tp->board_part_number, "BCM57760");
15637 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15638 strcpy(tp->board_part_number, "BCM57790");
15639 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15640 strcpy(tp->board_part_number, "BCM57788");
15641 else
15642 goto nomatch;
4153577a 15643 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15644 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15645 strcpy(tp->board_part_number, "BCM57761");
15646 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15647 strcpy(tp->board_part_number, "BCM57765");
15648 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15649 strcpy(tp->board_part_number, "BCM57781");
15650 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15651 strcpy(tp->board_part_number, "BCM57785");
15652 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15653 strcpy(tp->board_part_number, "BCM57791");
15654 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15655 strcpy(tp->board_part_number, "BCM57795");
15656 else
15657 goto nomatch;
4153577a 15658 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15659 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15660 strcpy(tp->board_part_number, "BCM57762");
15661 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15662 strcpy(tp->board_part_number, "BCM57766");
15663 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15664 strcpy(tp->board_part_number, "BCM57782");
15665 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15666 strcpy(tp->board_part_number, "BCM57786");
15667 else
15668 goto nomatch;
4153577a 15669 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15670 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15671 } else {
15672nomatch:
b5d3772c 15673 strcpy(tp->board_part_number, "none");
37a949c5 15674 }
1da177e4
LT		 15675}
15676
229b1ad1 15677static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15678{
15679 u32 val;
15680
e4f34110 15681 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15682 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15683 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15684 val != 0)
15685 return 0;
15686
15687 return 1;
15688}
15689
229b1ad1 15690static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15691{
ff3a7cb2 15692 u32 val, offset, start, ver_offset;
75f9936e 15693 int i, dst_off;
ff3a7cb2 15694 bool newver = false;
acd9c119
MC		 15695
15696 if (tg3_nvram_read(tp, 0xc, &offset) ||
15697 tg3_nvram_read(tp, 0x4, &start))
15698 return;
15699
15700 offset = tg3_nvram_logical_addr(tp, offset);
15701
ff3a7cb2 15702 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15703 return;
15704
ff3a7cb2
MC		 15705 if ((val & 0xfc000000) == 0x0c000000) {
15706 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15707 return;
15708
ff3a7cb2
MC		 15709 if (val == 0)
15710 newver = true;
15711 }
15712
75f9936e
MC		 15713 dst_off = strlen(tp->fw_ver);
15714
ff3a7cb2 15715 if (newver) {
75f9936e
MC		 15716 if (TG3_VER_SIZE - dst_off < 16 ||
15717 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15718 return;
15719
15720 offset = offset + ver_offset - start;
15721 for (i = 0; i < 16; i += 4) {
15722 __be32 v;
15723 if (tg3_nvram_read_be32(tp, offset + i, &v))
15724 return;
15725
75f9936e 15726 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15727 }
15728 } else {
15729 u32 major, minor;
15730
15731 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15732 return;
15733
15734 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15735 TG3_NVM_BCVER_MAJSFT;
15736 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15737 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15738 "v%d.%02d", major, minor);
acd9c119
MC		 15739 }
15740}
15741
229b1ad1 15742static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15743{
15744 u32 val, major, minor;
15745
15746 /* Use native endian representation */
15747 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15748 return;
15749
15750 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15751 TG3_NVM_HWSB_CFG1_MAJSFT;
15752 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15753 TG3_NVM_HWSB_CFG1_MINSFT;
15754
15755 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15756}
15757
229b1ad1 15758static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15759{
15760 u32 offset, major, minor, build;
15761
75f9936e 15762 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15763
15764 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15765 return;
15766
15767 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15768 case TG3_EEPROM_SB_REVISION_0:
15769 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15770 break;
15771 case TG3_EEPROM_SB_REVISION_2:
15772 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15773 break;
15774 case TG3_EEPROM_SB_REVISION_3:
15775 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15776 break;
a4153d40
MC		 15777 case TG3_EEPROM_SB_REVISION_4:
15778 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15779 break;
15780 case TG3_EEPROM_SB_REVISION_5:
15781 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15782 break;
bba226ac
MC		 15783 case TG3_EEPROM_SB_REVISION_6:
15784 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15785 break;
dfe00d7d
MC		 15786 default:
15787 return;
15788 }
15789
e4f34110 15790 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15791 return;
15792
15793 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15794 TG3_EEPROM_SB_EDH_BLD_SHFT;
15795 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15796 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15797 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15798
15799 if (minor > 99 || build > 26)
15800 return;
15801
75f9936e
MC		 15802 offset = strlen(tp->fw_ver);
15803 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15804 " v%d.%02d", major, minor);
dfe00d7d
MC		 15805
15806 if (build > 0) {
75f9936e
MC		 15807 offset = strlen(tp->fw_ver);
15808 if (offset < TG3_VER_SIZE - 1)
15809 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15810 }
15811}
15812
229b1ad1 15813static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15814{
15815 u32 val, offset, start;
acd9c119 15816 int i, vlen;
9c8a620e
MC		 15817
15818 for (offset = TG3_NVM_DIR_START;
15819 offset < TG3_NVM_DIR_END;
15820 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15821 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15822 return;
15823
9c8a620e
MC		 15824 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15825 break;
15826 }
15827
15828 if (offset == TG3_NVM_DIR_END)
15829 return;
15830
63c3a66f 15831 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15832 start = 0x08000000;
e4f34110 15833 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15834 return;
15835
e4f34110 15836 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15837 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15838 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15839 return;
15840
15841 offset += val - start;
15842
acd9c119 15843 vlen = strlen(tp->fw_ver);
9c8a620e 15844
acd9c119
MC		 15845 tp->fw_ver[vlen++] = ',';
15846 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15847
15848 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15849 __be32 v;
15850 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15851 return;
15852
b9fc7dc5 15853 offset += sizeof(v);
c4e6575c 15854
acd9c119
MC		 15855 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15856 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15857 break;
c4e6575c 15858 }
9c8a620e 15859
acd9c119
MC		 15860 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15861 vlen += sizeof(v);
c4e6575c 15862 }
acd9c119
MC		 15863}
15864
229b1ad1 15865static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15866{
7fd76445 15867 u32 apedata;
7fd76445
MC		 15868
15869 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15870 if (apedata != APE_SEG_SIG_MAGIC)
15871 return;
15872
15873 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15874 if (!(apedata & APE_FW_STATUS_READY))
15875 return;
15876
165f4d1c
MC		 15877 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15878 tg3_flag_set(tp, APE_HAS_NCSI);
15879}
15880
229b1ad1 15881static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15882{
15883 int vlen;
15884 u32 apedata;
15885 char *fwtype;
15886
7fd76445
MC		 15887 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15888
165f4d1c 15889 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15890 fwtype = "NCSI";
c86a8560
MC		 15891 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15892 fwtype = "SMASH";
165f4d1c 15893 else
ecc79648
MC		 15894 fwtype = "DASH";
15895
7fd76445
MC		 15896 vlen = strlen(tp->fw_ver);
15897
ecc79648
MC		 15898 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15899 fwtype,
7fd76445
MC		 15900 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15901 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15902 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15903 (apedata & APE_FW_VERSION_BLDMSK));
15904}
15905
c86a8560
MC		 15906static void tg3_read_otp_ver(struct tg3 *tp)
15907{
15908 u32 val, val2;
15909
4153577a 15910 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15911 return;
15912
15913 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15914 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15915 TG3_OTP_MAGIC0_VALID(val)) {
15916 u64 val64 = (u64) val << 32 | val2;
15917 u32 ver = 0;
15918 int i, vlen;
15919
15920 for (i = 0; i < 7; i++) {
15921 if ((val64 & 0xff) == 0)
15922 break;
15923 ver = val64 & 0xff;
15924 val64 >>= 8;
15925 }
15926 vlen = strlen(tp->fw_ver);
15927 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15928 }
15929}
15930
229b1ad1 15931static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15932{
15933 u32 val;
75f9936e 15934 bool vpd_vers = false;
acd9c119 15935
75f9936e
MC		 15936 if (tp->fw_ver[0] != 0)
15937 vpd_vers = true;
df259d8c 15938
63c3a66f 15939 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15940 strcat(tp->fw_ver, "sb");
c86a8560 15941 tg3_read_otp_ver(tp);
df259d8c
MC		 15942 return;
15943 }
15944
acd9c119
MC		 15945 if (tg3_nvram_read(tp, 0, &val))
15946 return;
15947
15948 if (val == TG3_EEPROM_MAGIC)
15949 tg3_read_bc_ver(tp);
15950 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15951 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15952 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15953 tg3_read_hwsb_ver(tp);
acd9c119 15954
165f4d1c
MC		 15955 if (tg3_flag(tp, ENABLE_ASF)) {
15956 if (tg3_flag(tp, ENABLE_APE)) {
15957 tg3_probe_ncsi(tp);
15958 if (!vpd_vers)
15959 tg3_read_dash_ver(tp);
15960 } else if (!vpd_vers) {
15961 tg3_read_mgmtfw_ver(tp);
15962 }
c9cab24e 15963 }
9c8a620e
MC		 15964
15965 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15966}
15967
7cb32cf2
MC		 15968static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15969{
63c3a66f 15970 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15971 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15972 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15973 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15974 else
de9f5230 15975 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15976}
15977
9baa3c34 15978static const struct pci_device_id tg3_write_reorder_chipsets[] = {
895950c2
JP		 15979 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15980 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15981 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15982 { },
15983};
15984
229b1ad1 15985static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15986{
15987 struct pci_dev *peer;
15988 unsigned int func, devnr = tp->pdev->devfn & ~7;
15989
15990 for (func = 0; func < 8; func++) {
15991 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15992 if (peer && peer != tp->pdev)
15993 break;
15994 pci_dev_put(peer);
15995 }
15996 /* 5704 can be configured in single-port mode, set peer to
15997 * tp->pdev in that case.
15998 */
15999 if (!peer) {
16000 peer = tp->pdev;
16001 return peer;
16002 }
16003
16004 /*
16005 * We don't need to keep the refcount elevated; there's no way
16006 * to remove one half of this device without removing the other
16007 */
16008 pci_dev_put(peer);
16009
16010 return peer;
16011}
16012
229b1ad1 16013static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 16014{
16015 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 16016 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 16017 u32 reg;
16018
16019 /* All devices that use the alternate
16020 * ASIC REV location have a CPMU.
16021 */
16022 tg3_flag_set(tp, CPMU_PRESENT);
16023
16024 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 16025 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 16026 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16027 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 16028 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 16029 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16030 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 16031 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16032 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 16033 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16034 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
42b123b1
MC		 16035 reg = TG3PCI_GEN2_PRODID_ASICREV;
16036 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16037 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16038 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16039 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16040 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16041 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16042 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16043 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16044 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16045 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16046 reg = TG3PCI_GEN15_PRODID_ASICREV;
16047 else
16048 reg = TG3PCI_PRODID_ASICREV;
16049
16050 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16051 }
16052
16053 /* Wrong chip ID in 5752 A0. This code can be removed later
16054 * as A0 is not in production.
16055 */
4153577a 16056 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 16057 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16058
4153577a 16059 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 16060 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16061
4153577a
JP		 16062 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16063 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16064 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 16065 tg3_flag_set(tp, 5717_PLUS);
16066
4153577a
JP		 16067 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16068 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 16069 tg3_flag_set(tp, 57765_CLASS);
16070
c65a17f4 16071 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 16072 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 16073 tg3_flag_set(tp, 57765_PLUS);
16074
16075 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 16076 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16077 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16078 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16079 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16080 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16081 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 16082 tg3_flag(tp, 57765_PLUS))
16083 tg3_flag_set(tp, 5755_PLUS);
16084
4153577a
JP		 16085 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16086 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 16087 tg3_flag_set(tp, 5780_CLASS);
16088
4153577a
JP		 16089 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16090 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16091 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 16092 tg3_flag(tp, 5755_PLUS) ||
16093 tg3_flag(tp, 5780_CLASS))
16094 tg3_flag_set(tp, 5750_PLUS);
16095
4153577a 16096 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 16097 tg3_flag(tp, 5750_PLUS))
16098 tg3_flag_set(tp, 5705_PLUS);
16099}
16100
3d567e0e
NNS		 16101static bool tg3_10_100_only_device(struct tg3 *tp,
16102 const struct pci_device_id *ent)
16103{
16104 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16105
4153577a
JP		 16106 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16107 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 16108 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16109 return true;
16110
16111 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 16112 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 16113 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16114 return true;
16115 } else {
16116 return true;
16117 }
16118 }
16119
16120 return false;
16121}
16122
1dd06ae8 16123static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 16124{
1da177e4 16125 u32 misc_ctrl_reg;
1da177e4
LT		 16126 u32 pci_state_reg, grc_misc_cfg;
16127 u32 val;
16128 u16 pci_cmd;
5e7dfd0f 16129 int err;
1da177e4 16130
1da177e4
LT		 16131 /* Force memory write invalidate off. If we leave it on,
16132 * then on 5700_BX chips we have to enable a workaround.
16133 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16134 * to match the cacheline size. The Broadcom driver have this
16135 * workaround but turns MWI off all the times so never uses
16136 * it. This seems to suggest that the workaround is insufficient.
16137 */
16138 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16139 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16140 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16141
16821285
MC		 16142 /* Important! -- Make sure register accesses are byteswapped
16143 * correctly. Also, for those chips that require it, make
16144 * sure that indirect register accesses are enabled before
16145 * the first operation.
1da177e4
LT		 16146 */
16147 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16148 &misc_ctrl_reg);
16821285
MC		 16149 tp->misc_host_ctrl |= (misc_ctrl_reg &
16150 MISC_HOST_CTRL_CHIPREV);
16151 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16152 tp->misc_host_ctrl);
1da177e4 16153
42b123b1 16154 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 16155
6892914f
MC		 16156 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16157 * we need to disable memory and use config. cycles
16158 * only to access all registers. The 5702/03 chips
16159 * can mistakenly decode the special cycles from the
16160 * ICH chipsets as memory write cycles, causing corruption
16161 * of register and memory space. Only certain ICH bridges
16162 * will drive special cycles with non-zero data during the
16163 * address phase which can fall within the 5703's address
16164 * range. This is not an ICH bug as the PCI spec allows
16165 * non-zero address during special cycles. However, only
16166 * these ICH bridges are known to drive non-zero addresses
16167 * during special cycles.
16168 *
16169 * Since special cycles do not cross PCI bridges, we only
16170 * enable this workaround if the 5703 is on the secondary
16171 * bus of these ICH bridges.
16172 */
4153577a
JP		 16173 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16174 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 16175 static struct tg3_dev_id {
16176 u32 vendor;
16177 u32 device;
16178 u32 rev;
16179 } ich_chipsets[] = {
16180 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16181 PCI_ANY_ID },
16182 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16183 PCI_ANY_ID },
16184 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16185 0xa },
16186 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16187 PCI_ANY_ID },
16188 { },
16189 };
16190 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16191 struct pci_dev *bridge = NULL;
16192
16193 while (pci_id->vendor != 0) {
16194 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16195 bridge);
16196 if (!bridge) {
16197 pci_id++;
16198 continue;
16199 }
16200 if (pci_id->rev != PCI_ANY_ID) {
44c10138 16201 if (bridge->revision > pci_id->rev)
6892914f
MC		 16202 continue;
16203 }
16204 if (bridge->subordinate &&
16205 (bridge->subordinate->number ==
16206 tp->pdev->bus->number)) {
63c3a66f 16207 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 16208 pci_dev_put(bridge);
16209 break;
16210 }
16211 }
16212 }
16213
4153577a 16214 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 16215 static struct tg3_dev_id {
16216 u32 vendor;
16217 u32 device;
16218 } bridge_chipsets[] = {
16219 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16220 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16221 { },
16222 };
16223 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16224 struct pci_dev *bridge = NULL;
16225
16226 while (pci_id->vendor != 0) {
16227 bridge = pci_get_device(pci_id->vendor,
16228 pci_id->device,
16229 bridge);
16230 if (!bridge) {
16231 pci_id++;
16232 continue;
16233 }
16234 if (bridge->subordinate &&
16235 (bridge->subordinate->number <=
16236 tp->pdev->bus->number) &&
b918c62e 16237 (bridge->subordinate->busn_res.end >=
41588ba1 16238 tp->pdev->bus->number)) {
63c3a66f 16239 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 16240 pci_dev_put(bridge);
16241 break;
16242 }
16243 }
16244 }
16245
4a29cc2e
MC		 16246 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16247 * DMA addresses > 40-bit. This bridge may have other additional
16248 * 57xx devices behind it in some 4-port NIC designs for example.
16249 * Any tg3 device found behind the bridge will also need the 40-bit
16250 * DMA workaround.
16251 */
42b123b1 16252 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 16253 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 16254 tp->msi_cap = tp->pdev->msi_cap;
859a5887 16255 } else {
4a29cc2e
MC		 16256 struct pci_dev *bridge = NULL;
16257
16258 do {
16259 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16260 PCI_DEVICE_ID_SERVERWORKS_EPB,
16261 bridge);
16262 if (bridge && bridge->subordinate &&
16263 (bridge->subordinate->number <=
16264 tp->pdev->bus->number) &&
b918c62e 16265 (bridge->subordinate->busn_res.end >=
4a29cc2e 16266 tp->pdev->bus->number)) {
63c3a66f 16267 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 16268 pci_dev_put(bridge);
16269 break;
16270 }
16271 } while (bridge);
16272 }
4cf78e4f 16273
4153577a
JP		 16274 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16275 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16276 tp->pdev_peer = tg3_find_peer(tp);
16277
507399f1 16278 /* Determine TSO capabilities */
4153577a 16279 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16280 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16281 else if (tg3_flag(tp, 57765_PLUS))
16282 tg3_flag_set(tp, HW_TSO_3);
16283 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16284 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16285 tg3_flag_set(tp, HW_TSO_2);
16286 else if (tg3_flag(tp, 5750_PLUS)) {
16287 tg3_flag_set(tp, HW_TSO_1);
16288 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16289 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16290 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16291 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16292 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16293 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16294 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16295 tg3_flag_set(tp, FW_TSO);
16296 tg3_flag_set(tp, TSO_BUG);
4153577a 16297 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16298 tp->fw_needed = FIRMWARE_TG3TSO5;
16299 else
16300 tp->fw_needed = FIRMWARE_TG3TSO;
16301 }
16302
dabc5c67 16303 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16304 if (tg3_flag(tp, HW_TSO_1) ||
16305 tg3_flag(tp, HW_TSO_2) ||
16306 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16307 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16308 /* For firmware TSO, assume ASF is disabled.
16309 * We'll disable TSO later if we discover ASF
16310 * is enabled in tg3_get_eeprom_hw_cfg().
16311 */
dabc5c67 16312 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16313 } else {
dabc5c67
MC		 16314 tg3_flag_clear(tp, TSO_CAPABLE);
16315 tg3_flag_clear(tp, TSO_BUG);
16316 tp->fw_needed = NULL;
16317 }
16318
4153577a 16319 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16320 tp->fw_needed = FIRMWARE_TG3;
16321
c4dab506
NS		 16322 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16323 tp->fw_needed = FIRMWARE_TG357766;
16324
507399f1
MC		 16325 tp->irq_max = 1;
16326
63c3a66f
JP		 16327 if (tg3_flag(tp, 5750_PLUS)) {
16328 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16329 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16330 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16331 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16332 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16333 tp->pdev_peer == tp->pdev))
63c3a66f 16334 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16335
63c3a66f 16336 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16337 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16338 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16339 }
4f125f42 16340
63c3a66f
JP		 16341 if (tg3_flag(tp, 57765_PLUS)) {
16342 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16343 tp->irq_max = TG3_IRQ_MAX_VECS;
16344 }
f6eb9b1f 16345 }
0e1406dd 16346
9102426a
MC		 16347 tp->txq_max = 1;
16348 tp->rxq_max = 1;
16349 if (tp->irq_max > 1) {
16350 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16351 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16352
4153577a
JP		 16353 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16354 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16355 tp->txq_max = tp->irq_max - 1;
16356 }
16357
b7abee6e 16358 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16359 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16360 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16361
4153577a 16362 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16363 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16364
4153577a
JP		 16365 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16366 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16367 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16368 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16369 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16370
63c3a66f 16371 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16372 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16373 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16374
63c3a66f
JP		 16375 if (!tg3_flag(tp, 5705_PLUS) ||
16376 tg3_flag(tp, 5780_CLASS) ||
16377 tg3_flag(tp, USE_JUMBO_BDFLAG))
16378 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16379
52f4490c
MC		 16380 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16381 &pci_state_reg);
16382
708ebb3a 16383 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16384 u16 lnkctl;
16385
63c3a66f 16386 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16387
0f49bfbd 16388 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16389 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16390 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16391 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16392 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16393 }
4153577a
JP		 16394 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16395 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16396 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16397 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16398 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16399 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16400 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16401 }
4153577a 16402 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16403 /* BCM5785 devices are effectively PCIe devices, and should
16404 * follow PCIe codepaths, but do not have a PCIe capabilities
16405 * section.
93a700a9 16406 */
63c3a66f
JP		 16407 tg3_flag_set(tp, PCI_EXPRESS);
16408 } else if (!tg3_flag(tp, 5705_PLUS) ||
16409 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16410 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16411 if (!tp->pcix_cap) {
2445e461
MC		 16412 dev_err(&tp->pdev->dev,
16413 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16414 return -EIO;
16415 }
16416
16417 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16418 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16419 }
1da177e4 16420
399de50b
MC		 16421 /* If we have an AMD 762 or VIA K8T800 chipset, write
16422 * reordering to the mailbox registers done by the host
16423 * controller can cause major troubles. We read back from
16424 * every mailbox register write to force the writes to be
16425 * posted to the chip in order.
16426 */
4143470c 16427 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16428 !tg3_flag(tp, PCI_EXPRESS))
16429 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16430
69fc4053
MC		 16431 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16432 &tp->pci_cacheline_sz);
16433 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16434 &tp->pci_lat_timer);
4153577a 16435 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16436 tp->pci_lat_timer < 64) {
16437 tp->pci_lat_timer = 64;
69fc4053
MC		 16438 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16439 tp->pci_lat_timer);
1da177e4
LT		 16440 }
16441
16821285
MC		 16442 /* Important! -- It is critical that the PCI-X hw workaround
16443 * situation is decided before the first MMIO register access.
16444 */
4153577a 16445 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16446 /* 5700 BX chips need to have their TX producer index
16447 * mailboxes written twice to workaround a bug.
16448 */
63c3a66f 16449 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16450
52f4490c 16451 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16452 *
16453 * The workaround is to use indirect register accesses
16454 * for all chip writes not to mailbox registers.
16455 */
63c3a66f 16456 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16457 u32 pm_reg;
1da177e4 16458
63c3a66f 16459 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16460
16461 /* The chip can have it's power management PCI config
16462 * space registers clobbered due to this bug.
16463 * So explicitly force the chip into D0 here.
16464 */
9974a356 16465 pci_read_config_dword(tp->pdev,
0319f30e 16466 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16467 &pm_reg);
16468 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16469 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16470 pci_write_config_dword(tp->pdev,
0319f30e 16471 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16472 pm_reg);
16473
16474 /* Also, force SERR#/PERR# in PCI command. */
16475 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16476 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16477 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16478 }
16479 }
16480
1da177e4 16481 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16482 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16483 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16484 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16485
16486 /* Chip-specific fixup from Broadcom driver */
4153577a 16487 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16488 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16489 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16490 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16491 }
16492
1ee582d8 16493 /* Default fast path register access methods */
20094930 16494 tp->read32 = tg3_read32;
1ee582d8 16495 tp->write32 = tg3_write32;
09ee929c 16496 tp->read32_mbox = tg3_read32;
20094930 16497 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16498 tp->write32_tx_mbox = tg3_write32;
16499 tp->write32_rx_mbox = tg3_write32;
16500
16501 /* Various workaround register access methods */
63c3a66f 16502 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16503 tp->write32 = tg3_write_indirect_reg32;
4153577a 16504 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16505 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16506 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16507 /*
16508 * Back to back register writes can cause problems on these
16509 * chips, the workaround is to read back all reg writes
16510 * except those to mailbox regs.
16511 *
16512 * See tg3_write_indirect_reg32().
16513 */
1ee582d8 16514 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16515 }
16516
63c3a66f 16517 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16518 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16519 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16520 tp->write32_rx_mbox = tg3_write_flush_reg32;
16521 }
20094930 16522
63c3a66f 16523 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16524 tp->read32 = tg3_read_indirect_reg32;
16525 tp->write32 = tg3_write_indirect_reg32;
16526 tp->read32_mbox = tg3_read_indirect_mbox;
16527 tp->write32_mbox = tg3_write_indirect_mbox;
16528 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16529 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16530
16531 iounmap(tp->regs);
22abe310 16532 tp->regs = NULL;
6892914f
MC		 16533
16534 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16535 pci_cmd &= ~PCI_COMMAND_MEMORY;
16536 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16537 }
4153577a 16538 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16539 tp->read32_mbox = tg3_read32_mbox_5906;
16540 tp->write32_mbox = tg3_write32_mbox_5906;
16541 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16542 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16543 }
6892914f 16544
bbadf503 16545 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16546 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16547 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16548 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16549 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16550
16821285
MC		 16551 /* The memory arbiter has to be enabled in order for SRAM accesses
16552 * to succeed. Normally on powerup the tg3 chip firmware will make
16553 * sure it is enabled, but other entities such as system netboot
16554 * code might disable it.
16555 */
16556 val = tr32(MEMARB_MODE);
16557 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16558
9dc5e342 16559 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16560 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16561 tg3_flag(tp, 5780_CLASS)) {
16562 if (tg3_flag(tp, PCIX_MODE)) {
16563 pci_read_config_dword(tp->pdev,
16564 tp->pcix_cap + PCI_X_STATUS,
16565 &val);
16566 tp->pci_fn = val & 0x7;
16567 }
4153577a
JP		 16568 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16569 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16570 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16571 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16572 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16573 val = tr32(TG3_CPMU_STATUS);
16574
4153577a 16575 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16576 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16577 else
9dc5e342
MC		 16578 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16579 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16580 }
16581
7e6c63f0
HM		 16582 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16583 tp->write32_tx_mbox = tg3_write_flush_reg32;
16584 tp->write32_rx_mbox = tg3_write_flush_reg32;
16585 }
16586
7d0c41ef 16587 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16588 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16589 * determined before calling tg3_set_power_state() so that
16590 * we know whether or not to switch out of Vaux power.
16591 * When the flag is set, it means that GPIO1 is used for eeprom
16592 * write protect and also implies that it is a LOM where GPIOs
16593 * are not used to switch power.
6aa20a22 16594 */
7d0c41ef
MC		 16595 tg3_get_eeprom_hw_cfg(tp);
16596
1caf13eb 16597 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16598 tg3_flag_clear(tp, TSO_CAPABLE);
16599 tg3_flag_clear(tp, TSO_BUG);
16600 tp->fw_needed = NULL;
16601 }
16602
63c3a66f 16603 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16604 /* Allow reads and writes to the
16605 * APE register and memory space.
16606 */
16607 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16608 PCISTATE_ALLOW_APE_SHMEM_WR |
16609 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16610 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16611 pci_state_reg);
c9cab24e
MC		 16612
16613 tg3_ape_lock_init(tp);
0d3031d9
MC		 16614 }
16615
16821285
MC		 16616 /* Set up tp->grc_local_ctrl before calling
16617 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16618 * will bring 5700's external PHY out of reset.
314fba34
MC		 16619 * It is also used as eeprom write protect on LOMs.
16620 */
16621 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16622 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16623 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16624 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16625 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16626 /* Unused GPIO3 must be driven as output on 5752 because there
16627 * are no pull-up resistors on unused GPIO pins.
16628 */
4153577a 16629 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16630 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16631
4153577a
JP		 16632 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16633 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16634 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16635 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16636
8d519ab2
MC		 16637 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16638 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16639 /* Turn off the debug UART. */
16640 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16641 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16642 /* Keep VMain power. */
16643 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16644 GRC_LCLCTRL_GPIO_OUTPUT0;
16645 }
16646
4153577a 16647 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16648 tp->grc_local_ctrl |=
16649 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16650
16821285
MC		 16651 /* Switch out of Vaux if it is a NIC */
16652 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16653
1da177e4
LT		 16654 /* Derive initial jumbo mode from MTU assigned in
16655 * ether_setup() via the alloc_etherdev() call
16656 */
63c3a66f
JP		 16657 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16658 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16659
16660 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16661 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16662 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16663 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16664 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16665 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16666 } else {
63c3a66f 16667 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16668 }
16669
4153577a 16670 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16671 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16672
1da177e4 16673 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16674 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16675 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16676 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16677 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16678 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16679 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16680 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16681
4153577a
JP		 16682 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16683 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16684 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16685 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16686 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16687
63c3a66f 16688 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16689 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16690 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16691 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16692 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16693 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16694 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16695 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16696 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16697 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16698 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16699 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16700 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16701 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16702 } else
f07e9af3 16703 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16704 }
1da177e4 16705
4153577a
JP		 16706 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16707 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16708 tp->phy_otp = tg3_read_otp_phycfg(tp);
16709 if (tp->phy_otp == 0)
16710 tp->phy_otp = TG3_OTP_DEFAULT;
16711 }
16712
63c3a66f 16713 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16714 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16715 else
16716 tp->mi_mode = MAC_MI_MODE_BASE;
16717
1da177e4 16718 tp->coalesce_mode = 0;
4153577a
JP		 16719 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16720 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16721 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16722
4d958473 16723 /* Set these bits to enable statistics workaround. */
4153577a 16724 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 16725 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 16726 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16727 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16728 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16729 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16730 }
16731
4153577a
JP		 16732 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16733 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16734 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16735
158d7abd
MC		 16736 err = tg3_mdio_init(tp);
16737 if (err)
16738 return err;
1da177e4
LT		 16739
16740 /* Initialize data/descriptor byte/word swapping. */
16741 val = tr32(GRC_MODE);
4153577a
JP		 16742 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16743 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16744 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16745 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16746 GRC_MODE_B2HRX_ENABLE |
16747 GRC_MODE_HTX2B_ENABLE |
16748 GRC_MODE_HOST_STACKUP);
16749 else
16750 val &= GRC_MODE_HOST_STACKUP;
16751
1da177e4
LT		 16752 tw32(GRC_MODE, val | tp->grc_mode);
16753
16754 tg3_switch_clocks(tp);
16755
16756 /* Clear this out for sanity. */
16757 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16758
388d3335
NG		 16759 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16760 tw32(TG3PCI_REG_BASE_ADDR, 0);
16761
1da177e4
LT		 16762 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16763 &pci_state_reg);
16764 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16765 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16766 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16767 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16768 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16769 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16770 void __iomem *sram_base;
16771
16772 /* Write some dummy words into the SRAM status block
16773 * area, see if it reads back correctly. If the return
16774 * value is bad, force enable the PCIX workaround.
16775 */
16776 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16777
16778 writel(0x00000000, sram_base);
16779 writel(0x00000000, sram_base + 4);
16780 writel(0xffffffff, sram_base + 4);
16781 if (readl(sram_base) != 0x00000000)
63c3a66f 16782 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16783 }
16784 }
16785
16786 udelay(50);
16787 tg3_nvram_init(tp);
16788
c4dab506
NS		 16789 /* If the device has an NVRAM, no need to load patch firmware */
16790 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16791 !tg3_flag(tp, NO_NVRAM))
16792 tp->fw_needed = NULL;
16793
1da177e4
LT		 16794 grc_misc_cfg = tr32(GRC_MISC_CFG);
16795 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16796
4153577a 16797 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16798 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16799 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16800 tg3_flag_set(tp, IS_5788);
1da177e4 16801
63c3a66f 16802 if (!tg3_flag(tp, IS_5788) &&
4153577a 16803 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16804 tg3_flag_set(tp, TAGGED_STATUS);
16805 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16806 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16807 HOSTCC_MODE_CLRTICK_TXBD);
16808
16809 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16810 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16811 tp->misc_host_ctrl);
16812 }
16813
3bda1258 16814 /* Preserve the APE MAC_MODE bits */
63c3a66f 16815 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16816 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16817 else
6e01b20b 16818 tp->mac_mode = 0;
3bda1258 16819
3d567e0e 16820 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16821 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16822
16823 err = tg3_phy_probe(tp);
16824 if (err) {
2445e461 16825 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16826 /* ... but do not return immediately ... */
b02fd9e3 16827 tg3_mdio_fini(tp);
1da177e4
LT		 16828 }
16829
184b8904 16830 tg3_read_vpd(tp);
c4e6575c 16831 tg3_read_fw_ver(tp);
1da177e4 16832
f07e9af3
MC		 16833 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16834 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16835 } else {
4153577a 16836 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16837 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16838 else
f07e9af3 16839 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16840 }
16841
16842 /* 5700 {AX,BX} chips have a broken status block link
16843 * change bit implementation, so we must use the
16844 * status register in those cases.
16845 */
4153577a 16846 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16847 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16848 else
63c3a66f 16849 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16850
16851 /* The led_ctrl is set during tg3_phy_probe, here we might
16852 * have to force the link status polling mechanism based
16853 * upon subsystem IDs.
16854 */
16855 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16856 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16857 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16858 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16859 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16860 }
16861
16862 /* For all SERDES we poll the MAC status register. */
f07e9af3 16863 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16864 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16865 else
63c3a66f 16866 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16867
1743b83c
NS		 16868 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16869 tg3_flag_set(tp, POLL_CPMU_LINK);
16870
9205fd9c 16871 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16872 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16873 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16874 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16875 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16876#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16877 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16878#endif
16879 }
1da177e4 16880
2c49a44d
MC		 16881 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16882 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16883 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16884
2c49a44d 16885 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16886
16887 /* Increment the rx prod index on the rx std ring by at most
16888 * 8 for these chips to workaround hw errata.
16889 */
4153577a
JP		 16890 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16891 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16892 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16893 tp->rx_std_max_post = 8;
16894
63c3a66f 16895 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16896 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16897 PCIE_PWR_MGMT_L1_THRESH_MSK;
16898
1da177e4
LT		 16899 return err;
16900}
16901
49b6e95f 16902#ifdef CONFIG_SPARC
229b1ad1 16903static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16904{
16905 struct net_device *dev = tp->dev;
16906 struct pci_dev *pdev = tp->pdev;
49b6e95f 16907 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16908 const unsigned char *addr;
49b6e95f
DM		 16909 int len;
16910
16911 addr = of_get_property(dp, "local-mac-address", &len);
d458cdf7
JP		 16912 if (addr && len == ETH_ALEN) {
16913 memcpy(dev->dev_addr, addr, ETH_ALEN);
49b6e95f 16914 return 0;
1da177e4
LT		 16915 }
16916 return -ENODEV;
16917}
16918
229b1ad1 16919static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16920{
16921 struct net_device *dev = tp->dev;
16922
d458cdf7 16923 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
1da177e4
LT		 16924 return 0;
16925}
16926#endif
16927
229b1ad1 16928static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16929{
16930 struct net_device *dev = tp->dev;
16931 u32 hi, lo, mac_offset;
008652b3 16932 int addr_ok = 0;
7e6c63f0 16933 int err;
1da177e4 16934
49b6e95f 16935#ifdef CONFIG_SPARC
1da177e4
LT		 16936 if (!tg3_get_macaddr_sparc(tp))
16937 return 0;
16938#endif
16939
7e6c63f0
HM		 16940 if (tg3_flag(tp, IS_SSB_CORE)) {
16941 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16942 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16943 return 0;
16944 }
16945
1da177e4 16946 mac_offset = 0x7c;
4153577a 16947 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16948 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16949 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16950 mac_offset = 0xcc;
16951 if (tg3_nvram_lock(tp))
16952 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16953 else
16954 tg3_nvram_unlock(tp);
63c3a66f 16955 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16956 if (tp->pci_fn & 1)
a1b950d5 16957 mac_offset = 0xcc;
69f11c99 16958 if (tp->pci_fn > 1)
a50d0796 16959 mac_offset += 0x18c;
4153577a 16960 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16961 mac_offset = 0x10;
1da177e4
LT		 16962
16963 /* First try to get it from MAC address mailbox. */
16964 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16965 if ((hi >> 16) == 0x484b) {
16966 dev->dev_addr[0] = (hi >> 8) & 0xff;
16967 dev->dev_addr[1] = (hi >> 0) & 0xff;
16968
16969 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16970 dev->dev_addr[2] = (lo >> 24) & 0xff;
16971 dev->dev_addr[3] = (lo >> 16) & 0xff;
16972 dev->dev_addr[4] = (lo >> 8) & 0xff;
16973 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16974
008652b3
MC		 16975 /* Some old bootcode may report a 0 MAC address in SRAM */
16976 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16977 }
16978 if (!addr_ok) {
16979 /* Next, try NVRAM. */
63c3a66f 16980 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16981 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16982 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16983 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16984 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16985 }
16986 /* Finally just fetch it out of the MAC control regs. */
16987 else {
16988 hi = tr32(MAC_ADDR_0_HIGH);
16989 lo = tr32(MAC_ADDR_0_LOW);
16990
16991 dev->dev_addr[5] = lo & 0xff;
16992 dev->dev_addr[4] = (lo >> 8) & 0xff;
16993 dev->dev_addr[3] = (lo >> 16) & 0xff;
16994 dev->dev_addr[2] = (lo >> 24) & 0xff;
16995 dev->dev_addr[1] = hi & 0xff;
16996 dev->dev_addr[0] = (hi >> 8) & 0xff;
16997 }
1da177e4
LT		 16998 }
16999
17000 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 17001#ifdef CONFIG_SPARC
1da177e4
LT		 17002 if (!tg3_get_default_macaddr_sparc(tp))
17003 return 0;
17004#endif
17005 return -EINVAL;
17006 }
17007 return 0;
17008}
17009
59e6b434
DM		 17010#define BOUNDARY_SINGLE_CACHELINE 1
17011#define BOUNDARY_MULTI_CACHELINE 2
17012
229b1ad1 17013static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 17014{
17015 int cacheline_size;
17016 u8 byte;
17017 int goal;
17018
17019 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17020 if (byte == 0)
17021 cacheline_size = 1024;
17022 else
17023 cacheline_size = (int) byte * 4;
17024
17025 /* On 5703 and later chips, the boundary bits have no
17026 * effect.
17027 */
4153577a
JP		 17028 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17029 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 17030 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 17031 goto out;
17032
17033#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17034 goal = BOUNDARY_MULTI_CACHELINE;
17035#else
17036#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17037 goal = BOUNDARY_SINGLE_CACHELINE;
17038#else
17039 goal = 0;
17040#endif
17041#endif
17042
63c3a66f 17043 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 17044 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17045 goto out;
17046 }
17047
59e6b434
DM		 17048 if (!goal)
17049 goto out;
17050
17051 /* PCI controllers on most RISC systems tend to disconnect
17052 * when a device tries to burst across a cache-line boundary.
17053 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17054 *
17055 * Unfortunately, for PCI-E there are only limited
17056 * write-side controls for this, and thus for reads
17057 * we will still get the disconnects. We'll also waste
17058 * these PCI cycles for both read and write for chips
17059 * other than 5700 and 5701 which do not implement the
17060 * boundary bits.
17061 */
63c3a66f 17062 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 17063 switch (cacheline_size) {
17064 case 16:
17065 case 32:
17066 case 64:
17067 case 128:
17068 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17069 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17070 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17071 } else {
17072 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17073 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17074 }
17075 break;
17076
17077 case 256:
17078 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17079 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17080 break;
17081
17082 default:
17083 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17084 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17085 break;
855e1111 17086 }
63c3a66f 17087 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 17088 switch (cacheline_size) {
17089 case 16:
17090 case 32:
17091 case 64:
17092 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17093 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17094 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17095 break;
17096 }
17097 /* fallthrough */
17098 case 128:
17099 default:
17100 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17101 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17102 break;
855e1111 17103 }
59e6b434
DM		 17104 } else {
17105 switch (cacheline_size) {
17106 case 16:
17107 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17108 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17109 DMA_RWCTRL_WRITE_BNDRY_16);
17110 break;
17111 }
17112 /* fallthrough */
17113 case 32:
17114 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17115 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17116 DMA_RWCTRL_WRITE_BNDRY_32);
17117 break;
17118 }
17119 /* fallthrough */
17120 case 64:
17121 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17122 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17123 DMA_RWCTRL_WRITE_BNDRY_64);
17124 break;
17125 }
17126 /* fallthrough */
17127 case 128:
17128 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17129 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17130 DMA_RWCTRL_WRITE_BNDRY_128);
17131 break;
17132 }
17133 /* fallthrough */
17134 case 256:
17135 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17136 DMA_RWCTRL_WRITE_BNDRY_256);
17137 break;
17138 case 512:
17139 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17140 DMA_RWCTRL_WRITE_BNDRY_512);
17141 break;
17142 case 1024:
17143 default:
17144 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17145 DMA_RWCTRL_WRITE_BNDRY_1024);
17146 break;
855e1111 17147 }
59e6b434
DM		 17148 }
17149
17150out:
17151 return val;
17152}
17153
229b1ad1 17154static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 17155 int size, bool to_device)
1da177e4
LT		 17156{
17157 struct tg3_internal_buffer_desc test_desc;
17158 u32 sram_dma_descs;
17159 int i, ret;
17160
17161 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17162
17163 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17164 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17165 tw32(RDMAC_STATUS, 0);
17166 tw32(WDMAC_STATUS, 0);
17167
17168 tw32(BUFMGR_MODE, 0);
17169 tw32(FTQ_RESET, 0);
17170
17171 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17172 test_desc.addr_lo = buf_dma & 0xffffffff;
17173 test_desc.nic_mbuf = 0x00002100;
17174 test_desc.len = size;
17175
17176 /*
17177 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17178 * the *second* time the tg3 driver was getting loaded after an
17179 * initial scan.
17180 *
17181 * Broadcom tells me:
17182 * ...the DMA engine is connected to the GRC block and a DMA
17183 * reset may affect the GRC block in some unpredictable way...
17184 * The behavior of resets to individual blocks has not been tested.
17185 *
17186 * Broadcom noted the GRC reset will also reset all sub-components.
17187 */
17188 if (to_device) {
17189 test_desc.cqid_sqid = (13 << 8) | 2;
17190
17191 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17192 udelay(40);
17193 } else {
17194 test_desc.cqid_sqid = (16 << 8) | 7;
17195
17196 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17197 udelay(40);
17198 }
17199 test_desc.flags = 0x00000005;
17200
17201 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17202 u32 val;
17203
17204 val = *(((u32 *)&test_desc) + i);
17205 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17206 sram_dma_descs + (i * sizeof(u32)));
17207 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17208 }
17209 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17210
859a5887 17211 if (to_device)
1da177e4 17212 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 17213 else
1da177e4 17214 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 17215
17216 ret = -ENODEV;
17217 for (i = 0; i < 40; i++) {
17218 u32 val;
17219
17220 if (to_device)
17221 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17222 else
17223 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17224 if ((val & 0xffff) == sram_dma_descs) {
17225 ret = 0;
17226 break;
17227 }
17228
17229 udelay(100);
17230 }
17231
17232 return ret;
17233}
17234
ded7340d 17235#define TEST_BUFFER_SIZE 0x2000
1da177e4 17236
9baa3c34 17237static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
895950c2
JP		 17238 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17239 { },
17240};
17241
229b1ad1 17242static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 17243{
17244 dma_addr_t buf_dma;
59e6b434 17245 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 17246 int ret = 0;
1da177e4 17247
4bae65c8
MC		 17248 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17249 &buf_dma, GFP_KERNEL);
1da177e4
LT		 17250 if (!buf) {
17251 ret = -ENOMEM;
17252 goto out_nofree;
17253 }
17254
17255 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17256 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17257
59e6b434 17258 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 17259
63c3a66f 17260 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 17261 goto out;
17262
63c3a66f 17263 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 17264 /* DMA read watermark not used on PCIE */
17265 tp->dma_rwctrl |= 0x00180000;
63c3a66f 17266 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 17267 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17268 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 17269 tp->dma_rwctrl |= 0x003f0000;
17270 else
17271 tp->dma_rwctrl |= 0x003f000f;
17272 } else {
4153577a
JP		 17273 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17274 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 17275 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 17276 u32 read_water = 0x7;
1da177e4 17277
4a29cc2e
MC		 17278 /* If the 5704 is behind the EPB bridge, we can
17279 * do the less restrictive ONE_DMA workaround for
17280 * better performance.
17281 */
63c3a66f 17282 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17283 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17284 tp->dma_rwctrl |= 0x8000;
17285 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17286 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17287
4153577a 17288 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17289 read_water = 4;
59e6b434 17290 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17291 tp->dma_rwctrl |=
17292 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17293 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17294 (1 << 23);
4153577a 17295 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17296 /* 5780 always in PCIX mode */
17297 tp->dma_rwctrl |= 0x00144000;
4153577a 17298 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17299 /* 5714 always in PCIX mode */
17300 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17301 } else {
17302 tp->dma_rwctrl |= 0x001b000f;
17303 }
17304 }
7e6c63f0
HM		 17305 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17306 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17307
4153577a
JP		 17308 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17309 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17310 tp->dma_rwctrl &= 0xfffffff0;
17311
4153577a
JP		 17312 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17313 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17314 /* Remove this if it causes problems for some boards. */
17315 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17316
17317 /* On 5700/5701 chips, we need to set this bit.
17318 * Otherwise the chip will issue cacheline transactions
17319 * to streamable DMA memory with not all the byte
17320 * enables turned on. This is an error on several
17321 * RISC PCI controllers, in particular sparc64.
17322 *
17323 * On 5703/5704 chips, this bit has been reassigned
17324 * a different meaning. In particular, it is used
17325 * on those chips to enable a PCI-X workaround.
17326 */
17327 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17328 }
17329
17330 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17331
1da177e4 17332
4153577a
JP		 17333 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17334 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17335 goto out;
17336
59e6b434
DM		 17337 /* It is best to perform DMA test with maximum write burst size
17338 * to expose the 5700/5701 write DMA bug.
17339 */
17340 saved_dma_rwctrl = tp->dma_rwctrl;
17341 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17342 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17343
1da177e4
LT		 17344 while (1) {
17345 u32 *p = buf, i;
17346
17347 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17348 p[i] = i;
17349
17350 /* Send the buffer to the chip. */
953c96e0 17351 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17352 if (ret) {
2445e461
MC		 17353 dev_err(&tp->pdev->dev,
17354 "%s: Buffer write failed. err = %d\n",
17355 __func__, ret);
1da177e4
LT		 17356 break;
17357 }
17358
1da177e4 17359 /* Now read it back. */
953c96e0 17360 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17361 if (ret) {
5129c3a3
MC		 17362 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17363 "err = %d\n", __func__, ret);
1da177e4
LT		 17364 break;
17365 }
17366
17367 /* Verify it. */
17368 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17369 if (p[i] == i)
17370 continue;
17371
59e6b434
DM		 17372 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17373 DMA_RWCTRL_WRITE_BNDRY_16) {
17374 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17375 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17376 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17377 break;
17378 } else {
2445e461
MC		 17379 dev_err(&tp->pdev->dev,
17380 "%s: Buffer corrupted on read back! "
17381 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17382 ret = -ENODEV;
17383 goto out;
17384 }
17385 }
17386
17387 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17388 /* Success. */
17389 ret = 0;
17390 break;
17391 }
17392 }
59e6b434
DM		 17393 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17394 DMA_RWCTRL_WRITE_BNDRY_16) {
17395 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17396 * now look for chipsets that are known to expose the
17397 * DMA bug without failing the test.
59e6b434 17398 */
4143470c 17399 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17400 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17401 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17402 } else {
6d1cfbab
MC		 17403 /* Safe to use the calculated DMA boundary. */
17404 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17405 }
6d1cfbab 17406
59e6b434
DM		 17407 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17408 }
1da177e4
LT		 17409
17410out:
4bae65c8 17411 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17412out_nofree:
17413 return ret;
17414}
17415
229b1ad1 17416static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17417{
63c3a66f 17418 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17419 tp->bufmgr_config.mbuf_read_dma_low_water =
17420 DEFAULT_MB_RDMA_LOW_WATER_5705;
17421 tp->bufmgr_config.mbuf_mac_rx_low_water =
17422 DEFAULT_MB_MACRX_LOW_WATER_57765;
17423 tp->bufmgr_config.mbuf_high_water =
17424 DEFAULT_MB_HIGH_WATER_57765;
17425
17426 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17427 DEFAULT_MB_RDMA_LOW_WATER_5705;
17428 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17429 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17430 tp->bufmgr_config.mbuf_high_water_jumbo =
17431 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17432 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17433 tp->bufmgr_config.mbuf_read_dma_low_water =
17434 DEFAULT_MB_RDMA_LOW_WATER_5705;
17435 tp->bufmgr_config.mbuf_mac_rx_low_water =
17436 DEFAULT_MB_MACRX_LOW_WATER_5705;
17437 tp->bufmgr_config.mbuf_high_water =
17438 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17439 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17440 tp->bufmgr_config.mbuf_mac_rx_low_water =
17441 DEFAULT_MB_MACRX_LOW_WATER_5906;
17442 tp->bufmgr_config.mbuf_high_water =
17443 DEFAULT_MB_HIGH_WATER_5906;
17444 }
fdfec172
MC		 17445
17446 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17447 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17448 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17449 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17450 tp->bufmgr_config.mbuf_high_water_jumbo =
17451 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17452 } else {
17453 tp->bufmgr_config.mbuf_read_dma_low_water =
17454 DEFAULT_MB_RDMA_LOW_WATER;
17455 tp->bufmgr_config.mbuf_mac_rx_low_water =
17456 DEFAULT_MB_MACRX_LOW_WATER;
17457 tp->bufmgr_config.mbuf_high_water =
17458 DEFAULT_MB_HIGH_WATER;
17459
17460 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17461 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17462 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17463 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17464 tp->bufmgr_config.mbuf_high_water_jumbo =
17465 DEFAULT_MB_HIGH_WATER_JUMBO;
17466 }
1da177e4
LT		 17467
17468 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17469 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17470}
17471
229b1ad1 17472static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17473{
79eb6904
MC		 17474 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17475 case TG3_PHY_ID_BCM5400: return "5400";
17476 case TG3_PHY_ID_BCM5401: return "5401";
17477 case TG3_PHY_ID_BCM5411: return "5411";
17478 case TG3_PHY_ID_BCM5701: return "5701";
17479 case TG3_PHY_ID_BCM5703: return "5703";
17480 case TG3_PHY_ID_BCM5704: return "5704";
17481 case TG3_PHY_ID_BCM5705: return "5705";
17482 case TG3_PHY_ID_BCM5750: return "5750";
17483 case TG3_PHY_ID_BCM5752: return "5752";
17484 case TG3_PHY_ID_BCM5714: return "5714";
17485 case TG3_PHY_ID_BCM5780: return "5780";
17486 case TG3_PHY_ID_BCM5755: return "5755";
17487 case TG3_PHY_ID_BCM5787: return "5787";
17488 case TG3_PHY_ID_BCM5784: return "5784";
17489 case TG3_PHY_ID_BCM5756: return "5722/5756";
17490 case TG3_PHY_ID_BCM5906: return "5906";
17491 case TG3_PHY_ID_BCM5761: return "5761";
17492 case TG3_PHY_ID_BCM5718C: return "5718C";
17493 case TG3_PHY_ID_BCM5718S: return "5718S";
17494 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17495 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17496 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17497 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17498 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17499 case 0: return "serdes";
17500 default: return "unknown";
855e1111 17501 }
1da177e4
LT		 17502}
17503
229b1ad1 17504static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17505{
63c3a66f 17506 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17507 strcpy(str, "PCI Express");
17508 return str;
63c3a66f 17509 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17510 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17511
17512 strcpy(str, "PCIX:");
17513
17514 if ((clock_ctrl == 7) ||
17515 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17516 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17517 strcat(str, "133MHz");
17518 else if (clock_ctrl == 0)
17519 strcat(str, "33MHz");
17520 else if (clock_ctrl == 2)
17521 strcat(str, "50MHz");
17522 else if (clock_ctrl == 4)
17523 strcat(str, "66MHz");
17524 else if (clock_ctrl == 6)
17525 strcat(str, "100MHz");
f9804ddb
MC		 17526 } else {
17527 strcpy(str, "PCI:");
63c3a66f 17528 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17529 strcat(str, "66MHz");
17530 else
17531 strcat(str, "33MHz");
17532 }
63c3a66f 17533 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17534 strcat(str, ":32-bit");
17535 else
17536 strcat(str, ":64-bit");
17537 return str;
17538}
17539
229b1ad1 17540static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17541{
17542 struct ethtool_coalesce *ec = &tp->coal;
17543
17544 memset(ec, 0, sizeof(*ec));
17545 ec->cmd = ETHTOOL_GCOALESCE;
17546 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17547 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17548 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17549 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17550 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17551 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17552 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17553 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17554 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17555
17556 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17557 HOSTCC_MODE_CLRTICK_TXBD)) {
17558 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17559 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17560 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17561 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17562 }
d244c892 17563
63c3a66f 17564 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17565 ec->rx_coalesce_usecs_irq = 0;
17566 ec->tx_coalesce_usecs_irq = 0;
17567 ec->stats_block_coalesce_usecs = 0;
17568 }
15f9850d
DM		 17569}
17570
229b1ad1 17571static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17572 const struct pci_device_id *ent)
17573{
1da177e4
LT		 17574 struct net_device *dev;
17575 struct tg3 *tp;
5865fc1b 17576 int i, err;
646c9edd 17577 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17578 char str[40];
72f2afb8 17579 u64 dma_mask, persist_dma_mask;
c8f44aff 17580 netdev_features_t features = 0;
1da177e4 17581
05dbe005 17582 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17583
17584 err = pci_enable_device(pdev);
17585 if (err) {
2445e461 17586 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17587 return err;
17588 }
17589
1da177e4
LT		 17590 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17591 if (err) {
2445e461 17592 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17593 goto err_out_disable_pdev;
17594 }
17595
17596 pci_set_master(pdev);
17597
fe5f5787 17598 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17599 if (!dev) {
1da177e4 17600 err = -ENOMEM;
5865fc1b 17601 goto err_out_free_res;
1da177e4
LT		 17602 }
17603
1da177e4
LT		 17604 SET_NETDEV_DEV(dev, &pdev->dev);
17605
1da177e4
LT		 17606 tp = netdev_priv(dev);
17607 tp->pdev = pdev;
17608 tp->dev = dev;
1da177e4
LT		 17609 tp->rx_mode = TG3_DEF_RX_MODE;
17610 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17611 tp->irq_sync = 1;
0486a063 17612 tp->pcierr_recovery = false;
8ef21428 17613
1da177e4
LT		 17614 if (tg3_debug > 0)
17615 tp->msg_enable = tg3_debug;
17616 else
17617 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17618
7e6c63f0
HM		 17619 if (pdev_is_ssb_gige_core(pdev)) {
17620 tg3_flag_set(tp, IS_SSB_CORE);
17621 if (ssb_gige_must_flush_posted_writes(pdev))
17622 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17623 if (ssb_gige_one_dma_at_once(pdev))
17624 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
ee002b64
HM		 17625 if (ssb_gige_have_roboswitch(pdev)) {
17626 tg3_flag_set(tp, USE_PHYLIB);
7e6c63f0 17627 tg3_flag_set(tp, ROBOSWITCH);
ee002b64 17628 }
7e6c63f0
HM		 17629 if (ssb_gige_is_rgmii(pdev))
17630 tg3_flag_set(tp, RGMII_MODE);
17631 }
17632
1da177e4
LT		 17633 /* The word/byte swap controls here control register access byte
17634 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17635 * setting below.
17636 */
17637 tp->misc_host_ctrl =
17638 MISC_HOST_CTRL_MASK_PCI_INT |
17639 MISC_HOST_CTRL_WORD_SWAP |
17640 MISC_HOST_CTRL_INDIR_ACCESS |
17641 MISC_HOST_CTRL_PCISTATE_RW;
17642
17643 /* The NONFRM (non-frame) byte/word swap controls take effect
17644 * on descriptor entries, anything which isn't packet data.
17645 *
17646 * The StrongARM chips on the board (one for tx, one for rx)
17647 * are running in big-endian mode.
17648 */
17649 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17650 GRC_MODE_WSWAP_NONFRM_DATA);
17651#ifdef __BIG_ENDIAN
17652 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17653#endif
17654 spin_lock_init(&tp->lock);
1da177e4 17655 spin_lock_init(&tp->indirect_lock);
c4028958 17656 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17657
d5fe488a 17658 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17659 if (!tp->regs) {
ab96b241 17660 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17661 err = -ENOMEM;
17662 goto err_out_free_dev;
17663 }
17664
c9cab24e
MC		 17665 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17666 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17667 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17668 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17669 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17670 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17671 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17672 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 17673 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 17674 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17675 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 17676 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17677 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 17678 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17679 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
c9cab24e
MC		 17680 tg3_flag_set(tp, ENABLE_APE);
17681 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17682 if (!tp->aperegs) {
17683 dev_err(&pdev->dev,
17684 "Cannot map APE registers, aborting\n");
17685 err = -ENOMEM;
17686 goto err_out_iounmap;
17687 }
17688 }
17689
1da177e4
LT		 17690 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17691 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17692
1da177e4 17693 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17694 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17695 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17696 dev->irq = pdev->irq;
1da177e4 17697
3d567e0e 17698 err = tg3_get_invariants(tp, ent);
1da177e4 17699 if (err) {
ab96b241
MC		 17700 dev_err(&pdev->dev,
17701 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17702 goto err_out_apeunmap;
1da177e4
LT		 17703 }
17704
4a29cc2e
MC		 17705 /* The EPB bridge inside 5714, 5715, and 5780 and any
17706 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17707 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17708 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17709 * do DMA address check in tg3_start_xmit().
17710 */
63c3a66f 17711 if (tg3_flag(tp, IS_5788))
284901a9 17712 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17713 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17714 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17715#ifdef CONFIG_HIGHMEM
6a35528a 17716 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17717#endif
4a29cc2e 17718 } else
6a35528a 17719 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17720
17721 /* Configure DMA attributes. */
284901a9 17722 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17723 err = pci_set_dma_mask(pdev, dma_mask);
17724 if (!err) {
0da0606f 17725 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17726 err = pci_set_consistent_dma_mask(pdev,
17727 persist_dma_mask);
17728 if (err < 0) {
ab96b241
MC		 17729 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17730 "DMA for consistent allocations\n");
c9cab24e 17731 goto err_out_apeunmap;
72f2afb8
MC		 17732 }
17733 }
17734 }
284901a9
YH		 17735 if (err || dma_mask == DMA_BIT_MASK(32)) {
17736 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17737 if (err) {
ab96b241
MC		 17738 dev_err(&pdev->dev,
17739 "No usable DMA configuration, aborting\n");
c9cab24e 17740 goto err_out_apeunmap;
72f2afb8
MC		 17741 }
17742 }
17743
fdfec172 17744 tg3_init_bufmgr_config(tp);
1da177e4 17745
0da0606f
MC		 17746 /* 5700 B0 chips do not support checksumming correctly due
17747 * to hardware bugs.
17748 */
4153577a 17749 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17750 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17751
17752 if (tg3_flag(tp, 5755_PLUS))
17753 features |= NETIF_F_IPV6_CSUM;
17754 }
17755
4e3a7aaa
MC		 17756 /* TSO is on by default on chips that support hardware TSO.
17757 * Firmware TSO on older chips gives lower performance, so it
17758 * is off by default, but can be enabled using ethtool.
17759 */
63c3a66f
JP		 17760 if ((tg3_flag(tp, HW_TSO_1) ||
17761 tg3_flag(tp, HW_TSO_2) ||
17762 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17763 (features & NETIF_F_IP_CSUM))
17764 features |= NETIF_F_TSO;
63c3a66f 17765 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17766 if (features & NETIF_F_IPV6_CSUM)
17767 features |= NETIF_F_TSO6;
63c3a66f 17768 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17769 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17770 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17771 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17772 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17773 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17774 features |= NETIF_F_TSO_ECN;
b0026624 17775 }
1da177e4 17776
51dfe7b9
VY		 17777 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17778 NETIF_F_HW_VLAN_CTAG_RX;
d542fe27
MC		 17779 dev->vlan_features |= features;
17780
06c03c02
MB		 17781 /*
17782 * Add loopback capability only for a subset of devices that support
17783 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17784 * loopback for the remaining devices.
17785 */
4153577a 17786 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17787 !tg3_flag(tp, CPMU_PRESENT))
17788 /* Add the loopback capability */
0da0606f
MC		 17789 features |= NETIF_F_LOOPBACK;
17790
0da0606f 17791 dev->hw_features |= features;
e565eec3 17792 dev->priv_flags |= IFF_UNICAST_FLT;
06c03c02 17793
4153577a 17794 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17795 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17796 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17797 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17798 tp->rx_pending = 63;
17799 }
17800
1da177e4
LT		 17801 err = tg3_get_device_address(tp);
17802 if (err) {
ab96b241
MC		 17803 dev_err(&pdev->dev,
17804 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17805 goto err_out_apeunmap;
c88864df
MC		 17806 }
17807
78f90dcf
MC		 17808 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17809 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17810 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17811 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17812 struct tg3_napi *tnapi = &tp->napi[i];
17813
17814 tnapi->tp = tp;
17815 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17816
17817 tnapi->int_mbox = intmbx;
93a700a9 17818 if (i <= 4)
78f90dcf
MC		 17819 intmbx += 0x8;
17820 else
17821 intmbx += 0x4;
17822
17823 tnapi->consmbox = rcvmbx;
17824 tnapi->prodmbox = sndmbx;
17825
66cfd1bd 17826 if (i)
78f90dcf 17827 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17828 else
78f90dcf 17829 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17830
63c3a66f 17831 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17832 break;
17833
17834 /*
17835 * If we support MSIX, we'll be using RSS. If we're using
17836 * RSS, the first vector only handles link interrupts and the
17837 * remaining vectors handle rx and tx interrupts. Reuse the
17838 * mailbox values for the next iteration. The values we setup
17839 * above are still useful for the single vectored mode.
17840 */
17841 if (!i)
17842 continue;
17843
17844 rcvmbx += 0x8;
17845
17846 if (sndmbx & 0x4)
17847 sndmbx -= 0x4;
17848 else
17849 sndmbx += 0xc;
17850 }
17851
05b0aa57
PS		 17852 /*
17853 * Reset chip in case UNDI or EFI driver did not shutdown
17854 * DMA self test will enable WDMAC and we'll see (spurious)
17855 * pending DMA on the PCI bus at that point.
17856 */
17857 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17858 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17859 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17860 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17861 }
17862
17863 err = tg3_test_dma(tp);
17864 if (err) {
17865 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17866 goto err_out_apeunmap;
17867 }
17868
15f9850d
DM		 17869 tg3_init_coal(tp);
17870
c49a1561
MC		 17871 pci_set_drvdata(pdev, dev);
17872
4153577a
JP		 17873 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17874 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17875 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17876 tg3_flag_set(tp, PTP_CAPABLE);
17877
21f7638e
MC		 17878 tg3_timer_init(tp);
17879
402e1398
MC		 17880 tg3_carrier_off(tp);
17881
1da177e4
LT		 17882 err = register_netdev(dev);
17883 if (err) {
ab96b241 17884 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17885 goto err_out_apeunmap;
1da177e4
LT		 17886 }
17887
05dbe005
JP		 17888 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17889 tp->board_part_number,
4153577a 17890 tg3_chip_rev_id(tp),
05dbe005
JP		 17891 tg3_bus_string(tp, str),
17892 dev->dev_addr);
1da177e4 17893
f07e9af3 17894 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 17895 struct phy_device *phydev;
ead2402c 17896 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
5129c3a3
MC		 17897 netdev_info(dev,
17898 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17899 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17900 } else {
17901 char *ethtype;
17902
17903 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17904 ethtype = "10/100Base-TX";
17905 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17906 ethtype = "1000Base-SX";
17907 else
17908 ethtype = "10/100/1000Base-T";
17909
5129c3a3 17910 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17911 "(WireSpeed[%d], EEE[%d])\n",
17912 tg3_phy_string(tp), ethtype,
17913 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17914 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17915 }
05dbe005
JP		 17916
17917 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17918 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17919 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17920 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17921 tg3_flag(tp, ENABLE_ASF) != 0,
17922 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17923 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17924 tp->dma_rwctrl,
17925 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17926 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17927
b45aa2f6
MC		 17928 pci_save_state(pdev);
17929
1da177e4
LT		 17930 return 0;
17931
0d3031d9
MC		 17932err_out_apeunmap:
17933 if (tp->aperegs) {
17934 iounmap(tp->aperegs);
17935 tp->aperegs = NULL;
17936 }
17937
1da177e4 17938err_out_iounmap:
6892914f
MC		 17939 if (tp->regs) {
17940 iounmap(tp->regs);
22abe310 17941 tp->regs = NULL;
6892914f 17942 }
1da177e4
LT		 17943
17944err_out_free_dev:
17945 free_netdev(dev);
17946
17947err_out_free_res:
17948 pci_release_regions(pdev);
17949
17950err_out_disable_pdev:
c80dc13d
GS		 17951 if (pci_is_enabled(pdev))
17952 pci_disable_device(pdev);
1da177e4
LT		 17953 return err;
17954}
17955
229b1ad1 17956static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17957{
17958 struct net_device *dev = pci_get_drvdata(pdev);
17959
17960 if (dev) {
17961 struct tg3 *tp = netdev_priv(dev);
17962
e3c5530b 17963 release_firmware(tp->fw);
077f849d 17964
db219973 17965 tg3_reset_task_cancel(tp);
158d7abd 17966
e730c823 17967 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17968 tg3_phy_fini(tp);
158d7abd 17969 tg3_mdio_fini(tp);
b02fd9e3 17970 }
158d7abd 17971
1da177e4 17972 unregister_netdev(dev);
0d3031d9
MC		 17973 if (tp->aperegs) {
17974 iounmap(tp->aperegs);
17975 tp->aperegs = NULL;
17976 }
6892914f
MC		 17977 if (tp->regs) {
17978 iounmap(tp->regs);
22abe310 17979 tp->regs = NULL;
6892914f 17980 }
1da177e4
LT		 17981 free_netdev(dev);
17982 pci_release_regions(pdev);
17983 pci_disable_device(pdev);
1da177e4
LT		 17984 }
17985}
17986
aa6027ca 17987#ifdef CONFIG_PM_SLEEP
c866b7ea 17988static int tg3_suspend(struct device *device)
1da177e4 17989{
c866b7ea 17990 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17991 struct net_device *dev = pci_get_drvdata(pdev);
17992 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17993 int err = 0;
17994
17995 rtnl_lock();
1da177e4
LT		 17996
17997 if (!netif_running(dev))
8496e85c 17998 goto unlock;
1da177e4 17999
db219973 18000 tg3_reset_task_cancel(tp);
b02fd9e3 18001 tg3_phy_stop(tp);
1da177e4
LT		 18002 tg3_netif_stop(tp);
18003
21f7638e 18004 tg3_timer_stop(tp);
1da177e4 18005
f47c11ee 18006 tg3_full_lock(tp, 1);
1da177e4 18007 tg3_disable_ints(tp);
f47c11ee 18008 tg3_full_unlock(tp);
1da177e4
LT		 18009
18010 netif_device_detach(dev);
18011
f47c11ee 18012 tg3_full_lock(tp, 0);
944d980e 18013 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 18014 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 18015 tg3_full_unlock(tp);
1da177e4 18016
c866b7ea 18017 err = tg3_power_down_prepare(tp);
1da177e4 18018 if (err) {
b02fd9e3
MC		 18019 int err2;
18020
f47c11ee 18021 tg3_full_lock(tp, 0);
1da177e4 18022
63c3a66f 18023 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 18024 err2 = tg3_restart_hw(tp, true);
b02fd9e3 18025 if (err2)
b9ec6c1b 18026 goto out;
1da177e4 18027
21f7638e 18028 tg3_timer_start(tp);
1da177e4
LT		 18029
18030 netif_device_attach(dev);
18031 tg3_netif_start(tp);
18032
b9ec6c1b 18033out:
f47c11ee 18034 tg3_full_unlock(tp);
b02fd9e3
MC		 18035
18036 if (!err2)
18037 tg3_phy_start(tp);
1da177e4
LT		 18038 }
18039
8496e85c
RW		 18040unlock:
18041 rtnl_unlock();
1da177e4
LT		 18042 return err;
18043}
18044
c866b7ea 18045static int tg3_resume(struct device *device)
1da177e4 18046{
c866b7ea 18047 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 18048 struct net_device *dev = pci_get_drvdata(pdev);
18049 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 18050 int err = 0;
18051
18052 rtnl_lock();
1da177e4
LT		 18053
18054 if (!netif_running(dev))
8496e85c 18055 goto unlock;
1da177e4 18056
1da177e4
LT		 18057 netif_device_attach(dev);
18058
f47c11ee 18059 tg3_full_lock(tp, 0);
1da177e4 18060
2e460fc0
NS		 18061 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18062
63c3a66f 18063 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 18064 err = tg3_restart_hw(tp,
18065 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 18066 if (err)
18067 goto out;
1da177e4 18068
21f7638e 18069 tg3_timer_start(tp);
1da177e4 18070
1da177e4
LT		 18071 tg3_netif_start(tp);
18072
b9ec6c1b 18073out:
f47c11ee 18074 tg3_full_unlock(tp);
1da177e4 18075
b02fd9e3
MC		 18076 if (!err)
18077 tg3_phy_start(tp);
18078
8496e85c
RW		 18079unlock:
18080 rtnl_unlock();
b9ec6c1b 18081 return err;
1da177e4 18082}
42df36a6 18083#endif /* CONFIG_PM_SLEEP */
1da177e4 18084
c866b7ea
RW		 18085static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18086
4c305fa2
NS		 18087static void tg3_shutdown(struct pci_dev *pdev)
18088{
18089 struct net_device *dev = pci_get_drvdata(pdev);
18090 struct tg3 *tp = netdev_priv(dev);
18091
18092 rtnl_lock();
18093 netif_device_detach(dev);
18094
18095 if (netif_running(dev))
18096 dev_close(dev);
18097
18098 if (system_state == SYSTEM_POWER_OFF)
18099 tg3_power_down(tp);
18100
18101 rtnl_unlock();
18102}
18103
b45aa2f6
MC		 18104/**
18105 * tg3_io_error_detected - called when PCI error is detected
18106 * @pdev: Pointer to PCI device
18107 * @state: The current pci connection state
18108 *
18109 * This function is called after a PCI bus error affecting
18110 * this device has been detected.
18111 */
18112static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18113 pci_channel_state_t state)
18114{
18115 struct net_device *netdev = pci_get_drvdata(pdev);
18116 struct tg3 *tp = netdev_priv(netdev);
18117 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18118
18119 netdev_info(netdev, "PCI I/O error detected\n");
18120
18121 rtnl_lock();
18122
0486a063
IV		 18123 tp->pcierr_recovery = true;
18124
d8af4dfd
GS		 18125 /* We probably don't have netdev yet */
18126 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 18127 goto done;
18128
18129 tg3_phy_stop(tp);
18130
18131 tg3_netif_stop(tp);
18132
21f7638e 18133 tg3_timer_stop(tp);
b45aa2f6
MC		 18134
18135 /* Want to make sure that the reset task doesn't run */
db219973 18136 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 18137
18138 netif_device_detach(netdev);
18139
18140 /* Clean up software state, even if MMIO is blocked */
18141 tg3_full_lock(tp, 0);
18142 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18143 tg3_full_unlock(tp);
18144
18145done:
72bb72b0 18146 if (state == pci_channel_io_perm_failure) {
68293099
DB		 18147 if (netdev) {
18148 tg3_napi_enable(tp);
18149 dev_close(netdev);
18150 }
b45aa2f6 18151 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 18152 } else {
b45aa2f6 18153 pci_disable_device(pdev);
72bb72b0 18154 }
b45aa2f6
MC		 18155
18156 rtnl_unlock();
18157
18158 return err;
18159}
18160
18161/**
18162 * tg3_io_slot_reset - called after the pci bus has been reset.
18163 * @pdev: Pointer to PCI device
18164 *
18165 * Restart the card from scratch, as if from a cold-boot.
18166 * At this point, the card has exprienced a hard reset,
18167 * followed by fixups by BIOS, and has its config space
18168 * set up identically to what it was at cold boot.
18169 */
18170static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18171{
18172 struct net_device *netdev = pci_get_drvdata(pdev);
18173 struct tg3 *tp = netdev_priv(netdev);
18174 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18175 int err;
18176
18177 rtnl_lock();
18178
18179 if (pci_enable_device(pdev)) {
68293099
DB		 18180 dev_err(&pdev->dev,
18181 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 18182 goto done;
18183 }
18184
18185 pci_set_master(pdev);
18186 pci_restore_state(pdev);
18187 pci_save_state(pdev);
18188
68293099 18189 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 18190 rc = PCI_ERS_RESULT_RECOVERED;
18191 goto done;
18192 }
18193
18194 err = tg3_power_up(tp);
bed9829f 18195 if (err)
b45aa2f6 18196 goto done;
b45aa2f6
MC		 18197
18198 rc = PCI_ERS_RESULT_RECOVERED;
18199
18200done:
68293099 18201 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 18202 tg3_napi_enable(tp);
18203 dev_close(netdev);
18204 }
b45aa2f6
MC		 18205 rtnl_unlock();
18206
18207 return rc;
18208}
18209
18210/**
18211 * tg3_io_resume - called when traffic can start flowing again.
18212 * @pdev: Pointer to PCI device
18213 *
18214 * This callback is called when the error recovery driver tells
18215 * us that its OK to resume normal operation.
18216 */
18217static void tg3_io_resume(struct pci_dev *pdev)
18218{
18219 struct net_device *netdev = pci_get_drvdata(pdev);
18220 struct tg3 *tp = netdev_priv(netdev);
18221 int err;
18222
18223 rtnl_lock();
18224
18225 if (!netif_running(netdev))
18226 goto done;
18227
18228 tg3_full_lock(tp, 0);
2e460fc0 18229 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 18230 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 18231 err = tg3_restart_hw(tp, true);
b45aa2f6 18232 if (err) {
35763066 18233 tg3_full_unlock(tp);
b45aa2f6
MC		 18234 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18235 goto done;
18236 }
18237
18238 netif_device_attach(netdev);
18239
21f7638e 18240 tg3_timer_start(tp);
b45aa2f6
MC		 18241
18242 tg3_netif_start(tp);
18243
35763066
NNS		 18244 tg3_full_unlock(tp);
18245
b45aa2f6
MC		 18246 tg3_phy_start(tp);
18247
18248done:
0486a063 18249 tp->pcierr_recovery = false;
b45aa2f6
MC		 18250 rtnl_unlock();
18251}
18252
3646f0e5 18253static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 18254 .error_detected = tg3_io_error_detected,
18255 .slot_reset = tg3_io_slot_reset,
18256 .resume = tg3_io_resume
18257};
18258
1da177e4
LT		 18259static struct pci_driver tg3_driver = {
18260 .name = DRV_MODULE_NAME,
18261 .id_table = tg3_pci_tbl,
18262 .probe = tg3_init_one,
229b1ad1 18263 .remove = tg3_remove_one,
b45aa2f6 18264 .err_handler = &tg3_err_handler,
42df36a6 18265 .driver.pm = &tg3_pm_ops,
4c305fa2 18266 .shutdown = tg3_shutdown,
1da177e4
LT		 18267};
18268
8dbb0dc2 18269module_pci_driver(tg3_driver);
Linux 6.x block layer and io_uring tree(s)