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tg3: Implement the shutdown handler
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
b681b65d 7 * Copyright (C) 2005-2013 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
1da177e4 28#include <linux/init.h>
a6b7a407 29#include <linux/interrupt.h>
1da177e4
LT		 30#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ethtool.h>
3110f5f5 36#include <linux/mdio.h>
1da177e4 37#include <linux/mii.h>
158d7abd 38#include <linux/phy.h>
a9daf367 39#include <linux/brcmphy.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
c2bba067 97#define TG3_MIN_NUM 132
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
c2bba067 100#define DRV_MODULE_RELDATE "May 21, 2013"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
c6cdf436 211#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 212#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 213
077f849d 214#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 215#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 216#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
217#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
218
229b1ad1 219static char version[] =
05dbe005 220 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 221
222MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
223MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 226MODULE_FIRMWARE(FIRMWARE_TG3);
227MODULE_FIRMWARE(FIRMWARE_TG3TSO);
228MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
229
1da177e4
LT		 230static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
231module_param(tg3_debug, int, 0);
232MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
233
3d567e0e
NNS		 234#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
235#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
236
a3aa1884 237static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
257 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
258 TG3_DRV_DATA_FLAG_5705_10_100},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
264 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
272 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
278 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 286 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
287 PCI_VENDOR_ID_LENOVO,
288 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
289 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
313 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
330 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
332 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
13185217
HK		 340 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
341 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
342 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
343 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
344 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
345 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
346 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 347 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 348 {}
1da177e4
LT		 349};
350
351MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
352
50da859d 353static const struct {
1da177e4 354 const char string[ETH_GSTRING_LEN];
48fa55a0 355} ethtool_stats_keys[] = {
1da177e4
LT		 356 { "rx_octets" },
357 { "rx_fragments" },
358 { "rx_ucast_packets" },
359 { "rx_mcast_packets" },
360 { "rx_bcast_packets" },
361 { "rx_fcs_errors" },
362 { "rx_align_errors" },
363 { "rx_xon_pause_rcvd" },
364 { "rx_xoff_pause_rcvd" },
365 { "rx_mac_ctrl_rcvd" },
366 { "rx_xoff_entered" },
367 { "rx_frame_too_long_errors" },
368 { "rx_jabbers" },
369 { "rx_undersize_packets" },
370 { "rx_in_length_errors" },
371 { "rx_out_length_errors" },
372 { "rx_64_or_less_octet_packets" },
373 { "rx_65_to_127_octet_packets" },
374 { "rx_128_to_255_octet_packets" },
375 { "rx_256_to_511_octet_packets" },
376 { "rx_512_to_1023_octet_packets" },
377 { "rx_1024_to_1522_octet_packets" },
378 { "rx_1523_to_2047_octet_packets" },
379 { "rx_2048_to_4095_octet_packets" },
380 { "rx_4096_to_8191_octet_packets" },
381 { "rx_8192_to_9022_octet_packets" },
382
383 { "tx_octets" },
384 { "tx_collisions" },
385
386 { "tx_xon_sent" },
387 { "tx_xoff_sent" },
388 { "tx_flow_control" },
389 { "tx_mac_errors" },
390 { "tx_single_collisions" },
391 { "tx_mult_collisions" },
392 { "tx_deferred" },
393 { "tx_excessive_collisions" },
394 { "tx_late_collisions" },
395 { "tx_collide_2times" },
396 { "tx_collide_3times" },
397 { "tx_collide_4times" },
398 { "tx_collide_5times" },
399 { "tx_collide_6times" },
400 { "tx_collide_7times" },
401 { "tx_collide_8times" },
402 { "tx_collide_9times" },
403 { "tx_collide_10times" },
404 { "tx_collide_11times" },
405 { "tx_collide_12times" },
406 { "tx_collide_13times" },
407 { "tx_collide_14times" },
408 { "tx_collide_15times" },
409 { "tx_ucast_packets" },
410 { "tx_mcast_packets" },
411 { "tx_bcast_packets" },
412 { "tx_carrier_sense_errors" },
413 { "tx_discards" },
414 { "tx_errors" },
415
416 { "dma_writeq_full" },
417 { "dma_write_prioq_full" },
418 { "rxbds_empty" },
419 { "rx_discards" },
420 { "rx_errors" },
421 { "rx_threshold_hit" },
422
423 { "dma_readq_full" },
424 { "dma_read_prioq_full" },
425 { "tx_comp_queue_full" },
426
427 { "ring_set_send_prod_index" },
428 { "ring_status_update" },
429 { "nic_irqs" },
430 { "nic_avoided_irqs" },
4452d099
MC		 431 { "nic_tx_threshold_hit" },
432
433 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 434};
435
48fa55a0 436#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 437#define TG3_NVRAM_TEST 0
438#define TG3_LINK_TEST 1
439#define TG3_REGISTER_TEST 2
440#define TG3_MEMORY_TEST 3
441#define TG3_MAC_LOOPB_TEST 4
442#define TG3_PHY_LOOPB_TEST 5
443#define TG3_EXT_LOOPB_TEST 6
444#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 445
446
50da859d 447static const struct {
4cafd3f5 448 const char string[ETH_GSTRING_LEN];
48fa55a0 449} ethtool_test_keys[] = {
93df8b8f
NNS		 450 [TG3_NVRAM_TEST] = { "nvram test (online) " },
451 [TG3_LINK_TEST] = { "link test (online) " },
452 [TG3_REGISTER_TEST] = { "register test (offline)" },
453 [TG3_MEMORY_TEST] = { "memory test (offline)" },
454 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
455 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
456 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
457 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 458};
459
48fa55a0
MC		 460#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
461
462
b401e9e2
MC		 463static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
464{
465 writel(val, tp->regs + off);
466}
467
468static u32 tg3_read32(struct tg3 *tp, u32 off)
469{
de6f31eb 470 return readl(tp->regs + off);
b401e9e2
MC		 471}
472
0d3031d9
MC		 473static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
474{
475 writel(val, tp->aperegs + off);
476}
477
478static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
479{
de6f31eb 480 return readl(tp->aperegs + off);
0d3031d9
MC		 481}
482
1da177e4
LT		 483static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
484{
6892914f
MC		 485 unsigned long flags;
486
487 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 488 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
489 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 490 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 491}
492
493static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
494{
495 writel(val, tp->regs + off);
496 readl(tp->regs + off);
1da177e4
LT		 497}
498
6892914f 499static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 500{
6892914f
MC		 501 unsigned long flags;
502 u32 val;
503
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
506 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
508 return val;
509}
510
511static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
512{
513 unsigned long flags;
514
515 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
516 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
517 TG3_64BIT_REG_LOW, val);
518 return;
519 }
66711e66 520 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 521 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
522 TG3_64BIT_REG_LOW, val);
523 return;
1da177e4 524 }
6892914f
MC		 525
526 spin_lock_irqsave(&tp->indirect_lock, flags);
527 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
528 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
529 spin_unlock_irqrestore(&tp->indirect_lock, flags);
530
531 /* In indirect mode when disabling interrupts, we also need
532 * to clear the interrupt bit in the GRC local ctrl register.
533 */
534 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
535 (val == 0x1)) {
536 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
537 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
538 }
539}
540
541static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
542{
543 unsigned long flags;
544 u32 val;
545
546 spin_lock_irqsave(&tp->indirect_lock, flags);
547 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
548 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
549 spin_unlock_irqrestore(&tp->indirect_lock, flags);
550 return val;
551}
552
b401e9e2
MC		 553/* usec_wait specifies the wait time in usec when writing to certain registers
554 * where it is unsafe to read back the register without some delay.
555 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
556 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
557 */
558static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 559{
63c3a66f 560 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 561 /* Non-posted methods */
562 tp->write32(tp, off, val);
563 else {
564 /* Posted method */
565 tg3_write32(tp, off, val);
566 if (usec_wait)
567 udelay(usec_wait);
568 tp->read32(tp, off);
569 }
570 /* Wait again after the read for the posted method to guarantee that
571 * the wait time is met.
572 */
573 if (usec_wait)
574 udelay(usec_wait);
1da177e4
LT		 575}
576
09ee929c
MC		 577static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
578{
579 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 580 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
581 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
582 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 583 tp->read32_mbox(tp, off);
09ee929c
MC		 584}
585
20094930 586static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 587{
588 void __iomem *mbox = tp->regs + off;
589 writel(val, mbox);
63c3a66f 590 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 591 writel(val, mbox);
7e6c63f0
HM		 592 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
593 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 594 readl(mbox);
595}
596
b5d3772c
MC		 597static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
598{
de6f31eb 599 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 600}
601
602static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
603{
604 writel(val, tp->regs + off + GRCMBOX_BASE);
605}
606
c6cdf436 607#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 608#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 609#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
610#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
611#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 612
c6cdf436
MC		 613#define tw32(reg, val) tp->write32(tp, reg, val)
614#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
615#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
616#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 617
618static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
619{
6892914f
MC		 620 unsigned long flags;
621
4153577a 622 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 623 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
624 return;
625
6892914f 626 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 627 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 628 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
629 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 630
bbadf503
MC		 631 /* Always leave this as zero. */
632 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
633 } else {
634 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
635 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 636
bbadf503
MC		 637 /* Always leave this as zero. */
638 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
639 }
640 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 641}
642
1da177e4
LT		 643static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
644{
6892914f
MC		 645 unsigned long flags;
646
4153577a 647 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 648 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
649 *val = 0;
650 return;
651 }
652
6892914f 653 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 654 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 655 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
656 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 657
bbadf503
MC		 658 /* Always leave this as zero. */
659 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
660 } else {
661 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
662 *val = tr32(TG3PCI_MEM_WIN_DATA);
663
664 /* Always leave this as zero. */
665 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
666 }
6892914f 667 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 668}
669
0d3031d9
MC		 670static void tg3_ape_lock_init(struct tg3 *tp)
671{
672 int i;
6f5c8f83 673 u32 regbase, bit;
f92d9dc1 674
4153577a 675 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 676 regbase = TG3_APE_LOCK_GRANT;
677 else
678 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 679
680 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 681 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
682 switch (i) {
683 case TG3_APE_LOCK_PHY0:
684 case TG3_APE_LOCK_PHY1:
685 case TG3_APE_LOCK_PHY2:
686 case TG3_APE_LOCK_PHY3:
687 bit = APE_LOCK_GRANT_DRIVER;
688 break;
689 default:
690 if (!tp->pci_fn)
691 bit = APE_LOCK_GRANT_DRIVER;
692 else
693 bit = 1 << tp->pci_fn;
694 }
695 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 696 }
697
0d3031d9
MC		 698}
699
700static int tg3_ape_lock(struct tg3 *tp, int locknum)
701{
702 int i, off;
703 int ret = 0;
6f5c8f83 704 u32 status, req, gnt, bit;
0d3031d9 705
63c3a66f 706 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 707 return 0;
708
709 switch (locknum) {
6f5c8f83 710 case TG3_APE_LOCK_GPIO:
4153577a 711 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 712 return 0;
33f401ae
MC		 713 case TG3_APE_LOCK_GRC:
714 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 715 if (!tp->pci_fn)
716 bit = APE_LOCK_REQ_DRIVER;
717 else
718 bit = 1 << tp->pci_fn;
33f401ae 719 break;
8151ad57
MC		 720 case TG3_APE_LOCK_PHY0:
721 case TG3_APE_LOCK_PHY1:
722 case TG3_APE_LOCK_PHY2:
723 case TG3_APE_LOCK_PHY3:
724 bit = APE_LOCK_REQ_DRIVER;
725 break;
33f401ae
MC		 726 default:
727 return -EINVAL;
0d3031d9
MC		 728 }
729
4153577a 730 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 731 req = TG3_APE_LOCK_REQ;
732 gnt = TG3_APE_LOCK_GRANT;
733 } else {
734 req = TG3_APE_PER_LOCK_REQ;
735 gnt = TG3_APE_PER_LOCK_GRANT;
736 }
737
0d3031d9
MC		 738 off = 4 * locknum;
739
6f5c8f83 740 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 741
742 /* Wait for up to 1 millisecond to acquire lock. */
743 for (i = 0; i < 100; i++) {
f92d9dc1 744 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 745 if (status == bit)
0d3031d9 746 break;
6d446ec3
GS		 747 if (pci_channel_offline(tp->pdev))
748 break;
749
0d3031d9
MC		 750 udelay(10);
751 }
752
6f5c8f83 753 if (status != bit) {
0d3031d9 754 /* Revoke the lock request. */
6f5c8f83 755 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 756 ret = -EBUSY;
757 }
758
759 return ret;
760}
761
762static void tg3_ape_unlock(struct tg3 *tp, int locknum)
763{
6f5c8f83 764 u32 gnt, bit;
0d3031d9 765
63c3a66f 766 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 767 return;
768
769 switch (locknum) {
6f5c8f83 770 case TG3_APE_LOCK_GPIO:
4153577a 771 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 772 return;
33f401ae
MC		 773 case TG3_APE_LOCK_GRC:
774 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 775 if (!tp->pci_fn)
776 bit = APE_LOCK_GRANT_DRIVER;
777 else
778 bit = 1 << tp->pci_fn;
33f401ae 779 break;
8151ad57
MC		 780 case TG3_APE_LOCK_PHY0:
781 case TG3_APE_LOCK_PHY1:
782 case TG3_APE_LOCK_PHY2:
783 case TG3_APE_LOCK_PHY3:
784 bit = APE_LOCK_GRANT_DRIVER;
785 break;
33f401ae
MC		 786 default:
787 return;
0d3031d9
MC		 788 }
789
4153577a 790 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 791 gnt = TG3_APE_LOCK_GRANT;
792 else
793 gnt = TG3_APE_PER_LOCK_GRANT;
794
6f5c8f83 795 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 796}
797
b65a372b 798static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 799{
fd6d3f0e
MC		 800 u32 apedata;
801
b65a372b
MC		 802 while (timeout_us) {
803 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
804 return -EBUSY;
805
806 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
807 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
808 break;
809
810 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
811
812 udelay(10);
813 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
814 }
815
816 return timeout_us ? 0 : -EBUSY;
817}
818
cf8d55ae
MC		 819static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
820{
821 u32 i, apedata;
822
823 for (i = 0; i < timeout_us / 10; i++) {
824 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
825
826 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
827 break;
828
829 udelay(10);
830 }
831
832 return i == timeout_us / 10;
833}
834
86449944
MC		 835static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
836 u32 len)
cf8d55ae
MC		 837{
838 int err;
839 u32 i, bufoff, msgoff, maxlen, apedata;
840
841 if (!tg3_flag(tp, APE_HAS_NCSI))
842 return 0;
843
844 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
845 if (apedata != APE_SEG_SIG_MAGIC)
846 return -ENODEV;
847
848 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
849 if (!(apedata & APE_FW_STATUS_READY))
850 return -EAGAIN;
851
852 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
853 TG3_APE_SHMEM_BASE;
854 msgoff = bufoff + 2 * sizeof(u32);
855 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
856
857 while (len) {
858 u32 length;
859
860 /* Cap xfer sizes to scratchpad limits. */
861 length = (len > maxlen) ? maxlen : len;
862 len -= length;
863
864 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
865 if (!(apedata & APE_FW_STATUS_READY))
866 return -EAGAIN;
867
868 /* Wait for up to 1 msec for APE to service previous event. */
869 err = tg3_ape_event_lock(tp, 1000);
870 if (err)
871 return err;
872
873 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
874 APE_EVENT_STATUS_SCRTCHPD_READ |
875 APE_EVENT_STATUS_EVENT_PENDING;
876 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
877
878 tg3_ape_write32(tp, bufoff, base_off);
879 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
880
881 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
882 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
883
884 base_off += length;
885
886 if (tg3_ape_wait_for_event(tp, 30000))
887 return -EAGAIN;
888
889 for (i = 0; length; i += 4, length -= 4) {
890 u32 val = tg3_ape_read32(tp, msgoff + i);
891 memcpy(data, &val, sizeof(u32));
892 data++;
893 }
894 }
895
896 return 0;
897}
898
b65a372b
MC		 899static int tg3_ape_send_event(struct tg3 *tp, u32 event)
900{
901 int err;
902 u32 apedata;
fd6d3f0e
MC		 903
904 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
905 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 906 return -EAGAIN;
fd6d3f0e
MC		 907
908 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
909 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 910 return -EAGAIN;
fd6d3f0e
MC		 911
912 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 913 err = tg3_ape_event_lock(tp, 1000);
914 if (err)
915 return err;
fd6d3f0e 916
b65a372b
MC		 917 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
918 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 919
b65a372b
MC		 920 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
921 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 922
b65a372b 923 return 0;
fd6d3f0e
MC		 924}
925
926static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
927{
928 u32 event;
929 u32 apedata;
930
931 if (!tg3_flag(tp, ENABLE_APE))
932 return;
933
934 switch (kind) {
935 case RESET_KIND_INIT:
936 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
937 APE_HOST_SEG_SIG_MAGIC);
938 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
939 APE_HOST_SEG_LEN_MAGIC);
940 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
941 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
942 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
943 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
944 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
945 APE_HOST_BEHAV_NO_PHYLOCK);
946 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
947 TG3_APE_HOST_DRVR_STATE_START);
948
949 event = APE_EVENT_STATUS_STATE_START;
950 break;
951 case RESET_KIND_SHUTDOWN:
952 /* With the interface we are currently using,
953 * APE does not track driver state. Wiping
954 * out the HOST SEGMENT SIGNATURE forces
955 * the APE to assume OS absent status.
956 */
957 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
958
959 if (device_may_wakeup(&tp->pdev->dev) &&
960 tg3_flag(tp, WOL_ENABLE)) {
961 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
962 TG3_APE_HOST_WOL_SPEED_AUTO);
963 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
964 } else
965 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
966
967 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
968
969 event = APE_EVENT_STATUS_STATE_UNLOAD;
970 break;
fd6d3f0e
MC		 971 default:
972 return;
973 }
974
975 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
976
977 tg3_ape_send_event(tp, event);
978}
979
1da177e4
LT		 980static void tg3_disable_ints(struct tg3 *tp)
981{
89aeb3bc
MC		 982 int i;
983
1da177e4
LT		 984 tw32(TG3PCI_MISC_HOST_CTRL,
985 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 986 for (i = 0; i < tp->irq_max; i++)
987 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 988}
989
1da177e4
LT		 990static void tg3_enable_ints(struct tg3 *tp)
991{
89aeb3bc 992 int i;
89aeb3bc 993
bbe832c0
MC		 994 tp->irq_sync = 0;
995 wmb();
996
1da177e4
LT		 997 tw32(TG3PCI_MISC_HOST_CTRL,
998 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 999
f89f38b8 1000 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1001 for (i = 0; i < tp->irq_cnt; i++) {
1002 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1003
898a56f8 1004 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1005 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1006 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1007
f89f38b8 1008 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1009 }
f19af9c2
MC		 1010
1011 /* Force an initial interrupt */
63c3a66f 1012 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1013 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1014 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1015 else
f89f38b8
MC		 1016 tw32(HOSTCC_MODE, tp->coal_now);
1017
1018 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1019}
1020
17375d25 1021static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1022{
17375d25 1023 struct tg3 *tp = tnapi->tp;
898a56f8 1024 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1025 unsigned int work_exists = 0;
1026
1027 /* check for phy events */
63c3a66f 1028 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1029 if (sblk->status & SD_STATUS_LINK_CHG)
1030 work_exists = 1;
1031 }
f891ea16
MC		 1032
1033 /* check for TX work to do */
1034 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1035 work_exists = 1;
1036
1037 /* check for RX work to do */
1038 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1039 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1040 work_exists = 1;
1041
1042 return work_exists;
1043}
1044
17375d25 1045/* tg3_int_reenable
04237ddd
MC		 1046 * similar to tg3_enable_ints, but it accurately determines whether there
1047 * is new work pending and can return without flushing the PIO write
6aa20a22 1048 * which reenables interrupts
1da177e4 1049 */
17375d25 1050static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1051{
17375d25
MC		 1052 struct tg3 *tp = tnapi->tp;
1053
898a56f8 1054 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1055 mmiowb();
1056
fac9b83e
DM		 1057 /* When doing tagged status, this work check is unnecessary.
1058 * The last_tag we write above tells the chip which piece of
1059 * work we've completed.
1060 */
63c3a66f 1061 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1062 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1063 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1064}
1065
1da177e4
LT		 1066static void tg3_switch_clocks(struct tg3 *tp)
1067{
f6eb9b1f 1068 u32 clock_ctrl;
1da177e4
LT		 1069 u32 orig_clock_ctrl;
1070
63c3a66f 1071 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1072 return;
1073
f6eb9b1f
MC		 1074 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1075
1da177e4
LT		 1076 orig_clock_ctrl = clock_ctrl;
1077 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1078 CLOCK_CTRL_CLKRUN_OENABLE |
1079 0x1f);
1080 tp->pci_clock_ctrl = clock_ctrl;
1081
63c3a66f 1082 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1083 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1084 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1085 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1086 }
1087 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1088 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1089 clock_ctrl |
1090 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1091 40);
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1094 40);
1da177e4 1095 }
b401e9e2 1096 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1097}
1098
1099#define PHY_BUSY_LOOPS 5000
1100
5c358045
HM		 1101static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1102 u32 *val)
1da177e4
LT		 1103{
1104 u32 frame_val;
1105 unsigned int loops;
1106 int ret;
1107
1108 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1109 tw32_f(MAC_MI_MODE,
1110 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1111 udelay(80);
1112 }
1113
8151ad57
MC		 1114 tg3_ape_lock(tp, tp->phy_ape_lock);
1115
1da177e4
LT		 1116 *val = 0x0;
1117
5c358045 1118 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1119 MI_COM_PHY_ADDR_MASK);
1120 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1121 MI_COM_REG_ADDR_MASK);
1122 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1123
1da177e4
LT		 1124 tw32_f(MAC_MI_COM, frame_val);
1125
1126 loops = PHY_BUSY_LOOPS;
1127 while (loops != 0) {
1128 udelay(10);
1129 frame_val = tr32(MAC_MI_COM);
1130
1131 if ((frame_val & MI_COM_BUSY) == 0) {
1132 udelay(5);
1133 frame_val = tr32(MAC_MI_COM);
1134 break;
1135 }
1136 loops -= 1;
1137 }
1138
1139 ret = -EBUSY;
1140 if (loops != 0) {
1141 *val = frame_val & MI_COM_DATA_MASK;
1142 ret = 0;
1143 }
1144
1145 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1146 tw32_f(MAC_MI_MODE, tp->mi_mode);
1147 udelay(80);
1148 }
1149
8151ad57
MC		 1150 tg3_ape_unlock(tp, tp->phy_ape_lock);
1151
1da177e4
LT		 1152 return ret;
1153}
1154
5c358045
HM		 1155static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1156{
1157 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1158}
1159
1160static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1161 u32 val)
1da177e4
LT		 1162{
1163 u32 frame_val;
1164 unsigned int loops;
1165 int ret;
1166
f07e9af3 1167 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1168 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1169 return 0;
1170
1da177e4
LT		 1171 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1172 tw32_f(MAC_MI_MODE,
1173 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1174 udelay(80);
1175 }
1176
8151ad57
MC		 1177 tg3_ape_lock(tp, tp->phy_ape_lock);
1178
5c358045 1179 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1180 MI_COM_PHY_ADDR_MASK);
1181 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1182 MI_COM_REG_ADDR_MASK);
1183 frame_val |= (val & MI_COM_DATA_MASK);
1184 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1185
1da177e4
LT		 1186 tw32_f(MAC_MI_COM, frame_val);
1187
1188 loops = PHY_BUSY_LOOPS;
1189 while (loops != 0) {
1190 udelay(10);
1191 frame_val = tr32(MAC_MI_COM);
1192 if ((frame_val & MI_COM_BUSY) == 0) {
1193 udelay(5);
1194 frame_val = tr32(MAC_MI_COM);
1195 break;
1196 }
1197 loops -= 1;
1198 }
1199
1200 ret = -EBUSY;
1201 if (loops != 0)
1202 ret = 0;
1203
1204 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1205 tw32_f(MAC_MI_MODE, tp->mi_mode);
1206 udelay(80);
1207 }
1208
8151ad57
MC		 1209 tg3_ape_unlock(tp, tp->phy_ape_lock);
1210
1da177e4
LT		 1211 return ret;
1212}
1213
5c358045
HM		 1214static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1215{
1216 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1217}
1218
b0988c15
MC		 1219static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1220{
1221 int err;
1222
1223 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1224 if (err)
1225 goto done;
1226
1227 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1228 if (err)
1229 goto done;
1230
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1232 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1233 if (err)
1234 goto done;
1235
1236 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1237
1238done:
1239 return err;
1240}
1241
1242static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1243{
1244 int err;
1245
1246 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1247 if (err)
1248 goto done;
1249
1250 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1251 if (err)
1252 goto done;
1253
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1255 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1256 if (err)
1257 goto done;
1258
1259 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1260
1261done:
1262 return err;
1263}
1264
1265static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1266{
1267 int err;
1268
1269 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1270 if (!err)
1271 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1272
1273 return err;
1274}
1275
1276static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1277{
1278 int err;
1279
1280 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1281 if (!err)
1282 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1283
1284 return err;
1285}
1286
15ee95c3
MC		 1287static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1288{
1289 int err;
1290
1291 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1292 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1293 MII_TG3_AUXCTL_SHDWSEL_MISC);
1294 if (!err)
1295 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1296
1297 return err;
1298}
1299
b4bd2929
MC		 1300static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1301{
1302 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1303 set |= MII_TG3_AUXCTL_MISC_WREN;
1304
1305 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1306}
1307
daf3ec68
NNS		 1308static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1309{
1310 u32 val;
1311 int err;
1d36ba45 1312
daf3ec68 1313 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1314
daf3ec68
NNS		 1315 if (err)
1316 return err;
daf3ec68 1317
7c10ee32 1318 if (enable)
daf3ec68
NNS		 1319 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1320 else
1321 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1322
1323 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1324 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1325
1326 return err;
1327}
1d36ba45 1328
95e2869a
MC		 1329static int tg3_bmcr_reset(struct tg3 *tp)
1330{
1331 u32 phy_control;
1332 int limit, err;
1333
1334 /* OK, reset it, and poll the BMCR_RESET bit until it
1335 * clears or we time out.
1336 */
1337 phy_control = BMCR_RESET;
1338 err = tg3_writephy(tp, MII_BMCR, phy_control);
1339 if (err != 0)
1340 return -EBUSY;
1341
1342 limit = 5000;
1343 while (limit--) {
1344 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1345 if (err != 0)
1346 return -EBUSY;
1347
1348 if ((phy_control & BMCR_RESET) == 0) {
1349 udelay(40);
1350 break;
1351 }
1352 udelay(10);
1353 }
d4675b52 1354 if (limit < 0)
95e2869a
MC		 1355 return -EBUSY;
1356
1357 return 0;
1358}
1359
158d7abd
MC		 1360static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1361{
3d16543d 1362 struct tg3 *tp = bp->priv;
158d7abd
MC		 1363 u32 val;
1364
24bb4fb6 1365 spin_lock_bh(&tp->lock);
158d7abd
MC		 1366
1367 if (tg3_readphy(tp, reg, &val))
24bb4fb6
MC		 1368 val = -EIO;
1369
1370 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1371
1372 return val;
1373}
1374
1375static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1376{
3d16543d 1377 struct tg3 *tp = bp->priv;
24bb4fb6 1378 u32 ret = 0;
158d7abd 1379
24bb4fb6 1380 spin_lock_bh(&tp->lock);
158d7abd
MC		 1381
1382 if (tg3_writephy(tp, reg, val))
24bb4fb6 1383 ret = -EIO;
158d7abd 1384
24bb4fb6
MC		 1385 spin_unlock_bh(&tp->lock);
1386
1387 return ret;
158d7abd
MC		 1388}
1389
1390static int tg3_mdio_reset(struct mii_bus *bp)
1391{
1392 return 0;
1393}
1394
9c61d6bc 1395static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1396{
1397 u32 val;
fcb389df 1398 struct phy_device *phydev;
a9daf367 1399
3f0e3ad7 1400 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
fcb389df 1401 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1402 case PHY_ID_BCM50610:
1403 case PHY_ID_BCM50610M:
fcb389df
MC		 1404 val = MAC_PHYCFG2_50610_LED_MODES;
1405 break;
6a443a0f 1406 case PHY_ID_BCMAC131:
fcb389df
MC		 1407 val = MAC_PHYCFG2_AC131_LED_MODES;
1408 break;
6a443a0f 1409 case PHY_ID_RTL8211C:
fcb389df
MC		 1410 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1411 break;
6a443a0f 1412 case PHY_ID_RTL8201E:
fcb389df
MC		 1413 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1414 break;
1415 default:
a9daf367 1416 return;
fcb389df
MC		 1417 }
1418
1419 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1420 tw32(MAC_PHYCFG2, val);
1421
1422 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1423 val &= ~(MAC_PHYCFG1_RGMII_INT |
1424 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1425 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1426 tw32(MAC_PHYCFG1, val);
1427
1428 return;
1429 }
1430
63c3a66f 1431 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1432 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1433 MAC_PHYCFG2_FMODE_MASK_MASK |
1434 MAC_PHYCFG2_GMODE_MASK_MASK |
1435 MAC_PHYCFG2_ACT_MASK_MASK |
1436 MAC_PHYCFG2_QUAL_MASK_MASK |
1437 MAC_PHYCFG2_INBAND_ENABLE;
1438
1439 tw32(MAC_PHYCFG2, val);
a9daf367 1440
bb85fbb6
MC		 1441 val = tr32(MAC_PHYCFG1);
1442 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1443 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1444 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1445 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1446 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1447 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1448 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1449 }
bb85fbb6
MC		 1450 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1451 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1452 tw32(MAC_PHYCFG1, val);
a9daf367 1453
a9daf367
MC		 1454 val = tr32(MAC_EXT_RGMII_MODE);
1455 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1456 MAC_RGMII_MODE_RX_QUALITY |
1457 MAC_RGMII_MODE_RX_ACTIVITY |
1458 MAC_RGMII_MODE_RX_ENG_DET |
1459 MAC_RGMII_MODE_TX_ENABLE |
1460 MAC_RGMII_MODE_TX_LOWPWR |
1461 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1462 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1463 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1464 val |= MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1468 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1469 val |= MAC_RGMII_MODE_TX_ENABLE |
1470 MAC_RGMII_MODE_TX_LOWPWR |
1471 MAC_RGMII_MODE_TX_RESET;
1472 }
1473 tw32(MAC_EXT_RGMII_MODE, val);
1474}
1475
158d7abd
MC		 1476static void tg3_mdio_start(struct tg3 *tp)
1477{
158d7abd
MC		 1478 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1479 tw32_f(MAC_MI_MODE, tp->mi_mode);
1480 udelay(80);
a9daf367 1481
63c3a66f 1482 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1483 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1484 tg3_mdio_config_5785(tp);
1485}
1486
1487static int tg3_mdio_init(struct tg3 *tp)
1488{
1489 int i;
1490 u32 reg;
1491 struct phy_device *phydev;
1492
63c3a66f 1493 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1494 u32 is_serdes;
882e9793 1495
69f11c99 1496 tp->phy_addr = tp->pci_fn + 1;
882e9793 1497
4153577a 1498 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1499 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1500 else
1501 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1502 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1503 if (is_serdes)
1504 tp->phy_addr += 7;
1505 } else
3f0e3ad7 1506 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1507
158d7abd
MC		 1508 tg3_mdio_start(tp);
1509
63c3a66f 1510 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1511 return 0;
1512
298cf9be
LB		 1513 tp->mdio_bus = mdiobus_alloc();
1514 if (tp->mdio_bus == NULL)
1515 return -ENOMEM;
158d7abd 1516
298cf9be
LB		 1517 tp->mdio_bus->name = "tg3 mdio bus";
1518 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1519 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1520 tp->mdio_bus->priv = tp;
1521 tp->mdio_bus->parent = &tp->pdev->dev;
1522 tp->mdio_bus->read = &tg3_mdio_read;
1523 tp->mdio_bus->write = &tg3_mdio_write;
1524 tp->mdio_bus->reset = &tg3_mdio_reset;
3f0e3ad7 1525 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
298cf9be 1526 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1527
1528 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1529 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1530
1531 /* The bus registration will look for all the PHYs on the mdio bus.
1532 * Unfortunately, it does not ensure the PHY is powered up before
1533 * accessing the PHY ID registers. A chip reset is the
1534 * quickest way to bring the device back to an operational state..
1535 */
1536 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1537 tg3_bmcr_reset(tp);
1538
298cf9be 1539 i = mdiobus_register(tp->mdio_bus);
a9daf367 1540 if (i) {
ab96b241 1541 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1542 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1543 return i;
1544 }
158d7abd 1545
3f0e3ad7 1546 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
a9daf367 1547
9c61d6bc 1548 if (!phydev || !phydev->drv) {
ab96b241 1549 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1550 mdiobus_unregister(tp->mdio_bus);
1551 mdiobus_free(tp->mdio_bus);
1552 return -ENODEV;
1553 }
1554
1555 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1556 case PHY_ID_BCM57780:
321d32a0 1557 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1558 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1559 break;
6a443a0f
MC		 1560 case PHY_ID_BCM50610:
1561 case PHY_ID_BCM50610M:
32e5a8d6 1562 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1563 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1564 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1565 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1566 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1567 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1568 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1569 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1570 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1571 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1572 /* fallthru */
6a443a0f 1573 case PHY_ID_RTL8211C:
fcb389df 1574 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1575 break;
6a443a0f
MC		 1576 case PHY_ID_RTL8201E:
1577 case PHY_ID_BCMAC131:
a9daf367 1578 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1579 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1580 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1581 break;
1582 }
1583
63c3a66f 1584 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1585
4153577a 1586 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1587 tg3_mdio_config_5785(tp);
a9daf367
MC		 1588
1589 return 0;
158d7abd
MC		 1590}
1591
1592static void tg3_mdio_fini(struct tg3 *tp)
1593{
63c3a66f
JP		 1594 if (tg3_flag(tp, MDIOBUS_INITED)) {
1595 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1596 mdiobus_unregister(tp->mdio_bus);
1597 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1598 }
1599}
1600
4ba526ce
MC		 1601/* tp->lock is held. */
1602static inline void tg3_generate_fw_event(struct tg3 *tp)
1603{
1604 u32 val;
1605
1606 val = tr32(GRC_RX_CPU_EVENT);
1607 val |= GRC_RX_CPU_DRIVER_EVENT;
1608 tw32_f(GRC_RX_CPU_EVENT, val);
1609
1610 tp->last_event_jiffies = jiffies;
1611}
1612
1613#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1614
95e2869a
MC		 1615/* tp->lock is held. */
1616static void tg3_wait_for_event_ack(struct tg3 *tp)
1617{
1618 int i;
4ba526ce
MC		 1619 unsigned int delay_cnt;
1620 long time_remain;
1621
1622 /* If enough time has passed, no wait is necessary. */
1623 time_remain = (long)(tp->last_event_jiffies + 1 +
1624 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1625 (long)jiffies;
1626 if (time_remain < 0)
1627 return;
1628
1629 /* Check if we can shorten the wait time. */
1630 delay_cnt = jiffies_to_usecs(time_remain);
1631 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1632 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1633 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1634
4ba526ce 1635 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1636 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1637 break;
6d446ec3
GS		 1638 if (pci_channel_offline(tp->pdev))
1639 break;
1640
4ba526ce 1641 udelay(8);
95e2869a
MC		 1642 }
1643}
1644
1645/* tp->lock is held. */
b28f389d 1646static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1647{
b28f389d 1648 u32 reg, val;
95e2869a
MC		 1649
1650 val = 0;
1651 if (!tg3_readphy(tp, MII_BMCR, &reg))
1652 val = reg << 16;
1653 if (!tg3_readphy(tp, MII_BMSR, &reg))
1654 val |= (reg & 0xffff);
b28f389d 1655 *data++ = val;
95e2869a
MC		 1656
1657 val = 0;
1658 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1659 val = reg << 16;
1660 if (!tg3_readphy(tp, MII_LPA, &reg))
1661 val |= (reg & 0xffff);
b28f389d 1662 *data++ = val;
95e2869a
MC		 1663
1664 val = 0;
f07e9af3 1665 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1666 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1667 val = reg << 16;
1668 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1669 val |= (reg & 0xffff);
1670 }
b28f389d 1671 *data++ = val;
95e2869a
MC		 1672
1673 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1674 val = reg << 16;
1675 else
1676 val = 0;
b28f389d
MC		 1677 *data++ = val;
1678}
1679
1680/* tp->lock is held. */
1681static void tg3_ump_link_report(struct tg3 *tp)
1682{
1683 u32 data[4];
1684
1685 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1686 return;
1687
1688 tg3_phy_gather_ump_data(tp, data);
1689
1690 tg3_wait_for_event_ack(tp);
1691
1692 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1693 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1694 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1695 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1696 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1697 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1698
4ba526ce 1699 tg3_generate_fw_event(tp);
95e2869a
MC		 1700}
1701
8d5a89b3
MC		 1702/* tp->lock is held. */
1703static void tg3_stop_fw(struct tg3 *tp)
1704{
1705 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1706 /* Wait for RX cpu to ACK the previous event. */
1707 tg3_wait_for_event_ack(tp);
1708
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1710
1711 tg3_generate_fw_event(tp);
1712
1713 /* Wait for RX cpu to ACK this event. */
1714 tg3_wait_for_event_ack(tp);
1715 }
1716}
1717
fd6d3f0e
MC		 1718/* tp->lock is held. */
1719static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1720{
1721 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1722 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1723
1724 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1725 switch (kind) {
1726 case RESET_KIND_INIT:
1727 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1728 DRV_STATE_START);
1729 break;
1730
1731 case RESET_KIND_SHUTDOWN:
1732 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1733 DRV_STATE_UNLOAD);
1734 break;
1735
1736 case RESET_KIND_SUSPEND:
1737 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1738 DRV_STATE_SUSPEND);
1739 break;
1740
1741 default:
1742 break;
1743 }
1744 }
fd6d3f0e
MC		 1745}
1746
1747/* tp->lock is held. */
1748static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1749{
1750 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1751 switch (kind) {
1752 case RESET_KIND_INIT:
1753 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1754 DRV_STATE_START_DONE);
1755 break;
1756
1757 case RESET_KIND_SHUTDOWN:
1758 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1759 DRV_STATE_UNLOAD_DONE);
1760 break;
1761
1762 default:
1763 break;
1764 }
1765 }
fd6d3f0e
MC		 1766}
1767
1768/* tp->lock is held. */
1769static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1770{
1771 if (tg3_flag(tp, ENABLE_ASF)) {
1772 switch (kind) {
1773 case RESET_KIND_INIT:
1774 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1775 DRV_STATE_START);
1776 break;
1777
1778 case RESET_KIND_SHUTDOWN:
1779 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1780 DRV_STATE_UNLOAD);
1781 break;
1782
1783 case RESET_KIND_SUSPEND:
1784 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1785 DRV_STATE_SUSPEND);
1786 break;
1787
1788 default:
1789 break;
1790 }
1791 }
1792}
1793
1794static int tg3_poll_fw(struct tg3 *tp)
1795{
1796 int i;
1797 u32 val;
1798
df465abf
NS		 1799 if (tg3_flag(tp, NO_FWARE_REPORTED))
1800 return 0;
1801
7e6c63f0
HM		 1802 if (tg3_flag(tp, IS_SSB_CORE)) {
1803 /* We don't use firmware. */
1804 return 0;
1805 }
1806
4153577a 1807 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1808 /* Wait up to 20ms for init done. */
1809 for (i = 0; i < 200; i++) {
1810 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1811 return 0;
6d446ec3
GS		 1812 if (pci_channel_offline(tp->pdev))
1813 return -ENODEV;
1814
fd6d3f0e
MC		 1815 udelay(100);
1816 }
1817 return -ENODEV;
1818 }
1819
1820 /* Wait for firmware initialization to complete. */
1821 for (i = 0; i < 100000; i++) {
1822 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1823 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1824 break;
6d446ec3
GS		 1825 if (pci_channel_offline(tp->pdev)) {
1826 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1827 tg3_flag_set(tp, NO_FWARE_REPORTED);
1828 netdev_info(tp->dev, "No firmware running\n");
1829 }
1830
1831 break;
1832 }
1833
fd6d3f0e
MC		 1834 udelay(10);
1835 }
1836
1837 /* Chip might not be fitted with firmware. Some Sun onboard
1838 * parts are configured like that. So don't signal the timeout
1839 * of the above loop as an error, but do report the lack of
1840 * running firmware once.
1841 */
1842 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1843 tg3_flag_set(tp, NO_FWARE_REPORTED);
1844
1845 netdev_info(tp->dev, "No firmware running\n");
1846 }
1847
4153577a 1848 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1849 /* The 57765 A0 needs a little more
1850 * time to do some important work.
1851 */
1852 mdelay(10);
1853 }
1854
1855 return 0;
1856}
1857
95e2869a
MC		 1858static void tg3_link_report(struct tg3 *tp)
1859{
1860 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1861 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1862 tg3_ump_link_report(tp);
1863 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1864 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1865 (tp->link_config.active_speed == SPEED_1000 ?
1866 1000 :
1867 (tp->link_config.active_speed == SPEED_100 ?
1868 100 : 10)),
1869 (tp->link_config.active_duplex == DUPLEX_FULL ?
1870 "full" : "half"));
1871
1872 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1873 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1874 "on" : "off",
1875 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1876 "on" : "off");
47007831
MC		 1877
1878 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1879 netdev_info(tp->dev, "EEE is %s\n",
1880 tp->setlpicnt ? "enabled" : "disabled");
1881
95e2869a
MC		 1882 tg3_ump_link_report(tp);
1883 }
84421b99
NS		 1884
1885 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1886}
1887
fdad8de4
NS		 1888static u32 tg3_decode_flowctrl_1000T(u32 adv)
1889{
1890 u32 flowctrl = 0;
1891
1892 if (adv & ADVERTISE_PAUSE_CAP) {
1893 flowctrl |= FLOW_CTRL_RX;
1894 if (!(adv & ADVERTISE_PAUSE_ASYM))
1895 flowctrl |= FLOW_CTRL_TX;
1896 } else if (adv & ADVERTISE_PAUSE_ASYM)
1897 flowctrl |= FLOW_CTRL_TX;
1898
1899 return flowctrl;
1900}
1901
95e2869a
MC		 1902static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1903{
1904 u16 miireg;
1905
e18ce346 1906 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1907 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1908 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1909 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1910 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1911 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1912 else
1913 miireg = 0;
1914
1915 return miireg;
1916}
1917
fdad8de4
NS		 1918static u32 tg3_decode_flowctrl_1000X(u32 adv)
1919{
1920 u32 flowctrl = 0;
1921
1922 if (adv & ADVERTISE_1000XPAUSE) {
1923 flowctrl |= FLOW_CTRL_RX;
1924 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1925 flowctrl |= FLOW_CTRL_TX;
1926 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1927 flowctrl |= FLOW_CTRL_TX;
1928
1929 return flowctrl;
1930}
1931
95e2869a
MC		 1932static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1933{
1934 u8 cap = 0;
1935
f3791cdf
MC		 1936 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1937 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1938 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1939 if (lcladv & ADVERTISE_1000XPAUSE)
1940 cap = FLOW_CTRL_RX;
1941 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1942 cap = FLOW_CTRL_TX;
95e2869a
MC		 1943 }
1944
1945 return cap;
1946}
1947
f51f3562 1948static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1949{
b02fd9e3 1950 u8 autoneg;
f51f3562 1951 u8 flowctrl = 0;
95e2869a
MC		 1952 u32 old_rx_mode = tp->rx_mode;
1953 u32 old_tx_mode = tp->tx_mode;
1954
63c3a66f 1955 if (tg3_flag(tp, USE_PHYLIB))
3f0e3ad7 1956 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
b02fd9e3
MC		 1957 else
1958 autoneg = tp->link_config.autoneg;
1959
63c3a66f 1960 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1961 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1962 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1963 else
bc02ff95 1964 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1965 } else
1966 flowctrl = tp->link_config.flowctrl;
95e2869a 1967
f51f3562 1968 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1969
e18ce346 1970 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1971 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1972 else
1973 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1974
f51f3562 1975 if (old_rx_mode != tp->rx_mode)
95e2869a 1976 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1977
e18ce346 1978 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1979 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1980 else
1981 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1982
f51f3562 1983 if (old_tx_mode != tp->tx_mode)
95e2869a 1984 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 1985}
1986
b02fd9e3
MC		 1987static void tg3_adjust_link(struct net_device *dev)
1988{
1989 u8 oldflowctrl, linkmesg = 0;
1990 u32 mac_mode, lcl_adv, rmt_adv;
1991 struct tg3 *tp = netdev_priv(dev);
3f0e3ad7 1992 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 1993
24bb4fb6 1994 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 1995
1996 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1997 MAC_MODE_HALF_DUPLEX);
1998
1999 oldflowctrl = tp->link_config.active_flowctrl;
2000
2001 if (phydev->link) {
2002 lcl_adv = 0;
2003 rmt_adv = 0;
2004
2005 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2006 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2007 else if (phydev->speed == SPEED_1000 ||
4153577a 2008 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2009 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2010 else
2011 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2012
2013 if (phydev->duplex == DUPLEX_HALF)
2014 mac_mode |= MAC_MODE_HALF_DUPLEX;
2015 else {
f88788f0 2016 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2017 tp->link_config.flowctrl);
2018
2019 if (phydev->pause)
2020 rmt_adv = LPA_PAUSE_CAP;
2021 if (phydev->asym_pause)
2022 rmt_adv |= LPA_PAUSE_ASYM;
2023 }
2024
2025 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2026 } else
2027 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2028
2029 if (mac_mode != tp->mac_mode) {
2030 tp->mac_mode = mac_mode;
2031 tw32_f(MAC_MODE, tp->mac_mode);
2032 udelay(40);
2033 }
2034
4153577a 2035 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2036 if (phydev->speed == SPEED_10)
2037 tw32(MAC_MI_STAT,
2038 MAC_MI_STAT_10MBPS_MODE |
2039 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2040 else
2041 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2042 }
2043
b02fd9e3
MC		 2044 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2045 tw32(MAC_TX_LENGTHS,
2046 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2047 (6 << TX_LENGTHS_IPG_SHIFT) |
2048 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2049 else
2050 tw32(MAC_TX_LENGTHS,
2051 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2052 (6 << TX_LENGTHS_IPG_SHIFT) |
2053 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2054
34655ad6 2055 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2056 phydev->speed != tp->link_config.active_speed ||
2057 phydev->duplex != tp->link_config.active_duplex ||
2058 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2059 linkmesg = 1;
b02fd9e3 2060
34655ad6 2061 tp->old_link = phydev->link;
b02fd9e3
MC		 2062 tp->link_config.active_speed = phydev->speed;
2063 tp->link_config.active_duplex = phydev->duplex;
2064
24bb4fb6 2065 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2066
2067 if (linkmesg)
2068 tg3_link_report(tp);
2069}
2070
2071static int tg3_phy_init(struct tg3 *tp)
2072{
2073 struct phy_device *phydev;
2074
f07e9af3 2075 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2076 return 0;
2077
2078 /* Bring the PHY back to a known state. */
2079 tg3_bmcr_reset(tp);
2080
3f0e3ad7 2081 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3
MC		 2082
2083 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2084 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2085 tg3_adjust_link, phydev->interface);
b02fd9e3 2086 if (IS_ERR(phydev)) {
ab96b241 2087 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2088 return PTR_ERR(phydev);
2089 }
2090
b02fd9e3 2091 /* Mask with MAC supported features. */
9c61d6bc
MC		 2092 switch (phydev->interface) {
2093 case PHY_INTERFACE_MODE_GMII:
2094 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2095 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2096 phydev->supported &= (PHY_GBIT_FEATURES |
2097 SUPPORTED_Pause |
2098 SUPPORTED_Asym_Pause);
2099 break;
2100 }
2101 /* fallthru */
9c61d6bc
MC		 2102 case PHY_INTERFACE_MODE_MII:
2103 phydev->supported &= (PHY_BASIC_FEATURES |
2104 SUPPORTED_Pause |
2105 SUPPORTED_Asym_Pause);
2106 break;
2107 default:
3f0e3ad7 2108 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9c61d6bc
MC		 2109 return -EINVAL;
2110 }
2111
f07e9af3 2112 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2113
2114 phydev->advertising = phydev->supported;
2115
b02fd9e3
MC		 2116 return 0;
2117}
2118
2119static void tg3_phy_start(struct tg3 *tp)
2120{
2121 struct phy_device *phydev;
2122
f07e9af3 2123 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2124 return;
2125
3f0e3ad7 2126 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 2127
80096068
MC		 2128 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2129 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2130 phydev->speed = tp->link_config.speed;
2131 phydev->duplex = tp->link_config.duplex;
2132 phydev->autoneg = tp->link_config.autoneg;
2133 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2134 }
2135
2136 phy_start(phydev);
2137
2138 phy_start_aneg(phydev);
2139}
2140
2141static void tg3_phy_stop(struct tg3 *tp)
2142{
f07e9af3 2143 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2144 return;
2145
3f0e3ad7 2146 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 2147}
2148
2149static void tg3_phy_fini(struct tg3 *tp)
2150{
f07e9af3 2151 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 2152 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
f07e9af3 2153 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2154 }
2155}
2156
941ec90f
MC		 2157static int tg3_phy_set_extloopbk(struct tg3 *tp)
2158{
2159 int err;
2160 u32 val;
2161
2162 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2163 return 0;
2164
2165 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2166 /* Cannot do read-modify-write on 5401 */
2167 err = tg3_phy_auxctl_write(tp,
2168 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2169 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2170 0x4c20);
2171 goto done;
2172 }
2173
2174 err = tg3_phy_auxctl_read(tp,
2175 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2176 if (err)
2177 return err;
2178
2179 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2180 err = tg3_phy_auxctl_write(tp,
2181 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2182
2183done:
2184 return err;
2185}
2186
7f97a4bd
MC		 2187static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2188{
2189 u32 phytest;
2190
2191 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2192 u32 phy;
2193
2194 tg3_writephy(tp, MII_TG3_FET_TEST,
2195 phytest | MII_TG3_FET_SHADOW_EN);
2196 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2197 if (enable)
2198 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2199 else
2200 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2201 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2202 }
2203 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2204 }
2205}
2206
6833c043
MC		 2207static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2208{
2209 u32 reg;
2210
63c3a66f
JP		 2211 if (!tg3_flag(tp, 5705_PLUS) ||
2212 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2213 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2214 return;
2215
f07e9af3 2216 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2217 tg3_phy_fet_toggle_apd(tp, enable);
2218 return;
2219 }
2220
6833c043
MC		 2221 reg = MII_TG3_MISC_SHDW_WREN |
2222 MII_TG3_MISC_SHDW_SCR5_SEL |
2223 MII_TG3_MISC_SHDW_SCR5_LPED |
2224 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2225 MII_TG3_MISC_SHDW_SCR5_SDTL |
2226 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2227 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2228 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2229
2230 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2231
2232
2233 reg = MII_TG3_MISC_SHDW_WREN |
2234 MII_TG3_MISC_SHDW_APD_SEL |
2235 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2236 if (enable)
2237 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2238
2239 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2240}
2241
953c96e0 2242static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2243{
2244 u32 phy;
2245
63c3a66f 2246 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2247 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2248 return;
2249
f07e9af3 2250 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2251 u32 ephy;
2252
535ef6e1
MC		 2253 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2254 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2255
2256 tg3_writephy(tp, MII_TG3_FET_TEST,
2257 ephy | MII_TG3_FET_SHADOW_EN);
2258 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2259 if (enable)
535ef6e1 2260 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2261 else
535ef6e1
MC		 2262 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2263 tg3_writephy(tp, reg, phy);
9ef8ca99 2264 }
535ef6e1 2265 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2266 }
2267 } else {
15ee95c3
MC		 2268 int ret;
2269
2270 ret = tg3_phy_auxctl_read(tp,
2271 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2272 if (!ret) {
9ef8ca99
MC		 2273 if (enable)
2274 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2275 else
2276 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2277 tg3_phy_auxctl_write(tp,
2278 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2279 }
2280 }
2281}
2282
1da177e4
LT		 2283static void tg3_phy_set_wirespeed(struct tg3 *tp)
2284{
15ee95c3 2285 int ret;
1da177e4
LT		 2286 u32 val;
2287
f07e9af3 2288 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2289 return;
2290
15ee95c3
MC		 2291 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2292 if (!ret)
b4bd2929
MC		 2293 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2294 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2295}
2296
b2a5c19c
MC		 2297static void tg3_phy_apply_otp(struct tg3 *tp)
2298{
2299 u32 otp, phy;
2300
2301 if (!tp->phy_otp)
2302 return;
2303
2304 otp = tp->phy_otp;
2305
daf3ec68 2306 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2307 return;
b2a5c19c
MC		 2308
2309 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2310 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2311 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2312
2313 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2314 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2315 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2316
2317 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2318 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2319 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2320
2321 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2322 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2323
2324 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2325 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2326
2327 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2328 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2329 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2330
daf3ec68 2331 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2332}
2333
400dfbaa
NS		 2334static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2335{
2336 u32 val;
2337 struct ethtool_eee *dest = &tp->eee;
2338
2339 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2340 return;
2341
2342 if (eee)
2343 dest = eee;
2344
2345 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2346 return;
2347
2348 /* Pull eee_active */
2349 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2350 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2351 dest->eee_active = 1;
2352 } else
2353 dest->eee_active = 0;
2354
2355 /* Pull lp advertised settings */
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2357 return;
2358 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2359
2360 /* Pull advertised and eee_enabled settings */
2361 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2362 return;
2363 dest->eee_enabled = !!val;
2364 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2365
2366 /* Pull tx_lpi_enabled */
2367 val = tr32(TG3_CPMU_EEE_MODE);
2368 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2369
2370 /* Pull lpi timer value */
2371 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2372}
2373
953c96e0 2374static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2375{
2376 u32 val;
2377
2378 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2379 return;
2380
2381 tp->setlpicnt = 0;
2382
2383 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2384 current_link_up &&
a6b68dab
MC		 2385 tp->link_config.active_duplex == DUPLEX_FULL &&
2386 (tp->link_config.active_speed == SPEED_100 ||
2387 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2388 u32 eeectl;
2389
2390 if (tp->link_config.active_speed == SPEED_1000)
2391 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2392 else
2393 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2394
2395 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2396
400dfbaa
NS		 2397 tg3_eee_pull_config(tp, NULL);
2398 if (tp->eee.eee_active)
52b02d04
MC		 2399 tp->setlpicnt = 2;
2400 }
2401
2402 if (!tp->setlpicnt) {
953c96e0 2403 if (current_link_up &&
daf3ec68 2404 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2405 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2406 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2407 }
2408
52b02d04
MC		 2409 val = tr32(TG3_CPMU_EEE_MODE);
2410 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2411 }
2412}
2413
b0c5943f
MC		 2414static void tg3_phy_eee_enable(struct tg3 *tp)
2415{
2416 u32 val;
2417
2418 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2419 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2420 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2421 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2422 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2423 val = MII_TG3_DSP_TAP26_ALNOKO |
2424 MII_TG3_DSP_TAP26_RMRXSTO;
2425 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2426 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2427 }
2428
2429 val = tr32(TG3_CPMU_EEE_MODE);
2430 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2431}
2432
1da177e4
LT		 2433static int tg3_wait_macro_done(struct tg3 *tp)
2434{
2435 int limit = 100;
2436
2437 while (limit--) {
2438 u32 tmp32;
2439
f08aa1a8 2440 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2441 if ((tmp32 & 0x1000) == 0)
2442 break;
2443 }
2444 }
d4675b52 2445 if (limit < 0)
1da177e4
LT		 2446 return -EBUSY;
2447
2448 return 0;
2449}
2450
2451static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2452{
2453 static const u32 test_pat[4][6] = {
2454 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2455 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2456 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2457 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2458 };
2459 int chan;
2460
2461 for (chan = 0; chan < 4; chan++) {
2462 int i;
2463
2464 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2465 (chan * 0x2000) | 0x0200);
f08aa1a8 2466 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2467
2468 for (i = 0; i < 6; i++)
2469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2470 test_pat[chan][i]);
2471
f08aa1a8 2472 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2473 if (tg3_wait_macro_done(tp)) {
2474 *resetp = 1;
2475 return -EBUSY;
2476 }
2477
2478 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2479 (chan * 0x2000) | 0x0200);
f08aa1a8 2480 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2481 if (tg3_wait_macro_done(tp)) {
2482 *resetp = 1;
2483 return -EBUSY;
2484 }
2485
f08aa1a8 2486 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2487 if (tg3_wait_macro_done(tp)) {
2488 *resetp = 1;
2489 return -EBUSY;
2490 }
2491
2492 for (i = 0; i < 6; i += 2) {
2493 u32 low, high;
2494
2495 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2496 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2497 tg3_wait_macro_done(tp)) {
2498 *resetp = 1;
2499 return -EBUSY;
2500 }
2501 low &= 0x7fff;
2502 high &= 0x000f;
2503 if (low != test_pat[chan][i] ||
2504 high != test_pat[chan][i+1]) {
2505 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2506 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2507 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2508
2509 return -EBUSY;
2510 }
2511 }
2512 }
2513
2514 return 0;
2515}
2516
2517static int tg3_phy_reset_chanpat(struct tg3 *tp)
2518{
2519 int chan;
2520
2521 for (chan = 0; chan < 4; chan++) {
2522 int i;
2523
2524 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2525 (chan * 0x2000) | 0x0200);
f08aa1a8 2526 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2527 for (i = 0; i < 6; i++)
2528 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2529 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2530 if (tg3_wait_macro_done(tp))
2531 return -EBUSY;
2532 }
2533
2534 return 0;
2535}
2536
2537static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2538{
2539 u32 reg32, phy9_orig;
2540 int retries, do_phy_reset, err;
2541
2542 retries = 10;
2543 do_phy_reset = 1;
2544 do {
2545 if (do_phy_reset) {
2546 err = tg3_bmcr_reset(tp);
2547 if (err)
2548 return err;
2549 do_phy_reset = 0;
2550 }
2551
2552 /* Disable transmitter and interrupt. */
2553 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2554 continue;
2555
2556 reg32 |= 0x3000;
2557 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2558
2559 /* Set full-duplex, 1000 mbps. */
2560 tg3_writephy(tp, MII_BMCR,
221c5637 2561 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2562
2563 /* Set to master mode. */
221c5637 2564 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2565 continue;
2566
221c5637
MC		 2567 tg3_writephy(tp, MII_CTRL1000,
2568 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2569
daf3ec68 2570 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2571 if (err)
2572 return err;
1da177e4
LT		 2573
2574 /* Block the PHY control access. */
6ee7c0a0 2575 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2576
2577 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2578 if (!err)
2579 break;
2580 } while (--retries);
2581
2582 err = tg3_phy_reset_chanpat(tp);
2583 if (err)
2584 return err;
2585
6ee7c0a0 2586 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2587
2588 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2589 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2590
daf3ec68 2591 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2592
221c5637 2593 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4
LT		 2594
2595 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2596 reg32 &= ~0x3000;
2597 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2598 } else if (!err)
2599 err = -EBUSY;
2600
2601 return err;
2602}
2603
f4a46d1f
NNS		 2604static void tg3_carrier_off(struct tg3 *tp)
2605{
2606 netif_carrier_off(tp->dev);
2607 tp->link_up = false;
2608}
2609
ce20f161
NS		 2610static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2611{
2612 if (tg3_flag(tp, ENABLE_ASF))
2613 netdev_warn(tp->dev,
2614 "Management side-band traffic will be interrupted during phy settings change\n");
2615}
2616
1da177e4
LT		 2617/* This will reset the tigon3 PHY if there is no valid
2618 * link unless the FORCE argument is non-zero.
2619 */
2620static int tg3_phy_reset(struct tg3 *tp)
2621{
f833c4c1 2622 u32 val, cpmuctrl;
1da177e4
LT		 2623 int err;
2624
4153577a 2625 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2626 val = tr32(GRC_MISC_CFG);
2627 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2628 udelay(40);
2629 }
f833c4c1
MC		 2630 err = tg3_readphy(tp, MII_BMSR, &val);
2631 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2632 if (err != 0)
2633 return -EBUSY;
2634
f4a46d1f 2635 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2636 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2637 tg3_link_report(tp);
2638 }
2639
4153577a
JP		 2640 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2641 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2642 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2643 err = tg3_phy_reset_5703_4_5(tp);
2644 if (err)
2645 return err;
2646 goto out;
2647 }
2648
b2a5c19c 2649 cpmuctrl = 0;
4153577a
JP		 2650 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2651 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2652 cpmuctrl = tr32(TG3_CPMU_CTRL);
2653 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2654 tw32(TG3_CPMU_CTRL,
2655 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2656 }
2657
1da177e4
LT		 2658 err = tg3_bmcr_reset(tp);
2659 if (err)
2660 return err;
2661
b2a5c19c 2662 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2663 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2664 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2665
2666 tw32(TG3_CPMU_CTRL, cpmuctrl);
2667 }
2668
4153577a
JP		 2669 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2670 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2671 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2672 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2673 CPMU_LSPD_1000MB_MACCLK_12_5) {
2674 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2675 udelay(40);
2676 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2677 }
2678 }
2679
63c3a66f 2680 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2681 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2682 return 0;
2683
b2a5c19c
MC		 2684 tg3_phy_apply_otp(tp);
2685
f07e9af3 2686 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2687 tg3_phy_toggle_apd(tp, true);
2688 else
2689 tg3_phy_toggle_apd(tp, false);
2690
1da177e4 2691out:
1d36ba45 2692 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2693 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2694 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2695 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2696 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2697 }
1d36ba45 2698
f07e9af3 2699 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2700 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2701 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2702 }
1d36ba45 2703
f07e9af3 2704 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2705 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2706 tg3_phydsp_write(tp, 0x000a, 0x310b);
2707 tg3_phydsp_write(tp, 0x201f, 0x9506);
2708 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2709 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2710 }
f07e9af3 2711 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2712 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2713 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2714 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2715 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2716 tg3_writephy(tp, MII_TG3_TEST1,
2717 MII_TG3_TEST1_TRIM_EN | 0x4);
2718 } else
2719 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2720
daf3ec68 2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2722 }
c424cb24 2723 }
1d36ba45 2724
1da177e4
LT		 2725 /* Set Extended packet length bit (bit 14) on all chips that */
2726 /* support jumbo frames */
79eb6904 2727 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2728 /* Cannot do read-modify-write on 5401 */
b4bd2929 2729 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2730 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2731 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2732 err = tg3_phy_auxctl_read(tp,
2733 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2734 if (!err)
b4bd2929
MC		 2735 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2736 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2737 }
2738
2739 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2740 * jumbo frames transmission.
2741 */
63c3a66f 2742 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2743 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2744 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2745 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2746 }
2747
4153577a 2748 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2749 /* adjust output voltage */
535ef6e1 2750 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2751 }
2752
4153577a 2753 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2754 tg3_phydsp_write(tp, 0xffb, 0x4000);
2755
953c96e0 2756 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2757 tg3_phy_set_wirespeed(tp);
2758 return 0;
2759}
2760
3a1e19d3
MC		 2761#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2762#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2763#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2764 TG3_GPIO_MSG_NEED_VAUX)
2765#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2766 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2767 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2768 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2769 (TG3_GPIO_MSG_DRVR_PRES << 12))
2770
2771#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2772 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2773 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2774 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2775 (TG3_GPIO_MSG_NEED_VAUX << 12))
2776
2777static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2778{
2779 u32 status, shift;
2780
4153577a
JP		 2781 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2782 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2783 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2784 else
2785 status = tr32(TG3_CPMU_DRV_STATUS);
2786
2787 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2788 status &= ~(TG3_GPIO_MSG_MASK << shift);
2789 status |= (newstat << shift);
2790
4153577a
JP		 2791 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2792 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2793 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2794 else
2795 tw32(TG3_CPMU_DRV_STATUS, status);
2796
2797 return status >> TG3_APE_GPIO_MSG_SHIFT;
2798}
2799
520b2756
MC		 2800static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2801{
2802 if (!tg3_flag(tp, IS_NIC))
2803 return 0;
2804
4153577a
JP		 2805 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2806 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2807 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2808 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2809 return -EIO;
520b2756 2810
3a1e19d3
MC		 2811 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2812
2813 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2814 TG3_GRC_LCLCTL_PWRSW_DELAY);
2815
2816 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2817 } else {
2818 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2819 TG3_GRC_LCLCTL_PWRSW_DELAY);
2820 }
6f5c8f83 2821
520b2756
MC		 2822 return 0;
2823}
2824
2825static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2826{
2827 u32 grc_local_ctrl;
2828
2829 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2830 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2831 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2832 return;
2833
2834 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2835
2836 tw32_wait_f(GRC_LOCAL_CTRL,
2837 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2838 TG3_GRC_LCLCTL_PWRSW_DELAY);
2839
2840 tw32_wait_f(GRC_LOCAL_CTRL,
2841 grc_local_ctrl,
2842 TG3_GRC_LCLCTL_PWRSW_DELAY);
2843
2844 tw32_wait_f(GRC_LOCAL_CTRL,
2845 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2846 TG3_GRC_LCLCTL_PWRSW_DELAY);
2847}
2848
2849static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2850{
2851 if (!tg3_flag(tp, IS_NIC))
2852 return;
2853
4153577a
JP		 2854 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2855 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2856 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2857 (GRC_LCLCTRL_GPIO_OE0 |
2858 GRC_LCLCTRL_GPIO_OE1 |
2859 GRC_LCLCTRL_GPIO_OE2 |
2860 GRC_LCLCTRL_GPIO_OUTPUT0 |
2861 GRC_LCLCTRL_GPIO_OUTPUT1),
2862 TG3_GRC_LCLCTL_PWRSW_DELAY);
2863 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2864 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2865 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2866 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2867 GRC_LCLCTRL_GPIO_OE1 |
2868 GRC_LCLCTRL_GPIO_OE2 |
2869 GRC_LCLCTRL_GPIO_OUTPUT0 |
2870 GRC_LCLCTRL_GPIO_OUTPUT1 |
2871 tp->grc_local_ctrl;
2872 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2873 TG3_GRC_LCLCTL_PWRSW_DELAY);
2874
2875 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2876 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2877 TG3_GRC_LCLCTL_PWRSW_DELAY);
2878
2879 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2880 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2881 TG3_GRC_LCLCTL_PWRSW_DELAY);
2882 } else {
2883 u32 no_gpio2;
2884 u32 grc_local_ctrl = 0;
2885
2886 /* Workaround to prevent overdrawing Amps. */
4153577a 2887 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2888 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2889 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2890 grc_local_ctrl,
2891 TG3_GRC_LCLCTL_PWRSW_DELAY);
2892 }
2893
2894 /* On 5753 and variants, GPIO2 cannot be used. */
2895 no_gpio2 = tp->nic_sram_data_cfg &
2896 NIC_SRAM_DATA_CFG_NO_GPIO2;
2897
2898 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2899 GRC_LCLCTRL_GPIO_OE1 |
2900 GRC_LCLCTRL_GPIO_OE2 |
2901 GRC_LCLCTRL_GPIO_OUTPUT1 |
2902 GRC_LCLCTRL_GPIO_OUTPUT2;
2903 if (no_gpio2) {
2904 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2905 GRC_LCLCTRL_GPIO_OUTPUT2);
2906 }
2907 tw32_wait_f(GRC_LOCAL_CTRL,
2908 tp->grc_local_ctrl | grc_local_ctrl,
2909 TG3_GRC_LCLCTL_PWRSW_DELAY);
2910
2911 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2912
2913 tw32_wait_f(GRC_LOCAL_CTRL,
2914 tp->grc_local_ctrl | grc_local_ctrl,
2915 TG3_GRC_LCLCTL_PWRSW_DELAY);
2916
2917 if (!no_gpio2) {
2918 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2922 }
2923 }
3a1e19d3
MC		 2924}
2925
cd0d7228 2926static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2927{
2928 u32 msg = 0;
2929
2930 /* Serialize power state transitions */
2931 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2932 return;
2933
cd0d7228 2934 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2935 msg = TG3_GPIO_MSG_NEED_VAUX;
2936
2937 msg = tg3_set_function_status(tp, msg);
2938
2939 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2940 goto done;
6f5c8f83 2941
3a1e19d3
MC		 2942 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2943 tg3_pwrsrc_switch_to_vaux(tp);
2944 else
2945 tg3_pwrsrc_die_with_vmain(tp);
2946
2947done:
6f5c8f83 2948 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2949}
2950
cd0d7228 2951static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2952{
683644b7 2953 bool need_vaux = false;
1da177e4 2954
334355aa 2955 /* The GPIOs do something completely different on 57765. */
55086ad9 2956 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2957 return;
2958
4153577a
JP		 2959 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2960 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2961 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2962 tg3_frob_aux_power_5717(tp, include_wol ?
2963 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2964 return;
2965 }
2966
2967 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2968 struct net_device *dev_peer;
2969
2970 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2971
bc1c7567 2972 /* remove_one() may have been run on the peer. */
683644b7
MC		 2973 if (dev_peer) {
2974 struct tg3 *tp_peer = netdev_priv(dev_peer);
2975
63c3a66f 2976 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2977 return;
2978
cd0d7228 2979 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2980 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2981 need_vaux = true;
2982 }
1da177e4
LT		 2983 }
2984
cd0d7228
MC		 2985 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2986 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 2987 need_vaux = true;
2988
520b2756
MC		 2989 if (need_vaux)
2990 tg3_pwrsrc_switch_to_vaux(tp);
2991 else
2992 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 2993}
2994
e8f3f6ca
MC		 2995static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2996{
2997 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2998 return 1;
79eb6904 2999 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3000 if (speed != SPEED_10)
3001 return 1;
3002 } else if (speed == SPEED_10)
3003 return 1;
3004
3005 return 0;
3006}
3007
44f3b503
NS		 3008static bool tg3_phy_power_bug(struct tg3 *tp)
3009{
3010 switch (tg3_asic_rev(tp)) {
3011 case ASIC_REV_5700:
3012 case ASIC_REV_5704:
3013 return true;
3014 case ASIC_REV_5780:
3015 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3016 return true;
3017 return false;
3018 case ASIC_REV_5717:
3019 if (!tp->pci_fn)
3020 return true;
3021 return false;
3022 case ASIC_REV_5719:
3023 case ASIC_REV_5720:
3024 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3025 !tp->pci_fn)
3026 return true;
3027 return false;
3028 }
3029
3030 return false;
3031}
3032
0a459aac 3033static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3034{
ce057f01
MC		 3035 u32 val;
3036
942d1af0
NS		 3037 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3038 return;
3039
f07e9af3 3040 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3041 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3042 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3043 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3044
3045 sg_dig_ctrl |=
3046 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3047 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3048 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3049 }
3f7045c1 3050 return;
5129724a 3051 }
3f7045c1 3052
4153577a 3053 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3054 tg3_bmcr_reset(tp);
3055 val = tr32(GRC_MISC_CFG);
3056 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3057 udelay(40);
3058 return;
f07e9af3 3059 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3060 u32 phytest;
3061 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3062 u32 phy;
3063
3064 tg3_writephy(tp, MII_ADVERTISE, 0);
3065 tg3_writephy(tp, MII_BMCR,
3066 BMCR_ANENABLE | BMCR_ANRESTART);
3067
3068 tg3_writephy(tp, MII_TG3_FET_TEST,
3069 phytest | MII_TG3_FET_SHADOW_EN);
3070 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3071 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3072 tg3_writephy(tp,
3073 MII_TG3_FET_SHDW_AUXMODE4,
3074 phy);
3075 }
3076 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3077 }
3078 return;
0a459aac 3079 } else if (do_low_power) {
715116a1
MC		 3080 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3081 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3082
b4bd2929
MC		 3083 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3084 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3085 MII_TG3_AUXCTL_PCTL_VREG_11V;
3086 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3087 }
3f7045c1 3088
15c3b696
MC		 3089 /* The PHY should not be powered down on some chips because
3090 * of bugs.
3091 */
44f3b503 3092 if (tg3_phy_power_bug(tp))
15c3b696 3093 return;
ce057f01 3094
4153577a
JP		 3095 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3096 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3097 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3098 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3099 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3100 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3101 }
3102
15c3b696
MC		 3103 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3104}
3105
ffbcfed4
MC		 3106/* tp->lock is held. */
3107static int tg3_nvram_lock(struct tg3 *tp)
3108{
63c3a66f 3109 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3110 int i;
3111
3112 if (tp->nvram_lock_cnt == 0) {
3113 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3114 for (i = 0; i < 8000; i++) {
3115 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3116 break;
3117 udelay(20);
3118 }
3119 if (i == 8000) {
3120 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3121 return -ENODEV;
3122 }
3123 }
3124 tp->nvram_lock_cnt++;
3125 }
3126 return 0;
3127}
3128
3129/* tp->lock is held. */
3130static void tg3_nvram_unlock(struct tg3 *tp)
3131{
63c3a66f 3132 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3133 if (tp->nvram_lock_cnt > 0)
3134 tp->nvram_lock_cnt--;
3135 if (tp->nvram_lock_cnt == 0)
3136 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3137 }
3138}
3139
3140/* tp->lock is held. */
3141static void tg3_enable_nvram_access(struct tg3 *tp)
3142{
63c3a66f 3143 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3144 u32 nvaccess = tr32(NVRAM_ACCESS);
3145
3146 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3147 }
3148}
3149
3150/* tp->lock is held. */
3151static void tg3_disable_nvram_access(struct tg3 *tp)
3152{
63c3a66f 3153 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3154 u32 nvaccess = tr32(NVRAM_ACCESS);
3155
3156 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3157 }
3158}
3159
3160static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3161 u32 offset, u32 *val)
3162{
3163 u32 tmp;
3164 int i;
3165
3166 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3167 return -EINVAL;
3168
3169 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3170 EEPROM_ADDR_DEVID_MASK |
3171 EEPROM_ADDR_READ);
3172 tw32(GRC_EEPROM_ADDR,
3173 tmp |
3174 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3175 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3176 EEPROM_ADDR_ADDR_MASK) |
3177 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3178
3179 for (i = 0; i < 1000; i++) {
3180 tmp = tr32(GRC_EEPROM_ADDR);
3181
3182 if (tmp & EEPROM_ADDR_COMPLETE)
3183 break;
3184 msleep(1);
3185 }
3186 if (!(tmp & EEPROM_ADDR_COMPLETE))
3187 return -EBUSY;
3188
62cedd11
MC		 3189 tmp = tr32(GRC_EEPROM_DATA);
3190
3191 /*
3192 * The data will always be opposite the native endian
3193 * format. Perform a blind byteswap to compensate.
3194 */
3195 *val = swab32(tmp);
3196
ffbcfed4
MC		 3197 return 0;
3198}
3199
3200#define NVRAM_CMD_TIMEOUT 10000
3201
3202static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3203{
3204 int i;
3205
3206 tw32(NVRAM_CMD, nvram_cmd);
3207 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3208 udelay(10);
3209 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3210 udelay(10);
3211 break;
3212 }
3213 }
3214
3215 if (i == NVRAM_CMD_TIMEOUT)
3216 return -EBUSY;
3217
3218 return 0;
3219}
3220
3221static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3222{
63c3a66f
JP		 3223 if (tg3_flag(tp, NVRAM) &&
3224 tg3_flag(tp, NVRAM_BUFFERED) &&
3225 tg3_flag(tp, FLASH) &&
3226 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3227 (tp->nvram_jedecnum == JEDEC_ATMEL))
3228
3229 addr = ((addr / tp->nvram_pagesize) <<
3230 ATMEL_AT45DB0X1B_PAGE_POS) +
3231 (addr % tp->nvram_pagesize);
3232
3233 return addr;
3234}
3235
3236static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3237{
63c3a66f
JP		 3238 if (tg3_flag(tp, NVRAM) &&
3239 tg3_flag(tp, NVRAM_BUFFERED) &&
3240 tg3_flag(tp, FLASH) &&
3241 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3242 (tp->nvram_jedecnum == JEDEC_ATMEL))
3243
3244 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3245 tp->nvram_pagesize) +
3246 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3247
3248 return addr;
3249}
3250
e4f34110
MC		 3251/* NOTE: Data read in from NVRAM is byteswapped according to
3252 * the byteswapping settings for all other register accesses.
3253 * tg3 devices are BE devices, so on a BE machine, the data
3254 * returned will be exactly as it is seen in NVRAM. On a LE
3255 * machine, the 32-bit value will be byteswapped.
3256 */
ffbcfed4
MC		 3257static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3258{
3259 int ret;
3260
63c3a66f 3261 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3262 return tg3_nvram_read_using_eeprom(tp, offset, val);
3263
3264 offset = tg3_nvram_phys_addr(tp, offset);
3265
3266 if (offset > NVRAM_ADDR_MSK)
3267 return -EINVAL;
3268
3269 ret = tg3_nvram_lock(tp);
3270 if (ret)
3271 return ret;
3272
3273 tg3_enable_nvram_access(tp);
3274
3275 tw32(NVRAM_ADDR, offset);
3276 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3277 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3278
3279 if (ret == 0)
e4f34110 3280 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3281
3282 tg3_disable_nvram_access(tp);
3283
3284 tg3_nvram_unlock(tp);
3285
3286 return ret;
3287}
3288
a9dc529d
MC		 3289/* Ensures NVRAM data is in bytestream format. */
3290static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3291{
3292 u32 v;
a9dc529d 3293 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3294 if (!res)
a9dc529d 3295 *val = cpu_to_be32(v);
ffbcfed4
MC		 3296 return res;
3297}
3298
dbe9b92a
MC		 3299static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3300 u32 offset, u32 len, u8 *buf)
3301{
3302 int i, j, rc = 0;
3303 u32 val;
3304
3305 for (i = 0; i < len; i += 4) {
3306 u32 addr;
3307 __be32 data;
3308
3309 addr = offset + i;
3310
3311 memcpy(&data, buf + i, 4);
3312
3313 /*
3314 * The SEEPROM interface expects the data to always be opposite
3315 * the native endian format. We accomplish this by reversing
3316 * all the operations that would have been performed on the
3317 * data from a call to tg3_nvram_read_be32().
3318 */
3319 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3320
3321 val = tr32(GRC_EEPROM_ADDR);
3322 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3323
3324 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3325 EEPROM_ADDR_READ);
3326 tw32(GRC_EEPROM_ADDR, val |
3327 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3328 (addr & EEPROM_ADDR_ADDR_MASK) |
3329 EEPROM_ADDR_START |
3330 EEPROM_ADDR_WRITE);
3331
3332 for (j = 0; j < 1000; j++) {
3333 val = tr32(GRC_EEPROM_ADDR);
3334
3335 if (val & EEPROM_ADDR_COMPLETE)
3336 break;
3337 msleep(1);
3338 }
3339 if (!(val & EEPROM_ADDR_COMPLETE)) {
3340 rc = -EBUSY;
3341 break;
3342 }
3343 }
3344
3345 return rc;
3346}
3347
3348/* offset and length are dword aligned */
3349static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3350 u8 *buf)
3351{
3352 int ret = 0;
3353 u32 pagesize = tp->nvram_pagesize;
3354 u32 pagemask = pagesize - 1;
3355 u32 nvram_cmd;
3356 u8 *tmp;
3357
3358 tmp = kmalloc(pagesize, GFP_KERNEL);
3359 if (tmp == NULL)
3360 return -ENOMEM;
3361
3362 while (len) {
3363 int j;
3364 u32 phy_addr, page_off, size;
3365
3366 phy_addr = offset & ~pagemask;
3367
3368 for (j = 0; j < pagesize; j += 4) {
3369 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3370 (__be32 *) (tmp + j));
3371 if (ret)
3372 break;
3373 }
3374 if (ret)
3375 break;
3376
3377 page_off = offset & pagemask;
3378 size = pagesize;
3379 if (len < size)
3380 size = len;
3381
3382 len -= size;
3383
3384 memcpy(tmp + page_off, buf, size);
3385
3386 offset = offset + (pagesize - page_off);
3387
3388 tg3_enable_nvram_access(tp);
3389
3390 /*
3391 * Before we can erase the flash page, we need
3392 * to issue a special "write enable" command.
3393 */
3394 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3395
3396 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3397 break;
3398
3399 /* Erase the target page */
3400 tw32(NVRAM_ADDR, phy_addr);
3401
3402 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3403 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3404
3405 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3406 break;
3407
3408 /* Issue another write enable to start the write. */
3409 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3410
3411 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3412 break;
3413
3414 for (j = 0; j < pagesize; j += 4) {
3415 __be32 data;
3416
3417 data = *((__be32 *) (tmp + j));
3418
3419 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3420
3421 tw32(NVRAM_ADDR, phy_addr + j);
3422
3423 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3424 NVRAM_CMD_WR;
3425
3426 if (j == 0)
3427 nvram_cmd |= NVRAM_CMD_FIRST;
3428 else if (j == (pagesize - 4))
3429 nvram_cmd |= NVRAM_CMD_LAST;
3430
3431 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3432 if (ret)
3433 break;
3434 }
3435 if (ret)
3436 break;
3437 }
3438
3439 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3440 tg3_nvram_exec_cmd(tp, nvram_cmd);
3441
3442 kfree(tmp);
3443
3444 return ret;
3445}
3446
3447/* offset and length are dword aligned */
3448static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3449 u8 *buf)
3450{
3451 int i, ret = 0;
3452
3453 for (i = 0; i < len; i += 4, offset += 4) {
3454 u32 page_off, phy_addr, nvram_cmd;
3455 __be32 data;
3456
3457 memcpy(&data, buf + i, 4);
3458 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3459
3460 page_off = offset % tp->nvram_pagesize;
3461
3462 phy_addr = tg3_nvram_phys_addr(tp, offset);
3463
dbe9b92a
MC		 3464 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3465
3466 if (page_off == 0 || i == 0)
3467 nvram_cmd |= NVRAM_CMD_FIRST;
3468 if (page_off == (tp->nvram_pagesize - 4))
3469 nvram_cmd |= NVRAM_CMD_LAST;
3470
3471 if (i == (len - 4))
3472 nvram_cmd |= NVRAM_CMD_LAST;
3473
42278224
MC		 3474 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3475 !tg3_flag(tp, FLASH) ||
3476 !tg3_flag(tp, 57765_PLUS))
3477 tw32(NVRAM_ADDR, phy_addr);
3478
4153577a 3479 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3480 !tg3_flag(tp, 5755_PLUS) &&
3481 (tp->nvram_jedecnum == JEDEC_ST) &&
3482 (nvram_cmd & NVRAM_CMD_FIRST)) {
3483 u32 cmd;
3484
3485 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3486 ret = tg3_nvram_exec_cmd(tp, cmd);
3487 if (ret)
3488 break;
3489 }
3490 if (!tg3_flag(tp, FLASH)) {
3491 /* We always do complete word writes to eeprom. */
3492 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3493 }
3494
3495 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3496 if (ret)
3497 break;
3498 }
3499 return ret;
3500}
3501
3502/* offset and length are dword aligned */
3503static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3504{
3505 int ret;
3506
3507 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3508 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3509 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3510 udelay(40);
3511 }
3512
3513 if (!tg3_flag(tp, NVRAM)) {
3514 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3515 } else {
3516 u32 grc_mode;
3517
3518 ret = tg3_nvram_lock(tp);
3519 if (ret)
3520 return ret;
3521
3522 tg3_enable_nvram_access(tp);
3523 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3524 tw32(NVRAM_WRITE1, 0x406);
3525
3526 grc_mode = tr32(GRC_MODE);
3527 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3528
3529 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3530 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3531 buf);
3532 } else {
3533 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3534 buf);
3535 }
3536
3537 grc_mode = tr32(GRC_MODE);
3538 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3539
3540 tg3_disable_nvram_access(tp);
3541 tg3_nvram_unlock(tp);
3542 }
3543
3544 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3545 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3546 udelay(40);
3547 }
3548
3549 return ret;
3550}
3551
997b4f13
MC		 3552#define RX_CPU_SCRATCH_BASE 0x30000
3553#define RX_CPU_SCRATCH_SIZE 0x04000
3554#define TX_CPU_SCRATCH_BASE 0x34000
3555#define TX_CPU_SCRATCH_SIZE 0x04000
3556
3557/* tp->lock is held. */
837c45bb 3558static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3559{
3560 int i;
837c45bb 3561 const int iters = 10000;
997b4f13 3562
837c45bb
NS		 3563 for (i = 0; i < iters; i++) {
3564 tw32(cpu_base + CPU_STATE, 0xffffffff);
3565 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3566 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3567 break;
6d446ec3
GS		 3568 if (pci_channel_offline(tp->pdev))
3569 return -EBUSY;
837c45bb
NS		 3570 }
3571
3572 return (i == iters) ? -EBUSY : 0;
3573}
3574
3575/* tp->lock is held. */
3576static int tg3_rxcpu_pause(struct tg3 *tp)
3577{
3578 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3579
3580 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3581 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3582 udelay(10);
3583
3584 return rc;
3585}
3586
3587/* tp->lock is held. */
3588static int tg3_txcpu_pause(struct tg3 *tp)
3589{
3590 return tg3_pause_cpu(tp, TX_CPU_BASE);
3591}
3592
3593/* tp->lock is held. */
3594static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3595{
3596 tw32(cpu_base + CPU_STATE, 0xffffffff);
3597 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3598}
3599
3600/* tp->lock is held. */
3601static void tg3_rxcpu_resume(struct tg3 *tp)
3602{
3603 tg3_resume_cpu(tp, RX_CPU_BASE);
3604}
3605
3606/* tp->lock is held. */
3607static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3608{
3609 int rc;
3610
3611 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3612
4153577a 3613 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3614 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3615
3616 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3617 return 0;
3618 }
837c45bb
NS		 3619 if (cpu_base == RX_CPU_BASE) {
3620 rc = tg3_rxcpu_pause(tp);
997b4f13 3621 } else {
7e6c63f0
HM		 3622 /*
3623 * There is only an Rx CPU for the 5750 derivative in the
3624 * BCM4785.
3625 */
3626 if (tg3_flag(tp, IS_SSB_CORE))
3627 return 0;
3628
837c45bb 3629 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3630 }
3631
837c45bb 3632 if (rc) {
997b4f13 3633 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3634 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3635 return -ENODEV;
3636 }
3637
3638 /* Clear firmware's nvram arbitration. */
3639 if (tg3_flag(tp, NVRAM))
3640 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3641 return 0;
3642}
3643
31f11a95
NS		 3644static int tg3_fw_data_len(struct tg3 *tp,
3645 const struct tg3_firmware_hdr *fw_hdr)
3646{
3647 int fw_len;
3648
3649 /* Non fragmented firmware have one firmware header followed by a
3650 * contiguous chunk of data to be written. The length field in that
3651 * header is not the length of data to be written but the complete
3652 * length of the bss. The data length is determined based on
3653 * tp->fw->size minus headers.
3654 *
3655 * Fragmented firmware have a main header followed by multiple
3656 * fragments. Each fragment is identical to non fragmented firmware
3657 * with a firmware header followed by a contiguous chunk of data. In
3658 * the main header, the length field is unused and set to 0xffffffff.
3659 * In each fragment header the length is the entire size of that
3660 * fragment i.e. fragment data + header length. Data length is
3661 * therefore length field in the header minus TG3_FW_HDR_LEN.
3662 */
3663 if (tp->fw_len == 0xffffffff)
3664 fw_len = be32_to_cpu(fw_hdr->len);
3665 else
3666 fw_len = tp->fw->size;
3667
3668 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3669}
3670
997b4f13
MC		 3671/* tp->lock is held. */
3672static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3673 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3674 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3675{
c4dab506 3676 int err, i;
997b4f13 3677 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3678 int total_len = tp->fw->size;
997b4f13
MC		 3679
3680 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3681 netdev_err(tp->dev,
3682 "%s: Trying to load TX cpu firmware which is 5705\n",
3683 __func__);
3684 return -EINVAL;
3685 }
3686
c4dab506 3687 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3688 write_op = tg3_write_mem;
3689 else
3690 write_op = tg3_write_indirect_reg32;
3691
c4dab506
NS		 3692 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3693 /* It is possible that bootcode is still loading at this point.
3694 * Get the nvram lock first before halting the cpu.
3695 */
3696 int lock_err = tg3_nvram_lock(tp);
3697 err = tg3_halt_cpu(tp, cpu_base);
3698 if (!lock_err)
3699 tg3_nvram_unlock(tp);
3700 if (err)
3701 goto out;
997b4f13 3702
c4dab506
NS		 3703 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3704 write_op(tp, cpu_scratch_base + i, 0);
3705 tw32(cpu_base + CPU_STATE, 0xffffffff);
3706 tw32(cpu_base + CPU_MODE,
3707 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3708 } else {
3709 /* Subtract additional main header for fragmented firmware and
3710 * advance to the first fragment
3711 */
3712 total_len -= TG3_FW_HDR_LEN;
3713 fw_hdr++;
3714 }
77997ea3 3715
31f11a95
NS		 3716 do {
3717 u32 *fw_data = (u32 *)(fw_hdr + 1);
3718 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3719 write_op(tp, cpu_scratch_base +
3720 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3721 (i * sizeof(u32)),
3722 be32_to_cpu(fw_data[i]));
3723
3724 total_len -= be32_to_cpu(fw_hdr->len);
3725
3726 /* Advance to next fragment */
3727 fw_hdr = (struct tg3_firmware_hdr *)
3728 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3729 } while (total_len > 0);
997b4f13
MC		 3730
3731 err = 0;
3732
3733out:
3734 return err;
3735}
3736
f4bffb28
NS		 3737/* tp->lock is held. */
3738static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3739{
3740 int i;
3741 const int iters = 5;
3742
3743 tw32(cpu_base + CPU_STATE, 0xffffffff);
3744 tw32_f(cpu_base + CPU_PC, pc);
3745
3746 for (i = 0; i < iters; i++) {
3747 if (tr32(cpu_base + CPU_PC) == pc)
3748 break;
3749 tw32(cpu_base + CPU_STATE, 0xffffffff);
3750 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3751 tw32_f(cpu_base + CPU_PC, pc);
3752 udelay(1000);
3753 }
3754
3755 return (i == iters) ? -EBUSY : 0;
3756}
3757
997b4f13
MC		 3758/* tp->lock is held. */
3759static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3760{
77997ea3 3761 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3762 int err;
997b4f13 3763
77997ea3 3764 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3765
3766 /* Firmware blob starts with version numbers, followed by
3767 start address and length. We are setting complete length.
3768 length = end_address_of_bss - start_address_of_text.
3769 Remainder is the blob to be loaded contiguously
3770 from start address. */
3771
997b4f13
MC		 3772 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3773 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3774 fw_hdr);
997b4f13
MC		 3775 if (err)
3776 return err;
3777
3778 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3779 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3780 fw_hdr);
997b4f13
MC		 3781 if (err)
3782 return err;
3783
3784 /* Now startup only the RX cpu. */
77997ea3
NS		 3785 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3786 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3787 if (err) {
997b4f13
MC		 3788 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3789 "should be %08x\n", __func__,
77997ea3
NS		 3790 tr32(RX_CPU_BASE + CPU_PC),
3791 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3792 return -ENODEV;
3793 }
837c45bb
NS		 3794
3795 tg3_rxcpu_resume(tp);
997b4f13
MC		 3796
3797 return 0;
3798}
3799
c4dab506
NS		 3800static int tg3_validate_rxcpu_state(struct tg3 *tp)
3801{
3802 const int iters = 1000;
3803 int i;
3804 u32 val;
3805
3806 /* Wait for boot code to complete initialization and enter service
3807 * loop. It is then safe to download service patches
3808 */
3809 for (i = 0; i < iters; i++) {
3810 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3811 break;
3812
3813 udelay(10);
3814 }
3815
3816 if (i == iters) {
3817 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3818 return -EBUSY;
3819 }
3820
3821 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3822 if (val & 0xff) {
3823 netdev_warn(tp->dev,
3824 "Other patches exist. Not downloading EEE patch\n");
3825 return -EEXIST;
3826 }
3827
3828 return 0;
3829}
3830
3831/* tp->lock is held. */
3832static void tg3_load_57766_firmware(struct tg3 *tp)
3833{
3834 struct tg3_firmware_hdr *fw_hdr;
3835
3836 if (!tg3_flag(tp, NO_NVRAM))
3837 return;
3838
3839 if (tg3_validate_rxcpu_state(tp))
3840 return;
3841
3842 if (!tp->fw)
3843 return;
3844
3845 /* This firmware blob has a different format than older firmware
3846 * releases as given below. The main difference is we have fragmented
3847 * data to be written to non-contiguous locations.
3848 *
3849 * In the beginning we have a firmware header identical to other
3850 * firmware which consists of version, base addr and length. The length
3851 * here is unused and set to 0xffffffff.
3852 *
3853 * This is followed by a series of firmware fragments which are
3854 * individually identical to previous firmware. i.e. they have the
3855 * firmware header and followed by data for that fragment. The version
3856 * field of the individual fragment header is unused.
3857 */
3858
3859 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3860 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3861 return;
3862
3863 if (tg3_rxcpu_pause(tp))
3864 return;
3865
3866 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3867 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3868
3869 tg3_rxcpu_resume(tp);
3870}
3871
997b4f13
MC		 3872/* tp->lock is held. */
3873static int tg3_load_tso_firmware(struct tg3 *tp)
3874{
77997ea3 3875 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3876 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3877 int err;
997b4f13 3878
1caf13eb 3879 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3880 return 0;
3881
77997ea3 3882 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3883
3884 /* Firmware blob starts with version numbers, followed by
3885 start address and length. We are setting complete length.
3886 length = end_address_of_bss - start_address_of_text.
3887 Remainder is the blob to be loaded contiguously
3888 from start address. */
3889
997b4f13 3890 cpu_scratch_size = tp->fw_len;
997b4f13 3891
4153577a 3892 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3893 cpu_base = RX_CPU_BASE;
3894 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3895 } else {
3896 cpu_base = TX_CPU_BASE;
3897 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3898 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3899 }
3900
3901 err = tg3_load_firmware_cpu(tp, cpu_base,
3902 cpu_scratch_base, cpu_scratch_size,
77997ea3 3903 fw_hdr);
997b4f13
MC		 3904 if (err)
3905 return err;
3906
3907 /* Now startup the cpu. */
77997ea3
NS		 3908 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3909 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3910 if (err) {
997b4f13
MC		 3911 netdev_err(tp->dev,
3912 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3913 __func__, tr32(cpu_base + CPU_PC),
3914 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3915 return -ENODEV;
3916 }
837c45bb
NS		 3917
3918 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3919 return 0;
3920}
3921
3922
3f007891 3923/* tp->lock is held. */
953c96e0 3924static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891
MC		 3925{
3926 u32 addr_high, addr_low;
3927 int i;
3928
3929 addr_high = ((tp->dev->dev_addr[0] << 8) |
3930 tp->dev->dev_addr[1]);
3931 addr_low = ((tp->dev->dev_addr[2] << 24) |
3932 (tp->dev->dev_addr[3] << 16) |
3933 (tp->dev->dev_addr[4] << 8) |
3934 (tp->dev->dev_addr[5] << 0));
3935 for (i = 0; i < 4; i++) {
3936 if (i == 1 && skip_mac_1)
3937 continue;
3938 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3939 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3940 }
3941
4153577a
JP		 3942 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3943 tg3_asic_rev(tp) == ASIC_REV_5704) {
3f007891
MC		 3944 for (i = 0; i < 12; i++) {
3945 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3946 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3947 }
3948 }
3949
3950 addr_high = (tp->dev->dev_addr[0] +
3951 tp->dev->dev_addr[1] +
3952 tp->dev->dev_addr[2] +
3953 tp->dev->dev_addr[3] +
3954 tp->dev->dev_addr[4] +
3955 tp->dev->dev_addr[5]) &
3956 TX_BACKOFF_SEED_MASK;
3957 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3958}
3959
c866b7ea 3960static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 3961{
c866b7ea
RW		 3962 /*
3963 * Make sure register accesses (indirect or otherwise) will function
3964 * correctly.
1da177e4
LT		 3965 */
3966 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 3967 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3968}
1da177e4 3969
c866b7ea
RW		 3970static int tg3_power_up(struct tg3 *tp)
3971{
bed9829f 3972 int err;
8c6bda1a 3973
bed9829f 3974 tg3_enable_register_access(tp);
1da177e4 3975
bed9829f
MC		 3976 err = pci_set_power_state(tp->pdev, PCI_D0);
3977 if (!err) {
3978 /* Switch out of Vaux if it is a NIC */
3979 tg3_pwrsrc_switch_to_vmain(tp);
3980 } else {
3981 netdev_err(tp->dev, "Transition to D0 failed\n");
3982 }
1da177e4 3983
bed9829f 3984 return err;
c866b7ea 3985}
1da177e4 3986
953c96e0 3987static int tg3_setup_phy(struct tg3 *, bool);
4b409522 3988
c866b7ea
RW		 3989static int tg3_power_down_prepare(struct tg3 *tp)
3990{
3991 u32 misc_host_ctrl;
3992 bool device_should_wake, do_low_power;
3993
3994 tg3_enable_register_access(tp);
5e7dfd0f
MC		 3995
3996 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 3997 if (tg3_flag(tp, CLKREQ_BUG))
3998 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
3999 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4000
1da177e4
LT		 4001 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4002 tw32(TG3PCI_MISC_HOST_CTRL,
4003 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4004
c866b7ea 4005 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4006 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4007
63c3a66f 4008 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4009 do_low_power = false;
f07e9af3 4010 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4011 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4012 struct phy_device *phydev;
0a459aac 4013 u32 phyid, advertising;
b02fd9e3 4014
3f0e3ad7 4015 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
b02fd9e3 4016
80096068 4017 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4018
c6700ce2
MC		 4019 tp->link_config.speed = phydev->speed;
4020 tp->link_config.duplex = phydev->duplex;
4021 tp->link_config.autoneg = phydev->autoneg;
4022 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4023
4024 advertising = ADVERTISED_TP |
4025 ADVERTISED_Pause |
4026 ADVERTISED_Autoneg |
4027 ADVERTISED_10baseT_Half;
4028
63c3a66f
JP		 4029 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4030 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4031 advertising |=
4032 ADVERTISED_100baseT_Half |
4033 ADVERTISED_100baseT_Full |
4034 ADVERTISED_10baseT_Full;
4035 else
4036 advertising |= ADVERTISED_10baseT_Full;
4037 }
4038
4039 phydev->advertising = advertising;
4040
4041 phy_start_aneg(phydev);
0a459aac
MC		 4042
4043 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4044 if (phyid != PHY_ID_BCMAC131) {
4045 phyid &= PHY_BCM_OUI_MASK;
4046 if (phyid == PHY_BCM_OUI_1 ||
4047 phyid == PHY_BCM_OUI_2 ||
4048 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4049 do_low_power = true;
4050 }
b02fd9e3 4051 }
dd477003 4052 } else {
2023276e 4053 do_low_power = true;
0a459aac 4054
c6700ce2 4055 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4056 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4057
2855b9fe 4058 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4059 tg3_setup_phy(tp, false);
1da177e4
LT		 4060 }
4061
4153577a 4062 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4063 u32 val;
4064
4065 val = tr32(GRC_VCPU_EXT_CTRL);
4066 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4067 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4068 int i;
4069 u32 val;
4070
4071 for (i = 0; i < 200; i++) {
4072 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4073 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4074 break;
4075 msleep(1);
4076 }
4077 }
63c3a66f 4078 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4079 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4080 WOL_DRV_STATE_SHUTDOWN |
4081 WOL_DRV_WOL |
4082 WOL_SET_MAGIC_PKT);
6921d201 4083
05ac4cb7 4084 if (device_should_wake) {
1da177e4
LT		 4085 u32 mac_mode;
4086
f07e9af3 4087 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4088 if (do_low_power &&
4089 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4090 tg3_phy_auxctl_write(tp,
4091 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4092 MII_TG3_AUXCTL_PCTL_WOL_EN |
4093 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4094 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4095 udelay(40);
4096 }
1da177e4 4097
f07e9af3 4098 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4099 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4100 else if (tp->phy_flags &
4101 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4102 if (tp->link_config.active_speed == SPEED_1000)
4103 mac_mode = MAC_MODE_PORT_MODE_GMII;
4104 else
4105 mac_mode = MAC_MODE_PORT_MODE_MII;
4106 } else
3f7045c1 4107 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4108
e8f3f6ca 4109 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4110 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4111 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4112 SPEED_100 : SPEED_10;
4113 if (tg3_5700_link_polarity(tp, speed))
4114 mac_mode |= MAC_MODE_LINK_POLARITY;
4115 else
4116 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4117 }
1da177e4
LT		 4118 } else {
4119 mac_mode = MAC_MODE_PORT_MODE_TBI;
4120 }
4121
63c3a66f 4122 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4123 tw32(MAC_LED_CTRL, tp->led_ctrl);
4124
05ac4cb7 4125 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4126 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4127 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4128 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4129
63c3a66f 4130 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4131 mac_mode |= MAC_MODE_APE_TX_EN |
4132 MAC_MODE_APE_RX_EN |
4133 MAC_MODE_TDE_ENABLE;
3bda1258 4134
1da177e4
LT		 4135 tw32_f(MAC_MODE, mac_mode);
4136 udelay(100);
4137
4138 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4139 udelay(10);
4140 }
4141
63c3a66f 4142 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4143 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4144 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4145 u32 base_val;
4146
4147 base_val = tp->pci_clock_ctrl;
4148 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4149 CLOCK_CTRL_TXCLK_DISABLE);
4150
b401e9e2
MC		 4151 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4152 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4153 } else if (tg3_flag(tp, 5780_CLASS) ||
4154 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4155 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4156 /* do nothing */
63c3a66f 4157 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4158 u32 newbits1, newbits2;
4159
4153577a
JP		 4160 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4161 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4162 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4163 CLOCK_CTRL_TXCLK_DISABLE |
4164 CLOCK_CTRL_ALTCLK);
4165 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4166 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4167 newbits1 = CLOCK_CTRL_625_CORE;
4168 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4169 } else {
4170 newbits1 = CLOCK_CTRL_ALTCLK;
4171 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4172 }
4173
b401e9e2
MC		 4174 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4175 40);
1da177e4 4176
b401e9e2
MC		 4177 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4178 40);
1da177e4 4179
63c3a66f 4180 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4181 u32 newbits3;
4182
4153577a
JP		 4183 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4184 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4185 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4186 CLOCK_CTRL_TXCLK_DISABLE |
4187 CLOCK_CTRL_44MHZ_CORE);
4188 } else {
4189 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4190 }
4191
b401e9e2
MC		 4192 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4193 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4194 }
4195 }
4196
63c3a66f 4197 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4198 tg3_power_down_phy(tp, do_low_power);
6921d201 4199
cd0d7228 4200 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4201
4202 /* Workaround for unstable PLL clock */
7e6c63f0 4203 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4204 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4205 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4206 u32 val = tr32(0x7d00);
4207
4208 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4209 tw32(0x7d00, val);
63c3a66f 4210 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4211 int err;
4212
4213 err = tg3_nvram_lock(tp);
1da177e4 4214 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4215 if (!err)
4216 tg3_nvram_unlock(tp);
6921d201 4217 }
1da177e4
LT		 4218 }
4219
bbadf503
MC		 4220 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4221
2e460fc0
NS		 4222 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4223
c866b7ea
RW		 4224 return 0;
4225}
12dac075 4226
c866b7ea
RW		 4227static void tg3_power_down(struct tg3 *tp)
4228{
63c3a66f 4229 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4230 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4231}
4232
1da177e4
LT		 4233static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4234{
4235 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4236 case MII_TG3_AUX_STAT_10HALF:
4237 *speed = SPEED_10;
4238 *duplex = DUPLEX_HALF;
4239 break;
4240
4241 case MII_TG3_AUX_STAT_10FULL:
4242 *speed = SPEED_10;
4243 *duplex = DUPLEX_FULL;
4244 break;
4245
4246 case MII_TG3_AUX_STAT_100HALF:
4247 *speed = SPEED_100;
4248 *duplex = DUPLEX_HALF;
4249 break;
4250
4251 case MII_TG3_AUX_STAT_100FULL:
4252 *speed = SPEED_100;
4253 *duplex = DUPLEX_FULL;
4254 break;
4255
4256 case MII_TG3_AUX_STAT_1000HALF:
4257 *speed = SPEED_1000;
4258 *duplex = DUPLEX_HALF;
4259 break;
4260
4261 case MII_TG3_AUX_STAT_1000FULL:
4262 *speed = SPEED_1000;
4263 *duplex = DUPLEX_FULL;
4264 break;
4265
4266 default:
f07e9af3 4267 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4268 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4269 SPEED_10;
4270 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4271 DUPLEX_HALF;
4272 break;
4273 }
e740522e
MC		 4274 *speed = SPEED_UNKNOWN;
4275 *duplex = DUPLEX_UNKNOWN;
1da177e4 4276 break;
855e1111 4277 }
1da177e4
LT		 4278}
4279
42b64a45 4280static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4281{
42b64a45
MC		 4282 int err = 0;
4283 u32 val, new_adv;
1da177e4 4284
42b64a45 4285 new_adv = ADVERTISE_CSMA;
202ff1c2 4286 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4287 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4288
42b64a45
MC		 4289 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4290 if (err)
4291 goto done;
ba4d07a8 4292
4f272096
MC		 4293 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4294 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4295
4153577a
JP		 4296 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4297 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4298 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4299
4f272096
MC		 4300 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4301 if (err)
4302 goto done;
4303 }
1da177e4 4304
42b64a45
MC		 4305 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4306 goto done;
52b02d04 4307
42b64a45
MC		 4308 tw32(TG3_CPMU_EEE_MODE,
4309 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4310
daf3ec68 4311 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4312 if (!err) {
4313 u32 err2;
52b02d04 4314
b715ce94
MC		 4315 val = 0;
4316 /* Advertise 100-BaseTX EEE ability */
4317 if (advertise & ADVERTISED_100baseT_Full)
4318 val |= MDIO_AN_EEE_ADV_100TX;
4319 /* Advertise 1000-BaseT EEE ability */
4320 if (advertise & ADVERTISED_1000baseT_Full)
4321 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4322
4323 if (!tp->eee.eee_enabled) {
4324 val = 0;
4325 tp->eee.advertised = 0;
4326 } else {
4327 tp->eee.advertised = advertise &
4328 (ADVERTISED_100baseT_Full |
4329 ADVERTISED_1000baseT_Full);
4330 }
4331
b715ce94
MC		 4332 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4333 if (err)
4334 val = 0;
4335
4153577a 4336 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4337 case ASIC_REV_5717:
4338 case ASIC_REV_57765:
55086ad9 4339 case ASIC_REV_57766:
21a00ab2 4340 case ASIC_REV_5719:
b715ce94
MC		 4341 /* If we advertised any eee advertisements above... */
4342 if (val)
4343 val = MII_TG3_DSP_TAP26_ALNOKO |
4344 MII_TG3_DSP_TAP26_RMRXSTO |
4345 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4346 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4347 /* Fall through */
4348 case ASIC_REV_5720:
c65a17f4 4349 case ASIC_REV_5762:
be671947
MC		 4350 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4351 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4352 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4353 }
52b02d04 4354
daf3ec68 4355 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4356 if (!err)
4357 err = err2;
4358 }
4359
4360done:
4361 return err;
4362}
4363
4364static void tg3_phy_copper_begin(struct tg3 *tp)
4365{
d13ba512
MC		 4366 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4367 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4368 u32 adv, fc;
4369
942d1af0
NS		 4370 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4371 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4372 adv = ADVERTISED_10baseT_Half |
4373 ADVERTISED_10baseT_Full;
4374 if (tg3_flag(tp, WOL_SPEED_100MB))
4375 adv |= ADVERTISED_100baseT_Half |
4376 ADVERTISED_100baseT_Full;
942d1af0
NS		 4377 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
4378 adv |= ADVERTISED_1000baseT_Half |
4379 ADVERTISED_1000baseT_Full;
d13ba512
MC		 4380
4381 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4382 } else {
d13ba512
MC		 4383 adv = tp->link_config.advertising;
4384 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4385 adv &= ~(ADVERTISED_1000baseT_Half |
4386 ADVERTISED_1000baseT_Full);
4387
4388 fc = tp->link_config.flowctrl;
52b02d04 4389 }
52b02d04 4390
d13ba512 4391 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4392
942d1af0
NS		 4393 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4394 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4395 /* Normally during power down we want to autonegotiate
4396 * the lowest possible speed for WOL. However, to avoid
4397 * link flap, we leave it untouched.
4398 */
4399 return;
4400 }
4401
d13ba512
MC		 4402 tg3_writephy(tp, MII_BMCR,
4403 BMCR_ANENABLE | BMCR_ANRESTART);
4404 } else {
4405 int i;
1da177e4
LT		 4406 u32 bmcr, orig_bmcr;
4407
4408 tp->link_config.active_speed = tp->link_config.speed;
4409 tp->link_config.active_duplex = tp->link_config.duplex;
4410
7c6cdead
NS		 4411 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4412 /* With autoneg disabled, 5715 only links up when the
4413 * advertisement register has the configured speed
4414 * enabled.
4415 */
4416 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4417 }
4418
1da177e4
LT		 4419 bmcr = 0;
4420 switch (tp->link_config.speed) {
4421 default:
4422 case SPEED_10:
4423 break;
4424
4425 case SPEED_100:
4426 bmcr |= BMCR_SPEED100;
4427 break;
4428
4429 case SPEED_1000:
221c5637 4430 bmcr |= BMCR_SPEED1000;
1da177e4 4431 break;
855e1111 4432 }
1da177e4
LT		 4433
4434 if (tp->link_config.duplex == DUPLEX_FULL)
4435 bmcr |= BMCR_FULLDPLX;
4436
4437 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4438 (bmcr != orig_bmcr)) {
4439 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4440 for (i = 0; i < 1500; i++) {
4441 u32 tmp;
4442
4443 udelay(10);
4444 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4445 tg3_readphy(tp, MII_BMSR, &tmp))
4446 continue;
4447 if (!(tmp & BMSR_LSTATUS)) {
4448 udelay(40);
4449 break;
4450 }
4451 }
4452 tg3_writephy(tp, MII_BMCR, bmcr);
4453 udelay(40);
4454 }
1da177e4
LT		 4455 }
4456}
4457
fdad8de4
NS		 4458static int tg3_phy_pull_config(struct tg3 *tp)
4459{
4460 int err;
4461 u32 val;
4462
4463 err = tg3_readphy(tp, MII_BMCR, &val);
4464 if (err)
4465 goto done;
4466
4467 if (!(val & BMCR_ANENABLE)) {
4468 tp->link_config.autoneg = AUTONEG_DISABLE;
4469 tp->link_config.advertising = 0;
4470 tg3_flag_clear(tp, PAUSE_AUTONEG);
4471
4472 err = -EIO;
4473
4474 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4475 case 0:
4476 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4477 goto done;
4478
4479 tp->link_config.speed = SPEED_10;
4480 break;
4481 case BMCR_SPEED100:
4482 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4483 goto done;
4484
4485 tp->link_config.speed = SPEED_100;
4486 break;
4487 case BMCR_SPEED1000:
4488 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4489 tp->link_config.speed = SPEED_1000;
4490 break;
4491 }
4492 /* Fall through */
4493 default:
4494 goto done;
4495 }
4496
4497 if (val & BMCR_FULLDPLX)
4498 tp->link_config.duplex = DUPLEX_FULL;
4499 else
4500 tp->link_config.duplex = DUPLEX_HALF;
4501
4502 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4503
4504 err = 0;
4505 goto done;
4506 }
4507
4508 tp->link_config.autoneg = AUTONEG_ENABLE;
4509 tp->link_config.advertising = ADVERTISED_Autoneg;
4510 tg3_flag_set(tp, PAUSE_AUTONEG);
4511
4512 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4513 u32 adv;
4514
4515 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4516 if (err)
4517 goto done;
4518
4519 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4520 tp->link_config.advertising |= adv | ADVERTISED_TP;
4521
4522 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4523 } else {
4524 tp->link_config.advertising |= ADVERTISED_FIBRE;
4525 }
4526
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 u32 adv;
4529
4530 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4531 err = tg3_readphy(tp, MII_CTRL1000, &val);
4532 if (err)
4533 goto done;
4534
4535 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4536 } else {
4537 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4538 if (err)
4539 goto done;
4540
4541 adv = tg3_decode_flowctrl_1000X(val);
4542 tp->link_config.flowctrl = adv;
4543
4544 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4545 adv = mii_adv_to_ethtool_adv_x(val);
4546 }
4547
4548 tp->link_config.advertising |= adv;
4549 }
4550
4551done:
4552 return err;
4553}
4554
1da177e4
LT		 4555static int tg3_init_5401phy_dsp(struct tg3 *tp)
4556{
4557 int err;
4558
4559 /* Turn off tap power management. */
4560 /* Set Extended packet length bit */
b4bd2929 4561 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4562
6ee7c0a0
MC		 4563 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4564 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4565 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4566 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4567 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4568
4569 udelay(40);
4570
4571 return err;
4572}
4573
ed1ff5c3
NS		 4574static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4575{
5b6c273a 4576 struct ethtool_eee eee;
ed1ff5c3
NS		 4577
4578 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4579 return true;
4580
5b6c273a 4581 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4582
5b6c273a
NS		 4583 if (tp->eee.eee_enabled) {
4584 if (tp->eee.advertised != eee.advertised ||
4585 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4586 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4587 return false;
4588 } else {
4589 /* EEE is disabled but we're advertising */
4590 if (eee.advertised)
4591 return false;
4592 }
ed1ff5c3
NS		 4593
4594 return true;
4595}
4596
e2bf73e7 4597static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4598{
e2bf73e7 4599 u32 advmsk, tgtadv, advertising;
3600d918 4600
e2bf73e7
MC		 4601 advertising = tp->link_config.advertising;
4602 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4603
e2bf73e7
MC		 4604 advmsk = ADVERTISE_ALL;
4605 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4606 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4607 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4608 }
1da177e4 4609
e2bf73e7
MC		 4610 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4611 return false;
4612
4613 if ((*lcladv & advmsk) != tgtadv)
4614 return false;
b99d2a57 4615
f07e9af3 4616 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4617 u32 tg3_ctrl;
4618
e2bf73e7 4619 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4620
221c5637 4621 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4622 return false;
1da177e4 4623
3198e07f 4624 if (tgtadv &&
4153577a
JP		 4625 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4626 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4627 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4628 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4629 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4630 } else {
4631 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4632 }
4633
e2bf73e7
MC		 4634 if (tg3_ctrl != tgtadv)
4635 return false;
ef167e27
MC		 4636 }
4637
e2bf73e7 4638 return true;
ef167e27
MC		 4639}
4640
859edb26
MC		 4641static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4642{
4643 u32 lpeth = 0;
4644
4645 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4646 u32 val;
4647
4648 if (tg3_readphy(tp, MII_STAT1000, &val))
4649 return false;
4650
4651 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4652 }
4653
4654 if (tg3_readphy(tp, MII_LPA, rmtadv))
4655 return false;
4656
4657 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4658 tp->link_config.rmt_adv = lpeth;
4659
4660 return true;
4661}
4662
953c96e0 4663static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4664{
4665 if (curr_link_up != tp->link_up) {
4666 if (curr_link_up) {
84421b99 4667 netif_carrier_on(tp->dev);
f4a46d1f 4668 } else {
84421b99 4669 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4670 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4671 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4672 }
4673
4674 tg3_link_report(tp);
4675 return true;
4676 }
4677
4678 return false;
4679}
4680
3310e248
MC		 4681static void tg3_clear_mac_status(struct tg3 *tp)
4682{
4683 tw32(MAC_EVENT, 0);
4684
4685 tw32_f(MAC_STATUS,
4686 MAC_STATUS_SYNC_CHANGED |
4687 MAC_STATUS_CFG_CHANGED |
4688 MAC_STATUS_MI_COMPLETION |
4689 MAC_STATUS_LNKSTATE_CHANGED);
4690 udelay(40);
4691}
4692
9e2ecbeb
NS		 4693static void tg3_setup_eee(struct tg3 *tp)
4694{
4695 u32 val;
4696
4697 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4698 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4699 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4700 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4701
4702 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4703
4704 tw32_f(TG3_CPMU_EEE_CTRL,
4705 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4706
4707 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4708 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4709 TG3_CPMU_EEEMD_LPI_IN_RX |
4710 TG3_CPMU_EEEMD_EEE_ENABLE;
4711
4712 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4713 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4714
4715 if (tg3_flag(tp, ENABLE_APE))
4716 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4717
4718 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4719
4720 tw32_f(TG3_CPMU_EEE_DBTMR1,
4721 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4722 (tp->eee.tx_lpi_timer & 0xffff));
4723
4724 tw32_f(TG3_CPMU_EEE_DBTMR2,
4725 TG3_CPMU_DBTMR2_APE_TX_2047US |
4726 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4727}
4728
953c96e0 4729static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4730{
953c96e0 4731 bool current_link_up;
f833c4c1 4732 u32 bmsr, val;
ef167e27 4733 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4734 u16 current_speed;
4735 u8 current_duplex;
4736 int i, err;
4737
3310e248 4738 tg3_clear_mac_status(tp);
1da177e4 4739
8ef21428
MC		 4740 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4741 tw32_f(MAC_MI_MODE,
4742 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4743 udelay(80);
4744 }
1da177e4 4745
b4bd2929 4746 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4747
4748 /* Some third-party PHYs need to be reset on link going
4749 * down.
4750 */
4153577a
JP		 4751 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4752 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4753 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4754 tp->link_up) {
1da177e4
LT		 4755 tg3_readphy(tp, MII_BMSR, &bmsr);
4756 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4757 !(bmsr & BMSR_LSTATUS))
953c96e0 4758 force_reset = true;
1da177e4
LT		 4759 }
4760 if (force_reset)
4761 tg3_phy_reset(tp);
4762
79eb6904 4763 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4764 tg3_readphy(tp, MII_BMSR, &bmsr);
4765 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4766 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4767 bmsr = 0;
4768
4769 if (!(bmsr & BMSR_LSTATUS)) {
4770 err = tg3_init_5401phy_dsp(tp);
4771 if (err)
4772 return err;
4773
4774 tg3_readphy(tp, MII_BMSR, &bmsr);
4775 for (i = 0; i < 1000; i++) {
4776 udelay(10);
4777 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4778 (bmsr & BMSR_LSTATUS)) {
4779 udelay(40);
4780 break;
4781 }
4782 }
4783
79eb6904
MC		 4784 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4785 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4786 !(bmsr & BMSR_LSTATUS) &&
4787 tp->link_config.active_speed == SPEED_1000) {
4788 err = tg3_phy_reset(tp);
4789 if (!err)
4790 err = tg3_init_5401phy_dsp(tp);
4791 if (err)
4792 return err;
4793 }
4794 }
4153577a
JP		 4795 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4796 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4797 /* 5701 {A0,B0} CRC bug workaround */
4798 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4799 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4800 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4801 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4802 }
4803
4804 /* Clear pending interrupts... */
f833c4c1
MC		 4805 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4806 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4807
f07e9af3 4808 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4809 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4810 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4811 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4812
4153577a
JP		 4813 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4814 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4815 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4816 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4817 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4818 else
4819 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4820 }
4821
953c96e0 4822 current_link_up = false;
e740522e
MC		 4823 current_speed = SPEED_UNKNOWN;
4824 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4825 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4826 tp->link_config.rmt_adv = 0;
1da177e4 4827
f07e9af3 4828 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4829 err = tg3_phy_auxctl_read(tp,
4830 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4831 &val);
4832 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4833 tg3_phy_auxctl_write(tp,
4834 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4835 val | (1 << 10));
1da177e4
LT		 4836 goto relink;
4837 }
4838 }
4839
4840 bmsr = 0;
4841 for (i = 0; i < 100; i++) {
4842 tg3_readphy(tp, MII_BMSR, &bmsr);
4843 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4844 (bmsr & BMSR_LSTATUS))
4845 break;
4846 udelay(40);
4847 }
4848
4849 if (bmsr & BMSR_LSTATUS) {
4850 u32 aux_stat, bmcr;
4851
4852 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4853 for (i = 0; i < 2000; i++) {
4854 udelay(10);
4855 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4856 aux_stat)
4857 break;
4858 }
4859
4860 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4861 &current_speed,
4862 &current_duplex);
4863
4864 bmcr = 0;
4865 for (i = 0; i < 200; i++) {
4866 tg3_readphy(tp, MII_BMCR, &bmcr);
4867 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4868 continue;
4869 if (bmcr && bmcr != 0x7fff)
4870 break;
4871 udelay(10);
4872 }
4873
ef167e27
MC		 4874 lcl_adv = 0;
4875 rmt_adv = 0;
1da177e4 4876
ef167e27
MC		 4877 tp->link_config.active_speed = current_speed;
4878 tp->link_config.active_duplex = current_duplex;
4879
4880 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4881 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4882
ef167e27 4883 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4884 eee_config_ok &&
e2bf73e7 4885 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4886 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4887 current_link_up = true;
ed1ff5c3
NS		 4888
4889 /* EEE settings changes take effect only after a phy
4890 * reset. If we have skipped a reset due to Link Flap
4891 * Avoidance being enabled, do it now.
4892 */
4893 if (!eee_config_ok &&
4894 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4895 !force_reset) {
4896 tg3_setup_eee(tp);
ed1ff5c3 4897 tg3_phy_reset(tp);
5b6c273a 4898 }
1da177e4
LT		 4899 } else {
4900 if (!(bmcr & BMCR_ANENABLE) &&
4901 tp->link_config.speed == current_speed &&
f0fcd7a9 4902 tp->link_config.duplex == current_duplex) {
953c96e0 4903 current_link_up = true;
1da177e4
LT		 4904 }
4905 }
4906
953c96e0 4907 if (current_link_up &&
e348c5e7
MC		 4908 tp->link_config.active_duplex == DUPLEX_FULL) {
4909 u32 reg, bit;
4910
4911 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4912 reg = MII_TG3_FET_GEN_STAT;
4913 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4914 } else {
4915 reg = MII_TG3_EXT_STAT;
4916 bit = MII_TG3_EXT_STAT_MDIX;
4917 }
4918
4919 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4920 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4921
ef167e27 4922 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4923 }
1da177e4
LT		 4924 }
4925
1da177e4 4926relink:
953c96e0 4927 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4928 tg3_phy_copper_begin(tp);
4929
7e6c63f0 4930 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4931 current_link_up = true;
7e6c63f0
HM		 4932 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4933 current_speed = SPEED_1000;
4934 current_duplex = DUPLEX_FULL;
4935 tp->link_config.active_speed = current_speed;
4936 tp->link_config.active_duplex = current_duplex;
4937 }
4938
f833c4c1 4939 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4940 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4941 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4942 current_link_up = true;
1da177e4
LT		 4943 }
4944
4945 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4946 if (current_link_up) {
1da177e4
LT		 4947 if (tp->link_config.active_speed == SPEED_100 ||
4948 tp->link_config.active_speed == SPEED_10)
4949 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4950 else
4951 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4952 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4953 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4954 else
1da177e4
LT		 4955 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4956
7e6c63f0
HM		 4957 /* In order for the 5750 core in BCM4785 chip to work properly
4958 * in RGMII mode, the Led Control Register must be set up.
4959 */
4960 if (tg3_flag(tp, RGMII_MODE)) {
4961 u32 led_ctrl = tr32(MAC_LED_CTRL);
4962 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
4963
4964 if (tp->link_config.active_speed == SPEED_10)
4965 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
4966 else if (tp->link_config.active_speed == SPEED_100)
4967 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4968 LED_CTRL_100MBPS_ON);
4969 else if (tp->link_config.active_speed == SPEED_1000)
4970 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4971 LED_CTRL_1000MBPS_ON);
4972
4973 tw32(MAC_LED_CTRL, led_ctrl);
4974 udelay(40);
4975 }
4976
1da177e4
LT		 4977 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4978 if (tp->link_config.active_duplex == DUPLEX_HALF)
4979 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4980
4153577a 4981 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 4982 if (current_link_up &&
e8f3f6ca 4983 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 4984 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 4985 else
4986 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 4987 }
4988
4989 /* ??? Without this setting Netgear GA302T PHY does not
4990 * ??? send/receive packets...
4991 */
79eb6904 4992 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 4993 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 4994 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4995 tw32_f(MAC_MI_MODE, tp->mi_mode);
4996 udelay(80);
4997 }
4998
4999 tw32_f(MAC_MODE, tp->mac_mode);
5000 udelay(40);
5001
52b02d04
MC		 5002 tg3_phy_eee_adjust(tp, current_link_up);
5003
63c3a66f 5004 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5005 /* Polled via timer. */
5006 tw32_f(MAC_EVENT, 0);
5007 } else {
5008 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5009 }
5010 udelay(40);
5011
4153577a 5012 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5013 current_link_up &&
1da177e4 5014 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5015 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5016 udelay(120);
5017 tw32_f(MAC_STATUS,
5018 (MAC_STATUS_SYNC_CHANGED |
5019 MAC_STATUS_CFG_CHANGED));
5020 udelay(40);
5021 tg3_write_mem(tp,
5022 NIC_SRAM_FIRMWARE_MBOX,
5023 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5024 }
5025
5e7dfd0f 5026 /* Prevent send BD corruption. */
63c3a66f 5027 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5028 if (tp->link_config.active_speed == SPEED_100 ||
5029 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5030 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5031 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5032 else
0f49bfbd
JL		 5033 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5034 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5035 }
5036
f4a46d1f 5037 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5038
5039 return 0;
5040}
5041
5042struct tg3_fiber_aneginfo {
5043 int state;
5044#define ANEG_STATE_UNKNOWN 0
5045#define ANEG_STATE_AN_ENABLE 1
5046#define ANEG_STATE_RESTART_INIT 2
5047#define ANEG_STATE_RESTART 3
5048#define ANEG_STATE_DISABLE_LINK_OK 4
5049#define ANEG_STATE_ABILITY_DETECT_INIT 5
5050#define ANEG_STATE_ABILITY_DETECT 6
5051#define ANEG_STATE_ACK_DETECT_INIT 7
5052#define ANEG_STATE_ACK_DETECT 8
5053#define ANEG_STATE_COMPLETE_ACK_INIT 9
5054#define ANEG_STATE_COMPLETE_ACK 10
5055#define ANEG_STATE_IDLE_DETECT_INIT 11
5056#define ANEG_STATE_IDLE_DETECT 12
5057#define ANEG_STATE_LINK_OK 13
5058#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5059#define ANEG_STATE_NEXT_PAGE_WAIT 15
5060
5061 u32 flags;
5062#define MR_AN_ENABLE 0x00000001
5063#define MR_RESTART_AN 0x00000002
5064#define MR_AN_COMPLETE 0x00000004
5065#define MR_PAGE_RX 0x00000008
5066#define MR_NP_LOADED 0x00000010
5067#define MR_TOGGLE_TX 0x00000020
5068#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5069#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5070#define MR_LP_ADV_SYM_PAUSE 0x00000100
5071#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5072#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5073#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5074#define MR_LP_ADV_NEXT_PAGE 0x00001000
5075#define MR_TOGGLE_RX 0x00002000
5076#define MR_NP_RX 0x00004000
5077
5078#define MR_LINK_OK 0x80000000
5079
5080 unsigned long link_time, cur_time;
5081
5082 u32 ability_match_cfg;
5083 int ability_match_count;
5084
5085 char ability_match, idle_match, ack_match;
5086
5087 u32 txconfig, rxconfig;
5088#define ANEG_CFG_NP 0x00000080
5089#define ANEG_CFG_ACK 0x00000040
5090#define ANEG_CFG_RF2 0x00000020
5091#define ANEG_CFG_RF1 0x00000010
5092#define ANEG_CFG_PS2 0x00000001
5093#define ANEG_CFG_PS1 0x00008000
5094#define ANEG_CFG_HD 0x00004000
5095#define ANEG_CFG_FD 0x00002000
5096#define ANEG_CFG_INVAL 0x00001f06
5097
5098};
5099#define ANEG_OK 0
5100#define ANEG_DONE 1
5101#define ANEG_TIMER_ENAB 2
5102#define ANEG_FAILED -1
5103
5104#define ANEG_STATE_SETTLE_TIME 10000
5105
5106static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5107 struct tg3_fiber_aneginfo *ap)
5108{
5be73b47 5109 u16 flowctrl;
1da177e4
LT		 5110 unsigned long delta;
5111 u32 rx_cfg_reg;
5112 int ret;
5113
5114 if (ap->state == ANEG_STATE_UNKNOWN) {
5115 ap->rxconfig = 0;
5116 ap->link_time = 0;
5117 ap->cur_time = 0;
5118 ap->ability_match_cfg = 0;
5119 ap->ability_match_count = 0;
5120 ap->ability_match = 0;
5121 ap->idle_match = 0;
5122 ap->ack_match = 0;
5123 }
5124 ap->cur_time++;
5125
5126 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5127 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5128
5129 if (rx_cfg_reg != ap->ability_match_cfg) {
5130 ap->ability_match_cfg = rx_cfg_reg;
5131 ap->ability_match = 0;
5132 ap->ability_match_count = 0;
5133 } else {
5134 if (++ap->ability_match_count > 1) {
5135 ap->ability_match = 1;
5136 ap->ability_match_cfg = rx_cfg_reg;
5137 }
5138 }
5139 if (rx_cfg_reg & ANEG_CFG_ACK)
5140 ap->ack_match = 1;
5141 else
5142 ap->ack_match = 0;
5143
5144 ap->idle_match = 0;
5145 } else {
5146 ap->idle_match = 1;
5147 ap->ability_match_cfg = 0;
5148 ap->ability_match_count = 0;
5149 ap->ability_match = 0;
5150 ap->ack_match = 0;
5151
5152 rx_cfg_reg = 0;
5153 }
5154
5155 ap->rxconfig = rx_cfg_reg;
5156 ret = ANEG_OK;
5157
33f401ae 5158 switch (ap->state) {
1da177e4
LT		 5159 case ANEG_STATE_UNKNOWN:
5160 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5161 ap->state = ANEG_STATE_AN_ENABLE;
5162
5163 /* fallthru */
5164 case ANEG_STATE_AN_ENABLE:
5165 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5166 if (ap->flags & MR_AN_ENABLE) {
5167 ap->link_time = 0;
5168 ap->cur_time = 0;
5169 ap->ability_match_cfg = 0;
5170 ap->ability_match_count = 0;
5171 ap->ability_match = 0;
5172 ap->idle_match = 0;
5173 ap->ack_match = 0;
5174
5175 ap->state = ANEG_STATE_RESTART_INIT;
5176 } else {
5177 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5178 }
5179 break;
5180
5181 case ANEG_STATE_RESTART_INIT:
5182 ap->link_time = ap->cur_time;
5183 ap->flags &= ~(MR_NP_LOADED);
5184 ap->txconfig = 0;
5185 tw32(MAC_TX_AUTO_NEG, 0);
5186 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5187 tw32_f(MAC_MODE, tp->mac_mode);
5188 udelay(40);
5189
5190 ret = ANEG_TIMER_ENAB;
5191 ap->state = ANEG_STATE_RESTART;
5192
5193 /* fallthru */
5194 case ANEG_STATE_RESTART:
5195 delta = ap->cur_time - ap->link_time;
859a5887 5196 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5197 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5198 else
1da177e4 5199 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5200 break;
5201
5202 case ANEG_STATE_DISABLE_LINK_OK:
5203 ret = ANEG_DONE;
5204 break;
5205
5206 case ANEG_STATE_ABILITY_DETECT_INIT:
5207 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5208 ap->txconfig = ANEG_CFG_FD;
5209 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5210 if (flowctrl & ADVERTISE_1000XPAUSE)
5211 ap->txconfig |= ANEG_CFG_PS1;
5212 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5213 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5214 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5215 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5216 tw32_f(MAC_MODE, tp->mac_mode);
5217 udelay(40);
5218
5219 ap->state = ANEG_STATE_ABILITY_DETECT;
5220 break;
5221
5222 case ANEG_STATE_ABILITY_DETECT:
859a5887 5223 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5224 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5225 break;
5226
5227 case ANEG_STATE_ACK_DETECT_INIT:
5228 ap->txconfig |= ANEG_CFG_ACK;
5229 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5230 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5231 tw32_f(MAC_MODE, tp->mac_mode);
5232 udelay(40);
5233
5234 ap->state = ANEG_STATE_ACK_DETECT;
5235
5236 /* fallthru */
5237 case ANEG_STATE_ACK_DETECT:
5238 if (ap->ack_match != 0) {
5239 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5240 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5241 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5242 } else {
5243 ap->state = ANEG_STATE_AN_ENABLE;
5244 }
5245 } else if (ap->ability_match != 0 &&
5246 ap->rxconfig == 0) {
5247 ap->state = ANEG_STATE_AN_ENABLE;
5248 }
5249 break;
5250
5251 case ANEG_STATE_COMPLETE_ACK_INIT:
5252 if (ap->rxconfig & ANEG_CFG_INVAL) {
5253 ret = ANEG_FAILED;
5254 break;
5255 }
5256 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5257 MR_LP_ADV_HALF_DUPLEX |
5258 MR_LP_ADV_SYM_PAUSE |
5259 MR_LP_ADV_ASYM_PAUSE |
5260 MR_LP_ADV_REMOTE_FAULT1 |
5261 MR_LP_ADV_REMOTE_FAULT2 |
5262 MR_LP_ADV_NEXT_PAGE |
5263 MR_TOGGLE_RX |
5264 MR_NP_RX);
5265 if (ap->rxconfig & ANEG_CFG_FD)
5266 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5267 if (ap->rxconfig & ANEG_CFG_HD)
5268 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5269 if (ap->rxconfig & ANEG_CFG_PS1)
5270 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5271 if (ap->rxconfig & ANEG_CFG_PS2)
5272 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5273 if (ap->rxconfig & ANEG_CFG_RF1)
5274 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5275 if (ap->rxconfig & ANEG_CFG_RF2)
5276 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5277 if (ap->rxconfig & ANEG_CFG_NP)
5278 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5279
5280 ap->link_time = ap->cur_time;
5281
5282 ap->flags ^= (MR_TOGGLE_TX);
5283 if (ap->rxconfig & 0x0008)
5284 ap->flags |= MR_TOGGLE_RX;
5285 if (ap->rxconfig & ANEG_CFG_NP)
5286 ap->flags |= MR_NP_RX;
5287 ap->flags |= MR_PAGE_RX;
5288
5289 ap->state = ANEG_STATE_COMPLETE_ACK;
5290 ret = ANEG_TIMER_ENAB;
5291 break;
5292
5293 case ANEG_STATE_COMPLETE_ACK:
5294 if (ap->ability_match != 0 &&
5295 ap->rxconfig == 0) {
5296 ap->state = ANEG_STATE_AN_ENABLE;
5297 break;
5298 }
5299 delta = ap->cur_time - ap->link_time;
5300 if (delta > ANEG_STATE_SETTLE_TIME) {
5301 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5302 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5303 } else {
5304 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5305 !(ap->flags & MR_NP_RX)) {
5306 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5307 } else {
5308 ret = ANEG_FAILED;
5309 }
5310 }
5311 }
5312 break;
5313
5314 case ANEG_STATE_IDLE_DETECT_INIT:
5315 ap->link_time = ap->cur_time;
5316 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5317 tw32_f(MAC_MODE, tp->mac_mode);
5318 udelay(40);
5319
5320 ap->state = ANEG_STATE_IDLE_DETECT;
5321 ret = ANEG_TIMER_ENAB;
5322 break;
5323
5324 case ANEG_STATE_IDLE_DETECT:
5325 if (ap->ability_match != 0 &&
5326 ap->rxconfig == 0) {
5327 ap->state = ANEG_STATE_AN_ENABLE;
5328 break;
5329 }
5330 delta = ap->cur_time - ap->link_time;
5331 if (delta > ANEG_STATE_SETTLE_TIME) {
5332 /* XXX another gem from the Broadcom driver :( */
5333 ap->state = ANEG_STATE_LINK_OK;
5334 }
5335 break;
5336
5337 case ANEG_STATE_LINK_OK:
5338 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5339 ret = ANEG_DONE;
5340 break;
5341
5342 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5343 /* ??? unimplemented */
5344 break;
5345
5346 case ANEG_STATE_NEXT_PAGE_WAIT:
5347 /* ??? unimplemented */
5348 break;
5349
5350 default:
5351 ret = ANEG_FAILED;
5352 break;
855e1111 5353 }
1da177e4
LT		 5354
5355 return ret;
5356}
5357
5be73b47 5358static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5359{
5360 int res = 0;
5361 struct tg3_fiber_aneginfo aninfo;
5362 int status = ANEG_FAILED;
5363 unsigned int tick;
5364 u32 tmp;
5365
5366 tw32_f(MAC_TX_AUTO_NEG, 0);
5367
5368 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5369 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5370 udelay(40);
5371
5372 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5373 udelay(40);
5374
5375 memset(&aninfo, 0, sizeof(aninfo));
5376 aninfo.flags |= MR_AN_ENABLE;
5377 aninfo.state = ANEG_STATE_UNKNOWN;
5378 aninfo.cur_time = 0;
5379 tick = 0;
5380 while (++tick < 195000) {
5381 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5382 if (status == ANEG_DONE || status == ANEG_FAILED)
5383 break;
5384
5385 udelay(1);
5386 }
5387
5388 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5389 tw32_f(MAC_MODE, tp->mac_mode);
5390 udelay(40);
5391
5be73b47
MC		 5392 *txflags = aninfo.txconfig;
5393 *rxflags = aninfo.flags;
1da177e4
LT		 5394
5395 if (status == ANEG_DONE &&
5396 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5397 MR_LP_ADV_FULL_DUPLEX)))
5398 res = 1;
5399
5400 return res;
5401}
5402
5403static void tg3_init_bcm8002(struct tg3 *tp)
5404{
5405 u32 mac_status = tr32(MAC_STATUS);
5406 int i;
5407
5408 /* Reset when initting first time or we have a link. */
63c3a66f 5409 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5410 !(mac_status & MAC_STATUS_PCS_SYNCED))
5411 return;
5412
5413 /* Set PLL lock range. */
5414 tg3_writephy(tp, 0x16, 0x8007);
5415
5416 /* SW reset */
5417 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5418
5419 /* Wait for reset to complete. */
5420 /* XXX schedule_timeout() ... */
5421 for (i = 0; i < 500; i++)
5422 udelay(10);
5423
5424 /* Config mode; select PMA/Ch 1 regs. */
5425 tg3_writephy(tp, 0x10, 0x8411);
5426
5427 /* Enable auto-lock and comdet, select txclk for tx. */
5428 tg3_writephy(tp, 0x11, 0x0a10);
5429
5430 tg3_writephy(tp, 0x18, 0x00a0);
5431 tg3_writephy(tp, 0x16, 0x41ff);
5432
5433 /* Assert and deassert POR. */
5434 tg3_writephy(tp, 0x13, 0x0400);
5435 udelay(40);
5436 tg3_writephy(tp, 0x13, 0x0000);
5437
5438 tg3_writephy(tp, 0x11, 0x0a50);
5439 udelay(40);
5440 tg3_writephy(tp, 0x11, 0x0a10);
5441
5442 /* Wait for signal to stabilize */
5443 /* XXX schedule_timeout() ... */
5444 for (i = 0; i < 15000; i++)
5445 udelay(10);
5446
5447 /* Deselect the channel register so we can read the PHYID
5448 * later.
5449 */
5450 tg3_writephy(tp, 0x10, 0x8011);
5451}
5452
953c96e0 5453static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5454{
82cd3d11 5455 u16 flowctrl;
953c96e0 5456 bool current_link_up;
1da177e4
LT		 5457 u32 sg_dig_ctrl, sg_dig_status;
5458 u32 serdes_cfg, expected_sg_dig_ctrl;
5459 int workaround, port_a;
1da177e4
LT		 5460
5461 serdes_cfg = 0;
5462 expected_sg_dig_ctrl = 0;
5463 workaround = 0;
5464 port_a = 1;
953c96e0 5465 current_link_up = false;
1da177e4 5466
4153577a
JP		 5467 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5468 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5469 workaround = 1;
5470 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5471 port_a = 0;
5472
5473 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5474 /* preserve bits 20-23 for voltage regulator */
5475 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5476 }
5477
5478 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5479
5480 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5481 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5482 if (workaround) {
5483 u32 val = serdes_cfg;
5484
5485 if (port_a)
5486 val |= 0xc010000;
5487 else
5488 val |= 0x4010000;
5489 tw32_f(MAC_SERDES_CFG, val);
5490 }
c98f6e3b
MC		 5491
5492 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5493 }
5494 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5495 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5496 current_link_up = true;
1da177e4
LT		 5497 }
5498 goto out;
5499 }
5500
5501 /* Want auto-negotiation. */
c98f6e3b 5502 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5503
82cd3d11
MC		 5504 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5505 if (flowctrl & ADVERTISE_1000XPAUSE)
5506 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5507 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5508 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5509
5510 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5511 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5512 tp->serdes_counter &&
5513 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5514 MAC_STATUS_RCVD_CFG)) ==
5515 MAC_STATUS_PCS_SYNCED)) {
5516 tp->serdes_counter--;
953c96e0 5517 current_link_up = true;
3d3ebe74
MC		 5518 goto out;
5519 }
5520restart_autoneg:
1da177e4
LT		 5521 if (workaround)
5522 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5523 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5524 udelay(5);
5525 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5526
3d3ebe74 5527 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5528 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5529 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5530 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5531 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5532 mac_status = tr32(MAC_STATUS);
5533
c98f6e3b 5534 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5535 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5536 u32 local_adv = 0, remote_adv = 0;
5537
5538 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5539 local_adv |= ADVERTISE_1000XPAUSE;
5540 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5541 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5542
c98f6e3b 5543 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5544 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5545 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5546 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5547
859edb26
MC		 5548 tp->link_config.rmt_adv =
5549 mii_adv_to_ethtool_adv_x(remote_adv);
5550
1da177e4 5551 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5552 current_link_up = true;
3d3ebe74 5553 tp->serdes_counter = 0;
f07e9af3 5554 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5555 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5556 if (tp->serdes_counter)
5557 tp->serdes_counter--;
1da177e4
LT		 5558 else {
5559 if (workaround) {
5560 u32 val = serdes_cfg;
5561
5562 if (port_a)
5563 val |= 0xc010000;
5564 else
5565 val |= 0x4010000;
5566
5567 tw32_f(MAC_SERDES_CFG, val);
5568 }
5569
c98f6e3b 5570 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5571 udelay(40);
5572
5573 /* Link parallel detection - link is up */
5574 /* only if we have PCS_SYNC and not */
5575 /* receiving config code words */
5576 mac_status = tr32(MAC_STATUS);
5577 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5578 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5579 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5580 current_link_up = true;
f07e9af3
MC		 5581 tp->phy_flags |=
5582 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5583 tp->serdes_counter =
5584 SERDES_PARALLEL_DET_TIMEOUT;
5585 } else
5586 goto restart_autoneg;
1da177e4
LT		 5587 }
5588 }
3d3ebe74
MC		 5589 } else {
5590 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5591 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5592 }
5593
5594out:
5595 return current_link_up;
5596}
5597
953c96e0 5598static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5599{
953c96e0 5600 bool current_link_up = false;
1da177e4 5601
5cf64b8a 5602 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5603 goto out;
1da177e4
LT		 5604
5605 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5606 u32 txflags, rxflags;
1da177e4 5607 int i;
6aa20a22 5608
5be73b47
MC		 5609 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5610 u32 local_adv = 0, remote_adv = 0;
1da177e4 5611
5be73b47
MC		 5612 if (txflags & ANEG_CFG_PS1)
5613 local_adv |= ADVERTISE_1000XPAUSE;
5614 if (txflags & ANEG_CFG_PS2)
5615 local_adv |= ADVERTISE_1000XPSE_ASYM;
5616
5617 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5618 remote_adv |= LPA_1000XPAUSE;
5619 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5620 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5621
859edb26
MC		 5622 tp->link_config.rmt_adv =
5623 mii_adv_to_ethtool_adv_x(remote_adv);
5624
1da177e4
LT		 5625 tg3_setup_flow_control(tp, local_adv, remote_adv);
5626
953c96e0 5627 current_link_up = true;
1da177e4
LT		 5628 }
5629 for (i = 0; i < 30; i++) {
5630 udelay(20);
5631 tw32_f(MAC_STATUS,
5632 (MAC_STATUS_SYNC_CHANGED |
5633 MAC_STATUS_CFG_CHANGED));
5634 udelay(40);
5635 if ((tr32(MAC_STATUS) &
5636 (MAC_STATUS_SYNC_CHANGED |
5637 MAC_STATUS_CFG_CHANGED)) == 0)
5638 break;
5639 }
5640
5641 mac_status = tr32(MAC_STATUS);
953c96e0 5642 if (!current_link_up &&
1da177e4
LT		 5643 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5644 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5645 current_link_up = true;
1da177e4 5646 } else {
5be73b47
MC		 5647 tg3_setup_flow_control(tp, 0, 0);
5648
1da177e4 5649 /* Forcing 1000FD link up. */
953c96e0 5650 current_link_up = true;
1da177e4
LT		 5651
5652 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5653 udelay(40);
e8f3f6ca
MC		 5654
5655 tw32_f(MAC_MODE, tp->mac_mode);
5656 udelay(40);
1da177e4
LT		 5657 }
5658
5659out:
5660 return current_link_up;
5661}
5662
953c96e0 5663static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5664{
5665 u32 orig_pause_cfg;
5666 u16 orig_active_speed;
5667 u8 orig_active_duplex;
5668 u32 mac_status;
953c96e0 5669 bool current_link_up;
1da177e4
LT		 5670 int i;
5671
8d018621 5672 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5673 orig_active_speed = tp->link_config.active_speed;
5674 orig_active_duplex = tp->link_config.active_duplex;
5675
63c3a66f 5676 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5677 tp->link_up &&
63c3a66f 5678 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5679 mac_status = tr32(MAC_STATUS);
5680 mac_status &= (MAC_STATUS_PCS_SYNCED |
5681 MAC_STATUS_SIGNAL_DET |
5682 MAC_STATUS_CFG_CHANGED |
5683 MAC_STATUS_RCVD_CFG);
5684 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5685 MAC_STATUS_SIGNAL_DET)) {
5686 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5687 MAC_STATUS_CFG_CHANGED));
5688 return 0;
5689 }
5690 }
5691
5692 tw32_f(MAC_TX_AUTO_NEG, 0);
5693
5694 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5695 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5696 tw32_f(MAC_MODE, tp->mac_mode);
5697 udelay(40);
5698
79eb6904 5699 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5700 tg3_init_bcm8002(tp);
5701
5702 /* Enable link change event even when serdes polling. */
5703 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5704 udelay(40);
5705
953c96e0 5706 current_link_up = false;
859edb26 5707 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5708 mac_status = tr32(MAC_STATUS);
5709
63c3a66f 5710 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5711 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5712 else
5713 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5714
898a56f8 5715 tp->napi[0].hw_status->status =
1da177e4 5716 (SD_STATUS_UPDATED |
898a56f8 5717 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5718
5719 for (i = 0; i < 100; i++) {
5720 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5721 MAC_STATUS_CFG_CHANGED));
5722 udelay(5);
5723 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5724 MAC_STATUS_CFG_CHANGED |
5725 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5726 break;
5727 }
5728
5729 mac_status = tr32(MAC_STATUS);
5730 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5731 current_link_up = false;
3d3ebe74
MC		 5732 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5733 tp->serdes_counter == 0) {
1da177e4
LT		 5734 tw32_f(MAC_MODE, (tp->mac_mode |
5735 MAC_MODE_SEND_CONFIGS));
5736 udelay(1);
5737 tw32_f(MAC_MODE, tp->mac_mode);
5738 }
5739 }
5740
953c96e0 5741 if (current_link_up) {
1da177e4
LT		 5742 tp->link_config.active_speed = SPEED_1000;
5743 tp->link_config.active_duplex = DUPLEX_FULL;
5744 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5745 LED_CTRL_LNKLED_OVERRIDE |
5746 LED_CTRL_1000MBPS_ON));
5747 } else {
e740522e
MC		 5748 tp->link_config.active_speed = SPEED_UNKNOWN;
5749 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5750 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5751 LED_CTRL_LNKLED_OVERRIDE |
5752 LED_CTRL_TRAFFIC_OVERRIDE));
5753 }
5754
f4a46d1f 5755 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5756 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5757 if (orig_pause_cfg != now_pause_cfg ||
5758 orig_active_speed != tp->link_config.active_speed ||
5759 orig_active_duplex != tp->link_config.active_duplex)
5760 tg3_link_report(tp);
5761 }
5762
5763 return 0;
5764}
5765
953c96e0 5766static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5767{
953c96e0 5768 int err = 0;
747e8f8b 5769 u32 bmsr, bmcr;
85730a63
MC		 5770 u16 current_speed = SPEED_UNKNOWN;
5771 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5772 bool current_link_up = false;
85730a63
MC		 5773 u32 local_adv, remote_adv, sgsr;
5774
5775 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5776 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5777 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5778 (sgsr & SERDES_TG3_SGMII_MODE)) {
5779
5780 if (force_reset)
5781 tg3_phy_reset(tp);
5782
5783 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5784
5785 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5786 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5787 } else {
953c96e0 5788 current_link_up = true;
85730a63
MC		 5789 if (sgsr & SERDES_TG3_SPEED_1000) {
5790 current_speed = SPEED_1000;
5791 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5792 } else if (sgsr & SERDES_TG3_SPEED_100) {
5793 current_speed = SPEED_100;
5794 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5795 } else {
5796 current_speed = SPEED_10;
5797 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5798 }
5799
5800 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5801 current_duplex = DUPLEX_FULL;
5802 else
5803 current_duplex = DUPLEX_HALF;
5804 }
5805
5806 tw32_f(MAC_MODE, tp->mac_mode);
5807 udelay(40);
5808
5809 tg3_clear_mac_status(tp);
5810
5811 goto fiber_setup_done;
5812 }
747e8f8b
MC		 5813
5814 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5815 tw32_f(MAC_MODE, tp->mac_mode);
5816 udelay(40);
5817
3310e248 5818 tg3_clear_mac_status(tp);
747e8f8b
MC		 5819
5820 if (force_reset)
5821 tg3_phy_reset(tp);
5822
859edb26 5823 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5824
5825 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5826 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5827 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5828 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5829 bmsr |= BMSR_LSTATUS;
5830 else
5831 bmsr &= ~BMSR_LSTATUS;
5832 }
747e8f8b
MC		 5833
5834 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5835
5836 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5837 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5838 /* do nothing, just check for link up at the end */
5839 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5840 u32 adv, newadv;
747e8f8b
MC		 5841
5842 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5843 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5844 ADVERTISE_1000XPAUSE |
5845 ADVERTISE_1000XPSE_ASYM |
5846 ADVERTISE_SLCT);
747e8f8b 5847
28011cf1 5848 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5849 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5850
28011cf1
MC		 5851 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5852 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5853 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5854 tg3_writephy(tp, MII_BMCR, bmcr);
5855
5856 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5857 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5858 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5859
5860 return err;
5861 }
5862 } else {
5863 u32 new_bmcr;
5864
5865 bmcr &= ~BMCR_SPEED1000;
5866 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5867
5868 if (tp->link_config.duplex == DUPLEX_FULL)
5869 new_bmcr |= BMCR_FULLDPLX;
5870
5871 if (new_bmcr != bmcr) {
5872 /* BMCR_SPEED1000 is a reserved bit that needs
5873 * to be set on write.
5874 */
5875 new_bmcr |= BMCR_SPEED1000;
5876
5877 /* Force a linkdown */
f4a46d1f 5878 if (tp->link_up) {
747e8f8b
MC		 5879 u32 adv;
5880
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5882 adv &= ~(ADVERTISE_1000XFULL |
5883 ADVERTISE_1000XHALF |
5884 ADVERTISE_SLCT);
5885 tg3_writephy(tp, MII_ADVERTISE, adv);
5886 tg3_writephy(tp, MII_BMCR, bmcr |
5887 BMCR_ANRESTART |
5888 BMCR_ANENABLE);
5889 udelay(10);
f4a46d1f 5890 tg3_carrier_off(tp);
747e8f8b
MC		 5891 }
5892 tg3_writephy(tp, MII_BMCR, new_bmcr);
5893 bmcr = new_bmcr;
5894 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5895 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5896 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5897 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5898 bmsr |= BMSR_LSTATUS;
5899 else
5900 bmsr &= ~BMSR_LSTATUS;
5901 }
f07e9af3 5902 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5903 }
5904 }
5905
5906 if (bmsr & BMSR_LSTATUS) {
5907 current_speed = SPEED_1000;
953c96e0 5908 current_link_up = true;
747e8f8b
MC		 5909 if (bmcr & BMCR_FULLDPLX)
5910 current_duplex = DUPLEX_FULL;
5911 else
5912 current_duplex = DUPLEX_HALF;
5913
ef167e27
MC		 5914 local_adv = 0;
5915 remote_adv = 0;
5916
747e8f8b 5917 if (bmcr & BMCR_ANENABLE) {
ef167e27 5918 u32 common;
747e8f8b
MC		 5919
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5921 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5922 common = local_adv & remote_adv;
5923 if (common & (ADVERTISE_1000XHALF |
5924 ADVERTISE_1000XFULL)) {
5925 if (common & ADVERTISE_1000XFULL)
5926 current_duplex = DUPLEX_FULL;
5927 else
5928 current_duplex = DUPLEX_HALF;
859edb26
MC		 5929
5930 tp->link_config.rmt_adv =
5931 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5932 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5933 /* Link is up via parallel detect */
859a5887 5934 } else {
953c96e0 5935 current_link_up = false;
859a5887 5936 }
747e8f8b
MC		 5937 }
5938 }
5939
85730a63 5940fiber_setup_done:
953c96e0 5941 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5942 tg3_setup_flow_control(tp, local_adv, remote_adv);
5943
747e8f8b
MC		 5944 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5945 if (tp->link_config.active_duplex == DUPLEX_HALF)
5946 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5947
5948 tw32_f(MAC_MODE, tp->mac_mode);
5949 udelay(40);
5950
5951 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5952
5953 tp->link_config.active_speed = current_speed;
5954 tp->link_config.active_duplex = current_duplex;
5955
f4a46d1f 5956 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 5957 return err;
5958}
5959
5960static void tg3_serdes_parallel_detect(struct tg3 *tp)
5961{
3d3ebe74 5962 if (tp->serdes_counter) {
747e8f8b 5963 /* Give autoneg time to complete. */
3d3ebe74 5964 tp->serdes_counter--;
747e8f8b
MC		 5965 return;
5966 }
c6cdf436 5967
f4a46d1f 5968 if (!tp->link_up &&
747e8f8b
MC		 5969 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5970 u32 bmcr;
5971
5972 tg3_readphy(tp, MII_BMCR, &bmcr);
5973 if (bmcr & BMCR_ANENABLE) {
5974 u32 phy1, phy2;
5975
5976 /* Select shadow register 0x1f */
f08aa1a8
MC		 5977 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5978 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 5979
5980 /* Select expansion interrupt status register */
f08aa1a8
MC		 5981 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5982 MII_TG3_DSP_EXP1_INT_STAT);
5983 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5984 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 5985
5986 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5987 /* We have signal detect and not receiving
5988 * config code words, link is up by parallel
5989 * detection.
5990 */
5991
5992 bmcr &= ~BMCR_ANENABLE;
5993 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5994 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 5995 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5996 }
5997 }
f4a46d1f 5998 } else if (tp->link_up &&
859a5887 5999 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6000 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6001 u32 phy2;
6002
6003 /* Select expansion interrupt status register */
f08aa1a8
MC		 6004 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6005 MII_TG3_DSP_EXP1_INT_STAT);
6006 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6007 if (phy2 & 0x20) {
6008 u32 bmcr;
6009
6010 /* Config code words received, turn on autoneg. */
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6013
f07e9af3 6014 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6015
6016 }
6017 }
6018}
6019
953c96e0 6020static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6021{
f2096f94 6022 u32 val;
1da177e4
LT		 6023 int err;
6024
f07e9af3 6025 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6026 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6027 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6028 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6029 else
1da177e4 6030 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6031
4153577a 6032 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6033 u32 scale;
aa6c91fe
MC		 6034
6035 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6036 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6037 scale = 65;
6038 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6039 scale = 6;
6040 else
6041 scale = 12;
6042
6043 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6044 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6045 tw32(GRC_MISC_CFG, val);
6046 }
6047
f2096f94
MC		 6048 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6049 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6050 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6051 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6052 val |= tr32(MAC_TX_LENGTHS) &
6053 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6054 TX_LENGTHS_CNT_DWN_VAL_MSK);
6055
1da177e4
LT		 6056 if (tp->link_config.active_speed == SPEED_1000 &&
6057 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6058 tw32(MAC_TX_LENGTHS, val |
6059 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6060 else
f2096f94
MC		 6061 tw32(MAC_TX_LENGTHS, val |
6062 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6063
63c3a66f 6064 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6065 if (tp->link_up) {
1da177e4 6066 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6067 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6068 } else {
6069 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6070 }
6071 }
6072
63c3a66f 6073 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6074 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6075 if (!tp->link_up)
8ed5d97e
MC		 6076 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6077 tp->pwrmgmt_thresh;
6078 else
6079 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6080 tw32(PCIE_PWR_MGMT_THRESH, val);
6081 }
6082
1da177e4
LT		 6083 return err;
6084}
6085
7d41e49a
MC		 6086/* tp->lock must be held */
6087static u64 tg3_refclk_read(struct tg3 *tp)
6088{
6089 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6090 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6091}
6092
be947307
MC		 6093/* tp->lock must be held */
6094static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6095{
6096 tw32(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_STOP);
6097 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6098 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6099 tw32_f(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_RESUME);
6100}
6101
7d41e49a
MC		 6102static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6103static inline void tg3_full_unlock(struct tg3 *tp);
6104static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6105{
6106 struct tg3 *tp = netdev_priv(dev);
6107
6108 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6109 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6110 SOF_TIMESTAMPING_SOFTWARE;
6111
6112 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6113 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6114 SOF_TIMESTAMPING_RX_HARDWARE |
6115 SOF_TIMESTAMPING_RAW_HARDWARE;
6116 }
7d41e49a
MC		 6117
6118 if (tp->ptp_clock)
6119 info->phc_index = ptp_clock_index(tp->ptp_clock);
6120 else
6121 info->phc_index = -1;
6122
6123 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6124
6125 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6126 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6127 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6128 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6129 return 0;
6130}
6131
6132static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6133{
6134 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6135 bool neg_adj = false;
6136 u32 correction = 0;
6137
6138 if (ppb < 0) {
6139 neg_adj = true;
6140 ppb = -ppb;
6141 }
6142
6143 /* Frequency adjustment is performed using hardware with a 24 bit
6144 * accumulator and a programmable correction value. On each clk, the
6145 * correction value gets added to the accumulator and when it
6146 * overflows, the time counter is incremented/decremented.
6147 *
6148 * So conversion from ppb to correction value is
6149 * ppb * (1 << 24) / 1000000000
6150 */
6151 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6152 TG3_EAV_REF_CLK_CORRECT_MASK;
6153
6154 tg3_full_lock(tp, 0);
6155
6156 if (correction)
6157 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6158 TG3_EAV_REF_CLK_CORRECT_EN |
6159 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6160 else
6161 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6162
6163 tg3_full_unlock(tp);
6164
6165 return 0;
6166}
6167
6168static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6169{
6170 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6171
6172 tg3_full_lock(tp, 0);
6173 tp->ptp_adjust += delta;
6174 tg3_full_unlock(tp);
6175
6176 return 0;
6177}
6178
6179static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6180{
6181 u64 ns;
6182 u32 remainder;
6183 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6184
6185 tg3_full_lock(tp, 0);
6186 ns = tg3_refclk_read(tp);
6187 ns += tp->ptp_adjust;
6188 tg3_full_unlock(tp);
6189
6190 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6191 ts->tv_nsec = remainder;
6192
6193 return 0;
6194}
6195
6196static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6197 const struct timespec *ts)
6198{
6199 u64 ns;
6200 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6201
6202 ns = timespec_to_ns(ts);
6203
6204 tg3_full_lock(tp, 0);
6205 tg3_refclk_write(tp, ns);
6206 tp->ptp_adjust = 0;
6207 tg3_full_unlock(tp);
6208
6209 return 0;
6210}
6211
6212static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6213 struct ptp_clock_request *rq, int on)
6214{
6215 return -EOPNOTSUPP;
6216}
6217
6218static const struct ptp_clock_info tg3_ptp_caps = {
6219 .owner = THIS_MODULE,
6220 .name = "tg3 clock",
6221 .max_adj = 250000000,
6222 .n_alarm = 0,
6223 .n_ext_ts = 0,
6224 .n_per_out = 0,
6225 .pps = 0,
6226 .adjfreq = tg3_ptp_adjfreq,
6227 .adjtime = tg3_ptp_adjtime,
6228 .gettime = tg3_ptp_gettime,
6229 .settime = tg3_ptp_settime,
6230 .enable = tg3_ptp_enable,
6231};
6232
fb4ce8ad
MC		 6233static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6234 struct skb_shared_hwtstamps *timestamp)
6235{
6236 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6237 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6238 tp->ptp_adjust);
6239}
6240
be947307
MC		 6241/* tp->lock must be held */
6242static void tg3_ptp_init(struct tg3 *tp)
6243{
6244 if (!tg3_flag(tp, PTP_CAPABLE))
6245 return;
6246
6247 /* Initialize the hardware clock to the system time. */
6248 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6249 tp->ptp_adjust = 0;
7d41e49a 6250 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6251}
6252
6253/* tp->lock must be held */
6254static void tg3_ptp_resume(struct tg3 *tp)
6255{
6256 if (!tg3_flag(tp, PTP_CAPABLE))
6257 return;
6258
6259 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6260 tp->ptp_adjust = 0;
6261}
6262
6263static void tg3_ptp_fini(struct tg3 *tp)
6264{
6265 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6266 return;
6267
7d41e49a 6268 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6269 tp->ptp_clock = NULL;
6270 tp->ptp_adjust = 0;
6271}
6272
66cfd1bd
MC		 6273static inline int tg3_irq_sync(struct tg3 *tp)
6274{
6275 return tp->irq_sync;
6276}
6277
97bd8e49
MC		 6278static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6279{
6280 int i;
6281
6282 dst = (u32 *)((u8 *)dst + off);
6283 for (i = 0; i < len; i += sizeof(u32))
6284 *dst++ = tr32(off + i);
6285}
6286
6287static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6288{
6289 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6290 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6291 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6292 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6293 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6294 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6295 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6296 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6297 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6298 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6299 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6300 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6301 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6302 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6303 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6304 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6305 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6306 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6307 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6308
63c3a66f 6309 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6310 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6311
6312 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6313 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6314 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6315 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6316 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6317 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6318 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6319 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6320
63c3a66f 6321 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6322 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6323 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6324 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6325 }
6326
6327 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6328 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6329 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6330 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6331 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6332
63c3a66f 6333 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6334 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6335}
6336
6337static void tg3_dump_state(struct tg3 *tp)
6338{
6339 int i;
6340 u32 *regs;
6341
6342 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6343 if (!regs)
97bd8e49 6344 return;
97bd8e49 6345
63c3a66f 6346 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6347 /* Read up to but not including private PCI registers */
6348 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6349 regs[i / sizeof(u32)] = tr32(i);
6350 } else
6351 tg3_dump_legacy_regs(tp, regs);
6352
6353 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6354 if (!regs[i + 0] && !regs[i + 1] &&
6355 !regs[i + 2] && !regs[i + 3])
6356 continue;
6357
6358 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6359 i * 4,
6360 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6361 }
6362
6363 kfree(regs);
6364
6365 for (i = 0; i < tp->irq_cnt; i++) {
6366 struct tg3_napi *tnapi = &tp->napi[i];
6367
6368 /* SW status block */
6369 netdev_err(tp->dev,
6370 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6371 i,
6372 tnapi->hw_status->status,
6373 tnapi->hw_status->status_tag,
6374 tnapi->hw_status->rx_jumbo_consumer,
6375 tnapi->hw_status->rx_consumer,
6376 tnapi->hw_status->rx_mini_consumer,
6377 tnapi->hw_status->idx[0].rx_producer,
6378 tnapi->hw_status->idx[0].tx_consumer);
6379
6380 netdev_err(tp->dev,
6381 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6382 i,
6383 tnapi->last_tag, tnapi->last_irq_tag,
6384 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6385 tnapi->rx_rcb_ptr,
6386 tnapi->prodring.rx_std_prod_idx,
6387 tnapi->prodring.rx_std_cons_idx,
6388 tnapi->prodring.rx_jmb_prod_idx,
6389 tnapi->prodring.rx_jmb_cons_idx);
6390 }
6391}
6392
df3e6548
MC		 6393/* This is called whenever we suspect that the system chipset is re-
6394 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6395 * is bogus tx completions. We try to recover by setting the
6396 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6397 * in the workqueue.
6398 */
6399static void tg3_tx_recover(struct tg3 *tp)
6400{
63c3a66f 6401 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6402 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6403
5129c3a3
MC		 6404 netdev_warn(tp->dev,
6405 "The system may be re-ordering memory-mapped I/O "
6406 "cycles to the network device, attempting to recover. "
6407 "Please report the problem to the driver maintainer "
6408 "and include system chipset information.\n");
df3e6548 6409
63c3a66f 6410 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6411}
6412
f3f3f27e 6413static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6414{
f65aac16
MC		 6415 /* Tell compiler to fetch tx indices from memory. */
6416 barrier();
f3f3f27e
MC		 6417 return tnapi->tx_pending -
6418 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6419}
6420
1da177e4
LT		 6421/* Tigon3 never reports partial packet sends. So we do not
6422 * need special logic to handle SKBs that have not had all
6423 * of their frags sent yet, like SunGEM does.
6424 */
17375d25 6425static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6426{
17375d25 6427 struct tg3 *tp = tnapi->tp;
898a56f8 6428 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6429 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6430 struct netdev_queue *txq;
6431 int index = tnapi - tp->napi;
298376d3 6432 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6433
63c3a66f 6434 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6435 index--;
6436
6437 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6438
6439 while (sw_idx != hw_idx) {
df8944cf 6440 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6441 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6442 int i, tx_bug = 0;
6443
6444 if (unlikely(skb == NULL)) {
6445 tg3_tx_recover(tp);
6446 return;
6447 }
1da177e4 6448
fb4ce8ad
MC		 6449 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6450 struct skb_shared_hwtstamps timestamp;
6451 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6452 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6453
6454 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6455
6456 skb_tstamp_tx(skb, &timestamp);
6457 }
6458
f4188d8a 6459 pci_unmap_single(tp->pdev,
4e5e4f0d 6460 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6461 skb_headlen(skb),
6462 PCI_DMA_TODEVICE);
1da177e4
LT		 6463
6464 ri->skb = NULL;
6465
e01ee14d
MC		 6466 while (ri->fragmented) {
6467 ri->fragmented = false;
6468 sw_idx = NEXT_TX(sw_idx);
6469 ri = &tnapi->tx_buffers[sw_idx];
6470 }
6471
1da177e4
LT		 6472 sw_idx = NEXT_TX(sw_idx);
6473
6474 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6475 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6476 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6477 tx_bug = 1;
f4188d8a
AD		 6478
6479 pci_unmap_page(tp->pdev,
4e5e4f0d 6480 dma_unmap_addr(ri, mapping),
9e903e08 6481 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6482 PCI_DMA_TODEVICE);
e01ee14d
MC		 6483
6484 while (ri->fragmented) {
6485 ri->fragmented = false;
6486 sw_idx = NEXT_TX(sw_idx);
6487 ri = &tnapi->tx_buffers[sw_idx];
6488 }
6489
1da177e4
LT		 6490 sw_idx = NEXT_TX(sw_idx);
6491 }
6492
298376d3
TH		 6493 pkts_compl++;
6494 bytes_compl += skb->len;
6495
f47c11ee 6496 dev_kfree_skb(skb);
df3e6548
MC		 6497
6498 if (unlikely(tx_bug)) {
6499 tg3_tx_recover(tp);
6500 return;
6501 }
1da177e4
LT		 6502 }
6503
5cb917bc 6504 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6505
f3f3f27e 6506 tnapi->tx_cons = sw_idx;
1da177e4 6507
1b2a7205
MC		 6508 /* Need to make the tx_cons update visible to tg3_start_xmit()
6509 * before checking for netif_queue_stopped(). Without the
6510 * memory barrier, there is a small possibility that tg3_start_xmit()
6511 * will miss it and cause the queue to be stopped forever.
6512 */
6513 smp_mb();
6514
fe5f5787 6515 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6516 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6517 __netif_tx_lock(txq, smp_processor_id());
6518 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6519 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6520 netif_tx_wake_queue(txq);
6521 __netif_tx_unlock(txq);
51b91468 6522 }
1da177e4
LT		 6523}
6524
8d4057a9
ED		 6525static void tg3_frag_free(bool is_frag, void *data)
6526{
6527 if (is_frag)
6528 put_page(virt_to_head_page(data));
6529 else
6530 kfree(data);
6531}
6532
9205fd9c 6533static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6534{
8d4057a9
ED		 6535 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6536 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6537
9205fd9c 6538 if (!ri->data)
2b2cdb65
MC		 6539 return;
6540
4e5e4f0d 6541 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6542 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6543 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6544 ri->data = NULL;
2b2cdb65
MC		 6545}
6546
8d4057a9 6547
1da177e4
LT		 6548/* Returns size of skb allocated or < 0 on error.
6549 *
6550 * We only need to fill in the address because the other members
6551 * of the RX descriptor are invariant, see tg3_init_rings.
6552 *
6553 * Note the purposeful assymetry of cpu vs. chip accesses. For
6554 * posting buffers we only dirty the first cache line of the RX
6555 * descriptor (containing the address). Whereas for the RX status
6556 * buffers the cpu only reads the last cacheline of the RX descriptor
6557 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6558 */
9205fd9c 6559static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6560 u32 opaque_key, u32 dest_idx_unmasked,
6561 unsigned int *frag_size)
1da177e4
LT		 6562{
6563 struct tg3_rx_buffer_desc *desc;
f94e290e 6564 struct ring_info *map;
9205fd9c 6565 u8 *data;
1da177e4 6566 dma_addr_t mapping;
9205fd9c 6567 int skb_size, data_size, dest_idx;
1da177e4 6568
1da177e4
LT		 6569 switch (opaque_key) {
6570 case RXD_OPAQUE_RING_STD:
2c49a44d 6571 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6572 desc = &tpr->rx_std[dest_idx];
6573 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6574 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6575 break;
6576
6577 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6578 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6579 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6580 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6581 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6582 break;
6583
6584 default:
6585 return -EINVAL;
855e1111 6586 }
1da177e4
LT		 6587
6588 /* Do not overwrite any of the map or rp information
6589 * until we are sure we can commit to a new buffer.
6590 *
6591 * Callers depend upon this behavior and assume that
6592 * we leave everything unchanged if we fail.
6593 */
9205fd9c
ED		 6594 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6595 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6596 if (skb_size <= PAGE_SIZE) {
6597 data = netdev_alloc_frag(skb_size);
6598 *frag_size = skb_size;
8d4057a9
ED		 6599 } else {
6600 data = kmalloc(skb_size, GFP_ATOMIC);
6601 *frag_size = 0;
6602 }
9205fd9c 6603 if (!data)
1da177e4
LT		 6604 return -ENOMEM;
6605
9205fd9c
ED		 6606 mapping = pci_map_single(tp->pdev,
6607 data + TG3_RX_OFFSET(tp),
6608 data_size,
1da177e4 6609 PCI_DMA_FROMDEVICE);
8d4057a9 6610 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6611 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6612 return -EIO;
6613 }
1da177e4 6614
9205fd9c 6615 map->data = data;
4e5e4f0d 6616 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6617
1da177e4
LT		 6618 desc->addr_hi = ((u64)mapping >> 32);
6619 desc->addr_lo = ((u64)mapping & 0xffffffff);
6620
9205fd9c 6621 return data_size;
1da177e4
LT		 6622}
6623
6624/* We only need to move over in the address because the other
6625 * members of the RX descriptor are invariant. See notes above
9205fd9c 6626 * tg3_alloc_rx_data for full details.
1da177e4 6627 */
a3896167
MC		 6628static void tg3_recycle_rx(struct tg3_napi *tnapi,
6629 struct tg3_rx_prodring_set *dpr,
6630 u32 opaque_key, int src_idx,
6631 u32 dest_idx_unmasked)
1da177e4 6632{
17375d25 6633 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6634 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6635 struct ring_info *src_map, *dest_map;
8fea32b9 6636 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6637 int dest_idx;
1da177e4
LT		 6638
6639 switch (opaque_key) {
6640 case RXD_OPAQUE_RING_STD:
2c49a44d 6641 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6642 dest_desc = &dpr->rx_std[dest_idx];
6643 dest_map = &dpr->rx_std_buffers[dest_idx];
6644 src_desc = &spr->rx_std[src_idx];
6645 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6646 break;
6647
6648 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6649 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6650 dest_desc = &dpr->rx_jmb[dest_idx].std;
6651 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6652 src_desc = &spr->rx_jmb[src_idx].std;
6653 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6654 break;
6655
6656 default:
6657 return;
855e1111 6658 }
1da177e4 6659
9205fd9c 6660 dest_map->data = src_map->data;
4e5e4f0d
FT		 6661 dma_unmap_addr_set(dest_map, mapping,
6662 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6663 dest_desc->addr_hi = src_desc->addr_hi;
6664 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6665
6666 /* Ensure that the update to the skb happens after the physical
6667 * addresses have been transferred to the new BD location.
6668 */
6669 smp_wmb();
6670
9205fd9c 6671 src_map->data = NULL;
1da177e4
LT		 6672}
6673
1da177e4
LT		 6674/* The RX ring scheme is composed of multiple rings which post fresh
6675 * buffers to the chip, and one special ring the chip uses to report
6676 * status back to the host.
6677 *
6678 * The special ring reports the status of received packets to the
6679 * host. The chip does not write into the original descriptor the
6680 * RX buffer was obtained from. The chip simply takes the original
6681 * descriptor as provided by the host, updates the status and length
6682 * field, then writes this into the next status ring entry.
6683 *
6684 * Each ring the host uses to post buffers to the chip is described
6685 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6686 * it is first placed into the on-chip ram. When the packet's length
6687 * is known, it walks down the TG3_BDINFO entries to select the ring.
6688 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6689 * which is within the range of the new packet's length is chosen.
6690 *
6691 * The "separate ring for rx status" scheme may sound queer, but it makes
6692 * sense from a cache coherency perspective. If only the host writes
6693 * to the buffer post rings, and only the chip writes to the rx status
6694 * rings, then cache lines never move beyond shared-modified state.
6695 * If both the host and chip were to write into the same ring, cache line
6696 * eviction could occur since both entities want it in an exclusive state.
6697 */
17375d25 6698static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6699{
17375d25 6700 struct tg3 *tp = tnapi->tp;
f92905de 6701 u32 work_mask, rx_std_posted = 0;
4361935a 6702 u32 std_prod_idx, jmb_prod_idx;
72334482 6703 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6704 u16 hw_idx;
1da177e4 6705 int received;
8fea32b9 6706 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6707
8d9d7cfc 6708 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6709 /*
6710 * We need to order the read of hw_idx and the read of
6711 * the opaque cookie.
6712 */
6713 rmb();
1da177e4
LT		 6714 work_mask = 0;
6715 received = 0;
4361935a
MC		 6716 std_prod_idx = tpr->rx_std_prod_idx;
6717 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6718 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6719 struct ring_info *ri;
72334482 6720 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6721 unsigned int len;
6722 struct sk_buff *skb;
6723 dma_addr_t dma_addr;
6724 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6725 u8 *data;
fb4ce8ad 6726 u64 tstamp = 0;
1da177e4
LT		 6727
6728 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6729 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6730 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6731 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6732 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6733 data = ri->data;
4361935a 6734 post_ptr = &std_prod_idx;
f92905de 6735 rx_std_posted++;
1da177e4 6736 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6737 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6738 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6739 data = ri->data;
4361935a 6740 post_ptr = &jmb_prod_idx;
21f581a5 6741 } else
1da177e4 6742 goto next_pkt_nopost;
1da177e4
LT		 6743
6744 work_mask |= opaque_key;
6745
6746 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6747 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6748 drop_it:
a3896167 6749 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6750 desc_idx, *post_ptr);
6751 drop_it_no_recycle:
6752 /* Other statistics kept track of by card. */
b0057c51 6753 tp->rx_dropped++;
1da177e4
LT		 6754 goto next_pkt;
6755 }
6756
9205fd9c 6757 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6758 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6759 ETH_FCS_LEN;
1da177e4 6760
fb4ce8ad
MC		 6761 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6762 RXD_FLAG_PTPSTAT_PTPV1 ||
6763 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6764 RXD_FLAG_PTPSTAT_PTPV2) {
6765 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6766 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6767 }
6768
d2757fc4 6769 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6770 int skb_size;
8d4057a9 6771 unsigned int frag_size;
1da177e4 6772
9205fd9c 6773 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6774 *post_ptr, &frag_size);
1da177e4
LT		 6775 if (skb_size < 0)
6776 goto drop_it;
6777
287be12e 6778 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6779 PCI_DMA_FROMDEVICE);
6780
8d4057a9 6781 skb = build_skb(data, frag_size);
9205fd9c 6782 if (!skb) {
8d4057a9 6783 tg3_frag_free(frag_size != 0, data);
9205fd9c
ED		 6784 goto drop_it_no_recycle;
6785 }
6786 skb_reserve(skb, TG3_RX_OFFSET(tp));
6787 /* Ensure that the update to the data happens
61e800cf
MC		 6788 * after the usage of the old DMA mapping.
6789 */
6790 smp_wmb();
6791
9205fd9c 6792 ri->data = NULL;
61e800cf 6793
1da177e4 6794 } else {
a3896167 6795 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6796 desc_idx, *post_ptr);
6797
9205fd9c
ED		 6798 skb = netdev_alloc_skb(tp->dev,
6799 len + TG3_RAW_IP_ALIGN);
6800 if (skb == NULL)
1da177e4
LT		 6801 goto drop_it_no_recycle;
6802
9205fd9c 6803 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6804 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6805 memcpy(skb->data,
6806 data + TG3_RX_OFFSET(tp),
6807 len);
1da177e4 6808 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6809 }
6810
9205fd9c 6811 skb_put(skb, len);
fb4ce8ad
MC		 6812 if (tstamp)
6813 tg3_hwclock_to_timestamp(tp, tstamp,
6814 skb_hwtstamps(skb));
6815
dc668910 6816 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6817 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6818 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6819 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6820 skb->ip_summed = CHECKSUM_UNNECESSARY;
6821 else
bc8acf2c 6822 skb_checksum_none_assert(skb);
1da177e4
LT		 6823
6824 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6825
6826 if (len > (tp->dev->mtu + ETH_HLEN) &&
6827 skb->protocol != htons(ETH_P_8021Q)) {
6828 dev_kfree_skb(skb);
b0057c51 6829 goto drop_it_no_recycle;
f7b493e0
MC		 6830 }
6831
9dc7a113 6832 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6833 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6834 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6835 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6836
bf933c80 6837 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6838
1da177e4
LT		 6839 received++;
6840 budget--;
6841
6842next_pkt:
6843 (*post_ptr)++;
f92905de
MC		 6844
6845 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6846 tpr->rx_std_prod_idx = std_prod_idx &
6847 tp->rx_std_ring_mask;
86cfe4ff
MC		 6848 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6849 tpr->rx_std_prod_idx);
f92905de
MC		 6850 work_mask &= ~RXD_OPAQUE_RING_STD;
6851 rx_std_posted = 0;
6852 }
1da177e4 6853next_pkt_nopost:
483ba50b 6854 sw_idx++;
7cb32cf2 6855 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6856
6857 /* Refresh hw_idx to see if there is new work */
6858 if (sw_idx == hw_idx) {
8d9d7cfc 6859 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6860 rmb();
6861 }
1da177e4
LT		 6862 }
6863
6864 /* ACK the status ring. */
72334482
MC		 6865 tnapi->rx_rcb_ptr = sw_idx;
6866 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6867
6868 /* Refill RX ring(s). */
63c3a66f 6869 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6870 /* Sync BD data before updating mailbox */
6871 wmb();
6872
b196c7e4 6873 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6874 tpr->rx_std_prod_idx = std_prod_idx &
6875 tp->rx_std_ring_mask;
b196c7e4
MC		 6876 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6877 tpr->rx_std_prod_idx);
6878 }
6879 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6880 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6881 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6882 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6883 tpr->rx_jmb_prod_idx);
6884 }
6885 mmiowb();
6886 } else if (work_mask) {
6887 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6888 * updated before the producer indices can be updated.
6889 */
6890 smp_wmb();
6891
2c49a44d
MC		 6892 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6893 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6894
7ae52890
MC		 6895 if (tnapi != &tp->napi[1]) {
6896 tp->rx_refill = true;
e4af1af9 6897 napi_schedule(&tp->napi[1].napi);
7ae52890 6898 }
1da177e4 6899 }
1da177e4
LT		 6900
6901 return received;
6902}
6903
35f2d7d0 6904static void tg3_poll_link(struct tg3 *tp)
1da177e4 6905{
1da177e4 6906 /* handle link change and other phy events */
63c3a66f 6907 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 6908 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6909
1da177e4
LT		 6910 if (sblk->status & SD_STATUS_LINK_CHG) {
6911 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 6912 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 6913 spin_lock(&tp->lock);
63c3a66f 6914 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 6915 tw32_f(MAC_STATUS,
6916 (MAC_STATUS_SYNC_CHANGED |
6917 MAC_STATUS_CFG_CHANGED |
6918 MAC_STATUS_MI_COMPLETION |
6919 MAC_STATUS_LNKSTATE_CHANGED));
6920 udelay(40);
6921 } else
953c96e0 6922 tg3_setup_phy(tp, false);
f47c11ee 6923 spin_unlock(&tp->lock);
1da177e4
LT		 6924 }
6925 }
35f2d7d0
MC		 6926}
6927
f89f38b8
MC		 6928static int tg3_rx_prodring_xfer(struct tg3 *tp,
6929 struct tg3_rx_prodring_set *dpr,
6930 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 6931{
6932 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 6933 int i, err = 0;
b196c7e4
MC		 6934
6935 while (1) {
6936 src_prod_idx = spr->rx_std_prod_idx;
6937
6938 /* Make sure updates to the rx_std_buffers[] entries and the
6939 * standard producer index are seen in the correct order.
6940 */
6941 smp_rmb();
6942
6943 if (spr->rx_std_cons_idx == src_prod_idx)
6944 break;
6945
6946 if (spr->rx_std_cons_idx < src_prod_idx)
6947 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
6948 else
2c49a44d
MC		 6949 cpycnt = tp->rx_std_ring_mask + 1 -
6950 spr->rx_std_cons_idx;
b196c7e4 6951
2c49a44d
MC		 6952 cpycnt = min(cpycnt,
6953 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 6954
6955 si = spr->rx_std_cons_idx;
6956 di = dpr->rx_std_prod_idx;
6957
e92967bf 6958 for (i = di; i < di + cpycnt; i++) {
9205fd9c 6959 if (dpr->rx_std_buffers[i].data) {
e92967bf 6960 cpycnt = i - di;
f89f38b8 6961 err = -ENOSPC;
e92967bf
MC		 6962 break;
6963 }
6964 }
6965
6966 if (!cpycnt)
6967 break;
6968
6969 /* Ensure that updates to the rx_std_buffers ring and the
6970 * shadowed hardware producer ring from tg3_recycle_skb() are
6971 * ordered correctly WRT the skb check above.
6972 */
6973 smp_rmb();
6974
b196c7e4
MC		 6975 memcpy(&dpr->rx_std_buffers[di],
6976 &spr->rx_std_buffers[si],
6977 cpycnt * sizeof(struct ring_info));
6978
6979 for (i = 0; i < cpycnt; i++, di++, si++) {
6980 struct tg3_rx_buffer_desc *sbd, *dbd;
6981 sbd = &spr->rx_std[si];
6982 dbd = &dpr->rx_std[di];
6983 dbd->addr_hi = sbd->addr_hi;
6984 dbd->addr_lo = sbd->addr_lo;
6985 }
6986
2c49a44d
MC		 6987 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
6988 tp->rx_std_ring_mask;
6989 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
6990 tp->rx_std_ring_mask;
b196c7e4
MC		 6991 }
6992
6993 while (1) {
6994 src_prod_idx = spr->rx_jmb_prod_idx;
6995
6996 /* Make sure updates to the rx_jmb_buffers[] entries and
6997 * the jumbo producer index are seen in the correct order.
6998 */
6999 smp_rmb();
7000
7001 if (spr->rx_jmb_cons_idx == src_prod_idx)
7002 break;
7003
7004 if (spr->rx_jmb_cons_idx < src_prod_idx)
7005 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7006 else
2c49a44d
MC		 7007 cpycnt = tp->rx_jmb_ring_mask + 1 -
7008 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7009
7010 cpycnt = min(cpycnt,
2c49a44d 7011 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7012
7013 si = spr->rx_jmb_cons_idx;
7014 di = dpr->rx_jmb_prod_idx;
7015
e92967bf 7016 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7017 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7018 cpycnt = i - di;
f89f38b8 7019 err = -ENOSPC;
e92967bf
MC		 7020 break;
7021 }
7022 }
7023
7024 if (!cpycnt)
7025 break;
7026
7027 /* Ensure that updates to the rx_jmb_buffers ring and the
7028 * shadowed hardware producer ring from tg3_recycle_skb() are
7029 * ordered correctly WRT the skb check above.
7030 */
7031 smp_rmb();
7032
b196c7e4
MC		 7033 memcpy(&dpr->rx_jmb_buffers[di],
7034 &spr->rx_jmb_buffers[si],
7035 cpycnt * sizeof(struct ring_info));
7036
7037 for (i = 0; i < cpycnt; i++, di++, si++) {
7038 struct tg3_rx_buffer_desc *sbd, *dbd;
7039 sbd = &spr->rx_jmb[si].std;
7040 dbd = &dpr->rx_jmb[di].std;
7041 dbd->addr_hi = sbd->addr_hi;
7042 dbd->addr_lo = sbd->addr_lo;
7043 }
7044
2c49a44d
MC		 7045 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7046 tp->rx_jmb_ring_mask;
7047 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7048 tp->rx_jmb_ring_mask;
b196c7e4 7049 }
f89f38b8
MC		 7050
7051 return err;
b196c7e4
MC		 7052}
7053
35f2d7d0
MC		 7054static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7055{
7056 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7057
7058 /* run TX completion thread */
f3f3f27e 7059 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7060 tg3_tx(tnapi);
63c3a66f 7061 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7062 return work_done;
1da177e4
LT		 7063 }
7064
f891ea16
MC		 7065 if (!tnapi->rx_rcb_prod_idx)
7066 return work_done;
7067
1da177e4
LT		 7068 /* run RX thread, within the bounds set by NAPI.
7069 * All RX "locking" is done by ensuring outside
bea3348e 7070 * code synchronizes with tg3->napi.poll()
1da177e4 7071 */
8d9d7cfc 7072 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7073 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7074
63c3a66f 7075 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7076 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7077 int i, err = 0;
e4af1af9
MC		 7078 u32 std_prod_idx = dpr->rx_std_prod_idx;
7079 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7080
7ae52890 7081 tp->rx_refill = false;
9102426a 7082 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7083 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7084 &tp->napi[i].prodring);
b196c7e4
MC		 7085
7086 wmb();
7087
e4af1af9
MC		 7088 if (std_prod_idx != dpr->rx_std_prod_idx)
7089 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7090 dpr->rx_std_prod_idx);
b196c7e4 7091
e4af1af9
MC		 7092 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7093 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7094 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7095
7096 mmiowb();
f89f38b8
MC		 7097
7098 if (err)
7099 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7100 }
7101
6f535763
DM		 7102 return work_done;
7103}
7104
db219973
MC		 7105static inline void tg3_reset_task_schedule(struct tg3 *tp)
7106{
7107 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7108 schedule_work(&tp->reset_task);
7109}
7110
7111static inline void tg3_reset_task_cancel(struct tg3 *tp)
7112{
7113 cancel_work_sync(&tp->reset_task);
7114 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7115 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7116}
7117
35f2d7d0
MC		 7118static int tg3_poll_msix(struct napi_struct *napi, int budget)
7119{
7120 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7121 struct tg3 *tp = tnapi->tp;
7122 int work_done = 0;
7123 struct tg3_hw_status *sblk = tnapi->hw_status;
7124
7125 while (1) {
7126 work_done = tg3_poll_work(tnapi, work_done, budget);
7127
63c3a66f 7128 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7129 goto tx_recovery;
7130
7131 if (unlikely(work_done >= budget))
7132 break;
7133
c6cdf436 7134 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7135 * to tell the hw how much work has been processed,
7136 * so we must read it before checking for more work.
7137 */
7138 tnapi->last_tag = sblk->status_tag;
7139 tnapi->last_irq_tag = tnapi->last_tag;
7140 rmb();
7141
7142 /* check for RX/TX work to do */
6d40db7b
MC		 7143 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7144 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7145
7146 /* This test here is not race free, but will reduce
7147 * the number of interrupts by looping again.
7148 */
7149 if (tnapi == &tp->napi[1] && tp->rx_refill)
7150 continue;
7151
35f2d7d0
MC		 7152 napi_complete(napi);
7153 /* Reenable interrupts. */
7154 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7155
7156 /* This test here is synchronized by napi_schedule()
7157 * and napi_complete() to close the race condition.
7158 */
7159 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7160 tw32(HOSTCC_MODE, tp->coalesce_mode |
7161 HOSTCC_MODE_ENABLE |
7162 tnapi->coal_now);
7163 }
35f2d7d0
MC		 7164 mmiowb();
7165 break;
7166 }
7167 }
7168
7169 return work_done;
7170
7171tx_recovery:
7172 /* work_done is guaranteed to be less than budget. */
7173 napi_complete(napi);
db219973 7174 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7175 return work_done;
7176}
7177
e64de4e6
MC		 7178static void tg3_process_error(struct tg3 *tp)
7179{
7180 u32 val;
7181 bool real_error = false;
7182
63c3a66f 7183 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7184 return;
7185
7186 /* Check Flow Attention register */
7187 val = tr32(HOSTCC_FLOW_ATTN);
7188 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7189 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7190 real_error = true;
7191 }
7192
7193 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7194 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7195 real_error = true;
7196 }
7197
7198 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7199 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7200 real_error = true;
7201 }
7202
7203 if (!real_error)
7204 return;
7205
7206 tg3_dump_state(tp);
7207
63c3a66f 7208 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7209 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7210}
7211
6f535763
DM		 7212static int tg3_poll(struct napi_struct *napi, int budget)
7213{
8ef0442f
MC		 7214 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7215 struct tg3 *tp = tnapi->tp;
6f535763 7216 int work_done = 0;
898a56f8 7217 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7218
7219 while (1) {
e64de4e6
MC		 7220 if (sblk->status & SD_STATUS_ERROR)
7221 tg3_process_error(tp);
7222
35f2d7d0
MC		 7223 tg3_poll_link(tp);
7224
17375d25 7225 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7226
63c3a66f 7227 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7228 goto tx_recovery;
7229
7230 if (unlikely(work_done >= budget))
7231 break;
7232
63c3a66f 7233 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7234 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7235 * to tell the hw how much work has been processed,
7236 * so we must read it before checking for more work.
7237 */
898a56f8
MC		 7238 tnapi->last_tag = sblk->status_tag;
7239 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7240 rmb();
7241 } else
7242 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7243
17375d25 7244 if (likely(!tg3_has_work(tnapi))) {
288379f0 7245 napi_complete(napi);
17375d25 7246 tg3_int_reenable(tnapi);
6f535763
DM		 7247 break;
7248 }
1da177e4
LT		 7249 }
7250
bea3348e 7251 return work_done;
6f535763
DM		 7252
7253tx_recovery:
4fd7ab59 7254 /* work_done is guaranteed to be less than budget. */
288379f0 7255 napi_complete(napi);
db219973 7256 tg3_reset_task_schedule(tp);
4fd7ab59 7257 return work_done;
1da177e4
LT		 7258}
7259
66cfd1bd
MC		 7260static void tg3_napi_disable(struct tg3 *tp)
7261{
7262 int i;
7263
7264 for (i = tp->irq_cnt - 1; i >= 0; i--)
7265 napi_disable(&tp->napi[i].napi);
7266}
7267
7268static void tg3_napi_enable(struct tg3 *tp)
7269{
7270 int i;
7271
7272 for (i = 0; i < tp->irq_cnt; i++)
7273 napi_enable(&tp->napi[i].napi);
7274}
7275
7276static void tg3_napi_init(struct tg3 *tp)
7277{
7278 int i;
7279
7280 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7281 for (i = 1; i < tp->irq_cnt; i++)
7282 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7283}
7284
7285static void tg3_napi_fini(struct tg3 *tp)
7286{
7287 int i;
7288
7289 for (i = 0; i < tp->irq_cnt; i++)
7290 netif_napi_del(&tp->napi[i].napi);
7291}
7292
7293static inline void tg3_netif_stop(struct tg3 *tp)
7294{
7295 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7296 tg3_napi_disable(tp);
f4a46d1f 7297 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7298 netif_tx_disable(tp->dev);
7299}
7300
35763066 7301/* tp->lock must be held */
66cfd1bd
MC		 7302static inline void tg3_netif_start(struct tg3 *tp)
7303{
be947307
MC		 7304 tg3_ptp_resume(tp);
7305
66cfd1bd
MC		 7306 /* NOTE: unconditional netif_tx_wake_all_queues is only
7307 * appropriate so long as all callers are assured to
7308 * have free tx slots (such as after tg3_init_hw)
7309 */
7310 netif_tx_wake_all_queues(tp->dev);
7311
f4a46d1f
NNS		 7312 if (tp->link_up)
7313 netif_carrier_on(tp->dev);
7314
66cfd1bd
MC		 7315 tg3_napi_enable(tp);
7316 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7317 tg3_enable_ints(tp);
7318}
7319
f47c11ee
DM		 7320static void tg3_irq_quiesce(struct tg3 *tp)
7321{
4f125f42
MC		 7322 int i;
7323
f47c11ee
DM		 7324 BUG_ON(tp->irq_sync);
7325
7326 tp->irq_sync = 1;
7327 smp_mb();
7328
4f125f42
MC		 7329 for (i = 0; i < tp->irq_cnt; i++)
7330 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7331}
7332
f47c11ee
DM		 7333/* Fully shutdown all tg3 driver activity elsewhere in the system.
7334 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7335 * with as well. Most of the time, this is not necessary except when
7336 * shutting down the device.
7337 */
7338static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7339{
46966545 7340 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7341 if (irq_sync)
7342 tg3_irq_quiesce(tp);
f47c11ee
DM		 7343}
7344
7345static inline void tg3_full_unlock(struct tg3 *tp)
7346{
f47c11ee
DM		 7347 spin_unlock_bh(&tp->lock);
7348}
7349
fcfa0a32
MC		 7350/* One-shot MSI handler - Chip automatically disables interrupt
7351 * after sending MSI so driver doesn't have to do it.
7352 */
7d12e780 7353static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7354{
09943a18
MC		 7355 struct tg3_napi *tnapi = dev_id;
7356 struct tg3 *tp = tnapi->tp;
fcfa0a32 7357
898a56f8 7358 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7359 if (tnapi->rx_rcb)
7360 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7361
7362 if (likely(!tg3_irq_sync(tp)))
09943a18 7363 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7364
7365 return IRQ_HANDLED;
7366}
7367
88b06bc2
MC		 7368/* MSI ISR - No need to check for interrupt sharing and no need to
7369 * flush status block and interrupt mailbox. PCI ordering rules
7370 * guarantee that MSI will arrive after the status block.
7371 */
7d12e780 7372static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7373{
09943a18
MC		 7374 struct tg3_napi *tnapi = dev_id;
7375 struct tg3 *tp = tnapi->tp;
88b06bc2 7376
898a56f8 7377 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7378 if (tnapi->rx_rcb)
7379 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7380 /*
fac9b83e 7381 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7382 * chip-internal interrupt pending events.
fac9b83e 7383 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7384 * NIC to stop sending us irqs, engaging "in-intr-handler"
7385 * event coalescing.
7386 */
5b39de91 7387 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7388 if (likely(!tg3_irq_sync(tp)))
09943a18 7389 napi_schedule(&tnapi->napi);
61487480 7390
88b06bc2
MC		 7391 return IRQ_RETVAL(1);
7392}
7393
7d12e780 7394static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7395{
09943a18
MC		 7396 struct tg3_napi *tnapi = dev_id;
7397 struct tg3 *tp = tnapi->tp;
898a56f8 7398 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7399 unsigned int handled = 1;
7400
1da177e4
LT		 7401 /* In INTx mode, it is possible for the interrupt to arrive at
7402 * the CPU before the status block posted prior to the interrupt.
7403 * Reading the PCI State register will confirm whether the
7404 * interrupt is ours and will flush the status block.
7405 */
d18edcb2 7406 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7407 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7408 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7409 handled = 0;
f47c11ee 7410 goto out;
fac9b83e 7411 }
d18edcb2
MC		 7412 }
7413
7414 /*
7415 * Writing any value to intr-mbox-0 clears PCI INTA# and
7416 * chip-internal interrupt pending events.
7417 * Writing non-zero to intr-mbox-0 additional tells the
7418 * NIC to stop sending us irqs, engaging "in-intr-handler"
7419 * event coalescing.
c04cb347
MC		 7420 *
7421 * Flush the mailbox to de-assert the IRQ immediately to prevent
7422 * spurious interrupts. The flush impacts performance but
7423 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7424 */
c04cb347 7425 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7426 if (tg3_irq_sync(tp))
7427 goto out;
7428 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7429 if (likely(tg3_has_work(tnapi))) {
72334482 7430 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7431 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7432 } else {
7433 /* No work, shared interrupt perhaps? re-enable
7434 * interrupts, and flush that PCI write
7435 */
7436 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7437 0x00000000);
fac9b83e 7438 }
f47c11ee 7439out:
fac9b83e
DM		 7440 return IRQ_RETVAL(handled);
7441}
7442
7d12e780 7443static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7444{
09943a18
MC		 7445 struct tg3_napi *tnapi = dev_id;
7446 struct tg3 *tp = tnapi->tp;
898a56f8 7447 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7448 unsigned int handled = 1;
7449
fac9b83e
DM		 7450 /* In INTx mode, it is possible for the interrupt to arrive at
7451 * the CPU before the status block posted prior to the interrupt.
7452 * Reading the PCI State register will confirm whether the
7453 * interrupt is ours and will flush the status block.
7454 */
898a56f8 7455 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7456 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7457 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7458 handled = 0;
f47c11ee 7459 goto out;
1da177e4 7460 }
d18edcb2
MC		 7461 }
7462
7463 /*
7464 * writing any value to intr-mbox-0 clears PCI INTA# and
7465 * chip-internal interrupt pending events.
7466 * writing non-zero to intr-mbox-0 additional tells the
7467 * NIC to stop sending us irqs, engaging "in-intr-handler"
7468 * event coalescing.
c04cb347
MC		 7469 *
7470 * Flush the mailbox to de-assert the IRQ immediately to prevent
7471 * spurious interrupts. The flush impacts performance but
7472 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7473 */
c04cb347 7474 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7475
7476 /*
7477 * In a shared interrupt configuration, sometimes other devices'
7478 * interrupts will scream. We record the current status tag here
7479 * so that the above check can report that the screaming interrupts
7480 * are unhandled. Eventually they will be silenced.
7481 */
898a56f8 7482 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7483
d18edcb2
MC		 7484 if (tg3_irq_sync(tp))
7485 goto out;
624f8e50 7486
72334482 7487 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7488
09943a18 7489 napi_schedule(&tnapi->napi);
624f8e50 7490
f47c11ee 7491out:
1da177e4
LT		 7492 return IRQ_RETVAL(handled);
7493}
7494
7938109f 7495/* ISR for interrupt test */
7d12e780 7496static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7497{
09943a18
MC		 7498 struct tg3_napi *tnapi = dev_id;
7499 struct tg3 *tp = tnapi->tp;
898a56f8 7500 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7501
f9804ddb
MC		 7502 if ((sblk->status & SD_STATUS_UPDATED) ||
7503 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7504 tg3_disable_ints(tp);
7938109f
MC		 7505 return IRQ_RETVAL(1);
7506 }
7507 return IRQ_RETVAL(0);
7508}
7509
1da177e4
LT		 7510#ifdef CONFIG_NET_POLL_CONTROLLER
7511static void tg3_poll_controller(struct net_device *dev)
7512{
4f125f42 7513 int i;
88b06bc2
MC		 7514 struct tg3 *tp = netdev_priv(dev);
7515
9c13cb8b
NNS		 7516 if (tg3_irq_sync(tp))
7517 return;
7518
4f125f42 7519 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7520 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7521}
7522#endif
7523
1da177e4
LT		 7524static void tg3_tx_timeout(struct net_device *dev)
7525{
7526 struct tg3 *tp = netdev_priv(dev);
7527
b0408751 7528 if (netif_msg_tx_err(tp)) {
05dbe005 7529 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7530 tg3_dump_state(tp);
b0408751 7531 }
1da177e4 7532
db219973 7533 tg3_reset_task_schedule(tp);
1da177e4
LT		 7534}
7535
c58ec932
MC		 7536/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7537static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7538{
7539 u32 base = (u32) mapping & 0xffffffff;
7540
807540ba 7541 return (base > 0xffffdcc0) && (base + len + 8 < base);
c58ec932
MC		 7542}
7543
0f0d1510
MC		 7544/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7545 * of any 4GB boundaries: 4G, 8G, etc
7546 */
7547static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7548 u32 len, u32 mss)
7549{
7550 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7551 u32 base = (u32) mapping & 0xffffffff;
7552
7553 return ((base + len + (mss & 0x3fff)) < base);
7554 }
7555 return 0;
7556}
7557
72f2afb8
MC		 7558/* Test for DMA addresses > 40-bit */
7559static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7560 int len)
7561{
7562#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7563 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7564 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7565 return 0;
7566#else
7567 return 0;
7568#endif
7569}
7570
d1a3b737 7571static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7572 dma_addr_t mapping, u32 len, u32 flags,
7573 u32 mss, u32 vlan)
2ffcc981 7574{
92cd3a17
MC		 7575 txbd->addr_hi = ((u64) mapping >> 32);
7576 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7577 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7578 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7579}
1da177e4 7580
84b67b27 7581static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7582 dma_addr_t map, u32 len, u32 flags,
7583 u32 mss, u32 vlan)
7584{
7585 struct tg3 *tp = tnapi->tp;
7586 bool hwbug = false;
7587
7588 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7589 hwbug = true;
d1a3b737
MC		 7590
7591 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7592 hwbug = true;
d1a3b737 7593
0f0d1510
MC		 7594 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7595 hwbug = true;
7596
d1a3b737 7597 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7598 hwbug = true;
d1a3b737 7599
a4cb428d 7600 if (tp->dma_limit) {
b9e45482 7601 u32 prvidx = *entry;
e31aa987 7602 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7603 while (len > tp->dma_limit && *budget) {
7604 u32 frag_len = tp->dma_limit;
7605 len -= tp->dma_limit;
e31aa987 7606
b9e45482
MC		 7607 /* Avoid the 8byte DMA problem */
7608 if (len <= 8) {
a4cb428d
MC		 7609 len += tp->dma_limit / 2;
7610 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7611 }
7612
b9e45482
MC		 7613 tnapi->tx_buffers[*entry].fragmented = true;
7614
7615 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7616 frag_len, tmp_flag, mss, vlan);
7617 *budget -= 1;
7618 prvidx = *entry;
7619 *entry = NEXT_TX(*entry);
7620
e31aa987
MC		 7621 map += frag_len;
7622 }
7623
7624 if (len) {
7625 if (*budget) {
7626 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7627 len, flags, mss, vlan);
b9e45482 7628 *budget -= 1;
e31aa987
MC		 7629 *entry = NEXT_TX(*entry);
7630 } else {
3db1cd5c 7631 hwbug = true;
b9e45482 7632 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7633 }
7634 }
7635 } else {
84b67b27
MC		 7636 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7637 len, flags, mss, vlan);
e31aa987
MC		 7638 *entry = NEXT_TX(*entry);
7639 }
d1a3b737
MC		 7640
7641 return hwbug;
7642}
7643
0d681b27 7644static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7645{
7646 int i;
0d681b27 7647 struct sk_buff *skb;
df8944cf 7648 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7649
0d681b27
MC		 7650 skb = txb->skb;
7651 txb->skb = NULL;
7652
432aa7ed
MC		 7653 pci_unmap_single(tnapi->tp->pdev,
7654 dma_unmap_addr(txb, mapping),
7655 skb_headlen(skb),
7656 PCI_DMA_TODEVICE);
e01ee14d
MC		 7657
7658 while (txb->fragmented) {
7659 txb->fragmented = false;
7660 entry = NEXT_TX(entry);
7661 txb = &tnapi->tx_buffers[entry];
7662 }
7663
ba1142e4 7664 for (i = 0; i <= last; i++) {
9e903e08 7665 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7666
7667 entry = NEXT_TX(entry);
7668 txb = &tnapi->tx_buffers[entry];
7669
7670 pci_unmap_page(tnapi->tp->pdev,
7671 dma_unmap_addr(txb, mapping),
9e903e08 7672 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7673
7674 while (txb->fragmented) {
7675 txb->fragmented = false;
7676 entry = NEXT_TX(entry);
7677 txb = &tnapi->tx_buffers[entry];
7678 }
432aa7ed
MC		 7679 }
7680}
7681
72f2afb8 7682/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7683static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7684 struct sk_buff **pskb,
84b67b27 7685 u32 *entry, u32 *budget,
92cd3a17 7686 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7687{
24f4efd4 7688 struct tg3 *tp = tnapi->tp;
f7ff1987 7689 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7690 dma_addr_t new_addr = 0;
432aa7ed 7691 int ret = 0;
1da177e4 7692
4153577a 7693 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7694 new_skb = skb_copy(skb, GFP_ATOMIC);
7695 else {
7696 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7697
7698 new_skb = skb_copy_expand(skb,
7699 skb_headroom(skb) + more_headroom,
7700 skb_tailroom(skb), GFP_ATOMIC);
7701 }
7702
1da177e4 7703 if (!new_skb) {
c58ec932
MC		 7704 ret = -1;
7705 } else {
7706 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7707 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7708 PCI_DMA_TODEVICE);
7709 /* Make sure the mapping succeeded */
7710 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
f4188d8a 7711 dev_kfree_skb(new_skb);
c58ec932 7712 ret = -1;
c58ec932 7713 } else {
b9e45482
MC		 7714 u32 save_entry = *entry;
7715
92cd3a17
MC		 7716 base_flags |= TXD_FLAG_END;
7717
84b67b27
MC		 7718 tnapi->tx_buffers[*entry].skb = new_skb;
7719 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7720 mapping, new_addr);
7721
84b67b27 7722 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7723 new_skb->len, base_flags,
7724 mss, vlan)) {
ba1142e4 7725 tg3_tx_skb_unmap(tnapi, save_entry, -1);
d1a3b737
MC		 7726 dev_kfree_skb(new_skb);
7727 ret = -1;
7728 }
f4188d8a 7729 }
1da177e4
LT		 7730 }
7731
7732 dev_kfree_skb(skb);
f7ff1987 7733 *pskb = new_skb;
c58ec932 7734 return ret;
1da177e4
LT		 7735}
7736
2ffcc981 7737static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83
MC		 7738
7739/* Use GSO to workaround a rare TSO bug that may be triggered when the
7740 * TSO header is greater than 80 bytes.
7741 */
7742static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7743{
7744 struct sk_buff *segs, *nskb;
f3f3f27e 7745 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7746
7747 /* Estimate the number of fragments in the worst case */
f3f3f27e 7748 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 7749 netif_stop_queue(tp->dev);
f65aac16
MC		 7750
7751 /* netif_tx_stop_queue() must be done before checking
7752 * checking tx index in tg3_tx_avail() below, because in
7753 * tg3_tx(), we update tx index before checking for
7754 * netif_tx_queue_stopped().
7755 */
7756 smp_mb();
f3f3f27e 7757 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 7758 return NETDEV_TX_BUSY;
7759
7760 netif_wake_queue(tp->dev);
52c0fd83
MC		 7761 }
7762
7763 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 7764 if (IS_ERR(segs))
52c0fd83
MC		 7765 goto tg3_tso_bug_end;
7766
7767 do {
7768 nskb = segs;
7769 segs = segs->next;
7770 nskb->next = NULL;
2ffcc981 7771 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7772 } while (segs);
7773
7774tg3_tso_bug_end:
7775 dev_kfree_skb(skb);
7776
7777 return NETDEV_TX_OK;
7778}
52c0fd83 7779
5a6f3074 7780/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
63c3a66f 7781 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5a6f3074 7782 */
2ffcc981 7783static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7784{
7785 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7786 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7787 u32 budget;
432aa7ed 7788 int i = -1, would_hit_hwbug;
90079ce8 7789 dma_addr_t mapping;
24f4efd4
MC		 7790 struct tg3_napi *tnapi;
7791 struct netdev_queue *txq;
432aa7ed 7792 unsigned int last;
f4188d8a 7793
24f4efd4
MC		 7794 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7795 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7796 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7797 tnapi++;
1da177e4 7798
84b67b27
MC		 7799 budget = tg3_tx_avail(tnapi);
7800
00b70504 7801 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7802 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7803 * interrupt. Furthermore, IRQ processing runs lockless so we have
7804 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7805 */
84b67b27 7806 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7807 if (!netif_tx_queue_stopped(txq)) {
7808 netif_tx_stop_queue(txq);
1f064a87
SH		 7809
7810 /* This is a hard error, log it. */
5129c3a3
MC		 7811 netdev_err(dev,
7812 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7813 }
1da177e4
LT		 7814 return NETDEV_TX_BUSY;
7815 }
7816
f3f3f27e 7817 entry = tnapi->tx_prod;
1da177e4 7818 base_flags = 0;
84fa7933 7819 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 7820 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 7821
be98da6a
MC		 7822 mss = skb_shinfo(skb)->gso_size;
7823 if (mss) {
eddc9ec5 7824 struct iphdr *iph;
34195c3d 7825 u32 tcp_opt_len, hdr_len;
1da177e4
LT		 7826
7827 if (skb_header_cloned(skb) &&
48855432
ED		 7828 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7829 goto drop;
1da177e4 7830
34195c3d 7831 iph = ip_hdr(skb);
ab6a5bb6 7832 tcp_opt_len = tcp_optlen(skb);
1da177e4 7833
a5a11955 7834 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7835
a5a11955 7836 if (!skb_is_gso_v6(skb)) {
34195c3d
MC		 7837 iph->check = 0;
7838 iph->tot_len = htons(mss + hdr_len);
7839 }
7840
52c0fd83 7841 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
63c3a66f 7842 tg3_flag(tp, TSO_BUG))
de6f31eb 7843 return tg3_tso_bug(tp, skb);
52c0fd83 7844
1da177e4
LT		 7845 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7846 TXD_FLAG_CPU_POST_DMA);
7847
63c3a66f
JP		 7848 if (tg3_flag(tp, HW_TSO_1) ||
7849 tg3_flag(tp, HW_TSO_2) ||
7850 tg3_flag(tp, HW_TSO_3)) {
aa8223c7 7851 tcp_hdr(skb)->check = 0;
1da177e4 7852 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
aa8223c7
ACM		 7853 } else
7854 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7855 iph->daddr, 0,
7856 IPPROTO_TCP,
7857 0);
1da177e4 7858
63c3a66f 7859 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7860 mss |= (hdr_len & 0xc) << 12;
7861 if (hdr_len & 0x10)
7862 base_flags |= 0x00000010;
7863 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7864 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7865 mss |= hdr_len << 9;
63c3a66f 7866 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7867 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7868 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7869 int tsflags;
7870
eddc9ec5 7871 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7872 mss |= (tsflags << 11);
7873 }
7874 } else {
eddc9ec5 7875 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7876 int tsflags;
7877
eddc9ec5 7878 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7879 base_flags |= tsflags << 12;
7880 }
7881 }
7882 }
bf933c80 7883
93a700a9
MC		 7884 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7885 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7886 base_flags |= TXD_FLAG_JMB_PKT;
7887
92cd3a17
MC		 7888 if (vlan_tx_tag_present(skb)) {
7889 base_flags |= TXD_FLAG_VLAN;
7890 vlan = vlan_tx_tag_get(skb);
7891 }
1da177e4 7892
fb4ce8ad
MC		 7893 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7894 tg3_flag(tp, TX_TSTAMP_EN)) {
7895 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7896 base_flags |= TXD_FLAG_HWTSTAMP;
7897 }
7898
f4188d8a
AD		 7899 len = skb_headlen(skb);
7900
7901 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 7902 if (pci_dma_mapping_error(tp->pdev, mapping))
7903 goto drop;
7904
90079ce8 7905
f3f3f27e 7906 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 7907 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 7908
7909 would_hit_hwbug = 0;
7910
63c3a66f 7911 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 7912 would_hit_hwbug = 1;
1da177e4 7913
84b67b27 7914 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 7915 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 7916 mss, vlan)) {
d1a3b737 7917 would_hit_hwbug = 1;
ba1142e4 7918 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 7919 u32 tmp_mss = mss;
7920
7921 if (!tg3_flag(tp, HW_TSO_1) &&
7922 !tg3_flag(tp, HW_TSO_2) &&
7923 !tg3_flag(tp, HW_TSO_3))
7924 tmp_mss = 0;
7925
c5665a53
MC		 7926 /* Now loop through additional data
7927 * fragments, and queue them.
7928 */
1da177e4
LT		 7929 last = skb_shinfo(skb)->nr_frags - 1;
7930 for (i = 0; i <= last; i++) {
7931 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7932
9e903e08 7933 len = skb_frag_size(frag);
dc234d0b 7934 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 7935 len, DMA_TO_DEVICE);
1da177e4 7936
f3f3f27e 7937 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 7938 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 7939 mapping);
5d6bcdfe 7940 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 7941 goto dma_error;
1da177e4 7942
b9e45482
MC		 7943 if (!budget ||
7944 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 7945 len, base_flags |
7946 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 7947 tmp_mss, vlan)) {
72f2afb8 7948 would_hit_hwbug = 1;
b9e45482
MC		 7949 break;
7950 }
1da177e4
LT		 7951 }
7952 }
7953
7954 if (would_hit_hwbug) {
0d681b27 7955 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4
LT		 7956
7957 /* If the workaround fails due to memory/mapping
7958 * failure, silently drop this packet.
7959 */
84b67b27
MC		 7960 entry = tnapi->tx_prod;
7961 budget = tg3_tx_avail(tnapi);
f7ff1987 7962 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 7963 base_flags, mss, vlan))
48855432 7964 goto drop_nofree;
1da177e4
LT		 7965 }
7966
d515b450 7967 skb_tx_timestamp(skb);
5cb917bc 7968 netdev_tx_sent_queue(txq, skb->len);
d515b450 7969
6541b806
MC		 7970 /* Sync BD data before updating mailbox */
7971 wmb();
7972
1da177e4 7973 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 7974 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 7975
f3f3f27e
MC		 7976 tnapi->tx_prod = entry;
7977 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 7978 netif_tx_stop_queue(txq);
f65aac16
MC		 7979
7980 /* netif_tx_stop_queue() must be done before checking
7981 * checking tx index in tg3_tx_avail() below, because in
7982 * tg3_tx(), we update tx index before checking for
7983 * netif_tx_queue_stopped().
7984 */
7985 smp_mb();
f3f3f27e 7986 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 7987 netif_tx_wake_queue(txq);
51b91468 7988 }
1da177e4 7989
cdd0db05 7990 mmiowb();
1da177e4 7991 return NETDEV_TX_OK;
f4188d8a
AD		 7992
7993dma_error:
ba1142e4 7994 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 7995 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432
ED		 7996drop:
7997 dev_kfree_skb(skb);
7998drop_nofree:
7999 tp->tx_dropped++;
f4188d8a 8000 return NETDEV_TX_OK;
1da177e4
LT		 8001}
8002
6e01b20b
MC		 8003static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8004{
8005 if (enable) {
8006 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8007 MAC_MODE_PORT_MODE_MASK);
8008
8009 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8010
8011 if (!tg3_flag(tp, 5705_PLUS))
8012 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8013
8014 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8015 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8016 else
8017 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8018 } else {
8019 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8020
8021 if (tg3_flag(tp, 5705_PLUS) ||
8022 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8023 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8024 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8025 }
8026
8027 tw32(MAC_MODE, tp->mac_mode);
8028 udelay(40);
8029}
8030
941ec90f 8031static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8032{
941ec90f 8033 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8034
8035 tg3_phy_toggle_apd(tp, false);
953c96e0 8036 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8037
941ec90f
MC		 8038 if (extlpbk && tg3_phy_set_extloopbk(tp))
8039 return -EIO;
8040
8041 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8042 switch (speed) {
8043 case SPEED_10:
8044 break;
8045 case SPEED_100:
8046 bmcr |= BMCR_SPEED100;
8047 break;
8048 case SPEED_1000:
8049 default:
8050 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8051 speed = SPEED_100;
8052 bmcr |= BMCR_SPEED100;
8053 } else {
8054 speed = SPEED_1000;
8055 bmcr |= BMCR_SPEED1000;
8056 }
8057 }
8058
941ec90f
MC		 8059 if (extlpbk) {
8060 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8061 tg3_readphy(tp, MII_CTRL1000, &val);
8062 val |= CTL1000_AS_MASTER |
8063 CTL1000_ENABLE_MASTER;
8064 tg3_writephy(tp, MII_CTRL1000, val);
8065 } else {
8066 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8067 MII_TG3_FET_PTEST_TRIM_2;
8068 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8069 }
8070 } else
8071 bmcr |= BMCR_LOOPBACK;
8072
5e5a7f37
MC		 8073 tg3_writephy(tp, MII_BMCR, bmcr);
8074
8075 /* The write needs to be flushed for the FETs */
8076 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8077 tg3_readphy(tp, MII_BMCR, &bmcr);
8078
8079 udelay(40);
8080
8081 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8082 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8083 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8084 MII_TG3_FET_PTEST_FRC_TX_LINK |
8085 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8086
8087 /* The write needs to be flushed for the AC131 */
8088 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8089 }
8090
8091 /* Reset to prevent losing 1st rx packet intermittently */
8092 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8093 tg3_flag(tp, 5780_CLASS)) {
8094 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8095 udelay(10);
8096 tw32_f(MAC_RX_MODE, tp->rx_mode);
8097 }
8098
8099 mac_mode = tp->mac_mode &
8100 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8101 if (speed == SPEED_1000)
8102 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8103 else
8104 mac_mode |= MAC_MODE_PORT_MODE_MII;
8105
4153577a 8106 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8107 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8108
8109 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8110 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8111 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8112 mac_mode |= MAC_MODE_LINK_POLARITY;
8113
8114 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8115 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8116 }
8117
8118 tw32(MAC_MODE, mac_mode);
8119 udelay(40);
941ec90f
MC		 8120
8121 return 0;
5e5a7f37
MC		 8122}
8123
c8f44aff 8124static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8125{
8126 struct tg3 *tp = netdev_priv(dev);
8127
8128 if (features & NETIF_F_LOOPBACK) {
8129 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8130 return;
8131
06c03c02 8132 spin_lock_bh(&tp->lock);
6e01b20b 8133 tg3_mac_loopback(tp, true);
06c03c02
MB		 8134 netif_carrier_on(tp->dev);
8135 spin_unlock_bh(&tp->lock);
8136 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8137 } else {
8138 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8139 return;
8140
06c03c02 8141 spin_lock_bh(&tp->lock);
6e01b20b 8142 tg3_mac_loopback(tp, false);
06c03c02 8143 /* Force link status check */
953c96e0 8144 tg3_setup_phy(tp, true);
06c03c02
MB		 8145 spin_unlock_bh(&tp->lock);
8146 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8147 }
8148}
8149
c8f44aff
MM		 8150static netdev_features_t tg3_fix_features(struct net_device *dev,
8151 netdev_features_t features)
dc668910
MM		 8152{
8153 struct tg3 *tp = netdev_priv(dev);
8154
63c3a66f 8155 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8156 features &= ~NETIF_F_ALL_TSO;
8157
8158 return features;
8159}
8160
c8f44aff 8161static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8162{
c8f44aff 8163 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8164
8165 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8166 tg3_set_loopback(dev, features);
8167
8168 return 0;
8169}
8170
21f581a5
MC		 8171static void tg3_rx_prodring_free(struct tg3 *tp,
8172 struct tg3_rx_prodring_set *tpr)
1da177e4 8173{
1da177e4
LT		 8174 int i;
8175
8fea32b9 8176 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8177 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8178 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8179 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8180 tp->rx_pkt_map_sz);
8181
63c3a66f 8182 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8183 for (i = tpr->rx_jmb_cons_idx;
8184 i != tpr->rx_jmb_prod_idx;
2c49a44d 8185 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8186 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8187 TG3_RX_JMB_MAP_SZ);
8188 }
8189 }
8190
2b2cdb65 8191 return;
b196c7e4 8192 }
1da177e4 8193
2c49a44d 8194 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8195 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8196 tp->rx_pkt_map_sz);
1da177e4 8197
63c3a66f 8198 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8199 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8200 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8201 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8202 }
8203}
8204
c6cdf436 8205/* Initialize rx rings for packet processing.
1da177e4
LT		 8206 *
8207 * The chip has been shut down and the driver detached from
8208 * the networking, so no interrupts or new tx packets will
8209 * end up in the driver. tp->{tx,}lock are held and thus
8210 * we may not sleep.
8211 */
21f581a5
MC		 8212static int tg3_rx_prodring_alloc(struct tg3 *tp,
8213 struct tg3_rx_prodring_set *tpr)
1da177e4 8214{
287be12e 8215 u32 i, rx_pkt_dma_sz;
1da177e4 8216
b196c7e4
MC		 8217 tpr->rx_std_cons_idx = 0;
8218 tpr->rx_std_prod_idx = 0;
8219 tpr->rx_jmb_cons_idx = 0;
8220 tpr->rx_jmb_prod_idx = 0;
8221
8fea32b9 8222 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8223 memset(&tpr->rx_std_buffers[0], 0,
8224 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8225 if (tpr->rx_jmb_buffers)
2b2cdb65 8226 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8227 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8228 goto done;
8229 }
8230
1da177e4 8231 /* Zero out all descriptors. */
2c49a44d 8232 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8233
287be12e 8234 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8235 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8236 tp->dev->mtu > ETH_DATA_LEN)
8237 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8238 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8239
1da177e4
LT		 8240 /* Initialize invariants of the rings, we only set this
8241 * stuff once. This works because the card does not
8242 * write into the rx buffer posting rings.
8243 */
2c49a44d 8244 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8245 struct tg3_rx_buffer_desc *rxd;
8246
21f581a5 8247 rxd = &tpr->rx_std[i];
287be12e 8248 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8249 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8250 rxd->opaque = (RXD_OPAQUE_RING_STD |
8251 (i << RXD_OPAQUE_INDEX_SHIFT));
8252 }
8253
1da177e4
LT		 8254 /* Now allocate fresh SKBs for each rx ring. */
8255 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8256 unsigned int frag_size;
8257
8258 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8259 &frag_size) < 0) {
5129c3a3
MC		 8260 netdev_warn(tp->dev,
8261 "Using a smaller RX standard ring. Only "
8262 "%d out of %d buffers were allocated "
8263 "successfully\n", i, tp->rx_pending);
32d8c572 8264 if (i == 0)
cf7a7298 8265 goto initfail;
32d8c572 8266 tp->rx_pending = i;
1da177e4 8267 break;
32d8c572 8268 }
1da177e4
LT		 8269 }
8270
63c3a66f 8271 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8272 goto done;
8273
2c49a44d 8274 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8275
63c3a66f 8276 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8277 goto done;
cf7a7298 8278
2c49a44d 8279 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8280 struct tg3_rx_buffer_desc *rxd;
8281
8282 rxd = &tpr->rx_jmb[i].std;
8283 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8284 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8285 RXD_FLAG_JUMBO;
8286 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8287 (i << RXD_OPAQUE_INDEX_SHIFT));
8288 }
8289
8290 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8291 unsigned int frag_size;
8292
8293 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8294 &frag_size) < 0) {
5129c3a3
MC		 8295 netdev_warn(tp->dev,
8296 "Using a smaller RX jumbo ring. Only %d "
8297 "out of %d buffers were allocated "
8298 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8299 if (i == 0)
8300 goto initfail;
8301 tp->rx_jumbo_pending = i;
8302 break;
1da177e4
LT		 8303 }
8304 }
cf7a7298
MC		 8305
8306done:
32d8c572 8307 return 0;
cf7a7298
MC		 8308
8309initfail:
21f581a5 8310 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8311 return -ENOMEM;
1da177e4
LT		 8312}
8313
21f581a5
MC		 8314static void tg3_rx_prodring_fini(struct tg3 *tp,
8315 struct tg3_rx_prodring_set *tpr)
1da177e4 8316{
21f581a5
MC		 8317 kfree(tpr->rx_std_buffers);
8318 tpr->rx_std_buffers = NULL;
8319 kfree(tpr->rx_jmb_buffers);
8320 tpr->rx_jmb_buffers = NULL;
8321 if (tpr->rx_std) {
4bae65c8
MC		 8322 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8323 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8324 tpr->rx_std = NULL;
1da177e4 8325 }
21f581a5 8326 if (tpr->rx_jmb) {
4bae65c8
MC		 8327 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8328 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8329 tpr->rx_jmb = NULL;
1da177e4 8330 }
cf7a7298
MC		 8331}
8332
21f581a5
MC		 8333static int tg3_rx_prodring_init(struct tg3 *tp,
8334 struct tg3_rx_prodring_set *tpr)
cf7a7298 8335{
2c49a44d
MC		 8336 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8337 GFP_KERNEL);
21f581a5 8338 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8339 return -ENOMEM;
8340
4bae65c8
MC		 8341 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8342 TG3_RX_STD_RING_BYTES(tp),
8343 &tpr->rx_std_mapping,
8344 GFP_KERNEL);
21f581a5 8345 if (!tpr->rx_std)
cf7a7298
MC		 8346 goto err_out;
8347
63c3a66f 8348 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8349 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8350 GFP_KERNEL);
8351 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8352 goto err_out;
8353
4bae65c8
MC		 8354 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8355 TG3_RX_JMB_RING_BYTES(tp),
8356 &tpr->rx_jmb_mapping,
8357 GFP_KERNEL);
21f581a5 8358 if (!tpr->rx_jmb)
cf7a7298
MC		 8359 goto err_out;
8360 }
8361
8362 return 0;
8363
8364err_out:
21f581a5 8365 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8366 return -ENOMEM;
8367}
8368
8369/* Free up pending packets in all rx/tx rings.
8370 *
8371 * The chip has been shut down and the driver detached from
8372 * the networking, so no interrupts or new tx packets will
8373 * end up in the driver. tp->{tx,}lock is not held and we are not
8374 * in an interrupt context and thus may sleep.
8375 */
8376static void tg3_free_rings(struct tg3 *tp)
8377{
f77a6a8e 8378 int i, j;
cf7a7298 8379
f77a6a8e
MC		 8380 for (j = 0; j < tp->irq_cnt; j++) {
8381 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8382
8fea32b9 8383 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8384
0c1d0e2b
MC		 8385 if (!tnapi->tx_buffers)
8386 continue;
8387
0d681b27
MC		 8388 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8389 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8390
0d681b27 8391 if (!skb)
f77a6a8e 8392 continue;
cf7a7298 8393
ba1142e4
MC		 8394 tg3_tx_skb_unmap(tnapi, i,
8395 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8396
8397 dev_kfree_skb_any(skb);
8398 }
5cb917bc 8399 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8400 }
cf7a7298
MC		 8401}
8402
8403/* Initialize tx/rx rings for packet processing.
8404 *
8405 * The chip has been shut down and the driver detached from
8406 * the networking, so no interrupts or new tx packets will
8407 * end up in the driver. tp->{tx,}lock are held and thus
8408 * we may not sleep.
8409 */
8410static int tg3_init_rings(struct tg3 *tp)
8411{
f77a6a8e 8412 int i;
72334482 8413
cf7a7298
MC		 8414 /* Free up all the SKBs. */
8415 tg3_free_rings(tp);
8416
f77a6a8e
MC		 8417 for (i = 0; i < tp->irq_cnt; i++) {
8418 struct tg3_napi *tnapi = &tp->napi[i];
8419
8420 tnapi->last_tag = 0;
8421 tnapi->last_irq_tag = 0;
8422 tnapi->hw_status->status = 0;
8423 tnapi->hw_status->status_tag = 0;
8424 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8425
f77a6a8e
MC		 8426 tnapi->tx_prod = 0;
8427 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8428 if (tnapi->tx_ring)
8429 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8430
8431 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8432 if (tnapi->rx_rcb)
8433 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8434
8fea32b9 8435 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8436 tg3_free_rings(tp);
2b2cdb65 8437 return -ENOMEM;
e4af1af9 8438 }
f77a6a8e 8439 }
72334482 8440
2b2cdb65 8441 return 0;
cf7a7298
MC		 8442}
8443
49a359e3 8444static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8445{
f77a6a8e 8446 int i;
898a56f8 8447
49a359e3 8448 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8449 struct tg3_napi *tnapi = &tp->napi[i];
8450
8451 if (tnapi->tx_ring) {
4bae65c8 8452 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8453 tnapi->tx_ring, tnapi->tx_desc_mapping);
8454 tnapi->tx_ring = NULL;
8455 }
8456
8457 kfree(tnapi->tx_buffers);
8458 tnapi->tx_buffers = NULL;
49a359e3
MC		 8459 }
8460}
f77a6a8e 8461
49a359e3
MC		 8462static int tg3_mem_tx_acquire(struct tg3 *tp)
8463{
8464 int i;
8465 struct tg3_napi *tnapi = &tp->napi[0];
8466
8467 /* If multivector TSS is enabled, vector 0 does not handle
8468 * tx interrupts. Don't allocate any resources for it.
8469 */
8470 if (tg3_flag(tp, ENABLE_TSS))
8471 tnapi++;
8472
8473 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8474 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8475 TG3_TX_RING_SIZE, GFP_KERNEL);
8476 if (!tnapi->tx_buffers)
8477 goto err_out;
8478
8479 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8480 TG3_TX_RING_BYTES,
8481 &tnapi->tx_desc_mapping,
8482 GFP_KERNEL);
8483 if (!tnapi->tx_ring)
8484 goto err_out;
8485 }
8486
8487 return 0;
8488
8489err_out:
8490 tg3_mem_tx_release(tp);
8491 return -ENOMEM;
8492}
8493
8494static void tg3_mem_rx_release(struct tg3 *tp)
8495{
8496 int i;
8497
8498 for (i = 0; i < tp->irq_max; i++) {
8499 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8500
8fea32b9
MC		 8501 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8502
49a359e3
MC		 8503 if (!tnapi->rx_rcb)
8504 continue;
8505
8506 dma_free_coherent(&tp->pdev->dev,
8507 TG3_RX_RCB_RING_BYTES(tp),
8508 tnapi->rx_rcb,
8509 tnapi->rx_rcb_mapping);
8510 tnapi->rx_rcb = NULL;
8511 }
8512}
8513
8514static int tg3_mem_rx_acquire(struct tg3 *tp)
8515{
8516 unsigned int i, limit;
8517
8518 limit = tp->rxq_cnt;
8519
8520 /* If RSS is enabled, we need a (dummy) producer ring
8521 * set on vector zero. This is the true hw prodring.
8522 */
8523 if (tg3_flag(tp, ENABLE_RSS))
8524 limit++;
8525
8526 for (i = 0; i < limit; i++) {
8527 struct tg3_napi *tnapi = &tp->napi[i];
8528
8529 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8530 goto err_out;
8531
8532 /* If multivector RSS is enabled, vector 0
8533 * does not handle rx or tx interrupts.
8534 * Don't allocate any resources for it.
8535 */
8536 if (!i && tg3_flag(tp, ENABLE_RSS))
8537 continue;
8538
8539 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
8540 TG3_RX_RCB_RING_BYTES(tp),
8541 &tnapi->rx_rcb_mapping,
1f9061d2 8542 GFP_KERNEL | __GFP_ZERO);
49a359e3
MC		 8543 if (!tnapi->rx_rcb)
8544 goto err_out;
49a359e3
MC		 8545 }
8546
8547 return 0;
8548
8549err_out:
8550 tg3_mem_rx_release(tp);
8551 return -ENOMEM;
8552}
8553
8554/*
8555 * Must not be invoked with interrupt sources disabled and
8556 * the hardware shutdown down.
8557 */
8558static void tg3_free_consistent(struct tg3 *tp)
8559{
8560 int i;
8561
8562 for (i = 0; i < tp->irq_cnt; i++) {
8563 struct tg3_napi *tnapi = &tp->napi[i];
8564
f77a6a8e 8565 if (tnapi->hw_status) {
4bae65c8
MC		 8566 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8567 tnapi->hw_status,
8568 tnapi->status_mapping);
f77a6a8e
MC		 8569 tnapi->hw_status = NULL;
8570 }
1da177e4 8571 }
f77a6a8e 8572
49a359e3
MC		 8573 tg3_mem_rx_release(tp);
8574 tg3_mem_tx_release(tp);
8575
1da177e4 8576 if (tp->hw_stats) {
4bae65c8
MC		 8577 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8578 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8579 tp->hw_stats = NULL;
8580 }
8581}
8582
8583/*
8584 * Must not be invoked with interrupt sources disabled and
8585 * the hardware shutdown down. Can sleep.
8586 */
8587static int tg3_alloc_consistent(struct tg3 *tp)
8588{
f77a6a8e 8589 int i;
898a56f8 8590
4bae65c8
MC		 8591 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
8592 sizeof(struct tg3_hw_stats),
8593 &tp->stats_mapping,
1f9061d2 8594 GFP_KERNEL | __GFP_ZERO);
f77a6a8e 8595 if (!tp->hw_stats)
1da177e4
LT		 8596 goto err_out;
8597
f77a6a8e
MC		 8598 for (i = 0; i < tp->irq_cnt; i++) {
8599 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8600 struct tg3_hw_status *sblk;
1da177e4 8601
4bae65c8
MC		 8602 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
8603 TG3_HW_STATUS_SIZE,
8604 &tnapi->status_mapping,
1f9061d2 8605 GFP_KERNEL | __GFP_ZERO);
f77a6a8e
MC		 8606 if (!tnapi->hw_status)
8607 goto err_out;
898a56f8 8608
8d9d7cfc
MC		 8609 sblk = tnapi->hw_status;
8610
49a359e3 8611 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8612 u16 *prodptr = NULL;
8fea32b9 8613
49a359e3
MC		 8614 /*
8615 * When RSS is enabled, the status block format changes
8616 * slightly. The "rx_jumbo_consumer", "reserved",
8617 * and "rx_mini_consumer" members get mapped to the
8618 * other three rx return ring producer indexes.
8619 */
8620 switch (i) {
8621 case 1:
8622 prodptr = &sblk->idx[0].rx_producer;
8623 break;
8624 case 2:
8625 prodptr = &sblk->rx_jumbo_consumer;
8626 break;
8627 case 3:
8628 prodptr = &sblk->reserved;
8629 break;
8630 case 4:
8631 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8632 break;
8633 }
49a359e3
MC		 8634 tnapi->rx_rcb_prod_idx = prodptr;
8635 } else {
8d9d7cfc 8636 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8637 }
f77a6a8e 8638 }
1da177e4 8639
49a359e3
MC		 8640 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8641 goto err_out;
8642
1da177e4
LT		 8643 return 0;
8644
8645err_out:
8646 tg3_free_consistent(tp);
8647 return -ENOMEM;
8648}
8649
8650#define MAX_WAIT_CNT 1000
8651
8652/* To stop a block, clear the enable bit and poll till it
8653 * clears. tp->lock is held.
8654 */
953c96e0 8655static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8656{
8657 unsigned int i;
8658 u32 val;
8659
63c3a66f 8660 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8661 switch (ofs) {
8662 case RCVLSC_MODE:
8663 case DMAC_MODE:
8664 case MBFREE_MODE:
8665 case BUFMGR_MODE:
8666 case MEMARB_MODE:
8667 /* We can't enable/disable these bits of the
8668 * 5705/5750, just say success.
8669 */
8670 return 0;
8671
8672 default:
8673 break;
855e1111 8674 }
1da177e4
LT		 8675 }
8676
8677 val = tr32(ofs);
8678 val &= ~enable_bit;
8679 tw32_f(ofs, val);
8680
8681 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8682 if (pci_channel_offline(tp->pdev)) {
8683 dev_err(&tp->pdev->dev,
8684 "tg3_stop_block device offline, "
8685 "ofs=%lx enable_bit=%x\n",
8686 ofs, enable_bit);
8687 return -ENODEV;
8688 }
8689
1da177e4
LT		 8690 udelay(100);
8691 val = tr32(ofs);
8692 if ((val & enable_bit) == 0)
8693 break;
8694 }
8695
b3b7d6be 8696 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8697 dev_err(&tp->pdev->dev,
8698 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8699 ofs, enable_bit);
1da177e4
LT		 8700 return -ENODEV;
8701 }
8702
8703 return 0;
8704}
8705
8706/* tp->lock is held. */
953c96e0 8707static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8708{
8709 int i, err;
8710
8711 tg3_disable_ints(tp);
8712
6d446ec3
GS		 8713 if (pci_channel_offline(tp->pdev)) {
8714 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8715 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8716 err = -ENODEV;
8717 goto err_no_dev;
8718 }
8719
1da177e4
LT		 8720 tp->rx_mode &= ~RX_MODE_ENABLE;
8721 tw32_f(MAC_RX_MODE, tp->rx_mode);
8722 udelay(10);
8723
b3b7d6be
DM		 8724 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8725 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8726 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8727 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8728 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8729 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8730
8731 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8732 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8733 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8734 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8735 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8736 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8737 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8738
8739 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8740 tw32_f(MAC_MODE, tp->mac_mode);
8741 udelay(40);
8742
8743 tp->tx_mode &= ~TX_MODE_ENABLE;
8744 tw32_f(MAC_TX_MODE, tp->tx_mode);
8745
8746 for (i = 0; i < MAX_WAIT_CNT; i++) {
8747 udelay(100);
8748 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8749 break;
8750 }
8751 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8752 dev_err(&tp->pdev->dev,
8753 "%s timed out, TX_MODE_ENABLE will not clear "
8754 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8755 err |= -ENODEV;
1da177e4
LT		 8756 }
8757
e6de8ad1 8758 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8759 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8760 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8761
8762 tw32(FTQ_RESET, 0xffffffff);
8763 tw32(FTQ_RESET, 0x00000000);
8764
b3b7d6be
DM		 8765 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8766 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8767
6d446ec3 8768err_no_dev:
f77a6a8e
MC		 8769 for (i = 0; i < tp->irq_cnt; i++) {
8770 struct tg3_napi *tnapi = &tp->napi[i];
8771 if (tnapi->hw_status)
8772 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8773 }
1da177e4 8774
1da177e4
LT		 8775 return err;
8776}
8777
ee6a99b5
MC		 8778/* Save PCI command register before chip reset */
8779static void tg3_save_pci_state(struct tg3 *tp)
8780{
8a6eac90 8781 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8782}
8783
8784/* Restore PCI state after chip reset */
8785static void tg3_restore_pci_state(struct tg3 *tp)
8786{
8787 u32 val;
8788
8789 /* Re-enable indirect register accesses. */
8790 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8791 tp->misc_host_ctrl);
8792
8793 /* Set MAX PCI retry to zero. */
8794 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8795 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8796 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8797 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8798 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8799 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8800 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8801 PCISTATE_ALLOW_APE_SHMEM_WR |
8802 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8803 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8804
8a6eac90 8805 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8806
2c55a3d0
MC		 8807 if (!tg3_flag(tp, PCI_EXPRESS)) {
8808 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8809 tp->pci_cacheline_sz);
8810 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8811 tp->pci_lat_timer);
114342f2 8812 }
5f5c51e3 8813
ee6a99b5 8814 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8815 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8816 u16 pcix_cmd;
8817
8818 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8819 &pcix_cmd);
8820 pcix_cmd &= ~PCI_X_CMD_ERO;
8821 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8822 pcix_cmd);
8823 }
ee6a99b5 8824
63c3a66f 8825 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8826
8827 /* Chip reset on 5780 will reset MSI enable bit,
8828 * so need to restore it.
8829 */
63c3a66f 8830 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8831 u16 ctrl;
8832
8833 pci_read_config_word(tp->pdev,
8834 tp->msi_cap + PCI_MSI_FLAGS,
8835 &ctrl);
8836 pci_write_config_word(tp->pdev,
8837 tp->msi_cap + PCI_MSI_FLAGS,
8838 ctrl | PCI_MSI_FLAGS_ENABLE);
8839 val = tr32(MSGINT_MODE);
8840 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8841 }
8842 }
8843}
8844
1da177e4
LT		 8845/* tp->lock is held. */
8846static int tg3_chip_reset(struct tg3 *tp)
8847{
8848 u32 val;
1ee582d8 8849 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 8850 int i, err;
1da177e4 8851
f49639e6
DM		 8852 tg3_nvram_lock(tp);
8853
77b483f1
MC		 8854 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8855
f49639e6
DM		 8856 /* No matching tg3_nvram_unlock() after this because
8857 * chip reset below will undo the nvram lock.
8858 */
8859 tp->nvram_lock_cnt = 0;
1da177e4 8860
ee6a99b5
MC		 8861 /* GRC_MISC_CFG core clock reset will clear the memory
8862 * enable bit in PCI register 4 and the MSI enable bit
8863 * on some chips, so we save relevant registers here.
8864 */
8865 tg3_save_pci_state(tp);
8866
4153577a 8867 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 8868 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 8869 tw32(GRC_FASTBOOT_PC, 0);
8870
1da177e4
LT		 8871 /*
8872 * We must avoid the readl() that normally takes place.
8873 * It locks machines, causes machine checks, and other
8874 * fun things. So, temporarily disable the 5701
8875 * hardware workaround, while we do the reset.
8876 */
1ee582d8
MC		 8877 write_op = tp->write32;
8878 if (write_op == tg3_write_flush_reg32)
8879 tp->write32 = tg3_write32;
1da177e4 8880
d18edcb2
MC		 8881 /* Prevent the irq handler from reading or writing PCI registers
8882 * during chip reset when the memory enable bit in the PCI command
8883 * register may be cleared. The chip does not generate interrupt
8884 * at this time, but the irq handler may still be called due to irq
8885 * sharing or irqpoll.
8886 */
63c3a66f 8887 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 8888 for (i = 0; i < tp->irq_cnt; i++) {
8889 struct tg3_napi *tnapi = &tp->napi[i];
8890 if (tnapi->hw_status) {
8891 tnapi->hw_status->status = 0;
8892 tnapi->hw_status->status_tag = 0;
8893 }
8894 tnapi->last_tag = 0;
8895 tnapi->last_irq_tag = 0;
b8fa2f3a 8896 }
d18edcb2 8897 smp_mb();
4f125f42
MC		 8898
8899 for (i = 0; i < tp->irq_cnt; i++)
8900 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 8901
4153577a 8902 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 8903 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8904 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8905 }
8906
1da177e4
LT		 8907 /* do the reset */
8908 val = GRC_MISC_CFG_CORECLK_RESET;
8909
63c3a66f 8910 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 8911 /* Force PCIe 1.0a mode */
4153577a 8912 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 8913 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 8914 tr32(TG3_PCIE_PHY_TSTCTL) ==
8915 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8916 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
8917
4153577a 8918 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 8919 tw32(GRC_MISC_CFG, (1 << 29));
8920 val |= (1 << 29);
8921 }
8922 }
8923
4153577a 8924 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 8925 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
8926 tw32(GRC_VCPU_EXT_CTRL,
8927 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
8928 }
8929
f37500d3 8930 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 8931 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 8932 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 8933
1da177e4
LT		 8934 tw32(GRC_MISC_CFG, val);
8935
1ee582d8
MC		 8936 /* restore 5701 hardware bug workaround write method */
8937 tp->write32 = write_op;
1da177e4
LT		 8938
8939 /* Unfortunately, we have to delay before the PCI read back.
8940 * Some 575X chips even will not respond to a PCI cfg access
8941 * when the reset command is given to the chip.
8942 *
8943 * How do these hardware designers expect things to work
8944 * properly if the PCI write is posted for a long period
8945 * of time? It is always necessary to have some method by
8946 * which a register read back can occur to push the write
8947 * out which does the reset.
8948 *
8949 * For most tg3 variants the trick below was working.
8950 * Ho hum...
8951 */
8952 udelay(120);
8953
8954 /* Flush PCI posted writes. The normal MMIO registers
8955 * are inaccessible at this time so this is the only
8956 * way to make this reliably (actually, this is no longer
8957 * the case, see above). I tried to use indirect
8958 * register read/write but this upset some 5701 variants.
8959 */
8960 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
8961
8962 udelay(120);
8963
0f49bfbd 8964 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 8965 u16 val16;
8966
4153577a 8967 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 8968 int j;
1da177e4
LT		 8969 u32 cfg_val;
8970
8971 /* Wait for link training to complete. */
86449944 8972 for (j = 0; j < 5000; j++)
1da177e4
LT		 8973 udelay(100);
8974
8975 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
8976 pci_write_config_dword(tp->pdev, 0xc4,
8977 cfg_val | (1 << 15));
8978 }
5e7dfd0f 8979
e7126997 8980 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 8981 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 8982 /*
8983 * Older PCIe devices only support the 128 byte
8984 * MPS setting. Enforce the restriction.
5e7dfd0f 8985 */
63c3a66f 8986 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 8987 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
8988 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 8989
5e7dfd0f 8990 /* Clear error status */
0f49bfbd 8991 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 8992 PCI_EXP_DEVSTA_CED |
8993 PCI_EXP_DEVSTA_NFED |
8994 PCI_EXP_DEVSTA_FED |
8995 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 8996 }
8997
ee6a99b5 8998 tg3_restore_pci_state(tp);
1da177e4 8999
63c3a66f
JP		 9000 tg3_flag_clear(tp, CHIP_RESETTING);
9001 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9002
ee6a99b5 9003 val = 0;
63c3a66f 9004 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9005 val = tr32(MEMARB_MODE);
ee6a99b5 9006 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9007
4153577a 9008 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9009 tg3_stop_fw(tp);
9010 tw32(0x5000, 0x400);
9011 }
9012
7e6c63f0
HM		 9013 if (tg3_flag(tp, IS_SSB_CORE)) {
9014 /*
9015 * BCM4785: In order to avoid repercussions from using
9016 * potentially defective internal ROM, stop the Rx RISC CPU,
9017 * which is not required.
9018 */
9019 tg3_stop_fw(tp);
9020 tg3_halt_cpu(tp, RX_CPU_BASE);
9021 }
9022
fb03a43f
NS		 9023 err = tg3_poll_fw(tp);
9024 if (err)
9025 return err;
9026
1da177e4
LT		 9027 tw32(GRC_MODE, tp->grc_mode);
9028
4153577a 9029 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9030 val = tr32(0xc4);
1da177e4
LT		 9031
9032 tw32(0xc4, val | (1 << 15));
9033 }
9034
9035 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9036 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9037 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9038 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9039 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9040 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9041 }
9042
f07e9af3 9043 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9044 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9045 val = tp->mac_mode;
f07e9af3 9046 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9047 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9048 val = tp->mac_mode;
1da177e4 9049 } else
d2394e6b
MC		 9050 val = 0;
9051
9052 tw32_f(MAC_MODE, val);
1da177e4
LT		 9053 udelay(40);
9054
77b483f1
MC		 9055 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9056
0a9140cf
MC		 9057 tg3_mdio_start(tp);
9058
63c3a66f 9059 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9060 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9061 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9062 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9063 val = tr32(0x7c00);
1da177e4
LT		 9064
9065 tw32(0x7c00, val | (1 << 25));
9066 }
9067
4153577a 9068 if (tg3_asic_rev(tp) == ASIC_REV_5720) {
d78b59f5
MC		 9069 val = tr32(TG3_CPMU_CLCK_ORIDE);
9070 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9071 }
9072
1da177e4 9073 /* Reprobe ASF enable state. */
63c3a66f 9074 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9075 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9076 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9077
63c3a66f 9078 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9079 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9080 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9081 u32 nic_cfg;
9082
9083 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9084 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9085 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9086 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9087 if (tg3_flag(tp, 5750_PLUS))
9088 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9089
9090 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9091 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9092 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9093 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9094 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9095 }
9096 }
9097
9098 return 0;
9099}
9100
65ec698d
MC		 9101static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9102static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
92feeabf 9103
1da177e4 9104/* tp->lock is held. */
953c96e0 9105static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9106{
9107 int err;
9108
9109 tg3_stop_fw(tp);
9110
944d980e 9111 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9112
b3b7d6be 9113 tg3_abort_hw(tp, silent);
1da177e4
LT		 9114 err = tg3_chip_reset(tp);
9115
953c96e0 9116 __tg3_set_mac_addr(tp, false);
daba2a63 9117
944d980e
MC		 9118 tg3_write_sig_legacy(tp, kind);
9119 tg3_write_sig_post_reset(tp, kind);
1da177e4 9120
92feeabf
MC		 9121 if (tp->hw_stats) {
9122 /* Save the stats across chip resets... */
b4017c53 9123 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9124 tg3_get_estats(tp, &tp->estats_prev);
9125
9126 /* And make sure the next sample is new data */
9127 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9128 }
9129
1da177e4
LT		 9130 if (err)
9131 return err;
9132
9133 return 0;
9134}
9135
1da177e4
LT		 9136static int tg3_set_mac_addr(struct net_device *dev, void *p)
9137{
9138 struct tg3 *tp = netdev_priv(dev);
9139 struct sockaddr *addr = p;
953c96e0
JP		 9140 int err = 0;
9141 bool skip_mac_1 = false;
1da177e4 9142
f9804ddb 9143 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9144 return -EADDRNOTAVAIL;
f9804ddb 9145
1da177e4
LT		 9146 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9147
e75f7c90
MC		 9148 if (!netif_running(dev))
9149 return 0;
9150
63c3a66f 9151 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9152 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9153
986e0aeb
MC		 9154 addr0_high = tr32(MAC_ADDR_0_HIGH);
9155 addr0_low = tr32(MAC_ADDR_0_LOW);
9156 addr1_high = tr32(MAC_ADDR_1_HIGH);
9157 addr1_low = tr32(MAC_ADDR_1_LOW);
9158
9159 /* Skip MAC addr 1 if ASF is using it. */
9160 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9161 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9162 skip_mac_1 = true;
58712ef9 9163 }
986e0aeb
MC		 9164 spin_lock_bh(&tp->lock);
9165 __tg3_set_mac_addr(tp, skip_mac_1);
9166 spin_unlock_bh(&tp->lock);
1da177e4 9167
b9ec6c1b 9168 return err;
1da177e4
LT		 9169}
9170
9171/* tp->lock is held. */
9172static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9173 dma_addr_t mapping, u32 maxlen_flags,
9174 u32 nic_addr)
9175{
9176 tg3_write_mem(tp,
9177 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9178 ((u64) mapping >> 32));
9179 tg3_write_mem(tp,
9180 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9181 ((u64) mapping & 0xffffffff));
9182 tg3_write_mem(tp,
9183 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9184 maxlen_flags);
9185
63c3a66f 9186 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9187 tg3_write_mem(tp,
9188 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9189 nic_addr);
9190}
9191
a489b6d9
MC		 9192
9193static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9194{
a489b6d9 9195 int i = 0;
b6080e12 9196
63c3a66f 9197 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9198 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9199 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9200 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9201 } else {
9202 tw32(HOSTCC_TXCOL_TICKS, 0);
9203 tw32(HOSTCC_TXMAX_FRAMES, 0);
9204 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9205
9206 for (; i < tp->txq_cnt; i++) {
9207 u32 reg;
9208
9209 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9210 tw32(reg, ec->tx_coalesce_usecs);
9211 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9212 tw32(reg, ec->tx_max_coalesced_frames);
9213 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9214 tw32(reg, ec->tx_max_coalesced_frames_irq);
9215 }
19cfaecc 9216 }
b6080e12 9217
a489b6d9
MC		 9218 for (; i < tp->irq_max - 1; i++) {
9219 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9220 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9221 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9222 }
9223}
9224
9225static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9226{
9227 int i = 0;
9228 u32 limit = tp->rxq_cnt;
9229
63c3a66f 9230 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9231 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9232 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9233 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9234 limit--;
19cfaecc 9235 } else {
b6080e12
MC		 9236 tw32(HOSTCC_RXCOL_TICKS, 0);
9237 tw32(HOSTCC_RXMAX_FRAMES, 0);
9238 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9239 }
b6080e12 9240
a489b6d9 9241 for (; i < limit; i++) {
b6080e12
MC		 9242 u32 reg;
9243
9244 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9245 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9246 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9247 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9248 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9249 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9250 }
9251
9252 for (; i < tp->irq_max - 1; i++) {
9253 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9254 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9255 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9256 }
9257}
19cfaecc 9258
a489b6d9
MC		 9259static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9260{
9261 tg3_coal_tx_init(tp, ec);
9262 tg3_coal_rx_init(tp, ec);
9263
9264 if (!tg3_flag(tp, 5705_PLUS)) {
9265 u32 val = ec->stats_block_coalesce_usecs;
9266
9267 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9268 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9269
f4a46d1f 9270 if (!tp->link_up)
a489b6d9
MC		 9271 val = 0;
9272
9273 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9274 }
15f9850d 9275}
1da177e4 9276
328947ff
NS		 9277/* tp->lock is held. */
9278static void tg3_tx_rcbs_disable(struct tg3 *tp)
9279{
9280 u32 txrcb, limit;
9281
9282 /* Disable all transmit rings but the first. */
9283 if (!tg3_flag(tp, 5705_PLUS))
9284 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9285 else if (tg3_flag(tp, 5717_PLUS))
9286 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9287 else if (tg3_flag(tp, 57765_CLASS) ||
9288 tg3_asic_rev(tp) == ASIC_REV_5762)
9289 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9290 else
9291 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9292
9293 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9294 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9295 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9296 BDINFO_FLAGS_DISABLED);
9297}
9298
32ba19ef
NS		 9299/* tp->lock is held. */
9300static void tg3_tx_rcbs_init(struct tg3 *tp)
9301{
9302 int i = 0;
9303 u32 txrcb = NIC_SRAM_SEND_RCB;
9304
9305 if (tg3_flag(tp, ENABLE_TSS))
9306 i++;
9307
9308 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9309 struct tg3_napi *tnapi = &tp->napi[i];
9310
9311 if (!tnapi->tx_ring)
9312 continue;
9313
9314 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9315 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9316 NIC_SRAM_TX_BUFFER_DESC);
9317 }
9318}
9319
328947ff
NS		 9320/* tp->lock is held. */
9321static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9322{
9323 u32 rxrcb, limit;
9324
9325 /* Disable all receive return rings but the first. */
9326 if (tg3_flag(tp, 5717_PLUS))
9327 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9328 else if (!tg3_flag(tp, 5705_PLUS))
9329 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9330 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9331 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9332 tg3_flag(tp, 57765_CLASS))
9333 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9334 else
9335 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9336
9337 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9338 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9339 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9340 BDINFO_FLAGS_DISABLED);
9341}
9342
32ba19ef
NS		 9343/* tp->lock is held. */
9344static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9345{
9346 int i = 0;
9347 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9348
9349 if (tg3_flag(tp, ENABLE_RSS))
9350 i++;
9351
9352 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9353 struct tg3_napi *tnapi = &tp->napi[i];
9354
9355 if (!tnapi->rx_rcb)
9356 continue;
9357
9358 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9359 (tp->rx_ret_ring_mask + 1) <<
9360 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9361 }
9362}
9363
2d31ecaf
MC		 9364/* tp->lock is held. */
9365static void tg3_rings_reset(struct tg3 *tp)
9366{
9367 int i;
328947ff 9368 u32 stblk;
2d31ecaf
MC		 9369 struct tg3_napi *tnapi = &tp->napi[0];
9370
328947ff 9371 tg3_tx_rcbs_disable(tp);
2d31ecaf 9372
328947ff 9373 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9374
9375 /* Disable interrupts */
9376 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9377 tp->napi[0].chk_msi_cnt = 0;
9378 tp->napi[0].last_rx_cons = 0;
9379 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9380
9381 /* Zero mailbox registers. */
63c3a66f 9382 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9383 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9384 tp->napi[i].tx_prod = 0;
9385 tp->napi[i].tx_cons = 0;
63c3a66f 9386 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9387 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9388 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9389 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9390 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9391 tp->napi[i].last_rx_cons = 0;
9392 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9393 }
63c3a66f 9394 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9395 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9396 } else {
9397 tp->napi[0].tx_prod = 0;
9398 tp->napi[0].tx_cons = 0;
9399 tw32_mailbox(tp->napi[0].prodmbox, 0);
9400 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9401 }
2d31ecaf
MC		 9402
9403 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9404 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9405 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9406 for (i = 0; i < 16; i++)
9407 tw32_tx_mbox(mbox + i * 8, 0);
9408 }
9409
2d31ecaf
MC		 9410 /* Clear status block in ram. */
9411 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9412
9413 /* Set status block DMA address */
9414 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9415 ((u64) tnapi->status_mapping >> 32));
9416 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9417 ((u64) tnapi->status_mapping & 0xffffffff));
9418
f77a6a8e 9419 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9420
f77a6a8e
MC		 9421 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9422 u64 mapping = (u64)tnapi->status_mapping;
9423 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9424 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9425 stblk += 8;
f77a6a8e
MC		 9426
9427 /* Clear status block in ram. */
9428 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9429 }
32ba19ef
NS		 9430
9431 tg3_tx_rcbs_init(tp);
9432 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9433}
9434
eb07a940
MC		 9435static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9436{
9437 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9438
63c3a66f
JP		 9439 if (!tg3_flag(tp, 5750_PLUS) ||
9440 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9441 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9442 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9443 tg3_flag(tp, 57765_PLUS))
eb07a940 9444 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9445 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9446 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9447 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9448 else
9449 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9450
9451 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9452 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9453
9454 val = min(nic_rep_thresh, host_rep_thresh);
9455 tw32(RCVBDI_STD_THRESH, val);
9456
63c3a66f 9457 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9458 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9459
63c3a66f 9460 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9461 return;
9462
513aa6ea 9463 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9464
9465 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9466
9467 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9468 tw32(RCVBDI_JUMBO_THRESH, val);
9469
63c3a66f 9470 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9471 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9472}
9473
ccd5ba9d
MC		 9474static inline u32 calc_crc(unsigned char *buf, int len)
9475{
9476 u32 reg;
9477 u32 tmp;
9478 int j, k;
9479
9480 reg = 0xffffffff;
9481
9482 for (j = 0; j < len; j++) {
9483 reg ^= buf[j];
9484
9485 for (k = 0; k < 8; k++) {
9486 tmp = reg & 0x01;
9487
9488 reg >>= 1;
9489
9490 if (tmp)
9491 reg ^= 0xedb88320;
9492 }
9493 }
9494
9495 return ~reg;
9496}
9497
9498static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9499{
9500 /* accept or reject all multicast frames */
9501 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9502 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9503 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9504 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9505}
9506
9507static void __tg3_set_rx_mode(struct net_device *dev)
9508{
9509 struct tg3 *tp = netdev_priv(dev);
9510 u32 rx_mode;
9511
9512 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9513 RX_MODE_KEEP_VLAN_TAG);
9514
9515#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9516 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9517 * flag clear.
9518 */
9519 if (!tg3_flag(tp, ENABLE_ASF))
9520 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9521#endif
9522
9523 if (dev->flags & IFF_PROMISC) {
9524 /* Promiscuous mode. */
9525 rx_mode |= RX_MODE_PROMISC;
9526 } else if (dev->flags & IFF_ALLMULTI) {
9527 /* Accept all multicast. */
9528 tg3_set_multi(tp, 1);
9529 } else if (netdev_mc_empty(dev)) {
9530 /* Reject all multicast. */
9531 tg3_set_multi(tp, 0);
9532 } else {
9533 /* Accept one or more multicast(s). */
9534 struct netdev_hw_addr *ha;
9535 u32 mc_filter[4] = { 0, };
9536 u32 regidx;
9537 u32 bit;
9538 u32 crc;
9539
9540 netdev_for_each_mc_addr(ha, dev) {
9541 crc = calc_crc(ha->addr, ETH_ALEN);
9542 bit = ~crc & 0x7f;
9543 regidx = (bit & 0x60) >> 5;
9544 bit &= 0x1f;
9545 mc_filter[regidx] |= (1 << bit);
9546 }
9547
9548 tw32(MAC_HASH_REG_0, mc_filter[0]);
9549 tw32(MAC_HASH_REG_1, mc_filter[1]);
9550 tw32(MAC_HASH_REG_2, mc_filter[2]);
9551 tw32(MAC_HASH_REG_3, mc_filter[3]);
9552 }
9553
9554 if (rx_mode != tp->rx_mode) {
9555 tp->rx_mode = rx_mode;
9556 tw32_f(MAC_RX_MODE, rx_mode);
9557 udelay(10);
9558 }
9559}
9560
9102426a 9561static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9562{
9563 int i;
9564
9565 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9566 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9567}
9568
9569static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9570{
9571 int i;
9572
9573 if (!tg3_flag(tp, SUPPORT_MSIX))
9574 return;
9575
0b3ba055 9576 if (tp->rxq_cnt == 1) {
bcebcc46 9577 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9578 return;
9579 }
9580
9581 /* Validate table against current IRQ count */
9582 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9583 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9584 break;
9585 }
9586
9587 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9588 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9589}
9590
90415477 9591static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9592{
9593 int i = 0;
9594 u32 reg = MAC_RSS_INDIR_TBL_0;
9595
9596 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9597 u32 val = tp->rss_ind_tbl[i];
9598 i++;
9599 for (; i % 8; i++) {
9600 val <<= 4;
9601 val |= tp->rss_ind_tbl[i];
9602 }
9603 tw32(reg, val);
9604 reg += 4;
9605 }
9606}
9607
9bc297ea
NS		 9608static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9609{
9610 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9611 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9612 else
9613 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9614}
9615
1da177e4 9616/* tp->lock is held. */
953c96e0 9617static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9618{
9619 u32 val, rdmac_mode;
9620 int i, err, limit;
8fea32b9 9621 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9622
9623 tg3_disable_ints(tp);
9624
9625 tg3_stop_fw(tp);
9626
9627 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9628
63c3a66f 9629 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9630 tg3_abort_hw(tp, 1);
1da177e4 9631
fdad8de4
NS		 9632 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9633 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9634 tg3_phy_pull_config(tp);
400dfbaa 9635 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9636 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9637 }
9638
400dfbaa
NS		 9639 /* Enable MAC control of LPI */
9640 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9641 tg3_setup_eee(tp);
9642
603f1173 9643 if (reset_phy)
d4d2c558
MC		 9644 tg3_phy_reset(tp);
9645
1da177e4
LT		 9646 err = tg3_chip_reset(tp);
9647 if (err)
9648 return err;
9649
9650 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9651
4153577a 9652 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9653 val = tr32(TG3_CPMU_CTRL);
9654 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9655 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9656
9657 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9658 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9659 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9660 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9661
9662 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9663 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9664 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9665 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9666
9667 val = tr32(TG3_CPMU_HST_ACC);
9668 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9669 val |= CPMU_HST_ACC_MACCLK_6_25;
9670 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9671 }
9672
4153577a 9673 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9674 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9675 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9676 PCIE_PWR_MGMT_L1_THRESH_4MS;
9677 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9678
9679 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9680 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9681
9682 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9683
f40386c8
MC		 9684 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9685 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9686 }
9687
63c3a66f 9688 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9689 u32 grc_mode = tr32(GRC_MODE);
9690
9691 /* Access the lower 1K of PL PCIE block registers. */
9692 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9693 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9694
9695 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9696 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9697 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9698
9699 tw32(GRC_MODE, grc_mode);
9700 }
9701
55086ad9 9702 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9703 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9704 u32 grc_mode = tr32(GRC_MODE);
cea46462 9705
5093eedc
MC		 9706 /* Access the lower 1K of PL PCIE block registers. */
9707 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9708 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9709
5093eedc
MC		 9710 val = tr32(TG3_PCIE_TLDLPL_PORT +
9711 TG3_PCIE_PL_LO_PHYCTL5);
9712 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9713 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9714
5093eedc
MC		 9715 tw32(GRC_MODE, grc_mode);
9716 }
a977dbe8 9717
4153577a 9718 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9719 u32 grc_mode;
9720
9721 /* Fix transmit hangs */
9722 val = tr32(TG3_CPMU_PADRNG_CTL);
9723 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9724 tw32(TG3_CPMU_PADRNG_CTL, val);
9725
9726 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9727
9728 /* Access the lower 1K of DL PCIE block registers. */
9729 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9730 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9731
9732 val = tr32(TG3_PCIE_TLDLPL_PORT +
9733 TG3_PCIE_DL_LO_FTSMAX);
9734 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9735 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9736 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9737
9738 tw32(GRC_MODE, grc_mode);
9739 }
9740
a977dbe8
MC		 9741 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9742 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9743 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9744 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9745 }
9746
1da177e4
LT		 9747 /* This works around an issue with Athlon chipsets on
9748 * B3 tigon3 silicon. This bit has no effect on any
9749 * other revision. But do not set this on PCI Express
795d01c5 9750 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9751 */
63c3a66f
JP		 9752 if (!tg3_flag(tp, CPMU_PRESENT)) {
9753 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9754 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9755 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9756 }
1da177e4 9757
4153577a 9758 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9759 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9760 val = tr32(TG3PCI_PCISTATE);
9761 val |= PCISTATE_RETRY_SAME_DMA;
9762 tw32(TG3PCI_PCISTATE, val);
9763 }
9764
63c3a66f 9765 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9766 /* Allow reads and writes to the
9767 * APE register and memory space.
9768 */
9769 val = tr32(TG3PCI_PCISTATE);
9770 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9771 PCISTATE_ALLOW_APE_SHMEM_WR |
9772 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9773 tw32(TG3PCI_PCISTATE, val);
9774 }
9775
4153577a 9776 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9777 /* Enable some hw fixes. */
9778 val = tr32(TG3PCI_MSI_DATA);
9779 val |= (1 << 26) | (1 << 28) | (1 << 29);
9780 tw32(TG3PCI_MSI_DATA, val);
9781 }
9782
9783 /* Descriptor ring init may make accesses to the
9784 * NIC SRAM area to setup the TX descriptors, so we
9785 * can only do this after the hardware has been
9786 * successfully reset.
9787 */
32d8c572
MC		 9788 err = tg3_init_rings(tp);
9789 if (err)
9790 return err;
1da177e4 9791
63c3a66f 9792 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9793 val = tr32(TG3PCI_DMA_RW_CTRL) &
9794 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9795 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9796 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9797 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9798 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9799 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9800 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9801 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9802 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9803 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9804 /* This value is determined during the probe time DMA
9805 * engine test, tg3_test_dma.
9806 */
9807 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9808 }
1da177e4
LT		 9809
9810 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9811 GRC_MODE_4X_NIC_SEND_RINGS |
9812 GRC_MODE_NO_TX_PHDR_CSUM |
9813 GRC_MODE_NO_RX_PHDR_CSUM);
9814 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 9815
9816 /* Pseudo-header checksum is done by hardware logic and not
9817 * the offload processers, so make the chip do the pseudo-
9818 * header checksums on receive. For transmit it is more
9819 * convenient to do the pseudo-header checksum in software
9820 * as Linux does that on transmit for us in all cases.
9821 */
9822 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 9823
fb4ce8ad
MC		 9824 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9825 if (tp->rxptpctl)
9826 tw32(TG3_RX_PTP_CTL,
9827 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9828
9829 if (tg3_flag(tp, PTP_CAPABLE))
9830 val |= GRC_MODE_TIME_SYNC_ENABLE;
9831
9832 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 9833
9834 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9835 val = tr32(GRC_MISC_CFG);
9836 val &= ~0xff;
9837 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9838 tw32(GRC_MISC_CFG, val);
9839
9840 /* Initialize MBUF/DESC pool. */
63c3a66f 9841 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 9842 /* Do nothing. */
4153577a 9843 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 9844 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 9845 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 9846 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
9847 else
9848 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
9849 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
9850 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 9851 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 9852 int fw_len;
9853
077f849d 9854 fw_len = tp->fw_len;
1da177e4
LT		 9855 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
9856 tw32(BUFMGR_MB_POOL_ADDR,
9857 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
9858 tw32(BUFMGR_MB_POOL_SIZE,
9859 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
9860 }
1da177e4 9861
0f893dc6 9862 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 9863 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9864 tp->bufmgr_config.mbuf_read_dma_low_water);
9865 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9866 tp->bufmgr_config.mbuf_mac_rx_low_water);
9867 tw32(BUFMGR_MB_HIGH_WATER,
9868 tp->bufmgr_config.mbuf_high_water);
9869 } else {
9870 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9871 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
9872 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9873 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
9874 tw32(BUFMGR_MB_HIGH_WATER,
9875 tp->bufmgr_config.mbuf_high_water_jumbo);
9876 }
9877 tw32(BUFMGR_DMA_LOW_WATER,
9878 tp->bufmgr_config.dma_low_water);
9879 tw32(BUFMGR_DMA_HIGH_WATER,
9880 tp->bufmgr_config.dma_high_water);
9881
d309a46e 9882 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 9883 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 9884 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a
JP		 9885 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
9886 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
9887 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 9888 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 9889 tw32(BUFMGR_MODE, val);
1da177e4
LT		 9890 for (i = 0; i < 2000; i++) {
9891 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
9892 break;
9893 udelay(10);
9894 }
9895 if (i >= 2000) {
05dbe005 9896 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 9897 return -ENODEV;
9898 }
9899
4153577a 9900 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 9901 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 9902
eb07a940 9903 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 9904
9905 /* Initialize TG3_BDINFO's at:
9906 * RCVDBDI_STD_BD: standard eth size rx ring
9907 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9908 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9909 *
9910 * like so:
9911 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9912 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9913 * ring attribute flags
9914 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9915 *
9916 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9917 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9918 *
9919 * The size of each ring is fixed in the firmware, but the location is
9920 * configurable.
9921 */
9922 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 9923 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 9924 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 9925 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 9926 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 9927 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
9928 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 9929
fdb72b38 9930 /* Disable the mini ring */
63c3a66f 9931 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9932 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
9933 BDINFO_FLAGS_DISABLED);
9934
fdb72b38
MC		 9935 /* Program the jumbo buffer descriptor ring control
9936 * blocks on those devices that have them.
9937 */
4153577a 9938 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 9939 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 9940
63c3a66f 9941 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 9942 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 9943 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 9944 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 9945 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 9946 val = TG3_RX_JMB_RING_SIZE(tp) <<
9947 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 9948 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 9949 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 9950 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 9951 tg3_flag(tp, 57765_CLASS) ||
4153577a 9952 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 9953 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
9954 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 9955 } else {
9956 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
9957 BDINFO_FLAGS_DISABLED);
9958 }
9959
63c3a66f 9960 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 9961 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 9962 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
9963 val |= (TG3_RX_STD_DMA_SZ << 2);
9964 } else
04380d40 9965 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 9966 } else
de9f5230 9967 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 9968
9969 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 9970
411da640 9971 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 9972 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 9973
63c3a66f
JP		 9974 tpr->rx_jmb_prod_idx =
9975 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 9976 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 9977
2d31ecaf
MC		 9978 tg3_rings_reset(tp);
9979
1da177e4 9980 /* Initialize MAC address and backoff seed. */
953c96e0 9981 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 9982
9983 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 9984 tw32(MAC_RX_MTU_SIZE,
9985 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 9986
9987 /* The slot time is changed by tg3_setup_phy if we
9988 * run at gigabit with half duplex.
9989 */
f2096f94
MC		 9990 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
9991 (6 << TX_LENGTHS_IPG_SHIFT) |
9992 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
9993
4153577a
JP		 9994 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
9995 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 9996 val |= tr32(MAC_TX_LENGTHS) &
9997 (TX_LENGTHS_JMB_FRM_LEN_MSK |
9998 TX_LENGTHS_CNT_DWN_VAL_MSK);
9999
10000 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10001
10002 /* Receive rules. */
10003 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10004 tw32(RCVLPC_CONFIG, 0x0181);
10005
10006 /* Calculate RDMAC_MODE setting early, we need it to determine
10007 * the RCVLPC_STATE_ENABLE mask.
10008 */
10009 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10010 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10011 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10012 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10013 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10014
4153577a 10015 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10016 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10017
4153577a
JP		 10018 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10019 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10020 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10021 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10022 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10023 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10024
4153577a
JP		 10025 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10026 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10027 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10028 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10029 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10030 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10031 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10032 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10033 }
10034 }
10035
63c3a66f 10036 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10037 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10038
4153577a 10039 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10040 tp->dma_limit = 0;
10041 if (tp->dev->mtu <= ETH_DATA_LEN) {
10042 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10043 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10044 }
10045 }
10046
63c3a66f
JP		 10047 if (tg3_flag(tp, HW_TSO_1) ||
10048 tg3_flag(tp, HW_TSO_2) ||
10049 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10050 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10051
108a6c16 10052 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10053 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10054 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10055 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10056
4153577a
JP		 10057 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10058 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10059 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10060
4153577a
JP		 10061 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10062 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10063 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10064 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10065 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10066 u32 tgtreg;
10067
4153577a 10068 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10069 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10070 else
10071 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10072
10073 val = tr32(tgtreg);
4153577a
JP		 10074 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10075 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10076 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10077 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10078 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10079 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10080 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10081 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10082 }
c65a17f4 10083 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10084 }
10085
4153577a
JP		 10086 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10087 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10088 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10089 u32 tgtreg;
10090
4153577a 10091 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10092 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10093 else
10094 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10095
10096 val = tr32(tgtreg);
10097 tw32(tgtreg, val |
d309a46e
MC		 10098 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10099 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10100 }
10101
1da177e4 10102 /* Receive/send statistics. */
63c3a66f 10103 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10104 val = tr32(RCVLPC_STATS_ENABLE);
10105 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10106 tw32(RCVLPC_STATS_ENABLE, val);
10107 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10108 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10109 val = tr32(RCVLPC_STATS_ENABLE);
10110 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10111 tw32(RCVLPC_STATS_ENABLE, val);
10112 } else {
10113 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10114 }
10115 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10116 tw32(SNDDATAI_STATSENAB, 0xffffff);
10117 tw32(SNDDATAI_STATSCTRL,
10118 (SNDDATAI_SCTRL_ENABLE |
10119 SNDDATAI_SCTRL_FASTUPD));
10120
10121 /* Setup host coalescing engine. */
10122 tw32(HOSTCC_MODE, 0);
10123 for (i = 0; i < 2000; i++) {
10124 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10125 break;
10126 udelay(10);
10127 }
10128
d244c892 10129 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10130
63c3a66f 10131 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10132 /* Status/statistics block address. See tg3_timer,
10133 * the tg3_periodic_fetch_stats call there, and
10134 * tg3_get_stats to see how this works for 5705/5750 chips.
10135 */
1da177e4
LT		 10136 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10137 ((u64) tp->stats_mapping >> 32));
10138 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10139 ((u64) tp->stats_mapping & 0xffffffff));
10140 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10141
1da177e4 10142 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10143
10144 /* Clear statistics and status block memory areas */
10145 for (i = NIC_SRAM_STATS_BLK;
10146 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10147 i += sizeof(u32)) {
10148 tg3_write_mem(tp, i, 0);
10149 udelay(40);
10150 }
1da177e4
LT		 10151 }
10152
10153 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10154
10155 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10156 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10157 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10158 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10159
f07e9af3
MC		 10160 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10161 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10162 /* reset to prevent losing 1st rx packet intermittently */
10163 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10164 udelay(10);
10165 }
10166
3bda1258 10167 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10168 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10169 MAC_MODE_FHDE_ENABLE;
10170 if (tg3_flag(tp, ENABLE_APE))
10171 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10172 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10173 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10174 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10175 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10176 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10177 udelay(40);
10178
314fba34 10179 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10180 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10181 * register to preserve the GPIO settings for LOMs. The GPIOs,
10182 * whether used as inputs or outputs, are set by boot code after
10183 * reset.
10184 */
63c3a66f 10185 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10186 u32 gpio_mask;
10187
9d26e213
MC		 10188 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10189 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10190 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10191
4153577a 10192 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10193 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10194 GRC_LCLCTRL_GPIO_OUTPUT3;
10195
4153577a 10196 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10197 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10198
aaf84465 10199 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10200 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10201
10202 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10203 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10204 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10205 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10206 }
1da177e4
LT		 10207 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10208 udelay(100);
10209
c3b5003b 10210 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10211 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10212 val |= MSGINT_MODE_ENABLE;
10213 if (tp->irq_cnt > 1)
10214 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10215 if (!tg3_flag(tp, 1SHOT_MSI))
10216 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10217 tw32(MSGINT_MODE, val);
10218 }
10219
63c3a66f 10220 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10221 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10222 udelay(40);
10223 }
10224
10225 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10226 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10227 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10228 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10229 WDMAC_MODE_LNGREAD_ENAB);
10230
4153577a
JP		 10231 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10232 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10233 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10234 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10235 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10236 /* nothing */
10237 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10238 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10239 val |= WDMAC_MODE_RX_ACCEL;
10240 }
10241 }
10242
d9ab5ad1 10243 /* Enable host coalescing bug fix */
63c3a66f 10244 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10245 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10246
4153577a 10247 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10248 val |= WDMAC_MODE_BURST_ALL_DATA;
10249
1da177e4
LT		 10250 tw32_f(WDMAC_MODE, val);
10251 udelay(40);
10252
63c3a66f 10253 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10254 u16 pcix_cmd;
10255
10256 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10257 &pcix_cmd);
4153577a 10258 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10259 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10260 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10261 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10262 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10263 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10264 }
9974a356
MC		 10265 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10266 pcix_cmd);
1da177e4
LT		 10267 }
10268
10269 tw32_f(RDMAC_MODE, rdmac_mode);
10270 udelay(40);
10271
9bc297ea
NS		 10272 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10273 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10274 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10275 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10276 break;
10277 }
10278 if (i < TG3_NUM_RDMA_CHANNELS) {
10279 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10280 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10281 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10282 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10283 }
10284 }
10285
1da177e4 10286 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10287 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10288 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10289
4153577a 10290 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10291 tw32(SNDDATAC_MODE,
10292 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10293 else
10294 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10295
1da177e4
LT		 10296 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10297 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10298 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10299 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10300 val |= RCVDBDI_MODE_LRG_RING_SZ;
10301 tw32(RCVDBDI_MODE, val);
1da177e4 10302 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10303 if (tg3_flag(tp, HW_TSO_1) ||
10304 tg3_flag(tp, HW_TSO_2) ||
10305 tg3_flag(tp, HW_TSO_3))
1da177e4 10306 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10307 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10308 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10309 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10310 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10311 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10312
4153577a 10313 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10314 err = tg3_load_5701_a0_firmware_fix(tp);
10315 if (err)
10316 return err;
10317 }
10318
c4dab506
NS		 10319 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10320 /* Ignore any errors for the firmware download. If download
10321 * fails, the device will operate with EEE disabled
10322 */
10323 tg3_load_57766_firmware(tp);
10324 }
10325
63c3a66f 10326 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10327 err = tg3_load_tso_firmware(tp);
10328 if (err)
10329 return err;
10330 }
1da177e4
LT		 10331
10332 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10333
63c3a66f 10334 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10335 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10336 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10337
4153577a
JP		 10338 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10339 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10340 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10341 tp->tx_mode &= ~val;
10342 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10343 }
10344
1da177e4
LT		 10345 tw32_f(MAC_TX_MODE, tp->tx_mode);
10346 udelay(100);
10347
63c3a66f 10348 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10349 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10350
10351 /* Setup the "secret" hash key. */
10352 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10353 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10354 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10355 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10356 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10357 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10358 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10359 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10360 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10361 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10362 }
10363
1da177e4 10364 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10365 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10366 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10367
63c3a66f 10368 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10369 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10370 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10371 RX_MODE_RSS_IPV6_HASH_EN |
10372 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10373 RX_MODE_RSS_IPV4_HASH_EN |
10374 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10375
1da177e4
LT		 10376 tw32_f(MAC_RX_MODE, tp->rx_mode);
10377 udelay(10);
10378
1da177e4
LT		 10379 tw32(MAC_LED_CTRL, tp->led_ctrl);
10380
10381 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10382 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10383 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10384 udelay(10);
10385 }
10386 tw32_f(MAC_RX_MODE, tp->rx_mode);
10387 udelay(10);
10388
f07e9af3 10389 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10390 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10391 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10392 /* Set drive transmission level to 1.2V */
10393 /* only if the signal pre-emphasis bit is not set */
10394 val = tr32(MAC_SERDES_CFG);
10395 val &= 0xfffff000;
10396 val |= 0x880;
10397 tw32(MAC_SERDES_CFG, val);
10398 }
4153577a 10399 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10400 tw32(MAC_SERDES_CFG, 0x616000);
10401 }
10402
10403 /* Prevent chip from dropping frames when flow control
10404 * is enabled.
10405 */
55086ad9 10406 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10407 val = 1;
10408 else
10409 val = 2;
10410 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10411
4153577a 10412 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10413 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10414 /* Use hardware link auto-negotiation */
63c3a66f 10415 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10416 }
10417
f07e9af3 10418 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10419 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10420 u32 tmp;
10421
10422 tmp = tr32(SERDES_RX_CTRL);
10423 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10424 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10425 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10426 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10427 }
10428
63c3a66f 10429 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10430 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10431 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10432
953c96e0 10433 err = tg3_setup_phy(tp, false);
dd477003
MC		 10434 if (err)
10435 return err;
1da177e4 10436
f07e9af3
MC		 10437 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10438 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10439 u32 tmp;
10440
10441 /* Clear CRC stats. */
10442 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10443 tg3_writephy(tp, MII_TG3_TEST1,
10444 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10445 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10446 }
1da177e4
LT		 10447 }
10448 }
10449
10450 __tg3_set_rx_mode(tp->dev);
10451
10452 /* Initialize receive rules. */
10453 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10454 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10455 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10456 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10457
63c3a66f 10458 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10459 limit = 8;
10460 else
10461 limit = 16;
63c3a66f 10462 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10463 limit -= 4;
10464 switch (limit) {
10465 case 16:
10466 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10467 case 15:
10468 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10469 case 14:
10470 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10471 case 13:
10472 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10473 case 12:
10474 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10475 case 11:
10476 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10477 case 10:
10478 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10479 case 9:
10480 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10481 case 8:
10482 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10483 case 7:
10484 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10485 case 6:
10486 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10487 case 5:
10488 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10489 case 4:
10490 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10491 case 3:
10492 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10493 case 2:
10494 case 1:
10495
10496 default:
10497 break;
855e1111 10498 }
1da177e4 10499
63c3a66f 10500 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10501 /* Write our heartbeat update interval to APE. */
10502 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10503 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10504
1da177e4
LT		 10505 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10506
1da177e4
LT		 10507 return 0;
10508}
10509
10510/* Called at device open time to get the chip ready for
10511 * packet processing. Invoked with tp->lock held.
10512 */
953c96e0 10513static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10514{
df465abf
NS		 10515 /* Chip may have been just powered on. If so, the boot code may still
10516 * be running initialization. Wait for it to finish to avoid races in
10517 * accessing the hardware.
10518 */
10519 tg3_enable_register_access(tp);
10520 tg3_poll_fw(tp);
10521
1da177e4
LT		 10522 tg3_switch_clocks(tp);
10523
10524 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10525
2f751b67 10526 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10527}
10528
aed93e0b
MC		 10529static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10530{
10531 int i;
10532
10533 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10534 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10535
10536 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10537 off += len;
10538
10539 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10540 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10541 memset(ocir, 0, TG3_OCIR_LEN);
10542 }
10543}
10544
10545/* sysfs attributes for hwmon */
10546static ssize_t tg3_show_temp(struct device *dev,
10547 struct device_attribute *devattr, char *buf)
10548{
10549 struct pci_dev *pdev = to_pci_dev(dev);
10550 struct net_device *netdev = pci_get_drvdata(pdev);
10551 struct tg3 *tp = netdev_priv(netdev);
10552 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10553 u32 temperature;
10554
10555 spin_lock_bh(&tp->lock);
10556 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10557 sizeof(temperature));
10558 spin_unlock_bh(&tp->lock);
10559 return sprintf(buf, "%u\n", temperature);
10560}
10561
10562
10563static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10564 TG3_TEMP_SENSOR_OFFSET);
10565static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10566 TG3_TEMP_CAUTION_OFFSET);
10567static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10568 TG3_TEMP_MAX_OFFSET);
10569
10570static struct attribute *tg3_attributes[] = {
10571 &sensor_dev_attr_temp1_input.dev_attr.attr,
10572 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10573 &sensor_dev_attr_temp1_max.dev_attr.attr,
10574 NULL
10575};
10576
10577static const struct attribute_group tg3_group = {
10578 .attrs = tg3_attributes,
10579};
10580
aed93e0b
MC		 10581static void tg3_hwmon_close(struct tg3 *tp)
10582{
aed93e0b
MC		 10583 if (tp->hwmon_dev) {
10584 hwmon_device_unregister(tp->hwmon_dev);
10585 tp->hwmon_dev = NULL;
10586 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
10587 }
aed93e0b
MC		 10588}
10589
10590static void tg3_hwmon_open(struct tg3 *tp)
10591{
aed93e0b
MC		 10592 int i, err;
10593 u32 size = 0;
10594 struct pci_dev *pdev = tp->pdev;
10595 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10596
10597 tg3_sd_scan_scratchpad(tp, ocirs);
10598
10599 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10600 if (!ocirs[i].src_data_length)
10601 continue;
10602
10603 size += ocirs[i].src_hdr_length;
10604 size += ocirs[i].src_data_length;
10605 }
10606
10607 if (!size)
10608 return;
10609
10610 /* Register hwmon sysfs hooks */
10611 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
10612 if (err) {
10613 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
10614 return;
10615 }
10616
10617 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
10618 if (IS_ERR(tp->hwmon_dev)) {
10619 tp->hwmon_dev = NULL;
10620 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10621 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
10622 }
aed93e0b
MC		 10623}
10624
10625
1da177e4
LT		 10626#define TG3_STAT_ADD32(PSTAT, REG) \
10627do { u32 __val = tr32(REG); \
10628 (PSTAT)->low += __val; \
10629 if ((PSTAT)->low < __val) \
10630 (PSTAT)->high += 1; \
10631} while (0)
10632
10633static void tg3_periodic_fetch_stats(struct tg3 *tp)
10634{
10635 struct tg3_hw_stats *sp = tp->hw_stats;
10636
f4a46d1f 10637 if (!tp->link_up)
1da177e4
LT		 10638 return;
10639
10640 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10641 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10642 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10643 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10644 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10645 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10646 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10647 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10648 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10649 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10650 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10651 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10652 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10653 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10654 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10655 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10656 u32 val;
10657
10658 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10659 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10660 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10661 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10662 }
1da177e4
LT		 10663
10664 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10665 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10666 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10667 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10668 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10669 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10670 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10671 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10672 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10673 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10674 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10675 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10676 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10677 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10678
10679 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a
JP		 10680 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10681 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10682 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10683 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10684 } else {
10685 u32 val = tr32(HOSTCC_FLOW_ATTN);
10686 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10687 if (val) {
10688 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10689 sp->rx_discards.low += val;
10690 if (sp->rx_discards.low < val)
10691 sp->rx_discards.high += 1;
10692 }
10693 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10694 }
463d305b 10695 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10696}
10697
0e6cf6a9
MC		 10698static void tg3_chk_missed_msi(struct tg3 *tp)
10699{
10700 u32 i;
10701
10702 for (i = 0; i < tp->irq_cnt; i++) {
10703 struct tg3_napi *tnapi = &tp->napi[i];
10704
10705 if (tg3_has_work(tnapi)) {
10706 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10707 tnapi->last_tx_cons == tnapi->tx_cons) {
10708 if (tnapi->chk_msi_cnt < 1) {
10709 tnapi->chk_msi_cnt++;
10710 return;
10711 }
7f230735 10712 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10713 }
10714 }
10715 tnapi->chk_msi_cnt = 0;
10716 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10717 tnapi->last_tx_cons = tnapi->tx_cons;
10718 }
10719}
10720
1da177e4
LT		 10721static void tg3_timer(unsigned long __opaque)
10722{
10723 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10724
5b190624 10725 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10726 goto restart_timer;
10727
f47c11ee 10728 spin_lock(&tp->lock);
1da177e4 10729
4153577a 10730 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10731 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10732 tg3_chk_missed_msi(tp);
10733
7e6c63f0
HM		 10734 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10735 /* BCM4785: Flush posted writes from GbE to host memory. */
10736 tr32(HOSTCC_MODE);
10737 }
10738
63c3a66f 10739 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10740 /* All of this garbage is because when using non-tagged
10741 * IRQ status the mailbox/status_block protocol the chip
10742 * uses with the cpu is race prone.
10743 */
898a56f8 10744 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10745 tw32(GRC_LOCAL_CTRL,
10746 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10747 } else {
10748 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10749 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10750 }
1da177e4 10751
fac9b83e 10752 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10753 spin_unlock(&tp->lock);
db219973 10754 tg3_reset_task_schedule(tp);
5b190624 10755 goto restart_timer;
fac9b83e 10756 }
1da177e4
LT		 10757 }
10758
1da177e4
LT		 10759 /* This part only runs once per second. */
10760 if (!--tp->timer_counter) {
63c3a66f 10761 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10762 tg3_periodic_fetch_stats(tp);
10763
b0c5943f
MC		 10764 if (tp->setlpicnt && !--tp->setlpicnt)
10765 tg3_phy_eee_enable(tp);
52b02d04 10766
63c3a66f 10767 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10768 u32 mac_stat;
10769 int phy_event;
10770
10771 mac_stat = tr32(MAC_STATUS);
10772
10773 phy_event = 0;
f07e9af3 10774 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10775 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10776 phy_event = 1;
10777 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10778 phy_event = 1;
10779
10780 if (phy_event)
953c96e0 10781 tg3_setup_phy(tp, false);
63c3a66f 10782 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10783 u32 mac_stat = tr32(MAC_STATUS);
10784 int need_setup = 0;
10785
f4a46d1f 10786 if (tp->link_up &&
1da177e4
LT		 10787 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10788 need_setup = 1;
10789 }
f4a46d1f 10790 if (!tp->link_up &&
1da177e4
LT		 10791 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10792 MAC_STATUS_SIGNAL_DET))) {
10793 need_setup = 1;
10794 }
10795 if (need_setup) {
3d3ebe74
MC		 10796 if (!tp->serdes_counter) {
10797 tw32_f(MAC_MODE,
10798 (tp->mac_mode &
10799 ~MAC_MODE_PORT_MODE_MASK));
10800 udelay(40);
10801 tw32_f(MAC_MODE, tp->mac_mode);
10802 udelay(40);
10803 }
953c96e0 10804 tg3_setup_phy(tp, false);
1da177e4 10805 }
f07e9af3 10806 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10807 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10808 tg3_serdes_parallel_detect(tp);
57d8b880 10809 }
1da177e4
LT		 10810
10811 tp->timer_counter = tp->timer_multiplier;
10812 }
10813
130b8e4d
MC		 10814 /* Heartbeat is only sent once every 2 seconds.
10815 *
10816 * The heartbeat is to tell the ASF firmware that the host
10817 * driver is still alive. In the event that the OS crashes,
10818 * ASF needs to reset the hardware to free up the FIFO space
10819 * that may be filled with rx packets destined for the host.
10820 * If the FIFO is full, ASF will no longer function properly.
10821 *
10822 * Unintended resets have been reported on real time kernels
10823 * where the timer doesn't run on time. Netpoll will also have
10824 * same problem.
10825 *
10826 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10827 * to check the ring condition when the heartbeat is expiring
10828 * before doing the reset. This will prevent most unintended
10829 * resets.
10830 */
1da177e4 10831 if (!--tp->asf_counter) {
63c3a66f 10832 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 10833 tg3_wait_for_event_ack(tp);
10834
bbadf503 10835 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 10836 FWCMD_NICDRV_ALIVE3);
bbadf503 10837 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 10838 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10839 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 10840
10841 tg3_generate_fw_event(tp);
1da177e4
LT		 10842 }
10843 tp->asf_counter = tp->asf_multiplier;
10844 }
10845
f47c11ee 10846 spin_unlock(&tp->lock);
1da177e4 10847
f475f163 10848restart_timer:
1da177e4
LT		 10849 tp->timer.expires = jiffies + tp->timer_offset;
10850 add_timer(&tp->timer);
10851}
10852
229b1ad1 10853static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 10854{
10855 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 10856 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 10857 !tg3_flag(tp, 57765_CLASS))
10858 tp->timer_offset = HZ;
10859 else
10860 tp->timer_offset = HZ / 10;
10861
10862 BUG_ON(tp->timer_offset > HZ);
10863
10864 tp->timer_multiplier = (HZ / tp->timer_offset);
10865 tp->asf_multiplier = (HZ / tp->timer_offset) *
10866 TG3_FW_UPDATE_FREQ_SEC;
10867
10868 init_timer(&tp->timer);
10869 tp->timer.data = (unsigned long) tp;
10870 tp->timer.function = tg3_timer;
10871}
10872
10873static void tg3_timer_start(struct tg3 *tp)
10874{
10875 tp->asf_counter = tp->asf_multiplier;
10876 tp->timer_counter = tp->timer_multiplier;
10877
10878 tp->timer.expires = jiffies + tp->timer_offset;
10879 add_timer(&tp->timer);
10880}
10881
10882static void tg3_timer_stop(struct tg3 *tp)
10883{
10884 del_timer_sync(&tp->timer);
10885}
10886
10887/* Restart hardware after configuration changes, self-test, etc.
10888 * Invoked with tp->lock held.
10889 */
953c96e0 10890static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 10891 __releases(tp->lock)
10892 __acquires(tp->lock)
10893{
10894 int err;
10895
10896 err = tg3_init_hw(tp, reset_phy);
10897 if (err) {
10898 netdev_err(tp->dev,
10899 "Failed to re-initialize device, aborting\n");
10900 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10901 tg3_full_unlock(tp);
10902 tg3_timer_stop(tp);
10903 tp->irq_sync = 0;
10904 tg3_napi_enable(tp);
10905 dev_close(tp->dev);
10906 tg3_full_lock(tp, 0);
10907 }
10908 return err;
10909}
10910
10911static void tg3_reset_task(struct work_struct *work)
10912{
10913 struct tg3 *tp = container_of(work, struct tg3, reset_task);
10914 int err;
10915
10916 tg3_full_lock(tp, 0);
10917
10918 if (!netif_running(tp->dev)) {
10919 tg3_flag_clear(tp, RESET_TASK_PENDING);
10920 tg3_full_unlock(tp);
10921 return;
10922 }
10923
10924 tg3_full_unlock(tp);
10925
10926 tg3_phy_stop(tp);
10927
10928 tg3_netif_stop(tp);
10929
10930 tg3_full_lock(tp, 1);
10931
10932 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
10933 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10934 tp->write32_rx_mbox = tg3_write_flush_reg32;
10935 tg3_flag_set(tp, MBOX_WRITE_REORDER);
10936 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
10937 }
10938
10939 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 10940 err = tg3_init_hw(tp, true);
21f7638e
MC		 10941 if (err)
10942 goto out;
10943
10944 tg3_netif_start(tp);
10945
10946out:
10947 tg3_full_unlock(tp);
10948
10949 if (!err)
10950 tg3_phy_start(tp);
10951
10952 tg3_flag_clear(tp, RESET_TASK_PENDING);
10953}
10954
4f125f42 10955static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 10956{
7d12e780 10957 irq_handler_t fn;
fcfa0a32 10958 unsigned long flags;
4f125f42
MC		 10959 char *name;
10960 struct tg3_napi *tnapi = &tp->napi[irq_num];
10961
10962 if (tp->irq_cnt == 1)
10963 name = tp->dev->name;
10964 else {
10965 name = &tnapi->irq_lbl[0];
10966 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
10967 name[IFNAMSIZ-1] = 0;
10968 }
fcfa0a32 10969
63c3a66f 10970 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 10971 fn = tg3_msi;
63c3a66f 10972 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 10973 fn = tg3_msi_1shot;
ab392d2d 10974 flags = 0;
fcfa0a32
MC		 10975 } else {
10976 fn = tg3_interrupt;
63c3a66f 10977 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 10978 fn = tg3_interrupt_tagged;
ab392d2d 10979 flags = IRQF_SHARED;
fcfa0a32 10980 }
4f125f42
MC		 10981
10982 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 10983}
10984
7938109f
MC		 10985static int tg3_test_interrupt(struct tg3 *tp)
10986{
09943a18 10987 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 10988 struct net_device *dev = tp->dev;
b16250e3 10989 int err, i, intr_ok = 0;
f6eb9b1f 10990 u32 val;
7938109f 10991
d4bc3927
MC		 10992 if (!netif_running(dev))
10993 return -ENODEV;
10994
7938109f
MC		 10995 tg3_disable_ints(tp);
10996
4f125f42 10997 free_irq(tnapi->irq_vec, tnapi);
7938109f 10998
f6eb9b1f
MC		 10999 /*
11000 * Turn off MSI one shot mode. Otherwise this test has no
11001 * observable way to know whether the interrupt was delivered.
11002 */
3aa1cdf8 11003 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11004 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11005 tw32(MSGINT_MODE, val);
11006 }
11007
4f125f42 11008 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11009 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11010 if (err)
11011 return err;
11012
898a56f8 11013 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11014 tg3_enable_ints(tp);
11015
11016 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11017 tnapi->coal_now);
7938109f
MC		 11018
11019 for (i = 0; i < 5; i++) {
b16250e3
MC		 11020 u32 int_mbox, misc_host_ctrl;
11021
898a56f8 11022 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11023 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11024
11025 if ((int_mbox != 0) ||
11026 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11027 intr_ok = 1;
7938109f 11028 break;
b16250e3
MC		 11029 }
11030
3aa1cdf8
MC		 11031 if (tg3_flag(tp, 57765_PLUS) &&
11032 tnapi->hw_status->status_tag != tnapi->last_tag)
11033 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11034
7938109f
MC		 11035 msleep(10);
11036 }
11037
11038 tg3_disable_ints(tp);
11039
4f125f42 11040 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11041
4f125f42 11042 err = tg3_request_irq(tp, 0);
7938109f
MC		 11043
11044 if (err)
11045 return err;
11046
f6eb9b1f
MC		 11047 if (intr_ok) {
11048 /* Reenable MSI one shot mode. */
5b39de91 11049 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11050 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11051 tw32(MSGINT_MODE, val);
11052 }
7938109f 11053 return 0;
f6eb9b1f 11054 }
7938109f
MC		 11055
11056 return -EIO;
11057}
11058
11059/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11060 * successfully restored
11061 */
11062static int tg3_test_msi(struct tg3 *tp)
11063{
7938109f
MC		 11064 int err;
11065 u16 pci_cmd;
11066
63c3a66f 11067 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11068 return 0;
11069
11070 /* Turn off SERR reporting in case MSI terminates with Master
11071 * Abort.
11072 */
11073 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11074 pci_write_config_word(tp->pdev, PCI_COMMAND,
11075 pci_cmd & ~PCI_COMMAND_SERR);
11076
11077 err = tg3_test_interrupt(tp);
11078
11079 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11080
11081 if (!err)
11082 return 0;
11083
11084 /* other failures */
11085 if (err != -EIO)
11086 return err;
11087
11088 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11089 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11090 "to INTx mode. Please report this failure to the PCI "
11091 "maintainer and include system chipset information\n");
7938109f 11092
4f125f42 11093 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11094
7938109f
MC		 11095 pci_disable_msi(tp->pdev);
11096
63c3a66f 11097 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11098 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11099
4f125f42 11100 err = tg3_request_irq(tp, 0);
7938109f
MC		 11101 if (err)
11102 return err;
11103
11104 /* Need to reset the chip because the MSI cycle may have terminated
11105 * with Master Abort.
11106 */
f47c11ee 11107 tg3_full_lock(tp, 1);
7938109f 11108
944d980e 11109 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11110 err = tg3_init_hw(tp, true);
7938109f 11111
f47c11ee 11112 tg3_full_unlock(tp);
7938109f
MC		 11113
11114 if (err)
4f125f42 11115 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11116
11117 return err;
11118}
11119
9e9fd12d
MC		 11120static int tg3_request_firmware(struct tg3 *tp)
11121{
77997ea3 11122 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11123
11124 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11125 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11126 tp->fw_needed);
9e9fd12d
MC		 11127 return -ENOENT;
11128 }
11129
77997ea3 11130 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11131
11132 /* Firmware blob starts with version numbers, followed by
11133 * start address and _full_ length including BSS sections
11134 * (which must be longer than the actual data, of course
11135 */
11136
77997ea3
NS		 11137 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11138 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11139 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11140 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11141 release_firmware(tp->fw);
11142 tp->fw = NULL;
11143 return -EINVAL;
11144 }
11145
11146 /* We no longer need firmware; we have it. */
11147 tp->fw_needed = NULL;
11148 return 0;
11149}
11150
9102426a 11151static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11152{
9102426a 11153 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11154
9102426a 11155 if (irq_cnt > 1) {
c3b5003b
MC		 11156 /* We want as many rx rings enabled as there are cpus.
11157 * In multiqueue MSI-X mode, the first MSI-X vector
11158 * only deals with link interrupts, etc, so we add
11159 * one to the number of vectors we are requesting.
11160 */
9102426a 11161 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11162 }
679563f4 11163
9102426a
MC		 11164 return irq_cnt;
11165}
11166
11167static bool tg3_enable_msix(struct tg3 *tp)
11168{
11169 int i, rc;
86449944 11170 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11171
0968169c
MC		 11172 tp->txq_cnt = tp->txq_req;
11173 tp->rxq_cnt = tp->rxq_req;
11174 if (!tp->rxq_cnt)
11175 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11176 if (tp->rxq_cnt > tp->rxq_max)
11177 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11178
11179 /* Disable multiple TX rings by default. Simple round-robin hardware
11180 * scheduling of the TX rings can cause starvation of rings with
11181 * small packets when other rings have TSO or jumbo packets.
11182 */
11183 if (!tp->txq_req)
11184 tp->txq_cnt = 1;
9102426a
MC		 11185
11186 tp->irq_cnt = tg3_irq_count(tp);
11187
679563f4
MC		 11188 for (i = 0; i < tp->irq_max; i++) {
11189 msix_ent[i].entry = i;
11190 msix_ent[i].vector = 0;
11191 }
11192
11193 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
2430b031
MC		 11194 if (rc < 0) {
11195 return false;
11196 } else if (rc != 0) {
679563f4
MC		 11197 if (pci_enable_msix(tp->pdev, msix_ent, rc))
11198 return false;
05dbe005
JP		 11199 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11200 tp->irq_cnt, rc);
679563f4 11201 tp->irq_cnt = rc;
49a359e3 11202 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11203 if (tp->txq_cnt)
11204 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11205 }
11206
11207 for (i = 0; i < tp->irq_max; i++)
11208 tp->napi[i].irq_vec = msix_ent[i].vector;
11209
49a359e3 11210 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11211 pci_disable_msix(tp->pdev);
11212 return false;
11213 }
b92b9040 11214
9102426a
MC		 11215 if (tp->irq_cnt == 1)
11216 return true;
d78b59f5 11217
9102426a
MC		 11218 tg3_flag_set(tp, ENABLE_RSS);
11219
11220 if (tp->txq_cnt > 1)
11221 tg3_flag_set(tp, ENABLE_TSS);
11222
11223 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11224
679563f4
MC		 11225 return true;
11226}
11227
07b0173c
MC		 11228static void tg3_ints_init(struct tg3 *tp)
11229{
63c3a66f
JP		 11230 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11231 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11232 /* All MSI supporting chips should support tagged
11233 * status. Assert that this is the case.
11234 */
5129c3a3
MC		 11235 netdev_warn(tp->dev,
11236 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11237 goto defcfg;
07b0173c 11238 }
4f125f42 11239
63c3a66f
JP		 11240 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11241 tg3_flag_set(tp, USING_MSIX);
11242 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11243 tg3_flag_set(tp, USING_MSI);
679563f4 11244
63c3a66f 11245 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11246 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11247 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11248 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11249 if (!tg3_flag(tp, 1SHOT_MSI))
11250 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11251 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11252 }
11253defcfg:
63c3a66f 11254 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11255 tp->irq_cnt = 1;
11256 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11257 }
11258
11259 if (tp->irq_cnt == 1) {
11260 tp->txq_cnt = 1;
11261 tp->rxq_cnt = 1;
2ddaad39 11262 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11263 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11264 }
07b0173c
MC		 11265}
11266
11267static void tg3_ints_fini(struct tg3 *tp)
11268{
63c3a66f 11269 if (tg3_flag(tp, USING_MSIX))
679563f4 11270 pci_disable_msix(tp->pdev);
63c3a66f 11271 else if (tg3_flag(tp, USING_MSI))
679563f4 11272 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11273 tg3_flag_clear(tp, USING_MSI);
11274 tg3_flag_clear(tp, USING_MSIX);
11275 tg3_flag_clear(tp, ENABLE_RSS);
11276 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11277}
11278
be947307
MC		 11279static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11280 bool init)
1da177e4 11281{
d8f4cd38 11282 struct net_device *dev = tp->dev;
4f125f42 11283 int i, err;
1da177e4 11284
679563f4
MC		 11285 /*
11286 * Setup interrupts first so we know how
11287 * many NAPI resources to allocate
11288 */
11289 tg3_ints_init(tp);
11290
90415477 11291 tg3_rss_check_indir_tbl(tp);
bcebcc46 11292
1da177e4
LT		 11293 /* The placement of this call is tied
11294 * to the setup and use of Host TX descriptors.
11295 */
11296 err = tg3_alloc_consistent(tp);
11297 if (err)
4a5f46f2 11298 goto out_ints_fini;
88b06bc2 11299
66cfd1bd
MC		 11300 tg3_napi_init(tp);
11301
fed97810 11302 tg3_napi_enable(tp);
1da177e4 11303
4f125f42
MC		 11304 for (i = 0; i < tp->irq_cnt; i++) {
11305 struct tg3_napi *tnapi = &tp->napi[i];
11306 err = tg3_request_irq(tp, i);
11307 if (err) {
5bc09186
MC		 11308 for (i--; i >= 0; i--) {
11309 tnapi = &tp->napi[i];
4f125f42 11310 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11311 }
4a5f46f2 11312 goto out_napi_fini;
4f125f42
MC		 11313 }
11314 }
1da177e4 11315
f47c11ee 11316 tg3_full_lock(tp, 0);
1da177e4 11317
2e460fc0
NS		 11318 if (init)
11319 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11320
d8f4cd38 11321 err = tg3_init_hw(tp, reset_phy);
1da177e4 11322 if (err) {
944d980e 11323 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11324 tg3_free_rings(tp);
1da177e4
LT		 11325 }
11326
f47c11ee 11327 tg3_full_unlock(tp);
1da177e4 11328
07b0173c 11329 if (err)
4a5f46f2 11330 goto out_free_irq;
1da177e4 11331
d8f4cd38 11332 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11333 err = tg3_test_msi(tp);
fac9b83e 11334
7938109f 11335 if (err) {
f47c11ee 11336 tg3_full_lock(tp, 0);
944d980e 11337 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11338 tg3_free_rings(tp);
f47c11ee 11339 tg3_full_unlock(tp);
7938109f 11340
4a5f46f2 11341 goto out_napi_fini;
7938109f 11342 }
fcfa0a32 11343
63c3a66f 11344 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11345 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11346
f6eb9b1f
MC		 11347 tw32(PCIE_TRANSACTION_CFG,
11348 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11349 }
7938109f
MC		 11350 }
11351
b02fd9e3
MC		 11352 tg3_phy_start(tp);
11353
aed93e0b
MC		 11354 tg3_hwmon_open(tp);
11355
f47c11ee 11356 tg3_full_lock(tp, 0);
1da177e4 11357
21f7638e 11358 tg3_timer_start(tp);
63c3a66f 11359 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11360 tg3_enable_ints(tp);
11361
be947307
MC		 11362 if (init)
11363 tg3_ptp_init(tp);
11364 else
11365 tg3_ptp_resume(tp);
11366
11367
f47c11ee 11368 tg3_full_unlock(tp);
1da177e4 11369
fe5f5787 11370 netif_tx_start_all_queues(dev);
1da177e4 11371
06c03c02
MB		 11372 /*
11373 * Reset loopback feature if it was turned on while the device was down
11374 * make sure that it's installed properly now.
11375 */
11376 if (dev->features & NETIF_F_LOOPBACK)
11377 tg3_set_loopback(dev, dev->features);
11378
1da177e4 11379 return 0;
07b0173c 11380
4a5f46f2 11381out_free_irq:
4f125f42
MC		 11382 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11383 struct tg3_napi *tnapi = &tp->napi[i];
11384 free_irq(tnapi->irq_vec, tnapi);
11385 }
07b0173c 11386
4a5f46f2 11387out_napi_fini:
fed97810 11388 tg3_napi_disable(tp);
66cfd1bd 11389 tg3_napi_fini(tp);
07b0173c 11390 tg3_free_consistent(tp);
679563f4 11391
4a5f46f2 11392out_ints_fini:
679563f4 11393 tg3_ints_fini(tp);
d8f4cd38 11394
07b0173c 11395 return err;
1da177e4
LT		 11396}
11397
65138594 11398static void tg3_stop(struct tg3 *tp)
1da177e4 11399{
4f125f42 11400 int i;
1da177e4 11401
db219973 11402 tg3_reset_task_cancel(tp);
bd473da3 11403 tg3_netif_stop(tp);
1da177e4 11404
21f7638e 11405 tg3_timer_stop(tp);
1da177e4 11406
aed93e0b
MC		 11407 tg3_hwmon_close(tp);
11408
24bb4fb6
MC		 11409 tg3_phy_stop(tp);
11410
f47c11ee 11411 tg3_full_lock(tp, 1);
1da177e4
LT		 11412
11413 tg3_disable_ints(tp);
11414
944d980e 11415 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11416 tg3_free_rings(tp);
63c3a66f 11417 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11418
f47c11ee 11419 tg3_full_unlock(tp);
1da177e4 11420
4f125f42
MC		 11421 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11422 struct tg3_napi *tnapi = &tp->napi[i];
11423 free_irq(tnapi->irq_vec, tnapi);
11424 }
07b0173c
MC		 11425
11426 tg3_ints_fini(tp);
1da177e4 11427
66cfd1bd
MC		 11428 tg3_napi_fini(tp);
11429
1da177e4 11430 tg3_free_consistent(tp);
65138594
MC		 11431}
11432
d8f4cd38
MC		 11433static int tg3_open(struct net_device *dev)
11434{
11435 struct tg3 *tp = netdev_priv(dev);
11436 int err;
11437
11438 if (tp->fw_needed) {
11439 err = tg3_request_firmware(tp);
c4dab506
NS		 11440 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11441 if (err) {
11442 netdev_warn(tp->dev, "EEE capability disabled\n");
11443 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11444 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11445 netdev_warn(tp->dev, "EEE capability restored\n");
11446 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11447 }
11448 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11449 if (err)
11450 return err;
11451 } else if (err) {
11452 netdev_warn(tp->dev, "TSO capability disabled\n");
11453 tg3_flag_clear(tp, TSO_CAPABLE);
11454 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11455 netdev_notice(tp->dev, "TSO capability restored\n");
11456 tg3_flag_set(tp, TSO_CAPABLE);
11457 }
11458 }
11459
f4a46d1f 11460 tg3_carrier_off(tp);
d8f4cd38
MC		 11461
11462 err = tg3_power_up(tp);
11463 if (err)
11464 return err;
11465
11466 tg3_full_lock(tp, 0);
11467
11468 tg3_disable_ints(tp);
11469 tg3_flag_clear(tp, INIT_COMPLETE);
11470
11471 tg3_full_unlock(tp);
11472
942d1af0
NS		 11473 err = tg3_start(tp,
11474 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11475 true, true);
d8f4cd38
MC		 11476 if (err) {
11477 tg3_frob_aux_power(tp, false);
11478 pci_set_power_state(tp->pdev, PCI_D3hot);
11479 }
be947307 11480
7d41e49a
MC		 11481 if (tg3_flag(tp, PTP_CAPABLE)) {
11482 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11483 &tp->pdev->dev);
11484 if (IS_ERR(tp->ptp_clock))
11485 tp->ptp_clock = NULL;
11486 }
11487
07b0173c 11488 return err;
1da177e4
LT		 11489}
11490
1da177e4
LT		 11491static int tg3_close(struct net_device *dev)
11492{
11493 struct tg3 *tp = netdev_priv(dev);
11494
be947307
MC		 11495 tg3_ptp_fini(tp);
11496
65138594 11497 tg3_stop(tp);
1da177e4 11498
92feeabf
MC		 11499 /* Clear stats across close / open calls */
11500 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11501 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11502
5137a2ee 11503 tg3_power_down_prepare(tp);
bc1c7567 11504
f4a46d1f 11505 tg3_carrier_off(tp);
bc1c7567 11506
1da177e4
LT		 11507 return 0;
11508}
11509
511d2224 11510static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11511{
11512 return ((u64)val->high << 32) | ((u64)val->low);
11513}
11514
65ec698d 11515static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11516{
11517 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11518
f07e9af3 11519 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11520 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11521 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11522 u32 val;
11523
569a5df8
MC		 11524 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11525 tg3_writephy(tp, MII_TG3_TEST1,
11526 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11527 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11528 } else
11529 val = 0;
1da177e4
LT		 11530
11531 tp->phy_crc_errors += val;
11532
11533 return tp->phy_crc_errors;
11534 }
11535
11536 return get_stat64(&hw_stats->rx_fcs_errors);
11537}
11538
11539#define ESTAT_ADD(member) \
11540 estats->member = old_estats->member + \
511d2224 11541 get_stat64(&hw_stats->member)
1da177e4 11542
65ec698d 11543static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11544{
1da177e4
LT		 11545 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11546 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11547
1da177e4
LT		 11548 ESTAT_ADD(rx_octets);
11549 ESTAT_ADD(rx_fragments);
11550 ESTAT_ADD(rx_ucast_packets);
11551 ESTAT_ADD(rx_mcast_packets);
11552 ESTAT_ADD(rx_bcast_packets);
11553 ESTAT_ADD(rx_fcs_errors);
11554 ESTAT_ADD(rx_align_errors);
11555 ESTAT_ADD(rx_xon_pause_rcvd);
11556 ESTAT_ADD(rx_xoff_pause_rcvd);
11557 ESTAT_ADD(rx_mac_ctrl_rcvd);
11558 ESTAT_ADD(rx_xoff_entered);
11559 ESTAT_ADD(rx_frame_too_long_errors);
11560 ESTAT_ADD(rx_jabbers);
11561 ESTAT_ADD(rx_undersize_packets);
11562 ESTAT_ADD(rx_in_length_errors);
11563 ESTAT_ADD(rx_out_length_errors);
11564 ESTAT_ADD(rx_64_or_less_octet_packets);
11565 ESTAT_ADD(rx_65_to_127_octet_packets);
11566 ESTAT_ADD(rx_128_to_255_octet_packets);
11567 ESTAT_ADD(rx_256_to_511_octet_packets);
11568 ESTAT_ADD(rx_512_to_1023_octet_packets);
11569 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11570 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11571 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11572 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11573 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11574
11575 ESTAT_ADD(tx_octets);
11576 ESTAT_ADD(tx_collisions);
11577 ESTAT_ADD(tx_xon_sent);
11578 ESTAT_ADD(tx_xoff_sent);
11579 ESTAT_ADD(tx_flow_control);
11580 ESTAT_ADD(tx_mac_errors);
11581 ESTAT_ADD(tx_single_collisions);
11582 ESTAT_ADD(tx_mult_collisions);
11583 ESTAT_ADD(tx_deferred);
11584 ESTAT_ADD(tx_excessive_collisions);
11585 ESTAT_ADD(tx_late_collisions);
11586 ESTAT_ADD(tx_collide_2times);
11587 ESTAT_ADD(tx_collide_3times);
11588 ESTAT_ADD(tx_collide_4times);
11589 ESTAT_ADD(tx_collide_5times);
11590 ESTAT_ADD(tx_collide_6times);
11591 ESTAT_ADD(tx_collide_7times);
11592 ESTAT_ADD(tx_collide_8times);
11593 ESTAT_ADD(tx_collide_9times);
11594 ESTAT_ADD(tx_collide_10times);
11595 ESTAT_ADD(tx_collide_11times);
11596 ESTAT_ADD(tx_collide_12times);
11597 ESTAT_ADD(tx_collide_13times);
11598 ESTAT_ADD(tx_collide_14times);
11599 ESTAT_ADD(tx_collide_15times);
11600 ESTAT_ADD(tx_ucast_packets);
11601 ESTAT_ADD(tx_mcast_packets);
11602 ESTAT_ADD(tx_bcast_packets);
11603 ESTAT_ADD(tx_carrier_sense_errors);
11604 ESTAT_ADD(tx_discards);
11605 ESTAT_ADD(tx_errors);
11606
11607 ESTAT_ADD(dma_writeq_full);
11608 ESTAT_ADD(dma_write_prioq_full);
11609 ESTAT_ADD(rxbds_empty);
11610 ESTAT_ADD(rx_discards);
11611 ESTAT_ADD(rx_errors);
11612 ESTAT_ADD(rx_threshold_hit);
11613
11614 ESTAT_ADD(dma_readq_full);
11615 ESTAT_ADD(dma_read_prioq_full);
11616 ESTAT_ADD(tx_comp_queue_full);
11617
11618 ESTAT_ADD(ring_set_send_prod_index);
11619 ESTAT_ADD(ring_status_update);
11620 ESTAT_ADD(nic_irqs);
11621 ESTAT_ADD(nic_avoided_irqs);
11622 ESTAT_ADD(nic_tx_threshold_hit);
11623
4452d099 11624 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11625}
11626
65ec698d 11627static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11628{
511d2224 11629 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11630 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11631
1da177e4
LT		 11632 stats->rx_packets = old_stats->rx_packets +
11633 get_stat64(&hw_stats->rx_ucast_packets) +
11634 get_stat64(&hw_stats->rx_mcast_packets) +
11635 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11636
1da177e4
LT		 11637 stats->tx_packets = old_stats->tx_packets +
11638 get_stat64(&hw_stats->tx_ucast_packets) +
11639 get_stat64(&hw_stats->tx_mcast_packets) +
11640 get_stat64(&hw_stats->tx_bcast_packets);
11641
11642 stats->rx_bytes = old_stats->rx_bytes +
11643 get_stat64(&hw_stats->rx_octets);
11644 stats->tx_bytes = old_stats->tx_bytes +
11645 get_stat64(&hw_stats->tx_octets);
11646
11647 stats->rx_errors = old_stats->rx_errors +
4f63b877 11648 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11649 stats->tx_errors = old_stats->tx_errors +
11650 get_stat64(&hw_stats->tx_errors) +
11651 get_stat64(&hw_stats->tx_mac_errors) +
11652 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11653 get_stat64(&hw_stats->tx_discards);
11654
11655 stats->multicast = old_stats->multicast +
11656 get_stat64(&hw_stats->rx_mcast_packets);
11657 stats->collisions = old_stats->collisions +
11658 get_stat64(&hw_stats->tx_collisions);
11659
11660 stats->rx_length_errors = old_stats->rx_length_errors +
11661 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11662 get_stat64(&hw_stats->rx_undersize_packets);
11663
11664 stats->rx_over_errors = old_stats->rx_over_errors +
11665 get_stat64(&hw_stats->rxbds_empty);
11666 stats->rx_frame_errors = old_stats->rx_frame_errors +
11667 get_stat64(&hw_stats->rx_align_errors);
11668 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11669 get_stat64(&hw_stats->tx_discards);
11670 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11671 get_stat64(&hw_stats->tx_carrier_sense_errors);
11672
11673 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11674 tg3_calc_crc_errors(tp);
1da177e4 11675
4f63b877
JL		 11676 stats->rx_missed_errors = old_stats->rx_missed_errors +
11677 get_stat64(&hw_stats->rx_discards);
11678
b0057c51 11679 stats->rx_dropped = tp->rx_dropped;
48855432 11680 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11681}
11682
1da177e4
LT		 11683static int tg3_get_regs_len(struct net_device *dev)
11684{
97bd8e49 11685 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11686}
11687
11688static void tg3_get_regs(struct net_device *dev,
11689 struct ethtool_regs *regs, void *_p)
11690{
1da177e4 11691 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11692
11693 regs->version = 0;
11694
97bd8e49 11695 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11696
80096068 11697 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11698 return;
11699
f47c11ee 11700 tg3_full_lock(tp, 0);
1da177e4 11701
97bd8e49 11702 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11703
f47c11ee 11704 tg3_full_unlock(tp);
1da177e4
LT		 11705}
11706
11707static int tg3_get_eeprom_len(struct net_device *dev)
11708{
11709 struct tg3 *tp = netdev_priv(dev);
11710
11711 return tp->nvram_size;
11712}
11713
1da177e4
LT		 11714static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11715{
11716 struct tg3 *tp = netdev_priv(dev);
11717 int ret;
11718 u8 *pd;
b9fc7dc5 11719 u32 i, offset, len, b_offset, b_count;
a9dc529d 11720 __be32 val;
1da177e4 11721
63c3a66f 11722 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11723 return -EINVAL;
11724
1da177e4
LT		 11725 offset = eeprom->offset;
11726 len = eeprom->len;
11727 eeprom->len = 0;
11728
11729 eeprom->magic = TG3_EEPROM_MAGIC;
11730
11731 if (offset & 3) {
11732 /* adjustments to start on required 4 byte boundary */
11733 b_offset = offset & 3;
11734 b_count = 4 - b_offset;
11735 if (b_count > len) {
11736 /* i.e. offset=1 len=2 */
11737 b_count = len;
11738 }
a9dc529d 11739 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 11740 if (ret)
11741 return ret;
be98da6a 11742 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11743 len -= b_count;
11744 offset += b_count;
c6cdf436 11745 eeprom->len += b_count;
1da177e4
LT		 11746 }
11747
25985edc 11748 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11749 pd = &data[eeprom->len];
11750 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11751 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 11752 if (ret) {
11753 eeprom->len += i;
11754 return ret;
11755 }
1da177e4
LT		 11756 memcpy(pd + i, &val, 4);
11757 }
11758 eeprom->len += i;
11759
11760 if (len & 3) {
11761 /* read last bytes not ending on 4 byte boundary */
11762 pd = &data[eeprom->len];
11763 b_count = len & 3;
11764 b_offset = offset + len - b_count;
a9dc529d 11765 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 11766 if (ret)
11767 return ret;
b9fc7dc5 11768 memcpy(pd, &val, b_count);
1da177e4
LT		 11769 eeprom->len += b_count;
11770 }
11771 return 0;
11772}
11773
1da177e4
LT		 11774static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11775{
11776 struct tg3 *tp = netdev_priv(dev);
11777 int ret;
b9fc7dc5 11778 u32 offset, len, b_offset, odd_len;
1da177e4 11779 u8 *buf;
a9dc529d 11780 __be32 start, end;
1da177e4 11781
63c3a66f 11782 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 11783 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 11784 return -EINVAL;
11785
11786 offset = eeprom->offset;
11787 len = eeprom->len;
11788
11789 if ((b_offset = (offset & 3))) {
11790 /* adjustments to start on required 4 byte boundary */
a9dc529d 11791 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 11792 if (ret)
11793 return ret;
1da177e4
LT		 11794 len += b_offset;
11795 offset &= ~3;
1c8594b4
MC		 11796 if (len < 4)
11797 len = 4;
1da177e4
LT		 11798 }
11799
11800 odd_len = 0;
1c8594b4 11801 if (len & 3) {
1da177e4
LT		 11802 /* adjustments to end on required 4 byte boundary */
11803 odd_len = 1;
11804 len = (len + 3) & ~3;
a9dc529d 11805 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 11806 if (ret)
11807 return ret;
1da177e4
LT		 11808 }
11809
11810 buf = data;
11811 if (b_offset || odd_len) {
11812 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 11813 if (!buf)
1da177e4
LT		 11814 return -ENOMEM;
11815 if (b_offset)
11816 memcpy(buf, &start, 4);
11817 if (odd_len)
11818 memcpy(buf+len-4, &end, 4);
11819 memcpy(buf + b_offset, data, eeprom->len);
11820 }
11821
11822 ret = tg3_nvram_write_block(tp, offset, len, buf);
11823
11824 if (buf != data)
11825 kfree(buf);
11826
11827 return ret;
11828}
11829
11830static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11831{
b02fd9e3
MC		 11832 struct tg3 *tp = netdev_priv(dev);
11833
63c3a66f 11834 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11835 struct phy_device *phydev;
f07e9af3 11836 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11837 return -EAGAIN;
3f0e3ad7
MC		 11838 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11839 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 11840 }
6aa20a22 11841
1da177e4
LT		 11842 cmd->supported = (SUPPORTED_Autoneg);
11843
f07e9af3 11844 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 11845 cmd->supported |= (SUPPORTED_1000baseT_Half |
11846 SUPPORTED_1000baseT_Full);
11847
f07e9af3 11848 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 11849 cmd->supported |= (SUPPORTED_100baseT_Half |
11850 SUPPORTED_100baseT_Full |
11851 SUPPORTED_10baseT_Half |
11852 SUPPORTED_10baseT_Full |
3bebab59 11853 SUPPORTED_TP);
ef348144
KK		 11854 cmd->port = PORT_TP;
11855 } else {
1da177e4 11856 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 11857 cmd->port = PORT_FIBRE;
11858 }
6aa20a22 11859
1da177e4 11860 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 11861 if (tg3_flag(tp, PAUSE_AUTONEG)) {
11862 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
11863 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11864 cmd->advertising |= ADVERTISED_Pause;
11865 } else {
11866 cmd->advertising |= ADVERTISED_Pause |
11867 ADVERTISED_Asym_Pause;
11868 }
11869 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11870 cmd->advertising |= ADVERTISED_Asym_Pause;
11871 }
11872 }
f4a46d1f 11873 if (netif_running(dev) && tp->link_up) {
70739497 11874 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 11875 cmd->duplex = tp->link_config.active_duplex;
859edb26 11876 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 11877 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11878 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
11879 cmd->eth_tp_mdix = ETH_TP_MDI_X;
11880 else
11881 cmd->eth_tp_mdix = ETH_TP_MDI;
11882 }
64c22182 11883 } else {
e740522e
MC		 11884 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
11885 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 11886 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 11887 }
882e9793 11888 cmd->phy_address = tp->phy_addr;
7e5856bd 11889 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 11890 cmd->autoneg = tp->link_config.autoneg;
11891 cmd->maxtxpkt = 0;
11892 cmd->maxrxpkt = 0;
11893 return 0;
11894}
6aa20a22 11895
1da177e4
LT		 11896static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11897{
11898 struct tg3 *tp = netdev_priv(dev);
25db0338 11899 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 11900
63c3a66f 11901 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 11902 struct phy_device *phydev;
f07e9af3 11903 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 11904 return -EAGAIN;
3f0e3ad7
MC		 11905 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11906 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 11907 }
11908
7e5856bd
MC		 11909 if (cmd->autoneg != AUTONEG_ENABLE &&
11910 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 11911 return -EINVAL;
7e5856bd
MC		 11912
11913 if (cmd->autoneg == AUTONEG_DISABLE &&
11914 cmd->duplex != DUPLEX_FULL &&
11915 cmd->duplex != DUPLEX_HALF)
37ff238d 11916 return -EINVAL;
1da177e4 11917
7e5856bd
MC		 11918 if (cmd->autoneg == AUTONEG_ENABLE) {
11919 u32 mask = ADVERTISED_Autoneg |
11920 ADVERTISED_Pause |
11921 ADVERTISED_Asym_Pause;
11922
f07e9af3 11923 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 11924 mask |= ADVERTISED_1000baseT_Half |
11925 ADVERTISED_1000baseT_Full;
11926
f07e9af3 11927 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 11928 mask |= ADVERTISED_100baseT_Half |
11929 ADVERTISED_100baseT_Full |
11930 ADVERTISED_10baseT_Half |
11931 ADVERTISED_10baseT_Full |
11932 ADVERTISED_TP;
11933 else
11934 mask |= ADVERTISED_FIBRE;
11935
11936 if (cmd->advertising & ~mask)
11937 return -EINVAL;
11938
11939 mask &= (ADVERTISED_1000baseT_Half |
11940 ADVERTISED_1000baseT_Full |
11941 ADVERTISED_100baseT_Half |
11942 ADVERTISED_100baseT_Full |
11943 ADVERTISED_10baseT_Half |
11944 ADVERTISED_10baseT_Full);
11945
11946 cmd->advertising &= mask;
11947 } else {
f07e9af3 11948 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 11949 if (speed != SPEED_1000)
7e5856bd
MC		 11950 return -EINVAL;
11951
11952 if (cmd->duplex != DUPLEX_FULL)
11953 return -EINVAL;
11954 } else {
25db0338
DD		 11955 if (speed != SPEED_100 &&
11956 speed != SPEED_10)
7e5856bd
MC		 11957 return -EINVAL;
11958 }
11959 }
11960
f47c11ee 11961 tg3_full_lock(tp, 0);
1da177e4
LT		 11962
11963 tp->link_config.autoneg = cmd->autoneg;
11964 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 11965 tp->link_config.advertising = (cmd->advertising |
11966 ADVERTISED_Autoneg);
e740522e
MC		 11967 tp->link_config.speed = SPEED_UNKNOWN;
11968 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 11969 } else {
11970 tp->link_config.advertising = 0;
25db0338 11971 tp->link_config.speed = speed;
1da177e4 11972 tp->link_config.duplex = cmd->duplex;
b02fd9e3 11973 }
6aa20a22 11974
fdad8de4
NS		 11975 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
11976
ce20f161
NS		 11977 tg3_warn_mgmt_link_flap(tp);
11978
1da177e4 11979 if (netif_running(dev))
953c96e0 11980 tg3_setup_phy(tp, true);
1da177e4 11981
f47c11ee 11982 tg3_full_unlock(tp);
6aa20a22 11983
1da177e4
LT		 11984 return 0;
11985}
6aa20a22 11986
1da177e4
LT		 11987static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
11988{
11989 struct tg3 *tp = netdev_priv(dev);
6aa20a22 11990
68aad78c
RJ		 11991 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
11992 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
11993 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
11994 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 11995}
6aa20a22 11996
1da177e4
LT		 11997static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
11998{
11999 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12000
63c3a66f 12001 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12002 wol->supported = WAKE_MAGIC;
12003 else
12004 wol->supported = 0;
1da177e4 12005 wol->wolopts = 0;
63c3a66f 12006 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12007 wol->wolopts = WAKE_MAGIC;
12008 memset(&wol->sopass, 0, sizeof(wol->sopass));
12009}
6aa20a22 12010
1da177e4
LT		 12011static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12012{
12013 struct tg3 *tp = netdev_priv(dev);
12dac075 12014 struct device *dp = &tp->pdev->dev;
6aa20a22 12015
1da177e4
LT		 12016 if (wol->wolopts & ~WAKE_MAGIC)
12017 return -EINVAL;
12018 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12019 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12020 return -EINVAL;
6aa20a22 12021
f2dc0d18
RW		 12022 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12023
f47c11ee 12024 spin_lock_bh(&tp->lock);
f2dc0d18 12025 if (device_may_wakeup(dp))
63c3a66f 12026 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12027 else
63c3a66f 12028 tg3_flag_clear(tp, WOL_ENABLE);
f47c11ee 12029 spin_unlock_bh(&tp->lock);
6aa20a22 12030
1da177e4
LT		 12031 return 0;
12032}
6aa20a22 12033
1da177e4
LT		 12034static u32 tg3_get_msglevel(struct net_device *dev)
12035{
12036 struct tg3 *tp = netdev_priv(dev);
12037 return tp->msg_enable;
12038}
6aa20a22 12039
1da177e4
LT		 12040static void tg3_set_msglevel(struct net_device *dev, u32 value)
12041{
12042 struct tg3 *tp = netdev_priv(dev);
12043 tp->msg_enable = value;
12044}
6aa20a22 12045
1da177e4
LT		 12046static int tg3_nway_reset(struct net_device *dev)
12047{
12048 struct tg3 *tp = netdev_priv(dev);
1da177e4 12049 int r;
6aa20a22 12050
1da177e4
LT		 12051 if (!netif_running(dev))
12052 return -EAGAIN;
12053
f07e9af3 12054 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12055 return -EINVAL;
12056
ce20f161
NS		 12057 tg3_warn_mgmt_link_flap(tp);
12058
63c3a66f 12059 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12060 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12061 return -EAGAIN;
3f0e3ad7 12062 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
b02fd9e3
MC		 12063 } else {
12064 u32 bmcr;
12065
12066 spin_lock_bh(&tp->lock);
12067 r = -EINVAL;
12068 tg3_readphy(tp, MII_BMCR, &bmcr);
12069 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12070 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12071 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12072 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12073 BMCR_ANENABLE);
12074 r = 0;
12075 }
12076 spin_unlock_bh(&tp->lock);
1da177e4 12077 }
6aa20a22 12078
1da177e4
LT		 12079 return r;
12080}
6aa20a22 12081
1da177e4
LT		 12082static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12083{
12084 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12085
2c49a44d 12086 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12087 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12088 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12089 else
12090 ering->rx_jumbo_max_pending = 0;
12091
12092 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12093
12094 ering->rx_pending = tp->rx_pending;
63c3a66f 12095 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12096 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12097 else
12098 ering->rx_jumbo_pending = 0;
12099
f3f3f27e 12100 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12101}
6aa20a22 12102
1da177e4
LT		 12103static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12104{
12105 struct tg3 *tp = netdev_priv(dev);
646c9edd 12106 int i, irq_sync = 0, err = 0;
6aa20a22 12107
2c49a44d
MC		 12108 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12109 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12110 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12111 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12112 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12113 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12114 return -EINVAL;
6aa20a22 12115
bbe832c0 12116 if (netif_running(dev)) {
b02fd9e3 12117 tg3_phy_stop(tp);
1da177e4 12118 tg3_netif_stop(tp);
bbe832c0
MC		 12119 irq_sync = 1;
12120 }
1da177e4 12121
bbe832c0 12122 tg3_full_lock(tp, irq_sync);
6aa20a22 12123
1da177e4
LT		 12124 tp->rx_pending = ering->rx_pending;
12125
63c3a66f 12126 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12127 tp->rx_pending > 63)
12128 tp->rx_pending = 63;
12129 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12130
6fd45cb8 12131 for (i = 0; i < tp->irq_max; i++)
646c9edd 12132 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12133
12134 if (netif_running(dev)) {
944d980e 12135 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12136 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12137 if (!err)
12138 tg3_netif_start(tp);
1da177e4
LT		 12139 }
12140
f47c11ee 12141 tg3_full_unlock(tp);
6aa20a22 12142
b02fd9e3
MC		 12143 if (irq_sync && !err)
12144 tg3_phy_start(tp);
12145
b9ec6c1b 12146 return err;
1da177e4 12147}
6aa20a22 12148
1da177e4
LT		 12149static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12150{
12151 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12152
63c3a66f 12153 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12154
4a2db503 12155 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12156 epause->rx_pause = 1;
12157 else
12158 epause->rx_pause = 0;
12159
4a2db503 12160 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12161 epause->tx_pause = 1;
12162 else
12163 epause->tx_pause = 0;
1da177e4 12164}
6aa20a22 12165
1da177e4
LT		 12166static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12167{
12168 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12169 int err = 0;
6aa20a22 12170
ce20f161
NS		 12171 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12172 tg3_warn_mgmt_link_flap(tp);
12173
63c3a66f 12174 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12175 u32 newadv;
12176 struct phy_device *phydev;
1da177e4 12177
2712168f 12178 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
f47c11ee 12179
2712168f
MC		 12180 if (!(phydev->supported & SUPPORTED_Pause) ||
12181 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12182 (epause->rx_pause != epause->tx_pause)))
2712168f 12183 return -EINVAL;
1da177e4 12184
2712168f
MC		 12185 tp->link_config.flowctrl = 0;
12186 if (epause->rx_pause) {
12187 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12188
12189 if (epause->tx_pause) {
12190 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12191 newadv = ADVERTISED_Pause;
b02fd9e3 12192 } else
2712168f
MC		 12193 newadv = ADVERTISED_Pause |
12194 ADVERTISED_Asym_Pause;
12195 } else if (epause->tx_pause) {
12196 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12197 newadv = ADVERTISED_Asym_Pause;
12198 } else
12199 newadv = 0;
12200
12201 if (epause->autoneg)
63c3a66f 12202 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12203 else
63c3a66f 12204 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12205
f07e9af3 12206 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12207 u32 oldadv = phydev->advertising &
12208 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12209 if (oldadv != newadv) {
12210 phydev->advertising &=
12211 ~(ADVERTISED_Pause |
12212 ADVERTISED_Asym_Pause);
12213 phydev->advertising |= newadv;
12214 if (phydev->autoneg) {
12215 /*
12216 * Always renegotiate the link to
12217 * inform our link partner of our
12218 * flow control settings, even if the
12219 * flow control is forced. Let
12220 * tg3_adjust_link() do the final
12221 * flow control setup.
12222 */
12223 return phy_start_aneg(phydev);
b02fd9e3 12224 }
b02fd9e3 12225 }
b02fd9e3 12226
2712168f 12227 if (!epause->autoneg)
b02fd9e3 12228 tg3_setup_flow_control(tp, 0, 0);
2712168f 12229 } else {
c6700ce2 12230 tp->link_config.advertising &=
2712168f
MC		 12231 ~(ADVERTISED_Pause |
12232 ADVERTISED_Asym_Pause);
c6700ce2 12233 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12234 }
12235 } else {
12236 int irq_sync = 0;
12237
12238 if (netif_running(dev)) {
12239 tg3_netif_stop(tp);
12240 irq_sync = 1;
12241 }
12242
12243 tg3_full_lock(tp, irq_sync);
12244
12245 if (epause->autoneg)
63c3a66f 12246 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12247 else
63c3a66f 12248 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12249 if (epause->rx_pause)
e18ce346 12250 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12251 else
e18ce346 12252 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12253 if (epause->tx_pause)
e18ce346 12254 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12255 else
e18ce346 12256 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12257
12258 if (netif_running(dev)) {
12259 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12260 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12261 if (!err)
12262 tg3_netif_start(tp);
12263 }
12264
12265 tg3_full_unlock(tp);
12266 }
6aa20a22 12267
fdad8de4
NS		 12268 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12269
b9ec6c1b 12270 return err;
1da177e4 12271}
6aa20a22 12272
de6f31eb 12273static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12274{
b9f2c044
JG		 12275 switch (sset) {
12276 case ETH_SS_TEST:
12277 return TG3_NUM_TEST;
12278 case ETH_SS_STATS:
12279 return TG3_NUM_STATS;
12280 default:
12281 return -EOPNOTSUPP;
12282 }
4cafd3f5
MC		 12283}
12284
90415477
MC		 12285static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12286 u32 *rules __always_unused)
12287{
12288 struct tg3 *tp = netdev_priv(dev);
12289
12290 if (!tg3_flag(tp, SUPPORT_MSIX))
12291 return -EOPNOTSUPP;
12292
12293 switch (info->cmd) {
12294 case ETHTOOL_GRXRINGS:
12295 if (netif_running(tp->dev))
9102426a 12296 info->data = tp->rxq_cnt;
90415477
MC		 12297 else {
12298 info->data = num_online_cpus();
9102426a
MC		 12299 if (info->data > TG3_RSS_MAX_NUM_QS)
12300 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12301 }
12302
12303 /* The first interrupt vector only
12304 * handles link interrupts.
12305 */
12306 info->data -= 1;
12307 return 0;
12308
12309 default:
12310 return -EOPNOTSUPP;
12311 }
12312}
12313
12314static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12315{
12316 u32 size = 0;
12317 struct tg3 *tp = netdev_priv(dev);
12318
12319 if (tg3_flag(tp, SUPPORT_MSIX))
12320 size = TG3_RSS_INDIR_TBL_SIZE;
12321
12322 return size;
12323}
12324
12325static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12326{
12327 struct tg3 *tp = netdev_priv(dev);
12328 int i;
12329
12330 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12331 indir[i] = tp->rss_ind_tbl[i];
12332
12333 return 0;
12334}
12335
12336static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12337{
12338 struct tg3 *tp = netdev_priv(dev);
12339 size_t i;
12340
12341 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12342 tp->rss_ind_tbl[i] = indir[i];
12343
12344 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12345 return 0;
12346
12347 /* It is legal to write the indirection
12348 * table while the device is running.
12349 */
12350 tg3_full_lock(tp, 0);
12351 tg3_rss_write_indir_tbl(tp);
12352 tg3_full_unlock(tp);
12353
12354 return 0;
12355}
12356
0968169c
MC		 12357static void tg3_get_channels(struct net_device *dev,
12358 struct ethtool_channels *channel)
12359{
12360 struct tg3 *tp = netdev_priv(dev);
12361 u32 deflt_qs = netif_get_num_default_rss_queues();
12362
12363 channel->max_rx = tp->rxq_max;
12364 channel->max_tx = tp->txq_max;
12365
12366 if (netif_running(dev)) {
12367 channel->rx_count = tp->rxq_cnt;
12368 channel->tx_count = tp->txq_cnt;
12369 } else {
12370 if (tp->rxq_req)
12371 channel->rx_count = tp->rxq_req;
12372 else
12373 channel->rx_count = min(deflt_qs, tp->rxq_max);
12374
12375 if (tp->txq_req)
12376 channel->tx_count = tp->txq_req;
12377 else
12378 channel->tx_count = min(deflt_qs, tp->txq_max);
12379 }
12380}
12381
12382static int tg3_set_channels(struct net_device *dev,
12383 struct ethtool_channels *channel)
12384{
12385 struct tg3 *tp = netdev_priv(dev);
12386
12387 if (!tg3_flag(tp, SUPPORT_MSIX))
12388 return -EOPNOTSUPP;
12389
12390 if (channel->rx_count > tp->rxq_max ||
12391 channel->tx_count > tp->txq_max)
12392 return -EINVAL;
12393
12394 tp->rxq_req = channel->rx_count;
12395 tp->txq_req = channel->tx_count;
12396
12397 if (!netif_running(dev))
12398 return 0;
12399
12400 tg3_stop(tp);
12401
f4a46d1f 12402 tg3_carrier_off(tp);
0968169c 12403
be947307 12404 tg3_start(tp, true, false, false);
0968169c
MC		 12405
12406 return 0;
12407}
12408
de6f31eb 12409static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12410{
12411 switch (stringset) {
12412 case ETH_SS_STATS:
12413 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12414 break;
4cafd3f5
MC		 12415 case ETH_SS_TEST:
12416 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12417 break;
1da177e4
LT		 12418 default:
12419 WARN_ON(1); /* we need a WARN() */
12420 break;
12421 }
12422}
12423
81b8709c 12424static int tg3_set_phys_id(struct net_device *dev,
12425 enum ethtool_phys_id_state state)
4009a93d
MC		 12426{
12427 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12428
12429 if (!netif_running(tp->dev))
12430 return -EAGAIN;
12431
81b8709c 12432 switch (state) {
12433 case ETHTOOL_ID_ACTIVE:
fce55922 12434 return 1; /* cycle on/off once per second */
4009a93d 12435
81b8709c 12436 case ETHTOOL_ID_ON:
12437 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12438 LED_CTRL_1000MBPS_ON |
12439 LED_CTRL_100MBPS_ON |
12440 LED_CTRL_10MBPS_ON |
12441 LED_CTRL_TRAFFIC_OVERRIDE |
12442 LED_CTRL_TRAFFIC_BLINK |
12443 LED_CTRL_TRAFFIC_LED);
12444 break;
6aa20a22 12445
81b8709c 12446 case ETHTOOL_ID_OFF:
12447 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12448 LED_CTRL_TRAFFIC_OVERRIDE);
12449 break;
4009a93d 12450
81b8709c 12451 case ETHTOOL_ID_INACTIVE:
12452 tw32(MAC_LED_CTRL, tp->led_ctrl);
12453 break;
4009a93d 12454 }
81b8709c 12455
4009a93d
MC		 12456 return 0;
12457}
12458
de6f31eb 12459static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12460 struct ethtool_stats *estats, u64 *tmp_stats)
12461{
12462 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12463
b546e46f
MC		 12464 if (tp->hw_stats)
12465 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12466 else
12467 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12468}
12469
535a490e 12470static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12471{
12472 int i;
12473 __be32 *buf;
12474 u32 offset = 0, len = 0;
12475 u32 magic, val;
12476
63c3a66f 12477 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12478 return NULL;
12479
12480 if (magic == TG3_EEPROM_MAGIC) {
12481 for (offset = TG3_NVM_DIR_START;
12482 offset < TG3_NVM_DIR_END;
12483 offset += TG3_NVM_DIRENT_SIZE) {
12484 if (tg3_nvram_read(tp, offset, &val))
12485 return NULL;
12486
12487 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12488 TG3_NVM_DIRTYPE_EXTVPD)
12489 break;
12490 }
12491
12492 if (offset != TG3_NVM_DIR_END) {
12493 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12494 if (tg3_nvram_read(tp, offset + 4, &offset))
12495 return NULL;
12496
12497 offset = tg3_nvram_logical_addr(tp, offset);
12498 }
12499 }
12500
12501 if (!offset || !len) {
12502 offset = TG3_NVM_VPD_OFF;
12503 len = TG3_NVM_VPD_LEN;
12504 }
12505
12506 buf = kmalloc(len, GFP_KERNEL);
12507 if (buf == NULL)
12508 return NULL;
12509
12510 if (magic == TG3_EEPROM_MAGIC) {
12511 for (i = 0; i < len; i += 4) {
12512 /* The data is in little-endian format in NVRAM.
12513 * Use the big-endian read routines to preserve
12514 * the byte order as it exists in NVRAM.
12515 */
12516 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12517 goto error;
12518 }
12519 } else {
12520 u8 *ptr;
12521 ssize_t cnt;
12522 unsigned int pos = 0;
12523
12524 ptr = (u8 *)&buf[0];
12525 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12526 cnt = pci_read_vpd(tp->pdev, pos,
12527 len - pos, ptr);
12528 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12529 cnt = 0;
12530 else if (cnt < 0)
12531 goto error;
12532 }
12533 if (pos != len)
12534 goto error;
12535 }
12536
535a490e
MC		 12537 *vpdlen = len;
12538
c3e94500
MC		 12539 return buf;
12540
12541error:
12542 kfree(buf);
12543 return NULL;
12544}
12545
566f86ad 12546#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12547#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12548#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12549#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12550#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12551#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12552#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12553#define NVRAM_SELFBOOT_HW_SIZE 0x20
12554#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12555
12556static int tg3_test_nvram(struct tg3 *tp)
12557{
535a490e 12558 u32 csum, magic, len;
a9dc529d 12559 __be32 *buf;
ab0049b4 12560 int i, j, k, err = 0, size;
566f86ad 12561
63c3a66f 12562 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12563 return 0;
12564
e4f34110 12565 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12566 return -EIO;
12567
1b27777a
MC		 12568 if (magic == TG3_EEPROM_MAGIC)
12569 size = NVRAM_TEST_SIZE;
b16250e3 12570 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12571 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12572 TG3_EEPROM_SB_FORMAT_1) {
12573 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12574 case TG3_EEPROM_SB_REVISION_0:
12575 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12576 break;
12577 case TG3_EEPROM_SB_REVISION_2:
12578 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12579 break;
12580 case TG3_EEPROM_SB_REVISION_3:
12581 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12582 break;
727a6d9f
MC		 12583 case TG3_EEPROM_SB_REVISION_4:
12584 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12585 break;
12586 case TG3_EEPROM_SB_REVISION_5:
12587 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12588 break;
12589 case TG3_EEPROM_SB_REVISION_6:
12590 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12591 break;
a5767dec 12592 default:
727a6d9f 12593 return -EIO;
a5767dec
MC		 12594 }
12595 } else
1b27777a 12596 return 0;
b16250e3
MC		 12597 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12598 size = NVRAM_SELFBOOT_HW_SIZE;
12599 else
1b27777a
MC		 12600 return -EIO;
12601
12602 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12603 if (buf == NULL)
12604 return -ENOMEM;
12605
1b27777a
MC		 12606 err = -EIO;
12607 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12608 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12609 if (err)
566f86ad 12610 break;
566f86ad 12611 }
1b27777a 12612 if (i < size)
566f86ad
MC		 12613 goto out;
12614
1b27777a 12615 /* Selfboot format */
a9dc529d 12616 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12617 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12618 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12619 u8 *buf8 = (u8 *) buf, csum8 = 0;
12620
b9fc7dc5 12621 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12622 TG3_EEPROM_SB_REVISION_2) {
12623 /* For rev 2, the csum doesn't include the MBA. */
12624 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12625 csum8 += buf8[i];
12626 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12627 csum8 += buf8[i];
12628 } else {
12629 for (i = 0; i < size; i++)
12630 csum8 += buf8[i];
12631 }
1b27777a 12632
ad96b485
AB		 12633 if (csum8 == 0) {
12634 err = 0;
12635 goto out;
12636 }
12637
12638 err = -EIO;
12639 goto out;
1b27777a 12640 }
566f86ad 12641
b9fc7dc5 12642 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12643 TG3_EEPROM_MAGIC_HW) {
12644 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12645 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12646 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12647
12648 /* Separate the parity bits and the data bytes. */
12649 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12650 if ((i == 0) || (i == 8)) {
12651 int l;
12652 u8 msk;
12653
12654 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12655 parity[k++] = buf8[i] & msk;
12656 i++;
859a5887 12657 } else if (i == 16) {
b16250e3
MC		 12658 int l;
12659 u8 msk;
12660
12661 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12662 parity[k++] = buf8[i] & msk;
12663 i++;
12664
12665 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12666 parity[k++] = buf8[i] & msk;
12667 i++;
12668 }
12669 data[j++] = buf8[i];
12670 }
12671
12672 err = -EIO;
12673 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12674 u8 hw8 = hweight8(data[i]);
12675
12676 if ((hw8 & 0x1) && parity[i])
12677 goto out;
12678 else if (!(hw8 & 0x1) && !parity[i])
12679 goto out;
12680 }
12681 err = 0;
12682 goto out;
12683 }
12684
01c3a392
MC		 12685 err = -EIO;
12686
566f86ad
MC		 12687 /* Bootstrap checksum at offset 0x10 */
12688 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12689 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12690 goto out;
12691
12692 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12693 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12694 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12695 goto out;
566f86ad 12696
c3e94500
MC		 12697 kfree(buf);
12698
535a490e 12699 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12700 if (!buf)
12701 return -ENOMEM;
d4894f3e 12702
535a490e 12703 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12704 if (i > 0) {
12705 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12706 if (j < 0)
12707 goto out;
12708
535a490e 12709 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12710 goto out;
12711
12712 i += PCI_VPD_LRDT_TAG_SIZE;
12713 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12714 PCI_VPD_RO_KEYWORD_CHKSUM);
12715 if (j > 0) {
12716 u8 csum8 = 0;
12717
12718 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12719
12720 for (i = 0; i <= j; i++)
12721 csum8 += ((u8 *)buf)[i];
12722
12723 if (csum8)
12724 goto out;
12725 }
12726 }
12727
566f86ad
MC		 12728 err = 0;
12729
12730out:
12731 kfree(buf);
12732 return err;
12733}
12734
ca43007a
MC		 12735#define TG3_SERDES_TIMEOUT_SEC 2
12736#define TG3_COPPER_TIMEOUT_SEC 6
12737
12738static int tg3_test_link(struct tg3 *tp)
12739{
12740 int i, max;
12741
12742 if (!netif_running(tp->dev))
12743 return -ENODEV;
12744
f07e9af3 12745 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12746 max = TG3_SERDES_TIMEOUT_SEC;
12747 else
12748 max = TG3_COPPER_TIMEOUT_SEC;
12749
12750 for (i = 0; i < max; i++) {
f4a46d1f 12751 if (tp->link_up)
ca43007a
MC		 12752 return 0;
12753
12754 if (msleep_interruptible(1000))
12755 break;
12756 }
12757
12758 return -EIO;
12759}
12760
a71116d1 12761/* Only test the commonly used registers */
30ca3e37 12762static int tg3_test_registers(struct tg3 *tp)
a71116d1 12763{
b16250e3 12764 int i, is_5705, is_5750;
a71116d1
MC		 12765 u32 offset, read_mask, write_mask, val, save_val, read_val;
12766 static struct {
12767 u16 offset;
12768 u16 flags;
12769#define TG3_FL_5705 0x1
12770#define TG3_FL_NOT_5705 0x2
12771#define TG3_FL_NOT_5788 0x4
b16250e3 12772#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 12773 u32 read_mask;
12774 u32 write_mask;
12775 } reg_tbl[] = {
12776 /* MAC Control Registers */
12777 { MAC_MODE, TG3_FL_NOT_5705,
12778 0x00000000, 0x00ef6f8c },
12779 { MAC_MODE, TG3_FL_5705,
12780 0x00000000, 0x01ef6b8c },
12781 { MAC_STATUS, TG3_FL_NOT_5705,
12782 0x03800107, 0x00000000 },
12783 { MAC_STATUS, TG3_FL_5705,
12784 0x03800100, 0x00000000 },
12785 { MAC_ADDR_0_HIGH, 0x0000,
12786 0x00000000, 0x0000ffff },
12787 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 12788 0x00000000, 0xffffffff },
a71116d1
MC		 12789 { MAC_RX_MTU_SIZE, 0x0000,
12790 0x00000000, 0x0000ffff },
12791 { MAC_TX_MODE, 0x0000,
12792 0x00000000, 0x00000070 },
12793 { MAC_TX_LENGTHS, 0x0000,
12794 0x00000000, 0x00003fff },
12795 { MAC_RX_MODE, TG3_FL_NOT_5705,
12796 0x00000000, 0x000007fc },
12797 { MAC_RX_MODE, TG3_FL_5705,
12798 0x00000000, 0x000007dc },
12799 { MAC_HASH_REG_0, 0x0000,
12800 0x00000000, 0xffffffff },
12801 { MAC_HASH_REG_1, 0x0000,
12802 0x00000000, 0xffffffff },
12803 { MAC_HASH_REG_2, 0x0000,
12804 0x00000000, 0xffffffff },
12805 { MAC_HASH_REG_3, 0x0000,
12806 0x00000000, 0xffffffff },
12807
12808 /* Receive Data and Receive BD Initiator Control Registers. */
12809 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12810 0x00000000, 0xffffffff },
12811 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12812 0x00000000, 0xffffffff },
12813 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12814 0x00000000, 0x00000003 },
12815 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12816 0x00000000, 0xffffffff },
12817 { RCVDBDI_STD_BD+0, 0x0000,
12818 0x00000000, 0xffffffff },
12819 { RCVDBDI_STD_BD+4, 0x0000,
12820 0x00000000, 0xffffffff },
12821 { RCVDBDI_STD_BD+8, 0x0000,
12822 0x00000000, 0xffff0002 },
12823 { RCVDBDI_STD_BD+0xc, 0x0000,
12824 0x00000000, 0xffffffff },
6aa20a22 12825
a71116d1
MC		 12826 /* Receive BD Initiator Control Registers. */
12827 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12828 0x00000000, 0xffffffff },
12829 { RCVBDI_STD_THRESH, TG3_FL_5705,
12830 0x00000000, 0x000003ff },
12831 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12832 0x00000000, 0xffffffff },
6aa20a22 12833
a71116d1
MC		 12834 /* Host Coalescing Control Registers. */
12835 { HOSTCC_MODE, TG3_FL_NOT_5705,
12836 0x00000000, 0x00000004 },
12837 { HOSTCC_MODE, TG3_FL_5705,
12838 0x00000000, 0x000000f6 },
12839 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
12840 0x00000000, 0xffffffff },
12841 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
12842 0x00000000, 0x000003ff },
12843 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
12844 0x00000000, 0xffffffff },
12845 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
12846 0x00000000, 0x000003ff },
12847 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
12848 0x00000000, 0xffffffff },
12849 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12850 0x00000000, 0x000000ff },
12851 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
12852 0x00000000, 0xffffffff },
12853 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12854 0x00000000, 0x000000ff },
12855 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
12856 0x00000000, 0xffffffff },
12857 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
12858 0x00000000, 0xffffffff },
12859 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12860 0x00000000, 0xffffffff },
12861 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12862 0x00000000, 0x000000ff },
12863 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12864 0x00000000, 0xffffffff },
12865 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12866 0x00000000, 0x000000ff },
12867 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
12868 0x00000000, 0xffffffff },
12869 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
12870 0x00000000, 0xffffffff },
12871 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
12872 0x00000000, 0xffffffff },
12873 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
12874 0x00000000, 0xffffffff },
12875 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
12876 0x00000000, 0xffffffff },
12877 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
12878 0xffffffff, 0x00000000 },
12879 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
12880 0xffffffff, 0x00000000 },
12881
12882 /* Buffer Manager Control Registers. */
b16250e3 12883 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 12884 0x00000000, 0x007fff80 },
b16250e3 12885 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 12886 0x00000000, 0x007fffff },
12887 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
12888 0x00000000, 0x0000003f },
12889 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
12890 0x00000000, 0x000001ff },
12891 { BUFMGR_MB_HIGH_WATER, 0x0000,
12892 0x00000000, 0x000001ff },
12893 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
12894 0xffffffff, 0x00000000 },
12895 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
12896 0xffffffff, 0x00000000 },
6aa20a22 12897
a71116d1
MC		 12898 /* Mailbox Registers */
12899 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
12900 0x00000000, 0x000001ff },
12901 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
12902 0x00000000, 0x000001ff },
12903 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
12904 0x00000000, 0x000007ff },
12905 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
12906 0x00000000, 0x000001ff },
12907
12908 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
12909 };
12910
b16250e3 12911 is_5705 = is_5750 = 0;
63c3a66f 12912 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 12913 is_5705 = 1;
63c3a66f 12914 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 12915 is_5750 = 1;
12916 }
a71116d1
MC		 12917
12918 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
12919 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
12920 continue;
12921
12922 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
12923 continue;
12924
63c3a66f 12925 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 12926 (reg_tbl[i].flags & TG3_FL_NOT_5788))
12927 continue;
12928
b16250e3
MC		 12929 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
12930 continue;
12931
a71116d1
MC		 12932 offset = (u32) reg_tbl[i].offset;
12933 read_mask = reg_tbl[i].read_mask;
12934 write_mask = reg_tbl[i].write_mask;
12935
12936 /* Save the original register content */
12937 save_val = tr32(offset);
12938
12939 /* Determine the read-only value. */
12940 read_val = save_val & read_mask;
12941
12942 /* Write zero to the register, then make sure the read-only bits
12943 * are not changed and the read/write bits are all zeros.
12944 */
12945 tw32(offset, 0);
12946
12947 val = tr32(offset);
12948
12949 /* Test the read-only and read/write bits. */
12950 if (((val & read_mask) != read_val) || (val & write_mask))
12951 goto out;
12952
12953 /* Write ones to all the bits defined by RdMask and WrMask, then
12954 * make sure the read-only bits are not changed and the
12955 * read/write bits are all ones.
12956 */
12957 tw32(offset, read_mask | write_mask);
12958
12959 val = tr32(offset);
12960
12961 /* Test the read-only bits. */
12962 if ((val & read_mask) != read_val)
12963 goto out;
12964
12965 /* Test the read/write bits. */
12966 if ((val & write_mask) != write_mask)
12967 goto out;
12968
12969 tw32(offset, save_val);
12970 }
12971
12972 return 0;
12973
12974out:
9f88f29f 12975 if (netif_msg_hw(tp))
2445e461
MC		 12976 netdev_err(tp->dev,
12977 "Register test failed at offset %x\n", offset);
a71116d1
MC		 12978 tw32(offset, save_val);
12979 return -EIO;
12980}
12981
7942e1db
MC		 12982static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
12983{
f71e1309 12984 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 12985 int i;
12986 u32 j;
12987
e9edda69 12988 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 12989 for (j = 0; j < len; j += 4) {
12990 u32 val;
12991
12992 tg3_write_mem(tp, offset + j, test_pattern[i]);
12993 tg3_read_mem(tp, offset + j, &val);
12994 if (val != test_pattern[i])
12995 return -EIO;
12996 }
12997 }
12998 return 0;
12999}
13000
13001static int tg3_test_memory(struct tg3 *tp)
13002{
13003 static struct mem_entry {
13004 u32 offset;
13005 u32 len;
13006 } mem_tbl_570x[] = {
38690194 13007 { 0x00000000, 0x00b50},
7942e1db
MC		 13008 { 0x00002000, 0x1c000},
13009 { 0xffffffff, 0x00000}
13010 }, mem_tbl_5705[] = {
13011 { 0x00000100, 0x0000c},
13012 { 0x00000200, 0x00008},
7942e1db
MC		 13013 { 0x00004000, 0x00800},
13014 { 0x00006000, 0x01000},
13015 { 0x00008000, 0x02000},
13016 { 0x00010000, 0x0e000},
13017 { 0xffffffff, 0x00000}
79f4d13a
MC		 13018 }, mem_tbl_5755[] = {
13019 { 0x00000200, 0x00008},
13020 { 0x00004000, 0x00800},
13021 { 0x00006000, 0x00800},
13022 { 0x00008000, 0x02000},
13023 { 0x00010000, 0x0c000},
13024 { 0xffffffff, 0x00000}
b16250e3
MC		 13025 }, mem_tbl_5906[] = {
13026 { 0x00000200, 0x00008},
13027 { 0x00004000, 0x00400},
13028 { 0x00006000, 0x00400},
13029 { 0x00008000, 0x01000},
13030 { 0x00010000, 0x01000},
13031 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13032 }, mem_tbl_5717[] = {
13033 { 0x00000200, 0x00008},
13034 { 0x00010000, 0x0a000},
13035 { 0x00020000, 0x13c00},
13036 { 0xffffffff, 0x00000}
13037 }, mem_tbl_57765[] = {
13038 { 0x00000200, 0x00008},
13039 { 0x00004000, 0x00800},
13040 { 0x00006000, 0x09800},
13041 { 0x00010000, 0x0a000},
13042 { 0xffffffff, 0x00000}
7942e1db
MC		 13043 };
13044 struct mem_entry *mem_tbl;
13045 int err = 0;
13046 int i;
13047
63c3a66f 13048 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13049 mem_tbl = mem_tbl_5717;
c65a17f4 13050 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13051 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13052 mem_tbl = mem_tbl_57765;
63c3a66f 13053 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13054 mem_tbl = mem_tbl_5755;
4153577a 13055 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13056 mem_tbl = mem_tbl_5906;
63c3a66f 13057 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13058 mem_tbl = mem_tbl_5705;
13059 else
7942e1db
MC		 13060 mem_tbl = mem_tbl_570x;
13061
13062 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13063 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13064 if (err)
7942e1db
MC		 13065 break;
13066 }
6aa20a22 13067
7942e1db
MC		 13068 return err;
13069}
13070
bb158d69
MC		 13071#define TG3_TSO_MSS 500
13072
13073#define TG3_TSO_IP_HDR_LEN 20
13074#define TG3_TSO_TCP_HDR_LEN 20
13075#define TG3_TSO_TCP_OPT_LEN 12
13076
13077static const u8 tg3_tso_header[] = {
130780x08, 0x00,
130790x45, 0x00, 0x00, 0x00,
130800x00, 0x00, 0x40, 0x00,
130810x40, 0x06, 0x00, 0x00,
130820x0a, 0x00, 0x00, 0x01,
130830x0a, 0x00, 0x00, 0x02,
130840x0d, 0x00, 0xe0, 0x00,
130850x00, 0x00, 0x01, 0x00,
130860x00, 0x00, 0x02, 0x00,
130870x80, 0x10, 0x10, 0x00,
130880x14, 0x09, 0x00, 0x00,
130890x01, 0x01, 0x08, 0x0a,
130900x11, 0x11, 0x11, 0x11,
130910x11, 0x11, 0x11, 0x11,
13092};
9f40dead 13093
28a45957 13094static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13095{
5e5a7f37 13096 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13097 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13098 u32 budget;
9205fd9c
ED		 13099 struct sk_buff *skb;
13100 u8 *tx_data, *rx_data;
c76949a6
MC		 13101 dma_addr_t map;
13102 int num_pkts, tx_len, rx_len, i, err;
13103 struct tg3_rx_buffer_desc *desc;
898a56f8 13104 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13105 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13106
c8873405
MC		 13107 tnapi = &tp->napi[0];
13108 rnapi = &tp->napi[0];
0c1d0e2b 13109 if (tp->irq_cnt > 1) {
63c3a66f 13110 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13111 rnapi = &tp->napi[1];
63c3a66f 13112 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13113 tnapi = &tp->napi[1];
0c1d0e2b 13114 }
fd2ce37f 13115 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13116
c76949a6
MC		 13117 err = -EIO;
13118
4852a861 13119 tx_len = pktsz;
a20e9c62 13120 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13121 if (!skb)
13122 return -ENOMEM;
13123
c76949a6
MC		 13124 tx_data = skb_put(skb, tx_len);
13125 memcpy(tx_data, tp->dev->dev_addr, 6);
13126 memset(tx_data + 6, 0x0, 8);
13127
4852a861 13128 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13129
28a45957 13130 if (tso_loopback) {
bb158d69
MC		 13131 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13132
13133 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13134 TG3_TSO_TCP_OPT_LEN;
13135
13136 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13137 sizeof(tg3_tso_header));
13138 mss = TG3_TSO_MSS;
13139
13140 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13141 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13142
13143 /* Set the total length field in the IP header */
13144 iph->tot_len = htons((u16)(mss + hdr_len));
13145
13146 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13147 TXD_FLAG_CPU_POST_DMA);
13148
63c3a66f
JP		 13149 if (tg3_flag(tp, HW_TSO_1) ||
13150 tg3_flag(tp, HW_TSO_2) ||
13151 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13152 struct tcphdr *th;
13153 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13154 th = (struct tcphdr *)&tx_data[val];
13155 th->check = 0;
13156 } else
13157 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13158
63c3a66f 13159 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13160 mss |= (hdr_len & 0xc) << 12;
13161 if (hdr_len & 0x10)
13162 base_flags |= 0x00000010;
13163 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13164 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13165 mss |= hdr_len << 9;
63c3a66f 13166 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13167 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13168 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13169 } else {
13170 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13171 }
13172
13173 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13174 } else {
13175 num_pkts = 1;
13176 data_off = ETH_HLEN;
c441b456
MC		 13177
13178 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13179 tx_len > VLAN_ETH_FRAME_LEN)
13180 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13181 }
13182
13183 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13184 tx_data[i] = (u8) (i & 0xff);
13185
f4188d8a
AD		 13186 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13187 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13188 dev_kfree_skb(skb);
13189 return -EIO;
13190 }
c76949a6 13191
0d681b27
MC		 13192 val = tnapi->tx_prod;
13193 tnapi->tx_buffers[val].skb = skb;
13194 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13195
c76949a6 13196 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13197 rnapi->coal_now);
c76949a6
MC		 13198
13199 udelay(10);
13200
898a56f8 13201 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13202
84b67b27
MC		 13203 budget = tg3_tx_avail(tnapi);
13204 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13205 base_flags | TXD_FLAG_END, mss, 0)) {
13206 tnapi->tx_buffers[val].skb = NULL;
13207 dev_kfree_skb(skb);
13208 return -EIO;
13209 }
c76949a6 13210
f3f3f27e 13211 tnapi->tx_prod++;
c76949a6 13212
6541b806
MC		 13213 /* Sync BD data before updating mailbox */
13214 wmb();
13215
f3f3f27e
MC		 13216 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13217 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13218
13219 udelay(10);
13220
303fc921
MC		 13221 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13222 for (i = 0; i < 35; i++) {
c76949a6 13223 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13224 coal_now);
c76949a6
MC		 13225
13226 udelay(10);
13227
898a56f8
MC		 13228 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13229 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13230 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13231 (rx_idx == (rx_start_idx + num_pkts)))
13232 break;
13233 }
13234
ba1142e4 13235 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13236 dev_kfree_skb(skb);
13237
f3f3f27e 13238 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13239 goto out;
13240
13241 if (rx_idx != rx_start_idx + num_pkts)
13242 goto out;
13243
bb158d69
MC		 13244 val = data_off;
13245 while (rx_idx != rx_start_idx) {
13246 desc = &rnapi->rx_rcb[rx_start_idx++];
13247 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13248 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13249
bb158d69
MC		 13250 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13251 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13252 goto out;
c76949a6 13253
bb158d69
MC		 13254 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13255 - ETH_FCS_LEN;
c76949a6 13256
28a45957 13257 if (!tso_loopback) {
bb158d69
MC		 13258 if (rx_len != tx_len)
13259 goto out;
4852a861 13260
bb158d69
MC		 13261 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13262 if (opaque_key != RXD_OPAQUE_RING_STD)
13263 goto out;
13264 } else {
13265 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13266 goto out;
13267 }
13268 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13269 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13270 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13271 goto out;
bb158d69 13272 }
4852a861 13273
bb158d69 13274 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13275 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13276 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13277 mapping);
13278 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13279 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13280 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13281 mapping);
13282 } else
13283 goto out;
c76949a6 13284
bb158d69
MC		 13285 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13286 PCI_DMA_FROMDEVICE);
c76949a6 13287
9205fd9c 13288 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13289 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13290 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13291 goto out;
13292 }
c76949a6 13293 }
bb158d69 13294
c76949a6 13295 err = 0;
6aa20a22 13296
9205fd9c 13297 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13298out:
13299 return err;
13300}
13301
00c266b7
MC		 13302#define TG3_STD_LOOPBACK_FAILED 1
13303#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13304#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13305#define TG3_LOOPBACK_FAILED \
13306 (TG3_STD_LOOPBACK_FAILED | \
13307 TG3_JMB_LOOPBACK_FAILED | \
13308 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13309
941ec90f 13310static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13311{
28a45957 13312 int err = -EIO;
2215e24c 13313 u32 eee_cap;
c441b456
MC		 13314 u32 jmb_pkt_sz = 9000;
13315
13316 if (tp->dma_limit)
13317 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13318
ab789046
MC		 13319 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13320 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13321
28a45957 13322 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13323 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13324 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13325 if (do_extlpbk)
93df8b8f 13326 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13327 goto done;
13328 }
13329
953c96e0 13330 err = tg3_reset_hw(tp, true);
ab789046 13331 if (err) {
93df8b8f
NNS		 13332 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13333 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13334 if (do_extlpbk)
93df8b8f 13335 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13336 goto done;
13337 }
9f40dead 13338
63c3a66f 13339 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13340 int i;
13341
13342 /* Reroute all rx packets to the 1st queue */
13343 for (i = MAC_RSS_INDIR_TBL_0;
13344 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13345 tw32(i, 0x0);
13346 }
13347
6e01b20b
MC		 13348 /* HW errata - mac loopback fails in some cases on 5780.
13349 * Normal traffic and PHY loopback are not affected by
13350 * errata. Also, the MAC loopback test is deprecated for
13351 * all newer ASIC revisions.
13352 */
4153577a 13353 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13354 !tg3_flag(tp, CPMU_PRESENT)) {
13355 tg3_mac_loopback(tp, true);
9936bcf6 13356
28a45957 13357 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13358 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13359
13360 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13361 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13362 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13363
13364 tg3_mac_loopback(tp, false);
13365 }
4852a861 13366
f07e9af3 13367 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13368 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13369 int i;
13370
941ec90f 13371 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13372
13373 /* Wait for link */
13374 for (i = 0; i < 100; i++) {
13375 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13376 break;
13377 mdelay(1);
13378 }
13379
28a45957 13380 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13381 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13382 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13383 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13384 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13385 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13386 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13387 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13388
941ec90f
MC		 13389 if (do_extlpbk) {
13390 tg3_phy_lpbk_set(tp, 0, true);
13391
13392 /* All link indications report up, but the hardware
13393 * isn't really ready for about 20 msec. Double it
13394 * to be sure.
13395 */
13396 mdelay(40);
13397
13398 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13399 data[TG3_EXT_LOOPB_TEST] |=
13400 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13401 if (tg3_flag(tp, TSO_CAPABLE) &&
13402 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13403 data[TG3_EXT_LOOPB_TEST] |=
13404 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13405 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13406 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13407 data[TG3_EXT_LOOPB_TEST] |=
13408 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13409 }
13410
5e5a7f37
MC		 13411 /* Re-enable gphy autopowerdown. */
13412 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13413 tg3_phy_toggle_apd(tp, true);
13414 }
6833c043 13415
93df8b8f
NNS		 13416 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13417 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13418
ab789046
MC		 13419done:
13420 tp->phy_flags |= eee_cap;
13421
9f40dead
MC		 13422 return err;
13423}
13424
4cafd3f5
MC		 13425static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13426 u64 *data)
13427{
566f86ad 13428 struct tg3 *tp = netdev_priv(dev);
941ec90f 13429 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13430
2e460fc0
NS		 13431 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13432 if (tg3_power_up(tp)) {
13433 etest->flags |= ETH_TEST_FL_FAILED;
13434 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13435 return;
13436 }
13437 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13438 }
bc1c7567 13439
566f86ad
MC		 13440 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13441
13442 if (tg3_test_nvram(tp) != 0) {
13443 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13444 data[TG3_NVRAM_TEST] = 1;
566f86ad 13445 }
941ec90f 13446 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13447 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13448 data[TG3_LINK_TEST] = 1;
ca43007a 13449 }
a71116d1 13450 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13451 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13452
13453 if (netif_running(dev)) {
b02fd9e3 13454 tg3_phy_stop(tp);
a71116d1 13455 tg3_netif_stop(tp);
bbe832c0
MC		 13456 irq_sync = 1;
13457 }
a71116d1 13458
bbe832c0 13459 tg3_full_lock(tp, irq_sync);
a71116d1 13460 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13461 err = tg3_nvram_lock(tp);
a71116d1 13462 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13463 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13464 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13465 if (!err)
13466 tg3_nvram_unlock(tp);
a71116d1 13467
f07e9af3 13468 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13469 tg3_phy_reset(tp);
13470
a71116d1
MC		 13471 if (tg3_test_registers(tp) != 0) {
13472 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13473 data[TG3_REGISTER_TEST] = 1;
a71116d1 13474 }
28a45957 13475
7942e1db
MC		 13476 if (tg3_test_memory(tp) != 0) {
13477 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13478 data[TG3_MEMORY_TEST] = 1;
7942e1db 13479 }
28a45957 13480
941ec90f
MC		 13481 if (doextlpbk)
13482 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13483
93df8b8f 13484 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13485 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13486
f47c11ee
DM		 13487 tg3_full_unlock(tp);
13488
d4bc3927
MC		 13489 if (tg3_test_interrupt(tp) != 0) {
13490 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13491 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13492 }
f47c11ee
DM		 13493
13494 tg3_full_lock(tp, 0);
d4bc3927 13495
a71116d1
MC		 13496 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13497 if (netif_running(dev)) {
63c3a66f 13498 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13499 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13500 if (!err2)
b9ec6c1b 13501 tg3_netif_start(tp);
a71116d1 13502 }
f47c11ee
DM		 13503
13504 tg3_full_unlock(tp);
b02fd9e3
MC		 13505
13506 if (irq_sync && !err2)
13507 tg3_phy_start(tp);
a71116d1 13508 }
80096068 13509 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13510 tg3_power_down_prepare(tp);
bc1c7567 13511
4cafd3f5
MC		 13512}
13513
0a633ac2
MC		 13514static int tg3_hwtstamp_ioctl(struct net_device *dev,
13515 struct ifreq *ifr, int cmd)
13516{
13517 struct tg3 *tp = netdev_priv(dev);
13518 struct hwtstamp_config stmpconf;
13519
13520 if (!tg3_flag(tp, PTP_CAPABLE))
13521 return -EINVAL;
13522
13523 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13524 return -EFAULT;
13525
13526 if (stmpconf.flags)
13527 return -EINVAL;
13528
13529 switch (stmpconf.tx_type) {
13530 case HWTSTAMP_TX_ON:
13531 tg3_flag_set(tp, TX_TSTAMP_EN);
13532 break;
13533 case HWTSTAMP_TX_OFF:
13534 tg3_flag_clear(tp, TX_TSTAMP_EN);
13535 break;
13536 default:
13537 return -ERANGE;
13538 }
13539
13540 switch (stmpconf.rx_filter) {
13541 case HWTSTAMP_FILTER_NONE:
13542 tp->rxptpctl = 0;
13543 break;
13544 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13545 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13546 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13547 break;
13548 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13549 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13550 TG3_RX_PTP_CTL_SYNC_EVNT;
13551 break;
13552 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13553 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13554 TG3_RX_PTP_CTL_DELAY_REQ;
13555 break;
13556 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13557 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13558 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13559 break;
13560 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13561 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13562 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13563 break;
13564 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13565 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13566 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13567 break;
13568 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13569 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13570 TG3_RX_PTP_CTL_SYNC_EVNT;
13571 break;
13572 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13573 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13574 TG3_RX_PTP_CTL_SYNC_EVNT;
13575 break;
13576 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13577 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13578 TG3_RX_PTP_CTL_SYNC_EVNT;
13579 break;
13580 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13581 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13582 TG3_RX_PTP_CTL_DELAY_REQ;
13583 break;
13584 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13585 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13586 TG3_RX_PTP_CTL_DELAY_REQ;
13587 break;
13588 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13589 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13590 TG3_RX_PTP_CTL_DELAY_REQ;
13591 break;
13592 default:
13593 return -ERANGE;
13594 }
13595
13596 if (netif_running(dev) && tp->rxptpctl)
13597 tw32(TG3_RX_PTP_CTL,
13598 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13599
13600 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13601 -EFAULT : 0;
13602}
13603
1da177e4
LT		 13604static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13605{
13606 struct mii_ioctl_data *data = if_mii(ifr);
13607 struct tg3 *tp = netdev_priv(dev);
13608 int err;
13609
63c3a66f 13610 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13611 struct phy_device *phydev;
f07e9af3 13612 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13613 return -EAGAIN;
3f0e3ad7 13614 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
28b04113 13615 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13616 }
13617
33f401ae 13618 switch (cmd) {
1da177e4 13619 case SIOCGMIIPHY:
882e9793 13620 data->phy_id = tp->phy_addr;
1da177e4
LT		 13621
13622 /* fallthru */
13623 case SIOCGMIIREG: {
13624 u32 mii_regval;
13625
f07e9af3 13626 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13627 break; /* We have no PHY */
13628
34eea5ac 13629 if (!netif_running(dev))
bc1c7567
MC		 13630 return -EAGAIN;
13631
f47c11ee 13632 spin_lock_bh(&tp->lock);
5c358045
HM		 13633 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13634 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13635 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13636
13637 data->val_out = mii_regval;
13638
13639 return err;
13640 }
13641
13642 case SIOCSMIIREG:
f07e9af3 13643 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13644 break; /* We have no PHY */
13645
34eea5ac 13646 if (!netif_running(dev))
bc1c7567
MC		 13647 return -EAGAIN;
13648
f47c11ee 13649 spin_lock_bh(&tp->lock);
5c358045
HM		 13650 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13651 data->reg_num & 0x1f, data->val_in);
f47c11ee 13652 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13653
13654 return err;
13655
0a633ac2
MC		 13656 case SIOCSHWTSTAMP:
13657 return tg3_hwtstamp_ioctl(dev, ifr, cmd);
13658
1da177e4
LT		 13659 default:
13660 /* do nothing */
13661 break;
13662 }
13663 return -EOPNOTSUPP;
13664}
13665
15f9850d
DM		 13666static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13667{
13668 struct tg3 *tp = netdev_priv(dev);
13669
13670 memcpy(ec, &tp->coal, sizeof(*ec));
13671 return 0;
13672}
13673
d244c892
MC		 13674static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13675{
13676 struct tg3 *tp = netdev_priv(dev);
13677 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13678 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13679
63c3a66f 13680 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13681 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13682 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13683 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13684 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13685 }
13686
13687 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13688 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13689 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13690 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13691 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13692 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13693 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13694 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13695 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13696 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13697 return -EINVAL;
13698
13699 /* No rx interrupts will be generated if both are zero */
13700 if ((ec->rx_coalesce_usecs == 0) &&
13701 (ec->rx_max_coalesced_frames == 0))
13702 return -EINVAL;
13703
13704 /* No tx interrupts will be generated if both are zero */
13705 if ((ec->tx_coalesce_usecs == 0) &&
13706 (ec->tx_max_coalesced_frames == 0))
13707 return -EINVAL;
13708
13709 /* Only copy relevant parameters, ignore all others. */
13710 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13711 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13712 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13713 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13714 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13715 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13716 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13717 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13718 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13719
13720 if (netif_running(dev)) {
13721 tg3_full_lock(tp, 0);
13722 __tg3_set_coalesce(tp, &tp->coal);
13723 tg3_full_unlock(tp);
13724 }
13725 return 0;
13726}
13727
1cbf9eb8
NS		 13728static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13729{
13730 struct tg3 *tp = netdev_priv(dev);
13731
13732 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13733 netdev_warn(tp->dev, "Board does not support EEE!\n");
13734 return -EOPNOTSUPP;
13735 }
13736
13737 if (edata->advertised != tp->eee.advertised) {
13738 netdev_warn(tp->dev,
13739 "Direct manipulation of EEE advertisement is not supported\n");
13740 return -EINVAL;
13741 }
13742
13743 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13744 netdev_warn(tp->dev,
13745 "Maximal Tx Lpi timer supported is %#x(u)\n",
13746 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13747 return -EINVAL;
13748 }
13749
13750 tp->eee = *edata;
13751
13752 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13753 tg3_warn_mgmt_link_flap(tp);
13754
13755 if (netif_running(tp->dev)) {
13756 tg3_full_lock(tp, 0);
13757 tg3_setup_eee(tp);
13758 tg3_phy_reset(tp);
13759 tg3_full_unlock(tp);
13760 }
13761
13762 return 0;
13763}
13764
13765static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13766{
13767 struct tg3 *tp = netdev_priv(dev);
13768
13769 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13770 netdev_warn(tp->dev,
13771 "Board does not support EEE!\n");
13772 return -EOPNOTSUPP;
13773 }
13774
13775 *edata = tp->eee;
13776 return 0;
13777}
13778
7282d491 13779static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 13780 .get_settings = tg3_get_settings,
13781 .set_settings = tg3_set_settings,
13782 .get_drvinfo = tg3_get_drvinfo,
13783 .get_regs_len = tg3_get_regs_len,
13784 .get_regs = tg3_get_regs,
13785 .get_wol = tg3_get_wol,
13786 .set_wol = tg3_set_wol,
13787 .get_msglevel = tg3_get_msglevel,
13788 .set_msglevel = tg3_set_msglevel,
13789 .nway_reset = tg3_nway_reset,
13790 .get_link = ethtool_op_get_link,
13791 .get_eeprom_len = tg3_get_eeprom_len,
13792 .get_eeprom = tg3_get_eeprom,
13793 .set_eeprom = tg3_set_eeprom,
13794 .get_ringparam = tg3_get_ringparam,
13795 .set_ringparam = tg3_set_ringparam,
13796 .get_pauseparam = tg3_get_pauseparam,
13797 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 13798 .self_test = tg3_self_test,
1da177e4 13799 .get_strings = tg3_get_strings,
81b8709c 13800 .set_phys_id = tg3_set_phys_id,
1da177e4 13801 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 13802 .get_coalesce = tg3_get_coalesce,
d244c892 13803 .set_coalesce = tg3_set_coalesce,
b9f2c044 13804 .get_sset_count = tg3_get_sset_count,
90415477
MC		 13805 .get_rxnfc = tg3_get_rxnfc,
13806 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
13807 .get_rxfh_indir = tg3_get_rxfh_indir,
13808 .set_rxfh_indir = tg3_set_rxfh_indir,
0968169c
MC		 13809 .get_channels = tg3_get_channels,
13810 .set_channels = tg3_set_channels,
7d41e49a 13811 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 13812 .get_eee = tg3_get_eee,
13813 .set_eee = tg3_set_eee,
1da177e4
LT		 13814};
13815
b4017c53
DM		 13816static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
13817 struct rtnl_link_stats64 *stats)
13818{
13819 struct tg3 *tp = netdev_priv(dev);
13820
0f566b20
MC		 13821 spin_lock_bh(&tp->lock);
13822 if (!tp->hw_stats) {
13823 spin_unlock_bh(&tp->lock);
b4017c53 13824 return &tp->net_stats_prev;
0f566b20 13825 }
b4017c53 13826
b4017c53
DM		 13827 tg3_get_nstats(tp, stats);
13828 spin_unlock_bh(&tp->lock);
13829
13830 return stats;
13831}
13832
ccd5ba9d
MC		 13833static void tg3_set_rx_mode(struct net_device *dev)
13834{
13835 struct tg3 *tp = netdev_priv(dev);
13836
13837 if (!netif_running(dev))
13838 return;
13839
13840 tg3_full_lock(tp, 0);
13841 __tg3_set_rx_mode(dev);
13842 tg3_full_unlock(tp);
13843}
13844
faf1627a
MC		 13845static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
13846 int new_mtu)
13847{
13848 dev->mtu = new_mtu;
13849
13850 if (new_mtu > ETH_DATA_LEN) {
13851 if (tg3_flag(tp, 5780_CLASS)) {
13852 netdev_update_features(dev);
13853 tg3_flag_clear(tp, TSO_CAPABLE);
13854 } else {
13855 tg3_flag_set(tp, JUMBO_RING_ENABLE);
13856 }
13857 } else {
13858 if (tg3_flag(tp, 5780_CLASS)) {
13859 tg3_flag_set(tp, TSO_CAPABLE);
13860 netdev_update_features(dev);
13861 }
13862 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
13863 }
13864}
13865
13866static int tg3_change_mtu(struct net_device *dev, int new_mtu)
13867{
13868 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 13869 int err;
13870 bool reset_phy = false;
faf1627a
MC		 13871
13872 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
13873 return -EINVAL;
13874
13875 if (!netif_running(dev)) {
13876 /* We'll just catch it later when the
13877 * device is up'd.
13878 */
13879 tg3_set_mtu(dev, tp, new_mtu);
13880 return 0;
13881 }
13882
13883 tg3_phy_stop(tp);
13884
13885 tg3_netif_stop(tp);
13886
13887 tg3_full_lock(tp, 1);
13888
13889 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13890
13891 tg3_set_mtu(dev, tp, new_mtu);
13892
2fae5e36
MC		 13893 /* Reset PHY, otherwise the read DMA engine will be in a mode that
13894 * breaks all requests to 256 bytes.
13895 */
4153577a 13896 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 13897 reset_phy = true;
2fae5e36
MC		 13898
13899 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 13900
13901 if (!err)
13902 tg3_netif_start(tp);
13903
13904 tg3_full_unlock(tp);
13905
13906 if (!err)
13907 tg3_phy_start(tp);
13908
13909 return err;
13910}
13911
13912static const struct net_device_ops tg3_netdev_ops = {
13913 .ndo_open = tg3_open,
13914 .ndo_stop = tg3_close,
13915 .ndo_start_xmit = tg3_start_xmit,
13916 .ndo_get_stats64 = tg3_get_stats64,
13917 .ndo_validate_addr = eth_validate_addr,
13918 .ndo_set_rx_mode = tg3_set_rx_mode,
13919 .ndo_set_mac_address = tg3_set_mac_addr,
13920 .ndo_do_ioctl = tg3_ioctl,
13921 .ndo_tx_timeout = tg3_tx_timeout,
13922 .ndo_change_mtu = tg3_change_mtu,
13923 .ndo_fix_features = tg3_fix_features,
13924 .ndo_set_features = tg3_set_features,
13925#ifdef CONFIG_NET_POLL_CONTROLLER
13926 .ndo_poll_controller = tg3_poll_controller,
13927#endif
13928};
13929
229b1ad1 13930static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 13931{
1b27777a 13932 u32 cursize, val, magic;
1da177e4
LT		 13933
13934 tp->nvram_size = EEPROM_CHIP_SIZE;
13935
e4f34110 13936 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 13937 return;
13938
b16250e3
MC		 13939 if ((magic != TG3_EEPROM_MAGIC) &&
13940 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
13941 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 13942 return;
13943
13944 /*
13945 * Size the chip by reading offsets at increasing powers of two.
13946 * When we encounter our validation signature, we know the addressing
13947 * has wrapped around, and thus have our chip size.
13948 */
1b27777a 13949 cursize = 0x10;
1da177e4
LT		 13950
13951 while (cursize < tp->nvram_size) {
e4f34110 13952 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 13953 return;
13954
1820180b 13955 if (val == magic)
1da177e4
LT		 13956 break;
13957
13958 cursize <<= 1;
13959 }
13960
13961 tp->nvram_size = cursize;
13962}
6aa20a22 13963
229b1ad1 13964static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 13965{
13966 u32 val;
13967
63c3a66f 13968 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 13969 return;
13970
13971 /* Selfboot format */
1820180b 13972 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 13973 tg3_get_eeprom_size(tp);
13974 return;
13975 }
13976
6d348f2c 13977 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 13978 if (val != 0) {
6d348f2c
MC		 13979 /* This is confusing. We want to operate on the
13980 * 16-bit value at offset 0xf2. The tg3_nvram_read()
13981 * call will read from NVRAM and byteswap the data
13982 * according to the byteswapping settings for all
13983 * other register accesses. This ensures the data we
13984 * want will always reside in the lower 16-bits.
13985 * However, the data in NVRAM is in LE format, which
13986 * means the data from the NVRAM read will always be
13987 * opposite the endianness of the CPU. The 16-bit
13988 * byteswap then brings the data to CPU endianness.
13989 */
13990 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 13991 return;
13992 }
13993 }
fd1122a2 13994 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 13995}
13996
229b1ad1 13997static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 13998{
13999 u32 nvcfg1;
14000
14001 nvcfg1 = tr32(NVRAM_CFG1);
14002 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14003 tg3_flag_set(tp, FLASH);
8590a603 14004 } else {
1da177e4
LT		 14005 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14006 tw32(NVRAM_CFG1, nvcfg1);
14007 }
14008
4153577a 14009 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14010 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14011 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14012 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14013 tp->nvram_jedecnum = JEDEC_ATMEL;
14014 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14015 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14016 break;
14017 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14018 tp->nvram_jedecnum = JEDEC_ATMEL;
14019 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14020 break;
14021 case FLASH_VENDOR_ATMEL_EEPROM:
14022 tp->nvram_jedecnum = JEDEC_ATMEL;
14023 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14024 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14025 break;
14026 case FLASH_VENDOR_ST:
14027 tp->nvram_jedecnum = JEDEC_ST;
14028 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14029 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14030 break;
14031 case FLASH_VENDOR_SAIFUN:
14032 tp->nvram_jedecnum = JEDEC_SAIFUN;
14033 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14034 break;
14035 case FLASH_VENDOR_SST_SMALL:
14036 case FLASH_VENDOR_SST_LARGE:
14037 tp->nvram_jedecnum = JEDEC_SST;
14038 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14039 break;
1da177e4 14040 }
8590a603 14041 } else {
1da177e4
LT		 14042 tp->nvram_jedecnum = JEDEC_ATMEL;
14043 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14044 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14045 }
14046}
14047
229b1ad1 14048static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14049{
14050 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14051 case FLASH_5752PAGE_SIZE_256:
14052 tp->nvram_pagesize = 256;
14053 break;
14054 case FLASH_5752PAGE_SIZE_512:
14055 tp->nvram_pagesize = 512;
14056 break;
14057 case FLASH_5752PAGE_SIZE_1K:
14058 tp->nvram_pagesize = 1024;
14059 break;
14060 case FLASH_5752PAGE_SIZE_2K:
14061 tp->nvram_pagesize = 2048;
14062 break;
14063 case FLASH_5752PAGE_SIZE_4K:
14064 tp->nvram_pagesize = 4096;
14065 break;
14066 case FLASH_5752PAGE_SIZE_264:
14067 tp->nvram_pagesize = 264;
14068 break;
14069 case FLASH_5752PAGE_SIZE_528:
14070 tp->nvram_pagesize = 528;
14071 break;
14072 }
14073}
14074
229b1ad1 14075static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14076{
14077 u32 nvcfg1;
14078
14079 nvcfg1 = tr32(NVRAM_CFG1);
14080
e6af301b
MC		 14081 /* NVRAM protection for TPM */
14082 if (nvcfg1 & (1 << 27))
63c3a66f 14083 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14084
361b4ac2 14085 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14086 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14087 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14088 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14089 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14090 break;
14091 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14092 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14093 tg3_flag_set(tp, NVRAM_BUFFERED);
14094 tg3_flag_set(tp, FLASH);
8590a603
MC		 14095 break;
14096 case FLASH_5752VENDOR_ST_M45PE10:
14097 case FLASH_5752VENDOR_ST_M45PE20:
14098 case FLASH_5752VENDOR_ST_M45PE40:
14099 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14100 tg3_flag_set(tp, NVRAM_BUFFERED);
14101 tg3_flag_set(tp, FLASH);
8590a603 14102 break;
361b4ac2
MC		 14103 }
14104
63c3a66f 14105 if (tg3_flag(tp, FLASH)) {
a1b950d5 14106 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14107 } else {
361b4ac2
MC		 14108 /* For eeprom, set pagesize to maximum eeprom size */
14109 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14110
14111 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14112 tw32(NVRAM_CFG1, nvcfg1);
14113 }
14114}
14115
229b1ad1 14116static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14117{
989a9d23 14118 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14119
14120 nvcfg1 = tr32(NVRAM_CFG1);
14121
14122 /* NVRAM protection for TPM */
989a9d23 14123 if (nvcfg1 & (1 << 27)) {
63c3a66f 14124 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14125 protect = 1;
14126 }
d3c7b886 14127
989a9d23
MC		 14128 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14129 switch (nvcfg1) {
8590a603
MC		 14130 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14131 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14132 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14133 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14134 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14135 tg3_flag_set(tp, NVRAM_BUFFERED);
14136 tg3_flag_set(tp, FLASH);
8590a603
MC		 14137 tp->nvram_pagesize = 264;
14138 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14139 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14140 tp->nvram_size = (protect ? 0x3e200 :
14141 TG3_NVRAM_SIZE_512KB);
14142 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14143 tp->nvram_size = (protect ? 0x1f200 :
14144 TG3_NVRAM_SIZE_256KB);
14145 else
14146 tp->nvram_size = (protect ? 0x1f200 :
14147 TG3_NVRAM_SIZE_128KB);
14148 break;
14149 case FLASH_5752VENDOR_ST_M45PE10:
14150 case FLASH_5752VENDOR_ST_M45PE20:
14151 case FLASH_5752VENDOR_ST_M45PE40:
14152 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14153 tg3_flag_set(tp, NVRAM_BUFFERED);
14154 tg3_flag_set(tp, FLASH);
8590a603
MC		 14155 tp->nvram_pagesize = 256;
14156 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14157 tp->nvram_size = (protect ?
14158 TG3_NVRAM_SIZE_64KB :
14159 TG3_NVRAM_SIZE_128KB);
14160 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14161 tp->nvram_size = (protect ?
14162 TG3_NVRAM_SIZE_64KB :
14163 TG3_NVRAM_SIZE_256KB);
14164 else
14165 tp->nvram_size = (protect ?
14166 TG3_NVRAM_SIZE_128KB :
14167 TG3_NVRAM_SIZE_512KB);
14168 break;
d3c7b886
MC		 14169 }
14170}
14171
229b1ad1 14172static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14173{
14174 u32 nvcfg1;
14175
14176 nvcfg1 = tr32(NVRAM_CFG1);
14177
14178 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14179 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14180 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14181 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14182 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14183 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14184 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14185 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14186
8590a603
MC		 14187 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14188 tw32(NVRAM_CFG1, nvcfg1);
14189 break;
14190 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14191 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14192 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14193 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14194 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14195 tg3_flag_set(tp, NVRAM_BUFFERED);
14196 tg3_flag_set(tp, FLASH);
8590a603
MC		 14197 tp->nvram_pagesize = 264;
14198 break;
14199 case FLASH_5752VENDOR_ST_M45PE10:
14200 case FLASH_5752VENDOR_ST_M45PE20:
14201 case FLASH_5752VENDOR_ST_M45PE40:
14202 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14203 tg3_flag_set(tp, NVRAM_BUFFERED);
14204 tg3_flag_set(tp, FLASH);
8590a603
MC		 14205 tp->nvram_pagesize = 256;
14206 break;
1b27777a
MC		 14207 }
14208}
14209
229b1ad1 14210static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14211{
14212 u32 nvcfg1, protect = 0;
14213
14214 nvcfg1 = tr32(NVRAM_CFG1);
14215
14216 /* NVRAM protection for TPM */
14217 if (nvcfg1 & (1 << 27)) {
63c3a66f 14218 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14219 protect = 1;
14220 }
14221
14222 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14223 switch (nvcfg1) {
8590a603
MC		 14224 case FLASH_5761VENDOR_ATMEL_ADB021D:
14225 case FLASH_5761VENDOR_ATMEL_ADB041D:
14226 case FLASH_5761VENDOR_ATMEL_ADB081D:
14227 case FLASH_5761VENDOR_ATMEL_ADB161D:
14228 case FLASH_5761VENDOR_ATMEL_MDB021D:
14229 case FLASH_5761VENDOR_ATMEL_MDB041D:
14230 case FLASH_5761VENDOR_ATMEL_MDB081D:
14231 case FLASH_5761VENDOR_ATMEL_MDB161D:
14232 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14233 tg3_flag_set(tp, NVRAM_BUFFERED);
14234 tg3_flag_set(tp, FLASH);
14235 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14236 tp->nvram_pagesize = 256;
14237 break;
14238 case FLASH_5761VENDOR_ST_A_M45PE20:
14239 case FLASH_5761VENDOR_ST_A_M45PE40:
14240 case FLASH_5761VENDOR_ST_A_M45PE80:
14241 case FLASH_5761VENDOR_ST_A_M45PE16:
14242 case FLASH_5761VENDOR_ST_M_M45PE20:
14243 case FLASH_5761VENDOR_ST_M_M45PE40:
14244 case FLASH_5761VENDOR_ST_M_M45PE80:
14245 case FLASH_5761VENDOR_ST_M_M45PE16:
14246 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14247 tg3_flag_set(tp, NVRAM_BUFFERED);
14248 tg3_flag_set(tp, FLASH);
8590a603
MC		 14249 tp->nvram_pagesize = 256;
14250 break;
6b91fa02
MC		 14251 }
14252
14253 if (protect) {
14254 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14255 } else {
14256 switch (nvcfg1) {
8590a603
MC		 14257 case FLASH_5761VENDOR_ATMEL_ADB161D:
14258 case FLASH_5761VENDOR_ATMEL_MDB161D:
14259 case FLASH_5761VENDOR_ST_A_M45PE16:
14260 case FLASH_5761VENDOR_ST_M_M45PE16:
14261 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14262 break;
14263 case FLASH_5761VENDOR_ATMEL_ADB081D:
14264 case FLASH_5761VENDOR_ATMEL_MDB081D:
14265 case FLASH_5761VENDOR_ST_A_M45PE80:
14266 case FLASH_5761VENDOR_ST_M_M45PE80:
14267 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14268 break;
14269 case FLASH_5761VENDOR_ATMEL_ADB041D:
14270 case FLASH_5761VENDOR_ATMEL_MDB041D:
14271 case FLASH_5761VENDOR_ST_A_M45PE40:
14272 case FLASH_5761VENDOR_ST_M_M45PE40:
14273 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14274 break;
14275 case FLASH_5761VENDOR_ATMEL_ADB021D:
14276 case FLASH_5761VENDOR_ATMEL_MDB021D:
14277 case FLASH_5761VENDOR_ST_A_M45PE20:
14278 case FLASH_5761VENDOR_ST_M_M45PE20:
14279 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14280 break;
6b91fa02
MC		 14281 }
14282 }
14283}
14284
229b1ad1 14285static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14286{
14287 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14288 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14289 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14290}
14291
229b1ad1 14292static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14293{
14294 u32 nvcfg1;
14295
14296 nvcfg1 = tr32(NVRAM_CFG1);
14297
14298 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14299 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14300 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14301 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14302 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14303 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14304
14305 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14306 tw32(NVRAM_CFG1, nvcfg1);
14307 return;
14308 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14309 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14310 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14311 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14312 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14313 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14314 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14315 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14316 tg3_flag_set(tp, NVRAM_BUFFERED);
14317 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14318
14319 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14320 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14321 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14322 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14323 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14324 break;
14325 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14326 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14327 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14328 break;
14329 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14330 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14331 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14332 break;
14333 }
14334 break;
14335 case FLASH_5752VENDOR_ST_M45PE10:
14336 case FLASH_5752VENDOR_ST_M45PE20:
14337 case FLASH_5752VENDOR_ST_M45PE40:
14338 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14339 tg3_flag_set(tp, NVRAM_BUFFERED);
14340 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14341
14342 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14343 case FLASH_5752VENDOR_ST_M45PE10:
14344 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14345 break;
14346 case FLASH_5752VENDOR_ST_M45PE20:
14347 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14348 break;
14349 case FLASH_5752VENDOR_ST_M45PE40:
14350 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14351 break;
14352 }
14353 break;
14354 default:
63c3a66f 14355 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14356 return;
14357 }
14358
a1b950d5
MC		 14359 tg3_nvram_get_pagesize(tp, nvcfg1);
14360 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14361 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14362}
14363
14364
229b1ad1 14365static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14366{
14367 u32 nvcfg1;
14368
14369 nvcfg1 = tr32(NVRAM_CFG1);
14370
14371 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14372 case FLASH_5717VENDOR_ATMEL_EEPROM:
14373 case FLASH_5717VENDOR_MICRO_EEPROM:
14374 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14375 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14376 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14377
14378 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14379 tw32(NVRAM_CFG1, nvcfg1);
14380 return;
14381 case FLASH_5717VENDOR_ATMEL_MDB011D:
14382 case FLASH_5717VENDOR_ATMEL_ADB011B:
14383 case FLASH_5717VENDOR_ATMEL_ADB011D:
14384 case FLASH_5717VENDOR_ATMEL_MDB021D:
14385 case FLASH_5717VENDOR_ATMEL_ADB021B:
14386 case FLASH_5717VENDOR_ATMEL_ADB021D:
14387 case FLASH_5717VENDOR_ATMEL_45USPT:
14388 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14389 tg3_flag_set(tp, NVRAM_BUFFERED);
14390 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14391
14392 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14393 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14394 /* Detect size with tg3_nvram_get_size() */
14395 break;
a1b950d5
MC		 14396 case FLASH_5717VENDOR_ATMEL_ADB021B:
14397 case FLASH_5717VENDOR_ATMEL_ADB021D:
14398 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14399 break;
14400 default:
14401 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14402 break;
14403 }
321d32a0 14404 break;
a1b950d5
MC		 14405 case FLASH_5717VENDOR_ST_M_M25PE10:
14406 case FLASH_5717VENDOR_ST_A_M25PE10:
14407 case FLASH_5717VENDOR_ST_M_M45PE10:
14408 case FLASH_5717VENDOR_ST_A_M45PE10:
14409 case FLASH_5717VENDOR_ST_M_M25PE20:
14410 case FLASH_5717VENDOR_ST_A_M25PE20:
14411 case FLASH_5717VENDOR_ST_M_M45PE20:
14412 case FLASH_5717VENDOR_ST_A_M45PE20:
14413 case FLASH_5717VENDOR_ST_25USPT:
14414 case FLASH_5717VENDOR_ST_45USPT:
14415 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14416 tg3_flag_set(tp, NVRAM_BUFFERED);
14417 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14418
14419 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14420 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14421 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14422 /* Detect size with tg3_nvram_get_size() */
14423 break;
14424 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14425 case FLASH_5717VENDOR_ST_A_M45PE20:
14426 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14427 break;
14428 default:
14429 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14430 break;
14431 }
321d32a0 14432 break;
a1b950d5 14433 default:
63c3a66f 14434 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14435 return;
321d32a0 14436 }
a1b950d5
MC		 14437
14438 tg3_nvram_get_pagesize(tp, nvcfg1);
14439 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14440 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14441}
14442
229b1ad1 14443static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14444{
14445 u32 nvcfg1, nvmpinstrp;
14446
14447 nvcfg1 = tr32(NVRAM_CFG1);
14448 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14449
4153577a 14450 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14451 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14452 tg3_flag_set(tp, NO_NVRAM);
14453 return;
14454 }
14455
14456 switch (nvmpinstrp) {
14457 case FLASH_5762_EEPROM_HD:
14458 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14459 break;
c86a8560
MC		 14460 case FLASH_5762_EEPROM_LD:
14461 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14462 break;
f6334bb8
MC		 14463 case FLASH_5720VENDOR_M_ST_M45PE20:
14464 /* This pinstrap supports multiple sizes, so force it
14465 * to read the actual size from location 0xf0.
14466 */
14467 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14468 break;
c86a8560
MC		 14469 }
14470 }
14471
9b91b5f1
MC		 14472 switch (nvmpinstrp) {
14473 case FLASH_5720_EEPROM_HD:
14474 case FLASH_5720_EEPROM_LD:
14475 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14476 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14477
14478 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14479 tw32(NVRAM_CFG1, nvcfg1);
14480 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14481 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14482 else
14483 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14484 return;
14485 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14486 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14487 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14488 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14489 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14490 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14491 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14492 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14493 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14494 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14495 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14496 case FLASH_5720VENDOR_ATMEL_45USPT:
14497 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14498 tg3_flag_set(tp, NVRAM_BUFFERED);
14499 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14500
14501 switch (nvmpinstrp) {
14502 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14503 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14504 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14505 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14506 break;
14507 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14508 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14509 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14510 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14511 break;
14512 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14513 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14514 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14515 break;
14516 default:
4153577a 14517 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14518 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14519 break;
14520 }
14521 break;
14522 case FLASH_5720VENDOR_M_ST_M25PE10:
14523 case FLASH_5720VENDOR_M_ST_M45PE10:
14524 case FLASH_5720VENDOR_A_ST_M25PE10:
14525 case FLASH_5720VENDOR_A_ST_M45PE10:
14526 case FLASH_5720VENDOR_M_ST_M25PE20:
14527 case FLASH_5720VENDOR_M_ST_M45PE20:
14528 case FLASH_5720VENDOR_A_ST_M25PE20:
14529 case FLASH_5720VENDOR_A_ST_M45PE20:
14530 case FLASH_5720VENDOR_M_ST_M25PE40:
14531 case FLASH_5720VENDOR_M_ST_M45PE40:
14532 case FLASH_5720VENDOR_A_ST_M25PE40:
14533 case FLASH_5720VENDOR_A_ST_M45PE40:
14534 case FLASH_5720VENDOR_M_ST_M25PE80:
14535 case FLASH_5720VENDOR_M_ST_M45PE80:
14536 case FLASH_5720VENDOR_A_ST_M25PE80:
14537 case FLASH_5720VENDOR_A_ST_M45PE80:
14538 case FLASH_5720VENDOR_ST_25USPT:
14539 case FLASH_5720VENDOR_ST_45USPT:
14540 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14541 tg3_flag_set(tp, NVRAM_BUFFERED);
14542 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14543
14544 switch (nvmpinstrp) {
14545 case FLASH_5720VENDOR_M_ST_M25PE20:
14546 case FLASH_5720VENDOR_M_ST_M45PE20:
14547 case FLASH_5720VENDOR_A_ST_M25PE20:
14548 case FLASH_5720VENDOR_A_ST_M45PE20:
14549 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14550 break;
14551 case FLASH_5720VENDOR_M_ST_M25PE40:
14552 case FLASH_5720VENDOR_M_ST_M45PE40:
14553 case FLASH_5720VENDOR_A_ST_M25PE40:
14554 case FLASH_5720VENDOR_A_ST_M45PE40:
14555 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14556 break;
14557 case FLASH_5720VENDOR_M_ST_M25PE80:
14558 case FLASH_5720VENDOR_M_ST_M45PE80:
14559 case FLASH_5720VENDOR_A_ST_M25PE80:
14560 case FLASH_5720VENDOR_A_ST_M45PE80:
14561 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14562 break;
14563 default:
4153577a 14564 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14565 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14566 break;
14567 }
14568 break;
14569 default:
63c3a66f 14570 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14571 return;
14572 }
14573
14574 tg3_nvram_get_pagesize(tp, nvcfg1);
14575 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14576 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14577
4153577a 14578 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14579 u32 val;
14580
14581 if (tg3_nvram_read(tp, 0, &val))
14582 return;
14583
14584 if (val != TG3_EEPROM_MAGIC &&
14585 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14586 tg3_flag_set(tp, NO_NVRAM);
14587 }
9b91b5f1
MC		 14588}
14589
1da177e4 14590/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14591static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14592{
7e6c63f0
HM		 14593 if (tg3_flag(tp, IS_SSB_CORE)) {
14594 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14595 tg3_flag_clear(tp, NVRAM);
14596 tg3_flag_clear(tp, NVRAM_BUFFERED);
14597 tg3_flag_set(tp, NO_NVRAM);
14598 return;
14599 }
14600
1da177e4
LT		 14601 tw32_f(GRC_EEPROM_ADDR,
14602 (EEPROM_ADDR_FSM_RESET |
14603 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14604 EEPROM_ADDR_CLKPERD_SHIFT)));
14605
9d57f01c 14606 msleep(1);
1da177e4
LT		 14607
14608 /* Enable seeprom accesses. */
14609 tw32_f(GRC_LOCAL_CTRL,
14610 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14611 udelay(100);
14612
4153577a
JP		 14613 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14614 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14615 tg3_flag_set(tp, NVRAM);
1da177e4 14616
ec41c7df 14617 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14618 netdev_warn(tp->dev,
14619 "Cannot get nvram lock, %s failed\n",
05dbe005 14620 __func__);
ec41c7df
MC		 14621 return;
14622 }
e6af301b 14623 tg3_enable_nvram_access(tp);
1da177e4 14624
989a9d23
MC		 14625 tp->nvram_size = 0;
14626
4153577a 14627 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14628 tg3_get_5752_nvram_info(tp);
4153577a 14629 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14630 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14631 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14632 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14633 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14634 tg3_get_5787_nvram_info(tp);
4153577a 14635 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14636 tg3_get_5761_nvram_info(tp);
4153577a 14637 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14638 tg3_get_5906_nvram_info(tp);
4153577a 14639 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14640 tg3_flag(tp, 57765_CLASS))
321d32a0 14641 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14642 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14643 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14644 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14645 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14646 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14647 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14648 else
14649 tg3_get_nvram_info(tp);
14650
989a9d23
MC		 14651 if (tp->nvram_size == 0)
14652 tg3_get_nvram_size(tp);
1da177e4 14653
e6af301b 14654 tg3_disable_nvram_access(tp);
381291b7 14655 tg3_nvram_unlock(tp);
1da177e4
LT		 14656
14657 } else {
63c3a66f
JP		 14658 tg3_flag_clear(tp, NVRAM);
14659 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14660
14661 tg3_get_eeprom_size(tp);
14662 }
14663}
14664
1da177e4
LT		 14665struct subsys_tbl_ent {
14666 u16 subsys_vendor, subsys_devid;
14667 u32 phy_id;
14668};
14669
229b1ad1 14670static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14671 /* Broadcom boards. */
24daf2b0 14672 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14673 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14674 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14675 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14676 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14677 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14678 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14679 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14680 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14681 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14682 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14683 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14684 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14685 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14686 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14687 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14688 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14689 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14690 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14691 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14692 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14693 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14694
14695 /* 3com boards. */
24daf2b0 14696 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14697 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 14698 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14699 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14700 { TG3PCI_SUBVENDOR_ID_3COM,
14701 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14702 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14703 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 14704 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14705 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14706
14707 /* DELL boards. */
24daf2b0 14708 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14709 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 14710 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14711 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 14712 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14713 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 14714 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14715 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 14716
14717 /* Compaq boards. */
24daf2b0 14718 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14719 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 14720 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14721 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14722 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14723 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14724 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14725 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 14726 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14727 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14728
14729 /* IBM boards. */
24daf2b0
MC		 14730 { TG3PCI_SUBVENDOR_ID_IBM,
14731 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 14732};
14733
229b1ad1 14734static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 14735{
14736 int i;
14737
14738 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14739 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14740 tp->pdev->subsystem_vendor) &&
14741 (subsys_id_to_phy_id[i].subsys_devid ==
14742 tp->pdev->subsystem_device))
14743 return &subsys_id_to_phy_id[i];
14744 }
14745 return NULL;
14746}
14747
229b1ad1 14748static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 14749{
1da177e4 14750 u32 val;
f49639e6 14751
79eb6904 14752 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 14753 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14754
a85feb8c 14755 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 14756 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14757 tg3_flag_set(tp, WOL_CAP);
72b845e0 14758
4153577a 14759 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 14760 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 14761 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14762 tg3_flag_set(tp, IS_NIC);
9d26e213 14763 }
0527ba35
MC		 14764 val = tr32(VCPU_CFGSHDW);
14765 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 14766 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 14767 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 14768 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 14769 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14770 device_set_wakeup_enable(&tp->pdev->dev, true);
14771 }
05ac4cb7 14772 goto done;
b5d3772c
MC		 14773 }
14774
1da177e4
LT		 14775 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14776 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14777 u32 nic_cfg, led_cfg;
a9daf367 14778 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
7d0c41ef 14779 int eeprom_phy_serdes = 0;
1da177e4
LT		 14780
14781 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
14782 tp->nic_sram_data_cfg = nic_cfg;
14783
14784 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
14785 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 14786 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14787 tg3_asic_rev(tp) != ASIC_REV_5701 &&
14788 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 14789 (ver > 0) && (ver < 0x100))
14790 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
14791
4153577a 14792 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 14793 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
14794
1da177e4
LT		 14795 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
14796 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
14797 eeprom_phy_serdes = 1;
14798
14799 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
14800 if (nic_phy_id != 0) {
14801 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
14802 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
14803
14804 eeprom_phy_id = (id1 >> 16) << 10;
14805 eeprom_phy_id |= (id2 & 0xfc00) << 16;
14806 eeprom_phy_id |= (id2 & 0x03ff) << 0;
14807 } else
14808 eeprom_phy_id = 0;
14809
7d0c41ef 14810 tp->phy_id = eeprom_phy_id;
747e8f8b 14811 if (eeprom_phy_serdes) {
63c3a66f 14812 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 14813 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 14814 else
f07e9af3 14815 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 14816 }
7d0c41ef 14817
63c3a66f 14818 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 14819 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
14820 SHASTA_EXT_LED_MODE_MASK);
cbf46853 14821 else
1da177e4
LT		 14822 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
14823
14824 switch (led_cfg) {
14825 default:
14826 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
14827 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14828 break;
14829
14830 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
14831 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14832 break;
14833
14834 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
14835 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 14836
14837 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
14838 * read on some older 5700/5701 bootcode.
14839 */
4153577a
JP		 14840 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
14841 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 14842 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14843
1da177e4
LT		 14844 break;
14845
14846 case SHASTA_EXT_LED_SHARED:
14847 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 14848 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
14849 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 14850 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14851 LED_CTRL_MODE_PHY_2);
14852 break;
14853
14854 case SHASTA_EXT_LED_MAC:
14855 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
14856 break;
14857
14858 case SHASTA_EXT_LED_COMBO:
14859 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 14860 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 14861 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14862 LED_CTRL_MODE_PHY_2);
14863 break;
14864
855e1111 14865 }
1da177e4 14866
4153577a
JP		 14867 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
14868 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 14869 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
14870 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14871
4153577a 14872 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 14873 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 14874
9d26e213 14875 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 14876 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 14877 if ((tp->pdev->subsystem_vendor ==
14878 PCI_VENDOR_ID_ARIMA) &&
14879 (tp->pdev->subsystem_device == 0x205a ||
14880 tp->pdev->subsystem_device == 0x2063))
63c3a66f 14881 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 14882 } else {
63c3a66f
JP		 14883 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14884 tg3_flag_set(tp, IS_NIC);
9d26e213 14885 }
1da177e4
LT		 14886
14887 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 14888 tg3_flag_set(tp, ENABLE_ASF);
14889 if (tg3_flag(tp, 5750_PLUS))
14890 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 14891 }
b2b98d4a
MC		 14892
14893 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 14894 tg3_flag(tp, 5750_PLUS))
14895 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 14896
f07e9af3 14897 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 14898 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 14899 tg3_flag_clear(tp, WOL_CAP);
1da177e4 14900
63c3a66f 14901 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 14902 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 14903 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 14904 device_set_wakeup_enable(&tp->pdev->dev, true);
14905 }
0527ba35 14906
1da177e4 14907 if (cfg2 & (1 << 17))
f07e9af3 14908 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 14909
14910 /* serdes signal pre-emphasis in register 0x590 set by */
14911 /* bootcode if bit 18 is set */
14912 if (cfg2 & (1 << 18))
f07e9af3 14913 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 14914
63c3a66f 14915 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 14916 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
14917 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 14918 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 14919 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 14920
942d1af0 14921 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 14922 u32 cfg3;
14923
14924 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 14925 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
14926 !tg3_flag(tp, 57765_PLUS) &&
14927 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 14928 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 14929 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
14930 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
14931 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
14932 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 14933 }
a9daf367 14934
14417063 14935 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 14936 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 14937 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 14938 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 14939 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 14940 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
1da177e4 14941 }
05ac4cb7 14942done:
63c3a66f 14943 if (tg3_flag(tp, WOL_CAP))
43067ed8 14944 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 14945 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 14946 else
14947 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 14948}
14949
c86a8560
MC		 14950static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
14951{
14952 int i, err;
14953 u32 val2, off = offset * 8;
14954
14955 err = tg3_nvram_lock(tp);
14956 if (err)
14957 return err;
14958
14959 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
14960 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
14961 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
14962 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
14963 udelay(10);
14964
14965 for (i = 0; i < 100; i++) {
14966 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
14967 if (val2 & APE_OTP_STATUS_CMD_DONE) {
14968 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
14969 break;
14970 }
14971 udelay(10);
14972 }
14973
14974 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
14975
14976 tg3_nvram_unlock(tp);
14977 if (val2 & APE_OTP_STATUS_CMD_DONE)
14978 return 0;
14979
14980 return -EBUSY;
14981}
14982
229b1ad1 14983static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 14984{
14985 int i;
14986 u32 val;
14987
14988 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
14989 tw32(OTP_CTRL, cmd);
14990
14991 /* Wait for up to 1 ms for command to execute. */
14992 for (i = 0; i < 100; i++) {
14993 val = tr32(OTP_STATUS);
14994 if (val & OTP_STATUS_CMD_DONE)
14995 break;
14996 udelay(10);
14997 }
14998
14999 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15000}
15001
15002/* Read the gphy configuration from the OTP region of the chip. The gphy
15003 * configuration is a 32-bit value that straddles the alignment boundary.
15004 * We do two 32-bit reads and then shift and merge the results.
15005 */
229b1ad1 15006static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15007{
15008 u32 bhalf_otp, thalf_otp;
15009
15010 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15011
15012 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15013 return 0;
15014
15015 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15016
15017 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15018 return 0;
15019
15020 thalf_otp = tr32(OTP_READ_DATA);
15021
15022 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15023
15024 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15025 return 0;
15026
15027 bhalf_otp = tr32(OTP_READ_DATA);
15028
15029 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15030}
15031
229b1ad1 15032static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15033{
202ff1c2 15034 u32 adv = ADVERTISED_Autoneg;
e256f8a3
MC		 15035
15036 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15037 adv |= ADVERTISED_1000baseT_Half |
15038 ADVERTISED_1000baseT_Full;
15039
15040 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15041 adv |= ADVERTISED_100baseT_Half |
15042 ADVERTISED_100baseT_Full |
15043 ADVERTISED_10baseT_Half |
15044 ADVERTISED_10baseT_Full |
15045 ADVERTISED_TP;
15046 else
15047 adv |= ADVERTISED_FIBRE;
15048
15049 tp->link_config.advertising = adv;
e740522e
MC		 15050 tp->link_config.speed = SPEED_UNKNOWN;
15051 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15052 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15053 tp->link_config.active_speed = SPEED_UNKNOWN;
15054 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15055
15056 tp->old_link = -1;
e256f8a3
MC		 15057}
15058
229b1ad1 15059static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15060{
15061 u32 hw_phy_id_1, hw_phy_id_2;
15062 u32 hw_phy_id, hw_phy_id_masked;
15063 int err;
1da177e4 15064
e256f8a3 15065 /* flow control autonegotiation is default behavior */
63c3a66f 15066 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15067 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15068
8151ad57
MC		 15069 if (tg3_flag(tp, ENABLE_APE)) {
15070 switch (tp->pci_fn) {
15071 case 0:
15072 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15073 break;
15074 case 1:
15075 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15076 break;
15077 case 2:
15078 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15079 break;
15080 case 3:
15081 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15082 break;
15083 }
15084 }
15085
942d1af0
NS		 15086 if (!tg3_flag(tp, ENABLE_ASF) &&
15087 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15088 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15089 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15090 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15091
63c3a66f 15092 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15093 return tg3_phy_init(tp);
15094
1da177e4 15095 /* Reading the PHY ID register can conflict with ASF
877d0310 15096 * firmware access to the PHY hardware.
1da177e4
LT		 15097 */
15098 err = 0;
63c3a66f 15099 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15100 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15101 } else {
15102 /* Now read the physical PHY_ID from the chip and verify
15103 * that it is sane. If it doesn't look good, we fall back
15104 * to either the hard-coded table based PHY_ID and failing
15105 * that the value found in the eeprom area.
15106 */
15107 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15108 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15109
15110 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15111 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15112 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15113
79eb6904 15114 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15115 }
15116
79eb6904 15117 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15118 tp->phy_id = hw_phy_id;
79eb6904 15119 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15120 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15121 else
f07e9af3 15122 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15123 } else {
79eb6904 15124 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15125 /* Do nothing, phy ID already set up in
15126 * tg3_get_eeprom_hw_cfg().
15127 */
1da177e4
LT		 15128 } else {
15129 struct subsys_tbl_ent *p;
15130
15131 /* No eeprom signature? Try the hardcoded
15132 * subsys device table.
15133 */
24daf2b0 15134 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15135 if (p) {
15136 tp->phy_id = p->phy_id;
15137 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15138 /* For now we saw the IDs 0xbc050cd0,
15139 * 0xbc050f80 and 0xbc050c30 on devices
15140 * connected to an BCM4785 and there are
15141 * probably more. Just assume that the phy is
15142 * supported when it is connected to a SSB core
15143 * for now.
15144 */
1da177e4 15145 return -ENODEV;
7e6c63f0 15146 }
1da177e4 15147
1da177e4 15148 if (!tp->phy_id ||
79eb6904 15149 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15150 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15151 }
15152 }
15153
a6b68dab 15154 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15155 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15156 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15157 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15158 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15159 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15160 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15161 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15162 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15163 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15164
9e2ecbeb
NS		 15165 tp->eee.supported = SUPPORTED_100baseT_Full |
15166 SUPPORTED_1000baseT_Full;
15167 tp->eee.advertised = ADVERTISED_100baseT_Full |
15168 ADVERTISED_1000baseT_Full;
15169 tp->eee.eee_enabled = 1;
15170 tp->eee.tx_lpi_enabled = 1;
15171 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15172 }
15173
e256f8a3
MC		 15174 tg3_phy_init_link_config(tp);
15175
942d1af0
NS		 15176 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15177 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15178 !tg3_flag(tp, ENABLE_APE) &&
15179 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15180 u32 bmsr, dummy;
1da177e4
LT		 15181
15182 tg3_readphy(tp, MII_BMSR, &bmsr);
15183 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15184 (bmsr & BMSR_LSTATUS))
15185 goto skip_phy_reset;
6aa20a22 15186
1da177e4
LT		 15187 err = tg3_phy_reset(tp);
15188 if (err)
15189 return err;
15190
42b64a45 15191 tg3_phy_set_wirespeed(tp);
1da177e4 15192
e2bf73e7 15193 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15194 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15195 tp->link_config.flowctrl);
1da177e4
LT		 15196
15197 tg3_writephy(tp, MII_BMCR,
15198 BMCR_ANENABLE | BMCR_ANRESTART);
15199 }
1da177e4
LT		 15200 }
15201
15202skip_phy_reset:
79eb6904 15203 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15204 err = tg3_init_5401phy_dsp(tp);
15205 if (err)
15206 return err;
1da177e4 15207
1da177e4
LT		 15208 err = tg3_init_5401phy_dsp(tp);
15209 }
15210
1da177e4
LT		 15211 return err;
15212}
15213
229b1ad1 15214static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15215{
a4a8bb15 15216 u8 *vpd_data;
4181b2c8 15217 unsigned int block_end, rosize, len;
535a490e 15218 u32 vpdlen;
184b8904 15219 int j, i = 0;
a4a8bb15 15220
535a490e 15221 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15222 if (!vpd_data)
15223 goto out_no_vpd;
1da177e4 15224
535a490e 15225 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15226 if (i < 0)
15227 goto out_not_found;
1da177e4 15228
4181b2c8
MC		 15229 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15230 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15231 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15232
535a490e 15233 if (block_end > vpdlen)
4181b2c8 15234 goto out_not_found;
af2c6a4a 15235
184b8904
MC		 15236 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15237 PCI_VPD_RO_KEYWORD_MFR_ID);
15238 if (j > 0) {
15239 len = pci_vpd_info_field_size(&vpd_data[j]);
15240
15241 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15242 if (j + len > block_end || len != 4 ||
15243 memcmp(&vpd_data[j], "1028", 4))
15244 goto partno;
15245
15246 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15247 PCI_VPD_RO_KEYWORD_VENDOR0);
15248 if (j < 0)
15249 goto partno;
15250
15251 len = pci_vpd_info_field_size(&vpd_data[j]);
15252
15253 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15254 if (j + len > block_end)
15255 goto partno;
15256
715230a4
KC		 15257 if (len >= sizeof(tp->fw_ver))
15258 len = sizeof(tp->fw_ver) - 1;
15259 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15260 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15261 &vpd_data[j]);
184b8904
MC		 15262 }
15263
15264partno:
4181b2c8
MC		 15265 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15266 PCI_VPD_RO_KEYWORD_PARTNO);
15267 if (i < 0)
15268 goto out_not_found;
af2c6a4a 15269
4181b2c8 15270 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15271
4181b2c8
MC		 15272 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15273 if (len > TG3_BPN_SIZE ||
535a490e 15274 (len + i) > vpdlen)
4181b2c8 15275 goto out_not_found;
1da177e4 15276
4181b2c8 15277 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15278
1da177e4 15279out_not_found:
a4a8bb15 15280 kfree(vpd_data);
37a949c5 15281 if (tp->board_part_number[0])
a4a8bb15
MC		 15282 return;
15283
15284out_no_vpd:
4153577a 15285 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15286 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15287 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15288 strcpy(tp->board_part_number, "BCM5717");
15289 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15290 strcpy(tp->board_part_number, "BCM5718");
15291 else
15292 goto nomatch;
4153577a 15293 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15294 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15295 strcpy(tp->board_part_number, "BCM57780");
15296 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15297 strcpy(tp->board_part_number, "BCM57760");
15298 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15299 strcpy(tp->board_part_number, "BCM57790");
15300 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15301 strcpy(tp->board_part_number, "BCM57788");
15302 else
15303 goto nomatch;
4153577a 15304 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15305 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15306 strcpy(tp->board_part_number, "BCM57761");
15307 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15308 strcpy(tp->board_part_number, "BCM57765");
15309 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15310 strcpy(tp->board_part_number, "BCM57781");
15311 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15312 strcpy(tp->board_part_number, "BCM57785");
15313 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15314 strcpy(tp->board_part_number, "BCM57791");
15315 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15316 strcpy(tp->board_part_number, "BCM57795");
15317 else
15318 goto nomatch;
4153577a 15319 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15320 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15321 strcpy(tp->board_part_number, "BCM57762");
15322 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15323 strcpy(tp->board_part_number, "BCM57766");
15324 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15325 strcpy(tp->board_part_number, "BCM57782");
15326 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15327 strcpy(tp->board_part_number, "BCM57786");
15328 else
15329 goto nomatch;
4153577a 15330 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15331 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15332 } else {
15333nomatch:
b5d3772c 15334 strcpy(tp->board_part_number, "none");
37a949c5 15335 }
1da177e4
LT		 15336}
15337
229b1ad1 15338static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15339{
15340 u32 val;
15341
e4f34110 15342 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15343 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15344 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15345 val != 0)
15346 return 0;
15347
15348 return 1;
15349}
15350
229b1ad1 15351static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15352{
ff3a7cb2 15353 u32 val, offset, start, ver_offset;
75f9936e 15354 int i, dst_off;
ff3a7cb2 15355 bool newver = false;
acd9c119
MC		 15356
15357 if (tg3_nvram_read(tp, 0xc, &offset) ||
15358 tg3_nvram_read(tp, 0x4, &start))
15359 return;
15360
15361 offset = tg3_nvram_logical_addr(tp, offset);
15362
ff3a7cb2 15363 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15364 return;
15365
ff3a7cb2
MC		 15366 if ((val & 0xfc000000) == 0x0c000000) {
15367 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15368 return;
15369
ff3a7cb2
MC		 15370 if (val == 0)
15371 newver = true;
15372 }
15373
75f9936e
MC		 15374 dst_off = strlen(tp->fw_ver);
15375
ff3a7cb2 15376 if (newver) {
75f9936e
MC		 15377 if (TG3_VER_SIZE - dst_off < 16 ||
15378 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15379 return;
15380
15381 offset = offset + ver_offset - start;
15382 for (i = 0; i < 16; i += 4) {
15383 __be32 v;
15384 if (tg3_nvram_read_be32(tp, offset + i, &v))
15385 return;
15386
75f9936e 15387 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15388 }
15389 } else {
15390 u32 major, minor;
15391
15392 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15393 return;
15394
15395 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15396 TG3_NVM_BCVER_MAJSFT;
15397 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15398 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15399 "v%d.%02d", major, minor);
acd9c119
MC		 15400 }
15401}
15402
229b1ad1 15403static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15404{
15405 u32 val, major, minor;
15406
15407 /* Use native endian representation */
15408 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15409 return;
15410
15411 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15412 TG3_NVM_HWSB_CFG1_MAJSFT;
15413 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15414 TG3_NVM_HWSB_CFG1_MINSFT;
15415
15416 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15417}
15418
229b1ad1 15419static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15420{
15421 u32 offset, major, minor, build;
15422
75f9936e 15423 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15424
15425 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15426 return;
15427
15428 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15429 case TG3_EEPROM_SB_REVISION_0:
15430 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15431 break;
15432 case TG3_EEPROM_SB_REVISION_2:
15433 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15434 break;
15435 case TG3_EEPROM_SB_REVISION_3:
15436 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15437 break;
a4153d40
MC		 15438 case TG3_EEPROM_SB_REVISION_4:
15439 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15440 break;
15441 case TG3_EEPROM_SB_REVISION_5:
15442 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15443 break;
bba226ac
MC		 15444 case TG3_EEPROM_SB_REVISION_6:
15445 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15446 break;
dfe00d7d
MC		 15447 default:
15448 return;
15449 }
15450
e4f34110 15451 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15452 return;
15453
15454 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15455 TG3_EEPROM_SB_EDH_BLD_SHFT;
15456 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15457 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15458 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15459
15460 if (minor > 99 || build > 26)
15461 return;
15462
75f9936e
MC		 15463 offset = strlen(tp->fw_ver);
15464 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15465 " v%d.%02d", major, minor);
dfe00d7d
MC		 15466
15467 if (build > 0) {
75f9936e
MC		 15468 offset = strlen(tp->fw_ver);
15469 if (offset < TG3_VER_SIZE - 1)
15470 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15471 }
15472}
15473
229b1ad1 15474static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15475{
15476 u32 val, offset, start;
acd9c119 15477 int i, vlen;
9c8a620e
MC		 15478
15479 for (offset = TG3_NVM_DIR_START;
15480 offset < TG3_NVM_DIR_END;
15481 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15482 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15483 return;
15484
9c8a620e
MC		 15485 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15486 break;
15487 }
15488
15489 if (offset == TG3_NVM_DIR_END)
15490 return;
15491
63c3a66f 15492 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15493 start = 0x08000000;
e4f34110 15494 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15495 return;
15496
e4f34110 15497 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15498 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15499 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15500 return;
15501
15502 offset += val - start;
15503
acd9c119 15504 vlen = strlen(tp->fw_ver);
9c8a620e 15505
acd9c119
MC		 15506 tp->fw_ver[vlen++] = ',';
15507 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15508
15509 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15510 __be32 v;
15511 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15512 return;
15513
b9fc7dc5 15514 offset += sizeof(v);
c4e6575c 15515
acd9c119
MC		 15516 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15517 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15518 break;
c4e6575c 15519 }
9c8a620e 15520
acd9c119
MC		 15521 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15522 vlen += sizeof(v);
c4e6575c 15523 }
acd9c119
MC		 15524}
15525
229b1ad1 15526static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15527{
7fd76445 15528 u32 apedata;
7fd76445
MC		 15529
15530 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15531 if (apedata != APE_SEG_SIG_MAGIC)
15532 return;
15533
15534 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15535 if (!(apedata & APE_FW_STATUS_READY))
15536 return;
15537
165f4d1c
MC		 15538 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15539 tg3_flag_set(tp, APE_HAS_NCSI);
15540}
15541
229b1ad1 15542static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15543{
15544 int vlen;
15545 u32 apedata;
15546 char *fwtype;
15547
7fd76445
MC		 15548 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15549
165f4d1c 15550 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15551 fwtype = "NCSI";
c86a8560
MC		 15552 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15553 fwtype = "SMASH";
165f4d1c 15554 else
ecc79648
MC		 15555 fwtype = "DASH";
15556
7fd76445
MC		 15557 vlen = strlen(tp->fw_ver);
15558
ecc79648
MC		 15559 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15560 fwtype,
7fd76445
MC		 15561 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15562 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15563 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15564 (apedata & APE_FW_VERSION_BLDMSK));
15565}
15566
c86a8560
MC		 15567static void tg3_read_otp_ver(struct tg3 *tp)
15568{
15569 u32 val, val2;
15570
4153577a 15571 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15572 return;
15573
15574 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15575 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15576 TG3_OTP_MAGIC0_VALID(val)) {
15577 u64 val64 = (u64) val << 32 | val2;
15578 u32 ver = 0;
15579 int i, vlen;
15580
15581 for (i = 0; i < 7; i++) {
15582 if ((val64 & 0xff) == 0)
15583 break;
15584 ver = val64 & 0xff;
15585 val64 >>= 8;
15586 }
15587 vlen = strlen(tp->fw_ver);
15588 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15589 }
15590}
15591
229b1ad1 15592static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15593{
15594 u32 val;
75f9936e 15595 bool vpd_vers = false;
acd9c119 15596
75f9936e
MC		 15597 if (tp->fw_ver[0] != 0)
15598 vpd_vers = true;
df259d8c 15599
63c3a66f 15600 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15601 strcat(tp->fw_ver, "sb");
c86a8560 15602 tg3_read_otp_ver(tp);
df259d8c
MC		 15603 return;
15604 }
15605
acd9c119
MC		 15606 if (tg3_nvram_read(tp, 0, &val))
15607 return;
15608
15609 if (val == TG3_EEPROM_MAGIC)
15610 tg3_read_bc_ver(tp);
15611 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15612 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15613 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15614 tg3_read_hwsb_ver(tp);
acd9c119 15615
165f4d1c
MC		 15616 if (tg3_flag(tp, ENABLE_ASF)) {
15617 if (tg3_flag(tp, ENABLE_APE)) {
15618 tg3_probe_ncsi(tp);
15619 if (!vpd_vers)
15620 tg3_read_dash_ver(tp);
15621 } else if (!vpd_vers) {
15622 tg3_read_mgmtfw_ver(tp);
15623 }
c9cab24e 15624 }
9c8a620e
MC		 15625
15626 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15627}
15628
7cb32cf2
MC		 15629static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15630{
63c3a66f 15631 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15632 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15633 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15634 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15635 else
de9f5230 15636 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15637}
15638
4143470c 15639static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
895950c2
JP		 15640 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15641 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15642 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15643 { },
15644};
15645
229b1ad1 15646static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15647{
15648 struct pci_dev *peer;
15649 unsigned int func, devnr = tp->pdev->devfn & ~7;
15650
15651 for (func = 0; func < 8; func++) {
15652 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15653 if (peer && peer != tp->pdev)
15654 break;
15655 pci_dev_put(peer);
15656 }
15657 /* 5704 can be configured in single-port mode, set peer to
15658 * tp->pdev in that case.
15659 */
15660 if (!peer) {
15661 peer = tp->pdev;
15662 return peer;
15663 }
15664
15665 /*
15666 * We don't need to keep the refcount elevated; there's no way
15667 * to remove one half of this device without removing the other
15668 */
15669 pci_dev_put(peer);
15670
15671 return peer;
15672}
15673
229b1ad1 15674static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15675{
15676 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15677 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15678 u32 reg;
15679
15680 /* All devices that use the alternate
15681 * ASIC REV location have a CPMU.
15682 */
15683 tg3_flag_set(tp, CPMU_PRESENT);
15684
15685 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 15686 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 15687 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15688 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4
MC		 15689 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
15690 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15691 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
15692 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727)
42b123b1
MC		 15693 reg = TG3PCI_GEN2_PRODID_ASICREV;
15694 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15695 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15696 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15697 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15698 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15699 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15700 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15701 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15702 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15703 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15704 reg = TG3PCI_GEN15_PRODID_ASICREV;
15705 else
15706 reg = TG3PCI_PRODID_ASICREV;
15707
15708 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15709 }
15710
15711 /* Wrong chip ID in 5752 A0. This code can be removed later
15712 * as A0 is not in production.
15713 */
4153577a 15714 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 15715 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15716
4153577a 15717 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 15718 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15719
4153577a
JP		 15720 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15721 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15722 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 15723 tg3_flag_set(tp, 5717_PLUS);
15724
4153577a
JP		 15725 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15726 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 15727 tg3_flag_set(tp, 57765_CLASS);
15728
c65a17f4 15729 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 15730 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 15731 tg3_flag_set(tp, 57765_PLUS);
15732
15733 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 15734 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15735 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15736 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15737 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15738 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15739 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 15740 tg3_flag(tp, 57765_PLUS))
15741 tg3_flag_set(tp, 5755_PLUS);
15742
4153577a
JP		 15743 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15744 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 15745 tg3_flag_set(tp, 5780_CLASS);
15746
4153577a
JP		 15747 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15748 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15749 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 15750 tg3_flag(tp, 5755_PLUS) ||
15751 tg3_flag(tp, 5780_CLASS))
15752 tg3_flag_set(tp, 5750_PLUS);
15753
4153577a 15754 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 15755 tg3_flag(tp, 5750_PLUS))
15756 tg3_flag_set(tp, 5705_PLUS);
15757}
15758
3d567e0e
NNS		 15759static bool tg3_10_100_only_device(struct tg3 *tp,
15760 const struct pci_device_id *ent)
15761{
15762 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
15763
4153577a
JP		 15764 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
15765 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 15766 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15767 return true;
15768
15769 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 15770 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 15771 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
15772 return true;
15773 } else {
15774 return true;
15775 }
15776 }
15777
15778 return false;
15779}
15780
1dd06ae8 15781static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 15782{
1da177e4 15783 u32 misc_ctrl_reg;
1da177e4
LT		 15784 u32 pci_state_reg, grc_misc_cfg;
15785 u32 val;
15786 u16 pci_cmd;
5e7dfd0f 15787 int err;
1da177e4 15788
1da177e4
LT		 15789 /* Force memory write invalidate off. If we leave it on,
15790 * then on 5700_BX chips we have to enable a workaround.
15791 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15792 * to match the cacheline size. The Broadcom driver have this
15793 * workaround but turns MWI off all the times so never uses
15794 * it. This seems to suggest that the workaround is insufficient.
15795 */
15796 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15797 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
15798 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15799
16821285
MC		 15800 /* Important! -- Make sure register accesses are byteswapped
15801 * correctly. Also, for those chips that require it, make
15802 * sure that indirect register accesses are enabled before
15803 * the first operation.
1da177e4
LT		 15804 */
15805 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15806 &misc_ctrl_reg);
16821285
MC		 15807 tp->misc_host_ctrl |= (misc_ctrl_reg &
15808 MISC_HOST_CTRL_CHIPREV);
15809 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15810 tp->misc_host_ctrl);
1da177e4 15811
42b123b1 15812 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 15813
6892914f
MC		 15814 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
15815 * we need to disable memory and use config. cycles
15816 * only to access all registers. The 5702/03 chips
15817 * can mistakenly decode the special cycles from the
15818 * ICH chipsets as memory write cycles, causing corruption
15819 * of register and memory space. Only certain ICH bridges
15820 * will drive special cycles with non-zero data during the
15821 * address phase which can fall within the 5703's address
15822 * range. This is not an ICH bug as the PCI spec allows
15823 * non-zero address during special cycles. However, only
15824 * these ICH bridges are known to drive non-zero addresses
15825 * during special cycles.
15826 *
15827 * Since special cycles do not cross PCI bridges, we only
15828 * enable this workaround if the 5703 is on the secondary
15829 * bus of these ICH bridges.
15830 */
4153577a
JP		 15831 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
15832 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 15833 static struct tg3_dev_id {
15834 u32 vendor;
15835 u32 device;
15836 u32 rev;
15837 } ich_chipsets[] = {
15838 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
15839 PCI_ANY_ID },
15840 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
15841 PCI_ANY_ID },
15842 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
15843 0xa },
15844 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
15845 PCI_ANY_ID },
15846 { },
15847 };
15848 struct tg3_dev_id *pci_id = &ich_chipsets[0];
15849 struct pci_dev *bridge = NULL;
15850
15851 while (pci_id->vendor != 0) {
15852 bridge = pci_get_device(pci_id->vendor, pci_id->device,
15853 bridge);
15854 if (!bridge) {
15855 pci_id++;
15856 continue;
15857 }
15858 if (pci_id->rev != PCI_ANY_ID) {
44c10138 15859 if (bridge->revision > pci_id->rev)
6892914f
MC		 15860 continue;
15861 }
15862 if (bridge->subordinate &&
15863 (bridge->subordinate->number ==
15864 tp->pdev->bus->number)) {
63c3a66f 15865 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 15866 pci_dev_put(bridge);
15867 break;
15868 }
15869 }
15870 }
15871
4153577a 15872 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 15873 static struct tg3_dev_id {
15874 u32 vendor;
15875 u32 device;
15876 } bridge_chipsets[] = {
15877 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
15878 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
15879 { },
15880 };
15881 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
15882 struct pci_dev *bridge = NULL;
15883
15884 while (pci_id->vendor != 0) {
15885 bridge = pci_get_device(pci_id->vendor,
15886 pci_id->device,
15887 bridge);
15888 if (!bridge) {
15889 pci_id++;
15890 continue;
15891 }
15892 if (bridge->subordinate &&
15893 (bridge->subordinate->number <=
15894 tp->pdev->bus->number) &&
b918c62e 15895 (bridge->subordinate->busn_res.end >=
41588ba1 15896 tp->pdev->bus->number)) {
63c3a66f 15897 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 15898 pci_dev_put(bridge);
15899 break;
15900 }
15901 }
15902 }
15903
4a29cc2e
MC		 15904 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
15905 * DMA addresses > 40-bit. This bridge may have other additional
15906 * 57xx devices behind it in some 4-port NIC designs for example.
15907 * Any tg3 device found behind the bridge will also need the 40-bit
15908 * DMA workaround.
15909 */
42b123b1 15910 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 15911 tg3_flag_set(tp, 40BIT_DMA_BUG);
4cf78e4f 15912 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
859a5887 15913 } else {
4a29cc2e
MC		 15914 struct pci_dev *bridge = NULL;
15915
15916 do {
15917 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
15918 PCI_DEVICE_ID_SERVERWORKS_EPB,
15919 bridge);
15920 if (bridge && bridge->subordinate &&
15921 (bridge->subordinate->number <=
15922 tp->pdev->bus->number) &&
b918c62e 15923 (bridge->subordinate->busn_res.end >=
4a29cc2e 15924 tp->pdev->bus->number)) {
63c3a66f 15925 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 15926 pci_dev_put(bridge);
15927 break;
15928 }
15929 } while (bridge);
15930 }
4cf78e4f 15931
4153577a
JP		 15932 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
15933 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 15934 tp->pdev_peer = tg3_find_peer(tp);
15935
507399f1 15936 /* Determine TSO capabilities */
4153577a 15937 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 15938 ; /* Do nothing. HW bug. */
63c3a66f
JP		 15939 else if (tg3_flag(tp, 57765_PLUS))
15940 tg3_flag_set(tp, HW_TSO_3);
15941 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 15942 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 15943 tg3_flag_set(tp, HW_TSO_2);
15944 else if (tg3_flag(tp, 5750_PLUS)) {
15945 tg3_flag_set(tp, HW_TSO_1);
15946 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 15947 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
15948 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 15949 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 15950 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15951 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15952 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 15953 tg3_flag_set(tp, FW_TSO);
15954 tg3_flag_set(tp, TSO_BUG);
4153577a 15955 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 15956 tp->fw_needed = FIRMWARE_TG3TSO5;
15957 else
15958 tp->fw_needed = FIRMWARE_TG3TSO;
15959 }
15960
dabc5c67 15961 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 15962 if (tg3_flag(tp, HW_TSO_1) ||
15963 tg3_flag(tp, HW_TSO_2) ||
15964 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 15965 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 15966 /* For firmware TSO, assume ASF is disabled.
15967 * We'll disable TSO later if we discover ASF
15968 * is enabled in tg3_get_eeprom_hw_cfg().
15969 */
dabc5c67 15970 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 15971 } else {
dabc5c67
MC		 15972 tg3_flag_clear(tp, TSO_CAPABLE);
15973 tg3_flag_clear(tp, TSO_BUG);
15974 tp->fw_needed = NULL;
15975 }
15976
4153577a 15977 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 15978 tp->fw_needed = FIRMWARE_TG3;
15979
c4dab506
NS		 15980 if (tg3_asic_rev(tp) == ASIC_REV_57766)
15981 tp->fw_needed = FIRMWARE_TG357766;
15982
507399f1
MC		 15983 tp->irq_max = 1;
15984
63c3a66f
JP		 15985 if (tg3_flag(tp, 5750_PLUS)) {
15986 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 15987 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
15988 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
15989 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
15990 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 15991 tp->pdev_peer == tp->pdev))
63c3a66f 15992 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 15993
63c3a66f 15994 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 15995 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 15996 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 15997 }
4f125f42 15998
63c3a66f
JP		 15999 if (tg3_flag(tp, 57765_PLUS)) {
16000 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16001 tp->irq_max = TG3_IRQ_MAX_VECS;
16002 }
f6eb9b1f 16003 }
0e1406dd 16004
9102426a
MC		 16005 tp->txq_max = 1;
16006 tp->rxq_max = 1;
16007 if (tp->irq_max > 1) {
16008 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16009 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16010
4153577a
JP		 16011 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16012 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16013 tp->txq_max = tp->irq_max - 1;
16014 }
16015
b7abee6e 16016 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16017 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16018 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16019
4153577a 16020 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16021 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16022
4153577a
JP		 16023 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16024 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16025 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16026 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16027 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16028
63c3a66f 16029 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16030 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16031 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16032
63c3a66f
JP		 16033 if (!tg3_flag(tp, 5705_PLUS) ||
16034 tg3_flag(tp, 5780_CLASS) ||
16035 tg3_flag(tp, USE_JUMBO_BDFLAG))
16036 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16037
52f4490c
MC		 16038 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16039 &pci_state_reg);
16040
708ebb3a 16041 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16042 u16 lnkctl;
16043
63c3a66f 16044 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16045
0f49bfbd 16046 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16047 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16048 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16049 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16050 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16051 }
4153577a
JP		 16052 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16053 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16054 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16055 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16056 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16057 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16058 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16059 }
4153577a 16060 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16061 /* BCM5785 devices are effectively PCIe devices, and should
16062 * follow PCIe codepaths, but do not have a PCIe capabilities
16063 * section.
93a700a9 16064 */
63c3a66f
JP		 16065 tg3_flag_set(tp, PCI_EXPRESS);
16066 } else if (!tg3_flag(tp, 5705_PLUS) ||
16067 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16068 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16069 if (!tp->pcix_cap) {
2445e461
MC		 16070 dev_err(&tp->pdev->dev,
16071 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16072 return -EIO;
16073 }
16074
16075 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16076 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16077 }
1da177e4 16078
399de50b
MC		 16079 /* If we have an AMD 762 or VIA K8T800 chipset, write
16080 * reordering to the mailbox registers done by the host
16081 * controller can cause major troubles. We read back from
16082 * every mailbox register write to force the writes to be
16083 * posted to the chip in order.
16084 */
4143470c 16085 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16086 !tg3_flag(tp, PCI_EXPRESS))
16087 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16088
69fc4053
MC		 16089 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16090 &tp->pci_cacheline_sz);
16091 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16092 &tp->pci_lat_timer);
4153577a 16093 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16094 tp->pci_lat_timer < 64) {
16095 tp->pci_lat_timer = 64;
69fc4053
MC		 16096 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16097 tp->pci_lat_timer);
1da177e4
LT		 16098 }
16099
16821285
MC		 16100 /* Important! -- It is critical that the PCI-X hw workaround
16101 * situation is decided before the first MMIO register access.
16102 */
4153577a 16103 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16104 /* 5700 BX chips need to have their TX producer index
16105 * mailboxes written twice to workaround a bug.
16106 */
63c3a66f 16107 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16108
52f4490c 16109 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16110 *
16111 * The workaround is to use indirect register accesses
16112 * for all chip writes not to mailbox registers.
16113 */
63c3a66f 16114 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16115 u32 pm_reg;
1da177e4 16116
63c3a66f 16117 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16118
16119 /* The chip can have it's power management PCI config
16120 * space registers clobbered due to this bug.
16121 * So explicitly force the chip into D0 here.
16122 */
9974a356
MC		 16123 pci_read_config_dword(tp->pdev,
16124 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16125 &pm_reg);
16126 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16127 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356
MC		 16128 pci_write_config_dword(tp->pdev,
16129 tp->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16130 pm_reg);
16131
16132 /* Also, force SERR#/PERR# in PCI command. */
16133 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16134 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16135 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16136 }
16137 }
16138
1da177e4 16139 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16140 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16141 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16142 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16143
16144 /* Chip-specific fixup from Broadcom driver */
4153577a 16145 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16146 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16147 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16148 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16149 }
16150
1ee582d8 16151 /* Default fast path register access methods */
20094930 16152 tp->read32 = tg3_read32;
1ee582d8 16153 tp->write32 = tg3_write32;
09ee929c 16154 tp->read32_mbox = tg3_read32;
20094930 16155 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16156 tp->write32_tx_mbox = tg3_write32;
16157 tp->write32_rx_mbox = tg3_write32;
16158
16159 /* Various workaround register access methods */
63c3a66f 16160 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16161 tp->write32 = tg3_write_indirect_reg32;
4153577a 16162 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16163 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16164 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16165 /*
16166 * Back to back register writes can cause problems on these
16167 * chips, the workaround is to read back all reg writes
16168 * except those to mailbox regs.
16169 *
16170 * See tg3_write_indirect_reg32().
16171 */
1ee582d8 16172 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16173 }
16174
63c3a66f 16175 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16176 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16177 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16178 tp->write32_rx_mbox = tg3_write_flush_reg32;
16179 }
20094930 16180
63c3a66f 16181 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16182 tp->read32 = tg3_read_indirect_reg32;
16183 tp->write32 = tg3_write_indirect_reg32;
16184 tp->read32_mbox = tg3_read_indirect_mbox;
16185 tp->write32_mbox = tg3_write_indirect_mbox;
16186 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16187 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16188
16189 iounmap(tp->regs);
22abe310 16190 tp->regs = NULL;
6892914f
MC		 16191
16192 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16193 pci_cmd &= ~PCI_COMMAND_MEMORY;
16194 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16195 }
4153577a 16196 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16197 tp->read32_mbox = tg3_read32_mbox_5906;
16198 tp->write32_mbox = tg3_write32_mbox_5906;
16199 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16200 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16201 }
6892914f 16202
bbadf503 16203 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16204 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16205 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16206 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16207 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16208
16821285
MC		 16209 /* The memory arbiter has to be enabled in order for SRAM accesses
16210 * to succeed. Normally on powerup the tg3 chip firmware will make
16211 * sure it is enabled, but other entities such as system netboot
16212 * code might disable it.
16213 */
16214 val = tr32(MEMARB_MODE);
16215 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16216
9dc5e342 16217 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16218 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16219 tg3_flag(tp, 5780_CLASS)) {
16220 if (tg3_flag(tp, PCIX_MODE)) {
16221 pci_read_config_dword(tp->pdev,
16222 tp->pcix_cap + PCI_X_STATUS,
16223 &val);
16224 tp->pci_fn = val & 0x7;
16225 }
4153577a
JP		 16226 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16227 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16228 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16229 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16230 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16231 val = tr32(TG3_CPMU_STATUS);
16232
4153577a 16233 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16234 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16235 else
9dc5e342
MC		 16236 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16237 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16238 }
16239
7e6c63f0
HM		 16240 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16241 tp->write32_tx_mbox = tg3_write_flush_reg32;
16242 tp->write32_rx_mbox = tg3_write_flush_reg32;
16243 }
16244
7d0c41ef 16245 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16246 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16247 * determined before calling tg3_set_power_state() so that
16248 * we know whether or not to switch out of Vaux power.
16249 * When the flag is set, it means that GPIO1 is used for eeprom
16250 * write protect and also implies that it is a LOM where GPIOs
16251 * are not used to switch power.
6aa20a22 16252 */
7d0c41ef
MC		 16253 tg3_get_eeprom_hw_cfg(tp);
16254
1caf13eb 16255 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16256 tg3_flag_clear(tp, TSO_CAPABLE);
16257 tg3_flag_clear(tp, TSO_BUG);
16258 tp->fw_needed = NULL;
16259 }
16260
63c3a66f 16261 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16262 /* Allow reads and writes to the
16263 * APE register and memory space.
16264 */
16265 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16266 PCISTATE_ALLOW_APE_SHMEM_WR |
16267 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16268 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16269 pci_state_reg);
c9cab24e
MC		 16270
16271 tg3_ape_lock_init(tp);
0d3031d9
MC		 16272 }
16273
16821285
MC		 16274 /* Set up tp->grc_local_ctrl before calling
16275 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16276 * will bring 5700's external PHY out of reset.
314fba34
MC		 16277 * It is also used as eeprom write protect on LOMs.
16278 */
16279 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16280 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16281 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16282 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16283 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16284 /* Unused GPIO3 must be driven as output on 5752 because there
16285 * are no pull-up resistors on unused GPIO pins.
16286 */
4153577a 16287 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16288 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16289
4153577a
JP		 16290 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16291 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16292 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16293 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16294
8d519ab2
MC		 16295 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16296 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16297 /* Turn off the debug UART. */
16298 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16299 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16300 /* Keep VMain power. */
16301 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16302 GRC_LCLCTRL_GPIO_OUTPUT0;
16303 }
16304
4153577a 16305 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16306 tp->grc_local_ctrl |=
16307 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16308
16821285
MC		 16309 /* Switch out of Vaux if it is a NIC */
16310 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16311
1da177e4
LT		 16312 /* Derive initial jumbo mode from MTU assigned in
16313 * ether_setup() via the alloc_etherdev() call
16314 */
63c3a66f
JP		 16315 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16316 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16317
16318 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16319 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16320 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16321 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16322 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16323 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16324 } else {
63c3a66f 16325 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16326 }
16327
4153577a 16328 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16329 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16330
1da177e4 16331 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16332 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16333 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16334 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16335 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16336 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16337 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16338 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16339
4153577a
JP		 16340 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16341 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16342 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16343 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16344 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16345
63c3a66f 16346 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16347 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16348 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16349 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16350 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16351 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16352 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16353 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16354 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16355 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16356 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16357 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16358 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16359 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16360 } else
f07e9af3 16361 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16362 }
1da177e4 16363
4153577a
JP		 16364 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16365 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16366 tp->phy_otp = tg3_read_otp_phycfg(tp);
16367 if (tp->phy_otp == 0)
16368 tp->phy_otp = TG3_OTP_DEFAULT;
16369 }
16370
63c3a66f 16371 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16372 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16373 else
16374 tp->mi_mode = MAC_MI_MODE_BASE;
16375
1da177e4 16376 tp->coalesce_mode = 0;
4153577a
JP		 16377 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16378 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16379 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16380
4d958473 16381 /* Set these bits to enable statistics workaround. */
4153577a
JP		 16382 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16383 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16384 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16385 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16386 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16387 }
16388
4153577a
JP		 16389 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16390 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16391 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16392
158d7abd
MC		 16393 err = tg3_mdio_init(tp);
16394 if (err)
16395 return err;
1da177e4
LT		 16396
16397 /* Initialize data/descriptor byte/word swapping. */
16398 val = tr32(GRC_MODE);
4153577a
JP		 16399 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16400 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16401 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16402 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16403 GRC_MODE_B2HRX_ENABLE |
16404 GRC_MODE_HTX2B_ENABLE |
16405 GRC_MODE_HOST_STACKUP);
16406 else
16407 val &= GRC_MODE_HOST_STACKUP;
16408
1da177e4
LT		 16409 tw32(GRC_MODE, val | tp->grc_mode);
16410
16411 tg3_switch_clocks(tp);
16412
16413 /* Clear this out for sanity. */
16414 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16415
16416 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16417 &pci_state_reg);
16418 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16419 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16420 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16421 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16422 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16423 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16424 void __iomem *sram_base;
16425
16426 /* Write some dummy words into the SRAM status block
16427 * area, see if it reads back correctly. If the return
16428 * value is bad, force enable the PCIX workaround.
16429 */
16430 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16431
16432 writel(0x00000000, sram_base);
16433 writel(0x00000000, sram_base + 4);
16434 writel(0xffffffff, sram_base + 4);
16435 if (readl(sram_base) != 0x00000000)
63c3a66f 16436 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16437 }
16438 }
16439
16440 udelay(50);
16441 tg3_nvram_init(tp);
16442
c4dab506
NS		 16443 /* If the device has an NVRAM, no need to load patch firmware */
16444 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16445 !tg3_flag(tp, NO_NVRAM))
16446 tp->fw_needed = NULL;
16447
1da177e4
LT		 16448 grc_misc_cfg = tr32(GRC_MISC_CFG);
16449 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16450
4153577a 16451 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16452 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16453 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16454 tg3_flag_set(tp, IS_5788);
1da177e4 16455
63c3a66f 16456 if (!tg3_flag(tp, IS_5788) &&
4153577a 16457 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16458 tg3_flag_set(tp, TAGGED_STATUS);
16459 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16460 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16461 HOSTCC_MODE_CLRTICK_TXBD);
16462
16463 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16464 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16465 tp->misc_host_ctrl);
16466 }
16467
3bda1258 16468 /* Preserve the APE MAC_MODE bits */
63c3a66f 16469 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16470 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16471 else
6e01b20b 16472 tp->mac_mode = 0;
3bda1258 16473
3d567e0e 16474 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16475 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16476
16477 err = tg3_phy_probe(tp);
16478 if (err) {
2445e461 16479 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16480 /* ... but do not return immediately ... */
b02fd9e3 16481 tg3_mdio_fini(tp);
1da177e4
LT		 16482 }
16483
184b8904 16484 tg3_read_vpd(tp);
c4e6575c 16485 tg3_read_fw_ver(tp);
1da177e4 16486
f07e9af3
MC		 16487 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16488 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16489 } else {
4153577a 16490 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16491 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16492 else
f07e9af3 16493 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16494 }
16495
16496 /* 5700 {AX,BX} chips have a broken status block link
16497 * change bit implementation, so we must use the
16498 * status register in those cases.
16499 */
4153577a 16500 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16501 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16502 else
63c3a66f 16503 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16504
16505 /* The led_ctrl is set during tg3_phy_probe, here we might
16506 * have to force the link status polling mechanism based
16507 * upon subsystem IDs.
16508 */
16509 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16510 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16511 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16512 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16513 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16514 }
16515
16516 /* For all SERDES we poll the MAC status register. */
f07e9af3 16517 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16518 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16519 else
63c3a66f 16520 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16521
9205fd9c 16522 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16523 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16524 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16525 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16526 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16527#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16528 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16529#endif
16530 }
1da177e4 16531
2c49a44d
MC		 16532 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16533 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16534 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16535
2c49a44d 16536 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16537
16538 /* Increment the rx prod index on the rx std ring by at most
16539 * 8 for these chips to workaround hw errata.
16540 */
4153577a
JP		 16541 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16542 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16543 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16544 tp->rx_std_max_post = 8;
16545
63c3a66f 16546 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16547 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16548 PCIE_PWR_MGMT_L1_THRESH_MSK;
16549
1da177e4
LT		 16550 return err;
16551}
16552
49b6e95f 16553#ifdef CONFIG_SPARC
229b1ad1 16554static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16555{
16556 struct net_device *dev = tp->dev;
16557 struct pci_dev *pdev = tp->pdev;
49b6e95f 16558 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16559 const unsigned char *addr;
49b6e95f
DM		 16560 int len;
16561
16562 addr = of_get_property(dp, "local-mac-address", &len);
16563 if (addr && len == 6) {
16564 memcpy(dev->dev_addr, addr, 6);
49b6e95f 16565 return 0;
1da177e4
LT		 16566 }
16567 return -ENODEV;
16568}
16569
229b1ad1 16570static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16571{
16572 struct net_device *dev = tp->dev;
16573
16574 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
16575 return 0;
16576}
16577#endif
16578
229b1ad1 16579static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16580{
16581 struct net_device *dev = tp->dev;
16582 u32 hi, lo, mac_offset;
008652b3 16583 int addr_ok = 0;
7e6c63f0 16584 int err;
1da177e4 16585
49b6e95f 16586#ifdef CONFIG_SPARC
1da177e4
LT		 16587 if (!tg3_get_macaddr_sparc(tp))
16588 return 0;
16589#endif
16590
7e6c63f0
HM		 16591 if (tg3_flag(tp, IS_SSB_CORE)) {
16592 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16593 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16594 return 0;
16595 }
16596
1da177e4 16597 mac_offset = 0x7c;
4153577a 16598 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16599 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16600 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16601 mac_offset = 0xcc;
16602 if (tg3_nvram_lock(tp))
16603 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16604 else
16605 tg3_nvram_unlock(tp);
63c3a66f 16606 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16607 if (tp->pci_fn & 1)
a1b950d5 16608 mac_offset = 0xcc;
69f11c99 16609 if (tp->pci_fn > 1)
a50d0796 16610 mac_offset += 0x18c;
4153577a 16611 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16612 mac_offset = 0x10;
1da177e4
LT		 16613
16614 /* First try to get it from MAC address mailbox. */
16615 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16616 if ((hi >> 16) == 0x484b) {
16617 dev->dev_addr[0] = (hi >> 8) & 0xff;
16618 dev->dev_addr[1] = (hi >> 0) & 0xff;
16619
16620 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16621 dev->dev_addr[2] = (lo >> 24) & 0xff;
16622 dev->dev_addr[3] = (lo >> 16) & 0xff;
16623 dev->dev_addr[4] = (lo >> 8) & 0xff;
16624 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16625
008652b3
MC		 16626 /* Some old bootcode may report a 0 MAC address in SRAM */
16627 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16628 }
16629 if (!addr_ok) {
16630 /* Next, try NVRAM. */
63c3a66f 16631 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16632 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16633 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16634 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16635 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16636 }
16637 /* Finally just fetch it out of the MAC control regs. */
16638 else {
16639 hi = tr32(MAC_ADDR_0_HIGH);
16640 lo = tr32(MAC_ADDR_0_LOW);
16641
16642 dev->dev_addr[5] = lo & 0xff;
16643 dev->dev_addr[4] = (lo >> 8) & 0xff;
16644 dev->dev_addr[3] = (lo >> 16) & 0xff;
16645 dev->dev_addr[2] = (lo >> 24) & 0xff;
16646 dev->dev_addr[1] = hi & 0xff;
16647 dev->dev_addr[0] = (hi >> 8) & 0xff;
16648 }
1da177e4
LT		 16649 }
16650
16651 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16652#ifdef CONFIG_SPARC
1da177e4
LT		 16653 if (!tg3_get_default_macaddr_sparc(tp))
16654 return 0;
16655#endif
16656 return -EINVAL;
16657 }
16658 return 0;
16659}
16660
59e6b434
DM		 16661#define BOUNDARY_SINGLE_CACHELINE 1
16662#define BOUNDARY_MULTI_CACHELINE 2
16663
229b1ad1 16664static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16665{
16666 int cacheline_size;
16667 u8 byte;
16668 int goal;
16669
16670 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16671 if (byte == 0)
16672 cacheline_size = 1024;
16673 else
16674 cacheline_size = (int) byte * 4;
16675
16676 /* On 5703 and later chips, the boundary bits have no
16677 * effect.
16678 */
4153577a
JP		 16679 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16680 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 16681 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 16682 goto out;
16683
16684#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16685 goal = BOUNDARY_MULTI_CACHELINE;
16686#else
16687#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16688 goal = BOUNDARY_SINGLE_CACHELINE;
16689#else
16690 goal = 0;
16691#endif
16692#endif
16693
63c3a66f 16694 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 16695 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16696 goto out;
16697 }
16698
59e6b434
DM		 16699 if (!goal)
16700 goto out;
16701
16702 /* PCI controllers on most RISC systems tend to disconnect
16703 * when a device tries to burst across a cache-line boundary.
16704 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16705 *
16706 * Unfortunately, for PCI-E there are only limited
16707 * write-side controls for this, and thus for reads
16708 * we will still get the disconnects. We'll also waste
16709 * these PCI cycles for both read and write for chips
16710 * other than 5700 and 5701 which do not implement the
16711 * boundary bits.
16712 */
63c3a66f 16713 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16714 switch (cacheline_size) {
16715 case 16:
16716 case 32:
16717 case 64:
16718 case 128:
16719 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16720 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16721 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16722 } else {
16723 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16724 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16725 }
16726 break;
16727
16728 case 256:
16729 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16730 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16731 break;
16732
16733 default:
16734 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16735 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16736 break;
855e1111 16737 }
63c3a66f 16738 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16739 switch (cacheline_size) {
16740 case 16:
16741 case 32:
16742 case 64:
16743 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16744 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16745 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
16746 break;
16747 }
16748 /* fallthrough */
16749 case 128:
16750 default:
16751 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16752 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
16753 break;
855e1111 16754 }
59e6b434
DM		 16755 } else {
16756 switch (cacheline_size) {
16757 case 16:
16758 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16759 val |= (DMA_RWCTRL_READ_BNDRY_16 |
16760 DMA_RWCTRL_WRITE_BNDRY_16);
16761 break;
16762 }
16763 /* fallthrough */
16764 case 32:
16765 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16766 val |= (DMA_RWCTRL_READ_BNDRY_32 |
16767 DMA_RWCTRL_WRITE_BNDRY_32);
16768 break;
16769 }
16770 /* fallthrough */
16771 case 64:
16772 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16773 val |= (DMA_RWCTRL_READ_BNDRY_64 |
16774 DMA_RWCTRL_WRITE_BNDRY_64);
16775 break;
16776 }
16777 /* fallthrough */
16778 case 128:
16779 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16780 val |= (DMA_RWCTRL_READ_BNDRY_128 |
16781 DMA_RWCTRL_WRITE_BNDRY_128);
16782 break;
16783 }
16784 /* fallthrough */
16785 case 256:
16786 val |= (DMA_RWCTRL_READ_BNDRY_256 |
16787 DMA_RWCTRL_WRITE_BNDRY_256);
16788 break;
16789 case 512:
16790 val |= (DMA_RWCTRL_READ_BNDRY_512 |
16791 DMA_RWCTRL_WRITE_BNDRY_512);
16792 break;
16793 case 1024:
16794 default:
16795 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
16796 DMA_RWCTRL_WRITE_BNDRY_1024);
16797 break;
855e1111 16798 }
59e6b434
DM		 16799 }
16800
16801out:
16802 return val;
16803}
16804
229b1ad1 16805static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 16806 int size, bool to_device)
1da177e4
LT		 16807{
16808 struct tg3_internal_buffer_desc test_desc;
16809 u32 sram_dma_descs;
16810 int i, ret;
16811
16812 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
16813
16814 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
16815 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
16816 tw32(RDMAC_STATUS, 0);
16817 tw32(WDMAC_STATUS, 0);
16818
16819 tw32(BUFMGR_MODE, 0);
16820 tw32(FTQ_RESET, 0);
16821
16822 test_desc.addr_hi = ((u64) buf_dma) >> 32;
16823 test_desc.addr_lo = buf_dma & 0xffffffff;
16824 test_desc.nic_mbuf = 0x00002100;
16825 test_desc.len = size;
16826
16827 /*
16828 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
16829 * the *second* time the tg3 driver was getting loaded after an
16830 * initial scan.
16831 *
16832 * Broadcom tells me:
16833 * ...the DMA engine is connected to the GRC block and a DMA
16834 * reset may affect the GRC block in some unpredictable way...
16835 * The behavior of resets to individual blocks has not been tested.
16836 *
16837 * Broadcom noted the GRC reset will also reset all sub-components.
16838 */
16839 if (to_device) {
16840 test_desc.cqid_sqid = (13 << 8) | 2;
16841
16842 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
16843 udelay(40);
16844 } else {
16845 test_desc.cqid_sqid = (16 << 8) | 7;
16846
16847 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
16848 udelay(40);
16849 }
16850 test_desc.flags = 0x00000005;
16851
16852 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
16853 u32 val;
16854
16855 val = *(((u32 *)&test_desc) + i);
16856 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
16857 sram_dma_descs + (i * sizeof(u32)));
16858 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
16859 }
16860 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
16861
859a5887 16862 if (to_device)
1da177e4 16863 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 16864 else
1da177e4 16865 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 16866
16867 ret = -ENODEV;
16868 for (i = 0; i < 40; i++) {
16869 u32 val;
16870
16871 if (to_device)
16872 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
16873 else
16874 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
16875 if ((val & 0xffff) == sram_dma_descs) {
16876 ret = 0;
16877 break;
16878 }
16879
16880 udelay(100);
16881 }
16882
16883 return ret;
16884}
16885
ded7340d 16886#define TEST_BUFFER_SIZE 0x2000
1da177e4 16887
4143470c 16888static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
895950c2
JP		 16889 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
16890 { },
16891};
16892
229b1ad1 16893static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 16894{
16895 dma_addr_t buf_dma;
59e6b434 16896 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 16897 int ret = 0;
1da177e4 16898
4bae65c8
MC		 16899 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
16900 &buf_dma, GFP_KERNEL);
1da177e4
LT		 16901 if (!buf) {
16902 ret = -ENOMEM;
16903 goto out_nofree;
16904 }
16905
16906 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
16907 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
16908
59e6b434 16909 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 16910
63c3a66f 16911 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 16912 goto out;
16913
63c3a66f 16914 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 16915 /* DMA read watermark not used on PCIE */
16916 tp->dma_rwctrl |= 0x00180000;
63c3a66f 16917 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 16918 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16919 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 16920 tp->dma_rwctrl |= 0x003f0000;
16921 else
16922 tp->dma_rwctrl |= 0x003f000f;
16923 } else {
4153577a
JP		 16924 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
16925 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 16926 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 16927 u32 read_water = 0x7;
1da177e4 16928
4a29cc2e
MC		 16929 /* If the 5704 is behind the EPB bridge, we can
16930 * do the less restrictive ONE_DMA workaround for
16931 * better performance.
16932 */
63c3a66f 16933 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 16934 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 16935 tp->dma_rwctrl |= 0x8000;
16936 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 16937 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
16938
4153577a 16939 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 16940 read_water = 4;
59e6b434 16941 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 16942 tp->dma_rwctrl |=
16943 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
16944 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
16945 (1 << 23);
4153577a 16946 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 16947 /* 5780 always in PCIX mode */
16948 tp->dma_rwctrl |= 0x00144000;
4153577a 16949 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 16950 /* 5714 always in PCIX mode */
16951 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 16952 } else {
16953 tp->dma_rwctrl |= 0x001b000f;
16954 }
16955 }
7e6c63f0
HM		 16956 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
16957 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 16958
4153577a
JP		 16959 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
16960 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 16961 tp->dma_rwctrl &= 0xfffffff0;
16962
4153577a
JP		 16963 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16964 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 16965 /* Remove this if it causes problems for some boards. */
16966 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
16967
16968 /* On 5700/5701 chips, we need to set this bit.
16969 * Otherwise the chip will issue cacheline transactions
16970 * to streamable DMA memory with not all the byte
16971 * enables turned on. This is an error on several
16972 * RISC PCI controllers, in particular sparc64.
16973 *
16974 * On 5703/5704 chips, this bit has been reassigned
16975 * a different meaning. In particular, it is used
16976 * on those chips to enable a PCI-X workaround.
16977 */
16978 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
16979 }
16980
16981 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
16982
16983#if 0
16984 /* Unneeded, already done by tg3_get_invariants. */
16985 tg3_switch_clocks(tp);
16986#endif
16987
4153577a
JP		 16988 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16989 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 16990 goto out;
16991
59e6b434
DM		 16992 /* It is best to perform DMA test with maximum write burst size
16993 * to expose the 5700/5701 write DMA bug.
16994 */
16995 saved_dma_rwctrl = tp->dma_rwctrl;
16996 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
16997 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
16998
1da177e4
LT		 16999 while (1) {
17000 u32 *p = buf, i;
17001
17002 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17003 p[i] = i;
17004
17005 /* Send the buffer to the chip. */
953c96e0 17006 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17007 if (ret) {
2445e461
MC		 17008 dev_err(&tp->pdev->dev,
17009 "%s: Buffer write failed. err = %d\n",
17010 __func__, ret);
1da177e4
LT		 17011 break;
17012 }
17013
17014#if 0
17015 /* validate data reached card RAM correctly. */
17016 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17017 u32 val;
17018 tg3_read_mem(tp, 0x2100 + (i*4), &val);
17019 if (le32_to_cpu(val) != p[i]) {
2445e461
MC		 17020 dev_err(&tp->pdev->dev,
17021 "%s: Buffer corrupted on device! "
17022 "(%d != %d)\n", __func__, val, i);
1da177e4
LT		 17023 /* ret = -ENODEV here? */
17024 }
17025 p[i] = 0;
17026 }
17027#endif
17028 /* Now read it back. */
953c96e0 17029 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17030 if (ret) {
5129c3a3
MC		 17031 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17032 "err = %d\n", __func__, ret);
1da177e4
LT		 17033 break;
17034 }
17035
17036 /* Verify it. */
17037 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17038 if (p[i] == i)
17039 continue;
17040
59e6b434
DM		 17041 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17042 DMA_RWCTRL_WRITE_BNDRY_16) {
17043 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17044 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17045 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17046 break;
17047 } else {
2445e461
MC		 17048 dev_err(&tp->pdev->dev,
17049 "%s: Buffer corrupted on read back! "
17050 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17051 ret = -ENODEV;
17052 goto out;
17053 }
17054 }
17055
17056 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17057 /* Success. */
17058 ret = 0;
17059 break;
17060 }
17061 }
59e6b434
DM		 17062 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17063 DMA_RWCTRL_WRITE_BNDRY_16) {
17064 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17065 * now look for chipsets that are known to expose the
17066 * DMA bug without failing the test.
59e6b434 17067 */
4143470c 17068 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17069 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17070 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17071 } else {
6d1cfbab
MC		 17072 /* Safe to use the calculated DMA boundary. */
17073 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17074 }
6d1cfbab 17075
59e6b434
DM		 17076 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17077 }
1da177e4
LT		 17078
17079out:
4bae65c8 17080 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17081out_nofree:
17082 return ret;
17083}
17084
229b1ad1 17085static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17086{
63c3a66f 17087 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17088 tp->bufmgr_config.mbuf_read_dma_low_water =
17089 DEFAULT_MB_RDMA_LOW_WATER_5705;
17090 tp->bufmgr_config.mbuf_mac_rx_low_water =
17091 DEFAULT_MB_MACRX_LOW_WATER_57765;
17092 tp->bufmgr_config.mbuf_high_water =
17093 DEFAULT_MB_HIGH_WATER_57765;
17094
17095 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17096 DEFAULT_MB_RDMA_LOW_WATER_5705;
17097 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17098 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17099 tp->bufmgr_config.mbuf_high_water_jumbo =
17100 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17101 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17102 tp->bufmgr_config.mbuf_read_dma_low_water =
17103 DEFAULT_MB_RDMA_LOW_WATER_5705;
17104 tp->bufmgr_config.mbuf_mac_rx_low_water =
17105 DEFAULT_MB_MACRX_LOW_WATER_5705;
17106 tp->bufmgr_config.mbuf_high_water =
17107 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17108 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17109 tp->bufmgr_config.mbuf_mac_rx_low_water =
17110 DEFAULT_MB_MACRX_LOW_WATER_5906;
17111 tp->bufmgr_config.mbuf_high_water =
17112 DEFAULT_MB_HIGH_WATER_5906;
17113 }
fdfec172
MC		 17114
17115 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17116 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17117 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17118 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17119 tp->bufmgr_config.mbuf_high_water_jumbo =
17120 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17121 } else {
17122 tp->bufmgr_config.mbuf_read_dma_low_water =
17123 DEFAULT_MB_RDMA_LOW_WATER;
17124 tp->bufmgr_config.mbuf_mac_rx_low_water =
17125 DEFAULT_MB_MACRX_LOW_WATER;
17126 tp->bufmgr_config.mbuf_high_water =
17127 DEFAULT_MB_HIGH_WATER;
17128
17129 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17130 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17131 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17132 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17133 tp->bufmgr_config.mbuf_high_water_jumbo =
17134 DEFAULT_MB_HIGH_WATER_JUMBO;
17135 }
1da177e4
LT		 17136
17137 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17138 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17139}
17140
229b1ad1 17141static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17142{
79eb6904
MC		 17143 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17144 case TG3_PHY_ID_BCM5400: return "5400";
17145 case TG3_PHY_ID_BCM5401: return "5401";
17146 case TG3_PHY_ID_BCM5411: return "5411";
17147 case TG3_PHY_ID_BCM5701: return "5701";
17148 case TG3_PHY_ID_BCM5703: return "5703";
17149 case TG3_PHY_ID_BCM5704: return "5704";
17150 case TG3_PHY_ID_BCM5705: return "5705";
17151 case TG3_PHY_ID_BCM5750: return "5750";
17152 case TG3_PHY_ID_BCM5752: return "5752";
17153 case TG3_PHY_ID_BCM5714: return "5714";
17154 case TG3_PHY_ID_BCM5780: return "5780";
17155 case TG3_PHY_ID_BCM5755: return "5755";
17156 case TG3_PHY_ID_BCM5787: return "5787";
17157 case TG3_PHY_ID_BCM5784: return "5784";
17158 case TG3_PHY_ID_BCM5756: return "5722/5756";
17159 case TG3_PHY_ID_BCM5906: return "5906";
17160 case TG3_PHY_ID_BCM5761: return "5761";
17161 case TG3_PHY_ID_BCM5718C: return "5718C";
17162 case TG3_PHY_ID_BCM5718S: return "5718S";
17163 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17164 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17165 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17166 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17167 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17168 case 0: return "serdes";
17169 default: return "unknown";
855e1111 17170 }
1da177e4
LT		 17171}
17172
229b1ad1 17173static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17174{
63c3a66f 17175 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17176 strcpy(str, "PCI Express");
17177 return str;
63c3a66f 17178 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17179 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17180
17181 strcpy(str, "PCIX:");
17182
17183 if ((clock_ctrl == 7) ||
17184 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17185 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17186 strcat(str, "133MHz");
17187 else if (clock_ctrl == 0)
17188 strcat(str, "33MHz");
17189 else if (clock_ctrl == 2)
17190 strcat(str, "50MHz");
17191 else if (clock_ctrl == 4)
17192 strcat(str, "66MHz");
17193 else if (clock_ctrl == 6)
17194 strcat(str, "100MHz");
f9804ddb
MC		 17195 } else {
17196 strcpy(str, "PCI:");
63c3a66f 17197 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17198 strcat(str, "66MHz");
17199 else
17200 strcat(str, "33MHz");
17201 }
63c3a66f 17202 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17203 strcat(str, ":32-bit");
17204 else
17205 strcat(str, ":64-bit");
17206 return str;
17207}
17208
229b1ad1 17209static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17210{
17211 struct ethtool_coalesce *ec = &tp->coal;
17212
17213 memset(ec, 0, sizeof(*ec));
17214 ec->cmd = ETHTOOL_GCOALESCE;
17215 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17216 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17217 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17218 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17219 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17220 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17221 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17222 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17223 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17224
17225 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17226 HOSTCC_MODE_CLRTICK_TXBD)) {
17227 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17228 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17229 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17230 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17231 }
d244c892 17232
63c3a66f 17233 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17234 ec->rx_coalesce_usecs_irq = 0;
17235 ec->tx_coalesce_usecs_irq = 0;
17236 ec->stats_block_coalesce_usecs = 0;
17237 }
15f9850d
DM		 17238}
17239
229b1ad1 17240static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17241 const struct pci_device_id *ent)
17242{
1da177e4
LT		 17243 struct net_device *dev;
17244 struct tg3 *tp;
5865fc1b 17245 int i, err;
646c9edd 17246 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17247 char str[40];
72f2afb8 17248 u64 dma_mask, persist_dma_mask;
c8f44aff 17249 netdev_features_t features = 0;
1da177e4 17250
05dbe005 17251 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17252
17253 err = pci_enable_device(pdev);
17254 if (err) {
2445e461 17255 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17256 return err;
17257 }
17258
1da177e4
LT		 17259 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17260 if (err) {
2445e461 17261 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17262 goto err_out_disable_pdev;
17263 }
17264
17265 pci_set_master(pdev);
17266
fe5f5787 17267 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17268 if (!dev) {
1da177e4 17269 err = -ENOMEM;
5865fc1b 17270 goto err_out_free_res;
1da177e4
LT		 17271 }
17272
1da177e4
LT		 17273 SET_NETDEV_DEV(dev, &pdev->dev);
17274
1da177e4
LT		 17275 tp = netdev_priv(dev);
17276 tp->pdev = pdev;
17277 tp->dev = dev;
5865fc1b 17278 tp->pm_cap = pdev->pm_cap;
1da177e4
LT		 17279 tp->rx_mode = TG3_DEF_RX_MODE;
17280 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17281 tp->irq_sync = 1;
8ef21428 17282
1da177e4
LT		 17283 if (tg3_debug > 0)
17284 tp->msg_enable = tg3_debug;
17285 else
17286 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17287
7e6c63f0
HM		 17288 if (pdev_is_ssb_gige_core(pdev)) {
17289 tg3_flag_set(tp, IS_SSB_CORE);
17290 if (ssb_gige_must_flush_posted_writes(pdev))
17291 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17292 if (ssb_gige_one_dma_at_once(pdev))
17293 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17294 if (ssb_gige_have_roboswitch(pdev))
17295 tg3_flag_set(tp, ROBOSWITCH);
17296 if (ssb_gige_is_rgmii(pdev))
17297 tg3_flag_set(tp, RGMII_MODE);
17298 }
17299
1da177e4
LT		 17300 /* The word/byte swap controls here control register access byte
17301 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17302 * setting below.
17303 */
17304 tp->misc_host_ctrl =
17305 MISC_HOST_CTRL_MASK_PCI_INT |
17306 MISC_HOST_CTRL_WORD_SWAP |
17307 MISC_HOST_CTRL_INDIR_ACCESS |
17308 MISC_HOST_CTRL_PCISTATE_RW;
17309
17310 /* The NONFRM (non-frame) byte/word swap controls take effect
17311 * on descriptor entries, anything which isn't packet data.
17312 *
17313 * The StrongARM chips on the board (one for tx, one for rx)
17314 * are running in big-endian mode.
17315 */
17316 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17317 GRC_MODE_WSWAP_NONFRM_DATA);
17318#ifdef __BIG_ENDIAN
17319 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17320#endif
17321 spin_lock_init(&tp->lock);
1da177e4 17322 spin_lock_init(&tp->indirect_lock);
c4028958 17323 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17324
d5fe488a 17325 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17326 if (!tp->regs) {
ab96b241 17327 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17328 err = -ENOMEM;
17329 goto err_out_free_dev;
17330 }
17331
c9cab24e
MC		 17332 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17333 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17334 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17335 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17336 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17337 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17338 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17339 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4
MC		 17340 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17341 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17342 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17343 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727) {
c9cab24e
MC		 17344 tg3_flag_set(tp, ENABLE_APE);
17345 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17346 if (!tp->aperegs) {
17347 dev_err(&pdev->dev,
17348 "Cannot map APE registers, aborting\n");
17349 err = -ENOMEM;
17350 goto err_out_iounmap;
17351 }
17352 }
17353
1da177e4
LT		 17354 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17355 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17356
1da177e4 17357 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17358 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17359 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17360 dev->irq = pdev->irq;
1da177e4 17361
3d567e0e 17362 err = tg3_get_invariants(tp, ent);
1da177e4 17363 if (err) {
ab96b241
MC		 17364 dev_err(&pdev->dev,
17365 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17366 goto err_out_apeunmap;
1da177e4
LT		 17367 }
17368
4a29cc2e
MC		 17369 /* The EPB bridge inside 5714, 5715, and 5780 and any
17370 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17371 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17372 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17373 * do DMA address check in tg3_start_xmit().
17374 */
63c3a66f 17375 if (tg3_flag(tp, IS_5788))
284901a9 17376 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17377 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17378 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17379#ifdef CONFIG_HIGHMEM
6a35528a 17380 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17381#endif
4a29cc2e 17382 } else
6a35528a 17383 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17384
17385 /* Configure DMA attributes. */
284901a9 17386 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17387 err = pci_set_dma_mask(pdev, dma_mask);
17388 if (!err) {
0da0606f 17389 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17390 err = pci_set_consistent_dma_mask(pdev,
17391 persist_dma_mask);
17392 if (err < 0) {
ab96b241
MC		 17393 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17394 "DMA for consistent allocations\n");
c9cab24e 17395 goto err_out_apeunmap;
72f2afb8
MC		 17396 }
17397 }
17398 }
284901a9
YH		 17399 if (err || dma_mask == DMA_BIT_MASK(32)) {
17400 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17401 if (err) {
ab96b241
MC		 17402 dev_err(&pdev->dev,
17403 "No usable DMA configuration, aborting\n");
c9cab24e 17404 goto err_out_apeunmap;
72f2afb8
MC		 17405 }
17406 }
17407
fdfec172 17408 tg3_init_bufmgr_config(tp);
1da177e4 17409
f646968f 17410 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
0da0606f
MC		 17411
17412 /* 5700 B0 chips do not support checksumming correctly due
17413 * to hardware bugs.
17414 */
4153577a 17415 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17416 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17417
17418 if (tg3_flag(tp, 5755_PLUS))
17419 features |= NETIF_F_IPV6_CSUM;
17420 }
17421
4e3a7aaa
MC		 17422 /* TSO is on by default on chips that support hardware TSO.
17423 * Firmware TSO on older chips gives lower performance, so it
17424 * is off by default, but can be enabled using ethtool.
17425 */
63c3a66f
JP		 17426 if ((tg3_flag(tp, HW_TSO_1) ||
17427 tg3_flag(tp, HW_TSO_2) ||
17428 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17429 (features & NETIF_F_IP_CSUM))
17430 features |= NETIF_F_TSO;
63c3a66f 17431 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17432 if (features & NETIF_F_IPV6_CSUM)
17433 features |= NETIF_F_TSO6;
63c3a66f 17434 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17435 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17436 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17437 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17438 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17439 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17440 features |= NETIF_F_TSO_ECN;
b0026624 17441 }
1da177e4 17442
d542fe27
MC		 17443 dev->features |= features;
17444 dev->vlan_features |= features;
17445
06c03c02
MB		 17446 /*
17447 * Add loopback capability only for a subset of devices that support
17448 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17449 * loopback for the remaining devices.
17450 */
4153577a 17451 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17452 !tg3_flag(tp, CPMU_PRESENT))
17453 /* Add the loopback capability */
0da0606f
MC		 17454 features |= NETIF_F_LOOPBACK;
17455
0da0606f 17456 dev->hw_features |= features;
06c03c02 17457
4153577a 17458 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17459 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17460 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17461 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17462 tp->rx_pending = 63;
17463 }
17464
1da177e4
LT		 17465 err = tg3_get_device_address(tp);
17466 if (err) {
ab96b241
MC		 17467 dev_err(&pdev->dev,
17468 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17469 goto err_out_apeunmap;
c88864df
MC		 17470 }
17471
1da177e4
LT		 17472 /*
17473 * Reset chip in case UNDI or EFI driver did not shutdown
17474 * DMA self test will enable WDMAC and we'll see (spurious)
17475 * pending DMA on the PCI bus at that point.
17476 */
17477 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17478 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17479 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17480 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17481 }
17482
17483 err = tg3_test_dma(tp);
17484 if (err) {
ab96b241 17485 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17486 goto err_out_apeunmap;
1da177e4
LT		 17487 }
17488
78f90dcf
MC		 17489 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17490 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17491 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17492 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17493 struct tg3_napi *tnapi = &tp->napi[i];
17494
17495 tnapi->tp = tp;
17496 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17497
17498 tnapi->int_mbox = intmbx;
93a700a9 17499 if (i <= 4)
78f90dcf
MC		 17500 intmbx += 0x8;
17501 else
17502 intmbx += 0x4;
17503
17504 tnapi->consmbox = rcvmbx;
17505 tnapi->prodmbox = sndmbx;
17506
66cfd1bd 17507 if (i)
78f90dcf 17508 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17509 else
78f90dcf 17510 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17511
63c3a66f 17512 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17513 break;
17514
17515 /*
17516 * If we support MSIX, we'll be using RSS. If we're using
17517 * RSS, the first vector only handles link interrupts and the
17518 * remaining vectors handle rx and tx interrupts. Reuse the
17519 * mailbox values for the next iteration. The values we setup
17520 * above are still useful for the single vectored mode.
17521 */
17522 if (!i)
17523 continue;
17524
17525 rcvmbx += 0x8;
17526
17527 if (sndmbx & 0x4)
17528 sndmbx -= 0x4;
17529 else
17530 sndmbx += 0xc;
17531 }
17532
15f9850d
DM		 17533 tg3_init_coal(tp);
17534
c49a1561
MC		 17535 pci_set_drvdata(pdev, dev);
17536
4153577a
JP		 17537 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17538 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17539 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17540 tg3_flag_set(tp, PTP_CAPABLE);
17541
21f7638e
MC		 17542 tg3_timer_init(tp);
17543
402e1398
MC		 17544 tg3_carrier_off(tp);
17545
1da177e4
LT		 17546 err = register_netdev(dev);
17547 if (err) {
ab96b241 17548 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17549 goto err_out_apeunmap;
1da177e4
LT		 17550 }
17551
05dbe005
JP		 17552 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17553 tp->board_part_number,
4153577a 17554 tg3_chip_rev_id(tp),
05dbe005
JP		 17555 tg3_bus_string(tp, str),
17556 dev->dev_addr);
1da177e4 17557
f07e9af3 17558 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7
MC		 17559 struct phy_device *phydev;
17560 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
5129c3a3
MC		 17561 netdev_info(dev,
17562 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17563 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17564 } else {
17565 char *ethtype;
17566
17567 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17568 ethtype = "10/100Base-TX";
17569 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17570 ethtype = "1000Base-SX";
17571 else
17572 ethtype = "10/100/1000Base-T";
17573
5129c3a3 17574 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17575 "(WireSpeed[%d], EEE[%d])\n",
17576 tg3_phy_string(tp), ethtype,
17577 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17578 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17579 }
05dbe005
JP		 17580
17581 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17582 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17583 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17584 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17585 tg3_flag(tp, ENABLE_ASF) != 0,
17586 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17587 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17588 tp->dma_rwctrl,
17589 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17590 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17591
b45aa2f6
MC		 17592 pci_save_state(pdev);
17593
1da177e4
LT		 17594 return 0;
17595
0d3031d9
MC		 17596err_out_apeunmap:
17597 if (tp->aperegs) {
17598 iounmap(tp->aperegs);
17599 tp->aperegs = NULL;
17600 }
17601
1da177e4 17602err_out_iounmap:
6892914f
MC		 17603 if (tp->regs) {
17604 iounmap(tp->regs);
22abe310 17605 tp->regs = NULL;
6892914f 17606 }
1da177e4
LT		 17607
17608err_out_free_dev:
17609 free_netdev(dev);
17610
17611err_out_free_res:
17612 pci_release_regions(pdev);
17613
17614err_out_disable_pdev:
17615 pci_disable_device(pdev);
17616 pci_set_drvdata(pdev, NULL);
17617 return err;
17618}
17619
229b1ad1 17620static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17621{
17622 struct net_device *dev = pci_get_drvdata(pdev);
17623
17624 if (dev) {
17625 struct tg3 *tp = netdev_priv(dev);
17626
e3c5530b 17627 release_firmware(tp->fw);
077f849d 17628
db219973 17629 tg3_reset_task_cancel(tp);
158d7abd 17630
e730c823 17631 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17632 tg3_phy_fini(tp);
158d7abd 17633 tg3_mdio_fini(tp);
b02fd9e3 17634 }
158d7abd 17635
1da177e4 17636 unregister_netdev(dev);
0d3031d9
MC		 17637 if (tp->aperegs) {
17638 iounmap(tp->aperegs);
17639 tp->aperegs = NULL;
17640 }
6892914f
MC		 17641 if (tp->regs) {
17642 iounmap(tp->regs);
22abe310 17643 tp->regs = NULL;
6892914f 17644 }
1da177e4
LT		 17645 free_netdev(dev);
17646 pci_release_regions(pdev);
17647 pci_disable_device(pdev);
17648 pci_set_drvdata(pdev, NULL);
17649 }
17650}
17651
aa6027ca 17652#ifdef CONFIG_PM_SLEEP
c866b7ea 17653static int tg3_suspend(struct device *device)
1da177e4 17654{
c866b7ea 17655 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17656 struct net_device *dev = pci_get_drvdata(pdev);
17657 struct tg3 *tp = netdev_priv(dev);
17658 int err;
17659
17660 if (!netif_running(dev))
17661 return 0;
17662
db219973 17663 tg3_reset_task_cancel(tp);
b02fd9e3 17664 tg3_phy_stop(tp);
1da177e4
LT		 17665 tg3_netif_stop(tp);
17666
21f7638e 17667 tg3_timer_stop(tp);
1da177e4 17668
f47c11ee 17669 tg3_full_lock(tp, 1);
1da177e4 17670 tg3_disable_ints(tp);
f47c11ee 17671 tg3_full_unlock(tp);
1da177e4
LT		 17672
17673 netif_device_detach(dev);
17674
f47c11ee 17675 tg3_full_lock(tp, 0);
944d980e 17676 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17677 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17678 tg3_full_unlock(tp);
1da177e4 17679
c866b7ea 17680 err = tg3_power_down_prepare(tp);
1da177e4 17681 if (err) {
b02fd9e3
MC		 17682 int err2;
17683
f47c11ee 17684 tg3_full_lock(tp, 0);
1da177e4 17685
63c3a66f 17686 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17687 err2 = tg3_restart_hw(tp, true);
b02fd9e3 17688 if (err2)
b9ec6c1b 17689 goto out;
1da177e4 17690
21f7638e 17691 tg3_timer_start(tp);
1da177e4
LT		 17692
17693 netif_device_attach(dev);
17694 tg3_netif_start(tp);
17695
b9ec6c1b 17696out:
f47c11ee 17697 tg3_full_unlock(tp);
b02fd9e3
MC		 17698
17699 if (!err2)
17700 tg3_phy_start(tp);
1da177e4
LT		 17701 }
17702
17703 return err;
17704}
17705
c866b7ea 17706static int tg3_resume(struct device *device)
1da177e4 17707{
c866b7ea 17708 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17709 struct net_device *dev = pci_get_drvdata(pdev);
17710 struct tg3 *tp = netdev_priv(dev);
17711 int err;
17712
17713 if (!netif_running(dev))
17714 return 0;
17715
1da177e4
LT		 17716 netif_device_attach(dev);
17717
f47c11ee 17718 tg3_full_lock(tp, 0);
1da177e4 17719
2e460fc0
NS		 17720 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17721
63c3a66f 17722 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 17723 err = tg3_restart_hw(tp,
17724 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 17725 if (err)
17726 goto out;
1da177e4 17727
21f7638e 17728 tg3_timer_start(tp);
1da177e4 17729
1da177e4
LT		 17730 tg3_netif_start(tp);
17731
b9ec6c1b 17732out:
f47c11ee 17733 tg3_full_unlock(tp);
1da177e4 17734
b02fd9e3
MC		 17735 if (!err)
17736 tg3_phy_start(tp);
17737
b9ec6c1b 17738 return err;
1da177e4 17739}
42df36a6 17740#endif /* CONFIG_PM_SLEEP */
1da177e4 17741
c866b7ea
RW		 17742static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17743
4c305fa2
NS		 17744static void tg3_shutdown(struct pci_dev *pdev)
17745{
17746 struct net_device *dev = pci_get_drvdata(pdev);
17747 struct tg3 *tp = netdev_priv(dev);
17748
17749 rtnl_lock();
17750 netif_device_detach(dev);
17751
17752 if (netif_running(dev))
17753 dev_close(dev);
17754
17755 if (system_state == SYSTEM_POWER_OFF)
17756 tg3_power_down(tp);
17757
17758 rtnl_unlock();
17759}
17760
b45aa2f6
MC		 17761/**
17762 * tg3_io_error_detected - called when PCI error is detected
17763 * @pdev: Pointer to PCI device
17764 * @state: The current pci connection state
17765 *
17766 * This function is called after a PCI bus error affecting
17767 * this device has been detected.
17768 */
17769static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
17770 pci_channel_state_t state)
17771{
17772 struct net_device *netdev = pci_get_drvdata(pdev);
17773 struct tg3 *tp = netdev_priv(netdev);
17774 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
17775
17776 netdev_info(netdev, "PCI I/O error detected\n");
17777
17778 rtnl_lock();
17779
17780 if (!netif_running(netdev))
17781 goto done;
17782
17783 tg3_phy_stop(tp);
17784
17785 tg3_netif_stop(tp);
17786
21f7638e 17787 tg3_timer_stop(tp);
b45aa2f6
MC		 17788
17789 /* Want to make sure that the reset task doesn't run */
db219973 17790 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 17791
17792 netif_device_detach(netdev);
17793
17794 /* Clean up software state, even if MMIO is blocked */
17795 tg3_full_lock(tp, 0);
17796 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
17797 tg3_full_unlock(tp);
17798
17799done:
72bb72b0
MC		 17800 if (state == pci_channel_io_perm_failure) {
17801 tg3_napi_enable(tp);
17802 dev_close(netdev);
b45aa2f6 17803 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 17804 } else {
b45aa2f6 17805 pci_disable_device(pdev);
72bb72b0 17806 }
b45aa2f6
MC		 17807
17808 rtnl_unlock();
17809
17810 return err;
17811}
17812
17813/**
17814 * tg3_io_slot_reset - called after the pci bus has been reset.
17815 * @pdev: Pointer to PCI device
17816 *
17817 * Restart the card from scratch, as if from a cold-boot.
17818 * At this point, the card has exprienced a hard reset,
17819 * followed by fixups by BIOS, and has its config space
17820 * set up identically to what it was at cold boot.
17821 */
17822static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
17823{
17824 struct net_device *netdev = pci_get_drvdata(pdev);
17825 struct tg3 *tp = netdev_priv(netdev);
17826 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
17827 int err;
17828
17829 rtnl_lock();
17830
17831 if (pci_enable_device(pdev)) {
17832 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
17833 goto done;
17834 }
17835
17836 pci_set_master(pdev);
17837 pci_restore_state(pdev);
17838 pci_save_state(pdev);
17839
17840 if (!netif_running(netdev)) {
17841 rc = PCI_ERS_RESULT_RECOVERED;
17842 goto done;
17843 }
17844
17845 err = tg3_power_up(tp);
bed9829f 17846 if (err)
b45aa2f6 17847 goto done;
b45aa2f6
MC		 17848
17849 rc = PCI_ERS_RESULT_RECOVERED;
17850
17851done:
72bb72b0
MC		 17852 if (rc != PCI_ERS_RESULT_RECOVERED && netif_running(netdev)) {
17853 tg3_napi_enable(tp);
17854 dev_close(netdev);
17855 }
b45aa2f6
MC		 17856 rtnl_unlock();
17857
17858 return rc;
17859}
17860
17861/**
17862 * tg3_io_resume - called when traffic can start flowing again.
17863 * @pdev: Pointer to PCI device
17864 *
17865 * This callback is called when the error recovery driver tells
17866 * us that its OK to resume normal operation.
17867 */
17868static void tg3_io_resume(struct pci_dev *pdev)
17869{
17870 struct net_device *netdev = pci_get_drvdata(pdev);
17871 struct tg3 *tp = netdev_priv(netdev);
17872 int err;
17873
17874 rtnl_lock();
17875
17876 if (!netif_running(netdev))
17877 goto done;
17878
17879 tg3_full_lock(tp, 0);
2e460fc0 17880 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 17881 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17882 err = tg3_restart_hw(tp, true);
b45aa2f6 17883 if (err) {
35763066 17884 tg3_full_unlock(tp);
b45aa2f6
MC		 17885 netdev_err(netdev, "Cannot restart hardware after reset.\n");
17886 goto done;
17887 }
17888
17889 netif_device_attach(netdev);
17890
21f7638e 17891 tg3_timer_start(tp);
b45aa2f6
MC		 17892
17893 tg3_netif_start(tp);
17894
35763066
NNS		 17895 tg3_full_unlock(tp);
17896
b45aa2f6
MC		 17897 tg3_phy_start(tp);
17898
17899done:
17900 rtnl_unlock();
17901}
17902
3646f0e5 17903static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 17904 .error_detected = tg3_io_error_detected,
17905 .slot_reset = tg3_io_slot_reset,
17906 .resume = tg3_io_resume
17907};
17908
1da177e4
LT		 17909static struct pci_driver tg3_driver = {
17910 .name = DRV_MODULE_NAME,
17911 .id_table = tg3_pci_tbl,
17912 .probe = tg3_init_one,
229b1ad1 17913 .remove = tg3_remove_one,
b45aa2f6 17914 .err_handler = &tg3_err_handler,
42df36a6 17915 .driver.pm = &tg3_pm_ops,
4c305fa2 17916 .shutdown = tg3_shutdown,
1da177e4
LT		 17917};
17918
8dbb0dc2 17919module_pci_driver(tg3_driver);
Linux 6.x block layer and io_uring tree(s)