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net: phy: adjust fixed_phy_register() return value
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
45
46#include <asm/unaligned.h>
47
48#include "bcmgenet.h"
49
50/* Maximum number of hardware queues, downsized if needed */
51#define GENET_MAX_MQ_CNT 4
52
53/* Default highest priority queue for multi queue support */
54#define GENET_Q0_PRIORITY 0
55
56#define GENET_DEFAULT_BD_CNT \
57 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
58
59#define RX_BUF_LENGTH 2048
60#define SKB_ALIGNMENT 32
61
62/* Tx/Rx DMA register offset, skip 256 descriptors */
63#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
64#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
65
66#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
67 TOTAL_DESC * DMA_DESC_SIZE)
68
69#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 73 void __iomem *d, u32 value)
1c1008c7
FF		 74{
75 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
76}
77
78static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 79 void __iomem *d)
1c1008c7
FF		 80{
81 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
82}
83
84static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
85 void __iomem *d,
86 dma_addr_t addr)
87{
88 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
89
90 /* Register writes to GISB bus can take couple hundred nanoseconds
91 * and are done for each packet, save these expensive writes unless
7fc527f9 92 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 93 */
94#ifdef CONFIG_PHYS_ADDR_T_64BIT
95 if (priv->hw_params->flags & GENET_HAS_40BITS)
96 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
97#endif
98}
99
100/* Combined address + length/status setter */
101static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 102 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 103{
104 dmadesc_set_length_status(priv, d, val);
105 dmadesc_set_addr(priv, d, addr);
106}
107
108static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
109 void __iomem *d)
110{
111 dma_addr_t addr;
112
113 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
114
115 /* Register writes to GISB bus can take couple hundred nanoseconds
116 * and are done for each packet, save these expensive writes unless
7fc527f9 117 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 118 */
119#ifdef CONFIG_PHYS_ADDR_T_64BIT
120 if (priv->hw_params->flags & GENET_HAS_40BITS)
121 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
122#endif
123 return addr;
124}
125
126#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
127
128#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
129 NETIF_MSG_LINK)
130
131static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
132{
133 if (GENET_IS_V1(priv))
134 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
135 else
136 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
137}
138
139static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
140{
141 if (GENET_IS_V1(priv))
142 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
143 else
144 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
145}
146
147/* These macros are defined to deal with register map change
148 * between GENET1.1 and GENET2. Only those currently being used
149 * by driver are defined.
150 */
151static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
152{
153 if (GENET_IS_V1(priv))
154 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
155 else
156 return __raw_readl(priv->base +
157 priv->hw_params->tbuf_offset + TBUF_CTRL);
158}
159
160static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
161{
162 if (GENET_IS_V1(priv))
163 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
164 else
165 __raw_writel(val, priv->base +
166 priv->hw_params->tbuf_offset + TBUF_CTRL);
167}
168
169static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
170{
171 if (GENET_IS_V1(priv))
172 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
173 else
174 return __raw_readl(priv->base +
175 priv->hw_params->tbuf_offset + TBUF_BP_MC);
176}
177
178static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
179{
180 if (GENET_IS_V1(priv))
181 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
182 else
183 __raw_writel(val, priv->base +
184 priv->hw_params->tbuf_offset + TBUF_BP_MC);
185}
186
187/* RX/TX DMA register accessors */
188enum dma_reg {
189 DMA_RING_CFG = 0,
190 DMA_CTRL,
191 DMA_STATUS,
192 DMA_SCB_BURST_SIZE,
193 DMA_ARB_CTRL,
194 DMA_PRIORITY,
195 DMA_RING_PRIORITY,
196};
197
198static const u8 bcmgenet_dma_regs_v3plus[] = {
199 [DMA_RING_CFG] = 0x00,
200 [DMA_CTRL] = 0x04,
201 [DMA_STATUS] = 0x08,
202 [DMA_SCB_BURST_SIZE] = 0x0C,
203 [DMA_ARB_CTRL] = 0x2C,
204 [DMA_PRIORITY] = 0x30,
205 [DMA_RING_PRIORITY] = 0x38,
206};
207
208static const u8 bcmgenet_dma_regs_v2[] = {
209 [DMA_RING_CFG] = 0x00,
210 [DMA_CTRL] = 0x04,
211 [DMA_STATUS] = 0x08,
212 [DMA_SCB_BURST_SIZE] = 0x0C,
213 [DMA_ARB_CTRL] = 0x30,
214 [DMA_PRIORITY] = 0x34,
215 [DMA_RING_PRIORITY] = 0x3C,
216};
217
218static const u8 bcmgenet_dma_regs_v1[] = {
219 [DMA_CTRL] = 0x00,
220 [DMA_STATUS] = 0x04,
221 [DMA_SCB_BURST_SIZE] = 0x0C,
222 [DMA_ARB_CTRL] = 0x30,
223 [DMA_PRIORITY] = 0x34,
224 [DMA_RING_PRIORITY] = 0x3C,
225};
226
227/* Set at runtime once bcmgenet version is known */
228static const u8 *bcmgenet_dma_regs;
229
230static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
231{
232 return netdev_priv(dev_get_drvdata(dev));
233}
234
235static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 236 enum dma_reg r)
1c1008c7
FF		 237{
238 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
239 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
240}
241
242static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
243 u32 val, enum dma_reg r)
244{
245 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
246 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
247}
248
249static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 250 enum dma_reg r)
1c1008c7
FF		 251{
252 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
253 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
254}
255
256static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
257 u32 val, enum dma_reg r)
258{
259 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
260 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
261}
262
263/* RDMA/TDMA ring registers and accessors
264 * we merge the common fields and just prefix with T/D the registers
265 * having different meaning depending on the direction
266 */
267enum dma_ring_reg {
268 TDMA_READ_PTR = 0,
269 RDMA_WRITE_PTR = TDMA_READ_PTR,
270 TDMA_READ_PTR_HI,
271 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
272 TDMA_CONS_INDEX,
273 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
274 TDMA_PROD_INDEX,
275 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
276 DMA_RING_BUF_SIZE,
277 DMA_START_ADDR,
278 DMA_START_ADDR_HI,
279 DMA_END_ADDR,
280 DMA_END_ADDR_HI,
281 DMA_MBUF_DONE_THRESH,
282 TDMA_FLOW_PERIOD,
283 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
284 TDMA_WRITE_PTR,
285 RDMA_READ_PTR = TDMA_WRITE_PTR,
286 TDMA_WRITE_PTR_HI,
287 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
288};
289
290/* GENET v4 supports 40-bits pointer addressing
291 * for obvious reasons the LO and HI word parts
292 * are contiguous, but this offsets the other
293 * registers.
294 */
295static const u8 genet_dma_ring_regs_v4[] = {
296 [TDMA_READ_PTR] = 0x00,
297 [TDMA_READ_PTR_HI] = 0x04,
298 [TDMA_CONS_INDEX] = 0x08,
299 [TDMA_PROD_INDEX] = 0x0C,
300 [DMA_RING_BUF_SIZE] = 0x10,
301 [DMA_START_ADDR] = 0x14,
302 [DMA_START_ADDR_HI] = 0x18,
303 [DMA_END_ADDR] = 0x1C,
304 [DMA_END_ADDR_HI] = 0x20,
305 [DMA_MBUF_DONE_THRESH] = 0x24,
306 [TDMA_FLOW_PERIOD] = 0x28,
307 [TDMA_WRITE_PTR] = 0x2C,
308 [TDMA_WRITE_PTR_HI] = 0x30,
309};
310
311static const u8 genet_dma_ring_regs_v123[] = {
312 [TDMA_READ_PTR] = 0x00,
313 [TDMA_CONS_INDEX] = 0x04,
314 [TDMA_PROD_INDEX] = 0x08,
315 [DMA_RING_BUF_SIZE] = 0x0C,
316 [DMA_START_ADDR] = 0x10,
317 [DMA_END_ADDR] = 0x14,
318 [DMA_MBUF_DONE_THRESH] = 0x18,
319 [TDMA_FLOW_PERIOD] = 0x1C,
320 [TDMA_WRITE_PTR] = 0x20,
321};
322
323/* Set at runtime once GENET version is known */
324static const u8 *genet_dma_ring_regs;
325
326static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 327 unsigned int ring,
328 enum dma_ring_reg r)
1c1008c7
FF		 329{
330 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
331 (DMA_RING_SIZE * ring) +
332 genet_dma_ring_regs[r]);
333}
334
335static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 336 unsigned int ring, u32 val,
337 enum dma_ring_reg r)
1c1008c7
FF		 338{
339 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
340 (DMA_RING_SIZE * ring) +
341 genet_dma_ring_regs[r]);
342}
343
344static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 345 unsigned int ring,
346 enum dma_ring_reg r)
1c1008c7
FF		 347{
348 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
349 (DMA_RING_SIZE * ring) +
350 genet_dma_ring_regs[r]);
351}
352
353static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 354 unsigned int ring, u32 val,
355 enum dma_ring_reg r)
1c1008c7
FF		 356{
357 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
358 (DMA_RING_SIZE * ring) +
359 genet_dma_ring_regs[r]);
360}
361
362static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 363 struct ethtool_cmd *cmd)
1c1008c7
FF		 364{
365 struct bcmgenet_priv *priv = netdev_priv(dev);
366
367 if (!netif_running(dev))
368 return -EINVAL;
369
370 if (!priv->phydev)
371 return -ENODEV;
372
373 return phy_ethtool_gset(priv->phydev, cmd);
374}
375
376static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 377 struct ethtool_cmd *cmd)
1c1008c7
FF		 378{
379 struct bcmgenet_priv *priv = netdev_priv(dev);
380
381 if (!netif_running(dev))
382 return -EINVAL;
383
384 if (!priv->phydev)
385 return -ENODEV;
386
387 return phy_ethtool_sset(priv->phydev, cmd);
388}
389
390static int bcmgenet_set_rx_csum(struct net_device *dev,
391 netdev_features_t wanted)
392{
393 struct bcmgenet_priv *priv = netdev_priv(dev);
394 u32 rbuf_chk_ctrl;
395 bool rx_csum_en;
396
397 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
398
399 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
400
401 /* enable rx checksumming */
402 if (rx_csum_en)
403 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
404 else
405 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
406 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 407
408 /* If UniMAC forwards CRC, we need to skip over it to get
409 * a valid CHK bit to be set in the per-packet status word
410 */
411 if (rx_csum_en && priv->crc_fwd_en)
412 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
413 else
414 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
415
1c1008c7
FF		 416 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
417
418 return 0;
419}
420
421static int bcmgenet_set_tx_csum(struct net_device *dev,
422 netdev_features_t wanted)
423{
424 struct bcmgenet_priv *priv = netdev_priv(dev);
425 bool desc_64b_en;
426 u32 tbuf_ctrl, rbuf_ctrl;
427
428 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
429 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
430
431 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
432
433 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
434 if (desc_64b_en) {
435 tbuf_ctrl |= RBUF_64B_EN;
436 rbuf_ctrl |= RBUF_64B_EN;
437 } else {
438 tbuf_ctrl &= ~RBUF_64B_EN;
439 rbuf_ctrl &= ~RBUF_64B_EN;
440 }
441 priv->desc_64b_en = desc_64b_en;
442
443 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
444 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
445
446 return 0;
447}
448
449static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 450 netdev_features_t features)
1c1008c7
FF		 451{
452 netdev_features_t changed = features ^ dev->features;
453 netdev_features_t wanted = dev->wanted_features;
454 int ret = 0;
455
456 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
457 ret = bcmgenet_set_tx_csum(dev, wanted);
458 if (changed & (NETIF_F_RXCSUM))
459 ret = bcmgenet_set_rx_csum(dev, wanted);
460
461 return ret;
462}
463
464static u32 bcmgenet_get_msglevel(struct net_device *dev)
465{
466 struct bcmgenet_priv *priv = netdev_priv(dev);
467
468 return priv->msg_enable;
469}
470
471static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
472{
473 struct bcmgenet_priv *priv = netdev_priv(dev);
474
475 priv->msg_enable = level;
476}
477
478/* standard ethtool support functions. */
479enum bcmgenet_stat_type {
480 BCMGENET_STAT_NETDEV = -1,
481 BCMGENET_STAT_MIB_RX,
482 BCMGENET_STAT_MIB_TX,
483 BCMGENET_STAT_RUNT,
484 BCMGENET_STAT_MISC,
485};
486
487struct bcmgenet_stats {
488 char stat_string[ETH_GSTRING_LEN];
489 int stat_sizeof;
490 int stat_offset;
491 enum bcmgenet_stat_type type;
492 /* reg offset from UMAC base for misc counters */
493 u16 reg_offset;
494};
495
496#define STAT_NETDEV(m) { \
497 .stat_string = __stringify(m), \
498 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
499 .stat_offset = offsetof(struct net_device_stats, m), \
500 .type = BCMGENET_STAT_NETDEV, \
501}
502
503#define STAT_GENET_MIB(str, m, _type) { \
504 .stat_string = str, \
505 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
506 .stat_offset = offsetof(struct bcmgenet_priv, m), \
507 .type = _type, \
508}
509
510#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
511#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
512#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
513
514#define STAT_GENET_MISC(str, m, offset) { \
515 .stat_string = str, \
516 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
517 .stat_offset = offsetof(struct bcmgenet_priv, m), \
518 .type = BCMGENET_STAT_MISC, \
519 .reg_offset = offset, \
520}
521
522
523/* There is a 0xC gap between the end of RX and beginning of TX stats and then
524 * between the end of TX stats and the beginning of the RX RUNT
525 */
526#define BCMGENET_STAT_OFFSET 0xc
527
528/* Hardware counters must be kept in sync because the order/offset
529 * is important here (order in structure declaration = order in hardware)
530 */
531static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
532 /* general stats */
533 STAT_NETDEV(rx_packets),
534 STAT_NETDEV(tx_packets),
535 STAT_NETDEV(rx_bytes),
536 STAT_NETDEV(tx_bytes),
537 STAT_NETDEV(rx_errors),
538 STAT_NETDEV(tx_errors),
539 STAT_NETDEV(rx_dropped),
540 STAT_NETDEV(tx_dropped),
541 STAT_NETDEV(multicast),
542 /* UniMAC RSV counters */
543 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
544 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
545 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
546 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
547 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
548 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
549 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
550 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
551 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
552 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
553 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
554 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
555 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
556 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
557 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
558 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
559 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
560 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
561 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
562 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
563 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
564 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
565 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
566 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
567 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
568 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
569 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
570 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
571 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
572 /* UniMAC TSV counters */
573 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
574 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
575 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
576 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
577 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
578 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
579 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
580 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
581 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
582 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
583 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
584 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
585 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
586 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
587 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
588 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
589 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
590 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
591 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
592 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
593 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
594 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
595 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
596 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
597 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
598 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
599 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
600 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
601 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
602 /* UniMAC RUNT counters */
603 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
604 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
605 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
606 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
607 /* Misc UniMAC counters */
608 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
609 UMAC_RBUF_OVFL_CNT),
610 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
611 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
612};
613
614#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
615
616static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 617 struct ethtool_drvinfo *info)
1c1008c7
FF		 618{
619 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
620 strlcpy(info->version, "v2.0", sizeof(info->version));
621 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 622}
623
624static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
625{
626 switch (string_set) {
627 case ETH_SS_STATS:
628 return BCMGENET_STATS_LEN;
629 default:
630 return -EOPNOTSUPP;
631 }
632}
633
c91b7f66
FF		 634static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
635 u8 *data)
1c1008c7
FF		 636{
637 int i;
638
639 switch (stringset) {
640 case ETH_SS_STATS:
641 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
642 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 643 bcmgenet_gstrings_stats[i].stat_string,
644 ETH_GSTRING_LEN);
1c1008c7
FF		 645 }
646 break;
647 }
648}
649
650static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
651{
652 int i, j = 0;
653
654 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
655 const struct bcmgenet_stats *s;
656 u8 offset = 0;
657 u32 val = 0;
658 char *p;
659
660 s = &bcmgenet_gstrings_stats[i];
661 switch (s->type) {
662 case BCMGENET_STAT_NETDEV:
663 continue;
664 case BCMGENET_STAT_MIB_RX:
665 case BCMGENET_STAT_MIB_TX:
666 case BCMGENET_STAT_RUNT:
667 if (s->type != BCMGENET_STAT_MIB_RX)
668 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 669 val = bcmgenet_umac_readl(priv,
670 UMAC_MIB_START + j + offset);
1c1008c7
FF		 671 break;
672 case BCMGENET_STAT_MISC:
673 val = bcmgenet_umac_readl(priv, s->reg_offset);
674 /* clear if overflowed */
675 if (val == ~0)
676 bcmgenet_umac_writel(priv, 0, s->reg_offset);
677 break;
678 }
679
680 j += s->stat_sizeof;
681 p = (char *)priv + s->stat_offset;
682 *(u32 *)p = val;
683 }
684}
685
686static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 687 struct ethtool_stats *stats,
688 u64 *data)
1c1008c7
FF		 689{
690 struct bcmgenet_priv *priv = netdev_priv(dev);
691 int i;
692
693 if (netif_running(dev))
694 bcmgenet_update_mib_counters(priv);
695
696 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
697 const struct bcmgenet_stats *s;
698 char *p;
699
700 s = &bcmgenet_gstrings_stats[i];
701 if (s->type == BCMGENET_STAT_NETDEV)
702 p = (char *)&dev->stats;
703 else
704 p = (char *)priv;
705 p += s->stat_offset;
706 data[i] = *(u32 *)p;
707 }
708}
709
710/* standard ethtool support functions. */
711static struct ethtool_ops bcmgenet_ethtool_ops = {
712 .get_strings = bcmgenet_get_strings,
713 .get_sset_count = bcmgenet_get_sset_count,
714 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
715 .get_settings = bcmgenet_get_settings,
716 .set_settings = bcmgenet_set_settings,
717 .get_drvinfo = bcmgenet_get_drvinfo,
718 .get_link = ethtool_op_get_link,
719 .get_msglevel = bcmgenet_get_msglevel,
720 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 721 .get_wol = bcmgenet_get_wol,
722 .set_wol = bcmgenet_set_wol,
1c1008c7
FF		 723};
724
725/* Power down the unimac, based on mode. */
726static void bcmgenet_power_down(struct bcmgenet_priv *priv,
727 enum bcmgenet_power_mode mode)
728{
729 u32 reg;
730
731 switch (mode) {
732 case GENET_POWER_CABLE_SENSE:
80d8e96d 733 phy_detach(priv->phydev);
1c1008c7
FF		 734 break;
735
c3ae64ae
FF		 736 case GENET_POWER_WOL_MAGIC:
737 bcmgenet_wol_power_down_cfg(priv, mode);
738 break;
739
1c1008c7
FF		 740 case GENET_POWER_PASSIVE:
741 /* Power down LED */
1c1008c7
FF		 742 if (priv->hw_params->flags & GENET_HAS_EXT) {
743 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
744 reg |= (EXT_PWR_DOWN_PHY |
745 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
746 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
747 }
748 break;
749 default:
750 break;
751 }
752}
753
754static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 755 enum bcmgenet_power_mode mode)
1c1008c7
FF		 756{
757 u32 reg;
758
759 if (!(priv->hw_params->flags & GENET_HAS_EXT))
760 return;
761
762 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
763
764 switch (mode) {
765 case GENET_POWER_PASSIVE:
766 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
767 EXT_PWR_DOWN_BIAS);
768 /* fallthrough */
769 case GENET_POWER_CABLE_SENSE:
770 /* enable APD */
771 reg |= EXT_PWR_DN_EN_LD;
772 break;
c3ae64ae
FF		 773 case GENET_POWER_WOL_MAGIC:
774 bcmgenet_wol_power_up_cfg(priv, mode);
775 return;
1c1008c7
FF		 776 default:
777 break;
778 }
779
780 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
cc013fb4
FF		 781
782 if (mode == GENET_POWER_PASSIVE)
783 bcmgenet_mii_reset(priv->dev);
1c1008c7
FF		 784}
785
786/* ioctl handle special commands that are not present in ethtool. */
787static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
788{
789 struct bcmgenet_priv *priv = netdev_priv(dev);
790 int val = 0;
791
792 if (!netif_running(dev))
793 return -EINVAL;
794
795 switch (cmd) {
796 case SIOCGMIIPHY:
797 case SIOCGMIIREG:
798 case SIOCSMIIREG:
799 if (!priv->phydev)
800 val = -ENODEV;
801 else
802 val = phy_mii_ioctl(priv->phydev, rq, cmd);
803 break;
804
805 default:
806 val = -EINVAL;
807 break;
808 }
809
810 return val;
811}
812
813static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
814 struct bcmgenet_tx_ring *ring)
815{
816 struct enet_cb *tx_cb_ptr;
817
818 tx_cb_ptr = ring->cbs;
819 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
820 tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
821 /* Advancing local write pointer */
822 if (ring->write_ptr == ring->end_ptr)
823 ring->write_ptr = ring->cb_ptr;
824 else
825 ring->write_ptr++;
826
827 return tx_cb_ptr;
828}
829
830/* Simple helper to free a control block's resources */
831static void bcmgenet_free_cb(struct enet_cb *cb)
832{
833 dev_kfree_skb_any(cb->skb);
834 cb->skb = NULL;
835 dma_unmap_addr_set(cb, dma_addr, 0);
836}
837
838static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
839 struct bcmgenet_tx_ring *ring)
840{
841 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 842 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
843 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 844}
845
846static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
847 struct bcmgenet_tx_ring *ring)
848{
849 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 850 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
851 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 852}
853
854static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
c91b7f66 855 struct bcmgenet_tx_ring *ring)
1c1008c7 856{
c91b7f66
FF		 857 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
858 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 859 priv->int1_mask &= ~(1 << ring->index);
860}
861
862static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
863 struct bcmgenet_tx_ring *ring)
864{
c91b7f66
FF		 865 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
866 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 867 priv->int1_mask |= (1 << ring->index);
868}
869
870/* Unlocked version of the reclaim routine */
871static void __bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 872 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 873{
874 struct bcmgenet_priv *priv = netdev_priv(dev);
875 int last_tx_cn, last_c_index, num_tx_bds;
876 struct enet_cb *tx_cb_ptr;
b2cde2cc 877 struct netdev_queue *txq;
478a010c 878 unsigned int bds_compl;
1c1008c7
FF		 879 unsigned int c_index;
880
7fc527f9 881 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 882 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
b2cde2cc 883 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 884
885 last_c_index = ring->c_index;
886 num_tx_bds = ring->size;
887
888 c_index &= (num_tx_bds - 1);
889
890 if (c_index >= last_c_index)
891 last_tx_cn = c_index - last_c_index;
892 else
893 last_tx_cn = num_tx_bds - last_c_index + c_index;
894
895 netif_dbg(priv, tx_done, dev,
c91b7f66
FF		 896 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
897 __func__, ring->index,
898 c_index, last_tx_cn, last_c_index);
1c1008c7
FF		 899
900 /* Reclaim transmitted buffers */
901 while (last_tx_cn-- > 0) {
902 tx_cb_ptr = ring->cbs + last_c_index;
478a010c 903 bds_compl = 0;
1c1008c7 904 if (tx_cb_ptr->skb) {
478a010c 905 bds_compl = skb_shinfo(tx_cb_ptr->skb)->nr_frags + 1;
1c1008c7
FF		 906 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
907 dma_unmap_single(&dev->dev,
c91b7f66
FF		 908 dma_unmap_addr(tx_cb_ptr, dma_addr),
909 tx_cb_ptr->skb->len,
910 DMA_TO_DEVICE);
1c1008c7
FF		 911 bcmgenet_free_cb(tx_cb_ptr);
912 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
913 dev->stats.tx_bytes +=
914 dma_unmap_len(tx_cb_ptr, dma_len);
915 dma_unmap_page(&dev->dev,
c91b7f66
FF		 916 dma_unmap_addr(tx_cb_ptr, dma_addr),
917 dma_unmap_len(tx_cb_ptr, dma_len),
918 DMA_TO_DEVICE);
1c1008c7
FF		 919 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
920 }
921 dev->stats.tx_packets++;
478a010c 922 ring->free_bds += bds_compl;
1c1008c7
FF		 923
924 last_c_index++;
925 last_c_index &= (num_tx_bds - 1);
926 }
927
928 if (ring->free_bds > (MAX_SKB_FRAGS + 1))
929 ring->int_disable(priv, ring);
930
b2cde2cc
FF		 931 if (netif_tx_queue_stopped(txq))
932 netif_tx_wake_queue(txq);
1c1008c7
FF		 933
934 ring->c_index = c_index;
935}
936
937static void bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 938 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 939{
940 unsigned long flags;
941
942 spin_lock_irqsave(&ring->lock, flags);
943 __bcmgenet_tx_reclaim(dev, ring);
944 spin_unlock_irqrestore(&ring->lock, flags);
945}
946
947static void bcmgenet_tx_reclaim_all(struct net_device *dev)
948{
949 struct bcmgenet_priv *priv = netdev_priv(dev);
950 int i;
951
952 if (netif_is_multiqueue(dev)) {
953 for (i = 0; i < priv->hw_params->tx_queues; i++)
954 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
955 }
956
957 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
958}
959
960/* Transmits a single SKB (either head of a fragment or a single SKB)
961 * caller must hold priv->lock
962 */
963static int bcmgenet_xmit_single(struct net_device *dev,
964 struct sk_buff *skb,
965 u16 dma_desc_flags,
966 struct bcmgenet_tx_ring *ring)
967{
968 struct bcmgenet_priv *priv = netdev_priv(dev);
969 struct device *kdev = &priv->pdev->dev;
970 struct enet_cb *tx_cb_ptr;
971 unsigned int skb_len;
972 dma_addr_t mapping;
973 u32 length_status;
974 int ret;
975
976 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
977
978 if (unlikely(!tx_cb_ptr))
979 BUG();
980
981 tx_cb_ptr->skb = skb;
982
983 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
984
985 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
986 ret = dma_mapping_error(kdev, mapping);
987 if (ret) {
988 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
989 dev_kfree_skb(skb);
990 return ret;
991 }
992
993 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
994 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
995 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
996 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
997 DMA_TX_APPEND_CRC;
998
999 if (skb->ip_summed == CHECKSUM_PARTIAL)
1000 length_status |= DMA_TX_DO_CSUM;
1001
1002 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1003
1004 /* Decrement total BD count and advance our write pointer */
1005 ring->free_bds -= 1;
1006 ring->prod_index += 1;
1007 ring->prod_index &= DMA_P_INDEX_MASK;
1008
1009 return 0;
1010}
1011
7fc527f9 1012/* Transmit a SKB fragment */
1c1008c7 1013static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1014 skb_frag_t *frag,
1015 u16 dma_desc_flags,
1016 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1017{
1018 struct bcmgenet_priv *priv = netdev_priv(dev);
1019 struct device *kdev = &priv->pdev->dev;
1020 struct enet_cb *tx_cb_ptr;
1021 dma_addr_t mapping;
1022 int ret;
1023
1024 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1025
1026 if (unlikely(!tx_cb_ptr))
1027 BUG();
1028 tx_cb_ptr->skb = NULL;
1029
1030 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1031 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1032 ret = dma_mapping_error(kdev, mapping);
1033 if (ret) {
1034 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1035 __func__);
1c1008c7
FF		 1036 return ret;
1037 }
1038
1039 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1040 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1041
1042 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1043 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1044 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7
FF		 1045
1046
1047 ring->free_bds -= 1;
1048 ring->prod_index += 1;
1049 ring->prod_index &= DMA_P_INDEX_MASK;
1050
1051 return 0;
1052}
1053
1054/* Reallocate the SKB to put enough headroom in front of it and insert
1055 * the transmit checksum offsets in the descriptors
1056 */
bc23333b
PG		 1057static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1058 struct sk_buff *skb)
1c1008c7
FF		 1059{
1060 struct status_64 *status = NULL;
1061 struct sk_buff *new_skb;
1062 u16 offset;
1063 u8 ip_proto;
1064 u16 ip_ver;
1065 u32 tx_csum_info;
1066
1067 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1068 /* If 64 byte status block enabled, must make sure skb has
1069 * enough headroom for us to insert 64B status block.
1070 */
1071 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1072 dev_kfree_skb(skb);
1073 if (!new_skb) {
1074 dev->stats.tx_errors++;
1075 dev->stats.tx_dropped++;
bc23333b 1076 return NULL;
1c1008c7
FF		 1077 }
1078 skb = new_skb;
1079 }
1080
1081 skb_push(skb, sizeof(*status));
1082 status = (struct status_64 *)skb->data;
1083
1084 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1085 ip_ver = htons(skb->protocol);
1086 switch (ip_ver) {
1087 case ETH_P_IP:
1088 ip_proto = ip_hdr(skb)->protocol;
1089 break;
1090 case ETH_P_IPV6:
1091 ip_proto = ipv6_hdr(skb)->nexthdr;
1092 break;
1093 default:
bc23333b 1094 return skb;
1c1008c7
FF		 1095 }
1096
1097 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1098 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1099 (offset + skb->csum_offset);
1100
1101 /* Set the length valid bit for TCP and UDP and just set
1102 * the special UDP flag for IPv4, else just set to 0.
1103 */
1104 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1105 tx_csum_info |= STATUS_TX_CSUM_LV;
1106 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1107 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1108 } else {
1c1008c7 1109 tx_csum_info = 0;
8900ea57 1110 }
1c1008c7
FF		 1111
1112 status->tx_csum_info = tx_csum_info;
1113 }
1114
bc23333b 1115 return skb;
1c1008c7
FF		 1116}
1117
1118static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1119{
1120 struct bcmgenet_priv *priv = netdev_priv(dev);
1121 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1122 struct netdev_queue *txq;
1c1008c7
FF		 1123 unsigned long flags = 0;
1124 int nr_frags, index;
1125 u16 dma_desc_flags;
1126 int ret;
1127 int i;
1128
1129 index = skb_get_queue_mapping(skb);
1130 /* Mapping strategy:
1131 * queue_mapping = 0, unclassified, packet xmited through ring16
1132 * queue_mapping = 1, goes to ring 0. (highest priority queue
1133 * queue_mapping = 2, goes to ring 1.
1134 * queue_mapping = 3, goes to ring 2.
1135 * queue_mapping = 4, goes to ring 3.
1136 */
1137 if (index == 0)
1138 index = DESC_INDEX;
1139 else
1140 index -= 1;
1141
1c1008c7
FF		 1142 nr_frags = skb_shinfo(skb)->nr_frags;
1143 ring = &priv->tx_rings[index];
b2cde2cc 1144 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1145
1146 spin_lock_irqsave(&ring->lock, flags);
1147 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1148 netif_tx_stop_queue(txq);
1c1008c7 1149 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1150 __func__, index, ring->queue);
1c1008c7
FF		 1151 ret = NETDEV_TX_BUSY;
1152 goto out;
1153 }
1154
474ea9ca
FF		 1155 if (skb_padto(skb, ETH_ZLEN)) {
1156 ret = NETDEV_TX_OK;
1157 goto out;
1158 }
1159
1c1008c7
FF		 1160 /* set the SKB transmit checksum */
1161 if (priv->desc_64b_en) {
bc23333b
PG		 1162 skb = bcmgenet_put_tx_csum(dev, skb);
1163 if (!skb) {
1c1008c7
FF		 1164 ret = NETDEV_TX_OK;
1165 goto out;
1166 }
1167 }
1168
1169 dma_desc_flags = DMA_SOP;
1170 if (nr_frags == 0)
1171 dma_desc_flags |= DMA_EOP;
1172
1173 /* Transmit single SKB or head of fragment list */
1174 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1175 if (ret) {
1176 ret = NETDEV_TX_OK;
1177 goto out;
1178 }
1179
1180 /* xmit fragment */
1181 for (i = 0; i < nr_frags; i++) {
1182 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1183 &skb_shinfo(skb)->frags[i],
1184 (i == nr_frags - 1) ? DMA_EOP : 0,
1185 ring);
1c1008c7
FF		 1186 if (ret) {
1187 ret = NETDEV_TX_OK;
1188 goto out;
1189 }
1190 }
1191
d03825fb
FF		 1192 skb_tx_timestamp(skb);
1193
1c1008c7
FF		 1194 /* we kept a software copy of how much we should advance the TDMA
1195 * producer index, now write it down to the hardware
1196 */
1197 bcmgenet_tdma_ring_writel(priv, ring->index,
c91b7f66 1198 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1199
1200 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
b2cde2cc 1201 netif_tx_stop_queue(txq);
1c1008c7
FF		 1202 ring->int_enable(priv, ring);
1203 }
1204
1205out:
1206 spin_unlock_irqrestore(&ring->lock, flags);
1207
1208 return ret;
1209}
1210
1211
c91b7f66 1212static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1c1008c7
FF		 1213{
1214 struct device *kdev = &priv->pdev->dev;
1215 struct sk_buff *skb;
1216 dma_addr_t mapping;
1217 int ret;
1218
c91b7f66 1219 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1c1008c7
FF		 1220 if (!skb)
1221 return -ENOMEM;
1222
1223 /* a caller did not release this control block */
1224 WARN_ON(cb->skb != NULL);
1225 cb->skb = skb;
1226 mapping = dma_map_single(kdev, skb->data,
c91b7f66 1227 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1228 ret = dma_mapping_error(kdev, mapping);
1229 if (ret) {
1230 bcmgenet_free_cb(cb);
1231 netif_err(priv, rx_err, priv->dev,
c91b7f66 1232 "%s DMA map failed\n", __func__);
1c1008c7
FF		 1233 return ret;
1234 }
1235
1236 dma_unmap_addr_set(cb, dma_addr, mapping);
1237 /* assign packet, prepare descriptor, and advance pointer */
1238
1239 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1240
1241 /* turn on the newly assigned BD for DMA to use */
1242 priv->rx_bd_assign_index++;
1243 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1244
1245 priv->rx_bd_assign_ptr = priv->rx_bds +
1246 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1247
1248 return 0;
1249}
1250
1251/* bcmgenet_desc_rx - descriptor based rx process.
1252 * this could be called from bottom half, or from NAPI polling method.
1253 */
1254static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1255 unsigned int budget)
1256{
1257 struct net_device *dev = priv->dev;
1258 struct enet_cb *cb;
1259 struct sk_buff *skb;
1260 u32 dma_length_status;
1261 unsigned long dma_flag;
1262 int len, err;
1263 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1264 unsigned int p_index;
1265 unsigned int chksum_ok = 0;
1266
c91b7f66 1267 p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX);
1c1008c7
FF		 1268 p_index &= DMA_P_INDEX_MASK;
1269
1270 if (p_index < priv->rx_c_index)
1271 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1272 priv->rx_c_index + p_index;
1273 else
1274 rxpkttoprocess = p_index - priv->rx_c_index;
1275
1276 netif_dbg(priv, rx_status, dev,
c91b7f66 1277 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1278
1279 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1280 (rxpktprocessed < budget)) {
b629be5c
FF		 1281 cb = &priv->rx_cbs[priv->rx_read_ptr];
1282 skb = cb->skb;
1283
1284 rxpktprocessed++;
1285
1286 priv->rx_read_ptr++;
1287 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1288
1289 /* We do not have a backing SKB, so we do not have a
1290 * corresponding DMA mapping for this incoming packet since
1291 * bcmgenet_rx_refill always either has both skb and mapping or
1292 * none.
1293 */
1294 if (unlikely(!skb)) {
1295 dev->stats.rx_dropped++;
1296 dev->stats.rx_errors++;
1297 goto refill;
1298 }
1299
1c1008c7
FF		 1300 /* Unmap the packet contents such that we can use the
1301 * RSV from the 64 bytes descriptor when enabled and save
1302 * a 32-bits register read
1303 */
1c1008c7 1304 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
c91b7f66 1305 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1306
1307 if (!priv->desc_64b_en) {
c91b7f66
FF		 1308 dma_length_status =
1309 dmadesc_get_length_status(priv,
1310 priv->rx_bds +
1311 (priv->rx_read_ptr *
1312 DMA_DESC_SIZE));
1c1008c7
FF		 1313 } else {
1314 struct status_64 *status;
164d4f20 1315
1c1008c7
FF		 1316 status = (struct status_64 *)skb->data;
1317 dma_length_status = status->length_status;
1318 }
1319
1320 /* DMA flags and length are still valid no matter how
1321 * we got the Receive Status Vector (64B RSB or register)
1322 */
1323 dma_flag = dma_length_status & 0xffff;
1324 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1325
1326 netif_dbg(priv, rx_status, dev,
c91b7f66
FF		 1327 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1328 __func__, p_index, priv->rx_c_index,
1329 priv->rx_read_ptr, dma_length_status);
1c1008c7 1330
1c1008c7
FF		 1331 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1332 netif_err(priv, rx_status, dev,
c91b7f66 1333 "dropping fragmented packet!\n");
1c1008c7
FF		 1334 dev->stats.rx_dropped++;
1335 dev->stats.rx_errors++;
1336 dev_kfree_skb_any(cb->skb);
1337 cb->skb = NULL;
1338 goto refill;
1339 }
1340 /* report errors */
1341 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1342 DMA_RX_OV |
1343 DMA_RX_NO |
1344 DMA_RX_LG |
1345 DMA_RX_RXER))) {
1346 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1347 (unsigned int)dma_flag);
1c1008c7
FF		 1348 if (dma_flag & DMA_RX_CRC_ERROR)
1349 dev->stats.rx_crc_errors++;
1350 if (dma_flag & DMA_RX_OV)
1351 dev->stats.rx_over_errors++;
1352 if (dma_flag & DMA_RX_NO)
1353 dev->stats.rx_frame_errors++;
1354 if (dma_flag & DMA_RX_LG)
1355 dev->stats.rx_length_errors++;
1356 dev->stats.rx_dropped++;
1357 dev->stats.rx_errors++;
1358
1359 /* discard the packet and advance consumer index.*/
1360 dev_kfree_skb_any(cb->skb);
1361 cb->skb = NULL;
1362 goto refill;
1363 } /* error packet */
1364
1365 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1366 priv->desc_rxchk_en;
1c1008c7
FF		 1367
1368 skb_put(skb, len);
1369 if (priv->desc_64b_en) {
1370 skb_pull(skb, 64);
1371 len -= 64;
1372 }
1373
1374 if (likely(chksum_ok))
1375 skb->ip_summed = CHECKSUM_UNNECESSARY;
1376
1377 /* remove hardware 2bytes added for IP alignment */
1378 skb_pull(skb, 2);
1379 len -= 2;
1380
1381 if (priv->crc_fwd_en) {
1382 skb_trim(skb, len - ETH_FCS_LEN);
1383 len -= ETH_FCS_LEN;
1384 }
1385
1386 /*Finish setting up the received SKB and send it to the kernel*/
1387 skb->protocol = eth_type_trans(skb, priv->dev);
1388 dev->stats.rx_packets++;
1389 dev->stats.rx_bytes += len;
1390 if (dma_flag & DMA_RX_MULT)
1391 dev->stats.multicast++;
1392
1393 /* Notify kernel */
1394 napi_gro_receive(&priv->napi, skb);
1395 cb->skb = NULL;
1396 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1397
1398 /* refill RX path on the current control block */
1399refill:
1400 err = bcmgenet_rx_refill(priv, cb);
1401 if (err)
1402 netif_err(priv, rx_err, dev, "Rx refill failed\n");
1403 }
1404
1405 return rxpktprocessed;
1406}
1407
1408/* Assign skb to RX DMA descriptor. */
1409static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1410{
1411 struct enet_cb *cb;
1412 int ret = 0;
1413 int i;
1414
1415 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1416
1417 /* loop here for each buffer needing assign */
1418 for (i = 0; i < priv->num_rx_bds; i++) {
1419 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1420 if (cb->skb)
1421 continue;
1422
1c1008c7
FF		 1423 ret = bcmgenet_rx_refill(priv, cb);
1424 if (ret)
1425 break;
1c1008c7
FF		 1426 }
1427
1428 return ret;
1429}
1430
1431static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1432{
1433 struct enet_cb *cb;
1434 int i;
1435
1436 for (i = 0; i < priv->num_rx_bds; i++) {
1437 cb = &priv->rx_cbs[i];
1438
1439 if (dma_unmap_addr(cb, dma_addr)) {
1440 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1441 dma_unmap_addr(cb, dma_addr),
1442 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1443 dma_unmap_addr_set(cb, dma_addr, 0);
1444 }
1445
1446 if (cb->skb)
1447 bcmgenet_free_cb(cb);
1448 }
1449}
1450
c91b7f66 1451static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1452{
1453 u32 reg;
1454
1455 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1456 if (enable)
1457 reg |= mask;
1458 else
1459 reg &= ~mask;
1460 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1461
1462 /* UniMAC stops on a packet boundary, wait for a full-size packet
1463 * to be processed
1464 */
1465 if (enable == 0)
1466 usleep_range(1000, 2000);
1467}
1468
1c1008c7
FF		 1469static int reset_umac(struct bcmgenet_priv *priv)
1470{
1471 struct device *kdev = &priv->pdev->dev;
1472 unsigned int timeout = 0;
1473 u32 reg;
1474
1475 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1476 bcmgenet_rbuf_ctrl_set(priv, 0);
1477 udelay(10);
1478
1479 /* disable MAC while updating its registers */
1480 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1481
1482 /* issue soft reset, wait for it to complete */
1483 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1484 while (timeout++ < 1000) {
1485 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1486 if (!(reg & CMD_SW_RESET))
1487 return 0;
1488
1489 udelay(1);
1490 }
1491
1492 if (timeout == 1000) {
1493 dev_err(kdev,
7fc527f9 1494 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1495 return -ETIMEDOUT;
1496 }
1497
1498 return 0;
1499}
1500
909ff5ef
FF		 1501static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1502{
1503 /* Mask all interrupts.*/
1504 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1505 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1506 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1507 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1508 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1509 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1510}
1511
1c1008c7
FF		 1512static int init_umac(struct bcmgenet_priv *priv)
1513{
1514 struct device *kdev = &priv->pdev->dev;
1515 int ret;
1516 u32 reg, cpu_mask_clear;
1517
1518 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1519
1520 ret = reset_umac(priv);
1521 if (ret)
1522 return ret;
1523
1524 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1525 /* clear tx/rx counter */
1526 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1527 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1528 UMAC_MIB_CTRL);
1c1008c7
FF		 1529 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1530
1531 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1532
1533 /* init rx registers, enable ip header optimization */
1534 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1535 reg |= RBUF_ALIGN_2B;
1536 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1537
1538 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1539 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1540
909ff5ef 1541 bcmgenet_intr_disable(priv);
1c1008c7
FF		 1542
1543 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1544
1545 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1546
7fc527f9 1547 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1548 if (phy_is_internal(priv->phydev)) {
1c1008c7 1549 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1550 } else if (priv->ext_phy) {
1c1008c7 1551 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1552 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1553 reg = bcmgenet_bp_mc_get(priv);
1554 reg |= BIT(priv->hw_params->bp_in_en_shift);
1555
1556 /* bp_mask: back pressure mask */
1557 if (netif_is_multiqueue(priv->dev))
1558 reg |= priv->hw_params->bp_in_mask;
1559 else
1560 reg &= ~priv->hw_params->bp_in_mask;
1561 bcmgenet_bp_mc_set(priv, reg);
1562 }
1563
1564 /* Enable MDIO interrupts on GENET v3+ */
1565 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1566 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1567
c91b7f66 1568 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1569
1570 /* Enable rx/tx engine.*/
1571 dev_dbg(kdev, "done init umac\n");
1572
1573 return 0;
1574}
1575
1576/* Initialize all house-keeping variables for a TX ring, along
1577 * with corresponding hardware registers
1578 */
1579static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1580 unsigned int index, unsigned int size,
1581 unsigned int write_ptr, unsigned int end_ptr)
1582{
1583 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1584 u32 words_per_bd = WORDS_PER_BD(priv);
1585 u32 flow_period_val = 0;
1586 unsigned int first_bd;
1587
1588 spin_lock_init(&ring->lock);
1589 ring->index = index;
1590 if (index == DESC_INDEX) {
1591 ring->queue = 0;
1592 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1593 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1594 } else {
1595 ring->queue = index + 1;
1596 ring->int_enable = bcmgenet_tx_ring_int_enable;
1597 ring->int_disable = bcmgenet_tx_ring_int_disable;
1598 }
1599 ring->cbs = priv->tx_cbs + write_ptr;
1600 ring->size = size;
1601 ring->c_index = 0;
1602 ring->free_bds = size;
1603 ring->write_ptr = write_ptr;
1604 ring->cb_ptr = write_ptr;
1605 ring->end_ptr = end_ptr - 1;
1606 ring->prod_index = 0;
1607
1608 /* Set flow period for ring != 16 */
1609 if (index != DESC_INDEX)
1610 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1611
1612 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1613 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1614 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1615 /* Disable rate control for now */
1616 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1617 TDMA_FLOW_PERIOD);
1c1008c7
FF		 1618 /* Unclassified traffic goes to ring 16 */
1619 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1620 ((size << DMA_RING_SIZE_SHIFT) |
1621 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7
FF		 1622
1623 first_bd = write_ptr;
1624
1625 /* Set start and end address, read and write pointers */
1626 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
c91b7f66 1627 DMA_START_ADDR);
1c1008c7 1628 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
c91b7f66 1629 TDMA_READ_PTR);
1c1008c7 1630 bcmgenet_tdma_ring_writel(priv, index, first_bd,
c91b7f66 1631 TDMA_WRITE_PTR);
1c1008c7 1632 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1633 DMA_END_ADDR);
1c1008c7
FF		 1634}
1635
1636/* Initialize a RDMA ring */
1637static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
c91b7f66 1638 unsigned int index, unsigned int size)
1c1008c7
FF		 1639{
1640 u32 words_per_bd = WORDS_PER_BD(priv);
1641 int ret;
1642
1643 priv->num_rx_bds = TOTAL_DESC;
1644 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1645 priv->rx_bd_assign_ptr = priv->rx_bds;
1646 priv->rx_bd_assign_index = 0;
1647 priv->rx_c_index = 0;
1648 priv->rx_read_ptr = 0;
c489be08
FF		 1649 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
1650 GFP_KERNEL);
1c1008c7
FF		 1651 if (!priv->rx_cbs)
1652 return -ENOMEM;
1653
1654 ret = bcmgenet_alloc_rx_buffers(priv);
1655 if (ret) {
1656 kfree(priv->rx_cbs);
1657 return ret;
1658 }
1659
1660 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1661 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1662 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1663 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1664 ((size << DMA_RING_SIZE_SHIFT) |
1665 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7
FF		 1666 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1667 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66 1668 words_per_bd * size - 1, DMA_END_ADDR);
1c1008c7 1669 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1670 (DMA_FC_THRESH_LO <<
1671 DMA_XOFF_THRESHOLD_SHIFT) |
1672 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1c1008c7
FF		 1673 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1674
1675 return ret;
1676}
1677
1678/* init multi xmit queues, only available for GENET2+
1679 * the queue is partitioned as follows:
1680 *
1681 * queue 0 - 3 is priority based, each one has 32 descriptors,
1682 * with queue 0 being the highest priority queue.
1683 *
1684 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1685 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1686 * descriptors.
1687 *
1688 * The transmit control block pool is then partitioned as following:
1689 * - tx_cbs[0...127] are for queue 16
1690 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1691 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1692 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1693 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1694 */
1695static void bcmgenet_init_multiq(struct net_device *dev)
1696{
1697 struct bcmgenet_priv *priv = netdev_priv(dev);
1698 unsigned int i, dma_enable;
1699 u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
1700
1701 if (!netif_is_multiqueue(dev)) {
1702 netdev_warn(dev, "called with non multi queue aware HW\n");
1703 return;
1704 }
1705
1706 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1707 dma_enable = dma_ctrl & DMA_EN;
1708 dma_ctrl &= ~DMA_EN;
1709 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1710
1711 /* Enable strict priority arbiter mode */
1712 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1713
1714 for (i = 0; i < priv->hw_params->tx_queues; i++) {
1715 /* first 64 tx_cbs are reserved for default tx queue
1716 * (ring 16)
1717 */
1718 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
c91b7f66
FF		 1719 i * priv->hw_params->bds_cnt,
1720 (i + 1) * priv->hw_params->bds_cnt);
1c1008c7 1721
7fc527f9 1722 /* Configure ring as descriptor ring and setup priority */
1c1008c7
FF		 1723 ring_cfg |= 1 << i;
1724 dma_priority |= ((GENET_Q0_PRIORITY + i) <<
1725 (GENET_MAX_MQ_CNT + 1) * i);
1726 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1727 }
1728
1729 /* Enable rings */
1730 reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1731 reg |= ring_cfg;
1732 bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1733
1734 /* Use configured rings priority and set ring #16 priority */
1735 reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
1736 reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
1737 reg |= dma_priority;
1738 bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
1739
1740 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1741 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1742 reg |= dma_ctrl;
1743 if (dma_enable)
1744 reg |= DMA_EN;
1745 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1746}
1747
4a0c081e
FF		 1748static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1749{
1750 int ret = 0;
1751 int timeout = 0;
1752 u32 reg;
1753
1754 /* Disable TDMA to stop add more frames in TX DMA */
1755 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1756 reg &= ~DMA_EN;
1757 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1758
1759 /* Check TDMA status register to confirm TDMA is disabled */
1760 while (timeout++ < DMA_TIMEOUT_VAL) {
1761 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1762 if (reg & DMA_DISABLED)
1763 break;
1764
1765 udelay(1);
1766 }
1767
1768 if (timeout == DMA_TIMEOUT_VAL) {
1769 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1770 ret = -ETIMEDOUT;
1771 }
1772
1773 /* Wait 10ms for packet drain in both tx and rx dma */
1774 usleep_range(10000, 20000);
1775
1776 /* Disable RDMA */
1777 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1778 reg &= ~DMA_EN;
1779 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1780
1781 timeout = 0;
1782 /* Check RDMA status register to confirm RDMA is disabled */
1783 while (timeout++ < DMA_TIMEOUT_VAL) {
1784 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
1785 if (reg & DMA_DISABLED)
1786 break;
1787
1788 udelay(1);
1789 }
1790
1791 if (timeout == DMA_TIMEOUT_VAL) {
1792 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
1793 ret = -ETIMEDOUT;
1794 }
1795
1796 return ret;
1797}
1798
1c1008c7
FF		 1799static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1800{
1801 int i;
1802
1803 /* disable DMA */
4a0c081e 1804 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 1805
1806 for (i = 0; i < priv->num_tx_bds; i++) {
1807 if (priv->tx_cbs[i].skb != NULL) {
1808 dev_kfree_skb(priv->tx_cbs[i].skb);
1809 priv->tx_cbs[i].skb = NULL;
1810 }
1811 }
1812
1813 bcmgenet_free_rx_buffers(priv);
1814 kfree(priv->rx_cbs);
1815 kfree(priv->tx_cbs);
1816}
1817
1818/* init_edma: Initialize DMA control register */
1819static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1820{
1821 int ret;
1822
1823 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1824
1825 /* by default, enable ring 16 (descriptor based) */
1826 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1827 if (ret) {
1828 netdev_err(priv->dev, "failed to initialize RX ring\n");
1829 return ret;
1830 }
1831
1832 /* init rDma */
1833 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1834
1835 /* Init tDma */
1836 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1837
7fc527f9 1838 /* Initialize common TX ring structures */
1c1008c7
FF		 1839 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1840 priv->num_tx_bds = TOTAL_DESC;
c489be08 1841 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 1842 GFP_KERNEL);
1c1008c7
FF		 1843 if (!priv->tx_cbs) {
1844 bcmgenet_fini_dma(priv);
1845 return -ENOMEM;
1846 }
1847
1848 /* initialize multi xmit queue */
1849 bcmgenet_init_multiq(priv->dev);
1850
1851 /* initialize special ring 16 */
1852 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
c91b7f66
FF		 1853 priv->hw_params->tx_queues *
1854 priv->hw_params->bds_cnt,
1855 TOTAL_DESC);
1c1008c7
FF		 1856
1857 return 0;
1858}
1859
1860/* NAPI polling method*/
1861static int bcmgenet_poll(struct napi_struct *napi, int budget)
1862{
1863 struct bcmgenet_priv *priv = container_of(napi,
1864 struct bcmgenet_priv, napi);
1865 unsigned int work_done;
1866
1867 /* tx reclaim */
1868 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1869
1870 work_done = bcmgenet_desc_rx(priv, budget);
1871
1872 /* Advancing our consumer index*/
1873 priv->rx_c_index += work_done;
1874 priv->rx_c_index &= DMA_C_INDEX_MASK;
1875 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
c91b7f66 1876 priv->rx_c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1877 if (work_done < budget) {
1878 napi_complete(napi);
c91b7f66
FF		 1879 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
1880 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1881 }
1882
1883 return work_done;
1884}
1885
1886/* Interrupt bottom half */
1887static void bcmgenet_irq_task(struct work_struct *work)
1888{
1889 struct bcmgenet_priv *priv = container_of(
1890 work, struct bcmgenet_priv, bcmgenet_irq_work);
1891
1892 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1893
8fdb0e0f
FF		 1894 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
1895 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
1896 netif_dbg(priv, wol, priv->dev,
1897 "magic packet detected, waking up\n");
1898 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
1899 }
1900
1c1008c7
FF		 1901 /* Link UP/DOWN event */
1902 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 1903 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d 1904 phy_mac_interrupt(priv->phydev,
c91b7f66 1905 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 1906 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
1907 }
1908}
1909
1910/* bcmgenet_isr1: interrupt handler for ring buffer. */
1911static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
1912{
1913 struct bcmgenet_priv *priv = dev_id;
1914 unsigned int index;
1915
1916 /* Save irq status for bottom-half processing. */
1917 priv->irq1_stat =
1918 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
1919 ~priv->int1_mask;
7fc527f9 1920 /* clear interrupts */
1c1008c7
FF		 1921 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
1922
1923 netif_dbg(priv, intr, priv->dev,
c91b7f66 1924 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1c1008c7
FF		 1925 /* Check the MBDONE interrupts.
1926 * packet is done, reclaim descriptors
1927 */
1928 if (priv->irq1_stat & 0x0000ffff) {
1929 index = 0;
1930 for (index = 0; index < 16; index++) {
1931 if (priv->irq1_stat & (1 << index))
1932 bcmgenet_tx_reclaim(priv->dev,
c91b7f66 1933 &priv->tx_rings[index]);
1c1008c7
FF		 1934 }
1935 }
1936 return IRQ_HANDLED;
1937}
1938
1939/* bcmgenet_isr0: Handle various interrupts. */
1940static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
1941{
1942 struct bcmgenet_priv *priv = dev_id;
1943
1944 /* Save irq status for bottom-half processing. */
1945 priv->irq0_stat =
1946 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1947 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 1948 /* clear interrupts */
1c1008c7
FF		 1949 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1950
1951 netif_dbg(priv, intr, priv->dev,
c91b7f66 1952 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7
FF		 1953
1954 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
1955 /* We use NAPI(software interrupt throttling, if
1956 * Rx Descriptor throttling is not used.
1957 * Disable interrupt, will be enabled in the poll method.
1958 */
1959 if (likely(napi_schedule_prep(&priv->napi))) {
c91b7f66
FF		 1960 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
1961 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1962 __napi_schedule(&priv->napi);
1963 }
1964 }
1965 if (priv->irq0_stat &
1966 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
1967 /* Tx reclaim */
1968 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1969 }
1970 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
1971 UMAC_IRQ_PHY_DET_F |
1972 UMAC_IRQ_LINK_UP |
1973 UMAC_IRQ_LINK_DOWN |
1974 UMAC_IRQ_HFB_SM |
1975 UMAC_IRQ_HFB_MM |
1976 UMAC_IRQ_MPD_R)) {
1977 /* all other interested interrupts handled in bottom half */
1978 schedule_work(&priv->bcmgenet_irq_work);
1979 }
1980
1981 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 1982 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 1983 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1984 wake_up(&priv->wq);
1985 }
1986
1987 return IRQ_HANDLED;
1988}
1989
8562056f
FF		 1990static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
1991{
1992 struct bcmgenet_priv *priv = dev_id;
1993
1994 pm_wakeup_event(&priv->pdev->dev, 0);
1995
1996 return IRQ_HANDLED;
1997}
1998
1c1008c7
FF		 1999static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2000{
2001 u32 reg;
2002
2003 reg = bcmgenet_rbuf_ctrl_get(priv);
2004 reg |= BIT(1);
2005 bcmgenet_rbuf_ctrl_set(priv, reg);
2006 udelay(10);
2007
2008 reg &= ~BIT(1);
2009 bcmgenet_rbuf_ctrl_set(priv, reg);
2010 udelay(10);
2011}
2012
2013static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2014 unsigned char *addr)
1c1008c7
FF		 2015{
2016 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2017 (addr[2] << 8) | addr[3], UMAC_MAC0);
2018 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2019}
2020
1c1008c7
FF		 2021/* Returns a reusable dma control register value */
2022static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2023{
2024 u32 reg;
2025 u32 dma_ctrl;
2026
2027 /* disable DMA */
2028 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2029 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2030 reg &= ~dma_ctrl;
2031 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2032
2033 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2034 reg &= ~dma_ctrl;
2035 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2036
2037 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2038 udelay(10);
2039 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2040
2041 return dma_ctrl;
2042}
2043
2044static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2045{
2046 u32 reg;
2047
2048 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2049 reg |= dma_ctrl;
2050 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2051
2052 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2053 reg |= dma_ctrl;
2054 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2055}
2056
909ff5ef
FF		 2057static void bcmgenet_netif_start(struct net_device *dev)
2058{
2059 struct bcmgenet_priv *priv = netdev_priv(dev);
2060
2061 /* Start the network engine */
2062 napi_enable(&priv->napi);
2063
2064 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2065
2066 if (phy_is_internal(priv->phydev))
2067 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2068
2069 netif_tx_start_all_queues(dev);
2070
2071 phy_start(priv->phydev);
2072}
2073
1c1008c7
FF		 2074static int bcmgenet_open(struct net_device *dev)
2075{
2076 struct bcmgenet_priv *priv = netdev_priv(dev);
2077 unsigned long dma_ctrl;
2078 u32 reg;
2079 int ret;
2080
2081 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2082
2083 /* Turn on the clock */
2084 if (!IS_ERR(priv->clk))
2085 clk_prepare_enable(priv->clk);
2086
2087 /* take MAC out of reset */
2088 bcmgenet_umac_reset(priv);
2089
2090 ret = init_umac(priv);
2091 if (ret)
2092 goto err_clk_disable;
2093
2094 /* disable ethernet MAC while updating its registers */
e29585b8 2095 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2096
909ff5ef
FF		 2097 /* Make sure we reflect the value of CRC_CMD_FWD */
2098 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2099 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2100
1c1008c7
FF		 2101 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2102
1c1008c7
FF		 2103 if (phy_is_internal(priv->phydev)) {
2104 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2105 reg |= EXT_ENERGY_DET_MASK;
2106 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2107 }
2108
2109 /* Disable RX/TX DMA and flush TX queues */
2110 dma_ctrl = bcmgenet_dma_disable(priv);
2111
2112 /* Reinitialize TDMA and RDMA and SW housekeeping */
2113 ret = bcmgenet_init_dma(priv);
2114 if (ret) {
2115 netdev_err(dev, "failed to initialize DMA\n");
2116 goto err_fini_dma;
2117 }
2118
2119 /* Always enable ring 16 - descriptor ring */
2120 bcmgenet_enable_dma(priv, dma_ctrl);
2121
2122 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2123 dev->name, priv);
1c1008c7
FF		 2124 if (ret < 0) {
2125 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2126 goto err_fini_dma;
2127 }
2128
2129 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2130 dev->name, priv);
1c1008c7
FF		 2131 if (ret < 0) {
2132 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2133 goto err_irq0;
2134 }
2135
909ff5ef 2136 bcmgenet_netif_start(dev);
1c1008c7
FF		 2137
2138 return 0;
2139
2140err_irq0:
2141 free_irq(priv->irq0, dev);
2142err_fini_dma:
2143 bcmgenet_fini_dma(priv);
2144err_clk_disable:
2145 if (!IS_ERR(priv->clk))
2146 clk_disable_unprepare(priv->clk);
2147 return ret;
2148}
2149
909ff5ef
FF		 2150static void bcmgenet_netif_stop(struct net_device *dev)
2151{
2152 struct bcmgenet_priv *priv = netdev_priv(dev);
2153
2154 netif_tx_stop_all_queues(dev);
2155 napi_disable(&priv->napi);
2156 phy_stop(priv->phydev);
2157
2158 bcmgenet_intr_disable(priv);
2159
2160 /* Wait for pending work items to complete. Since interrupts are
2161 * disabled no new work will be scheduled.
2162 */
2163 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2164
cc013fb4 2165 priv->old_link = -1;
5ad6e6c5 2166 priv->old_speed = -1;
cc013fb4 2167 priv->old_duplex = -1;
5ad6e6c5 2168 priv->old_pause = -1;
909ff5ef
FF		 2169}
2170
1c1008c7
FF		 2171static int bcmgenet_close(struct net_device *dev)
2172{
2173 struct bcmgenet_priv *priv = netdev_priv(dev);
2174 int ret;
1c1008c7
FF		 2175
2176 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2177
909ff5ef 2178 bcmgenet_netif_stop(dev);
1c1008c7
FF		 2179
2180 /* Disable MAC receive */
e29585b8 2181 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2182
1c1008c7
FF		 2183 ret = bcmgenet_dma_teardown(priv);
2184 if (ret)
2185 return ret;
2186
2187 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2188 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2189
1c1008c7
FF		 2190 /* tx reclaim */
2191 bcmgenet_tx_reclaim_all(dev);
2192 bcmgenet_fini_dma(priv);
2193
2194 free_irq(priv->irq0, priv);
2195 free_irq(priv->irq1, priv);
2196
1c1008c7
FF		 2197 if (phy_is_internal(priv->phydev))
2198 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2199
1c1008c7
FF		 2200 if (!IS_ERR(priv->clk))
2201 clk_disable_unprepare(priv->clk);
2202
2203 return 0;
2204}
2205
2206static void bcmgenet_timeout(struct net_device *dev)
2207{
2208 struct bcmgenet_priv *priv = netdev_priv(dev);
2209
2210 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2211
2212 dev->trans_start = jiffies;
2213
2214 dev->stats.tx_errors++;
2215
2216 netif_tx_wake_all_queues(dev);
2217}
2218
2219#define MAX_MC_COUNT 16
2220
2221static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2222 unsigned char *addr,
2223 int *i,
2224 int *mc)
2225{
2226 u32 reg;
2227
c91b7f66
FF		 2228 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2229 UMAC_MDF_ADDR + (*i * 4));
2230 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2231 addr[4] << 8 | addr[5],
2232 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2233 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2234 reg |= (1 << (MAX_MC_COUNT - *mc));
2235 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2236 *i += 2;
2237 (*mc)++;
2238}
2239
2240static void bcmgenet_set_rx_mode(struct net_device *dev)
2241{
2242 struct bcmgenet_priv *priv = netdev_priv(dev);
2243 struct netdev_hw_addr *ha;
2244 int i, mc;
2245 u32 reg;
2246
2247 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2248
7fc527f9 2249 /* Promiscuous mode */
1c1008c7
FF		 2250 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2251 if (dev->flags & IFF_PROMISC) {
2252 reg |= CMD_PROMISC;
2253 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2254 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2255 return;
2256 } else {
2257 reg &= ~CMD_PROMISC;
2258 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2259 }
2260
2261 /* UniMac doesn't support ALLMULTI */
2262 if (dev->flags & IFF_ALLMULTI) {
2263 netdev_warn(dev, "ALLMULTI is not supported\n");
2264 return;
2265 }
2266
2267 /* update MDF filter */
2268 i = 0;
2269 mc = 0;
2270 /* Broadcast */
2271 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2272 /* my own address.*/
2273 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2274 /* Unicast list*/
2275 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2276 return;
2277
2278 if (!netdev_uc_empty(dev))
2279 netdev_for_each_uc_addr(ha, dev)
2280 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2281 /* Multicast */
2282 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2283 return;
2284
2285 netdev_for_each_mc_addr(ha, dev)
2286 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2287}
2288
2289/* Set the hardware MAC address. */
2290static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2291{
2292 struct sockaddr *addr = p;
2293
2294 /* Setting the MAC address at the hardware level is not possible
2295 * without disabling the UniMAC RX/TX enable bits.
2296 */
2297 if (netif_running(dev))
2298 return -EBUSY;
2299
2300 ether_addr_copy(dev->dev_addr, addr->sa_data);
2301
2302 return 0;
2303}
2304
1c1008c7
FF		 2305static const struct net_device_ops bcmgenet_netdev_ops = {
2306 .ndo_open = bcmgenet_open,
2307 .ndo_stop = bcmgenet_close,
2308 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2309 .ndo_tx_timeout = bcmgenet_timeout,
2310 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2311 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2312 .ndo_do_ioctl = bcmgenet_ioctl,
2313 .ndo_set_features = bcmgenet_set_features,
2314};
2315
2316/* Array of GENET hardware parameters/characteristics */
2317static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2318 [GENET_V1] = {
2319 .tx_queues = 0,
2320 .rx_queues = 0,
2321 .bds_cnt = 0,
2322 .bp_in_en_shift = 16,
2323 .bp_in_mask = 0xffff,
2324 .hfb_filter_cnt = 16,
2325 .qtag_mask = 0x1F,
2326 .hfb_offset = 0x1000,
2327 .rdma_offset = 0x2000,
2328 .tdma_offset = 0x3000,
2329 .words_per_bd = 2,
2330 },
2331 [GENET_V2] = {
2332 .tx_queues = 4,
2333 .rx_queues = 4,
2334 .bds_cnt = 32,
2335 .bp_in_en_shift = 16,
2336 .bp_in_mask = 0xffff,
2337 .hfb_filter_cnt = 16,
2338 .qtag_mask = 0x1F,
2339 .tbuf_offset = 0x0600,
2340 .hfb_offset = 0x1000,
2341 .hfb_reg_offset = 0x2000,
2342 .rdma_offset = 0x3000,
2343 .tdma_offset = 0x4000,
2344 .words_per_bd = 2,
2345 .flags = GENET_HAS_EXT,
2346 },
2347 [GENET_V3] = {
2348 .tx_queues = 4,
2349 .rx_queues = 4,
2350 .bds_cnt = 32,
2351 .bp_in_en_shift = 17,
2352 .bp_in_mask = 0x1ffff,
2353 .hfb_filter_cnt = 48,
2354 .qtag_mask = 0x3F,
2355 .tbuf_offset = 0x0600,
2356 .hfb_offset = 0x8000,
2357 .hfb_reg_offset = 0xfc00,
2358 .rdma_offset = 0x10000,
2359 .tdma_offset = 0x11000,
2360 .words_per_bd = 2,
2361 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2362 },
2363 [GENET_V4] = {
2364 .tx_queues = 4,
2365 .rx_queues = 4,
2366 .bds_cnt = 32,
2367 .bp_in_en_shift = 17,
2368 .bp_in_mask = 0x1ffff,
2369 .hfb_filter_cnt = 48,
2370 .qtag_mask = 0x3F,
2371 .tbuf_offset = 0x0600,
2372 .hfb_offset = 0x8000,
2373 .hfb_reg_offset = 0xfc00,
2374 .rdma_offset = 0x2000,
2375 .tdma_offset = 0x4000,
2376 .words_per_bd = 3,
2377 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2378 },
2379};
2380
2381/* Infer hardware parameters from the detected GENET version */
2382static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2383{
2384 struct bcmgenet_hw_params *params;
2385 u32 reg;
2386 u8 major;
2387
2388 if (GENET_IS_V4(priv)) {
2389 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2390 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2391 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2392 priv->version = GENET_V4;
2393 } else if (GENET_IS_V3(priv)) {
2394 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2395 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2396 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2397 priv->version = GENET_V3;
2398 } else if (GENET_IS_V2(priv)) {
2399 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2400 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2401 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2402 priv->version = GENET_V2;
2403 } else if (GENET_IS_V1(priv)) {
2404 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2405 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2406 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2407 priv->version = GENET_V1;
2408 }
2409
2410 /* enum genet_version starts at 1 */
2411 priv->hw_params = &bcmgenet_hw_params[priv->version];
2412 params = priv->hw_params;
2413
2414 /* Read GENET HW version */
2415 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2416 major = (reg >> 24 & 0x0f);
2417 if (major == 5)
2418 major = 4;
2419 else if (major == 0)
2420 major = 1;
2421 if (major != priv->version) {
2422 dev_err(&priv->pdev->dev,
2423 "GENET version mismatch, got: %d, configured for: %d\n",
2424 major, priv->version);
2425 }
2426
2427 /* Print the GENET core version */
2428 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 2429 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 2430
487320c5
FF		 2431 /* Store the integrated PHY revision for the MDIO probing function
2432 * to pass this information to the PHY driver. The PHY driver expects
2433 * to find the PHY major revision in bits 15:8 while the GENET register
2434 * stores that information in bits 7:0, account for that.
2435 */
2436 priv->gphy_rev = (reg & 0xffff) << 8;
2437
1c1008c7
FF		 2438#ifdef CONFIG_PHYS_ADDR_T_64BIT
2439 if (!(params->flags & GENET_HAS_40BITS))
2440 pr_warn("GENET does not support 40-bits PA\n");
2441#endif
2442
2443 pr_debug("Configuration for version: %d\n"
2444 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2445 "BP << en: %2d, BP msk: 0x%05x\n"
2446 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2447 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2448 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2449 "Words/BD: %d\n",
2450 priv->version,
2451 params->tx_queues, params->rx_queues, params->bds_cnt,
2452 params->bp_in_en_shift, params->bp_in_mask,
2453 params->hfb_filter_cnt, params->qtag_mask,
2454 params->tbuf_offset, params->hfb_offset,
2455 params->hfb_reg_offset,
2456 params->rdma_offset, params->tdma_offset,
2457 params->words_per_bd);
2458}
2459
2460static const struct of_device_id bcmgenet_match[] = {
2461 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2462 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2463 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2464 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2465 { },
2466};
2467
2468static int bcmgenet_probe(struct platform_device *pdev)
2469{
2470 struct device_node *dn = pdev->dev.of_node;
2471 const struct of_device_id *of_id;
2472 struct bcmgenet_priv *priv;
2473 struct net_device *dev;
2474 const void *macaddr;
2475 struct resource *r;
2476 int err = -EIO;
2477
2478 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2479 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2480 if (!dev) {
2481 dev_err(&pdev->dev, "can't allocate net device\n");
2482 return -ENOMEM;
2483 }
2484
2485 of_id = of_match_node(bcmgenet_match, dn);
2486 if (!of_id)
2487 return -EINVAL;
2488
2489 priv = netdev_priv(dev);
2490 priv->irq0 = platform_get_irq(pdev, 0);
2491 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2492 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2493 if (!priv->irq0 || !priv->irq1) {
2494 dev_err(&pdev->dev, "can't find IRQs\n");
2495 err = -EINVAL;
2496 goto err;
2497 }
2498
2499 macaddr = of_get_mac_address(dn);
2500 if (!macaddr) {
2501 dev_err(&pdev->dev, "can't find MAC address\n");
2502 err = -EINVAL;
2503 goto err;
2504 }
2505
2506 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2507 priv->base = devm_ioremap_resource(&pdev->dev, r);
2508 if (IS_ERR(priv->base)) {
2509 err = PTR_ERR(priv->base);
1c1008c7
FF		 2510 goto err;
2511 }
2512
2513 SET_NETDEV_DEV(dev, &pdev->dev);
2514 dev_set_drvdata(&pdev->dev, dev);
2515 ether_addr_copy(dev->dev_addr, macaddr);
2516 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2517 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2518 dev->netdev_ops = &bcmgenet_netdev_ops;
2519 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2520
2521 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2522
2523 /* Set hardware features */
2524 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2525 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2526
8562056f
FF		 2527 /* Request the WOL interrupt and advertise suspend if available */
2528 priv->wol_irq_disabled = true;
2529 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2530 dev->name, priv);
2531 if (!err)
2532 device_set_wakeup_capable(&pdev->dev, 1);
2533
1c1008c7
FF		 2534 /* Set the needed headroom to account for any possible
2535 * features enabling/disabling at runtime
2536 */
2537 dev->needed_headroom += 64;
2538
2539 netdev_boot_setup_check(dev);
2540
2541 priv->dev = dev;
2542 priv->pdev = pdev;
2543 priv->version = (enum bcmgenet_version)of_id->data;
2544
e4a60a93
FF		 2545 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2546 if (IS_ERR(priv->clk))
2547 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2548
2549 if (!IS_ERR(priv->clk))
2550 clk_prepare_enable(priv->clk);
2551
1c1008c7
FF		 2552 bcmgenet_set_hw_params(priv);
2553
1c1008c7
FF		 2554 /* Mii wait queue */
2555 init_waitqueue_head(&priv->wq);
2556 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2557 priv->rx_buf_len = RX_BUF_LENGTH;
2558 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2559
1c1008c7
FF		 2560 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2561 if (IS_ERR(priv->clk_wol))
2562 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2563
1c1008c7
FF		 2564 err = reset_umac(priv);
2565 if (err)
2566 goto err_clk_disable;
2567
2568 err = bcmgenet_mii_init(dev);
2569 if (err)
2570 goto err_clk_disable;
2571
2572 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2573 * just the ring 16 descriptor based TX
2574 */
2575 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2576 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2577
219575eb
FF		 2578 /* libphy will determine the link state */
2579 netif_carrier_off(dev);
2580
1c1008c7
FF		 2581 /* Turn off the main clock, WOL clock is handled separately */
2582 if (!IS_ERR(priv->clk))
2583 clk_disable_unprepare(priv->clk);
2584
0f50ce96
FF		 2585 err = register_netdev(dev);
2586 if (err)
2587 goto err;
2588
1c1008c7
FF		 2589 return err;
2590
2591err_clk_disable:
2592 if (!IS_ERR(priv->clk))
2593 clk_disable_unprepare(priv->clk);
2594err:
2595 free_netdev(dev);
2596 return err;
2597}
2598
2599static int bcmgenet_remove(struct platform_device *pdev)
2600{
2601 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2602
2603 dev_set_drvdata(&pdev->dev, NULL);
2604 unregister_netdev(priv->dev);
2605 bcmgenet_mii_exit(priv->dev);
2606 free_netdev(priv->dev);
2607
2608 return 0;
2609}
2610
b6e978e5
FF		 2611#ifdef CONFIG_PM_SLEEP
2612static int bcmgenet_suspend(struct device *d)
2613{
2614 struct net_device *dev = dev_get_drvdata(d);
2615 struct bcmgenet_priv *priv = netdev_priv(dev);
2616 int ret;
2617
2618 if (!netif_running(dev))
2619 return 0;
2620
2621 bcmgenet_netif_stop(dev);
2622
cc013fb4
FF		 2623 phy_suspend(priv->phydev);
2624
b6e978e5
FF		 2625 netif_device_detach(dev);
2626
2627 /* Disable MAC receive */
2628 umac_enable_set(priv, CMD_RX_EN, false);
2629
2630 ret = bcmgenet_dma_teardown(priv);
2631 if (ret)
2632 return ret;
2633
2634 /* Disable MAC transmit. TX DMA disabled have to done before this */
2635 umac_enable_set(priv, CMD_TX_EN, false);
2636
2637 /* tx reclaim */
2638 bcmgenet_tx_reclaim_all(dev);
2639 bcmgenet_fini_dma(priv);
2640
8c90db72
FF		 2641 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2642 if (device_may_wakeup(d) && priv->wolopts) {
2643 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2644 clk_prepare_enable(priv->clk_wol);
2645 }
2646
b6e978e5
FF		 2647 /* Turn off the clocks */
2648 clk_disable_unprepare(priv->clk);
2649
2650 return 0;
2651}
2652
2653static int bcmgenet_resume(struct device *d)
2654{
2655 struct net_device *dev = dev_get_drvdata(d);
2656 struct bcmgenet_priv *priv = netdev_priv(dev);
2657 unsigned long dma_ctrl;
2658 int ret;
2659 u32 reg;
2660
2661 if (!netif_running(dev))
2662 return 0;
2663
2664 /* Turn on the clock */
2665 ret = clk_prepare_enable(priv->clk);
2666 if (ret)
2667 return ret;
2668
2669 bcmgenet_umac_reset(priv);
2670
2671 ret = init_umac(priv);
2672 if (ret)
2673 goto out_clk_disable;
2674
0a29b3da
TK		 2675 /* From WOL-enabled suspend, switch to regular clock */
2676 if (priv->wolopts)
2677 clk_disable_unprepare(priv->clk_wol);
2678
2679 phy_init_hw(priv->phydev);
2680 /* Speed settings must be restored */
2681 bcmgenet_mii_config(priv->dev);
8c90db72 2682
b6e978e5
FF		 2683 /* disable ethernet MAC while updating its registers */
2684 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2685
2686 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2687
2688 if (phy_is_internal(priv->phydev)) {
2689 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2690 reg |= EXT_ENERGY_DET_MASK;
2691 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2692 }
2693
98bb7399
FF		 2694 if (priv->wolopts)
2695 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2696
b6e978e5
FF		 2697 /* Disable RX/TX DMA and flush TX queues */
2698 dma_ctrl = bcmgenet_dma_disable(priv);
2699
2700 /* Reinitialize TDMA and RDMA and SW housekeeping */
2701 ret = bcmgenet_init_dma(priv);
2702 if (ret) {
2703 netdev_err(dev, "failed to initialize DMA\n");
2704 goto out_clk_disable;
2705 }
2706
2707 /* Always enable ring 16 - descriptor ring */
2708 bcmgenet_enable_dma(priv, dma_ctrl);
2709
2710 netif_device_attach(dev);
2711
cc013fb4
FF		 2712 phy_resume(priv->phydev);
2713
b6e978e5
FF		 2714 bcmgenet_netif_start(dev);
2715
2716 return 0;
2717
2718out_clk_disable:
2719 clk_disable_unprepare(priv->clk);
2720 return ret;
2721}
2722#endif /* CONFIG_PM_SLEEP */
2723
2724static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2725
1c1008c7
FF		 2726static struct platform_driver bcmgenet_driver = {
2727 .probe = bcmgenet_probe,
2728 .remove = bcmgenet_remove,
2729 .driver = {
2730 .name = "bcmgenet",
2731 .owner = THIS_MODULE,
2732 .of_match_table = bcmgenet_match,
b6e978e5 2733 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 2734 },
2735};
2736module_platform_driver(bcmgenet_driver);
2737
2738MODULE_AUTHOR("Broadcom Corporation");
2739MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2740MODULE_ALIAS("platform:bcmgenet");
2741MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)