projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: bcmgenet: Remove excessive PHY reset
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 106{
107 dmadesc_set_length_status(priv, d, val);
108 dmadesc_set_addr(priv, d, addr);
109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
0034de41
PG		 200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
1c1008c7
FF		 208};
209
210static const u8 bcmgenet_dma_regs_v3plus[] = {
211 [DMA_RING_CFG] = 0x00,
212 [DMA_CTRL] = 0x04,
213 [DMA_STATUS] = 0x08,
214 [DMA_SCB_BURST_SIZE] = 0x0C,
215 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 216 [DMA_PRIORITY_0] = 0x30,
217 [DMA_PRIORITY_1] = 0x34,
218 [DMA_PRIORITY_2] = 0x38,
0034de41
PG		 219 [DMA_INDEX2RING_0] = 0x70,
220 [DMA_INDEX2RING_1] = 0x74,
221 [DMA_INDEX2RING_2] = 0x78,
222 [DMA_INDEX2RING_3] = 0x7C,
223 [DMA_INDEX2RING_4] = 0x80,
224 [DMA_INDEX2RING_5] = 0x84,
225 [DMA_INDEX2RING_6] = 0x88,
226 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 227};
228
229static const u8 bcmgenet_dma_regs_v2[] = {
230 [DMA_RING_CFG] = 0x00,
231 [DMA_CTRL] = 0x04,
232 [DMA_STATUS] = 0x08,
233 [DMA_SCB_BURST_SIZE] = 0x0C,
234 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 235 [DMA_PRIORITY_0] = 0x34,
236 [DMA_PRIORITY_1] = 0x38,
237 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 238};
239
240static const u8 bcmgenet_dma_regs_v1[] = {
241 [DMA_CTRL] = 0x00,
242 [DMA_STATUS] = 0x04,
243 [DMA_SCB_BURST_SIZE] = 0x0C,
244 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 245 [DMA_PRIORITY_0] = 0x34,
246 [DMA_PRIORITY_1] = 0x38,
247 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 248};
249
250/* Set at runtime once bcmgenet version is known */
251static const u8 *bcmgenet_dma_regs;
252
253static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
254{
255 return netdev_priv(dev_get_drvdata(dev));
256}
257
258static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 259 enum dma_reg r)
1c1008c7
FF		 260{
261 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
262 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
263}
264
265static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
266 u32 val, enum dma_reg r)
267{
268 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
269 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
270}
271
272static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 273 enum dma_reg r)
1c1008c7
FF		 274{
275 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
276 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
277}
278
279static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
280 u32 val, enum dma_reg r)
281{
282 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
283 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
284}
285
286/* RDMA/TDMA ring registers and accessors
287 * we merge the common fields and just prefix with T/D the registers
288 * having different meaning depending on the direction
289 */
290enum dma_ring_reg {
291 TDMA_READ_PTR = 0,
292 RDMA_WRITE_PTR = TDMA_READ_PTR,
293 TDMA_READ_PTR_HI,
294 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
295 TDMA_CONS_INDEX,
296 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
297 TDMA_PROD_INDEX,
298 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
299 DMA_RING_BUF_SIZE,
300 DMA_START_ADDR,
301 DMA_START_ADDR_HI,
302 DMA_END_ADDR,
303 DMA_END_ADDR_HI,
304 DMA_MBUF_DONE_THRESH,
305 TDMA_FLOW_PERIOD,
306 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
307 TDMA_WRITE_PTR,
308 RDMA_READ_PTR = TDMA_WRITE_PTR,
309 TDMA_WRITE_PTR_HI,
310 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
311};
312
313/* GENET v4 supports 40-bits pointer addressing
314 * for obvious reasons the LO and HI word parts
315 * are contiguous, but this offsets the other
316 * registers.
317 */
318static const u8 genet_dma_ring_regs_v4[] = {
319 [TDMA_READ_PTR] = 0x00,
320 [TDMA_READ_PTR_HI] = 0x04,
321 [TDMA_CONS_INDEX] = 0x08,
322 [TDMA_PROD_INDEX] = 0x0C,
323 [DMA_RING_BUF_SIZE] = 0x10,
324 [DMA_START_ADDR] = 0x14,
325 [DMA_START_ADDR_HI] = 0x18,
326 [DMA_END_ADDR] = 0x1C,
327 [DMA_END_ADDR_HI] = 0x20,
328 [DMA_MBUF_DONE_THRESH] = 0x24,
329 [TDMA_FLOW_PERIOD] = 0x28,
330 [TDMA_WRITE_PTR] = 0x2C,
331 [TDMA_WRITE_PTR_HI] = 0x30,
332};
333
334static const u8 genet_dma_ring_regs_v123[] = {
335 [TDMA_READ_PTR] = 0x00,
336 [TDMA_CONS_INDEX] = 0x04,
337 [TDMA_PROD_INDEX] = 0x08,
338 [DMA_RING_BUF_SIZE] = 0x0C,
339 [DMA_START_ADDR] = 0x10,
340 [DMA_END_ADDR] = 0x14,
341 [DMA_MBUF_DONE_THRESH] = 0x18,
342 [TDMA_FLOW_PERIOD] = 0x1C,
343 [TDMA_WRITE_PTR] = 0x20,
344};
345
346/* Set at runtime once GENET version is known */
347static const u8 *genet_dma_ring_regs;
348
349static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 350 unsigned int ring,
351 enum dma_ring_reg r)
1c1008c7
FF		 352{
353 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
354 (DMA_RING_SIZE * ring) +
355 genet_dma_ring_regs[r]);
356}
357
358static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 359 unsigned int ring, u32 val,
360 enum dma_ring_reg r)
1c1008c7
FF		 361{
362 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
363 (DMA_RING_SIZE * ring) +
364 genet_dma_ring_regs[r]);
365}
366
367static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 368 unsigned int ring,
369 enum dma_ring_reg r)
1c1008c7
FF		 370{
371 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
372 (DMA_RING_SIZE * ring) +
373 genet_dma_ring_regs[r]);
374}
375
376static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 377 unsigned int ring, u32 val,
378 enum dma_ring_reg r)
1c1008c7
FF		 379{
380 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
381 (DMA_RING_SIZE * ring) +
382 genet_dma_ring_regs[r]);
383}
384
385static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 386 struct ethtool_cmd *cmd)
1c1008c7
FF		 387{
388 struct bcmgenet_priv *priv = netdev_priv(dev);
389
390 if (!netif_running(dev))
391 return -EINVAL;
392
393 if (!priv->phydev)
394 return -ENODEV;
395
396 return phy_ethtool_gset(priv->phydev, cmd);
397}
398
399static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 400 struct ethtool_cmd *cmd)
1c1008c7
FF		 401{
402 struct bcmgenet_priv *priv = netdev_priv(dev);
403
404 if (!netif_running(dev))
405 return -EINVAL;
406
407 if (!priv->phydev)
408 return -ENODEV;
409
410 return phy_ethtool_sset(priv->phydev, cmd);
411}
412
413static int bcmgenet_set_rx_csum(struct net_device *dev,
414 netdev_features_t wanted)
415{
416 struct bcmgenet_priv *priv = netdev_priv(dev);
417 u32 rbuf_chk_ctrl;
418 bool rx_csum_en;
419
420 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
421
422 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
423
424 /* enable rx checksumming */
425 if (rx_csum_en)
426 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
427 else
428 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
429 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 430
431 /* If UniMAC forwards CRC, we need to skip over it to get
432 * a valid CHK bit to be set in the per-packet status word
433 */
434 if (rx_csum_en && priv->crc_fwd_en)
435 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
436 else
437 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
438
1c1008c7
FF		 439 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
440
441 return 0;
442}
443
444static int bcmgenet_set_tx_csum(struct net_device *dev,
445 netdev_features_t wanted)
446{
447 struct bcmgenet_priv *priv = netdev_priv(dev);
448 bool desc_64b_en;
449 u32 tbuf_ctrl, rbuf_ctrl;
450
451 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
452 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
453
454 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
455
456 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
457 if (desc_64b_en) {
458 tbuf_ctrl |= RBUF_64B_EN;
459 rbuf_ctrl |= RBUF_64B_EN;
460 } else {
461 tbuf_ctrl &= ~RBUF_64B_EN;
462 rbuf_ctrl &= ~RBUF_64B_EN;
463 }
464 priv->desc_64b_en = desc_64b_en;
465
466 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
467 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
468
469 return 0;
470}
471
472static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 473 netdev_features_t features)
1c1008c7
FF		 474{
475 netdev_features_t changed = features ^ dev->features;
476 netdev_features_t wanted = dev->wanted_features;
477 int ret = 0;
478
479 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
480 ret = bcmgenet_set_tx_csum(dev, wanted);
481 if (changed & (NETIF_F_RXCSUM))
482 ret = bcmgenet_set_rx_csum(dev, wanted);
483
484 return ret;
485}
486
487static u32 bcmgenet_get_msglevel(struct net_device *dev)
488{
489 struct bcmgenet_priv *priv = netdev_priv(dev);
490
491 return priv->msg_enable;
492}
493
494static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
495{
496 struct bcmgenet_priv *priv = netdev_priv(dev);
497
498 priv->msg_enable = level;
499}
500
501/* standard ethtool support functions. */
502enum bcmgenet_stat_type {
503 BCMGENET_STAT_NETDEV = -1,
504 BCMGENET_STAT_MIB_RX,
505 BCMGENET_STAT_MIB_TX,
506 BCMGENET_STAT_RUNT,
507 BCMGENET_STAT_MISC,
f62ba9c1 508 BCMGENET_STAT_SOFT,
1c1008c7
FF		 509};
510
511struct bcmgenet_stats {
512 char stat_string[ETH_GSTRING_LEN];
513 int stat_sizeof;
514 int stat_offset;
515 enum bcmgenet_stat_type type;
516 /* reg offset from UMAC base for misc counters */
517 u16 reg_offset;
518};
519
520#define STAT_NETDEV(m) { \
521 .stat_string = __stringify(m), \
522 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
523 .stat_offset = offsetof(struct net_device_stats, m), \
524 .type = BCMGENET_STAT_NETDEV, \
525}
526
527#define STAT_GENET_MIB(str, m, _type) { \
528 .stat_string = str, \
529 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
530 .stat_offset = offsetof(struct bcmgenet_priv, m), \
531 .type = _type, \
532}
533
534#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
535#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
536#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 537#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 538
539#define STAT_GENET_MISC(str, m, offset) { \
540 .stat_string = str, \
541 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
542 .stat_offset = offsetof(struct bcmgenet_priv, m), \
543 .type = BCMGENET_STAT_MISC, \
544 .reg_offset = offset, \
545}
546
547
548/* There is a 0xC gap between the end of RX and beginning of TX stats and then
549 * between the end of TX stats and the beginning of the RX RUNT
550 */
551#define BCMGENET_STAT_OFFSET 0xc
552
553/* Hardware counters must be kept in sync because the order/offset
554 * is important here (order in structure declaration = order in hardware)
555 */
556static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
557 /* general stats */
558 STAT_NETDEV(rx_packets),
559 STAT_NETDEV(tx_packets),
560 STAT_NETDEV(rx_bytes),
561 STAT_NETDEV(tx_bytes),
562 STAT_NETDEV(rx_errors),
563 STAT_NETDEV(tx_errors),
564 STAT_NETDEV(rx_dropped),
565 STAT_NETDEV(tx_dropped),
566 STAT_NETDEV(multicast),
567 /* UniMAC RSV counters */
568 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
569 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
570 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
571 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
572 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
573 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
574 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
575 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
576 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
577 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
578 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
579 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
580 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
581 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
582 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
583 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
584 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
585 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
586 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
587 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
588 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
589 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
590 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
591 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
592 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
593 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
594 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
595 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
596 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
597 /* UniMAC TSV counters */
598 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
599 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
600 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
601 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
602 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
603 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
604 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
605 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
606 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
607 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
608 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
609 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
610 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
611 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
612 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
613 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
614 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
615 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
616 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
617 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
618 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
619 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
620 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
621 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
622 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
623 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
624 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
625 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
626 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
627 /* UniMAC RUNT counters */
628 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
629 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
630 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
631 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
632 /* Misc UniMAC counters */
633 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
634 UMAC_RBUF_OVFL_CNT),
635 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
636 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 637 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
638 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
639 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 640};
641
642#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
643
644static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 645 struct ethtool_drvinfo *info)
1c1008c7
FF		 646{
647 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
648 strlcpy(info->version, "v2.0", sizeof(info->version));
649 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 650}
651
652static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
653{
654 switch (string_set) {
655 case ETH_SS_STATS:
656 return BCMGENET_STATS_LEN;
657 default:
658 return -EOPNOTSUPP;
659 }
660}
661
c91b7f66
FF		 662static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
663 u8 *data)
1c1008c7
FF		 664{
665 int i;
666
667 switch (stringset) {
668 case ETH_SS_STATS:
669 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
670 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 671 bcmgenet_gstrings_stats[i].stat_string,
672 ETH_GSTRING_LEN);
1c1008c7
FF		 673 }
674 break;
675 }
676}
677
678static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
679{
680 int i, j = 0;
681
682 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
683 const struct bcmgenet_stats *s;
684 u8 offset = 0;
685 u32 val = 0;
686 char *p;
687
688 s = &bcmgenet_gstrings_stats[i];
689 switch (s->type) {
690 case BCMGENET_STAT_NETDEV:
f62ba9c1 691 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 692 continue;
693 case BCMGENET_STAT_MIB_RX:
694 case BCMGENET_STAT_MIB_TX:
695 case BCMGENET_STAT_RUNT:
696 if (s->type != BCMGENET_STAT_MIB_RX)
697 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 698 val = bcmgenet_umac_readl(priv,
699 UMAC_MIB_START + j + offset);
1c1008c7
FF		 700 break;
701 case BCMGENET_STAT_MISC:
702 val = bcmgenet_umac_readl(priv, s->reg_offset);
703 /* clear if overflowed */
704 if (val == ~0)
705 bcmgenet_umac_writel(priv, 0, s->reg_offset);
706 break;
707 }
708
709 j += s->stat_sizeof;
710 p = (char *)priv + s->stat_offset;
711 *(u32 *)p = val;
712 }
713}
714
715static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 716 struct ethtool_stats *stats,
717 u64 *data)
1c1008c7
FF		 718{
719 struct bcmgenet_priv *priv = netdev_priv(dev);
720 int i;
721
722 if (netif_running(dev))
723 bcmgenet_update_mib_counters(priv);
724
725 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
726 const struct bcmgenet_stats *s;
727 char *p;
728
729 s = &bcmgenet_gstrings_stats[i];
730 if (s->type == BCMGENET_STAT_NETDEV)
731 p = (char *)&dev->stats;
732 else
733 p = (char *)priv;
734 p += s->stat_offset;
735 data[i] = *(u32 *)p;
736 }
737}
738
6ef398ea
FF		 739static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
740{
741 struct bcmgenet_priv *priv = netdev_priv(dev);
742 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
743 u32 reg;
744
745 if (enable && !priv->clk_eee_enabled) {
746 clk_prepare_enable(priv->clk_eee);
747 priv->clk_eee_enabled = true;
748 }
749
750 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
751 if (enable)
752 reg |= EEE_EN;
753 else
754 reg &= ~EEE_EN;
755 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
756
757 /* Enable EEE and switch to a 27Mhz clock automatically */
758 reg = __raw_readl(priv->base + off);
759 if (enable)
760 reg |= TBUF_EEE_EN | TBUF_PM_EN;
761 else
762 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
763 __raw_writel(reg, priv->base + off);
764
765 /* Do the same for thing for RBUF */
766 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
767 if (enable)
768 reg |= RBUF_EEE_EN | RBUF_PM_EN;
769 else
770 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
771 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
772
773 if (!enable && priv->clk_eee_enabled) {
774 clk_disable_unprepare(priv->clk_eee);
775 priv->clk_eee_enabled = false;
776 }
777
778 priv->eee.eee_enabled = enable;
779 priv->eee.eee_active = enable;
780}
781
782static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
783{
784 struct bcmgenet_priv *priv = netdev_priv(dev);
785 struct ethtool_eee *p = &priv->eee;
786
787 if (GENET_IS_V1(priv))
788 return -EOPNOTSUPP;
789
790 e->eee_enabled = p->eee_enabled;
791 e->eee_active = p->eee_active;
792 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
793
794 return phy_ethtool_get_eee(priv->phydev, e);
795}
796
797static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
798{
799 struct bcmgenet_priv *priv = netdev_priv(dev);
800 struct ethtool_eee *p = &priv->eee;
801 int ret = 0;
802
803 if (GENET_IS_V1(priv))
804 return -EOPNOTSUPP;
805
806 p->eee_enabled = e->eee_enabled;
807
808 if (!p->eee_enabled) {
809 bcmgenet_eee_enable_set(dev, false);
810 } else {
811 ret = phy_init_eee(priv->phydev, 0);
812 if (ret) {
813 netif_err(priv, hw, dev, "EEE initialization failed\n");
814 return ret;
815 }
816
817 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
818 bcmgenet_eee_enable_set(dev, true);
819 }
820
821 return phy_ethtool_set_eee(priv->phydev, e);
822}
823
6b0c5406
FF		 824static int bcmgenet_nway_reset(struct net_device *dev)
825{
826 struct bcmgenet_priv *priv = netdev_priv(dev);
827
828 return genphy_restart_aneg(priv->phydev);
829}
830
1c1008c7
FF		 831/* standard ethtool support functions. */
832static struct ethtool_ops bcmgenet_ethtool_ops = {
833 .get_strings = bcmgenet_get_strings,
834 .get_sset_count = bcmgenet_get_sset_count,
835 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
836 .get_settings = bcmgenet_get_settings,
837 .set_settings = bcmgenet_set_settings,
838 .get_drvinfo = bcmgenet_get_drvinfo,
839 .get_link = ethtool_op_get_link,
840 .get_msglevel = bcmgenet_get_msglevel,
841 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 842 .get_wol = bcmgenet_get_wol,
843 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 844 .get_eee = bcmgenet_get_eee,
845 .set_eee = bcmgenet_set_eee,
6b0c5406 846 .nway_reset = bcmgenet_nway_reset,
1c1008c7
FF		 847};
848
849/* Power down the unimac, based on mode. */
ca8cf341 850static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 851 enum bcmgenet_power_mode mode)
852{
ca8cf341 853 int ret = 0;
1c1008c7
FF		 854 u32 reg;
855
856 switch (mode) {
857 case GENET_POWER_CABLE_SENSE:
80d8e96d 858 phy_detach(priv->phydev);
1c1008c7
FF		 859 break;
860
c3ae64ae 861 case GENET_POWER_WOL_MAGIC:
ca8cf341 862 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 863 break;
864
1c1008c7
FF		 865 case GENET_POWER_PASSIVE:
866 /* Power down LED */
1c1008c7
FF		 867 if (priv->hw_params->flags & GENET_HAS_EXT) {
868 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
869 reg |= (EXT_PWR_DOWN_PHY |
870 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
871 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 872
873 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 874 }
875 break;
876 default:
877 break;
878 }
ca8cf341
FF		 879
880 return 0;
1c1008c7
FF		 881}
882
883static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 884 enum bcmgenet_power_mode mode)
1c1008c7
FF		 885{
886 u32 reg;
887
888 if (!(priv->hw_params->flags & GENET_HAS_EXT))
889 return;
890
891 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
892
893 switch (mode) {
894 case GENET_POWER_PASSIVE:
895 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
896 EXT_PWR_DOWN_BIAS);
897 /* fallthrough */
898 case GENET_POWER_CABLE_SENSE:
899 /* enable APD */
900 reg |= EXT_PWR_DN_EN_LD;
901 break;
c3ae64ae
FF		 902 case GENET_POWER_WOL_MAGIC:
903 bcmgenet_wol_power_up_cfg(priv, mode);
904 return;
1c1008c7
FF		 905 default:
906 break;
907 }
908
909 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1c1008c7
FF		 910}
911
912/* ioctl handle special commands that are not present in ethtool. */
913static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
914{
915 struct bcmgenet_priv *priv = netdev_priv(dev);
916 int val = 0;
917
918 if (!netif_running(dev))
919 return -EINVAL;
920
921 switch (cmd) {
922 case SIOCGMIIPHY:
923 case SIOCGMIIREG:
924 case SIOCSMIIREG:
925 if (!priv->phydev)
926 val = -ENODEV;
927 else
928 val = phy_mii_ioctl(priv->phydev, rq, cmd);
929 break;
930
931 default:
932 val = -EINVAL;
933 break;
934 }
935
936 return val;
937}
938
939static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
940 struct bcmgenet_tx_ring *ring)
941{
942 struct enet_cb *tx_cb_ptr;
943
944 tx_cb_ptr = ring->cbs;
945 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 946
1c1008c7
FF		 947 /* Advancing local write pointer */
948 if (ring->write_ptr == ring->end_ptr)
949 ring->write_ptr = ring->cb_ptr;
950 else
951 ring->write_ptr++;
952
953 return tx_cb_ptr;
954}
955
956/* Simple helper to free a control block's resources */
957static void bcmgenet_free_cb(struct enet_cb *cb)
958{
959 dev_kfree_skb_any(cb->skb);
960 cb->skb = NULL;
961 dma_unmap_addr_set(cb, dma_addr, 0);
962}
963
4055eaef
PG		 964static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
965{
ee7d8c20 966 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 967 INTRL2_CPU_MASK_SET);
968}
969
970static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
971{
ee7d8c20 972 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 973 INTRL2_CPU_MASK_CLEAR);
974}
975
976static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
977{
978 bcmgenet_intrl2_1_writel(ring->priv,
979 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
980 INTRL2_CPU_MASK_SET);
981}
982
983static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
984{
985 bcmgenet_intrl2_1_writel(ring->priv,
986 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
987 INTRL2_CPU_MASK_CLEAR);
988}
989
9dbac28f 990static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 991{
ee7d8c20 992 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 993 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 994}
995
9dbac28f 996static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 997{
ee7d8c20 998 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 999 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1000}
1001
9dbac28f 1002static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1003{
9dbac28f 1004 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1005 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1006}
1007
9dbac28f 1008static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1009{
9dbac28f 1010 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1011 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1012}
1013
1014/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1015static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1016 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1017{
1018 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 1019 struct enet_cb *tx_cb_ptr;
b2cde2cc 1020 struct netdev_queue *txq;
4092e6ac 1021 unsigned int pkts_compl = 0;
1c1008c7 1022 unsigned int c_index;
66d06757
PG		 1023 unsigned int txbds_ready;
1024 unsigned int txbds_processed = 0;
1c1008c7 1025
7fc527f9 1026 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 1027 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 1028 c_index &= DMA_C_INDEX_MASK;
1c1008c7 1029
66d06757
PG		 1030 if (likely(c_index >= ring->c_index))
1031 txbds_ready = c_index - ring->c_index;
1c1008c7 1032 else
66d06757 1033 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 1034
1035 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1036 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1037 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1038
1039 /* Reclaim transmitted buffers */
66d06757
PG		 1040 while (txbds_processed < txbds_ready) {
1041 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1042 if (tx_cb_ptr->skb) {
4092e6ac 1043 pkts_compl++;
66d06757 1044 dev->stats.tx_packets++;
1c1008c7
FF		 1045 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1046 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1047 dma_unmap_addr(tx_cb_ptr, dma_addr),
1048 tx_cb_ptr->skb->len,
1049 DMA_TO_DEVICE);
1c1008c7
FF		 1050 bcmgenet_free_cb(tx_cb_ptr);
1051 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1052 dev->stats.tx_bytes +=
1053 dma_unmap_len(tx_cb_ptr, dma_len);
1054 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1055 dma_unmap_addr(tx_cb_ptr, dma_addr),
1056 dma_unmap_len(tx_cb_ptr, dma_len),
1057 DMA_TO_DEVICE);
1c1008c7
FF		 1058 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1059 }
1c1008c7 1060
66d06757
PG		 1061 txbds_processed++;
1062 if (likely(ring->clean_ptr < ring->end_ptr))
1063 ring->clean_ptr++;
1064 else
1065 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1066 }
1067
66d06757
PG		 1068 ring->free_bds += txbds_processed;
1069 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1070
4092e6ac 1071 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
66d06757 1072 txq = netdev_get_tx_queue(dev, ring->queue);
4092e6ac
JS		 1073 if (netif_tx_queue_stopped(txq))
1074 netif_tx_wake_queue(txq);
1075 }
1c1008c7 1076
4092e6ac 1077 return pkts_compl;
1c1008c7
FF		 1078}
1079
4092e6ac 1080static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1081 struct bcmgenet_tx_ring *ring)
1c1008c7 1082{
4092e6ac 1083 unsigned int released;
1c1008c7
FF		 1084 unsigned long flags;
1085
1086 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1087 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1088 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1089
1090 return released;
1091}
1092
1093static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1094{
1095 struct bcmgenet_tx_ring *ring =
1096 container_of(napi, struct bcmgenet_tx_ring, napi);
1097 unsigned int work_done = 0;
1098
1099 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1100
1101 if (work_done == 0) {
1102 napi_complete(napi);
9dbac28f 1103 ring->int_enable(ring);
4092e6ac
JS		 1104
1105 return 0;
1106 }
1107
1108 return budget;
1c1008c7
FF		 1109}
1110
1111static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1112{
1113 struct bcmgenet_priv *priv = netdev_priv(dev);
1114 int i;
1115
1116 if (netif_is_multiqueue(dev)) {
1117 for (i = 0; i < priv->hw_params->tx_queues; i++)
1118 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1119 }
1120
1121 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1122}
1123
1124/* Transmits a single SKB (either head of a fragment or a single SKB)
1125 * caller must hold priv->lock
1126 */
1127static int bcmgenet_xmit_single(struct net_device *dev,
1128 struct sk_buff *skb,
1129 u16 dma_desc_flags,
1130 struct bcmgenet_tx_ring *ring)
1131{
1132 struct bcmgenet_priv *priv = netdev_priv(dev);
1133 struct device *kdev = &priv->pdev->dev;
1134 struct enet_cb *tx_cb_ptr;
1135 unsigned int skb_len;
1136 dma_addr_t mapping;
1137 u32 length_status;
1138 int ret;
1139
1140 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1141
1142 if (unlikely(!tx_cb_ptr))
1143 BUG();
1144
1145 tx_cb_ptr->skb = skb;
1146
1147 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1148
1149 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1150 ret = dma_mapping_error(kdev, mapping);
1151 if (ret) {
44c8bc3c 1152 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1153 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1154 dev_kfree_skb(skb);
1155 return ret;
1156 }
1157
1158 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1159 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1160 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1161 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1162 DMA_TX_APPEND_CRC;
1163
1164 if (skb->ip_summed == CHECKSUM_PARTIAL)
1165 length_status |= DMA_TX_DO_CSUM;
1166
1167 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1168
1c1008c7
FF		 1169 return 0;
1170}
1171
7fc527f9 1172/* Transmit a SKB fragment */
1c1008c7 1173static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1174 skb_frag_t *frag,
1175 u16 dma_desc_flags,
1176 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1177{
1178 struct bcmgenet_priv *priv = netdev_priv(dev);
1179 struct device *kdev = &priv->pdev->dev;
1180 struct enet_cb *tx_cb_ptr;
1181 dma_addr_t mapping;
1182 int ret;
1183
1184 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1185
1186 if (unlikely(!tx_cb_ptr))
1187 BUG();
1188 tx_cb_ptr->skb = NULL;
1189
1190 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1191 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1192 ret = dma_mapping_error(kdev, mapping);
1193 if (ret) {
44c8bc3c 1194 priv->mib.tx_dma_failed++;
1c1008c7 1195 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1196 __func__);
1c1008c7
FF		 1197 return ret;
1198 }
1199
1200 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1201 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1202
1203 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1204 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1205 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7 1206
1c1008c7
FF		 1207 return 0;
1208}
1209
1210/* Reallocate the SKB to put enough headroom in front of it and insert
1211 * the transmit checksum offsets in the descriptors
1212 */
bc23333b
PG		 1213static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1214 struct sk_buff *skb)
1c1008c7
FF		 1215{
1216 struct status_64 *status = NULL;
1217 struct sk_buff *new_skb;
1218 u16 offset;
1219 u8 ip_proto;
1220 u16 ip_ver;
1221 u32 tx_csum_info;
1222
1223 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1224 /* If 64 byte status block enabled, must make sure skb has
1225 * enough headroom for us to insert 64B status block.
1226 */
1227 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1228 dev_kfree_skb(skb);
1229 if (!new_skb) {
1c1008c7 1230 dev->stats.tx_dropped++;
bc23333b 1231 return NULL;
1c1008c7
FF		 1232 }
1233 skb = new_skb;
1234 }
1235
1236 skb_push(skb, sizeof(*status));
1237 status = (struct status_64 *)skb->data;
1238
1239 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1240 ip_ver = htons(skb->protocol);
1241 switch (ip_ver) {
1242 case ETH_P_IP:
1243 ip_proto = ip_hdr(skb)->protocol;
1244 break;
1245 case ETH_P_IPV6:
1246 ip_proto = ipv6_hdr(skb)->nexthdr;
1247 break;
1248 default:
bc23333b 1249 return skb;
1c1008c7
FF		 1250 }
1251
1252 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1253 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1254 (offset + skb->csum_offset);
1255
1256 /* Set the length valid bit for TCP and UDP and just set
1257 * the special UDP flag for IPv4, else just set to 0.
1258 */
1259 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1260 tx_csum_info |= STATUS_TX_CSUM_LV;
1261 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1262 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1263 } else {
1c1008c7 1264 tx_csum_info = 0;
8900ea57 1265 }
1c1008c7
FF		 1266
1267 status->tx_csum_info = tx_csum_info;
1268 }
1269
bc23333b 1270 return skb;
1c1008c7
FF		 1271}
1272
1273static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1274{
1275 struct bcmgenet_priv *priv = netdev_priv(dev);
1276 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1277 struct netdev_queue *txq;
1c1008c7
FF		 1278 unsigned long flags = 0;
1279 int nr_frags, index;
1280 u16 dma_desc_flags;
1281 int ret;
1282 int i;
1283
1284 index = skb_get_queue_mapping(skb);
1285 /* Mapping strategy:
1286 * queue_mapping = 0, unclassified, packet xmited through ring16
1287 * queue_mapping = 1, goes to ring 0. (highest priority queue
1288 * queue_mapping = 2, goes to ring 1.
1289 * queue_mapping = 3, goes to ring 2.
1290 * queue_mapping = 4, goes to ring 3.
1291 */
1292 if (index == 0)
1293 index = DESC_INDEX;
1294 else
1295 index -= 1;
1296
1c1008c7
FF		 1297 nr_frags = skb_shinfo(skb)->nr_frags;
1298 ring = &priv->tx_rings[index];
b2cde2cc 1299 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1300
1301 spin_lock_irqsave(&ring->lock, flags);
1302 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1303 netif_tx_stop_queue(txq);
1c1008c7 1304 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1305 __func__, index, ring->queue);
1c1008c7
FF		 1306 ret = NETDEV_TX_BUSY;
1307 goto out;
1308 }
1309
474ea9ca
FF		 1310 if (skb_padto(skb, ETH_ZLEN)) {
1311 ret = NETDEV_TX_OK;
1312 goto out;
1313 }
1314
1c1008c7
FF		 1315 /* set the SKB transmit checksum */
1316 if (priv->desc_64b_en) {
bc23333b
PG		 1317 skb = bcmgenet_put_tx_csum(dev, skb);
1318 if (!skb) {
1c1008c7
FF		 1319 ret = NETDEV_TX_OK;
1320 goto out;
1321 }
1322 }
1323
1324 dma_desc_flags = DMA_SOP;
1325 if (nr_frags == 0)
1326 dma_desc_flags |= DMA_EOP;
1327
1328 /* Transmit single SKB or head of fragment list */
1329 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1330 if (ret) {
1331 ret = NETDEV_TX_OK;
1332 goto out;
1333 }
1334
1335 /* xmit fragment */
1336 for (i = 0; i < nr_frags; i++) {
1337 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1338 &skb_shinfo(skb)->frags[i],
1339 (i == nr_frags - 1) ? DMA_EOP : 0,
1340 ring);
1c1008c7
FF		 1341 if (ret) {
1342 ret = NETDEV_TX_OK;
1343 goto out;
1344 }
1345 }
1346
d03825fb
FF		 1347 skb_tx_timestamp(skb);
1348
ae67bf01
FF		 1349 /* Decrement total BD count and advance our write pointer */
1350 ring->free_bds -= nr_frags + 1;
1351 ring->prod_index += nr_frags + 1;
1352 ring->prod_index &= DMA_P_INDEX_MASK;
1353
4092e6ac 1354 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1355 netif_tx_stop_queue(txq);
1c1008c7 1356
ddd0ca5d
FF		 1357 if (!skb->xmit_more || netif_xmit_stopped(txq))
1358 /* Packets are ready, update producer index */
1359 bcmgenet_tdma_ring_writel(priv, ring->index,
1360 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1361out:
1362 spin_unlock_irqrestore(&ring->lock, flags);
1363
1364 return ret;
1365}
1366
d6707bec
PG		 1367static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1368 struct enet_cb *cb)
1c1008c7
FF		 1369{
1370 struct device *kdev = &priv->pdev->dev;
1371 struct sk_buff *skb;
d6707bec 1372 struct sk_buff *rx_skb;
1c1008c7 1373 dma_addr_t mapping;
1c1008c7 1374
d6707bec 1375 /* Allocate a new Rx skb */
c91b7f66 1376 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
d6707bec
PG		 1377 if (!skb) {
1378 priv->mib.alloc_rx_buff_failed++;
1379 netif_err(priv, rx_err, priv->dev,
1380 "%s: Rx skb allocation failed\n", __func__);
1381 return NULL;
1382 }
1c1008c7 1383
d6707bec
PG		 1384 /* DMA-map the new Rx skb */
1385 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1386 DMA_FROM_DEVICE);
1387 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 1388 priv->mib.rx_dma_failed++;
d6707bec 1389 dev_kfree_skb_any(skb);
1c1008c7 1390 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 1391 "%s: Rx skb DMA mapping failed\n", __func__);
1392 return NULL;
1c1008c7
FF		 1393 }
1394
d6707bec
PG		 1395 /* Grab the current Rx skb from the ring and DMA-unmap it */
1396 rx_skb = cb->skb;
1397 if (likely(rx_skb))
1398 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1399 priv->rx_buf_len, DMA_FROM_DEVICE);
1400
1401 /* Put the new Rx skb on the ring */
1402 cb->skb = skb;
1c1008c7 1403 dma_unmap_addr_set(cb, dma_addr, mapping);
8ac467e8 1404 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 1405
d6707bec
PG		 1406 /* Return the current Rx skb to caller */
1407 return rx_skb;
1c1008c7
FF		 1408}
1409
1410/* bcmgenet_desc_rx - descriptor based rx process.
1411 * this could be called from bottom half, or from NAPI polling method.
1412 */
4055eaef 1413static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 1414 unsigned int budget)
1415{
4055eaef 1416 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 1417 struct net_device *dev = priv->dev;
1418 struct enet_cb *cb;
1419 struct sk_buff *skb;
1420 u32 dma_length_status;
1421 unsigned long dma_flag;
d6707bec 1422 int len;
1c1008c7
FF		 1423 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1424 unsigned int p_index;
d26ea6cc 1425 unsigned int discards;
1c1008c7
FF		 1426 unsigned int chksum_ok = 0;
1427
4055eaef 1428 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 1429
1430 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1431 DMA_P_INDEX_DISCARD_CNT_MASK;
1432 if (discards > ring->old_discards) {
1433 discards = discards - ring->old_discards;
1434 dev->stats.rx_missed_errors += discards;
1435 dev->stats.rx_errors += discards;
1436 ring->old_discards += discards;
1437
1438 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1439 if (ring->old_discards >= 0xC000) {
1440 ring->old_discards = 0;
4055eaef 1441 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 1442 RDMA_PROD_INDEX);
1443 }
1444 }
1445
1c1008c7
FF		 1446 p_index &= DMA_P_INDEX_MASK;
1447
8ac467e8
PG		 1448 if (likely(p_index >= ring->c_index))
1449 rxpkttoprocess = p_index - ring->c_index;
1c1008c7 1450 else
8ac467e8
PG		 1451 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1452 p_index;
1c1008c7
FF		 1453
1454 netif_dbg(priv, rx_status, dev,
c91b7f66 1455 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1456
1457 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1458 (rxpktprocessed < budget)) {
8ac467e8 1459 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 1460 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 1461
b629be5c
FF		 1462 if (unlikely(!skb)) {
1463 dev->stats.rx_dropped++;
d6707bec 1464 goto next;
b629be5c
FF		 1465 }
1466
1c1008c7 1467 if (!priv->desc_64b_en) {
c91b7f66 1468 dma_length_status =
8ac467e8 1469 dmadesc_get_length_status(priv, cb->bd_addr);
1c1008c7
FF		 1470 } else {
1471 struct status_64 *status;
164d4f20 1472
1c1008c7
FF		 1473 status = (struct status_64 *)skb->data;
1474 dma_length_status = status->length_status;
1475 }
1476
1477 /* DMA flags and length are still valid no matter how
1478 * we got the Receive Status Vector (64B RSB or register)
1479 */
1480 dma_flag = dma_length_status & 0xffff;
1481 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1482
1483 netif_dbg(priv, rx_status, dev,
c91b7f66 1484 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1485 __func__, p_index, ring->c_index,
1486 ring->read_ptr, dma_length_status);
1c1008c7 1487
1c1008c7
FF		 1488 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1489 netif_err(priv, rx_status, dev,
c91b7f66 1490 "dropping fragmented packet!\n");
1c1008c7 1491 dev->stats.rx_errors++;
d6707bec
PG		 1492 dev_kfree_skb_any(skb);
1493 goto next;
1c1008c7 1494 }
d6707bec 1495
1c1008c7
FF		 1496 /* report errors */
1497 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1498 DMA_RX_OV |
1499 DMA_RX_NO |
1500 DMA_RX_LG |
1501 DMA_RX_RXER))) {
1502 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1503 (unsigned int)dma_flag);
1c1008c7
FF		 1504 if (dma_flag & DMA_RX_CRC_ERROR)
1505 dev->stats.rx_crc_errors++;
1506 if (dma_flag & DMA_RX_OV)
1507 dev->stats.rx_over_errors++;
1508 if (dma_flag & DMA_RX_NO)
1509 dev->stats.rx_frame_errors++;
1510 if (dma_flag & DMA_RX_LG)
1511 dev->stats.rx_length_errors++;
1c1008c7 1512 dev->stats.rx_errors++;
d6707bec
PG		 1513 dev_kfree_skb_any(skb);
1514 goto next;
1c1008c7
FF		 1515 } /* error packet */
1516
1517 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1518 priv->desc_rxchk_en;
1c1008c7
FF		 1519
1520 skb_put(skb, len);
1521 if (priv->desc_64b_en) {
1522 skb_pull(skb, 64);
1523 len -= 64;
1524 }
1525
1526 if (likely(chksum_ok))
1527 skb->ip_summed = CHECKSUM_UNNECESSARY;
1528
1529 /* remove hardware 2bytes added for IP alignment */
1530 skb_pull(skb, 2);
1531 len -= 2;
1532
1533 if (priv->crc_fwd_en) {
1534 skb_trim(skb, len - ETH_FCS_LEN);
1535 len -= ETH_FCS_LEN;
1536 }
1537
1538 /*Finish setting up the received SKB and send it to the kernel*/
1539 skb->protocol = eth_type_trans(skb, priv->dev);
1540 dev->stats.rx_packets++;
1541 dev->stats.rx_bytes += len;
1542 if (dma_flag & DMA_RX_MULT)
1543 dev->stats.multicast++;
1544
1545 /* Notify kernel */
4055eaef 1546 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 1547 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1548
d6707bec 1549next:
cf377d88 1550 rxpktprocessed++;
8ac467e8
PG		 1551 if (likely(ring->read_ptr < ring->end_ptr))
1552 ring->read_ptr++;
1553 else
1554 ring->read_ptr = ring->cb_ptr;
1555
1556 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 1557 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1558 }
1559
1560 return rxpktprocessed;
1561}
1562
3ab11339
PG		 1563/* Rx NAPI polling method */
1564static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1565{
4055eaef
PG		 1566 struct bcmgenet_rx_ring *ring = container_of(napi,
1567 struct bcmgenet_rx_ring, napi);
3ab11339
PG		 1568 unsigned int work_done;
1569
4055eaef 1570 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 1571
1572 if (work_done < budget) {
1573 napi_complete(napi);
4055eaef 1574 ring->int_enable(ring);
3ab11339
PG		 1575 }
1576
1577 return work_done;
1578}
1579
1c1008c7 1580/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1581static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1582 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1583{
1584 struct enet_cb *cb;
d6707bec 1585 struct sk_buff *skb;
1c1008c7
FF		 1586 int i;
1587
8ac467e8 1588 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1589
1590 /* loop here for each buffer needing assign */
8ac467e8
PG		 1591 for (i = 0; i < ring->size; i++) {
1592 cb = ring->cbs + i;
d6707bec
PG		 1593 skb = bcmgenet_rx_refill(priv, cb);
1594 if (skb)
1595 dev_kfree_skb_any(skb);
1596 if (!cb->skb)
1597 return -ENOMEM;
1c1008c7
FF		 1598 }
1599
d6707bec 1600 return 0;
1c1008c7
FF		 1601}
1602
1603static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1604{
1605 struct enet_cb *cb;
1606 int i;
1607
1608 for (i = 0; i < priv->num_rx_bds; i++) {
1609 cb = &priv->rx_cbs[i];
1610
1611 if (dma_unmap_addr(cb, dma_addr)) {
1612 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1613 dma_unmap_addr(cb, dma_addr),
1614 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1615 dma_unmap_addr_set(cb, dma_addr, 0);
1616 }
1617
1618 if (cb->skb)
1619 bcmgenet_free_cb(cb);
1620 }
1621}
1622
c91b7f66 1623static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1624{
1625 u32 reg;
1626
1627 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1628 if (enable)
1629 reg |= mask;
1630 else
1631 reg &= ~mask;
1632 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1633
1634 /* UniMAC stops on a packet boundary, wait for a full-size packet
1635 * to be processed
1636 */
1637 if (enable == 0)
1638 usleep_range(1000, 2000);
1639}
1640
1c1008c7
FF		 1641static int reset_umac(struct bcmgenet_priv *priv)
1642{
1643 struct device *kdev = &priv->pdev->dev;
1644 unsigned int timeout = 0;
1645 u32 reg;
1646
1647 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1648 bcmgenet_rbuf_ctrl_set(priv, 0);
1649 udelay(10);
1650
1651 /* disable MAC while updating its registers */
1652 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1653
1654 /* issue soft reset, wait for it to complete */
1655 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1656 while (timeout++ < 1000) {
1657 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1658 if (!(reg & CMD_SW_RESET))
1659 return 0;
1660
1661 udelay(1);
1662 }
1663
1664 if (timeout == 1000) {
1665 dev_err(kdev,
7fc527f9 1666 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1667 return -ETIMEDOUT;
1668 }
1669
1670 return 0;
1671}
1672
909ff5ef
FF		 1673static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1674{
1675 /* Mask all interrupts.*/
1676 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1677 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1678 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1679 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1680 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1681 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1682}
1683
1c1008c7
FF		 1684static int init_umac(struct bcmgenet_priv *priv)
1685{
1686 struct device *kdev = &priv->pdev->dev;
1687 int ret;
b2e97eca
PG		 1688 u32 reg;
1689 u32 int0_enable = 0;
1690 u32 int1_enable = 0;
1691 int i;
1c1008c7
FF		 1692
1693 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1694
1695 ret = reset_umac(priv);
1696 if (ret)
1697 return ret;
1698
1699 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1700 /* clear tx/rx counter */
1701 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1702 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1703 UMAC_MIB_CTRL);
1c1008c7
FF		 1704 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1705
1706 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1707
1708 /* init rx registers, enable ip header optimization */
1709 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1710 reg |= RBUF_ALIGN_2B;
1711 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1712
1713 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1714 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1715
909ff5ef 1716 bcmgenet_intr_disable(priv);
1c1008c7 1717
b2e97eca 1718 /* Enable Rx default queue 16 interrupts */
ee7d8c20 1719 int0_enable |= UMAC_IRQ_RXDMA_DONE;
1c1008c7 1720
b2e97eca 1721 /* Enable Tx default queue 16 interrupts */
ee7d8c20 1722 int0_enable |= UMAC_IRQ_TXDMA_DONE;
1c1008c7 1723
7fc527f9 1724 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1725 if (phy_is_internal(priv->phydev)) {
e122966d 1726 int0_enable |= UMAC_IRQ_LINK_EVENT;
8900ea57 1727 } else if (priv->ext_phy) {
e122966d 1728 int0_enable |= UMAC_IRQ_LINK_EVENT;
8900ea57 1729 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
8d88c6eb
PG		 1730 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1731 int0_enable |= UMAC_IRQ_LINK_EVENT;
1732
1c1008c7
FF		 1733 reg = bcmgenet_bp_mc_get(priv);
1734 reg |= BIT(priv->hw_params->bp_in_en_shift);
1735
1736 /* bp_mask: back pressure mask */
1737 if (netif_is_multiqueue(priv->dev))
1738 reg |= priv->hw_params->bp_in_mask;
1739 else
1740 reg &= ~priv->hw_params->bp_in_mask;
1741 bcmgenet_bp_mc_set(priv, reg);
1742 }
1743
1744 /* Enable MDIO interrupts on GENET v3+ */
1745 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 1746 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 1747
4055eaef
PG		 1748 /* Enable Rx priority queue interrupts */
1749 for (i = 0; i < priv->hw_params->rx_queues; ++i)
1750 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1751
b2e97eca
PG		 1752 /* Enable Tx priority queue interrupts */
1753 for (i = 0; i < priv->hw_params->tx_queues; ++i)
1754 int1_enable |= (1 << i);
1c1008c7 1755
b2e97eca
PG		 1756 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1757 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 1758
1c1008c7
FF		 1759 /* Enable rx/tx engine.*/
1760 dev_dbg(kdev, "done init umac\n");
1761
1762 return 0;
1763}
1764
4f8b2d7d 1765/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1766static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1767 unsigned int index, unsigned int size,
4f8b2d7d 1768 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1769{
1770 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1771 u32 words_per_bd = WORDS_PER_BD(priv);
1772 u32 flow_period_val = 0;
1c1008c7
FF		 1773
1774 spin_lock_init(&ring->lock);
4092e6ac 1775 ring->priv = priv;
1c1008c7
FF		 1776 ring->index = index;
1777 if (index == DESC_INDEX) {
1778 ring->queue = 0;
1779 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1780 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1781 } else {
1782 ring->queue = index + 1;
1783 ring->int_enable = bcmgenet_tx_ring_int_enable;
1784 ring->int_disable = bcmgenet_tx_ring_int_disable;
1785 }
4f8b2d7d 1786 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1787 ring->size = size;
66d06757 1788 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1789 ring->c_index = 0;
1790 ring->free_bds = size;
4f8b2d7d
PG		 1791 ring->write_ptr = start_ptr;
1792 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1793 ring->end_ptr = end_ptr - 1;
1794 ring->prod_index = 0;
1795
1796 /* Set flow period for ring != 16 */
1797 if (index != DESC_INDEX)
1798 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1799
1800 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1801 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1802 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1803 /* Disable rate control for now */
1804 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1805 TDMA_FLOW_PERIOD);
1c1008c7 1806 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1807 ((size << DMA_RING_SIZE_SHIFT) |
1808 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1809
1c1008c7 1810 /* Set start and end address, read and write pointers */
4f8b2d7d 1811 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1812 DMA_START_ADDR);
4f8b2d7d 1813 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1814 TDMA_READ_PTR);
4f8b2d7d 1815 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1816 TDMA_WRITE_PTR);
1c1008c7 1817 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1818 DMA_END_ADDR);
1c1008c7
FF		 1819}
1820
1821/* Initialize a RDMA ring */
1822static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 1823 unsigned int index, unsigned int size,
1824 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 1825{
8ac467e8 1826 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 1827 u32 words_per_bd = WORDS_PER_BD(priv);
1828 int ret;
1829
4055eaef 1830 ring->priv = priv;
8ac467e8 1831 ring->index = index;
4055eaef
PG		 1832 if (index == DESC_INDEX) {
1833 ring->int_enable = bcmgenet_rx_ring16_int_enable;
1834 ring->int_disable = bcmgenet_rx_ring16_int_disable;
1835 } else {
1836 ring->int_enable = bcmgenet_rx_ring_int_enable;
1837 ring->int_disable = bcmgenet_rx_ring_int_disable;
1838 }
8ac467e8
PG		 1839 ring->cbs = priv->rx_cbs + start_ptr;
1840 ring->size = size;
1841 ring->c_index = 0;
1842 ring->read_ptr = start_ptr;
1843 ring->cb_ptr = start_ptr;
1844 ring->end_ptr = end_ptr - 1;
1c1008c7 1845
8ac467e8
PG		 1846 ret = bcmgenet_alloc_rx_buffers(priv, ring);
1847 if (ret)
1c1008c7 1848 return ret;
1c1008c7 1849
1c1008c7
FF		 1850 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1851 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 1852 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 1853 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1854 ((size << DMA_RING_SIZE_SHIFT) |
1855 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1856 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1857 (DMA_FC_THRESH_LO <<
1858 DMA_XOFF_THRESHOLD_SHIFT) |
1859 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 1860
1861 /* Set start and end address, read and write pointers */
8ac467e8
PG		 1862 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1863 DMA_START_ADDR);
1864 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1865 RDMA_READ_PTR);
1866 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1867 RDMA_WRITE_PTR);
1868 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 1869 DMA_END_ADDR);
1c1008c7
FF		 1870
1871 return ret;
1872}
1873
e2aadb4a
PG		 1874static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
1875{
1876 unsigned int i;
1877 struct bcmgenet_tx_ring *ring;
1878
1879 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1880 ring = &priv->tx_rings[i];
1881 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1882 }
1883
1884 ring = &priv->tx_rings[DESC_INDEX];
1885 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1886}
1887
1888static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
1889{
1890 unsigned int i;
1891 struct bcmgenet_tx_ring *ring;
1892
1893 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1894 ring = &priv->tx_rings[i];
1895 napi_enable(&ring->napi);
1896 }
1897
1898 ring = &priv->tx_rings[DESC_INDEX];
1899 napi_enable(&ring->napi);
1900}
1901
1902static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
1903{
1904 unsigned int i;
1905 struct bcmgenet_tx_ring *ring;
1906
1907 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1908 ring = &priv->tx_rings[i];
1909 napi_disable(&ring->napi);
1910 }
1911
1912 ring = &priv->tx_rings[DESC_INDEX];
1913 napi_disable(&ring->napi);
1914}
1915
1916static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
1917{
1918 unsigned int i;
1919 struct bcmgenet_tx_ring *ring;
1920
1921 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1922 ring = &priv->tx_rings[i];
1923 netif_napi_del(&ring->napi);
1924 }
1925
1926 ring = &priv->tx_rings[DESC_INDEX];
1927 netif_napi_del(&ring->napi);
1928}
1929
16c6d667 1930/* Initialize Tx queues
1c1008c7 1931 *
16c6d667 1932 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 1933 * with queue 0 being the highest priority queue.
1934 *
16c6d667 1935 * Queue 16 is the default Tx queue with
51a966a7 1936 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 1937 *
16c6d667
PG		 1938 * The transmit control block pool is then partitioned as follows:
1939 * - Tx queue 0 uses tx_cbs[0..31]
1940 * - Tx queue 1 uses tx_cbs[32..63]
1941 * - Tx queue 2 uses tx_cbs[64..95]
1942 * - Tx queue 3 uses tx_cbs[96..127]
1943 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 1944 */
16c6d667 1945static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 1946{
1947 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 1948 u32 i, dma_enable;
1949 u32 dma_ctrl, ring_cfg;
37742166 1950 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 1951
1c1008c7
FF		 1952 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1953 dma_enable = dma_ctrl & DMA_EN;
1954 dma_ctrl &= ~DMA_EN;
1955 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1956
16c6d667
PG		 1957 dma_ctrl = 0;
1958 ring_cfg = 0;
1959
1c1008c7
FF		 1960 /* Enable strict priority arbiter mode */
1961 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1962
16c6d667 1963 /* Initialize Tx priority queues */
1c1008c7 1964 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 1965 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
1966 i * priv->hw_params->tx_bds_per_q,
1967 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 1968 ring_cfg |= (1 << i);
1969 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1970 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1971 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 1972 }
1973
16c6d667 1974 /* Initialize Tx default queue 16 */
51a966a7 1975 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 1976 priv->hw_params->tx_queues *
51a966a7 1977 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 1978 TOTAL_DESC);
1979 ring_cfg |= (1 << DESC_INDEX);
1980 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1981 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1982 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1983 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 1984
1985 /* Set Tx queue priorities */
37742166
PG		 1986 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1987 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1988 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1989
e2aadb4a
PG		 1990 /* Initialize Tx NAPI */
1991 bcmgenet_init_tx_napi(priv);
1992
16c6d667
PG		 1993 /* Enable Tx queues */
1994 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 1995
16c6d667 1996 /* Enable Tx DMA */
1c1008c7 1997 if (dma_enable)
16c6d667
PG		 1998 dma_ctrl |= DMA_EN;
1999 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2000}
2001
3ab11339
PG		 2002static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2003{
4055eaef
PG		 2004 unsigned int i;
2005 struct bcmgenet_rx_ring *ring;
2006
2007 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2008 ring = &priv->rx_rings[i];
2009 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2010 }
2011
2012 ring = &priv->rx_rings[DESC_INDEX];
2013 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
3ab11339
PG		 2014}
2015
2016static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2017{
4055eaef
PG		 2018 unsigned int i;
2019 struct bcmgenet_rx_ring *ring;
2020
2021 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2022 ring = &priv->rx_rings[i];
2023 napi_enable(&ring->napi);
2024 }
2025
2026 ring = &priv->rx_rings[DESC_INDEX];
2027 napi_enable(&ring->napi);
3ab11339
PG		 2028}
2029
2030static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2031{
4055eaef
PG		 2032 unsigned int i;
2033 struct bcmgenet_rx_ring *ring;
2034
2035 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2036 ring = &priv->rx_rings[i];
2037 napi_disable(&ring->napi);
2038 }
2039
2040 ring = &priv->rx_rings[DESC_INDEX];
2041 napi_disable(&ring->napi);
3ab11339
PG		 2042}
2043
2044static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2045{
4055eaef
PG		 2046 unsigned int i;
2047 struct bcmgenet_rx_ring *ring;
2048
2049 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2050 ring = &priv->rx_rings[i];
2051 netif_napi_del(&ring->napi);
2052 }
2053
2054 ring = &priv->rx_rings[DESC_INDEX];
2055 netif_napi_del(&ring->napi);
3ab11339
PG		 2056}
2057
8ac467e8
PG		 2058/* Initialize Rx queues
2059 *
2060 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2061 * used to direct traffic to these queues.
2062 *
2063 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2064 */
2065static int bcmgenet_init_rx_queues(struct net_device *dev)
2066{
2067 struct bcmgenet_priv *priv = netdev_priv(dev);
2068 u32 i;
2069 u32 dma_enable;
2070 u32 dma_ctrl;
2071 u32 ring_cfg;
2072 int ret;
2073
2074 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2075 dma_enable = dma_ctrl & DMA_EN;
2076 dma_ctrl &= ~DMA_EN;
2077 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2078
2079 dma_ctrl = 0;
2080 ring_cfg = 0;
2081
2082 /* Initialize Rx priority queues */
2083 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2084 ret = bcmgenet_init_rx_ring(priv, i,
2085 priv->hw_params->rx_bds_per_q,
2086 i * priv->hw_params->rx_bds_per_q,
2087 (i + 1) *
2088 priv->hw_params->rx_bds_per_q);
2089 if (ret)
2090 return ret;
2091
2092 ring_cfg |= (1 << i);
2093 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2094 }
2095
2096 /* Initialize Rx default queue 16 */
2097 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2098 priv->hw_params->rx_queues *
2099 priv->hw_params->rx_bds_per_q,
2100 TOTAL_DESC);
2101 if (ret)
2102 return ret;
2103
2104 ring_cfg |= (1 << DESC_INDEX);
2105 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2106
3ab11339
PG		 2107 /* Initialize Rx NAPI */
2108 bcmgenet_init_rx_napi(priv);
2109
8ac467e8
PG		 2110 /* Enable rings */
2111 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2112
2113 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2114 if (dma_enable)
2115 dma_ctrl |= DMA_EN;
2116 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2117
2118 return 0;
2119}
2120
4a0c081e
FF		 2121static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2122{
2123 int ret = 0;
2124 int timeout = 0;
2125 u32 reg;
2126
2127 /* Disable TDMA to stop add more frames in TX DMA */
2128 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2129 reg &= ~DMA_EN;
2130 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2131
2132 /* Check TDMA status register to confirm TDMA is disabled */
2133 while (timeout++ < DMA_TIMEOUT_VAL) {
2134 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2135 if (reg & DMA_DISABLED)
2136 break;
2137
2138 udelay(1);
2139 }
2140
2141 if (timeout == DMA_TIMEOUT_VAL) {
2142 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2143 ret = -ETIMEDOUT;
2144 }
2145
2146 /* Wait 10ms for packet drain in both tx and rx dma */
2147 usleep_range(10000, 20000);
2148
2149 /* Disable RDMA */
2150 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2151 reg &= ~DMA_EN;
2152 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2153
2154 timeout = 0;
2155 /* Check RDMA status register to confirm RDMA is disabled */
2156 while (timeout++ < DMA_TIMEOUT_VAL) {
2157 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2158 if (reg & DMA_DISABLED)
2159 break;
2160
2161 udelay(1);
2162 }
2163
2164 if (timeout == DMA_TIMEOUT_VAL) {
2165 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2166 ret = -ETIMEDOUT;
2167 }
2168
2169 return ret;
2170}
2171
9abab96d 2172static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 2173{
2174 int i;
2175
9abab96d
PG		 2176 bcmgenet_fini_rx_napi(priv);
2177 bcmgenet_fini_tx_napi(priv);
2178
1c1008c7 2179 /* disable DMA */
4a0c081e 2180 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2181
2182 for (i = 0; i < priv->num_tx_bds; i++) {
2183 if (priv->tx_cbs[i].skb != NULL) {
2184 dev_kfree_skb(priv->tx_cbs[i].skb);
2185 priv->tx_cbs[i].skb = NULL;
2186 }
2187 }
2188
2189 bcmgenet_free_rx_buffers(priv);
2190 kfree(priv->rx_cbs);
2191 kfree(priv->tx_cbs);
2192}
2193
2194/* init_edma: Initialize DMA control register */
2195static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2196{
2197 int ret;
014012a4
PG		 2198 unsigned int i;
2199 struct enet_cb *cb;
1c1008c7 2200
6f5a272c 2201 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2202
6f5a272c
PG		 2203 /* Initialize common Rx ring structures */
2204 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2205 priv->num_rx_bds = TOTAL_DESC;
2206 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2207 GFP_KERNEL);
2208 if (!priv->rx_cbs)
2209 return -ENOMEM;
2210
2211 for (i = 0; i < priv->num_rx_bds; i++) {
2212 cb = priv->rx_cbs + i;
2213 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2214 }
2215
7fc527f9 2216 /* Initialize common TX ring structures */
1c1008c7
FF		 2217 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2218 priv->num_tx_bds = TOTAL_DESC;
c489be08 2219 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2220 GFP_KERNEL);
1c1008c7 2221 if (!priv->tx_cbs) {
ebbd96fb 2222 kfree(priv->rx_cbs);
1c1008c7
FF		 2223 return -ENOMEM;
2224 }
2225
014012a4
PG		 2226 for (i = 0; i < priv->num_tx_bds; i++) {
2227 cb = priv->tx_cbs + i;
2228 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2229 }
2230
ebbd96fb
PG		 2231 /* Init rDma */
2232 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2233
2234 /* Initialize Rx queues */
2235 ret = bcmgenet_init_rx_queues(priv->dev);
2236 if (ret) {
2237 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2238 bcmgenet_free_rx_buffers(priv);
2239 kfree(priv->rx_cbs);
2240 kfree(priv->tx_cbs);
2241 return ret;
2242 }
2243
2244 /* Init tDma */
2245 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2246
16c6d667
PG		 2247 /* Initialize Tx queues */
2248 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2249
2250 return 0;
2251}
2252
1c1008c7
FF		 2253/* Interrupt bottom half */
2254static void bcmgenet_irq_task(struct work_struct *work)
2255{
2256 struct bcmgenet_priv *priv = container_of(
2257 work, struct bcmgenet_priv, bcmgenet_irq_work);
2258
2259 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2260
8fdb0e0f
FF		 2261 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2262 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2263 netif_dbg(priv, wol, priv->dev,
2264 "magic packet detected, waking up\n");
2265 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2266 }
2267
1c1008c7
FF		 2268 /* Link UP/DOWN event */
2269 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
e122966d 2270 (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) {
80d8e96d 2271 phy_mac_interrupt(priv->phydev,
451e1ca2 2272 !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
e122966d 2273 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
1c1008c7
FF		 2274 }
2275}
2276
4055eaef 2277/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 2278static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2279{
2280 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2281 struct bcmgenet_rx_ring *rx_ring;
2282 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2283 unsigned int index;
2284
2285 /* Save irq status for bottom-half processing. */
2286 priv->irq1_stat =
2287 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2288 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2289
7fc527f9 2290 /* clear interrupts */
1c1008c7
FF		 2291 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2292
2293 netif_dbg(priv, intr, priv->dev,
c91b7f66 2294 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2295
4055eaef
PG		 2296 /* Check Rx priority queue interrupts */
2297 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2298 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2299 continue;
2300
2301 rx_ring = &priv->rx_rings[index];
2302
2303 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2304 rx_ring->int_disable(rx_ring);
2305 __napi_schedule(&rx_ring->napi);
2306 }
2307 }
2308
2309 /* Check Tx priority queue interrupts */
4092e6ac
JS		 2310 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2311 if (!(priv->irq1_stat & BIT(index)))
2312 continue;
2313
4055eaef 2314 tx_ring = &priv->tx_rings[index];
4092e6ac 2315
4055eaef
PG		 2316 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2317 tx_ring->int_disable(tx_ring);
2318 __napi_schedule(&tx_ring->napi);
1c1008c7
FF		 2319 }
2320 }
4092e6ac 2321
1c1008c7
FF		 2322 return IRQ_HANDLED;
2323}
2324
4055eaef 2325/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 2326static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2327{
2328 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2329 struct bcmgenet_rx_ring *rx_ring;
2330 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2331
2332 /* Save irq status for bottom-half processing. */
2333 priv->irq0_stat =
2334 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2335 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2336
7fc527f9 2337 /* clear interrupts */
1c1008c7
FF		 2338 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2339
2340 netif_dbg(priv, intr, priv->dev,
c91b7f66 2341 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7 2342
ee7d8c20 2343 if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
4055eaef
PG		 2344 rx_ring = &priv->rx_rings[DESC_INDEX];
2345
2346 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2347 rx_ring->int_disable(rx_ring);
2348 __napi_schedule(&rx_ring->napi);
1c1008c7
FF		 2349 }
2350 }
4092e6ac 2351
ee7d8c20 2352 if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 2353 tx_ring = &priv->tx_rings[DESC_INDEX];
2354
2355 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2356 tx_ring->int_disable(tx_ring);
2357 __napi_schedule(&tx_ring->napi);
4092e6ac 2358 }
1c1008c7 2359 }
4055eaef 2360
1c1008c7
FF		 2361 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2362 UMAC_IRQ_PHY_DET_F |
e122966d 2363 UMAC_IRQ_LINK_EVENT |
1c1008c7
FF		 2364 UMAC_IRQ_HFB_SM |
2365 UMAC_IRQ_HFB_MM |
2366 UMAC_IRQ_MPD_R)) {
2367 /* all other interested interrupts handled in bottom half */
2368 schedule_work(&priv->bcmgenet_irq_work);
2369 }
2370
2371 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2372 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2373 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2374 wake_up(&priv->wq);
2375 }
2376
2377 return IRQ_HANDLED;
2378}
2379
8562056f
FF		 2380static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2381{
2382 struct bcmgenet_priv *priv = dev_id;
2383
2384 pm_wakeup_event(&priv->pdev->dev, 0);
2385
2386 return IRQ_HANDLED;
2387}
2388
1c1008c7
FF		 2389static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2390{
2391 u32 reg;
2392
2393 reg = bcmgenet_rbuf_ctrl_get(priv);
2394 reg |= BIT(1);
2395 bcmgenet_rbuf_ctrl_set(priv, reg);
2396 udelay(10);
2397
2398 reg &= ~BIT(1);
2399 bcmgenet_rbuf_ctrl_set(priv, reg);
2400 udelay(10);
2401}
2402
2403static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2404 unsigned char *addr)
1c1008c7
FF		 2405{
2406 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2407 (addr[2] << 8) | addr[3], UMAC_MAC0);
2408 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2409}
2410
1c1008c7
FF		 2411/* Returns a reusable dma control register value */
2412static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2413{
2414 u32 reg;
2415 u32 dma_ctrl;
2416
2417 /* disable DMA */
2418 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2419 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2420 reg &= ~dma_ctrl;
2421 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2422
2423 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2424 reg &= ~dma_ctrl;
2425 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2426
2427 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2428 udelay(10);
2429 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2430
2431 return dma_ctrl;
2432}
2433
2434static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2435{
2436 u32 reg;
2437
2438 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2439 reg |= dma_ctrl;
2440 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2441
2442 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2443 reg |= dma_ctrl;
2444 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2445}
2446
0034de41
PG		 2447static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2448 u32 f_index)
2449{
2450 u32 offset;
2451 u32 reg;
2452
2453 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2454 reg = bcmgenet_hfb_reg_readl(priv, offset);
2455 return !!(reg & (1 << (f_index % 32)));
2456}
2457
2458static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2459{
2460 u32 offset;
2461 u32 reg;
2462
2463 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2464 reg = bcmgenet_hfb_reg_readl(priv, offset);
2465 reg |= (1 << (f_index % 32));
2466 bcmgenet_hfb_reg_writel(priv, reg, offset);
2467}
2468
2469static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2470 u32 f_index, u32 rx_queue)
2471{
2472 u32 offset;
2473 u32 reg;
2474
2475 offset = f_index / 8;
2476 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2477 reg &= ~(0xF << (4 * (f_index % 8)));
2478 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2479 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2480}
2481
2482static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2483 u32 f_index, u32 f_length)
2484{
2485 u32 offset;
2486 u32 reg;
2487
2488 offset = HFB_FLT_LEN_V3PLUS +
2489 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2490 sizeof(u32);
2491 reg = bcmgenet_hfb_reg_readl(priv, offset);
2492 reg &= ~(0xFF << (8 * (f_index % 4)));
2493 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2494 bcmgenet_hfb_reg_writel(priv, reg, offset);
2495}
2496
2497static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2498{
2499 u32 f_index;
2500
2501 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2502 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2503 return f_index;
2504
2505 return -ENOMEM;
2506}
2507
2508/* bcmgenet_hfb_add_filter
2509 *
2510 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2511 * desired Rx queue.
2512 *
2513 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2514 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2515 *
2516 * bits 31:20 - unused
2517 * bit 19 - nibble 0 match enable
2518 * bit 18 - nibble 1 match enable
2519 * bit 17 - nibble 2 match enable
2520 * bit 16 - nibble 3 match enable
2521 * bits 15:12 - nibble 0 data
2522 * bits 11:8 - nibble 1 data
2523 * bits 7:4 - nibble 2 data
2524 * bits 3:0 - nibble 3 data
2525 *
2526 * Example:
2527 * In order to match:
2528 * - Ethernet frame type = 0x0800 (IP)
2529 * - IP version field = 4
2530 * - IP protocol field = 0x11 (UDP)
2531 *
2532 * The following filter is needed:
2533 * u32 hfb_filter_ipv4_udp[] = {
2534 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2535 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2536 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2537 * };
2538 *
2539 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2540 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2541 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2542 */
2543int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2544 u32 f_length, u32 rx_queue)
2545{
2546 int f_index;
2547 u32 i;
2548
2549 f_index = bcmgenet_hfb_find_unused_filter(priv);
2550 if (f_index < 0)
2551 return -ENOMEM;
2552
2553 if (f_length > priv->hw_params->hfb_filter_size)
2554 return -EINVAL;
2555
2556 for (i = 0; i < f_length; i++)
2557 bcmgenet_hfb_writel(priv, f_data[i],
2558 (f_index * priv->hw_params->hfb_filter_size + i) *
2559 sizeof(u32));
2560
2561 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2562 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2563 bcmgenet_hfb_enable_filter(priv, f_index);
2564 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2565
2566 return 0;
2567}
2568
2569/* bcmgenet_hfb_clear
2570 *
2571 * Clear Hardware Filter Block and disable all filtering.
2572 */
2573static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2574{
2575 u32 i;
2576
2577 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2578 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2579 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2580
2581 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2582 bcmgenet_rdma_writel(priv, 0x0, i);
2583
2584 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2585 bcmgenet_hfb_reg_writel(priv, 0x0,
2586 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2587
2588 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2589 priv->hw_params->hfb_filter_size; i++)
2590 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2591}
2592
2593static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2594{
2595 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2596 return;
2597
2598 bcmgenet_hfb_clear(priv);
2599}
2600
909ff5ef
FF		 2601static void bcmgenet_netif_start(struct net_device *dev)
2602{
2603 struct bcmgenet_priv *priv = netdev_priv(dev);
2604
2605 /* Start the network engine */
3ab11339 2606 bcmgenet_enable_rx_napi(priv);
e2aadb4a 2607 bcmgenet_enable_tx_napi(priv);
909ff5ef
FF		 2608
2609 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2610
909ff5ef
FF		 2611 netif_tx_start_all_queues(dev);
2612
2613 phy_start(priv->phydev);
2614}
2615
1c1008c7
FF		 2616static int bcmgenet_open(struct net_device *dev)
2617{
2618 struct bcmgenet_priv *priv = netdev_priv(dev);
2619 unsigned long dma_ctrl;
2620 u32 reg;
2621 int ret;
2622
2623 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2624
2625 /* Turn on the clock */
2626 if (!IS_ERR(priv->clk))
2627 clk_prepare_enable(priv->clk);
2628
a642c4f7
FF		 2629 /* If this is an internal GPHY, power it back on now, before UniMAC is
2630 * brought out of reset as absolutely no UniMAC activity is allowed
2631 */
2632 if (phy_is_internal(priv->phydev))
2633 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2634
1c1008c7
FF		 2635 /* take MAC out of reset */
2636 bcmgenet_umac_reset(priv);
2637
2638 ret = init_umac(priv);
2639 if (ret)
2640 goto err_clk_disable;
2641
2642 /* disable ethernet MAC while updating its registers */
e29585b8 2643 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2644
909ff5ef
FF		 2645 /* Make sure we reflect the value of CRC_CMD_FWD */
2646 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2647 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2648
1c1008c7
FF		 2649 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2650
1c1008c7
FF		 2651 if (phy_is_internal(priv->phydev)) {
2652 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2653 reg |= EXT_ENERGY_DET_MASK;
2654 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2655 }
2656
2657 /* Disable RX/TX DMA and flush TX queues */
2658 dma_ctrl = bcmgenet_dma_disable(priv);
2659
2660 /* Reinitialize TDMA and RDMA and SW housekeeping */
2661 ret = bcmgenet_init_dma(priv);
2662 if (ret) {
2663 netdev_err(dev, "failed to initialize DMA\n");
fac25940 2664 goto err_clk_disable;
1c1008c7
FF		 2665 }
2666
2667 /* Always enable ring 16 - descriptor ring */
2668 bcmgenet_enable_dma(priv, dma_ctrl);
2669
0034de41
PG		 2670 /* HFB init */
2671 bcmgenet_hfb_init(priv);
2672
1c1008c7 2673 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2674 dev->name, priv);
1c1008c7
FF		 2675 if (ret < 0) {
2676 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2677 goto err_fini_dma;
2678 }
2679
2680 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2681 dev->name, priv);
1c1008c7
FF		 2682 if (ret < 0) {
2683 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2684 goto err_irq0;
2685 }
2686
dbd479db
FF		 2687 /* Re-configure the port multiplexer towards the PHY device */
2688 bcmgenet_mii_config(priv->dev, false);
2689
c96e731c
FF		 2690 phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2691 priv->phy_interface);
2692
909ff5ef 2693 bcmgenet_netif_start(dev);
1c1008c7
FF		 2694
2695 return 0;
2696
2697err_irq0:
2698 free_irq(priv->irq0, dev);
2699err_fini_dma:
2700 bcmgenet_fini_dma(priv);
2701err_clk_disable:
2702 if (!IS_ERR(priv->clk))
2703 clk_disable_unprepare(priv->clk);
2704 return ret;
2705}
2706
909ff5ef
FF		 2707static void bcmgenet_netif_stop(struct net_device *dev)
2708{
2709 struct bcmgenet_priv *priv = netdev_priv(dev);
2710
2711 netif_tx_stop_all_queues(dev);
909ff5ef 2712 phy_stop(priv->phydev);
909ff5ef 2713 bcmgenet_intr_disable(priv);
3ab11339 2714 bcmgenet_disable_rx_napi(priv);
e2aadb4a 2715 bcmgenet_disable_tx_napi(priv);
909ff5ef
FF		 2716
2717 /* Wait for pending work items to complete. Since interrupts are
2718 * disabled no new work will be scheduled.
2719 */
2720 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2721
cc013fb4 2722 priv->old_link = -1;
5ad6e6c5 2723 priv->old_speed = -1;
cc013fb4 2724 priv->old_duplex = -1;
5ad6e6c5 2725 priv->old_pause = -1;
909ff5ef
FF		 2726}
2727
1c1008c7
FF		 2728static int bcmgenet_close(struct net_device *dev)
2729{
2730 struct bcmgenet_priv *priv = netdev_priv(dev);
2731 int ret;
1c1008c7
FF		 2732
2733 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2734
909ff5ef 2735 bcmgenet_netif_stop(dev);
1c1008c7 2736
c96e731c
FF		 2737 /* Really kill the PHY state machine and disconnect from it */
2738 phy_disconnect(priv->phydev);
2739
1c1008c7 2740 /* Disable MAC receive */
e29585b8 2741 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2742
1c1008c7
FF		 2743 ret = bcmgenet_dma_teardown(priv);
2744 if (ret)
2745 return ret;
2746
2747 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2748 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2749
1c1008c7
FF		 2750 /* tx reclaim */
2751 bcmgenet_tx_reclaim_all(dev);
2752 bcmgenet_fini_dma(priv);
2753
2754 free_irq(priv->irq0, priv);
2755 free_irq(priv->irq1, priv);
2756
1c1008c7 2757 if (phy_is_internal(priv->phydev))
ca8cf341 2758 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 2759
1c1008c7
FF		 2760 if (!IS_ERR(priv->clk))
2761 clk_disable_unprepare(priv->clk);
2762
ca8cf341 2763 return ret;
1c1008c7
FF		 2764}
2765
13ea6578
FF		 2766static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2767{
2768 struct bcmgenet_priv *priv = ring->priv;
2769 u32 p_index, c_index, intsts, intmsk;
2770 struct netdev_queue *txq;
2771 unsigned int free_bds;
2772 unsigned long flags;
2773 bool txq_stopped;
2774
2775 if (!netif_msg_tx_err(priv))
2776 return;
2777
2778 txq = netdev_get_tx_queue(priv->dev, ring->queue);
2779
2780 spin_lock_irqsave(&ring->lock, flags);
2781 if (ring->index == DESC_INDEX) {
2782 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2783 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2784 } else {
2785 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2786 intmsk = 1 << ring->index;
2787 }
2788 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2789 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2790 txq_stopped = netif_tx_queue_stopped(txq);
2791 free_bds = ring->free_bds;
2792 spin_unlock_irqrestore(&ring->lock, flags);
2793
2794 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2795 "TX queue status: %s, interrupts: %s\n"
2796 "(sw)free_bds: %d (sw)size: %d\n"
2797 "(sw)p_index: %d (hw)p_index: %d\n"
2798 "(sw)c_index: %d (hw)c_index: %d\n"
2799 "(sw)clean_p: %d (sw)write_p: %d\n"
2800 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2801 ring->index, ring->queue,
2802 txq_stopped ? "stopped" : "active",
2803 intsts & intmsk ? "enabled" : "disabled",
2804 free_bds, ring->size,
2805 ring->prod_index, p_index & DMA_P_INDEX_MASK,
2806 ring->c_index, c_index & DMA_C_INDEX_MASK,
2807 ring->clean_ptr, ring->write_ptr,
2808 ring->cb_ptr, ring->end_ptr);
2809}
2810
1c1008c7
FF		 2811static void bcmgenet_timeout(struct net_device *dev)
2812{
2813 struct bcmgenet_priv *priv = netdev_priv(dev);
13ea6578
FF		 2814 u32 int0_enable = 0;
2815 u32 int1_enable = 0;
2816 unsigned int q;
1c1008c7
FF		 2817
2818 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2819
13ea6578
FF		 2820 bcmgenet_disable_tx_napi(priv);
2821
2822 for (q = 0; q < priv->hw_params->tx_queues; q++)
2823 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
2824 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
2825
2826 bcmgenet_tx_reclaim_all(dev);
2827
2828 for (q = 0; q < priv->hw_params->tx_queues; q++)
2829 int1_enable |= (1 << q);
2830
2831 int0_enable = UMAC_IRQ_TXDMA_DONE;
2832
2833 /* Re-enable TX interrupts if disabled */
2834 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2835 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2836
2837 bcmgenet_enable_tx_napi(priv);
2838
1c1008c7
FF		 2839 dev->trans_start = jiffies;
2840
2841 dev->stats.tx_errors++;
2842
2843 netif_tx_wake_all_queues(dev);
2844}
2845
2846#define MAX_MC_COUNT 16
2847
2848static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2849 unsigned char *addr,
2850 int *i,
2851 int *mc)
2852{
2853 u32 reg;
2854
c91b7f66
FF		 2855 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2856 UMAC_MDF_ADDR + (*i * 4));
2857 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2858 addr[4] << 8 | addr[5],
2859 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2860 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2861 reg |= (1 << (MAX_MC_COUNT - *mc));
2862 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2863 *i += 2;
2864 (*mc)++;
2865}
2866
2867static void bcmgenet_set_rx_mode(struct net_device *dev)
2868{
2869 struct bcmgenet_priv *priv = netdev_priv(dev);
2870 struct netdev_hw_addr *ha;
2871 int i, mc;
2872 u32 reg;
2873
2874 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2875
7fc527f9 2876 /* Promiscuous mode */
1c1008c7
FF		 2877 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2878 if (dev->flags & IFF_PROMISC) {
2879 reg |= CMD_PROMISC;
2880 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2881 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2882 return;
2883 } else {
2884 reg &= ~CMD_PROMISC;
2885 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2886 }
2887
2888 /* UniMac doesn't support ALLMULTI */
2889 if (dev->flags & IFF_ALLMULTI) {
2890 netdev_warn(dev, "ALLMULTI is not supported\n");
2891 return;
2892 }
2893
2894 /* update MDF filter */
2895 i = 0;
2896 mc = 0;
2897 /* Broadcast */
2898 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2899 /* my own address.*/
2900 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2901 /* Unicast list*/
2902 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2903 return;
2904
2905 if (!netdev_uc_empty(dev))
2906 netdev_for_each_uc_addr(ha, dev)
2907 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2908 /* Multicast */
2909 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2910 return;
2911
2912 netdev_for_each_mc_addr(ha, dev)
2913 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2914}
2915
2916/* Set the hardware MAC address. */
2917static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2918{
2919 struct sockaddr *addr = p;
2920
2921 /* Setting the MAC address at the hardware level is not possible
2922 * without disabling the UniMAC RX/TX enable bits.
2923 */
2924 if (netif_running(dev))
2925 return -EBUSY;
2926
2927 ether_addr_copy(dev->dev_addr, addr->sa_data);
2928
2929 return 0;
2930}
2931
1c1008c7
FF		 2932static const struct net_device_ops bcmgenet_netdev_ops = {
2933 .ndo_open = bcmgenet_open,
2934 .ndo_stop = bcmgenet_close,
2935 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2936 .ndo_tx_timeout = bcmgenet_timeout,
2937 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2938 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2939 .ndo_do_ioctl = bcmgenet_ioctl,
2940 .ndo_set_features = bcmgenet_set_features,
2941};
2942
2943/* Array of GENET hardware parameters/characteristics */
2944static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2945 [GENET_V1] = {
2946 .tx_queues = 0,
51a966a7 2947 .tx_bds_per_q = 0,
1c1008c7 2948 .rx_queues = 0,
3feafa02 2949 .rx_bds_per_q = 0,
1c1008c7
FF		 2950 .bp_in_en_shift = 16,
2951 .bp_in_mask = 0xffff,
2952 .hfb_filter_cnt = 16,
2953 .qtag_mask = 0x1F,
2954 .hfb_offset = 0x1000,
2955 .rdma_offset = 0x2000,
2956 .tdma_offset = 0x3000,
2957 .words_per_bd = 2,
2958 },
2959 [GENET_V2] = {
2960 .tx_queues = 4,
51a966a7 2961 .tx_bds_per_q = 32,
7e906e02 2962 .rx_queues = 0,
3feafa02 2963 .rx_bds_per_q = 0,
1c1008c7
FF		 2964 .bp_in_en_shift = 16,
2965 .bp_in_mask = 0xffff,
2966 .hfb_filter_cnt = 16,
2967 .qtag_mask = 0x1F,
2968 .tbuf_offset = 0x0600,
2969 .hfb_offset = 0x1000,
2970 .hfb_reg_offset = 0x2000,
2971 .rdma_offset = 0x3000,
2972 .tdma_offset = 0x4000,
2973 .words_per_bd = 2,
2974 .flags = GENET_HAS_EXT,
2975 },
2976 [GENET_V3] = {
2977 .tx_queues = 4,
51a966a7 2978 .tx_bds_per_q = 32,
7e906e02 2979 .rx_queues = 0,
3feafa02 2980 .rx_bds_per_q = 0,
1c1008c7
FF		 2981 .bp_in_en_shift = 17,
2982 .bp_in_mask = 0x1ffff,
2983 .hfb_filter_cnt = 48,
0034de41 2984 .hfb_filter_size = 128,
1c1008c7
FF		 2985 .qtag_mask = 0x3F,
2986 .tbuf_offset = 0x0600,
2987 .hfb_offset = 0x8000,
2988 .hfb_reg_offset = 0xfc00,
2989 .rdma_offset = 0x10000,
2990 .tdma_offset = 0x11000,
2991 .words_per_bd = 2,
8d88c6eb
PG		 2992 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
2993 GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 2994 },
2995 [GENET_V4] = {
2996 .tx_queues = 4,
51a966a7 2997 .tx_bds_per_q = 32,
7e906e02 2998 .rx_queues = 0,
3feafa02 2999 .rx_bds_per_q = 0,
1c1008c7
FF		 3000 .bp_in_en_shift = 17,
3001 .bp_in_mask = 0x1ffff,
3002 .hfb_filter_cnt = 48,
0034de41 3003 .hfb_filter_size = 128,
1c1008c7
FF		 3004 .qtag_mask = 0x3F,
3005 .tbuf_offset = 0x0600,
3006 .hfb_offset = 0x8000,
3007 .hfb_reg_offset = 0xfc00,
3008 .rdma_offset = 0x2000,
3009 .tdma_offset = 0x4000,
3010 .words_per_bd = 3,
8d88c6eb
PG		 3011 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3012 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3013 },
3014};
3015
3016/* Infer hardware parameters from the detected GENET version */
3017static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3018{
3019 struct bcmgenet_hw_params *params;
3020 u32 reg;
3021 u8 major;
b04a2f5b 3022 u16 gphy_rev;
1c1008c7
FF		 3023
3024 if (GENET_IS_V4(priv)) {
3025 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3026 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3027 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3028 priv->version = GENET_V4;
3029 } else if (GENET_IS_V3(priv)) {
3030 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3031 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3032 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3033 priv->version = GENET_V3;
3034 } else if (GENET_IS_V2(priv)) {
3035 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3036 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3037 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3038 priv->version = GENET_V2;
3039 } else if (GENET_IS_V1(priv)) {
3040 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3041 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3042 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3043 priv->version = GENET_V1;
3044 }
3045
3046 /* enum genet_version starts at 1 */
3047 priv->hw_params = &bcmgenet_hw_params[priv->version];
3048 params = priv->hw_params;
3049
3050 /* Read GENET HW version */
3051 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3052 major = (reg >> 24 & 0x0f);
3053 if (major == 5)
3054 major = 4;
3055 else if (major == 0)
3056 major = 1;
3057 if (major != priv->version) {
3058 dev_err(&priv->pdev->dev,
3059 "GENET version mismatch, got: %d, configured for: %d\n",
3060 major, priv->version);
3061 }
3062
3063 /* Print the GENET core version */
3064 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3065 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3066
487320c5
FF		 3067 /* Store the integrated PHY revision for the MDIO probing function
3068 * to pass this information to the PHY driver. The PHY driver expects
3069 * to find the PHY major revision in bits 15:8 while the GENET register
3070 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3071 *
3072 * On newer chips, starting with PHY revision G0, a new scheme is
3073 * deployed similar to the Starfighter 2 switch with GPHY major
3074 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3075 * is reserved as well as special value 0x01ff, we have a small
3076 * heuristic to check for the new GPHY revision and re-arrange things
3077 * so the GPHY driver is happy.
487320c5 3078 */
b04a2f5b
FF		 3079 gphy_rev = reg & 0xffff;
3080
3081 /* This is the good old scheme, just GPHY major, no minor nor patch */
3082 if ((gphy_rev & 0xf0) != 0)
3083 priv->gphy_rev = gphy_rev << 8;
3084
3085 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3086 else if ((gphy_rev & 0xff00) != 0)
3087 priv->gphy_rev = gphy_rev;
3088
3089 /* This is reserved so should require special treatment */
3090 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3091 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3092 return;
3093 }
487320c5 3094
1c1008c7
FF		 3095#ifdef CONFIG_PHYS_ADDR_T_64BIT
3096 if (!(params->flags & GENET_HAS_40BITS))
3097 pr_warn("GENET does not support 40-bits PA\n");
3098#endif
3099
3100 pr_debug("Configuration for version: %d\n"
3feafa02 3101 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3102 "BP << en: %2d, BP msk: 0x%05x\n"
3103 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3104 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3105 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3106 "Words/BD: %d\n",
3107 priv->version,
51a966a7 3108 params->tx_queues, params->tx_bds_per_q,
3feafa02 3109 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3110 params->bp_in_en_shift, params->bp_in_mask,
3111 params->hfb_filter_cnt, params->qtag_mask,
3112 params->tbuf_offset, params->hfb_offset,
3113 params->hfb_reg_offset,
3114 params->rdma_offset, params->tdma_offset,
3115 params->words_per_bd);
3116}
3117
3118static const struct of_device_id bcmgenet_match[] = {
3119 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3120 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3121 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3122 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3123 { },
3124};
3125
3126static int bcmgenet_probe(struct platform_device *pdev)
3127{
b0ba512e 3128 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 3129 struct device_node *dn = pdev->dev.of_node;
b0ba512e 3130 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 3131 struct bcmgenet_priv *priv;
3132 struct net_device *dev;
3133 const void *macaddr;
3134 struct resource *r;
3135 int err = -EIO;
3136
3feafeed
PG		 3137 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3138 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3139 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3140 if (!dev) {
3141 dev_err(&pdev->dev, "can't allocate net device\n");
3142 return -ENOMEM;
3143 }
3144
b0ba512e
PG		 3145 if (dn) {
3146 of_id = of_match_node(bcmgenet_match, dn);
3147 if (!of_id)
3148 return -EINVAL;
3149 }
1c1008c7
FF		 3150
3151 priv = netdev_priv(dev);
3152 priv->irq0 = platform_get_irq(pdev, 0);
3153 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 3154 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 3155 if (!priv->irq0 || !priv->irq1) {
3156 dev_err(&pdev->dev, "can't find IRQs\n");
3157 err = -EINVAL;
3158 goto err;
3159 }
3160
b0ba512e
PG		 3161 if (dn) {
3162 macaddr = of_get_mac_address(dn);
3163 if (!macaddr) {
3164 dev_err(&pdev->dev, "can't find MAC address\n");
3165 err = -EINVAL;
3166 goto err;
3167 }
3168 } else {
3169 macaddr = pd->mac_address;
1c1008c7
FF		 3170 }
3171
3172 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 3173 priv->base = devm_ioremap_resource(&pdev->dev, r);
3174 if (IS_ERR(priv->base)) {
3175 err = PTR_ERR(priv->base);
1c1008c7
FF		 3176 goto err;
3177 }
3178
3179 SET_NETDEV_DEV(dev, &pdev->dev);
3180 dev_set_drvdata(&pdev->dev, dev);
3181 ether_addr_copy(dev->dev_addr, macaddr);
3182 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 3183 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 3184 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 3185
3186 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3187
3188 /* Set hardware features */
3189 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3190 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3191
8562056f
FF		 3192 /* Request the WOL interrupt and advertise suspend if available */
3193 priv->wol_irq_disabled = true;
3194 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3195 dev->name, priv);
3196 if (!err)
3197 device_set_wakeup_capable(&pdev->dev, 1);
3198
1c1008c7
FF		 3199 /* Set the needed headroom to account for any possible
3200 * features enabling/disabling at runtime
3201 */
3202 dev->needed_headroom += 64;
3203
3204 netdev_boot_setup_check(dev);
3205
3206 priv->dev = dev;
3207 priv->pdev = pdev;
b0ba512e
PG		 3208 if (of_id)
3209 priv->version = (enum bcmgenet_version)of_id->data;
3210 else
3211 priv->version = pd->genet_version;
1c1008c7 3212
e4a60a93
FF		 3213 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3214 if (IS_ERR(priv->clk))
3215 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3216
3217 if (!IS_ERR(priv->clk))
3218 clk_prepare_enable(priv->clk);
3219
1c1008c7
FF		 3220 bcmgenet_set_hw_params(priv);
3221
1c1008c7
FF		 3222 /* Mii wait queue */
3223 init_waitqueue_head(&priv->wq);
3224 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3225 priv->rx_buf_len = RX_BUF_LENGTH;
3226 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3227
1c1008c7
FF		 3228 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3229 if (IS_ERR(priv->clk_wol))
3230 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3231
6ef398ea
FF		 3232 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3233 if (IS_ERR(priv->clk_eee)) {
3234 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3235 priv->clk_eee = NULL;
3236 }
3237
1c1008c7
FF		 3238 err = reset_umac(priv);
3239 if (err)
3240 goto err_clk_disable;
3241
3242 err = bcmgenet_mii_init(dev);
3243 if (err)
3244 goto err_clk_disable;
3245
3246 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3247 * just the ring 16 descriptor based TX
3248 */
3249 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3250 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3251
219575eb
FF		 3252 /* libphy will determine the link state */
3253 netif_carrier_off(dev);
3254
1c1008c7
FF		 3255 /* Turn off the main clock, WOL clock is handled separately */
3256 if (!IS_ERR(priv->clk))
3257 clk_disable_unprepare(priv->clk);
3258
0f50ce96
FF		 3259 err = register_netdev(dev);
3260 if (err)
3261 goto err;
3262
1c1008c7
FF		 3263 return err;
3264
3265err_clk_disable:
3266 if (!IS_ERR(priv->clk))
3267 clk_disable_unprepare(priv->clk);
3268err:
3269 free_netdev(dev);
3270 return err;
3271}
3272
3273static int bcmgenet_remove(struct platform_device *pdev)
3274{
3275 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3276
3277 dev_set_drvdata(&pdev->dev, NULL);
3278 unregister_netdev(priv->dev);
3279 bcmgenet_mii_exit(priv->dev);
3280 free_netdev(priv->dev);
3281
3282 return 0;
3283}
3284
b6e978e5
FF		 3285#ifdef CONFIG_PM_SLEEP
3286static int bcmgenet_suspend(struct device *d)
3287{
3288 struct net_device *dev = dev_get_drvdata(d);
3289 struct bcmgenet_priv *priv = netdev_priv(dev);
3290 int ret;
3291
3292 if (!netif_running(dev))
3293 return 0;
3294
3295 bcmgenet_netif_stop(dev);
3296
cc013fb4
FF		 3297 phy_suspend(priv->phydev);
3298
b6e978e5
FF		 3299 netif_device_detach(dev);
3300
3301 /* Disable MAC receive */
3302 umac_enable_set(priv, CMD_RX_EN, false);
3303
3304 ret = bcmgenet_dma_teardown(priv);
3305 if (ret)
3306 return ret;
3307
3308 /* Disable MAC transmit. TX DMA disabled have to done before this */
3309 umac_enable_set(priv, CMD_TX_EN, false);
3310
3311 /* tx reclaim */
3312 bcmgenet_tx_reclaim_all(dev);
3313 bcmgenet_fini_dma(priv);
3314
8c90db72
FF		 3315 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3316 if (device_may_wakeup(d) && priv->wolopts) {
ca8cf341 3317 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
8c90db72 3318 clk_prepare_enable(priv->clk_wol);
a6f31f5e
FF		 3319 } else if (phy_is_internal(priv->phydev)) {
3320 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
8c90db72
FF		 3321 }
3322
b6e978e5
FF		 3323 /* Turn off the clocks */
3324 clk_disable_unprepare(priv->clk);
3325
ca8cf341 3326 return ret;
b6e978e5
FF		 3327}
3328
3329static int bcmgenet_resume(struct device *d)
3330{
3331 struct net_device *dev = dev_get_drvdata(d);
3332 struct bcmgenet_priv *priv = netdev_priv(dev);
3333 unsigned long dma_ctrl;
3334 int ret;
3335 u32 reg;
3336
3337 if (!netif_running(dev))
3338 return 0;
3339
3340 /* Turn on the clock */
3341 ret = clk_prepare_enable(priv->clk);
3342 if (ret)
3343 return ret;
3344
a6f31f5e
FF		 3345 /* If this is an internal GPHY, power it back on now, before UniMAC is
3346 * brought out of reset as absolutely no UniMAC activity is allowed
3347 */
3348 if (phy_is_internal(priv->phydev))
3349 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3350
b6e978e5
FF		 3351 bcmgenet_umac_reset(priv);
3352
3353 ret = init_umac(priv);
3354 if (ret)
3355 goto out_clk_disable;
3356
0a29b3da
TK		 3357 /* From WOL-enabled suspend, switch to regular clock */
3358 if (priv->wolopts)
3359 clk_disable_unprepare(priv->clk_wol);
3360
3361 phy_init_hw(priv->phydev);
3362 /* Speed settings must be restored */
dbd479db 3363 bcmgenet_mii_config(priv->dev, false);
8c90db72 3364
b6e978e5
FF		 3365 /* disable ethernet MAC while updating its registers */
3366 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3367
3368 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3369
3370 if (phy_is_internal(priv->phydev)) {
3371 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3372 reg |= EXT_ENERGY_DET_MASK;
3373 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3374 }
3375
98bb7399
FF		 3376 if (priv->wolopts)
3377 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3378
b6e978e5
FF		 3379 /* Disable RX/TX DMA and flush TX queues */
3380 dma_ctrl = bcmgenet_dma_disable(priv);
3381
3382 /* Reinitialize TDMA and RDMA and SW housekeeping */
3383 ret = bcmgenet_init_dma(priv);
3384 if (ret) {
3385 netdev_err(dev, "failed to initialize DMA\n");
3386 goto out_clk_disable;
3387 }
3388
3389 /* Always enable ring 16 - descriptor ring */
3390 bcmgenet_enable_dma(priv, dma_ctrl);
3391
3392 netif_device_attach(dev);
3393
cc013fb4
FF		 3394 phy_resume(priv->phydev);
3395
6ef398ea
FF		 3396 if (priv->eee.eee_enabled)
3397 bcmgenet_eee_enable_set(dev, true);
3398
b6e978e5
FF		 3399 bcmgenet_netif_start(dev);
3400
3401 return 0;
3402
3403out_clk_disable:
3404 clk_disable_unprepare(priv->clk);
3405 return ret;
3406}
3407#endif /* CONFIG_PM_SLEEP */
3408
3409static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3410
1c1008c7
FF		 3411static struct platform_driver bcmgenet_driver = {
3412 .probe = bcmgenet_probe,
3413 .remove = bcmgenet_remove,
3414 .driver = {
3415 .name = "bcmgenet",
1c1008c7 3416 .of_match_table = bcmgenet_match,
b6e978e5 3417 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 3418 },
3419};
3420module_platform_driver(bcmgenet_driver);
3421
3422MODULE_AUTHOR("Broadcom Corporation");
3423MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3424MODULE_ALIAS("platform:bcmgenet");
3425MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)