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fib_trie: Fix uninitialized variable warning
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 106{
107 dmadesc_set_length_status(priv, d, val);
108 dmadesc_set_addr(priv, d, addr);
109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
1c1008c7
FF		 200};
201
202static const u8 bcmgenet_dma_regs_v3plus[] = {
203 [DMA_RING_CFG] = 0x00,
204 [DMA_CTRL] = 0x04,
205 [DMA_STATUS] = 0x08,
206 [DMA_SCB_BURST_SIZE] = 0x0C,
207 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 208 [DMA_PRIORITY_0] = 0x30,
209 [DMA_PRIORITY_1] = 0x34,
210 [DMA_PRIORITY_2] = 0x38,
1c1008c7
FF		 211};
212
213static const u8 bcmgenet_dma_regs_v2[] = {
214 [DMA_RING_CFG] = 0x00,
215 [DMA_CTRL] = 0x04,
216 [DMA_STATUS] = 0x08,
217 [DMA_SCB_BURST_SIZE] = 0x0C,
218 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 219 [DMA_PRIORITY_0] = 0x34,
220 [DMA_PRIORITY_1] = 0x38,
221 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 222};
223
224static const u8 bcmgenet_dma_regs_v1[] = {
225 [DMA_CTRL] = 0x00,
226 [DMA_STATUS] = 0x04,
227 [DMA_SCB_BURST_SIZE] = 0x0C,
228 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 229 [DMA_PRIORITY_0] = 0x34,
230 [DMA_PRIORITY_1] = 0x38,
231 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 232};
233
234/* Set at runtime once bcmgenet version is known */
235static const u8 *bcmgenet_dma_regs;
236
237static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
238{
239 return netdev_priv(dev_get_drvdata(dev));
240}
241
242static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 243 enum dma_reg r)
1c1008c7
FF		 244{
245 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
246 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
247}
248
249static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
250 u32 val, enum dma_reg r)
251{
252 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
253 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
254}
255
256static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 257 enum dma_reg r)
1c1008c7
FF		 258{
259 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
260 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
261}
262
263static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
264 u32 val, enum dma_reg r)
265{
266 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
267 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
268}
269
270/* RDMA/TDMA ring registers and accessors
271 * we merge the common fields and just prefix with T/D the registers
272 * having different meaning depending on the direction
273 */
274enum dma_ring_reg {
275 TDMA_READ_PTR = 0,
276 RDMA_WRITE_PTR = TDMA_READ_PTR,
277 TDMA_READ_PTR_HI,
278 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
279 TDMA_CONS_INDEX,
280 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
281 TDMA_PROD_INDEX,
282 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
283 DMA_RING_BUF_SIZE,
284 DMA_START_ADDR,
285 DMA_START_ADDR_HI,
286 DMA_END_ADDR,
287 DMA_END_ADDR_HI,
288 DMA_MBUF_DONE_THRESH,
289 TDMA_FLOW_PERIOD,
290 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
291 TDMA_WRITE_PTR,
292 RDMA_READ_PTR = TDMA_WRITE_PTR,
293 TDMA_WRITE_PTR_HI,
294 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
295};
296
297/* GENET v4 supports 40-bits pointer addressing
298 * for obvious reasons the LO and HI word parts
299 * are contiguous, but this offsets the other
300 * registers.
301 */
302static const u8 genet_dma_ring_regs_v4[] = {
303 [TDMA_READ_PTR] = 0x00,
304 [TDMA_READ_PTR_HI] = 0x04,
305 [TDMA_CONS_INDEX] = 0x08,
306 [TDMA_PROD_INDEX] = 0x0C,
307 [DMA_RING_BUF_SIZE] = 0x10,
308 [DMA_START_ADDR] = 0x14,
309 [DMA_START_ADDR_HI] = 0x18,
310 [DMA_END_ADDR] = 0x1C,
311 [DMA_END_ADDR_HI] = 0x20,
312 [DMA_MBUF_DONE_THRESH] = 0x24,
313 [TDMA_FLOW_PERIOD] = 0x28,
314 [TDMA_WRITE_PTR] = 0x2C,
315 [TDMA_WRITE_PTR_HI] = 0x30,
316};
317
318static const u8 genet_dma_ring_regs_v123[] = {
319 [TDMA_READ_PTR] = 0x00,
320 [TDMA_CONS_INDEX] = 0x04,
321 [TDMA_PROD_INDEX] = 0x08,
322 [DMA_RING_BUF_SIZE] = 0x0C,
323 [DMA_START_ADDR] = 0x10,
324 [DMA_END_ADDR] = 0x14,
325 [DMA_MBUF_DONE_THRESH] = 0x18,
326 [TDMA_FLOW_PERIOD] = 0x1C,
327 [TDMA_WRITE_PTR] = 0x20,
328};
329
330/* Set at runtime once GENET version is known */
331static const u8 *genet_dma_ring_regs;
332
333static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 334 unsigned int ring,
335 enum dma_ring_reg r)
1c1008c7
FF		 336{
337 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
338 (DMA_RING_SIZE * ring) +
339 genet_dma_ring_regs[r]);
340}
341
342static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 343 unsigned int ring, u32 val,
344 enum dma_ring_reg r)
1c1008c7
FF		 345{
346 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
347 (DMA_RING_SIZE * ring) +
348 genet_dma_ring_regs[r]);
349}
350
351static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 352 unsigned int ring,
353 enum dma_ring_reg r)
1c1008c7
FF		 354{
355 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
356 (DMA_RING_SIZE * ring) +
357 genet_dma_ring_regs[r]);
358}
359
360static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 361 unsigned int ring, u32 val,
362 enum dma_ring_reg r)
1c1008c7
FF		 363{
364 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
365 (DMA_RING_SIZE * ring) +
366 genet_dma_ring_regs[r]);
367}
368
369static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 370 struct ethtool_cmd *cmd)
1c1008c7
FF		 371{
372 struct bcmgenet_priv *priv = netdev_priv(dev);
373
374 if (!netif_running(dev))
375 return -EINVAL;
376
377 if (!priv->phydev)
378 return -ENODEV;
379
380 return phy_ethtool_gset(priv->phydev, cmd);
381}
382
383static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 384 struct ethtool_cmd *cmd)
1c1008c7
FF		 385{
386 struct bcmgenet_priv *priv = netdev_priv(dev);
387
388 if (!netif_running(dev))
389 return -EINVAL;
390
391 if (!priv->phydev)
392 return -ENODEV;
393
394 return phy_ethtool_sset(priv->phydev, cmd);
395}
396
397static int bcmgenet_set_rx_csum(struct net_device *dev,
398 netdev_features_t wanted)
399{
400 struct bcmgenet_priv *priv = netdev_priv(dev);
401 u32 rbuf_chk_ctrl;
402 bool rx_csum_en;
403
404 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
405
406 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
407
408 /* enable rx checksumming */
409 if (rx_csum_en)
410 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
411 else
412 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
413 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 414
415 /* If UniMAC forwards CRC, we need to skip over it to get
416 * a valid CHK bit to be set in the per-packet status word
417 */
418 if (rx_csum_en && priv->crc_fwd_en)
419 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
420 else
421 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
422
1c1008c7
FF		 423 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
424
425 return 0;
426}
427
428static int bcmgenet_set_tx_csum(struct net_device *dev,
429 netdev_features_t wanted)
430{
431 struct bcmgenet_priv *priv = netdev_priv(dev);
432 bool desc_64b_en;
433 u32 tbuf_ctrl, rbuf_ctrl;
434
435 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
436 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
437
438 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
439
440 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
441 if (desc_64b_en) {
442 tbuf_ctrl |= RBUF_64B_EN;
443 rbuf_ctrl |= RBUF_64B_EN;
444 } else {
445 tbuf_ctrl &= ~RBUF_64B_EN;
446 rbuf_ctrl &= ~RBUF_64B_EN;
447 }
448 priv->desc_64b_en = desc_64b_en;
449
450 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
451 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
452
453 return 0;
454}
455
456static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 457 netdev_features_t features)
1c1008c7
FF		 458{
459 netdev_features_t changed = features ^ dev->features;
460 netdev_features_t wanted = dev->wanted_features;
461 int ret = 0;
462
463 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
464 ret = bcmgenet_set_tx_csum(dev, wanted);
465 if (changed & (NETIF_F_RXCSUM))
466 ret = bcmgenet_set_rx_csum(dev, wanted);
467
468 return ret;
469}
470
471static u32 bcmgenet_get_msglevel(struct net_device *dev)
472{
473 struct bcmgenet_priv *priv = netdev_priv(dev);
474
475 return priv->msg_enable;
476}
477
478static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
479{
480 struct bcmgenet_priv *priv = netdev_priv(dev);
481
482 priv->msg_enable = level;
483}
484
485/* standard ethtool support functions. */
486enum bcmgenet_stat_type {
487 BCMGENET_STAT_NETDEV = -1,
488 BCMGENET_STAT_MIB_RX,
489 BCMGENET_STAT_MIB_TX,
490 BCMGENET_STAT_RUNT,
491 BCMGENET_STAT_MISC,
f62ba9c1 492 BCMGENET_STAT_SOFT,
1c1008c7
FF		 493};
494
495struct bcmgenet_stats {
496 char stat_string[ETH_GSTRING_LEN];
497 int stat_sizeof;
498 int stat_offset;
499 enum bcmgenet_stat_type type;
500 /* reg offset from UMAC base for misc counters */
501 u16 reg_offset;
502};
503
504#define STAT_NETDEV(m) { \
505 .stat_string = __stringify(m), \
506 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
507 .stat_offset = offsetof(struct net_device_stats, m), \
508 .type = BCMGENET_STAT_NETDEV, \
509}
510
511#define STAT_GENET_MIB(str, m, _type) { \
512 .stat_string = str, \
513 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
514 .stat_offset = offsetof(struct bcmgenet_priv, m), \
515 .type = _type, \
516}
517
518#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
519#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
520#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 521#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 522
523#define STAT_GENET_MISC(str, m, offset) { \
524 .stat_string = str, \
525 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
526 .stat_offset = offsetof(struct bcmgenet_priv, m), \
527 .type = BCMGENET_STAT_MISC, \
528 .reg_offset = offset, \
529}
530
531
532/* There is a 0xC gap between the end of RX and beginning of TX stats and then
533 * between the end of TX stats and the beginning of the RX RUNT
534 */
535#define BCMGENET_STAT_OFFSET 0xc
536
537/* Hardware counters must be kept in sync because the order/offset
538 * is important here (order in structure declaration = order in hardware)
539 */
540static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
541 /* general stats */
542 STAT_NETDEV(rx_packets),
543 STAT_NETDEV(tx_packets),
544 STAT_NETDEV(rx_bytes),
545 STAT_NETDEV(tx_bytes),
546 STAT_NETDEV(rx_errors),
547 STAT_NETDEV(tx_errors),
548 STAT_NETDEV(rx_dropped),
549 STAT_NETDEV(tx_dropped),
550 STAT_NETDEV(multicast),
551 /* UniMAC RSV counters */
552 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
553 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
554 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
555 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
556 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
557 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
558 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
559 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
560 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
561 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
562 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
563 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
564 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
565 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
566 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
567 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
568 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
569 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
570 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
571 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
572 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
573 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
574 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
575 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
576 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
577 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
578 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
579 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
580 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
581 /* UniMAC TSV counters */
582 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
583 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
584 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
585 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
586 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
587 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
588 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
589 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
590 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
591 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
592 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
593 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
594 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
595 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
596 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
597 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
598 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
599 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
600 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
601 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
602 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
603 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
604 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
605 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
606 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
607 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
608 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
609 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
610 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
611 /* UniMAC RUNT counters */
612 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
613 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
614 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
615 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
616 /* Misc UniMAC counters */
617 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
618 UMAC_RBUF_OVFL_CNT),
619 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
620 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 621 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
622 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
623 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 624};
625
626#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
627
628static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 629 struct ethtool_drvinfo *info)
1c1008c7
FF		 630{
631 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
632 strlcpy(info->version, "v2.0", sizeof(info->version));
633 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 634}
635
636static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
637{
638 switch (string_set) {
639 case ETH_SS_STATS:
640 return BCMGENET_STATS_LEN;
641 default:
642 return -EOPNOTSUPP;
643 }
644}
645
c91b7f66
FF		 646static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
647 u8 *data)
1c1008c7
FF		 648{
649 int i;
650
651 switch (stringset) {
652 case ETH_SS_STATS:
653 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
654 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 655 bcmgenet_gstrings_stats[i].stat_string,
656 ETH_GSTRING_LEN);
1c1008c7
FF		 657 }
658 break;
659 }
660}
661
662static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
663{
664 int i, j = 0;
665
666 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
667 const struct bcmgenet_stats *s;
668 u8 offset = 0;
669 u32 val = 0;
670 char *p;
671
672 s = &bcmgenet_gstrings_stats[i];
673 switch (s->type) {
674 case BCMGENET_STAT_NETDEV:
f62ba9c1 675 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 676 continue;
677 case BCMGENET_STAT_MIB_RX:
678 case BCMGENET_STAT_MIB_TX:
679 case BCMGENET_STAT_RUNT:
680 if (s->type != BCMGENET_STAT_MIB_RX)
681 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 682 val = bcmgenet_umac_readl(priv,
683 UMAC_MIB_START + j + offset);
1c1008c7
FF		 684 break;
685 case BCMGENET_STAT_MISC:
686 val = bcmgenet_umac_readl(priv, s->reg_offset);
687 /* clear if overflowed */
688 if (val == ~0)
689 bcmgenet_umac_writel(priv, 0, s->reg_offset);
690 break;
691 }
692
693 j += s->stat_sizeof;
694 p = (char *)priv + s->stat_offset;
695 *(u32 *)p = val;
696 }
697}
698
699static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 700 struct ethtool_stats *stats,
701 u64 *data)
1c1008c7
FF		 702{
703 struct bcmgenet_priv *priv = netdev_priv(dev);
704 int i;
705
706 if (netif_running(dev))
707 bcmgenet_update_mib_counters(priv);
708
709 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
710 const struct bcmgenet_stats *s;
711 char *p;
712
713 s = &bcmgenet_gstrings_stats[i];
714 if (s->type == BCMGENET_STAT_NETDEV)
715 p = (char *)&dev->stats;
716 else
717 p = (char *)priv;
718 p += s->stat_offset;
719 data[i] = *(u32 *)p;
720 }
721}
722
6ef398ea
FF		 723static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
724{
725 struct bcmgenet_priv *priv = netdev_priv(dev);
726 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
727 u32 reg;
728
729 if (enable && !priv->clk_eee_enabled) {
730 clk_prepare_enable(priv->clk_eee);
731 priv->clk_eee_enabled = true;
732 }
733
734 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
735 if (enable)
736 reg |= EEE_EN;
737 else
738 reg &= ~EEE_EN;
739 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
740
741 /* Enable EEE and switch to a 27Mhz clock automatically */
742 reg = __raw_readl(priv->base + off);
743 if (enable)
744 reg |= TBUF_EEE_EN | TBUF_PM_EN;
745 else
746 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
747 __raw_writel(reg, priv->base + off);
748
749 /* Do the same for thing for RBUF */
750 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
751 if (enable)
752 reg |= RBUF_EEE_EN | RBUF_PM_EN;
753 else
754 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
755 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
756
757 if (!enable && priv->clk_eee_enabled) {
758 clk_disable_unprepare(priv->clk_eee);
759 priv->clk_eee_enabled = false;
760 }
761
762 priv->eee.eee_enabled = enable;
763 priv->eee.eee_active = enable;
764}
765
766static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
767{
768 struct bcmgenet_priv *priv = netdev_priv(dev);
769 struct ethtool_eee *p = &priv->eee;
770
771 if (GENET_IS_V1(priv))
772 return -EOPNOTSUPP;
773
774 e->eee_enabled = p->eee_enabled;
775 e->eee_active = p->eee_active;
776 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
777
778 return phy_ethtool_get_eee(priv->phydev, e);
779}
780
781static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
782{
783 struct bcmgenet_priv *priv = netdev_priv(dev);
784 struct ethtool_eee *p = &priv->eee;
785 int ret = 0;
786
787 if (GENET_IS_V1(priv))
788 return -EOPNOTSUPP;
789
790 p->eee_enabled = e->eee_enabled;
791
792 if (!p->eee_enabled) {
793 bcmgenet_eee_enable_set(dev, false);
794 } else {
795 ret = phy_init_eee(priv->phydev, 0);
796 if (ret) {
797 netif_err(priv, hw, dev, "EEE initialization failed\n");
798 return ret;
799 }
800
801 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
802 bcmgenet_eee_enable_set(dev, true);
803 }
804
805 return phy_ethtool_set_eee(priv->phydev, e);
806}
807
6b0c5406
FF		 808static int bcmgenet_nway_reset(struct net_device *dev)
809{
810 struct bcmgenet_priv *priv = netdev_priv(dev);
811
812 return genphy_restart_aneg(priv->phydev);
813}
814
1c1008c7
FF		 815/* standard ethtool support functions. */
816static struct ethtool_ops bcmgenet_ethtool_ops = {
817 .get_strings = bcmgenet_get_strings,
818 .get_sset_count = bcmgenet_get_sset_count,
819 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
820 .get_settings = bcmgenet_get_settings,
821 .set_settings = bcmgenet_set_settings,
822 .get_drvinfo = bcmgenet_get_drvinfo,
823 .get_link = ethtool_op_get_link,
824 .get_msglevel = bcmgenet_get_msglevel,
825 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 826 .get_wol = bcmgenet_get_wol,
827 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 828 .get_eee = bcmgenet_get_eee,
829 .set_eee = bcmgenet_set_eee,
6b0c5406 830 .nway_reset = bcmgenet_nway_reset,
1c1008c7
FF		 831};
832
833/* Power down the unimac, based on mode. */
834static void bcmgenet_power_down(struct bcmgenet_priv *priv,
835 enum bcmgenet_power_mode mode)
836{
837 u32 reg;
838
839 switch (mode) {
840 case GENET_POWER_CABLE_SENSE:
80d8e96d 841 phy_detach(priv->phydev);
1c1008c7
FF		 842 break;
843
c3ae64ae
FF		 844 case GENET_POWER_WOL_MAGIC:
845 bcmgenet_wol_power_down_cfg(priv, mode);
846 break;
847
1c1008c7
FF		 848 case GENET_POWER_PASSIVE:
849 /* Power down LED */
1c1008c7
FF		 850 if (priv->hw_params->flags & GENET_HAS_EXT) {
851 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
852 reg |= (EXT_PWR_DOWN_PHY |
853 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
854 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
855 }
856 break;
857 default:
858 break;
859 }
860}
861
862static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 863 enum bcmgenet_power_mode mode)
1c1008c7
FF		 864{
865 u32 reg;
866
867 if (!(priv->hw_params->flags & GENET_HAS_EXT))
868 return;
869
870 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
871
872 switch (mode) {
873 case GENET_POWER_PASSIVE:
874 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
875 EXT_PWR_DOWN_BIAS);
876 /* fallthrough */
877 case GENET_POWER_CABLE_SENSE:
878 /* enable APD */
879 reg |= EXT_PWR_DN_EN_LD;
880 break;
c3ae64ae
FF		 881 case GENET_POWER_WOL_MAGIC:
882 bcmgenet_wol_power_up_cfg(priv, mode);
883 return;
1c1008c7
FF		 884 default:
885 break;
886 }
887
888 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
cc013fb4
FF		 889
890 if (mode == GENET_POWER_PASSIVE)
891 bcmgenet_mii_reset(priv->dev);
1c1008c7
FF		 892}
893
894/* ioctl handle special commands that are not present in ethtool. */
895static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
896{
897 struct bcmgenet_priv *priv = netdev_priv(dev);
898 int val = 0;
899
900 if (!netif_running(dev))
901 return -EINVAL;
902
903 switch (cmd) {
904 case SIOCGMIIPHY:
905 case SIOCGMIIREG:
906 case SIOCSMIIREG:
907 if (!priv->phydev)
908 val = -ENODEV;
909 else
910 val = phy_mii_ioctl(priv->phydev, rq, cmd);
911 break;
912
913 default:
914 val = -EINVAL;
915 break;
916 }
917
918 return val;
919}
920
921static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
922 struct bcmgenet_tx_ring *ring)
923{
924 struct enet_cb *tx_cb_ptr;
925
926 tx_cb_ptr = ring->cbs;
927 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 928
1c1008c7
FF		 929 /* Advancing local write pointer */
930 if (ring->write_ptr == ring->end_ptr)
931 ring->write_ptr = ring->cb_ptr;
932 else
933 ring->write_ptr++;
934
935 return tx_cb_ptr;
936}
937
938/* Simple helper to free a control block's resources */
939static void bcmgenet_free_cb(struct enet_cb *cb)
940{
941 dev_kfree_skb_any(cb->skb);
942 cb->skb = NULL;
943 dma_unmap_addr_set(cb, dma_addr, 0);
944}
945
946static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
947 struct bcmgenet_tx_ring *ring)
948{
949 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 950 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
951 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 952}
953
954static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
955 struct bcmgenet_tx_ring *ring)
956{
957 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 958 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
959 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 960}
961
962static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
c91b7f66 963 struct bcmgenet_tx_ring *ring)
1c1008c7 964{
c91b7f66
FF		 965 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
966 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 967 priv->int1_mask &= ~(1 << ring->index);
968}
969
970static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
971 struct bcmgenet_tx_ring *ring)
972{
c91b7f66
FF		 973 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
974 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 975 priv->int1_mask |= (1 << ring->index);
976}
977
978/* Unlocked version of the reclaim routine */
4092e6ac
JS		 979static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
980 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 981{
982 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 983 struct enet_cb *tx_cb_ptr;
b2cde2cc 984 struct netdev_queue *txq;
4092e6ac 985 unsigned int pkts_compl = 0;
1c1008c7 986 unsigned int c_index;
66d06757
PG		 987 unsigned int txbds_ready;
988 unsigned int txbds_processed = 0;
1c1008c7 989
7fc527f9 990 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 991 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 992 c_index &= DMA_C_INDEX_MASK;
1c1008c7 993
66d06757
PG		 994 if (likely(c_index >= ring->c_index))
995 txbds_ready = c_index - ring->c_index;
1c1008c7 996 else
66d06757 997 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 998
999 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1000 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1001 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1002
1003 /* Reclaim transmitted buffers */
66d06757
PG		 1004 while (txbds_processed < txbds_ready) {
1005 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1006 if (tx_cb_ptr->skb) {
4092e6ac 1007 pkts_compl++;
66d06757 1008 dev->stats.tx_packets++;
1c1008c7
FF		 1009 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1010 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1011 dma_unmap_addr(tx_cb_ptr, dma_addr),
1012 tx_cb_ptr->skb->len,
1013 DMA_TO_DEVICE);
1c1008c7
FF		 1014 bcmgenet_free_cb(tx_cb_ptr);
1015 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1016 dev->stats.tx_bytes +=
1017 dma_unmap_len(tx_cb_ptr, dma_len);
1018 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1019 dma_unmap_addr(tx_cb_ptr, dma_addr),
1020 dma_unmap_len(tx_cb_ptr, dma_len),
1021 DMA_TO_DEVICE);
1c1008c7
FF		 1022 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1023 }
1c1008c7 1024
66d06757
PG		 1025 txbds_processed++;
1026 if (likely(ring->clean_ptr < ring->end_ptr))
1027 ring->clean_ptr++;
1028 else
1029 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1030 }
1031
66d06757
PG		 1032 ring->free_bds += txbds_processed;
1033 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1034
4092e6ac 1035 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
66d06757 1036 txq = netdev_get_tx_queue(dev, ring->queue);
4092e6ac
JS		 1037 if (netif_tx_queue_stopped(txq))
1038 netif_tx_wake_queue(txq);
1039 }
1c1008c7 1040
4092e6ac 1041 return pkts_compl;
1c1008c7
FF		 1042}
1043
4092e6ac 1044static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1045 struct bcmgenet_tx_ring *ring)
1c1008c7 1046{
4092e6ac 1047 unsigned int released;
1c1008c7
FF		 1048 unsigned long flags;
1049
1050 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1051 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1052 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1053
1054 return released;
1055}
1056
1057static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1058{
1059 struct bcmgenet_tx_ring *ring =
1060 container_of(napi, struct bcmgenet_tx_ring, napi);
1061 unsigned int work_done = 0;
1062
1063 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1064
1065 if (work_done == 0) {
1066 napi_complete(napi);
1067 ring->int_enable(ring->priv, ring);
1068
1069 return 0;
1070 }
1071
1072 return budget;
1c1008c7
FF		 1073}
1074
1075static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1076{
1077 struct bcmgenet_priv *priv = netdev_priv(dev);
1078 int i;
1079
1080 if (netif_is_multiqueue(dev)) {
1081 for (i = 0; i < priv->hw_params->tx_queues; i++)
1082 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1083 }
1084
1085 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1086}
1087
1088/* Transmits a single SKB (either head of a fragment or a single SKB)
1089 * caller must hold priv->lock
1090 */
1091static int bcmgenet_xmit_single(struct net_device *dev,
1092 struct sk_buff *skb,
1093 u16 dma_desc_flags,
1094 struct bcmgenet_tx_ring *ring)
1095{
1096 struct bcmgenet_priv *priv = netdev_priv(dev);
1097 struct device *kdev = &priv->pdev->dev;
1098 struct enet_cb *tx_cb_ptr;
1099 unsigned int skb_len;
1100 dma_addr_t mapping;
1101 u32 length_status;
1102 int ret;
1103
1104 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1105
1106 if (unlikely(!tx_cb_ptr))
1107 BUG();
1108
1109 tx_cb_ptr->skb = skb;
1110
1111 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1112
1113 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1114 ret = dma_mapping_error(kdev, mapping);
1115 if (ret) {
44c8bc3c 1116 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1117 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1118 dev_kfree_skb(skb);
1119 return ret;
1120 }
1121
1122 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1123 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1124 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1125 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1126 DMA_TX_APPEND_CRC;
1127
1128 if (skb->ip_summed == CHECKSUM_PARTIAL)
1129 length_status |= DMA_TX_DO_CSUM;
1130
1131 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1132
1133 /* Decrement total BD count and advance our write pointer */
1134 ring->free_bds -= 1;
1135 ring->prod_index += 1;
1136 ring->prod_index &= DMA_P_INDEX_MASK;
1137
1138 return 0;
1139}
1140
7fc527f9 1141/* Transmit a SKB fragment */
1c1008c7 1142static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1143 skb_frag_t *frag,
1144 u16 dma_desc_flags,
1145 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1146{
1147 struct bcmgenet_priv *priv = netdev_priv(dev);
1148 struct device *kdev = &priv->pdev->dev;
1149 struct enet_cb *tx_cb_ptr;
1150 dma_addr_t mapping;
1151 int ret;
1152
1153 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1154
1155 if (unlikely(!tx_cb_ptr))
1156 BUG();
1157 tx_cb_ptr->skb = NULL;
1158
1159 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1160 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1161 ret = dma_mapping_error(kdev, mapping);
1162 if (ret) {
44c8bc3c 1163 priv->mib.tx_dma_failed++;
1c1008c7 1164 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1165 __func__);
1c1008c7
FF		 1166 return ret;
1167 }
1168
1169 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1170 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1171
1172 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1173 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1174 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7
FF		 1175
1176
1177 ring->free_bds -= 1;
1178 ring->prod_index += 1;
1179 ring->prod_index &= DMA_P_INDEX_MASK;
1180
1181 return 0;
1182}
1183
1184/* Reallocate the SKB to put enough headroom in front of it and insert
1185 * the transmit checksum offsets in the descriptors
1186 */
bc23333b
PG		 1187static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1188 struct sk_buff *skb)
1c1008c7
FF		 1189{
1190 struct status_64 *status = NULL;
1191 struct sk_buff *new_skb;
1192 u16 offset;
1193 u8 ip_proto;
1194 u16 ip_ver;
1195 u32 tx_csum_info;
1196
1197 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1198 /* If 64 byte status block enabled, must make sure skb has
1199 * enough headroom for us to insert 64B status block.
1200 */
1201 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1202 dev_kfree_skb(skb);
1203 if (!new_skb) {
1204 dev->stats.tx_errors++;
1205 dev->stats.tx_dropped++;
bc23333b 1206 return NULL;
1c1008c7
FF		 1207 }
1208 skb = new_skb;
1209 }
1210
1211 skb_push(skb, sizeof(*status));
1212 status = (struct status_64 *)skb->data;
1213
1214 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1215 ip_ver = htons(skb->protocol);
1216 switch (ip_ver) {
1217 case ETH_P_IP:
1218 ip_proto = ip_hdr(skb)->protocol;
1219 break;
1220 case ETH_P_IPV6:
1221 ip_proto = ipv6_hdr(skb)->nexthdr;
1222 break;
1223 default:
bc23333b 1224 return skb;
1c1008c7
FF		 1225 }
1226
1227 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1228 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1229 (offset + skb->csum_offset);
1230
1231 /* Set the length valid bit for TCP and UDP and just set
1232 * the special UDP flag for IPv4, else just set to 0.
1233 */
1234 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1235 tx_csum_info |= STATUS_TX_CSUM_LV;
1236 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1237 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1238 } else {
1c1008c7 1239 tx_csum_info = 0;
8900ea57 1240 }
1c1008c7
FF		 1241
1242 status->tx_csum_info = tx_csum_info;
1243 }
1244
bc23333b 1245 return skb;
1c1008c7
FF		 1246}
1247
1248static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1249{
1250 struct bcmgenet_priv *priv = netdev_priv(dev);
1251 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1252 struct netdev_queue *txq;
1c1008c7
FF		 1253 unsigned long flags = 0;
1254 int nr_frags, index;
1255 u16 dma_desc_flags;
1256 int ret;
1257 int i;
1258
1259 index = skb_get_queue_mapping(skb);
1260 /* Mapping strategy:
1261 * queue_mapping = 0, unclassified, packet xmited through ring16
1262 * queue_mapping = 1, goes to ring 0. (highest priority queue
1263 * queue_mapping = 2, goes to ring 1.
1264 * queue_mapping = 3, goes to ring 2.
1265 * queue_mapping = 4, goes to ring 3.
1266 */
1267 if (index == 0)
1268 index = DESC_INDEX;
1269 else
1270 index -= 1;
1271
1c1008c7
FF		 1272 nr_frags = skb_shinfo(skb)->nr_frags;
1273 ring = &priv->tx_rings[index];
b2cde2cc 1274 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1275
1276 spin_lock_irqsave(&ring->lock, flags);
1277 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1278 netif_tx_stop_queue(txq);
1c1008c7 1279 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1280 __func__, index, ring->queue);
1c1008c7
FF		 1281 ret = NETDEV_TX_BUSY;
1282 goto out;
1283 }
1284
474ea9ca
FF		 1285 if (skb_padto(skb, ETH_ZLEN)) {
1286 ret = NETDEV_TX_OK;
1287 goto out;
1288 }
1289
1c1008c7
FF		 1290 /* set the SKB transmit checksum */
1291 if (priv->desc_64b_en) {
bc23333b
PG		 1292 skb = bcmgenet_put_tx_csum(dev, skb);
1293 if (!skb) {
1c1008c7
FF		 1294 ret = NETDEV_TX_OK;
1295 goto out;
1296 }
1297 }
1298
1299 dma_desc_flags = DMA_SOP;
1300 if (nr_frags == 0)
1301 dma_desc_flags |= DMA_EOP;
1302
1303 /* Transmit single SKB or head of fragment list */
1304 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1305 if (ret) {
1306 ret = NETDEV_TX_OK;
1307 goto out;
1308 }
1309
1310 /* xmit fragment */
1311 for (i = 0; i < nr_frags; i++) {
1312 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1313 &skb_shinfo(skb)->frags[i],
1314 (i == nr_frags - 1) ? DMA_EOP : 0,
1315 ring);
1c1008c7
FF		 1316 if (ret) {
1317 ret = NETDEV_TX_OK;
1318 goto out;
1319 }
1320 }
1321
d03825fb
FF		 1322 skb_tx_timestamp(skb);
1323
1c1008c7
FF		 1324 /* we kept a software copy of how much we should advance the TDMA
1325 * producer index, now write it down to the hardware
1326 */
1327 bcmgenet_tdma_ring_writel(priv, ring->index,
c91b7f66 1328 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7 1329
4092e6ac 1330 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1331 netif_tx_stop_queue(txq);
1c1008c7
FF		 1332
1333out:
1334 spin_unlock_irqrestore(&ring->lock, flags);
1335
1336 return ret;
1337}
1338
1339
c91b7f66 1340static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1c1008c7
FF		 1341{
1342 struct device *kdev = &priv->pdev->dev;
1343 struct sk_buff *skb;
1344 dma_addr_t mapping;
1345 int ret;
1346
c91b7f66 1347 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1c1008c7
FF		 1348 if (!skb)
1349 return -ENOMEM;
1350
1351 /* a caller did not release this control block */
1352 WARN_ON(cb->skb != NULL);
1353 cb->skb = skb;
1354 mapping = dma_map_single(kdev, skb->data,
c91b7f66 1355 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1356 ret = dma_mapping_error(kdev, mapping);
1357 if (ret) {
44c8bc3c 1358 priv->mib.rx_dma_failed++;
1c1008c7
FF		 1359 bcmgenet_free_cb(cb);
1360 netif_err(priv, rx_err, priv->dev,
c91b7f66 1361 "%s DMA map failed\n", __func__);
1c1008c7
FF		 1362 return ret;
1363 }
1364
1365 dma_unmap_addr_set(cb, dma_addr, mapping);
8ac467e8 1366 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7
FF		 1367
1368 return 0;
1369}
1370
1371/* bcmgenet_desc_rx - descriptor based rx process.
1372 * this could be called from bottom half, or from NAPI polling method.
1373 */
1374static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
8ac467e8 1375 unsigned int index,
1c1008c7
FF		 1376 unsigned int budget)
1377{
8ac467e8 1378 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 1379 struct net_device *dev = priv->dev;
1380 struct enet_cb *cb;
1381 struct sk_buff *skb;
1382 u32 dma_length_status;
1383 unsigned long dma_flag;
1384 int len, err;
1385 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1386 unsigned int p_index;
1387 unsigned int chksum_ok = 0;
1388
8ac467e8 1389 p_index = bcmgenet_rdma_ring_readl(priv, index, RDMA_PROD_INDEX);
1c1008c7
FF		 1390 p_index &= DMA_P_INDEX_MASK;
1391
8ac467e8
PG		 1392 if (likely(p_index >= ring->c_index))
1393 rxpkttoprocess = p_index - ring->c_index;
1c1008c7 1394 else
8ac467e8
PG		 1395 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1396 p_index;
1c1008c7
FF		 1397
1398 netif_dbg(priv, rx_status, dev,
c91b7f66 1399 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1400
1401 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1402 (rxpktprocessed < budget)) {
8ac467e8 1403 cb = &priv->rx_cbs[ring->read_ptr];
b629be5c
FF		 1404 skb = cb->skb;
1405
b629be5c
FF		 1406 /* We do not have a backing SKB, so we do not have a
1407 * corresponding DMA mapping for this incoming packet since
1408 * bcmgenet_rx_refill always either has both skb and mapping or
1409 * none.
1410 */
1411 if (unlikely(!skb)) {
1412 dev->stats.rx_dropped++;
1413 dev->stats.rx_errors++;
1414 goto refill;
1415 }
1416
1c1008c7
FF		 1417 /* Unmap the packet contents such that we can use the
1418 * RSV from the 64 bytes descriptor when enabled and save
1419 * a 32-bits register read
1420 */
1c1008c7 1421 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
c91b7f66 1422 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1423
1424 if (!priv->desc_64b_en) {
c91b7f66 1425 dma_length_status =
8ac467e8 1426 dmadesc_get_length_status(priv, cb->bd_addr);
1c1008c7
FF		 1427 } else {
1428 struct status_64 *status;
164d4f20 1429
1c1008c7
FF		 1430 status = (struct status_64 *)skb->data;
1431 dma_length_status = status->length_status;
1432 }
1433
1434 /* DMA flags and length are still valid no matter how
1435 * we got the Receive Status Vector (64B RSB or register)
1436 */
1437 dma_flag = dma_length_status & 0xffff;
1438 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1439
1440 netif_dbg(priv, rx_status, dev,
c91b7f66 1441 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1442 __func__, p_index, ring->c_index,
1443 ring->read_ptr, dma_length_status);
1c1008c7 1444
1c1008c7
FF		 1445 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1446 netif_err(priv, rx_status, dev,
c91b7f66 1447 "dropping fragmented packet!\n");
1c1008c7
FF		 1448 dev->stats.rx_dropped++;
1449 dev->stats.rx_errors++;
1450 dev_kfree_skb_any(cb->skb);
1451 cb->skb = NULL;
1452 goto refill;
1453 }
1454 /* report errors */
1455 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1456 DMA_RX_OV |
1457 DMA_RX_NO |
1458 DMA_RX_LG |
1459 DMA_RX_RXER))) {
1460 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1461 (unsigned int)dma_flag);
1c1008c7
FF		 1462 if (dma_flag & DMA_RX_CRC_ERROR)
1463 dev->stats.rx_crc_errors++;
1464 if (dma_flag & DMA_RX_OV)
1465 dev->stats.rx_over_errors++;
1466 if (dma_flag & DMA_RX_NO)
1467 dev->stats.rx_frame_errors++;
1468 if (dma_flag & DMA_RX_LG)
1469 dev->stats.rx_length_errors++;
1470 dev->stats.rx_dropped++;
1471 dev->stats.rx_errors++;
1472
1473 /* discard the packet and advance consumer index.*/
1474 dev_kfree_skb_any(cb->skb);
1475 cb->skb = NULL;
1476 goto refill;
1477 } /* error packet */
1478
1479 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1480 priv->desc_rxchk_en;
1c1008c7
FF		 1481
1482 skb_put(skb, len);
1483 if (priv->desc_64b_en) {
1484 skb_pull(skb, 64);
1485 len -= 64;
1486 }
1487
1488 if (likely(chksum_ok))
1489 skb->ip_summed = CHECKSUM_UNNECESSARY;
1490
1491 /* remove hardware 2bytes added for IP alignment */
1492 skb_pull(skb, 2);
1493 len -= 2;
1494
1495 if (priv->crc_fwd_en) {
1496 skb_trim(skb, len - ETH_FCS_LEN);
1497 len -= ETH_FCS_LEN;
1498 }
1499
1500 /*Finish setting up the received SKB and send it to the kernel*/
1501 skb->protocol = eth_type_trans(skb, priv->dev);
1502 dev->stats.rx_packets++;
1503 dev->stats.rx_bytes += len;
1504 if (dma_flag & DMA_RX_MULT)
1505 dev->stats.multicast++;
1506
1507 /* Notify kernel */
1508 napi_gro_receive(&priv->napi, skb);
1509 cb->skb = NULL;
1510 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1511
1512 /* refill RX path on the current control block */
1513refill:
1514 err = bcmgenet_rx_refill(priv, cb);
44c8bc3c
FF		 1515 if (err) {
1516 priv->mib.alloc_rx_buff_failed++;
1c1008c7 1517 netif_err(priv, rx_err, dev, "Rx refill failed\n");
44c8bc3c 1518 }
cf377d88
FF		 1519
1520 rxpktprocessed++;
8ac467e8
PG		 1521 if (likely(ring->read_ptr < ring->end_ptr))
1522 ring->read_ptr++;
1523 else
1524 ring->read_ptr = ring->cb_ptr;
1525
1526 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1527 bcmgenet_rdma_ring_writel(priv, index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1528 }
1529
1530 return rxpktprocessed;
1531}
1532
1533/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1534static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1535 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1536{
1537 struct enet_cb *cb;
1538 int ret = 0;
1539 int i;
1540
8ac467e8 1541 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1542
1543 /* loop here for each buffer needing assign */
8ac467e8
PG		 1544 for (i = 0; i < ring->size; i++) {
1545 cb = ring->cbs + i;
1c1008c7
FF		 1546 if (cb->skb)
1547 continue;
1548
1c1008c7
FF		 1549 ret = bcmgenet_rx_refill(priv, cb);
1550 if (ret)
1551 break;
1c1008c7
FF		 1552 }
1553
1554 return ret;
1555}
1556
1557static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1558{
1559 struct enet_cb *cb;
1560 int i;
1561
1562 for (i = 0; i < priv->num_rx_bds; i++) {
1563 cb = &priv->rx_cbs[i];
1564
1565 if (dma_unmap_addr(cb, dma_addr)) {
1566 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1567 dma_unmap_addr(cb, dma_addr),
1568 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1569 dma_unmap_addr_set(cb, dma_addr, 0);
1570 }
1571
1572 if (cb->skb)
1573 bcmgenet_free_cb(cb);
1574 }
1575}
1576
c91b7f66 1577static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1578{
1579 u32 reg;
1580
1581 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1582 if (enable)
1583 reg |= mask;
1584 else
1585 reg &= ~mask;
1586 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1587
1588 /* UniMAC stops on a packet boundary, wait for a full-size packet
1589 * to be processed
1590 */
1591 if (enable == 0)
1592 usleep_range(1000, 2000);
1593}
1594
1c1008c7
FF		 1595static int reset_umac(struct bcmgenet_priv *priv)
1596{
1597 struct device *kdev = &priv->pdev->dev;
1598 unsigned int timeout = 0;
1599 u32 reg;
1600
1601 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1602 bcmgenet_rbuf_ctrl_set(priv, 0);
1603 udelay(10);
1604
1605 /* disable MAC while updating its registers */
1606 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1607
1608 /* issue soft reset, wait for it to complete */
1609 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1610 while (timeout++ < 1000) {
1611 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1612 if (!(reg & CMD_SW_RESET))
1613 return 0;
1614
1615 udelay(1);
1616 }
1617
1618 if (timeout == 1000) {
1619 dev_err(kdev,
7fc527f9 1620 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1621 return -ETIMEDOUT;
1622 }
1623
1624 return 0;
1625}
1626
909ff5ef
FF		 1627static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1628{
1629 /* Mask all interrupts.*/
1630 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1631 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1632 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1633 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1634 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1635 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1636}
1637
1c1008c7
FF		 1638static int init_umac(struct bcmgenet_priv *priv)
1639{
1640 struct device *kdev = &priv->pdev->dev;
1641 int ret;
1642 u32 reg, cpu_mask_clear;
4092e6ac 1643 int index;
1c1008c7
FF		 1644
1645 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1646
1647 ret = reset_umac(priv);
1648 if (ret)
1649 return ret;
1650
1651 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1652 /* clear tx/rx counter */
1653 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1654 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1655 UMAC_MIB_CTRL);
1c1008c7
FF		 1656 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1657
1658 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1659
1660 /* init rx registers, enable ip header optimization */
1661 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1662 reg |= RBUF_ALIGN_2B;
1663 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1664
1665 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1666 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1667
909ff5ef 1668 bcmgenet_intr_disable(priv);
1c1008c7 1669
4092e6ac 1670 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_TXDMA_BDONE;
1c1008c7
FF		 1671
1672 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1673
7fc527f9 1674 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1675 if (phy_is_internal(priv->phydev)) {
1c1008c7 1676 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1677 } else if (priv->ext_phy) {
1c1008c7 1678 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1679 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1680 reg = bcmgenet_bp_mc_get(priv);
1681 reg |= BIT(priv->hw_params->bp_in_en_shift);
1682
1683 /* bp_mask: back pressure mask */
1684 if (netif_is_multiqueue(priv->dev))
1685 reg |= priv->hw_params->bp_in_mask;
1686 else
1687 reg &= ~priv->hw_params->bp_in_mask;
1688 bcmgenet_bp_mc_set(priv, reg);
1689 }
1690
1691 /* Enable MDIO interrupts on GENET v3+ */
1692 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1693 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1694
c91b7f66 1695 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1c1008c7 1696
4092e6ac
JS		 1697 for (index = 0; index < priv->hw_params->tx_queues; index++)
1698 bcmgenet_intrl2_1_writel(priv, (1 << index),
1699 INTRL2_CPU_MASK_CLEAR);
1700
1c1008c7
FF		 1701 /* Enable rx/tx engine.*/
1702 dev_dbg(kdev, "done init umac\n");
1703
1704 return 0;
1705}
1706
4f8b2d7d 1707/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1708static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1709 unsigned int index, unsigned int size,
4f8b2d7d 1710 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1711{
1712 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1713 u32 words_per_bd = WORDS_PER_BD(priv);
1714 u32 flow_period_val = 0;
1c1008c7
FF		 1715
1716 spin_lock_init(&ring->lock);
4092e6ac
JS		 1717 ring->priv = priv;
1718 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1c1008c7
FF		 1719 ring->index = index;
1720 if (index == DESC_INDEX) {
1721 ring->queue = 0;
1722 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1723 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1724 } else {
1725 ring->queue = index + 1;
1726 ring->int_enable = bcmgenet_tx_ring_int_enable;
1727 ring->int_disable = bcmgenet_tx_ring_int_disable;
1728 }
4f8b2d7d 1729 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1730 ring->size = size;
66d06757 1731 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1732 ring->c_index = 0;
1733 ring->free_bds = size;
4f8b2d7d
PG		 1734 ring->write_ptr = start_ptr;
1735 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1736 ring->end_ptr = end_ptr - 1;
1737 ring->prod_index = 0;
1738
1739 /* Set flow period for ring != 16 */
1740 if (index != DESC_INDEX)
1741 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1742
1743 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1744 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1745 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1746 /* Disable rate control for now */
1747 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1748 TDMA_FLOW_PERIOD);
1c1008c7 1749 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1750 ((size << DMA_RING_SIZE_SHIFT) |
1751 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1752
1c1008c7 1753 /* Set start and end address, read and write pointers */
4f8b2d7d 1754 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1755 DMA_START_ADDR);
4f8b2d7d 1756 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1757 TDMA_READ_PTR);
4f8b2d7d 1758 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1759 TDMA_WRITE_PTR);
1c1008c7 1760 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1761 DMA_END_ADDR);
4092e6ac
JS		 1762
1763 napi_enable(&ring->napi);
1764}
1765
1766static void bcmgenet_fini_tx_ring(struct bcmgenet_priv *priv,
1767 unsigned int index)
1768{
1769 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1770
1771 napi_disable(&ring->napi);
1772 netif_napi_del(&ring->napi);
1c1008c7
FF		 1773}
1774
1775/* Initialize a RDMA ring */
1776static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 1777 unsigned int index, unsigned int size,
1778 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 1779{
8ac467e8 1780 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 1781 u32 words_per_bd = WORDS_PER_BD(priv);
1782 int ret;
1783
8ac467e8
PG		 1784 ring->index = index;
1785 ring->cbs = priv->rx_cbs + start_ptr;
1786 ring->size = size;
1787 ring->c_index = 0;
1788 ring->read_ptr = start_ptr;
1789 ring->cb_ptr = start_ptr;
1790 ring->end_ptr = end_ptr - 1;
1c1008c7 1791
8ac467e8
PG		 1792 ret = bcmgenet_alloc_rx_buffers(priv, ring);
1793 if (ret)
1c1008c7 1794 return ret;
1c1008c7 1795
1c1008c7
FF		 1796 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1797 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 1798 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 1799 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1800 ((size << DMA_RING_SIZE_SHIFT) |
1801 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1802 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1803 (DMA_FC_THRESH_LO <<
1804 DMA_XOFF_THRESHOLD_SHIFT) |
1805 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 1806
1807 /* Set start and end address, read and write pointers */
8ac467e8
PG		 1808 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1809 DMA_START_ADDR);
1810 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1811 RDMA_READ_PTR);
1812 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1813 RDMA_WRITE_PTR);
1814 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 1815 DMA_END_ADDR);
1c1008c7
FF		 1816
1817 return ret;
1818}
1819
16c6d667 1820/* Initialize Tx queues
1c1008c7 1821 *
16c6d667 1822 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 1823 * with queue 0 being the highest priority queue.
1824 *
16c6d667 1825 * Queue 16 is the default Tx queue with
51a966a7 1826 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 1827 *
16c6d667
PG		 1828 * The transmit control block pool is then partitioned as follows:
1829 * - Tx queue 0 uses tx_cbs[0..31]
1830 * - Tx queue 1 uses tx_cbs[32..63]
1831 * - Tx queue 2 uses tx_cbs[64..95]
1832 * - Tx queue 3 uses tx_cbs[96..127]
1833 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 1834 */
16c6d667 1835static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 1836{
1837 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 1838 u32 i, dma_enable;
1839 u32 dma_ctrl, ring_cfg;
37742166 1840 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 1841
1c1008c7
FF		 1842 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1843 dma_enable = dma_ctrl & DMA_EN;
1844 dma_ctrl &= ~DMA_EN;
1845 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1846
16c6d667
PG		 1847 dma_ctrl = 0;
1848 ring_cfg = 0;
1849
1c1008c7
FF		 1850 /* Enable strict priority arbiter mode */
1851 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1852
16c6d667 1853 /* Initialize Tx priority queues */
1c1008c7 1854 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 1855 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
1856 i * priv->hw_params->tx_bds_per_q,
1857 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 1858 ring_cfg |= (1 << i);
1859 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1860 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1861 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 1862 }
1863
16c6d667 1864 /* Initialize Tx default queue 16 */
51a966a7 1865 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 1866 priv->hw_params->tx_queues *
51a966a7 1867 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 1868 TOTAL_DESC);
1869 ring_cfg |= (1 << DESC_INDEX);
1870 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1871 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1872 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1873 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 1874
1875 /* Set Tx queue priorities */
37742166
PG		 1876 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1877 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1878 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1879
16c6d667
PG		 1880 /* Enable Tx queues */
1881 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 1882
16c6d667 1883 /* Enable Tx DMA */
1c1008c7 1884 if (dma_enable)
16c6d667
PG		 1885 dma_ctrl |= DMA_EN;
1886 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 1887}
1888
8ac467e8
PG		 1889/* Initialize Rx queues
1890 *
1891 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
1892 * used to direct traffic to these queues.
1893 *
1894 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
1895 */
1896static int bcmgenet_init_rx_queues(struct net_device *dev)
1897{
1898 struct bcmgenet_priv *priv = netdev_priv(dev);
1899 u32 i;
1900 u32 dma_enable;
1901 u32 dma_ctrl;
1902 u32 ring_cfg;
1903 int ret;
1904
1905 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
1906 dma_enable = dma_ctrl & DMA_EN;
1907 dma_ctrl &= ~DMA_EN;
1908 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
1909
1910 dma_ctrl = 0;
1911 ring_cfg = 0;
1912
1913 /* Initialize Rx priority queues */
1914 for (i = 0; i < priv->hw_params->rx_queues; i++) {
1915 ret = bcmgenet_init_rx_ring(priv, i,
1916 priv->hw_params->rx_bds_per_q,
1917 i * priv->hw_params->rx_bds_per_q,
1918 (i + 1) *
1919 priv->hw_params->rx_bds_per_q);
1920 if (ret)
1921 return ret;
1922
1923 ring_cfg |= (1 << i);
1924 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
1925 }
1926
1927 /* Initialize Rx default queue 16 */
1928 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
1929 priv->hw_params->rx_queues *
1930 priv->hw_params->rx_bds_per_q,
1931 TOTAL_DESC);
1932 if (ret)
1933 return ret;
1934
1935 ring_cfg |= (1 << DESC_INDEX);
1936 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
1937
1938 /* Enable rings */
1939 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
1940
1941 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1942 if (dma_enable)
1943 dma_ctrl |= DMA_EN;
1944 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
1945
1946 return 0;
1947}
1948
4a0c081e
FF		 1949static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1950{
1951 int ret = 0;
1952 int timeout = 0;
1953 u32 reg;
1954
1955 /* Disable TDMA to stop add more frames in TX DMA */
1956 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1957 reg &= ~DMA_EN;
1958 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1959
1960 /* Check TDMA status register to confirm TDMA is disabled */
1961 while (timeout++ < DMA_TIMEOUT_VAL) {
1962 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1963 if (reg & DMA_DISABLED)
1964 break;
1965
1966 udelay(1);
1967 }
1968
1969 if (timeout == DMA_TIMEOUT_VAL) {
1970 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1971 ret = -ETIMEDOUT;
1972 }
1973
1974 /* Wait 10ms for packet drain in both tx and rx dma */
1975 usleep_range(10000, 20000);
1976
1977 /* Disable RDMA */
1978 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1979 reg &= ~DMA_EN;
1980 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1981
1982 timeout = 0;
1983 /* Check RDMA status register to confirm RDMA is disabled */
1984 while (timeout++ < DMA_TIMEOUT_VAL) {
1985 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
1986 if (reg & DMA_DISABLED)
1987 break;
1988
1989 udelay(1);
1990 }
1991
1992 if (timeout == DMA_TIMEOUT_VAL) {
1993 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
1994 ret = -ETIMEDOUT;
1995 }
1996
1997 return ret;
1998}
1999
4092e6ac 2000static void __bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 2001{
2002 int i;
2003
2004 /* disable DMA */
4a0c081e 2005 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2006
2007 for (i = 0; i < priv->num_tx_bds; i++) {
2008 if (priv->tx_cbs[i].skb != NULL) {
2009 dev_kfree_skb(priv->tx_cbs[i].skb);
2010 priv->tx_cbs[i].skb = NULL;
2011 }
2012 }
2013
2014 bcmgenet_free_rx_buffers(priv);
2015 kfree(priv->rx_cbs);
2016 kfree(priv->tx_cbs);
2017}
2018
4092e6ac
JS		 2019static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2020{
2021 int i;
2022
2023 bcmgenet_fini_tx_ring(priv, DESC_INDEX);
2024
2025 for (i = 0; i < priv->hw_params->tx_queues; i++)
2026 bcmgenet_fini_tx_ring(priv, i);
2027
2028 __bcmgenet_fini_dma(priv);
2029}
2030
1c1008c7
FF		 2031/* init_edma: Initialize DMA control register */
2032static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2033{
2034 int ret;
014012a4
PG		 2035 unsigned int i;
2036 struct enet_cb *cb;
1c1008c7 2037
6f5a272c 2038 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2039
6f5a272c
PG		 2040 /* Init rDma */
2041 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2042
2043 /* Initialize common Rx ring structures */
2044 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2045 priv->num_rx_bds = TOTAL_DESC;
2046 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2047 GFP_KERNEL);
2048 if (!priv->rx_cbs)
2049 return -ENOMEM;
2050
2051 for (i = 0; i < priv->num_rx_bds; i++) {
2052 cb = priv->rx_cbs + i;
2053 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2054 }
2055
8ac467e8
PG		 2056 /* Initialize Rx queues */
2057 ret = bcmgenet_init_rx_queues(priv->dev);
1c1008c7 2058 if (ret) {
8ac467e8 2059 netdev_err(priv->dev, "failed to initialize Rx queues\n");
6f5a272c
PG		 2060 bcmgenet_free_rx_buffers(priv);
2061 kfree(priv->rx_cbs);
1c1008c7
FF		 2062 return ret;
2063 }
2064
1c1008c7
FF		 2065 /* Init tDma */
2066 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2067
7fc527f9 2068 /* Initialize common TX ring structures */
1c1008c7
FF		 2069 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2070 priv->num_tx_bds = TOTAL_DESC;
c489be08 2071 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2072 GFP_KERNEL);
1c1008c7 2073 if (!priv->tx_cbs) {
4092e6ac 2074 __bcmgenet_fini_dma(priv);
1c1008c7
FF		 2075 return -ENOMEM;
2076 }
2077
014012a4
PG		 2078 for (i = 0; i < priv->num_tx_bds; i++) {
2079 cb = priv->tx_cbs + i;
2080 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2081 }
2082
16c6d667
PG		 2083 /* Initialize Tx queues */
2084 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2085
2086 return 0;
2087}
2088
2089/* NAPI polling method*/
2090static int bcmgenet_poll(struct napi_struct *napi, int budget)
2091{
2092 struct bcmgenet_priv *priv = container_of(napi,
2093 struct bcmgenet_priv, napi);
2094 unsigned int work_done;
2095
8ac467e8 2096 work_done = bcmgenet_desc_rx(priv, DESC_INDEX, budget);
1c1008c7 2097
1c1008c7
FF		 2098 if (work_done < budget) {
2099 napi_complete(napi);
c91b7f66
FF		 2100 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2101 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 2102 }
2103
2104 return work_done;
2105}
2106
2107/* Interrupt bottom half */
2108static void bcmgenet_irq_task(struct work_struct *work)
2109{
2110 struct bcmgenet_priv *priv = container_of(
2111 work, struct bcmgenet_priv, bcmgenet_irq_work);
2112
2113 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2114
8fdb0e0f
FF		 2115 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2116 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2117 netif_dbg(priv, wol, priv->dev,
2118 "magic packet detected, waking up\n");
2119 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2120 }
2121
1c1008c7
FF		 2122 /* Link UP/DOWN event */
2123 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2124 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d 2125 phy_mac_interrupt(priv->phydev,
c91b7f66 2126 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 2127 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
2128 }
2129}
2130
2131/* bcmgenet_isr1: interrupt handler for ring buffer. */
2132static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2133{
2134 struct bcmgenet_priv *priv = dev_id;
4092e6ac 2135 struct bcmgenet_tx_ring *ring;
1c1008c7
FF		 2136 unsigned int index;
2137
2138 /* Save irq status for bottom-half processing. */
2139 priv->irq1_stat =
2140 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2141 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2142 /* clear interrupts */
1c1008c7
FF		 2143 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2144
2145 netif_dbg(priv, intr, priv->dev,
c91b7f66 2146 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2147
1c1008c7
FF		 2148 /* Check the MBDONE interrupts.
2149 * packet is done, reclaim descriptors
2150 */
4092e6ac
JS		 2151 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2152 if (!(priv->irq1_stat & BIT(index)))
2153 continue;
2154
2155 ring = &priv->tx_rings[index];
2156
2157 if (likely(napi_schedule_prep(&ring->napi))) {
2158 ring->int_disable(priv, ring);
2159 __napi_schedule(&ring->napi);
1c1008c7
FF		 2160 }
2161 }
4092e6ac 2162
1c1008c7
FF		 2163 return IRQ_HANDLED;
2164}
2165
2166/* bcmgenet_isr0: Handle various interrupts. */
2167static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2168{
2169 struct bcmgenet_priv *priv = dev_id;
2170
2171 /* Save irq status for bottom-half processing. */
2172 priv->irq0_stat =
2173 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2174 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2175 /* clear interrupts */
1c1008c7
FF		 2176 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2177
2178 netif_dbg(priv, intr, priv->dev,
c91b7f66 2179 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7
FF		 2180
2181 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
2182 /* We use NAPI(software interrupt throttling, if
2183 * Rx Descriptor throttling is not used.
2184 * Disable interrupt, will be enabled in the poll method.
2185 */
2186 if (likely(napi_schedule_prep(&priv->napi))) {
c91b7f66
FF		 2187 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2188 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 2189 __napi_schedule(&priv->napi);
2190 }
2191 }
2192 if (priv->irq0_stat &
2193 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
4092e6ac
JS		 2194 struct bcmgenet_tx_ring *ring = &priv->tx_rings[DESC_INDEX];
2195
2196 if (likely(napi_schedule_prep(&ring->napi))) {
2197 ring->int_disable(priv, ring);
2198 __napi_schedule(&ring->napi);
2199 }
1c1008c7
FF		 2200 }
2201 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2202 UMAC_IRQ_PHY_DET_F |
2203 UMAC_IRQ_LINK_UP |
2204 UMAC_IRQ_LINK_DOWN |
2205 UMAC_IRQ_HFB_SM |
2206 UMAC_IRQ_HFB_MM |
2207 UMAC_IRQ_MPD_R)) {
2208 /* all other interested interrupts handled in bottom half */
2209 schedule_work(&priv->bcmgenet_irq_work);
2210 }
2211
2212 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2213 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2214 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2215 wake_up(&priv->wq);
2216 }
2217
2218 return IRQ_HANDLED;
2219}
2220
8562056f
FF		 2221static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2222{
2223 struct bcmgenet_priv *priv = dev_id;
2224
2225 pm_wakeup_event(&priv->pdev->dev, 0);
2226
2227 return IRQ_HANDLED;
2228}
2229
1c1008c7
FF		 2230static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2231{
2232 u32 reg;
2233
2234 reg = bcmgenet_rbuf_ctrl_get(priv);
2235 reg |= BIT(1);
2236 bcmgenet_rbuf_ctrl_set(priv, reg);
2237 udelay(10);
2238
2239 reg &= ~BIT(1);
2240 bcmgenet_rbuf_ctrl_set(priv, reg);
2241 udelay(10);
2242}
2243
2244static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2245 unsigned char *addr)
1c1008c7
FF		 2246{
2247 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2248 (addr[2] << 8) | addr[3], UMAC_MAC0);
2249 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2250}
2251
1c1008c7
FF		 2252/* Returns a reusable dma control register value */
2253static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2254{
2255 u32 reg;
2256 u32 dma_ctrl;
2257
2258 /* disable DMA */
2259 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2260 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2261 reg &= ~dma_ctrl;
2262 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2263
2264 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2265 reg &= ~dma_ctrl;
2266 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2267
2268 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2269 udelay(10);
2270 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2271
2272 return dma_ctrl;
2273}
2274
2275static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2276{
2277 u32 reg;
2278
2279 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2280 reg |= dma_ctrl;
2281 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2282
2283 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2284 reg |= dma_ctrl;
2285 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2286}
2287
909ff5ef
FF		 2288static void bcmgenet_netif_start(struct net_device *dev)
2289{
2290 struct bcmgenet_priv *priv = netdev_priv(dev);
2291
2292 /* Start the network engine */
2293 napi_enable(&priv->napi);
2294
2295 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2296
2297 if (phy_is_internal(priv->phydev))
2298 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2299
2300 netif_tx_start_all_queues(dev);
2301
2302 phy_start(priv->phydev);
2303}
2304
1c1008c7
FF		 2305static int bcmgenet_open(struct net_device *dev)
2306{
2307 struct bcmgenet_priv *priv = netdev_priv(dev);
2308 unsigned long dma_ctrl;
2309 u32 reg;
2310 int ret;
2311
2312 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2313
2314 /* Turn on the clock */
2315 if (!IS_ERR(priv->clk))
2316 clk_prepare_enable(priv->clk);
2317
2318 /* take MAC out of reset */
2319 bcmgenet_umac_reset(priv);
2320
2321 ret = init_umac(priv);
2322 if (ret)
2323 goto err_clk_disable;
2324
2325 /* disable ethernet MAC while updating its registers */
e29585b8 2326 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2327
909ff5ef
FF		 2328 /* Make sure we reflect the value of CRC_CMD_FWD */
2329 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2330 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2331
1c1008c7
FF		 2332 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2333
1c1008c7
FF		 2334 if (phy_is_internal(priv->phydev)) {
2335 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2336 reg |= EXT_ENERGY_DET_MASK;
2337 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2338 }
2339
2340 /* Disable RX/TX DMA and flush TX queues */
2341 dma_ctrl = bcmgenet_dma_disable(priv);
2342
2343 /* Reinitialize TDMA and RDMA and SW housekeeping */
2344 ret = bcmgenet_init_dma(priv);
2345 if (ret) {
2346 netdev_err(dev, "failed to initialize DMA\n");
2347 goto err_fini_dma;
2348 }
2349
2350 /* Always enable ring 16 - descriptor ring */
2351 bcmgenet_enable_dma(priv, dma_ctrl);
2352
2353 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2354 dev->name, priv);
1c1008c7
FF		 2355 if (ret < 0) {
2356 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2357 goto err_fini_dma;
2358 }
2359
2360 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2361 dev->name, priv);
1c1008c7
FF		 2362 if (ret < 0) {
2363 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2364 goto err_irq0;
2365 }
2366
dbd479db
FF		 2367 /* Re-configure the port multiplexer towards the PHY device */
2368 bcmgenet_mii_config(priv->dev, false);
2369
c96e731c
FF		 2370 phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2371 priv->phy_interface);
2372
909ff5ef 2373 bcmgenet_netif_start(dev);
1c1008c7
FF		 2374
2375 return 0;
2376
2377err_irq0:
2378 free_irq(priv->irq0, dev);
2379err_fini_dma:
2380 bcmgenet_fini_dma(priv);
2381err_clk_disable:
2382 if (!IS_ERR(priv->clk))
2383 clk_disable_unprepare(priv->clk);
2384 return ret;
2385}
2386
909ff5ef
FF		 2387static void bcmgenet_netif_stop(struct net_device *dev)
2388{
2389 struct bcmgenet_priv *priv = netdev_priv(dev);
2390
2391 netif_tx_stop_all_queues(dev);
2392 napi_disable(&priv->napi);
2393 phy_stop(priv->phydev);
2394
2395 bcmgenet_intr_disable(priv);
2396
2397 /* Wait for pending work items to complete. Since interrupts are
2398 * disabled no new work will be scheduled.
2399 */
2400 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2401
cc013fb4 2402 priv->old_link = -1;
5ad6e6c5 2403 priv->old_speed = -1;
cc013fb4 2404 priv->old_duplex = -1;
5ad6e6c5 2405 priv->old_pause = -1;
909ff5ef
FF		 2406}
2407
1c1008c7
FF		 2408static int bcmgenet_close(struct net_device *dev)
2409{
2410 struct bcmgenet_priv *priv = netdev_priv(dev);
2411 int ret;
1c1008c7
FF		 2412
2413 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2414
909ff5ef 2415 bcmgenet_netif_stop(dev);
1c1008c7 2416
c96e731c
FF		 2417 /* Really kill the PHY state machine and disconnect from it */
2418 phy_disconnect(priv->phydev);
2419
1c1008c7 2420 /* Disable MAC receive */
e29585b8 2421 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2422
1c1008c7
FF		 2423 ret = bcmgenet_dma_teardown(priv);
2424 if (ret)
2425 return ret;
2426
2427 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2428 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2429
1c1008c7
FF		 2430 /* tx reclaim */
2431 bcmgenet_tx_reclaim_all(dev);
2432 bcmgenet_fini_dma(priv);
2433
2434 free_irq(priv->irq0, priv);
2435 free_irq(priv->irq1, priv);
2436
1c1008c7
FF		 2437 if (phy_is_internal(priv->phydev))
2438 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2439
1c1008c7
FF		 2440 if (!IS_ERR(priv->clk))
2441 clk_disable_unprepare(priv->clk);
2442
2443 return 0;
2444}
2445
2446static void bcmgenet_timeout(struct net_device *dev)
2447{
2448 struct bcmgenet_priv *priv = netdev_priv(dev);
2449
2450 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2451
2452 dev->trans_start = jiffies;
2453
2454 dev->stats.tx_errors++;
2455
2456 netif_tx_wake_all_queues(dev);
2457}
2458
2459#define MAX_MC_COUNT 16
2460
2461static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2462 unsigned char *addr,
2463 int *i,
2464 int *mc)
2465{
2466 u32 reg;
2467
c91b7f66
FF		 2468 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2469 UMAC_MDF_ADDR + (*i * 4));
2470 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2471 addr[4] << 8 | addr[5],
2472 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2473 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2474 reg |= (1 << (MAX_MC_COUNT - *mc));
2475 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2476 *i += 2;
2477 (*mc)++;
2478}
2479
2480static void bcmgenet_set_rx_mode(struct net_device *dev)
2481{
2482 struct bcmgenet_priv *priv = netdev_priv(dev);
2483 struct netdev_hw_addr *ha;
2484 int i, mc;
2485 u32 reg;
2486
2487 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2488
7fc527f9 2489 /* Promiscuous mode */
1c1008c7
FF		 2490 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2491 if (dev->flags & IFF_PROMISC) {
2492 reg |= CMD_PROMISC;
2493 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2494 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2495 return;
2496 } else {
2497 reg &= ~CMD_PROMISC;
2498 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2499 }
2500
2501 /* UniMac doesn't support ALLMULTI */
2502 if (dev->flags & IFF_ALLMULTI) {
2503 netdev_warn(dev, "ALLMULTI is not supported\n");
2504 return;
2505 }
2506
2507 /* update MDF filter */
2508 i = 0;
2509 mc = 0;
2510 /* Broadcast */
2511 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2512 /* my own address.*/
2513 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2514 /* Unicast list*/
2515 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2516 return;
2517
2518 if (!netdev_uc_empty(dev))
2519 netdev_for_each_uc_addr(ha, dev)
2520 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2521 /* Multicast */
2522 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2523 return;
2524
2525 netdev_for_each_mc_addr(ha, dev)
2526 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2527}
2528
2529/* Set the hardware MAC address. */
2530static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2531{
2532 struct sockaddr *addr = p;
2533
2534 /* Setting the MAC address at the hardware level is not possible
2535 * without disabling the UniMAC RX/TX enable bits.
2536 */
2537 if (netif_running(dev))
2538 return -EBUSY;
2539
2540 ether_addr_copy(dev->dev_addr, addr->sa_data);
2541
2542 return 0;
2543}
2544
1c1008c7
FF		 2545static const struct net_device_ops bcmgenet_netdev_ops = {
2546 .ndo_open = bcmgenet_open,
2547 .ndo_stop = bcmgenet_close,
2548 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2549 .ndo_tx_timeout = bcmgenet_timeout,
2550 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2551 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2552 .ndo_do_ioctl = bcmgenet_ioctl,
2553 .ndo_set_features = bcmgenet_set_features,
2554};
2555
2556/* Array of GENET hardware parameters/characteristics */
2557static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2558 [GENET_V1] = {
2559 .tx_queues = 0,
51a966a7 2560 .tx_bds_per_q = 0,
1c1008c7 2561 .rx_queues = 0,
3feafa02 2562 .rx_bds_per_q = 0,
1c1008c7
FF		 2563 .bp_in_en_shift = 16,
2564 .bp_in_mask = 0xffff,
2565 .hfb_filter_cnt = 16,
2566 .qtag_mask = 0x1F,
2567 .hfb_offset = 0x1000,
2568 .rdma_offset = 0x2000,
2569 .tdma_offset = 0x3000,
2570 .words_per_bd = 2,
2571 },
2572 [GENET_V2] = {
2573 .tx_queues = 4,
51a966a7 2574 .tx_bds_per_q = 32,
7e906e02 2575 .rx_queues = 0,
3feafa02 2576 .rx_bds_per_q = 0,
1c1008c7
FF		 2577 .bp_in_en_shift = 16,
2578 .bp_in_mask = 0xffff,
2579 .hfb_filter_cnt = 16,
2580 .qtag_mask = 0x1F,
2581 .tbuf_offset = 0x0600,
2582 .hfb_offset = 0x1000,
2583 .hfb_reg_offset = 0x2000,
2584 .rdma_offset = 0x3000,
2585 .tdma_offset = 0x4000,
2586 .words_per_bd = 2,
2587 .flags = GENET_HAS_EXT,
2588 },
2589 [GENET_V3] = {
2590 .tx_queues = 4,
51a966a7 2591 .tx_bds_per_q = 32,
7e906e02 2592 .rx_queues = 0,
3feafa02 2593 .rx_bds_per_q = 0,
1c1008c7
FF		 2594 .bp_in_en_shift = 17,
2595 .bp_in_mask = 0x1ffff,
2596 .hfb_filter_cnt = 48,
2597 .qtag_mask = 0x3F,
2598 .tbuf_offset = 0x0600,
2599 .hfb_offset = 0x8000,
2600 .hfb_reg_offset = 0xfc00,
2601 .rdma_offset = 0x10000,
2602 .tdma_offset = 0x11000,
2603 .words_per_bd = 2,
2604 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2605 },
2606 [GENET_V4] = {
2607 .tx_queues = 4,
51a966a7 2608 .tx_bds_per_q = 32,
7e906e02 2609 .rx_queues = 0,
3feafa02 2610 .rx_bds_per_q = 0,
1c1008c7
FF		 2611 .bp_in_en_shift = 17,
2612 .bp_in_mask = 0x1ffff,
2613 .hfb_filter_cnt = 48,
2614 .qtag_mask = 0x3F,
2615 .tbuf_offset = 0x0600,
2616 .hfb_offset = 0x8000,
2617 .hfb_reg_offset = 0xfc00,
2618 .rdma_offset = 0x2000,
2619 .tdma_offset = 0x4000,
2620 .words_per_bd = 3,
2621 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2622 },
2623};
2624
2625/* Infer hardware parameters from the detected GENET version */
2626static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2627{
2628 struct bcmgenet_hw_params *params;
2629 u32 reg;
2630 u8 major;
b04a2f5b 2631 u16 gphy_rev;
1c1008c7
FF		 2632
2633 if (GENET_IS_V4(priv)) {
2634 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2635 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2636 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2637 priv->version = GENET_V4;
2638 } else if (GENET_IS_V3(priv)) {
2639 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2640 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2641 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2642 priv->version = GENET_V3;
2643 } else if (GENET_IS_V2(priv)) {
2644 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2645 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2646 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2647 priv->version = GENET_V2;
2648 } else if (GENET_IS_V1(priv)) {
2649 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2650 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2651 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2652 priv->version = GENET_V1;
2653 }
2654
2655 /* enum genet_version starts at 1 */
2656 priv->hw_params = &bcmgenet_hw_params[priv->version];
2657 params = priv->hw_params;
2658
2659 /* Read GENET HW version */
2660 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2661 major = (reg >> 24 & 0x0f);
2662 if (major == 5)
2663 major = 4;
2664 else if (major == 0)
2665 major = 1;
2666 if (major != priv->version) {
2667 dev_err(&priv->pdev->dev,
2668 "GENET version mismatch, got: %d, configured for: %d\n",
2669 major, priv->version);
2670 }
2671
2672 /* Print the GENET core version */
2673 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 2674 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 2675
487320c5
FF		 2676 /* Store the integrated PHY revision for the MDIO probing function
2677 * to pass this information to the PHY driver. The PHY driver expects
2678 * to find the PHY major revision in bits 15:8 while the GENET register
2679 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 2680 *
2681 * On newer chips, starting with PHY revision G0, a new scheme is
2682 * deployed similar to the Starfighter 2 switch with GPHY major
2683 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
2684 * is reserved as well as special value 0x01ff, we have a small
2685 * heuristic to check for the new GPHY revision and re-arrange things
2686 * so the GPHY driver is happy.
487320c5 2687 */
b04a2f5b
FF		 2688 gphy_rev = reg & 0xffff;
2689
2690 /* This is the good old scheme, just GPHY major, no minor nor patch */
2691 if ((gphy_rev & 0xf0) != 0)
2692 priv->gphy_rev = gphy_rev << 8;
2693
2694 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
2695 else if ((gphy_rev & 0xff00) != 0)
2696 priv->gphy_rev = gphy_rev;
2697
2698 /* This is reserved so should require special treatment */
2699 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
2700 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
2701 return;
2702 }
487320c5 2703
1c1008c7
FF		 2704#ifdef CONFIG_PHYS_ADDR_T_64BIT
2705 if (!(params->flags & GENET_HAS_40BITS))
2706 pr_warn("GENET does not support 40-bits PA\n");
2707#endif
2708
2709 pr_debug("Configuration for version: %d\n"
3feafa02 2710 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 2711 "BP << en: %2d, BP msk: 0x%05x\n"
2712 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2713 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2714 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2715 "Words/BD: %d\n",
2716 priv->version,
51a966a7 2717 params->tx_queues, params->tx_bds_per_q,
3feafa02 2718 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 2719 params->bp_in_en_shift, params->bp_in_mask,
2720 params->hfb_filter_cnt, params->qtag_mask,
2721 params->tbuf_offset, params->hfb_offset,
2722 params->hfb_reg_offset,
2723 params->rdma_offset, params->tdma_offset,
2724 params->words_per_bd);
2725}
2726
2727static const struct of_device_id bcmgenet_match[] = {
2728 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2729 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2730 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2731 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2732 { },
2733};
2734
2735static int bcmgenet_probe(struct platform_device *pdev)
2736{
b0ba512e 2737 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 2738 struct device_node *dn = pdev->dev.of_node;
b0ba512e 2739 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 2740 struct bcmgenet_priv *priv;
2741 struct net_device *dev;
2742 const void *macaddr;
2743 struct resource *r;
2744 int err = -EIO;
2745
3feafeed
PG		 2746 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
2747 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
2748 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 2749 if (!dev) {
2750 dev_err(&pdev->dev, "can't allocate net device\n");
2751 return -ENOMEM;
2752 }
2753
b0ba512e
PG		 2754 if (dn) {
2755 of_id = of_match_node(bcmgenet_match, dn);
2756 if (!of_id)
2757 return -EINVAL;
2758 }
1c1008c7
FF		 2759
2760 priv = netdev_priv(dev);
2761 priv->irq0 = platform_get_irq(pdev, 0);
2762 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2763 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2764 if (!priv->irq0 || !priv->irq1) {
2765 dev_err(&pdev->dev, "can't find IRQs\n");
2766 err = -EINVAL;
2767 goto err;
2768 }
2769
b0ba512e
PG		 2770 if (dn) {
2771 macaddr = of_get_mac_address(dn);
2772 if (!macaddr) {
2773 dev_err(&pdev->dev, "can't find MAC address\n");
2774 err = -EINVAL;
2775 goto err;
2776 }
2777 } else {
2778 macaddr = pd->mac_address;
1c1008c7
FF		 2779 }
2780
2781 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2782 priv->base = devm_ioremap_resource(&pdev->dev, r);
2783 if (IS_ERR(priv->base)) {
2784 err = PTR_ERR(priv->base);
1c1008c7
FF		 2785 goto err;
2786 }
2787
2788 SET_NETDEV_DEV(dev, &pdev->dev);
2789 dev_set_drvdata(&pdev->dev, dev);
2790 ether_addr_copy(dev->dev_addr, macaddr);
2791 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2792 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2793 dev->netdev_ops = &bcmgenet_netdev_ops;
2794 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2795
2796 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2797
2798 /* Set hardware features */
2799 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2800 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2801
8562056f
FF		 2802 /* Request the WOL interrupt and advertise suspend if available */
2803 priv->wol_irq_disabled = true;
2804 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2805 dev->name, priv);
2806 if (!err)
2807 device_set_wakeup_capable(&pdev->dev, 1);
2808
1c1008c7
FF		 2809 /* Set the needed headroom to account for any possible
2810 * features enabling/disabling at runtime
2811 */
2812 dev->needed_headroom += 64;
2813
2814 netdev_boot_setup_check(dev);
2815
2816 priv->dev = dev;
2817 priv->pdev = pdev;
b0ba512e
PG		 2818 if (of_id)
2819 priv->version = (enum bcmgenet_version)of_id->data;
2820 else
2821 priv->version = pd->genet_version;
1c1008c7 2822
e4a60a93
FF		 2823 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2824 if (IS_ERR(priv->clk))
2825 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2826
2827 if (!IS_ERR(priv->clk))
2828 clk_prepare_enable(priv->clk);
2829
1c1008c7
FF		 2830 bcmgenet_set_hw_params(priv);
2831
1c1008c7
FF		 2832 /* Mii wait queue */
2833 init_waitqueue_head(&priv->wq);
2834 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2835 priv->rx_buf_len = RX_BUF_LENGTH;
2836 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2837
1c1008c7
FF		 2838 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2839 if (IS_ERR(priv->clk_wol))
2840 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2841
6ef398ea
FF		 2842 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
2843 if (IS_ERR(priv->clk_eee)) {
2844 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
2845 priv->clk_eee = NULL;
2846 }
2847
1c1008c7
FF		 2848 err = reset_umac(priv);
2849 if (err)
2850 goto err_clk_disable;
2851
2852 err = bcmgenet_mii_init(dev);
2853 if (err)
2854 goto err_clk_disable;
2855
2856 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2857 * just the ring 16 descriptor based TX
2858 */
2859 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2860 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2861
219575eb
FF		 2862 /* libphy will determine the link state */
2863 netif_carrier_off(dev);
2864
1c1008c7
FF		 2865 /* Turn off the main clock, WOL clock is handled separately */
2866 if (!IS_ERR(priv->clk))
2867 clk_disable_unprepare(priv->clk);
2868
0f50ce96
FF		 2869 err = register_netdev(dev);
2870 if (err)
2871 goto err;
2872
1c1008c7
FF		 2873 return err;
2874
2875err_clk_disable:
2876 if (!IS_ERR(priv->clk))
2877 clk_disable_unprepare(priv->clk);
2878err:
2879 free_netdev(dev);
2880 return err;
2881}
2882
2883static int bcmgenet_remove(struct platform_device *pdev)
2884{
2885 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2886
2887 dev_set_drvdata(&pdev->dev, NULL);
2888 unregister_netdev(priv->dev);
2889 bcmgenet_mii_exit(priv->dev);
2890 free_netdev(priv->dev);
2891
2892 return 0;
2893}
2894
b6e978e5
FF		 2895#ifdef CONFIG_PM_SLEEP
2896static int bcmgenet_suspend(struct device *d)
2897{
2898 struct net_device *dev = dev_get_drvdata(d);
2899 struct bcmgenet_priv *priv = netdev_priv(dev);
2900 int ret;
2901
2902 if (!netif_running(dev))
2903 return 0;
2904
2905 bcmgenet_netif_stop(dev);
2906
cc013fb4
FF		 2907 phy_suspend(priv->phydev);
2908
b6e978e5
FF		 2909 netif_device_detach(dev);
2910
2911 /* Disable MAC receive */
2912 umac_enable_set(priv, CMD_RX_EN, false);
2913
2914 ret = bcmgenet_dma_teardown(priv);
2915 if (ret)
2916 return ret;
2917
2918 /* Disable MAC transmit. TX DMA disabled have to done before this */
2919 umac_enable_set(priv, CMD_TX_EN, false);
2920
2921 /* tx reclaim */
2922 bcmgenet_tx_reclaim_all(dev);
2923 bcmgenet_fini_dma(priv);
2924
8c90db72
FF		 2925 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2926 if (device_may_wakeup(d) && priv->wolopts) {
2927 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2928 clk_prepare_enable(priv->clk_wol);
2929 }
2930
b6e978e5
FF		 2931 /* Turn off the clocks */
2932 clk_disable_unprepare(priv->clk);
2933
2934 return 0;
2935}
2936
2937static int bcmgenet_resume(struct device *d)
2938{
2939 struct net_device *dev = dev_get_drvdata(d);
2940 struct bcmgenet_priv *priv = netdev_priv(dev);
2941 unsigned long dma_ctrl;
2942 int ret;
2943 u32 reg;
2944
2945 if (!netif_running(dev))
2946 return 0;
2947
2948 /* Turn on the clock */
2949 ret = clk_prepare_enable(priv->clk);
2950 if (ret)
2951 return ret;
2952
2953 bcmgenet_umac_reset(priv);
2954
2955 ret = init_umac(priv);
2956 if (ret)
2957 goto out_clk_disable;
2958
0a29b3da
TK		 2959 /* From WOL-enabled suspend, switch to regular clock */
2960 if (priv->wolopts)
2961 clk_disable_unprepare(priv->clk_wol);
2962
2963 phy_init_hw(priv->phydev);
2964 /* Speed settings must be restored */
dbd479db 2965 bcmgenet_mii_config(priv->dev, false);
8c90db72 2966
b6e978e5
FF		 2967 /* disable ethernet MAC while updating its registers */
2968 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2969
2970 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2971
2972 if (phy_is_internal(priv->phydev)) {
2973 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2974 reg |= EXT_ENERGY_DET_MASK;
2975 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2976 }
2977
98bb7399
FF		 2978 if (priv->wolopts)
2979 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2980
b6e978e5
FF		 2981 /* Disable RX/TX DMA and flush TX queues */
2982 dma_ctrl = bcmgenet_dma_disable(priv);
2983
2984 /* Reinitialize TDMA and RDMA and SW housekeeping */
2985 ret = bcmgenet_init_dma(priv);
2986 if (ret) {
2987 netdev_err(dev, "failed to initialize DMA\n");
2988 goto out_clk_disable;
2989 }
2990
2991 /* Always enable ring 16 - descriptor ring */
2992 bcmgenet_enable_dma(priv, dma_ctrl);
2993
2994 netif_device_attach(dev);
2995
cc013fb4
FF		 2996 phy_resume(priv->phydev);
2997
6ef398ea
FF		 2998 if (priv->eee.eee_enabled)
2999 bcmgenet_eee_enable_set(dev, true);
3000
b6e978e5
FF		 3001 bcmgenet_netif_start(dev);
3002
3003 return 0;
3004
3005out_clk_disable:
3006 clk_disable_unprepare(priv->clk);
3007 return ret;
3008}
3009#endif /* CONFIG_PM_SLEEP */
3010
3011static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3012
1c1008c7
FF		 3013static struct platform_driver bcmgenet_driver = {
3014 .probe = bcmgenet_probe,
3015 .remove = bcmgenet_remove,
3016 .driver = {
3017 .name = "bcmgenet",
1c1008c7 3018 .of_match_table = bcmgenet_match,
b6e978e5 3019 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 3020 },
3021};
3022module_platform_driver(bcmgenet_driver);
3023
3024MODULE_AUTHOR("Broadcom Corporation");
3025MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3026MODULE_ALIAS("platform:bcmgenet");
3027MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)