projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: bcmgenet: remove FSF mail address
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
45
46#include <asm/unaligned.h>
47
48#include "bcmgenet.h"
49
50/* Maximum number of hardware queues, downsized if needed */
51#define GENET_MAX_MQ_CNT 4
52
53/* Default highest priority queue for multi queue support */
54#define GENET_Q0_PRIORITY 0
55
56#define GENET_DEFAULT_BD_CNT \
57 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
58
59#define RX_BUF_LENGTH 2048
60#define SKB_ALIGNMENT 32
61
62/* Tx/Rx DMA register offset, skip 256 descriptors */
63#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
64#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
65
66#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
67 TOTAL_DESC * DMA_DESC_SIZE)
68
69#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
73 void __iomem *d, u32 value)
74{
75 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
76}
77
78static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
79 void __iomem *d)
80{
81 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
82}
83
84static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
85 void __iomem *d,
86 dma_addr_t addr)
87{
88 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
89
90 /* Register writes to GISB bus can take couple hundred nanoseconds
91 * and are done for each packet, save these expensive writes unless
92 * the platform is explicitely configured for 64-bits/LPAE.
93 */
94#ifdef CONFIG_PHYS_ADDR_T_64BIT
95 if (priv->hw_params->flags & GENET_HAS_40BITS)
96 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
97#endif
98}
99
100/* Combined address + length/status setter */
101static inline void dmadesc_set(struct bcmgenet_priv *priv,
102 void __iomem *d, dma_addr_t addr, u32 val)
103{
104 dmadesc_set_length_status(priv, d, val);
105 dmadesc_set_addr(priv, d, addr);
106}
107
108static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
109 void __iomem *d)
110{
111 dma_addr_t addr;
112
113 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
114
115 /* Register writes to GISB bus can take couple hundred nanoseconds
116 * and are done for each packet, save these expensive writes unless
117 * the platform is explicitely configured for 64-bits/LPAE.
118 */
119#ifdef CONFIG_PHYS_ADDR_T_64BIT
120 if (priv->hw_params->flags & GENET_HAS_40BITS)
121 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
122#endif
123 return addr;
124}
125
126#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
127
128#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
129 NETIF_MSG_LINK)
130
131static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
132{
133 if (GENET_IS_V1(priv))
134 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
135 else
136 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
137}
138
139static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
140{
141 if (GENET_IS_V1(priv))
142 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
143 else
144 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
145}
146
147/* These macros are defined to deal with register map change
148 * between GENET1.1 and GENET2. Only those currently being used
149 * by driver are defined.
150 */
151static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
152{
153 if (GENET_IS_V1(priv))
154 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
155 else
156 return __raw_readl(priv->base +
157 priv->hw_params->tbuf_offset + TBUF_CTRL);
158}
159
160static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
161{
162 if (GENET_IS_V1(priv))
163 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
164 else
165 __raw_writel(val, priv->base +
166 priv->hw_params->tbuf_offset + TBUF_CTRL);
167}
168
169static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
170{
171 if (GENET_IS_V1(priv))
172 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
173 else
174 return __raw_readl(priv->base +
175 priv->hw_params->tbuf_offset + TBUF_BP_MC);
176}
177
178static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
179{
180 if (GENET_IS_V1(priv))
181 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
182 else
183 __raw_writel(val, priv->base +
184 priv->hw_params->tbuf_offset + TBUF_BP_MC);
185}
186
187/* RX/TX DMA register accessors */
188enum dma_reg {
189 DMA_RING_CFG = 0,
190 DMA_CTRL,
191 DMA_STATUS,
192 DMA_SCB_BURST_SIZE,
193 DMA_ARB_CTRL,
194 DMA_PRIORITY,
195 DMA_RING_PRIORITY,
196};
197
198static const u8 bcmgenet_dma_regs_v3plus[] = {
199 [DMA_RING_CFG] = 0x00,
200 [DMA_CTRL] = 0x04,
201 [DMA_STATUS] = 0x08,
202 [DMA_SCB_BURST_SIZE] = 0x0C,
203 [DMA_ARB_CTRL] = 0x2C,
204 [DMA_PRIORITY] = 0x30,
205 [DMA_RING_PRIORITY] = 0x38,
206};
207
208static const u8 bcmgenet_dma_regs_v2[] = {
209 [DMA_RING_CFG] = 0x00,
210 [DMA_CTRL] = 0x04,
211 [DMA_STATUS] = 0x08,
212 [DMA_SCB_BURST_SIZE] = 0x0C,
213 [DMA_ARB_CTRL] = 0x30,
214 [DMA_PRIORITY] = 0x34,
215 [DMA_RING_PRIORITY] = 0x3C,
216};
217
218static const u8 bcmgenet_dma_regs_v1[] = {
219 [DMA_CTRL] = 0x00,
220 [DMA_STATUS] = 0x04,
221 [DMA_SCB_BURST_SIZE] = 0x0C,
222 [DMA_ARB_CTRL] = 0x30,
223 [DMA_PRIORITY] = 0x34,
224 [DMA_RING_PRIORITY] = 0x3C,
225};
226
227/* Set at runtime once bcmgenet version is known */
228static const u8 *bcmgenet_dma_regs;
229
230static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
231{
232 return netdev_priv(dev_get_drvdata(dev));
233}
234
235static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
236 enum dma_reg r)
237{
238 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
239 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
240}
241
242static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
243 u32 val, enum dma_reg r)
244{
245 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
246 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
247}
248
249static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
250 enum dma_reg r)
251{
252 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
253 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
254}
255
256static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
257 u32 val, enum dma_reg r)
258{
259 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
260 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
261}
262
263/* RDMA/TDMA ring registers and accessors
264 * we merge the common fields and just prefix with T/D the registers
265 * having different meaning depending on the direction
266 */
267enum dma_ring_reg {
268 TDMA_READ_PTR = 0,
269 RDMA_WRITE_PTR = TDMA_READ_PTR,
270 TDMA_READ_PTR_HI,
271 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
272 TDMA_CONS_INDEX,
273 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
274 TDMA_PROD_INDEX,
275 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
276 DMA_RING_BUF_SIZE,
277 DMA_START_ADDR,
278 DMA_START_ADDR_HI,
279 DMA_END_ADDR,
280 DMA_END_ADDR_HI,
281 DMA_MBUF_DONE_THRESH,
282 TDMA_FLOW_PERIOD,
283 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
284 TDMA_WRITE_PTR,
285 RDMA_READ_PTR = TDMA_WRITE_PTR,
286 TDMA_WRITE_PTR_HI,
287 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
288};
289
290/* GENET v4 supports 40-bits pointer addressing
291 * for obvious reasons the LO and HI word parts
292 * are contiguous, but this offsets the other
293 * registers.
294 */
295static const u8 genet_dma_ring_regs_v4[] = {
296 [TDMA_READ_PTR] = 0x00,
297 [TDMA_READ_PTR_HI] = 0x04,
298 [TDMA_CONS_INDEX] = 0x08,
299 [TDMA_PROD_INDEX] = 0x0C,
300 [DMA_RING_BUF_SIZE] = 0x10,
301 [DMA_START_ADDR] = 0x14,
302 [DMA_START_ADDR_HI] = 0x18,
303 [DMA_END_ADDR] = 0x1C,
304 [DMA_END_ADDR_HI] = 0x20,
305 [DMA_MBUF_DONE_THRESH] = 0x24,
306 [TDMA_FLOW_PERIOD] = 0x28,
307 [TDMA_WRITE_PTR] = 0x2C,
308 [TDMA_WRITE_PTR_HI] = 0x30,
309};
310
311static const u8 genet_dma_ring_regs_v123[] = {
312 [TDMA_READ_PTR] = 0x00,
313 [TDMA_CONS_INDEX] = 0x04,
314 [TDMA_PROD_INDEX] = 0x08,
315 [DMA_RING_BUF_SIZE] = 0x0C,
316 [DMA_START_ADDR] = 0x10,
317 [DMA_END_ADDR] = 0x14,
318 [DMA_MBUF_DONE_THRESH] = 0x18,
319 [TDMA_FLOW_PERIOD] = 0x1C,
320 [TDMA_WRITE_PTR] = 0x20,
321};
322
323/* Set at runtime once GENET version is known */
324static const u8 *genet_dma_ring_regs;
325
326static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
327 unsigned int ring,
328 enum dma_ring_reg r)
329{
330 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
331 (DMA_RING_SIZE * ring) +
332 genet_dma_ring_regs[r]);
333}
334
335static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
336 unsigned int ring,
337 u32 val,
338 enum dma_ring_reg r)
339{
340 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
341 (DMA_RING_SIZE * ring) +
342 genet_dma_ring_regs[r]);
343}
344
345static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
346 unsigned int ring,
347 enum dma_ring_reg r)
348{
349 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
350 (DMA_RING_SIZE * ring) +
351 genet_dma_ring_regs[r]);
352}
353
354static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
355 unsigned int ring,
356 u32 val,
357 enum dma_ring_reg r)
358{
359 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
360 (DMA_RING_SIZE * ring) +
361 genet_dma_ring_regs[r]);
362}
363
364static int bcmgenet_get_settings(struct net_device *dev,
365 struct ethtool_cmd *cmd)
366{
367 struct bcmgenet_priv *priv = netdev_priv(dev);
368
369 if (!netif_running(dev))
370 return -EINVAL;
371
372 if (!priv->phydev)
373 return -ENODEV;
374
375 return phy_ethtool_gset(priv->phydev, cmd);
376}
377
378static int bcmgenet_set_settings(struct net_device *dev,
379 struct ethtool_cmd *cmd)
380{
381 struct bcmgenet_priv *priv = netdev_priv(dev);
382
383 if (!netif_running(dev))
384 return -EINVAL;
385
386 if (!priv->phydev)
387 return -ENODEV;
388
389 return phy_ethtool_sset(priv->phydev, cmd);
390}
391
392static int bcmgenet_set_rx_csum(struct net_device *dev,
393 netdev_features_t wanted)
394{
395 struct bcmgenet_priv *priv = netdev_priv(dev);
396 u32 rbuf_chk_ctrl;
397 bool rx_csum_en;
398
399 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
400
401 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
402
403 /* enable rx checksumming */
404 if (rx_csum_en)
405 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
406 else
407 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
408 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 409
410 /* If UniMAC forwards CRC, we need to skip over it to get
411 * a valid CHK bit to be set in the per-packet status word
412 */
413 if (rx_csum_en && priv->crc_fwd_en)
414 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
415 else
416 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
417
1c1008c7
FF		 418 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
419
420 return 0;
421}
422
423static int bcmgenet_set_tx_csum(struct net_device *dev,
424 netdev_features_t wanted)
425{
426 struct bcmgenet_priv *priv = netdev_priv(dev);
427 bool desc_64b_en;
428 u32 tbuf_ctrl, rbuf_ctrl;
429
430 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
431 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
432
433 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
434
435 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
436 if (desc_64b_en) {
437 tbuf_ctrl |= RBUF_64B_EN;
438 rbuf_ctrl |= RBUF_64B_EN;
439 } else {
440 tbuf_ctrl &= ~RBUF_64B_EN;
441 rbuf_ctrl &= ~RBUF_64B_EN;
442 }
443 priv->desc_64b_en = desc_64b_en;
444
445 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
446 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
447
448 return 0;
449}
450
451static int bcmgenet_set_features(struct net_device *dev,
452 netdev_features_t features)
453{
454 netdev_features_t changed = features ^ dev->features;
455 netdev_features_t wanted = dev->wanted_features;
456 int ret = 0;
457
458 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
459 ret = bcmgenet_set_tx_csum(dev, wanted);
460 if (changed & (NETIF_F_RXCSUM))
461 ret = bcmgenet_set_rx_csum(dev, wanted);
462
463 return ret;
464}
465
466static u32 bcmgenet_get_msglevel(struct net_device *dev)
467{
468 struct bcmgenet_priv *priv = netdev_priv(dev);
469
470 return priv->msg_enable;
471}
472
473static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
474{
475 struct bcmgenet_priv *priv = netdev_priv(dev);
476
477 priv->msg_enable = level;
478}
479
480/* standard ethtool support functions. */
481enum bcmgenet_stat_type {
482 BCMGENET_STAT_NETDEV = -1,
483 BCMGENET_STAT_MIB_RX,
484 BCMGENET_STAT_MIB_TX,
485 BCMGENET_STAT_RUNT,
486 BCMGENET_STAT_MISC,
487};
488
489struct bcmgenet_stats {
490 char stat_string[ETH_GSTRING_LEN];
491 int stat_sizeof;
492 int stat_offset;
493 enum bcmgenet_stat_type type;
494 /* reg offset from UMAC base for misc counters */
495 u16 reg_offset;
496};
497
498#define STAT_NETDEV(m) { \
499 .stat_string = __stringify(m), \
500 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
501 .stat_offset = offsetof(struct net_device_stats, m), \
502 .type = BCMGENET_STAT_NETDEV, \
503}
504
505#define STAT_GENET_MIB(str, m, _type) { \
506 .stat_string = str, \
507 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
508 .stat_offset = offsetof(struct bcmgenet_priv, m), \
509 .type = _type, \
510}
511
512#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
513#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
514#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
515
516#define STAT_GENET_MISC(str, m, offset) { \
517 .stat_string = str, \
518 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
519 .stat_offset = offsetof(struct bcmgenet_priv, m), \
520 .type = BCMGENET_STAT_MISC, \
521 .reg_offset = offset, \
522}
523
524
525/* There is a 0xC gap between the end of RX and beginning of TX stats and then
526 * between the end of TX stats and the beginning of the RX RUNT
527 */
528#define BCMGENET_STAT_OFFSET 0xc
529
530/* Hardware counters must be kept in sync because the order/offset
531 * is important here (order in structure declaration = order in hardware)
532 */
533static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
534 /* general stats */
535 STAT_NETDEV(rx_packets),
536 STAT_NETDEV(tx_packets),
537 STAT_NETDEV(rx_bytes),
538 STAT_NETDEV(tx_bytes),
539 STAT_NETDEV(rx_errors),
540 STAT_NETDEV(tx_errors),
541 STAT_NETDEV(rx_dropped),
542 STAT_NETDEV(tx_dropped),
543 STAT_NETDEV(multicast),
544 /* UniMAC RSV counters */
545 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
546 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
547 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
548 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
549 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
550 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
551 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
552 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
553 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
554 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
555 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
556 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
557 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
558 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
559 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
560 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
561 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
562 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
563 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
564 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
565 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
566 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
567 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
568 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
569 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
570 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
571 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
572 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
573 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
574 /* UniMAC TSV counters */
575 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
576 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
577 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
578 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
579 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
580 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
581 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
582 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
583 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
584 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
585 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
586 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
587 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
588 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
589 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
590 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
591 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
592 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
593 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
594 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
595 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
596 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
597 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
598 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
599 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
600 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
601 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
602 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
603 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
604 /* UniMAC RUNT counters */
605 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
606 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
607 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
608 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
609 /* Misc UniMAC counters */
610 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
611 UMAC_RBUF_OVFL_CNT),
612 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
613 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
614};
615
616#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
617
618static void bcmgenet_get_drvinfo(struct net_device *dev,
619 struct ethtool_drvinfo *info)
620{
621 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
622 strlcpy(info->version, "v2.0", sizeof(info->version));
623 info->n_stats = BCMGENET_STATS_LEN;
624
625}
626
627static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
628{
629 switch (string_set) {
630 case ETH_SS_STATS:
631 return BCMGENET_STATS_LEN;
632 default:
633 return -EOPNOTSUPP;
634 }
635}
636
637static void bcmgenet_get_strings(struct net_device *dev,
638 u32 stringset, u8 *data)
639{
640 int i;
641
642 switch (stringset) {
643 case ETH_SS_STATS:
644 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
645 memcpy(data + i * ETH_GSTRING_LEN,
646 bcmgenet_gstrings_stats[i].stat_string,
647 ETH_GSTRING_LEN);
648 }
649 break;
650 }
651}
652
653static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
654{
655 int i, j = 0;
656
657 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
658 const struct bcmgenet_stats *s;
659 u8 offset = 0;
660 u32 val = 0;
661 char *p;
662
663 s = &bcmgenet_gstrings_stats[i];
664 switch (s->type) {
665 case BCMGENET_STAT_NETDEV:
666 continue;
667 case BCMGENET_STAT_MIB_RX:
668 case BCMGENET_STAT_MIB_TX:
669 case BCMGENET_STAT_RUNT:
670 if (s->type != BCMGENET_STAT_MIB_RX)
671 offset = BCMGENET_STAT_OFFSET;
672 val = bcmgenet_umac_readl(priv, UMAC_MIB_START +
673 j + offset);
674 break;
675 case BCMGENET_STAT_MISC:
676 val = bcmgenet_umac_readl(priv, s->reg_offset);
677 /* clear if overflowed */
678 if (val == ~0)
679 bcmgenet_umac_writel(priv, 0, s->reg_offset);
680 break;
681 }
682
683 j += s->stat_sizeof;
684 p = (char *)priv + s->stat_offset;
685 *(u32 *)p = val;
686 }
687}
688
689static void bcmgenet_get_ethtool_stats(struct net_device *dev,
690 struct ethtool_stats *stats,
691 u64 *data)
692{
693 struct bcmgenet_priv *priv = netdev_priv(dev);
694 int i;
695
696 if (netif_running(dev))
697 bcmgenet_update_mib_counters(priv);
698
699 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
700 const struct bcmgenet_stats *s;
701 char *p;
702
703 s = &bcmgenet_gstrings_stats[i];
704 if (s->type == BCMGENET_STAT_NETDEV)
705 p = (char *)&dev->stats;
706 else
707 p = (char *)priv;
708 p += s->stat_offset;
709 data[i] = *(u32 *)p;
710 }
711}
712
713/* standard ethtool support functions. */
714static struct ethtool_ops bcmgenet_ethtool_ops = {
715 .get_strings = bcmgenet_get_strings,
716 .get_sset_count = bcmgenet_get_sset_count,
717 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
718 .get_settings = bcmgenet_get_settings,
719 .set_settings = bcmgenet_set_settings,
720 .get_drvinfo = bcmgenet_get_drvinfo,
721 .get_link = ethtool_op_get_link,
722 .get_msglevel = bcmgenet_get_msglevel,
723 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 724 .get_wol = bcmgenet_get_wol,
725 .set_wol = bcmgenet_set_wol,
1c1008c7
FF		 726};
727
728/* Power down the unimac, based on mode. */
729static void bcmgenet_power_down(struct bcmgenet_priv *priv,
730 enum bcmgenet_power_mode mode)
731{
732 u32 reg;
733
734 switch (mode) {
735 case GENET_POWER_CABLE_SENSE:
80d8e96d 736 phy_detach(priv->phydev);
1c1008c7
FF		 737 break;
738
c3ae64ae
FF		 739 case GENET_POWER_WOL_MAGIC:
740 bcmgenet_wol_power_down_cfg(priv, mode);
741 break;
742
1c1008c7
FF		 743 case GENET_POWER_PASSIVE:
744 /* Power down LED */
745 bcmgenet_mii_reset(priv->dev);
746 if (priv->hw_params->flags & GENET_HAS_EXT) {
747 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
748 reg |= (EXT_PWR_DOWN_PHY |
749 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
750 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
751 }
752 break;
753 default:
754 break;
755 }
756}
757
758static void bcmgenet_power_up(struct bcmgenet_priv *priv,
759 enum bcmgenet_power_mode mode)
760{
761 u32 reg;
762
763 if (!(priv->hw_params->flags & GENET_HAS_EXT))
764 return;
765
766 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
767
768 switch (mode) {
769 case GENET_POWER_PASSIVE:
770 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
771 EXT_PWR_DOWN_BIAS);
772 /* fallthrough */
773 case GENET_POWER_CABLE_SENSE:
774 /* enable APD */
775 reg |= EXT_PWR_DN_EN_LD;
776 break;
c3ae64ae
FF		 777 case GENET_POWER_WOL_MAGIC:
778 bcmgenet_wol_power_up_cfg(priv, mode);
779 return;
1c1008c7
FF		 780 default:
781 break;
782 }
783
784 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
785 bcmgenet_mii_reset(priv->dev);
786}
787
788/* ioctl handle special commands that are not present in ethtool. */
789static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
790{
791 struct bcmgenet_priv *priv = netdev_priv(dev);
792 int val = 0;
793
794 if (!netif_running(dev))
795 return -EINVAL;
796
797 switch (cmd) {
798 case SIOCGMIIPHY:
799 case SIOCGMIIREG:
800 case SIOCSMIIREG:
801 if (!priv->phydev)
802 val = -ENODEV;
803 else
804 val = phy_mii_ioctl(priv->phydev, rq, cmd);
805 break;
806
807 default:
808 val = -EINVAL;
809 break;
810 }
811
812 return val;
813}
814
815static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
816 struct bcmgenet_tx_ring *ring)
817{
818 struct enet_cb *tx_cb_ptr;
819
820 tx_cb_ptr = ring->cbs;
821 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
822 tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
823 /* Advancing local write pointer */
824 if (ring->write_ptr == ring->end_ptr)
825 ring->write_ptr = ring->cb_ptr;
826 else
827 ring->write_ptr++;
828
829 return tx_cb_ptr;
830}
831
832/* Simple helper to free a control block's resources */
833static void bcmgenet_free_cb(struct enet_cb *cb)
834{
835 dev_kfree_skb_any(cb->skb);
836 cb->skb = NULL;
837 dma_unmap_addr_set(cb, dma_addr, 0);
838}
839
840static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
841 struct bcmgenet_tx_ring *ring)
842{
843 bcmgenet_intrl2_0_writel(priv,
844 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
845 INTRL2_CPU_MASK_SET);
846}
847
848static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
849 struct bcmgenet_tx_ring *ring)
850{
851 bcmgenet_intrl2_0_writel(priv,
852 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
853 INTRL2_CPU_MASK_CLEAR);
854}
855
856static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
857 struct bcmgenet_tx_ring *ring)
858{
859 bcmgenet_intrl2_1_writel(priv,
860 (1 << ring->index), INTRL2_CPU_MASK_CLEAR);
861 priv->int1_mask &= ~(1 << ring->index);
862}
863
864static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
865 struct bcmgenet_tx_ring *ring)
866{
867 bcmgenet_intrl2_1_writel(priv,
868 (1 << ring->index), INTRL2_CPU_MASK_SET);
869 priv->int1_mask |= (1 << ring->index);
870}
871
872/* Unlocked version of the reclaim routine */
873static void __bcmgenet_tx_reclaim(struct net_device *dev,
874 struct bcmgenet_tx_ring *ring)
875{
876 struct bcmgenet_priv *priv = netdev_priv(dev);
877 int last_tx_cn, last_c_index, num_tx_bds;
878 struct enet_cb *tx_cb_ptr;
b2cde2cc 879 struct netdev_queue *txq;
1c1008c7
FF		 880 unsigned int c_index;
881
882 /* Compute how many buffers are transmited since last xmit call */
883 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
b2cde2cc 884 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 885
886 last_c_index = ring->c_index;
887 num_tx_bds = ring->size;
888
889 c_index &= (num_tx_bds - 1);
890
891 if (c_index >= last_c_index)
892 last_tx_cn = c_index - last_c_index;
893 else
894 last_tx_cn = num_tx_bds - last_c_index + c_index;
895
896 netif_dbg(priv, tx_done, dev,
897 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
898 __func__, ring->index,
899 c_index, last_tx_cn, last_c_index);
900
901 /* Reclaim transmitted buffers */
902 while (last_tx_cn-- > 0) {
903 tx_cb_ptr = ring->cbs + last_c_index;
904 if (tx_cb_ptr->skb) {
905 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
906 dma_unmap_single(&dev->dev,
907 dma_unmap_addr(tx_cb_ptr, dma_addr),
908 tx_cb_ptr->skb->len,
909 DMA_TO_DEVICE);
910 bcmgenet_free_cb(tx_cb_ptr);
911 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
912 dev->stats.tx_bytes +=
913 dma_unmap_len(tx_cb_ptr, dma_len);
914 dma_unmap_page(&dev->dev,
915 dma_unmap_addr(tx_cb_ptr, dma_addr),
916 dma_unmap_len(tx_cb_ptr, dma_len),
917 DMA_TO_DEVICE);
918 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
919 }
920 dev->stats.tx_packets++;
921 ring->free_bds += 1;
922
923 last_c_index++;
924 last_c_index &= (num_tx_bds - 1);
925 }
926
927 if (ring->free_bds > (MAX_SKB_FRAGS + 1))
928 ring->int_disable(priv, ring);
929
b2cde2cc
FF		 930 if (netif_tx_queue_stopped(txq))
931 netif_tx_wake_queue(txq);
1c1008c7
FF		 932
933 ring->c_index = c_index;
934}
935
936static void bcmgenet_tx_reclaim(struct net_device *dev,
937 struct bcmgenet_tx_ring *ring)
938{
939 unsigned long flags;
940
941 spin_lock_irqsave(&ring->lock, flags);
942 __bcmgenet_tx_reclaim(dev, ring);
943 spin_unlock_irqrestore(&ring->lock, flags);
944}
945
946static void bcmgenet_tx_reclaim_all(struct net_device *dev)
947{
948 struct bcmgenet_priv *priv = netdev_priv(dev);
949 int i;
950
951 if (netif_is_multiqueue(dev)) {
952 for (i = 0; i < priv->hw_params->tx_queues; i++)
953 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
954 }
955
956 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
957}
958
959/* Transmits a single SKB (either head of a fragment or a single SKB)
960 * caller must hold priv->lock
961 */
962static int bcmgenet_xmit_single(struct net_device *dev,
963 struct sk_buff *skb,
964 u16 dma_desc_flags,
965 struct bcmgenet_tx_ring *ring)
966{
967 struct bcmgenet_priv *priv = netdev_priv(dev);
968 struct device *kdev = &priv->pdev->dev;
969 struct enet_cb *tx_cb_ptr;
970 unsigned int skb_len;
971 dma_addr_t mapping;
972 u32 length_status;
973 int ret;
974
975 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
976
977 if (unlikely(!tx_cb_ptr))
978 BUG();
979
980 tx_cb_ptr->skb = skb;
981
982 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
983
984 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
985 ret = dma_mapping_error(kdev, mapping);
986 if (ret) {
987 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
988 dev_kfree_skb(skb);
989 return ret;
990 }
991
992 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
993 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
994 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
995 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
996 DMA_TX_APPEND_CRC;
997
998 if (skb->ip_summed == CHECKSUM_PARTIAL)
999 length_status |= DMA_TX_DO_CSUM;
1000
1001 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1002
1003 /* Decrement total BD count and advance our write pointer */
1004 ring->free_bds -= 1;
1005 ring->prod_index += 1;
1006 ring->prod_index &= DMA_P_INDEX_MASK;
1007
1008 return 0;
1009}
1010
1011/* Transmit a SKB fragement */
1012static int bcmgenet_xmit_frag(struct net_device *dev,
1013 skb_frag_t *frag,
1014 u16 dma_desc_flags,
1015 struct bcmgenet_tx_ring *ring)
1016{
1017 struct bcmgenet_priv *priv = netdev_priv(dev);
1018 struct device *kdev = &priv->pdev->dev;
1019 struct enet_cb *tx_cb_ptr;
1020 dma_addr_t mapping;
1021 int ret;
1022
1023 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1024
1025 if (unlikely(!tx_cb_ptr))
1026 BUG();
1027 tx_cb_ptr->skb = NULL;
1028
1029 mapping = skb_frag_dma_map(kdev, frag, 0,
1030 skb_frag_size(frag), DMA_TO_DEVICE);
1031 ret = dma_mapping_error(kdev, mapping);
1032 if (ret) {
1033 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1034 __func__);
1035 return ret;
1036 }
1037
1038 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1039 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1040
1041 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1042 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1043 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1044
1045
1046 ring->free_bds -= 1;
1047 ring->prod_index += 1;
1048 ring->prod_index &= DMA_P_INDEX_MASK;
1049
1050 return 0;
1051}
1052
1053/* Reallocate the SKB to put enough headroom in front of it and insert
1054 * the transmit checksum offsets in the descriptors
1055 */
1056static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb)
1057{
1058 struct status_64 *status = NULL;
1059 struct sk_buff *new_skb;
1060 u16 offset;
1061 u8 ip_proto;
1062 u16 ip_ver;
1063 u32 tx_csum_info;
1064
1065 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1066 /* If 64 byte status block enabled, must make sure skb has
1067 * enough headroom for us to insert 64B status block.
1068 */
1069 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1070 dev_kfree_skb(skb);
1071 if (!new_skb) {
1072 dev->stats.tx_errors++;
1073 dev->stats.tx_dropped++;
1074 return -ENOMEM;
1075 }
1076 skb = new_skb;
1077 }
1078
1079 skb_push(skb, sizeof(*status));
1080 status = (struct status_64 *)skb->data;
1081
1082 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1083 ip_ver = htons(skb->protocol);
1084 switch (ip_ver) {
1085 case ETH_P_IP:
1086 ip_proto = ip_hdr(skb)->protocol;
1087 break;
1088 case ETH_P_IPV6:
1089 ip_proto = ipv6_hdr(skb)->nexthdr;
1090 break;
1091 default:
1092 return 0;
1093 }
1094
1095 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1096 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1097 (offset + skb->csum_offset);
1098
1099 /* Set the length valid bit for TCP and UDP and just set
1100 * the special UDP flag for IPv4, else just set to 0.
1101 */
1102 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1103 tx_csum_info |= STATUS_TX_CSUM_LV;
1104 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1105 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1106 } else
1107 tx_csum_info = 0;
1108
1109 status->tx_csum_info = tx_csum_info;
1110 }
1111
1112 return 0;
1113}
1114
1115static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1116{
1117 struct bcmgenet_priv *priv = netdev_priv(dev);
1118 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1119 struct netdev_queue *txq;
1c1008c7
FF		 1120 unsigned long flags = 0;
1121 int nr_frags, index;
1122 u16 dma_desc_flags;
1123 int ret;
1124 int i;
1125
1126 index = skb_get_queue_mapping(skb);
1127 /* Mapping strategy:
1128 * queue_mapping = 0, unclassified, packet xmited through ring16
1129 * queue_mapping = 1, goes to ring 0. (highest priority queue
1130 * queue_mapping = 2, goes to ring 1.
1131 * queue_mapping = 3, goes to ring 2.
1132 * queue_mapping = 4, goes to ring 3.
1133 */
1134 if (index == 0)
1135 index = DESC_INDEX;
1136 else
1137 index -= 1;
1138
1c1008c7
FF		 1139 nr_frags = skb_shinfo(skb)->nr_frags;
1140 ring = &priv->tx_rings[index];
b2cde2cc 1141 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1142
1143 spin_lock_irqsave(&ring->lock, flags);
1144 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1145 netif_tx_stop_queue(txq);
1c1008c7
FF		 1146 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1147 __func__, index, ring->queue);
1148 ret = NETDEV_TX_BUSY;
1149 goto out;
1150 }
1151
1c1008c7
FF		 1152 /* set the SKB transmit checksum */
1153 if (priv->desc_64b_en) {
1154 ret = bcmgenet_put_tx_csum(dev, skb);
1155 if (ret) {
1156 ret = NETDEV_TX_OK;
1157 goto out;
1158 }
1159 }
1160
1161 dma_desc_flags = DMA_SOP;
1162 if (nr_frags == 0)
1163 dma_desc_flags |= DMA_EOP;
1164
1165 /* Transmit single SKB or head of fragment list */
1166 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1167 if (ret) {
1168 ret = NETDEV_TX_OK;
1169 goto out;
1170 }
1171
1172 /* xmit fragment */
1173 for (i = 0; i < nr_frags; i++) {
1174 ret = bcmgenet_xmit_frag(dev,
1175 &skb_shinfo(skb)->frags[i],
1176 (i == nr_frags - 1) ? DMA_EOP : 0, ring);
1177 if (ret) {
1178 ret = NETDEV_TX_OK;
1179 goto out;
1180 }
1181 }
1182
d03825fb
FF		 1183 skb_tx_timestamp(skb);
1184
1c1008c7
FF		 1185 /* we kept a software copy of how much we should advance the TDMA
1186 * producer index, now write it down to the hardware
1187 */
1188 bcmgenet_tdma_ring_writel(priv, ring->index,
1189 ring->prod_index, TDMA_PROD_INDEX);
1190
1191 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
b2cde2cc 1192 netif_tx_stop_queue(txq);
1c1008c7
FF		 1193 ring->int_enable(priv, ring);
1194 }
1195
1196out:
1197 spin_unlock_irqrestore(&ring->lock, flags);
1198
1199 return ret;
1200}
1201
1202
1203static int bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1204 struct enet_cb *cb)
1205{
1206 struct device *kdev = &priv->pdev->dev;
1207 struct sk_buff *skb;
1208 dma_addr_t mapping;
1209 int ret;
1210
1211 skb = netdev_alloc_skb(priv->dev,
1212 priv->rx_buf_len + SKB_ALIGNMENT);
1213 if (!skb)
1214 return -ENOMEM;
1215
1216 /* a caller did not release this control block */
1217 WARN_ON(cb->skb != NULL);
1218 cb->skb = skb;
1219 mapping = dma_map_single(kdev, skb->data,
1220 priv->rx_buf_len, DMA_FROM_DEVICE);
1221 ret = dma_mapping_error(kdev, mapping);
1222 if (ret) {
1223 bcmgenet_free_cb(cb);
1224 netif_err(priv, rx_err, priv->dev,
1225 "%s DMA map failed\n", __func__);
1226 return ret;
1227 }
1228
1229 dma_unmap_addr_set(cb, dma_addr, mapping);
1230 /* assign packet, prepare descriptor, and advance pointer */
1231
1232 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1233
1234 /* turn on the newly assigned BD for DMA to use */
1235 priv->rx_bd_assign_index++;
1236 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1237
1238 priv->rx_bd_assign_ptr = priv->rx_bds +
1239 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1240
1241 return 0;
1242}
1243
1244/* bcmgenet_desc_rx - descriptor based rx process.
1245 * this could be called from bottom half, or from NAPI polling method.
1246 */
1247static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1248 unsigned int budget)
1249{
1250 struct net_device *dev = priv->dev;
1251 struct enet_cb *cb;
1252 struct sk_buff *skb;
1253 u32 dma_length_status;
1254 unsigned long dma_flag;
1255 int len, err;
1256 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1257 unsigned int p_index;
1258 unsigned int chksum_ok = 0;
1259
1260 p_index = bcmgenet_rdma_ring_readl(priv,
1261 DESC_INDEX, RDMA_PROD_INDEX);
1262 p_index &= DMA_P_INDEX_MASK;
1263
1264 if (p_index < priv->rx_c_index)
1265 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1266 priv->rx_c_index + p_index;
1267 else
1268 rxpkttoprocess = p_index - priv->rx_c_index;
1269
1270 netif_dbg(priv, rx_status, dev,
1271 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1272
1273 while ((rxpktprocessed < rxpkttoprocess) &&
1274 (rxpktprocessed < budget)) {
1275
1276 /* Unmap the packet contents such that we can use the
1277 * RSV from the 64 bytes descriptor when enabled and save
1278 * a 32-bits register read
1279 */
1280 cb = &priv->rx_cbs[priv->rx_read_ptr];
1281 skb = cb->skb;
1282 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1283 priv->rx_buf_len, DMA_FROM_DEVICE);
1284
1285 if (!priv->desc_64b_en) {
1286 dma_length_status = dmadesc_get_length_status(priv,
1287 priv->rx_bds +
1288 (priv->rx_read_ptr *
1289 DMA_DESC_SIZE));
1290 } else {
1291 struct status_64 *status;
1292 status = (struct status_64 *)skb->data;
1293 dma_length_status = status->length_status;
1294 }
1295
1296 /* DMA flags and length are still valid no matter how
1297 * we got the Receive Status Vector (64B RSB or register)
1298 */
1299 dma_flag = dma_length_status & 0xffff;
1300 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1301
1302 netif_dbg(priv, rx_status, dev,
1303 "%s: p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1304 __func__, p_index, priv->rx_c_index, priv->rx_read_ptr,
1305 dma_length_status);
1306
1307 rxpktprocessed++;
1308
1309 priv->rx_read_ptr++;
1310 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1311
1312 /* out of memory, just drop packets at the hardware level */
1313 if (unlikely(!skb)) {
1314 dev->stats.rx_dropped++;
1315 dev->stats.rx_errors++;
1316 goto refill;
1317 }
1318
1319 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1320 netif_err(priv, rx_status, dev,
1321 "Droping fragmented packet!\n");
1322 dev->stats.rx_dropped++;
1323 dev->stats.rx_errors++;
1324 dev_kfree_skb_any(cb->skb);
1325 cb->skb = NULL;
1326 goto refill;
1327 }
1328 /* report errors */
1329 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1330 DMA_RX_OV |
1331 DMA_RX_NO |
1332 DMA_RX_LG |
1333 DMA_RX_RXER))) {
1334 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1335 (unsigned int)dma_flag);
1336 if (dma_flag & DMA_RX_CRC_ERROR)
1337 dev->stats.rx_crc_errors++;
1338 if (dma_flag & DMA_RX_OV)
1339 dev->stats.rx_over_errors++;
1340 if (dma_flag & DMA_RX_NO)
1341 dev->stats.rx_frame_errors++;
1342 if (dma_flag & DMA_RX_LG)
1343 dev->stats.rx_length_errors++;
1344 dev->stats.rx_dropped++;
1345 dev->stats.rx_errors++;
1346
1347 /* discard the packet and advance consumer index.*/
1348 dev_kfree_skb_any(cb->skb);
1349 cb->skb = NULL;
1350 goto refill;
1351 } /* error packet */
1352
1353 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1354 priv->desc_rxchk_en;
1355
1356 skb_put(skb, len);
1357 if (priv->desc_64b_en) {
1358 skb_pull(skb, 64);
1359 len -= 64;
1360 }
1361
1362 if (likely(chksum_ok))
1363 skb->ip_summed = CHECKSUM_UNNECESSARY;
1364
1365 /* remove hardware 2bytes added for IP alignment */
1366 skb_pull(skb, 2);
1367 len -= 2;
1368
1369 if (priv->crc_fwd_en) {
1370 skb_trim(skb, len - ETH_FCS_LEN);
1371 len -= ETH_FCS_LEN;
1372 }
1373
1374 /*Finish setting up the received SKB and send it to the kernel*/
1375 skb->protocol = eth_type_trans(skb, priv->dev);
1376 dev->stats.rx_packets++;
1377 dev->stats.rx_bytes += len;
1378 if (dma_flag & DMA_RX_MULT)
1379 dev->stats.multicast++;
1380
1381 /* Notify kernel */
1382 napi_gro_receive(&priv->napi, skb);
1383 cb->skb = NULL;
1384 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1385
1386 /* refill RX path on the current control block */
1387refill:
1388 err = bcmgenet_rx_refill(priv, cb);
1389 if (err)
1390 netif_err(priv, rx_err, dev, "Rx refill failed\n");
1391 }
1392
1393 return rxpktprocessed;
1394}
1395
1396/* Assign skb to RX DMA descriptor. */
1397static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1398{
1399 struct enet_cb *cb;
1400 int ret = 0;
1401 int i;
1402
1403 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1404
1405 /* loop here for each buffer needing assign */
1406 for (i = 0; i < priv->num_rx_bds; i++) {
1407 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1408 if (cb->skb)
1409 continue;
1410
1c1008c7
FF		 1411 ret = bcmgenet_rx_refill(priv, cb);
1412 if (ret)
1413 break;
1414
1415 }
1416
1417 return ret;
1418}
1419
1420static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1421{
1422 struct enet_cb *cb;
1423 int i;
1424
1425 for (i = 0; i < priv->num_rx_bds; i++) {
1426 cb = &priv->rx_cbs[i];
1427
1428 if (dma_unmap_addr(cb, dma_addr)) {
1429 dma_unmap_single(&priv->dev->dev,
1430 dma_unmap_addr(cb, dma_addr),
1431 priv->rx_buf_len, DMA_FROM_DEVICE);
1432 dma_unmap_addr_set(cb, dma_addr, 0);
1433 }
1434
1435 if (cb->skb)
1436 bcmgenet_free_cb(cb);
1437 }
1438}
1439
e29585b8
FF		 1440static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask,
1441 bool enable)
1442{
1443 u32 reg;
1444
1445 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1446 if (enable)
1447 reg |= mask;
1448 else
1449 reg &= ~mask;
1450 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1451
1452 /* UniMAC stops on a packet boundary, wait for a full-size packet
1453 * to be processed
1454 */
1455 if (enable == 0)
1456 usleep_range(1000, 2000);
1457}
1458
1c1008c7
FF		 1459static int reset_umac(struct bcmgenet_priv *priv)
1460{
1461 struct device *kdev = &priv->pdev->dev;
1462 unsigned int timeout = 0;
1463 u32 reg;
1464
1465 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1466 bcmgenet_rbuf_ctrl_set(priv, 0);
1467 udelay(10);
1468
1469 /* disable MAC while updating its registers */
1470 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1471
1472 /* issue soft reset, wait for it to complete */
1473 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1474 while (timeout++ < 1000) {
1475 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1476 if (!(reg & CMD_SW_RESET))
1477 return 0;
1478
1479 udelay(1);
1480 }
1481
1482 if (timeout == 1000) {
1483 dev_err(kdev,
1484 "timeout waiting for MAC to come out of resetn\n");
1485 return -ETIMEDOUT;
1486 }
1487
1488 return 0;
1489}
1490
909ff5ef
FF		 1491static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1492{
1493 /* Mask all interrupts.*/
1494 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1495 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1496 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1497 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1498 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1499 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1500}
1501
1c1008c7
FF		 1502static int init_umac(struct bcmgenet_priv *priv)
1503{
1504 struct device *kdev = &priv->pdev->dev;
1505 int ret;
1506 u32 reg, cpu_mask_clear;
1507
1508 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1509
1510 ret = reset_umac(priv);
1511 if (ret)
1512 return ret;
1513
1514 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1515 /* clear tx/rx counter */
1516 bcmgenet_umac_writel(priv,
1517 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, UMAC_MIB_CTRL);
1518 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1519
1520 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1521
1522 /* init rx registers, enable ip header optimization */
1523 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1524 reg |= RBUF_ALIGN_2B;
1525 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1526
1527 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1528 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1529
909ff5ef 1530 bcmgenet_intr_disable(priv);
1c1008c7
FF		 1531
1532 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1533
1534 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1535
1536 /* Monitor cable plug/unpluged event for internal PHY */
1537 if (phy_is_internal(priv->phydev))
1538 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1539 else if (priv->ext_phy)
1540 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1541 else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1542 reg = bcmgenet_bp_mc_get(priv);
1543 reg |= BIT(priv->hw_params->bp_in_en_shift);
1544
1545 /* bp_mask: back pressure mask */
1546 if (netif_is_multiqueue(priv->dev))
1547 reg |= priv->hw_params->bp_in_mask;
1548 else
1549 reg &= ~priv->hw_params->bp_in_mask;
1550 bcmgenet_bp_mc_set(priv, reg);
1551 }
1552
1553 /* Enable MDIO interrupts on GENET v3+ */
1554 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1555 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1556
1557 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear,
1558 INTRL2_CPU_MASK_CLEAR);
1559
1560 /* Enable rx/tx engine.*/
1561 dev_dbg(kdev, "done init umac\n");
1562
1563 return 0;
1564}
1565
1566/* Initialize all house-keeping variables for a TX ring, along
1567 * with corresponding hardware registers
1568 */
1569static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1570 unsigned int index, unsigned int size,
1571 unsigned int write_ptr, unsigned int end_ptr)
1572{
1573 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1574 u32 words_per_bd = WORDS_PER_BD(priv);
1575 u32 flow_period_val = 0;
1576 unsigned int first_bd;
1577
1578 spin_lock_init(&ring->lock);
1579 ring->index = index;
1580 if (index == DESC_INDEX) {
1581 ring->queue = 0;
1582 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1583 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1584 } else {
1585 ring->queue = index + 1;
1586 ring->int_enable = bcmgenet_tx_ring_int_enable;
1587 ring->int_disable = bcmgenet_tx_ring_int_disable;
1588 }
1589 ring->cbs = priv->tx_cbs + write_ptr;
1590 ring->size = size;
1591 ring->c_index = 0;
1592 ring->free_bds = size;
1593 ring->write_ptr = write_ptr;
1594 ring->cb_ptr = write_ptr;
1595 ring->end_ptr = end_ptr - 1;
1596 ring->prod_index = 0;
1597
1598 /* Set flow period for ring != 16 */
1599 if (index != DESC_INDEX)
1600 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1601
1602 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1603 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1604 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1605 /* Disable rate control for now */
1606 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1607 TDMA_FLOW_PERIOD);
1608 /* Unclassified traffic goes to ring 16 */
1609 bcmgenet_tdma_ring_writel(priv, index,
1610 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1611 DMA_RING_BUF_SIZE);
1612
1613 first_bd = write_ptr;
1614
1615 /* Set start and end address, read and write pointers */
1616 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1617 DMA_START_ADDR);
1618 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1619 TDMA_READ_PTR);
1620 bcmgenet_tdma_ring_writel(priv, index, first_bd,
1621 TDMA_WRITE_PTR);
1622 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1623 DMA_END_ADDR);
1624}
1625
1626/* Initialize a RDMA ring */
1627static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1628 unsigned int index, unsigned int size)
1629{
1630 u32 words_per_bd = WORDS_PER_BD(priv);
1631 int ret;
1632
1633 priv->num_rx_bds = TOTAL_DESC;
1634 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1635 priv->rx_bd_assign_ptr = priv->rx_bds;
1636 priv->rx_bd_assign_index = 0;
1637 priv->rx_c_index = 0;
1638 priv->rx_read_ptr = 0;
1639 priv->rx_cbs = kzalloc(priv->num_rx_bds * sizeof(struct enet_cb),
1640 GFP_KERNEL);
1641 if (!priv->rx_cbs)
1642 return -ENOMEM;
1643
1644 ret = bcmgenet_alloc_rx_buffers(priv);
1645 if (ret) {
1646 kfree(priv->rx_cbs);
1647 return ret;
1648 }
1649
1650 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1651 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1652 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1653 bcmgenet_rdma_ring_writel(priv, index,
1654 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1655 DMA_RING_BUF_SIZE);
1656 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1657 bcmgenet_rdma_ring_writel(priv, index,
1658 words_per_bd * size - 1, DMA_END_ADDR);
1659 bcmgenet_rdma_ring_writel(priv, index,
1660 (DMA_FC_THRESH_LO << DMA_XOFF_THRESHOLD_SHIFT) |
1661 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1662 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1663
1664 return ret;
1665}
1666
1667/* init multi xmit queues, only available for GENET2+
1668 * the queue is partitioned as follows:
1669 *
1670 * queue 0 - 3 is priority based, each one has 32 descriptors,
1671 * with queue 0 being the highest priority queue.
1672 *
1673 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1674 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1675 * descriptors.
1676 *
1677 * The transmit control block pool is then partitioned as following:
1678 * - tx_cbs[0...127] are for queue 16
1679 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1680 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1681 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1682 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1683 */
1684static void bcmgenet_init_multiq(struct net_device *dev)
1685{
1686 struct bcmgenet_priv *priv = netdev_priv(dev);
1687 unsigned int i, dma_enable;
1688 u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
1689
1690 if (!netif_is_multiqueue(dev)) {
1691 netdev_warn(dev, "called with non multi queue aware HW\n");
1692 return;
1693 }
1694
1695 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1696 dma_enable = dma_ctrl & DMA_EN;
1697 dma_ctrl &= ~DMA_EN;
1698 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1699
1700 /* Enable strict priority arbiter mode */
1701 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1702
1703 for (i = 0; i < priv->hw_params->tx_queues; i++) {
1704 /* first 64 tx_cbs are reserved for default tx queue
1705 * (ring 16)
1706 */
1707 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1708 i * priv->hw_params->bds_cnt,
1709 (i + 1) * priv->hw_params->bds_cnt);
1710
1711 /* Configure ring as decriptor ring and setup priority */
1712 ring_cfg |= 1 << i;
1713 dma_priority |= ((GENET_Q0_PRIORITY + i) <<
1714 (GENET_MAX_MQ_CNT + 1) * i);
1715 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1716 }
1717
1718 /* Enable rings */
1719 reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1720 reg |= ring_cfg;
1721 bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1722
1723 /* Use configured rings priority and set ring #16 priority */
1724 reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
1725 reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
1726 reg |= dma_priority;
1727 bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
1728
1729 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1730 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1731 reg |= dma_ctrl;
1732 if (dma_enable)
1733 reg |= DMA_EN;
1734 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1735}
1736
1737static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1738{
1739 int i;
1740
1741 /* disable DMA */
1742 bcmgenet_rdma_writel(priv, 0, DMA_CTRL);
1743 bcmgenet_tdma_writel(priv, 0, DMA_CTRL);
1744
1745 for (i = 0; i < priv->num_tx_bds; i++) {
1746 if (priv->tx_cbs[i].skb != NULL) {
1747 dev_kfree_skb(priv->tx_cbs[i].skb);
1748 priv->tx_cbs[i].skb = NULL;
1749 }
1750 }
1751
1752 bcmgenet_free_rx_buffers(priv);
1753 kfree(priv->rx_cbs);
1754 kfree(priv->tx_cbs);
1755}
1756
1757/* init_edma: Initialize DMA control register */
1758static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1759{
1760 int ret;
1761
1762 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1763
1764 /* by default, enable ring 16 (descriptor based) */
1765 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1766 if (ret) {
1767 netdev_err(priv->dev, "failed to initialize RX ring\n");
1768 return ret;
1769 }
1770
1771 /* init rDma */
1772 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1773
1774 /* Init tDma */
1775 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1776
1777 /* Initialize commont TX ring structures */
1778 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1779 priv->num_tx_bds = TOTAL_DESC;
1780 priv->tx_cbs = kzalloc(priv->num_tx_bds * sizeof(struct enet_cb),
1781 GFP_KERNEL);
1782 if (!priv->tx_cbs) {
1783 bcmgenet_fini_dma(priv);
1784 return -ENOMEM;
1785 }
1786
1787 /* initialize multi xmit queue */
1788 bcmgenet_init_multiq(priv->dev);
1789
1790 /* initialize special ring 16 */
1791 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1792 priv->hw_params->tx_queues * priv->hw_params->bds_cnt,
1793 TOTAL_DESC);
1794
1795 return 0;
1796}
1797
1798/* NAPI polling method*/
1799static int bcmgenet_poll(struct napi_struct *napi, int budget)
1800{
1801 struct bcmgenet_priv *priv = container_of(napi,
1802 struct bcmgenet_priv, napi);
1803 unsigned int work_done;
1804
1805 /* tx reclaim */
1806 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1807
1808 work_done = bcmgenet_desc_rx(priv, budget);
1809
1810 /* Advancing our consumer index*/
1811 priv->rx_c_index += work_done;
1812 priv->rx_c_index &= DMA_C_INDEX_MASK;
1813 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1814 priv->rx_c_index, RDMA_CONS_INDEX);
1815 if (work_done < budget) {
1816 napi_complete(napi);
1817 bcmgenet_intrl2_0_writel(priv,
1818 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_CLEAR);
1819 }
1820
1821 return work_done;
1822}
1823
1824/* Interrupt bottom half */
1825static void bcmgenet_irq_task(struct work_struct *work)
1826{
1827 struct bcmgenet_priv *priv = container_of(
1828 work, struct bcmgenet_priv, bcmgenet_irq_work);
1829
1830 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1831
8fdb0e0f
FF		 1832 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
1833 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
1834 netif_dbg(priv, wol, priv->dev,
1835 "magic packet detected, waking up\n");
1836 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
1837 }
1838
1c1008c7
FF		 1839 /* Link UP/DOWN event */
1840 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1841 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d
FF		 1842 phy_mac_interrupt(priv->phydev,
1843 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 1844 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
1845 }
1846}
1847
1848/* bcmgenet_isr1: interrupt handler for ring buffer. */
1849static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
1850{
1851 struct bcmgenet_priv *priv = dev_id;
1852 unsigned int index;
1853
1854 /* Save irq status for bottom-half processing. */
1855 priv->irq1_stat =
1856 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
1857 ~priv->int1_mask;
1858 /* clear inerrupts*/
1859 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
1860
1861 netif_dbg(priv, intr, priv->dev,
1862 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1863 /* Check the MBDONE interrupts.
1864 * packet is done, reclaim descriptors
1865 */
1866 if (priv->irq1_stat & 0x0000ffff) {
1867 index = 0;
1868 for (index = 0; index < 16; index++) {
1869 if (priv->irq1_stat & (1 << index))
1870 bcmgenet_tx_reclaim(priv->dev,
1871 &priv->tx_rings[index]);
1872 }
1873 }
1874 return IRQ_HANDLED;
1875}
1876
1877/* bcmgenet_isr0: Handle various interrupts. */
1878static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
1879{
1880 struct bcmgenet_priv *priv = dev_id;
1881
1882 /* Save irq status for bottom-half processing. */
1883 priv->irq0_stat =
1884 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1885 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1886 /* clear inerrupts*/
1887 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1888
1889 netif_dbg(priv, intr, priv->dev,
1890 "IRQ=0x%x\n", priv->irq0_stat);
1891
1892 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
1893 /* We use NAPI(software interrupt throttling, if
1894 * Rx Descriptor throttling is not used.
1895 * Disable interrupt, will be enabled in the poll method.
1896 */
1897 if (likely(napi_schedule_prep(&priv->napi))) {
1898 bcmgenet_intrl2_0_writel(priv,
1899 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_SET);
1900 __napi_schedule(&priv->napi);
1901 }
1902 }
1903 if (priv->irq0_stat &
1904 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
1905 /* Tx reclaim */
1906 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1907 }
1908 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
1909 UMAC_IRQ_PHY_DET_F |
1910 UMAC_IRQ_LINK_UP |
1911 UMAC_IRQ_LINK_DOWN |
1912 UMAC_IRQ_HFB_SM |
1913 UMAC_IRQ_HFB_MM |
1914 UMAC_IRQ_MPD_R)) {
1915 /* all other interested interrupts handled in bottom half */
1916 schedule_work(&priv->bcmgenet_irq_work);
1917 }
1918
1919 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1920 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1921 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1922 wake_up(&priv->wq);
1923 }
1924
1925 return IRQ_HANDLED;
1926}
1927
8562056f
FF		 1928static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
1929{
1930 struct bcmgenet_priv *priv = dev_id;
1931
1932 pm_wakeup_event(&priv->pdev->dev, 0);
1933
1934 return IRQ_HANDLED;
1935}
1936
1c1008c7
FF		 1937static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
1938{
1939 u32 reg;
1940
1941 reg = bcmgenet_rbuf_ctrl_get(priv);
1942 reg |= BIT(1);
1943 bcmgenet_rbuf_ctrl_set(priv, reg);
1944 udelay(10);
1945
1946 reg &= ~BIT(1);
1947 bcmgenet_rbuf_ctrl_set(priv, reg);
1948 udelay(10);
1949}
1950
1951static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
1952 unsigned char *addr)
1953{
1954 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1955 (addr[2] << 8) | addr[3], UMAC_MAC0);
1956 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1957}
1958
1959static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
1960{
1c1008c7 1961 /* From WOL-enabled suspend, switch to regular clock */
1c3c1e79 1962 clk_disable_unprepare(priv->clk_wol);
1c1008c7 1963
80d8e96d 1964 phy_init_hw(priv->phydev);
1c1008c7
FF		 1965 /* Speed settings must be restored */
1966 bcmgenet_mii_config(priv->dev);
1967
1968 return 0;
1969}
1970
1971/* Returns a reusable dma control register value */
1972static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
1973{
1974 u32 reg;
1975 u32 dma_ctrl;
1976
1977 /* disable DMA */
1978 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
1979 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1980 reg &= ~dma_ctrl;
1981 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1982
1983 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1984 reg &= ~dma_ctrl;
1985 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1986
1987 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
1988 udelay(10);
1989 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
1990
1991 return dma_ctrl;
1992}
1993
1994static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
1995{
1996 u32 reg;
1997
1998 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1999 reg |= dma_ctrl;
2000 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2001
2002 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2003 reg |= dma_ctrl;
2004 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2005}
2006
909ff5ef
FF		 2007static void bcmgenet_netif_start(struct net_device *dev)
2008{
2009 struct bcmgenet_priv *priv = netdev_priv(dev);
2010
2011 /* Start the network engine */
2012 napi_enable(&priv->napi);
2013
2014 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2015
2016 if (phy_is_internal(priv->phydev))
2017 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2018
2019 netif_tx_start_all_queues(dev);
2020
2021 phy_start(priv->phydev);
2022}
2023
1c1008c7
FF		 2024static int bcmgenet_open(struct net_device *dev)
2025{
2026 struct bcmgenet_priv *priv = netdev_priv(dev);
2027 unsigned long dma_ctrl;
2028 u32 reg;
2029 int ret;
2030
2031 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2032
2033 /* Turn on the clock */
2034 if (!IS_ERR(priv->clk))
2035 clk_prepare_enable(priv->clk);
2036
2037 /* take MAC out of reset */
2038 bcmgenet_umac_reset(priv);
2039
2040 ret = init_umac(priv);
2041 if (ret)
2042 goto err_clk_disable;
2043
2044 /* disable ethernet MAC while updating its registers */
e29585b8 2045 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2046
909ff5ef
FF		 2047 /* Make sure we reflect the value of CRC_CMD_FWD */
2048 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2049 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2050
1c1008c7
FF		 2051 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2052
1c1008c7
FF		 2053 if (phy_is_internal(priv->phydev)) {
2054 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2055 reg |= EXT_ENERGY_DET_MASK;
2056 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2057 }
2058
2059 /* Disable RX/TX DMA and flush TX queues */
2060 dma_ctrl = bcmgenet_dma_disable(priv);
2061
2062 /* Reinitialize TDMA and RDMA and SW housekeeping */
2063 ret = bcmgenet_init_dma(priv);
2064 if (ret) {
2065 netdev_err(dev, "failed to initialize DMA\n");
2066 goto err_fini_dma;
2067 }
2068
2069 /* Always enable ring 16 - descriptor ring */
2070 bcmgenet_enable_dma(priv, dma_ctrl);
2071
2072 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2073 dev->name, priv);
2074 if (ret < 0) {
2075 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2076 goto err_fini_dma;
2077 }
2078
2079 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2080 dev->name, priv);
2081 if (ret < 0) {
2082 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2083 goto err_irq0;
2084 }
2085
909ff5ef 2086 bcmgenet_netif_start(dev);
1c1008c7
FF		 2087
2088 return 0;
2089
2090err_irq0:
2091 free_irq(priv->irq0, dev);
2092err_fini_dma:
2093 bcmgenet_fini_dma(priv);
2094err_clk_disable:
2095 if (!IS_ERR(priv->clk))
2096 clk_disable_unprepare(priv->clk);
2097 return ret;
2098}
2099
2100static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2101{
2102 int ret = 0;
2103 int timeout = 0;
2104 u32 reg;
2105
2106 /* Disable TDMA to stop add more frames in TX DMA */
2107 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2108 reg &= ~DMA_EN;
2109 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2110
2111 /* Check TDMA status register to confirm TDMA is disabled */
2112 while (timeout++ < DMA_TIMEOUT_VAL) {
2113 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2114 if (reg & DMA_DISABLED)
2115 break;
2116
2117 udelay(1);
2118 }
2119
2120 if (timeout == DMA_TIMEOUT_VAL) {
2121 netdev_warn(priv->dev,
2122 "Timed out while disabling TX DMA\n");
2123 ret = -ETIMEDOUT;
2124 }
2125
2126 /* Wait 10ms for packet drain in both tx and rx dma */
2127 usleep_range(10000, 20000);
2128
2129 /* Disable RDMA */
2130 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2131 reg &= ~DMA_EN;
2132 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2133
2134 timeout = 0;
2135 /* Check RDMA status register to confirm RDMA is disabled */
2136 while (timeout++ < DMA_TIMEOUT_VAL) {
2137 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2138 if (reg & DMA_DISABLED)
2139 break;
2140
2141 udelay(1);
2142 }
2143
2144 if (timeout == DMA_TIMEOUT_VAL) {
2145 netdev_warn(priv->dev,
2146 "Timed out while disabling RX DMA\n");
2147 ret = -ETIMEDOUT;
2148 }
2149
2150 return ret;
2151}
2152
909ff5ef
FF		 2153static void bcmgenet_netif_stop(struct net_device *dev)
2154{
2155 struct bcmgenet_priv *priv = netdev_priv(dev);
2156
2157 netif_tx_stop_all_queues(dev);
2158 napi_disable(&priv->napi);
2159 phy_stop(priv->phydev);
2160
2161 bcmgenet_intr_disable(priv);
2162
2163 /* Wait for pending work items to complete. Since interrupts are
2164 * disabled no new work will be scheduled.
2165 */
2166 cancel_work_sync(&priv->bcmgenet_irq_work);
2167}
2168
1c1008c7
FF		 2169static int bcmgenet_close(struct net_device *dev)
2170{
2171 struct bcmgenet_priv *priv = netdev_priv(dev);
2172 int ret;
1c1008c7
FF		 2173
2174 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2175
909ff5ef 2176 bcmgenet_netif_stop(dev);
1c1008c7
FF		 2177
2178 /* Disable MAC receive */
e29585b8 2179 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2180
1c1008c7
FF		 2181 ret = bcmgenet_dma_teardown(priv);
2182 if (ret)
2183 return ret;
2184
2185 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2186 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2187
1c1008c7
FF		 2188 /* tx reclaim */
2189 bcmgenet_tx_reclaim_all(dev);
2190 bcmgenet_fini_dma(priv);
2191
2192 free_irq(priv->irq0, priv);
2193 free_irq(priv->irq1, priv);
2194
1c1008c7
FF		 2195 if (phy_is_internal(priv->phydev))
2196 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2197
1c1008c7
FF		 2198 if (!IS_ERR(priv->clk))
2199 clk_disable_unprepare(priv->clk);
2200
2201 return 0;
2202}
2203
2204static void bcmgenet_timeout(struct net_device *dev)
2205{
2206 struct bcmgenet_priv *priv = netdev_priv(dev);
2207
2208 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2209
2210 dev->trans_start = jiffies;
2211
2212 dev->stats.tx_errors++;
2213
2214 netif_tx_wake_all_queues(dev);
2215}
2216
2217#define MAX_MC_COUNT 16
2218
2219static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2220 unsigned char *addr,
2221 int *i,
2222 int *mc)
2223{
2224 u32 reg;
2225
2226 bcmgenet_umac_writel(priv,
2227 addr[0] << 8 | addr[1], UMAC_MDF_ADDR + (*i * 4));
2228 bcmgenet_umac_writel(priv,
2229 addr[2] << 24 | addr[3] << 16 |
2230 addr[4] << 8 | addr[5],
2231 UMAC_MDF_ADDR + ((*i + 1) * 4));
2232 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2233 reg |= (1 << (MAX_MC_COUNT - *mc));
2234 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2235 *i += 2;
2236 (*mc)++;
2237}
2238
2239static void bcmgenet_set_rx_mode(struct net_device *dev)
2240{
2241 struct bcmgenet_priv *priv = netdev_priv(dev);
2242 struct netdev_hw_addr *ha;
2243 int i, mc;
2244 u32 reg;
2245
2246 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2247
2248 /* Promiscous mode */
2249 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2250 if (dev->flags & IFF_PROMISC) {
2251 reg |= CMD_PROMISC;
2252 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2253 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2254 return;
2255 } else {
2256 reg &= ~CMD_PROMISC;
2257 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2258 }
2259
2260 /* UniMac doesn't support ALLMULTI */
2261 if (dev->flags & IFF_ALLMULTI) {
2262 netdev_warn(dev, "ALLMULTI is not supported\n");
2263 return;
2264 }
2265
2266 /* update MDF filter */
2267 i = 0;
2268 mc = 0;
2269 /* Broadcast */
2270 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2271 /* my own address.*/
2272 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2273 /* Unicast list*/
2274 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2275 return;
2276
2277 if (!netdev_uc_empty(dev))
2278 netdev_for_each_uc_addr(ha, dev)
2279 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2280 /* Multicast */
2281 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2282 return;
2283
2284 netdev_for_each_mc_addr(ha, dev)
2285 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2286}
2287
2288/* Set the hardware MAC address. */
2289static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2290{
2291 struct sockaddr *addr = p;
2292
2293 /* Setting the MAC address at the hardware level is not possible
2294 * without disabling the UniMAC RX/TX enable bits.
2295 */
2296 if (netif_running(dev))
2297 return -EBUSY;
2298
2299 ether_addr_copy(dev->dev_addr, addr->sa_data);
2300
2301 return 0;
2302}
2303
1c1008c7
FF		 2304static const struct net_device_ops bcmgenet_netdev_ops = {
2305 .ndo_open = bcmgenet_open,
2306 .ndo_stop = bcmgenet_close,
2307 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2308 .ndo_tx_timeout = bcmgenet_timeout,
2309 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2310 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2311 .ndo_do_ioctl = bcmgenet_ioctl,
2312 .ndo_set_features = bcmgenet_set_features,
2313};
2314
2315/* Array of GENET hardware parameters/characteristics */
2316static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2317 [GENET_V1] = {
2318 .tx_queues = 0,
2319 .rx_queues = 0,
2320 .bds_cnt = 0,
2321 .bp_in_en_shift = 16,
2322 .bp_in_mask = 0xffff,
2323 .hfb_filter_cnt = 16,
2324 .qtag_mask = 0x1F,
2325 .hfb_offset = 0x1000,
2326 .rdma_offset = 0x2000,
2327 .tdma_offset = 0x3000,
2328 .words_per_bd = 2,
2329 },
2330 [GENET_V2] = {
2331 .tx_queues = 4,
2332 .rx_queues = 4,
2333 .bds_cnt = 32,
2334 .bp_in_en_shift = 16,
2335 .bp_in_mask = 0xffff,
2336 .hfb_filter_cnt = 16,
2337 .qtag_mask = 0x1F,
2338 .tbuf_offset = 0x0600,
2339 .hfb_offset = 0x1000,
2340 .hfb_reg_offset = 0x2000,
2341 .rdma_offset = 0x3000,
2342 .tdma_offset = 0x4000,
2343 .words_per_bd = 2,
2344 .flags = GENET_HAS_EXT,
2345 },
2346 [GENET_V3] = {
2347 .tx_queues = 4,
2348 .rx_queues = 4,
2349 .bds_cnt = 32,
2350 .bp_in_en_shift = 17,
2351 .bp_in_mask = 0x1ffff,
2352 .hfb_filter_cnt = 48,
2353 .qtag_mask = 0x3F,
2354 .tbuf_offset = 0x0600,
2355 .hfb_offset = 0x8000,
2356 .hfb_reg_offset = 0xfc00,
2357 .rdma_offset = 0x10000,
2358 .tdma_offset = 0x11000,
2359 .words_per_bd = 2,
2360 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2361 },
2362 [GENET_V4] = {
2363 .tx_queues = 4,
2364 .rx_queues = 4,
2365 .bds_cnt = 32,
2366 .bp_in_en_shift = 17,
2367 .bp_in_mask = 0x1ffff,
2368 .hfb_filter_cnt = 48,
2369 .qtag_mask = 0x3F,
2370 .tbuf_offset = 0x0600,
2371 .hfb_offset = 0x8000,
2372 .hfb_reg_offset = 0xfc00,
2373 .rdma_offset = 0x2000,
2374 .tdma_offset = 0x4000,
2375 .words_per_bd = 3,
2376 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2377 },
2378};
2379
2380/* Infer hardware parameters from the detected GENET version */
2381static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2382{
2383 struct bcmgenet_hw_params *params;
2384 u32 reg;
2385 u8 major;
2386
2387 if (GENET_IS_V4(priv)) {
2388 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2389 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2390 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2391 priv->version = GENET_V4;
2392 } else if (GENET_IS_V3(priv)) {
2393 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2394 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2395 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2396 priv->version = GENET_V3;
2397 } else if (GENET_IS_V2(priv)) {
2398 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2399 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2400 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2401 priv->version = GENET_V2;
2402 } else if (GENET_IS_V1(priv)) {
2403 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2404 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2405 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2406 priv->version = GENET_V1;
2407 }
2408
2409 /* enum genet_version starts at 1 */
2410 priv->hw_params = &bcmgenet_hw_params[priv->version];
2411 params = priv->hw_params;
2412
2413 /* Read GENET HW version */
2414 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2415 major = (reg >> 24 & 0x0f);
2416 if (major == 5)
2417 major = 4;
2418 else if (major == 0)
2419 major = 1;
2420 if (major != priv->version) {
2421 dev_err(&priv->pdev->dev,
2422 "GENET version mismatch, got: %d, configured for: %d\n",
2423 major, priv->version);
2424 }
2425
2426 /* Print the GENET core version */
2427 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2428 major, (reg >> 16) & 0x0f, reg & 0xffff);
2429
2430#ifdef CONFIG_PHYS_ADDR_T_64BIT
2431 if (!(params->flags & GENET_HAS_40BITS))
2432 pr_warn("GENET does not support 40-bits PA\n");
2433#endif
2434
2435 pr_debug("Configuration for version: %d\n"
2436 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2437 "BP << en: %2d, BP msk: 0x%05x\n"
2438 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2439 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2440 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2441 "Words/BD: %d\n",
2442 priv->version,
2443 params->tx_queues, params->rx_queues, params->bds_cnt,
2444 params->bp_in_en_shift, params->bp_in_mask,
2445 params->hfb_filter_cnt, params->qtag_mask,
2446 params->tbuf_offset, params->hfb_offset,
2447 params->hfb_reg_offset,
2448 params->rdma_offset, params->tdma_offset,
2449 params->words_per_bd);
2450}
2451
2452static const struct of_device_id bcmgenet_match[] = {
2453 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2454 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2455 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2456 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2457 { },
2458};
2459
2460static int bcmgenet_probe(struct platform_device *pdev)
2461{
2462 struct device_node *dn = pdev->dev.of_node;
2463 const struct of_device_id *of_id;
2464 struct bcmgenet_priv *priv;
2465 struct net_device *dev;
2466 const void *macaddr;
2467 struct resource *r;
2468 int err = -EIO;
2469
2470 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2471 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2472 if (!dev) {
2473 dev_err(&pdev->dev, "can't allocate net device\n");
2474 return -ENOMEM;
2475 }
2476
2477 of_id = of_match_node(bcmgenet_match, dn);
2478 if (!of_id)
2479 return -EINVAL;
2480
2481 priv = netdev_priv(dev);
2482 priv->irq0 = platform_get_irq(pdev, 0);
2483 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2484 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2485 if (!priv->irq0 || !priv->irq1) {
2486 dev_err(&pdev->dev, "can't find IRQs\n");
2487 err = -EINVAL;
2488 goto err;
2489 }
2490
2491 macaddr = of_get_mac_address(dn);
2492 if (!macaddr) {
2493 dev_err(&pdev->dev, "can't find MAC address\n");
2494 err = -EINVAL;
2495 goto err;
2496 }
2497
2498 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2499 priv->base = devm_ioremap_resource(&pdev->dev, r);
2500 if (IS_ERR(priv->base)) {
2501 err = PTR_ERR(priv->base);
1c1008c7
FF		 2502 goto err;
2503 }
2504
2505 SET_NETDEV_DEV(dev, &pdev->dev);
2506 dev_set_drvdata(&pdev->dev, dev);
2507 ether_addr_copy(dev->dev_addr, macaddr);
2508 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2509 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2510 dev->netdev_ops = &bcmgenet_netdev_ops;
2511 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2512
2513 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2514
2515 /* Set hardware features */
2516 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2517 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2518
8562056f
FF		 2519 /* Request the WOL interrupt and advertise suspend if available */
2520 priv->wol_irq_disabled = true;
2521 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2522 dev->name, priv);
2523 if (!err)
2524 device_set_wakeup_capable(&pdev->dev, 1);
2525
1c1008c7
FF		 2526 /* Set the needed headroom to account for any possible
2527 * features enabling/disabling at runtime
2528 */
2529 dev->needed_headroom += 64;
2530
2531 netdev_boot_setup_check(dev);
2532
2533 priv->dev = dev;
2534 priv->pdev = pdev;
2535 priv->version = (enum bcmgenet_version)of_id->data;
2536
2537 bcmgenet_set_hw_params(priv);
2538
1c1008c7
FF		 2539 /* Mii wait queue */
2540 init_waitqueue_head(&priv->wq);
2541 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2542 priv->rx_buf_len = RX_BUF_LENGTH;
2543 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2544
2545 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2546 if (IS_ERR(priv->clk))
2547 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2548
2549 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2550 if (IS_ERR(priv->clk_wol))
2551 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2552
2553 if (!IS_ERR(priv->clk))
2554 clk_prepare_enable(priv->clk);
2555
2556 err = reset_umac(priv);
2557 if (err)
2558 goto err_clk_disable;
2559
2560 err = bcmgenet_mii_init(dev);
2561 if (err)
2562 goto err_clk_disable;
2563
2564 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2565 * just the ring 16 descriptor based TX
2566 */
2567 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2568 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2569
219575eb
FF		 2570 /* libphy will determine the link state */
2571 netif_carrier_off(dev);
2572
1c1008c7
FF		 2573 /* Turn off the main clock, WOL clock is handled separately */
2574 if (!IS_ERR(priv->clk))
2575 clk_disable_unprepare(priv->clk);
2576
0f50ce96
FF		 2577 err = register_netdev(dev);
2578 if (err)
2579 goto err;
2580
1c1008c7
FF		 2581 return err;
2582
2583err_clk_disable:
2584 if (!IS_ERR(priv->clk))
2585 clk_disable_unprepare(priv->clk);
2586err:
2587 free_netdev(dev);
2588 return err;
2589}
2590
2591static int bcmgenet_remove(struct platform_device *pdev)
2592{
2593 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2594
2595 dev_set_drvdata(&pdev->dev, NULL);
2596 unregister_netdev(priv->dev);
2597 bcmgenet_mii_exit(priv->dev);
2598 free_netdev(priv->dev);
2599
2600 return 0;
2601}
2602
b6e978e5
FF		 2603#ifdef CONFIG_PM_SLEEP
2604static int bcmgenet_suspend(struct device *d)
2605{
2606 struct net_device *dev = dev_get_drvdata(d);
2607 struct bcmgenet_priv *priv = netdev_priv(dev);
2608 int ret;
2609
2610 if (!netif_running(dev))
2611 return 0;
2612
2613 bcmgenet_netif_stop(dev);
2614
2615 netif_device_detach(dev);
2616
2617 /* Disable MAC receive */
2618 umac_enable_set(priv, CMD_RX_EN, false);
2619
2620 ret = bcmgenet_dma_teardown(priv);
2621 if (ret)
2622 return ret;
2623
2624 /* Disable MAC transmit. TX DMA disabled have to done before this */
2625 umac_enable_set(priv, CMD_TX_EN, false);
2626
2627 /* tx reclaim */
2628 bcmgenet_tx_reclaim_all(dev);
2629 bcmgenet_fini_dma(priv);
2630
8c90db72
FF		 2631 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2632 if (device_may_wakeup(d) && priv->wolopts) {
2633 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2634 clk_prepare_enable(priv->clk_wol);
2635 }
2636
b6e978e5
FF		 2637 /* Turn off the clocks */
2638 clk_disable_unprepare(priv->clk);
2639
2640 return 0;
2641}
2642
2643static int bcmgenet_resume(struct device *d)
2644{
2645 struct net_device *dev = dev_get_drvdata(d);
2646 struct bcmgenet_priv *priv = netdev_priv(dev);
2647 unsigned long dma_ctrl;
2648 int ret;
2649 u32 reg;
2650
2651 if (!netif_running(dev))
2652 return 0;
2653
2654 /* Turn on the clock */
2655 ret = clk_prepare_enable(priv->clk);
2656 if (ret)
2657 return ret;
2658
2659 bcmgenet_umac_reset(priv);
2660
2661 ret = init_umac(priv);
2662 if (ret)
2663 goto out_clk_disable;
2664
8c90db72
FF		 2665 if (priv->wolopts)
2666 ret = bcmgenet_wol_resume(priv);
2667
2668 if (ret)
2669 goto out_clk_disable;
2670
b6e978e5
FF		 2671 /* disable ethernet MAC while updating its registers */
2672 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2673
2674 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2675
2676 if (phy_is_internal(priv->phydev)) {
2677 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2678 reg |= EXT_ENERGY_DET_MASK;
2679 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2680 }
2681
2682 /* Disable RX/TX DMA and flush TX queues */
2683 dma_ctrl = bcmgenet_dma_disable(priv);
2684
2685 /* Reinitialize TDMA and RDMA and SW housekeeping */
2686 ret = bcmgenet_init_dma(priv);
2687 if (ret) {
2688 netdev_err(dev, "failed to initialize DMA\n");
2689 goto out_clk_disable;
2690 }
2691
2692 /* Always enable ring 16 - descriptor ring */
2693 bcmgenet_enable_dma(priv, dma_ctrl);
2694
2695 netif_device_attach(dev);
2696
2697 bcmgenet_netif_start(dev);
2698
2699 return 0;
2700
2701out_clk_disable:
2702 clk_disable_unprepare(priv->clk);
2703 return ret;
2704}
2705#endif /* CONFIG_PM_SLEEP */
2706
2707static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2708
1c1008c7
FF		 2709static struct platform_driver bcmgenet_driver = {
2710 .probe = bcmgenet_probe,
2711 .remove = bcmgenet_remove,
2712 .driver = {
2713 .name = "bcmgenet",
2714 .owner = THIS_MODULE,
2715 .of_match_table = bcmgenet_match,
b6e978e5 2716 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 2717 },
2718};
2719module_platform_driver(bcmgenet_driver);
2720
2721MODULE_AUTHOR("Broadcom Corporation");
2722MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2723MODULE_ALIAS("platform:bcmgenet");
2724MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)