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net: bcmgenet: rework Tx queue init
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
57#define GENET_DEFAULT_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
59
60#define RX_BUF_LENGTH 2048
61#define SKB_ALIGNMENT 32
62
63/* Tx/Rx DMA register offset, skip 256 descriptors */
64#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
65#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
66
67#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
68 TOTAL_DESC * DMA_DESC_SIZE)
69
70#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
71 TOTAL_DESC * DMA_DESC_SIZE)
72
73static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 74 void __iomem *d, u32 value)
1c1008c7
FF		 75{
76 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
77}
78
79static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 80 void __iomem *d)
1c1008c7
FF		 81{
82 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
83}
84
85static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
86 void __iomem *d,
87 dma_addr_t addr)
88{
89 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
90
91 /* Register writes to GISB bus can take couple hundred nanoseconds
92 * and are done for each packet, save these expensive writes unless
7fc527f9 93 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 94 */
95#ifdef CONFIG_PHYS_ADDR_T_64BIT
96 if (priv->hw_params->flags & GENET_HAS_40BITS)
97 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
98#endif
99}
100
101/* Combined address + length/status setter */
102static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 103 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 104{
105 dmadesc_set_length_status(priv, d, val);
106 dmadesc_set_addr(priv, d, addr);
107}
108
109static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
110 void __iomem *d)
111{
112 dma_addr_t addr;
113
114 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
115
116 /* Register writes to GISB bus can take couple hundred nanoseconds
117 * and are done for each packet, save these expensive writes unless
7fc527f9 118 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 119 */
120#ifdef CONFIG_PHYS_ADDR_T_64BIT
121 if (priv->hw_params->flags & GENET_HAS_40BITS)
122 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
123#endif
124 return addr;
125}
126
127#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
128
129#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
130 NETIF_MSG_LINK)
131
132static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
133{
134 if (GENET_IS_V1(priv))
135 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
136 else
137 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
138}
139
140static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
141{
142 if (GENET_IS_V1(priv))
143 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
144 else
145 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
146}
147
148/* These macros are defined to deal with register map change
149 * between GENET1.1 and GENET2. Only those currently being used
150 * by driver are defined.
151 */
152static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
153{
154 if (GENET_IS_V1(priv))
155 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
156 else
157 return __raw_readl(priv->base +
158 priv->hw_params->tbuf_offset + TBUF_CTRL);
159}
160
161static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
162{
163 if (GENET_IS_V1(priv))
164 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
165 else
166 __raw_writel(val, priv->base +
167 priv->hw_params->tbuf_offset + TBUF_CTRL);
168}
169
170static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
171{
172 if (GENET_IS_V1(priv))
173 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
174 else
175 return __raw_readl(priv->base +
176 priv->hw_params->tbuf_offset + TBUF_BP_MC);
177}
178
179static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
180{
181 if (GENET_IS_V1(priv))
182 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
183 else
184 __raw_writel(val, priv->base +
185 priv->hw_params->tbuf_offset + TBUF_BP_MC);
186}
187
188/* RX/TX DMA register accessors */
189enum dma_reg {
190 DMA_RING_CFG = 0,
191 DMA_CTRL,
192 DMA_STATUS,
193 DMA_SCB_BURST_SIZE,
194 DMA_ARB_CTRL,
37742166
PG		 195 DMA_PRIORITY_0,
196 DMA_PRIORITY_1,
197 DMA_PRIORITY_2,
1c1008c7
FF		 198};
199
200static const u8 bcmgenet_dma_regs_v3plus[] = {
201 [DMA_RING_CFG] = 0x00,
202 [DMA_CTRL] = 0x04,
203 [DMA_STATUS] = 0x08,
204 [DMA_SCB_BURST_SIZE] = 0x0C,
205 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 206 [DMA_PRIORITY_0] = 0x30,
207 [DMA_PRIORITY_1] = 0x34,
208 [DMA_PRIORITY_2] = 0x38,
1c1008c7
FF		 209};
210
211static const u8 bcmgenet_dma_regs_v2[] = {
212 [DMA_RING_CFG] = 0x00,
213 [DMA_CTRL] = 0x04,
214 [DMA_STATUS] = 0x08,
215 [DMA_SCB_BURST_SIZE] = 0x0C,
216 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 217 [DMA_PRIORITY_0] = 0x34,
218 [DMA_PRIORITY_1] = 0x38,
219 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 220};
221
222static const u8 bcmgenet_dma_regs_v1[] = {
223 [DMA_CTRL] = 0x00,
224 [DMA_STATUS] = 0x04,
225 [DMA_SCB_BURST_SIZE] = 0x0C,
226 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 227 [DMA_PRIORITY_0] = 0x34,
228 [DMA_PRIORITY_1] = 0x38,
229 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 230};
231
232/* Set at runtime once bcmgenet version is known */
233static const u8 *bcmgenet_dma_regs;
234
235static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
236{
237 return netdev_priv(dev_get_drvdata(dev));
238}
239
240static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 241 enum dma_reg r)
1c1008c7
FF		 242{
243 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
244 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
245}
246
247static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
248 u32 val, enum dma_reg r)
249{
250 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
251 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
252}
253
254static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 255 enum dma_reg r)
1c1008c7
FF		 256{
257 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
258 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
259}
260
261static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
262 u32 val, enum dma_reg r)
263{
264 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
265 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
266}
267
268/* RDMA/TDMA ring registers and accessors
269 * we merge the common fields and just prefix with T/D the registers
270 * having different meaning depending on the direction
271 */
272enum dma_ring_reg {
273 TDMA_READ_PTR = 0,
274 RDMA_WRITE_PTR = TDMA_READ_PTR,
275 TDMA_READ_PTR_HI,
276 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
277 TDMA_CONS_INDEX,
278 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
279 TDMA_PROD_INDEX,
280 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
281 DMA_RING_BUF_SIZE,
282 DMA_START_ADDR,
283 DMA_START_ADDR_HI,
284 DMA_END_ADDR,
285 DMA_END_ADDR_HI,
286 DMA_MBUF_DONE_THRESH,
287 TDMA_FLOW_PERIOD,
288 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
289 TDMA_WRITE_PTR,
290 RDMA_READ_PTR = TDMA_WRITE_PTR,
291 TDMA_WRITE_PTR_HI,
292 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
293};
294
295/* GENET v4 supports 40-bits pointer addressing
296 * for obvious reasons the LO and HI word parts
297 * are contiguous, but this offsets the other
298 * registers.
299 */
300static const u8 genet_dma_ring_regs_v4[] = {
301 [TDMA_READ_PTR] = 0x00,
302 [TDMA_READ_PTR_HI] = 0x04,
303 [TDMA_CONS_INDEX] = 0x08,
304 [TDMA_PROD_INDEX] = 0x0C,
305 [DMA_RING_BUF_SIZE] = 0x10,
306 [DMA_START_ADDR] = 0x14,
307 [DMA_START_ADDR_HI] = 0x18,
308 [DMA_END_ADDR] = 0x1C,
309 [DMA_END_ADDR_HI] = 0x20,
310 [DMA_MBUF_DONE_THRESH] = 0x24,
311 [TDMA_FLOW_PERIOD] = 0x28,
312 [TDMA_WRITE_PTR] = 0x2C,
313 [TDMA_WRITE_PTR_HI] = 0x30,
314};
315
316static const u8 genet_dma_ring_regs_v123[] = {
317 [TDMA_READ_PTR] = 0x00,
318 [TDMA_CONS_INDEX] = 0x04,
319 [TDMA_PROD_INDEX] = 0x08,
320 [DMA_RING_BUF_SIZE] = 0x0C,
321 [DMA_START_ADDR] = 0x10,
322 [DMA_END_ADDR] = 0x14,
323 [DMA_MBUF_DONE_THRESH] = 0x18,
324 [TDMA_FLOW_PERIOD] = 0x1C,
325 [TDMA_WRITE_PTR] = 0x20,
326};
327
328/* Set at runtime once GENET version is known */
329static const u8 *genet_dma_ring_regs;
330
331static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 332 unsigned int ring,
333 enum dma_ring_reg r)
1c1008c7
FF		 334{
335 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
336 (DMA_RING_SIZE * ring) +
337 genet_dma_ring_regs[r]);
338}
339
340static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 341 unsigned int ring, u32 val,
342 enum dma_ring_reg r)
1c1008c7
FF		 343{
344 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
345 (DMA_RING_SIZE * ring) +
346 genet_dma_ring_regs[r]);
347}
348
349static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 350 unsigned int ring,
351 enum dma_ring_reg r)
1c1008c7
FF		 352{
353 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
354 (DMA_RING_SIZE * ring) +
355 genet_dma_ring_regs[r]);
356}
357
358static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 359 unsigned int ring, u32 val,
360 enum dma_ring_reg r)
1c1008c7
FF		 361{
362 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
363 (DMA_RING_SIZE * ring) +
364 genet_dma_ring_regs[r]);
365}
366
367static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 368 struct ethtool_cmd *cmd)
1c1008c7
FF		 369{
370 struct bcmgenet_priv *priv = netdev_priv(dev);
371
372 if (!netif_running(dev))
373 return -EINVAL;
374
375 if (!priv->phydev)
376 return -ENODEV;
377
378 return phy_ethtool_gset(priv->phydev, cmd);
379}
380
381static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 382 struct ethtool_cmd *cmd)
1c1008c7
FF		 383{
384 struct bcmgenet_priv *priv = netdev_priv(dev);
385
386 if (!netif_running(dev))
387 return -EINVAL;
388
389 if (!priv->phydev)
390 return -ENODEV;
391
392 return phy_ethtool_sset(priv->phydev, cmd);
393}
394
395static int bcmgenet_set_rx_csum(struct net_device *dev,
396 netdev_features_t wanted)
397{
398 struct bcmgenet_priv *priv = netdev_priv(dev);
399 u32 rbuf_chk_ctrl;
400 bool rx_csum_en;
401
402 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
403
404 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
405
406 /* enable rx checksumming */
407 if (rx_csum_en)
408 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
409 else
410 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
411 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 412
413 /* If UniMAC forwards CRC, we need to skip over it to get
414 * a valid CHK bit to be set in the per-packet status word
415 */
416 if (rx_csum_en && priv->crc_fwd_en)
417 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
418 else
419 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
420
1c1008c7
FF		 421 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
422
423 return 0;
424}
425
426static int bcmgenet_set_tx_csum(struct net_device *dev,
427 netdev_features_t wanted)
428{
429 struct bcmgenet_priv *priv = netdev_priv(dev);
430 bool desc_64b_en;
431 u32 tbuf_ctrl, rbuf_ctrl;
432
433 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
434 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
435
436 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
437
438 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
439 if (desc_64b_en) {
440 tbuf_ctrl |= RBUF_64B_EN;
441 rbuf_ctrl |= RBUF_64B_EN;
442 } else {
443 tbuf_ctrl &= ~RBUF_64B_EN;
444 rbuf_ctrl &= ~RBUF_64B_EN;
445 }
446 priv->desc_64b_en = desc_64b_en;
447
448 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
449 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
450
451 return 0;
452}
453
454static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 455 netdev_features_t features)
1c1008c7
FF		 456{
457 netdev_features_t changed = features ^ dev->features;
458 netdev_features_t wanted = dev->wanted_features;
459 int ret = 0;
460
461 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
462 ret = bcmgenet_set_tx_csum(dev, wanted);
463 if (changed & (NETIF_F_RXCSUM))
464 ret = bcmgenet_set_rx_csum(dev, wanted);
465
466 return ret;
467}
468
469static u32 bcmgenet_get_msglevel(struct net_device *dev)
470{
471 struct bcmgenet_priv *priv = netdev_priv(dev);
472
473 return priv->msg_enable;
474}
475
476static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
477{
478 struct bcmgenet_priv *priv = netdev_priv(dev);
479
480 priv->msg_enable = level;
481}
482
483/* standard ethtool support functions. */
484enum bcmgenet_stat_type {
485 BCMGENET_STAT_NETDEV = -1,
486 BCMGENET_STAT_MIB_RX,
487 BCMGENET_STAT_MIB_TX,
488 BCMGENET_STAT_RUNT,
489 BCMGENET_STAT_MISC,
490};
491
492struct bcmgenet_stats {
493 char stat_string[ETH_GSTRING_LEN];
494 int stat_sizeof;
495 int stat_offset;
496 enum bcmgenet_stat_type type;
497 /* reg offset from UMAC base for misc counters */
498 u16 reg_offset;
499};
500
501#define STAT_NETDEV(m) { \
502 .stat_string = __stringify(m), \
503 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
504 .stat_offset = offsetof(struct net_device_stats, m), \
505 .type = BCMGENET_STAT_NETDEV, \
506}
507
508#define STAT_GENET_MIB(str, m, _type) { \
509 .stat_string = str, \
510 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
511 .stat_offset = offsetof(struct bcmgenet_priv, m), \
512 .type = _type, \
513}
514
515#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
516#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
517#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
518
519#define STAT_GENET_MISC(str, m, offset) { \
520 .stat_string = str, \
521 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
522 .stat_offset = offsetof(struct bcmgenet_priv, m), \
523 .type = BCMGENET_STAT_MISC, \
524 .reg_offset = offset, \
525}
526
527
528/* There is a 0xC gap between the end of RX and beginning of TX stats and then
529 * between the end of TX stats and the beginning of the RX RUNT
530 */
531#define BCMGENET_STAT_OFFSET 0xc
532
533/* Hardware counters must be kept in sync because the order/offset
534 * is important here (order in structure declaration = order in hardware)
535 */
536static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
537 /* general stats */
538 STAT_NETDEV(rx_packets),
539 STAT_NETDEV(tx_packets),
540 STAT_NETDEV(rx_bytes),
541 STAT_NETDEV(tx_bytes),
542 STAT_NETDEV(rx_errors),
543 STAT_NETDEV(tx_errors),
544 STAT_NETDEV(rx_dropped),
545 STAT_NETDEV(tx_dropped),
546 STAT_NETDEV(multicast),
547 /* UniMAC RSV counters */
548 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
549 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
550 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
551 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
552 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
553 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
554 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
555 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
556 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
557 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
558 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
559 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
560 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
561 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
562 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
563 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
564 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
565 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
566 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
567 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
568 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
569 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
570 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
571 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
572 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
573 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
574 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
575 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
576 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
577 /* UniMAC TSV counters */
578 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
579 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
580 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
581 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
582 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
583 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
584 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
585 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
586 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
587 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
588 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
589 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
590 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
591 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
592 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
593 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
594 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
595 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
596 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
597 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
598 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
599 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
600 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
601 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
602 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
603 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
604 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
605 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
606 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
607 /* UniMAC RUNT counters */
608 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
609 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
610 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
611 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
612 /* Misc UniMAC counters */
613 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
614 UMAC_RBUF_OVFL_CNT),
615 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
616 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
44c8bc3c
FF		 617 STAT_GENET_MIB_RX("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
618 STAT_GENET_MIB_RX("rx_dma_failed", mib.rx_dma_failed),
619 STAT_GENET_MIB_TX("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 620};
621
622#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
623
624static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 625 struct ethtool_drvinfo *info)
1c1008c7
FF		 626{
627 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
628 strlcpy(info->version, "v2.0", sizeof(info->version));
629 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 630}
631
632static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
633{
634 switch (string_set) {
635 case ETH_SS_STATS:
636 return BCMGENET_STATS_LEN;
637 default:
638 return -EOPNOTSUPP;
639 }
640}
641
c91b7f66
FF		 642static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
643 u8 *data)
1c1008c7
FF		 644{
645 int i;
646
647 switch (stringset) {
648 case ETH_SS_STATS:
649 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
650 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 651 bcmgenet_gstrings_stats[i].stat_string,
652 ETH_GSTRING_LEN);
1c1008c7
FF		 653 }
654 break;
655 }
656}
657
658static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
659{
660 int i, j = 0;
661
662 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
663 const struct bcmgenet_stats *s;
664 u8 offset = 0;
665 u32 val = 0;
666 char *p;
667
668 s = &bcmgenet_gstrings_stats[i];
669 switch (s->type) {
670 case BCMGENET_STAT_NETDEV:
671 continue;
672 case BCMGENET_STAT_MIB_RX:
673 case BCMGENET_STAT_MIB_TX:
674 case BCMGENET_STAT_RUNT:
675 if (s->type != BCMGENET_STAT_MIB_RX)
676 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 677 val = bcmgenet_umac_readl(priv,
678 UMAC_MIB_START + j + offset);
1c1008c7
FF		 679 break;
680 case BCMGENET_STAT_MISC:
681 val = bcmgenet_umac_readl(priv, s->reg_offset);
682 /* clear if overflowed */
683 if (val == ~0)
684 bcmgenet_umac_writel(priv, 0, s->reg_offset);
685 break;
686 }
687
688 j += s->stat_sizeof;
689 p = (char *)priv + s->stat_offset;
690 *(u32 *)p = val;
691 }
692}
693
694static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 695 struct ethtool_stats *stats,
696 u64 *data)
1c1008c7
FF		 697{
698 struct bcmgenet_priv *priv = netdev_priv(dev);
699 int i;
700
701 if (netif_running(dev))
702 bcmgenet_update_mib_counters(priv);
703
704 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
705 const struct bcmgenet_stats *s;
706 char *p;
707
708 s = &bcmgenet_gstrings_stats[i];
709 if (s->type == BCMGENET_STAT_NETDEV)
710 p = (char *)&dev->stats;
711 else
712 p = (char *)priv;
713 p += s->stat_offset;
714 data[i] = *(u32 *)p;
715 }
716}
717
6ef398ea
FF		 718static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
719{
720 struct bcmgenet_priv *priv = netdev_priv(dev);
721 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
722 u32 reg;
723
724 if (enable && !priv->clk_eee_enabled) {
725 clk_prepare_enable(priv->clk_eee);
726 priv->clk_eee_enabled = true;
727 }
728
729 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
730 if (enable)
731 reg |= EEE_EN;
732 else
733 reg &= ~EEE_EN;
734 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
735
736 /* Enable EEE and switch to a 27Mhz clock automatically */
737 reg = __raw_readl(priv->base + off);
738 if (enable)
739 reg |= TBUF_EEE_EN | TBUF_PM_EN;
740 else
741 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
742 __raw_writel(reg, priv->base + off);
743
744 /* Do the same for thing for RBUF */
745 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
746 if (enable)
747 reg |= RBUF_EEE_EN | RBUF_PM_EN;
748 else
749 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
750 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
751
752 if (!enable && priv->clk_eee_enabled) {
753 clk_disable_unprepare(priv->clk_eee);
754 priv->clk_eee_enabled = false;
755 }
756
757 priv->eee.eee_enabled = enable;
758 priv->eee.eee_active = enable;
759}
760
761static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
762{
763 struct bcmgenet_priv *priv = netdev_priv(dev);
764 struct ethtool_eee *p = &priv->eee;
765
766 if (GENET_IS_V1(priv))
767 return -EOPNOTSUPP;
768
769 e->eee_enabled = p->eee_enabled;
770 e->eee_active = p->eee_active;
771 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
772
773 return phy_ethtool_get_eee(priv->phydev, e);
774}
775
776static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
777{
778 struct bcmgenet_priv *priv = netdev_priv(dev);
779 struct ethtool_eee *p = &priv->eee;
780 int ret = 0;
781
782 if (GENET_IS_V1(priv))
783 return -EOPNOTSUPP;
784
785 p->eee_enabled = e->eee_enabled;
786
787 if (!p->eee_enabled) {
788 bcmgenet_eee_enable_set(dev, false);
789 } else {
790 ret = phy_init_eee(priv->phydev, 0);
791 if (ret) {
792 netif_err(priv, hw, dev, "EEE initialization failed\n");
793 return ret;
794 }
795
796 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
797 bcmgenet_eee_enable_set(dev, true);
798 }
799
800 return phy_ethtool_set_eee(priv->phydev, e);
801}
802
6b0c5406
FF		 803static int bcmgenet_nway_reset(struct net_device *dev)
804{
805 struct bcmgenet_priv *priv = netdev_priv(dev);
806
807 return genphy_restart_aneg(priv->phydev);
808}
809
1c1008c7
FF		 810/* standard ethtool support functions. */
811static struct ethtool_ops bcmgenet_ethtool_ops = {
812 .get_strings = bcmgenet_get_strings,
813 .get_sset_count = bcmgenet_get_sset_count,
814 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
815 .get_settings = bcmgenet_get_settings,
816 .set_settings = bcmgenet_set_settings,
817 .get_drvinfo = bcmgenet_get_drvinfo,
818 .get_link = ethtool_op_get_link,
819 .get_msglevel = bcmgenet_get_msglevel,
820 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 821 .get_wol = bcmgenet_get_wol,
822 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 823 .get_eee = bcmgenet_get_eee,
824 .set_eee = bcmgenet_set_eee,
6b0c5406 825 .nway_reset = bcmgenet_nway_reset,
1c1008c7
FF		 826};
827
828/* Power down the unimac, based on mode. */
829static void bcmgenet_power_down(struct bcmgenet_priv *priv,
830 enum bcmgenet_power_mode mode)
831{
832 u32 reg;
833
834 switch (mode) {
835 case GENET_POWER_CABLE_SENSE:
80d8e96d 836 phy_detach(priv->phydev);
1c1008c7
FF		 837 break;
838
c3ae64ae
FF		 839 case GENET_POWER_WOL_MAGIC:
840 bcmgenet_wol_power_down_cfg(priv, mode);
841 break;
842
1c1008c7
FF		 843 case GENET_POWER_PASSIVE:
844 /* Power down LED */
1c1008c7
FF		 845 if (priv->hw_params->flags & GENET_HAS_EXT) {
846 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
847 reg |= (EXT_PWR_DOWN_PHY |
848 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
849 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
850 }
851 break;
852 default:
853 break;
854 }
855}
856
857static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 858 enum bcmgenet_power_mode mode)
1c1008c7
FF		 859{
860 u32 reg;
861
862 if (!(priv->hw_params->flags & GENET_HAS_EXT))
863 return;
864
865 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
866
867 switch (mode) {
868 case GENET_POWER_PASSIVE:
869 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
870 EXT_PWR_DOWN_BIAS);
871 /* fallthrough */
872 case GENET_POWER_CABLE_SENSE:
873 /* enable APD */
874 reg |= EXT_PWR_DN_EN_LD;
875 break;
c3ae64ae
FF		 876 case GENET_POWER_WOL_MAGIC:
877 bcmgenet_wol_power_up_cfg(priv, mode);
878 return;
1c1008c7
FF		 879 default:
880 break;
881 }
882
883 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
cc013fb4
FF		 884
885 if (mode == GENET_POWER_PASSIVE)
886 bcmgenet_mii_reset(priv->dev);
1c1008c7
FF		 887}
888
889/* ioctl handle special commands that are not present in ethtool. */
890static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
891{
892 struct bcmgenet_priv *priv = netdev_priv(dev);
893 int val = 0;
894
895 if (!netif_running(dev))
896 return -EINVAL;
897
898 switch (cmd) {
899 case SIOCGMIIPHY:
900 case SIOCGMIIREG:
901 case SIOCSMIIREG:
902 if (!priv->phydev)
903 val = -ENODEV;
904 else
905 val = phy_mii_ioctl(priv->phydev, rq, cmd);
906 break;
907
908 default:
909 val = -EINVAL;
910 break;
911 }
912
913 return val;
914}
915
916static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
917 struct bcmgenet_tx_ring *ring)
918{
919 struct enet_cb *tx_cb_ptr;
920
921 tx_cb_ptr = ring->cbs;
922 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
923 tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
924 /* Advancing local write pointer */
925 if (ring->write_ptr == ring->end_ptr)
926 ring->write_ptr = ring->cb_ptr;
927 else
928 ring->write_ptr++;
929
930 return tx_cb_ptr;
931}
932
933/* Simple helper to free a control block's resources */
934static void bcmgenet_free_cb(struct enet_cb *cb)
935{
936 dev_kfree_skb_any(cb->skb);
937 cb->skb = NULL;
938 dma_unmap_addr_set(cb, dma_addr, 0);
939}
940
941static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
942 struct bcmgenet_tx_ring *ring)
943{
944 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 945 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
946 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 947}
948
949static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
950 struct bcmgenet_tx_ring *ring)
951{
952 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 953 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
954 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 955}
956
957static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
c91b7f66 958 struct bcmgenet_tx_ring *ring)
1c1008c7 959{
c91b7f66
FF		 960 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
961 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 962 priv->int1_mask &= ~(1 << ring->index);
963}
964
965static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
966 struct bcmgenet_tx_ring *ring)
967{
c91b7f66
FF		 968 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
969 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 970 priv->int1_mask |= (1 << ring->index);
971}
972
973/* Unlocked version of the reclaim routine */
974static void __bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 975 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 976{
977 struct bcmgenet_priv *priv = netdev_priv(dev);
978 int last_tx_cn, last_c_index, num_tx_bds;
979 struct enet_cb *tx_cb_ptr;
b2cde2cc 980 struct netdev_queue *txq;
478a010c 981 unsigned int bds_compl;
1c1008c7
FF		 982 unsigned int c_index;
983
7fc527f9 984 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 985 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
b2cde2cc 986 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 987
988 last_c_index = ring->c_index;
989 num_tx_bds = ring->size;
990
991 c_index &= (num_tx_bds - 1);
992
993 if (c_index >= last_c_index)
994 last_tx_cn = c_index - last_c_index;
995 else
996 last_tx_cn = num_tx_bds - last_c_index + c_index;
997
998 netif_dbg(priv, tx_done, dev,
c91b7f66
FF		 999 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
1000 __func__, ring->index,
1001 c_index, last_tx_cn, last_c_index);
1c1008c7
FF		 1002
1003 /* Reclaim transmitted buffers */
1004 while (last_tx_cn-- > 0) {
1005 tx_cb_ptr = ring->cbs + last_c_index;
478a010c 1006 bds_compl = 0;
1c1008c7 1007 if (tx_cb_ptr->skb) {
478a010c 1008 bds_compl = skb_shinfo(tx_cb_ptr->skb)->nr_frags + 1;
1c1008c7
FF		 1009 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1010 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1011 dma_unmap_addr(tx_cb_ptr, dma_addr),
1012 tx_cb_ptr->skb->len,
1013 DMA_TO_DEVICE);
1c1008c7
FF		 1014 bcmgenet_free_cb(tx_cb_ptr);
1015 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1016 dev->stats.tx_bytes +=
1017 dma_unmap_len(tx_cb_ptr, dma_len);
1018 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1019 dma_unmap_addr(tx_cb_ptr, dma_addr),
1020 dma_unmap_len(tx_cb_ptr, dma_len),
1021 DMA_TO_DEVICE);
1c1008c7
FF		 1022 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1023 }
1024 dev->stats.tx_packets++;
478a010c 1025 ring->free_bds += bds_compl;
1c1008c7
FF		 1026
1027 last_c_index++;
1028 last_c_index &= (num_tx_bds - 1);
1029 }
1030
1031 if (ring->free_bds > (MAX_SKB_FRAGS + 1))
1032 ring->int_disable(priv, ring);
1033
b2cde2cc
FF		 1034 if (netif_tx_queue_stopped(txq))
1035 netif_tx_wake_queue(txq);
1c1008c7
FF		 1036
1037 ring->c_index = c_index;
1038}
1039
1040static void bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1041 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1042{
1043 unsigned long flags;
1044
1045 spin_lock_irqsave(&ring->lock, flags);
1046 __bcmgenet_tx_reclaim(dev, ring);
1047 spin_unlock_irqrestore(&ring->lock, flags);
1048}
1049
1050static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1051{
1052 struct bcmgenet_priv *priv = netdev_priv(dev);
1053 int i;
1054
1055 if (netif_is_multiqueue(dev)) {
1056 for (i = 0; i < priv->hw_params->tx_queues; i++)
1057 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1058 }
1059
1060 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1061}
1062
1063/* Transmits a single SKB (either head of a fragment or a single SKB)
1064 * caller must hold priv->lock
1065 */
1066static int bcmgenet_xmit_single(struct net_device *dev,
1067 struct sk_buff *skb,
1068 u16 dma_desc_flags,
1069 struct bcmgenet_tx_ring *ring)
1070{
1071 struct bcmgenet_priv *priv = netdev_priv(dev);
1072 struct device *kdev = &priv->pdev->dev;
1073 struct enet_cb *tx_cb_ptr;
1074 unsigned int skb_len;
1075 dma_addr_t mapping;
1076 u32 length_status;
1077 int ret;
1078
1079 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1080
1081 if (unlikely(!tx_cb_ptr))
1082 BUG();
1083
1084 tx_cb_ptr->skb = skb;
1085
1086 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1087
1088 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1089 ret = dma_mapping_error(kdev, mapping);
1090 if (ret) {
44c8bc3c 1091 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1092 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1093 dev_kfree_skb(skb);
1094 return ret;
1095 }
1096
1097 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1098 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1099 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1100 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1101 DMA_TX_APPEND_CRC;
1102
1103 if (skb->ip_summed == CHECKSUM_PARTIAL)
1104 length_status |= DMA_TX_DO_CSUM;
1105
1106 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1107
1108 /* Decrement total BD count and advance our write pointer */
1109 ring->free_bds -= 1;
1110 ring->prod_index += 1;
1111 ring->prod_index &= DMA_P_INDEX_MASK;
1112
1113 return 0;
1114}
1115
7fc527f9 1116/* Transmit a SKB fragment */
1c1008c7 1117static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1118 skb_frag_t *frag,
1119 u16 dma_desc_flags,
1120 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1121{
1122 struct bcmgenet_priv *priv = netdev_priv(dev);
1123 struct device *kdev = &priv->pdev->dev;
1124 struct enet_cb *tx_cb_ptr;
1125 dma_addr_t mapping;
1126 int ret;
1127
1128 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1129
1130 if (unlikely(!tx_cb_ptr))
1131 BUG();
1132 tx_cb_ptr->skb = NULL;
1133
1134 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1135 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1136 ret = dma_mapping_error(kdev, mapping);
1137 if (ret) {
44c8bc3c 1138 priv->mib.tx_dma_failed++;
1c1008c7 1139 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1140 __func__);
1c1008c7
FF		 1141 return ret;
1142 }
1143
1144 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1145 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1146
1147 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1148 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1149 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7
FF		 1150
1151
1152 ring->free_bds -= 1;
1153 ring->prod_index += 1;
1154 ring->prod_index &= DMA_P_INDEX_MASK;
1155
1156 return 0;
1157}
1158
1159/* Reallocate the SKB to put enough headroom in front of it and insert
1160 * the transmit checksum offsets in the descriptors
1161 */
bc23333b
PG		 1162static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1163 struct sk_buff *skb)
1c1008c7
FF		 1164{
1165 struct status_64 *status = NULL;
1166 struct sk_buff *new_skb;
1167 u16 offset;
1168 u8 ip_proto;
1169 u16 ip_ver;
1170 u32 tx_csum_info;
1171
1172 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1173 /* If 64 byte status block enabled, must make sure skb has
1174 * enough headroom for us to insert 64B status block.
1175 */
1176 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1177 dev_kfree_skb(skb);
1178 if (!new_skb) {
1179 dev->stats.tx_errors++;
1180 dev->stats.tx_dropped++;
bc23333b 1181 return NULL;
1c1008c7
FF		 1182 }
1183 skb = new_skb;
1184 }
1185
1186 skb_push(skb, sizeof(*status));
1187 status = (struct status_64 *)skb->data;
1188
1189 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1190 ip_ver = htons(skb->protocol);
1191 switch (ip_ver) {
1192 case ETH_P_IP:
1193 ip_proto = ip_hdr(skb)->protocol;
1194 break;
1195 case ETH_P_IPV6:
1196 ip_proto = ipv6_hdr(skb)->nexthdr;
1197 break;
1198 default:
bc23333b 1199 return skb;
1c1008c7
FF		 1200 }
1201
1202 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1203 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1204 (offset + skb->csum_offset);
1205
1206 /* Set the length valid bit for TCP and UDP and just set
1207 * the special UDP flag for IPv4, else just set to 0.
1208 */
1209 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1210 tx_csum_info |= STATUS_TX_CSUM_LV;
1211 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1212 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1213 } else {
1c1008c7 1214 tx_csum_info = 0;
8900ea57 1215 }
1c1008c7
FF		 1216
1217 status->tx_csum_info = tx_csum_info;
1218 }
1219
bc23333b 1220 return skb;
1c1008c7
FF		 1221}
1222
1223static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1224{
1225 struct bcmgenet_priv *priv = netdev_priv(dev);
1226 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1227 struct netdev_queue *txq;
1c1008c7
FF		 1228 unsigned long flags = 0;
1229 int nr_frags, index;
1230 u16 dma_desc_flags;
1231 int ret;
1232 int i;
1233
1234 index = skb_get_queue_mapping(skb);
1235 /* Mapping strategy:
1236 * queue_mapping = 0, unclassified, packet xmited through ring16
1237 * queue_mapping = 1, goes to ring 0. (highest priority queue
1238 * queue_mapping = 2, goes to ring 1.
1239 * queue_mapping = 3, goes to ring 2.
1240 * queue_mapping = 4, goes to ring 3.
1241 */
1242 if (index == 0)
1243 index = DESC_INDEX;
1244 else
1245 index -= 1;
1246
1c1008c7
FF		 1247 nr_frags = skb_shinfo(skb)->nr_frags;
1248 ring = &priv->tx_rings[index];
b2cde2cc 1249 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1250
1251 spin_lock_irqsave(&ring->lock, flags);
1252 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1253 netif_tx_stop_queue(txq);
1c1008c7 1254 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1255 __func__, index, ring->queue);
1c1008c7
FF		 1256 ret = NETDEV_TX_BUSY;
1257 goto out;
1258 }
1259
474ea9ca
FF		 1260 if (skb_padto(skb, ETH_ZLEN)) {
1261 ret = NETDEV_TX_OK;
1262 goto out;
1263 }
1264
1c1008c7
FF		 1265 /* set the SKB transmit checksum */
1266 if (priv->desc_64b_en) {
bc23333b
PG		 1267 skb = bcmgenet_put_tx_csum(dev, skb);
1268 if (!skb) {
1c1008c7
FF		 1269 ret = NETDEV_TX_OK;
1270 goto out;
1271 }
1272 }
1273
1274 dma_desc_flags = DMA_SOP;
1275 if (nr_frags == 0)
1276 dma_desc_flags |= DMA_EOP;
1277
1278 /* Transmit single SKB or head of fragment list */
1279 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1280 if (ret) {
1281 ret = NETDEV_TX_OK;
1282 goto out;
1283 }
1284
1285 /* xmit fragment */
1286 for (i = 0; i < nr_frags; i++) {
1287 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1288 &skb_shinfo(skb)->frags[i],
1289 (i == nr_frags - 1) ? DMA_EOP : 0,
1290 ring);
1c1008c7
FF		 1291 if (ret) {
1292 ret = NETDEV_TX_OK;
1293 goto out;
1294 }
1295 }
1296
d03825fb
FF		 1297 skb_tx_timestamp(skb);
1298
1c1008c7
FF		 1299 /* we kept a software copy of how much we should advance the TDMA
1300 * producer index, now write it down to the hardware
1301 */
1302 bcmgenet_tdma_ring_writel(priv, ring->index,
c91b7f66 1303 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1304
1305 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
b2cde2cc 1306 netif_tx_stop_queue(txq);
1c1008c7
FF		 1307 ring->int_enable(priv, ring);
1308 }
1309
1310out:
1311 spin_unlock_irqrestore(&ring->lock, flags);
1312
1313 return ret;
1314}
1315
1316
c91b7f66 1317static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1c1008c7
FF		 1318{
1319 struct device *kdev = &priv->pdev->dev;
1320 struct sk_buff *skb;
1321 dma_addr_t mapping;
1322 int ret;
1323
c91b7f66 1324 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1c1008c7
FF		 1325 if (!skb)
1326 return -ENOMEM;
1327
1328 /* a caller did not release this control block */
1329 WARN_ON(cb->skb != NULL);
1330 cb->skb = skb;
1331 mapping = dma_map_single(kdev, skb->data,
c91b7f66 1332 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1333 ret = dma_mapping_error(kdev, mapping);
1334 if (ret) {
44c8bc3c 1335 priv->mib.rx_dma_failed++;
1c1008c7
FF		 1336 bcmgenet_free_cb(cb);
1337 netif_err(priv, rx_err, priv->dev,
c91b7f66 1338 "%s DMA map failed\n", __func__);
1c1008c7
FF		 1339 return ret;
1340 }
1341
1342 dma_unmap_addr_set(cb, dma_addr, mapping);
1343 /* assign packet, prepare descriptor, and advance pointer */
1344
1345 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1346
1347 /* turn on the newly assigned BD for DMA to use */
1348 priv->rx_bd_assign_index++;
1349 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1350
1351 priv->rx_bd_assign_ptr = priv->rx_bds +
1352 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1353
1354 return 0;
1355}
1356
1357/* bcmgenet_desc_rx - descriptor based rx process.
1358 * this could be called from bottom half, or from NAPI polling method.
1359 */
1360static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1361 unsigned int budget)
1362{
1363 struct net_device *dev = priv->dev;
1364 struct enet_cb *cb;
1365 struct sk_buff *skb;
1366 u32 dma_length_status;
1367 unsigned long dma_flag;
1368 int len, err;
1369 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1370 unsigned int p_index;
1371 unsigned int chksum_ok = 0;
1372
c91b7f66 1373 p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX);
1c1008c7
FF		 1374 p_index &= DMA_P_INDEX_MASK;
1375
1376 if (p_index < priv->rx_c_index)
1377 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1378 priv->rx_c_index + p_index;
1379 else
1380 rxpkttoprocess = p_index - priv->rx_c_index;
1381
1382 netif_dbg(priv, rx_status, dev,
c91b7f66 1383 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1384
1385 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1386 (rxpktprocessed < budget)) {
b629be5c
FF		 1387 cb = &priv->rx_cbs[priv->rx_read_ptr];
1388 skb = cb->skb;
1389
b629be5c
FF		 1390 /* We do not have a backing SKB, so we do not have a
1391 * corresponding DMA mapping for this incoming packet since
1392 * bcmgenet_rx_refill always either has both skb and mapping or
1393 * none.
1394 */
1395 if (unlikely(!skb)) {
1396 dev->stats.rx_dropped++;
1397 dev->stats.rx_errors++;
1398 goto refill;
1399 }
1400
1c1008c7
FF		 1401 /* Unmap the packet contents such that we can use the
1402 * RSV from the 64 bytes descriptor when enabled and save
1403 * a 32-bits register read
1404 */
1c1008c7 1405 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
c91b7f66 1406 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1407
1408 if (!priv->desc_64b_en) {
c91b7f66
FF		 1409 dma_length_status =
1410 dmadesc_get_length_status(priv,
1411 priv->rx_bds +
1412 (priv->rx_read_ptr *
1413 DMA_DESC_SIZE));
1c1008c7
FF		 1414 } else {
1415 struct status_64 *status;
164d4f20 1416
1c1008c7
FF		 1417 status = (struct status_64 *)skb->data;
1418 dma_length_status = status->length_status;
1419 }
1420
1421 /* DMA flags and length are still valid no matter how
1422 * we got the Receive Status Vector (64B RSB or register)
1423 */
1424 dma_flag = dma_length_status & 0xffff;
1425 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1426
1427 netif_dbg(priv, rx_status, dev,
c91b7f66
FF		 1428 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1429 __func__, p_index, priv->rx_c_index,
1430 priv->rx_read_ptr, dma_length_status);
1c1008c7 1431
1c1008c7
FF		 1432 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1433 netif_err(priv, rx_status, dev,
c91b7f66 1434 "dropping fragmented packet!\n");
1c1008c7
FF		 1435 dev->stats.rx_dropped++;
1436 dev->stats.rx_errors++;
1437 dev_kfree_skb_any(cb->skb);
1438 cb->skb = NULL;
1439 goto refill;
1440 }
1441 /* report errors */
1442 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1443 DMA_RX_OV |
1444 DMA_RX_NO |
1445 DMA_RX_LG |
1446 DMA_RX_RXER))) {
1447 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1448 (unsigned int)dma_flag);
1c1008c7
FF		 1449 if (dma_flag & DMA_RX_CRC_ERROR)
1450 dev->stats.rx_crc_errors++;
1451 if (dma_flag & DMA_RX_OV)
1452 dev->stats.rx_over_errors++;
1453 if (dma_flag & DMA_RX_NO)
1454 dev->stats.rx_frame_errors++;
1455 if (dma_flag & DMA_RX_LG)
1456 dev->stats.rx_length_errors++;
1457 dev->stats.rx_dropped++;
1458 dev->stats.rx_errors++;
1459
1460 /* discard the packet and advance consumer index.*/
1461 dev_kfree_skb_any(cb->skb);
1462 cb->skb = NULL;
1463 goto refill;
1464 } /* error packet */
1465
1466 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1467 priv->desc_rxchk_en;
1c1008c7
FF		 1468
1469 skb_put(skb, len);
1470 if (priv->desc_64b_en) {
1471 skb_pull(skb, 64);
1472 len -= 64;
1473 }
1474
1475 if (likely(chksum_ok))
1476 skb->ip_summed = CHECKSUM_UNNECESSARY;
1477
1478 /* remove hardware 2bytes added for IP alignment */
1479 skb_pull(skb, 2);
1480 len -= 2;
1481
1482 if (priv->crc_fwd_en) {
1483 skb_trim(skb, len - ETH_FCS_LEN);
1484 len -= ETH_FCS_LEN;
1485 }
1486
1487 /*Finish setting up the received SKB and send it to the kernel*/
1488 skb->protocol = eth_type_trans(skb, priv->dev);
1489 dev->stats.rx_packets++;
1490 dev->stats.rx_bytes += len;
1491 if (dma_flag & DMA_RX_MULT)
1492 dev->stats.multicast++;
1493
1494 /* Notify kernel */
1495 napi_gro_receive(&priv->napi, skb);
1496 cb->skb = NULL;
1497 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1498
1499 /* refill RX path on the current control block */
1500refill:
1501 err = bcmgenet_rx_refill(priv, cb);
44c8bc3c
FF		 1502 if (err) {
1503 priv->mib.alloc_rx_buff_failed++;
1c1008c7 1504 netif_err(priv, rx_err, dev, "Rx refill failed\n");
44c8bc3c 1505 }
cf377d88
FF		 1506
1507 rxpktprocessed++;
1508 priv->rx_read_ptr++;
1509 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1c1008c7
FF		 1510 }
1511
1512 return rxpktprocessed;
1513}
1514
1515/* Assign skb to RX DMA descriptor. */
1516static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1517{
1518 struct enet_cb *cb;
1519 int ret = 0;
1520 int i;
1521
1522 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1523
1524 /* loop here for each buffer needing assign */
1525 for (i = 0; i < priv->num_rx_bds; i++) {
1526 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1527 if (cb->skb)
1528 continue;
1529
1c1008c7
FF		 1530 ret = bcmgenet_rx_refill(priv, cb);
1531 if (ret)
1532 break;
1c1008c7
FF		 1533 }
1534
1535 return ret;
1536}
1537
1538static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1539{
1540 struct enet_cb *cb;
1541 int i;
1542
1543 for (i = 0; i < priv->num_rx_bds; i++) {
1544 cb = &priv->rx_cbs[i];
1545
1546 if (dma_unmap_addr(cb, dma_addr)) {
1547 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1548 dma_unmap_addr(cb, dma_addr),
1549 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1550 dma_unmap_addr_set(cb, dma_addr, 0);
1551 }
1552
1553 if (cb->skb)
1554 bcmgenet_free_cb(cb);
1555 }
1556}
1557
c91b7f66 1558static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1559{
1560 u32 reg;
1561
1562 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1563 if (enable)
1564 reg |= mask;
1565 else
1566 reg &= ~mask;
1567 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1568
1569 /* UniMAC stops on a packet boundary, wait for a full-size packet
1570 * to be processed
1571 */
1572 if (enable == 0)
1573 usleep_range(1000, 2000);
1574}
1575
1c1008c7
FF		 1576static int reset_umac(struct bcmgenet_priv *priv)
1577{
1578 struct device *kdev = &priv->pdev->dev;
1579 unsigned int timeout = 0;
1580 u32 reg;
1581
1582 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1583 bcmgenet_rbuf_ctrl_set(priv, 0);
1584 udelay(10);
1585
1586 /* disable MAC while updating its registers */
1587 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1588
1589 /* issue soft reset, wait for it to complete */
1590 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1591 while (timeout++ < 1000) {
1592 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1593 if (!(reg & CMD_SW_RESET))
1594 return 0;
1595
1596 udelay(1);
1597 }
1598
1599 if (timeout == 1000) {
1600 dev_err(kdev,
7fc527f9 1601 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1602 return -ETIMEDOUT;
1603 }
1604
1605 return 0;
1606}
1607
909ff5ef
FF		 1608static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1609{
1610 /* Mask all interrupts.*/
1611 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1612 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1613 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1614 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1615 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1616 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1617}
1618
1c1008c7
FF		 1619static int init_umac(struct bcmgenet_priv *priv)
1620{
1621 struct device *kdev = &priv->pdev->dev;
1622 int ret;
1623 u32 reg, cpu_mask_clear;
1624
1625 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1626
1627 ret = reset_umac(priv);
1628 if (ret)
1629 return ret;
1630
1631 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1632 /* clear tx/rx counter */
1633 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1634 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1635 UMAC_MIB_CTRL);
1c1008c7
FF		 1636 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1637
1638 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1639
1640 /* init rx registers, enable ip header optimization */
1641 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1642 reg |= RBUF_ALIGN_2B;
1643 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1644
1645 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1646 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1647
909ff5ef 1648 bcmgenet_intr_disable(priv);
1c1008c7
FF		 1649
1650 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1651
1652 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1653
7fc527f9 1654 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1655 if (phy_is_internal(priv->phydev)) {
1c1008c7 1656 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1657 } else if (priv->ext_phy) {
1c1008c7 1658 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1659 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1660 reg = bcmgenet_bp_mc_get(priv);
1661 reg |= BIT(priv->hw_params->bp_in_en_shift);
1662
1663 /* bp_mask: back pressure mask */
1664 if (netif_is_multiqueue(priv->dev))
1665 reg |= priv->hw_params->bp_in_mask;
1666 else
1667 reg &= ~priv->hw_params->bp_in_mask;
1668 bcmgenet_bp_mc_set(priv, reg);
1669 }
1670
1671 /* Enable MDIO interrupts on GENET v3+ */
1672 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1673 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1674
c91b7f66 1675 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1676
1677 /* Enable rx/tx engine.*/
1678 dev_dbg(kdev, "done init umac\n");
1679
1680 return 0;
1681}
1682
4f8b2d7d 1683/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1684static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1685 unsigned int index, unsigned int size,
4f8b2d7d 1686 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1687{
1688 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1689 u32 words_per_bd = WORDS_PER_BD(priv);
1690 u32 flow_period_val = 0;
1c1008c7
FF		 1691
1692 spin_lock_init(&ring->lock);
1693 ring->index = index;
1694 if (index == DESC_INDEX) {
1695 ring->queue = 0;
1696 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1697 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1698 } else {
1699 ring->queue = index + 1;
1700 ring->int_enable = bcmgenet_tx_ring_int_enable;
1701 ring->int_disable = bcmgenet_tx_ring_int_disable;
1702 }
4f8b2d7d 1703 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7
FF		 1704 ring->size = size;
1705 ring->c_index = 0;
1706 ring->free_bds = size;
4f8b2d7d
PG		 1707 ring->write_ptr = start_ptr;
1708 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1709 ring->end_ptr = end_ptr - 1;
1710 ring->prod_index = 0;
1711
1712 /* Set flow period for ring != 16 */
1713 if (index != DESC_INDEX)
1714 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1715
1716 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1717 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1718 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1719 /* Disable rate control for now */
1720 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1721 TDMA_FLOW_PERIOD);
1c1008c7 1722 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1723 ((size << DMA_RING_SIZE_SHIFT) |
1724 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1725
1c1008c7 1726 /* Set start and end address, read and write pointers */
4f8b2d7d 1727 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1728 DMA_START_ADDR);
4f8b2d7d 1729 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1730 TDMA_READ_PTR);
4f8b2d7d 1731 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1732 TDMA_WRITE_PTR);
1c1008c7 1733 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1734 DMA_END_ADDR);
1c1008c7
FF		 1735}
1736
1737/* Initialize a RDMA ring */
1738static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
c91b7f66 1739 unsigned int index, unsigned int size)
1c1008c7
FF		 1740{
1741 u32 words_per_bd = WORDS_PER_BD(priv);
1742 int ret;
1743
1744 priv->num_rx_bds = TOTAL_DESC;
1745 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1746 priv->rx_bd_assign_ptr = priv->rx_bds;
1747 priv->rx_bd_assign_index = 0;
1748 priv->rx_c_index = 0;
1749 priv->rx_read_ptr = 0;
c489be08
FF		 1750 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
1751 GFP_KERNEL);
1c1008c7
FF		 1752 if (!priv->rx_cbs)
1753 return -ENOMEM;
1754
1755 ret = bcmgenet_alloc_rx_buffers(priv);
1756 if (ret) {
1757 kfree(priv->rx_cbs);
1758 return ret;
1759 }
1760
1761 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1762 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1763 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1764 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1765 ((size << DMA_RING_SIZE_SHIFT) |
1766 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7
FF		 1767 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1768 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66 1769 words_per_bd * size - 1, DMA_END_ADDR);
1c1008c7 1770 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1771 (DMA_FC_THRESH_LO <<
1772 DMA_XOFF_THRESHOLD_SHIFT) |
1773 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1c1008c7
FF		 1774 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1775
1776 return ret;
1777}
1778
16c6d667 1779/* Initialize Tx queues
1c1008c7 1780 *
16c6d667 1781 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 1782 * with queue 0 being the highest priority queue.
1783 *
16c6d667
PG		 1784 * Queue 16 is the default Tx queue with
1785 * GENET_DEFAULT_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 1786 *
16c6d667
PG		 1787 * The transmit control block pool is then partitioned as follows:
1788 * - Tx queue 0 uses tx_cbs[0..31]
1789 * - Tx queue 1 uses tx_cbs[32..63]
1790 * - Tx queue 2 uses tx_cbs[64..95]
1791 * - Tx queue 3 uses tx_cbs[96..127]
1792 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 1793 */
16c6d667 1794static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 1795{
1796 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 1797 u32 i, dma_enable;
1798 u32 dma_ctrl, ring_cfg;
37742166 1799 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 1800
1c1008c7
FF		 1801 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1802 dma_enable = dma_ctrl & DMA_EN;
1803 dma_ctrl &= ~DMA_EN;
1804 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1805
16c6d667
PG		 1806 dma_ctrl = 0;
1807 ring_cfg = 0;
1808
1c1008c7
FF		 1809 /* Enable strict priority arbiter mode */
1810 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1811
16c6d667 1812 /* Initialize Tx priority queues */
1c1008c7 1813 for (i = 0; i < priv->hw_params->tx_queues; i++) {
1c1008c7 1814 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
c91b7f66
FF		 1815 i * priv->hw_params->bds_cnt,
1816 (i + 1) * priv->hw_params->bds_cnt);
16c6d667
PG		 1817 ring_cfg |= (1 << i);
1818 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1819 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1820 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 1821 }
1822
16c6d667
PG		 1823 /* Initialize Tx default queue 16 */
1824 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1825 priv->hw_params->tx_queues *
1826 priv->hw_params->bds_cnt,
1827 TOTAL_DESC);
1828 ring_cfg |= (1 << DESC_INDEX);
1829 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1830 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1831 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1832 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 1833
1834 /* Set Tx queue priorities */
37742166
PG		 1835 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1836 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1837 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1838
16c6d667
PG		 1839 /* Enable Tx queues */
1840 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 1841
16c6d667 1842 /* Enable Tx DMA */
1c1008c7 1843 if (dma_enable)
16c6d667
PG		 1844 dma_ctrl |= DMA_EN;
1845 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 1846}
1847
4a0c081e
FF		 1848static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1849{
1850 int ret = 0;
1851 int timeout = 0;
1852 u32 reg;
1853
1854 /* Disable TDMA to stop add more frames in TX DMA */
1855 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1856 reg &= ~DMA_EN;
1857 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1858
1859 /* Check TDMA status register to confirm TDMA is disabled */
1860 while (timeout++ < DMA_TIMEOUT_VAL) {
1861 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1862 if (reg & DMA_DISABLED)
1863 break;
1864
1865 udelay(1);
1866 }
1867
1868 if (timeout == DMA_TIMEOUT_VAL) {
1869 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1870 ret = -ETIMEDOUT;
1871 }
1872
1873 /* Wait 10ms for packet drain in both tx and rx dma */
1874 usleep_range(10000, 20000);
1875
1876 /* Disable RDMA */
1877 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1878 reg &= ~DMA_EN;
1879 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1880
1881 timeout = 0;
1882 /* Check RDMA status register to confirm RDMA is disabled */
1883 while (timeout++ < DMA_TIMEOUT_VAL) {
1884 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
1885 if (reg & DMA_DISABLED)
1886 break;
1887
1888 udelay(1);
1889 }
1890
1891 if (timeout == DMA_TIMEOUT_VAL) {
1892 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
1893 ret = -ETIMEDOUT;
1894 }
1895
1896 return ret;
1897}
1898
1c1008c7
FF		 1899static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1900{
1901 int i;
1902
1903 /* disable DMA */
4a0c081e 1904 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 1905
1906 for (i = 0; i < priv->num_tx_bds; i++) {
1907 if (priv->tx_cbs[i].skb != NULL) {
1908 dev_kfree_skb(priv->tx_cbs[i].skb);
1909 priv->tx_cbs[i].skb = NULL;
1910 }
1911 }
1912
1913 bcmgenet_free_rx_buffers(priv);
1914 kfree(priv->rx_cbs);
1915 kfree(priv->tx_cbs);
1916}
1917
1918/* init_edma: Initialize DMA control register */
1919static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1920{
1921 int ret;
1922
1923 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1924
1925 /* by default, enable ring 16 (descriptor based) */
1926 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1927 if (ret) {
1928 netdev_err(priv->dev, "failed to initialize RX ring\n");
1929 return ret;
1930 }
1931
1932 /* init rDma */
1933 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1934
1935 /* Init tDma */
1936 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1937
7fc527f9 1938 /* Initialize common TX ring structures */
1c1008c7
FF		 1939 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1940 priv->num_tx_bds = TOTAL_DESC;
c489be08 1941 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 1942 GFP_KERNEL);
1c1008c7
FF		 1943 if (!priv->tx_cbs) {
1944 bcmgenet_fini_dma(priv);
1945 return -ENOMEM;
1946 }
1947
16c6d667
PG		 1948 /* Initialize Tx queues */
1949 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 1950
1951 return 0;
1952}
1953
1954/* NAPI polling method*/
1955static int bcmgenet_poll(struct napi_struct *napi, int budget)
1956{
1957 struct bcmgenet_priv *priv = container_of(napi,
1958 struct bcmgenet_priv, napi);
1959 unsigned int work_done;
1960
1961 /* tx reclaim */
1962 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1963
1964 work_done = bcmgenet_desc_rx(priv, budget);
1965
1966 /* Advancing our consumer index*/
1967 priv->rx_c_index += work_done;
1968 priv->rx_c_index &= DMA_C_INDEX_MASK;
1969 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
c91b7f66 1970 priv->rx_c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1971 if (work_done < budget) {
1972 napi_complete(napi);
c91b7f66
FF		 1973 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
1974 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1975 }
1976
1977 return work_done;
1978}
1979
1980/* Interrupt bottom half */
1981static void bcmgenet_irq_task(struct work_struct *work)
1982{
1983 struct bcmgenet_priv *priv = container_of(
1984 work, struct bcmgenet_priv, bcmgenet_irq_work);
1985
1986 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1987
8fdb0e0f
FF		 1988 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
1989 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
1990 netif_dbg(priv, wol, priv->dev,
1991 "magic packet detected, waking up\n");
1992 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
1993 }
1994
1c1008c7
FF		 1995 /* Link UP/DOWN event */
1996 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 1997 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d 1998 phy_mac_interrupt(priv->phydev,
c91b7f66 1999 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 2000 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
2001 }
2002}
2003
2004/* bcmgenet_isr1: interrupt handler for ring buffer. */
2005static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2006{
2007 struct bcmgenet_priv *priv = dev_id;
2008 unsigned int index;
2009
2010 /* Save irq status for bottom-half processing. */
2011 priv->irq1_stat =
2012 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2013 ~priv->int1_mask;
7fc527f9 2014 /* clear interrupts */
1c1008c7
FF		 2015 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2016
2017 netif_dbg(priv, intr, priv->dev,
c91b7f66 2018 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1c1008c7
FF		 2019 /* Check the MBDONE interrupts.
2020 * packet is done, reclaim descriptors
2021 */
2022 if (priv->irq1_stat & 0x0000ffff) {
2023 index = 0;
2024 for (index = 0; index < 16; index++) {
2025 if (priv->irq1_stat & (1 << index))
2026 bcmgenet_tx_reclaim(priv->dev,
c91b7f66 2027 &priv->tx_rings[index]);
1c1008c7
FF		 2028 }
2029 }
2030 return IRQ_HANDLED;
2031}
2032
2033/* bcmgenet_isr0: Handle various interrupts. */
2034static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2035{
2036 struct bcmgenet_priv *priv = dev_id;
2037
2038 /* Save irq status for bottom-half processing. */
2039 priv->irq0_stat =
2040 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2041 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2042 /* clear interrupts */
1c1008c7
FF		 2043 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2044
2045 netif_dbg(priv, intr, priv->dev,
c91b7f66 2046 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7
FF		 2047
2048 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
2049 /* We use NAPI(software interrupt throttling, if
2050 * Rx Descriptor throttling is not used.
2051 * Disable interrupt, will be enabled in the poll method.
2052 */
2053 if (likely(napi_schedule_prep(&priv->napi))) {
c91b7f66
FF		 2054 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2055 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 2056 __napi_schedule(&priv->napi);
2057 }
2058 }
2059 if (priv->irq0_stat &
2060 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
2061 /* Tx reclaim */
2062 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
2063 }
2064 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2065 UMAC_IRQ_PHY_DET_F |
2066 UMAC_IRQ_LINK_UP |
2067 UMAC_IRQ_LINK_DOWN |
2068 UMAC_IRQ_HFB_SM |
2069 UMAC_IRQ_HFB_MM |
2070 UMAC_IRQ_MPD_R)) {
2071 /* all other interested interrupts handled in bottom half */
2072 schedule_work(&priv->bcmgenet_irq_work);
2073 }
2074
2075 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2076 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2077 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2078 wake_up(&priv->wq);
2079 }
2080
2081 return IRQ_HANDLED;
2082}
2083
8562056f
FF		 2084static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2085{
2086 struct bcmgenet_priv *priv = dev_id;
2087
2088 pm_wakeup_event(&priv->pdev->dev, 0);
2089
2090 return IRQ_HANDLED;
2091}
2092
1c1008c7
FF		 2093static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2094{
2095 u32 reg;
2096
2097 reg = bcmgenet_rbuf_ctrl_get(priv);
2098 reg |= BIT(1);
2099 bcmgenet_rbuf_ctrl_set(priv, reg);
2100 udelay(10);
2101
2102 reg &= ~BIT(1);
2103 bcmgenet_rbuf_ctrl_set(priv, reg);
2104 udelay(10);
2105}
2106
2107static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2108 unsigned char *addr)
1c1008c7
FF		 2109{
2110 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2111 (addr[2] << 8) | addr[3], UMAC_MAC0);
2112 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2113}
2114
1c1008c7
FF		 2115/* Returns a reusable dma control register value */
2116static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2117{
2118 u32 reg;
2119 u32 dma_ctrl;
2120
2121 /* disable DMA */
2122 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2123 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2124 reg &= ~dma_ctrl;
2125 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2126
2127 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2128 reg &= ~dma_ctrl;
2129 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2130
2131 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2132 udelay(10);
2133 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2134
2135 return dma_ctrl;
2136}
2137
2138static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2139{
2140 u32 reg;
2141
2142 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2143 reg |= dma_ctrl;
2144 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2145
2146 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2147 reg |= dma_ctrl;
2148 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2149}
2150
909ff5ef
FF		 2151static void bcmgenet_netif_start(struct net_device *dev)
2152{
2153 struct bcmgenet_priv *priv = netdev_priv(dev);
2154
2155 /* Start the network engine */
2156 napi_enable(&priv->napi);
2157
2158 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2159
2160 if (phy_is_internal(priv->phydev))
2161 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2162
2163 netif_tx_start_all_queues(dev);
2164
2165 phy_start(priv->phydev);
2166}
2167
1c1008c7
FF		 2168static int bcmgenet_open(struct net_device *dev)
2169{
2170 struct bcmgenet_priv *priv = netdev_priv(dev);
2171 unsigned long dma_ctrl;
2172 u32 reg;
2173 int ret;
2174
2175 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2176
2177 /* Turn on the clock */
2178 if (!IS_ERR(priv->clk))
2179 clk_prepare_enable(priv->clk);
2180
2181 /* take MAC out of reset */
2182 bcmgenet_umac_reset(priv);
2183
2184 ret = init_umac(priv);
2185 if (ret)
2186 goto err_clk_disable;
2187
2188 /* disable ethernet MAC while updating its registers */
e29585b8 2189 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2190
909ff5ef
FF		 2191 /* Make sure we reflect the value of CRC_CMD_FWD */
2192 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2193 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2194
1c1008c7
FF		 2195 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2196
1c1008c7
FF		 2197 if (phy_is_internal(priv->phydev)) {
2198 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2199 reg |= EXT_ENERGY_DET_MASK;
2200 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2201 }
2202
2203 /* Disable RX/TX DMA and flush TX queues */
2204 dma_ctrl = bcmgenet_dma_disable(priv);
2205
2206 /* Reinitialize TDMA and RDMA and SW housekeeping */
2207 ret = bcmgenet_init_dma(priv);
2208 if (ret) {
2209 netdev_err(dev, "failed to initialize DMA\n");
2210 goto err_fini_dma;
2211 }
2212
2213 /* Always enable ring 16 - descriptor ring */
2214 bcmgenet_enable_dma(priv, dma_ctrl);
2215
2216 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2217 dev->name, priv);
1c1008c7
FF		 2218 if (ret < 0) {
2219 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2220 goto err_fini_dma;
2221 }
2222
2223 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2224 dev->name, priv);
1c1008c7
FF		 2225 if (ret < 0) {
2226 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2227 goto err_irq0;
2228 }
2229
dbd479db
FF		 2230 /* Re-configure the port multiplexer towards the PHY device */
2231 bcmgenet_mii_config(priv->dev, false);
2232
c96e731c
FF		 2233 phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2234 priv->phy_interface);
2235
909ff5ef 2236 bcmgenet_netif_start(dev);
1c1008c7
FF		 2237
2238 return 0;
2239
2240err_irq0:
2241 free_irq(priv->irq0, dev);
2242err_fini_dma:
2243 bcmgenet_fini_dma(priv);
2244err_clk_disable:
2245 if (!IS_ERR(priv->clk))
2246 clk_disable_unprepare(priv->clk);
2247 return ret;
2248}
2249
909ff5ef
FF		 2250static void bcmgenet_netif_stop(struct net_device *dev)
2251{
2252 struct bcmgenet_priv *priv = netdev_priv(dev);
2253
2254 netif_tx_stop_all_queues(dev);
2255 napi_disable(&priv->napi);
2256 phy_stop(priv->phydev);
2257
2258 bcmgenet_intr_disable(priv);
2259
2260 /* Wait for pending work items to complete. Since interrupts are
2261 * disabled no new work will be scheduled.
2262 */
2263 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2264
cc013fb4 2265 priv->old_link = -1;
5ad6e6c5 2266 priv->old_speed = -1;
cc013fb4 2267 priv->old_duplex = -1;
5ad6e6c5 2268 priv->old_pause = -1;
909ff5ef
FF		 2269}
2270
1c1008c7
FF		 2271static int bcmgenet_close(struct net_device *dev)
2272{
2273 struct bcmgenet_priv *priv = netdev_priv(dev);
2274 int ret;
1c1008c7
FF		 2275
2276 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2277
909ff5ef 2278 bcmgenet_netif_stop(dev);
1c1008c7 2279
c96e731c
FF		 2280 /* Really kill the PHY state machine and disconnect from it */
2281 phy_disconnect(priv->phydev);
2282
1c1008c7 2283 /* Disable MAC receive */
e29585b8 2284 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2285
1c1008c7
FF		 2286 ret = bcmgenet_dma_teardown(priv);
2287 if (ret)
2288 return ret;
2289
2290 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2291 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2292
1c1008c7
FF		 2293 /* tx reclaim */
2294 bcmgenet_tx_reclaim_all(dev);
2295 bcmgenet_fini_dma(priv);
2296
2297 free_irq(priv->irq0, priv);
2298 free_irq(priv->irq1, priv);
2299
1c1008c7
FF		 2300 if (phy_is_internal(priv->phydev))
2301 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2302
1c1008c7
FF		 2303 if (!IS_ERR(priv->clk))
2304 clk_disable_unprepare(priv->clk);
2305
2306 return 0;
2307}
2308
2309static void bcmgenet_timeout(struct net_device *dev)
2310{
2311 struct bcmgenet_priv *priv = netdev_priv(dev);
2312
2313 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2314
2315 dev->trans_start = jiffies;
2316
2317 dev->stats.tx_errors++;
2318
2319 netif_tx_wake_all_queues(dev);
2320}
2321
2322#define MAX_MC_COUNT 16
2323
2324static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2325 unsigned char *addr,
2326 int *i,
2327 int *mc)
2328{
2329 u32 reg;
2330
c91b7f66
FF		 2331 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2332 UMAC_MDF_ADDR + (*i * 4));
2333 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2334 addr[4] << 8 | addr[5],
2335 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2336 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2337 reg |= (1 << (MAX_MC_COUNT - *mc));
2338 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2339 *i += 2;
2340 (*mc)++;
2341}
2342
2343static void bcmgenet_set_rx_mode(struct net_device *dev)
2344{
2345 struct bcmgenet_priv *priv = netdev_priv(dev);
2346 struct netdev_hw_addr *ha;
2347 int i, mc;
2348 u32 reg;
2349
2350 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2351
7fc527f9 2352 /* Promiscuous mode */
1c1008c7
FF		 2353 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2354 if (dev->flags & IFF_PROMISC) {
2355 reg |= CMD_PROMISC;
2356 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2357 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2358 return;
2359 } else {
2360 reg &= ~CMD_PROMISC;
2361 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2362 }
2363
2364 /* UniMac doesn't support ALLMULTI */
2365 if (dev->flags & IFF_ALLMULTI) {
2366 netdev_warn(dev, "ALLMULTI is not supported\n");
2367 return;
2368 }
2369
2370 /* update MDF filter */
2371 i = 0;
2372 mc = 0;
2373 /* Broadcast */
2374 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2375 /* my own address.*/
2376 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2377 /* Unicast list*/
2378 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2379 return;
2380
2381 if (!netdev_uc_empty(dev))
2382 netdev_for_each_uc_addr(ha, dev)
2383 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2384 /* Multicast */
2385 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2386 return;
2387
2388 netdev_for_each_mc_addr(ha, dev)
2389 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2390}
2391
2392/* Set the hardware MAC address. */
2393static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2394{
2395 struct sockaddr *addr = p;
2396
2397 /* Setting the MAC address at the hardware level is not possible
2398 * without disabling the UniMAC RX/TX enable bits.
2399 */
2400 if (netif_running(dev))
2401 return -EBUSY;
2402
2403 ether_addr_copy(dev->dev_addr, addr->sa_data);
2404
2405 return 0;
2406}
2407
1c1008c7
FF		 2408static const struct net_device_ops bcmgenet_netdev_ops = {
2409 .ndo_open = bcmgenet_open,
2410 .ndo_stop = bcmgenet_close,
2411 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2412 .ndo_tx_timeout = bcmgenet_timeout,
2413 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2414 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2415 .ndo_do_ioctl = bcmgenet_ioctl,
2416 .ndo_set_features = bcmgenet_set_features,
2417};
2418
2419/* Array of GENET hardware parameters/characteristics */
2420static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2421 [GENET_V1] = {
2422 .tx_queues = 0,
2423 .rx_queues = 0,
2424 .bds_cnt = 0,
2425 .bp_in_en_shift = 16,
2426 .bp_in_mask = 0xffff,
2427 .hfb_filter_cnt = 16,
2428 .qtag_mask = 0x1F,
2429 .hfb_offset = 0x1000,
2430 .rdma_offset = 0x2000,
2431 .tdma_offset = 0x3000,
2432 .words_per_bd = 2,
2433 },
2434 [GENET_V2] = {
2435 .tx_queues = 4,
2436 .rx_queues = 4,
2437 .bds_cnt = 32,
2438 .bp_in_en_shift = 16,
2439 .bp_in_mask = 0xffff,
2440 .hfb_filter_cnt = 16,
2441 .qtag_mask = 0x1F,
2442 .tbuf_offset = 0x0600,
2443 .hfb_offset = 0x1000,
2444 .hfb_reg_offset = 0x2000,
2445 .rdma_offset = 0x3000,
2446 .tdma_offset = 0x4000,
2447 .words_per_bd = 2,
2448 .flags = GENET_HAS_EXT,
2449 },
2450 [GENET_V3] = {
2451 .tx_queues = 4,
2452 .rx_queues = 4,
2453 .bds_cnt = 32,
2454 .bp_in_en_shift = 17,
2455 .bp_in_mask = 0x1ffff,
2456 .hfb_filter_cnt = 48,
2457 .qtag_mask = 0x3F,
2458 .tbuf_offset = 0x0600,
2459 .hfb_offset = 0x8000,
2460 .hfb_reg_offset = 0xfc00,
2461 .rdma_offset = 0x10000,
2462 .tdma_offset = 0x11000,
2463 .words_per_bd = 2,
2464 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2465 },
2466 [GENET_V4] = {
2467 .tx_queues = 4,
2468 .rx_queues = 4,
2469 .bds_cnt = 32,
2470 .bp_in_en_shift = 17,
2471 .bp_in_mask = 0x1ffff,
2472 .hfb_filter_cnt = 48,
2473 .qtag_mask = 0x3F,
2474 .tbuf_offset = 0x0600,
2475 .hfb_offset = 0x8000,
2476 .hfb_reg_offset = 0xfc00,
2477 .rdma_offset = 0x2000,
2478 .tdma_offset = 0x4000,
2479 .words_per_bd = 3,
2480 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2481 },
2482};
2483
2484/* Infer hardware parameters from the detected GENET version */
2485static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2486{
2487 struct bcmgenet_hw_params *params;
2488 u32 reg;
2489 u8 major;
b04a2f5b 2490 u16 gphy_rev;
1c1008c7
FF		 2491
2492 if (GENET_IS_V4(priv)) {
2493 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2494 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2495 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2496 priv->version = GENET_V4;
2497 } else if (GENET_IS_V3(priv)) {
2498 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2499 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2500 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2501 priv->version = GENET_V3;
2502 } else if (GENET_IS_V2(priv)) {
2503 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2504 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2505 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2506 priv->version = GENET_V2;
2507 } else if (GENET_IS_V1(priv)) {
2508 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2509 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2510 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2511 priv->version = GENET_V1;
2512 }
2513
2514 /* enum genet_version starts at 1 */
2515 priv->hw_params = &bcmgenet_hw_params[priv->version];
2516 params = priv->hw_params;
2517
2518 /* Read GENET HW version */
2519 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2520 major = (reg >> 24 & 0x0f);
2521 if (major == 5)
2522 major = 4;
2523 else if (major == 0)
2524 major = 1;
2525 if (major != priv->version) {
2526 dev_err(&priv->pdev->dev,
2527 "GENET version mismatch, got: %d, configured for: %d\n",
2528 major, priv->version);
2529 }
2530
2531 /* Print the GENET core version */
2532 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 2533 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 2534
487320c5
FF		 2535 /* Store the integrated PHY revision for the MDIO probing function
2536 * to pass this information to the PHY driver. The PHY driver expects
2537 * to find the PHY major revision in bits 15:8 while the GENET register
2538 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 2539 *
2540 * On newer chips, starting with PHY revision G0, a new scheme is
2541 * deployed similar to the Starfighter 2 switch with GPHY major
2542 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
2543 * is reserved as well as special value 0x01ff, we have a small
2544 * heuristic to check for the new GPHY revision and re-arrange things
2545 * so the GPHY driver is happy.
487320c5 2546 */
b04a2f5b
FF		 2547 gphy_rev = reg & 0xffff;
2548
2549 /* This is the good old scheme, just GPHY major, no minor nor patch */
2550 if ((gphy_rev & 0xf0) != 0)
2551 priv->gphy_rev = gphy_rev << 8;
2552
2553 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
2554 else if ((gphy_rev & 0xff00) != 0)
2555 priv->gphy_rev = gphy_rev;
2556
2557 /* This is reserved so should require special treatment */
2558 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
2559 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
2560 return;
2561 }
487320c5 2562
1c1008c7
FF		 2563#ifdef CONFIG_PHYS_ADDR_T_64BIT
2564 if (!(params->flags & GENET_HAS_40BITS))
2565 pr_warn("GENET does not support 40-bits PA\n");
2566#endif
2567
2568 pr_debug("Configuration for version: %d\n"
2569 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2570 "BP << en: %2d, BP msk: 0x%05x\n"
2571 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2572 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2573 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2574 "Words/BD: %d\n",
2575 priv->version,
2576 params->tx_queues, params->rx_queues, params->bds_cnt,
2577 params->bp_in_en_shift, params->bp_in_mask,
2578 params->hfb_filter_cnt, params->qtag_mask,
2579 params->tbuf_offset, params->hfb_offset,
2580 params->hfb_reg_offset,
2581 params->rdma_offset, params->tdma_offset,
2582 params->words_per_bd);
2583}
2584
2585static const struct of_device_id bcmgenet_match[] = {
2586 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2587 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2588 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2589 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2590 { },
2591};
2592
2593static int bcmgenet_probe(struct platform_device *pdev)
2594{
b0ba512e 2595 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 2596 struct device_node *dn = pdev->dev.of_node;
b0ba512e 2597 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 2598 struct bcmgenet_priv *priv;
2599 struct net_device *dev;
2600 const void *macaddr;
2601 struct resource *r;
2602 int err = -EIO;
2603
2604 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2605 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2606 if (!dev) {
2607 dev_err(&pdev->dev, "can't allocate net device\n");
2608 return -ENOMEM;
2609 }
2610
b0ba512e
PG		 2611 if (dn) {
2612 of_id = of_match_node(bcmgenet_match, dn);
2613 if (!of_id)
2614 return -EINVAL;
2615 }
1c1008c7
FF		 2616
2617 priv = netdev_priv(dev);
2618 priv->irq0 = platform_get_irq(pdev, 0);
2619 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2620 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2621 if (!priv->irq0 || !priv->irq1) {
2622 dev_err(&pdev->dev, "can't find IRQs\n");
2623 err = -EINVAL;
2624 goto err;
2625 }
2626
b0ba512e
PG		 2627 if (dn) {
2628 macaddr = of_get_mac_address(dn);
2629 if (!macaddr) {
2630 dev_err(&pdev->dev, "can't find MAC address\n");
2631 err = -EINVAL;
2632 goto err;
2633 }
2634 } else {
2635 macaddr = pd->mac_address;
1c1008c7
FF		 2636 }
2637
2638 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2639 priv->base = devm_ioremap_resource(&pdev->dev, r);
2640 if (IS_ERR(priv->base)) {
2641 err = PTR_ERR(priv->base);
1c1008c7
FF		 2642 goto err;
2643 }
2644
2645 SET_NETDEV_DEV(dev, &pdev->dev);
2646 dev_set_drvdata(&pdev->dev, dev);
2647 ether_addr_copy(dev->dev_addr, macaddr);
2648 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2649 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2650 dev->netdev_ops = &bcmgenet_netdev_ops;
2651 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2652
2653 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2654
2655 /* Set hardware features */
2656 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2657 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2658
8562056f
FF		 2659 /* Request the WOL interrupt and advertise suspend if available */
2660 priv->wol_irq_disabled = true;
2661 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2662 dev->name, priv);
2663 if (!err)
2664 device_set_wakeup_capable(&pdev->dev, 1);
2665
1c1008c7
FF		 2666 /* Set the needed headroom to account for any possible
2667 * features enabling/disabling at runtime
2668 */
2669 dev->needed_headroom += 64;
2670
2671 netdev_boot_setup_check(dev);
2672
2673 priv->dev = dev;
2674 priv->pdev = pdev;
b0ba512e
PG		 2675 if (of_id)
2676 priv->version = (enum bcmgenet_version)of_id->data;
2677 else
2678 priv->version = pd->genet_version;
1c1008c7 2679
e4a60a93
FF		 2680 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2681 if (IS_ERR(priv->clk))
2682 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2683
2684 if (!IS_ERR(priv->clk))
2685 clk_prepare_enable(priv->clk);
2686
1c1008c7
FF		 2687 bcmgenet_set_hw_params(priv);
2688
1c1008c7
FF		 2689 /* Mii wait queue */
2690 init_waitqueue_head(&priv->wq);
2691 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2692 priv->rx_buf_len = RX_BUF_LENGTH;
2693 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2694
1c1008c7
FF		 2695 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2696 if (IS_ERR(priv->clk_wol))
2697 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2698
6ef398ea
FF		 2699 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
2700 if (IS_ERR(priv->clk_eee)) {
2701 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
2702 priv->clk_eee = NULL;
2703 }
2704
1c1008c7
FF		 2705 err = reset_umac(priv);
2706 if (err)
2707 goto err_clk_disable;
2708
2709 err = bcmgenet_mii_init(dev);
2710 if (err)
2711 goto err_clk_disable;
2712
2713 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2714 * just the ring 16 descriptor based TX
2715 */
2716 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2717 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2718
219575eb
FF		 2719 /* libphy will determine the link state */
2720 netif_carrier_off(dev);
2721
1c1008c7
FF		 2722 /* Turn off the main clock, WOL clock is handled separately */
2723 if (!IS_ERR(priv->clk))
2724 clk_disable_unprepare(priv->clk);
2725
0f50ce96
FF		 2726 err = register_netdev(dev);
2727 if (err)
2728 goto err;
2729
1c1008c7
FF		 2730 return err;
2731
2732err_clk_disable:
2733 if (!IS_ERR(priv->clk))
2734 clk_disable_unprepare(priv->clk);
2735err:
2736 free_netdev(dev);
2737 return err;
2738}
2739
2740static int bcmgenet_remove(struct platform_device *pdev)
2741{
2742 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2743
2744 dev_set_drvdata(&pdev->dev, NULL);
2745 unregister_netdev(priv->dev);
2746 bcmgenet_mii_exit(priv->dev);
2747 free_netdev(priv->dev);
2748
2749 return 0;
2750}
2751
b6e978e5
FF		 2752#ifdef CONFIG_PM_SLEEP
2753static int bcmgenet_suspend(struct device *d)
2754{
2755 struct net_device *dev = dev_get_drvdata(d);
2756 struct bcmgenet_priv *priv = netdev_priv(dev);
2757 int ret;
2758
2759 if (!netif_running(dev))
2760 return 0;
2761
2762 bcmgenet_netif_stop(dev);
2763
cc013fb4
FF		 2764 phy_suspend(priv->phydev);
2765
b6e978e5
FF		 2766 netif_device_detach(dev);
2767
2768 /* Disable MAC receive */
2769 umac_enable_set(priv, CMD_RX_EN, false);
2770
2771 ret = bcmgenet_dma_teardown(priv);
2772 if (ret)
2773 return ret;
2774
2775 /* Disable MAC transmit. TX DMA disabled have to done before this */
2776 umac_enable_set(priv, CMD_TX_EN, false);
2777
2778 /* tx reclaim */
2779 bcmgenet_tx_reclaim_all(dev);
2780 bcmgenet_fini_dma(priv);
2781
8c90db72
FF		 2782 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2783 if (device_may_wakeup(d) && priv->wolopts) {
2784 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2785 clk_prepare_enable(priv->clk_wol);
2786 }
2787
b6e978e5
FF		 2788 /* Turn off the clocks */
2789 clk_disable_unprepare(priv->clk);
2790
2791 return 0;
2792}
2793
2794static int bcmgenet_resume(struct device *d)
2795{
2796 struct net_device *dev = dev_get_drvdata(d);
2797 struct bcmgenet_priv *priv = netdev_priv(dev);
2798 unsigned long dma_ctrl;
2799 int ret;
2800 u32 reg;
2801
2802 if (!netif_running(dev))
2803 return 0;
2804
2805 /* Turn on the clock */
2806 ret = clk_prepare_enable(priv->clk);
2807 if (ret)
2808 return ret;
2809
2810 bcmgenet_umac_reset(priv);
2811
2812 ret = init_umac(priv);
2813 if (ret)
2814 goto out_clk_disable;
2815
0a29b3da
TK		 2816 /* From WOL-enabled suspend, switch to regular clock */
2817 if (priv->wolopts)
2818 clk_disable_unprepare(priv->clk_wol);
2819
2820 phy_init_hw(priv->phydev);
2821 /* Speed settings must be restored */
dbd479db 2822 bcmgenet_mii_config(priv->dev, false);
8c90db72 2823
b6e978e5
FF		 2824 /* disable ethernet MAC while updating its registers */
2825 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2826
2827 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2828
2829 if (phy_is_internal(priv->phydev)) {
2830 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2831 reg |= EXT_ENERGY_DET_MASK;
2832 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2833 }
2834
98bb7399
FF		 2835 if (priv->wolopts)
2836 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2837
b6e978e5
FF		 2838 /* Disable RX/TX DMA and flush TX queues */
2839 dma_ctrl = bcmgenet_dma_disable(priv);
2840
2841 /* Reinitialize TDMA and RDMA and SW housekeeping */
2842 ret = bcmgenet_init_dma(priv);
2843 if (ret) {
2844 netdev_err(dev, "failed to initialize DMA\n");
2845 goto out_clk_disable;
2846 }
2847
2848 /* Always enable ring 16 - descriptor ring */
2849 bcmgenet_enable_dma(priv, dma_ctrl);
2850
2851 netif_device_attach(dev);
2852
cc013fb4
FF		 2853 phy_resume(priv->phydev);
2854
6ef398ea
FF		 2855 if (priv->eee.eee_enabled)
2856 bcmgenet_eee_enable_set(dev, true);
2857
b6e978e5
FF		 2858 bcmgenet_netif_start(dev);
2859
2860 return 0;
2861
2862out_clk_disable:
2863 clk_disable_unprepare(priv->clk);
2864 return ret;
2865}
2866#endif /* CONFIG_PM_SLEEP */
2867
2868static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2869
1c1008c7
FF		 2870static struct platform_driver bcmgenet_driver = {
2871 .probe = bcmgenet_probe,
2872 .remove = bcmgenet_remove,
2873 .driver = {
2874 .name = "bcmgenet",
1c1008c7 2875 .of_match_table = bcmgenet_match,
b6e978e5 2876 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 2877 },
2878};
2879module_platform_driver(bcmgenet_driver);
2880
2881MODULE_AUTHOR("Broadcom Corporation");
2882MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2883MODULE_ALIAS("platform:bcmgenet");
2884MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)