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bnx2x: Add timestamping and PTP hardware clock support
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
08f6dd89 9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
24e3fcef 10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
33d8e6a5 30#include <linux/aer.h>
a2fbb9ea
ET		 31#include <linux/init.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/dma-mapping.h>
36#include <linux/bitops.h>
37#include <linux/irq.h>
38#include <linux/delay.h>
39#include <asm/byteorder.h>
40#include <linux/time.h>
41#include <linux/ethtool.h>
42#include <linux/mii.h>
0c6671b0 43#include <linux/if_vlan.h>
a2fbb9ea 44#include <net/ip.h>
619c5cb6 45#include <net/ipv6.h>
a2fbb9ea
ET		 46#include <net/tcp.h>
47#include <net/checksum.h>
34f80b04 48#include <net/ip6_checksum.h>
a2fbb9ea
ET		 49#include <linux/workqueue.h>
50#include <linux/crc32.h>
34f80b04 51#include <linux/crc32c.h>
a2fbb9ea
ET		 52#include <linux/prefetch.h>
53#include <linux/zlib.h>
a2fbb9ea 54#include <linux/io.h>
452427b0 55#include <linux/semaphore.h>
45229b42 56#include <linux/stringify.h>
7ab24bfd 57#include <linux/vmalloc.h>
a2fbb9ea 58
a2fbb9ea
ET		 59#include "bnx2x.h"
60#include "bnx2x_init.h"
94a78b79 61#include "bnx2x_init_ops.h"
9f6c9258 62#include "bnx2x_cmn.h"
1ab4434c 63#include "bnx2x_vfpf.h"
e4901dde 64#include "bnx2x_dcb.h"
042181f5 65#include "bnx2x_sp.h"
94a78b79
VZ		 66#include <linux/firmware.h>
67#include "bnx2x_fw_file_hdr.h"
68/* FW files */
45229b42
BH		 69#define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 74#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 76#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 77
34f80b04
EG		 78/* Time in jiffies before concluding the transmitter is hung */
79#define TX_TIMEOUT (5*HZ)
a2fbb9ea 80
0329aba1 81static char version[] =
619c5cb6 82 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 83 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
84
24e3fcef 85MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 86MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 87 "BCM57710/57711/57711E/"
88 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
89 "57840/57840_MF Driver");
a2fbb9ea
ET		 90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 92MODULE_FIRMWARE(FW_FILE_NAME_E1);
93MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 94MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 95
a8f47eb7 96int bnx2x_num_queues;
1c8bb760 97module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
96305234
DK		 98MODULE_PARM_DESC(num_queues,
99 " Set number of queues (default is as a number of CPUs)");
555f6c78 100
19680c48 101static int disable_tpa;
1c8bb760 102module_param(disable_tpa, int, S_IRUGO);
9898f86d 103MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 104
a8f47eb7 105static int int_mode;
1c8bb760 106module_param(int_mode, int, S_IRUGO);
619c5cb6 107MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 108 "(1 INT#x; 2 MSI)");
8badd27a 109
a18f5128 110static int dropless_fc;
1c8bb760 111module_param(dropless_fc, int, S_IRUGO);
a18f5128
EG		 112MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
113
8d5726c4 114static int mrrs = -1;
1c8bb760 115module_param(mrrs, int, S_IRUGO);
8d5726c4
EG		 116MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
117
9898f86d 118static int debug;
1c8bb760 119module_param(debug, int, S_IRUGO);
9898f86d
EG		 120MODULE_PARM_DESC(debug, " Default debug msglevel");
121
370d4a26
YM		 122static struct workqueue_struct *bnx2x_wq;
123struct workqueue_struct *bnx2x_iov_wq;
ec6ba945 124
1ef1d45a
BW		 125struct bnx2x_mac_vals {
126 u32 xmac_addr;
127 u32 xmac_val;
128 u32 emac_addr;
129 u32 emac_val;
130 u32 umac_addr;
131 u32 umac_val;
132 u32 bmac_addr;
133 u32 bmac_val[2];
134};
135
a2fbb9ea
ET		 136enum bnx2x_board_type {
137 BCM57710 = 0,
619c5cb6
VZ		 138 BCM57711,
139 BCM57711E,
140 BCM57712,
141 BCM57712_MF,
1ab4434c 142 BCM57712_VF,
619c5cb6
VZ		 143 BCM57800,
144 BCM57800_MF,
1ab4434c 145 BCM57800_VF,
619c5cb6
VZ		 146 BCM57810,
147 BCM57810_MF,
1ab4434c 148 BCM57810_VF,
c3def943
YM		 149 BCM57840_4_10,
150 BCM57840_2_20,
7e8e02df 151 BCM57840_MF,
1ab4434c 152 BCM57840_VF,
7e8e02df 153 BCM57811,
1ab4434c
AE		 154 BCM57811_MF,
155 BCM57840_O,
156 BCM57840_MFO,
157 BCM57811_VF
a2fbb9ea
ET		 158};
159
34f80b04 160/* indexed by board_type, above */
53a10565 161static struct {
a2fbb9ea 162 char *name;
0329aba1 163} board_info[] = {
1ab4434c
AE		 164 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
165 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
166 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
167 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
168 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
169 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
170 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
171 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
172 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
173 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
174 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
175 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
176 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
177 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
178 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
179 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
180 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
181 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
182 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
183 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
184 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 185};
186
619c5cb6
VZ		 187#ifndef PCI_DEVICE_ID_NX2_57710
188#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
189#endif
190#ifndef PCI_DEVICE_ID_NX2_57711
191#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
192#endif
193#ifndef PCI_DEVICE_ID_NX2_57711E
194#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
195#endif
196#ifndef PCI_DEVICE_ID_NX2_57712
197#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
198#endif
199#ifndef PCI_DEVICE_ID_NX2_57712_MF
200#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
201#endif
8395be5e
AE		 202#ifndef PCI_DEVICE_ID_NX2_57712_VF
203#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
204#endif
619c5cb6
VZ		 205#ifndef PCI_DEVICE_ID_NX2_57800
206#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
207#endif
208#ifndef PCI_DEVICE_ID_NX2_57800_MF
209#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
210#endif
8395be5e
AE		 211#ifndef PCI_DEVICE_ID_NX2_57800_VF
212#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
213#endif
619c5cb6
VZ		 214#ifndef PCI_DEVICE_ID_NX2_57810
215#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
216#endif
217#ifndef PCI_DEVICE_ID_NX2_57810_MF
218#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
219#endif
c3def943
YM		 220#ifndef PCI_DEVICE_ID_NX2_57840_O
221#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
222#endif
8395be5e
AE		 223#ifndef PCI_DEVICE_ID_NX2_57810_VF
224#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
225#endif
c3def943
YM		 226#ifndef PCI_DEVICE_ID_NX2_57840_4_10
227#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
228#endif
229#ifndef PCI_DEVICE_ID_NX2_57840_2_20
230#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
231#endif
232#ifndef PCI_DEVICE_ID_NX2_57840_MFO
233#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 234#endif
235#ifndef PCI_DEVICE_ID_NX2_57840_MF
236#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
237#endif
8395be5e
AE		 238#ifndef PCI_DEVICE_ID_NX2_57840_VF
239#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
240#endif
7e8e02df
BW		 241#ifndef PCI_DEVICE_ID_NX2_57811
242#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
243#endif
244#ifndef PCI_DEVICE_ID_NX2_57811_MF
245#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
246#endif
8395be5e
AE		 247#ifndef PCI_DEVICE_ID_NX2_57811_VF
248#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
249#endif
250
9baa3c34 251static const struct pci_device_id bnx2x_pci_tbl[] = {
e4ed7113
EG		 252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 273 { 0 }
274};
275
276MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
277
452427b0
YM		 278/* Global resources for unloading a previously loaded device */
279#define BNX2X_PREV_WAIT_NEEDED 1
280static DEFINE_SEMAPHORE(bnx2x_prev_sem);
281static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 282
283/* Forward declaration */
284static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
285static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
286static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
287
a2fbb9ea
ET		 288/****************************************************************************
289* General service functions
290****************************************************************************/
291
eeed018c
MK		 292static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
293
1191cb83 294static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 295 u32 addr, dma_addr_t mapping)
296{
297 REG_WR(bp, addr, U64_LO(mapping));
298 REG_WR(bp, addr + 4, U64_HI(mapping));
299}
300
1191cb83
ED		 301static void storm_memset_spq_addr(struct bnx2x *bp,
302 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 303{
304 u32 addr = XSEM_REG_FAST_MEMORY +
305 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
306
307 __storm_memset_dma_mapping(bp, addr, mapping);
308}
309
1191cb83
ED		 310static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
311 u16 pf_id)
523224a3 312{
619c5cb6
VZ		 313 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
314 pf_id);
315 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
316 pf_id);
317 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
318 pf_id);
319 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
320 pf_id);
523224a3
DK		 321}
322
1191cb83
ED		 323static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
324 u8 enable)
619c5cb6
VZ		 325{
326 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
327 enable);
328 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
329 enable);
330 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
331 enable);
332 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
333 enable);
334}
523224a3 335
1191cb83
ED		 336static void storm_memset_eq_data(struct bnx2x *bp,
337 struct event_ring_data *eq_data,
523224a3
DK		 338 u16 pfid)
339{
340 size_t size = sizeof(struct event_ring_data);
341
342 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
343
344 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
345}
346
1191cb83
ED		 347static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
348 u16 pfid)
523224a3
DK		 349{
350 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
351 REG_WR16(bp, addr, eq_prod);
352}
353
a2fbb9ea
ET		 354/* used only at init
355 * locking is done by mcp
356 */
8d96286a 357static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 358{
359 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
360 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
361 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
362 PCICFG_VENDOR_ID_OFFSET);
363}
364
a2fbb9ea
ET		 365static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
366{
367 u32 val;
368
369 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
370 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
371 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
372 PCICFG_VENDOR_ID_OFFSET);
373
374 return val;
375}
a2fbb9ea 376
f2e0899f
DK		 377#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
378#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
379#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
380#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
381#define DMAE_DP_DST_NONE "dst_addr [none]"
382
6bf07b8e
YM		 383static void bnx2x_dp_dmae(struct bnx2x *bp,
384 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 385{
386 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 387 int i;
fd1fc79d
AE		 388
389 switch (dmae->opcode & DMAE_COMMAND_DST) {
390 case DMAE_CMD_DST_PCI:
391 if (src_type == DMAE_CMD_SRC_PCI)
392 DP(msglvl, "DMAE: opcode 0x%08x\n"
393 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
394 "comp_addr [%x:%08x], comp_val 0x%08x\n",
395 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
396 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
397 dmae->comp_addr_hi, dmae->comp_addr_lo,
398 dmae->comp_val);
399 else
400 DP(msglvl, "DMAE: opcode 0x%08x\n"
401 "src [%08x], len [%d*4], dst [%x:%08x]\n"
402 "comp_addr [%x:%08x], comp_val 0x%08x\n",
403 dmae->opcode, dmae->src_addr_lo >> 2,
404 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
405 dmae->comp_addr_hi, dmae->comp_addr_lo,
406 dmae->comp_val);
407 break;
408 case DMAE_CMD_DST_GRC:
409 if (src_type == DMAE_CMD_SRC_PCI)
410 DP(msglvl, "DMAE: opcode 0x%08x\n"
411 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
412 "comp_addr [%x:%08x], comp_val 0x%08x\n",
413 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
414 dmae->len, dmae->dst_addr_lo >> 2,
415 dmae->comp_addr_hi, dmae->comp_addr_lo,
416 dmae->comp_val);
417 else
418 DP(msglvl, "DMAE: opcode 0x%08x\n"
419 "src [%08x], len [%d*4], dst [%08x]\n"
420 "comp_addr [%x:%08x], comp_val 0x%08x\n",
421 dmae->opcode, dmae->src_addr_lo >> 2,
422 dmae->len, dmae->dst_addr_lo >> 2,
423 dmae->comp_addr_hi, dmae->comp_addr_lo,
424 dmae->comp_val);
425 break;
426 default:
427 if (src_type == DMAE_CMD_SRC_PCI)
428 DP(msglvl, "DMAE: opcode 0x%08x\n"
429 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
430 "comp_addr [%x:%08x] comp_val 0x%08x\n",
431 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
432 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
433 dmae->comp_val);
434 else
435 DP(msglvl, "DMAE: opcode 0x%08x\n"
436 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
437 "comp_addr [%x:%08x] comp_val 0x%08x\n",
438 dmae->opcode, dmae->src_addr_lo >> 2,
439 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
440 dmae->comp_val);
441 break;
442 }
6bf07b8e
YM		 443
444 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
445 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
446 i, *(((u32 *)dmae) + i));
fd1fc79d 447}
f2e0899f 448
a2fbb9ea 449/* copy command into DMAE command memory and set DMAE command go */
6c719d00 450void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 451{
452 u32 cmd_offset;
453 int i;
454
455 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
456 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
457 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 458 }
459 REG_WR(bp, dmae_reg_go_c[idx], 1);
460}
461
f2e0899f 462u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 463{
f2e0899f
DK		 464 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
465 DMAE_CMD_C_ENABLE);
466}
ad8d3948 467
f2e0899f
DK		 468u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
469{
470 return opcode & ~DMAE_CMD_SRC_RESET;
471}
ad8d3948 472
f2e0899f
DK		 473u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
474 bool with_comp, u8 comp_type)
475{
476 u32 opcode = 0;
477
478 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
479 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 480
f2e0899f
DK		 481 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
482
483 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 484 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
485 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 486 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 487
a2fbb9ea 488#ifdef __BIG_ENDIAN
f2e0899f 489 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 490#else
f2e0899f 491 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 492#endif
f2e0899f
DK		 493 if (with_comp)
494 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
495 return opcode;
496}
497
fd1fc79d 498void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 499 struct dmae_command *dmae,
500 u8 src_type, u8 dst_type)
f2e0899f
DK		 501{
502 memset(dmae, 0, sizeof(struct dmae_command));
503
504 /* set the opcode */
505 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
506 true, DMAE_COMP_PCI);
507
508 /* fill in the completion parameters */
509 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
510 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
511 dmae->comp_val = DMAE_COMP_VAL;
512}
513
fd1fc79d 514/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 515int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
516 u32 *comp)
f2e0899f 517{
5e374b5a 518 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 519 int rc = 0;
520
6bf07b8e
YM		 521 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
522
523 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 524 * as long as this code is called both from syscall context and
525 * from ndo_set_rx_mode() flow that may be called from BH.
526 */
eeed018c 527
6e30dd4e 528 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 529
f2e0899f 530 /* reset completion */
32316a46 531 *comp = 0;
a2fbb9ea 532
f2e0899f
DK		 533 /* post the command on the channel used for initializations */
534 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 535
f2e0899f 536 /* wait for completion */
a2fbb9ea 537 udelay(5);
32316a46 538 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 539
95c6c616
AE		 540 if (!cnt ||
541 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
542 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 543 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 544 rc = DMAE_TIMEOUT;
545 goto unlock;
a2fbb9ea 546 }
ad8d3948 547 cnt--;
f2e0899f 548 udelay(50);
a2fbb9ea 549 }
32316a46 550 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 551 BNX2X_ERR("DMAE PCI error!\n");
552 rc = DMAE_PCI_ERROR;
553 }
554
f2e0899f 555unlock:
eeed018c 556
6e30dd4e 557 spin_unlock_bh(&bp->dmae_lock);
eeed018c 558
f2e0899f
DK		 559 return rc;
560}
561
562void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
563 u32 len32)
564{
6bf07b8e 565 int rc;
f2e0899f
DK		 566 struct dmae_command dmae;
567
568 if (!bp->dmae_ready) {
569 u32 *data = bnx2x_sp(bp, wb_data[0]);
570
127a425e
AE		 571 if (CHIP_IS_E1(bp))
572 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
573 else
574 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 575 return;
576 }
577
578 /* set opcode and fixed command fields */
579 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
580
581 /* fill in addresses and len */
582 dmae.src_addr_lo = U64_LO(dma_addr);
583 dmae.src_addr_hi = U64_HI(dma_addr);
584 dmae.dst_addr_lo = dst_addr >> 2;
585 dmae.dst_addr_hi = 0;
586 dmae.len = len32;
587
f2e0899f 588 /* issue the command and wait for completion */
32316a46 589 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 590 if (rc) {
591 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 592#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 593 bnx2x_panic();
9dcd9acd 594#endif
6bf07b8e 595 }
a2fbb9ea
ET		 596}
597
c18487ee 598void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 599{
6bf07b8e 600 int rc;
5ff7b6d4 601 struct dmae_command dmae;
ad8d3948
EG		 602
603 if (!bp->dmae_ready) {
604 u32 *data = bnx2x_sp(bp, wb_data[0]);
605 int i;
606
51c1a580 607 if (CHIP_IS_E1(bp))
127a425e
AE		 608 for (i = 0; i < len32; i++)
609 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 610 else
127a425e
AE		 611 for (i = 0; i < len32; i++)
612 data[i] = REG_RD(bp, src_addr + i*4);
613
ad8d3948
EG		 614 return;
615 }
616
f2e0899f
DK		 617 /* set opcode and fixed command fields */
618 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 619
f2e0899f 620 /* fill in addresses and len */
5ff7b6d4
EG		 621 dmae.src_addr_lo = src_addr >> 2;
622 dmae.src_addr_hi = 0;
623 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
624 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
625 dmae.len = len32;
ad8d3948 626
f2e0899f 627 /* issue the command and wait for completion */
32316a46 628 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 629 if (rc) {
630 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 631#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 632 bnx2x_panic();
9dcd9acd 633#endif
c957d09f 634 }
ad8d3948
EG		 635}
636
8d96286a 637static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
638 u32 addr, u32 len)
573f2035 639{
02e3c6cb 640 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 641 int offset = 0;
642
02e3c6cb 643 while (len > dmae_wr_max) {
573f2035 644 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 645 addr + offset, dmae_wr_max);
646 offset += dmae_wr_max * 4;
647 len -= dmae_wr_max;
573f2035
EG		 648 }
649
650 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
651}
652
a2fbb9ea
ET		 653static int bnx2x_mc_assert(struct bnx2x *bp)
654{
a2fbb9ea 655 char last_idx;
34f80b04
EG		 656 int i, rc = 0;
657 u32 row0, row1, row2, row3;
658
659 /* XSTORM */
660 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
661 XSTORM_ASSERT_LIST_INDEX_OFFSET);
662 if (last_idx)
663 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
664
665 /* print the asserts */
666 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
667
668 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
669 XSTORM_ASSERT_LIST_OFFSET(i));
670 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
671 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
672 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
673 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
674 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
675 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
676
677 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 678 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 679 i, row3, row2, row1, row0);
680 rc++;
681 } else {
682 break;
683 }
684 }
685
686 /* TSTORM */
687 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
688 TSTORM_ASSERT_LIST_INDEX_OFFSET);
689 if (last_idx)
690 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
691
692 /* print the asserts */
693 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
694
695 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
696 TSTORM_ASSERT_LIST_OFFSET(i));
697 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
698 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
699 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
700 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
701 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
702 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
703
704 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 705 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 706 i, row3, row2, row1, row0);
707 rc++;
708 } else {
709 break;
710 }
711 }
712
713 /* CSTORM */
714 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
715 CSTORM_ASSERT_LIST_INDEX_OFFSET);
716 if (last_idx)
717 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
718
719 /* print the asserts */
720 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
721
722 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
723 CSTORM_ASSERT_LIST_OFFSET(i));
724 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
725 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
726 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
727 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
728 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
729 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
730
731 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 732 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 733 i, row3, row2, row1, row0);
734 rc++;
735 } else {
736 break;
737 }
738 }
739
740 /* USTORM */
741 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
742 USTORM_ASSERT_LIST_INDEX_OFFSET);
743 if (last_idx)
744 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
745
746 /* print the asserts */
747 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
748
749 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
750 USTORM_ASSERT_LIST_OFFSET(i));
751 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
752 USTORM_ASSERT_LIST_OFFSET(i) + 4);
753 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
754 USTORM_ASSERT_LIST_OFFSET(i) + 8);
755 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
756 USTORM_ASSERT_LIST_OFFSET(i) + 12);
757
758 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 759 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 760 i, row3, row2, row1, row0);
761 rc++;
762 } else {
763 break;
a2fbb9ea
ET		 764 }
765 }
34f80b04 766
a2fbb9ea
ET		 767 return rc;
768}
c14423fe 769
1a6974b2
YM		 770#define MCPR_TRACE_BUFFER_SIZE (0x800)
771#define SCRATCH_BUFFER_SIZE(bp) \
772 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
773
7a25cc73 774void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 775{
7a25cc73 776 u32 addr, val;
a2fbb9ea 777 u32 mark, offset;
4781bfad 778 __be32 data[9];
a2fbb9ea 779 int word;
f2e0899f 780 u32 trace_shmem_base;
2145a920
VZ		 781 if (BP_NOMCP(bp)) {
782 BNX2X_ERR("NO MCP - can not dump\n");
783 return;
784 }
7a25cc73
DK		 785 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
786 (bp->common.bc_ver & 0xff0000) >> 16,
787 (bp->common.bc_ver & 0xff00) >> 8,
788 (bp->common.bc_ver & 0xff));
789
790 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
791 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 792 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 793
f2e0899f
DK		 794 if (BP_PATH(bp) == 0)
795 trace_shmem_base = bp->common.shmem_base;
796 else
797 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 798
799 /* sanity */
800 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
801 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
802 SCRATCH_BUFFER_SIZE(bp)) {
803 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
804 trace_shmem_base);
805 return;
806 }
807
808 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 809
810 /* validate TRCB signature */
811 mark = REG_RD(bp, addr);
812 if (mark != MFW_TRACE_SIGNATURE) {
813 BNX2X_ERR("Trace buffer signature is missing.");
814 return ;
815 }
816
817 /* read cyclic buffer pointer */
818 addr += 4;
cdaa7cb8 819 mark = REG_RD(bp, addr);
1a6974b2
YM		 820 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
821 if (mark >= trace_shmem_base || mark < addr + 4) {
822 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
823 return;
824 }
7a25cc73 825 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 826
7a25cc73 827 printk("%s", lvl);
2de67439
YM		 828
829 /* dump buffer after the mark */
1a6974b2 830 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 831 for (word = 0; word < 8; word++)
cdaa7cb8 832 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 833 data[8] = 0x0;
7995c64e 834 pr_cont("%s", (char *)data);
a2fbb9ea 835 }
2de67439
YM		 836
837 /* dump buffer before the mark */
cdaa7cb8 838 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 839 for (word = 0; word < 8; word++)
cdaa7cb8 840 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 841 data[8] = 0x0;
7995c64e 842 pr_cont("%s", (char *)data);
a2fbb9ea 843 }
7a25cc73
DK		 844 printk("%s" "end of fw dump\n", lvl);
845}
846
1191cb83 847static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 848{
849 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 850}
851
823e1d90
YM		 852static void bnx2x_hc_int_disable(struct bnx2x *bp)
853{
854 int port = BP_PORT(bp);
855 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
856 u32 val = REG_RD(bp, addr);
857
858 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 859 * MSI/MSIX capability
860 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 861 */
862 if (CHIP_IS_E1(bp)) {
863 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
864 * Use mask register to prevent from HC sending interrupts
865 * after we exit the function
866 */
867 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
868
869 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
870 HC_CONFIG_0_REG_INT_LINE_EN_0 |
871 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
872 } else
873 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
874 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
875 HC_CONFIG_0_REG_INT_LINE_EN_0 |
876 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
877
878 DP(NETIF_MSG_IFDOWN,
879 "write %x to HC %d (addr 0x%x)\n",
880 val, port, addr);
881
882 /* flush all outstanding writes */
883 mmiowb();
884
885 REG_WR(bp, addr, val);
886 if (REG_RD(bp, addr) != val)
6bf07b8e 887 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 888}
889
890static void bnx2x_igu_int_disable(struct bnx2x *bp)
891{
892 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
893
894 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
895 IGU_PF_CONF_INT_LINE_EN |
896 IGU_PF_CONF_ATTN_BIT_EN);
897
898 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
899
900 /* flush all outstanding writes */
901 mmiowb();
902
903 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
904 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 905 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 906}
907
908static void bnx2x_int_disable(struct bnx2x *bp)
909{
910 if (bp->common.int_block == INT_BLOCK_HC)
911 bnx2x_hc_int_disable(bp);
912 else
913 bnx2x_igu_int_disable(bp);
914}
915
916void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 917{
918 int i;
523224a3
DK		 919 u16 j;
920 struct hc_sp_status_block_data sp_sb_data;
921 int func = BP_FUNC(bp);
922#ifdef BNX2X_STOP_ON_ERROR
923 u16 start = 0, end = 0;
6383c0b3 924 u8 cos;
523224a3 925#endif
0155a27c 926 if (IS_PF(bp) && disable_int)
823e1d90 927 bnx2x_int_disable(bp);
a2fbb9ea 928
66e855f3 929 bp->stats_state = STATS_STATE_DISABLED;
7a752993 930 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 931 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
932
a2fbb9ea
ET		 933 BNX2X_ERR("begin crash dump -----------------\n");
934
8440d2b6
EG		 935 /* Indices */
936 /* Common */
0155a27c
YM		 937 if (IS_PF(bp)) {
938 struct host_sp_status_block *def_sb = bp->def_status_blk;
939 int data_size, cstorm_offset;
940
941 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
942 bp->def_idx, bp->def_att_idx, bp->attn_state,
943 bp->spq_prod_idx, bp->stats_counter);
944 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
945 def_sb->atten_status_block.attn_bits,
946 def_sb->atten_status_block.attn_bits_ack,
947 def_sb->atten_status_block.status_block_id,
948 def_sb->atten_status_block.attn_bits_index);
949 BNX2X_ERR(" def (");
950 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
951 pr_cont("0x%x%s",
952 def_sb->sp_sb.index_values[i],
953 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
954
955 data_size = sizeof(struct hc_sp_status_block_data) /
956 sizeof(u32);
957 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
958 for (i = 0; i < data_size; i++)
959 *((u32 *)&sp_sb_data + i) =
960 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
961 i * sizeof(u32));
962
963 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
964 sp_sb_data.igu_sb_id,
965 sp_sb_data.igu_seg_id,
966 sp_sb_data.p_func.pf_id,
967 sp_sb_data.p_func.vnic_id,
968 sp_sb_data.p_func.vf_id,
969 sp_sb_data.p_func.vf_valid,
970 sp_sb_data.state);
971 }
523224a3 972
ec6ba945 973 for_each_eth_queue(bp, i) {
a2fbb9ea 974 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 975 int loop;
f2e0899f 976 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 977 struct hc_status_block_data_e1x sb_data_e1x;
978 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 979 CHIP_IS_E1x(bp) ?
980 sb_data_e1x.common.state_machine :
981 sb_data_e2.common.state_machine;
523224a3 982 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 983 CHIP_IS_E1x(bp) ?
984 sb_data_e1x.index_data :
985 sb_data_e2.index_data;
6383c0b3 986 u8 data_size, cos;
523224a3 987 u32 *sb_data_p;
6383c0b3 988 struct bnx2x_fp_txdata txdata;
523224a3
DK		 989
990 /* Rx */
51c1a580 991 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 992 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 993 fp->rx_comp_prod,
66e855f3 994 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 995 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 996 fp->rx_sge_prod, fp->last_max_sge,
523224a3 997 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 998
523224a3 999 /* Tx */
6383c0b3
AE		 1000 for_each_cos_in_tx_queue(fp, cos)
1001 {
65565884 1002 txdata = *fp->txdata_ptr[cos];
51c1a580 1003 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 1004 i, txdata.tx_pkt_prod,
1005 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1006 txdata.tx_bd_cons,
1007 le16_to_cpu(*txdata.tx_cons_sb));
1008 }
523224a3 1009
619c5cb6
VZ		 1010 loop = CHIP_IS_E1x(bp) ?
1011 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1012
1013 /* host sb data */
1014
ec6ba945
VZ		 1015 if (IS_FCOE_FP(fp))
1016 continue;
55c11941 1017
523224a3
DK		 1018 BNX2X_ERR(" run indexes (");
1019 for (j = 0; j < HC_SB_MAX_SM; j++)
1020 pr_cont("0x%x%s",
1021 fp->sb_running_index[j],
1022 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1023
1024 BNX2X_ERR(" indexes (");
1025 for (j = 0; j < loop; j++)
1026 pr_cont("0x%x%s",
1027 fp->sb_index_values[j],
1028 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1029
1030 /* VF cannot access FW refelection for status block */
1031 if (IS_VF(bp))
1032 continue;
1033
523224a3 1034 /* fw sb data */
619c5cb6
VZ		 1035 data_size = CHIP_IS_E1x(bp) ?
1036 sizeof(struct hc_status_block_data_e1x) :
1037 sizeof(struct hc_status_block_data_e2);
523224a3 1038 data_size /= sizeof(u32);
619c5cb6
VZ		 1039 sb_data_p = CHIP_IS_E1x(bp) ?
1040 (u32 *)&sb_data_e1x :
1041 (u32 *)&sb_data_e2;
523224a3
DK		 1042 /* copy sb data in here */
1043 for (j = 0; j < data_size; j++)
1044 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1045 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1046 j * sizeof(u32));
1047
619c5cb6 1048 if (!CHIP_IS_E1x(bp)) {
51c1a580 1049 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1050 sb_data_e2.common.p_func.pf_id,
1051 sb_data_e2.common.p_func.vf_id,
1052 sb_data_e2.common.p_func.vf_valid,
1053 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1054 sb_data_e2.common.same_igu_sb_1b,
1055 sb_data_e2.common.state);
f2e0899f 1056 } else {
51c1a580 1057 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1058 sb_data_e1x.common.p_func.pf_id,
1059 sb_data_e1x.common.p_func.vf_id,
1060 sb_data_e1x.common.p_func.vf_valid,
1061 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1062 sb_data_e1x.common.same_igu_sb_1b,
1063 sb_data_e1x.common.state);
f2e0899f 1064 }
523224a3
DK		 1065
1066 /* SB_SMs data */
1067 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1068 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1069 j, hc_sm_p[j].__flags,
1070 hc_sm_p[j].igu_sb_id,
1071 hc_sm_p[j].igu_seg_id,
1072 hc_sm_p[j].time_to_expire,
1073 hc_sm_p[j].timer_value);
523224a3
DK		 1074 }
1075
16a5fd92 1076 /* Indices data */
523224a3 1077 for (j = 0; j < loop; j++) {
51c1a580 1078 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1079 hc_index_p[j].flags,
1080 hc_index_p[j].timeout);
1081 }
8440d2b6 1082 }
a2fbb9ea 1083
523224a3 1084#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1085 if (IS_PF(bp)) {
1086 /* event queue */
1087 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1088 for (i = 0; i < NUM_EQ_DESC; i++) {
1089 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1090
1091 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1092 i, bp->eq_ring[i].message.opcode,
1093 bp->eq_ring[i].message.error);
1094 BNX2X_ERR("data: %x %x %x\n",
1095 data[0], data[1], data[2]);
1096 }
04c46736
YM		 1097 }
1098
8440d2b6
EG		 1099 /* Rings */
1100 /* Rx */
55c11941 1101 for_each_valid_rx_queue(bp, i) {
8440d2b6 1102 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 1103
1104 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1105 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1106 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1107 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1108 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1109
c3eefaf6 1110 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1111 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1112 }
1113
3196a88a
EG		 1114 start = RX_SGE(fp->rx_sge_prod);
1115 end = RX_SGE(fp->last_max_sge);
8440d2b6 1116 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1117 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1118 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1119
c3eefaf6
EG		 1120 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1121 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1122 }
1123
a2fbb9ea
ET		 1124 start = RCQ_BD(fp->rx_comp_cons - 10);
1125 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1126 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1127 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1128
c3eefaf6
EG		 1129 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1130 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1131 }
1132 }
1133
8440d2b6 1134 /* Tx */
55c11941 1135 for_each_valid_tx_queue(bp, i) {
8440d2b6 1136 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3 1137 for_each_cos_in_tx_queue(fp, cos) {
65565884 1138 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3
AE		 1139
1140 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1141 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1142 for (j = start; j != end; j = TX_BD(j + 1)) {
1143 struct sw_tx_bd *sw_bd =
1144 &txdata->tx_buf_ring[j];
1145
51c1a580 1146 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1147 i, cos, j, sw_bd->skb,
1148 sw_bd->first_bd);
1149 }
8440d2b6 1150
6383c0b3
AE		 1151 start = TX_BD(txdata->tx_bd_cons - 10);
1152 end = TX_BD(txdata->tx_bd_cons + 254);
1153 for (j = start; j != end; j = TX_BD(j + 1)) {
1154 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1155
51c1a580 1156 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1157 i, cos, j, tx_bd[0], tx_bd[1],
1158 tx_bd[2], tx_bd[3]);
1159 }
8440d2b6
EG		 1160 }
1161 }
523224a3 1162#endif
0155a27c
YM		 1163 if (IS_PF(bp)) {
1164 bnx2x_fw_dump(bp);
1165 bnx2x_mc_assert(bp);
1166 }
a2fbb9ea 1167 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1168}
1169
619c5cb6
VZ		 1170/*
1171 * FLR Support for E2
1172 *
1173 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1174 * initialization.
1175 */
16a5fd92 1176#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1177#define FLR_WAIT_INTERVAL 50 /* usec */
1178#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1179
1180struct pbf_pN_buf_regs {
1181 int pN;
1182 u32 init_crd;
1183 u32 crd;
1184 u32 crd_freed;
1185};
1186
1187struct pbf_pN_cmd_regs {
1188 int pN;
1189 u32 lines_occup;
1190 u32 lines_freed;
1191};
1192
1193static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1194 struct pbf_pN_buf_regs *regs,
1195 u32 poll_count)
1196{
1197 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1198 u32 cur_cnt = poll_count;
1199
1200 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1201 crd = crd_start = REG_RD(bp, regs->crd);
1202 init_crd = REG_RD(bp, regs->init_crd);
1203
1204 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1205 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1206 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1207
1208 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1209 (init_crd - crd_start))) {
1210 if (cur_cnt--) {
89db4ad8 1211 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1212 crd = REG_RD(bp, regs->crd);
1213 crd_freed = REG_RD(bp, regs->crd_freed);
1214 } else {
1215 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1216 regs->pN);
1217 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1218 regs->pN, crd);
1219 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1220 regs->pN, crd_freed);
1221 break;
1222 }
1223 }
1224 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1225 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1226}
1227
1228static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1229 struct pbf_pN_cmd_regs *regs,
1230 u32 poll_count)
1231{
1232 u32 occup, to_free, freed, freed_start;
1233 u32 cur_cnt = poll_count;
1234
1235 occup = to_free = REG_RD(bp, regs->lines_occup);
1236 freed = freed_start = REG_RD(bp, regs->lines_freed);
1237
1238 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1239 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1240
1241 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1242 if (cur_cnt--) {
89db4ad8 1243 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1244 occup = REG_RD(bp, regs->lines_occup);
1245 freed = REG_RD(bp, regs->lines_freed);
1246 } else {
1247 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1248 regs->pN);
1249 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1250 regs->pN, occup);
1251 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1252 regs->pN, freed);
1253 break;
1254 }
1255 }
1256 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1257 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1258}
1259
1191cb83
ED		 1260static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1261 u32 expected, u32 poll_count)
619c5cb6
VZ		 1262{
1263 u32 cur_cnt = poll_count;
1264 u32 val;
1265
1266 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1267 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1268
1269 return val;
1270}
1271
d16132ce
AE		 1272int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1273 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1274{
1275 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1276 if (val != 0) {
1277 BNX2X_ERR("%s usage count=%d\n", msg, val);
1278 return 1;
1279 }
1280 return 0;
1281}
1282
d16132ce
AE		 1283/* Common routines with VF FLR cleanup */
1284u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1285{
1286 /* adjust polling timeout */
1287 if (CHIP_REV_IS_EMUL(bp))
1288 return FLR_POLL_CNT * 2000;
1289
1290 if (CHIP_REV_IS_FPGA(bp))
1291 return FLR_POLL_CNT * 120;
1292
1293 return FLR_POLL_CNT;
1294}
1295
d16132ce 1296void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1297{
1298 struct pbf_pN_cmd_regs cmd_regs[] = {
1299 {0, (CHIP_IS_E3B0(bp)) ?
1300 PBF_REG_TQ_OCCUPANCY_Q0 :
1301 PBF_REG_P0_TQ_OCCUPANCY,
1302 (CHIP_IS_E3B0(bp)) ?
1303 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1304 PBF_REG_P0_TQ_LINES_FREED_CNT},
1305 {1, (CHIP_IS_E3B0(bp)) ?
1306 PBF_REG_TQ_OCCUPANCY_Q1 :
1307 PBF_REG_P1_TQ_OCCUPANCY,
1308 (CHIP_IS_E3B0(bp)) ?
1309 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1310 PBF_REG_P1_TQ_LINES_FREED_CNT},
1311 {4, (CHIP_IS_E3B0(bp)) ?
1312 PBF_REG_TQ_OCCUPANCY_LB_Q :
1313 PBF_REG_P4_TQ_OCCUPANCY,
1314 (CHIP_IS_E3B0(bp)) ?
1315 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1316 PBF_REG_P4_TQ_LINES_FREED_CNT}
1317 };
1318
1319 struct pbf_pN_buf_regs buf_regs[] = {
1320 {0, (CHIP_IS_E3B0(bp)) ?
1321 PBF_REG_INIT_CRD_Q0 :
1322 PBF_REG_P0_INIT_CRD ,
1323 (CHIP_IS_E3B0(bp)) ?
1324 PBF_REG_CREDIT_Q0 :
1325 PBF_REG_P0_CREDIT,
1326 (CHIP_IS_E3B0(bp)) ?
1327 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1328 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1329 {1, (CHIP_IS_E3B0(bp)) ?
1330 PBF_REG_INIT_CRD_Q1 :
1331 PBF_REG_P1_INIT_CRD,
1332 (CHIP_IS_E3B0(bp)) ?
1333 PBF_REG_CREDIT_Q1 :
1334 PBF_REG_P1_CREDIT,
1335 (CHIP_IS_E3B0(bp)) ?
1336 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1337 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1338 {4, (CHIP_IS_E3B0(bp)) ?
1339 PBF_REG_INIT_CRD_LB_Q :
1340 PBF_REG_P4_INIT_CRD,
1341 (CHIP_IS_E3B0(bp)) ?
1342 PBF_REG_CREDIT_LB_Q :
1343 PBF_REG_P4_CREDIT,
1344 (CHIP_IS_E3B0(bp)) ?
1345 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1346 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1347 };
1348
1349 int i;
1350
1351 /* Verify the command queues are flushed P0, P1, P4 */
1352 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1353 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1354
619c5cb6
VZ		 1355 /* Verify the transmission buffers are flushed P0, P1, P4 */
1356 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1357 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1358}
1359
1360#define OP_GEN_PARAM(param) \
1361 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1362
1363#define OP_GEN_TYPE(type) \
1364 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1365
1366#define OP_GEN_AGG_VECT(index) \
1367 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1368
d16132ce 1369int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1370{
86564c3f 1371 u32 op_gen_command = 0;
619c5cb6
VZ		 1372 u32 comp_addr = BAR_CSTRORM_INTMEM +
1373 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1374 int ret = 0;
1375
1376 if (REG_RD(bp, comp_addr)) {
89db4ad8 1377 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1378 return 1;
1379 }
1380
86564c3f
YM		 1381 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1382 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1383 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1384 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1385
89db4ad8 1386 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1387 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1388
1389 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1390 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1391 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1392 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1393 bnx2x_panic();
1394 return 1;
619c5cb6 1395 }
16a5fd92 1396 /* Zero completion for next FLR */
619c5cb6
VZ		 1397 REG_WR(bp, comp_addr, 0);
1398
1399 return ret;
1400}
1401
b56e9670 1402u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1403{
619c5cb6
VZ		 1404 u16 status;
1405
2a80eebc 1406 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1407 return status & PCI_EXP_DEVSTA_TRPND;
1408}
1409
1410/* PF FLR specific routines
1411*/
1412static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1413{
619c5cb6
VZ		 1414 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1415 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1416 CFC_REG_NUM_LCIDS_INSIDE_PF,
1417 "CFC PF usage counter timed out",
1418 poll_cnt))
1419 return 1;
1420
619c5cb6
VZ		 1421 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1422 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1423 DORQ_REG_PF_USAGE_CNT,
1424 "DQ PF usage counter timed out",
1425 poll_cnt))
1426 return 1;
1427
1428 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1429 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1430 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1431 "QM PF usage counter timed out",
1432 poll_cnt))
1433 return 1;
1434
1435 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1436 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1437 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1438 "Timers VNIC usage counter timed out",
1439 poll_cnt))
1440 return 1;
1441 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1442 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1443 "Timers NUM_SCANS usage counter timed out",
1444 poll_cnt))
1445 return 1;
1446
1447 /* Wait DMAE PF usage counter to zero */
1448 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1449 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1450 "DMAE command register timed out",
619c5cb6
VZ		 1451 poll_cnt))
1452 return 1;
1453
1454 return 0;
1455}
1456
1457static void bnx2x_hw_enable_status(struct bnx2x *bp)
1458{
1459 u32 val;
1460
1461 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1462 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1463
1464 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1465 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1466
1467 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1468 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1469
1470 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1471 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1472
1473 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1474 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1475
1476 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1477 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1478
1479 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1480 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1481
1482 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1483 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1484 val);
1485}
1486
1487static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1488{
1489 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1490
1491 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1492
1493 /* Re-enable PF target read access */
1494 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1495
1496 /* Poll HW usage counters */
89db4ad8 1497 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1498 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1499 return -EBUSY;
1500
1501 /* Zero the igu 'trailing edge' and 'leading edge' */
1502
1503 /* Send the FW cleanup command */
1504 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1505 return -EBUSY;
1506
1507 /* ATC cleanup */
1508
1509 /* Verify TX hw is flushed */
1510 bnx2x_tx_hw_flushed(bp, poll_cnt);
1511
1512 /* Wait 100ms (not adjusted according to platform) */
1513 msleep(100);
1514
1515 /* Verify no pending pci transactions */
1516 if (bnx2x_is_pcie_pending(bp->pdev))
1517 BNX2X_ERR("PCIE Transactions still pending\n");
1518
1519 /* Debug */
1520 bnx2x_hw_enable_status(bp);
1521
1522 /*
1523 * Master enable - Due to WB DMAE writes performed before this
1524 * register is re-initialized as part of the regular function init
1525 */
1526 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1527
1528 return 0;
1529}
1530
f2e0899f 1531static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1532{
34f80b04 1533 int port = BP_PORT(bp);
a2fbb9ea
ET		 1534 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1535 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1536 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1537 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1538 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1539
1540 if (msix) {
8badd27a
EG		 1541 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1542 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1543 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1544 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1545 if (single_msix)
1546 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1547 } else if (msi) {
1548 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1549 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1550 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1551 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1552 } else {
1553 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1554 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1555 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1556 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1557
a0fd065c 1558 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1559 DP(NETIF_MSG_IFUP,
1560 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1561
a0fd065c 1562 REG_WR(bp, addr, val);
615f8fd9 1563
a0fd065c
DK		 1564 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1565 }
a2fbb9ea
ET		 1566 }
1567
a0fd065c
DK		 1568 if (CHIP_IS_E1(bp))
1569 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1570
51c1a580
MS		 1571 DP(NETIF_MSG_IFUP,
1572 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1573 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1574
1575 REG_WR(bp, addr, val);
37dbbf32
EG		 1576 /*
1577 * Ensure that HC_CONFIG is written before leading/trailing edge config
1578 */
1579 mmiowb();
1580 barrier();
34f80b04 1581
f2e0899f 1582 if (!CHIP_IS_E1(bp)) {
34f80b04 1583 /* init leading/trailing edge */
fb3bff17 1584 if (IS_MF(bp)) {
3395a033 1585 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1586 if (bp->port.pmf)
4acac6a5
EG		 1587 /* enable nig and gpio3 attention */
1588 val |= 0x1100;
34f80b04
EG		 1589 } else
1590 val = 0xffff;
1591
1592 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1593 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1594 }
37dbbf32
EG		 1595
1596 /* Make sure that interrupts are indeed enabled from here on */
1597 mmiowb();
a2fbb9ea
ET		 1598}
1599
f2e0899f
DK		 1600static void bnx2x_igu_int_enable(struct bnx2x *bp)
1601{
1602 u32 val;
30a5de77
DK		 1603 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1604 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1605 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1606
1607 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1608
1609 if (msix) {
1610 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1611 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1612 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1613 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1614
1615 if (single_msix)
1616 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1617 } else if (msi) {
1618 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1619 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1620 IGU_PF_CONF_ATTN_BIT_EN |
1621 IGU_PF_CONF_SINGLE_ISR_EN);
1622 } else {
1623 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1624 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1625 IGU_PF_CONF_ATTN_BIT_EN |
1626 IGU_PF_CONF_SINGLE_ISR_EN);
1627 }
1628
ebe61d80
YM		 1629 /* Clean previous status - need to configure igu prior to ack*/
1630 if ((!msix) || single_msix) {
1631 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1632 bnx2x_ack_int(bp);
1633 }
1634
1635 val |= IGU_PF_CONF_FUNC_EN;
1636
51c1a580 1637 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1638 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1639
1640 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1641
79a8557a
YM		 1642 if (val & IGU_PF_CONF_INT_LINE_EN)
1643 pci_intx(bp->pdev, true);
1644
f2e0899f
DK		 1645 barrier();
1646
1647 /* init leading/trailing edge */
1648 if (IS_MF(bp)) {
3395a033 1649 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1650 if (bp->port.pmf)
1651 /* enable nig and gpio3 attention */
1652 val |= 0x1100;
1653 } else
1654 val = 0xffff;
1655
1656 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1657 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1658
1659 /* Make sure that interrupts are indeed enabled from here on */
1660 mmiowb();
1661}
1662
1663void bnx2x_int_enable(struct bnx2x *bp)
1664{
1665 if (bp->common.int_block == INT_BLOCK_HC)
1666 bnx2x_hc_int_enable(bp);
1667 else
1668 bnx2x_igu_int_enable(bp);
1669}
1670
9f6c9258 1671void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1672{
a2fbb9ea 1673 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1674 int i, offset;
a2fbb9ea 1675
f8ef6e44
YG		 1676 if (disable_hw)
1677 /* prevent the HW from sending interrupts */
1678 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1679
1680 /* make sure all ISRs are done */
1681 if (msix) {
8badd27a
EG		 1682 synchronize_irq(bp->msix_table[0].vector);
1683 offset = 1;
55c11941
MS		 1684 if (CNIC_SUPPORT(bp))
1685 offset++;
ec6ba945 1686 for_each_eth_queue(bp, i)
754a2f52 1687 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1688 } else
1689 synchronize_irq(bp->pdev->irq);
1690
1691 /* make sure sp_task is not running */
1cf167f2 1692 cancel_delayed_work(&bp->sp_task);
3deb8167 1693 cancel_delayed_work(&bp->period_task);
1cf167f2 1694 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1695}
1696
34f80b04 1697/* fast path */
a2fbb9ea
ET		 1698
1699/*
34f80b04 1700 * General service functions
a2fbb9ea
ET		 1701 */
1702
72fd0718
VZ		 1703/* Return true if succeeded to acquire the lock */
1704static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1705{
1706 u32 lock_status;
1707 u32 resource_bit = (1 << resource);
1708 int func = BP_FUNC(bp);
1709 u32 hw_lock_control_reg;
1710
51c1a580
MS		 1711 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1712 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1713
1714 /* Validating that the resource is within range */
1715 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1716 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1717 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1718 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1719 return false;
72fd0718
VZ		 1720 }
1721
1722 if (func <= 5)
1723 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1724 else
1725 hw_lock_control_reg =
1726 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1727
1728 /* Try to acquire the lock */
1729 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1730 lock_status = REG_RD(bp, hw_lock_control_reg);
1731 if (lock_status & resource_bit)
1732 return true;
1733
51c1a580
MS		 1734 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1735 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1736 return false;
1737}
1738
c9ee9206
VZ		 1739/**
1740 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1741 *
1742 * @bp: driver handle
1743 *
1744 * Returns the recovery leader resource id according to the engine this function
1745 * belongs to. Currently only only 2 engines is supported.
1746 */
1191cb83 1747static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1748{
1749 if (BP_PATH(bp))
1750 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1751 else
1752 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1753}
1754
1755/**
2de67439 1756 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1757 *
1758 * @bp: driver handle
1759 *
2de67439 1760 * Tries to acquire a leader lock for current engine.
c9ee9206 1761 */
1191cb83 1762static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1763{
1764 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1765}
1766
619c5cb6 1767static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1768
fd1fc79d
AE		 1769/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1770static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1771{
1772 /* Set the interrupt occurred bit for the sp-task to recognize it
1773 * must ack the interrupt and transition according to the IGU
1774 * state machine.
1775 */
1776 atomic_set(&bp->interrupt_occurred, 1);
1777
1778 /* The sp_task must execute only after this bit
1779 * is set, otherwise we will get out of sync and miss all
1780 * further interrupts. Hence, the barrier.
1781 */
1782 smp_wmb();
1783
1784 /* schedule sp_task to workqueue */
1785 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1786}
3196a88a 1787
619c5cb6 1788void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1789{
1790 struct bnx2x *bp = fp->bp;
1791 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1792 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1793 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1794 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1795
34f80b04 1796 DP(BNX2X_MSG_SP,
a2fbb9ea 1797 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1798 fp->index, cid, command, bp->state,
34f80b04 1799 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1800
fd1fc79d
AE		 1801 /* If cid is within VF range, replace the slowpath object with the
1802 * one corresponding to this VF
1803 */
1804 if (cid >= BNX2X_FIRST_VF_CID &&
1805 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1806 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1807
619c5cb6
VZ		 1808 switch (command) {
1809 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1810 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1811 drv_cmd = BNX2X_Q_CMD_UPDATE;
1812 break;
d6cae238 1813
619c5cb6 1814 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1815 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1816 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1817 break;
1818
6383c0b3 1819 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1820 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1821 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1822 break;
1823
619c5cb6 1824 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1825 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1826 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1827 break;
1828
619c5cb6 1829 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1830 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1831 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1832 break;
1833
619c5cb6 1834 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1835 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1836 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1837 break;
619c5cb6 1838
14a94ebd
MK		 1839 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1840 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1841 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1842 break;
1843
619c5cb6
VZ		 1844 default:
1845 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1846 command, fp->index);
1847 return;
523224a3 1848 }
3196a88a 1849
619c5cb6
VZ		 1850 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1851 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1852 /* q_obj->complete_cmd() failure means that this was
1853 * an unexpected completion.
1854 *
1855 * In this case we don't want to increase the bp->spq_left
1856 * because apparently we haven't sent this command the first
1857 * place.
1858 */
1859#ifdef BNX2X_STOP_ON_ERROR
1860 bnx2x_panic();
1861#else
1862 return;
1863#endif
1864
4e857c58 1865 smp_mb__before_atomic();
6e30dd4e 1866 atomic_inc(&bp->cq_spq_left);
619c5cb6 1867 /* push the change in bp->spq_left and towards the memory */
4e857c58 1868 smp_mb__after_atomic();
49d66772 1869
d6cae238
VZ		 1870 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1871
a3348722
BW		 1872 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1873 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1874 /* if Q update ramrod is completed for last Q in AFEX vif set
1875 * flow, then ACK MCP at the end
1876 *
1877 * mark pending ACK to MCP bit.
1878 * prevent case that both bits are cleared.
1879 * At the end of load/unload driver checks that
2de67439 1880 * sp_state is cleared, and this order prevents
a3348722
BW		 1881 * races
1882 */
4e857c58 1883 smp_mb__before_atomic();
a3348722
BW		 1884 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1885 wmb();
1886 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 1887 smp_mb__after_atomic();
a3348722 1888
fd1fc79d
AE		 1889 /* schedule the sp task as mcp ack is required */
1890 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1891 }
1892
523224a3 1893 return;
a2fbb9ea
ET		 1894}
1895
9f6c9258 1896irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1897{
555f6c78 1898 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1899 u16 status = bnx2x_ack_int(bp);
34f80b04 1900 u16 mask;
ca00392c 1901 int i;
6383c0b3 1902 u8 cos;
a2fbb9ea 1903
34f80b04 1904 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1905 if (unlikely(status == 0)) {
1906 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1907 return IRQ_NONE;
1908 }
f5372251 1909 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1910
3196a88a
EG		 1911#ifdef BNX2X_STOP_ON_ERROR
1912 if (unlikely(bp->panic))
1913 return IRQ_HANDLED;
1914#endif
1915
ec6ba945 1916 for_each_eth_queue(bp, i) {
ca00392c 1917 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1918
55c11941 1919 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1920 if (status & mask) {
619c5cb6 1921 /* Handle Rx or Tx according to SB id */
6383c0b3 1922 for_each_cos_in_tx_queue(fp, cos)
65565884 1923 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1924 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1925 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1926 status &= ~mask;
1927 }
a2fbb9ea
ET		 1928 }
1929
55c11941
MS		 1930 if (CNIC_SUPPORT(bp)) {
1931 mask = 0x2;
1932 if (status & (mask | 0x1)) {
1933 struct cnic_ops *c_ops = NULL;
993ac7b5 1934
ad9b4359
MC		 1935 rcu_read_lock();
1936 c_ops = rcu_dereference(bp->cnic_ops);
1937 if (c_ops && (bp->cnic_eth_dev.drv_state &
1938 CNIC_DRV_STATE_HANDLES_IRQ))
1939 c_ops->cnic_handler(bp->cnic_data, NULL);
1940 rcu_read_unlock();
993ac7b5 1941
55c11941
MS		 1942 status &= ~mask;
1943 }
993ac7b5 1944 }
a2fbb9ea 1945
34f80b04 1946 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1947
1948 /* schedule sp task to perform default status block work, ack
1949 * attentions and enable interrupts.
1950 */
1951 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1952
1953 status &= ~0x1;
1954 if (!status)
1955 return IRQ_HANDLED;
1956 }
1957
cdaa7cb8
VZ		 1958 if (unlikely(status))
1959 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1960 status);
a2fbb9ea 1961
c18487ee 1962 return IRQ_HANDLED;
a2fbb9ea
ET		 1963}
1964
c18487ee
YR		 1965/* Link */
1966
1967/*
1968 * General service functions
1969 */
a2fbb9ea 1970
9f6c9258 1971int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1972{
1973 u32 lock_status;
1974 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1975 int func = BP_FUNC(bp);
1976 u32 hw_lock_control_reg;
c18487ee 1977 int cnt;
a2fbb9ea 1978
c18487ee
YR		 1979 /* Validating that the resource is within range */
1980 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1981 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1982 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1983 return -EINVAL;
1984 }
a2fbb9ea 1985
4a37fb66
YG		 1986 if (func <= 5) {
1987 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1988 } else {
1989 hw_lock_control_reg =
1990 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1991 }
1992
c18487ee 1993 /* Validating that the resource is not already taken */
4a37fb66 1994 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1995 if (lock_status & resource_bit) {
51c1a580 1996 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 1997 lock_status, resource_bit);
1998 return -EEXIST;
1999 }
a2fbb9ea 2000
46230476
EG		 2001 /* Try for 5 second every 5ms */
2002 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 2003 /* Try to acquire the lock */
4a37fb66
YG		 2004 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2005 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2006 if (lock_status & resource_bit)
2007 return 0;
a2fbb9ea 2008
639d65b8 2009 usleep_range(5000, 10000);
a2fbb9ea 2010 }
51c1a580 2011 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2012 return -EAGAIN;
2013}
a2fbb9ea 2014
c9ee9206
VZ		 2015int bnx2x_release_leader_lock(struct bnx2x *bp)
2016{
2017 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2018}
2019
9f6c9258 2020int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2021{
2022 u32 lock_status;
2023 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2024 int func = BP_FUNC(bp);
2025 u32 hw_lock_control_reg;
a2fbb9ea 2026
c18487ee
YR		 2027 /* Validating that the resource is within range */
2028 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2029 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2030 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2031 return -EINVAL;
2032 }
2033
4a37fb66
YG		 2034 if (func <= 5) {
2035 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2036 } else {
2037 hw_lock_control_reg =
2038 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2039 }
2040
c18487ee 2041 /* Validating that the resource is currently taken */
4a37fb66 2042 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2043 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2044 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2045 lock_status, resource_bit);
c18487ee 2046 return -EFAULT;
a2fbb9ea
ET		 2047 }
2048
9f6c9258
DK		 2049 REG_WR(bp, hw_lock_control_reg, resource_bit);
2050 return 0;
c18487ee 2051}
a2fbb9ea 2052
4acac6a5
EG		 2053int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2054{
2055 /* The GPIO should be swapped if swap register is set and active */
2056 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2057 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2058 int gpio_shift = gpio_num +
2059 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2060 u32 gpio_mask = (1 << gpio_shift);
2061 u32 gpio_reg;
2062 int value;
2063
2064 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2065 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2066 return -EINVAL;
2067 }
2068
2069 /* read GPIO value */
2070 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2071
2072 /* get the requested pin value */
2073 if ((gpio_reg & gpio_mask) == gpio_mask)
2074 value = 1;
2075 else
2076 value = 0;
2077
2078 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2079
2080 return value;
2081}
2082
17de50b7 2083int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2084{
2085 /* The GPIO should be swapped if swap register is set and active */
2086 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2087 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2088 int gpio_shift = gpio_num +
2089 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2090 u32 gpio_mask = (1 << gpio_shift);
2091 u32 gpio_reg;
a2fbb9ea 2092
c18487ee
YR		 2093 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2094 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2095 return -EINVAL;
2096 }
a2fbb9ea 2097
4a37fb66 2098 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2099 /* read GPIO and mask except the float bits */
2100 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2101
c18487ee
YR		 2102 switch (mode) {
2103 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2104 DP(NETIF_MSG_LINK,
2105 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2106 gpio_num, gpio_shift);
2107 /* clear FLOAT and set CLR */
2108 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2109 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2110 break;
a2fbb9ea 2111
c18487ee 2112 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2113 DP(NETIF_MSG_LINK,
2114 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2115 gpio_num, gpio_shift);
2116 /* clear FLOAT and set SET */
2117 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2118 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2119 break;
a2fbb9ea 2120
17de50b7 2121 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2122 DP(NETIF_MSG_LINK,
2123 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2124 gpio_num, gpio_shift);
2125 /* set FLOAT */
2126 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2127 break;
a2fbb9ea 2128
c18487ee
YR		 2129 default:
2130 break;
a2fbb9ea
ET		 2131 }
2132
c18487ee 2133 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2134 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2135
c18487ee 2136 return 0;
a2fbb9ea
ET		 2137}
2138
0d40f0d4
YR		 2139int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2140{
2141 u32 gpio_reg = 0;
2142 int rc = 0;
2143
2144 /* Any port swapping should be handled by caller. */
2145
2146 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2147 /* read GPIO and mask except the float bits */
2148 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2149 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2150 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2151 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2152
2153 switch (mode) {
2154 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2155 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2156 /* set CLR */
2157 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2158 break;
2159
2160 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2161 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2162 /* set SET */
2163 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2164 break;
2165
2166 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2167 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2168 /* set FLOAT */
2169 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2170 break;
2171
2172 default:
2173 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2174 rc = -EINVAL;
2175 break;
2176 }
2177
2178 if (rc == 0)
2179 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2180
2181 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2182
2183 return rc;
2184}
2185
4acac6a5
EG		 2186int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2187{
2188 /* The GPIO should be swapped if swap register is set and active */
2189 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2190 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2191 int gpio_shift = gpio_num +
2192 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2193 u32 gpio_mask = (1 << gpio_shift);
2194 u32 gpio_reg;
2195
2196 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2197 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2198 return -EINVAL;
2199 }
2200
2201 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2202 /* read GPIO int */
2203 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2204
2205 switch (mode) {
2206 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2207 DP(NETIF_MSG_LINK,
2208 "Clear GPIO INT %d (shift %d) -> output low\n",
2209 gpio_num, gpio_shift);
4acac6a5
EG		 2210 /* clear SET and set CLR */
2211 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2212 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2213 break;
2214
2215 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2216 DP(NETIF_MSG_LINK,
2217 "Set GPIO INT %d (shift %d) -> output high\n",
2218 gpio_num, gpio_shift);
4acac6a5
EG		 2219 /* clear CLR and set SET */
2220 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2221 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2222 break;
2223
2224 default:
2225 break;
2226 }
2227
2228 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2229 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2230
2231 return 0;
2232}
2233
d6d99a3f 2234static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2235{
c18487ee 2236 u32 spio_reg;
a2fbb9ea 2237
d6d99a3f
YM		 2238 /* Only 2 SPIOs are configurable */
2239 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2240 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2241 return -EINVAL;
a2fbb9ea
ET		 2242 }
2243
4a37fb66 2244 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2245 /* read SPIO and mask except the float bits */
d6d99a3f 2246 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2247
c18487ee 2248 switch (mode) {
d6d99a3f
YM		 2249 case MISC_SPIO_OUTPUT_LOW:
2250 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2251 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2252 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2253 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2254 break;
a2fbb9ea 2255
d6d99a3f
YM		 2256 case MISC_SPIO_OUTPUT_HIGH:
2257 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2258 /* clear FLOAT and set SET */
d6d99a3f
YM		 2259 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2260 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2261 break;
a2fbb9ea 2262
d6d99a3f
YM		 2263 case MISC_SPIO_INPUT_HI_Z:
2264 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2265 /* set FLOAT */
d6d99a3f 2266 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2267 break;
a2fbb9ea 2268
c18487ee
YR		 2269 default:
2270 break;
a2fbb9ea
ET		 2271 }
2272
c18487ee 2273 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2274 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2275
a2fbb9ea
ET		 2276 return 0;
2277}
2278
9f6c9258 2279void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2280{
a22f0788 2281 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2282 switch (bp->link_vars.ieee_fc &
2283 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2284 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2285 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2286 ADVERTISED_Pause);
c18487ee 2287 break;
356e2385 2288
c18487ee 2289 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2290 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2291 ADVERTISED_Pause);
c18487ee 2292 break;
356e2385 2293
c18487ee 2294 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2295 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2296 break;
356e2385 2297
c18487ee 2298 default:
a22f0788 2299 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2300 ADVERTISED_Pause);
c18487ee
YR		 2301 break;
2302 }
2303}
f1410647 2304
cd1dfce2 2305static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2306{
cd1dfce2
YM		 2307 /* Initialize link parameters structure variables
2308 * It is recommended to turn off RX FC for jumbo frames
2309 * for better performance
2310 */
2311 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2312 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2313 else
2314 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2315}
a2fbb9ea 2316
9156b30b
DK		 2317static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2318{
2319 u32 pause_enabled = 0;
2320
2321 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2322 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2323 pause_enabled = 1;
2324
2325 REG_WR(bp, BAR_USTRORM_INTMEM +
2326 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2327 pause_enabled);
2328 }
2329
2330 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2331 pause_enabled ? "enabled" : "disabled");
2332}
2333
cd1dfce2
YM		 2334int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2335{
2336 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2337 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2338
2339 if (!BP_NOMCP(bp)) {
2340 bnx2x_set_requested_fc(bp);
4a37fb66 2341 bnx2x_acquire_phy_lock(bp);
b5bf9068 2342
a22f0788 2343 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2344 struct link_params *lp = &bp->link_params;
2345 lp->loopback_mode = LOOPBACK_XGXS;
2346 /* do PHY loopback at 10G speed, if possible */
2347 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2348 if (lp->speed_cap_mask[cfx_idx] &
2349 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2350 lp->req_line_speed[cfx_idx] =
2351 SPEED_10000;
2352 else
2353 lp->req_line_speed[cfx_idx] =
2354 SPEED_1000;
2355 }
a22f0788 2356 }
b5bf9068 2357
8970b2e4
MS		 2358 if (load_mode == LOAD_LOOPBACK_EXT) {
2359 struct link_params *lp = &bp->link_params;
2360 lp->loopback_mode = LOOPBACK_EXT;
2361 }
2362
19680c48 2363 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2364
4a37fb66 2365 bnx2x_release_phy_lock(bp);
a2fbb9ea 2366
9156b30b
DK		 2367 bnx2x_init_dropless_fc(bp);
2368
3c96c68b
EG		 2369 bnx2x_calc_fc_adv(bp);
2370
cd1dfce2 2371 if (bp->link_vars.link_up) {
b5bf9068 2372 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2373 bnx2x_link_report(bp);
cd1dfce2
YM		 2374 }
2375 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2376 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2377 return rc;
2378 }
f5372251 2379 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2380 return -EINVAL;
a2fbb9ea
ET		 2381}
2382
9f6c9258 2383void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2384{
19680c48 2385 if (!BP_NOMCP(bp)) {
4a37fb66 2386 bnx2x_acquire_phy_lock(bp);
19680c48 2387 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2388 bnx2x_release_phy_lock(bp);
a2fbb9ea 2389
9156b30b
DK		 2390 bnx2x_init_dropless_fc(bp);
2391
19680c48
EG		 2392 bnx2x_calc_fc_adv(bp);
2393 } else
f5372251 2394 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2395}
a2fbb9ea 2396
c18487ee
YR		 2397static void bnx2x__link_reset(struct bnx2x *bp)
2398{
19680c48 2399 if (!BP_NOMCP(bp)) {
4a37fb66 2400 bnx2x_acquire_phy_lock(bp);
5d07d868 2401 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2402 bnx2x_release_phy_lock(bp);
19680c48 2403 } else
f5372251 2404 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2405}
a2fbb9ea 2406
5d07d868
YM		 2407void bnx2x_force_link_reset(struct bnx2x *bp)
2408{
2409 bnx2x_acquire_phy_lock(bp);
2410 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2411 bnx2x_release_phy_lock(bp);
2412}
2413
a22f0788 2414u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2415{
2145a920 2416 u8 rc = 0;
a2fbb9ea 2417
2145a920
VZ		 2418 if (!BP_NOMCP(bp)) {
2419 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2420 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2421 is_serdes);
2145a920
VZ		 2422 bnx2x_release_phy_lock(bp);
2423 } else
2424 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2425
c18487ee
YR		 2426 return rc;
2427}
a2fbb9ea 2428
2691d51d
EG		 2429/* Calculates the sum of vn_min_rates.
2430 It's needed for further normalizing of the min_rates.
2431 Returns:
2432 sum of vn_min_rates.
2433 or
2434 0 - if all the min_rates are 0.
16a5fd92 2435 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2436 If not all min_rates are zero then those that are zeroes will be set to 1.
2437 */
b475d78f
YM		 2438static void bnx2x_calc_vn_min(struct bnx2x *bp,
2439 struct cmng_init_input *input)
2691d51d
EG		 2440{
2441 int all_zero = 1;
2691d51d
EG		 2442 int vn;
2443
3395a033 2444 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2445 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2446 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2447 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2448
2449 /* Skip hidden vns */
2450 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2451 vn_min_rate = 0;
2691d51d 2452 /* If min rate is zero - set it to 1 */
b475d78f 2453 else if (!vn_min_rate)
2691d51d
EG		 2454 vn_min_rate = DEF_MIN_RATE;
2455 else
2456 all_zero = 0;
2457
b475d78f 2458 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2459 }
2460
30ae438b
DK		 2461 /* if ETS or all min rates are zeros - disable fairness */
2462 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2463 input->flags.cmng_enables &=
30ae438b
DK		 2464 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2465 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2466 } else if (all_zero) {
b475d78f 2467 input->flags.cmng_enables &=
b015e3d1 2468 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2469 DP(NETIF_MSG_IFUP,
2470 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2471 } else
b475d78f 2472 input->flags.cmng_enables |=
b015e3d1 2473 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2474}
2475
b475d78f
YM		 2476static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2477 struct cmng_init_input *input)
34f80b04 2478{
b475d78f 2479 u16 vn_max_rate;
f2e0899f 2480 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2481
b475d78f 2482 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2483 vn_max_rate = 0;
b475d78f 2484 else {
faa6fcbb
DK		 2485 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2486
b475d78f 2487 if (IS_MF_SI(bp)) {
faa6fcbb
DK		 2488 /* maxCfg in percents of linkspeed */
2489 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2490 } else /* SD modes */
faa6fcbb
DK		 2491 /* maxCfg is absolute in 100Mb units */
2492 vn_max_rate = maxCfg * 100;
34f80b04 2493 }
f85582f8 2494
b475d78f 2495 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2496
b475d78f 2497 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2498}
f85582f8 2499
523224a3
DK		 2500static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2501{
2502 if (CHIP_REV_IS_SLOW(bp))
2503 return CMNG_FNS_NONE;
fb3bff17 2504 if (IS_MF(bp))
523224a3
DK		 2505 return CMNG_FNS_MINMAX;
2506
2507 return CMNG_FNS_NONE;
2508}
2509
2ae17f66 2510void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2511{
0793f83f 2512 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2513
2514 if (BP_NOMCP(bp))
16a5fd92 2515 return; /* what should be the default value in this case */
523224a3 2516
0793f83f
DK		 2517 /* For 2 port configuration the absolute function number formula
2518 * is:
2519 * abs_func = 2 * vn + BP_PORT + BP_PATH
2520 *
2521 * and there are 4 functions per port
2522 *
2523 * For 4 port configuration it is
2524 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2525 *
2526 * and there are 2 functions per port
2527 */
3395a033 2528 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2529 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2530
2531 if (func >= E1H_FUNC_MAX)
2532 break;
2533
f2e0899f 2534 bp->mf_config[vn] =
523224a3
DK		 2535 MF_CFG_RD(bp, func_mf_config[func].config);
2536 }
a3348722
BW		 2537 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2538 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2539 bp->flags |= MF_FUNC_DIS;
2540 } else {
2541 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2542 bp->flags &= ~MF_FUNC_DIS;
2543 }
523224a3
DK		 2544}
2545
2546static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2547{
b475d78f
YM		 2548 struct cmng_init_input input;
2549 memset(&input, 0, sizeof(struct cmng_init_input));
2550
2551 input.port_rate = bp->link_vars.line_speed;
523224a3 2552
568e2426 2553 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2554 int vn;
2555
523224a3
DK		 2556 /* read mf conf from shmem */
2557 if (read_cfg)
2558 bnx2x_read_mf_cfg(bp);
2559
523224a3 2560 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2561 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2562
2563 /* calculate and set min-max rate for each vn */
c4154f25 2564 if (bp->port.pmf)
3395a033 2565 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2566 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2567
2568 /* always enable rate shaping and fairness */
b475d78f 2569 input.flags.cmng_enables |=
523224a3 2570 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2571
2572 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2573 return;
2574 }
2575
2576 /* rate shaping and fairness are disabled */
2577 DP(NETIF_MSG_IFUP,
2578 "rate shaping and fairness are disabled\n");
2579}
34f80b04 2580
1191cb83
ED		 2581static void storm_memset_cmng(struct bnx2x *bp,
2582 struct cmng_init *cmng,
2583 u8 port)
2584{
2585 int vn;
2586 size_t size = sizeof(struct cmng_struct_per_port);
2587
2588 u32 addr = BAR_XSTRORM_INTMEM +
2589 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2590
2591 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2592
2593 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2594 int func = func_by_vn(bp, vn);
2595
2596 addr = BAR_XSTRORM_INTMEM +
2597 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2598 size = sizeof(struct rate_shaping_vars_per_vn);
2599 __storm_memset_struct(bp, addr, size,
2600 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2601
2602 addr = BAR_XSTRORM_INTMEM +
2603 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2604 size = sizeof(struct fairness_vars_per_vn);
2605 __storm_memset_struct(bp, addr, size,
2606 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2607 }
2608}
2609
568e2426
DK		 2610/* init cmng mode in HW according to local configuration */
2611void bnx2x_set_local_cmng(struct bnx2x *bp)
2612{
2613 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2614
2615 if (cmng_fns != CMNG_FNS_NONE) {
2616 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2617 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2618 } else {
2619 /* rate shaping and fairness are disabled */
2620 DP(NETIF_MSG_IFUP,
2621 "single function mode without fairness\n");
2622 }
2623}
2624
c18487ee
YR		 2625/* This function is called upon link interrupt */
2626static void bnx2x_link_attn(struct bnx2x *bp)
2627{
bb2a0f7a
YG		 2628 /* Make sure that we are synced with the current statistics */
2629 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2630
c18487ee 2631 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2632
9156b30b 2633 bnx2x_init_dropless_fc(bp);
1c06328c 2634
9156b30b 2635 if (bp->link_vars.link_up) {
1c06328c 2636
619c5cb6 2637 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2638 struct host_port_stats *pstats;
2639
2640 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2641 /* reset old mac stats */
bb2a0f7a
YG		 2642 memset(&(pstats->mac_stx[0]), 0,
2643 sizeof(struct mac_stx));
2644 }
f34d28ea 2645 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2646 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2647 }
2648
568e2426
DK		 2649 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2650 bnx2x_set_local_cmng(bp);
9fdc3e95 2651
2ae17f66
VZ		 2652 __bnx2x_link_report(bp);
2653
9fdc3e95
DK		 2654 if (IS_MF(bp))
2655 bnx2x_link_sync_notify(bp);
c18487ee 2656}
a2fbb9ea 2657
9f6c9258 2658void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2659{
2ae17f66 2660 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2661 return;
a2fbb9ea 2662
00253a8c 2663 /* read updated dcb configuration */
ad5afc89
AE		 2664 if (IS_PF(bp)) {
2665 bnx2x_dcbx_pmf_update(bp);
2666 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2667 if (bp->link_vars.link_up)
2668 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2669 else
2670 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2671 /* indicate link status */
2672 bnx2x_link_report(bp);
a2fbb9ea 2673
ad5afc89
AE		 2674 } else { /* VF */
2675 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2676 SUPPORTED_10baseT_Full |
2677 SUPPORTED_100baseT_Half |
2678 SUPPORTED_100baseT_Full |
2679 SUPPORTED_1000baseT_Full |
2680 SUPPORTED_2500baseX_Full |
2681 SUPPORTED_10000baseT_Full |
2682 SUPPORTED_TP |
2683 SUPPORTED_FIBRE |
2684 SUPPORTED_Autoneg |
2685 SUPPORTED_Pause |
2686 SUPPORTED_Asym_Pause);
2687 bp->port.advertising[0] = bp->port.supported[0];
2688
2689 bp->link_params.bp = bp;
2690 bp->link_params.port = BP_PORT(bp);
2691 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2692 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2693 bp->link_params.req_line_speed[0] = SPEED_10000;
2694 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2695 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2696 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2697 bp->link_vars.line_speed = SPEED_10000;
2698 bp->link_vars.link_status =
2699 (LINK_STATUS_LINK_UP |
2700 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2701 bp->link_vars.link_up = 1;
2702 bp->link_vars.duplex = DUPLEX_FULL;
2703 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2704 __bnx2x_link_report(bp);
6495d15a
DK		 2705
2706 bnx2x_sample_bulletin(bp);
2707
2708 /* if bulletin board did not have an update for link status
2709 * __bnx2x_link_report will report current status
2710 * but it will NOT duplicate report in case of already reported
2711 * during sampling bulletin board.
2712 */
bb2a0f7a 2713 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2714 }
a2fbb9ea 2715}
a2fbb9ea 2716
a3348722
BW		 2717static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2718 u16 vlan_val, u8 allowed_prio)
2719{
86564c3f 2720 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2721 struct bnx2x_func_afex_update_params *f_update_params =
2722 &func_params.params.afex_update;
2723
2724 func_params.f_obj = &bp->func_obj;
2725 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2726
2727 /* no need to wait for RAMROD completion, so don't
2728 * set RAMROD_COMP_WAIT flag
2729 */
2730
2731 f_update_params->vif_id = vifid;
2732 f_update_params->afex_default_vlan = vlan_val;
2733 f_update_params->allowed_priorities = allowed_prio;
2734
2735 /* if ramrod can not be sent, response to MCP immediately */
2736 if (bnx2x_func_state_change(bp, &func_params) < 0)
2737 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2738
2739 return 0;
2740}
2741
2742static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2743 u16 vif_index, u8 func_bit_map)
2744{
86564c3f 2745 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2746 struct bnx2x_func_afex_viflists_params *update_params =
2747 &func_params.params.afex_viflists;
2748 int rc;
2749 u32 drv_msg_code;
2750
2751 /* validate only LIST_SET and LIST_GET are received from switch */
2752 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2753 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2754 cmd_type);
2755
2756 func_params.f_obj = &bp->func_obj;
2757 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2758
2759 /* set parameters according to cmd_type */
2760 update_params->afex_vif_list_command = cmd_type;
86564c3f 2761 update_params->vif_list_index = vif_index;
a3348722
BW		 2762 update_params->func_bit_map =
2763 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2764 update_params->func_to_clear = 0;
2765 drv_msg_code =
2766 (cmd_type == VIF_LIST_RULE_GET) ?
2767 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2768 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2769
2770 /* if ramrod can not be sent, respond to MCP immediately for
2771 * SET and GET requests (other are not triggered from MCP)
2772 */
2773 rc = bnx2x_func_state_change(bp, &func_params);
2774 if (rc < 0)
2775 bnx2x_fw_command(bp, drv_msg_code, 0);
2776
2777 return 0;
2778}
2779
2780static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2781{
2782 struct afex_stats afex_stats;
2783 u32 func = BP_ABS_FUNC(bp);
2784 u32 mf_config;
2785 u16 vlan_val;
2786 u32 vlan_prio;
2787 u16 vif_id;
2788 u8 allowed_prio;
2789 u8 vlan_mode;
2790 u32 addr_to_write, vifid, addrs, stats_type, i;
2791
2792 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2793 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2794 DP(BNX2X_MSG_MCP,
2795 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2796 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2797 }
2798
2799 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2800 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2801 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2802 DP(BNX2X_MSG_MCP,
2803 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2804 vifid, addrs);
2805 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2806 addrs);
2807 }
2808
2809 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2810 addr_to_write = SHMEM2_RD(bp,
2811 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2812 stats_type = SHMEM2_RD(bp,
2813 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2814
2815 DP(BNX2X_MSG_MCP,
2816 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2817 addr_to_write);
2818
2819 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2820
2821 /* write response to scratchpad, for MCP */
2822 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2823 REG_WR(bp, addr_to_write + i*sizeof(u32),
2824 *(((u32 *)(&afex_stats))+i));
2825
2826 /* send ack message to MCP */
2827 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2828 }
2829
2830 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2831 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2832 bp->mf_config[BP_VN(bp)] = mf_config;
2833 DP(BNX2X_MSG_MCP,
2834 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2835 mf_config);
2836
2837 /* if VIF_SET is "enabled" */
2838 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2839 /* set rate limit directly to internal RAM */
2840 struct cmng_init_input cmng_input;
2841 struct rate_shaping_vars_per_vn m_rs_vn;
2842 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2843 u32 addr = BAR_XSTRORM_INTMEM +
2844 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2845
2846 bp->mf_config[BP_VN(bp)] = mf_config;
2847
2848 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2849 m_rs_vn.vn_counter.rate =
2850 cmng_input.vnic_max_rate[BP_VN(bp)];
2851 m_rs_vn.vn_counter.quota =
2852 (m_rs_vn.vn_counter.rate *
2853 RS_PERIODIC_TIMEOUT_USEC) / 8;
2854
2855 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2856
2857 /* read relevant values from mf_cfg struct in shmem */
2858 vif_id =
2859 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2860 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2861 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2862 vlan_val =
2863 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2864 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2865 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2866 vlan_prio = (mf_config &
2867 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2868 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2869 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2870 vlan_mode =
2871 (MF_CFG_RD(bp,
2872 func_mf_config[func].afex_config) &
2873 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2874 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2875 allowed_prio =
2876 (MF_CFG_RD(bp,
2877 func_mf_config[func].afex_config) &
2878 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2879 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2880
2881 /* send ramrod to FW, return in case of failure */
2882 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2883 allowed_prio))
2884 return;
2885
2886 bp->afex_def_vlan_tag = vlan_val;
2887 bp->afex_vlan_mode = vlan_mode;
2888 } else {
2889 /* notify link down because BP->flags is disabled */
2890 bnx2x_link_report(bp);
2891
2892 /* send INVALID VIF ramrod to FW */
2893 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2894
2895 /* Reset the default afex VLAN */
2896 bp->afex_def_vlan_tag = -1;
2897 }
2898 }
2899}
2900
34f80b04
EG		 2901static void bnx2x_pmf_update(struct bnx2x *bp)
2902{
2903 int port = BP_PORT(bp);
2904 u32 val;
2905
2906 bp->port.pmf = 1;
51c1a580 2907 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2908
3deb8167
YR		 2909 /*
2910 * We need the mb() to ensure the ordering between the writing to
2911 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2912 */
2913 smp_mb();
2914
2915 /* queue a periodic task */
2916 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2917
ef01854e
DK		 2918 bnx2x_dcbx_pmf_update(bp);
2919
34f80b04 2920 /* enable nig attention */
3395a033 2921 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2922 if (bp->common.int_block == INT_BLOCK_HC) {
2923 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2924 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2925 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2926 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2927 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2928 }
bb2a0f7a
YG		 2929
2930 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2931}
2932
c18487ee 2933/* end of Link */
a2fbb9ea
ET		 2934
2935/* slow path */
2936
2937/*
2938 * General service functions
2939 */
2940
2691d51d 2941/* send the MCP a request, block until there is a reply */
a22f0788 2942u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2943{
f2e0899f 2944 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2945 u32 seq;
2691d51d
EG		 2946 u32 rc = 0;
2947 u32 cnt = 1;
2948 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2949
c4ff7cbf 2950 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2951 seq = ++bp->fw_seq;
f2e0899f
DK		 2952 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2953 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2954
754a2f52
DK		 2955 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2956 (command | seq), param);
2691d51d
EG		 2957
2958 do {
2959 /* let the FW do it's magic ... */
2960 msleep(delay);
2961
f2e0899f 2962 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2963
c4ff7cbf
EG		 2964 /* Give the FW up to 5 second (500*10ms) */
2965 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2966
2967 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2968 cnt*delay, rc, seq);
2969
2970 /* is this a reply to our command? */
2971 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2972 rc &= FW_MSG_CODE_MASK;
2973 else {
2974 /* FW BUG! */
2975 BNX2X_ERR("FW failed to respond!\n");
2976 bnx2x_fw_dump(bp);
2977 rc = 0;
2978 }
c4ff7cbf 2979 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2980
2981 return rc;
2982}
2983
1191cb83
ED		 2984static void storm_memset_func_cfg(struct bnx2x *bp,
2985 struct tstorm_eth_function_common_config *tcfg,
2986 u16 abs_fid)
2987{
2988 size_t size = sizeof(struct tstorm_eth_function_common_config);
2989
2990 u32 addr = BAR_TSTRORM_INTMEM +
2991 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2992
2993 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2994}
2995
619c5cb6
VZ		 2996void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2997{
2998 if (CHIP_IS_E1x(bp)) {
2999 struct tstorm_eth_function_common_config tcfg = {0};
3000
3001 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3002 }
3003
3004 /* Enable the function in the FW */
3005 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3006 storm_memset_func_en(bp, p->func_id, 1);
3007
3008 /* spq */
3009 if (p->func_flgs & FUNC_FLG_SPQ) {
3010 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3011 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3012 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3013 }
3014}
3015
6383c0b3 3016/**
16a5fd92 3017 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3018 *
3019 * @bp device handle
3020 * @fp queue handle
3021 * @zero_stats TRUE if statistics zeroing is needed
3022 *
3023 * Return the flags that are common for the Tx-only and not normal connections.
3024 */
1191cb83
ED		 3025static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3026 struct bnx2x_fastpath *fp,
3027 bool zero_stats)
28912902 3028{
619c5cb6
VZ		 3029 unsigned long flags = 0;
3030
3031 /* PF driver will always initialize the Queue to an ACTIVE state */
3032 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3033
6383c0b3 3034 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3035 * parent connection). The statistics are zeroed when the parent
3036 * connection is initialized.
6383c0b3 3037 */
50f0a562
BW		 3038
3039 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3040 if (zero_stats)
3041 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3042
c14db202
YM		 3043 if (bp->flags & TX_SWITCHING)
3044 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3045
91226790 3046 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3047 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3048
823e1d90
YM		 3049#ifdef BNX2X_STOP_ON_ERROR
3050 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3051#endif
3052
6383c0b3
AE		 3053 return flags;
3054}
3055
1191cb83
ED		 3056static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3057 struct bnx2x_fastpath *fp,
3058 bool leading)
6383c0b3
AE		 3059{
3060 unsigned long flags = 0;
3061
619c5cb6
VZ		 3062 /* calculate other queue flags */
3063 if (IS_MF_SD(bp))
3064 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3065
a3348722 3066 if (IS_FCOE_FP(fp)) {
619c5cb6 3067 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3068 /* For FCoE - force usage of default priority (for afex) */
3069 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3070 }
523224a3 3071
f5219d8e 3072 if (!fp->disable_tpa) {
619c5cb6 3073 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3074 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3075 if (fp->mode == TPA_MODE_GRO)
3076 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3077 }
619c5cb6 3078
619c5cb6
VZ		 3079 if (leading) {
3080 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3081 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3082 }
523224a3 3083
619c5cb6
VZ		 3084 /* Always set HW VLAN stripping */
3085 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3086
a3348722
BW		 3087 /* configure silent vlan removal */
3088 if (IS_MF_AFEX(bp))
3089 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3090
6383c0b3 3091 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3092}
3093
619c5cb6 3094static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3095 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3096 u8 cos)
619c5cb6
VZ		 3097{
3098 gen_init->stat_id = bnx2x_stats_id(fp);
3099 gen_init->spcl_id = fp->cl_id;
3100
3101 /* Always use mini-jumbo MTU for FCoE L2 ring */
3102 if (IS_FCOE_FP(fp))
3103 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3104 else
3105 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3106
3107 gen_init->cos = cos;
619c5cb6
VZ		 3108}
3109
3110static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3111 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3112 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3113{
619c5cb6 3114 u8 max_sge = 0;
523224a3
DK		 3115 u16 sge_sz = 0;
3116 u16 tpa_agg_size = 0;
3117
523224a3 3118 if (!fp->disable_tpa) {
dfacf138
DK		 3119 pause->sge_th_lo = SGE_TH_LO(bp);
3120 pause->sge_th_hi = SGE_TH_HI(bp);
3121
3122 /* validate SGE ring has enough to cross high threshold */
3123 WARN_ON(bp->dropless_fc &&
3124 pause->sge_th_hi + FW_PREFETCH_CNT >
3125 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3126
924d75ab 3127 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3128 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3129 SGE_PAGE_SHIFT;
3130 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3131 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3132 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3133 }
3134
3135 /* pause - not for e1 */
3136 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3137 pause->bd_th_lo = BD_TH_LO(bp);
3138 pause->bd_th_hi = BD_TH_HI(bp);
3139
3140 pause->rcq_th_lo = RCQ_TH_LO(bp);
3141 pause->rcq_th_hi = RCQ_TH_HI(bp);
3142 /*
3143 * validate that rings have enough entries to cross
3144 * high thresholds
3145 */
3146 WARN_ON(bp->dropless_fc &&
3147 pause->bd_th_hi + FW_PREFETCH_CNT >
3148 bp->rx_ring_size);
3149 WARN_ON(bp->dropless_fc &&
3150 pause->rcq_th_hi + FW_PREFETCH_CNT >
3151 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3152
523224a3
DK		 3153 pause->pri_map = 1;
3154 }
3155
3156 /* rxq setup */
523224a3
DK		 3157 rxq_init->dscr_map = fp->rx_desc_mapping;
3158 rxq_init->sge_map = fp->rx_sge_mapping;
3159 rxq_init->rcq_map = fp->rx_comp_mapping;
3160 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3161
619c5cb6
VZ		 3162 /* This should be a maximum number of data bytes that may be
3163 * placed on the BD (not including paddings).
3164 */
e52fcb24 3165 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3166 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3167
523224a3 3168 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3169 rxq_init->tpa_agg_sz = tpa_agg_size;
3170 rxq_init->sge_buf_sz = sge_sz;
3171 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3172 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3173 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3174
3175 /* Maximum number or simultaneous TPA aggregation for this Queue.
3176 *
2de67439 3177 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3178 * VF driver(s) may want to define it to a smaller value.
3179 */
dfacf138 3180 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3181
523224a3
DK		 3182 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3183 rxq_init->fw_sb_id = fp->fw_sb_id;
3184
ec6ba945
VZ		 3185 if (IS_FCOE_FP(fp))
3186 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3187 else
6383c0b3 3188 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3189 /* configure silent vlan removal
3190 * if multi function mode is afex, then mask default vlan
3191 */
3192 if (IS_MF_AFEX(bp)) {
3193 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3194 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3195 }
523224a3
DK		 3196}
3197
619c5cb6 3198static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3199 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3200 u8 cos)
523224a3 3201{
65565884 3202 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3203 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3204 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3205 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3206
619c5cb6 3207 /*
16a5fd92 3208 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3209 * leading RSS client id
3210 */
3211 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3212
ec6ba945
VZ		 3213 if (IS_FCOE_FP(fp)) {
3214 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3215 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3216 }
523224a3
DK		 3217}
3218
8d96286a 3219static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3220{
3221 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 3222 struct event_ring_data eq_data = { {0} };
3223 u16 flags;
3224
619c5cb6 3225 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3226 /* reset IGU PF statistics: MSIX + ATTN */
3227 /* PF */
3228 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3229 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3230 (CHIP_MODE_IS_4_PORT(bp) ?
3231 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3232 /* ATTN */
3233 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3234 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3235 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3236 (CHIP_MODE_IS_4_PORT(bp) ?
3237 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3238 }
3239
523224a3
DK		 3240 /* function setup flags */
3241 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3242
619c5cb6
VZ		 3243 /* This flag is relevant for E1x only.
3244 * E2 doesn't have a TPA configuration in a function level.
523224a3 3245 */
619c5cb6 3246 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 3247
3248 func_init.func_flgs = flags;
3249 func_init.pf_id = BP_FUNC(bp);
3250 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3251 func_init.spq_map = bp->spq_mapping;
3252 func_init.spq_prod = bp->spq_prod_idx;
3253
3254 bnx2x_func_init(bp, &func_init);
3255
3256 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3257
3258 /*
619c5cb6
VZ		 3259 * Congestion management values depend on the link rate
3260 * There is no active link so initial link rate is set to 10 Gbps.
3261 * When the link comes up The congestion management values are
3262 * re-calculated according to the actual link rate.
3263 */
523224a3
DK		 3264 bp->link_vars.line_speed = SPEED_10000;
3265 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3266
3267 /* Only the PMF sets the HW */
3268 if (bp->port.pmf)
3269 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3270
86564c3f 3271 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3272 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3273 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3274 eq_data.producer = bp->eq_prod;
3275 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3276 eq_data.sb_id = DEF_SB_ID;
3277 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3278}
3279
523224a3
DK		 3280static void bnx2x_e1h_disable(struct bnx2x *bp)
3281{
3282 int port = BP_PORT(bp);
3283
619c5cb6 3284 bnx2x_tx_disable(bp);
523224a3
DK		 3285
3286 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3287}
3288
3289static void bnx2x_e1h_enable(struct bnx2x *bp)
3290{
3291 int port = BP_PORT(bp);
3292
3293 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3294
16a5fd92 3295 /* Tx queue should be only re-enabled */
523224a3
DK		 3296 netif_tx_wake_all_queues(bp->dev);
3297
3298 /*
3299 * Should not call netif_carrier_on since it will be called if the link
3300 * is up when checking for link state
3301 */
3302}
3303
1d187b34
BW		 3304#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3305
3306static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3307{
3308 struct eth_stats_info *ether_stat =
3309 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3310 struct bnx2x_vlan_mac_obj *mac_obj =
3311 &bp->sp_objs->mac_obj;
3312 int i;
1d187b34 3313
786fdf0b
DC		 3314 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3315 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3316
3ec9f9ca
AE		 3317 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3318 * mac_local field in ether_stat struct. The base address is offset by 2
3319 * bytes to account for the field being 8 bytes but a mac address is
3320 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3321 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3322 * allocated by the ether_stat struct, so the macs will land in their
3323 * proper positions.
3324 */
3325 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3326 memset(ether_stat->mac_local + i, 0,
3327 sizeof(ether_stat->mac_local[0]));
3328 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3329 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3330 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3331 ETH_ALEN);
1d187b34 3332 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3333 if (bp->dev->features & NETIF_F_RXCSUM)
3334 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3335 if (bp->dev->features & NETIF_F_TSO)
3336 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3337 ether_stat->feature_flags |= bp->common.boot_mode;
3338
3339 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3340
3341 ether_stat->txq_size = bp->tx_ring_size;
3342 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3343
fcf93a0a 3344#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3345 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3346#endif
1d187b34
BW		 3347}
3348
3349static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3350{
3351 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3352 struct fcoe_stats_info *fcoe_stat =
3353 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3354
55c11941
MS		 3355 if (!CNIC_LOADED(bp))
3356 return;
3357
3ec9f9ca 3358 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3359
3360 fcoe_stat->qos_priority =
3361 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3362
3363 /* insert FCoE stats from ramrod response */
3364 if (!NO_FCOE(bp)) {
3365 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3366 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3367 tstorm_queue_statistics;
3368
3369 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3370 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3371 xstorm_queue_statistics;
3372
3373 struct fcoe_statistics_params *fw_fcoe_stat =
3374 &bp->fw_stats_data->fcoe;
3375
86564c3f
YM		 3376 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3377 fcoe_stat->rx_bytes_lo,
3378 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3379
86564c3f
YM		 3380 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3381 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3382 fcoe_stat->rx_bytes_lo,
3383 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3384
86564c3f
YM		 3385 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3386 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3387 fcoe_stat->rx_bytes_lo,
3388 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3389
86564c3f
YM		 3390 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3391 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3392 fcoe_stat->rx_bytes_lo,
3393 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3394
86564c3f
YM		 3395 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3396 fcoe_stat->rx_frames_lo,
3397 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3398
86564c3f
YM		 3399 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3400 fcoe_stat->rx_frames_lo,
3401 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3402
86564c3f
YM		 3403 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3404 fcoe_stat->rx_frames_lo,
3405 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3406
86564c3f
YM		 3407 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3408 fcoe_stat->rx_frames_lo,
3409 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3410
86564c3f
YM		 3411 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3412 fcoe_stat->tx_bytes_lo,
3413 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3414
86564c3f
YM		 3415 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3416 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3417 fcoe_stat->tx_bytes_lo,
3418 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3419
86564c3f
YM		 3420 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3421 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3422 fcoe_stat->tx_bytes_lo,
3423 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3424
86564c3f
YM		 3425 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3426 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3427 fcoe_stat->tx_bytes_lo,
3428 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3429
86564c3f
YM		 3430 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3431 fcoe_stat->tx_frames_lo,
3432 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3433
86564c3f
YM		 3434 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3435 fcoe_stat->tx_frames_lo,
3436 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3437
86564c3f
YM		 3438 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3439 fcoe_stat->tx_frames_lo,
3440 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3441
86564c3f
YM		 3442 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3443 fcoe_stat->tx_frames_lo,
3444 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3445 }
3446
1d187b34
BW		 3447 /* ask L5 driver to add data to the struct */
3448 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3449}
3450
3451static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3452{
3453 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3454 struct iscsi_stats_info *iscsi_stat =
3455 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3456
55c11941
MS		 3457 if (!CNIC_LOADED(bp))
3458 return;
3459
3ec9f9ca
AE		 3460 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3461 ETH_ALEN);
1d187b34
BW		 3462
3463 iscsi_stat->qos_priority =
3464 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3465
1d187b34
BW		 3466 /* ask L5 driver to add data to the struct */
3467 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3468}
3469
0793f83f
DK		 3470/* called due to MCP event (on pmf):
3471 * reread new bandwidth configuration
3472 * configure FW
3473 * notify others function about the change
3474 */
1191cb83 3475static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3476{
3477 if (bp->link_vars.link_up) {
3478 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3479 bnx2x_link_sync_notify(bp);
3480 }
3481 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3482}
3483
1191cb83 3484static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3485{
3486 bnx2x_config_mf_bw(bp);
3487 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3488}
3489
c8c60d88
YM		 3490static void bnx2x_handle_eee_event(struct bnx2x *bp)
3491{
3492 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3493 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3494}
3495
42f8277f
YM		 3496#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3497#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3498
1d187b34
BW		 3499static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3500{
3501 enum drv_info_opcode op_code;
3502 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
42f8277f
YM		 3503 bool release = false;
3504 int wait;
1d187b34
BW		 3505
3506 /* if drv_info version supported by MFW doesn't match - send NACK */
3507 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3508 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3509 return;
3510 }
3511
3512 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3513 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3514
42f8277f
YM		 3515 /* Must prevent other flows from accessing drv_info_to_mcp */
3516 mutex_lock(&bp->drv_info_mutex);
3517
1d187b34
BW		 3518 memset(&bp->slowpath->drv_info_to_mcp, 0,
3519 sizeof(union drv_info_to_mcp));
3520
3521 switch (op_code) {
3522 case ETH_STATS_OPCODE:
3523 bnx2x_drv_info_ether_stat(bp);
3524 break;
3525 case FCOE_STATS_OPCODE:
3526 bnx2x_drv_info_fcoe_stat(bp);
3527 break;
3528 case ISCSI_STATS_OPCODE:
3529 bnx2x_drv_info_iscsi_stat(bp);
3530 break;
3531 default:
3532 /* if op code isn't supported - send NACK */
3533 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
42f8277f 3534 goto out;
1d187b34
BW		 3535 }
3536
3537 /* if we got drv_info attn from MFW then these fields are defined in
3538 * shmem2 for sure
3539 */
3540 SHMEM2_WR(bp, drv_info_host_addr_lo,
3541 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3542 SHMEM2_WR(bp, drv_info_host_addr_hi,
3543 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3544
3545 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
42f8277f
YM		 3546
3547 /* Since possible management wants both this and get_driver_version
3548 * need to wait until management notifies us it finished utilizing
3549 * the buffer.
3550 */
3551 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3552 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3553 } else if (!bp->drv_info_mng_owner) {
3554 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3555
3556 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3557 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3558
3559 /* Management is done; need to clear indication */
3560 if (indication & bit) {
3561 SHMEM2_WR(bp, mfw_drv_indication,
3562 indication & ~bit);
3563 release = true;
3564 break;
3565 }
3566
3567 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3568 }
3569 }
3570 if (!release) {
3571 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3572 bp->drv_info_mng_owner = true;
3573 }
3574
3575out:
3576 mutex_unlock(&bp->drv_info_mutex);
3577}
3578
3579static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3580{
3581 u8 vals[4];
3582 int i = 0;
3583
3584 if (bnx2x_format) {
3585 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3586 &vals[0], &vals[1], &vals[2], &vals[3]);
3587 if (i > 0)
3588 vals[0] -= '0';
3589 } else {
3590 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3591 &vals[0], &vals[1], &vals[2], &vals[3]);
3592 }
3593
3594 while (i < 4)
3595 vals[i++] = 0;
3596
3597 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3598}
3599
3600void bnx2x_update_mng_version(struct bnx2x *bp)
3601{
3602 u32 iscsiver = DRV_VER_NOT_LOADED;
3603 u32 fcoever = DRV_VER_NOT_LOADED;
3604 u32 ethver = DRV_VER_NOT_LOADED;
3605 int idx = BP_FW_MB_IDX(bp);
3606 u8 *version;
3607
3608 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3609 return;
3610
3611 mutex_lock(&bp->drv_info_mutex);
3612 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3613 if (bp->drv_info_mng_owner)
3614 goto out;
3615
3616 if (bp->state != BNX2X_STATE_OPEN)
3617 goto out;
3618
3619 /* Parse ethernet driver version */
3620 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3621 if (!CNIC_LOADED(bp))
3622 goto out;
3623
3624 /* Try getting storage driver version via cnic */
3625 memset(&bp->slowpath->drv_info_to_mcp, 0,
3626 sizeof(union drv_info_to_mcp));
3627 bnx2x_drv_info_iscsi_stat(bp);
3628 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3629 iscsiver = bnx2x_update_mng_version_utility(version, false);
3630
3631 memset(&bp->slowpath->drv_info_to_mcp, 0,
3632 sizeof(union drv_info_to_mcp));
3633 bnx2x_drv_info_fcoe_stat(bp);
3634 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3635 fcoever = bnx2x_update_mng_version_utility(version, false);
3636
3637out:
3638 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3639 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3640 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3641
3642 mutex_unlock(&bp->drv_info_mutex);
3643
3644 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3645 ethver, iscsiver, fcoever);
1d187b34
BW		 3646}
3647
523224a3
DK		 3648static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3649{
3650 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3651
3652 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3653
3654 /*
3655 * This is the only place besides the function initialization
3656 * where the bp->flags can change so it is done without any
3657 * locks
3658 */
f2e0899f 3659 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3660 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3661 bp->flags |= MF_FUNC_DIS;
3662
3663 bnx2x_e1h_disable(bp);
3664 } else {
51c1a580 3665 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3666 bp->flags &= ~MF_FUNC_DIS;
3667
3668 bnx2x_e1h_enable(bp);
3669 }
3670 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3671 }
3672 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3673 bnx2x_config_mf_bw(bp);
523224a3
DK		 3674 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3675 }
3676
3677 /* Report results to MCP */
3678 if (dcc_event)
3679 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3680 else
3681 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3682}
3683
3684/* must be called under the spq lock */
1191cb83 3685static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3686{
3687 struct eth_spe *next_spe = bp->spq_prod_bd;
3688
3689 if (bp->spq_prod_bd == bp->spq_last_bd) {
3690 bp->spq_prod_bd = bp->spq;
3691 bp->spq_prod_idx = 0;
51c1a580 3692 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3693 } else {
3694 bp->spq_prod_bd++;
3695 bp->spq_prod_idx++;
3696 }
3697 return next_spe;
3698}
3699
3700/* must be called under the spq lock */
1191cb83 3701static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3702{
3703 int func = BP_FUNC(bp);
3704
53e51e2f
VZ		 3705 /*
3706 * Make sure that BD data is updated before writing the producer:
3707 * BD data is written to the memory, the producer is read from the
3708 * memory, thus we need a full memory barrier to ensure the ordering.
3709 */
3710 mb();
28912902 3711
523224a3 3712 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3713 bp->spq_prod_idx);
28912902
MC		 3714 mmiowb();
3715}
3716
619c5cb6
VZ		 3717/**
3718 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3719 *
3720 * @cmd: command to check
3721 * @cmd_type: command type
3722 */
1191cb83 3723static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3724{
3725 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3726 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3727 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3728 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3729 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3730 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3731 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3732 return true;
3733 else
3734 return false;
619c5cb6
VZ		 3735}
3736
619c5cb6
VZ		 3737/**
3738 * bnx2x_sp_post - place a single command on an SP ring
3739 *
3740 * @bp: driver handle
3741 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3742 * @cid: SW CID the command is related to
3743 * @data_hi: command private data address (high 32 bits)
3744 * @data_lo: command private data address (low 32 bits)
3745 * @cmd_type: command type (e.g. NONE, ETH)
3746 *
3747 * SP data is handled as if it's always an address pair, thus data fields are
3748 * not swapped to little endian in upper functions. Instead this function swaps
3749 * data as if it's two u32 fields.
3750 */
9f6c9258 3751int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3752 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3753{
28912902 3754 struct eth_spe *spe;
523224a3 3755 u16 type;
619c5cb6 3756 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3757
a2fbb9ea 3758#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3759 if (unlikely(bp->panic)) {
3760 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3761 return -EIO;
51c1a580 3762 }
a2fbb9ea
ET		 3763#endif
3764
34f80b04 3765 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3766
6e30dd4e
VZ		 3767 if (common) {
3768 if (!atomic_read(&bp->eq_spq_left)) {
3769 BNX2X_ERR("BUG! EQ ring full!\n");
3770 spin_unlock_bh(&bp->spq_lock);
3771 bnx2x_panic();
3772 return -EBUSY;
3773 }
3774 } else if (!atomic_read(&bp->cq_spq_left)) {
3775 BNX2X_ERR("BUG! SPQ ring full!\n");
3776 spin_unlock_bh(&bp->spq_lock);
3777 bnx2x_panic();
3778 return -EBUSY;
a2fbb9ea 3779 }
f1410647 3780
28912902
MC		 3781 spe = bnx2x_sp_get_next(bp);
3782
a2fbb9ea 3783 /* CID needs port number to be encoded int it */
28912902 3784 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3785 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3786 HW_CID(bp, cid));
523224a3 3787
14a94ebd
MK		 3788 /* In some cases, type may already contain the func-id
3789 * mainly in SRIOV related use cases, so we add it here only
3790 * if it's not already set.
3791 */
3792 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3793 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3794 SPE_HDR_CONN_TYPE;
3795 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3796 SPE_HDR_FUNCTION_ID);
3797 } else {
3798 type = cmd_type;
3799 }
a2fbb9ea 3800
523224a3
DK		 3801 spe->hdr.type = cpu_to_le16(type);
3802
3803 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3804 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3805
d6cae238
VZ		 3806 /*
3807 * It's ok if the actual decrement is issued towards the memory
3808 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3809 * more explicit memory barrier is needed.
d6cae238
VZ		 3810 */
3811 if (common)
3812 atomic_dec(&bp->eq_spq_left);
3813 else
3814 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3815
51c1a580
MS		 3816 DP(BNX2X_MSG_SP,
3817 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3818 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3819 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3820 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3821 HW_CID(bp, cid), data_hi, data_lo, type,
3822 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3823
28912902 3824 bnx2x_sp_prod_update(bp);
34f80b04 3825 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3826 return 0;
3827}
3828
3829/* acquire split MCP access lock register */
4a37fb66 3830static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3831{
72fd0718 3832 u32 j, val;
34f80b04 3833 int rc = 0;
a2fbb9ea
ET		 3834
3835 might_sleep();
72fd0718 3836 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3837 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3838 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3839 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3840 break;
3841
639d65b8 3842 usleep_range(5000, 10000);
a2fbb9ea 3843 }
3cdeec22 3844 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3845 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3846 rc = -EBUSY;
3847 }
3848
3849 return rc;
3850}
3851
4a37fb66
YG		 3852/* release split MCP access lock register */
3853static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3854{
3cdeec22 3855 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3856}
3857
523224a3
DK		 3858#define BNX2X_DEF_SB_ATT_IDX 0x0001
3859#define BNX2X_DEF_SB_IDX 0x0002
3860
1191cb83 3861static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3862{
523224a3 3863 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3864 u16 rc = 0;
3865
3866 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3867 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3868 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3869 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3870 }
523224a3
DK		 3871
3872 if (bp->def_idx != def_sb->sp_sb.running_index) {
3873 bp->def_idx = def_sb->sp_sb.running_index;
3874 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3875 }
523224a3 3876
16a5fd92 3877 /* Do not reorder: indices reading should complete before handling */
523224a3 3878 barrier();
a2fbb9ea
ET		 3879 return rc;
3880}
3881
3882/*
3883 * slow path service functions
3884 */
3885
3886static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3887{
34f80b04 3888 int port = BP_PORT(bp);
a2fbb9ea
ET		 3889 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3890 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3891 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3892 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3893 u32 aeu_mask;
87942b46 3894 u32 nig_mask = 0;
f2e0899f 3895 u32 reg_addr;
a2fbb9ea 3896
a2fbb9ea
ET		 3897 if (bp->attn_state & asserted)
3898 BNX2X_ERR("IGU ERROR\n");
3899
3fcaf2e5
EG		 3900 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3901 aeu_mask = REG_RD(bp, aeu_addr);
3902
a2fbb9ea 3903 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3904 aeu_mask, asserted);
72fd0718 3905 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3906 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3907
3fcaf2e5
EG		 3908 REG_WR(bp, aeu_addr, aeu_mask);
3909 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3910
3fcaf2e5 3911 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3912 bp->attn_state |= asserted;
3fcaf2e5 3913 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3914
3915 if (asserted & ATTN_HARD_WIRED_MASK) {
3916 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3917
a5e9a7cf
EG		 3918 bnx2x_acquire_phy_lock(bp);
3919
877e9aa4 3920 /* save nig interrupt mask */
87942b46 3921 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3922
361c391e
YR		 3923 /* If nig_mask is not set, no need to call the update
3924 * function.
3925 */
3926 if (nig_mask) {
3927 REG_WR(bp, nig_int_mask_addr, 0);
3928
3929 bnx2x_link_attn(bp);
3930 }
a2fbb9ea
ET		 3931
3932 /* handle unicore attn? */
3933 }
3934 if (asserted & ATTN_SW_TIMER_4_FUNC)
3935 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3936
3937 if (asserted & GPIO_2_FUNC)
3938 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3939
3940 if (asserted & GPIO_3_FUNC)
3941 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3942
3943 if (asserted & GPIO_4_FUNC)
3944 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3945
3946 if (port == 0) {
3947 if (asserted & ATTN_GENERAL_ATTN_1) {
3948 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3949 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3950 }
3951 if (asserted & ATTN_GENERAL_ATTN_2) {
3952 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3953 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3954 }
3955 if (asserted & ATTN_GENERAL_ATTN_3) {
3956 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3957 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3958 }
3959 } else {
3960 if (asserted & ATTN_GENERAL_ATTN_4) {
3961 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3962 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3963 }
3964 if (asserted & ATTN_GENERAL_ATTN_5) {
3965 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3966 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3967 }
3968 if (asserted & ATTN_GENERAL_ATTN_6) {
3969 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3970 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3971 }
3972 }
3973
3974 } /* if hardwired */
3975
f2e0899f
DK		 3976 if (bp->common.int_block == INT_BLOCK_HC)
3977 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3978 COMMAND_REG_ATTN_BITS_SET);
3979 else
3980 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3981
3982 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3983 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3984 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3985
3986 /* now set back the mask */
a5e9a7cf 3987 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 3988 /* Verify that IGU ack through BAR was written before restoring
3989 * NIG mask. This loop should exit after 2-3 iterations max.
3990 */
3991 if (bp->common.int_block != INT_BLOCK_HC) {
3992 u32 cnt = 0, igu_acked;
3993 do {
3994 igu_acked = REG_RD(bp,
3995 IGU_REG_ATTENTION_ACK_BITS);
3996 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3997 (++cnt < MAX_IGU_ATTN_ACK_TO));
3998 if (!igu_acked)
3999 DP(NETIF_MSG_HW,
4000 "Failed to verify IGU ack on time\n");
4001 barrier();
4002 }
87942b46 4003 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 4004 bnx2x_release_phy_lock(bp);
4005 }
a2fbb9ea
ET		 4006}
4007
1191cb83 4008static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 4009{
4010 int port = BP_PORT(bp);
b7737c9b 4011 u32 ext_phy_config;
fd4ef40d 4012 /* mark the failure */
b7737c9b
YR		 4013 ext_phy_config =
4014 SHMEM_RD(bp,
4015 dev_info.port_hw_config[port].external_phy_config);
4016
4017 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4018 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 4019 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 4020 ext_phy_config);
fd4ef40d
EG		 4021
4022 /* log the failure */
51c1a580
MS		 4023 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4024 "Please contact OEM Support for assistance\n");
8304859a 4025
16a5fd92 4026 /* Schedule device reset (unload)
8304859a
AE		 4027 * This is due to some boards consuming sufficient power when driver is
4028 * up to overheat if fan fails.
4029 */
230bb0f3 4030 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
fd4ef40d 4031}
ab6ad5a4 4032
1191cb83 4033static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 4034{
34f80b04 4035 int port = BP_PORT(bp);
877e9aa4 4036 int reg_offset;
d90d96ba 4037 u32 val;
877e9aa4 4038
34f80b04
EG		 4039 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4040 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 4041
34f80b04 4042 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 4043
4044 val = REG_RD(bp, reg_offset);
4045 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4046 REG_WR(bp, reg_offset, val);
4047
4048 BNX2X_ERR("SPIO5 hw attention\n");
4049
fd4ef40d 4050 /* Fan failure attention */
d90d96ba 4051 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 4052 bnx2x_fan_failure(bp);
877e9aa4 4053 }
34f80b04 4054
3deb8167 4055 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 4056 bnx2x_acquire_phy_lock(bp);
4057 bnx2x_handle_module_detect_int(&bp->link_params);
4058 bnx2x_release_phy_lock(bp);
4059 }
4060
34f80b04
EG		 4061 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4062
4063 val = REG_RD(bp, reg_offset);
4064 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4065 REG_WR(bp, reg_offset, val);
4066
4067 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 4068 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 4069 bnx2x_panic();
4070 }
877e9aa4
ET		 4071}
4072
1191cb83 4073static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4074{
4075 u32 val;
4076
0626b899 4077 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 4078
4079 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4080 BNX2X_ERR("DB hw attention 0x%x\n", val);
4081 /* DORQ discard attention */
4082 if (val & 0x2)
4083 BNX2X_ERR("FATAL error from DORQ\n");
4084 }
34f80b04
EG		 4085
4086 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4087
4088 int port = BP_PORT(bp);
4089 int reg_offset;
4090
4091 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4092 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4093
4094 val = REG_RD(bp, reg_offset);
4095 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4096 REG_WR(bp, reg_offset, val);
4097
4098 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 4099 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 4100 bnx2x_panic();
4101 }
877e9aa4
ET		 4102}
4103
1191cb83 4104static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4105{
4106 u32 val;
4107
4108 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4109
4110 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4111 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4112 /* CFC error attention */
4113 if (val & 0x2)
4114 BNX2X_ERR("FATAL error from CFC\n");
4115 }
4116
4117 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 4118 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4119 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4120 /* RQ_USDMDP_FIFO_OVERFLOW */
4121 if (val & 0x18000)
4122 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4123
4124 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4125 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4126 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4127 }
877e9aa4 4128 }
34f80b04
EG		 4129
4130 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4131
4132 int port = BP_PORT(bp);
4133 int reg_offset;
4134
4135 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4136 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4137
4138 val = REG_RD(bp, reg_offset);
4139 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4140 REG_WR(bp, reg_offset, val);
4141
4142 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 4143 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 4144 bnx2x_panic();
4145 }
877e9aa4
ET		 4146}
4147
1191cb83 4148static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4149{
34f80b04
EG		 4150 u32 val;
4151
877e9aa4
ET		 4152 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4153
34f80b04
EG		 4154 if (attn & BNX2X_PMF_LINK_ASSERT) {
4155 int func = BP_FUNC(bp);
4156
4157 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4158 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4159 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4160 func_mf_config[BP_ABS_FUNC(bp)].config);
4161 val = SHMEM_RD(bp,
4162 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 4163 if (val & DRV_STATUS_DCC_EVENT_MASK)
4164 bnx2x_dcc_event(bp,
4165 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 4166
4167 if (val & DRV_STATUS_SET_MF_BW)
4168 bnx2x_set_mf_bw(bp);
4169
1d187b34
BW		 4170 if (val & DRV_STATUS_DRV_INFO_REQ)
4171 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4172
4173 if (val & DRV_STATUS_VF_DISABLED)
370d4a26
YM		 4174 bnx2x_schedule_iov_task(bp,
4175 BNX2X_IOV_HANDLE_FLR);
d16132ce 4176
2691d51d 4177 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4178 bnx2x_pmf_update(bp);
4179
e4901dde 4180 if (bp->port.pmf &&
785b9b1a
SR		 4181 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4182 bp->dcbx_enabled > 0)
e4901dde
VZ		 4183 /* start dcbx state machine */
4184 bnx2x_dcbx_set_params(bp,
4185 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4186 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4187 bnx2x_handle_afex_cmd(bp,
4188 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4189 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4190 bnx2x_handle_eee_event(bp);
3deb8167
YR		 4191 if (bp->link_vars.periodic_flags &
4192 PERIODIC_FLAGS_LINK_EVENT) {
4193 /* sync with link */
4194 bnx2x_acquire_phy_lock(bp);
4195 bp->link_vars.periodic_flags &=
4196 ~PERIODIC_FLAGS_LINK_EVENT;
4197 bnx2x_release_phy_lock(bp);
4198 if (IS_MF(bp))
4199 bnx2x_link_sync_notify(bp);
4200 bnx2x_link_report(bp);
4201 }
4202 /* Always call it here: bnx2x_link_report() will
4203 * prevent the link indication duplication.
4204 */
4205 bnx2x__link_status_update(bp);
34f80b04 4206 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4207
4208 BNX2X_ERR("MC assert!\n");
d6cae238 4209 bnx2x_mc_assert(bp);
877e9aa4
ET		 4210 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4211 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4212 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4213 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4214 bnx2x_panic();
4215
4216 } else if (attn & BNX2X_MCP_ASSERT) {
4217
4218 BNX2X_ERR("MCP assert!\n");
4219 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4220 bnx2x_fw_dump(bp);
877e9aa4
ET		 4221
4222 } else
4223 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4224 }
4225
4226 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4227 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4228 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4229 val = CHIP_IS_E1(bp) ? 0 :
4230 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4231 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4232 }
4233 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4234 val = CHIP_IS_E1(bp) ? 0 :
4235 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4236 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4237 }
877e9aa4 4238 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4239 }
4240}
4241
c9ee9206
VZ		 4242/*
4243 * Bits map:
4244 * 0-7 - Engine0 load counter.
4245 * 8-15 - Engine1 load counter.
4246 * 16 - Engine0 RESET_IN_PROGRESS bit.
4247 * 17 - Engine1 RESET_IN_PROGRESS bit.
4248 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4249 * on the engine
4250 * 19 - Engine1 ONE_IS_LOADED.
4251 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4252 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4253 * just the one belonging to its engine).
4254 *
4255 */
4256#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4257
4258#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4259#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4260#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4261#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4262#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4263#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4264#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4265
4266/*
4267 * Set the GLOBAL_RESET bit.
4268 *
4269 * Should be run under rtnl lock
4270 */
4271void bnx2x_set_reset_global(struct bnx2x *bp)
4272{
f16da43b
AE		 4273 u32 val;
4274 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4275 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4276 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4277 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4278}
4279
4280/*
4281 * Clear the GLOBAL_RESET bit.
4282 *
4283 * Should be run under rtnl lock
4284 */
1191cb83 4285static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4286{
f16da43b
AE		 4287 u32 val;
4288 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4289 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4290 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4291 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4292}
f85582f8 4293
72fd0718 4294/*
c9ee9206
VZ		 4295 * Checks the GLOBAL_RESET bit.
4296 *
72fd0718
VZ		 4297 * should be run under rtnl lock
4298 */
1191cb83 4299static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4300{
3cdeec22 4301 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4302
4303 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4304 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4305}
4306
4307/*
4308 * Clear RESET_IN_PROGRESS bit for the current engine.
4309 *
4310 * Should be run under rtnl lock
4311 */
1191cb83 4312static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4313{
f16da43b 4314 u32 val;
c9ee9206
VZ		 4315 u32 bit = BP_PATH(bp) ?
4316 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4317 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4318 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4319
4320 /* Clear the bit */
4321 val &= ~bit;
4322 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4323
4324 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4325}
4326
4327/*
c9ee9206
VZ		 4328 * Set RESET_IN_PROGRESS for the current engine.
4329 *
72fd0718
VZ		 4330 * should be run under rtnl lock
4331 */
c9ee9206 4332void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4333{
f16da43b 4334 u32 val;
c9ee9206
VZ		 4335 u32 bit = BP_PATH(bp) ?
4336 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4337 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4338 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4339
4340 /* Set the bit */
4341 val |= bit;
4342 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4343 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4344}
4345
4346/*
c9ee9206 4347 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4348 * should be run under rtnl lock
4349 */
c9ee9206 4350bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4351{
3cdeec22 4352 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4353 u32 bit = engine ?
4354 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4355
4356 /* return false if bit is set */
4357 return (val & bit) ? false : true;
72fd0718
VZ		 4358}
4359
4360/*
889b9af3 4361 * set pf load for the current pf.
c9ee9206 4362 *
72fd0718
VZ		 4363 * should be run under rtnl lock
4364 */
889b9af3 4365void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4366{
f16da43b 4367 u32 val1, val;
c9ee9206
VZ		 4368 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4369 BNX2X_PATH0_LOAD_CNT_MASK;
4370 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4371 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4372
f16da43b
AE		 4373 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4374 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4375
51c1a580 4376 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4377
c9ee9206
VZ		 4378 /* get the current counter value */
4379 val1 = (val & mask) >> shift;
4380
889b9af3
AE		 4381 /* set bit of that PF */
4382 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4383
4384 /* clear the old value */
4385 val &= ~mask;
4386
4387 /* set the new one */
4388 val |= ((val1 << shift) & mask);
4389
4390 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4391 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4392}
4393
c9ee9206 4394/**
889b9af3 4395 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4396 *
4397 * @bp: driver handle
4398 *
4399 * Should be run under rtnl lock.
4400 * Decrements the load counter for the current engine. Returns
889b9af3 4401 * whether other functions are still loaded
72fd0718 4402 */
889b9af3 4403bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4404{
f16da43b 4405 u32 val1, val;
c9ee9206
VZ		 4406 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4407 BNX2X_PATH0_LOAD_CNT_MASK;
4408 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4409 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4410
f16da43b
AE		 4411 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4412 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4413 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4414
c9ee9206
VZ		 4415 /* get the current counter value */
4416 val1 = (val & mask) >> shift;
4417
889b9af3
AE		 4418 /* clear bit of that PF */
4419 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4420
4421 /* clear the old value */
4422 val &= ~mask;
4423
4424 /* set the new one */
4425 val |= ((val1 << shift) & mask);
4426
4427 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4428 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4429 return val1 != 0;
72fd0718
VZ		 4430}
4431
4432/*
889b9af3 4433 * Read the load status for the current engine.
c9ee9206 4434 *
72fd0718
VZ		 4435 * should be run under rtnl lock
4436 */
1191cb83 4437static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4438{
c9ee9206
VZ		 4439 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4440 BNX2X_PATH0_LOAD_CNT_MASK);
4441 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4442 BNX2X_PATH0_LOAD_CNT_SHIFT);
4443 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4444
51c1a580 4445 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4446
4447 val = (val & mask) >> shift;
4448
51c1a580
MS		 4449 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4450 engine, val);
c9ee9206 4451
889b9af3 4452 return val != 0;
72fd0718
VZ		 4453}
4454
6bf07b8e
YM		 4455static void _print_parity(struct bnx2x *bp, u32 reg)
4456{
4457 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4458}
4459
1191cb83 4460static void _print_next_block(int idx, const char *blk)
72fd0718 4461{
f1deab50 4462 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4463}
4464
4293b9f5
DK		 4465static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4466 int *par_num, bool print)
72fd0718 4467{
4293b9f5
DK		 4468 u32 cur_bit;
4469 bool res;
4470 int i;
4471
4472 res = false;
4473
72fd0718 4474 for (i = 0; sig; i++) {
4293b9f5 4475 cur_bit = (0x1UL << i);
72fd0718 4476 if (sig & cur_bit) {
4293b9f5
DK		 4477 res |= true; /* Each bit is real error! */
4478
4479 if (print) {
4480 switch (cur_bit) {
4481 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4482 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4483 _print_parity(bp,
4484 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4485 break;
4486 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4487 _print_next_block((*par_num)++,
4488 "PARSER");
6bf07b8e 4489 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4490 break;
4491 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4492 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4493 _print_parity(bp,
4494 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4495 break;
4496 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4497 _print_next_block((*par_num)++,
c9ee9206 4498 "SEARCHER");
6bf07b8e 4499 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4500 break;
4501 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4502 _print_next_block((*par_num)++, "TCM");
4503 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4504 break;
4505 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4506 _print_next_block((*par_num)++,
4507 "TSEMI");
6bf07b8e
YM		 4508 _print_parity(bp,
4509 TSEM_REG_TSEM_PRTY_STS_0);
4510 _print_parity(bp,
4511 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4512 break;
4513 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4514 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4515 _print_parity(bp, GRCBASE_XPB +
4516 PB_REG_PB_PRTY_STS);
4293b9f5 4517 break;
6bf07b8e 4518 }
72fd0718
VZ		 4519 }
4520
4521 /* Clear the bit */
4522 sig &= ~cur_bit;
4523 }
4524 }
4525
4293b9f5 4526 return res;
72fd0718
VZ		 4527}
4528
4293b9f5
DK		 4529static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4530 int *par_num, bool *global,
6bf07b8e 4531 bool print)
72fd0718 4532{
4293b9f5
DK		 4533 u32 cur_bit;
4534 bool res;
4535 int i;
4536
4537 res = false;
4538
72fd0718 4539 for (i = 0; sig; i++) {
4293b9f5 4540 cur_bit = (0x1UL << i);
72fd0718 4541 if (sig & cur_bit) {
4293b9f5 4542 res |= true; /* Each bit is real error! */
72fd0718 4543 switch (cur_bit) {
c9ee9206 4544 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4545 if (print) {
4293b9f5 4546 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4547 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4548 }
72fd0718
VZ		 4549 break;
4550 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4551 if (print) {
4293b9f5 4552 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4553 _print_parity(bp, QM_REG_QM_PRTY_STS);
4554 }
c9ee9206
VZ		 4555 break;
4556 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4557 if (print) {
4293b9f5 4558 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4559 _print_parity(bp, TM_REG_TM_PRTY_STS);
4560 }
72fd0718
VZ		 4561 break;
4562 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4563 if (print) {
4293b9f5 4564 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4565 _print_parity(bp,
4566 XSDM_REG_XSDM_PRTY_STS);
4567 }
c9ee9206
VZ		 4568 break;
4569 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4570 if (print) {
4293b9f5 4571 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4572 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4573 }
72fd0718
VZ		 4574 break;
4575 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4576 if (print) {
4293b9f5
DK		 4577 _print_next_block((*par_num)++,
4578 "XSEMI");
6bf07b8e
YM		 4579 _print_parity(bp,
4580 XSEM_REG_XSEM_PRTY_STS_0);
4581 _print_parity(bp,
4582 XSEM_REG_XSEM_PRTY_STS_1);
4583 }
72fd0718
VZ		 4584 break;
4585 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4586 if (print) {
4293b9f5 4587 _print_next_block((*par_num)++,
c9ee9206 4588 "DOORBELLQ");
6bf07b8e
YM		 4589 _print_parity(bp,
4590 DORQ_REG_DORQ_PRTY_STS);
4591 }
c9ee9206
VZ		 4592 break;
4593 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4594 if (print) {
4293b9f5 4595 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4596 if (CHIP_IS_E1x(bp)) {
4597 _print_parity(bp,
4598 NIG_REG_NIG_PRTY_STS);
4599 } else {
4600 _print_parity(bp,
4601 NIG_REG_NIG_PRTY_STS_0);
4602 _print_parity(bp,
4603 NIG_REG_NIG_PRTY_STS_1);
4604 }
4605 }
72fd0718
VZ		 4606 break;
4607 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4608 if (print)
4293b9f5 4609 _print_next_block((*par_num)++,
c9ee9206
VZ		 4610 "VAUX PCI CORE");
4611 *global = true;
72fd0718
VZ		 4612 break;
4613 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4614 if (print) {
4293b9f5
DK		 4615 _print_next_block((*par_num)++,
4616 "DEBUG");
6bf07b8e
YM		 4617 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4618 }
72fd0718
VZ		 4619 break;
4620 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4621 if (print) {
4293b9f5 4622 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4623 _print_parity(bp,
4624 USDM_REG_USDM_PRTY_STS);
4625 }
72fd0718 4626 break;
8736c826 4627 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4628 if (print) {
4293b9f5 4629 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4630 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4631 }
8736c826 4632 break;
72fd0718 4633 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4634 if (print) {
4293b9f5
DK		 4635 _print_next_block((*par_num)++,
4636 "USEMI");
6bf07b8e
YM		 4637 _print_parity(bp,
4638 USEM_REG_USEM_PRTY_STS_0);
4639 _print_parity(bp,
4640 USEM_REG_USEM_PRTY_STS_1);
4641 }
72fd0718
VZ		 4642 break;
4643 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4644 if (print) {
4293b9f5 4645 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4646 _print_parity(bp, GRCBASE_UPB +
4647 PB_REG_PB_PRTY_STS);
4648 }
72fd0718
VZ		 4649 break;
4650 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4651 if (print) {
4293b9f5 4652 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4653 _print_parity(bp,
4654 CSDM_REG_CSDM_PRTY_STS);
4655 }
72fd0718 4656 break;
8736c826 4657 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4658 if (print) {
4293b9f5 4659 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4660 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4661 }
8736c826 4662 break;
72fd0718
VZ		 4663 }
4664
4665 /* Clear the bit */
4666 sig &= ~cur_bit;
4667 }
4668 }
4669
4293b9f5 4670 return res;
72fd0718
VZ		 4671}
4672
4293b9f5
DK		 4673static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4674 int *par_num, bool print)
72fd0718 4675{
4293b9f5
DK		 4676 u32 cur_bit;
4677 bool res;
4678 int i;
4679
4680 res = false;
4681
72fd0718 4682 for (i = 0; sig; i++) {
4293b9f5 4683 cur_bit = (0x1UL << i);
72fd0718 4684 if (sig & cur_bit) {
4293b9f5
DK		 4685 res |= true; /* Each bit is real error! */
4686 if (print) {
4687 switch (cur_bit) {
4688 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4689 _print_next_block((*par_num)++,
4690 "CSEMI");
6bf07b8e
YM		 4691 _print_parity(bp,
4692 CSEM_REG_CSEM_PRTY_STS_0);
4693 _print_parity(bp,
4694 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4695 break;
4696 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4697 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4698 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4699 _print_parity(bp,
4700 PXP2_REG_PXP2_PRTY_STS_0);
4701 _print_parity(bp,
4702 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4703 break;
4704 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4705 _print_next_block((*par_num)++,
4706 "PXPPCICLOCKCLIENT");
4707 break;
4708 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4709 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4710 _print_parity(bp,
4711 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4712 break;
4713 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4714 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4715 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4716 break;
4717 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4718 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4719 _print_parity(bp,
4720 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4721 break;
4722 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4723 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4724 if (CHIP_IS_E1x(bp))
4725 _print_parity(bp,
4726 HC_REG_HC_PRTY_STS);
4727 else
4728 _print_parity(bp,
4729 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4730 break;
4731 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4732 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4733 _print_parity(bp,
4734 MISC_REG_MISC_PRTY_STS);
4293b9f5 4735 break;
6bf07b8e 4736 }
72fd0718
VZ		 4737 }
4738
4739 /* Clear the bit */
4740 sig &= ~cur_bit;
4741 }
4742 }
4743
4293b9f5 4744 return res;
72fd0718
VZ		 4745}
4746
4293b9f5
DK		 4747static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4748 int *par_num, bool *global,
4749 bool print)
72fd0718 4750{
4293b9f5
DK		 4751 bool res = false;
4752 u32 cur_bit;
4753 int i;
4754
72fd0718 4755 for (i = 0; sig; i++) {
4293b9f5 4756 cur_bit = (0x1UL << i);
72fd0718
VZ		 4757 if (sig & cur_bit) {
4758 switch (cur_bit) {
4759 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4760 if (print)
4293b9f5
DK		 4761 _print_next_block((*par_num)++,
4762 "MCP ROM");
c9ee9206 4763 *global = true;
4293b9f5 4764 res |= true;
72fd0718
VZ		 4765 break;
4766 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4767 if (print)
4293b9f5 4768 _print_next_block((*par_num)++,
c9ee9206
VZ		 4769 "MCP UMP RX");
4770 *global = true;
4293b9f5 4771 res |= true;
72fd0718
VZ		 4772 break;
4773 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4774 if (print)
4293b9f5 4775 _print_next_block((*par_num)++,
c9ee9206
VZ		 4776 "MCP UMP TX");
4777 *global = true;
4293b9f5 4778 res |= true;
72fd0718
VZ		 4779 break;
4780 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206 4781 if (print)
4293b9f5 4782 _print_next_block((*par_num)++,
c9ee9206 4783 "MCP SCPAD");
4293b9f5
DK		 4784 /* clear latched SCPAD PATIRY from MCP */
4785 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4786 1UL << 10);
72fd0718
VZ		 4787 break;
4788 }
4789
4790 /* Clear the bit */
4791 sig &= ~cur_bit;
4792 }
4793 }
4794
4293b9f5 4795 return res;
72fd0718
VZ		 4796}
4797
4293b9f5
DK		 4798static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4799 int *par_num, bool print)
8736c826 4800{
4293b9f5
DK		 4801 u32 cur_bit;
4802 bool res;
4803 int i;
4804
4805 res = false;
4806
8736c826 4807 for (i = 0; sig; i++) {
4293b9f5 4808 cur_bit = (0x1UL << i);
8736c826 4809 if (sig & cur_bit) {
4293b9f5
DK		 4810 res |= true; /* Each bit is real error! */
4811 if (print) {
4812 switch (cur_bit) {
4813 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4814 _print_next_block((*par_num)++,
4815 "PGLUE_B");
6bf07b8e 4816 _print_parity(bp,
4293b9f5
DK		 4817 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4818 break;
4819 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4820 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4821 _print_parity(bp,
4822 ATC_REG_ATC_PRTY_STS);
4293b9f5 4823 break;
6bf07b8e 4824 }
8736c826 4825 }
8736c826
VZ		 4826 /* Clear the bit */
4827 sig &= ~cur_bit;
4828 }
4829 }
4830
4293b9f5 4831 return res;
8736c826
VZ		 4832}
4833
1191cb83
ED		 4834static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4835 u32 *sig)
72fd0718 4836{
4293b9f5
DK		 4837 bool res = false;
4838
8736c826
VZ		 4839 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4840 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4841 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4842 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4843 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4844 int par_num = 0;
51c1a580
MS		 4845 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4846 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4847 sig[0] & HW_PRTY_ASSERT_SET_0,
4848 sig[1] & HW_PRTY_ASSERT_SET_1,
4849 sig[2] & HW_PRTY_ASSERT_SET_2,
4850 sig[3] & HW_PRTY_ASSERT_SET_3,
4851 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4852 if (print)
4853 netdev_err(bp->dev,
4854 "Parity errors detected in blocks: ");
4293b9f5
DK		 4855 res |= bnx2x_check_blocks_with_parity0(bp,
4856 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4857 res |= bnx2x_check_blocks_with_parity1(bp,
4858 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4859 res |= bnx2x_check_blocks_with_parity2(bp,
4860 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4861 res |= bnx2x_check_blocks_with_parity3(bp,
4862 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4863 res |= bnx2x_check_blocks_with_parity4(bp,
4864 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4865
c9ee9206
VZ		 4866 if (print)
4867 pr_cont("\n");
4293b9f5 4868 }
8736c826 4869
4293b9f5 4870 return res;
72fd0718
VZ		 4871}
4872
c9ee9206
VZ		 4873/**
4874 * bnx2x_chk_parity_attn - checks for parity attentions.
4875 *
4876 * @bp: driver handle
4877 * @global: true if there was a global attention
4878 * @print: show parity attention in syslog
4879 */
4880bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4881{
8736c826 4882 struct attn_route attn = { {0} };
72fd0718
VZ		 4883 int port = BP_PORT(bp);
4884
4885 attn.sig[0] = REG_RD(bp,
4886 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4887 port*4);
4888 attn.sig[1] = REG_RD(bp,
4889 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4890 port*4);
4891 attn.sig[2] = REG_RD(bp,
4892 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4893 port*4);
4894 attn.sig[3] = REG_RD(bp,
4895 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4896 port*4);
0a5ccb75
YM		 4897 /* Since MCP attentions can't be disabled inside the block, we need to
4898 * read AEU registers to see whether they're currently disabled
4899 */
4900 attn.sig[3] &= ((REG_RD(bp,
4901 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4902 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4903 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4904 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 4905
8736c826
VZ		 4906 if (!CHIP_IS_E1x(bp))
4907 attn.sig[4] = REG_RD(bp,
4908 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4909 port*4);
4910
4911 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4912}
4913
1191cb83 4914static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 4915{
4916 u32 val;
4917 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4918
4919 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4920 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4921 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 4922 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 4923 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 4924 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 4925 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 4926 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 4927 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 4928 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 4929 if (val &
4930 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 4931 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 4932 if (val &
4933 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 4934 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 4935 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 4936 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 4937 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 4938 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 4939 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 4940 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 4941 }
4942 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4943 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4944 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4945 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4946 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4947 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 4948 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 4949 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 4950 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 4951 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 4952 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 4953 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4954 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4955 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 4956 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 4957 }
4958
4959 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4960 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4961 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4962 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4963 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4964 }
f2e0899f
DK		 4965}
4966
72fd0718
VZ		 4967static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4968{
4969 struct attn_route attn, *group_mask;
34f80b04 4970 int port = BP_PORT(bp);
877e9aa4 4971 int index;
a2fbb9ea
ET		 4972 u32 reg_addr;
4973 u32 val;
3fcaf2e5 4974 u32 aeu_mask;
c9ee9206 4975 bool global = false;
a2fbb9ea
ET		 4976
4977 /* need to take HW lock because MCP or other port might also
4978 try to handle this event */
4a37fb66 4979 bnx2x_acquire_alr(bp);
a2fbb9ea 4980
c9ee9206
VZ		 4981 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4982#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4983 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4984 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4985 /* Disable HW interrupts */
4986 bnx2x_int_disable(bp);
72fd0718
VZ		 4987 /* In case of parity errors don't handle attentions so that
4988 * other function would "see" parity errors.
4989 */
c9ee9206
VZ		 4990#else
4991 bnx2x_panic();
4992#endif
4993 bnx2x_release_alr(bp);
72fd0718
VZ		 4994 return;
4995 }
4996
a2fbb9ea
ET		 4997 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4998 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4999 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5000 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 5001 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5002 attn.sig[4] =
5003 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5004 else
5005 attn.sig[4] = 0;
5006
5007 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5008 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 5009
5010 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5011 if (deasserted & (1 << index)) {
72fd0718 5012 group_mask = &bp->attn_group[index];
a2fbb9ea 5013
51c1a580 5014 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 5015 index,
5016 group_mask->sig[0], group_mask->sig[1],
5017 group_mask->sig[2], group_mask->sig[3],
5018 group_mask->sig[4]);
a2fbb9ea 5019
f2e0899f
DK		 5020 bnx2x_attn_int_deasserted4(bp,
5021 attn.sig[4] & group_mask->sig[4]);
877e9aa4 5022 bnx2x_attn_int_deasserted3(bp,
72fd0718 5023 attn.sig[3] & group_mask->sig[3]);
877e9aa4 5024 bnx2x_attn_int_deasserted1(bp,
72fd0718 5025 attn.sig[1] & group_mask->sig[1]);
877e9aa4 5026 bnx2x_attn_int_deasserted2(bp,
72fd0718 5027 attn.sig[2] & group_mask->sig[2]);
877e9aa4 5028 bnx2x_attn_int_deasserted0(bp,
72fd0718 5029 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 5030 }
5031 }
5032
4a37fb66 5033 bnx2x_release_alr(bp);
a2fbb9ea 5034
f2e0899f
DK		 5035 if (bp->common.int_block == INT_BLOCK_HC)
5036 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5037 COMMAND_REG_ATTN_BITS_CLR);
5038 else
5039 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 5040
5041 val = ~deasserted;
f2e0899f
DK		 5042 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5043 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 5044 REG_WR(bp, reg_addr, val);
a2fbb9ea 5045
a2fbb9ea 5046 if (~bp->attn_state & deasserted)
3fcaf2e5 5047 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 5048
5049 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5050 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5051
3fcaf2e5
EG		 5052 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5053 aeu_mask = REG_RD(bp, reg_addr);
5054
5055 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5056 aeu_mask, deasserted);
72fd0718 5057 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 5058 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 5059
3fcaf2e5
EG		 5060 REG_WR(bp, reg_addr, aeu_mask);
5061 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 5062
5063 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5064 bp->attn_state &= ~deasserted;
5065 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5066}
5067
5068static void bnx2x_attn_int(struct bnx2x *bp)
5069{
5070 /* read local copy of bits */
68d59484
EG		 5071 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5072 attn_bits);
5073 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5074 attn_bits_ack);
a2fbb9ea
ET		 5075 u32 attn_state = bp->attn_state;
5076
5077 /* look for changed bits */
5078 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5079 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5080
5081 DP(NETIF_MSG_HW,
5082 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5083 attn_bits, attn_ack, asserted, deasserted);
5084
5085 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 5086 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 5087
5088 /* handle bits that were raised */
5089 if (asserted)
5090 bnx2x_attn_int_asserted(bp, asserted);
5091
5092 if (deasserted)
5093 bnx2x_attn_int_deasserted(bp, deasserted);
5094}
5095
619c5cb6
VZ		 5096void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5097 u16 index, u8 op, u8 update)
5098{
dc1ba591
AE		 5099 u32 igu_addr = bp->igu_base_addr;
5100 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 5101 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5102 igu_addr);
5103}
5104
1191cb83 5105static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 5106{
5107 /* No memory barriers */
5108 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5109 mmiowb(); /* keep prod updates ordered */
5110}
5111
523224a3
DK		 5112static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5113 union event_ring_elem *elem)
5114{
619c5cb6
VZ		 5115 u8 err = elem->message.error;
5116
523224a3 5117 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 5118 (cid < bp->cnic_eth_dev.starting_cid &&
5119 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5120 return 1;
5121
5122 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5123
619c5cb6
VZ		 5124 if (unlikely(err)) {
5125
523224a3
DK		 5126 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5127 cid);
823e1d90 5128 bnx2x_panic_dump(bp, false);
523224a3 5129 }
619c5cb6 5130 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5131 return 0;
5132}
523224a3 5133
1191cb83 5134static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5135{
5136 struct bnx2x_mcast_ramrod_params rparam;
5137 int rc;
5138
5139 memset(&rparam, 0, sizeof(rparam));
5140
5141 rparam.mcast_obj = &bp->mcast_obj;
5142
5143 netif_addr_lock_bh(bp->dev);
5144
5145 /* Clear pending state for the last command */
5146 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5147
5148 /* If there are pending mcast commands - send them */
5149 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5150 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5151 if (rc < 0)
5152 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5153 rc);
5154 }
5155
5156 netif_addr_unlock_bh(bp->dev);
5157}
5158
1191cb83
ED		 5159static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5160 union event_ring_elem *elem)
619c5cb6
VZ		 5161{
5162 unsigned long ramrod_flags = 0;
5163 int rc = 0;
5164 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5165 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5166
5167 /* Always push next commands out, don't wait here */
5168 __set_bit(RAMROD_CONT, &ramrod_flags);
5169
86564c3f
YM		 5170 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5171 >> BNX2X_SWCID_SHIFT) {
619c5cb6 5172 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5173 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5174 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5175 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5176 else
15192a8c 5177 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6
VZ		 5178
5179 break;
619c5cb6 5180 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5181 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5182 /* This is only relevant for 57710 where multicast MACs are
5183 * configured as unicast MACs using the same ramrod.
5184 */
5185 bnx2x_handle_mcast_eqe(bp);
5186 return;
5187 default:
5188 BNX2X_ERR("Unsupported classification command: %d\n",
5189 elem->message.data.eth_event.echo);
5190 return;
5191 }
5192
5193 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5194
5195 if (rc < 0)
5196 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5197 else if (rc > 0)
5198 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5199}
5200
619c5cb6 5201static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5202
1191cb83 5203static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5204{
5205 netif_addr_lock_bh(bp->dev);
5206
5207 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5208
5209 /* Send rx_mode command again if was requested */
5210 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5211 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5212 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5213 &bp->sp_state))
5214 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5215 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5216 &bp->sp_state))
5217 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5218
5219 netif_addr_unlock_bh(bp->dev);
5220}
5221
1191cb83 5222static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5223 union event_ring_elem *elem)
5224{
5225 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5226 DP(BNX2X_MSG_SP,
5227 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5228 elem->message.data.vif_list_event.func_bit_map);
5229 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5230 elem->message.data.vif_list_event.func_bit_map);
5231 } else if (elem->message.data.vif_list_event.echo ==
5232 VIF_LIST_RULE_SET) {
5233 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5234 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5235 }
5236}
5237
5238/* called with rtnl_lock */
1191cb83 5239static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5240{
5241 int q, rc;
5242 struct bnx2x_fastpath *fp;
5243 struct bnx2x_queue_state_params queue_params = {NULL};
5244 struct bnx2x_queue_update_params *q_update_params =
5245 &queue_params.params.update;
5246
2de67439 5247 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5248 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5249
5250 /* set silent vlan removal values according to vlan mode */
5251 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5252 &q_update_params->update_flags);
5253 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5254 &q_update_params->update_flags);
5255 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5256
5257 /* in access mode mark mask and value are 0 to strip all vlans */
5258 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5259 q_update_params->silent_removal_value = 0;
5260 q_update_params->silent_removal_mask = 0;
5261 } else {
5262 q_update_params->silent_removal_value =
5263 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5264 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5265 }
5266
5267 for_each_eth_queue(bp, q) {
5268 /* Set the appropriate Queue object */
5269 fp = &bp->fp[q];
15192a8c 5270 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5271
5272 /* send the ramrod */
5273 rc = bnx2x_queue_state_change(bp, &queue_params);
5274 if (rc < 0)
5275 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5276 q);
5277 }
5278
fea75645 5279 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5280 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5281 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5282
5283 /* clear pending completion bit */
5284 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5285
5286 /* mark latest Q bit */
4e857c58 5287 smp_mb__before_atomic();
a3348722 5288 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 5289 smp_mb__after_atomic();
a3348722
BW		 5290
5291 /* send Q update ramrod for FCoE Q */
5292 rc = bnx2x_queue_state_change(bp, &queue_params);
5293 if (rc < 0)
5294 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5295 q);
5296 } else {
5297 /* If no FCoE ring - ACK MCP now */
5298 bnx2x_link_report(bp);
5299 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5300 }
a3348722
BW		 5301}
5302
1191cb83 5303static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5304 struct bnx2x *bp, u32 cid)
5305{
94f05b0f 5306 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5307
5308 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5309 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5310 else
15192a8c 5311 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5312}
5313
523224a3
DK		 5314static void bnx2x_eq_int(struct bnx2x *bp)
5315{
5316 u16 hw_cons, sw_cons, sw_prod;
5317 union event_ring_elem *elem;
55c11941 5318 u8 echo;
523224a3
DK		 5319 u32 cid;
5320 u8 opcode;
fd1fc79d 5321 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5322 struct bnx2x_queue_sp_obj *q_obj;
5323 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5324 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5325
5326 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5327
5328 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5329 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5330 * condition below will be met. The next element is the size of a
5331 * regular element and hence incrementing by 1
5332 */
5333 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5334 hw_cons++;
5335
25985edc 5336 /* This function may never run in parallel with itself for a
523224a3
DK		 5337 * specific bp, thus there is no need in "paired" read memory
5338 * barrier here.
5339 */
5340 sw_cons = bp->eq_cons;
5341 sw_prod = bp->eq_prod;
5342
d6cae238 5343 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5344 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5345
5346 for (; sw_cons != hw_cons;
5347 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5348
523224a3
DK		 5349 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5350
fd1fc79d
AE		 5351 rc = bnx2x_iov_eq_sp_event(bp, elem);
5352 if (!rc) {
5353 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5354 rc);
5355 goto next_spqe;
5356 }
523224a3 5357
86564c3f
YM		 5358 /* elem CID originates from FW; actually LE */
5359 cid = SW_CID((__force __le32)
5360 elem->message.data.cfc_del_event.cid);
5361 opcode = elem->message.opcode;
523224a3
DK		 5362
5363 /* handle eq element */
5364 switch (opcode) {
fd1fc79d 5365 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
370d4a26
YM		 5366 bnx2x_vf_mbx_schedule(bp,
5367 &elem->message.data.vf_pf_event);
fd1fc79d
AE		 5368 continue;
5369
523224a3 5370 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5371 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5372 "got statistics comp event %d\n",
5373 bp->stats_comp++);
523224a3 5374 /* nothing to do with stats comp */
d6cae238 5375 goto next_spqe;
523224a3
DK		 5376
5377 case EVENT_RING_OPCODE_CFC_DEL:
5378 /* handle according to cid range */
5379 /*
5380 * we may want to verify here that the bp state is
5381 * HALTING
5382 */
d6cae238 5383 DP(BNX2X_MSG_SP,
523224a3 5384 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5385
5386 if (CNIC_LOADED(bp) &&
5387 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5388 goto next_spqe;
55c11941 5389
619c5cb6
VZ		 5390 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5391
5392 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5393 break;
5394
523224a3 5395 goto next_spqe;
e4901dde
VZ		 5396
5397 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5398 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5399 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5400 if (f_obj->complete_cmd(bp, f_obj,
5401 BNX2X_F_CMD_TX_STOP))
5402 break;
e4901dde 5403 goto next_spqe;
619c5cb6 5404
e4901dde 5405 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5406 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5407 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5408 if (f_obj->complete_cmd(bp, f_obj,
5409 BNX2X_F_CMD_TX_START))
5410 break;
e4901dde 5411 goto next_spqe;
55c11941 5412
a3348722 5413 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5414 echo = elem->message.data.function_update_event.echo;
5415 if (echo == SWITCH_UPDATE) {
5416 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5417 "got FUNC_SWITCH_UPDATE ramrod\n");
5418 if (f_obj->complete_cmd(
5419 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5420 break;
a3348722 5421
55c11941 5422 } else {
230bb0f3
YM		 5423 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5424
55c11941
MS		 5425 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5426 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5427 f_obj->complete_cmd(bp, f_obj,
5428 BNX2X_F_CMD_AFEX_UPDATE);
5429
5430 /* We will perform the Queues update from
5431 * sp_rtnl task as all Queue SP operations
5432 * should run under rtnl_lock.
5433 */
230bb0f3 5434 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
55c11941 5435 }
a3348722 5436
a3348722
BW		 5437 goto next_spqe;
5438
5439 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5440 f_obj->complete_cmd(bp, f_obj,
5441 BNX2X_F_CMD_AFEX_VIFLISTS);
5442 bnx2x_after_afex_vif_lists(bp, elem);
5443 goto next_spqe;
619c5cb6 5444 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5445 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5446 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5447 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5448 break;
5449
5450 goto next_spqe;
5451
5452 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5453 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5454 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5455 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5456 break;
5457
5458 goto next_spqe;
eeed018c
MK		 5459
5460 case EVENT_RING_OPCODE_SET_TIMESYNC:
5461 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5462 "got set_timesync ramrod completion\n");
5463 if (f_obj->complete_cmd(bp, f_obj,
5464 BNX2X_F_CMD_SET_TIMESYNC))
5465 break;
5466 goto next_spqe;
523224a3
DK		 5467 }
5468
5469 switch (opcode | bp->state) {
619c5cb6
VZ		 5470 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5471 BNX2X_STATE_OPEN):
5472 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5473 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 5474 cid = elem->message.data.eth_event.echo &
5475 BNX2X_SWCID_MASK;
d6cae238 5476 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 5477 cid);
5478 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5479 break;
5480
619c5cb6
VZ		 5481 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5482 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5483 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5484 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5485 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5486 BNX2X_STATE_OPEN):
5487 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5488 BNX2X_STATE_DIAG):
5489 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5490 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5491 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 5492 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5493 break;
5494
619c5cb6
VZ		 5495 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5496 BNX2X_STATE_OPEN):
5497 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5498 BNX2X_STATE_DIAG):
5499 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5500 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5501 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5502 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5503 break;
5504
619c5cb6
VZ		 5505 case (EVENT_RING_OPCODE_FILTERS_RULES |
5506 BNX2X_STATE_OPEN):
5507 case (EVENT_RING_OPCODE_FILTERS_RULES |
5508 BNX2X_STATE_DIAG):
5509 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5510 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5511 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5512 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5513 break;
5514 default:
5515 /* unknown event log error and continue */
619c5cb6
VZ		 5516 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5517 elem->message.opcode, bp->state);
523224a3
DK		 5518 }
5519next_spqe:
5520 spqe_cnt++;
5521 } /* for */
5522
4e857c58 5523 smp_mb__before_atomic();
6e30dd4e 5524 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5525
5526 bp->eq_cons = sw_cons;
5527 bp->eq_prod = sw_prod;
5528 /* Make sure that above mem writes were issued towards the memory */
5529 smp_wmb();
5530
5531 /* update producer */
5532 bnx2x_update_eq_prod(bp, bp->eq_prod);
5533}
5534
a2fbb9ea
ET		 5535static void bnx2x_sp_task(struct work_struct *work)
5536{
1cf167f2 5537 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5538
fd1fc79d 5539 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5540
16a5fd92 5541 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5542 smp_rmb();
5543 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5544
fd1fc79d
AE		 5545 /* what work needs to be performed? */
5546 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5547
fd1fc79d
AE		 5548 DP(BNX2X_MSG_SP, "status %x\n", status);
5549 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5550 atomic_set(&bp->interrupt_occurred, 0);
5551
5552 /* HW attentions */
5553 if (status & BNX2X_DEF_SB_ATT_IDX) {
5554 bnx2x_attn_int(bp);
5555 status &= ~BNX2X_DEF_SB_ATT_IDX;
5556 }
5557
5558 /* SP events: STAT_QUERY and others */
5559 if (status & BNX2X_DEF_SB_IDX) {
5560 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5561
55c11941 5562 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5563 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5564 /* Prevent local bottom-halves from running as
5565 * we are going to change the local NAPI list.
5566 */
5567 local_bh_disable();
5568 napi_schedule(&bnx2x_fcoe(bp, napi));
5569 local_bh_enable();
5570 }
5571
5572 /* Handle EQ completions */
5573 bnx2x_eq_int(bp);
5574 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5575 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5576
5577 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5578 }
55c11941 5579
fd1fc79d
AE		 5580 /* if status is non zero then perhaps something went wrong */
5581 if (unlikely(status))
5582 DP(BNX2X_MSG_SP,
5583 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5584
fd1fc79d
AE		 5585 /* ack status block only if something was actually handled */
5586 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5587 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5588 }
5589
a3348722
BW		 5590 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5591 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5592 &bp->sp_state)) {
5593 bnx2x_link_report(bp);
5594 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5595 }
a2fbb9ea
ET		 5596}
5597
9f6c9258 5598irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5599{
5600 struct net_device *dev = dev_instance;
5601 struct bnx2x *bp = netdev_priv(dev);
5602
523224a3
DK		 5603 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5604 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5605
5606#ifdef BNX2X_STOP_ON_ERROR
5607 if (unlikely(bp->panic))
5608 return IRQ_HANDLED;
5609#endif
5610
55c11941 5611 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5612 struct cnic_ops *c_ops;
5613
5614 rcu_read_lock();
5615 c_ops = rcu_dereference(bp->cnic_ops);
5616 if (c_ops)
5617 c_ops->cnic_handler(bp->cnic_data, NULL);
5618 rcu_read_unlock();
5619 }
55c11941 5620
fd1fc79d
AE		 5621 /* schedule sp task to perform default status block work, ack
5622 * attentions and enable interrupts.
5623 */
5624 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5625
5626 return IRQ_HANDLED;
5627}
5628
5629/* end of slow path */
5630
619c5cb6
VZ		 5631void bnx2x_drv_pulse(struct bnx2x *bp)
5632{
5633 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5634 bp->fw_drv_pulse_wr_seq);
5635}
5636
a2fbb9ea
ET		 5637static void bnx2x_timer(unsigned long data)
5638{
5639 struct bnx2x *bp = (struct bnx2x *) data;
5640
5641 if (!netif_running(bp->dev))
5642 return;
5643
67c431a5
AE		 5644 if (IS_PF(bp) &&
5645 !BP_NOMCP(bp)) {
f2e0899f 5646 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5647 u16 drv_pulse;
5648 u16 mcp_pulse;
a2fbb9ea
ET		 5649
5650 ++bp->fw_drv_pulse_wr_seq;
5651 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5652 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5653 bnx2x_drv_pulse(bp);
a2fbb9ea 5654
f2e0899f 5655 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5656 MCP_PULSE_SEQ_MASK);
5657 /* The delta between driver pulse and mcp response
4c868664
EG		 5658 * should not get too big. If the MFW is more than 5 pulses
5659 * behind, we should worry about it enough to generate an error
5660 * log.
a2fbb9ea 5661 */
4c868664
EG		 5662 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5663 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5664 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5665 }
5666
f34d28ea 5667 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5668 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5669
abc5a021 5670 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5671 if (IS_VF(bp))
5672 bnx2x_timer_sriov(bp);
78c3bcc5 5673
a2fbb9ea
ET		 5674 mod_timer(&bp->timer, jiffies + bp->current_interval);
5675}
5676
5677/* end of Statistics */
5678
5679/* nic init */
5680
5681/*
5682 * nic init service functions
5683 */
5684
1191cb83 5685static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5686{
523224a3
DK		 5687 u32 i;
5688 if (!(len%4) && !(addr%4))
5689 for (i = 0; i < len; i += 4)
5690 REG_WR(bp, addr + i, fill);
5691 else
5692 for (i = 0; i < len; i++)
5693 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5694}
5695
523224a3 5696/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5697static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5698 int fw_sb_id,
5699 u32 *sb_data_p,
5700 u32 data_size)
34f80b04 5701{
a2fbb9ea 5702 int index;
523224a3
DK		 5703 for (index = 0; index < data_size; index++)
5704 REG_WR(bp, BAR_CSTRORM_INTMEM +
5705 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5706 sizeof(u32)*index,
5707 *(sb_data_p + index));
5708}
a2fbb9ea 5709
1191cb83 5710static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5711{
5712 u32 *sb_data_p;
5713 u32 data_size = 0;
f2e0899f 5714 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5715 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5716
523224a3 5717 /* disable the function first */
619c5cb6 5718 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5719 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5720 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5721 sb_data_e2.common.p_func.vf_valid = false;
5722 sb_data_p = (u32 *)&sb_data_e2;
5723 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5724 } else {
5725 memset(&sb_data_e1x, 0,
5726 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5727 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5728 sb_data_e1x.common.p_func.vf_valid = false;
5729 sb_data_p = (u32 *)&sb_data_e1x;
5730 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5731 }
523224a3 5732 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5733
523224a3
DK		 5734 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5735 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5736 CSTORM_STATUS_BLOCK_SIZE);
5737 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5738 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5739 CSTORM_SYNC_BLOCK_SIZE);
5740}
34f80b04 5741
523224a3 5742/* helper: writes SP SB data to FW */
1191cb83 5743static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5744 struct hc_sp_status_block_data *sp_sb_data)
5745{
5746 int func = BP_FUNC(bp);
5747 int i;
5748 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5749 REG_WR(bp, BAR_CSTRORM_INTMEM +
5750 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5751 i*sizeof(u32),
5752 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5753}
5754
1191cb83 5755static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5756{
5757 int func = BP_FUNC(bp);
523224a3
DK		 5758 struct hc_sp_status_block_data sp_sb_data;
5759 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5760
619c5cb6 5761 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5762 sp_sb_data.p_func.vf_valid = false;
5763
5764 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5765
5766 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5767 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5768 CSTORM_SP_STATUS_BLOCK_SIZE);
5769 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5770 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5771 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5772}
5773
1191cb83 5774static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5775 int igu_sb_id, int igu_seg_id)
5776{
5777 hc_sm->igu_sb_id = igu_sb_id;
5778 hc_sm->igu_seg_id = igu_seg_id;
5779 hc_sm->timer_value = 0xFF;
5780 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5781}
5782
150966ad 5783/* allocates state machine ids. */
1191cb83 5784static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5785{
5786 /* zero out state machine indices */
5787 /* rx indices */
5788 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5789
5790 /* tx indices */
5791 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5792 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5793 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5794 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5795
5796 /* map indices */
5797 /* rx indices */
5798 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5799 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5800
5801 /* tx indices */
5802 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5803 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5804 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5805 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5806 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5807 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5808 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5809 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5810}
5811
b93288d5 5812void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5813 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5814{
523224a3
DK		 5815 int igu_seg_id;
5816
f2e0899f 5817 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5818 struct hc_status_block_data_e1x sb_data_e1x;
5819 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5820 int data_size;
5821 u32 *sb_data_p;
5822
f2e0899f
DK		 5823 if (CHIP_INT_MODE_IS_BC(bp))
5824 igu_seg_id = HC_SEG_ACCESS_NORM;
5825 else
5826 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5827
5828 bnx2x_zero_fp_sb(bp, fw_sb_id);
5829
619c5cb6 5830 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5831 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5832 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5833 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5834 sb_data_e2.common.p_func.vf_id = vfid;
5835 sb_data_e2.common.p_func.vf_valid = vf_valid;
5836 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5837 sb_data_e2.common.same_igu_sb_1b = true;
5838 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5839 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5840 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5841 sb_data_p = (u32 *)&sb_data_e2;
5842 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5843 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5844 } else {
5845 memset(&sb_data_e1x, 0,
5846 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5847 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5848 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5849 sb_data_e1x.common.p_func.vf_id = 0xff;
5850 sb_data_e1x.common.p_func.vf_valid = false;
5851 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5852 sb_data_e1x.common.same_igu_sb_1b = true;
5853 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5854 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5855 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5856 sb_data_p = (u32 *)&sb_data_e1x;
5857 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5858 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5859 }
523224a3
DK		 5860
5861 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5862 igu_sb_id, igu_seg_id);
5863 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5864 igu_sb_id, igu_seg_id);
5865
51c1a580 5866 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 5867
86564c3f 5868 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 5869 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5870}
5871
619c5cb6 5872static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5873 u16 tx_usec, u16 rx_usec)
5874{
6383c0b3 5875 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5876 false, rx_usec);
6383c0b3
AE		 5877 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5878 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5879 tx_usec);
5880 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5881 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5882 tx_usec);
5883 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5884 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5885 tx_usec);
523224a3 5886}
f2e0899f 5887
523224a3
DK		 5888static void bnx2x_init_def_sb(struct bnx2x *bp)
5889{
5890 struct host_sp_status_block *def_sb = bp->def_status_blk;
5891 dma_addr_t mapping = bp->def_status_blk_mapping;
5892 int igu_sp_sb_index;
5893 int igu_seg_id;
34f80b04
EG		 5894 int port = BP_PORT(bp);
5895 int func = BP_FUNC(bp);
f2eaeb58 5896 int reg_offset, reg_offset_en5;
a2fbb9ea 5897 u64 section;
523224a3
DK		 5898 int index;
5899 struct hc_sp_status_block_data sp_sb_data;
5900 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5901
f2e0899f
DK		 5902 if (CHIP_INT_MODE_IS_BC(bp)) {
5903 igu_sp_sb_index = DEF_SB_IGU_ID;
5904 igu_seg_id = HC_SEG_ACCESS_DEF;
5905 } else {
5906 igu_sp_sb_index = bp->igu_dsb_id;
5907 igu_seg_id = IGU_SEG_ACCESS_DEF;
5908 }
a2fbb9ea
ET		 5909
5910 /* ATTN */
523224a3 5911 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5912 atten_status_block);
523224a3 5913 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5914
49d66772
ET		 5915 bp->attn_state = 0;
5916
a2fbb9ea
ET		 5917 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5918 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5919 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5920 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5921 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5922 int sindex;
5923 /* take care of sig[0]..sig[4] */
5924 for (sindex = 0; sindex < 4; sindex++)
5925 bp->attn_group[index].sig[sindex] =
5926 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5927
619c5cb6 5928 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5929 /*
5930 * enable5 is separate from the rest of the registers,
5931 * and therefore the address skip is 4
5932 * and not 16 between the different groups
5933 */
5934 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5935 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5936 else
5937 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5938 }
5939
f2e0899f
DK		 5940 if (bp->common.int_block == INT_BLOCK_HC) {
5941 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5942 HC_REG_ATTN_MSG0_ADDR_L);
5943
5944 REG_WR(bp, reg_offset, U64_LO(section));
5945 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5946 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5947 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5948 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5949 }
a2fbb9ea 5950
523224a3
DK		 5951 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5952 sp_sb);
a2fbb9ea 5953
523224a3 5954 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5955
86564c3f 5956 /* PCI guarantees endianity of regpairs */
619c5cb6 5957 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5958 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5959 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5960 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5961 sp_sb_data.igu_seg_id = igu_seg_id;
5962 sp_sb_data.p_func.pf_id = func;
f2e0899f 5963 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5964 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5965
523224a3 5966 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5967
523224a3 5968 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5969}
5970
9f6c9258 5971void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5972{
a2fbb9ea
ET		 5973 int i;
5974
ec6ba945 5975 for_each_eth_queue(bp, i)
523224a3 5976 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5977 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5978}
5979
a2fbb9ea
ET		 5980static void bnx2x_init_sp_ring(struct bnx2x *bp)
5981{
a2fbb9ea 5982 spin_lock_init(&bp->spq_lock);
6e30dd4e 5983 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5984
a2fbb9ea 5985 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5986 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5987 bp->spq_prod_bd = bp->spq;
5988 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5989}
5990
523224a3 5991static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5992{
5993 int i;
523224a3
DK		 5994 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5995 union event_ring_elem *elem =
5996 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5997
523224a3
DK		 5998 elem->next_page.addr.hi =
5999 cpu_to_le32(U64_HI(bp->eq_mapping +
6000 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6001 elem->next_page.addr.lo =
6002 cpu_to_le32(U64_LO(bp->eq_mapping +
6003 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 6004 }
523224a3
DK		 6005 bp->eq_cons = 0;
6006 bp->eq_prod = NUM_EQ_DESC;
6007 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 6008 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 6009 atomic_set(&bp->eq_spq_left,
6010 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 6011}
6012
619c5cb6 6013/* called with netif_addr_lock_bh() */
a8f47eb7 6014static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6015 unsigned long rx_mode_flags,
6016 unsigned long rx_accept_flags,
6017 unsigned long tx_accept_flags,
6018 unsigned long ramrod_flags)
ab532cf3 6019{
619c5cb6
VZ		 6020 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6021 int rc;
6022
6023 memset(&ramrod_param, 0, sizeof(ramrod_param));
6024
6025 /* Prepare ramrod parameters */
6026 ramrod_param.cid = 0;
6027 ramrod_param.cl_id = cl_id;
6028 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6029 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 6030
619c5cb6
VZ		 6031 ramrod_param.pstate = &bp->sp_state;
6032 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 6033
619c5cb6
VZ		 6034 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6035 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6036
6037 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6038
6039 ramrod_param.ramrod_flags = ramrod_flags;
6040 ramrod_param.rx_mode_flags = rx_mode_flags;
6041
6042 ramrod_param.rx_accept_flags = rx_accept_flags;
6043 ramrod_param.tx_accept_flags = tx_accept_flags;
6044
6045 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6046 if (rc < 0) {
6047 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 6048 return rc;
619c5cb6 6049 }
924d75ab
YM		 6050
6051 return 0;
a2fbb9ea
ET		 6052}
6053
86564c3f
YM		 6054static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6055 unsigned long *rx_accept_flags,
6056 unsigned long *tx_accept_flags)
471de716 6057{
924d75ab
YM		 6058 /* Clear the flags first */
6059 *rx_accept_flags = 0;
6060 *tx_accept_flags = 0;
619c5cb6 6061
924d75ab 6062 switch (rx_mode) {
619c5cb6
VZ		 6063 case BNX2X_RX_MODE_NONE:
6064 /*
6065 * 'drop all' supersedes any accept flags that may have been
6066 * passed to the function.
6067 */
6068 break;
6069 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 6070 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6071 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6072 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6073
6074 /* internal switching mode */
924d75ab
YM		 6075 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6076 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6077 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6078
6079 break;
6080 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 6081 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6082 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6083 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6084
6085 /* internal switching mode */
924d75ab
YM		 6086 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6087 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6088 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6089
6090 break;
6091 case BNX2X_RX_MODE_PROMISC:
16a5fd92 6092 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 6093 * should receive matched and unmatched (in resolution of port)
6094 * unicast packets.
6095 */
924d75ab
YM		 6096 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6097 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6098 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6099 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6100
6101 /* internal switching mode */
924d75ab
YM		 6102 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6103 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6104
6105 if (IS_MF_SI(bp))
924d75ab 6106 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 6107 else
924d75ab 6108 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6
VZ		 6109
6110 break;
6111 default:
924d75ab
YM		 6112 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6113 return -EINVAL;
619c5cb6 6114 }
de832a55 6115
924d75ab 6116 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
619c5cb6 6117 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
924d75ab
YM		 6118 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6119 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
34f80b04
EG		 6120 }
6121
924d75ab
YM		 6122 return 0;
6123}
6124
6125/* called with netif_addr_lock_bh() */
a8f47eb7 6126static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6127{
6128 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6129 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6130 int rc;
6131
6132 if (!NO_FCOE(bp))
6133 /* Configure rx_mode of FCoE Queue */
6134 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6135
6136 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6137 &tx_accept_flags);
6138 if (rc)
6139 return rc;
6140
619c5cb6
VZ		 6141 __set_bit(RAMROD_RX, &ramrod_flags);
6142 __set_bit(RAMROD_TX, &ramrod_flags);
6143
924d75ab
YM		 6144 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6145 rx_accept_flags, tx_accept_flags,
6146 ramrod_flags);
619c5cb6
VZ		 6147}
6148
6149static void bnx2x_init_internal_common(struct bnx2x *bp)
6150{
6151 int i;
6152
523224a3
DK		 6153 /* Zero this manually as its initialization is
6154 currently missing in the initTool */
6155 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6156 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6157 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6158 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6159 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6160 CHIP_INT_MODE_IS_BC(bp) ?
6161 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6162 }
523224a3 6163}
8a1c38d1 6164
471de716
EG		 6165static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6166{
6167 switch (load_code) {
6168 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6169 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6170 bnx2x_init_internal_common(bp);
6171 /* no break */
6172
6173 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6174 /* nothing to do */
471de716
EG		 6175 /* no break */
6176
6177 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6178 /* internal memory per function is
6179 initialized inside bnx2x_pf_init */
471de716
EG		 6180 break;
6181
6182 default:
6183 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6184 break;
6185 }
6186}
6187
619c5cb6 6188static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6189{
55c11941 6190 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6191}
523224a3 6192
619c5cb6
VZ		 6193static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6194{
55c11941 6195 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6196}
6197
1191cb83 6198static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6199{
6200 if (CHIP_IS_E1x(fp->bp))
6201 return BP_L_ID(fp->bp) + fp->index;
6202 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6203 return bnx2x_fp_igu_sb_id(fp);
6204}
6205
6383c0b3 6206static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6207{
6208 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6209 u8 cos;
619c5cb6 6210 unsigned long q_type = 0;
6383c0b3 6211 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6212 fp->rx_queue = fp_idx;
b3b83c3f 6213 fp->cid = fp_idx;
619c5cb6
VZ		 6214 fp->cl_id = bnx2x_fp_cl_id(fp);
6215 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6216 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6217 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6218 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6219
523224a3 6220 /* init shortcut */
619c5cb6 6221 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6222
16a5fd92 6223 /* Setup SB indices */
523224a3 6224 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6225
619c5cb6
VZ		 6226 /* Configure Queue State object */
6227 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6228 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6229
6230 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6231
6232 /* init tx data */
6233 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6234 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6235 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6236 FP_COS_TO_TXQ(fp, cos, bp),
6237 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6238 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6239 }
6240
ad5afc89
AE		 6241 /* nothing more for vf to do here */
6242 if (IS_VF(bp))
6243 return;
6244
6245 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6246 fp->fw_sb_id, fp->igu_sb_id);
6247 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6248 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6249 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6250 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6251
6252 /**
6253 * Configure classification DBs: Always enable Tx switching
6254 */
6255 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6256
ad5afc89
AE		 6257 DP(NETIF_MSG_IFUP,
6258 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6259 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6260 fp->igu_sb_id);
523224a3
DK		 6261}
6262
1191cb83
ED		 6263static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6264{
6265 int i;
6266
6267 for (i = 1; i <= NUM_TX_RINGS; i++) {
6268 struct eth_tx_next_bd *tx_next_bd =
6269 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6270
6271 tx_next_bd->addr_hi =
6272 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6273 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6274 tx_next_bd->addr_lo =
6275 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6276 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6277 }
6278
639d65b8
YM		 6279 *txdata->tx_cons_sb = cpu_to_le16(0);
6280
1191cb83
ED		 6281 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6282 txdata->tx_db.data.zero_fill1 = 0;
6283 txdata->tx_db.data.prod = 0;
6284
6285 txdata->tx_pkt_prod = 0;
6286 txdata->tx_pkt_cons = 0;
6287 txdata->tx_bd_prod = 0;
6288 txdata->tx_bd_cons = 0;
6289 txdata->tx_pkt = 0;
6290}
6291
55c11941
MS		 6292static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6293{
6294 int i;
6295
6296 for_each_tx_queue_cnic(bp, i)
6297 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6298}
d76a6111 6299
1191cb83
ED		 6300static void bnx2x_init_tx_rings(struct bnx2x *bp)
6301{
6302 int i;
6303 u8 cos;
6304
55c11941 6305 for_each_eth_queue(bp, i)
1191cb83 6306 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6307 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6308}
6309
a8f47eb7 6310static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6311{
6312 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6313 unsigned long q_type = 0;
6314
6315 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6316 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6317 BNX2X_FCOE_ETH_CL_ID_IDX);
6318 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6319 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6320 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6321 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6322 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6323 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6324 fp);
6325
6326 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6327
6328 /* qZone id equals to FW (per path) client id */
6329 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6330 /* init shortcut */
6331 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6332 bnx2x_rx_ustorm_prods_offset(fp);
6333
6334 /* Configure Queue State object */
6335 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6336 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6337
6338 /* No multi-CoS for FCoE L2 client */
6339 BUG_ON(fp->max_cos != 1);
6340
6341 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6342 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6343 bnx2x_sp_mapping(bp, q_rdata), q_type);
6344
6345 DP(NETIF_MSG_IFUP,
6346 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6347 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6348 fp->igu_sb_id);
6349}
6350
55c11941 6351void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6352{
ec6ba945
VZ		 6353 if (!NO_FCOE(bp))
6354 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6355
6356 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6357 BNX2X_VF_ID_INVALID, false,
619c5cb6 6358 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6359
55c11941
MS		 6360 /* ensure status block indices were read */
6361 rmb();
6362 bnx2x_init_rx_rings_cnic(bp);
6363 bnx2x_init_tx_rings_cnic(bp);
6364
6365 /* flush all */
6366 mb();
6367 mmiowb();
6368}
a2fbb9ea 6369
ecf01c22 6370void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6371{
6372 int i;
6373
ecf01c22 6374 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6375 for_each_eth_queue(bp, i)
6376 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6377
6378 /* ensure status block indices were read */
6379 rmb();
6380 bnx2x_init_rx_rings(bp);
6381 bnx2x_init_tx_rings(bp);
6382
ecf01c22
YM		 6383 if (IS_PF(bp)) {
6384 /* Initialize MOD_ABS interrupts */
6385 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6386 bp->common.shmem_base,
6387 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6388
ecf01c22
YM		 6389 /* initialize the default status block and sp ring */
6390 bnx2x_init_def_sb(bp);
6391 bnx2x_update_dsb_idx(bp);
6392 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6393 } else {
6394 bnx2x_memset_stats(bp);
ecf01c22
YM		 6395 }
6396}
16119785 6397
ecf01c22
YM		 6398void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6399{
523224a3 6400 bnx2x_init_eq_ring(bp);
471de716 6401 bnx2x_init_internal(bp, load_code);
523224a3 6402 bnx2x_pf_init(bp);
0ef00459
EG		 6403 bnx2x_stats_init(bp);
6404
0ef00459
EG		 6405 /* flush all before enabling interrupts */
6406 mb();
6407 mmiowb();
6408
615f8fd9 6409 bnx2x_int_enable(bp);
eb8da205
EG		 6410
6411 /* Check for SPIO5 */
6412 bnx2x_attn_int_deasserted0(bp,
6413 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6414 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6415}
6416
ecf01c22 6417/* gzip service functions */
a2fbb9ea
ET		 6418static int bnx2x_gunzip_init(struct bnx2x *bp)
6419{
1a983142
FT		 6420 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6421 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6422 if (bp->gunzip_buf == NULL)
6423 goto gunzip_nomem1;
6424
6425 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6426 if (bp->strm == NULL)
6427 goto gunzip_nomem2;
6428
7ab24bfd 6429 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6430 if (bp->strm->workspace == NULL)
6431 goto gunzip_nomem3;
6432
6433 return 0;
6434
6435gunzip_nomem3:
6436 kfree(bp->strm);
6437 bp->strm = NULL;
6438
6439gunzip_nomem2:
1a983142
FT		 6440 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6441 bp->gunzip_mapping);
a2fbb9ea
ET		 6442 bp->gunzip_buf = NULL;
6443
6444gunzip_nomem1:
51c1a580 6445 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6446 return -ENOMEM;
6447}
6448
6449static void bnx2x_gunzip_end(struct bnx2x *bp)
6450{
b3b83c3f 6451 if (bp->strm) {
7ab24bfd 6452 vfree(bp->strm->workspace);
b3b83c3f
DK		 6453 kfree(bp->strm);
6454 bp->strm = NULL;
6455 }
a2fbb9ea
ET		 6456
6457 if (bp->gunzip_buf) {
1a983142
FT		 6458 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6459 bp->gunzip_mapping);
a2fbb9ea
ET		 6460 bp->gunzip_buf = NULL;
6461 }
6462}
6463
94a78b79 6464static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6465{
6466 int n, rc;
6467
6468 /* check gzip header */
94a78b79
VZ		 6469 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6470 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6471 return -EINVAL;
94a78b79 6472 }
a2fbb9ea
ET		 6473
6474 n = 10;
6475
34f80b04 6476#define FNAME 0x8
a2fbb9ea
ET		 6477
6478 if (zbuf[3] & FNAME)
6479 while ((zbuf[n++] != 0) && (n < len));
6480
94a78b79 6481 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6482 bp->strm->avail_in = len - n;
6483 bp->strm->next_out = bp->gunzip_buf;
6484 bp->strm->avail_out = FW_BUF_SIZE;
6485
6486 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6487 if (rc != Z_OK)
6488 return rc;
6489
6490 rc = zlib_inflate(bp->strm, Z_FINISH);
6491 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6492 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6493 bp->strm->msg);
a2fbb9ea
ET		 6494
6495 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6496 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6497 netdev_err(bp->dev,
6498 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6499 bp->gunzip_outlen);
a2fbb9ea
ET		 6500 bp->gunzip_outlen >>= 2;
6501
6502 zlib_inflateEnd(bp->strm);
6503
6504 if (rc == Z_STREAM_END)
6505 return 0;
6506
6507 return rc;
6508}
6509
6510/* nic load/unload */
6511
6512/*
34f80b04 6513 * General service functions
a2fbb9ea
ET		 6514 */
6515
6516/* send a NIG loopback debug packet */
6517static void bnx2x_lb_pckt(struct bnx2x *bp)
6518{
a2fbb9ea 6519 u32 wb_write[3];
a2fbb9ea
ET		 6520
6521 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6522 wb_write[0] = 0x55555555;
6523 wb_write[1] = 0x55555555;
34f80b04 6524 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6525 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6526
6527 /* NON-IP protocol */
a2fbb9ea
ET		 6528 wb_write[0] = 0x09000000;
6529 wb_write[1] = 0x55555555;
34f80b04 6530 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6531 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6532}
6533
6534/* some of the internal memories
6535 * are not directly readable from the driver
6536 * to test them we send debug packets
6537 */
6538static int bnx2x_int_mem_test(struct bnx2x *bp)
6539{
6540 int factor;
6541 int count, i;
6542 u32 val = 0;
6543
ad8d3948 6544 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6545 factor = 120;
ad8d3948
EG		 6546 else if (CHIP_REV_IS_EMUL(bp))
6547 factor = 200;
6548 else
a2fbb9ea 6549 factor = 1;
a2fbb9ea 6550
a2fbb9ea
ET		 6551 /* Disable inputs of parser neighbor blocks */
6552 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6553 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6554 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6555 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6556
6557 /* Write 0 to parser credits for CFC search request */
6558 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6559
6560 /* send Ethernet packet */
6561 bnx2x_lb_pckt(bp);
6562
6563 /* TODO do i reset NIG statistic? */
6564 /* Wait until NIG register shows 1 packet of size 0x10 */
6565 count = 1000 * factor;
6566 while (count) {
34f80b04 6567
a2fbb9ea
ET		 6568 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6569 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6570 if (val == 0x10)
6571 break;
6572
639d65b8 6573 usleep_range(10000, 20000);
a2fbb9ea
ET		 6574 count--;
6575 }
6576 if (val != 0x10) {
6577 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6578 return -1;
6579 }
6580
6581 /* Wait until PRS register shows 1 packet */
6582 count = 1000 * factor;
6583 while (count) {
6584 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6585 if (val == 1)
6586 break;
6587
639d65b8 6588 usleep_range(10000, 20000);
a2fbb9ea
ET		 6589 count--;
6590 }
6591 if (val != 0x1) {
6592 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6593 return -2;
6594 }
6595
6596 /* Reset and init BRB, PRS */
34f80b04 6597 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6598 msleep(50);
34f80b04 6599 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6600 msleep(50);
619c5cb6
VZ		 6601 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6602 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6603
6604 DP(NETIF_MSG_HW, "part2\n");
6605
6606 /* Disable inputs of parser neighbor blocks */
6607 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6608 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6609 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6610 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6611
6612 /* Write 0 to parser credits for CFC search request */
6613 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6614
6615 /* send 10 Ethernet packets */
6616 for (i = 0; i < 10; i++)
6617 bnx2x_lb_pckt(bp);
6618
6619 /* Wait until NIG register shows 10 + 1
6620 packets of size 11*0x10 = 0xb0 */
6621 count = 1000 * factor;
6622 while (count) {
34f80b04 6623
a2fbb9ea
ET		 6624 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6625 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6626 if (val == 0xb0)
6627 break;
6628
639d65b8 6629 usleep_range(10000, 20000);
a2fbb9ea
ET		 6630 count--;
6631 }
6632 if (val != 0xb0) {
6633 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6634 return -3;
6635 }
6636
6637 /* Wait until PRS register shows 2 packets */
6638 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6639 if (val != 2)
6640 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6641
6642 /* Write 1 to parser credits for CFC search request */
6643 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6644
6645 /* Wait until PRS register shows 3 packets */
6646 msleep(10 * factor);
6647 /* Wait until NIG register shows 1 packet of size 0x10 */
6648 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6649 if (val != 3)
6650 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6651
6652 /* clear NIG EOP FIFO */
6653 for (i = 0; i < 11; i++)
6654 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6655 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6656 if (val != 1) {
6657 BNX2X_ERR("clear of NIG failed\n");
6658 return -4;
6659 }
6660
6661 /* Reset and init BRB, PRS, NIG */
6662 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6663 msleep(50);
6664 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6665 msleep(50);
619c5cb6
VZ		 6666 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6667 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6668 if (!CNIC_SUPPORT(bp))
6669 /* set NIC mode */
6670 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6671
6672 /* Enable inputs of parser neighbor blocks */
6673 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6674 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6675 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6676 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6677
6678 DP(NETIF_MSG_HW, "done\n");
6679
6680 return 0; /* OK */
6681}
6682
4a33bc03 6683static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6684{
b343d002
YM		 6685 u32 val;
6686
a2fbb9ea 6687 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6688 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6689 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6690 else
6691 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6692 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6693 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6694 /*
6695 * mask read length error interrupts in brb for parser
6696 * (parsing unit and 'checksum and crc' unit)
6697 * these errors are legal (PU reads fixed length and CAC can cause
6698 * read length error on truncated packets)
6699 */
6700 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6701 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6702 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6703 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6704 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6705 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6706/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6707/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6708 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6709 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6710 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6711/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6712/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6713 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6714 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6715 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6716 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6717/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6718/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6719
b343d002
YM		 6720 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6721 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6722 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6723 if (!CHIP_IS_E1x(bp))
6724 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6725 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6726 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6727
a2fbb9ea
ET		 6728 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6729 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6730 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6731/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6732
6733 if (!CHIP_IS_E1x(bp))
6734 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6735 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6736
a2fbb9ea
ET		 6737 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6738 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6739/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6740 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6741}
6742
81f75bbf
EG		 6743static void bnx2x_reset_common(struct bnx2x *bp)
6744{
619c5cb6
VZ		 6745 u32 val = 0x1400;
6746
81f75bbf
EG		 6747 /* reset_common */
6748 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6749 0xd3ffff7f);
619c5cb6
VZ		 6750
6751 if (CHIP_IS_E3(bp)) {
6752 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6753 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6754 }
6755
6756 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6757}
6758
6759static void bnx2x_setup_dmae(struct bnx2x *bp)
6760{
6761 bp->dmae_ready = 0;
6762 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6763}
6764
573f2035
EG		 6765static void bnx2x_init_pxp(struct bnx2x *bp)
6766{
6767 u16 devctl;
6768 int r_order, w_order;
6769
2a80eebc 6770 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6771 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6772 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6773 if (bp->mrrs == -1)
6774 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6775 else {
6776 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6777 r_order = bp->mrrs;
6778 }
6779
6780 bnx2x_init_pxp_arb(bp, r_order, w_order);
6781}
fd4ef40d
EG		 6782
6783static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6784{
2145a920 6785 int is_required;
fd4ef40d 6786 u32 val;
2145a920 6787 int port;
fd4ef40d 6788
2145a920
VZ		 6789 if (BP_NOMCP(bp))
6790 return;
6791
6792 is_required = 0;
fd4ef40d
EG		 6793 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6794 SHARED_HW_CFG_FAN_FAILURE_MASK;
6795
6796 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6797 is_required = 1;
6798
6799 /*
6800 * The fan failure mechanism is usually related to the PHY type since
6801 * the power consumption of the board is affected by the PHY. Currently,
6802 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6803 */
6804 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6805 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6806 is_required |=
d90d96ba
YR		 6807 bnx2x_fan_failure_det_req(
6808 bp,
6809 bp->common.shmem_base,
a22f0788 6810 bp->common.shmem2_base,
d90d96ba 6811 port);
fd4ef40d
EG		 6812 }
6813
6814 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6815
6816 if (is_required == 0)
6817 return;
6818
6819 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6820 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6821
6822 /* set to active low mode */
6823 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6824 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6825 REG_WR(bp, MISC_REG_SPIO_INT, val);
6826
6827 /* enable interrupt to signal the IGU */
6828 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6829 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6830 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6831}
6832
c9ee9206 6833void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6834{
6835 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6836 val &= ~IGU_PF_CONF_FUNC_EN;
6837
6838 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6839 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6840 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6841}
6842
1191cb83 6843static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6844{
6845 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6846 /* Avoid common init in case MFW supports LFA */
6847 if (SHMEM2_RD(bp, size) >
6848 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6849 return;
619c5cb6
VZ		 6850 shmem_base[0] = bp->common.shmem_base;
6851 shmem2_base[0] = bp->common.shmem2_base;
6852 if (!CHIP_IS_E1x(bp)) {
6853 shmem_base[1] =
6854 SHMEM2_RD(bp, other_shmem_base_addr);
6855 shmem2_base[1] =
6856 SHMEM2_RD(bp, other_shmem2_base_addr);
6857 }
6858 bnx2x_acquire_phy_lock(bp);
6859 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6860 bp->common.chip_id);
6861 bnx2x_release_phy_lock(bp);
6862}
6863
6864/**
6865 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6866 *
6867 * @bp: driver handle
6868 */
6869static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6870{
619c5cb6 6871 u32 val;
a2fbb9ea 6872
51c1a580 6873 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6874
2031bd3a 6875 /*
2de67439 6876 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 6877 * registers while we're resetting the chip
6878 */
7a06a122 6879 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6880
81f75bbf 6881 bnx2x_reset_common(bp);
34f80b04 6882 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6883
619c5cb6
VZ		 6884 val = 0xfffc;
6885 if (CHIP_IS_E3(bp)) {
6886 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6887 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6888 }
6889 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6890
7a06a122 6891 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6892
619c5cb6 6893 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6894
619c5cb6
VZ		 6895 if (!CHIP_IS_E1x(bp)) {
6896 u8 abs_func_id;
f2e0899f
DK		 6897
6898 /**
6899 * 4-port mode or 2-port mode we need to turn of master-enable
6900 * for everyone, after that, turn it back on for self.
6901 * so, we disregard multi-function or not, and always disable
6902 * for all functions on the given path, this means 0,2,4,6 for
6903 * path 0 and 1,3,5,7 for path 1
6904 */
619c5cb6
VZ		 6905 for (abs_func_id = BP_PATH(bp);
6906 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6907 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6908 REG_WR(bp,
6909 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6910 1);
6911 continue;
6912 }
6913
619c5cb6 6914 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6915 /* clear pf enable */
6916 bnx2x_pf_disable(bp);
6917 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6918 }
6919 }
a2fbb9ea 6920
619c5cb6 6921 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6922 if (CHIP_IS_E1(bp)) {
6923 /* enable HW interrupt from PXP on USDM overflow
6924 bit 16 on INT_MASK_0 */
6925 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6926 }
a2fbb9ea 6927
619c5cb6 6928 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6929 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 6930
6931#ifdef __BIG_ENDIAN
34f80b04
EG		 6932 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6933 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6934 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6935 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6936 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 6937 /* make sure this value is 0 */
6938 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 6939
6940/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6941 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6942 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6943 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6944 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 6945#endif
6946
523224a3
DK		 6947 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6948
34f80b04
EG		 6949 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6950 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6951
34f80b04
EG		 6952 /* let the HW do it's magic ... */
6953 msleep(100);
6954 /* finish PXP init */
6955 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6956 if (val != 1) {
6957 BNX2X_ERR("PXP2 CFG failed\n");
6958 return -EBUSY;
6959 }
6960 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6961 if (val != 1) {
6962 BNX2X_ERR("PXP2 RD_INIT failed\n");
6963 return -EBUSY;
6964 }
a2fbb9ea 6965
f2e0899f
DK		 6966 /* Timers bug workaround E2 only. We need to set the entire ILT to
6967 * have entries with value "0" and valid bit on.
6968 * This needs to be done by the first PF that is loaded in a path
6969 * (i.e. common phase)
6970 */
619c5cb6
VZ		 6971 if (!CHIP_IS_E1x(bp)) {
6972/* In E2 there is a bug in the timers block that can cause function 6 / 7
6973 * (i.e. vnic3) to start even if it is marked as "scan-off".
6974 * This occurs when a different function (func2,3) is being marked
6975 * as "scan-off". Real-life scenario for example: if a driver is being
6976 * load-unloaded while func6,7 are down. This will cause the timer to access
6977 * the ilt, translate to a logical address and send a request to read/write.
6978 * Since the ilt for the function that is down is not valid, this will cause
6979 * a translation error which is unrecoverable.
6980 * The Workaround is intended to make sure that when this happens nothing fatal
6981 * will occur. The workaround:
6982 * 1. First PF driver which loads on a path will:
6983 * a. After taking the chip out of reset, by using pretend,
6984 * it will write "0" to the following registers of
6985 * the other vnics.
6986 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6987 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6988 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6989 * And for itself it will write '1' to
6990 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6991 * dmae-operations (writing to pram for example.)
6992 * note: can be done for only function 6,7 but cleaner this
6993 * way.
6994 * b. Write zero+valid to the entire ILT.
6995 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6996 * VNIC3 (of that port). The range allocated will be the
6997 * entire ILT. This is needed to prevent ILT range error.
6998 * 2. Any PF driver load flow:
6999 * a. ILT update with the physical addresses of the allocated
7000 * logical pages.
7001 * b. Wait 20msec. - note that this timeout is needed to make
7002 * sure there are no requests in one of the PXP internal
7003 * queues with "old" ILT addresses.
7004 * c. PF enable in the PGLC.
7005 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 7006 * occurred while driver was down)
619c5cb6
VZ		 7007 * e. PF enable in the CFC (WEAK + STRONG)
7008 * f. Timers scan enable
7009 * 3. PF driver unload flow:
7010 * a. Clear the Timers scan_en.
7011 * b. Polling for scan_on=0 for that PF.
7012 * c. Clear the PF enable bit in the PXP.
7013 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7014 * e. Write zero+valid to all ILT entries (The valid bit must
7015 * stay set)
7016 * f. If this is VNIC 3 of a port then also init
7017 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 7018 * to the last entry in the ILT.
619c5cb6
VZ		 7019 *
7020 * Notes:
7021 * Currently the PF error in the PGLC is non recoverable.
7022 * In the future the there will be a recovery routine for this error.
7023 * Currently attention is masked.
7024 * Having an MCP lock on the load/unload process does not guarantee that
7025 * there is no Timer disable during Func6/7 enable. This is because the
7026 * Timers scan is currently being cleared by the MCP on FLR.
7027 * Step 2.d can be done only for PF6/7 and the driver can also check if
7028 * there is error before clearing it. But the flow above is simpler and
7029 * more general.
7030 * All ILT entries are written by zero+valid and not just PF6/7
7031 * ILT entries since in the future the ILT entries allocation for
7032 * PF-s might be dynamic.
7033 */
f2e0899f
DK		 7034 struct ilt_client_info ilt_cli;
7035 struct bnx2x_ilt ilt;
7036 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7037 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7038
b595076a 7039 /* initialize dummy TM client */
f2e0899f
DK		 7040 ilt_cli.start = 0;
7041 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7042 ilt_cli.client_num = ILT_CLIENT_TM;
7043
7044 /* Step 1: set zeroes to all ilt page entries with valid bit on
7045 * Step 2: set the timers first/last ilt entry to point
7046 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 7047 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 7048 *
7049 * both steps performed by call to bnx2x_ilt_client_init_op()
7050 * with dummy TM client
7051 *
7052 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7053 * and his brother are split registers
7054 */
7055 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7056 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7057 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7058
7059 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7060 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7061 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7062 }
7063
34f80b04
EG		 7064 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7065 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 7066
619c5cb6 7067 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7068 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7069 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 7070 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 7071
619c5cb6 7072 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 7073
7074 /* let the HW do it's magic ... */
7075 do {
7076 msleep(200);
7077 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7078 } while (factor-- && (val != 1));
7079
7080 if (val != 1) {
7081 BNX2X_ERR("ATC_INIT failed\n");
7082 return -EBUSY;
7083 }
7084 }
7085
619c5cb6 7086 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 7087
b56e9670
AE		 7088 bnx2x_iov_init_dmae(bp);
7089
34f80b04
EG		 7090 /* clean the DMAE memory */
7091 bp->dmae_ready = 1;
619c5cb6
VZ		 7092 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7093
7094 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7095
7096 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7097
7098 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 7099
619c5cb6 7100 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 7101
34f80b04
EG		 7102 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7103 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7104 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7105 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7106
619c5cb6 7107 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 7108
523224a3
DK		 7109 /* QM queues pointers table */
7110 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7111
34f80b04
EG		 7112 /* soft reset pulse */
7113 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7114 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 7115
55c11941
MS		 7116 if (CNIC_SUPPORT(bp))
7117 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 7118
619c5cb6 7119 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 7120
619c5cb6 7121 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7122 /* enable hw interrupt from doorbell Q */
7123 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7124
619c5cb6 7125 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7126
619c5cb6 7127 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7128 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7129
f2e0899f 7130 if (!CHIP_IS_E1(bp))
619c5cb6 7131 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7132
a3348722
BW		 7133 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7134 if (IS_MF_AFEX(bp)) {
7135 /* configure that VNTag and VLAN headers must be
7136 * received in afex mode
7137 */
7138 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7139 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7140 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7141 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7142 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7143 } else {
7144 /* Bit-map indicating which L2 hdrs may appear
7145 * after the basic Ethernet header
7146 */
7147 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7148 bp->path_has_ovlan ? 7 : 6);
7149 }
7150 }
a2fbb9ea 7151
619c5cb6
VZ		 7152 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7153 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7154 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7155 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7156
619c5cb6
VZ		 7157 if (!CHIP_IS_E1x(bp)) {
7158 /* reset VFC memories */
7159 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7160 VFC_MEMORIES_RST_REG_CAM_RST |
7161 VFC_MEMORIES_RST_REG_RAM_RST);
7162 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7163 VFC_MEMORIES_RST_REG_CAM_RST |
7164 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7165
619c5cb6
VZ		 7166 msleep(20);
7167 }
a2fbb9ea 7168
619c5cb6
VZ		 7169 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7170 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7171 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7172 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7173
34f80b04
EG		 7174 /* sync semi rtc */
7175 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7176 0x80000000);
7177 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7178 0x80000000);
a2fbb9ea 7179
619c5cb6
VZ		 7180 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7181 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7182 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7183
a3348722
BW		 7184 if (!CHIP_IS_E1x(bp)) {
7185 if (IS_MF_AFEX(bp)) {
7186 /* configure that VNTag and VLAN headers must be
7187 * sent in afex mode
7188 */
7189 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7190 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7191 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7192 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7193 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7194 } else {
7195 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7196 bp->path_has_ovlan ? 7 : 6);
7197 }
7198 }
f2e0899f 7199
34f80b04 7200 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7201
619c5cb6
VZ		 7202 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7203
55c11941
MS		 7204 if (CNIC_SUPPORT(bp)) {
7205 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7206 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7207 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7208 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7209 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7210 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7211 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7212 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7213 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7214 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7215 }
34f80b04 7216 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7217
34f80b04
EG		 7218 if (sizeof(union cdu_context) != 1024)
7219 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7220 dev_alert(&bp->pdev->dev,
7221 "please adjust the size of cdu_context(%ld)\n",
7222 (long)sizeof(union cdu_context));
a2fbb9ea 7223
619c5cb6 7224 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7225 val = (4 << 24) + (0 << 12) + 1024;
7226 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7227
619c5cb6 7228 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7229 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7230 /* enable context validation interrupt from CFC */
7231 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7232
7233 /* set the thresholds to prevent CFC/CDU race */
7234 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7235
619c5cb6 7236 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7237
619c5cb6 7238 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7239 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7240
619c5cb6
VZ		 7241 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7242 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7243
34f80b04
EG		 7244 /* Reset PCIE errors for debug */
7245 REG_WR(bp, 0x2814, 0xffffffff);
7246 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7247
619c5cb6 7248 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7249 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7250 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7251 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7252 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7253 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7254 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7255 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7256 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7257 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7258 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7259 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7260 }
7261
619c5cb6 7262 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7263 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7264 /* in E3 this done in per-port section */
7265 if (!CHIP_IS_E3(bp))
7266 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7267 }
619c5cb6
VZ		 7268 if (CHIP_IS_E1H(bp))
7269 /* not applicable for E2 (and above ...) */
7270 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7271
7272 if (CHIP_REV_IS_SLOW(bp))
7273 msleep(200);
7274
7275 /* finish CFC init */
7276 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7277 if (val != 1) {
7278 BNX2X_ERR("CFC LL_INIT failed\n");
7279 return -EBUSY;
7280 }
7281 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7282 if (val != 1) {
7283 BNX2X_ERR("CFC AC_INIT failed\n");
7284 return -EBUSY;
7285 }
7286 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7287 if (val != 1) {
7288 BNX2X_ERR("CFC CAM_INIT failed\n");
7289 return -EBUSY;
7290 }
7291 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7292
f2e0899f
DK		 7293 if (CHIP_IS_E1(bp)) {
7294 /* read NIG statistic
7295 to see if this is our first up since powerup */
7296 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7297 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7298
f2e0899f
DK		 7299 /* do internal memory self test */
7300 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7301 BNX2X_ERR("internal mem self test failed\n");
7302 return -EBUSY;
7303 }
34f80b04
EG		 7304 }
7305
fd4ef40d
EG		 7306 bnx2x_setup_fan_failure_detection(bp);
7307
34f80b04
EG		 7308 /* clear PXP2 attentions */
7309 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7310
4a33bc03 7311 bnx2x_enable_blocks_attention(bp);
c9ee9206 7312 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7313
6bbca910 7314 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7315 if (CHIP_IS_E1x(bp))
7316 bnx2x__common_init_phy(bp);
6bbca910
YR		 7317 } else
7318 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7319
34f80b04
EG		 7320 return 0;
7321}
a2fbb9ea 7322
619c5cb6
VZ		 7323/**
7324 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7325 *
7326 * @bp: driver handle
7327 */
7328static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7329{
7330 int rc = bnx2x_init_hw_common(bp);
7331
7332 if (rc)
7333 return rc;
7334
7335 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7336 if (!BP_NOMCP(bp))
7337 bnx2x__common_init_phy(bp);
7338
7339 return 0;
7340}
7341
523224a3 7342static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7343{
7344 int port = BP_PORT(bp);
619c5cb6 7345 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7346 u32 low, high;
4293b9f5 7347 u32 val, reg;
a2fbb9ea 7348
51c1a580 7349 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7350
7351 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7352
619c5cb6
VZ		 7353 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7354 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7355 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7356
f2e0899f
DK		 7357 /* Timers bug workaround: disables the pf_master bit in pglue at
7358 * common phase, we need to enable it here before any dmae access are
7359 * attempted. Therefore we manually added the enable-master to the
7360 * port phase (it also happens in the function phase)
7361 */
619c5cb6 7362 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7363 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7364
619c5cb6
VZ		 7365 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7366 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7367 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7368 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7369
7370 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7371 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7372 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7373 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7374
523224a3
DK		 7375 /* QM cid (connection) count */
7376 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7377
55c11941
MS		 7378 if (CNIC_SUPPORT(bp)) {
7379 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7380 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7381 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7382 }
cdaa7cb8 7383
619c5cb6 7384 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7385
2b674047
DK		 7386 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7387
f2e0899f 7388 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7389
7390 if (IS_MF(bp))
7391 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7392 else if (bp->dev->mtu > 4096) {
7393 if (bp->flags & ONE_PORT_FLAG)
7394 low = 160;
7395 else {
7396 val = bp->dev->mtu;
7397 /* (24*1024 + val*4)/256 */
7398 low = 96 + (val/64) +
7399 ((val % 64) ? 1 : 0);
7400 }
7401 } else
7402 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7403 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7404 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7405 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7406 }
1c06328c 7407
619c5cb6
VZ		 7408 if (CHIP_MODE_IS_4_PORT(bp))
7409 REG_WR(bp, (BP_PORT(bp) ?
7410 BRB1_REG_MAC_GUARANTIED_1 :
7411 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7412
619c5cb6 7413 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7414 if (CHIP_IS_E3B0(bp)) {
7415 if (IS_MF_AFEX(bp)) {
7416 /* configure headers for AFEX mode */
7417 REG_WR(bp, BP_PORT(bp) ?
7418 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7419 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7420 REG_WR(bp, BP_PORT(bp) ?
7421 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7422 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7423 REG_WR(bp, BP_PORT(bp) ?
7424 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7425 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7426 } else {
7427 /* Ovlan exists only if we are in multi-function +
7428 * switch-dependent mode, in switch-independent there
7429 * is no ovlan headers
7430 */
7431 REG_WR(bp, BP_PORT(bp) ?
7432 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7433 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7434 (bp->path_has_ovlan ? 7 : 6));
7435 }
7436 }
356e2385 7437
619c5cb6
VZ		 7438 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7439 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7440 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7441 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7442
619c5cb6
VZ		 7443 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7444 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7445 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7446 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7447
619c5cb6
VZ		 7448 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7449 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7450
619c5cb6
VZ		 7451 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7452
7453 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7454 /* configure PBF to work without PAUSE mtu 9000 */
7455 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7456
f2e0899f
DK		 7457 /* update threshold */
7458 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7459 /* update init credit */
7460 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7461
f2e0899f
DK		 7462 /* probe changes */
7463 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7464 udelay(50);
7465 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7466 }
a2fbb9ea 7467
55c11941
MS		 7468 if (CNIC_SUPPORT(bp))
7469 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7470
619c5cb6
VZ		 7471 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7472 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7473
7474 if (CHIP_IS_E1(bp)) {
7475 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7476 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7477 }
619c5cb6 7478 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7479
619c5cb6 7480 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7481
619c5cb6 7482 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7483 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7484 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7485 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7486 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7487 val = IS_MF(bp) ? 0xF7 : 0x7;
7488 /* Enable DCBX attention for all but E1 */
7489 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7490 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7491
4293b9f5
DK		 7492 /* SCPAD_PARITY should NOT trigger close the gates */
7493 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7494 REG_WR(bp, reg,
7495 REG_RD(bp, reg) &
7496 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7497
7498 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7499 REG_WR(bp, reg,
7500 REG_RD(bp, reg) &
7501 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7502
619c5cb6
VZ		 7503 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7504
7505 if (!CHIP_IS_E1x(bp)) {
7506 /* Bit-map indicating which L2 hdrs may appear after the
7507 * basic Ethernet header
7508 */
a3348722
BW		 7509 if (IS_MF_AFEX(bp))
7510 REG_WR(bp, BP_PORT(bp) ?
7511 NIG_REG_P1_HDRS_AFTER_BASIC :
7512 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7513 else
7514 REG_WR(bp, BP_PORT(bp) ?
7515 NIG_REG_P1_HDRS_AFTER_BASIC :
7516 NIG_REG_P0_HDRS_AFTER_BASIC,
7517 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7518
7519 if (CHIP_IS_E3(bp))
7520 REG_WR(bp, BP_PORT(bp) ?
7521 NIG_REG_LLH1_MF_MODE :
7522 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7523 }
7524 if (!CHIP_IS_E3(bp))
7525 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7526
f2e0899f 7527 if (!CHIP_IS_E1(bp)) {
fb3bff17 7528 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7529 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7530 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7531
619c5cb6 7532 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7533 val = 0;
7534 switch (bp->mf_mode) {
7535 case MULTI_FUNCTION_SD:
7536 val = 1;
7537 break;
7538 case MULTI_FUNCTION_SI:
a3348722 7539 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7540 val = 2;
7541 break;
7542 }
7543
7544 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7545 NIG_REG_LLH0_CLS_TYPE), val);
7546 }
1c06328c
EG		 7547 {
7548 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7549 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7550 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7551 }
34f80b04
EG		 7552 }
7553
619c5cb6
VZ		 7554 /* If SPIO5 is set to generate interrupts, enable it for this port */
7555 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7556 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7557 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7558 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7559 val = REG_RD(bp, reg_addr);
f1410647 7560 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7561 REG_WR(bp, reg_addr, val);
f1410647 7562 }
a2fbb9ea 7563
34f80b04
EG		 7564 return 0;
7565}
7566
34f80b04
EG		 7567static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7568{
7569 int reg;
32d68de1 7570 u32 wb_write[2];
34f80b04 7571
f2e0899f 7572 if (CHIP_IS_E1(bp))
34f80b04 7573 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7574 else
7575 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7576
32d68de1
YM		 7577 wb_write[0] = ONCHIP_ADDR1(addr);
7578 wb_write[1] = ONCHIP_ADDR2(addr);
7579 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7580}
7581
b56e9670 7582void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7583{
7584 u32 data, ctl, cnt = 100;
7585 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7586 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7587 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7588 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7589 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7590 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7591
7592 /* Not supported in BC mode */
7593 if (CHIP_INT_MODE_IS_BC(bp))
7594 return;
7595
7596 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7597 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7598 IGU_REGULAR_CLEANUP_SET |
7599 IGU_REGULAR_BCLEANUP;
7600
7601 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7602 func_encode << IGU_CTRL_REG_FID_SHIFT |
7603 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7604
7605 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7606 data, igu_addr_data);
7607 REG_WR(bp, igu_addr_data, data);
7608 mmiowb();
7609 barrier();
7610 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7611 ctl, igu_addr_ctl);
7612 REG_WR(bp, igu_addr_ctl, ctl);
7613 mmiowb();
7614 barrier();
7615
7616 /* wait for clean up to finish */
7617 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7618 msleep(20);
7619
1191cb83
ED		 7620 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7621 DP(NETIF_MSG_HW,
7622 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7623 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7624 }
7625}
7626
7627static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7628{
619c5cb6 7629 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7630}
7631
1191cb83 7632static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7633{
7634 u32 i, base = FUNC_ILT_BASE(func);
7635 for (i = base; i < base + ILT_PER_FUNC; i++)
7636 bnx2x_ilt_wr(bp, i, 0);
7637}
7638
910cc727 7639static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7640{
7641 int port = BP_PORT(bp);
7642 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7643 /* T1 hash bits value determines the T1 number of entries */
7644 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7645}
7646
7647static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7648{
7649 int rc;
7650 struct bnx2x_func_state_params func_params = {NULL};
7651 struct bnx2x_func_switch_update_params *switch_update_params =
7652 &func_params.params.switch_update;
7653
7654 /* Prepare parameters for function state transitions */
7655 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7656 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7657
7658 func_params.f_obj = &bp->func_obj;
7659 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7660
7661 /* Function parameters */
e42780b6
DK		 7662 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7663 &switch_update_params->changes);
7664 if (suspend)
7665 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7666 &switch_update_params->changes);
55c11941
MS		 7667
7668 rc = bnx2x_func_state_change(bp, &func_params);
7669
7670 return rc;
7671}
7672
910cc727 7673static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7674{
7675 int rc, i, port = BP_PORT(bp);
7676 int vlan_en = 0, mac_en[NUM_MACS];
7677
55c11941
MS		 7678 /* Close input from network */
7679 if (bp->mf_mode == SINGLE_FUNCTION) {
7680 bnx2x_set_rx_filter(&bp->link_params, 0);
7681 } else {
7682 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7683 NIG_REG_LLH0_FUNC_EN);
7684 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7685 NIG_REG_LLH0_FUNC_EN, 0);
7686 for (i = 0; i < NUM_MACS; i++) {
7687 mac_en[i] = REG_RD(bp, port ?
7688 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7689 4 * i) :
7690 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7691 4 * i));
7692 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7693 4 * i) :
7694 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7695 }
7696 }
7697
7698 /* Close BMC to host */
7699 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7700 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7701
7702 /* Suspend Tx switching to the PF. Completion of this ramrod
7703 * further guarantees that all the packets of that PF / child
7704 * VFs in BRB were processed by the Parser, so it is safe to
7705 * change the NIC_MODE register.
7706 */
7707 rc = bnx2x_func_switch_update(bp, 1);
7708 if (rc) {
7709 BNX2X_ERR("Can't suspend tx-switching!\n");
7710 return rc;
7711 }
7712
7713 /* Change NIC_MODE register */
7714 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7715
7716 /* Open input from network */
7717 if (bp->mf_mode == SINGLE_FUNCTION) {
7718 bnx2x_set_rx_filter(&bp->link_params, 1);
7719 } else {
7720 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7721 NIG_REG_LLH0_FUNC_EN, vlan_en);
7722 for (i = 0; i < NUM_MACS; i++) {
7723 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7724 4 * i) :
7725 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7726 mac_en[i]);
7727 }
7728 }
7729
7730 /* Enable BMC to host */
7731 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7732 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7733
7734 /* Resume Tx switching to the PF */
7735 rc = bnx2x_func_switch_update(bp, 0);
7736 if (rc) {
7737 BNX2X_ERR("Can't resume tx-switching!\n");
7738 return rc;
7739 }
7740
7741 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7742 return 0;
7743}
7744
7745int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7746{
7747 int rc;
7748
7749 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7750
7751 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7752 /* Configure searcher as part of function hw init */
55c11941
MS		 7753 bnx2x_init_searcher(bp);
7754
7755 /* Reset NIC mode */
7756 rc = bnx2x_reset_nic_mode(bp);
7757 if (rc)
7758 BNX2X_ERR("Can't change NIC mode!\n");
7759 return rc;
7760 }
7761
7762 return 0;
7763}
7764
523224a3 7765static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7766{
7767 int port = BP_PORT(bp);
7768 int func = BP_FUNC(bp);
619c5cb6 7769 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7770 struct bnx2x_ilt *ilt = BP_ILT(bp);
7771 u16 cdu_ilt_start;
8badd27a 7772 u32 addr, val;
f4a66897 7773 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7774 int i, main_mem_width, rc;
34f80b04 7775
51c1a580 7776 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7777
619c5cb6 7778 /* FLR cleanup - hmmm */
89db4ad8
AE		 7779 if (!CHIP_IS_E1x(bp)) {
7780 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7781 if (rc) {
7782 bnx2x_fw_dump(bp);
89db4ad8 7783 return rc;
04c46736 7784 }
89db4ad8 7785 }
619c5cb6 7786
8badd27a 7787 /* set MSI reconfigure capability */
f2e0899f
DK		 7788 if (bp->common.int_block == INT_BLOCK_HC) {
7789 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7790 val = REG_RD(bp, addr);
7791 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7792 REG_WR(bp, addr, val);
7793 }
8badd27a 7794
619c5cb6
VZ		 7795 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7796 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7797
523224a3
DK		 7798 ilt = BP_ILT(bp);
7799 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7800
290ca2bb
AE		 7801 if (IS_SRIOV(bp))
7802 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7803 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7804
7805 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7806 * those of the VFs, so start line should be reset
7807 */
7808 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7809 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7810 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7811 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7812 bp->context[i].cxt_mapping;
7813 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7814 }
290ca2bb 7815
523224a3 7816 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7817
55c11941
MS		 7818 if (!CONFIGURE_NIC_MODE(bp)) {
7819 bnx2x_init_searcher(bp);
7820 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7821 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7822 } else {
7823 /* Set NIC mode */
7824 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 7825 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 7826 }
37b091ba 7827
619c5cb6 7828 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7829 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7830
7831 /* Turn on a single ISR mode in IGU if driver is going to use
7832 * INT#x or MSI
7833 */
7834 if (!(bp->flags & USING_MSIX_FLAG))
7835 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7836 /*
7837 * Timers workaround bug: function init part.
7838 * Need to wait 20msec after initializing ILT,
7839 * needed to make sure there are no requests in
7840 * one of the PXP internal queues with "old" ILT addresses
7841 */
7842 msleep(20);
7843 /*
7844 * Master enable - Due to WB DMAE writes performed before this
7845 * register is re-initialized as part of the regular function
7846 * init
7847 */
7848 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7849 /* Enable the function in IGU */
7850 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7851 }
7852
523224a3 7853 bp->dmae_ready = 1;
34f80b04 7854
619c5cb6 7855 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 7856
619c5cb6 7857 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7858 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7859
619c5cb6
VZ		 7860 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7861 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7862 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7863 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7864 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7865 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7866 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7867 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7868 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7869 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7870 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7871 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7872 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7873
7874 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7875 REG_WR(bp, QM_REG_PF_EN, 1);
7876
619c5cb6
VZ		 7877 if (!CHIP_IS_E1x(bp)) {
7878 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7879 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7880 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7881 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7882 }
7883 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7884
7885 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7886 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 7887 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 7888
7889 bnx2x_iov_init_dq(bp);
7890
619c5cb6
VZ		 7891 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7892 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7893 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7894 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7895 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7896 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7897 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7898 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7899 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7900 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7901 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7902
619c5cb6 7903 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 7904
619c5cb6 7905 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 7906
619c5cb6 7907 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7908 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7909
fb3bff17 7910 if (IS_MF(bp)) {
34f80b04 7911 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 7912 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 7913 }
7914
619c5cb6 7915 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 7916
34f80b04 7917 /* HC init per function */
f2e0899f
DK		 7918 if (bp->common.int_block == INT_BLOCK_HC) {
7919 if (CHIP_IS_E1H(bp)) {
7920 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7921
7922 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7923 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7924 }
619c5cb6 7925 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 7926
7927 } else {
7928 int num_segs, sb_idx, prod_offset;
7929
34f80b04
EG		 7930 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7931
619c5cb6 7932 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7933 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7934 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7935 }
7936
619c5cb6 7937 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7938
619c5cb6 7939 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7940 int dsb_idx = 0;
7941 /**
7942 * Producer memory:
7943 * E2 mode: address 0-135 match to the mapping memory;
7944 * 136 - PF0 default prod; 137 - PF1 default prod;
7945 * 138 - PF2 default prod; 139 - PF3 default prod;
7946 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7947 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7948 * 144-147 reserved.
7949 *
7950 * E1.5 mode - In backward compatible mode;
7951 * for non default SB; each even line in the memory
7952 * holds the U producer and each odd line hold
7953 * the C producer. The first 128 producers are for
7954 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7955 * producers are for the DSB for each PF.
7956 * Each PF has five segments: (the order inside each
7957 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7958 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7959 * 144-147 attn prods;
7960 */
7961 /* non-default-status-blocks */
7962 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7963 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7964 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7965 prod_offset = (bp->igu_base_sb + sb_idx) *
7966 num_segs;
7967
7968 for (i = 0; i < num_segs; i++) {
7969 addr = IGU_REG_PROD_CONS_MEMORY +
7970 (prod_offset + i) * 4;
7971 REG_WR(bp, addr, 0);
7972 }
7973 /* send consumer update with value 0 */
7974 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7975 USTORM_ID, 0, IGU_INT_NOP, 1);
7976 bnx2x_igu_clear_sb(bp,
7977 bp->igu_base_sb + sb_idx);
7978 }
7979
7980 /* default-status-blocks */
7981 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7982 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7983
7984 if (CHIP_MODE_IS_4_PORT(bp))
7985 dsb_idx = BP_FUNC(bp);
7986 else
3395a033 7987 dsb_idx = BP_VN(bp);
f2e0899f
DK		 7988
7989 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7990 IGU_BC_BASE_DSB_PROD + dsb_idx :
7991 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7992
3395a033
DK		 7993 /*
7994 * igu prods come in chunks of E1HVN_MAX (4) -
7995 * does not matters what is the current chip mode
7996 */
f2e0899f
DK		 7997 for (i = 0; i < (num_segs * E1HVN_MAX);
7998 i += E1HVN_MAX) {
7999 addr = IGU_REG_PROD_CONS_MEMORY +
8000 (prod_offset + i)*4;
8001 REG_WR(bp, addr, 0);
8002 }
8003 /* send consumer update with 0 */
8004 if (CHIP_INT_MODE_IS_BC(bp)) {
8005 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8006 USTORM_ID, 0, IGU_INT_NOP, 1);
8007 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8008 CSTORM_ID, 0, IGU_INT_NOP, 1);
8009 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8010 XSTORM_ID, 0, IGU_INT_NOP, 1);
8011 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8012 TSTORM_ID, 0, IGU_INT_NOP, 1);
8013 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8014 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8015 } else {
8016 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8017 USTORM_ID, 0, IGU_INT_NOP, 1);
8018 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8019 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8020 }
8021 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8022
16a5fd92 8023 /* !!! These should become driver const once
f2e0899f
DK		 8024 rf-tool supports split-68 const */
8025 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8026 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8027 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8028 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8029 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8030 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8031 }
34f80b04 8032 }
34f80b04 8033
c14423fe 8034 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 8035 REG_WR(bp, 0x2114, 0xffffffff);
8036 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 8037
f4a66897
VZ		 8038 if (CHIP_IS_E1x(bp)) {
8039 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8040 main_mem_base = HC_REG_MAIN_MEMORY +
8041 BP_PORT(bp) * (main_mem_size * 4);
8042 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8043 main_mem_width = 8;
8044
8045 val = REG_RD(bp, main_mem_prty_clr);
8046 if (val)
51c1a580
MS		 8047 DP(NETIF_MSG_HW,
8048 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8049 val);
f4a66897
VZ		 8050
8051 /* Clear "false" parity errors in MSI-X table */
8052 for (i = main_mem_base;
8053 i < main_mem_base + main_mem_size * 4;
8054 i += main_mem_width) {
8055 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8056 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8057 i, main_mem_width / 4);
8058 }
8059 /* Clear HC parity attention */
8060 REG_RD(bp, main_mem_prty_clr);
8061 }
8062
619c5cb6
VZ		 8063#ifdef BNX2X_STOP_ON_ERROR
8064 /* Enable STORMs SP logging */
8065 REG_WR8(bp, BAR_USTRORM_INTMEM +
8066 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8067 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8068 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8069 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8070 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8071 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8072 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8073#endif
8074
b7737c9b 8075 bnx2x_phy_probe(&bp->link_params);
f85582f8 8076
34f80b04
EG		 8077 return 0;
8078}
8079
55c11941
MS		 8080void bnx2x_free_mem_cnic(struct bnx2x *bp)
8081{
8082 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8083
8084 if (!CHIP_IS_E1x(bp))
8085 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8086 sizeof(struct host_hc_status_block_e2));
8087 else
8088 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8089 sizeof(struct host_hc_status_block_e1x));
8090
8091 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8092}
8093
9f6c9258 8094void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 8095{
a052997e
MS		 8096 int i;
8097
619c5cb6
VZ		 8098 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8099 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8100
b4cddbd6
AE		 8101 if (IS_VF(bp))
8102 return;
8103
8104 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8105 sizeof(struct host_sp_status_block));
8106
a2fbb9ea 8107 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 8108 sizeof(struct bnx2x_slowpath));
a2fbb9ea 8109
a052997e
MS		 8110 for (i = 0; i < L2_ILT_LINES(bp); i++)
8111 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8112 bp->context[i].size);
523224a3
DK		 8113 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8114
8115 BNX2X_FREE(bp->ilt->lines);
f85582f8 8116
7a9b2557 8117 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 8118
523224a3
DK		 8119 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8120 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 8121
05952246
YM		 8122 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8123
580d9d08 8124 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8125}
8126
55c11941 8127int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8128{
cd2b0389 8129 if (!CHIP_IS_E1x(bp)) {
619c5cb6 8130 /* size = the status block + ramrod buffers */
cd2b0389
JP		 8131 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8132 sizeof(struct host_hc_status_block_e2));
8133 if (!bp->cnic_sb.e2_sb)
8134 goto alloc_mem_err;
8135 } else {
8136 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8137 sizeof(struct host_hc_status_block_e1x));
8138 if (!bp->cnic_sb.e1x_sb)
8139 goto alloc_mem_err;
8140 }
8badd27a 8141
cd2b0389 8142 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
16a5fd92 8143 /* allocate searcher T2 table, as it wasn't allocated before */
cd2b0389
JP		 8144 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8145 if (!bp->t2)
8146 goto alloc_mem_err;
8147 }
55c11941
MS		 8148
8149 /* write address to which L5 should insert its values */
8150 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8151 &bp->slowpath->drv_info_to_mcp;
8152
8153 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8154 goto alloc_mem_err;
8155
8156 return 0;
8157
8158alloc_mem_err:
8159 bnx2x_free_mem_cnic(bp);
8160 BNX2X_ERR("Can't allocate memory\n");
8161 return -ENOMEM;
8162}
8163
8164int bnx2x_alloc_mem(struct bnx2x *bp)
8165{
8166 int i, allocated, context_size;
a2fbb9ea 8167
cd2b0389 8168 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
55c11941 8169 /* allocate searcher T2 table */
cd2b0389
JP		 8170 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8171 if (!bp->t2)
8172 goto alloc_mem_err;
8173 }
8badd27a 8174
cd2b0389
JP		 8175 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8176 sizeof(struct host_sp_status_block));
8177 if (!bp->def_status_blk)
8178 goto alloc_mem_err;
a2fbb9ea 8179
cd2b0389
JP		 8180 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8181 sizeof(struct bnx2x_slowpath));
8182 if (!bp->slowpath)
8183 goto alloc_mem_err;
a2fbb9ea 8184
a052997e
MS		 8185 /* Allocate memory for CDU context:
8186 * This memory is allocated separately and not in the generic ILT
8187 * functions because CDU differs in few aspects:
8188 * 1. There are multiple entities allocating memory for context -
8189 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8190 * its own ILT lines.
8191 * 2. Since CDU page-size is not a single 4KB page (which is the case
8192 * for the other ILT clients), to be efficient we want to support
8193 * allocation of sub-page-size in the last entry.
8194 * 3. Context pointers are used by the driver to pass to FW / update
8195 * the context (for the other ILT clients the pointers are used just to
8196 * free the memory during unload).
8197 */
8198 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8199
a052997e
MS		 8200 for (i = 0, allocated = 0; allocated < context_size; i++) {
8201 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8202 (context_size - allocated));
cd2b0389
JP		 8203 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8204 bp->context[i].size);
8205 if (!bp->context[i].vcxt)
8206 goto alloc_mem_err;
a052997e
MS		 8207 allocated += bp->context[i].size;
8208 }
cd2b0389
JP		 8209 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8210 GFP_KERNEL);
8211 if (!bp->ilt->lines)
8212 goto alloc_mem_err;
65abd74d 8213
523224a3
DK		 8214 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8215 goto alloc_mem_err;
65abd74d 8216
67c431a5
AE		 8217 if (bnx2x_iov_alloc_mem(bp))
8218 goto alloc_mem_err;
8219
9f6c9258 8220 /* Slow path ring */
cd2b0389
JP		 8221 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8222 if (!bp->spq)
8223 goto alloc_mem_err;
65abd74d 8224
523224a3 8225 /* EQ */
cd2b0389
JP		 8226 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8227 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8228 if (!bp->eq_ring)
8229 goto alloc_mem_err;
ab532cf3 8230
9f6c9258 8231 return 0;
e1510706 8232
9f6c9258
DK		 8233alloc_mem_err:
8234 bnx2x_free_mem(bp);
51c1a580 8235 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8236 return -ENOMEM;
65abd74d
YG		 8237}
8238
a2fbb9ea
ET		 8239/*
8240 * Init service functions
8241 */
a2fbb9ea 8242
619c5cb6
VZ		 8243int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8244 struct bnx2x_vlan_mac_obj *obj, bool set,
8245 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8246{
619c5cb6
VZ		 8247 int rc;
8248 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8249
619c5cb6 8250 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8251
619c5cb6
VZ		 8252 /* Fill general parameters */
8253 ramrod_param.vlan_mac_obj = obj;
8254 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8255
619c5cb6
VZ		 8256 /* Fill a user request section if needed */
8257 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8258 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8259
619c5cb6 8260 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8261
619c5cb6
VZ		 8262 /* Set the command: ADD or DEL */
8263 if (set)
8264 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8265 else
8266 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8267 }
8268
619c5cb6 8269 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8270
8271 if (rc == -EEXIST) {
8272 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8273 /* do not treat adding same MAC as error */
8274 rc = 0;
8275 } else if (rc < 0)
619c5cb6 8276 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8277
619c5cb6 8278 return rc;
a2fbb9ea
ET		 8279}
8280
619c5cb6
VZ		 8281int bnx2x_del_all_macs(struct bnx2x *bp,
8282 struct bnx2x_vlan_mac_obj *mac_obj,
8283 int mac_type, bool wait_for_comp)
e665bfda 8284{
619c5cb6
VZ		 8285 int rc;
8286 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8287
619c5cb6
VZ		 8288 /* Wait for completion of requested */
8289 if (wait_for_comp)
8290 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8291
619c5cb6
VZ		 8292 /* Set the mac type of addresses we want to clear */
8293 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8294
619c5cb6
VZ		 8295 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8296 if (rc < 0)
8297 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8298
619c5cb6 8299 return rc;
0793f83f
DK		 8300}
8301
619c5cb6 8302int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8303{
a3348722
BW		 8304 if (is_zero_ether_addr(bp->dev->dev_addr) &&
8305 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
51c1a580
MS		 8306 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8307 "Ignoring Zero MAC for STORAGE SD mode\n");
614c76df
DK		 8308 return 0;
8309 }
614c76df 8310
f8f4f61a
DK		 8311 if (IS_PF(bp)) {
8312 unsigned long ramrod_flags = 0;
0793f83f 8313
f8f4f61a
DK		 8314 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8315 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8316 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8317 &bp->sp_objs->mac_obj, set,
8318 BNX2X_ETH_MAC, &ramrod_flags);
8319 } else { /* vf */
8320 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8321 bp->fp->index, true);
8322 }
e665bfda 8323}
6e30dd4e 8324
619c5cb6 8325int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8326{
60cad4e6
AE		 8327 if (IS_PF(bp))
8328 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8329 else /* VF */
8330 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8331}
a2fbb9ea 8332
d6214d7a 8333/**
e8920674 8334 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8335 *
e8920674 8336 * @bp: driver handle
d6214d7a 8337 *
e8920674 8338 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8339 */
1ab4434c 8340int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8341{
1ab4434c
AE		 8342 int rc = 0;
8343
60cad4e6
AE		 8344 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8345 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8346 return -EINVAL;
60cad4e6 8347 }
1ab4434c 8348
9ee3d37b 8349 switch (int_mode) {
1ab4434c
AE		 8350 case BNX2X_INT_MODE_MSIX:
8351 /* attempt to enable msix */
8352 rc = bnx2x_enable_msix(bp);
8353
8354 /* msix attained */
8355 if (!rc)
8356 return 0;
8357
8358 /* vfs use only msix */
8359 if (rc && IS_VF(bp))
8360 return rc;
8361
8362 /* failed to enable multiple MSI-X */
8363 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8364 bp->num_queues,
8365 1 + bp->num_cnic_queues);
8366
8367 /* falling through... */
8368 case BNX2X_INT_MODE_MSI:
d6214d7a 8369 bnx2x_enable_msi(bp);
1ab4434c 8370
d6214d7a 8371 /* falling through... */
1ab4434c 8372 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8373 bp->num_ethernet_queues = 1;
8374 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8375 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8376 break;
d6214d7a 8377 default:
1ab4434c
AE		 8378 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8379 return -EINVAL;
9f6c9258 8380 }
1ab4434c 8381 return 0;
a2fbb9ea
ET		 8382}
8383
1ab4434c 8384/* must be called prior to any HW initializations */
c2bff63f
DK		 8385static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8386{
290ca2bb
AE		 8387 if (IS_SRIOV(bp))
8388 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8389 return L2_ILT_LINES(bp);
8390}
8391
523224a3
DK		 8392void bnx2x_ilt_set_info(struct bnx2x *bp)
8393{
8394 struct ilt_client_info *ilt_client;
8395 struct bnx2x_ilt *ilt = BP_ILT(bp);
8396 u16 line = 0;
8397
8398 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8399 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8400
8401 /* CDU */
8402 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8403 ilt_client->client_num = ILT_CLIENT_CDU;
8404 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8405 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8406 ilt_client->start = line;
619c5cb6 8407 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8408
8409 if (CNIC_SUPPORT(bp))
8410 line += CNIC_ILT_LINES;
523224a3
DK		 8411 ilt_client->end = line - 1;
8412
51c1a580 8413 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8414 ilt_client->start,
8415 ilt_client->end,
8416 ilt_client->page_size,
8417 ilt_client->flags,
8418 ilog2(ilt_client->page_size >> 12));
8419
8420 /* QM */
8421 if (QM_INIT(bp->qm_cid_count)) {
8422 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8423 ilt_client->client_num = ILT_CLIENT_QM;
8424 ilt_client->page_size = QM_ILT_PAGE_SZ;
8425 ilt_client->flags = 0;
8426 ilt_client->start = line;
8427
8428 /* 4 bytes for each cid */
8429 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8430 QM_ILT_PAGE_SZ);
8431
8432 ilt_client->end = line - 1;
8433
51c1a580
MS		 8434 DP(NETIF_MSG_IFUP,
8435 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8436 ilt_client->start,
8437 ilt_client->end,
8438 ilt_client->page_size,
8439 ilt_client->flags,
8440 ilog2(ilt_client->page_size >> 12));
523224a3 8441 }
523224a3 8442
55c11941
MS		 8443 if (CNIC_SUPPORT(bp)) {
8444 /* SRC */
8445 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8446 ilt_client->client_num = ILT_CLIENT_SRC;
8447 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8448 ilt_client->flags = 0;
8449 ilt_client->start = line;
8450 line += SRC_ILT_LINES;
8451 ilt_client->end = line - 1;
523224a3 8452
55c11941
MS		 8453 DP(NETIF_MSG_IFUP,
8454 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8455 ilt_client->start,
8456 ilt_client->end,
8457 ilt_client->page_size,
8458 ilt_client->flags,
8459 ilog2(ilt_client->page_size >> 12));
9f6c9258 8460
55c11941
MS		 8461 /* TM */
8462 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8463 ilt_client->client_num = ILT_CLIENT_TM;
8464 ilt_client->page_size = TM_ILT_PAGE_SZ;
8465 ilt_client->flags = 0;
8466 ilt_client->start = line;
8467 line += TM_ILT_LINES;
8468 ilt_client->end = line - 1;
523224a3 8469
55c11941
MS		 8470 DP(NETIF_MSG_IFUP,
8471 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8472 ilt_client->start,
8473 ilt_client->end,
8474 ilt_client->page_size,
8475 ilt_client->flags,
8476 ilog2(ilt_client->page_size >> 12));
8477 }
9f6c9258 8478
619c5cb6 8479 BUG_ON(line > ILT_MAX_LINES);
523224a3 8480}
f85582f8 8481
619c5cb6
VZ		 8482/**
8483 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8484 *
8485 * @bp: driver handle
8486 * @fp: pointer to fastpath
8487 * @init_params: pointer to parameters structure
8488 *
8489 * parameters configured:
8490 * - HC configuration
8491 * - Queue's CDU context
8492 */
1191cb83 8493static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8494 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8495{
6383c0b3 8496 u8 cos;
a052997e
MS		 8497 int cxt_index, cxt_offset;
8498
619c5cb6
VZ		 8499 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8500 if (!IS_FCOE_FP(fp)) {
8501 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8502 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8503
16a5fd92 8504 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8505 * to INIT state.
8506 */
8507 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8508 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8509
8510 /* HC rate */
8511 init_params->rx.hc_rate = bp->rx_ticks ?
8512 (1000000 / bp->rx_ticks) : 0;
8513 init_params->tx.hc_rate = bp->tx_ticks ?
8514 (1000000 / bp->tx_ticks) : 0;
8515
8516 /* FW SB ID */
8517 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8518 fp->fw_sb_id;
8519
8520 /*
8521 * CQ index among the SB indices: FCoE clients uses the default
8522 * SB, therefore it's different.
8523 */
6383c0b3
AE		 8524 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8525 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8526 }
8527
6383c0b3
AE		 8528 /* set maximum number of COSs supported by this queue */
8529 init_params->max_cos = fp->max_cos;
8530
51c1a580 8531 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8532 fp->index, init_params->max_cos);
8533
8534 /* set the context pointers queue object */
a052997e 8535 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8536 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8537 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8538 ILT_PAGE_CIDS);
6383c0b3 8539 init_params->cxts[cos] =
a052997e
MS		 8540 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8541 }
619c5cb6
VZ		 8542}
8543
910cc727 8544static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8545 struct bnx2x_queue_state_params *q_params,
8546 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8547 int tx_index, bool leading)
8548{
8549 memset(tx_only_params, 0, sizeof(*tx_only_params));
8550
8551 /* Set the command */
8552 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8553
8554 /* Set tx-only QUEUE flags: don't zero statistics */
8555 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8556
8557 /* choose the index of the cid to send the slow path on */
8558 tx_only_params->cid_index = tx_index;
8559
8560 /* Set general TX_ONLY_SETUP parameters */
8561 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8562
8563 /* Set Tx TX_ONLY_SETUP parameters */
8564 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8565
51c1a580
MS		 8566 DP(NETIF_MSG_IFUP,
8567 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8568 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8569 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8570 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8571
8572 /* send the ramrod */
8573 return bnx2x_queue_state_change(bp, q_params);
8574}
8575
619c5cb6
VZ		 8576/**
8577 * bnx2x_setup_queue - setup queue
8578 *
8579 * @bp: driver handle
8580 * @fp: pointer to fastpath
8581 * @leading: is leading
8582 *
8583 * This function performs 2 steps in a Queue state machine
8584 * actually: 1) RESET->INIT 2) INIT->SETUP
8585 */
8586
8587int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8588 bool leading)
8589{
3b603066 8590 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8591 struct bnx2x_queue_setup_params *setup_params =
8592 &q_params.params.setup;
6383c0b3
AE		 8593 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8594 &q_params.params.tx_only;
a2fbb9ea 8595 int rc;
6383c0b3
AE		 8596 u8 tx_index;
8597
51c1a580 8598 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8599
ec6ba945
VZ		 8600 /* reset IGU state skip FCoE L2 queue */
8601 if (!IS_FCOE_FP(fp))
8602 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8603 IGU_INT_ENABLE, 0);
a2fbb9ea 8604
15192a8c 8605 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8606 /* We want to wait for completion in this context */
8607 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8608
619c5cb6
VZ		 8609 /* Prepare the INIT parameters */
8610 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8611
619c5cb6
VZ		 8612 /* Set the command */
8613 q_params.cmd = BNX2X_Q_CMD_INIT;
8614
8615 /* Change the state to INIT */
8616 rc = bnx2x_queue_state_change(bp, &q_params);
8617 if (rc) {
6383c0b3 8618 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8619 return rc;
8620 }
ec6ba945 8621
51c1a580 8622 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8623
619c5cb6
VZ		 8624 /* Now move the Queue to the SETUP state... */
8625 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8626
619c5cb6
VZ		 8627 /* Set QUEUE flags */
8628 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8629
619c5cb6 8630 /* Set general SETUP parameters */
6383c0b3
AE		 8631 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8632 FIRST_TX_COS_INDEX);
619c5cb6 8633
6383c0b3 8634 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8635 &setup_params->rxq_params);
8636
6383c0b3
AE		 8637 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8638 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8639
8640 /* Set the command */
8641 q_params.cmd = BNX2X_Q_CMD_SETUP;
8642
55c11941
MS		 8643 if (IS_FCOE_FP(fp))
8644 bp->fcoe_init = true;
8645
619c5cb6
VZ		 8646 /* Change the state to SETUP */
8647 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8648 if (rc) {
8649 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8650 return rc;
8651 }
8652
8653 /* loop through the relevant tx-only indices */
8654 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8655 tx_index < fp->max_cos;
8656 tx_index++) {
8657
8658 /* prepare and send tx-only ramrod*/
8659 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8660 tx_only_params, tx_index, leading);
8661 if (rc) {
8662 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8663 fp->index, tx_index);
8664 return rc;
8665 }
8666 }
523224a3 8667
34f80b04 8668 return rc;
a2fbb9ea
ET		 8669}
8670
619c5cb6 8671static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8672{
619c5cb6 8673 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8674 struct bnx2x_fp_txdata *txdata;
3b603066 8675 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8676 int rc, tx_index;
8677
51c1a580 8678 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8679
15192a8c 8680 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8681 /* We want to wait for completion in this context */
8682 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8683
6383c0b3
AE		 8684 /* close tx-only connections */
8685 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8686 tx_index < fp->max_cos;
8687 tx_index++){
8688
8689 /* ascertain this is a normal queue*/
65565884 8690 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8691
51c1a580 8692 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8693 txdata->txq_index);
8694
8695 /* send halt terminate on tx-only connection */
8696 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8697 memset(&q_params.params.terminate, 0,
8698 sizeof(q_params.params.terminate));
8699 q_params.params.terminate.cid_index = tx_index;
8700
8701 rc = bnx2x_queue_state_change(bp, &q_params);
8702 if (rc)
8703 return rc;
8704
8705 /* send halt terminate on tx-only connection */
8706 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8707 memset(&q_params.params.cfc_del, 0,
8708 sizeof(q_params.params.cfc_del));
8709 q_params.params.cfc_del.cid_index = tx_index;
8710 rc = bnx2x_queue_state_change(bp, &q_params);
8711 if (rc)
8712 return rc;
8713 }
8714 /* Stop the primary connection: */
8715 /* ...halt the connection */
619c5cb6
VZ		 8716 q_params.cmd = BNX2X_Q_CMD_HALT;
8717 rc = bnx2x_queue_state_change(bp, &q_params);
8718 if (rc)
da5a662a 8719 return rc;
a2fbb9ea 8720
6383c0b3 8721 /* ...terminate the connection */
619c5cb6 8722 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8723 memset(&q_params.params.terminate, 0,
8724 sizeof(q_params.params.terminate));
8725 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8726 rc = bnx2x_queue_state_change(bp, &q_params);
8727 if (rc)
523224a3 8728 return rc;
6383c0b3 8729 /* ...delete cfc entry */
619c5cb6 8730 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8731 memset(&q_params.params.cfc_del, 0,
8732 sizeof(q_params.params.cfc_del));
8733 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8734 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8735}
8736
34f80b04
EG		 8737static void bnx2x_reset_func(struct bnx2x *bp)
8738{
8739 int port = BP_PORT(bp);
8740 int func = BP_FUNC(bp);
f2e0899f 8741 int i;
523224a3
DK		 8742
8743 /* Disable the function in the FW */
8744 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8745 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8746 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8747 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8748
8749 /* FP SBs */
ec6ba945 8750 for_each_eth_queue(bp, i) {
523224a3 8751 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8752 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8753 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8754 SB_DISABLED);
523224a3
DK		 8755 }
8756
55c11941
MS		 8757 if (CNIC_LOADED(bp))
8758 /* CNIC SB */
8759 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8760 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8761 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8762
523224a3 8763 /* SP SB */
619c5cb6 8764 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8765 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8766 SB_DISABLED);
523224a3
DK		 8767
8768 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8769 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8770 0);
34f80b04
EG		 8771
8772 /* Configure IGU */
f2e0899f
DK		 8773 if (bp->common.int_block == INT_BLOCK_HC) {
8774 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8775 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8776 } else {
8777 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8778 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8779 }
34f80b04 8780
55c11941
MS		 8781 if (CNIC_LOADED(bp)) {
8782 /* Disable Timer scan */
8783 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8784 /*
8785 * Wait for at least 10ms and up to 2 second for the timers
8786 * scan to complete
8787 */
8788 for (i = 0; i < 200; i++) {
639d65b8 8789 usleep_range(10000, 20000);
55c11941
MS		 8790 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8791 break;
8792 }
37b091ba 8793 }
34f80b04 8794 /* Clear ILT */
f2e0899f
DK		 8795 bnx2x_clear_func_ilt(bp, func);
8796
8797 /* Timers workaround bug for E2: if this is vnic-3,
8798 * we need to set the entire ilt range for this timers.
8799 */
619c5cb6 8800 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8801 struct ilt_client_info ilt_cli;
8802 /* use dummy TM client */
8803 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8804 ilt_cli.start = 0;
8805 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8806 ilt_cli.client_num = ILT_CLIENT_TM;
8807
8808 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8809 }
8810
8811 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 8812 if (!CHIP_IS_E1x(bp))
f2e0899f 8813 bnx2x_pf_disable(bp);
523224a3
DK		 8814
8815 bp->dmae_ready = 0;
34f80b04
EG		 8816}
8817
8818static void bnx2x_reset_port(struct bnx2x *bp)
8819{
8820 int port = BP_PORT(bp);
8821 u32 val;
8822
619c5cb6
VZ		 8823 /* Reset physical Link */
8824 bnx2x__link_reset(bp);
8825
34f80b04
EG		 8826 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8827
8828 /* Do not rcv packets to BRB */
8829 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8830 /* Do not direct rcv packets that are not for MCP to the BRB */
8831 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8832 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8833
8834 /* Configure AEU */
8835 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8836
8837 msleep(100);
8838 /* Check for BRB port occupancy */
8839 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8840 if (val)
8841 DP(NETIF_MSG_IFDOWN,
33471629 8842 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 8843
8844 /* TODO: Close Doorbell port? */
8845}
8846
1191cb83 8847static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 8848{
3b603066 8849 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 8850
619c5cb6
VZ		 8851 /* Prepare parameters for function state transitions */
8852 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 8853
619c5cb6
VZ		 8854 func_params.f_obj = &bp->func_obj;
8855 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 8856
619c5cb6 8857 func_params.params.hw_init.load_phase = load_code;
49d66772 8858
619c5cb6 8859 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 8860}
8861
1191cb83 8862static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 8863{
3b603066 8864 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 8865 int rc;
228241eb 8866
619c5cb6
VZ		 8867 /* Prepare parameters for function state transitions */
8868 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8869 func_params.f_obj = &bp->func_obj;
8870 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 8871
619c5cb6
VZ		 8872 /*
8873 * Try to stop the function the 'good way'. If fails (in case
8874 * of a parity error during bnx2x_chip_cleanup()) and we are
8875 * not in a debug mode, perform a state transaction in order to
8876 * enable further HW_RESET transaction.
8877 */
8878 rc = bnx2x_func_state_change(bp, &func_params);
8879 if (rc) {
34f80b04 8880#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 8881 return rc;
34f80b04 8882#else
51c1a580 8883 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 8884 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8885 return bnx2x_func_state_change(bp, &func_params);
34f80b04 8886#endif
228241eb 8887 }
a2fbb9ea 8888
619c5cb6
VZ		 8889 return 0;
8890}
523224a3 8891
619c5cb6
VZ		 8892/**
8893 * bnx2x_send_unload_req - request unload mode from the MCP.
8894 *
8895 * @bp: driver handle
8896 * @unload_mode: requested function's unload mode
8897 *
8898 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8899 */
8900u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8901{
8902 u32 reset_code = 0;
8903 int port = BP_PORT(bp);
3101c2bc 8904
619c5cb6 8905 /* Select the UNLOAD request mode */
65abd74d
YG		 8906 if (unload_mode == UNLOAD_NORMAL)
8907 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8908
7d0446c2 8909 else if (bp->flags & NO_WOL_FLAG)
65abd74d 8910 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 8911
7d0446c2 8912 else if (bp->wol) {
65abd74d
YG		 8913 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8914 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 8915 struct pci_dev *pdev = bp->pdev;
65abd74d 8916 u32 val;
f9977903
DK		 8917 u16 pmc;
8918
65abd74d 8919 /* The mac address is written to entries 1-4 to
f9977903
DK		 8920 * preserve entry 0 which is used by the PMF
8921 */
3395a033 8922 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 8923
8924 val = (mac_addr[0] << 8) | mac_addr[1];
8925 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8926
8927 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8928 (mac_addr[4] << 8) | mac_addr[5];
8929 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8930
f9977903 8931 /* Enable the PME and clear the status */
29ed74c3 8932 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 8933 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 8934 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 8935
65abd74d
YG		 8936 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8937
8938 } else
8939 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 8940
619c5cb6
VZ		 8941 /* Send the request to the MCP */
8942 if (!BP_NOMCP(bp))
8943 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8944 else {
8945 int path = BP_PATH(bp);
8946
51c1a580 8947 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 8948 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8949 bnx2x_load_count[path][2]);
8950 bnx2x_load_count[path][0]--;
8951 bnx2x_load_count[path][1 + port]--;
51c1a580 8952 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 8953 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8954 bnx2x_load_count[path][2]);
8955 if (bnx2x_load_count[path][0] == 0)
619c5cb6 8956 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 8957 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 8958 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8959 else
8960 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8961 }
8962
8963 return reset_code;
8964}
8965
8966/**
8967 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8968 *
8969 * @bp: driver handle
5d07d868 8970 * @keep_link: true iff link should be kept up
619c5cb6 8971 */
5d07d868 8972void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 8973{
5d07d868
YM		 8974 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8975
619c5cb6
VZ		 8976 /* Report UNLOAD_DONE to MCP */
8977 if (!BP_NOMCP(bp))
5d07d868 8978 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 8979}
8980
1191cb83 8981static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 8982{
8983 int tout = 50;
8984 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8985
8986 if (!bp->port.pmf)
8987 return 0;
8988
8989 /*
8990 * (assumption: No Attention from MCP at this stage)
16a5fd92 8991 * PMF probably in the middle of TX disable/enable transaction
6debea87 8992 * 1. Sync IRS for default SB
16a5fd92
YM		 8993 * 2. Sync SP queue - this guarantees us that attention handling started
8994 * 3. Wait, that TX disable/enable transaction completes
6debea87 8995 *
16a5fd92
YM		 8996 * 1+2 guarantee that if DCBx attention was scheduled it already changed
8997 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8998 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 8999 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9000 * transaction.
9001 */
9002
9003 /* make sure default SB ISR is done */
9004 if (msix)
9005 synchronize_irq(bp->msix_table[0].vector);
9006 else
9007 synchronize_irq(bp->pdev->irq);
9008
9009 flush_workqueue(bnx2x_wq);
370d4a26 9010 flush_workqueue(bnx2x_iov_wq);
6debea87
DK		 9011
9012 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9013 BNX2X_F_STATE_STARTED && tout--)
9014 msleep(20);
9015
9016 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9017 BNX2X_F_STATE_STARTED) {
9018#ifdef BNX2X_STOP_ON_ERROR
51c1a580 9019 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 9020 return -EBUSY;
9021#else
9022 /*
9023 * Failed to complete the transaction in a "good way"
9024 * Force both transactions with CLR bit
9025 */
3b603066 9026 struct bnx2x_func_state_params func_params = {NULL};
6debea87 9027
51c1a580 9028 DP(NETIF_MSG_IFDOWN,
6bf07b8e 9029 "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
6debea87
DK		 9030
9031 func_params.f_obj = &bp->func_obj;
9032 __set_bit(RAMROD_DRV_CLR_ONLY,
9033 &func_params.ramrod_flags);
9034
9035 /* STARTED-->TX_ST0PPED */
9036 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9037 bnx2x_func_state_change(bp, &func_params);
9038
9039 /* TX_ST0PPED-->STARTED */
9040 func_params.cmd = BNX2X_F_CMD_TX_START;
9041 return bnx2x_func_state_change(bp, &func_params);
9042#endif
9043 }
9044
9045 return 0;
9046}
9047
eeed018c
MK		 9048static void bnx2x_disable_ptp(struct bnx2x *bp)
9049{
9050 int port = BP_PORT(bp);
9051
9052 /* Disable sending PTP packets to host */
9053 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9054 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9055
9056 /* Reset PTP event detection rules */
9057 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9058 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9059 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9060 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9061 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9062 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9063 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9064 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9065
9066 /* Disable the PTP feature */
9067 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9068 NIG_REG_P0_PTP_EN, 0x0);
9069}
9070
9071/* Called during unload, to stop PTP-related stuff */
9072void bnx2x_stop_ptp(struct bnx2x *bp)
9073{
9074 /* Cancel PTP work queue. Should be done after the Tx queues are
9075 * drained to prevent additional scheduling.
9076 */
9077 cancel_work_sync(&bp->ptp_task);
9078
9079 if (bp->ptp_tx_skb) {
9080 dev_kfree_skb_any(bp->ptp_tx_skb);
9081 bp->ptp_tx_skb = NULL;
9082 }
9083
9084 /* Disable PTP in HW */
9085 bnx2x_disable_ptp(bp);
9086
9087 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9088}
9089
5d07d868 9090void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 9091{
9092 int port = BP_PORT(bp);
6383c0b3
AE		 9093 int i, rc = 0;
9094 u8 cos;
3b603066 9095 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 9096 u32 reset_code;
9097
9098 /* Wait until tx fastpath tasks complete */
9099 for_each_tx_queue(bp, i) {
9100 struct bnx2x_fastpath *fp = &bp->fp[i];
9101
6383c0b3 9102 for_each_cos_in_tx_queue(fp, cos)
65565884 9103 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 9104#ifdef BNX2X_STOP_ON_ERROR
9105 if (rc)
9106 return;
9107#endif
9108 }
9109
9110 /* Give HW time to discard old tx messages */
0926d499 9111 usleep_range(1000, 2000);
619c5cb6
VZ		 9112
9113 /* Clean all ETH MACs */
15192a8c
BW		 9114 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9115 false);
619c5cb6
VZ		 9116 if (rc < 0)
9117 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9118
9119 /* Clean up UC list */
15192a8c 9120 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 9121 true);
9122 if (rc < 0)
51c1a580
MS		 9123 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9124 rc);
619c5cb6
VZ		 9125
9126 /* Disable LLH */
9127 if (!CHIP_IS_E1(bp))
9128 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9129
9130 /* Set "drop all" (stop Rx).
9131 * We need to take a netif_addr_lock() here in order to prevent
9132 * a race between the completion code and this code.
9133 */
9134 netif_addr_lock_bh(bp->dev);
9135 /* Schedule the rx_mode command */
9136 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9137 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9138 else
9139 bnx2x_set_storm_rx_mode(bp);
9140
9141 /* Cleanup multicast configuration */
9142 rparam.mcast_obj = &bp->mcast_obj;
9143 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9144 if (rc < 0)
9145 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9146
9147 netif_addr_unlock_bh(bp->dev);
9148
f1929b01 9149 bnx2x_iov_chip_cleanup(bp);
619c5cb6 9150
6debea87
DK		 9151 /*
9152 * Send the UNLOAD_REQUEST to the MCP. This will return if
9153 * this function should perform FUNC, PORT or COMMON HW
9154 * reset.
9155 */
9156 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9157
9158 /*
9159 * (assumption: No Attention from MCP at this stage)
16a5fd92 9160 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 9161 */
9162 rc = bnx2x_func_wait_started(bp);
9163 if (rc) {
9164 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9165#ifdef BNX2X_STOP_ON_ERROR
9166 return;
9167#endif
9168 }
9169
34f80b04 9170 /* Close multi and leading connections
619c5cb6
VZ		 9171 * Completions for ramrods are collected in a synchronous way
9172 */
55c11941 9173 for_each_eth_queue(bp, i)
619c5cb6 9174 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 9175#ifdef BNX2X_STOP_ON_ERROR
9176 return;
9177#else
228241eb 9178 goto unload_error;
523224a3 9179#endif
55c11941
MS		 9180
9181 if (CNIC_LOADED(bp)) {
9182 for_each_cnic_queue(bp, i)
9183 if (bnx2x_stop_queue(bp, i))
9184#ifdef BNX2X_STOP_ON_ERROR
9185 return;
9186#else
9187 goto unload_error;
9188#endif
9189 }
9190
619c5cb6
VZ		 9191 /* If SP settings didn't get completed so far - something
9192 * very wrong has happen.
9193 */
9194 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9195 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9196
619c5cb6
VZ		 9197#ifndef BNX2X_STOP_ON_ERROR
9198unload_error:
9199#endif
523224a3 9200 rc = bnx2x_func_stop(bp);
da5a662a 9201 if (rc) {
523224a3 9202 BNX2X_ERR("Function stop failed!\n");
da5a662a 9203#ifdef BNX2X_STOP_ON_ERROR
523224a3 9204 return;
523224a3 9205#endif
34f80b04 9206 }
a2fbb9ea 9207
eeed018c
MK		 9208 /* stop_ptp should be after the Tx queues are drained to prevent
9209 * scheduling to the cancelled PTP work queue. It should also be after
9210 * function stop ramrod is sent, since as part of this ramrod FW access
9211 * PTP registers.
9212 */
9213 bnx2x_stop_ptp(bp);
9214
523224a3
DK		 9215 /* Disable HW interrupts, NAPI */
9216 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9217 /* Delete all NAPI objects */
9218 bnx2x_del_all_napi(bp);
55c11941
MS		 9219 if (CNIC_LOADED(bp))
9220 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9221
9222 /* Release IRQs */
d6214d7a 9223 bnx2x_free_irq(bp);
523224a3 9224
a2fbb9ea 9225 /* Reset the chip */
619c5cb6
VZ		 9226 rc = bnx2x_reset_hw(bp, reset_code);
9227 if (rc)
9228 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 9229
619c5cb6 9230 /* Report UNLOAD_DONE to MCP */
5d07d868 9231 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9232}
9233
9f6c9258 9234void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9235{
9236 u32 val;
9237
51c1a580 9238 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9239
9240 if (CHIP_IS_E1(bp)) {
9241 int port = BP_PORT(bp);
9242 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9243 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9244
9245 val = REG_RD(bp, addr);
9246 val &= ~(0x300);
9247 REG_WR(bp, addr, val);
619c5cb6 9248 } else {
72fd0718
VZ		 9249 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9250 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9251 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9252 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9253 }
9254}
9255
72fd0718
VZ		 9256/* Close gates #2, #3 and #4: */
9257static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9258{
c9ee9206 9259 u32 val;
72fd0718
VZ		 9260
9261 /* Gates #2 and #4a are closed/opened for "not E1" only */
9262 if (!CHIP_IS_E1(bp)) {
9263 /* #4 */
c9ee9206 9264 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9265 /* #2 */
c9ee9206 9266 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9267 }
9268
9269 /* #3 */
c9ee9206
VZ		 9270 if (CHIP_IS_E1x(bp)) {
9271 /* Prevent interrupts from HC on both ports */
9272 val = REG_RD(bp, HC_REG_CONFIG_1);
9273 REG_WR(bp, HC_REG_CONFIG_1,
9274 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9275 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9276
9277 val = REG_RD(bp, HC_REG_CONFIG_0);
9278 REG_WR(bp, HC_REG_CONFIG_0,
9279 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9280 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9281 } else {
d82603c6 9282 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9283 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9284
9285 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9286 (!close) ?
9287 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9288 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9289 }
72fd0718 9290
51c1a580 9291 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9292 close ? "closing" : "opening");
9293 mmiowb();
9294}
9295
9296#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9297
9298static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9299{
9300 /* Do some magic... */
9301 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9302 *magic_val = val & SHARED_MF_CLP_MAGIC;
9303 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9304}
9305
e8920674
DK		 9306/**
9307 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9308 *
e8920674
DK		 9309 * @bp: driver handle
9310 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9311 */
9312static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9313{
9314 /* Restore the `magic' bit value... */
72fd0718
VZ		 9315 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9316 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9317 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9318}
9319
f85582f8 9320/**
e8920674 9321 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9322 *
e8920674
DK		 9323 * @bp: driver handle
9324 * @magic_val: old value of 'magic' bit.
9325 *
9326 * Takes care of CLP configurations.
72fd0718
VZ		 9327 */
9328static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9329{
9330 u32 shmem;
9331 u32 validity_offset;
9332
51c1a580 9333 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9334
9335 /* Set `magic' bit in order to save MF config */
9336 if (!CHIP_IS_E1(bp))
9337 bnx2x_clp_reset_prep(bp, magic_val);
9338
9339 /* Get shmem offset */
9340 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9341 validity_offset =
9342 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9343
9344 /* Clear validity map flags */
9345 if (shmem > 0)
9346 REG_WR(bp, shmem + validity_offset, 0);
9347}
9348
9349#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9350#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9351
e8920674
DK		 9352/**
9353 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9354 *
e8920674 9355 * @bp: driver handle
72fd0718 9356 */
1191cb83 9357static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9358{
9359 /* special handling for emulation and FPGA,
9360 wait 10 times longer */
9361 if (CHIP_REV_IS_SLOW(bp))
9362 msleep(MCP_ONE_TIMEOUT*10);
9363 else
9364 msleep(MCP_ONE_TIMEOUT);
9365}
9366
1b6e2ceb
DK		 9367/*
9368 * initializes bp->common.shmem_base and waits for validity signature to appear
9369 */
9370static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9371{
1b6e2ceb
DK		 9372 int cnt = 0;
9373 u32 val = 0;
72fd0718 9374
1b6e2ceb
DK		 9375 do {
9376 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9377 if (bp->common.shmem_base) {
9378 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9379 if (val & SHR_MEM_VALIDITY_MB)
9380 return 0;
9381 }
72fd0718 9382
1b6e2ceb 9383 bnx2x_mcp_wait_one(bp);
72fd0718 9384
1b6e2ceb 9385 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9386
1b6e2ceb 9387 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9388
1b6e2ceb
DK		 9389 return -ENODEV;
9390}
72fd0718 9391
1b6e2ceb
DK		 9392static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9393{
9394 int rc = bnx2x_init_shmem(bp);
72fd0718 9395
72fd0718
VZ		 9396 /* Restore the `magic' bit value */
9397 if (!CHIP_IS_E1(bp))
9398 bnx2x_clp_reset_done(bp, magic_val);
9399
9400 return rc;
9401}
9402
9403static void bnx2x_pxp_prep(struct bnx2x *bp)
9404{
9405 if (!CHIP_IS_E1(bp)) {
9406 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9407 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9408 mmiowb();
9409 }
9410}
9411
9412/*
9413 * Reset the whole chip except for:
9414 * - PCIE core
9415 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9416 * one reset bit)
9417 * - IGU
9418 * - MISC (including AEU)
9419 * - GRC
9420 * - RBCN, RBCP
9421 */
c9ee9206 9422static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9423{
9424 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9425 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9426
9427 /*
9428 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9429 * (per chip) blocks.
9430 */
9431 global_bits2 =
9432 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9433 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9434
c55e771b
BW		 9435 /* Don't reset the following blocks.
9436 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9437 * reset, as in 4 port device they might still be owned
9438 * by the MCP (there is only one leader per path).
9439 */
72fd0718
VZ		 9440 not_reset_mask1 =
9441 MISC_REGISTERS_RESET_REG_1_RST_HC |
9442 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9443 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9444
9445 not_reset_mask2 =
c9ee9206 9446 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9447 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9448 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9449 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9450 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9451 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9452 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9453 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9454 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9455 MISC_REGISTERS_RESET_REG_2_PGLC |
9456 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9457 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9458 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9459 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9460 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9461 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9462
8736c826
VZ		 9463 /*
9464 * Keep the following blocks in reset:
9465 * - all xxMACs are handled by the bnx2x_link code.
9466 */
9467 stay_reset2 =
8736c826
VZ		 9468 MISC_REGISTERS_RESET_REG_2_XMAC |
9469 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9470
9471 /* Full reset masks according to the chip */
72fd0718
VZ		 9472 reset_mask1 = 0xffffffff;
9473
9474 if (CHIP_IS_E1(bp))
9475 reset_mask2 = 0xffff;
8736c826 9476 else if (CHIP_IS_E1H(bp))
72fd0718 9477 reset_mask2 = 0x1ffff;
8736c826
VZ		 9478 else if (CHIP_IS_E2(bp))
9479 reset_mask2 = 0xfffff;
9480 else /* CHIP_IS_E3 */
9481 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9482
9483 /* Don't reset global blocks unless we need to */
9484 if (!global)
9485 reset_mask2 &= ~global_bits2;
9486
9487 /*
9488 * In case of attention in the QM, we need to reset PXP
9489 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9490 * because otherwise QM reset would release 'close the gates' shortly
9491 * before resetting the PXP, then the PSWRQ would send a write
9492 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9493 * read the payload data from PSWWR, but PSWWR would not
9494 * respond. The write queue in PGLUE would stuck, dmae commands
9495 * would not return. Therefore it's important to reset the second
9496 * reset register (containing the
9497 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9498 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9499 * bit).
9500 */
72fd0718
VZ		 9501 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9502 reset_mask2 & (~not_reset_mask2));
9503
c9ee9206
VZ		 9504 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9505 reset_mask1 & (~not_reset_mask1));
9506
72fd0718
VZ		 9507 barrier();
9508 mmiowb();
9509
8736c826
VZ		 9510 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9511 reset_mask2 & (~stay_reset2));
9512
9513 barrier();
9514 mmiowb();
9515
c9ee9206 9516 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9517 mmiowb();
9518}
9519
c9ee9206
VZ		 9520/**
9521 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9522 * It should get cleared in no more than 1s.
9523 *
9524 * @bp: driver handle
9525 *
9526 * It should get cleared in no more than 1s. Returns 0 if
9527 * pending writes bit gets cleared.
9528 */
9529static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9530{
9531 u32 cnt = 1000;
9532 u32 pend_bits = 0;
9533
9534 do {
9535 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9536
9537 if (pend_bits == 0)
9538 break;
9539
0926d499 9540 usleep_range(1000, 2000);
c9ee9206
VZ		 9541 } while (cnt-- > 0);
9542
9543 if (cnt <= 0) {
9544 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9545 pend_bits);
9546 return -EBUSY;
9547 }
9548
9549 return 0;
9550}
9551
9552static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9553{
9554 int cnt = 1000;
9555 u32 val = 0;
9556 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9557 u32 tags_63_32 = 0;
72fd0718
VZ		 9558
9559 /* Empty the Tetris buffer, wait for 1s */
9560 do {
9561 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9562 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9563 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9564 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9565 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9566 if (CHIP_IS_E3(bp))
9567 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9568
72fd0718
VZ		 9569 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9570 ((port_is_idle_0 & 0x1) == 0x1) &&
9571 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9572 (pgl_exp_rom2 == 0xffffffff) &&
9573 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9574 break;
0926d499 9575 usleep_range(1000, 2000);
72fd0718
VZ		 9576 } while (cnt-- > 0);
9577
9578 if (cnt <= 0) {
51c1a580
MS		 9579 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9580 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9581 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9582 pgl_exp_rom2);
9583 return -EAGAIN;
9584 }
9585
9586 barrier();
9587
9588 /* Close gates #2, #3 and #4 */
9589 bnx2x_set_234_gates(bp, true);
9590
c9ee9206
VZ		 9591 /* Poll for IGU VQs for 57712 and newer chips */
9592 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9593 return -EAGAIN;
9594
72fd0718
VZ		 9595 /* TBD: Indicate that "process kill" is in progress to MCP */
9596
9597 /* Clear "unprepared" bit */
9598 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9599 barrier();
9600
9601 /* Make sure all is written to the chip before the reset */
9602 mmiowb();
9603
9604 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9605 * PSWHST, GRC and PSWRD Tetris buffer.
9606 */
0926d499 9607 usleep_range(1000, 2000);
72fd0718
VZ		 9608
9609 /* Prepare to chip reset: */
9610 /* MCP */
c9ee9206
VZ		 9611 if (global)
9612 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9613
9614 /* PXP */
9615 bnx2x_pxp_prep(bp);
9616 barrier();
9617
9618 /* reset the chip */
c9ee9206 9619 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9620 barrier();
9621
9dcd9acd
DK		 9622 /* clear errors in PGB */
9623 if (!CHIP_IS_E1x(bp))
9624 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9625
72fd0718
VZ		 9626 /* Recover after reset: */
9627 /* MCP */
c9ee9206 9628 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9629 return -EAGAIN;
9630
c9ee9206
VZ		 9631 /* TBD: Add resetting the NO_MCP mode DB here */
9632
72fd0718
VZ		 9633 /* Open the gates #2, #3 and #4 */
9634 bnx2x_set_234_gates(bp, false);
9635
9636 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9637 * reset state, re-enable attentions. */
9638
a2fbb9ea
ET		 9639 return 0;
9640}
9641
910cc727 9642static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9643{
9644 int rc = 0;
c9ee9206 9645 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9646 u32 load_code;
9647
9648 /* if not going to reset MCP - load "fake" driver to reset HW while
9649 * driver is owner of the HW
9650 */
9651 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9652 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9653 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9654 if (!load_code) {
9655 BNX2X_ERR("MCP response failure, aborting\n");
9656 rc = -EAGAIN;
9657 goto exit_leader_reset;
9658 }
9659 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9660 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9661 BNX2X_ERR("MCP unexpected resp, aborting\n");
9662 rc = -EAGAIN;
9663 goto exit_leader_reset2;
9664 }
9665 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9666 if (!load_code) {
9667 BNX2X_ERR("MCP response failure, aborting\n");
9668 rc = -EAGAIN;
9669 goto exit_leader_reset2;
9670 }
9671 }
c9ee9206 9672
72fd0718 9673 /* Try to recover after the failure */
c9ee9206 9674 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9675 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9676 BP_PATH(bp));
72fd0718 9677 rc = -EAGAIN;
95c6c616 9678 goto exit_leader_reset2;
72fd0718
VZ		 9679 }
9680
c9ee9206
VZ		 9681 /*
9682 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9683 * state.
9684 */
72fd0718 9685 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9686 if (global)
9687 bnx2x_clear_reset_global(bp);
72fd0718 9688
95c6c616
AE		 9689exit_leader_reset2:
9690 /* unload "fake driver" if it was loaded */
9691 if (!global && !BP_NOMCP(bp)) {
9692 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9693 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9694 }
72fd0718
VZ		 9695exit_leader_reset:
9696 bp->is_leader = 0;
c9ee9206
VZ		 9697 bnx2x_release_leader_lock(bp);
9698 smp_mb();
72fd0718
VZ		 9699 return rc;
9700}
9701
1191cb83 9702static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9703{
9704 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9705
9706 /* Disconnect this device */
9707 netif_device_detach(bp->dev);
9708
9709 /*
9710 * Block ifup for all function on this engine until "process kill"
9711 * or power cycle.
9712 */
9713 bnx2x_set_reset_in_progress(bp);
9714
9715 /* Shut down the power */
9716 bnx2x_set_power_state(bp, PCI_D3hot);
9717
9718 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9719
9720 smp_mb();
9721}
9722
9723/*
9724 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9725 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9726 * will never be called when netif_running(bp->dev) is false.
9727 */
9728static void bnx2x_parity_recover(struct bnx2x *bp)
9729{
c9ee9206 9730 bool global = false;
7a752993 9731 u32 error_recovered, error_unrecovered;
95c6c616 9732 bool is_parity;
c9ee9206 9733
72fd0718
VZ		 9734 DP(NETIF_MSG_HW, "Handling parity\n");
9735 while (1) {
9736 switch (bp->recovery_state) {
9737 case BNX2X_RECOVERY_INIT:
9738 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9739 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9740 WARN_ON(!is_parity);
c9ee9206 9741
72fd0718 9742 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9743 if (bnx2x_trylock_leader_lock(bp)) {
9744 bnx2x_set_reset_in_progress(bp);
9745 /*
9746 * Check if there is a global attention and if
9747 * there was a global attention, set the global
9748 * reset bit.
9749 */
9750
9751 if (global)
9752 bnx2x_set_reset_global(bp);
9753
72fd0718 9754 bp->is_leader = 1;
c9ee9206 9755 }
72fd0718
VZ		 9756
9757 /* Stop the driver */
9758 /* If interface has been removed - break */
5d07d868 9759 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9760 return;
9761
9762 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9763
c9ee9206
VZ		 9764 /* Ensure "is_leader", MCP command sequence and
9765 * "recovery_state" update values are seen on other
9766 * CPUs.
72fd0718 9767 */
c9ee9206 9768 smp_mb();
72fd0718
VZ		 9769 break;
9770
9771 case BNX2X_RECOVERY_WAIT:
9772 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9773 if (bp->is_leader) {
c9ee9206 9774 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9775 bool other_load_status =
9776 bnx2x_get_load_status(bp, other_engine);
9777 bool load_status =
9778 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9779 global = bnx2x_reset_is_global(bp);
9780
9781 /*
9782 * In case of a parity in a global block, let
9783 * the first leader that performs a
9784 * leader_reset() reset the global blocks in
9785 * order to clear global attentions. Otherwise
16a5fd92 9786 * the gates will remain closed for that
c9ee9206
VZ		 9787 * engine.
9788 */
889b9af3
AE		 9789 if (load_status ||
9790 (global && other_load_status)) {
72fd0718
VZ		 9791 /* Wait until all other functions get
9792 * down.
9793 */
7be08a72 9794 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9795 HZ/10);
9796 return;
9797 } else {
9798 /* If all other functions got down -
9799 * try to bring the chip back to
9800 * normal. In any case it's an exit
9801 * point for a leader.
9802 */
c9ee9206
VZ		 9803 if (bnx2x_leader_reset(bp)) {
9804 bnx2x_recovery_failed(bp);
72fd0718
VZ		 9805 return;
9806 }
9807
c9ee9206
VZ		 9808 /* If we are here, means that the
9809 * leader has succeeded and doesn't
9810 * want to be a leader any more. Try
9811 * to continue as a none-leader.
9812 */
9813 break;
72fd0718
VZ		 9814 }
9815 } else { /* non-leader */
c9ee9206 9816 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 9817 /* Try to get a LEADER_LOCK HW lock as
9818 * long as a former leader may have
9819 * been unloaded by the user or
9820 * released a leadership by another
9821 * reason.
9822 */
c9ee9206 9823 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 9824 /* I'm a leader now! Restart a
9825 * switch case.
9826 */
9827 bp->is_leader = 1;
9828 break;
9829 }
9830
7be08a72 9831 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9832 HZ/10);
9833 return;
9834
c9ee9206
VZ		 9835 } else {
9836 /*
9837 * If there was a global attention, wait
9838 * for it to be cleared.
9839 */
9840 if (bnx2x_reset_is_global(bp)) {
9841 schedule_delayed_work(
7be08a72
AE		 9842 &bp->sp_rtnl_task,
9843 HZ/10);
c9ee9206
VZ		 9844 return;
9845 }
9846
7a752993
AE		 9847 error_recovered =
9848 bp->eth_stats.recoverable_error;
9849 error_unrecovered =
9850 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 9851 bp->recovery_state =
9852 BNX2X_RECOVERY_NIC_LOADING;
9853 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 9854 error_unrecovered++;
95c6c616 9855 netdev_err(bp->dev,
51c1a580 9856 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 9857 /* Disconnect this device */
9858 netif_device_detach(bp->dev);
9859 /* Shut down the power */
9860 bnx2x_set_power_state(
9861 bp, PCI_D3hot);
9862 smp_mb();
9863 } else {
c9ee9206
VZ		 9864 bp->recovery_state =
9865 BNX2X_RECOVERY_DONE;
7a752993 9866 error_recovered++;
c9ee9206
VZ		 9867 smp_mb();
9868 }
7a752993
AE		 9869 bp->eth_stats.recoverable_error =
9870 error_recovered;
9871 bp->eth_stats.unrecoverable_error =
9872 error_unrecovered;
c9ee9206 9873
72fd0718
VZ		 9874 return;
9875 }
9876 }
9877 default:
9878 return;
9879 }
9880 }
9881}
9882
56ad3152
MS		 9883static int bnx2x_close(struct net_device *dev);
9884
72fd0718
VZ		 9885/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9886 * scheduled on a general queue in order to prevent a dead lock.
9887 */
7be08a72 9888static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 9889{
7be08a72 9890 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 9891
9892 rtnl_lock();
9893
8395be5e
AE		 9894 if (!netif_running(bp->dev)) {
9895 rtnl_unlock();
9896 return;
9897 }
7be08a72 9898
6bf07b8e 9899 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 9900#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 9901 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9902 "you will need to reboot when done\n");
9903 goto sp_rtnl_not_reset;
7be08a72 9904#endif
7be08a72 9905 /*
b1fb8740
VZ		 9906 * Clear all pending SP commands as we are going to reset the
9907 * function anyway.
7be08a72 9908 */
b1fb8740
VZ		 9909 bp->sp_rtnl_state = 0;
9910 smp_mb();
9911
72fd0718 9912 bnx2x_parity_recover(bp);
b1fb8740 9913
8395be5e
AE		 9914 rtnl_unlock();
9915 return;
b1fb8740
VZ		 9916 }
9917
9918 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 9919#ifdef BNX2X_STOP_ON_ERROR
9920 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9921 "you will need to reboot when done\n");
9922 goto sp_rtnl_not_reset;
9923#endif
9924
b1fb8740
VZ		 9925 /*
9926 * Clear all pending SP commands as we are going to reset the
9927 * function anyway.
9928 */
9929 bp->sp_rtnl_state = 0;
9930 smp_mb();
9931
5d07d868 9932 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 9933 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740 9934
8395be5e
AE		 9935 rtnl_unlock();
9936 return;
72fd0718 9937 }
b1fb8740
VZ		 9938#ifdef BNX2X_STOP_ON_ERROR
9939sp_rtnl_not_reset:
9940#endif
9941 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9942 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 9943 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9944 bnx2x_after_function_update(bp);
8304859a
AE		 9945 /*
9946 * in case of fan failure we need to reset id if the "stop on error"
9947 * debug flag is set, since we trying to prevent permanent overheating
9948 * damage
9949 */
9950 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 9951 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 9952 netif_device_detach(bp->dev);
9953 bnx2x_close(bp->dev);
8395be5e
AE		 9954 rtnl_unlock();
9955 return;
8304859a
AE		 9956 }
9957
381ac16b
AE		 9958 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9959 DP(BNX2X_MSG_SP,
9960 "sending set mcast vf pf channel message from rtnl sp-task\n");
9961 bnx2x_vfpf_set_mcast(bp->dev);
9962 }
78c3bcc5
AE		 9963 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9964 &bp->sp_rtnl_state)){
9965 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9966 bnx2x_tx_disable(bp);
9967 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9968 }
9969 }
381ac16b 9970
8b09be5f
YM		 9971 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9972 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9973 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 9974 }
9975
3ec9f9ca
AE		 9976 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9977 &bp->sp_rtnl_state))
9978 bnx2x_pf_set_vfs_vlan(bp);
9979
6ffa39f2 9980 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 9981 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 9982 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 9983 }
07b4eb3b 9984
42f8277f
YM		 9985 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
9986 &bp->sp_rtnl_state))
9987 bnx2x_update_mng_version(bp);
9988
8395be5e
AE		 9989 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9990 * can be called from other contexts as well)
9991 */
34f80b04 9992 rtnl_unlock();
8395be5e 9993
6411280a 9994 /* enable SR-IOV if applicable */
8395be5e 9995 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 9996 &bp->sp_rtnl_state)) {
9997 bnx2x_disable_sriov(bp);
6411280a 9998 bnx2x_enable_sriov(bp);
3c76feff 9999 }
34f80b04
EG		 10000}
10001
3deb8167
YR		 10002static void bnx2x_period_task(struct work_struct *work)
10003{
10004 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10005
10006 if (!netif_running(bp->dev))
10007 goto period_task_exit;
10008
10009 if (CHIP_REV_IS_SLOW(bp)) {
10010 BNX2X_ERR("period task called on emulation, ignoring\n");
10011 goto period_task_exit;
10012 }
10013
10014 bnx2x_acquire_phy_lock(bp);
10015 /*
10016 * The barrier is needed to ensure the ordering between the writing to
10017 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10018 * the reading here.
10019 */
10020 smp_mb();
10021 if (bp->port.pmf) {
10022 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10023
10024 /* Re-queue task in 1 sec */
10025 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10026 }
10027
10028 bnx2x_release_phy_lock(bp);
10029period_task_exit:
10030 return;
10031}
10032
a2fbb9ea
ET		 10033/*
10034 * Init service functions
10035 */
10036
a8f47eb7 10037static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 10038{
10039 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10040 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10041 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 10042}
10043
1ef1d45a
BW		 10044static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10045 struct bnx2x_mac_vals *vals)
34f80b04 10046{
452427b0
YM		 10047 u32 val, base_addr, offset, mask, reset_reg;
10048 bool mac_stopped = false;
10049 u8 port = BP_PORT(bp);
34f80b04 10050
1ef1d45a
BW		 10051 /* reset addresses as they also mark which values were changed */
10052 vals->bmac_addr = 0;
10053 vals->umac_addr = 0;
10054 vals->xmac_addr = 0;
10055 vals->emac_addr = 0;
10056
452427b0 10057 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 10058
452427b0
YM		 10059 if (!CHIP_IS_E3(bp)) {
10060 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10061 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10062 if ((mask & reset_reg) && val) {
10063 u32 wb_data[2];
10064 BNX2X_DEV_INFO("Disable bmac Rx\n");
10065 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10066 : NIG_REG_INGRESS_BMAC0_MEM;
10067 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10068 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 10069
452427b0
YM		 10070 /*
10071 * use rd/wr since we cannot use dmae. This is safe
10072 * since MCP won't access the bus due to the request
10073 * to unload, and no function on the path can be
10074 * loaded at this time.
10075 */
10076 wb_data[0] = REG_RD(bp, base_addr + offset);
10077 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 10078 vals->bmac_addr = base_addr + offset;
10079 vals->bmac_val[0] = wb_data[0];
10080 vals->bmac_val[1] = wb_data[1];
452427b0 10081 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 10082 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10083 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 10084 }
10085 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 10086 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10087 vals->emac_val = REG_RD(bp, vals->emac_addr);
10088 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 10089 mac_stopped = true;
10090 } else {
10091 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10092 BNX2X_DEV_INFO("Disable xmac Rx\n");
10093 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10094 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10095 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10096 val & ~(1 << 1));
10097 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10098 val | (1 << 1));
1ef1d45a
BW		 10099 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10100 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10101 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 10102 mac_stopped = true;
10103 }
10104 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10105 if (mask & reset_reg) {
10106 BNX2X_DEV_INFO("Disable umac Rx\n");
10107 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1ef1d45a
BW		 10108 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10109 vals->umac_val = REG_RD(bp, vals->umac_addr);
10110 REG_WR(bp, vals->umac_addr, 0);
452427b0
YM		 10111 mac_stopped = true;
10112 }
10113 }
10114
10115 if (mac_stopped)
10116 msleep(20);
452427b0
YM		 10117}
10118
10119#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10120#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10121#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10122#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10123
91ebb929
YM		 10124#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10125#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10126#define BCM_5710_UNDI_FW_MF_VERS (0x05)
de682941
YM		 10127#define BNX2X_PREV_UNDI_MF_PORT(p) (BAR_TSTRORM_INTMEM + 0x150c + ((p) << 4))
10128#define BNX2X_PREV_UNDI_MF_FUNC(f) (BAR_TSTRORM_INTMEM + 0x184c + ((f) << 4))
b17b0ca1
YM		 10129
10130static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10131{
10132 /* UNDI marks its presence in DORQ -
10133 * it initializes CID offset for normal bell to 0x7
10134 */
10135 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10136 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10137 return false;
10138
10139 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10140 BNX2X_DEV_INFO("UNDI previously loaded\n");
10141 return true;
10142 }
10143
10144 return false;
10145}
10146
91ebb929
YM		 10147static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
10148{
10149 u8 major, minor, version;
10150 u32 fw;
10151
10152 /* Must check that FW is loaded */
10153 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10154 MISC_REGISTERS_RESET_REG_1_RST_XSEM)) {
10155 BNX2X_DEV_INFO("XSEM is reset - UNDI MF FW is not loaded\n");
10156 return false;
10157 }
10158
10159 /* Read Currently loaded FW version */
10160 fw = REG_RD(bp, XSEM_REG_PRAM);
10161 major = fw & 0xff;
10162 minor = (fw >> 0x8) & 0xff;
10163 version = (fw >> 0x10) & 0xff;
10164 BNX2X_DEV_INFO("Loaded FW: 0x%08x: Major 0x%02x Minor 0x%02x Version 0x%02x\n",
10165 fw, major, minor, version);
10166
10167 if (major > BCM_5710_UNDI_FW_MF_MAJOR)
10168 return true;
10169
10170 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
10171 (minor > BCM_5710_UNDI_FW_MF_MINOR))
10172 return true;
10173
10174 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
10175 (minor == BCM_5710_UNDI_FW_MF_MINOR) &&
10176 (version >= BCM_5710_UNDI_FW_MF_VERS))
10177 return true;
10178
10179 return false;
10180}
10181
10182static void bnx2x_prev_unload_undi_mf(struct bnx2x *bp)
10183{
10184 int i;
10185
10186 /* Due to legacy (FW) code, the first function on each engine has a
10187 * different offset macro from the rest of the functions.
10188 * Setting this for all 8 functions is harmless regardless of whether
10189 * this is actually a multi-function device.
10190 */
10191 for (i = 0; i < 2; i++)
10192 REG_WR(bp, BNX2X_PREV_UNDI_MF_PORT(i), 1);
10193
10194 for (i = 2; i < 8; i++)
10195 REG_WR(bp, BNX2X_PREV_UNDI_MF_FUNC(i - 2), 1);
10196
10197 BNX2X_DEV_INFO("UNDI FW (MF) set to discard\n");
10198}
10199
1dd06ae8 10200static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
452427b0
YM		 10201{
10202 u16 rcq, bd;
10203 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
10204
10205 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10206 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10207
10208 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10209 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
10210
10211 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10212 port, bd, rcq);
10213}
10214
0329aba1 10215static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10216{
5d07d868
YM		 10217 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10218 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10219 if (!rc) {
10220 BNX2X_ERR("MCP response failure, aborting\n");
10221 return -EBUSY;
10222 }
10223
10224 return 0;
10225}
10226
c63da990
BW		 10227static struct bnx2x_prev_path_list *
10228 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10229{
10230 struct bnx2x_prev_path_list *tmp_list;
10231
10232 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10233 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10234 bp->pdev->bus->number == tmp_list->bus &&
10235 BP_PATH(bp) == tmp_list->path)
10236 return tmp_list;
10237
10238 return NULL;
10239}
10240
7fa6f340
YM		 10241static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10242{
10243 struct bnx2x_prev_path_list *tmp_list;
10244 int rc;
10245
10246 rc = down_interruptible(&bnx2x_prev_sem);
10247 if (rc) {
10248 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10249 return rc;
10250 }
10251
10252 tmp_list = bnx2x_prev_path_get_entry(bp);
10253 if (tmp_list) {
10254 tmp_list->aer = 1;
10255 rc = 0;
10256 } else {
10257 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10258 BP_PATH(bp));
10259 }
10260
10261 up(&bnx2x_prev_sem);
10262
10263 return rc;
10264}
10265
0329aba1 10266static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10267{
10268 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10269 bool rc = false;
452427b0
YM		 10270
10271 if (down_trylock(&bnx2x_prev_sem))
10272 return false;
10273
7fa6f340
YM		 10274 tmp_list = bnx2x_prev_path_get_entry(bp);
10275 if (tmp_list) {
10276 if (tmp_list->aer) {
10277 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10278 BP_PATH(bp));
10279 } else {
452427b0
YM		 10280 rc = true;
10281 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10282 BP_PATH(bp));
452427b0
YM		 10283 }
10284 }
10285
10286 up(&bnx2x_prev_sem);
10287
10288 return rc;
10289}
10290
178135c1
DK		 10291bool bnx2x_port_after_undi(struct bnx2x *bp)
10292{
10293 struct bnx2x_prev_path_list *entry;
10294 bool val;
10295
10296 down(&bnx2x_prev_sem);
10297
10298 entry = bnx2x_prev_path_get_entry(bp);
10299 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10300
10301 up(&bnx2x_prev_sem);
10302
10303 return val;
10304}
10305
c63da990 10306static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10307{
10308 struct bnx2x_prev_path_list *tmp_list;
10309 int rc;
10310
7fa6f340
YM		 10311 rc = down_interruptible(&bnx2x_prev_sem);
10312 if (rc) {
10313 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10314 return rc;
10315 }
10316
10317 /* Check whether the entry for this path already exists */
10318 tmp_list = bnx2x_prev_path_get_entry(bp);
10319 if (tmp_list) {
10320 if (!tmp_list->aer) {
10321 BNX2X_ERR("Re-Marking the path.\n");
10322 } else {
10323 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10324 BP_PATH(bp));
10325 tmp_list->aer = 0;
10326 }
10327 up(&bnx2x_prev_sem);
10328 return 0;
10329 }
10330 up(&bnx2x_prev_sem);
10331
10332 /* Create an entry for this path and add it */
ea4b3857 10333 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10334 if (!tmp_list) {
10335 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10336 return -ENOMEM;
10337 }
10338
10339 tmp_list->bus = bp->pdev->bus->number;
10340 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10341 tmp_list->path = BP_PATH(bp);
7fa6f340 10342 tmp_list->aer = 0;
c63da990 10343 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10344
10345 rc = down_interruptible(&bnx2x_prev_sem);
10346 if (rc) {
10347 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10348 kfree(tmp_list);
10349 } else {
7fa6f340
YM		 10350 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10351 BP_PATH(bp));
452427b0
YM		 10352 list_add(&tmp_list->list, &bnx2x_prev_list);
10353 up(&bnx2x_prev_sem);
10354 }
10355
10356 return rc;
10357}
10358
0329aba1 10359static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10360{
452427b0
YM		 10361 struct pci_dev *dev = bp->pdev;
10362
8eee694c
YM		 10363 if (CHIP_IS_E1x(bp)) {
10364 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10365 return -EINVAL;
10366 }
10367
10368 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10369 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10370 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10371 bp->common.bc_ver);
10372 return -EINVAL;
10373 }
452427b0 10374
8903b9eb
CL		 10375 if (!pci_wait_for_pending_transaction(dev))
10376 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10377
8eee694c 10378 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10379 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10380
10381 return 0;
10382}
10383
0329aba1 10384static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10385{
10386 int rc;
10387
10388 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10389
10390 /* Test if previous unload process was already finished for this path */
10391 if (bnx2x_prev_is_path_marked(bp))
10392 return bnx2x_prev_mcp_done(bp);
10393
04c46736
YM		 10394 BNX2X_DEV_INFO("Path is unmarked\n");
10395
b17b0ca1
YM		 10396 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10397 if (bnx2x_prev_is_after_undi(bp))
10398 goto out;
10399
452427b0
YM		 10400 /* If function has FLR capabilities, and existing FW version matches
10401 * the one required, then FLR will be sufficient to clean any residue
10402 * left by previous driver
10403 */
91ebb929 10404 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10405
10406 if (!rc) {
10407 /* fw version is good */
10408 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10409 rc = bnx2x_do_flr(bp);
10410 }
10411
10412 if (!rc) {
10413 /* FLR was performed */
10414 BNX2X_DEV_INFO("FLR successful\n");
10415 return 0;
10416 }
10417
10418 BNX2X_DEV_INFO("Could not FLR\n");
452427b0 10419
b17b0ca1 10420out:
452427b0
YM		 10421 /* Close the MCP request, return failure*/
10422 rc = bnx2x_prev_mcp_done(bp);
10423 if (!rc)
10424 rc = BNX2X_PREV_WAIT_NEEDED;
10425
10426 return rc;
10427}
10428
0329aba1 10429static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10430{
10431 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10432 bool prev_undi = false;
1ef1d45a
BW		 10433 struct bnx2x_mac_vals mac_vals;
10434
452427b0
YM		 10435 /* It is possible a previous function received 'common' answer,
10436 * but hasn't loaded yet, therefore creating a scenario of
10437 * multiple functions receiving 'common' on the same path.
10438 */
10439 BNX2X_DEV_INFO("Common unload Flow\n");
10440
1ef1d45a
BW		 10441 memset(&mac_vals, 0, sizeof(mac_vals));
10442
452427b0
YM		 10443 if (bnx2x_prev_is_path_marked(bp))
10444 return bnx2x_prev_mcp_done(bp);
10445
10446 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10447
10448 /* Reset should be performed after BRB is emptied */
10449 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10450 u32 timer_count = 1000;
de682941 10451 bool need_write = true;
452427b0
YM		 10452
10453 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10454 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10455
10456 /* close LLH filters towards the BRB */
10457 bnx2x_set_rx_filter(&bp->link_params, 0);
452427b0 10458
b17b0ca1
YM		 10459 /* Check if the UNDI driver was previously loaded */
10460 if (bnx2x_prev_is_after_undi(bp)) {
10461 prev_undi = true;
10462 /* clear the UNDI indication */
10463 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10464 /* clear possible idle check errors */
10465 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
452427b0 10466 }
d46f7c4d
DK		 10467 if (!CHIP_IS_E1x(bp))
10468 /* block FW from writing to host */
10469 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10470
452427b0
YM		 10471 /* wait until BRB is empty */
10472 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10473 while (timer_count) {
10474 u32 prev_brb = tmp_reg;
34f80b04 10475
452427b0
YM		 10476 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10477 if (!tmp_reg)
10478 break;
619c5cb6 10479
452427b0 10480 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10481
452427b0
YM		 10482 /* reset timer as long as BRB actually gets emptied */
10483 if (prev_brb > tmp_reg)
10484 timer_count = 1000;
10485 else
10486 timer_count--;
da5a662a 10487
91ebb929
YM		 10488 /* New UNDI FW supports MF and contains better
10489 * cleaning methods - might be redundant but harmless.
10490 */
10491 if (bnx2x_prev_unload_undi_fw_supports_mf(bp)) {
de682941
YM		 10492 if (need_write) {
10493 bnx2x_prev_unload_undi_mf(bp);
10494 need_write = false;
10495 }
91ebb929
YM		 10496 } else if (prev_undi) {
10497 /* If UNDI resides in memory,
10498 * manually increment it
10499 */
452427b0 10500 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
91ebb929 10501 }
452427b0 10502 udelay(10);
7a06a122 10503 }
452427b0
YM		 10504
10505 if (!timer_count)
10506 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10507 }
f16da43b 10508
452427b0
YM		 10509 /* No packets are in the pipeline, path is ready for reset */
10510 bnx2x_reset_common(bp);
10511
1ef1d45a
BW		 10512 if (mac_vals.xmac_addr)
10513 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10514 if (mac_vals.umac_addr)
10515 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10516 if (mac_vals.emac_addr)
10517 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10518 if (mac_vals.bmac_addr) {
10519 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10520 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10521 }
10522
c63da990 10523 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10524 if (rc) {
10525 bnx2x_prev_mcp_done(bp);
10526 return rc;
10527 }
10528
10529 return bnx2x_prev_mcp_done(bp);
10530}
10531
24f06716
AE		 10532/* previous driver DMAE transaction may have occurred when pre-boot stage ended
10533 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10534 * the addresses of the transaction, resulting in was-error bit set in the pci
10535 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10536 * to clear the interrupt which detected this from the pglueb and the was done
10537 * bit
10538 */
0329aba1 10539static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
24f06716 10540{
4a25417c
AE		 10541 if (!CHIP_IS_E1x(bp)) {
10542 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10543 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
04c46736
YM		 10544 DP(BNX2X_MSG_SP,
10545 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
4a25417c
AE		 10546 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10547 1 << BP_FUNC(bp));
10548 }
24f06716
AE		 10549 }
10550}
10551
0329aba1 10552static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10553{
10554 int time_counter = 10;
10555 u32 rc, fw, hw_lock_reg, hw_lock_val;
10556 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10557
24f06716
AE		 10558 /* clear hw from errors which may have resulted from an interrupted
10559 * dmae transaction.
10560 */
10561 bnx2x_prev_interrupted_dmae(bp);
10562
10563 /* Release previously held locks */
452427b0
YM		 10564 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10565 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10566 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10567
3cdeec22 10568 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10569 if (hw_lock_val) {
10570 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10571 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10572 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10573 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10574 }
10575
10576 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10577 REG_WR(bp, hw_lock_reg, 0xffffffff);
10578 } else
10579 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10580
10581 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10582 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10583 bnx2x_release_alr(bp);
452427b0
YM		 10584 }
10585
452427b0 10586 do {
7fa6f340 10587 int aer = 0;
452427b0
YM		 10588 /* Lock MCP using an unload request */
10589 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10590 if (!fw) {
10591 BNX2X_ERR("MCP response failure, aborting\n");
10592 rc = -EBUSY;
10593 break;
10594 }
10595
7fa6f340
YM		 10596 rc = down_interruptible(&bnx2x_prev_sem);
10597 if (rc) {
10598 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10599 rc);
10600 } else {
10601 /* If Path is marked by EEH, ignore unload status */
10602 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10603 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10604 up(&bnx2x_prev_sem);
7fa6f340 10605 }
7fa6f340
YM		 10606
10607 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10608 rc = bnx2x_prev_unload_common(bp);
10609 break;
10610 }
10611
16a5fd92 10612 /* non-common reply from MCP might require looping */
452427b0
YM		 10613 rc = bnx2x_prev_unload_uncommon(bp);
10614 if (rc != BNX2X_PREV_WAIT_NEEDED)
10615 break;
10616
10617 msleep(20);
10618 } while (--time_counter);
10619
10620 if (!time_counter || rc) {
91ebb929
YM		 10621 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10622 rc = -EPROBE_DEFER;
452427b0
YM		 10623 }
10624
c63da990 10625 /* Mark function if its port was used to boot from SAN */
178135c1 10626 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10627 bp->link_params.feature_config_flags |=
10628 FEATURE_CONFIG_BOOT_FROM_SAN;
10629
452427b0
YM		 10630 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10631
10632 return rc;
34f80b04
EG		 10633}
10634
0329aba1 10635static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10636{
1d187b34 10637 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10638 u16 pmc;
34f80b04
EG		 10639
10640 /* Get the chip revision id and number. */
10641 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10642 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10643 id = ((val & 0xffff) << 16);
10644 val = REG_RD(bp, MISC_REG_CHIP_REV);
10645 id |= ((val & 0xf) << 12);
f22fdf25
YM		 10646
10647 /* Metal is read from PCI regs, but we can't access >=0x400 from
10648 * the configuration space (so we need to reg_rd)
10649 */
10650 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10651 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 10652 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10653 id |= (val & 0xf);
10654 bp->common.chip_id = id;
523224a3 10655
7e8e02df
BW		 10656 /* force 57811 according to MISC register */
10657 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10658 if (CHIP_IS_57810(bp))
10659 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10660 (bp->common.chip_id & 0x0000FFFF);
10661 else if (CHIP_IS_57810_MF(bp))
10662 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10663 (bp->common.chip_id & 0x0000FFFF);
10664 bp->common.chip_id |= 0x1;
10665 }
10666
523224a3
DK		 10667 /* Set doorbell size */
10668 bp->db_size = (1 << BNX2X_DB_SHIFT);
10669
619c5cb6 10670 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10671 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10672 if ((val & 1) == 0)
10673 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10674 else
10675 val = (val >> 1) & 1;
10676 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10677 "2_PORT_MODE");
10678 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10679 CHIP_2_PORT_MODE;
10680
10681 if (CHIP_MODE_IS_4_PORT(bp))
10682 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10683 else
10684 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10685 } else {
10686 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10687 bp->pfid = bp->pf_num; /* 0..7 */
10688 }
10689
51c1a580
MS		 10690 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10691
f2e0899f
DK		 10692 bp->link_params.chip_id = bp->common.chip_id;
10693 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10694
1c06328c
EG		 10695 val = (REG_RD(bp, 0x2874) & 0x55);
10696 if ((bp->common.chip_id & 0x1) ||
10697 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10698 bp->flags |= ONE_PORT_FLAG;
10699 BNX2X_DEV_INFO("single port device\n");
10700 }
10701
34f80b04 10702 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 10703 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 10704 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10705 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10706 bp->common.flash_size, bp->common.flash_size);
10707
1b6e2ceb
DK		 10708 bnx2x_init_shmem(bp);
10709
f2e0899f
DK		 10710 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10711 MISC_REG_GENERIC_CR_1 :
10712 MISC_REG_GENERIC_CR_0));
1b6e2ceb 10713
34f80b04 10714 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 10715 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 10716 if (SHMEM2_RD(bp, size) >
10717 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10718 bp->link_params.lfa_base =
10719 REG_RD(bp, bp->common.shmem2_base +
10720 (u32)offsetof(struct shmem2_region,
10721 lfa_host_addr[BP_PORT(bp)]));
10722 else
10723 bp->link_params.lfa_base = 0;
2691d51d
EG		 10724 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10725 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 10726
f2e0899f 10727 if (!bp->common.shmem_base) {
34f80b04
EG		 10728 BNX2X_DEV_INFO("MCP not active\n");
10729 bp->flags |= NO_MCP_FLAG;
10730 return;
10731 }
10732
34f80b04 10733 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 10734 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 10735
10736 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10737 SHARED_HW_CFG_LED_MODE_MASK) >>
10738 SHARED_HW_CFG_LED_MODE_SHIFT);
10739
c2c8b03e
EG		 10740 bp->link_params.feature_config_flags = 0;
10741 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10742 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10743 bp->link_params.feature_config_flags |=
10744 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10745 else
10746 bp->link_params.feature_config_flags &=
10747 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10748
34f80b04
EG		 10749 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10750 bp->common.bc_ver = val;
10751 BNX2X_DEV_INFO("bc_ver %X\n", val);
10752 if (val < BNX2X_BC_VER) {
10753 /* for now only warn
10754 * later we might need to enforce this */
51c1a580
MS		 10755 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10756 BNX2X_BC_VER, val);
34f80b04 10757 }
4d295db0 10758 bp->link_params.feature_config_flags |=
a22f0788 10759 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 10760 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10761
a22f0788
YR		 10762 bp->link_params.feature_config_flags |=
10763 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10764 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 10765 bp->link_params.feature_config_flags |=
10766 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10767 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 10768 bp->link_params.feature_config_flags |=
10769 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10770 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 10771
10772 bp->link_params.feature_config_flags |=
10773 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10774 FEATURE_CONFIG_MT_SUPPORT : 0;
10775
0e898dd7
BW		 10776 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10777 BC_SUPPORTS_PFC_STATS : 0;
85242eea 10778
2e499d3c
BW		 10779 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10780 BC_SUPPORTS_FCOE_FEATURES : 0;
10781
9876879f
BW		 10782 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10783 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 10784
10785 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10786 BC_SUPPORTS_RMMOD_CMD : 0;
10787
1d187b34
BW		 10788 boot_mode = SHMEM_RD(bp,
10789 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10790 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10791 switch (boot_mode) {
10792 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10793 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10794 break;
10795 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10796 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10797 break;
10798 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10799 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10800 break;
10801 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10802 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10803 break;
10804 }
10805
29ed74c3 10806 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 10807 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10808
72ce58c3 10809 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 10810 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 10811
10812 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10813 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10814 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10815 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10816
cdaa7cb8
VZ		 10817 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10818 val, val2, val3, val4);
34f80b04
EG		 10819}
10820
f2e0899f
DK		 10821#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10822#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10823
0329aba1 10824static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 10825{
10826 int pfid = BP_FUNC(bp);
f2e0899f
DK		 10827 int igu_sb_id;
10828 u32 val;
6383c0b3 10829 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 10830
10831 bp->igu_base_sb = 0xff;
f2e0899f 10832 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 10833 int vn = BP_VN(bp);
6383c0b3 10834 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 10835 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10836 FP_SB_MAX_E1x;
10837
10838 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10839 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10840
9b341bb1 10841 return 0;
f2e0899f
DK		 10842 }
10843
10844 /* IGU in normal mode - read CAM */
10845 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10846 igu_sb_id++) {
10847 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10848 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10849 continue;
10850 fid = IGU_FID(val);
10851 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10852 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10853 continue;
10854 if (IGU_VEC(val) == 0)
10855 /* default status block */
10856 bp->igu_dsb_id = igu_sb_id;
10857 else {
10858 if (bp->igu_base_sb == 0xff)
10859 bp->igu_base_sb = igu_sb_id;
6383c0b3 10860 igu_sb_cnt++;
f2e0899f
DK		 10861 }
10862 }
10863 }
619c5cb6 10864
6383c0b3 10865#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 10866 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10867 * optional that number of CAM entries will not be equal to the value
10868 * advertised in PCI.
10869 * Driver should use the minimal value of both as the actual status
10870 * block count
619c5cb6 10871 */
185d4c8b 10872 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 10873#endif
619c5cb6 10874
9b341bb1 10875 if (igu_sb_cnt == 0) {
f2e0899f 10876 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 10877 return -EINVAL;
10878 }
10879
10880 return 0;
f2e0899f
DK		 10881}
10882
1dd06ae8 10883static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 10884{
a22f0788
YR		 10885 int cfg_size = 0, idx, port = BP_PORT(bp);
10886
10887 /* Aggregation of supported attributes of all external phys */
10888 bp->port.supported[0] = 0;
10889 bp->port.supported[1] = 0;
b7737c9b
YR		 10890 switch (bp->link_params.num_phys) {
10891 case 1:
a22f0788
YR		 10892 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10893 cfg_size = 1;
10894 break;
b7737c9b 10895 case 2:
a22f0788
YR		 10896 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10897 cfg_size = 1;
10898 break;
10899 case 3:
10900 if (bp->link_params.multi_phy_config &
10901 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10902 bp->port.supported[1] =
10903 bp->link_params.phy[EXT_PHY1].supported;
10904 bp->port.supported[0] =
10905 bp->link_params.phy[EXT_PHY2].supported;
10906 } else {
10907 bp->port.supported[0] =
10908 bp->link_params.phy[EXT_PHY1].supported;
10909 bp->port.supported[1] =
10910 bp->link_params.phy[EXT_PHY2].supported;
10911 }
10912 cfg_size = 2;
10913 break;
b7737c9b 10914 }
a2fbb9ea 10915
a22f0788 10916 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 10917 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 10918 SHMEM_RD(bp,
a22f0788
YR		 10919 dev_info.port_hw_config[port].external_phy_config),
10920 SHMEM_RD(bp,
10921 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 10922 return;
f85582f8 10923 }
a2fbb9ea 10924
619c5cb6
VZ		 10925 if (CHIP_IS_E3(bp))
10926 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10927 else {
10928 switch (switch_cfg) {
10929 case SWITCH_CFG_1G:
10930 bp->port.phy_addr = REG_RD(
10931 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10932 break;
10933 case SWITCH_CFG_10G:
10934 bp->port.phy_addr = REG_RD(
10935 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10936 break;
10937 default:
10938 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10939 bp->port.link_config[0]);
10940 return;
10941 }
a2fbb9ea 10942 }
619c5cb6 10943 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 10944 /* mask what we support according to speed_cap_mask per configuration */
10945 for (idx = 0; idx < cfg_size; idx++) {
10946 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10947 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 10948 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 10949
a22f0788 10950 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10951 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 10952 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 10953
a22f0788 10954 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10955 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 10956 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 10957
a22f0788 10958 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10959 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 10960 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 10961
a22f0788 10962 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10963 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 10964 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 10965 SUPPORTED_1000baseT_Full);
a2fbb9ea 10966
a22f0788 10967 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10968 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 10969 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 10970
a22f0788 10971 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10972 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 10973 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 10974
10975 if (!(bp->link_params.speed_cap_mask[idx] &
10976 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10977 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 10978 }
a2fbb9ea 10979
a22f0788
YR		 10980 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10981 bp->port.supported[1]);
a2fbb9ea
ET		 10982}
10983
0329aba1 10984static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 10985{
a22f0788
YR		 10986 u32 link_config, idx, cfg_size = 0;
10987 bp->port.advertising[0] = 0;
10988 bp->port.advertising[1] = 0;
10989 switch (bp->link_params.num_phys) {
10990 case 1:
10991 case 2:
10992 cfg_size = 1;
10993 break;
10994 case 3:
10995 cfg_size = 2;
10996 break;
10997 }
10998 for (idx = 0; idx < cfg_size; idx++) {
10999 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11000 link_config = bp->port.link_config[idx];
11001 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 11002 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 11003 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11004 bp->link_params.req_line_speed[idx] =
11005 SPEED_AUTO_NEG;
11006 bp->port.advertising[idx] |=
11007 bp->port.supported[idx];
10bd1f24
MY		 11008 if (bp->link_params.phy[EXT_PHY1].type ==
11009 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11010 bp->port.advertising[idx] |=
11011 (SUPPORTED_100baseT_Half |
11012 SUPPORTED_100baseT_Full);
f85582f8
DK		 11013 } else {
11014 /* force 10G, no AN */
a22f0788
YR		 11015 bp->link_params.req_line_speed[idx] =
11016 SPEED_10000;
11017 bp->port.advertising[idx] |=
11018 (ADVERTISED_10000baseT_Full |
f85582f8 11019 ADVERTISED_FIBRE);
a22f0788 11020 continue;
f85582f8
DK		 11021 }
11022 break;
a2fbb9ea 11023
f85582f8 11024 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 11025 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11026 bp->link_params.req_line_speed[idx] =
11027 SPEED_10;
11028 bp->port.advertising[idx] |=
11029 (ADVERTISED_10baseT_Full |
f85582f8
DK		 11030 ADVERTISED_TP);
11031 } else {
51c1a580 11032 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 11033 link_config,
a22f0788 11034 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11035 return;
11036 }
11037 break;
a2fbb9ea 11038
f85582f8 11039 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 11040 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11041 bp->link_params.req_line_speed[idx] =
11042 SPEED_10;
11043 bp->link_params.req_duplex[idx] =
11044 DUPLEX_HALF;
11045 bp->port.advertising[idx] |=
11046 (ADVERTISED_10baseT_Half |
f85582f8
DK		 11047 ADVERTISED_TP);
11048 } else {
51c1a580 11049 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11050 link_config,
11051 bp->link_params.speed_cap_mask[idx]);
11052 return;
11053 }
11054 break;
a2fbb9ea 11055
f85582f8
DK		 11056 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11057 if (bp->port.supported[idx] &
11058 SUPPORTED_100baseT_Full) {
a22f0788
YR		 11059 bp->link_params.req_line_speed[idx] =
11060 SPEED_100;
11061 bp->port.advertising[idx] |=
11062 (ADVERTISED_100baseT_Full |
f85582f8
DK		 11063 ADVERTISED_TP);
11064 } else {
51c1a580 11065 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11066 link_config,
11067 bp->link_params.speed_cap_mask[idx]);
11068 return;
11069 }
11070 break;
a2fbb9ea 11071
f85582f8
DK		 11072 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11073 if (bp->port.supported[idx] &
11074 SUPPORTED_100baseT_Half) {
11075 bp->link_params.req_line_speed[idx] =
11076 SPEED_100;
11077 bp->link_params.req_duplex[idx] =
11078 DUPLEX_HALF;
a22f0788
YR		 11079 bp->port.advertising[idx] |=
11080 (ADVERTISED_100baseT_Half |
f85582f8
DK		 11081 ADVERTISED_TP);
11082 } else {
51c1a580 11083 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11084 link_config,
11085 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11086 return;
11087 }
11088 break;
a2fbb9ea 11089
f85582f8 11090 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 11091 if (bp->port.supported[idx] &
11092 SUPPORTED_1000baseT_Full) {
11093 bp->link_params.req_line_speed[idx] =
11094 SPEED_1000;
11095 bp->port.advertising[idx] |=
11096 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 11097 ADVERTISED_TP);
11098 } else {
51c1a580 11099 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11100 link_config,
11101 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11102 return;
11103 }
11104 break;
a2fbb9ea 11105
f85582f8 11106 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 11107 if (bp->port.supported[idx] &
11108 SUPPORTED_2500baseX_Full) {
11109 bp->link_params.req_line_speed[idx] =
11110 SPEED_2500;
11111 bp->port.advertising[idx] |=
11112 (ADVERTISED_2500baseX_Full |
34f80b04 11113 ADVERTISED_TP);
f85582f8 11114 } else {
51c1a580 11115 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11116 link_config,
f85582f8
DK		 11117 bp->link_params.speed_cap_mask[idx]);
11118 return;
11119 }
11120 break;
a2fbb9ea 11121
f85582f8 11122 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 11123 if (bp->port.supported[idx] &
11124 SUPPORTED_10000baseT_Full) {
11125 bp->link_params.req_line_speed[idx] =
11126 SPEED_10000;
11127 bp->port.advertising[idx] |=
11128 (ADVERTISED_10000baseT_Full |
34f80b04 11129 ADVERTISED_FIBRE);
f85582f8 11130 } else {
51c1a580 11131 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11132 link_config,
f85582f8
DK		 11133 bp->link_params.speed_cap_mask[idx]);
11134 return;
11135 }
11136 break;
3c9ada22
YR		 11137 case PORT_FEATURE_LINK_SPEED_20G:
11138 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 11139
3c9ada22 11140 break;
f85582f8 11141 default:
51c1a580 11142 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 11143 link_config);
f85582f8
DK		 11144 bp->link_params.req_line_speed[idx] =
11145 SPEED_AUTO_NEG;
11146 bp->port.advertising[idx] =
11147 bp->port.supported[idx];
11148 break;
11149 }
a2fbb9ea 11150
a22f0788 11151 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 11152 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 11153 if (bp->link_params.req_flow_ctrl[idx] ==
11154 BNX2X_FLOW_CTRL_AUTO) {
11155 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11156 bp->link_params.req_flow_ctrl[idx] =
11157 BNX2X_FLOW_CTRL_NONE;
11158 else
11159 bnx2x_set_requested_fc(bp);
a22f0788 11160 }
a2fbb9ea 11161
51c1a580 11162 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 11163 bp->link_params.req_line_speed[idx],
11164 bp->link_params.req_duplex[idx],
11165 bp->link_params.req_flow_ctrl[idx],
11166 bp->port.advertising[idx]);
11167 }
a2fbb9ea
ET		 11168}
11169
0329aba1 11170static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 11171{
86564c3f
YM		 11172 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11173 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11174 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11175 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 11176}
11177
0329aba1 11178static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 11179{
34f80b04 11180 int port = BP_PORT(bp);
589abe3a 11181 u32 config;
c8c60d88 11182 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 11183
c18487ee 11184 bp->link_params.bp = bp;
34f80b04 11185 bp->link_params.port = port;
c18487ee 11186
c18487ee 11187 bp->link_params.lane_config =
a2fbb9ea 11188 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 11189
a22f0788 11190 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 11191 SHMEM_RD(bp,
b0261926
YR		 11192 dev_info.port_hw_config[port].speed_capability_mask) &
11193 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 11194 bp->link_params.speed_cap_mask[1] =
11195 SHMEM_RD(bp,
b0261926
YR		 11196 dev_info.port_hw_config[port].speed_capability_mask2) &
11197 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 11198 bp->port.link_config[0] =
a2fbb9ea
ET		 11199 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11200
a22f0788
YR		 11201 bp->port.link_config[1] =
11202 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 11203
a22f0788
YR		 11204 bp->link_params.multi_phy_config =
11205 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 11206 /* If the device is capable of WoL, set the default state according
11207 * to the HW
11208 */
4d295db0 11209 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 11210 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11211 (config & PORT_FEATURE_WOL_ENABLED));
11212
4ba7699b
YM		 11213 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11214 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11215 bp->flags |= NO_ISCSI_FLAG;
11216 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11217 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11218 bp->flags |= NO_FCOE_FLAG;
11219
51c1a580 11220 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11221 bp->link_params.lane_config,
a22f0788
YR		 11222 bp->link_params.speed_cap_mask[0],
11223 bp->port.link_config[0]);
a2fbb9ea 11224
a22f0788 11225 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11226 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11227 bnx2x_phy_probe(&bp->link_params);
c18487ee 11228 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11229
11230 bnx2x_link_settings_requested(bp);
11231
01cd4528
EG		 11232 /*
11233 * If connected directly, work with the internal PHY, otherwise, work
11234 * with the external PHY
11235 */
b7737c9b
YR		 11236 ext_phy_config =
11237 SHMEM_RD(bp,
11238 dev_info.port_hw_config[port].external_phy_config);
11239 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11240 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11241 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11242
11243 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11244 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11245 bp->mdio.prtad =
b7737c9b 11246 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11247
c8c60d88
YM		 11248 /* Configure link feature according to nvram value */
11249 eee_mode = (((SHMEM_RD(bp, dev_info.
11250 port_feature_config[port].eee_power_mode)) &
11251 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11252 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11253 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11254 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11255 EEE_MODE_ENABLE_LPI |
11256 EEE_MODE_OUTPUT_TIME;
11257 } else {
11258 bp->link_params.eee_mode = 0;
11259 }
0793f83f 11260}
01cd4528 11261
b306f5ed 11262void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11263{
9e62e912 11264 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11265 int port = BP_PORT(bp);
2ba45142 11266 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11267 drv_lic_key[port].max_iscsi_conn);
2ba45142 11268
55c11941
MS		 11269 if (!CNIC_SUPPORT(bp)) {
11270 bp->flags |= no_flags;
11271 return;
11272 }
11273
b306f5ed 11274 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11275 bp->cnic_eth_dev.max_iscsi_conn =
11276 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11277 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11278
b306f5ed
DK		 11279 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11280 bp->cnic_eth_dev.max_iscsi_conn);
11281
11282 /*
11283 * If maximum allowed number of connections is zero -
11284 * disable the feature.
11285 */
11286 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11287 bp->flags |= no_flags;
b306f5ed
DK		 11288}
11289
0329aba1 11290static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11291{
11292 /* Port info */
11293 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11294 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11295 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11296 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11297
11298 /* Node info */
11299 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11300 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11301 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11302 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11303}
86800194
DK		 11304
11305static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11306{
11307 u8 count = 0;
11308
11309 if (IS_MF(bp)) {
11310 u8 fid;
11311
11312 /* iterate over absolute function ids for this path: */
11313 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11314 if (IS_MF_SD(bp)) {
11315 u32 cfg = MF_CFG_RD(bp,
11316 func_mf_config[fid].config);
11317
11318 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11319 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11320 FUNC_MF_CFG_PROTOCOL_FCOE))
11321 count++;
11322 } else {
11323 u32 cfg = MF_CFG_RD(bp,
11324 func_ext_config[fid].
11325 func_cfg);
11326
11327 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11328 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11329 count++;
11330 }
11331 }
11332 } else { /* SF */
11333 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11334
11335 for (port = 0; port < port_cnt; port++) {
11336 u32 lic = SHMEM_RD(bp,
11337 drv_lic_key[port].max_fcoe_conn) ^
11338 FW_ENCODE_32BIT_PATTERN;
11339 if (lic)
11340 count++;
11341 }
11342 }
11343
11344 return count;
11345}
11346
0329aba1 11347static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11348{
11349 int port = BP_PORT(bp);
11350 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11351 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11352 drv_lic_key[port].max_fcoe_conn);
86800194 11353 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11354
55c11941
MS		 11355 if (!CNIC_SUPPORT(bp)) {
11356 bp->flags |= NO_FCOE_FLAG;
11357 return;
11358 }
11359
b306f5ed 11360 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11361 bp->cnic_eth_dev.max_fcoe_conn =
11362 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11363 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11364
0eb43b4b
BPG		 11365 /* Calculate the number of maximum allowed FCoE tasks */
11366 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11367
11368 /* check if FCoE resources must be shared between different functions */
11369 if (num_fcoe_func)
11370 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11371
bf61ee14
VZ		 11372 /* Read the WWN: */
11373 if (!IS_MF(bp)) {
11374 /* Port info */
11375 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11376 SHMEM_RD(bp,
2de67439 11377 dev_info.port_hw_config[port].
bf61ee14
VZ		 11378 fcoe_wwn_port_name_upper);
11379 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11380 SHMEM_RD(bp,
2de67439 11381 dev_info.port_hw_config[port].
bf61ee14
VZ		 11382 fcoe_wwn_port_name_lower);
11383
11384 /* Node info */
11385 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11386 SHMEM_RD(bp,
2de67439 11387 dev_info.port_hw_config[port].
bf61ee14
VZ		 11388 fcoe_wwn_node_name_upper);
11389 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11390 SHMEM_RD(bp,
2de67439 11391 dev_info.port_hw_config[port].
bf61ee14
VZ		 11392 fcoe_wwn_node_name_lower);
11393 } else if (!IS_MF_SD(bp)) {
bf61ee14
VZ		 11394 /*
11395 * Read the WWN info only if the FCoE feature is enabled for
11396 * this function.
11397 */
7b5342d9 11398 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912
DK		 11399 bnx2x_get_ext_wwn_info(bp, func);
11400
382e513a 11401 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
9e62e912 11402 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11403 }
bf61ee14 11404
b306f5ed 11405 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11406
bf61ee14
VZ		 11407 /*
11408 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11409 * disable the feature.
11410 */
2ba45142
VZ		 11411 if (!bp->cnic_eth_dev.max_fcoe_conn)
11412 bp->flags |= NO_FCOE_FLAG;
11413}
b306f5ed 11414
0329aba1 11415static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11416{
11417 /*
11418 * iSCSI may be dynamically disabled but reading
11419 * info here we will decrease memory usage by driver
11420 * if the feature is disabled for good
11421 */
11422 bnx2x_get_iscsi_info(bp);
11423 bnx2x_get_fcoe_info(bp);
11424}
2ba45142 11425
0329aba1 11426static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11427{
11428 u32 val, val2;
11429 int func = BP_ABS_FUNC(bp);
11430 int port = BP_PORT(bp);
2ba45142
VZ		 11431 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11432 u8 *fip_mac = bp->fip_mac;
0793f83f 11433
55c11941
MS		 11434 if (IS_MF(bp)) {
11435 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11436 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11437 * In non SD mode features configuration comes from struct
11438 * func_ext_config.
2ba45142 11439 */
55c11941 11440 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
0793f83f
DK		 11441 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11442 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11443 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11444 iscsi_mac_addr_upper);
0793f83f 11445 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11446 iscsi_mac_addr_lower);
2ba45142 11447 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11448 BNX2X_DEV_INFO
11449 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11450 } else {
2ba45142 11451 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11452 }
2ba45142
VZ		 11453
11454 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11455 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11456 fcoe_mac_addr_upper);
2ba45142 11457 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11458 fcoe_mac_addr_lower);
2ba45142 11459 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11460 BNX2X_DEV_INFO
11461 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11462 } else {
2ba45142 11463 bp->flags |= NO_FCOE_FLAG;
55c11941 11464 }
a3348722
BW		 11465
11466 bp->mf_ext_config = cfg;
11467
9e62e912 11468 } else { /* SD MODE */
55c11941
MS		 11469 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11470 /* use primary mac as iscsi mac */
11471 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11472
11473 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11474 BNX2X_DEV_INFO
11475 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11476 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11477 /* use primary mac as fip mac */
11478 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11479 BNX2X_DEV_INFO("SD FCoE MODE\n");
11480 BNX2X_DEV_INFO
11481 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11482 }
0793f83f 11483 }
a3348722 11484
82594f8f
YM		 11485 /* If this is a storage-only interface, use SAN mac as
11486 * primary MAC. Notice that for SD this is already the case,
11487 * as the SAN mac was copied from the primary MAC.
11488 */
11489 if (IS_MF_FCOE_AFEX(bp))
a3348722 11490 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11491 } else {
0793f83f 11492 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11493 iscsi_mac_upper);
0793f83f 11494 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11495 iscsi_mac_lower);
2ba45142 11496 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11497
11498 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11499 fcoe_fip_mac_upper);
c03bd39c 11500 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11501 fcoe_fip_mac_lower);
c03bd39c 11502 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11503 }
11504
55c11941 11505 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11506 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11507 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
426b9241
DK		 11508 memset(iscsi_mac, 0, ETH_ALEN);
11509 }
11510
55c11941 11511 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11512 if (!is_valid_ether_addr(fip_mac)) {
11513 bp->flags |= NO_FCOE_FLAG;
11514 memset(bp->fip_mac, 0, ETH_ALEN);
11515 }
55c11941
MS		 11516}
11517
0329aba1 11518static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11519{
11520 u32 val, val2;
11521 int func = BP_ABS_FUNC(bp);
11522 int port = BP_PORT(bp);
11523
11524 /* Zero primary MAC configuration */
11525 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11526
11527 if (BP_NOMCP(bp)) {
11528 BNX2X_ERROR("warning: random MAC workaround active\n");
11529 eth_hw_addr_random(bp->dev);
11530 } else if (IS_MF(bp)) {
11531 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11532 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11533 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11534 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11535 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11536
11537 if (CNIC_SUPPORT(bp))
11538 bnx2x_get_cnic_mac_hwinfo(bp);
11539 } else {
11540 /* in SF read MACs from port configuration */
11541 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11542 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11543 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11544
11545 if (CNIC_SUPPORT(bp))
11546 bnx2x_get_cnic_mac_hwinfo(bp);
11547 }
11548
3d7d562c
YM		 11549 if (!BP_NOMCP(bp)) {
11550 /* Read physical port identifier from shmem */
11551 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11552 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11553 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11554 bp->flags |= HAS_PHYS_PORT_ID;
11555 }
11556
55c11941 11557 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11558
614c76df 11559 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6 11560 dev_err(&bp->pdev->dev,
51c1a580
MS		 11561 "bad Ethernet MAC address configuration: %pM\n"
11562 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11563 bp->dev->dev_addr);
7964211d 11564}
51c1a580 11565
0329aba1 11566static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11567{
11568 int tmp;
11569 u32 cfg;
51c1a580 11570
aeeddb8b
YM		 11571 if (IS_VF(bp))
11572 return 0;
11573
7964211d
YM		 11574 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11575 /* Take function: tmp = func */
11576 tmp = BP_ABS_FUNC(bp);
11577 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11578 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11579 } else {
11580 /* Take port: tmp = port */
11581 tmp = BP_PORT(bp);
11582 cfg = SHMEM_RD(bp,
11583 dev_info.port_hw_config[tmp].generic_features);
11584 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11585 }
11586 return cfg;
34f80b04
EG		 11587}
11588
0329aba1 11589static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11590{
0793f83f 11591 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 11592 int vn;
0793f83f 11593 u32 val = 0;
34f80b04 11594 int rc = 0;
a2fbb9ea 11595
34f80b04 11596 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11597
6383c0b3
AE		 11598 /*
11599 * initialize IGU parameters
11600 */
f2e0899f
DK		 11601 if (CHIP_IS_E1x(bp)) {
11602 bp->common.int_block = INT_BLOCK_HC;
11603
11604 bp->igu_dsb_id = DEF_SB_IGU_ID;
11605 bp->igu_base_sb = 0;
f2e0899f
DK		 11606 } else {
11607 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 11608
16a5fd92 11609 /* do not allow device reset during IGU info processing */
7a06a122
DK		 11610 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11611
f2e0899f 11612 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 11613
11614 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11615 int tout = 5000;
11616
11617 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11618
11619 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11620 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11621 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11622
11623 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11624 tout--;
0926d499 11625 usleep_range(1000, 2000);
619c5cb6
VZ		 11626 }
11627
11628 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11629 dev_err(&bp->pdev->dev,
11630 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 11631 bnx2x_release_hw_lock(bp,
11632 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 11633 return -EPERM;
11634 }
11635 }
11636
f2e0899f 11637 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 11638 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 11639 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11640 } else
619c5cb6 11641 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 11642
9b341bb1 11643 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 11644 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 11645 if (rc)
11646 return rc;
f2e0899f 11647 }
619c5cb6
VZ		 11648
11649 /*
11650 * set base FW non-default (fast path) status block id, this value is
11651 * used to initialize the fw_sb_id saved on the fp/queue structure to
11652 * determine the id used by the FW.
11653 */
11654 if (CHIP_IS_E1x(bp))
11655 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11656 else /*
11657 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11658 * the same queue are indicated on the same IGU SB). So we prefer
11659 * FW and IGU SBs to be the same value.
11660 */
11661 bp->base_fw_ndsb = bp->igu_base_sb;
11662
11663 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11664 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11665 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 11666
11667 /*
11668 * Initialize MF configuration
11669 */
523224a3 11670
fb3bff17
DK		 11671 bp->mf_ov = 0;
11672 bp->mf_mode = 0;
3395a033 11673 vn = BP_VN(bp);
0793f83f 11674
f2e0899f 11675 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 11676 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11677 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11678 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11679
f2e0899f
DK		 11680 if (SHMEM2_HAS(bp, mf_cfg_addr))
11681 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11682 else
11683 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 11684 offsetof(struct shmem_region, func_mb) +
11685 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 11686 /*
11687 * get mf configuration:
16a5fd92 11688 * 1. Existence of MF configuration
0793f83f
DK		 11689 * 2. MAC address must be legal (check only upper bytes)
11690 * for Switch-Independent mode;
11691 * OVLAN must be legal for Switch-Dependent mode
11692 * 3. SF_MODE configures specific MF mode
11693 */
11694 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11695 /* get mf configuration */
11696 val = SHMEM_RD(bp,
11697 dev_info.shared_feature_config.config);
11698 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11699
11700 switch (val) {
11701 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11702 val = MF_CFG_RD(bp, func_mf_config[func].
11703 mac_upper);
11704 /* check for legal mac (upper bytes)*/
11705 if (val != 0xffff) {
11706 bp->mf_mode = MULTI_FUNCTION_SI;
11707 bp->mf_config[vn] = MF_CFG_RD(bp,
11708 func_mf_config[func].config);
11709 } else
51c1a580 11710 BNX2X_DEV_INFO("illegal MAC address for SI\n");
0793f83f 11711 break;
a3348722
BW		 11712 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11713 if ((!CHIP_IS_E1x(bp)) &&
11714 (MF_CFG_RD(bp, func_mf_config[func].
11715 mac_upper) != 0xffff) &&
11716 (SHMEM2_HAS(bp,
11717 afex_driver_support))) {
11718 bp->mf_mode = MULTI_FUNCTION_AFEX;
11719 bp->mf_config[vn] = MF_CFG_RD(bp,
11720 func_mf_config[func].config);
11721 } else {
11722 BNX2X_DEV_INFO("can not configure afex mode\n");
11723 }
11724 break;
0793f83f
DK		 11725 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11726 /* get OV configuration */
11727 val = MF_CFG_RD(bp,
11728 func_mf_config[FUNC_0].e1hov_tag);
11729 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11730
11731 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11732 bp->mf_mode = MULTI_FUNCTION_SD;
11733 bp->mf_config[vn] = MF_CFG_RD(bp,
11734 func_mf_config[func].config);
11735 } else
754a2f52 11736 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 11737 break;
3786b942
AE		 11738 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11739 bp->mf_config[vn] = 0;
11740 break;
0793f83f
DK		 11741 default:
11742 /* Unknown configuration: reset mf_config */
11743 bp->mf_config[vn] = 0;
51c1a580 11744 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 11745 }
11746 }
a2fbb9ea 11747
2691d51d 11748 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 11749 IS_MF(bp) ? "multi" : "single");
2691d51d 11750
0793f83f
DK		 11751 switch (bp->mf_mode) {
11752 case MULTI_FUNCTION_SD:
11753 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11754 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 11755 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 11756 bp->mf_ov = val;
619c5cb6
VZ		 11757 bp->path_has_ovlan = true;
11758
51c1a580
MS		 11759 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11760 func, bp->mf_ov, bp->mf_ov);
2691d51d 11761 } else {
619c5cb6 11762 dev_err(&bp->pdev->dev,
51c1a580
MS		 11763 "No valid MF OV for func %d, aborting\n",
11764 func);
619c5cb6 11765 return -EPERM;
34f80b04 11766 }
0793f83f 11767 break;
a3348722
BW		 11768 case MULTI_FUNCTION_AFEX:
11769 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11770 break;
0793f83f 11771 case MULTI_FUNCTION_SI:
51c1a580
MS		 11772 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11773 func);
0793f83f
DK		 11774 break;
11775 default:
11776 if (vn) {
619c5cb6 11777 dev_err(&bp->pdev->dev,
51c1a580
MS		 11778 "VN %d is in a single function mode, aborting\n",
11779 vn);
619c5cb6 11780 return -EPERM;
2691d51d 11781 }
0793f83f 11782 break;
34f80b04 11783 }
0793f83f 11784
619c5cb6
VZ		 11785 /* check if other port on the path needs ovlan:
11786 * Since MF configuration is shared between ports
11787 * Possible mixed modes are only
11788 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11789 */
11790 if (CHIP_MODE_IS_4_PORT(bp) &&
11791 !bp->path_has_ovlan &&
11792 !IS_MF(bp) &&
11793 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11794 u8 other_port = !BP_PORT(bp);
11795 u8 other_func = BP_PATH(bp) + 2*other_port;
11796 val = MF_CFG_RD(bp,
11797 func_mf_config[other_func].e1hov_tag);
11798 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11799 bp->path_has_ovlan = true;
11800 }
34f80b04 11801 }
a2fbb9ea 11802
e848582c
DK		 11803 /* adjust igu_sb_cnt to MF for E1H */
11804 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11805 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 11806
619c5cb6
VZ		 11807 /* port info */
11808 bnx2x_get_port_hwinfo(bp);
f2e0899f 11809
0793f83f
DK		 11810 /* Get MAC addresses */
11811 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 11812
2ba45142 11813 bnx2x_get_cnic_info(bp);
2ba45142 11814
34f80b04
EG		 11815 return rc;
11816}
11817
0329aba1 11818static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 11819{
11820 int cnt, i, block_end, rodi;
fcdf95cb 11821 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 11822 char str_id_reg[VENDOR_ID_LEN+1];
11823 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 11824 char *vpd_data;
11825 char *vpd_extended_data = NULL;
34f24c7f
VZ		 11826 u8 len;
11827
fcdf95cb 11828 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 11829 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11830
11831 if (cnt < BNX2X_VPD_LEN)
11832 goto out_not_found;
11833
fcdf95cb
BW		 11834 /* VPD RO tag should be first tag after identifier string, hence
11835 * we should be able to find it in first BNX2X_VPD_LEN chars
11836 */
11837 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 11838 PCI_VPD_LRDT_RO_DATA);
11839 if (i < 0)
11840 goto out_not_found;
11841
34f24c7f 11842 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 11843 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 11844
11845 i += PCI_VPD_LRDT_TAG_SIZE;
11846
fcdf95cb
BW		 11847 if (block_end > BNX2X_VPD_LEN) {
11848 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11849 if (vpd_extended_data == NULL)
11850 goto out_not_found;
11851
11852 /* read rest of vpd image into vpd_extended_data */
11853 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11854 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11855 block_end - BNX2X_VPD_LEN,
11856 vpd_extended_data + BNX2X_VPD_LEN);
11857 if (cnt < (block_end - BNX2X_VPD_LEN))
11858 goto out_not_found;
11859 vpd_data = vpd_extended_data;
11860 } else
11861 vpd_data = vpd_start;
11862
11863 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 11864
11865 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11866 PCI_VPD_RO_KEYWORD_MFR_ID);
11867 if (rodi < 0)
11868 goto out_not_found;
11869
11870 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11871
11872 if (len != VENDOR_ID_LEN)
11873 goto out_not_found;
11874
11875 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11876
11877 /* vendor specific info */
11878 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11879 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11880 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11881 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11882
11883 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11884 PCI_VPD_RO_KEYWORD_VENDOR0);
11885 if (rodi >= 0) {
11886 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11887
11888 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11889
11890 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11891 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11892 bp->fw_ver[len] = ' ';
11893 }
11894 }
fcdf95cb 11895 kfree(vpd_extended_data);
34f24c7f
VZ		 11896 return;
11897 }
11898out_not_found:
fcdf95cb 11899 kfree(vpd_extended_data);
34f24c7f
VZ		 11900 return;
11901}
11902
0329aba1 11903static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 11904{
11905 u32 flags = 0;
11906
11907 if (CHIP_REV_IS_FPGA(bp))
11908 SET_FLAGS(flags, MODE_FPGA);
11909 else if (CHIP_REV_IS_EMUL(bp))
11910 SET_FLAGS(flags, MODE_EMUL);
11911 else
11912 SET_FLAGS(flags, MODE_ASIC);
11913
11914 if (CHIP_MODE_IS_4_PORT(bp))
11915 SET_FLAGS(flags, MODE_PORT4);
11916 else
11917 SET_FLAGS(flags, MODE_PORT2);
11918
11919 if (CHIP_IS_E2(bp))
11920 SET_FLAGS(flags, MODE_E2);
11921 else if (CHIP_IS_E3(bp)) {
11922 SET_FLAGS(flags, MODE_E3);
11923 if (CHIP_REV(bp) == CHIP_REV_Ax)
11924 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 11925 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11926 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 11927 }
11928
11929 if (IS_MF(bp)) {
11930 SET_FLAGS(flags, MODE_MF);
11931 switch (bp->mf_mode) {
11932 case MULTI_FUNCTION_SD:
11933 SET_FLAGS(flags, MODE_MF_SD);
11934 break;
11935 case MULTI_FUNCTION_SI:
11936 SET_FLAGS(flags, MODE_MF_SI);
11937 break;
a3348722
BW		 11938 case MULTI_FUNCTION_AFEX:
11939 SET_FLAGS(flags, MODE_MF_AFEX);
11940 break;
619c5cb6
VZ		 11941 }
11942 } else
11943 SET_FLAGS(flags, MODE_SF);
11944
11945#if defined(__LITTLE_ENDIAN)
11946 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11947#else /*(__BIG_ENDIAN)*/
11948 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11949#endif
11950 INIT_MODE_FLAGS(bp) = flags;
11951}
11952
0329aba1 11953static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 11954{
f2e0899f 11955 int func;
34f80b04
EG		 11956 int rc;
11957
34f80b04 11958 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 11959 mutex_init(&bp->fw_mb_mutex);
42f8277f
YM		 11960 mutex_init(&bp->drv_info_mutex);
11961 bp->drv_info_mng_owner = false;
bb7e95c8 11962 spin_lock_init(&bp->stats_lock);
507393eb 11963 sema_init(&bp->stats_sema, 1);
55c11941 11964
1cf167f2 11965 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 11966 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 11967 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
370d4a26 11968 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
1ab4434c
AE		 11969 if (IS_PF(bp)) {
11970 rc = bnx2x_get_hwinfo(bp);
11971 if (rc)
11972 return rc;
11973 } else {
e09b74d0 11974 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 11975 }
34f80b04 11976
619c5cb6
VZ		 11977 bnx2x_set_modes_bitmap(bp);
11978
11979 rc = bnx2x_alloc_mem_bp(bp);
11980 if (rc)
11981 return rc;
523224a3 11982
34f24c7f 11983 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 11984
11985 func = BP_FUNC(bp);
11986
34f80b04 11987 /* need to reset chip if undi was active */
1ab4434c 11988 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 11989 /* init fw_seq */
11990 bp->fw_seq =
11991 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11992 DRV_MSG_SEQ_NUMBER_MASK;
11993 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11994
91ebb929
YM		 11995 rc = bnx2x_prev_unload(bp);
11996 if (rc) {
11997 bnx2x_free_mem_bp(bp);
11998 return rc;
11999 }
452427b0
YM		 12000 }
12001
34f80b04 12002 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 12003 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 12004
12005 if (BP_NOMCP(bp) && (func == 0))
51c1a580 12006 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 12007
614c76df 12008 bp->disable_tpa = disable_tpa;
a3348722 12009 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
94d9de3c
MS		 12010 /* Reduce memory usage in kdump environment by disabling TPA */
12011 bp->disable_tpa |= reset_devices;
614c76df 12012
7a9b2557 12013 /* Set TPA flags */
614c76df 12014 if (bp->disable_tpa) {
621b4d66 12015 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 12016 bp->dev->features &= ~NETIF_F_LRO;
12017 } else {
621b4d66 12018 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 12019 bp->dev->features |= NETIF_F_LRO;
12020 }
12021
a18f5128
EG		 12022 if (CHIP_IS_E1(bp))
12023 bp->dropless_fc = 0;
12024 else
7964211d 12025 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 12026
8d5726c4 12027 bp->mrrs = mrrs;
7a9b2557 12028
a3348722 12029 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 12030 if (IS_VF(bp))
12031 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 12032
7d323bfd 12033 /* make sure that the numbers are in the right granularity */
523224a3
DK		 12034 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12035 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 12036
fc543637 12037 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 12038
12039 init_timer(&bp->timer);
12040 bp->timer.expires = jiffies + bp->current_interval;
12041 bp->timer.data = (unsigned long) bp;
12042 bp->timer.function = bnx2x_timer;
12043
0370cf90
BW		 12044 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12045 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12046 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12047 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12048 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12049 bnx2x_dcbx_init_params(bp);
12050 } else {
12051 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12052 }
e4901dde 12053
619c5cb6
VZ		 12054 if (CHIP_IS_E1x(bp))
12055 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12056 else
12057 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 12058
6383c0b3 12059 /* multiple tx priority */
1ab4434c
AE		 12060 if (IS_VF(bp))
12061 bp->max_cos = 1;
12062 else if (CHIP_IS_E1x(bp))
6383c0b3 12063 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 12064 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 12065 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 12066 else if (CHIP_IS_E3B0(bp))
6383c0b3 12067 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 12068 else
12069 BNX2X_ERR("unknown chip %x revision %x\n",
12070 CHIP_NUM(bp), CHIP_REV(bp));
12071 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 12072
55c11941
MS		 12073 /* We need at least one default status block for slow-path events,
12074 * second status block for the L2 queue, and a third status block for
16a5fd92 12075 * CNIC if supported.
55c11941 12076 */
60cad4e6
AE		 12077 if (IS_VF(bp))
12078 bp->min_msix_vec_cnt = 1;
12079 else if (CNIC_SUPPORT(bp))
55c11941 12080 bp->min_msix_vec_cnt = 3;
60cad4e6 12081 else /* PF w/o cnic */
55c11941
MS		 12082 bp->min_msix_vec_cnt = 2;
12083 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12084
5bb680d6
MS		 12085 bp->dump_preset_idx = 1;
12086
eeed018c
MK		 12087 if (CHIP_IS_E3B0(bp))
12088 bp->flags |= PTP_SUPPORTED;
12089
34f80b04 12090 return rc;
a2fbb9ea
ET		 12091}
12092
de0c62db
DK		 12093/****************************************************************************
12094* General service functions
12095****************************************************************************/
a2fbb9ea 12096
619c5cb6
VZ		 12097/*
12098 * net_device service functions
12099 */
12100
bb2a0f7a 12101/* called with rtnl_lock */
a2fbb9ea
ET		 12102static int bnx2x_open(struct net_device *dev)
12103{
12104 struct bnx2x *bp = netdev_priv(dev);
8395be5e 12105 int rc;
a2fbb9ea 12106
1355b704
MY		 12107 bp->stats_init = true;
12108
6eccabb3
EG		 12109 netif_carrier_off(dev);
12110
a2fbb9ea
ET		 12111 bnx2x_set_power_state(bp, PCI_D0);
12112
ad5afc89 12113 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 12114 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12115 * want the first function loaded on the current engine to
12116 * complete the recovery.
ad5afc89 12117 * Parity recovery is only relevant for PF driver.
c9ee9206 12118 */
ad5afc89 12119 if (IS_PF(bp)) {
1a6974b2
YM		 12120 int other_engine = BP_PATH(bp) ? 0 : 1;
12121 bool other_load_status, load_status;
12122 bool global = false;
12123
ad5afc89
AE		 12124 other_load_status = bnx2x_get_load_status(bp, other_engine);
12125 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12126 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12127 bnx2x_chk_parity_attn(bp, &global, true)) {
12128 do {
12129 /* If there are attentions and they are in a
12130 * global blocks, set the GLOBAL_RESET bit
12131 * regardless whether it will be this function
12132 * that will complete the recovery or not.
12133 */
12134 if (global)
12135 bnx2x_set_reset_global(bp);
72fd0718 12136
ad5afc89
AE		 12137 /* Only the first function on the current
12138 * engine should try to recover in open. In case
12139 * of attentions in global blocks only the first
12140 * in the chip should try to recover.
12141 */
12142 if ((!load_status &&
12143 (!global || !other_load_status)) &&
12144 bnx2x_trylock_leader_lock(bp) &&
12145 !bnx2x_leader_reset(bp)) {
12146 netdev_info(bp->dev,
12147 "Recovered in open\n");
12148 break;
12149 }
72fd0718 12150
ad5afc89
AE		 12151 /* recovery has failed... */
12152 bnx2x_set_power_state(bp, PCI_D3hot);
12153 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 12154
ad5afc89
AE		 12155 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12156 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 12157
ad5afc89
AE		 12158 return -EAGAIN;
12159 } while (0);
12160 }
12161 }
72fd0718
VZ		 12162
12163 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 12164 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12165 if (rc)
12166 return rc;
9a8130bc 12167 return 0;
a2fbb9ea
ET		 12168}
12169
bb2a0f7a 12170/* called with rtnl_lock */
56ad3152 12171static int bnx2x_close(struct net_device *dev)
a2fbb9ea 12172{
a2fbb9ea
ET		 12173 struct bnx2x *bp = netdev_priv(dev);
12174
12175 /* Unload the driver, release IRQs */
5d07d868 12176 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 12177
a2fbb9ea
ET		 12178 return 0;
12179}
12180
1191cb83
ED		 12181static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12182 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 12183{
619c5cb6
VZ		 12184 int mc_count = netdev_mc_count(bp->dev);
12185 struct bnx2x_mcast_list_elem *mc_mac =
cd2b0389 12186 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
619c5cb6 12187 struct netdev_hw_addr *ha;
6e30dd4e 12188
619c5cb6
VZ		 12189 if (!mc_mac)
12190 return -ENOMEM;
6e30dd4e 12191
619c5cb6 12192 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 12193
619c5cb6
VZ		 12194 netdev_for_each_mc_addr(ha, bp->dev) {
12195 mc_mac->mac = bnx2x_mc_addr(ha);
12196 list_add_tail(&mc_mac->link, &p->mcast_list);
12197 mc_mac++;
6e30dd4e 12198 }
619c5cb6
VZ		 12199
12200 p->mcast_list_len = mc_count;
12201
12202 return 0;
6e30dd4e
VZ		 12203}
12204
1191cb83 12205static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 12206 struct bnx2x_mcast_ramrod_params *p)
12207{
12208 struct bnx2x_mcast_list_elem *mc_mac =
12209 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12210 link);
12211
12212 WARN_ON(!mc_mac);
12213 kfree(mc_mac);
12214}
12215
12216/**
12217 * bnx2x_set_uc_list - configure a new unicast MACs list.
12218 *
12219 * @bp: driver handle
6e30dd4e 12220 *
619c5cb6 12221 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 12222 */
1191cb83 12223static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12224{
619c5cb6 12225 int rc;
6e30dd4e 12226 struct net_device *dev = bp->dev;
6e30dd4e 12227 struct netdev_hw_addr *ha;
15192a8c 12228 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12229 unsigned long ramrod_flags = 0;
6e30dd4e 12230
619c5cb6
VZ		 12231 /* First schedule a cleanup up of old configuration */
12232 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12233 if (rc < 0) {
12234 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12235 return rc;
12236 }
6e30dd4e
VZ		 12237
12238 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12239 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12240 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12241 if (rc == -EEXIST) {
12242 DP(BNX2X_MSG_SP,
12243 "Failed to schedule ADD operations: %d\n", rc);
12244 /* do not treat adding same MAC as error */
12245 rc = 0;
12246
12247 } else if (rc < 0) {
12248
619c5cb6
VZ		 12249 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12250 rc);
12251 return rc;
6e30dd4e
VZ		 12252 }
12253 }
12254
619c5cb6
VZ		 12255 /* Execute the pending commands */
12256 __set_bit(RAMROD_CONT, &ramrod_flags);
12257 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12258 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12259}
12260
1191cb83 12261static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 12262{
619c5cb6 12263 struct net_device *dev = bp->dev;
3b603066 12264 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12265 int rc = 0;
6e30dd4e 12266
619c5cb6 12267 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12268
619c5cb6
VZ		 12269 /* first, clear all configured multicast MACs */
12270 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12271 if (rc < 0) {
51c1a580 12272 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12273 return rc;
12274 }
6e30dd4e 12275
619c5cb6
VZ		 12276 /* then, configure a new MACs list */
12277 if (netdev_mc_count(dev)) {
12278 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12279 if (rc) {
51c1a580
MS		 12280 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12281 rc);
619c5cb6
VZ		 12282 return rc;
12283 }
6e30dd4e 12284
619c5cb6
VZ		 12285 /* Now add the new MACs */
12286 rc = bnx2x_config_mcast(bp, &rparam,
12287 BNX2X_MCAST_CMD_ADD);
12288 if (rc < 0)
51c1a580
MS		 12289 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12290 rc);
6e30dd4e 12291
619c5cb6
VZ		 12292 bnx2x_free_mcast_macs_list(&rparam);
12293 }
6e30dd4e 12294
619c5cb6 12295 return rc;
6e30dd4e
VZ		 12296}
12297
619c5cb6 12298/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12299static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12300{
12301 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12302
12303 if (bp->state != BNX2X_STATE_OPEN) {
12304 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12305 return;
8b09be5f
YM		 12306 } else {
12307 /* Schedule an SP task to handle rest of change */
230bb0f3
YM		 12308 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12309 NETIF_MSG_IFUP);
34f80b04 12310 }
8b09be5f
YM		 12311}
12312
12313void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12314{
12315 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12316
619c5cb6 12317 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12318
8b09be5f
YM		 12319 netif_addr_lock_bh(bp->dev);
12320
12321 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12322 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12323 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12324 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12325 CHIP_IS_E1(bp))) {
34f80b04 12326 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12327 } else {
381ac16b
AE		 12328 if (IS_PF(bp)) {
12329 /* some multicasts */
12330 if (bnx2x_set_mc_list(bp) < 0)
12331 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12332
8b09be5f
YM		 12333 /* release bh lock, as bnx2x_set_uc_list might sleep */
12334 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12335 if (bnx2x_set_uc_list(bp) < 0)
12336 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12337 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12338 } else {
12339 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12340 * wait for the pf's response).
381ac16b 12341 */
230bb0f3
YM		 12342 bnx2x_schedule_sp_rtnl(bp,
12343 BNX2X_SP_RTNL_VFPF_MCAST, 0);
381ac16b 12344 }
34f80b04
EG		 12345 }
12346
12347 bp->rx_mode = rx_mode;
614c76df
DK		 12348 /* handle ISCSI SD mode */
12349 if (IS_MF_ISCSI_SD(bp))
12350 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12351
12352 /* Schedule the rx_mode command */
12353 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12354 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12355 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12356 return;
12357 }
12358
381ac16b
AE		 12359 if (IS_PF(bp)) {
12360 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12361 netif_addr_unlock_bh(bp->dev);
381ac16b 12362 } else {
8b09be5f
YM		 12363 /* VF will need to request the PF to make this change, and so
12364 * the VF needs to release the bottom-half lock prior to the
12365 * request (as it will likely require sleep on the VF side)
381ac16b 12366 */
8b09be5f
YM		 12367 netif_addr_unlock_bh(bp->dev);
12368 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12369 }
34f80b04
EG		 12370}
12371
c18487ee 12372/* called with rtnl_lock */
01cd4528
EG		 12373static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12374 int devad, u16 addr)
a2fbb9ea 12375{
01cd4528
EG		 12376 struct bnx2x *bp = netdev_priv(netdev);
12377 u16 value;
12378 int rc;
a2fbb9ea 12379
01cd4528
EG		 12380 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12381 prtad, devad, addr);
a2fbb9ea 12382
01cd4528
EG		 12383 /* The HW expects different devad if CL22 is used */
12384 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12385
01cd4528 12386 bnx2x_acquire_phy_lock(bp);
e10bc84d 12387 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12388 bnx2x_release_phy_lock(bp);
12389 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12390
01cd4528
EG		 12391 if (!rc)
12392 rc = value;
12393 return rc;
12394}
a2fbb9ea 12395
01cd4528
EG		 12396/* called with rtnl_lock */
12397static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12398 u16 addr, u16 value)
12399{
12400 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12401 int rc;
12402
51c1a580
MS		 12403 DP(NETIF_MSG_LINK,
12404 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12405 prtad, devad, addr, value);
01cd4528 12406
01cd4528
EG		 12407 /* The HW expects different devad if CL22 is used */
12408 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12409
01cd4528 12410 bnx2x_acquire_phy_lock(bp);
e10bc84d 12411 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12412 bnx2x_release_phy_lock(bp);
12413 return rc;
12414}
c18487ee 12415
01cd4528
EG		 12416/* called with rtnl_lock */
12417static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12418{
12419 struct bnx2x *bp = netdev_priv(dev);
12420 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12421
01cd4528
EG		 12422 if (!netif_running(dev))
12423 return -EAGAIN;
12424
eeed018c
MK		 12425 switch (cmd) {
12426 case SIOCSHWTSTAMP:
12427 return bnx2x_hwtstamp_ioctl(bp, ifr);
12428 default:
12429 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12430 mdio->phy_id, mdio->reg_num, mdio->val_in);
12431 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12432 }
a2fbb9ea
ET		 12433}
12434
257ddbda 12435#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 12436static void poll_bnx2x(struct net_device *dev)
12437{
12438 struct bnx2x *bp = netdev_priv(dev);
14a15d61 12439 int i;
a2fbb9ea 12440
14a15d61
MS		 12441 for_each_eth_queue(bp, i) {
12442 struct bnx2x_fastpath *fp = &bp->fp[i];
12443 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12444 }
a2fbb9ea
ET		 12445}
12446#endif
12447
614c76df
DK		 12448static int bnx2x_validate_addr(struct net_device *dev)
12449{
12450 struct bnx2x *bp = netdev_priv(dev);
12451
e09b74d0
AE		 12452 /* query the bulletin board for mac address configured by the PF */
12453 if (IS_VF(bp))
12454 bnx2x_sample_bulletin(bp);
12455
51c1a580
MS		 12456 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12457 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12458 return -EADDRNOTAVAIL;
51c1a580 12459 }
614c76df
DK		 12460 return 0;
12461}
12462
3d7d562c
YM		 12463static int bnx2x_get_phys_port_id(struct net_device *netdev,
12464 struct netdev_phys_port_id *ppid)
12465{
12466 struct bnx2x *bp = netdev_priv(netdev);
12467
12468 if (!(bp->flags & HAS_PHYS_PORT_ID))
12469 return -EOPNOTSUPP;
12470
12471 ppid->id_len = sizeof(bp->phys_port_id);
12472 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12473
12474 return 0;
12475}
12476
c64213cd
SH		 12477static const struct net_device_ops bnx2x_netdev_ops = {
12478 .ndo_open = bnx2x_open,
12479 .ndo_stop = bnx2x_close,
12480 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 12481 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 12482 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 12483 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 12484 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 12485 .ndo_do_ioctl = bnx2x_ioctl,
12486 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 12487 .ndo_fix_features = bnx2x_fix_features,
12488 .ndo_set_features = bnx2x_set_features,
c64213cd 12489 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 12490#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 12491 .ndo_poll_controller = poll_bnx2x,
12492#endif
6383c0b3 12493 .ndo_setup_tc = bnx2x_setup_tc,
6411280a 12494#ifdef CONFIG_BNX2X_SRIOV
abc5a021 12495 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 12496 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 12497 .ndo_get_vf_config = bnx2x_get_vf_config,
6411280a 12498#endif
55c11941 12499#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 12500 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12501#endif
8f20aa57 12502
e0d1095a 12503#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 12504 .ndo_busy_poll = bnx2x_low_latency_recv,
8f20aa57 12505#endif
3d7d562c 12506 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
6495d15a 12507 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
c64213cd
SH		 12508};
12509
1191cb83 12510static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 12511{
12512 struct device *dev = &bp->pdev->dev;
12513
8ceafbfa
LT		 12514 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12515 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 12516 dev_err(dev, "System does not support DMA, aborting\n");
12517 return -EIO;
12518 }
12519
12520 return 0;
12521}
12522
33d8e6a5
YM		 12523static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12524{
12525 if (bp->flags & AER_ENABLED) {
12526 pci_disable_pcie_error_reporting(bp->pdev);
12527 bp->flags &= ~AER_ENABLED;
12528 }
12529}
12530
1ab4434c
AE		 12531static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12532 struct net_device *dev, unsigned long board_type)
a2fbb9ea 12533{
a2fbb9ea 12534 int rc;
c22610d0 12535 u32 pci_cfg_dword;
65087cfe
AE		 12536 bool chip_is_e1x = (board_type == BCM57710 ||
12537 board_type == BCM57711 ||
12538 board_type == BCM57711E);
a2fbb9ea
ET		 12539
12540 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 12541
34f80b04
EG		 12542 bp->dev = dev;
12543 bp->pdev = pdev;
a2fbb9ea
ET		 12544
12545 rc = pci_enable_device(pdev);
12546 if (rc) {
cdaa7cb8
VZ		 12547 dev_err(&bp->pdev->dev,
12548 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 12549 goto err_out;
12550 }
12551
12552 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 12553 dev_err(&bp->pdev->dev,
12554 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 12555 rc = -ENODEV;
12556 goto err_out_disable;
12557 }
12558
1ab4434c
AE		 12559 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12560 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 12561 rc = -ENODEV;
12562 goto err_out_disable;
12563 }
12564
092a5fc9
YR		 12565 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12566 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12567 PCICFG_REVESION_ID_ERROR_VAL) {
12568 pr_err("PCI device error, probably due to fan failure, aborting\n");
12569 rc = -ENODEV;
12570 goto err_out_disable;
12571 }
12572
34f80b04
EG		 12573 if (atomic_read(&pdev->enable_cnt) == 1) {
12574 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12575 if (rc) {
cdaa7cb8
VZ		 12576 dev_err(&bp->pdev->dev,
12577 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 12578 goto err_out_disable;
12579 }
a2fbb9ea 12580
34f80b04
EG		 12581 pci_set_master(pdev);
12582 pci_save_state(pdev);
12583 }
a2fbb9ea 12584
1ab4434c 12585 if (IS_PF(bp)) {
29ed74c3 12586 if (!pdev->pm_cap) {
1ab4434c
AE		 12587 dev_err(&bp->pdev->dev,
12588 "Cannot find power management capability, aborting\n");
12589 rc = -EIO;
12590 goto err_out_release;
12591 }
a2fbb9ea
ET		 12592 }
12593
77c98e6a 12594 if (!pci_is_pcie(pdev)) {
51c1a580 12595 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 12596 rc = -EIO;
12597 goto err_out_release;
12598 }
12599
619c5cb6
VZ		 12600 rc = bnx2x_set_coherency_mask(bp);
12601 if (rc)
a2fbb9ea 12602 goto err_out_release;
a2fbb9ea 12603
34f80b04
EG		 12604 dev->mem_start = pci_resource_start(pdev, 0);
12605 dev->base_addr = dev->mem_start;
12606 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 12607
12608 dev->irq = pdev->irq;
12609
275f165f 12610 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 12611 if (!bp->regview) {
cdaa7cb8
VZ		 12612 dev_err(&bp->pdev->dev,
12613 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 12614 rc = -ENOMEM;
12615 goto err_out_release;
12616 }
12617
c22610d0
AE		 12618 /* In E1/E1H use pci device function given by kernel.
12619 * In E2/E3 read physical function from ME register since these chips
12620 * support Physical Device Assignment where kernel BDF maybe arbitrary
12621 * (depending on hypervisor).
12622 */
2de67439 12623 if (chip_is_e1x) {
c22610d0 12624 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 12625 } else {
12626 /* chip is E2/3*/
c22610d0
AE		 12627 pci_read_config_dword(bp->pdev,
12628 PCICFG_ME_REGISTER, &pci_cfg_dword);
12629 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 12630 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 12631 }
51c1a580 12632 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 12633
34f80b04
EG		 12634 /* clean indirect addresses */
12635 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12636 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5
YM		 12637
12638 /* AER (Advanced Error reporting) configuration */
12639 rc = pci_enable_pcie_error_reporting(pdev);
12640 if (!rc)
12641 bp->flags |= AER_ENABLED;
12642 else
12643 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12644
a5c53dbc
DK		 12645 /*
12646 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 12647 * is not used by the driver.
12648 */
1ab4434c
AE		 12649 if (IS_PF(bp)) {
12650 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12651 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12652 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12653 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12654
12655 if (chip_is_e1x) {
12656 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12657 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12658 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12659 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12660 }
a5c53dbc 12661
1ab4434c
AE		 12662 /* Enable internal target-read (in case we are probed after PF
12663 * FLR). Must be done prior to any BAR read access. Only for
12664 * 57712 and up
12665 */
12666 if (!chip_is_e1x)
12667 REG_WR(bp,
12668 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 12669 }
a2fbb9ea 12670
34f80b04 12671 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 12672
c64213cd 12673 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 12674 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 12675
01789349
JP		 12676 dev->priv_flags |= IFF_UNICAST_FLT;
12677
66371c44 12678 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 12679 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12680 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
f646968f 12681 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a848ade4 12682 if (!CHIP_IS_E1x(bp)) {
117401ee 12683 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2e3bd6a4 12684 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
a848ade4
DK		 12685 dev->hw_enc_features =
12686 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12687 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
117401ee 12688 NETIF_F_GSO_IPIP |
2e3bd6a4 12689 NETIF_F_GSO_SIT |
65bc0cfe 12690 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
a848ade4 12691 }
66371c44
MM		 12692
12693 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12694 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12695
f646968f 12696 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 12697 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 12698
538dd2e3
MB		 12699 /* Add Loopback capability to the device */
12700 dev->hw_features |= NETIF_F_LOOPBACK;
12701
98507672 12702#ifdef BCM_DCBNL
785b9b1a
SR		 12703 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12704#endif
12705
01cd4528
EG		 12706 /* get_port_hwinfo() will set prtad and mmds properly */
12707 bp->mdio.prtad = MDIO_PRTAD_NONE;
12708 bp->mdio.mmds = 0;
12709 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12710 bp->mdio.dev = dev;
12711 bp->mdio.mdio_read = bnx2x_mdio_read;
12712 bp->mdio.mdio_write = bnx2x_mdio_write;
12713
a2fbb9ea
ET		 12714 return 0;
12715
a2fbb9ea 12716err_out_release:
34f80b04
EG		 12717 if (atomic_read(&pdev->enable_cnt) == 1)
12718 pci_release_regions(pdev);
a2fbb9ea
ET		 12719
12720err_out_disable:
12721 pci_disable_device(pdev);
a2fbb9ea
ET		 12722
12723err_out:
12724 return rc;
12725}
12726
6891dd25 12727static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 12728{
37f9ce62 12729 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 12730 struct bnx2x_fw_file_hdr *fw_hdr;
12731 struct bnx2x_fw_file_section *sections;
94a78b79 12732 u32 offset, len, num_ops;
86564c3f 12733 __be16 *ops_offsets;
94a78b79 12734 int i;
37f9ce62 12735 const u8 *fw_ver;
94a78b79 12736
51c1a580
MS		 12737 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12738 BNX2X_ERR("Wrong FW size\n");
94a78b79 12739 return -EINVAL;
51c1a580 12740 }
94a78b79
VZ		 12741
12742 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12743 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12744
12745 /* Make sure none of the offsets and sizes make us read beyond
12746 * the end of the firmware data */
12747 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12748 offset = be32_to_cpu(sections[i].offset);
12749 len = be32_to_cpu(sections[i].len);
12750 if (offset + len > firmware->size) {
51c1a580 12751 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 12752 return -EINVAL;
12753 }
12754 }
12755
12756 /* Likewise for the init_ops offsets */
12757 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 12758 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 12759 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12760
12761 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12762 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 12763 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 12764 return -EINVAL;
12765 }
12766 }
12767
12768 /* Check FW version */
12769 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12770 fw_ver = firmware->data + offset;
12771 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12772 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12773 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12774 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 12775 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12776 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12777 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 12778 BCM_5710_FW_MINOR_VERSION,
12779 BCM_5710_FW_REVISION_VERSION,
12780 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 12781 return -EINVAL;
94a78b79
VZ		 12782 }
12783
12784 return 0;
12785}
12786
1191cb83 12787static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12788{
ab6ad5a4
EG		 12789 const __be32 *source = (const __be32 *)_source;
12790 u32 *target = (u32 *)_target;
94a78b79 12791 u32 i;
94a78b79
VZ		 12792
12793 for (i = 0; i < n/4; i++)
12794 target[i] = be32_to_cpu(source[i]);
12795}
12796
12797/*
12798 Ops array is stored in the following format:
12799 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12800 */
1191cb83 12801static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 12802{
ab6ad5a4
EG		 12803 const __be32 *source = (const __be32 *)_source;
12804 struct raw_op *target = (struct raw_op *)_target;
94a78b79 12805 u32 i, j, tmp;
94a78b79 12806
ab6ad5a4 12807 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 12808 tmp = be32_to_cpu(source[j]);
12809 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 12810 target[i].offset = tmp & 0xffffff;
12811 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 12812 }
12813}
ab6ad5a4 12814
1aa8b471 12815/* IRO array is stored in the following format:
523224a3
DK		 12816 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12817 */
1191cb83 12818static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 12819{
12820 const __be32 *source = (const __be32 *)_source;
12821 struct iro *target = (struct iro *)_target;
12822 u32 i, j, tmp;
12823
12824 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12825 target[i].base = be32_to_cpu(source[j]);
12826 j++;
12827 tmp = be32_to_cpu(source[j]);
12828 target[i].m1 = (tmp >> 16) & 0xffff;
12829 target[i].m2 = tmp & 0xffff;
12830 j++;
12831 tmp = be32_to_cpu(source[j]);
12832 target[i].m3 = (tmp >> 16) & 0xffff;
12833 target[i].size = tmp & 0xffff;
12834 j++;
12835 }
12836}
12837
1191cb83 12838static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12839{
ab6ad5a4
EG		 12840 const __be16 *source = (const __be16 *)_source;
12841 u16 *target = (u16 *)_target;
94a78b79 12842 u32 i;
94a78b79
VZ		 12843
12844 for (i = 0; i < n/2; i++)
12845 target[i] = be16_to_cpu(source[i]);
12846}
12847
7995c64e
JP		 12848#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12849do { \
12850 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12851 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 12852 if (!bp->arr) \
7995c64e 12853 goto lbl; \
7995c64e
JP		 12854 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12855 (u8 *)bp->arr, len); \
12856} while (0)
94a78b79 12857
3b603066 12858static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 12859{
c0ea452e 12860 const char *fw_file_name;
94a78b79 12861 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 12862 int rc;
94a78b79 12863
c0ea452e
MS		 12864 if (bp->firmware)
12865 return 0;
94a78b79 12866
c0ea452e
MS		 12867 if (CHIP_IS_E1(bp))
12868 fw_file_name = FW_FILE_NAME_E1;
12869 else if (CHIP_IS_E1H(bp))
12870 fw_file_name = FW_FILE_NAME_E1H;
12871 else if (!CHIP_IS_E1x(bp))
12872 fw_file_name = FW_FILE_NAME_E2;
12873 else {
12874 BNX2X_ERR("Unsupported chip revision\n");
12875 return -EINVAL;
12876 }
12877 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 12878
c0ea452e
MS		 12879 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12880 if (rc) {
12881 BNX2X_ERR("Can't load firmware file %s\n",
12882 fw_file_name);
12883 goto request_firmware_exit;
12884 }
eb2afd4a 12885
c0ea452e
MS		 12886 rc = bnx2x_check_firmware(bp);
12887 if (rc) {
12888 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12889 goto request_firmware_exit;
94a78b79
VZ		 12890 }
12891
12892 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12893
12894 /* Initialize the pointers to the init arrays */
12895 /* Blob */
12896 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12897
12898 /* Opcodes */
12899 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12900
12901 /* Offsets */
ab6ad5a4
EG		 12902 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12903 be16_to_cpu_n);
94a78b79
VZ		 12904
12905 /* STORMs firmware */
573f2035
EG		 12906 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12907 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12908 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12909 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12910 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12911 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12912 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12913 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12914 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12915 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12916 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12917 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12918 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12919 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12920 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12921 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 12922 /* IRO */
12923 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 12924
12925 return 0;
ab6ad5a4 12926
523224a3
DK		 12927iro_alloc_err:
12928 kfree(bp->init_ops_offsets);
94a78b79
VZ		 12929init_offsets_alloc_err:
12930 kfree(bp->init_ops);
12931init_ops_alloc_err:
12932 kfree(bp->init_data);
12933request_firmware_exit:
12934 release_firmware(bp->firmware);
127d0a19 12935 bp->firmware = NULL;
94a78b79
VZ		 12936
12937 return rc;
12938}
12939
619c5cb6
VZ		 12940static void bnx2x_release_firmware(struct bnx2x *bp)
12941{
12942 kfree(bp->init_ops_offsets);
12943 kfree(bp->init_ops);
12944 kfree(bp->init_data);
12945 release_firmware(bp->firmware);
eb2afd4a 12946 bp->firmware = NULL;
619c5cb6
VZ		 12947}
12948
619c5cb6
VZ		 12949static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12950 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12951 .init_hw_cmn = bnx2x_init_hw_common,
12952 .init_hw_port = bnx2x_init_hw_port,
12953 .init_hw_func = bnx2x_init_hw_func,
12954
12955 .reset_hw_cmn = bnx2x_reset_common,
12956 .reset_hw_port = bnx2x_reset_port,
12957 .reset_hw_func = bnx2x_reset_func,
12958
12959 .gunzip_init = bnx2x_gunzip_init,
12960 .gunzip_end = bnx2x_gunzip_end,
12961
12962 .init_fw = bnx2x_init_firmware,
12963 .release_fw = bnx2x_release_firmware,
12964};
12965
12966void bnx2x__init_func_obj(struct bnx2x *bp)
12967{
12968 /* Prepare DMAE related driver resources */
12969 bnx2x_setup_dmae(bp);
12970
12971 bnx2x_init_func_obj(bp, &bp->func_obj,
12972 bnx2x_sp(bp, func_rdata),
12973 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 12974 bnx2x_sp(bp, func_afex_rdata),
12975 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 12976 &bnx2x_func_sp_drv);
12977}
12978
12979/* must be called after sriov-enable */
1191cb83 12980static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 12981{
37ae41a9 12982 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 12983
290ca2bb
AE		 12984 if (IS_SRIOV(bp))
12985 cid_count += BNX2X_VF_CIDS;
12986
55c11941
MS		 12987 if (CNIC_SUPPORT(bp))
12988 cid_count += CNIC_CID_MAX;
290ca2bb 12989
523224a3
DK		 12990 return roundup(cid_count, QM_CID_ROUND);
12991}
f85582f8 12992
619c5cb6 12993/**
6383c0b3 12994 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 12995 *
12996 * @dev: pci device
12997 *
12998 */
60cad4e6 12999static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 13000{
ae2104be 13001 int index;
1ab4434c 13002 u16 control = 0;
619c5cb6 13003
6383c0b3
AE		 13004 /*
13005 * If MSI-X is not supported - return number of SBs needed to support
13006 * one fast path queue: one FP queue + SB for CNIC
13007 */
ae2104be 13008 if (!pdev->msix_cap) {
1ab4434c 13009 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 13010 return 1 + cnic_cnt;
1ab4434c
AE		 13011 }
13012 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 13013
6383c0b3
AE		 13014 /*
13015 * The value in the PCI configuration space is the index of the last
13016 * entry, namely one less than the actual size of the table, which is
13017 * exactly what we want to return from this function: number of all SBs
13018 * without the default SB.
1ab4434c 13019 * For VFs there is no default SB, then we return (index+1).
6383c0b3 13020 */
73413ffa 13021 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
619c5cb6 13022
1ab4434c 13023 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 13024
60cad4e6 13025 return index;
1ab4434c 13026}
523224a3 13027
1ab4434c
AE		 13028static int set_max_cos_est(int chip_id)
13029{
13030 switch (chip_id) {
f2e0899f
DK		 13031 case BCM57710:
13032 case BCM57711:
13033 case BCM57711E:
1ab4434c 13034 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 13035 case BCM57712:
619c5cb6 13036 case BCM57712_MF:
1ab4434c 13037 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 13038 case BCM57800:
13039 case BCM57800_MF:
13040 case BCM57810:
13041 case BCM57810_MF:
c3def943
YM		 13042 case BCM57840_4_10:
13043 case BCM57840_2_20:
1ab4434c 13044 case BCM57840_O:
c3def943 13045 case BCM57840_MFO:
619c5cb6 13046 case BCM57840_MF:
7e8e02df
BW		 13047 case BCM57811:
13048 case BCM57811_MF:
1ab4434c 13049 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 13050 case BCM57712_VF:
13051 case BCM57800_VF:
13052 case BCM57810_VF:
13053 case BCM57840_VF:
13054 case BCM57811_VF:
1ab4434c 13055 return 1;
f2e0899f 13056 default:
1ab4434c 13057 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 13058 return -ENODEV;
f2e0899f 13059 }
1ab4434c 13060}
f2e0899f 13061
1ab4434c
AE		 13062static int set_is_vf(int chip_id)
13063{
13064 switch (chip_id) {
13065 case BCM57712_VF:
13066 case BCM57800_VF:
13067 case BCM57810_VF:
13068 case BCM57840_VF:
13069 case BCM57811_VF:
13070 return true;
13071 default:
13072 return false;
13073 }
13074}
6383c0b3 13075
eeed018c
MK		 13076/* nig_tsgen registers relative address */
13077#define tsgen_ctrl 0x0
13078#define tsgen_freecount 0x10
13079#define tsgen_synctime_t0 0x20
13080#define tsgen_offset_t0 0x28
13081#define tsgen_drift_t0 0x30
13082#define tsgen_synctime_t1 0x58
13083#define tsgen_offset_t1 0x60
13084#define tsgen_drift_t1 0x68
13085
13086/* FW workaround for setting drift */
13087static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13088 int best_val, int best_period)
13089{
13090 struct bnx2x_func_state_params func_params = {NULL};
13091 struct bnx2x_func_set_timesync_params *set_timesync_params =
13092 &func_params.params.set_timesync;
13093
13094 /* Prepare parameters for function state transitions */
13095 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13096 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13097
13098 func_params.f_obj = &bp->func_obj;
13099 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13100
13101 /* Function parameters */
13102 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13103 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13104 set_timesync_params->add_sub_drift_adjust_value =
13105 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13106 set_timesync_params->drift_adjust_value = best_val;
13107 set_timesync_params->drift_adjust_period = best_period;
13108
13109 return bnx2x_func_state_change(bp, &func_params);
13110}
13111
13112static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13113{
13114 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13115 int rc;
13116 int drift_dir = 1;
13117 int val, period, period1, period2, dif, dif1, dif2;
13118 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13119
13120 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13121
13122 if (!netif_running(bp->dev)) {
13123 DP(BNX2X_MSG_PTP,
13124 "PTP adjfreq called while the interface is down\n");
13125 return -EFAULT;
13126 }
13127
13128 if (ppb < 0) {
13129 ppb = -ppb;
13130 drift_dir = 0;
13131 }
13132
13133 if (ppb == 0) {
13134 best_val = 1;
13135 best_period = 0x1FFFFFF;
13136 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13137 best_val = 31;
13138 best_period = 1;
13139 } else {
13140 /* Changed not to allow val = 8, 16, 24 as these values
13141 * are not supported in workaround.
13142 */
13143 for (val = 0; val <= 31; val++) {
13144 if ((val & 0x7) == 0)
13145 continue;
13146 period1 = val * 1000000 / ppb;
13147 period2 = period1 + 1;
13148 if (period1 != 0)
13149 dif1 = ppb - (val * 1000000 / period1);
13150 else
13151 dif1 = BNX2X_MAX_PHC_DRIFT;
13152 if (dif1 < 0)
13153 dif1 = -dif1;
13154 dif2 = ppb - (val * 1000000 / period2);
13155 if (dif2 < 0)
13156 dif2 = -dif2;
13157 dif = (dif1 < dif2) ? dif1 : dif2;
13158 period = (dif1 < dif2) ? period1 : period2;
13159 if (dif < best_dif) {
13160 best_dif = dif;
13161 best_val = val;
13162 best_period = period;
13163 }
13164 }
13165 }
13166
13167 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13168 best_period);
13169 if (rc) {
13170 BNX2X_ERR("Failed to set drift\n");
13171 return -EFAULT;
13172 }
13173
13174 DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
13175 best_period);
13176
13177 return 0;
13178}
13179
13180static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13181{
13182 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13183 u64 now;
13184
13185 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13186
13187 now = timecounter_read(&bp->timecounter);
13188 now += delta;
13189 /* Re-init the timecounter */
13190 timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
13191
13192 return 0;
13193}
13194
13195static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
13196{
13197 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13198 u64 ns;
13199 u32 remainder;
13200
13201 ns = timecounter_read(&bp->timecounter);
13202
13203 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13204
13205 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
13206 ts->tv_nsec = remainder;
13207
13208 return 0;
13209}
13210
13211static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13212 const struct timespec *ts)
13213{
13214 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13215 u64 ns;
13216
13217 ns = ts->tv_sec * 1000000000ULL;
13218 ns += ts->tv_nsec;
13219
13220 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13221
13222 /* Re-init the timecounter */
13223 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13224
13225 return 0;
13226}
13227
13228/* Enable (or disable) ancillary features of the phc subsystem */
13229static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13230 struct ptp_clock_request *rq, int on)
13231{
13232 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13233
13234 BNX2X_ERR("PHC ancillary features are not supported\n");
13235 return -ENOTSUPP;
13236}
13237
13238void bnx2x_register_phc(struct bnx2x *bp)
13239{
13240 /* Fill the ptp_clock_info struct and register PTP clock*/
13241 bp->ptp_clock_info.owner = THIS_MODULE;
13242 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13243 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13244 bp->ptp_clock_info.n_alarm = 0;
13245 bp->ptp_clock_info.n_ext_ts = 0;
13246 bp->ptp_clock_info.n_per_out = 0;
13247 bp->ptp_clock_info.pps = 0;
13248 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13249 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13250 bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
13251 bp->ptp_clock_info.settime = bnx2x_ptp_settime;
13252 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13253
13254 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13255 if (IS_ERR(bp->ptp_clock)) {
13256 bp->ptp_clock = NULL;
13257 BNX2X_ERR("PTP clock registeration failed\n");
13258 }
13259}
13260
1ab4434c
AE		 13261static int bnx2x_init_one(struct pci_dev *pdev,
13262 const struct pci_device_id *ent)
13263{
13264 struct net_device *dev = NULL;
13265 struct bnx2x *bp;
b91e1a1a
YM		 13266 enum pcie_link_width pcie_width;
13267 enum pci_bus_speed pcie_speed;
1ab4434c
AE		 13268 int rc, max_non_def_sbs;
13269 int rx_count, tx_count, rss_count, doorbell_size;
13270 int max_cos_est;
13271 bool is_vf;
13272 int cnic_cnt;
13273
13274 /* An estimated maximum supported CoS number according to the chip
13275 * version.
13276 * We will try to roughly estimate the maximum number of CoSes this chip
13277 * may support in order to minimize the memory allocated for Tx
13278 * netdev_queue's. This number will be accurately calculated during the
13279 * initialization of bp->max_cos based on the chip versions AND chip
13280 * revision in the bnx2x_init_bp().
13281 */
13282 max_cos_est = set_max_cos_est(ent->driver_data);
13283 if (max_cos_est < 0)
13284 return max_cos_est;
13285 is_vf = set_is_vf(ent->driver_data);
13286 cnic_cnt = is_vf ? 0 : 1;
13287
60cad4e6
AE		 13288 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13289
13290 /* add another SB for VF as it has no default SB */
13291 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 13292
13293 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 13294 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 13295
13296 if (rss_count < 1)
13297 return -EINVAL;
6383c0b3
AE		 13298
13299 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 13300 rx_count = rss_count + cnic_cnt;
6383c0b3 13301
1ab4434c 13302 /* Maximum number of netdev Tx queues:
37ae41a9 13303 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 13304 */
55c11941 13305 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 13306
a2fbb9ea 13307 /* dev zeroed in init_etherdev */
6383c0b3 13308 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 13309 if (!dev)
a2fbb9ea
ET		 13310 return -ENOMEM;
13311
a2fbb9ea 13312 bp = netdev_priv(dev);
a2fbb9ea 13313
1ab4434c
AE		 13314 bp->flags = 0;
13315 if (is_vf)
13316 bp->flags |= IS_VF_FLAG;
13317
6383c0b3 13318 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 13319 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 13320 bp->msg_enable = debug;
55c11941 13321 bp->cnic_support = cnic_cnt;
4bd9b0ff 13322 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 13323
6383c0b3 13324 pci_set_drvdata(pdev, dev);
523224a3 13325
1ab4434c 13326 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 13327 if (rc < 0) {
13328 free_netdev(dev);
13329 return rc;
13330 }
13331
1ab4434c
AE		 13332 BNX2X_DEV_INFO("This is a %s function\n",
13333 IS_PF(bp) ? "physical" : "virtual");
55c11941 13334 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 13335 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 13336 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 13337 tx_count, rx_count);
60aa0509 13338
34f80b04 13339 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 13340 if (rc)
13341 goto init_one_exit;
13342
1ab4434c
AE		 13343 /* Map doorbells here as we need the real value of bp->max_cos which
13344 * is initialized in bnx2x_init_bp() to determine the number of
13345 * l2 connections.
6383c0b3 13346 */
1ab4434c 13347 if (IS_VF(bp)) {
1d6f3cd8 13348 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 13349 rc = bnx2x_vf_pci_alloc(bp);
13350 if (rc)
13351 goto init_one_exit;
1ab4434c
AE		 13352 } else {
13353 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13354 if (doorbell_size > pci_resource_len(pdev, 2)) {
13355 dev_err(&bp->pdev->dev,
13356 "Cannot map doorbells, bar size too small, aborting\n");
13357 rc = -ENOMEM;
13358 goto init_one_exit;
13359 }
13360 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13361 doorbell_size);
37ae41a9 13362 }
6383c0b3
AE		 13363 if (!bp->doorbells) {
13364 dev_err(&bp->pdev->dev,
13365 "Cannot map doorbell space, aborting\n");
13366 rc = -ENOMEM;
13367 goto init_one_exit;
13368 }
13369
be1f1ffa
AE		 13370 if (IS_VF(bp)) {
13371 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13372 if (rc)
13373 goto init_one_exit;
13374 }
13375
3c76feff
AE		 13376 /* Enable SRIOV if capability found in configuration space */
13377 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb
AE		 13378 if (rc)
13379 goto init_one_exit;
13380
523224a3 13381 /* calc qm_cid_count */
6383c0b3 13382 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 13383 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 13384
55c11941 13385 /* disable FCOE L2 queue for E1x*/
62ac0dc9 13386 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 13387 bp->flags |= NO_FCOE_FLAG;
13388
0e8d2ec5
MS		 13389 /* Set bp->num_queues for MSI-X mode*/
13390 bnx2x_set_num_queues(bp);
13391
25985edc 13392 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 13393 * needed.
d6214d7a 13394 */
1ab4434c
AE		 13395 rc = bnx2x_set_int_mode(bp);
13396 if (rc) {
13397 dev_err(&pdev->dev, "Cannot set interrupts\n");
13398 goto init_one_exit;
13399 }
04c46736 13400 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 13401
1ab4434c 13402 /* register the net device */
b340007f
VZ		 13403 rc = register_netdev(dev);
13404 if (rc) {
13405 dev_err(&pdev->dev, "Cannot register net device\n");
13406 goto init_one_exit;
13407 }
1ab4434c 13408 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 13409
ec6ba945
VZ		 13410 if (!NO_FCOE(bp)) {
13411 /* Add storage MAC address */
13412 rtnl_lock();
13413 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13414 rtnl_unlock();
13415 }
b91e1a1a
YM		 13416 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13417 pcie_speed == PCI_SPEED_UNKNOWN ||
13418 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13419 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13420 else
13421 BNX2X_DEV_INFO(
13422 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
ca1ee4b2
DK		 13423 board_info[ent->driver_data].name,
13424 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13425 pcie_width,
b91e1a1a
YM		 13426 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13427 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13428 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
ca1ee4b2
DK		 13429 "Unknown",
13430 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 13431
eeed018c
MK		 13432 bnx2x_register_phc(bp);
13433
a2fbb9ea 13434 return 0;
34f80b04
EG		 13435
13436init_one_exit:
33d8e6a5
YM		 13437 bnx2x_disable_pcie_error_reporting(bp);
13438
34f80b04
EG		 13439 if (bp->regview)
13440 iounmap(bp->regview);
13441
1ab4434c 13442 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 13443 iounmap(bp->doorbells);
13444
13445 free_netdev(dev);
13446
13447 if (atomic_read(&pdev->enable_cnt) == 1)
13448 pci_release_regions(pdev);
13449
13450 pci_disable_device(pdev);
34f80b04
EG		 13451
13452 return rc;
a2fbb9ea
ET		 13453}
13454
b030ed2f
YM		 13455static void __bnx2x_remove(struct pci_dev *pdev,
13456 struct net_device *dev,
13457 struct bnx2x *bp,
13458 bool remove_netdev)
a2fbb9ea 13459{
eeed018c
MK		 13460 if (bp->ptp_clock) {
13461 ptp_clock_unregister(bp->ptp_clock);
13462 bp->ptp_clock = NULL;
13463 }
13464
ec6ba945
VZ		 13465 /* Delete storage MAC address */
13466 if (!NO_FCOE(bp)) {
13467 rtnl_lock();
13468 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13469 rtnl_unlock();
13470 }
ec6ba945 13471
98507672
SR		 13472#ifdef BCM_DCBNL
13473 /* Delete app tlvs from dcbnl */
13474 bnx2x_dcbnl_update_applist(bp, true);
13475#endif
13476
a6d3a5ba
BW		 13477 if (IS_PF(bp) &&
13478 !BP_NOMCP(bp) &&
13479 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13480 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13481
b030ed2f
YM		 13482 /* Close the interface - either directly or implicitly */
13483 if (remove_netdev) {
13484 unregister_netdev(dev);
13485 } else {
13486 rtnl_lock();
6ef5a92c 13487 dev_close(dev);
b030ed2f
YM		 13488 rtnl_unlock();
13489 }
a2fbb9ea 13490
78c3bcc5
AE		 13491 bnx2x_iov_remove_one(bp);
13492
084d6cbb 13493 /* Power on: we can't let PCI layer write to us while we are in D3 */
1ab4434c
AE		 13494 if (IS_PF(bp))
13495 bnx2x_set_power_state(bp, PCI_D0);
084d6cbb 13496
d6214d7a
DK		 13497 /* Disable MSI/MSI-X */
13498 bnx2x_disable_msi(bp);
f85582f8 13499
084d6cbb 13500 /* Power off */
1ab4434c
AE		 13501 if (IS_PF(bp))
13502 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 13503
72fd0718 13504 /* Make sure RESET task is not scheduled before continuing */
7be08a72 13505 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 13506
4513f925
AE		 13507 /* send message via vfpf channel to release the resources of this vf */
13508 if (IS_VF(bp))
13509 bnx2x_vfpf_release(bp);
72fd0718 13510
b030ed2f
YM		 13511 /* Assumes no further PCIe PM changes will occur */
13512 if (system_state == SYSTEM_POWER_OFF) {
13513 pci_wake_from_d3(pdev, bp->wol);
13514 pci_set_power_state(pdev, PCI_D3hot);
13515 }
13516
33d8e6a5 13517 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 13518 if (remove_netdev) {
13519 if (bp->regview)
13520 iounmap(bp->regview);
33d8e6a5 13521
d9aee591
YM		 13522 /* For vfs, doorbells are part of the regview and were unmapped
13523 * along with it. FW is only loaded by PF.
13524 */
13525 if (IS_PF(bp)) {
13526 if (bp->doorbells)
13527 iounmap(bp->doorbells);
eb2afd4a 13528
d9aee591 13529 bnx2x_release_firmware(bp);
e2a367f8
YM		 13530 } else {
13531 bnx2x_vf_pci_dealloc(bp);
d9aee591
YM		 13532 }
13533 bnx2x_free_mem_bp(bp);
523224a3 13534
b030ed2f 13535 free_netdev(dev);
34f80b04 13536
d9aee591
YM		 13537 if (atomic_read(&pdev->enable_cnt) == 1)
13538 pci_release_regions(pdev);
34f80b04 13539
5f6db130
YM		 13540 pci_disable_device(pdev);
13541 }
a2fbb9ea
ET		 13542}
13543
b030ed2f
YM		 13544static void bnx2x_remove_one(struct pci_dev *pdev)
13545{
13546 struct net_device *dev = pci_get_drvdata(pdev);
13547 struct bnx2x *bp;
13548
13549 if (!dev) {
13550 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13551 return;
13552 }
13553 bp = netdev_priv(dev);
13554
13555 __bnx2x_remove(pdev, dev, bp, true);
13556}
13557
f8ef6e44
YG		 13558static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13559{
7fa6f340 13560 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 13561
13562 bp->rx_mode = BNX2X_RX_MODE_NONE;
13563
55c11941
MS		 13564 if (CNIC_LOADED(bp))
13565 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13566
619c5cb6
VZ		 13567 /* Stop Tx */
13568 bnx2x_tx_disable(bp);
26614ba5
MS		 13569 /* Delete all NAPI objects */
13570 bnx2x_del_all_napi(bp);
55c11941
MS		 13571 if (CNIC_LOADED(bp))
13572 bnx2x_del_all_napi_cnic(bp);
7fa6f340 13573 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 13574
13575 del_timer_sync(&bp->timer);
0c0e6341 13576 cancel_delayed_work_sync(&bp->sp_task);
13577 cancel_delayed_work_sync(&bp->period_task);
619c5cb6 13578
7fa6f340
YM		 13579 spin_lock_bh(&bp->stats_lock);
13580 bp->stats_state = STATS_STATE_DISABLED;
13581 spin_unlock_bh(&bp->stats_lock);
f8ef6e44 13582
7fa6f340 13583 bnx2x_save_statistics(bp);
f8ef6e44 13584
619c5cb6
VZ		 13585 netif_carrier_off(bp->dev);
13586
f8ef6e44
YG		 13587 return 0;
13588}
13589
493adb1f
WX		 13590/**
13591 * bnx2x_io_error_detected - called when PCI error is detected
13592 * @pdev: Pointer to PCI device
13593 * @state: The current pci connection state
13594 *
13595 * This function is called after a PCI bus error affecting
13596 * this device has been detected.
13597 */
13598static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13599 pci_channel_state_t state)
13600{
13601 struct net_device *dev = pci_get_drvdata(pdev);
13602 struct bnx2x *bp = netdev_priv(dev);
13603
13604 rtnl_lock();
13605
7fa6f340
YM		 13606 BNX2X_ERR("IO error detected\n");
13607
493adb1f
WX		 13608 netif_device_detach(dev);
13609
07ce50e4
DN		 13610 if (state == pci_channel_io_perm_failure) {
13611 rtnl_unlock();
13612 return PCI_ERS_RESULT_DISCONNECT;
13613 }
13614
493adb1f 13615 if (netif_running(dev))
f8ef6e44 13616 bnx2x_eeh_nic_unload(bp);
493adb1f 13617
7fa6f340
YM		 13618 bnx2x_prev_path_mark_eeh(bp);
13619
493adb1f
WX		 13620 pci_disable_device(pdev);
13621
13622 rtnl_unlock();
13623
13624 /* Request a slot reset */
13625 return PCI_ERS_RESULT_NEED_RESET;
13626}
13627
13628/**
13629 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13630 * @pdev: Pointer to PCI device
13631 *
13632 * Restart the card from scratch, as if from a cold-boot.
13633 */
13634static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13635{
13636 struct net_device *dev = pci_get_drvdata(pdev);
13637 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 13638 int i;
493adb1f
WX		 13639
13640 rtnl_lock();
7fa6f340 13641 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 13642 if (pci_enable_device(pdev)) {
13643 dev_err(&pdev->dev,
13644 "Cannot re-enable PCI device after reset\n");
13645 rtnl_unlock();
13646 return PCI_ERS_RESULT_DISCONNECT;
13647 }
13648
13649 pci_set_master(pdev);
13650 pci_restore_state(pdev);
70632d0a 13651 pci_save_state(pdev);
493adb1f
WX		 13652
13653 if (netif_running(dev))
13654 bnx2x_set_power_state(bp, PCI_D0);
13655
7fa6f340
YM		 13656 if (netif_running(dev)) {
13657 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 13658
13659 /* MCP should have been reset; Need to wait for validity */
13660 bnx2x_init_shmem(bp);
13661
7fa6f340
YM		 13662 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13663 u32 v;
13664
13665 v = SHMEM2_RD(bp,
13666 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13667 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13668 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13669 }
13670 bnx2x_drain_tx_queues(bp);
13671 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13672 bnx2x_netif_stop(bp, 1);
13673 bnx2x_free_irq(bp);
13674
13675 /* Report UNLOAD_DONE to MCP */
13676 bnx2x_send_unload_done(bp, true);
13677
13678 bp->sp_state = 0;
13679 bp->port.pmf = 0;
13680
13681 bnx2x_prev_unload(bp);
13682
16a5fd92 13683 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 13684 * assume the FW will no longer write to the bnx2x driver.
13685 */
13686 bnx2x_squeeze_objects(bp);
13687 bnx2x_free_skbs(bp);
13688 for_each_rx_queue(bp, i)
13689 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13690 bnx2x_free_fp_mem(bp);
13691 bnx2x_free_mem(bp);
13692
13693 bp->state = BNX2X_STATE_CLOSED;
13694 }
13695
493adb1f
WX		 13696 rtnl_unlock();
13697
33d8e6a5
YM		 13698 /* If AER, perform cleanup of the PCIe registers */
13699 if (bp->flags & AER_ENABLED) {
13700 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13701 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13702 else
13703 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13704 }
13705
493adb1f
WX		 13706 return PCI_ERS_RESULT_RECOVERED;
13707}
13708
13709/**
13710 * bnx2x_io_resume - called when traffic can start flowing again
13711 * @pdev: Pointer to PCI device
13712 *
13713 * This callback is called when the error recovery driver tells us that
13714 * its OK to resume normal operation.
13715 */
13716static void bnx2x_io_resume(struct pci_dev *pdev)
13717{
13718 struct net_device *dev = pci_get_drvdata(pdev);
13719 struct bnx2x *bp = netdev_priv(dev);
13720
72fd0718 13721 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 13722 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 13723 return;
13724 }
13725
493adb1f
WX		 13726 rtnl_lock();
13727
7fa6f340
YM		 13728 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13729 DRV_MSG_SEQ_NUMBER_MASK;
13730
493adb1f 13731 if (netif_running(dev))
f8ef6e44 13732 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 13733
13734 netif_device_attach(dev);
13735
13736 rtnl_unlock();
13737}
13738
3646f0e5 13739static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 13740 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 13741 .slot_reset = bnx2x_io_slot_reset,
13742 .resume = bnx2x_io_resume,
493adb1f
WX		 13743};
13744
b030ed2f
YM		 13745static void bnx2x_shutdown(struct pci_dev *pdev)
13746{
13747 struct net_device *dev = pci_get_drvdata(pdev);
13748 struct bnx2x *bp;
13749
13750 if (!dev)
13751 return;
13752
13753 bp = netdev_priv(dev);
13754 if (!bp)
13755 return;
13756
13757 rtnl_lock();
13758 netif_device_detach(dev);
13759 rtnl_unlock();
13760
13761 /* Don't remove the netdevice, as there are scenarios which will cause
13762 * the kernel to hang, e.g., when trying to remove bnx2i while the
13763 * rootfs is mounted from SAN.
13764 */
13765 __bnx2x_remove(pdev, dev, bp, false);
13766}
13767
a2fbb9ea 13768static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 13769 .name = DRV_MODULE_NAME,
13770 .id_table = bnx2x_pci_tbl,
13771 .probe = bnx2x_init_one,
0329aba1 13772 .remove = bnx2x_remove_one,
493adb1f
WX		 13773 .suspend = bnx2x_suspend,
13774 .resume = bnx2x_resume,
13775 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 13776#ifdef CONFIG_BNX2X_SRIOV
13777 .sriov_configure = bnx2x_sriov_configure,
13778#endif
b030ed2f 13779 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 13780};
13781
13782static int __init bnx2x_init(void)
13783{
dd21ca6d
SG		 13784 int ret;
13785
7995c64e 13786 pr_info("%s", version);
938cf541 13787
1cf167f2
EG		 13788 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13789 if (bnx2x_wq == NULL) {
7995c64e 13790 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 13791 return -ENOMEM;
13792 }
370d4a26
YM		 13793 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13794 if (!bnx2x_iov_wq) {
13795 pr_err("Cannot create iov workqueue\n");
13796 destroy_workqueue(bnx2x_wq);
13797 return -ENOMEM;
13798 }
1cf167f2 13799
dd21ca6d
SG		 13800 ret = pci_register_driver(&bnx2x_pci_driver);
13801 if (ret) {
7995c64e 13802 pr_err("Cannot register driver\n");
dd21ca6d 13803 destroy_workqueue(bnx2x_wq);
370d4a26 13804 destroy_workqueue(bnx2x_iov_wq);
dd21ca6d
SG		 13805 }
13806 return ret;
a2fbb9ea
ET		 13807}
13808
13809static void __exit bnx2x_cleanup(void)
13810{
452427b0 13811 struct list_head *pos, *q;
d76a6111 13812
a2fbb9ea 13813 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 13814
13815 destroy_workqueue(bnx2x_wq);
370d4a26 13816 destroy_workqueue(bnx2x_iov_wq);
452427b0 13817
16a5fd92 13818 /* Free globally allocated resources */
452427b0
YM		 13819 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13820 struct bnx2x_prev_path_list *tmp =
13821 list_entry(pos, struct bnx2x_prev_path_list, list);
13822 list_del(pos);
13823 kfree(tmp);
13824 }
a2fbb9ea
ET		 13825}
13826
3deb8167
YR		 13827void bnx2x_notify_link_changed(struct bnx2x *bp)
13828{
13829 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13830}
13831
a2fbb9ea
ET		 13832module_init(bnx2x_init);
13833module_exit(bnx2x_cleanup);
13834
619c5cb6
VZ		 13835/**
13836 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13837 *
13838 * @bp: driver handle
13839 * @set: set or clear the CAM entry
13840 *
16a5fd92 13841 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 13842 * Return 0 if success, -ENODEV if ramrod doesn't return.
13843 */
1191cb83 13844static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 13845{
13846 unsigned long ramrod_flags = 0;
13847
13848 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13849 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13850 &bp->iscsi_l2_mac_obj, true,
13851 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13852}
993ac7b5
MC		 13853
13854/* count denotes the number of new completions we have seen */
13855static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13856{
13857 struct eth_spe *spe;
a052997e 13858 int cxt_index, cxt_offset;
993ac7b5
MC		 13859
13860#ifdef BNX2X_STOP_ON_ERROR
13861 if (unlikely(bp->panic))
13862 return;
13863#endif
13864
13865 spin_lock_bh(&bp->spq_lock);
c2bff63f 13866 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 13867 bp->cnic_spq_pending -= count;
13868
c2bff63f
DK		 13869 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13870 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13871 & SPE_HDR_CONN_TYPE) >>
13872 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 13873 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13874 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 13875
13876 /* Set validation for iSCSI L2 client before sending SETUP
13877 * ramrod
13878 */
13879 if (type == ETH_CONNECTION_TYPE) {
a052997e 13880 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 13881 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 13882 ILT_PAGE_CIDS;
37ae41a9 13883 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 13884 (cxt_index * ILT_PAGE_CIDS);
13885 bnx2x_set_ctx_validation(bp,
13886 &bp->context[cxt_index].
13887 vcxt[cxt_offset].eth,
37ae41a9 13888 BNX2X_ISCSI_ETH_CID(bp));
a052997e 13889 }
c2bff63f
DK		 13890 }
13891
619c5cb6
VZ		 13892 /*
13893 * There may be not more than 8 L2, not more than 8 L5 SPEs
13894 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 13895 * COMMON ramrods is not more than the EQ and SPQ can
13896 * accommodate.
c2bff63f 13897 */
6e30dd4e
VZ		 13898 if (type == ETH_CONNECTION_TYPE) {
13899 if (!atomic_read(&bp->cq_spq_left))
13900 break;
13901 else
13902 atomic_dec(&bp->cq_spq_left);
13903 } else if (type == NONE_CONNECTION_TYPE) {
13904 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 13905 break;
13906 else
6e30dd4e 13907 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 13908 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13909 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 13910 if (bp->cnic_spq_pending >=
13911 bp->cnic_eth_dev.max_kwqe_pending)
13912 break;
13913 else
13914 bp->cnic_spq_pending++;
13915 } else {
13916 BNX2X_ERR("Unknown SPE type: %d\n", type);
13917 bnx2x_panic();
993ac7b5 13918 break;
c2bff63f 13919 }
993ac7b5
MC		 13920
13921 spe = bnx2x_sp_get_next(bp);
13922 *spe = *bp->cnic_kwq_cons;
13923
51c1a580 13924 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 13925 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13926
13927 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13928 bp->cnic_kwq_cons = bp->cnic_kwq;
13929 else
13930 bp->cnic_kwq_cons++;
13931 }
13932 bnx2x_sp_prod_update(bp);
13933 spin_unlock_bh(&bp->spq_lock);
13934}
13935
13936static int bnx2x_cnic_sp_queue(struct net_device *dev,
13937 struct kwqe_16 *kwqes[], u32 count)
13938{
13939 struct bnx2x *bp = netdev_priv(dev);
13940 int i;
13941
13942#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 13943 if (unlikely(bp->panic)) {
13944 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 13945 return -EIO;
51c1a580 13946 }
993ac7b5
MC		 13947#endif
13948
95c6c616
AE		 13949 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13950 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 13951 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 13952 return -EAGAIN;
13953 }
13954
993ac7b5
MC		 13955 spin_lock_bh(&bp->spq_lock);
13956
13957 for (i = 0; i < count; i++) {
13958 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13959
13960 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13961 break;
13962
13963 *bp->cnic_kwq_prod = *spe;
13964
13965 bp->cnic_kwq_pending++;
13966
51c1a580 13967 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 13968 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 13969 spe->data.update_data_addr.hi,
13970 spe->data.update_data_addr.lo,
993ac7b5
MC		 13971 bp->cnic_kwq_pending);
13972
13973 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13974 bp->cnic_kwq_prod = bp->cnic_kwq;
13975 else
13976 bp->cnic_kwq_prod++;
13977 }
13978
13979 spin_unlock_bh(&bp->spq_lock);
13980
13981 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13982 bnx2x_cnic_sp_post(bp, 0);
13983
13984 return i;
13985}
13986
13987static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13988{
13989 struct cnic_ops *c_ops;
13990 int rc = 0;
13991
13992 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 13993 c_ops = rcu_dereference_protected(bp->cnic_ops,
13994 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 13995 if (c_ops)
13996 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13997 mutex_unlock(&bp->cnic_mutex);
13998
13999 return rc;
14000}
14001
14002static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14003{
14004 struct cnic_ops *c_ops;
14005 int rc = 0;
14006
14007 rcu_read_lock();
14008 c_ops = rcu_dereference(bp->cnic_ops);
14009 if (c_ops)
14010 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14011 rcu_read_unlock();
14012
14013 return rc;
14014}
14015
14016/*
14017 * for commands that have no data
14018 */
9f6c9258 14019int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 14020{
14021 struct cnic_ctl_info ctl = {0};
14022
14023 ctl.cmd = cmd;
14024
14025 return bnx2x_cnic_ctl_send(bp, &ctl);
14026}
14027
619c5cb6 14028static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 14029{
619c5cb6 14030 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 14031
14032 /* first we tell CNIC and only then we count this as a completion */
14033 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14034 ctl.data.comp.cid = cid;
619c5cb6 14035 ctl.data.comp.error = err;
993ac7b5
MC		 14036
14037 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 14038 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 14039}
14040
619c5cb6
VZ		 14041/* Called with netif_addr_lock_bh() taken.
14042 * Sets an rx_mode config for an iSCSI ETH client.
14043 * Doesn't block.
14044 * Completion should be checked outside.
14045 */
14046static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14047{
14048 unsigned long accept_flags = 0, ramrod_flags = 0;
14049 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14050 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14051
14052 if (start) {
14053 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14054 * because it's the only way for UIO Queue to accept
14055 * multicasts (in non-promiscuous mode only one Queue per
14056 * function will receive multicast packets (leading in our
14057 * case).
14058 */
14059 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14060 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14061 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14062 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14063
14064 /* Clear STOP_PENDING bit if START is requested */
14065 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14066
14067 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14068 } else
14069 /* Clear START_PENDING bit if STOP is requested */
14070 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14071
14072 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14073 set_bit(sched_state, &bp->sp_state);
14074 else {
14075 __set_bit(RAMROD_RX, &ramrod_flags);
14076 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14077 ramrod_flags);
14078 }
14079}
14080
993ac7b5
MC		 14081static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14082{
14083 struct bnx2x *bp = netdev_priv(dev);
14084 int rc = 0;
14085
14086 switch (ctl->cmd) {
14087 case DRV_CTL_CTXTBL_WR_CMD: {
14088 u32 index = ctl->data.io.offset;
14089 dma_addr_t addr = ctl->data.io.dma_addr;
14090
14091 bnx2x_ilt_wr(bp, index, addr);
14092 break;
14093 }
14094
c2bff63f
DK		 14095 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14096 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 14097
14098 bnx2x_cnic_sp_post(bp, count);
14099 break;
14100 }
14101
14102 /* rtnl_lock is held. */
14103 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 14104 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14105 unsigned long sp_bits = 0;
14106
14107 /* Configure the iSCSI classification object */
14108 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14109 cp->iscsi_l2_client_id,
14110 cp->iscsi_l2_cid, BP_FUNC(bp),
14111 bnx2x_sp(bp, mac_rdata),
14112 bnx2x_sp_mapping(bp, mac_rdata),
14113 BNX2X_FILTER_MAC_PENDING,
14114 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14115 &bp->macs_pool);
ec6ba945 14116
523224a3 14117 /* Set iSCSI MAC address */
619c5cb6
VZ		 14118 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14119 if (rc)
14120 break;
523224a3
DK		 14121
14122 mmiowb();
14123 barrier();
14124
619c5cb6
VZ		 14125 /* Start accepting on iSCSI L2 ring */
14126
14127 netif_addr_lock_bh(dev);
14128 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14129 netif_addr_unlock_bh(dev);
14130
14131 /* bits to wait on */
14132 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14133 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14134
14135 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14136 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 14137
993ac7b5
MC		 14138 break;
14139 }
14140
14141 /* rtnl_lock is held. */
14142 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 14143 unsigned long sp_bits = 0;
993ac7b5 14144
523224a3 14145 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 14146 netif_addr_lock_bh(dev);
14147 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14148 netif_addr_unlock_bh(dev);
14149
14150 /* bits to wait on */
14151 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14152 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14153
14154 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14155 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 14156
14157 mmiowb();
14158 barrier();
14159
14160 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 14161 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14162 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 14163 break;
14164 }
c2bff63f
DK		 14165 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14166 int count = ctl->data.credit.credit_count;
14167
4e857c58 14168 smp_mb__before_atomic();
6e30dd4e 14169 atomic_add(count, &bp->cq_spq_left);
4e857c58 14170 smp_mb__after_atomic();
c2bff63f
DK		 14171 break;
14172 }
1d187b34 14173 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 14174 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 14175
14176 if (CHIP_IS_E3(bp)) {
14177 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 14178 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14179 int path = BP_PATH(bp);
14180 int port = BP_PORT(bp);
14181 int i;
14182 u32 scratch_offset;
14183 u32 *host_addr;
1d187b34 14184
2e499d3c 14185 /* first write capability to shmem2 */
1d187b34
BW		 14186 if (ulp_type == CNIC_ULP_ISCSI)
14187 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14188 else if (ulp_type == CNIC_ULP_FCOE)
14189 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14190 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 14191
14192 if ((ulp_type != CNIC_ULP_FCOE) ||
14193 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14194 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14195 break;
14196
14197 /* if reached here - should write fcoe capabilities */
14198 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14199 if (!scratch_offset)
14200 break;
14201 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14202 fcoe_features[path][port]);
14203 host_addr = (u32 *) &(ctl->data.register_data.
14204 fcoe_features);
14205 for (i = 0; i < sizeof(struct fcoe_capabilities);
14206 i += 4)
14207 REG_WR(bp, scratch_offset + i,
14208 *(host_addr + i/4));
1d187b34 14209 }
42f8277f 14210 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14211 break;
14212 }
2e499d3c 14213
1d187b34
BW		 14214 case DRV_CTL_ULP_UNREGISTER_CMD: {
14215 int ulp_type = ctl->data.ulp_type;
14216
14217 if (CHIP_IS_E3(bp)) {
14218 int idx = BP_FW_MB_IDX(bp);
14219 u32 cap;
14220
14221 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14222 if (ulp_type == CNIC_ULP_ISCSI)
14223 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14224 else if (ulp_type == CNIC_ULP_FCOE)
14225 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14226 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14227 }
42f8277f 14228 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14229 break;
14230 }
993ac7b5
MC		 14231
14232 default:
14233 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14234 rc = -EINVAL;
14235 }
14236
14237 return rc;
14238}
14239
9f6c9258 14240void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 14241{
14242 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14243
14244 if (bp->flags & USING_MSIX_FLAG) {
14245 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14246 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14247 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14248 } else {
14249 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14250 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14251 }
619c5cb6 14252 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 14253 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14254 else
14255 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14256
619c5cb6
VZ		 14257 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14258 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 14259 cp->irq_arr[1].status_blk = bp->def_status_blk;
14260 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 14261 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 14262
14263 cp->num_irq = 2;
14264}
14265
37ae41a9
MS		 14266void bnx2x_setup_cnic_info(struct bnx2x *bp)
14267{
14268 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14269
37ae41a9
MS		 14270 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14271 bnx2x_cid_ilt_lines(bp);
14272 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14273 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14274 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14275
f78afb35
MC		 14276 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14277 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14278 cp->iscsi_l2_cid);
14279
37ae41a9
MS		 14280 if (NO_ISCSI_OOO(bp))
14281 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14282}
14283
993ac7b5
MC		 14284static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14285 void *data)
14286{
14287 struct bnx2x *bp = netdev_priv(dev);
14288 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 14289 int rc;
14290
14291 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 14292
51c1a580
MS		 14293 if (ops == NULL) {
14294 BNX2X_ERR("NULL ops received\n");
993ac7b5 14295 return -EINVAL;
51c1a580 14296 }
993ac7b5 14297
55c11941
MS		 14298 if (!CNIC_SUPPORT(bp)) {
14299 BNX2X_ERR("Can't register CNIC when not supported\n");
14300 return -EOPNOTSUPP;
14301 }
14302
14303 if (!CNIC_LOADED(bp)) {
14304 rc = bnx2x_load_cnic(bp);
14305 if (rc) {
14306 BNX2X_ERR("CNIC-related load failed\n");
14307 return rc;
14308 }
55c11941
MS		 14309 }
14310
14311 bp->cnic_enabled = true;
14312
993ac7b5
MC		 14313 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14314 if (!bp->cnic_kwq)
14315 return -ENOMEM;
14316
14317 bp->cnic_kwq_cons = bp->cnic_kwq;
14318 bp->cnic_kwq_prod = bp->cnic_kwq;
14319 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14320
14321 bp->cnic_spq_pending = 0;
14322 bp->cnic_kwq_pending = 0;
14323
14324 bp->cnic_data = data;
14325
14326 cp->num_irq = 0;
619c5cb6 14327 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 14328 cp->iro_arr = bp->iro_arr;
993ac7b5 14329
993ac7b5 14330 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 14331
993ac7b5
MC		 14332 rcu_assign_pointer(bp->cnic_ops, ops);
14333
42f8277f
YM		 14334 /* Schedule driver to read CNIC driver versions */
14335 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14336
993ac7b5
MC		 14337 return 0;
14338}
14339
14340static int bnx2x_unregister_cnic(struct net_device *dev)
14341{
14342 struct bnx2x *bp = netdev_priv(dev);
14343 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14344
14345 mutex_lock(&bp->cnic_mutex);
993ac7b5 14346 cp->drv_state = 0;
2cfa5a04 14347 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 14348 mutex_unlock(&bp->cnic_mutex);
14349 synchronize_rcu();
fea75645 14350 bp->cnic_enabled = false;
993ac7b5
MC		 14351 kfree(bp->cnic_kwq);
14352 bp->cnic_kwq = NULL;
14353
14354 return 0;
14355}
14356
a8f47eb7 14357static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 14358{
14359 struct bnx2x *bp = netdev_priv(dev);
14360 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14361
2ba45142
VZ		 14362 /* If both iSCSI and FCoE are disabled - return NULL in
14363 * order to indicate CNIC that it should not try to work
14364 * with this device.
14365 */
14366 if (NO_ISCSI(bp) && NO_FCOE(bp))
14367 return NULL;
14368
993ac7b5
MC		 14369 cp->drv_owner = THIS_MODULE;
14370 cp->chip_id = CHIP_ID(bp);
14371 cp->pdev = bp->pdev;
14372 cp->io_base = bp->regview;
14373 cp->io_base2 = bp->doorbells;
14374 cp->max_kwqe_pending = 8;
523224a3 14375 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 14376 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14377 bnx2x_cid_ilt_lines(bp);
993ac7b5 14378 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 14379 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 14380 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14381 cp->drv_ctl = bnx2x_drv_ctl;
14382 cp->drv_register_cnic = bnx2x_register_cnic;
14383 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 14384 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 14385 cp->iscsi_l2_client_id =
14386 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 14387 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 14388
2ba45142
VZ		 14389 if (NO_ISCSI_OOO(bp))
14390 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14391
14392 if (NO_ISCSI(bp))
14393 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14394
14395 if (NO_FCOE(bp))
14396 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14397
51c1a580
MS		 14398 BNX2X_DEV_INFO(
14399 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 14400 cp->ctx_blk_size,
14401 cp->ctx_tbl_offset,
14402 cp->ctx_tbl_len,
14403 cp->starting_cid);
993ac7b5
MC		 14404 return cp;
14405}
993ac7b5 14406
a8f47eb7 14407static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 14408{
6411280a
AE		 14409 struct bnx2x *bp = fp->bp;
14410 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 14411
6411280a
AE		 14412 if (IS_VF(bp))
14413 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14414 else if (!CHIP_IS_E1x(bp))
14415 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14416 else
14417 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 14418
6411280a 14419 return offset;
8d9ac297 14420}
381ac16b 14421
6411280a
AE		 14422/* called only on E1H or E2.
14423 * When pretending to be PF, the pretend value is the function number 0...7
14424 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14425 * combination
14426 */
14427int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 14428{
6411280a 14429 u32 pretend_reg;
381ac16b 14430
23826850 14431 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 14432 return -1;
381ac16b 14433
6411280a
AE		 14434 /* get my own pretend register */
14435 pretend_reg = bnx2x_get_pretend_reg(bp);
14436 REG_WR(bp, pretend_reg, pretend_func_val);
14437 REG_RD(bp, pretend_reg);
381ac16b
AE		 14438 return 0;
14439}
eeed018c
MK		 14440
14441static void bnx2x_ptp_task(struct work_struct *work)
14442{
14443 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14444 int port = BP_PORT(bp);
14445 u32 val_seq;
14446 u64 timestamp, ns;
14447 struct skb_shared_hwtstamps shhwtstamps;
14448
14449 /* Read Tx timestamp registers */
14450 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14451 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14452 if (val_seq & 0x10000) {
14453 /* There is a valid timestamp value */
14454 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14455 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14456 timestamp <<= 32;
14457 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14458 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14459 /* Reset timestamp register to allow new timestamp */
14460 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14461 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14462 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14463
14464 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14465 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14466 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14467 dev_kfree_skb_any(bp->ptp_tx_skb);
14468 bp->ptp_tx_skb = NULL;
14469
14470 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14471 timestamp, ns);
14472 } else {
14473 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14474 /* Reschedule to keep checking for a valid timestamp value */
14475 schedule_work(&bp->ptp_task);
14476 }
14477}
14478
14479void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14480{
14481 int port = BP_PORT(bp);
14482 u64 timestamp, ns;
14483
14484 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14485 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14486 timestamp <<= 32;
14487 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14488 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14489
14490 /* Reset timestamp register to allow new timestamp */
14491 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14492 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14493
14494 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14495
14496 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14497
14498 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14499 timestamp, ns);
14500}
14501
14502/* Read the PHC */
14503static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14504{
14505 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14506 int port = BP_PORT(bp);
14507 u32 wb_data[2];
14508 u64 phc_cycles;
14509
14510 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14511 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14512 phc_cycles = wb_data[1];
14513 phc_cycles = (phc_cycles << 32) + wb_data[0];
14514
14515 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14516
14517 return phc_cycles;
14518}
14519
14520static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14521{
14522 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14523 bp->cyclecounter.read = bnx2x_cyclecounter_read;
14524 bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
14525 bp->cyclecounter.shift = 1;
14526 bp->cyclecounter.mult = 1;
14527}
14528
14529static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14530{
14531 struct bnx2x_func_state_params func_params = {NULL};
14532 struct bnx2x_func_set_timesync_params *set_timesync_params =
14533 &func_params.params.set_timesync;
14534
14535 /* Prepare parameters for function state transitions */
14536 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14537 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14538
14539 func_params.f_obj = &bp->func_obj;
14540 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14541
14542 /* Function parameters */
14543 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14544 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14545
14546 return bnx2x_func_state_change(bp, &func_params);
14547}
14548
14549int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14550{
14551 struct bnx2x_queue_state_params q_params;
14552 int rc, i;
14553
14554 /* send queue update ramrod to enable PTP packets */
14555 memset(&q_params, 0, sizeof(q_params));
14556 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14557 q_params.cmd = BNX2X_Q_CMD_UPDATE;
14558 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14559 &q_params.params.update.update_flags);
14560 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14561 &q_params.params.update.update_flags);
14562
14563 /* send the ramrod on all the queues of the PF */
14564 for_each_eth_queue(bp, i) {
14565 struct bnx2x_fastpath *fp = &bp->fp[i];
14566
14567 /* Set the appropriate Queue object */
14568 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14569
14570 /* Update the Queue state */
14571 rc = bnx2x_queue_state_change(bp, &q_params);
14572 if (rc) {
14573 BNX2X_ERR("Failed to enable PTP packets\n");
14574 return rc;
14575 }
14576 }
14577
14578 return 0;
14579}
14580
14581int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14582{
14583 int port = BP_PORT(bp);
14584 int rc;
14585
14586 if (!bp->hwtstamp_ioctl_called)
14587 return 0;
14588
14589 switch (bp->tx_type) {
14590 case HWTSTAMP_TX_ON:
14591 bp->flags |= TX_TIMESTAMPING_EN;
14592 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14593 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14594 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14595 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14596 break;
14597 case HWTSTAMP_TX_ONESTEP_SYNC:
14598 BNX2X_ERR("One-step timestamping is not supported\n");
14599 return -ERANGE;
14600 }
14601
14602 switch (bp->rx_filter) {
14603 case HWTSTAMP_FILTER_NONE:
14604 break;
14605 case HWTSTAMP_FILTER_ALL:
14606 case HWTSTAMP_FILTER_SOME:
14607 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14608 break;
14609 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14610 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14611 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14612 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14613 /* Initialize PTP detection for UDP/IPv4 events */
14614 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14615 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14616 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14617 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14618 break;
14619 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14620 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14621 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14622 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14623 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14624 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14625 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14626 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14627 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14628 break;
14629 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14630 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14631 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14632 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14633 /* Initialize PTP detection L2 events */
14634 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14635 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14636 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14637 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14638
14639 break;
14640 case HWTSTAMP_FILTER_PTP_V2_EVENT:
14641 case HWTSTAMP_FILTER_PTP_V2_SYNC:
14642 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14643 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14644 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14645 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14646 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14647 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14648 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14649 break;
14650 }
14651
14652 /* Indicate to FW that this PF expects recorded PTP packets */
14653 rc = bnx2x_enable_ptp_packets(bp);
14654 if (rc)
14655 return rc;
14656
14657 /* Enable sending PTP packets to host */
14658 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14659 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14660
14661 return 0;
14662}
14663
14664static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14665{
14666 struct hwtstamp_config config;
14667 int rc;
14668
14669 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14670
14671 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14672 return -EFAULT;
14673
14674 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14675 config.tx_type, config.rx_filter);
14676
14677 if (config.flags) {
14678 BNX2X_ERR("config.flags is reserved for future use\n");
14679 return -EINVAL;
14680 }
14681
14682 bp->hwtstamp_ioctl_called = 1;
14683 bp->tx_type = config.tx_type;
14684 bp->rx_filter = config.rx_filter;
14685
14686 rc = bnx2x_configure_ptp_filters(bp);
14687 if (rc)
14688 return rc;
14689
14690 config.rx_filter = bp->rx_filter;
14691
14692 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14693 -EFAULT : 0;
14694}
14695
14696/* Configrues HW for PTP */
14697static int bnx2x_configure_ptp(struct bnx2x *bp)
14698{
14699 int rc, port = BP_PORT(bp);
14700 u32 wb_data[2];
14701
14702 /* Reset PTP event detection rules - will be configured in the IOCTL */
14703 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14704 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14705 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14706 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14707 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14708 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14709 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14710 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14711
14712 /* Disable PTP packets to host - will be configured in the IOCTL*/
14713 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14714 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14715
14716 /* Enable the PTP feature */
14717 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14718 NIG_REG_P0_PTP_EN, 0x3F);
14719
14720 /* Enable the free-running counter */
14721 wb_data[0] = 0;
14722 wb_data[1] = 0;
14723 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14724
14725 /* Reset drift register (offset register is not reset) */
14726 rc = bnx2x_send_reset_timesync_ramrod(bp);
14727 if (rc) {
14728 BNX2X_ERR("Failed to reset PHC drift register\n");
14729 return -EFAULT;
14730 }
14731
14732 /* Reset possibly old timestamps */
14733 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14734 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14735 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14736 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14737
14738 return 0;
14739}
14740
14741/* Called during load, to initialize PTP-related stuff */
14742void bnx2x_init_ptp(struct bnx2x *bp)
14743{
14744 int rc;
14745
14746 /* Configure PTP in HW */
14747 rc = bnx2x_configure_ptp(bp);
14748 if (rc) {
14749 BNX2X_ERR("Stopping PTP initialization\n");
14750 return;
14751 }
14752
14753 /* Init work queue for Tx timestamping */
14754 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14755
14756 /* Init cyclecounter and timecounter. This is done only in the first
14757 * load. If done in every load, PTP application will fail when doing
14758 * unload / load (e.g. MTU change) while it is running.
14759 */
14760 if (!bp->timecounter_init_done) {
14761 bnx2x_init_cyclecounter(bp);
14762 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14763 ktime_to_ns(ktime_get_real()));
14764 bp->timecounter_init_done = 1;
14765 }
14766
14767 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14768}
Linux 6.x block layer and io_uring tree(s)