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Merge branch 'pktgen'
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
08f6dd89 9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
24e3fcef 10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
33d8e6a5 30#include <linux/aer.h>
a2fbb9ea
ET		 31#include <linux/init.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/dma-mapping.h>
36#include <linux/bitops.h>
37#include <linux/irq.h>
38#include <linux/delay.h>
39#include <asm/byteorder.h>
40#include <linux/time.h>
41#include <linux/ethtool.h>
42#include <linux/mii.h>
0c6671b0 43#include <linux/if_vlan.h>
a2fbb9ea 44#include <net/ip.h>
619c5cb6 45#include <net/ipv6.h>
a2fbb9ea
ET		 46#include <net/tcp.h>
47#include <net/checksum.h>
34f80b04 48#include <net/ip6_checksum.h>
a2fbb9ea
ET		 49#include <linux/workqueue.h>
50#include <linux/crc32.h>
34f80b04 51#include <linux/crc32c.h>
a2fbb9ea
ET		 52#include <linux/prefetch.h>
53#include <linux/zlib.h>
a2fbb9ea 54#include <linux/io.h>
452427b0 55#include <linux/semaphore.h>
45229b42 56#include <linux/stringify.h>
7ab24bfd 57#include <linux/vmalloc.h>
a2fbb9ea 58
a2fbb9ea
ET		 59#include "bnx2x.h"
60#include "bnx2x_init.h"
94a78b79 61#include "bnx2x_init_ops.h"
9f6c9258 62#include "bnx2x_cmn.h"
1ab4434c 63#include "bnx2x_vfpf.h"
e4901dde 64#include "bnx2x_dcb.h"
042181f5 65#include "bnx2x_sp.h"
a2fbb9ea 66
94a78b79
VZ		 67#include <linux/firmware.h>
68#include "bnx2x_fw_file_hdr.h"
69/* FW files */
45229b42
BH		 70#define FW_FILE_VERSION \
71 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
72 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
73 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
74 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 75#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
76#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 77#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 78
34f80b04
EG		 79/* Time in jiffies before concluding the transmitter is hung */
80#define TX_TIMEOUT (5*HZ)
a2fbb9ea 81
0329aba1 82static char version[] =
619c5cb6 83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85
24e3fcef 86MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 87MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
a2fbb9ea
ET		 91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 93MODULE_FIRMWARE(FW_FILE_NAME_E1);
94MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 95MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 96
a8f47eb7 97int bnx2x_num_queues;
1c8bb760 98module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
96305234
DK		 99MODULE_PARM_DESC(num_queues,
100 " Set number of queues (default is as a number of CPUs)");
555f6c78 101
19680c48 102static int disable_tpa;
1c8bb760 103module_param(disable_tpa, int, S_IRUGO);
9898f86d 104MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 105
a8f47eb7 106static int int_mode;
1c8bb760 107module_param(int_mode, int, S_IRUGO);
619c5cb6 108MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 109 "(1 INT#x; 2 MSI)");
8badd27a 110
a18f5128 111static int dropless_fc;
1c8bb760 112module_param(dropless_fc, int, S_IRUGO);
a18f5128
EG		 113MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114
8d5726c4 115static int mrrs = -1;
1c8bb760 116module_param(mrrs, int, S_IRUGO);
8d5726c4
EG		 117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
9898f86d 119static int debug;
1c8bb760 120module_param(debug, int, S_IRUGO);
9898f86d
EG		 121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
370d4a26
YM		 123static struct workqueue_struct *bnx2x_wq;
124struct workqueue_struct *bnx2x_iov_wq;
ec6ba945 125
1ef1d45a
BW		 126struct bnx2x_mac_vals {
127 u32 xmac_addr;
128 u32 xmac_val;
129 u32 emac_addr;
130 u32 emac_val;
131 u32 umac_addr;
132 u32 umac_val;
133 u32 bmac_addr;
134 u32 bmac_val[2];
135};
136
a2fbb9ea
ET		 137enum bnx2x_board_type {
138 BCM57710 = 0,
619c5cb6
VZ		 139 BCM57711,
140 BCM57711E,
141 BCM57712,
142 BCM57712_MF,
1ab4434c 143 BCM57712_VF,
619c5cb6
VZ		 144 BCM57800,
145 BCM57800_MF,
1ab4434c 146 BCM57800_VF,
619c5cb6
VZ		 147 BCM57810,
148 BCM57810_MF,
1ab4434c 149 BCM57810_VF,
c3def943
YM		 150 BCM57840_4_10,
151 BCM57840_2_20,
7e8e02df 152 BCM57840_MF,
1ab4434c 153 BCM57840_VF,
7e8e02df 154 BCM57811,
1ab4434c
AE		 155 BCM57811_MF,
156 BCM57840_O,
157 BCM57840_MFO,
158 BCM57811_VF
a2fbb9ea
ET		 159};
160
34f80b04 161/* indexed by board_type, above */
53a10565 162static struct {
a2fbb9ea 163 char *name;
0329aba1 164} board_info[] = {
1ab4434c
AE		 165 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
166 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
167 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
168 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
169 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
170 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
171 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
172 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
173 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
174 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
175 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
176 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
177 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
178 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
179 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
180 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
181 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
182 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
183 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
184 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
185 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 186};
187
619c5cb6
VZ		 188#ifndef PCI_DEVICE_ID_NX2_57710
189#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
190#endif
191#ifndef PCI_DEVICE_ID_NX2_57711
192#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
193#endif
194#ifndef PCI_DEVICE_ID_NX2_57711E
195#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
196#endif
197#ifndef PCI_DEVICE_ID_NX2_57712
198#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
199#endif
200#ifndef PCI_DEVICE_ID_NX2_57712_MF
201#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
202#endif
8395be5e
AE		 203#ifndef PCI_DEVICE_ID_NX2_57712_VF
204#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
205#endif
619c5cb6
VZ		 206#ifndef PCI_DEVICE_ID_NX2_57800
207#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
208#endif
209#ifndef PCI_DEVICE_ID_NX2_57800_MF
210#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
211#endif
8395be5e
AE		 212#ifndef PCI_DEVICE_ID_NX2_57800_VF
213#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
214#endif
619c5cb6
VZ		 215#ifndef PCI_DEVICE_ID_NX2_57810
216#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
217#endif
218#ifndef PCI_DEVICE_ID_NX2_57810_MF
219#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
220#endif
c3def943
YM		 221#ifndef PCI_DEVICE_ID_NX2_57840_O
222#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
223#endif
8395be5e
AE		 224#ifndef PCI_DEVICE_ID_NX2_57810_VF
225#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
226#endif
c3def943
YM		 227#ifndef PCI_DEVICE_ID_NX2_57840_4_10
228#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
229#endif
230#ifndef PCI_DEVICE_ID_NX2_57840_2_20
231#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
232#endif
233#ifndef PCI_DEVICE_ID_NX2_57840_MFO
234#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 235#endif
236#ifndef PCI_DEVICE_ID_NX2_57840_MF
237#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
238#endif
8395be5e
AE		 239#ifndef PCI_DEVICE_ID_NX2_57840_VF
240#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
241#endif
7e8e02df
BW		 242#ifndef PCI_DEVICE_ID_NX2_57811
243#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
244#endif
245#ifndef PCI_DEVICE_ID_NX2_57811_MF
246#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
247#endif
8395be5e
AE		 248#ifndef PCI_DEVICE_ID_NX2_57811_VF
249#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
250#endif
251
a3aa1884 252static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 274 { 0 }
275};
276
277MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
278
452427b0
YM		 279/* Global resources for unloading a previously loaded device */
280#define BNX2X_PREV_WAIT_NEEDED 1
281static DEFINE_SEMAPHORE(bnx2x_prev_sem);
282static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 283
284/* Forward declaration */
285static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
286static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
287static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
288
a2fbb9ea
ET		 289/****************************************************************************
290* General service functions
291****************************************************************************/
292
1191cb83 293static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 294 u32 addr, dma_addr_t mapping)
295{
296 REG_WR(bp, addr, U64_LO(mapping));
297 REG_WR(bp, addr + 4, U64_HI(mapping));
298}
299
1191cb83
ED		 300static void storm_memset_spq_addr(struct bnx2x *bp,
301 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 302{
303 u32 addr = XSEM_REG_FAST_MEMORY +
304 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
305
306 __storm_memset_dma_mapping(bp, addr, mapping);
307}
308
1191cb83
ED		 309static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
310 u16 pf_id)
523224a3 311{
619c5cb6
VZ		 312 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
313 pf_id);
314 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
315 pf_id);
316 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
317 pf_id);
318 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
319 pf_id);
523224a3
DK		 320}
321
1191cb83
ED		 322static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
323 u8 enable)
619c5cb6
VZ		 324{
325 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
326 enable);
327 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
328 enable);
329 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
330 enable);
331 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
332 enable);
333}
523224a3 334
1191cb83
ED		 335static void storm_memset_eq_data(struct bnx2x *bp,
336 struct event_ring_data *eq_data,
523224a3
DK		 337 u16 pfid)
338{
339 size_t size = sizeof(struct event_ring_data);
340
341 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
342
343 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
344}
345
1191cb83
ED		 346static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
347 u16 pfid)
523224a3
DK		 348{
349 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
350 REG_WR16(bp, addr, eq_prod);
351}
352
a2fbb9ea
ET		 353/* used only at init
354 * locking is done by mcp
355 */
8d96286a 356static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 357{
358 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
359 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
360 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
361 PCICFG_VENDOR_ID_OFFSET);
362}
363
a2fbb9ea
ET		 364static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
365{
366 u32 val;
367
368 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
369 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
370 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
371 PCICFG_VENDOR_ID_OFFSET);
372
373 return val;
374}
a2fbb9ea 375
f2e0899f
DK		 376#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
377#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
378#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
379#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
380#define DMAE_DP_DST_NONE "dst_addr [none]"
381
6bf07b8e
YM		 382static void bnx2x_dp_dmae(struct bnx2x *bp,
383 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 384{
385 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 386 int i;
fd1fc79d
AE		 387
388 switch (dmae->opcode & DMAE_COMMAND_DST) {
389 case DMAE_CMD_DST_PCI:
390 if (src_type == DMAE_CMD_SRC_PCI)
391 DP(msglvl, "DMAE: opcode 0x%08x\n"
392 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
393 "comp_addr [%x:%08x], comp_val 0x%08x\n",
394 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
395 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
396 dmae->comp_addr_hi, dmae->comp_addr_lo,
397 dmae->comp_val);
398 else
399 DP(msglvl, "DMAE: opcode 0x%08x\n"
400 "src [%08x], len [%d*4], dst [%x:%08x]\n"
401 "comp_addr [%x:%08x], comp_val 0x%08x\n",
402 dmae->opcode, dmae->src_addr_lo >> 2,
403 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
404 dmae->comp_addr_hi, dmae->comp_addr_lo,
405 dmae->comp_val);
406 break;
407 case DMAE_CMD_DST_GRC:
408 if (src_type == DMAE_CMD_SRC_PCI)
409 DP(msglvl, "DMAE: opcode 0x%08x\n"
410 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
411 "comp_addr [%x:%08x], comp_val 0x%08x\n",
412 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
413 dmae->len, dmae->dst_addr_lo >> 2,
414 dmae->comp_addr_hi, dmae->comp_addr_lo,
415 dmae->comp_val);
416 else
417 DP(msglvl, "DMAE: opcode 0x%08x\n"
418 "src [%08x], len [%d*4], dst [%08x]\n"
419 "comp_addr [%x:%08x], comp_val 0x%08x\n",
420 dmae->opcode, dmae->src_addr_lo >> 2,
421 dmae->len, dmae->dst_addr_lo >> 2,
422 dmae->comp_addr_hi, dmae->comp_addr_lo,
423 dmae->comp_val);
424 break;
425 default:
426 if (src_type == DMAE_CMD_SRC_PCI)
427 DP(msglvl, "DMAE: opcode 0x%08x\n"
428 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
429 "comp_addr [%x:%08x] comp_val 0x%08x\n",
430 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
431 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
432 dmae->comp_val);
433 else
434 DP(msglvl, "DMAE: opcode 0x%08x\n"
435 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
436 "comp_addr [%x:%08x] comp_val 0x%08x\n",
437 dmae->opcode, dmae->src_addr_lo >> 2,
438 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
439 dmae->comp_val);
440 break;
441 }
6bf07b8e
YM		 442
443 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
444 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
445 i, *(((u32 *)dmae) + i));
fd1fc79d 446}
f2e0899f 447
a2fbb9ea 448/* copy command into DMAE command memory and set DMAE command go */
6c719d00 449void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 450{
451 u32 cmd_offset;
452 int i;
453
454 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
455 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
456 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 457 }
458 REG_WR(bp, dmae_reg_go_c[idx], 1);
459}
460
f2e0899f 461u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 462{
f2e0899f
DK		 463 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
464 DMAE_CMD_C_ENABLE);
465}
ad8d3948 466
f2e0899f
DK		 467u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
468{
469 return opcode & ~DMAE_CMD_SRC_RESET;
470}
ad8d3948 471
f2e0899f
DK		 472u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
473 bool with_comp, u8 comp_type)
474{
475 u32 opcode = 0;
476
477 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
478 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 479
f2e0899f
DK		 480 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
481
482 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 483 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
484 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 485 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 486
a2fbb9ea 487#ifdef __BIG_ENDIAN
f2e0899f 488 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 489#else
f2e0899f 490 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 491#endif
f2e0899f
DK		 492 if (with_comp)
493 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
494 return opcode;
495}
496
fd1fc79d 497void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 498 struct dmae_command *dmae,
499 u8 src_type, u8 dst_type)
f2e0899f
DK		 500{
501 memset(dmae, 0, sizeof(struct dmae_command));
502
503 /* set the opcode */
504 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
505 true, DMAE_COMP_PCI);
506
507 /* fill in the completion parameters */
508 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
509 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
510 dmae->comp_val = DMAE_COMP_VAL;
511}
512
fd1fc79d 513/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 514int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
515 u32 *comp)
f2e0899f 516{
5e374b5a 517 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 518 int rc = 0;
519
6bf07b8e
YM		 520 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
521
522 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 523 * as long as this code is called both from syscall context and
524 * from ndo_set_rx_mode() flow that may be called from BH.
525 */
6e30dd4e 526 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 527
f2e0899f 528 /* reset completion */
32316a46 529 *comp = 0;
a2fbb9ea 530
f2e0899f
DK		 531 /* post the command on the channel used for initializations */
532 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 533
f2e0899f 534 /* wait for completion */
a2fbb9ea 535 udelay(5);
32316a46 536 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 537
95c6c616
AE		 538 if (!cnt ||
539 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
540 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 541 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 542 rc = DMAE_TIMEOUT;
543 goto unlock;
a2fbb9ea 544 }
ad8d3948 545 cnt--;
f2e0899f 546 udelay(50);
a2fbb9ea 547 }
32316a46 548 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 549 BNX2X_ERR("DMAE PCI error!\n");
550 rc = DMAE_PCI_ERROR;
551 }
552
f2e0899f 553unlock:
6e30dd4e 554 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 555 return rc;
556}
557
558void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
559 u32 len32)
560{
6bf07b8e 561 int rc;
f2e0899f
DK		 562 struct dmae_command dmae;
563
564 if (!bp->dmae_ready) {
565 u32 *data = bnx2x_sp(bp, wb_data[0]);
566
127a425e
AE		 567 if (CHIP_IS_E1(bp))
568 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
569 else
570 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 571 return;
572 }
573
574 /* set opcode and fixed command fields */
575 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
576
577 /* fill in addresses and len */
578 dmae.src_addr_lo = U64_LO(dma_addr);
579 dmae.src_addr_hi = U64_HI(dma_addr);
580 dmae.dst_addr_lo = dst_addr >> 2;
581 dmae.dst_addr_hi = 0;
582 dmae.len = len32;
583
f2e0899f 584 /* issue the command and wait for completion */
32316a46 585 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 586 if (rc) {
587 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 588#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 589 bnx2x_panic();
9dcd9acd 590#endif
6bf07b8e 591 }
a2fbb9ea
ET		 592}
593
c18487ee 594void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 595{
6bf07b8e 596 int rc;
5ff7b6d4 597 struct dmae_command dmae;
ad8d3948
EG		 598
599 if (!bp->dmae_ready) {
600 u32 *data = bnx2x_sp(bp, wb_data[0]);
601 int i;
602
51c1a580 603 if (CHIP_IS_E1(bp))
127a425e
AE		 604 for (i = 0; i < len32; i++)
605 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 606 else
127a425e
AE		 607 for (i = 0; i < len32; i++)
608 data[i] = REG_RD(bp, src_addr + i*4);
609
ad8d3948
EG		 610 return;
611 }
612
f2e0899f
DK		 613 /* set opcode and fixed command fields */
614 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 615
f2e0899f 616 /* fill in addresses and len */
5ff7b6d4
EG		 617 dmae.src_addr_lo = src_addr >> 2;
618 dmae.src_addr_hi = 0;
619 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
620 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
621 dmae.len = len32;
ad8d3948 622
f2e0899f 623 /* issue the command and wait for completion */
32316a46 624 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 625 if (rc) {
626 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 627#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 628 bnx2x_panic();
9dcd9acd 629#endif
c957d09f 630 }
ad8d3948
EG		 631}
632
8d96286a 633static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
634 u32 addr, u32 len)
573f2035 635{
02e3c6cb 636 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 637 int offset = 0;
638
02e3c6cb 639 while (len > dmae_wr_max) {
573f2035 640 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 641 addr + offset, dmae_wr_max);
642 offset += dmae_wr_max * 4;
643 len -= dmae_wr_max;
573f2035
EG		 644 }
645
646 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
647}
648
a2fbb9ea
ET		 649static int bnx2x_mc_assert(struct bnx2x *bp)
650{
a2fbb9ea 651 char last_idx;
34f80b04
EG		 652 int i, rc = 0;
653 u32 row0, row1, row2, row3;
654
655 /* XSTORM */
656 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
657 XSTORM_ASSERT_LIST_INDEX_OFFSET);
658 if (last_idx)
659 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
660
661 /* print the asserts */
662 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
663
664 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
665 XSTORM_ASSERT_LIST_OFFSET(i));
666 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
667 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
668 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
669 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
670 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
671 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
672
673 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 674 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 675 i, row3, row2, row1, row0);
676 rc++;
677 } else {
678 break;
679 }
680 }
681
682 /* TSTORM */
683 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
684 TSTORM_ASSERT_LIST_INDEX_OFFSET);
685 if (last_idx)
686 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
687
688 /* print the asserts */
689 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
690
691 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
692 TSTORM_ASSERT_LIST_OFFSET(i));
693 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
694 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
695 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
696 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
697 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
698 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
699
700 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 701 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 702 i, row3, row2, row1, row0);
703 rc++;
704 } else {
705 break;
706 }
707 }
708
709 /* CSTORM */
710 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
711 CSTORM_ASSERT_LIST_INDEX_OFFSET);
712 if (last_idx)
713 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
714
715 /* print the asserts */
716 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
717
718 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
719 CSTORM_ASSERT_LIST_OFFSET(i));
720 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
721 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
722 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
723 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
724 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
725 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
726
727 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 728 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 729 i, row3, row2, row1, row0);
730 rc++;
731 } else {
732 break;
733 }
734 }
735
736 /* USTORM */
737 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
738 USTORM_ASSERT_LIST_INDEX_OFFSET);
739 if (last_idx)
740 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
741
742 /* print the asserts */
743 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
744
745 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
746 USTORM_ASSERT_LIST_OFFSET(i));
747 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
748 USTORM_ASSERT_LIST_OFFSET(i) + 4);
749 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
750 USTORM_ASSERT_LIST_OFFSET(i) + 8);
751 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
752 USTORM_ASSERT_LIST_OFFSET(i) + 12);
753
754 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 755 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 756 i, row3, row2, row1, row0);
757 rc++;
758 } else {
759 break;
a2fbb9ea
ET		 760 }
761 }
34f80b04 762
a2fbb9ea
ET		 763 return rc;
764}
c14423fe 765
1a6974b2
YM		 766#define MCPR_TRACE_BUFFER_SIZE (0x800)
767#define SCRATCH_BUFFER_SIZE(bp) \
768 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
769
7a25cc73 770void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 771{
7a25cc73 772 u32 addr, val;
a2fbb9ea 773 u32 mark, offset;
4781bfad 774 __be32 data[9];
a2fbb9ea 775 int word;
f2e0899f 776 u32 trace_shmem_base;
2145a920
VZ		 777 if (BP_NOMCP(bp)) {
778 BNX2X_ERR("NO MCP - can not dump\n");
779 return;
780 }
7a25cc73
DK		 781 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
782 (bp->common.bc_ver & 0xff0000) >> 16,
783 (bp->common.bc_ver & 0xff00) >> 8,
784 (bp->common.bc_ver & 0xff));
785
786 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
787 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 788 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 789
f2e0899f
DK		 790 if (BP_PATH(bp) == 0)
791 trace_shmem_base = bp->common.shmem_base;
792 else
793 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 794
795 /* sanity */
796 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
797 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
798 SCRATCH_BUFFER_SIZE(bp)) {
799 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
800 trace_shmem_base);
801 return;
802 }
803
804 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 805
806 /* validate TRCB signature */
807 mark = REG_RD(bp, addr);
808 if (mark != MFW_TRACE_SIGNATURE) {
809 BNX2X_ERR("Trace buffer signature is missing.");
810 return ;
811 }
812
813 /* read cyclic buffer pointer */
814 addr += 4;
cdaa7cb8 815 mark = REG_RD(bp, addr);
1a6974b2
YM		 816 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
817 if (mark >= trace_shmem_base || mark < addr + 4) {
818 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
819 return;
820 }
7a25cc73 821 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 822
7a25cc73 823 printk("%s", lvl);
2de67439
YM		 824
825 /* dump buffer after the mark */
1a6974b2 826 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 827 for (word = 0; word < 8; word++)
cdaa7cb8 828 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 829 data[8] = 0x0;
7995c64e 830 pr_cont("%s", (char *)data);
a2fbb9ea 831 }
2de67439
YM		 832
833 /* dump buffer before the mark */
cdaa7cb8 834 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 835 for (word = 0; word < 8; word++)
cdaa7cb8 836 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 837 data[8] = 0x0;
7995c64e 838 pr_cont("%s", (char *)data);
a2fbb9ea 839 }
7a25cc73
DK		 840 printk("%s" "end of fw dump\n", lvl);
841}
842
1191cb83 843static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 844{
845 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 846}
847
823e1d90
YM		 848static void bnx2x_hc_int_disable(struct bnx2x *bp)
849{
850 int port = BP_PORT(bp);
851 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
852 u32 val = REG_RD(bp, addr);
853
854 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 855 * MSI/MSIX capability
856 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 857 */
858 if (CHIP_IS_E1(bp)) {
859 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
860 * Use mask register to prevent from HC sending interrupts
861 * after we exit the function
862 */
863 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
864
865 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
866 HC_CONFIG_0_REG_INT_LINE_EN_0 |
867 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
868 } else
869 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
870 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
871 HC_CONFIG_0_REG_INT_LINE_EN_0 |
872 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
873
874 DP(NETIF_MSG_IFDOWN,
875 "write %x to HC %d (addr 0x%x)\n",
876 val, port, addr);
877
878 /* flush all outstanding writes */
879 mmiowb();
880
881 REG_WR(bp, addr, val);
882 if (REG_RD(bp, addr) != val)
6bf07b8e 883 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 884}
885
886static void bnx2x_igu_int_disable(struct bnx2x *bp)
887{
888 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
889
890 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
891 IGU_PF_CONF_INT_LINE_EN |
892 IGU_PF_CONF_ATTN_BIT_EN);
893
894 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
895
896 /* flush all outstanding writes */
897 mmiowb();
898
899 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
900 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 901 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 902}
903
904static void bnx2x_int_disable(struct bnx2x *bp)
905{
906 if (bp->common.int_block == INT_BLOCK_HC)
907 bnx2x_hc_int_disable(bp);
908 else
909 bnx2x_igu_int_disable(bp);
910}
911
912void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 913{
914 int i;
523224a3
DK		 915 u16 j;
916 struct hc_sp_status_block_data sp_sb_data;
917 int func = BP_FUNC(bp);
918#ifdef BNX2X_STOP_ON_ERROR
919 u16 start = 0, end = 0;
6383c0b3 920 u8 cos;
523224a3 921#endif
0155a27c 922 if (IS_PF(bp) && disable_int)
823e1d90 923 bnx2x_int_disable(bp);
a2fbb9ea 924
66e855f3 925 bp->stats_state = STATS_STATE_DISABLED;
7a752993 926 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 927 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
928
a2fbb9ea
ET		 929 BNX2X_ERR("begin crash dump -----------------\n");
930
8440d2b6
EG		 931 /* Indices */
932 /* Common */
0155a27c
YM		 933 if (IS_PF(bp)) {
934 struct host_sp_status_block *def_sb = bp->def_status_blk;
935 int data_size, cstorm_offset;
936
937 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
938 bp->def_idx, bp->def_att_idx, bp->attn_state,
939 bp->spq_prod_idx, bp->stats_counter);
940 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
941 def_sb->atten_status_block.attn_bits,
942 def_sb->atten_status_block.attn_bits_ack,
943 def_sb->atten_status_block.status_block_id,
944 def_sb->atten_status_block.attn_bits_index);
945 BNX2X_ERR(" def (");
946 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
947 pr_cont("0x%x%s",
948 def_sb->sp_sb.index_values[i],
949 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
950
951 data_size = sizeof(struct hc_sp_status_block_data) /
952 sizeof(u32);
953 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
954 for (i = 0; i < data_size; i++)
955 *((u32 *)&sp_sb_data + i) =
956 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
957 i * sizeof(u32));
958
959 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
960 sp_sb_data.igu_sb_id,
961 sp_sb_data.igu_seg_id,
962 sp_sb_data.p_func.pf_id,
963 sp_sb_data.p_func.vnic_id,
964 sp_sb_data.p_func.vf_id,
965 sp_sb_data.p_func.vf_valid,
966 sp_sb_data.state);
967 }
523224a3 968
ec6ba945 969 for_each_eth_queue(bp, i) {
a2fbb9ea 970 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 971 int loop;
f2e0899f 972 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 973 struct hc_status_block_data_e1x sb_data_e1x;
974 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 975 CHIP_IS_E1x(bp) ?
976 sb_data_e1x.common.state_machine :
977 sb_data_e2.common.state_machine;
523224a3 978 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 979 CHIP_IS_E1x(bp) ?
980 sb_data_e1x.index_data :
981 sb_data_e2.index_data;
6383c0b3 982 u8 data_size, cos;
523224a3 983 u32 *sb_data_p;
6383c0b3 984 struct bnx2x_fp_txdata txdata;
523224a3
DK		 985
986 /* Rx */
51c1a580 987 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 988 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 989 fp->rx_comp_prod,
66e855f3 990 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 991 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 992 fp->rx_sge_prod, fp->last_max_sge,
523224a3 993 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 994
523224a3 995 /* Tx */
6383c0b3
AE		 996 for_each_cos_in_tx_queue(fp, cos)
997 {
65565884 998 txdata = *fp->txdata_ptr[cos];
51c1a580 999 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 1000 i, txdata.tx_pkt_prod,
1001 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1002 txdata.tx_bd_cons,
1003 le16_to_cpu(*txdata.tx_cons_sb));
1004 }
523224a3 1005
619c5cb6
VZ		 1006 loop = CHIP_IS_E1x(bp) ?
1007 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1008
1009 /* host sb data */
1010
ec6ba945
VZ		 1011 if (IS_FCOE_FP(fp))
1012 continue;
55c11941 1013
523224a3
DK		 1014 BNX2X_ERR(" run indexes (");
1015 for (j = 0; j < HC_SB_MAX_SM; j++)
1016 pr_cont("0x%x%s",
1017 fp->sb_running_index[j],
1018 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1019
1020 BNX2X_ERR(" indexes (");
1021 for (j = 0; j < loop; j++)
1022 pr_cont("0x%x%s",
1023 fp->sb_index_values[j],
1024 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1025
1026 /* VF cannot access FW refelection for status block */
1027 if (IS_VF(bp))
1028 continue;
1029
523224a3 1030 /* fw sb data */
619c5cb6
VZ		 1031 data_size = CHIP_IS_E1x(bp) ?
1032 sizeof(struct hc_status_block_data_e1x) :
1033 sizeof(struct hc_status_block_data_e2);
523224a3 1034 data_size /= sizeof(u32);
619c5cb6
VZ		 1035 sb_data_p = CHIP_IS_E1x(bp) ?
1036 (u32 *)&sb_data_e1x :
1037 (u32 *)&sb_data_e2;
523224a3
DK		 1038 /* copy sb data in here */
1039 for (j = 0; j < data_size; j++)
1040 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1041 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1042 j * sizeof(u32));
1043
619c5cb6 1044 if (!CHIP_IS_E1x(bp)) {
51c1a580 1045 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1046 sb_data_e2.common.p_func.pf_id,
1047 sb_data_e2.common.p_func.vf_id,
1048 sb_data_e2.common.p_func.vf_valid,
1049 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1050 sb_data_e2.common.same_igu_sb_1b,
1051 sb_data_e2.common.state);
f2e0899f 1052 } else {
51c1a580 1053 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1054 sb_data_e1x.common.p_func.pf_id,
1055 sb_data_e1x.common.p_func.vf_id,
1056 sb_data_e1x.common.p_func.vf_valid,
1057 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1058 sb_data_e1x.common.same_igu_sb_1b,
1059 sb_data_e1x.common.state);
f2e0899f 1060 }
523224a3
DK		 1061
1062 /* SB_SMs data */
1063 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1064 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1065 j, hc_sm_p[j].__flags,
1066 hc_sm_p[j].igu_sb_id,
1067 hc_sm_p[j].igu_seg_id,
1068 hc_sm_p[j].time_to_expire,
1069 hc_sm_p[j].timer_value);
523224a3
DK		 1070 }
1071
16a5fd92 1072 /* Indices data */
523224a3 1073 for (j = 0; j < loop; j++) {
51c1a580 1074 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1075 hc_index_p[j].flags,
1076 hc_index_p[j].timeout);
1077 }
8440d2b6 1078 }
a2fbb9ea 1079
523224a3 1080#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1081 if (IS_PF(bp)) {
1082 /* event queue */
1083 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1084 for (i = 0; i < NUM_EQ_DESC; i++) {
1085 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1086
1087 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1088 i, bp->eq_ring[i].message.opcode,
1089 bp->eq_ring[i].message.error);
1090 BNX2X_ERR("data: %x %x %x\n",
1091 data[0], data[1], data[2]);
1092 }
04c46736
YM		 1093 }
1094
8440d2b6
EG		 1095 /* Rings */
1096 /* Rx */
55c11941 1097 for_each_valid_rx_queue(bp, i) {
8440d2b6 1098 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 1099
1100 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1101 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1102 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1103 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1104 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1105
c3eefaf6 1106 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1107 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1108 }
1109
3196a88a
EG		 1110 start = RX_SGE(fp->rx_sge_prod);
1111 end = RX_SGE(fp->last_max_sge);
8440d2b6 1112 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1113 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1114 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1115
c3eefaf6
EG		 1116 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1117 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1118 }
1119
a2fbb9ea
ET		 1120 start = RCQ_BD(fp->rx_comp_cons - 10);
1121 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1122 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1123 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1124
c3eefaf6
EG		 1125 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1126 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1127 }
1128 }
1129
8440d2b6 1130 /* Tx */
55c11941 1131 for_each_valid_tx_queue(bp, i) {
8440d2b6 1132 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3 1133 for_each_cos_in_tx_queue(fp, cos) {
65565884 1134 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3
AE		 1135
1136 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1137 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1138 for (j = start; j != end; j = TX_BD(j + 1)) {
1139 struct sw_tx_bd *sw_bd =
1140 &txdata->tx_buf_ring[j];
1141
51c1a580 1142 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1143 i, cos, j, sw_bd->skb,
1144 sw_bd->first_bd);
1145 }
8440d2b6 1146
6383c0b3
AE		 1147 start = TX_BD(txdata->tx_bd_cons - 10);
1148 end = TX_BD(txdata->tx_bd_cons + 254);
1149 for (j = start; j != end; j = TX_BD(j + 1)) {
1150 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1151
51c1a580 1152 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1153 i, cos, j, tx_bd[0], tx_bd[1],
1154 tx_bd[2], tx_bd[3]);
1155 }
8440d2b6
EG		 1156 }
1157 }
523224a3 1158#endif
0155a27c
YM		 1159 if (IS_PF(bp)) {
1160 bnx2x_fw_dump(bp);
1161 bnx2x_mc_assert(bp);
1162 }
a2fbb9ea 1163 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1164}
1165
619c5cb6
VZ		 1166/*
1167 * FLR Support for E2
1168 *
1169 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1170 * initialization.
1171 */
16a5fd92 1172#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1173#define FLR_WAIT_INTERVAL 50 /* usec */
1174#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1175
1176struct pbf_pN_buf_regs {
1177 int pN;
1178 u32 init_crd;
1179 u32 crd;
1180 u32 crd_freed;
1181};
1182
1183struct pbf_pN_cmd_regs {
1184 int pN;
1185 u32 lines_occup;
1186 u32 lines_freed;
1187};
1188
1189static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1190 struct pbf_pN_buf_regs *regs,
1191 u32 poll_count)
1192{
1193 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1194 u32 cur_cnt = poll_count;
1195
1196 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1197 crd = crd_start = REG_RD(bp, regs->crd);
1198 init_crd = REG_RD(bp, regs->init_crd);
1199
1200 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1201 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1202 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1203
1204 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1205 (init_crd - crd_start))) {
1206 if (cur_cnt--) {
89db4ad8 1207 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1208 crd = REG_RD(bp, regs->crd);
1209 crd_freed = REG_RD(bp, regs->crd_freed);
1210 } else {
1211 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1212 regs->pN);
1213 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1214 regs->pN, crd);
1215 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1216 regs->pN, crd_freed);
1217 break;
1218 }
1219 }
1220 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1221 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1222}
1223
1224static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1225 struct pbf_pN_cmd_regs *regs,
1226 u32 poll_count)
1227{
1228 u32 occup, to_free, freed, freed_start;
1229 u32 cur_cnt = poll_count;
1230
1231 occup = to_free = REG_RD(bp, regs->lines_occup);
1232 freed = freed_start = REG_RD(bp, regs->lines_freed);
1233
1234 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1235 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1236
1237 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1238 if (cur_cnt--) {
89db4ad8 1239 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1240 occup = REG_RD(bp, regs->lines_occup);
1241 freed = REG_RD(bp, regs->lines_freed);
1242 } else {
1243 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1244 regs->pN);
1245 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1246 regs->pN, occup);
1247 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1248 regs->pN, freed);
1249 break;
1250 }
1251 }
1252 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1253 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1254}
1255
1191cb83
ED		 1256static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1257 u32 expected, u32 poll_count)
619c5cb6
VZ		 1258{
1259 u32 cur_cnt = poll_count;
1260 u32 val;
1261
1262 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1263 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1264
1265 return val;
1266}
1267
d16132ce
AE		 1268int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1269 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1270{
1271 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1272 if (val != 0) {
1273 BNX2X_ERR("%s usage count=%d\n", msg, val);
1274 return 1;
1275 }
1276 return 0;
1277}
1278
d16132ce
AE		 1279/* Common routines with VF FLR cleanup */
1280u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1281{
1282 /* adjust polling timeout */
1283 if (CHIP_REV_IS_EMUL(bp))
1284 return FLR_POLL_CNT * 2000;
1285
1286 if (CHIP_REV_IS_FPGA(bp))
1287 return FLR_POLL_CNT * 120;
1288
1289 return FLR_POLL_CNT;
1290}
1291
d16132ce 1292void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1293{
1294 struct pbf_pN_cmd_regs cmd_regs[] = {
1295 {0, (CHIP_IS_E3B0(bp)) ?
1296 PBF_REG_TQ_OCCUPANCY_Q0 :
1297 PBF_REG_P0_TQ_OCCUPANCY,
1298 (CHIP_IS_E3B0(bp)) ?
1299 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1300 PBF_REG_P0_TQ_LINES_FREED_CNT},
1301 {1, (CHIP_IS_E3B0(bp)) ?
1302 PBF_REG_TQ_OCCUPANCY_Q1 :
1303 PBF_REG_P1_TQ_OCCUPANCY,
1304 (CHIP_IS_E3B0(bp)) ?
1305 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1306 PBF_REG_P1_TQ_LINES_FREED_CNT},
1307 {4, (CHIP_IS_E3B0(bp)) ?
1308 PBF_REG_TQ_OCCUPANCY_LB_Q :
1309 PBF_REG_P4_TQ_OCCUPANCY,
1310 (CHIP_IS_E3B0(bp)) ?
1311 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1312 PBF_REG_P4_TQ_LINES_FREED_CNT}
1313 };
1314
1315 struct pbf_pN_buf_regs buf_regs[] = {
1316 {0, (CHIP_IS_E3B0(bp)) ?
1317 PBF_REG_INIT_CRD_Q0 :
1318 PBF_REG_P0_INIT_CRD ,
1319 (CHIP_IS_E3B0(bp)) ?
1320 PBF_REG_CREDIT_Q0 :
1321 PBF_REG_P0_CREDIT,
1322 (CHIP_IS_E3B0(bp)) ?
1323 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1324 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1325 {1, (CHIP_IS_E3B0(bp)) ?
1326 PBF_REG_INIT_CRD_Q1 :
1327 PBF_REG_P1_INIT_CRD,
1328 (CHIP_IS_E3B0(bp)) ?
1329 PBF_REG_CREDIT_Q1 :
1330 PBF_REG_P1_CREDIT,
1331 (CHIP_IS_E3B0(bp)) ?
1332 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1333 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1334 {4, (CHIP_IS_E3B0(bp)) ?
1335 PBF_REG_INIT_CRD_LB_Q :
1336 PBF_REG_P4_INIT_CRD,
1337 (CHIP_IS_E3B0(bp)) ?
1338 PBF_REG_CREDIT_LB_Q :
1339 PBF_REG_P4_CREDIT,
1340 (CHIP_IS_E3B0(bp)) ?
1341 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1342 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1343 };
1344
1345 int i;
1346
1347 /* Verify the command queues are flushed P0, P1, P4 */
1348 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1349 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1350
619c5cb6
VZ		 1351 /* Verify the transmission buffers are flushed P0, P1, P4 */
1352 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1353 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1354}
1355
1356#define OP_GEN_PARAM(param) \
1357 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1358
1359#define OP_GEN_TYPE(type) \
1360 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1361
1362#define OP_GEN_AGG_VECT(index) \
1363 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1364
d16132ce 1365int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1366{
86564c3f 1367 u32 op_gen_command = 0;
619c5cb6
VZ		 1368 u32 comp_addr = BAR_CSTRORM_INTMEM +
1369 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1370 int ret = 0;
1371
1372 if (REG_RD(bp, comp_addr)) {
89db4ad8 1373 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1374 return 1;
1375 }
1376
86564c3f
YM		 1377 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1378 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1379 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1380 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1381
89db4ad8 1382 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1383 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1384
1385 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1386 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1387 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1388 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1389 bnx2x_panic();
1390 return 1;
619c5cb6 1391 }
16a5fd92 1392 /* Zero completion for next FLR */
619c5cb6
VZ		 1393 REG_WR(bp, comp_addr, 0);
1394
1395 return ret;
1396}
1397
b56e9670 1398u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1399{
619c5cb6
VZ		 1400 u16 status;
1401
2a80eebc 1402 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1403 return status & PCI_EXP_DEVSTA_TRPND;
1404}
1405
1406/* PF FLR specific routines
1407*/
1408static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1409{
619c5cb6
VZ		 1410 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1411 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1412 CFC_REG_NUM_LCIDS_INSIDE_PF,
1413 "CFC PF usage counter timed out",
1414 poll_cnt))
1415 return 1;
1416
619c5cb6
VZ		 1417 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1418 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1419 DORQ_REG_PF_USAGE_CNT,
1420 "DQ PF usage counter timed out",
1421 poll_cnt))
1422 return 1;
1423
1424 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1425 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1426 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1427 "QM PF usage counter timed out",
1428 poll_cnt))
1429 return 1;
1430
1431 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1432 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1433 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1434 "Timers VNIC usage counter timed out",
1435 poll_cnt))
1436 return 1;
1437 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1438 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1439 "Timers NUM_SCANS usage counter timed out",
1440 poll_cnt))
1441 return 1;
1442
1443 /* Wait DMAE PF usage counter to zero */
1444 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1445 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1446 "DMAE command register timed out",
619c5cb6
VZ		 1447 poll_cnt))
1448 return 1;
1449
1450 return 0;
1451}
1452
1453static void bnx2x_hw_enable_status(struct bnx2x *bp)
1454{
1455 u32 val;
1456
1457 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1458 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1459
1460 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1461 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1462
1463 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1464 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1465
1466 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1467 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1468
1469 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1470 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1471
1472 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1473 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1474
1475 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1476 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1477
1478 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1479 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1480 val);
1481}
1482
1483static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1484{
1485 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1486
1487 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1488
1489 /* Re-enable PF target read access */
1490 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1491
1492 /* Poll HW usage counters */
89db4ad8 1493 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1494 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1495 return -EBUSY;
1496
1497 /* Zero the igu 'trailing edge' and 'leading edge' */
1498
1499 /* Send the FW cleanup command */
1500 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1501 return -EBUSY;
1502
1503 /* ATC cleanup */
1504
1505 /* Verify TX hw is flushed */
1506 bnx2x_tx_hw_flushed(bp, poll_cnt);
1507
1508 /* Wait 100ms (not adjusted according to platform) */
1509 msleep(100);
1510
1511 /* Verify no pending pci transactions */
1512 if (bnx2x_is_pcie_pending(bp->pdev))
1513 BNX2X_ERR("PCIE Transactions still pending\n");
1514
1515 /* Debug */
1516 bnx2x_hw_enable_status(bp);
1517
1518 /*
1519 * Master enable - Due to WB DMAE writes performed before this
1520 * register is re-initialized as part of the regular function init
1521 */
1522 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1523
1524 return 0;
1525}
1526
f2e0899f 1527static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1528{
34f80b04 1529 int port = BP_PORT(bp);
a2fbb9ea
ET		 1530 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1531 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1532 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1533 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1534 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1535
1536 if (msix) {
8badd27a
EG		 1537 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1538 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1539 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1540 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1541 if (single_msix)
1542 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1543 } else if (msi) {
1544 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1545 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1546 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1547 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1548 } else {
1549 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1550 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1551 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1552 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1553
a0fd065c 1554 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1555 DP(NETIF_MSG_IFUP,
1556 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1557
a0fd065c 1558 REG_WR(bp, addr, val);
615f8fd9 1559
a0fd065c
DK		 1560 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1561 }
a2fbb9ea
ET		 1562 }
1563
a0fd065c
DK		 1564 if (CHIP_IS_E1(bp))
1565 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1566
51c1a580
MS		 1567 DP(NETIF_MSG_IFUP,
1568 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1569 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1570
1571 REG_WR(bp, addr, val);
37dbbf32
EG		 1572 /*
1573 * Ensure that HC_CONFIG is written before leading/trailing edge config
1574 */
1575 mmiowb();
1576 barrier();
34f80b04 1577
f2e0899f 1578 if (!CHIP_IS_E1(bp)) {
34f80b04 1579 /* init leading/trailing edge */
fb3bff17 1580 if (IS_MF(bp)) {
3395a033 1581 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1582 if (bp->port.pmf)
4acac6a5
EG		 1583 /* enable nig and gpio3 attention */
1584 val |= 0x1100;
34f80b04
EG		 1585 } else
1586 val = 0xffff;
1587
1588 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1589 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1590 }
37dbbf32
EG		 1591
1592 /* Make sure that interrupts are indeed enabled from here on */
1593 mmiowb();
a2fbb9ea
ET		 1594}
1595
f2e0899f
DK		 1596static void bnx2x_igu_int_enable(struct bnx2x *bp)
1597{
1598 u32 val;
30a5de77
DK		 1599 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1600 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1601 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1602
1603 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1604
1605 if (msix) {
1606 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1607 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1608 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1609 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1610
1611 if (single_msix)
1612 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1613 } else if (msi) {
1614 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1615 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1616 IGU_PF_CONF_ATTN_BIT_EN |
1617 IGU_PF_CONF_SINGLE_ISR_EN);
1618 } else {
1619 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1620 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1621 IGU_PF_CONF_ATTN_BIT_EN |
1622 IGU_PF_CONF_SINGLE_ISR_EN);
1623 }
1624
ebe61d80
YM		 1625 /* Clean previous status - need to configure igu prior to ack*/
1626 if ((!msix) || single_msix) {
1627 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1628 bnx2x_ack_int(bp);
1629 }
1630
1631 val |= IGU_PF_CONF_FUNC_EN;
1632
51c1a580 1633 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1634 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1635
1636 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1637
79a8557a
YM		 1638 if (val & IGU_PF_CONF_INT_LINE_EN)
1639 pci_intx(bp->pdev, true);
1640
f2e0899f
DK		 1641 barrier();
1642
1643 /* init leading/trailing edge */
1644 if (IS_MF(bp)) {
3395a033 1645 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1646 if (bp->port.pmf)
1647 /* enable nig and gpio3 attention */
1648 val |= 0x1100;
1649 } else
1650 val = 0xffff;
1651
1652 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1653 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1654
1655 /* Make sure that interrupts are indeed enabled from here on */
1656 mmiowb();
1657}
1658
1659void bnx2x_int_enable(struct bnx2x *bp)
1660{
1661 if (bp->common.int_block == INT_BLOCK_HC)
1662 bnx2x_hc_int_enable(bp);
1663 else
1664 bnx2x_igu_int_enable(bp);
1665}
1666
9f6c9258 1667void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1668{
a2fbb9ea 1669 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1670 int i, offset;
a2fbb9ea 1671
f8ef6e44
YG		 1672 if (disable_hw)
1673 /* prevent the HW from sending interrupts */
1674 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1675
1676 /* make sure all ISRs are done */
1677 if (msix) {
8badd27a
EG		 1678 synchronize_irq(bp->msix_table[0].vector);
1679 offset = 1;
55c11941
MS		 1680 if (CNIC_SUPPORT(bp))
1681 offset++;
ec6ba945 1682 for_each_eth_queue(bp, i)
754a2f52 1683 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1684 } else
1685 synchronize_irq(bp->pdev->irq);
1686
1687 /* make sure sp_task is not running */
1cf167f2 1688 cancel_delayed_work(&bp->sp_task);
3deb8167 1689 cancel_delayed_work(&bp->period_task);
1cf167f2 1690 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1691}
1692
34f80b04 1693/* fast path */
a2fbb9ea
ET		 1694
1695/*
34f80b04 1696 * General service functions
a2fbb9ea
ET		 1697 */
1698
72fd0718
VZ		 1699/* Return true if succeeded to acquire the lock */
1700static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1701{
1702 u32 lock_status;
1703 u32 resource_bit = (1 << resource);
1704 int func = BP_FUNC(bp);
1705 u32 hw_lock_control_reg;
1706
51c1a580
MS		 1707 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1708 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1709
1710 /* Validating that the resource is within range */
1711 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1712 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1713 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1714 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1715 return false;
72fd0718
VZ		 1716 }
1717
1718 if (func <= 5)
1719 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1720 else
1721 hw_lock_control_reg =
1722 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1723
1724 /* Try to acquire the lock */
1725 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1726 lock_status = REG_RD(bp, hw_lock_control_reg);
1727 if (lock_status & resource_bit)
1728 return true;
1729
51c1a580
MS		 1730 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1731 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1732 return false;
1733}
1734
c9ee9206
VZ		 1735/**
1736 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1737 *
1738 * @bp: driver handle
1739 *
1740 * Returns the recovery leader resource id according to the engine this function
1741 * belongs to. Currently only only 2 engines is supported.
1742 */
1191cb83 1743static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1744{
1745 if (BP_PATH(bp))
1746 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1747 else
1748 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1749}
1750
1751/**
2de67439 1752 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1753 *
1754 * @bp: driver handle
1755 *
2de67439 1756 * Tries to acquire a leader lock for current engine.
c9ee9206 1757 */
1191cb83 1758static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1759{
1760 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1761}
1762
619c5cb6 1763static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1764
fd1fc79d
AE		 1765/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1766static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1767{
1768 /* Set the interrupt occurred bit for the sp-task to recognize it
1769 * must ack the interrupt and transition according to the IGU
1770 * state machine.
1771 */
1772 atomic_set(&bp->interrupt_occurred, 1);
1773
1774 /* The sp_task must execute only after this bit
1775 * is set, otherwise we will get out of sync and miss all
1776 * further interrupts. Hence, the barrier.
1777 */
1778 smp_wmb();
1779
1780 /* schedule sp_task to workqueue */
1781 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1782}
3196a88a 1783
619c5cb6 1784void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1785{
1786 struct bnx2x *bp = fp->bp;
1787 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1788 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1789 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1790 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1791
34f80b04 1792 DP(BNX2X_MSG_SP,
a2fbb9ea 1793 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1794 fp->index, cid, command, bp->state,
34f80b04 1795 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1796
fd1fc79d
AE		 1797 /* If cid is within VF range, replace the slowpath object with the
1798 * one corresponding to this VF
1799 */
1800 if (cid >= BNX2X_FIRST_VF_CID &&
1801 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1802 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1803
619c5cb6
VZ		 1804 switch (command) {
1805 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1806 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1807 drv_cmd = BNX2X_Q_CMD_UPDATE;
1808 break;
d6cae238 1809
619c5cb6 1810 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1811 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1812 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1813 break;
1814
6383c0b3 1815 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1816 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1817 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1818 break;
1819
619c5cb6 1820 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1821 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1822 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1823 break;
1824
619c5cb6 1825 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1826 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1827 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1828 break;
1829
619c5cb6 1830 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1831 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1832 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1833 break;
619c5cb6 1834
14a94ebd
MK		 1835 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1836 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1837 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1838 break;
1839
619c5cb6
VZ		 1840 default:
1841 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1842 command, fp->index);
1843 return;
523224a3 1844 }
3196a88a 1845
619c5cb6
VZ		 1846 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1847 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1848 /* q_obj->complete_cmd() failure means that this was
1849 * an unexpected completion.
1850 *
1851 * In this case we don't want to increase the bp->spq_left
1852 * because apparently we haven't sent this command the first
1853 * place.
1854 */
1855#ifdef BNX2X_STOP_ON_ERROR
1856 bnx2x_panic();
1857#else
1858 return;
1859#endif
1860
4e857c58 1861 smp_mb__before_atomic();
6e30dd4e 1862 atomic_inc(&bp->cq_spq_left);
619c5cb6 1863 /* push the change in bp->spq_left and towards the memory */
4e857c58 1864 smp_mb__after_atomic();
49d66772 1865
d6cae238
VZ		 1866 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1867
a3348722
BW		 1868 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1869 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1870 /* if Q update ramrod is completed for last Q in AFEX vif set
1871 * flow, then ACK MCP at the end
1872 *
1873 * mark pending ACK to MCP bit.
1874 * prevent case that both bits are cleared.
1875 * At the end of load/unload driver checks that
2de67439 1876 * sp_state is cleared, and this order prevents
a3348722
BW		 1877 * races
1878 */
4e857c58 1879 smp_mb__before_atomic();
a3348722
BW		 1880 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1881 wmb();
1882 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 1883 smp_mb__after_atomic();
a3348722 1884
fd1fc79d
AE		 1885 /* schedule the sp task as mcp ack is required */
1886 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1887 }
1888
523224a3 1889 return;
a2fbb9ea
ET		 1890}
1891
9f6c9258 1892irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1893{
555f6c78 1894 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1895 u16 status = bnx2x_ack_int(bp);
34f80b04 1896 u16 mask;
ca00392c 1897 int i;
6383c0b3 1898 u8 cos;
a2fbb9ea 1899
34f80b04 1900 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1901 if (unlikely(status == 0)) {
1902 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1903 return IRQ_NONE;
1904 }
f5372251 1905 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1906
3196a88a
EG		 1907#ifdef BNX2X_STOP_ON_ERROR
1908 if (unlikely(bp->panic))
1909 return IRQ_HANDLED;
1910#endif
1911
ec6ba945 1912 for_each_eth_queue(bp, i) {
ca00392c 1913 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1914
55c11941 1915 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1916 if (status & mask) {
619c5cb6 1917 /* Handle Rx or Tx according to SB id */
6383c0b3 1918 for_each_cos_in_tx_queue(fp, cos)
65565884 1919 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1920 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1921 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1922 status &= ~mask;
1923 }
a2fbb9ea
ET		 1924 }
1925
55c11941
MS		 1926 if (CNIC_SUPPORT(bp)) {
1927 mask = 0x2;
1928 if (status & (mask | 0x1)) {
1929 struct cnic_ops *c_ops = NULL;
993ac7b5 1930
ad9b4359
MC		 1931 rcu_read_lock();
1932 c_ops = rcu_dereference(bp->cnic_ops);
1933 if (c_ops && (bp->cnic_eth_dev.drv_state &
1934 CNIC_DRV_STATE_HANDLES_IRQ))
1935 c_ops->cnic_handler(bp->cnic_data, NULL);
1936 rcu_read_unlock();
993ac7b5 1937
55c11941
MS		 1938 status &= ~mask;
1939 }
993ac7b5 1940 }
a2fbb9ea 1941
34f80b04 1942 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1943
1944 /* schedule sp task to perform default status block work, ack
1945 * attentions and enable interrupts.
1946 */
1947 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1948
1949 status &= ~0x1;
1950 if (!status)
1951 return IRQ_HANDLED;
1952 }
1953
cdaa7cb8
VZ		 1954 if (unlikely(status))
1955 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1956 status);
a2fbb9ea 1957
c18487ee 1958 return IRQ_HANDLED;
a2fbb9ea
ET		 1959}
1960
c18487ee
YR		 1961/* Link */
1962
1963/*
1964 * General service functions
1965 */
a2fbb9ea 1966
9f6c9258 1967int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1968{
1969 u32 lock_status;
1970 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1971 int func = BP_FUNC(bp);
1972 u32 hw_lock_control_reg;
c18487ee 1973 int cnt;
a2fbb9ea 1974
c18487ee
YR		 1975 /* Validating that the resource is within range */
1976 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1977 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1978 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1979 return -EINVAL;
1980 }
a2fbb9ea 1981
4a37fb66
YG		 1982 if (func <= 5) {
1983 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1984 } else {
1985 hw_lock_control_reg =
1986 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1987 }
1988
c18487ee 1989 /* Validating that the resource is not already taken */
4a37fb66 1990 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1991 if (lock_status & resource_bit) {
51c1a580 1992 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 1993 lock_status, resource_bit);
1994 return -EEXIST;
1995 }
a2fbb9ea 1996
46230476
EG		 1997 /* Try for 5 second every 5ms */
1998 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1999 /* Try to acquire the lock */
4a37fb66
YG		 2000 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2001 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2002 if (lock_status & resource_bit)
2003 return 0;
a2fbb9ea 2004
639d65b8 2005 usleep_range(5000, 10000);
a2fbb9ea 2006 }
51c1a580 2007 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2008 return -EAGAIN;
2009}
a2fbb9ea 2010
c9ee9206
VZ		 2011int bnx2x_release_leader_lock(struct bnx2x *bp)
2012{
2013 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2014}
2015
9f6c9258 2016int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2017{
2018 u32 lock_status;
2019 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2020 int func = BP_FUNC(bp);
2021 u32 hw_lock_control_reg;
a2fbb9ea 2022
c18487ee
YR		 2023 /* Validating that the resource is within range */
2024 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2025 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2026 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2027 return -EINVAL;
2028 }
2029
4a37fb66
YG		 2030 if (func <= 5) {
2031 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2032 } else {
2033 hw_lock_control_reg =
2034 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2035 }
2036
c18487ee 2037 /* Validating that the resource is currently taken */
4a37fb66 2038 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2039 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2040 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2041 lock_status, resource_bit);
c18487ee 2042 return -EFAULT;
a2fbb9ea
ET		 2043 }
2044
9f6c9258
DK		 2045 REG_WR(bp, hw_lock_control_reg, resource_bit);
2046 return 0;
c18487ee 2047}
a2fbb9ea 2048
4acac6a5
EG		 2049int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2050{
2051 /* The GPIO should be swapped if swap register is set and active */
2052 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2053 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2054 int gpio_shift = gpio_num +
2055 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2056 u32 gpio_mask = (1 << gpio_shift);
2057 u32 gpio_reg;
2058 int value;
2059
2060 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2061 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2062 return -EINVAL;
2063 }
2064
2065 /* read GPIO value */
2066 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2067
2068 /* get the requested pin value */
2069 if ((gpio_reg & gpio_mask) == gpio_mask)
2070 value = 1;
2071 else
2072 value = 0;
2073
2074 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2075
2076 return value;
2077}
2078
17de50b7 2079int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2080{
2081 /* The GPIO should be swapped if swap register is set and active */
2082 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2083 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2084 int gpio_shift = gpio_num +
2085 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2086 u32 gpio_mask = (1 << gpio_shift);
2087 u32 gpio_reg;
a2fbb9ea 2088
c18487ee
YR		 2089 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2090 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2091 return -EINVAL;
2092 }
a2fbb9ea 2093
4a37fb66 2094 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2095 /* read GPIO and mask except the float bits */
2096 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2097
c18487ee
YR		 2098 switch (mode) {
2099 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2100 DP(NETIF_MSG_LINK,
2101 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2102 gpio_num, gpio_shift);
2103 /* clear FLOAT and set CLR */
2104 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2105 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2106 break;
a2fbb9ea 2107
c18487ee 2108 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2109 DP(NETIF_MSG_LINK,
2110 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2111 gpio_num, gpio_shift);
2112 /* clear FLOAT and set SET */
2113 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2114 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2115 break;
a2fbb9ea 2116
17de50b7 2117 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2118 DP(NETIF_MSG_LINK,
2119 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2120 gpio_num, gpio_shift);
2121 /* set FLOAT */
2122 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2123 break;
a2fbb9ea 2124
c18487ee
YR		 2125 default:
2126 break;
a2fbb9ea
ET		 2127 }
2128
c18487ee 2129 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2130 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2131
c18487ee 2132 return 0;
a2fbb9ea
ET		 2133}
2134
0d40f0d4
YR		 2135int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2136{
2137 u32 gpio_reg = 0;
2138 int rc = 0;
2139
2140 /* Any port swapping should be handled by caller. */
2141
2142 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2143 /* read GPIO and mask except the float bits */
2144 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2145 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2146 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2147 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2148
2149 switch (mode) {
2150 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2151 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2152 /* set CLR */
2153 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2154 break;
2155
2156 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2157 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2158 /* set SET */
2159 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2160 break;
2161
2162 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2163 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2164 /* set FLOAT */
2165 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2166 break;
2167
2168 default:
2169 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2170 rc = -EINVAL;
2171 break;
2172 }
2173
2174 if (rc == 0)
2175 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2176
2177 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2178
2179 return rc;
2180}
2181
4acac6a5
EG		 2182int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2183{
2184 /* The GPIO should be swapped if swap register is set and active */
2185 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2186 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2187 int gpio_shift = gpio_num +
2188 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2189 u32 gpio_mask = (1 << gpio_shift);
2190 u32 gpio_reg;
2191
2192 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2193 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2194 return -EINVAL;
2195 }
2196
2197 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2198 /* read GPIO int */
2199 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2200
2201 switch (mode) {
2202 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2203 DP(NETIF_MSG_LINK,
2204 "Clear GPIO INT %d (shift %d) -> output low\n",
2205 gpio_num, gpio_shift);
4acac6a5
EG		 2206 /* clear SET and set CLR */
2207 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2208 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2209 break;
2210
2211 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2212 DP(NETIF_MSG_LINK,
2213 "Set GPIO INT %d (shift %d) -> output high\n",
2214 gpio_num, gpio_shift);
4acac6a5
EG		 2215 /* clear CLR and set SET */
2216 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2217 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2218 break;
2219
2220 default:
2221 break;
2222 }
2223
2224 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2225 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2226
2227 return 0;
2228}
2229
d6d99a3f 2230static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2231{
c18487ee 2232 u32 spio_reg;
a2fbb9ea 2233
d6d99a3f
YM		 2234 /* Only 2 SPIOs are configurable */
2235 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2236 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2237 return -EINVAL;
a2fbb9ea
ET		 2238 }
2239
4a37fb66 2240 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2241 /* read SPIO and mask except the float bits */
d6d99a3f 2242 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2243
c18487ee 2244 switch (mode) {
d6d99a3f
YM		 2245 case MISC_SPIO_OUTPUT_LOW:
2246 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2247 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2248 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2249 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2250 break;
a2fbb9ea 2251
d6d99a3f
YM		 2252 case MISC_SPIO_OUTPUT_HIGH:
2253 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2254 /* clear FLOAT and set SET */
d6d99a3f
YM		 2255 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2256 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2257 break;
a2fbb9ea 2258
d6d99a3f
YM		 2259 case MISC_SPIO_INPUT_HI_Z:
2260 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2261 /* set FLOAT */
d6d99a3f 2262 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2263 break;
a2fbb9ea 2264
c18487ee
YR		 2265 default:
2266 break;
a2fbb9ea
ET		 2267 }
2268
c18487ee 2269 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2270 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2271
a2fbb9ea
ET		 2272 return 0;
2273}
2274
9f6c9258 2275void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2276{
a22f0788 2277 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2278 switch (bp->link_vars.ieee_fc &
2279 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2280 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2281 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2282 ADVERTISED_Pause);
c18487ee 2283 break;
356e2385 2284
c18487ee 2285 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2286 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2287 ADVERTISED_Pause);
c18487ee 2288 break;
356e2385 2289
c18487ee 2290 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2291 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2292 break;
356e2385 2293
c18487ee 2294 default:
a22f0788 2295 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2296 ADVERTISED_Pause);
c18487ee
YR		 2297 break;
2298 }
2299}
f1410647 2300
cd1dfce2 2301static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2302{
cd1dfce2
YM		 2303 /* Initialize link parameters structure variables
2304 * It is recommended to turn off RX FC for jumbo frames
2305 * for better performance
2306 */
2307 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2308 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2309 else
2310 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2311}
a2fbb9ea 2312
9156b30b
DK		 2313static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2314{
2315 u32 pause_enabled = 0;
2316
2317 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2318 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2319 pause_enabled = 1;
2320
2321 REG_WR(bp, BAR_USTRORM_INTMEM +
2322 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2323 pause_enabled);
2324 }
2325
2326 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2327 pause_enabled ? "enabled" : "disabled");
2328}
2329
cd1dfce2
YM		 2330int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2331{
2332 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2333 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2334
2335 if (!BP_NOMCP(bp)) {
2336 bnx2x_set_requested_fc(bp);
4a37fb66 2337 bnx2x_acquire_phy_lock(bp);
b5bf9068 2338
a22f0788 2339 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2340 struct link_params *lp = &bp->link_params;
2341 lp->loopback_mode = LOOPBACK_XGXS;
2342 /* do PHY loopback at 10G speed, if possible */
2343 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2344 if (lp->speed_cap_mask[cfx_idx] &
2345 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2346 lp->req_line_speed[cfx_idx] =
2347 SPEED_10000;
2348 else
2349 lp->req_line_speed[cfx_idx] =
2350 SPEED_1000;
2351 }
a22f0788 2352 }
b5bf9068 2353
8970b2e4
MS		 2354 if (load_mode == LOAD_LOOPBACK_EXT) {
2355 struct link_params *lp = &bp->link_params;
2356 lp->loopback_mode = LOOPBACK_EXT;
2357 }
2358
19680c48 2359 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2360
4a37fb66 2361 bnx2x_release_phy_lock(bp);
a2fbb9ea 2362
9156b30b
DK		 2363 bnx2x_init_dropless_fc(bp);
2364
3c96c68b
EG		 2365 bnx2x_calc_fc_adv(bp);
2366
cd1dfce2 2367 if (bp->link_vars.link_up) {
b5bf9068 2368 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2369 bnx2x_link_report(bp);
cd1dfce2
YM		 2370 }
2371 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2372 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2373 return rc;
2374 }
f5372251 2375 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2376 return -EINVAL;
a2fbb9ea
ET		 2377}
2378
9f6c9258 2379void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2380{
19680c48 2381 if (!BP_NOMCP(bp)) {
4a37fb66 2382 bnx2x_acquire_phy_lock(bp);
19680c48 2383 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2384 bnx2x_release_phy_lock(bp);
a2fbb9ea 2385
9156b30b
DK		 2386 bnx2x_init_dropless_fc(bp);
2387
19680c48
EG		 2388 bnx2x_calc_fc_adv(bp);
2389 } else
f5372251 2390 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2391}
a2fbb9ea 2392
c18487ee
YR		 2393static void bnx2x__link_reset(struct bnx2x *bp)
2394{
19680c48 2395 if (!BP_NOMCP(bp)) {
4a37fb66 2396 bnx2x_acquire_phy_lock(bp);
5d07d868 2397 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2398 bnx2x_release_phy_lock(bp);
19680c48 2399 } else
f5372251 2400 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2401}
a2fbb9ea 2402
5d07d868
YM		 2403void bnx2x_force_link_reset(struct bnx2x *bp)
2404{
2405 bnx2x_acquire_phy_lock(bp);
2406 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2407 bnx2x_release_phy_lock(bp);
2408}
2409
a22f0788 2410u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2411{
2145a920 2412 u8 rc = 0;
a2fbb9ea 2413
2145a920
VZ		 2414 if (!BP_NOMCP(bp)) {
2415 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2416 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2417 is_serdes);
2145a920
VZ		 2418 bnx2x_release_phy_lock(bp);
2419 } else
2420 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2421
c18487ee
YR		 2422 return rc;
2423}
a2fbb9ea 2424
2691d51d
EG		 2425/* Calculates the sum of vn_min_rates.
2426 It's needed for further normalizing of the min_rates.
2427 Returns:
2428 sum of vn_min_rates.
2429 or
2430 0 - if all the min_rates are 0.
16a5fd92 2431 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2432 If not all min_rates are zero then those that are zeroes will be set to 1.
2433 */
b475d78f
YM		 2434static void bnx2x_calc_vn_min(struct bnx2x *bp,
2435 struct cmng_init_input *input)
2691d51d
EG		 2436{
2437 int all_zero = 1;
2691d51d
EG		 2438 int vn;
2439
3395a033 2440 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2441 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2442 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2443 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2444
2445 /* Skip hidden vns */
2446 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2447 vn_min_rate = 0;
2691d51d 2448 /* If min rate is zero - set it to 1 */
b475d78f 2449 else if (!vn_min_rate)
2691d51d
EG		 2450 vn_min_rate = DEF_MIN_RATE;
2451 else
2452 all_zero = 0;
2453
b475d78f 2454 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2455 }
2456
30ae438b
DK		 2457 /* if ETS or all min rates are zeros - disable fairness */
2458 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2459 input->flags.cmng_enables &=
30ae438b
DK		 2460 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2461 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2462 } else if (all_zero) {
b475d78f 2463 input->flags.cmng_enables &=
b015e3d1 2464 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2465 DP(NETIF_MSG_IFUP,
2466 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2467 } else
b475d78f 2468 input->flags.cmng_enables |=
b015e3d1 2469 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2470}
2471
b475d78f
YM		 2472static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2473 struct cmng_init_input *input)
34f80b04 2474{
b475d78f 2475 u16 vn_max_rate;
f2e0899f 2476 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2477
b475d78f 2478 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2479 vn_max_rate = 0;
b475d78f 2480 else {
faa6fcbb
DK		 2481 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2482
b475d78f 2483 if (IS_MF_SI(bp)) {
faa6fcbb
DK		 2484 /* maxCfg in percents of linkspeed */
2485 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2486 } else /* SD modes */
faa6fcbb
DK		 2487 /* maxCfg is absolute in 100Mb units */
2488 vn_max_rate = maxCfg * 100;
34f80b04 2489 }
f85582f8 2490
b475d78f 2491 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2492
b475d78f 2493 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2494}
f85582f8 2495
523224a3
DK		 2496static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2497{
2498 if (CHIP_REV_IS_SLOW(bp))
2499 return CMNG_FNS_NONE;
fb3bff17 2500 if (IS_MF(bp))
523224a3
DK		 2501 return CMNG_FNS_MINMAX;
2502
2503 return CMNG_FNS_NONE;
2504}
2505
2ae17f66 2506void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2507{
0793f83f 2508 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2509
2510 if (BP_NOMCP(bp))
16a5fd92 2511 return; /* what should be the default value in this case */
523224a3 2512
0793f83f
DK		 2513 /* For 2 port configuration the absolute function number formula
2514 * is:
2515 * abs_func = 2 * vn + BP_PORT + BP_PATH
2516 *
2517 * and there are 4 functions per port
2518 *
2519 * For 4 port configuration it is
2520 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2521 *
2522 * and there are 2 functions per port
2523 */
3395a033 2524 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2525 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2526
2527 if (func >= E1H_FUNC_MAX)
2528 break;
2529
f2e0899f 2530 bp->mf_config[vn] =
523224a3
DK		 2531 MF_CFG_RD(bp, func_mf_config[func].config);
2532 }
a3348722
BW		 2533 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2534 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2535 bp->flags |= MF_FUNC_DIS;
2536 } else {
2537 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2538 bp->flags &= ~MF_FUNC_DIS;
2539 }
523224a3
DK		 2540}
2541
2542static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2543{
b475d78f
YM		 2544 struct cmng_init_input input;
2545 memset(&input, 0, sizeof(struct cmng_init_input));
2546
2547 input.port_rate = bp->link_vars.line_speed;
523224a3 2548
568e2426 2549 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2550 int vn;
2551
523224a3
DK		 2552 /* read mf conf from shmem */
2553 if (read_cfg)
2554 bnx2x_read_mf_cfg(bp);
2555
523224a3 2556 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2557 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2558
2559 /* calculate and set min-max rate for each vn */
c4154f25 2560 if (bp->port.pmf)
3395a033 2561 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2562 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2563
2564 /* always enable rate shaping and fairness */
b475d78f 2565 input.flags.cmng_enables |=
523224a3 2566 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2567
2568 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2569 return;
2570 }
2571
2572 /* rate shaping and fairness are disabled */
2573 DP(NETIF_MSG_IFUP,
2574 "rate shaping and fairness are disabled\n");
2575}
34f80b04 2576
1191cb83
ED		 2577static void storm_memset_cmng(struct bnx2x *bp,
2578 struct cmng_init *cmng,
2579 u8 port)
2580{
2581 int vn;
2582 size_t size = sizeof(struct cmng_struct_per_port);
2583
2584 u32 addr = BAR_XSTRORM_INTMEM +
2585 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2586
2587 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2588
2589 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2590 int func = func_by_vn(bp, vn);
2591
2592 addr = BAR_XSTRORM_INTMEM +
2593 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2594 size = sizeof(struct rate_shaping_vars_per_vn);
2595 __storm_memset_struct(bp, addr, size,
2596 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2597
2598 addr = BAR_XSTRORM_INTMEM +
2599 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2600 size = sizeof(struct fairness_vars_per_vn);
2601 __storm_memset_struct(bp, addr, size,
2602 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2603 }
2604}
2605
568e2426
DK		 2606/* init cmng mode in HW according to local configuration */
2607void bnx2x_set_local_cmng(struct bnx2x *bp)
2608{
2609 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2610
2611 if (cmng_fns != CMNG_FNS_NONE) {
2612 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2613 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2614 } else {
2615 /* rate shaping and fairness are disabled */
2616 DP(NETIF_MSG_IFUP,
2617 "single function mode without fairness\n");
2618 }
2619}
2620
c18487ee
YR		 2621/* This function is called upon link interrupt */
2622static void bnx2x_link_attn(struct bnx2x *bp)
2623{
bb2a0f7a
YG		 2624 /* Make sure that we are synced with the current statistics */
2625 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2626
c18487ee 2627 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2628
9156b30b 2629 bnx2x_init_dropless_fc(bp);
1c06328c 2630
9156b30b 2631 if (bp->link_vars.link_up) {
1c06328c 2632
619c5cb6 2633 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2634 struct host_port_stats *pstats;
2635
2636 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2637 /* reset old mac stats */
bb2a0f7a
YG		 2638 memset(&(pstats->mac_stx[0]), 0,
2639 sizeof(struct mac_stx));
2640 }
f34d28ea 2641 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2642 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2643 }
2644
568e2426
DK		 2645 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2646 bnx2x_set_local_cmng(bp);
9fdc3e95 2647
2ae17f66
VZ		 2648 __bnx2x_link_report(bp);
2649
9fdc3e95
DK		 2650 if (IS_MF(bp))
2651 bnx2x_link_sync_notify(bp);
c18487ee 2652}
a2fbb9ea 2653
9f6c9258 2654void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2655{
2ae17f66 2656 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2657 return;
a2fbb9ea 2658
00253a8c 2659 /* read updated dcb configuration */
ad5afc89
AE		 2660 if (IS_PF(bp)) {
2661 bnx2x_dcbx_pmf_update(bp);
2662 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2663 if (bp->link_vars.link_up)
2664 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2665 else
2666 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2667 /* indicate link status */
2668 bnx2x_link_report(bp);
a2fbb9ea 2669
ad5afc89
AE		 2670 } else { /* VF */
2671 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2672 SUPPORTED_10baseT_Full |
2673 SUPPORTED_100baseT_Half |
2674 SUPPORTED_100baseT_Full |
2675 SUPPORTED_1000baseT_Full |
2676 SUPPORTED_2500baseX_Full |
2677 SUPPORTED_10000baseT_Full |
2678 SUPPORTED_TP |
2679 SUPPORTED_FIBRE |
2680 SUPPORTED_Autoneg |
2681 SUPPORTED_Pause |
2682 SUPPORTED_Asym_Pause);
2683 bp->port.advertising[0] = bp->port.supported[0];
2684
2685 bp->link_params.bp = bp;
2686 bp->link_params.port = BP_PORT(bp);
2687 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2688 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2689 bp->link_params.req_line_speed[0] = SPEED_10000;
2690 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2691 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2692 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2693 bp->link_vars.line_speed = SPEED_10000;
2694 bp->link_vars.link_status =
2695 (LINK_STATUS_LINK_UP |
2696 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2697 bp->link_vars.link_up = 1;
2698 bp->link_vars.duplex = DUPLEX_FULL;
2699 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2700 __bnx2x_link_report(bp);
bb2a0f7a 2701 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2702 }
a2fbb9ea 2703}
a2fbb9ea 2704
a3348722
BW		 2705static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2706 u16 vlan_val, u8 allowed_prio)
2707{
86564c3f 2708 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2709 struct bnx2x_func_afex_update_params *f_update_params =
2710 &func_params.params.afex_update;
2711
2712 func_params.f_obj = &bp->func_obj;
2713 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2714
2715 /* no need to wait for RAMROD completion, so don't
2716 * set RAMROD_COMP_WAIT flag
2717 */
2718
2719 f_update_params->vif_id = vifid;
2720 f_update_params->afex_default_vlan = vlan_val;
2721 f_update_params->allowed_priorities = allowed_prio;
2722
2723 /* if ramrod can not be sent, response to MCP immediately */
2724 if (bnx2x_func_state_change(bp, &func_params) < 0)
2725 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2726
2727 return 0;
2728}
2729
2730static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2731 u16 vif_index, u8 func_bit_map)
2732{
86564c3f 2733 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2734 struct bnx2x_func_afex_viflists_params *update_params =
2735 &func_params.params.afex_viflists;
2736 int rc;
2737 u32 drv_msg_code;
2738
2739 /* validate only LIST_SET and LIST_GET are received from switch */
2740 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2741 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2742 cmd_type);
2743
2744 func_params.f_obj = &bp->func_obj;
2745 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2746
2747 /* set parameters according to cmd_type */
2748 update_params->afex_vif_list_command = cmd_type;
86564c3f 2749 update_params->vif_list_index = vif_index;
a3348722
BW		 2750 update_params->func_bit_map =
2751 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2752 update_params->func_to_clear = 0;
2753 drv_msg_code =
2754 (cmd_type == VIF_LIST_RULE_GET) ?
2755 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2756 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2757
2758 /* if ramrod can not be sent, respond to MCP immediately for
2759 * SET and GET requests (other are not triggered from MCP)
2760 */
2761 rc = bnx2x_func_state_change(bp, &func_params);
2762 if (rc < 0)
2763 bnx2x_fw_command(bp, drv_msg_code, 0);
2764
2765 return 0;
2766}
2767
2768static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2769{
2770 struct afex_stats afex_stats;
2771 u32 func = BP_ABS_FUNC(bp);
2772 u32 mf_config;
2773 u16 vlan_val;
2774 u32 vlan_prio;
2775 u16 vif_id;
2776 u8 allowed_prio;
2777 u8 vlan_mode;
2778 u32 addr_to_write, vifid, addrs, stats_type, i;
2779
2780 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2781 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2782 DP(BNX2X_MSG_MCP,
2783 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2784 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2785 }
2786
2787 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2788 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2789 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2790 DP(BNX2X_MSG_MCP,
2791 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2792 vifid, addrs);
2793 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2794 addrs);
2795 }
2796
2797 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2798 addr_to_write = SHMEM2_RD(bp,
2799 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2800 stats_type = SHMEM2_RD(bp,
2801 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2802
2803 DP(BNX2X_MSG_MCP,
2804 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2805 addr_to_write);
2806
2807 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2808
2809 /* write response to scratchpad, for MCP */
2810 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2811 REG_WR(bp, addr_to_write + i*sizeof(u32),
2812 *(((u32 *)(&afex_stats))+i));
2813
2814 /* send ack message to MCP */
2815 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2816 }
2817
2818 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2819 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2820 bp->mf_config[BP_VN(bp)] = mf_config;
2821 DP(BNX2X_MSG_MCP,
2822 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2823 mf_config);
2824
2825 /* if VIF_SET is "enabled" */
2826 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2827 /* set rate limit directly to internal RAM */
2828 struct cmng_init_input cmng_input;
2829 struct rate_shaping_vars_per_vn m_rs_vn;
2830 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2831 u32 addr = BAR_XSTRORM_INTMEM +
2832 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2833
2834 bp->mf_config[BP_VN(bp)] = mf_config;
2835
2836 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2837 m_rs_vn.vn_counter.rate =
2838 cmng_input.vnic_max_rate[BP_VN(bp)];
2839 m_rs_vn.vn_counter.quota =
2840 (m_rs_vn.vn_counter.rate *
2841 RS_PERIODIC_TIMEOUT_USEC) / 8;
2842
2843 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2844
2845 /* read relevant values from mf_cfg struct in shmem */
2846 vif_id =
2847 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2848 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2849 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2850 vlan_val =
2851 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2852 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2853 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2854 vlan_prio = (mf_config &
2855 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2856 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2857 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2858 vlan_mode =
2859 (MF_CFG_RD(bp,
2860 func_mf_config[func].afex_config) &
2861 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2862 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2863 allowed_prio =
2864 (MF_CFG_RD(bp,
2865 func_mf_config[func].afex_config) &
2866 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2867 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2868
2869 /* send ramrod to FW, return in case of failure */
2870 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2871 allowed_prio))
2872 return;
2873
2874 bp->afex_def_vlan_tag = vlan_val;
2875 bp->afex_vlan_mode = vlan_mode;
2876 } else {
2877 /* notify link down because BP->flags is disabled */
2878 bnx2x_link_report(bp);
2879
2880 /* send INVALID VIF ramrod to FW */
2881 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2882
2883 /* Reset the default afex VLAN */
2884 bp->afex_def_vlan_tag = -1;
2885 }
2886 }
2887}
2888
34f80b04
EG		 2889static void bnx2x_pmf_update(struct bnx2x *bp)
2890{
2891 int port = BP_PORT(bp);
2892 u32 val;
2893
2894 bp->port.pmf = 1;
51c1a580 2895 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2896
3deb8167
YR		 2897 /*
2898 * We need the mb() to ensure the ordering between the writing to
2899 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2900 */
2901 smp_mb();
2902
2903 /* queue a periodic task */
2904 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2905
ef01854e
DK		 2906 bnx2x_dcbx_pmf_update(bp);
2907
34f80b04 2908 /* enable nig attention */
3395a033 2909 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2910 if (bp->common.int_block == INT_BLOCK_HC) {
2911 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2912 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2913 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2914 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2915 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2916 }
bb2a0f7a
YG		 2917
2918 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2919}
2920
c18487ee 2921/* end of Link */
a2fbb9ea
ET		 2922
2923/* slow path */
2924
2925/*
2926 * General service functions
2927 */
2928
2691d51d 2929/* send the MCP a request, block until there is a reply */
a22f0788 2930u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2931{
f2e0899f 2932 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2933 u32 seq;
2691d51d
EG		 2934 u32 rc = 0;
2935 u32 cnt = 1;
2936 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2937
c4ff7cbf 2938 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2939 seq = ++bp->fw_seq;
f2e0899f
DK		 2940 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2941 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2942
754a2f52
DK		 2943 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2944 (command | seq), param);
2691d51d
EG		 2945
2946 do {
2947 /* let the FW do it's magic ... */
2948 msleep(delay);
2949
f2e0899f 2950 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2951
c4ff7cbf
EG		 2952 /* Give the FW up to 5 second (500*10ms) */
2953 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2954
2955 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2956 cnt*delay, rc, seq);
2957
2958 /* is this a reply to our command? */
2959 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2960 rc &= FW_MSG_CODE_MASK;
2961 else {
2962 /* FW BUG! */
2963 BNX2X_ERR("FW failed to respond!\n");
2964 bnx2x_fw_dump(bp);
2965 rc = 0;
2966 }
c4ff7cbf 2967 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2968
2969 return rc;
2970}
2971
1191cb83
ED		 2972static void storm_memset_func_cfg(struct bnx2x *bp,
2973 struct tstorm_eth_function_common_config *tcfg,
2974 u16 abs_fid)
2975{
2976 size_t size = sizeof(struct tstorm_eth_function_common_config);
2977
2978 u32 addr = BAR_TSTRORM_INTMEM +
2979 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2980
2981 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2982}
2983
619c5cb6
VZ		 2984void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2985{
2986 if (CHIP_IS_E1x(bp)) {
2987 struct tstorm_eth_function_common_config tcfg = {0};
2988
2989 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2990 }
2991
2992 /* Enable the function in the FW */
2993 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2994 storm_memset_func_en(bp, p->func_id, 1);
2995
2996 /* spq */
2997 if (p->func_flgs & FUNC_FLG_SPQ) {
2998 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2999 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3000 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3001 }
3002}
3003
6383c0b3 3004/**
16a5fd92 3005 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3006 *
3007 * @bp device handle
3008 * @fp queue handle
3009 * @zero_stats TRUE if statistics zeroing is needed
3010 *
3011 * Return the flags that are common for the Tx-only and not normal connections.
3012 */
1191cb83
ED		 3013static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3014 struct bnx2x_fastpath *fp,
3015 bool zero_stats)
28912902 3016{
619c5cb6
VZ		 3017 unsigned long flags = 0;
3018
3019 /* PF driver will always initialize the Queue to an ACTIVE state */
3020 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3021
6383c0b3 3022 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3023 * parent connection). The statistics are zeroed when the parent
3024 * connection is initialized.
6383c0b3 3025 */
50f0a562
BW		 3026
3027 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3028 if (zero_stats)
3029 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3030
c14db202
YM		 3031 if (bp->flags & TX_SWITCHING)
3032 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3033
91226790 3034 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3035 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3036
823e1d90
YM		 3037#ifdef BNX2X_STOP_ON_ERROR
3038 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3039#endif
3040
6383c0b3
AE		 3041 return flags;
3042}
3043
1191cb83
ED		 3044static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3045 struct bnx2x_fastpath *fp,
3046 bool leading)
6383c0b3
AE		 3047{
3048 unsigned long flags = 0;
3049
619c5cb6
VZ		 3050 /* calculate other queue flags */
3051 if (IS_MF_SD(bp))
3052 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3053
a3348722 3054 if (IS_FCOE_FP(fp)) {
619c5cb6 3055 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3056 /* For FCoE - force usage of default priority (for afex) */
3057 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3058 }
523224a3 3059
f5219d8e 3060 if (!fp->disable_tpa) {
619c5cb6 3061 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3062 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3063 if (fp->mode == TPA_MODE_GRO)
3064 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3065 }
619c5cb6 3066
619c5cb6
VZ		 3067 if (leading) {
3068 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3069 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3070 }
523224a3 3071
619c5cb6
VZ		 3072 /* Always set HW VLAN stripping */
3073 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3074
a3348722
BW		 3075 /* configure silent vlan removal */
3076 if (IS_MF_AFEX(bp))
3077 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3078
6383c0b3 3079 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3080}
3081
619c5cb6 3082static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3083 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3084 u8 cos)
619c5cb6
VZ		 3085{
3086 gen_init->stat_id = bnx2x_stats_id(fp);
3087 gen_init->spcl_id = fp->cl_id;
3088
3089 /* Always use mini-jumbo MTU for FCoE L2 ring */
3090 if (IS_FCOE_FP(fp))
3091 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3092 else
3093 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3094
3095 gen_init->cos = cos;
619c5cb6
VZ		 3096}
3097
3098static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3099 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3100 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3101{
619c5cb6 3102 u8 max_sge = 0;
523224a3
DK		 3103 u16 sge_sz = 0;
3104 u16 tpa_agg_size = 0;
3105
523224a3 3106 if (!fp->disable_tpa) {
dfacf138
DK		 3107 pause->sge_th_lo = SGE_TH_LO(bp);
3108 pause->sge_th_hi = SGE_TH_HI(bp);
3109
3110 /* validate SGE ring has enough to cross high threshold */
3111 WARN_ON(bp->dropless_fc &&
3112 pause->sge_th_hi + FW_PREFETCH_CNT >
3113 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3114
924d75ab 3115 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3116 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3117 SGE_PAGE_SHIFT;
3118 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3119 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3120 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3121 }
3122
3123 /* pause - not for e1 */
3124 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3125 pause->bd_th_lo = BD_TH_LO(bp);
3126 pause->bd_th_hi = BD_TH_HI(bp);
3127
3128 pause->rcq_th_lo = RCQ_TH_LO(bp);
3129 pause->rcq_th_hi = RCQ_TH_HI(bp);
3130 /*
3131 * validate that rings have enough entries to cross
3132 * high thresholds
3133 */
3134 WARN_ON(bp->dropless_fc &&
3135 pause->bd_th_hi + FW_PREFETCH_CNT >
3136 bp->rx_ring_size);
3137 WARN_ON(bp->dropless_fc &&
3138 pause->rcq_th_hi + FW_PREFETCH_CNT >
3139 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3140
523224a3
DK		 3141 pause->pri_map = 1;
3142 }
3143
3144 /* rxq setup */
523224a3
DK		 3145 rxq_init->dscr_map = fp->rx_desc_mapping;
3146 rxq_init->sge_map = fp->rx_sge_mapping;
3147 rxq_init->rcq_map = fp->rx_comp_mapping;
3148 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3149
619c5cb6
VZ		 3150 /* This should be a maximum number of data bytes that may be
3151 * placed on the BD (not including paddings).
3152 */
e52fcb24 3153 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3154 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3155
523224a3 3156 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3157 rxq_init->tpa_agg_sz = tpa_agg_size;
3158 rxq_init->sge_buf_sz = sge_sz;
3159 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3160 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3161 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3162
3163 /* Maximum number or simultaneous TPA aggregation for this Queue.
3164 *
2de67439 3165 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3166 * VF driver(s) may want to define it to a smaller value.
3167 */
dfacf138 3168 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3169
523224a3
DK		 3170 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3171 rxq_init->fw_sb_id = fp->fw_sb_id;
3172
ec6ba945
VZ		 3173 if (IS_FCOE_FP(fp))
3174 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3175 else
6383c0b3 3176 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3177 /* configure silent vlan removal
3178 * if multi function mode is afex, then mask default vlan
3179 */
3180 if (IS_MF_AFEX(bp)) {
3181 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3182 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3183 }
523224a3
DK		 3184}
3185
619c5cb6 3186static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3187 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3188 u8 cos)
523224a3 3189{
65565884 3190 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3191 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3192 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3193 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3194
619c5cb6 3195 /*
16a5fd92 3196 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3197 * leading RSS client id
3198 */
3199 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3200
ec6ba945
VZ		 3201 if (IS_FCOE_FP(fp)) {
3202 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3203 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3204 }
523224a3
DK		 3205}
3206
8d96286a 3207static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3208{
3209 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 3210 struct event_ring_data eq_data = { {0} };
3211 u16 flags;
3212
619c5cb6 3213 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3214 /* reset IGU PF statistics: MSIX + ATTN */
3215 /* PF */
3216 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3217 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3218 (CHIP_MODE_IS_4_PORT(bp) ?
3219 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3220 /* ATTN */
3221 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3222 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3223 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3224 (CHIP_MODE_IS_4_PORT(bp) ?
3225 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3226 }
3227
523224a3
DK		 3228 /* function setup flags */
3229 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3230
619c5cb6
VZ		 3231 /* This flag is relevant for E1x only.
3232 * E2 doesn't have a TPA configuration in a function level.
523224a3 3233 */
619c5cb6 3234 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 3235
3236 func_init.func_flgs = flags;
3237 func_init.pf_id = BP_FUNC(bp);
3238 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3239 func_init.spq_map = bp->spq_mapping;
3240 func_init.spq_prod = bp->spq_prod_idx;
3241
3242 bnx2x_func_init(bp, &func_init);
3243
3244 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3245
3246 /*
619c5cb6
VZ		 3247 * Congestion management values depend on the link rate
3248 * There is no active link so initial link rate is set to 10 Gbps.
3249 * When the link comes up The congestion management values are
3250 * re-calculated according to the actual link rate.
3251 */
523224a3
DK		 3252 bp->link_vars.line_speed = SPEED_10000;
3253 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3254
3255 /* Only the PMF sets the HW */
3256 if (bp->port.pmf)
3257 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3258
86564c3f 3259 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3260 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3261 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3262 eq_data.producer = bp->eq_prod;
3263 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3264 eq_data.sb_id = DEF_SB_ID;
3265 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3266}
3267
523224a3
DK		 3268static void bnx2x_e1h_disable(struct bnx2x *bp)
3269{
3270 int port = BP_PORT(bp);
3271
619c5cb6 3272 bnx2x_tx_disable(bp);
523224a3
DK		 3273
3274 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3275}
3276
3277static void bnx2x_e1h_enable(struct bnx2x *bp)
3278{
3279 int port = BP_PORT(bp);
3280
3281 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3282
16a5fd92 3283 /* Tx queue should be only re-enabled */
523224a3
DK		 3284 netif_tx_wake_all_queues(bp->dev);
3285
3286 /*
3287 * Should not call netif_carrier_on since it will be called if the link
3288 * is up when checking for link state
3289 */
3290}
3291
1d187b34
BW		 3292#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3293
3294static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3295{
3296 struct eth_stats_info *ether_stat =
3297 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3298 struct bnx2x_vlan_mac_obj *mac_obj =
3299 &bp->sp_objs->mac_obj;
3300 int i;
1d187b34 3301
786fdf0b
DC		 3302 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3303 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3304
3ec9f9ca
AE		 3305 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3306 * mac_local field in ether_stat struct. The base address is offset by 2
3307 * bytes to account for the field being 8 bytes but a mac address is
3308 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3309 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3310 * allocated by the ether_stat struct, so the macs will land in their
3311 * proper positions.
3312 */
3313 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3314 memset(ether_stat->mac_local + i, 0,
3315 sizeof(ether_stat->mac_local[0]));
3316 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3317 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3318 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3319 ETH_ALEN);
1d187b34 3320 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3321 if (bp->dev->features & NETIF_F_RXCSUM)
3322 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3323 if (bp->dev->features & NETIF_F_TSO)
3324 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3325 ether_stat->feature_flags |= bp->common.boot_mode;
3326
3327 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3328
3329 ether_stat->txq_size = bp->tx_ring_size;
3330 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3331
fcf93a0a 3332#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3333 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3334#endif
1d187b34
BW		 3335}
3336
3337static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3338{
3339 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3340 struct fcoe_stats_info *fcoe_stat =
3341 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3342
55c11941
MS		 3343 if (!CNIC_LOADED(bp))
3344 return;
3345
3ec9f9ca 3346 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3347
3348 fcoe_stat->qos_priority =
3349 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3350
3351 /* insert FCoE stats from ramrod response */
3352 if (!NO_FCOE(bp)) {
3353 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3354 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3355 tstorm_queue_statistics;
3356
3357 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3358 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3359 xstorm_queue_statistics;
3360
3361 struct fcoe_statistics_params *fw_fcoe_stat =
3362 &bp->fw_stats_data->fcoe;
3363
86564c3f
YM		 3364 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3365 fcoe_stat->rx_bytes_lo,
3366 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3367
86564c3f
YM		 3368 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3369 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3370 fcoe_stat->rx_bytes_lo,
3371 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3372
86564c3f
YM		 3373 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3374 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3375 fcoe_stat->rx_bytes_lo,
3376 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3377
86564c3f
YM		 3378 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3379 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3380 fcoe_stat->rx_bytes_lo,
3381 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3382
86564c3f
YM		 3383 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3384 fcoe_stat->rx_frames_lo,
3385 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3386
86564c3f
YM		 3387 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3388 fcoe_stat->rx_frames_lo,
3389 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3390
86564c3f
YM		 3391 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3392 fcoe_stat->rx_frames_lo,
3393 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3394
86564c3f
YM		 3395 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3396 fcoe_stat->rx_frames_lo,
3397 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3398
86564c3f
YM		 3399 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3400 fcoe_stat->tx_bytes_lo,
3401 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3402
86564c3f
YM		 3403 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3404 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3405 fcoe_stat->tx_bytes_lo,
3406 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3407
86564c3f
YM		 3408 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3409 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3410 fcoe_stat->tx_bytes_lo,
3411 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3412
86564c3f
YM		 3413 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3414 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3415 fcoe_stat->tx_bytes_lo,
3416 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3417
86564c3f
YM		 3418 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3419 fcoe_stat->tx_frames_lo,
3420 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3421
86564c3f
YM		 3422 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3423 fcoe_stat->tx_frames_lo,
3424 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3425
86564c3f
YM		 3426 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3427 fcoe_stat->tx_frames_lo,
3428 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3429
86564c3f
YM		 3430 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3431 fcoe_stat->tx_frames_lo,
3432 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3433 }
3434
1d187b34
BW		 3435 /* ask L5 driver to add data to the struct */
3436 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3437}
3438
3439static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3440{
3441 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3442 struct iscsi_stats_info *iscsi_stat =
3443 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3444
55c11941
MS		 3445 if (!CNIC_LOADED(bp))
3446 return;
3447
3ec9f9ca
AE		 3448 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3449 ETH_ALEN);
1d187b34
BW		 3450
3451 iscsi_stat->qos_priority =
3452 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3453
1d187b34
BW		 3454 /* ask L5 driver to add data to the struct */
3455 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3456}
3457
0793f83f
DK		 3458/* called due to MCP event (on pmf):
3459 * reread new bandwidth configuration
3460 * configure FW
3461 * notify others function about the change
3462 */
1191cb83 3463static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3464{
3465 if (bp->link_vars.link_up) {
3466 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3467 bnx2x_link_sync_notify(bp);
3468 }
3469 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3470}
3471
1191cb83 3472static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3473{
3474 bnx2x_config_mf_bw(bp);
3475 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3476}
3477
c8c60d88
YM		 3478static void bnx2x_handle_eee_event(struct bnx2x *bp)
3479{
3480 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3481 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3482}
3483
42f8277f
YM		 3484#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3485#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3486
1d187b34
BW		 3487static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3488{
3489 enum drv_info_opcode op_code;
3490 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
42f8277f
YM		 3491 bool release = false;
3492 int wait;
1d187b34
BW		 3493
3494 /* if drv_info version supported by MFW doesn't match - send NACK */
3495 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3496 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3497 return;
3498 }
3499
3500 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3501 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3502
42f8277f
YM		 3503 /* Must prevent other flows from accessing drv_info_to_mcp */
3504 mutex_lock(&bp->drv_info_mutex);
3505
1d187b34
BW		 3506 memset(&bp->slowpath->drv_info_to_mcp, 0,
3507 sizeof(union drv_info_to_mcp));
3508
3509 switch (op_code) {
3510 case ETH_STATS_OPCODE:
3511 bnx2x_drv_info_ether_stat(bp);
3512 break;
3513 case FCOE_STATS_OPCODE:
3514 bnx2x_drv_info_fcoe_stat(bp);
3515 break;
3516 case ISCSI_STATS_OPCODE:
3517 bnx2x_drv_info_iscsi_stat(bp);
3518 break;
3519 default:
3520 /* if op code isn't supported - send NACK */
3521 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
42f8277f 3522 goto out;
1d187b34
BW		 3523 }
3524
3525 /* if we got drv_info attn from MFW then these fields are defined in
3526 * shmem2 for sure
3527 */
3528 SHMEM2_WR(bp, drv_info_host_addr_lo,
3529 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3530 SHMEM2_WR(bp, drv_info_host_addr_hi,
3531 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3532
3533 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
42f8277f
YM		 3534
3535 /* Since possible management wants both this and get_driver_version
3536 * need to wait until management notifies us it finished utilizing
3537 * the buffer.
3538 */
3539 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3540 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3541 } else if (!bp->drv_info_mng_owner) {
3542 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3543
3544 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3545 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3546
3547 /* Management is done; need to clear indication */
3548 if (indication & bit) {
3549 SHMEM2_WR(bp, mfw_drv_indication,
3550 indication & ~bit);
3551 release = true;
3552 break;
3553 }
3554
3555 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3556 }
3557 }
3558 if (!release) {
3559 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3560 bp->drv_info_mng_owner = true;
3561 }
3562
3563out:
3564 mutex_unlock(&bp->drv_info_mutex);
3565}
3566
3567static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3568{
3569 u8 vals[4];
3570 int i = 0;
3571
3572 if (bnx2x_format) {
3573 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3574 &vals[0], &vals[1], &vals[2], &vals[3]);
3575 if (i > 0)
3576 vals[0] -= '0';
3577 } else {
3578 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3579 &vals[0], &vals[1], &vals[2], &vals[3]);
3580 }
3581
3582 while (i < 4)
3583 vals[i++] = 0;
3584
3585 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3586}
3587
3588void bnx2x_update_mng_version(struct bnx2x *bp)
3589{
3590 u32 iscsiver = DRV_VER_NOT_LOADED;
3591 u32 fcoever = DRV_VER_NOT_LOADED;
3592 u32 ethver = DRV_VER_NOT_LOADED;
3593 int idx = BP_FW_MB_IDX(bp);
3594 u8 *version;
3595
3596 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3597 return;
3598
3599 mutex_lock(&bp->drv_info_mutex);
3600 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3601 if (bp->drv_info_mng_owner)
3602 goto out;
3603
3604 if (bp->state != BNX2X_STATE_OPEN)
3605 goto out;
3606
3607 /* Parse ethernet driver version */
3608 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3609 if (!CNIC_LOADED(bp))
3610 goto out;
3611
3612 /* Try getting storage driver version via cnic */
3613 memset(&bp->slowpath->drv_info_to_mcp, 0,
3614 sizeof(union drv_info_to_mcp));
3615 bnx2x_drv_info_iscsi_stat(bp);
3616 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3617 iscsiver = bnx2x_update_mng_version_utility(version, false);
3618
3619 memset(&bp->slowpath->drv_info_to_mcp, 0,
3620 sizeof(union drv_info_to_mcp));
3621 bnx2x_drv_info_fcoe_stat(bp);
3622 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3623 fcoever = bnx2x_update_mng_version_utility(version, false);
3624
3625out:
3626 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3627 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3628 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3629
3630 mutex_unlock(&bp->drv_info_mutex);
3631
3632 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3633 ethver, iscsiver, fcoever);
1d187b34
BW		 3634}
3635
523224a3
DK		 3636static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3637{
3638 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3639
3640 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3641
3642 /*
3643 * This is the only place besides the function initialization
3644 * where the bp->flags can change so it is done without any
3645 * locks
3646 */
f2e0899f 3647 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3648 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3649 bp->flags |= MF_FUNC_DIS;
3650
3651 bnx2x_e1h_disable(bp);
3652 } else {
51c1a580 3653 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3654 bp->flags &= ~MF_FUNC_DIS;
3655
3656 bnx2x_e1h_enable(bp);
3657 }
3658 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3659 }
3660 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3661 bnx2x_config_mf_bw(bp);
523224a3
DK		 3662 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3663 }
3664
3665 /* Report results to MCP */
3666 if (dcc_event)
3667 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3668 else
3669 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3670}
3671
3672/* must be called under the spq lock */
1191cb83 3673static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3674{
3675 struct eth_spe *next_spe = bp->spq_prod_bd;
3676
3677 if (bp->spq_prod_bd == bp->spq_last_bd) {
3678 bp->spq_prod_bd = bp->spq;
3679 bp->spq_prod_idx = 0;
51c1a580 3680 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3681 } else {
3682 bp->spq_prod_bd++;
3683 bp->spq_prod_idx++;
3684 }
3685 return next_spe;
3686}
3687
3688/* must be called under the spq lock */
1191cb83 3689static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3690{
3691 int func = BP_FUNC(bp);
3692
53e51e2f
VZ		 3693 /*
3694 * Make sure that BD data is updated before writing the producer:
3695 * BD data is written to the memory, the producer is read from the
3696 * memory, thus we need a full memory barrier to ensure the ordering.
3697 */
3698 mb();
28912902 3699
523224a3 3700 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3701 bp->spq_prod_idx);
28912902
MC		 3702 mmiowb();
3703}
3704
619c5cb6
VZ		 3705/**
3706 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3707 *
3708 * @cmd: command to check
3709 * @cmd_type: command type
3710 */
1191cb83 3711static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3712{
3713 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3714 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3715 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3716 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3717 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3718 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3719 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3720 return true;
3721 else
3722 return false;
619c5cb6
VZ		 3723}
3724
619c5cb6
VZ		 3725/**
3726 * bnx2x_sp_post - place a single command on an SP ring
3727 *
3728 * @bp: driver handle
3729 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3730 * @cid: SW CID the command is related to
3731 * @data_hi: command private data address (high 32 bits)
3732 * @data_lo: command private data address (low 32 bits)
3733 * @cmd_type: command type (e.g. NONE, ETH)
3734 *
3735 * SP data is handled as if it's always an address pair, thus data fields are
3736 * not swapped to little endian in upper functions. Instead this function swaps
3737 * data as if it's two u32 fields.
3738 */
9f6c9258 3739int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3740 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3741{
28912902 3742 struct eth_spe *spe;
523224a3 3743 u16 type;
619c5cb6 3744 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3745
a2fbb9ea 3746#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3747 if (unlikely(bp->panic)) {
3748 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3749 return -EIO;
51c1a580 3750 }
a2fbb9ea
ET		 3751#endif
3752
34f80b04 3753 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3754
6e30dd4e
VZ		 3755 if (common) {
3756 if (!atomic_read(&bp->eq_spq_left)) {
3757 BNX2X_ERR("BUG! EQ ring full!\n");
3758 spin_unlock_bh(&bp->spq_lock);
3759 bnx2x_panic();
3760 return -EBUSY;
3761 }
3762 } else if (!atomic_read(&bp->cq_spq_left)) {
3763 BNX2X_ERR("BUG! SPQ ring full!\n");
3764 spin_unlock_bh(&bp->spq_lock);
3765 bnx2x_panic();
3766 return -EBUSY;
a2fbb9ea 3767 }
f1410647 3768
28912902
MC		 3769 spe = bnx2x_sp_get_next(bp);
3770
a2fbb9ea 3771 /* CID needs port number to be encoded int it */
28912902 3772 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3773 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3774 HW_CID(bp, cid));
523224a3 3775
14a94ebd
MK		 3776 /* In some cases, type may already contain the func-id
3777 * mainly in SRIOV related use cases, so we add it here only
3778 * if it's not already set.
3779 */
3780 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3781 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3782 SPE_HDR_CONN_TYPE;
3783 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3784 SPE_HDR_FUNCTION_ID);
3785 } else {
3786 type = cmd_type;
3787 }
a2fbb9ea 3788
523224a3
DK		 3789 spe->hdr.type = cpu_to_le16(type);
3790
3791 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3792 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3793
d6cae238
VZ		 3794 /*
3795 * It's ok if the actual decrement is issued towards the memory
3796 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3797 * more explicit memory barrier is needed.
d6cae238
VZ		 3798 */
3799 if (common)
3800 atomic_dec(&bp->eq_spq_left);
3801 else
3802 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3803
51c1a580
MS		 3804 DP(BNX2X_MSG_SP,
3805 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3806 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3807 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3808 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3809 HW_CID(bp, cid), data_hi, data_lo, type,
3810 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3811
28912902 3812 bnx2x_sp_prod_update(bp);
34f80b04 3813 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3814 return 0;
3815}
3816
3817/* acquire split MCP access lock register */
4a37fb66 3818static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3819{
72fd0718 3820 u32 j, val;
34f80b04 3821 int rc = 0;
a2fbb9ea
ET		 3822
3823 might_sleep();
72fd0718 3824 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3825 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3826 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3827 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3828 break;
3829
639d65b8 3830 usleep_range(5000, 10000);
a2fbb9ea 3831 }
3cdeec22 3832 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3833 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3834 rc = -EBUSY;
3835 }
3836
3837 return rc;
3838}
3839
4a37fb66
YG		 3840/* release split MCP access lock register */
3841static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3842{
3cdeec22 3843 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3844}
3845
523224a3
DK		 3846#define BNX2X_DEF_SB_ATT_IDX 0x0001
3847#define BNX2X_DEF_SB_IDX 0x0002
3848
1191cb83 3849static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3850{
523224a3 3851 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3852 u16 rc = 0;
3853
3854 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3855 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3856 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3857 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3858 }
523224a3
DK		 3859
3860 if (bp->def_idx != def_sb->sp_sb.running_index) {
3861 bp->def_idx = def_sb->sp_sb.running_index;
3862 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3863 }
523224a3 3864
16a5fd92 3865 /* Do not reorder: indices reading should complete before handling */
523224a3 3866 barrier();
a2fbb9ea
ET		 3867 return rc;
3868}
3869
3870/*
3871 * slow path service functions
3872 */
3873
3874static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3875{
34f80b04 3876 int port = BP_PORT(bp);
a2fbb9ea
ET		 3877 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3878 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3879 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3880 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3881 u32 aeu_mask;
87942b46 3882 u32 nig_mask = 0;
f2e0899f 3883 u32 reg_addr;
a2fbb9ea 3884
a2fbb9ea
ET		 3885 if (bp->attn_state & asserted)
3886 BNX2X_ERR("IGU ERROR\n");
3887
3fcaf2e5
EG		 3888 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3889 aeu_mask = REG_RD(bp, aeu_addr);
3890
a2fbb9ea 3891 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3892 aeu_mask, asserted);
72fd0718 3893 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3894 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3895
3fcaf2e5
EG		 3896 REG_WR(bp, aeu_addr, aeu_mask);
3897 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3898
3fcaf2e5 3899 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3900 bp->attn_state |= asserted;
3fcaf2e5 3901 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3902
3903 if (asserted & ATTN_HARD_WIRED_MASK) {
3904 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3905
a5e9a7cf
EG		 3906 bnx2x_acquire_phy_lock(bp);
3907
877e9aa4 3908 /* save nig interrupt mask */
87942b46 3909 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3910
361c391e
YR		 3911 /* If nig_mask is not set, no need to call the update
3912 * function.
3913 */
3914 if (nig_mask) {
3915 REG_WR(bp, nig_int_mask_addr, 0);
3916
3917 bnx2x_link_attn(bp);
3918 }
a2fbb9ea
ET		 3919
3920 /* handle unicore attn? */
3921 }
3922 if (asserted & ATTN_SW_TIMER_4_FUNC)
3923 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3924
3925 if (asserted & GPIO_2_FUNC)
3926 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3927
3928 if (asserted & GPIO_3_FUNC)
3929 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3930
3931 if (asserted & GPIO_4_FUNC)
3932 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3933
3934 if (port == 0) {
3935 if (asserted & ATTN_GENERAL_ATTN_1) {
3936 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3937 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3938 }
3939 if (asserted & ATTN_GENERAL_ATTN_2) {
3940 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3941 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3942 }
3943 if (asserted & ATTN_GENERAL_ATTN_3) {
3944 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3945 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3946 }
3947 } else {
3948 if (asserted & ATTN_GENERAL_ATTN_4) {
3949 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3950 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3951 }
3952 if (asserted & ATTN_GENERAL_ATTN_5) {
3953 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3954 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3955 }
3956 if (asserted & ATTN_GENERAL_ATTN_6) {
3957 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3958 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3959 }
3960 }
3961
3962 } /* if hardwired */
3963
f2e0899f
DK		 3964 if (bp->common.int_block == INT_BLOCK_HC)
3965 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3966 COMMAND_REG_ATTN_BITS_SET);
3967 else
3968 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3969
3970 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3971 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3972 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3973
3974 /* now set back the mask */
a5e9a7cf 3975 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 3976 /* Verify that IGU ack through BAR was written before restoring
3977 * NIG mask. This loop should exit after 2-3 iterations max.
3978 */
3979 if (bp->common.int_block != INT_BLOCK_HC) {
3980 u32 cnt = 0, igu_acked;
3981 do {
3982 igu_acked = REG_RD(bp,
3983 IGU_REG_ATTENTION_ACK_BITS);
3984 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3985 (++cnt < MAX_IGU_ATTN_ACK_TO));
3986 if (!igu_acked)
3987 DP(NETIF_MSG_HW,
3988 "Failed to verify IGU ack on time\n");
3989 barrier();
3990 }
87942b46 3991 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3992 bnx2x_release_phy_lock(bp);
3993 }
a2fbb9ea
ET		 3994}
3995
1191cb83 3996static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 3997{
3998 int port = BP_PORT(bp);
b7737c9b 3999 u32 ext_phy_config;
fd4ef40d 4000 /* mark the failure */
b7737c9b
YR		 4001 ext_phy_config =
4002 SHMEM_RD(bp,
4003 dev_info.port_hw_config[port].external_phy_config);
4004
4005 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4006 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 4007 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 4008 ext_phy_config);
fd4ef40d
EG		 4009
4010 /* log the failure */
51c1a580
MS		 4011 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4012 "Please contact OEM Support for assistance\n");
8304859a 4013
16a5fd92 4014 /* Schedule device reset (unload)
8304859a
AE		 4015 * This is due to some boards consuming sufficient power when driver is
4016 * up to overheat if fan fails.
4017 */
230bb0f3 4018 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
fd4ef40d 4019}
ab6ad5a4 4020
1191cb83 4021static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 4022{
34f80b04 4023 int port = BP_PORT(bp);
877e9aa4 4024 int reg_offset;
d90d96ba 4025 u32 val;
877e9aa4 4026
34f80b04
EG		 4027 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4028 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 4029
34f80b04 4030 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 4031
4032 val = REG_RD(bp, reg_offset);
4033 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4034 REG_WR(bp, reg_offset, val);
4035
4036 BNX2X_ERR("SPIO5 hw attention\n");
4037
fd4ef40d 4038 /* Fan failure attention */
d90d96ba 4039 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 4040 bnx2x_fan_failure(bp);
877e9aa4 4041 }
34f80b04 4042
3deb8167 4043 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 4044 bnx2x_acquire_phy_lock(bp);
4045 bnx2x_handle_module_detect_int(&bp->link_params);
4046 bnx2x_release_phy_lock(bp);
4047 }
4048
34f80b04
EG		 4049 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4050
4051 val = REG_RD(bp, reg_offset);
4052 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4053 REG_WR(bp, reg_offset, val);
4054
4055 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 4056 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 4057 bnx2x_panic();
4058 }
877e9aa4
ET		 4059}
4060
1191cb83 4061static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4062{
4063 u32 val;
4064
0626b899 4065 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 4066
4067 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4068 BNX2X_ERR("DB hw attention 0x%x\n", val);
4069 /* DORQ discard attention */
4070 if (val & 0x2)
4071 BNX2X_ERR("FATAL error from DORQ\n");
4072 }
34f80b04
EG		 4073
4074 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4075
4076 int port = BP_PORT(bp);
4077 int reg_offset;
4078
4079 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4080 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4081
4082 val = REG_RD(bp, reg_offset);
4083 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4084 REG_WR(bp, reg_offset, val);
4085
4086 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 4087 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 4088 bnx2x_panic();
4089 }
877e9aa4
ET		 4090}
4091
1191cb83 4092static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4093{
4094 u32 val;
4095
4096 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4097
4098 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4099 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4100 /* CFC error attention */
4101 if (val & 0x2)
4102 BNX2X_ERR("FATAL error from CFC\n");
4103 }
4104
4105 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 4106 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4107 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4108 /* RQ_USDMDP_FIFO_OVERFLOW */
4109 if (val & 0x18000)
4110 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4111
4112 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4113 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4114 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4115 }
877e9aa4 4116 }
34f80b04
EG		 4117
4118 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4119
4120 int port = BP_PORT(bp);
4121 int reg_offset;
4122
4123 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4124 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4125
4126 val = REG_RD(bp, reg_offset);
4127 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4128 REG_WR(bp, reg_offset, val);
4129
4130 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 4131 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 4132 bnx2x_panic();
4133 }
877e9aa4
ET		 4134}
4135
1191cb83 4136static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4137{
34f80b04
EG		 4138 u32 val;
4139
877e9aa4
ET		 4140 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4141
34f80b04
EG		 4142 if (attn & BNX2X_PMF_LINK_ASSERT) {
4143 int func = BP_FUNC(bp);
4144
4145 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4146 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4147 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4148 func_mf_config[BP_ABS_FUNC(bp)].config);
4149 val = SHMEM_RD(bp,
4150 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 4151 if (val & DRV_STATUS_DCC_EVENT_MASK)
4152 bnx2x_dcc_event(bp,
4153 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 4154
4155 if (val & DRV_STATUS_SET_MF_BW)
4156 bnx2x_set_mf_bw(bp);
4157
1d187b34
BW		 4158 if (val & DRV_STATUS_DRV_INFO_REQ)
4159 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4160
4161 if (val & DRV_STATUS_VF_DISABLED)
370d4a26
YM		 4162 bnx2x_schedule_iov_task(bp,
4163 BNX2X_IOV_HANDLE_FLR);
d16132ce 4164
2691d51d 4165 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4166 bnx2x_pmf_update(bp);
4167
e4901dde 4168 if (bp->port.pmf &&
785b9b1a
SR		 4169 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4170 bp->dcbx_enabled > 0)
e4901dde
VZ		 4171 /* start dcbx state machine */
4172 bnx2x_dcbx_set_params(bp,
4173 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4174 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4175 bnx2x_handle_afex_cmd(bp,
4176 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4177 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4178 bnx2x_handle_eee_event(bp);
3deb8167
YR		 4179 if (bp->link_vars.periodic_flags &
4180 PERIODIC_FLAGS_LINK_EVENT) {
4181 /* sync with link */
4182 bnx2x_acquire_phy_lock(bp);
4183 bp->link_vars.periodic_flags &=
4184 ~PERIODIC_FLAGS_LINK_EVENT;
4185 bnx2x_release_phy_lock(bp);
4186 if (IS_MF(bp))
4187 bnx2x_link_sync_notify(bp);
4188 bnx2x_link_report(bp);
4189 }
4190 /* Always call it here: bnx2x_link_report() will
4191 * prevent the link indication duplication.
4192 */
4193 bnx2x__link_status_update(bp);
34f80b04 4194 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4195
4196 BNX2X_ERR("MC assert!\n");
d6cae238 4197 bnx2x_mc_assert(bp);
877e9aa4
ET		 4198 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4199 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4200 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4201 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4202 bnx2x_panic();
4203
4204 } else if (attn & BNX2X_MCP_ASSERT) {
4205
4206 BNX2X_ERR("MCP assert!\n");
4207 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4208 bnx2x_fw_dump(bp);
877e9aa4
ET		 4209
4210 } else
4211 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4212 }
4213
4214 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4215 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4216 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4217 val = CHIP_IS_E1(bp) ? 0 :
4218 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4219 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4220 }
4221 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4222 val = CHIP_IS_E1(bp) ? 0 :
4223 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4224 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4225 }
877e9aa4 4226 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4227 }
4228}
4229
c9ee9206
VZ		 4230/*
4231 * Bits map:
4232 * 0-7 - Engine0 load counter.
4233 * 8-15 - Engine1 load counter.
4234 * 16 - Engine0 RESET_IN_PROGRESS bit.
4235 * 17 - Engine1 RESET_IN_PROGRESS bit.
4236 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4237 * on the engine
4238 * 19 - Engine1 ONE_IS_LOADED.
4239 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4240 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4241 * just the one belonging to its engine).
4242 *
4243 */
4244#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4245
4246#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4247#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4248#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4249#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4250#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4251#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4252#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4253
4254/*
4255 * Set the GLOBAL_RESET bit.
4256 *
4257 * Should be run under rtnl lock
4258 */
4259void bnx2x_set_reset_global(struct bnx2x *bp)
4260{
f16da43b
AE		 4261 u32 val;
4262 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4263 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4264 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4265 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4266}
4267
4268/*
4269 * Clear the GLOBAL_RESET bit.
4270 *
4271 * Should be run under rtnl lock
4272 */
1191cb83 4273static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4274{
f16da43b
AE		 4275 u32 val;
4276 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4277 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4278 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4279 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4280}
f85582f8 4281
72fd0718 4282/*
c9ee9206
VZ		 4283 * Checks the GLOBAL_RESET bit.
4284 *
72fd0718
VZ		 4285 * should be run under rtnl lock
4286 */
1191cb83 4287static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4288{
3cdeec22 4289 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4290
4291 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4292 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4293}
4294
4295/*
4296 * Clear RESET_IN_PROGRESS bit for the current engine.
4297 *
4298 * Should be run under rtnl lock
4299 */
1191cb83 4300static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4301{
f16da43b 4302 u32 val;
c9ee9206
VZ		 4303 u32 bit = BP_PATH(bp) ?
4304 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4305 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4306 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4307
4308 /* Clear the bit */
4309 val &= ~bit;
4310 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4311
4312 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4313}
4314
4315/*
c9ee9206
VZ		 4316 * Set RESET_IN_PROGRESS for the current engine.
4317 *
72fd0718
VZ		 4318 * should be run under rtnl lock
4319 */
c9ee9206 4320void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4321{
f16da43b 4322 u32 val;
c9ee9206
VZ		 4323 u32 bit = BP_PATH(bp) ?
4324 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4325 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4326 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4327
4328 /* Set the bit */
4329 val |= bit;
4330 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4331 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4332}
4333
4334/*
c9ee9206 4335 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4336 * should be run under rtnl lock
4337 */
c9ee9206 4338bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4339{
3cdeec22 4340 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4341 u32 bit = engine ?
4342 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4343
4344 /* return false if bit is set */
4345 return (val & bit) ? false : true;
72fd0718
VZ		 4346}
4347
4348/*
889b9af3 4349 * set pf load for the current pf.
c9ee9206 4350 *
72fd0718
VZ		 4351 * should be run under rtnl lock
4352 */
889b9af3 4353void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4354{
f16da43b 4355 u32 val1, val;
c9ee9206
VZ		 4356 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4357 BNX2X_PATH0_LOAD_CNT_MASK;
4358 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4359 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4360
f16da43b
AE		 4361 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4362 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4363
51c1a580 4364 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4365
c9ee9206
VZ		 4366 /* get the current counter value */
4367 val1 = (val & mask) >> shift;
4368
889b9af3
AE		 4369 /* set bit of that PF */
4370 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4371
4372 /* clear the old value */
4373 val &= ~mask;
4374
4375 /* set the new one */
4376 val |= ((val1 << shift) & mask);
4377
4378 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4379 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4380}
4381
c9ee9206 4382/**
889b9af3 4383 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4384 *
4385 * @bp: driver handle
4386 *
4387 * Should be run under rtnl lock.
4388 * Decrements the load counter for the current engine. Returns
889b9af3 4389 * whether other functions are still loaded
72fd0718 4390 */
889b9af3 4391bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4392{
f16da43b 4393 u32 val1, val;
c9ee9206
VZ		 4394 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4395 BNX2X_PATH0_LOAD_CNT_MASK;
4396 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4397 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4398
f16da43b
AE		 4399 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4400 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4401 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4402
c9ee9206
VZ		 4403 /* get the current counter value */
4404 val1 = (val & mask) >> shift;
4405
889b9af3
AE		 4406 /* clear bit of that PF */
4407 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4408
4409 /* clear the old value */
4410 val &= ~mask;
4411
4412 /* set the new one */
4413 val |= ((val1 << shift) & mask);
4414
4415 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4416 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4417 return val1 != 0;
72fd0718
VZ		 4418}
4419
4420/*
889b9af3 4421 * Read the load status for the current engine.
c9ee9206 4422 *
72fd0718
VZ		 4423 * should be run under rtnl lock
4424 */
1191cb83 4425static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4426{
c9ee9206
VZ		 4427 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4428 BNX2X_PATH0_LOAD_CNT_MASK);
4429 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4430 BNX2X_PATH0_LOAD_CNT_SHIFT);
4431 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4432
51c1a580 4433 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4434
4435 val = (val & mask) >> shift;
4436
51c1a580
MS		 4437 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4438 engine, val);
c9ee9206 4439
889b9af3 4440 return val != 0;
72fd0718
VZ		 4441}
4442
6bf07b8e
YM		 4443static void _print_parity(struct bnx2x *bp, u32 reg)
4444{
4445 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4446}
4447
1191cb83 4448static void _print_next_block(int idx, const char *blk)
72fd0718 4449{
f1deab50 4450 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4451}
4452
4293b9f5
DK		 4453static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4454 int *par_num, bool print)
72fd0718 4455{
4293b9f5
DK		 4456 u32 cur_bit;
4457 bool res;
4458 int i;
4459
4460 res = false;
4461
72fd0718 4462 for (i = 0; sig; i++) {
4293b9f5 4463 cur_bit = (0x1UL << i);
72fd0718 4464 if (sig & cur_bit) {
4293b9f5
DK		 4465 res |= true; /* Each bit is real error! */
4466
4467 if (print) {
4468 switch (cur_bit) {
4469 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4470 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4471 _print_parity(bp,
4472 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4473 break;
4474 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4475 _print_next_block((*par_num)++,
4476 "PARSER");
6bf07b8e 4477 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4478 break;
4479 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4480 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4481 _print_parity(bp,
4482 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4483 break;
4484 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4485 _print_next_block((*par_num)++,
c9ee9206 4486 "SEARCHER");
6bf07b8e 4487 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4488 break;
4489 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4490 _print_next_block((*par_num)++, "TCM");
4491 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4492 break;
4493 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4494 _print_next_block((*par_num)++,
4495 "TSEMI");
6bf07b8e
YM		 4496 _print_parity(bp,
4497 TSEM_REG_TSEM_PRTY_STS_0);
4498 _print_parity(bp,
4499 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4500 break;
4501 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4502 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4503 _print_parity(bp, GRCBASE_XPB +
4504 PB_REG_PB_PRTY_STS);
4293b9f5 4505 break;
6bf07b8e 4506 }
72fd0718
VZ		 4507 }
4508
4509 /* Clear the bit */
4510 sig &= ~cur_bit;
4511 }
4512 }
4513
4293b9f5 4514 return res;
72fd0718
VZ		 4515}
4516
4293b9f5
DK		 4517static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4518 int *par_num, bool *global,
6bf07b8e 4519 bool print)
72fd0718 4520{
4293b9f5
DK		 4521 u32 cur_bit;
4522 bool res;
4523 int i;
4524
4525 res = false;
4526
72fd0718 4527 for (i = 0; sig; i++) {
4293b9f5 4528 cur_bit = (0x1UL << i);
72fd0718 4529 if (sig & cur_bit) {
4293b9f5 4530 res |= true; /* Each bit is real error! */
72fd0718 4531 switch (cur_bit) {
c9ee9206 4532 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4533 if (print) {
4293b9f5 4534 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4535 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4536 }
72fd0718
VZ		 4537 break;
4538 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4539 if (print) {
4293b9f5 4540 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4541 _print_parity(bp, QM_REG_QM_PRTY_STS);
4542 }
c9ee9206
VZ		 4543 break;
4544 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4545 if (print) {
4293b9f5 4546 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4547 _print_parity(bp, TM_REG_TM_PRTY_STS);
4548 }
72fd0718
VZ		 4549 break;
4550 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4551 if (print) {
4293b9f5 4552 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4553 _print_parity(bp,
4554 XSDM_REG_XSDM_PRTY_STS);
4555 }
c9ee9206
VZ		 4556 break;
4557 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4558 if (print) {
4293b9f5 4559 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4560 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4561 }
72fd0718
VZ		 4562 break;
4563 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4564 if (print) {
4293b9f5
DK		 4565 _print_next_block((*par_num)++,
4566 "XSEMI");
6bf07b8e
YM		 4567 _print_parity(bp,
4568 XSEM_REG_XSEM_PRTY_STS_0);
4569 _print_parity(bp,
4570 XSEM_REG_XSEM_PRTY_STS_1);
4571 }
72fd0718
VZ		 4572 break;
4573 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4574 if (print) {
4293b9f5 4575 _print_next_block((*par_num)++,
c9ee9206 4576 "DOORBELLQ");
6bf07b8e
YM		 4577 _print_parity(bp,
4578 DORQ_REG_DORQ_PRTY_STS);
4579 }
c9ee9206
VZ		 4580 break;
4581 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4582 if (print) {
4293b9f5 4583 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4584 if (CHIP_IS_E1x(bp)) {
4585 _print_parity(bp,
4586 NIG_REG_NIG_PRTY_STS);
4587 } else {
4588 _print_parity(bp,
4589 NIG_REG_NIG_PRTY_STS_0);
4590 _print_parity(bp,
4591 NIG_REG_NIG_PRTY_STS_1);
4592 }
4593 }
72fd0718
VZ		 4594 break;
4595 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4596 if (print)
4293b9f5 4597 _print_next_block((*par_num)++,
c9ee9206
VZ		 4598 "VAUX PCI CORE");
4599 *global = true;
72fd0718
VZ		 4600 break;
4601 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4602 if (print) {
4293b9f5
DK		 4603 _print_next_block((*par_num)++,
4604 "DEBUG");
6bf07b8e
YM		 4605 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4606 }
72fd0718
VZ		 4607 break;
4608 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4609 if (print) {
4293b9f5 4610 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4611 _print_parity(bp,
4612 USDM_REG_USDM_PRTY_STS);
4613 }
72fd0718 4614 break;
8736c826 4615 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4616 if (print) {
4293b9f5 4617 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4618 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4619 }
8736c826 4620 break;
72fd0718 4621 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4622 if (print) {
4293b9f5
DK		 4623 _print_next_block((*par_num)++,
4624 "USEMI");
6bf07b8e
YM		 4625 _print_parity(bp,
4626 USEM_REG_USEM_PRTY_STS_0);
4627 _print_parity(bp,
4628 USEM_REG_USEM_PRTY_STS_1);
4629 }
72fd0718
VZ		 4630 break;
4631 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4632 if (print) {
4293b9f5 4633 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4634 _print_parity(bp, GRCBASE_UPB +
4635 PB_REG_PB_PRTY_STS);
4636 }
72fd0718
VZ		 4637 break;
4638 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4639 if (print) {
4293b9f5 4640 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4641 _print_parity(bp,
4642 CSDM_REG_CSDM_PRTY_STS);
4643 }
72fd0718 4644 break;
8736c826 4645 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4646 if (print) {
4293b9f5 4647 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4648 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4649 }
8736c826 4650 break;
72fd0718
VZ		 4651 }
4652
4653 /* Clear the bit */
4654 sig &= ~cur_bit;
4655 }
4656 }
4657
4293b9f5 4658 return res;
72fd0718
VZ		 4659}
4660
4293b9f5
DK		 4661static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4662 int *par_num, bool print)
72fd0718 4663{
4293b9f5
DK		 4664 u32 cur_bit;
4665 bool res;
4666 int i;
4667
4668 res = false;
4669
72fd0718 4670 for (i = 0; sig; i++) {
4293b9f5 4671 cur_bit = (0x1UL << i);
72fd0718 4672 if (sig & cur_bit) {
4293b9f5
DK		 4673 res |= true; /* Each bit is real error! */
4674 if (print) {
4675 switch (cur_bit) {
4676 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4677 _print_next_block((*par_num)++,
4678 "CSEMI");
6bf07b8e
YM		 4679 _print_parity(bp,
4680 CSEM_REG_CSEM_PRTY_STS_0);
4681 _print_parity(bp,
4682 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4683 break;
4684 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4685 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4686 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4687 _print_parity(bp,
4688 PXP2_REG_PXP2_PRTY_STS_0);
4689 _print_parity(bp,
4690 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4691 break;
4692 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4693 _print_next_block((*par_num)++,
4694 "PXPPCICLOCKCLIENT");
4695 break;
4696 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4697 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4698 _print_parity(bp,
4699 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4700 break;
4701 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4702 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4703 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4704 break;
4705 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4706 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4707 _print_parity(bp,
4708 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4709 break;
4710 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4711 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4712 if (CHIP_IS_E1x(bp))
4713 _print_parity(bp,
4714 HC_REG_HC_PRTY_STS);
4715 else
4716 _print_parity(bp,
4717 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4718 break;
4719 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4720 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4721 _print_parity(bp,
4722 MISC_REG_MISC_PRTY_STS);
4293b9f5 4723 break;
6bf07b8e 4724 }
72fd0718
VZ		 4725 }
4726
4727 /* Clear the bit */
4728 sig &= ~cur_bit;
4729 }
4730 }
4731
4293b9f5 4732 return res;
72fd0718
VZ		 4733}
4734
4293b9f5
DK		 4735static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4736 int *par_num, bool *global,
4737 bool print)
72fd0718 4738{
4293b9f5
DK		 4739 bool res = false;
4740 u32 cur_bit;
4741 int i;
4742
72fd0718 4743 for (i = 0; sig; i++) {
4293b9f5 4744 cur_bit = (0x1UL << i);
72fd0718
VZ		 4745 if (sig & cur_bit) {
4746 switch (cur_bit) {
4747 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4748 if (print)
4293b9f5
DK		 4749 _print_next_block((*par_num)++,
4750 "MCP ROM");
c9ee9206 4751 *global = true;
4293b9f5 4752 res |= true;
72fd0718
VZ		 4753 break;
4754 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4755 if (print)
4293b9f5 4756 _print_next_block((*par_num)++,
c9ee9206
VZ		 4757 "MCP UMP RX");
4758 *global = true;
4293b9f5 4759 res |= true;
72fd0718
VZ		 4760 break;
4761 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4762 if (print)
4293b9f5 4763 _print_next_block((*par_num)++,
c9ee9206
VZ		 4764 "MCP UMP TX");
4765 *global = true;
4293b9f5 4766 res |= true;
72fd0718
VZ		 4767 break;
4768 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206 4769 if (print)
4293b9f5 4770 _print_next_block((*par_num)++,
c9ee9206 4771 "MCP SCPAD");
4293b9f5
DK		 4772 /* clear latched SCPAD PATIRY from MCP */
4773 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4774 1UL << 10);
72fd0718
VZ		 4775 break;
4776 }
4777
4778 /* Clear the bit */
4779 sig &= ~cur_bit;
4780 }
4781 }
4782
4293b9f5 4783 return res;
72fd0718
VZ		 4784}
4785
4293b9f5
DK		 4786static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4787 int *par_num, bool print)
8736c826 4788{
4293b9f5
DK		 4789 u32 cur_bit;
4790 bool res;
4791 int i;
4792
4793 res = false;
4794
8736c826 4795 for (i = 0; sig; i++) {
4293b9f5 4796 cur_bit = (0x1UL << i);
8736c826 4797 if (sig & cur_bit) {
4293b9f5
DK		 4798 res |= true; /* Each bit is real error! */
4799 if (print) {
4800 switch (cur_bit) {
4801 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4802 _print_next_block((*par_num)++,
4803 "PGLUE_B");
6bf07b8e 4804 _print_parity(bp,
4293b9f5
DK		 4805 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4806 break;
4807 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4808 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4809 _print_parity(bp,
4810 ATC_REG_ATC_PRTY_STS);
4293b9f5 4811 break;
6bf07b8e 4812 }
8736c826 4813 }
8736c826
VZ		 4814 /* Clear the bit */
4815 sig &= ~cur_bit;
4816 }
4817 }
4818
4293b9f5 4819 return res;
8736c826
VZ		 4820}
4821
1191cb83
ED		 4822static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4823 u32 *sig)
72fd0718 4824{
4293b9f5
DK		 4825 bool res = false;
4826
8736c826
VZ		 4827 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4828 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4829 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4830 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4831 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4832 int par_num = 0;
51c1a580
MS		 4833 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4834 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4835 sig[0] & HW_PRTY_ASSERT_SET_0,
4836 sig[1] & HW_PRTY_ASSERT_SET_1,
4837 sig[2] & HW_PRTY_ASSERT_SET_2,
4838 sig[3] & HW_PRTY_ASSERT_SET_3,
4839 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4840 if (print)
4841 netdev_err(bp->dev,
4842 "Parity errors detected in blocks: ");
4293b9f5
DK		 4843 res |= bnx2x_check_blocks_with_parity0(bp,
4844 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4845 res |= bnx2x_check_blocks_with_parity1(bp,
4846 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4847 res |= bnx2x_check_blocks_with_parity2(bp,
4848 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4849 res |= bnx2x_check_blocks_with_parity3(bp,
4850 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4851 res |= bnx2x_check_blocks_with_parity4(bp,
4852 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4853
c9ee9206
VZ		 4854 if (print)
4855 pr_cont("\n");
4293b9f5 4856 }
8736c826 4857
4293b9f5 4858 return res;
72fd0718
VZ		 4859}
4860
c9ee9206
VZ		 4861/**
4862 * bnx2x_chk_parity_attn - checks for parity attentions.
4863 *
4864 * @bp: driver handle
4865 * @global: true if there was a global attention
4866 * @print: show parity attention in syslog
4867 */
4868bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4869{
8736c826 4870 struct attn_route attn = { {0} };
72fd0718
VZ		 4871 int port = BP_PORT(bp);
4872
4873 attn.sig[0] = REG_RD(bp,
4874 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4875 port*4);
4876 attn.sig[1] = REG_RD(bp,
4877 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4878 port*4);
4879 attn.sig[2] = REG_RD(bp,
4880 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4881 port*4);
4882 attn.sig[3] = REG_RD(bp,
4883 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4884 port*4);
0a5ccb75
YM		 4885 /* Since MCP attentions can't be disabled inside the block, we need to
4886 * read AEU registers to see whether they're currently disabled
4887 */
4888 attn.sig[3] &= ((REG_RD(bp,
4889 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4890 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4891 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4892 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 4893
8736c826
VZ		 4894 if (!CHIP_IS_E1x(bp))
4895 attn.sig[4] = REG_RD(bp,
4896 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4897 port*4);
4898
4899 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4900}
4901
1191cb83 4902static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 4903{
4904 u32 val;
4905 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4906
4907 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4908 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4909 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 4910 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 4911 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 4912 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 4913 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 4914 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 4915 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 4916 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 4917 if (val &
4918 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 4919 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 4920 if (val &
4921 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 4922 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 4923 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 4924 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 4925 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 4926 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 4927 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 4928 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 4929 }
4930 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4931 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4932 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4933 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4934 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4935 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 4936 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 4937 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 4938 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 4939 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 4940 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 4941 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4942 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4943 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 4944 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 4945 }
4946
4947 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4948 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4949 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4950 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4951 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4952 }
f2e0899f
DK		 4953}
4954
72fd0718
VZ		 4955static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4956{
4957 struct attn_route attn, *group_mask;
34f80b04 4958 int port = BP_PORT(bp);
877e9aa4 4959 int index;
a2fbb9ea
ET		 4960 u32 reg_addr;
4961 u32 val;
3fcaf2e5 4962 u32 aeu_mask;
c9ee9206 4963 bool global = false;
a2fbb9ea
ET		 4964
4965 /* need to take HW lock because MCP or other port might also
4966 try to handle this event */
4a37fb66 4967 bnx2x_acquire_alr(bp);
a2fbb9ea 4968
c9ee9206
VZ		 4969 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4970#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4971 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4972 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4973 /* Disable HW interrupts */
4974 bnx2x_int_disable(bp);
72fd0718
VZ		 4975 /* In case of parity errors don't handle attentions so that
4976 * other function would "see" parity errors.
4977 */
c9ee9206
VZ		 4978#else
4979 bnx2x_panic();
4980#endif
4981 bnx2x_release_alr(bp);
72fd0718
VZ		 4982 return;
4983 }
4984
a2fbb9ea
ET		 4985 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4986 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4987 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4988 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4989 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4990 attn.sig[4] =
4991 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4992 else
4993 attn.sig[4] = 0;
4994
4995 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4996 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4997
4998 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4999 if (deasserted & (1 << index)) {
72fd0718 5000 group_mask = &bp->attn_group[index];
a2fbb9ea 5001
51c1a580 5002 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 5003 index,
5004 group_mask->sig[0], group_mask->sig[1],
5005 group_mask->sig[2], group_mask->sig[3],
5006 group_mask->sig[4]);
a2fbb9ea 5007
f2e0899f
DK		 5008 bnx2x_attn_int_deasserted4(bp,
5009 attn.sig[4] & group_mask->sig[4]);
877e9aa4 5010 bnx2x_attn_int_deasserted3(bp,
72fd0718 5011 attn.sig[3] & group_mask->sig[3]);
877e9aa4 5012 bnx2x_attn_int_deasserted1(bp,
72fd0718 5013 attn.sig[1] & group_mask->sig[1]);
877e9aa4 5014 bnx2x_attn_int_deasserted2(bp,
72fd0718 5015 attn.sig[2] & group_mask->sig[2]);
877e9aa4 5016 bnx2x_attn_int_deasserted0(bp,
72fd0718 5017 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 5018 }
5019 }
5020
4a37fb66 5021 bnx2x_release_alr(bp);
a2fbb9ea 5022
f2e0899f
DK		 5023 if (bp->common.int_block == INT_BLOCK_HC)
5024 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5025 COMMAND_REG_ATTN_BITS_CLR);
5026 else
5027 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 5028
5029 val = ~deasserted;
f2e0899f
DK		 5030 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5031 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 5032 REG_WR(bp, reg_addr, val);
a2fbb9ea 5033
a2fbb9ea 5034 if (~bp->attn_state & deasserted)
3fcaf2e5 5035 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 5036
5037 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5038 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5039
3fcaf2e5
EG		 5040 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5041 aeu_mask = REG_RD(bp, reg_addr);
5042
5043 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5044 aeu_mask, deasserted);
72fd0718 5045 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 5046 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 5047
3fcaf2e5
EG		 5048 REG_WR(bp, reg_addr, aeu_mask);
5049 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 5050
5051 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5052 bp->attn_state &= ~deasserted;
5053 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5054}
5055
5056static void bnx2x_attn_int(struct bnx2x *bp)
5057{
5058 /* read local copy of bits */
68d59484
EG		 5059 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5060 attn_bits);
5061 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5062 attn_bits_ack);
a2fbb9ea
ET		 5063 u32 attn_state = bp->attn_state;
5064
5065 /* look for changed bits */
5066 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5067 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5068
5069 DP(NETIF_MSG_HW,
5070 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5071 attn_bits, attn_ack, asserted, deasserted);
5072
5073 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 5074 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 5075
5076 /* handle bits that were raised */
5077 if (asserted)
5078 bnx2x_attn_int_asserted(bp, asserted);
5079
5080 if (deasserted)
5081 bnx2x_attn_int_deasserted(bp, deasserted);
5082}
5083
619c5cb6
VZ		 5084void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5085 u16 index, u8 op, u8 update)
5086{
dc1ba591
AE		 5087 u32 igu_addr = bp->igu_base_addr;
5088 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 5089 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5090 igu_addr);
5091}
5092
1191cb83 5093static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 5094{
5095 /* No memory barriers */
5096 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5097 mmiowb(); /* keep prod updates ordered */
5098}
5099
523224a3
DK		 5100static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5101 union event_ring_elem *elem)
5102{
619c5cb6
VZ		 5103 u8 err = elem->message.error;
5104
523224a3 5105 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 5106 (cid < bp->cnic_eth_dev.starting_cid &&
5107 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5108 return 1;
5109
5110 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5111
619c5cb6
VZ		 5112 if (unlikely(err)) {
5113
523224a3
DK		 5114 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5115 cid);
823e1d90 5116 bnx2x_panic_dump(bp, false);
523224a3 5117 }
619c5cb6 5118 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5119 return 0;
5120}
523224a3 5121
1191cb83 5122static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5123{
5124 struct bnx2x_mcast_ramrod_params rparam;
5125 int rc;
5126
5127 memset(&rparam, 0, sizeof(rparam));
5128
5129 rparam.mcast_obj = &bp->mcast_obj;
5130
5131 netif_addr_lock_bh(bp->dev);
5132
5133 /* Clear pending state for the last command */
5134 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5135
5136 /* If there are pending mcast commands - send them */
5137 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5138 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5139 if (rc < 0)
5140 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5141 rc);
5142 }
5143
5144 netif_addr_unlock_bh(bp->dev);
5145}
5146
1191cb83
ED		 5147static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5148 union event_ring_elem *elem)
619c5cb6
VZ		 5149{
5150 unsigned long ramrod_flags = 0;
5151 int rc = 0;
5152 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5153 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5154
5155 /* Always push next commands out, don't wait here */
5156 __set_bit(RAMROD_CONT, &ramrod_flags);
5157
86564c3f
YM		 5158 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5159 >> BNX2X_SWCID_SHIFT) {
619c5cb6 5160 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5161 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5162 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5163 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5164 else
15192a8c 5165 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6
VZ		 5166
5167 break;
619c5cb6 5168 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5169 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5170 /* This is only relevant for 57710 where multicast MACs are
5171 * configured as unicast MACs using the same ramrod.
5172 */
5173 bnx2x_handle_mcast_eqe(bp);
5174 return;
5175 default:
5176 BNX2X_ERR("Unsupported classification command: %d\n",
5177 elem->message.data.eth_event.echo);
5178 return;
5179 }
5180
5181 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5182
5183 if (rc < 0)
5184 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5185 else if (rc > 0)
5186 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5187}
5188
619c5cb6 5189static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5190
1191cb83 5191static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5192{
5193 netif_addr_lock_bh(bp->dev);
5194
5195 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5196
5197 /* Send rx_mode command again if was requested */
5198 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5199 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5200 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5201 &bp->sp_state))
5202 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5203 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5204 &bp->sp_state))
5205 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5206
5207 netif_addr_unlock_bh(bp->dev);
5208}
5209
1191cb83 5210static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5211 union event_ring_elem *elem)
5212{
5213 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5214 DP(BNX2X_MSG_SP,
5215 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5216 elem->message.data.vif_list_event.func_bit_map);
5217 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5218 elem->message.data.vif_list_event.func_bit_map);
5219 } else if (elem->message.data.vif_list_event.echo ==
5220 VIF_LIST_RULE_SET) {
5221 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5222 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5223 }
5224}
5225
5226/* called with rtnl_lock */
1191cb83 5227static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5228{
5229 int q, rc;
5230 struct bnx2x_fastpath *fp;
5231 struct bnx2x_queue_state_params queue_params = {NULL};
5232 struct bnx2x_queue_update_params *q_update_params =
5233 &queue_params.params.update;
5234
2de67439 5235 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5236 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5237
5238 /* set silent vlan removal values according to vlan mode */
5239 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5240 &q_update_params->update_flags);
5241 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5242 &q_update_params->update_flags);
5243 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5244
5245 /* in access mode mark mask and value are 0 to strip all vlans */
5246 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5247 q_update_params->silent_removal_value = 0;
5248 q_update_params->silent_removal_mask = 0;
5249 } else {
5250 q_update_params->silent_removal_value =
5251 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5252 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5253 }
5254
5255 for_each_eth_queue(bp, q) {
5256 /* Set the appropriate Queue object */
5257 fp = &bp->fp[q];
15192a8c 5258 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5259
5260 /* send the ramrod */
5261 rc = bnx2x_queue_state_change(bp, &queue_params);
5262 if (rc < 0)
5263 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5264 q);
5265 }
5266
fea75645 5267 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5268 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5269 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5270
5271 /* clear pending completion bit */
5272 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5273
5274 /* mark latest Q bit */
4e857c58 5275 smp_mb__before_atomic();
a3348722 5276 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 5277 smp_mb__after_atomic();
a3348722
BW		 5278
5279 /* send Q update ramrod for FCoE Q */
5280 rc = bnx2x_queue_state_change(bp, &queue_params);
5281 if (rc < 0)
5282 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5283 q);
5284 } else {
5285 /* If no FCoE ring - ACK MCP now */
5286 bnx2x_link_report(bp);
5287 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5288 }
a3348722
BW		 5289}
5290
1191cb83 5291static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5292 struct bnx2x *bp, u32 cid)
5293{
94f05b0f 5294 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5295
5296 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5297 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5298 else
15192a8c 5299 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5300}
5301
523224a3
DK		 5302static void bnx2x_eq_int(struct bnx2x *bp)
5303{
5304 u16 hw_cons, sw_cons, sw_prod;
5305 union event_ring_elem *elem;
55c11941 5306 u8 echo;
523224a3
DK		 5307 u32 cid;
5308 u8 opcode;
fd1fc79d 5309 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5310 struct bnx2x_queue_sp_obj *q_obj;
5311 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5312 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5313
5314 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5315
5316 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5317 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5318 * condition below will be met. The next element is the size of a
5319 * regular element and hence incrementing by 1
5320 */
5321 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5322 hw_cons++;
5323
25985edc 5324 /* This function may never run in parallel with itself for a
523224a3
DK		 5325 * specific bp, thus there is no need in "paired" read memory
5326 * barrier here.
5327 */
5328 sw_cons = bp->eq_cons;
5329 sw_prod = bp->eq_prod;
5330
d6cae238 5331 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5332 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5333
5334 for (; sw_cons != hw_cons;
5335 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5336
523224a3
DK		 5337 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5338
fd1fc79d
AE		 5339 rc = bnx2x_iov_eq_sp_event(bp, elem);
5340 if (!rc) {
5341 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5342 rc);
5343 goto next_spqe;
5344 }
523224a3 5345
86564c3f
YM		 5346 /* elem CID originates from FW; actually LE */
5347 cid = SW_CID((__force __le32)
5348 elem->message.data.cfc_del_event.cid);
5349 opcode = elem->message.opcode;
523224a3
DK		 5350
5351 /* handle eq element */
5352 switch (opcode) {
fd1fc79d 5353 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
370d4a26
YM		 5354 bnx2x_vf_mbx_schedule(bp,
5355 &elem->message.data.vf_pf_event);
fd1fc79d
AE		 5356 continue;
5357
523224a3 5358 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5359 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5360 "got statistics comp event %d\n",
5361 bp->stats_comp++);
523224a3 5362 /* nothing to do with stats comp */
d6cae238 5363 goto next_spqe;
523224a3
DK		 5364
5365 case EVENT_RING_OPCODE_CFC_DEL:
5366 /* handle according to cid range */
5367 /*
5368 * we may want to verify here that the bp state is
5369 * HALTING
5370 */
d6cae238 5371 DP(BNX2X_MSG_SP,
523224a3 5372 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5373
5374 if (CNIC_LOADED(bp) &&
5375 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5376 goto next_spqe;
55c11941 5377
619c5cb6
VZ		 5378 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5379
5380 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5381 break;
5382
523224a3 5383 goto next_spqe;
e4901dde
VZ		 5384
5385 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5386 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5387 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5388 if (f_obj->complete_cmd(bp, f_obj,
5389 BNX2X_F_CMD_TX_STOP))
5390 break;
e4901dde 5391 goto next_spqe;
619c5cb6 5392
e4901dde 5393 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5394 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5395 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5396 if (f_obj->complete_cmd(bp, f_obj,
5397 BNX2X_F_CMD_TX_START))
5398 break;
e4901dde 5399 goto next_spqe;
55c11941 5400
a3348722 5401 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5402 echo = elem->message.data.function_update_event.echo;
5403 if (echo == SWITCH_UPDATE) {
5404 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5405 "got FUNC_SWITCH_UPDATE ramrod\n");
5406 if (f_obj->complete_cmd(
5407 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5408 break;
a3348722 5409
55c11941 5410 } else {
230bb0f3
YM		 5411 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5412
55c11941
MS		 5413 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5414 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5415 f_obj->complete_cmd(bp, f_obj,
5416 BNX2X_F_CMD_AFEX_UPDATE);
5417
5418 /* We will perform the Queues update from
5419 * sp_rtnl task as all Queue SP operations
5420 * should run under rtnl_lock.
5421 */
230bb0f3 5422 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
55c11941 5423 }
a3348722 5424
a3348722
BW		 5425 goto next_spqe;
5426
5427 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5428 f_obj->complete_cmd(bp, f_obj,
5429 BNX2X_F_CMD_AFEX_VIFLISTS);
5430 bnx2x_after_afex_vif_lists(bp, elem);
5431 goto next_spqe;
619c5cb6 5432 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5433 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5434 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5435 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5436 break;
5437
5438 goto next_spqe;
5439
5440 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5441 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5442 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5443 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5444 break;
5445
5446 goto next_spqe;
523224a3
DK		 5447 }
5448
5449 switch (opcode | bp->state) {
619c5cb6
VZ		 5450 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5451 BNX2X_STATE_OPEN):
5452 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5453 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 5454 cid = elem->message.data.eth_event.echo &
5455 BNX2X_SWCID_MASK;
d6cae238 5456 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 5457 cid);
5458 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5459 break;
5460
619c5cb6
VZ		 5461 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5462 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5463 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5464 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5465 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5466 BNX2X_STATE_OPEN):
5467 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5468 BNX2X_STATE_DIAG):
5469 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5470 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5471 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 5472 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5473 break;
5474
619c5cb6
VZ		 5475 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5476 BNX2X_STATE_OPEN):
5477 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5478 BNX2X_STATE_DIAG):
5479 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5480 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5481 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5482 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5483 break;
5484
619c5cb6
VZ		 5485 case (EVENT_RING_OPCODE_FILTERS_RULES |
5486 BNX2X_STATE_OPEN):
5487 case (EVENT_RING_OPCODE_FILTERS_RULES |
5488 BNX2X_STATE_DIAG):
5489 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5490 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5491 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5492 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5493 break;
5494 default:
5495 /* unknown event log error and continue */
619c5cb6
VZ		 5496 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5497 elem->message.opcode, bp->state);
523224a3
DK		 5498 }
5499next_spqe:
5500 spqe_cnt++;
5501 } /* for */
5502
4e857c58 5503 smp_mb__before_atomic();
6e30dd4e 5504 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5505
5506 bp->eq_cons = sw_cons;
5507 bp->eq_prod = sw_prod;
5508 /* Make sure that above mem writes were issued towards the memory */
5509 smp_wmb();
5510
5511 /* update producer */
5512 bnx2x_update_eq_prod(bp, bp->eq_prod);
5513}
5514
a2fbb9ea
ET		 5515static void bnx2x_sp_task(struct work_struct *work)
5516{
1cf167f2 5517 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5518
fd1fc79d 5519 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5520
16a5fd92 5521 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5522 smp_rmb();
5523 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5524
fd1fc79d
AE		 5525 /* what work needs to be performed? */
5526 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5527
fd1fc79d
AE		 5528 DP(BNX2X_MSG_SP, "status %x\n", status);
5529 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5530 atomic_set(&bp->interrupt_occurred, 0);
5531
5532 /* HW attentions */
5533 if (status & BNX2X_DEF_SB_ATT_IDX) {
5534 bnx2x_attn_int(bp);
5535 status &= ~BNX2X_DEF_SB_ATT_IDX;
5536 }
5537
5538 /* SP events: STAT_QUERY and others */
5539 if (status & BNX2X_DEF_SB_IDX) {
5540 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5541
55c11941 5542 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5543 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5544 /* Prevent local bottom-halves from running as
5545 * we are going to change the local NAPI list.
5546 */
5547 local_bh_disable();
5548 napi_schedule(&bnx2x_fcoe(bp, napi));
5549 local_bh_enable();
5550 }
5551
5552 /* Handle EQ completions */
5553 bnx2x_eq_int(bp);
5554 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5555 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5556
5557 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5558 }
55c11941 5559
fd1fc79d
AE		 5560 /* if status is non zero then perhaps something went wrong */
5561 if (unlikely(status))
5562 DP(BNX2X_MSG_SP,
5563 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5564
fd1fc79d
AE		 5565 /* ack status block only if something was actually handled */
5566 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5567 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5568 }
5569
a3348722
BW		 5570 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5571 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5572 &bp->sp_state)) {
5573 bnx2x_link_report(bp);
5574 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5575 }
a2fbb9ea
ET		 5576}
5577
9f6c9258 5578irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5579{
5580 struct net_device *dev = dev_instance;
5581 struct bnx2x *bp = netdev_priv(dev);
5582
523224a3
DK		 5583 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5584 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5585
5586#ifdef BNX2X_STOP_ON_ERROR
5587 if (unlikely(bp->panic))
5588 return IRQ_HANDLED;
5589#endif
5590
55c11941 5591 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5592 struct cnic_ops *c_ops;
5593
5594 rcu_read_lock();
5595 c_ops = rcu_dereference(bp->cnic_ops);
5596 if (c_ops)
5597 c_ops->cnic_handler(bp->cnic_data, NULL);
5598 rcu_read_unlock();
5599 }
55c11941 5600
fd1fc79d
AE		 5601 /* schedule sp task to perform default status block work, ack
5602 * attentions and enable interrupts.
5603 */
5604 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5605
5606 return IRQ_HANDLED;
5607}
5608
5609/* end of slow path */
5610
619c5cb6
VZ		 5611void bnx2x_drv_pulse(struct bnx2x *bp)
5612{
5613 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5614 bp->fw_drv_pulse_wr_seq);
5615}
5616
a2fbb9ea
ET		 5617static void bnx2x_timer(unsigned long data)
5618{
5619 struct bnx2x *bp = (struct bnx2x *) data;
5620
5621 if (!netif_running(bp->dev))
5622 return;
5623
67c431a5
AE		 5624 if (IS_PF(bp) &&
5625 !BP_NOMCP(bp)) {
f2e0899f 5626 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5627 u16 drv_pulse;
5628 u16 mcp_pulse;
a2fbb9ea
ET		 5629
5630 ++bp->fw_drv_pulse_wr_seq;
5631 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5632 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5633 bnx2x_drv_pulse(bp);
a2fbb9ea 5634
f2e0899f 5635 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5636 MCP_PULSE_SEQ_MASK);
5637 /* The delta between driver pulse and mcp response
4c868664
EG		 5638 * should not get too big. If the MFW is more than 5 pulses
5639 * behind, we should worry about it enough to generate an error
5640 * log.
a2fbb9ea 5641 */
4c868664
EG		 5642 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5643 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5644 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5645 }
5646
f34d28ea 5647 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5648 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5649
abc5a021 5650 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5651 if (IS_VF(bp))
5652 bnx2x_timer_sriov(bp);
78c3bcc5 5653
a2fbb9ea
ET		 5654 mod_timer(&bp->timer, jiffies + bp->current_interval);
5655}
5656
5657/* end of Statistics */
5658
5659/* nic init */
5660
5661/*
5662 * nic init service functions
5663 */
5664
1191cb83 5665static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5666{
523224a3
DK		 5667 u32 i;
5668 if (!(len%4) && !(addr%4))
5669 for (i = 0; i < len; i += 4)
5670 REG_WR(bp, addr + i, fill);
5671 else
5672 for (i = 0; i < len; i++)
5673 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5674}
5675
523224a3 5676/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5677static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5678 int fw_sb_id,
5679 u32 *sb_data_p,
5680 u32 data_size)
34f80b04 5681{
a2fbb9ea 5682 int index;
523224a3
DK		 5683 for (index = 0; index < data_size; index++)
5684 REG_WR(bp, BAR_CSTRORM_INTMEM +
5685 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5686 sizeof(u32)*index,
5687 *(sb_data_p + index));
5688}
a2fbb9ea 5689
1191cb83 5690static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5691{
5692 u32 *sb_data_p;
5693 u32 data_size = 0;
f2e0899f 5694 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5695 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5696
523224a3 5697 /* disable the function first */
619c5cb6 5698 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5699 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5700 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5701 sb_data_e2.common.p_func.vf_valid = false;
5702 sb_data_p = (u32 *)&sb_data_e2;
5703 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5704 } else {
5705 memset(&sb_data_e1x, 0,
5706 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5707 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5708 sb_data_e1x.common.p_func.vf_valid = false;
5709 sb_data_p = (u32 *)&sb_data_e1x;
5710 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5711 }
523224a3 5712 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5713
523224a3
DK		 5714 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5715 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5716 CSTORM_STATUS_BLOCK_SIZE);
5717 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5718 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5719 CSTORM_SYNC_BLOCK_SIZE);
5720}
34f80b04 5721
523224a3 5722/* helper: writes SP SB data to FW */
1191cb83 5723static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5724 struct hc_sp_status_block_data *sp_sb_data)
5725{
5726 int func = BP_FUNC(bp);
5727 int i;
5728 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5729 REG_WR(bp, BAR_CSTRORM_INTMEM +
5730 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5731 i*sizeof(u32),
5732 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5733}
5734
1191cb83 5735static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5736{
5737 int func = BP_FUNC(bp);
523224a3
DK		 5738 struct hc_sp_status_block_data sp_sb_data;
5739 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5740
619c5cb6 5741 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5742 sp_sb_data.p_func.vf_valid = false;
5743
5744 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5745
5746 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5747 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5748 CSTORM_SP_STATUS_BLOCK_SIZE);
5749 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5750 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5751 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5752}
5753
1191cb83 5754static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5755 int igu_sb_id, int igu_seg_id)
5756{
5757 hc_sm->igu_sb_id = igu_sb_id;
5758 hc_sm->igu_seg_id = igu_seg_id;
5759 hc_sm->timer_value = 0xFF;
5760 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5761}
5762
150966ad 5763/* allocates state machine ids. */
1191cb83 5764static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5765{
5766 /* zero out state machine indices */
5767 /* rx indices */
5768 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5769
5770 /* tx indices */
5771 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5772 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5773 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5774 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5775
5776 /* map indices */
5777 /* rx indices */
5778 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5779 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5780
5781 /* tx indices */
5782 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5783 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5784 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5785 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5786 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5787 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5788 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5789 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5790}
5791
b93288d5 5792void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5793 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5794{
523224a3
DK		 5795 int igu_seg_id;
5796
f2e0899f 5797 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5798 struct hc_status_block_data_e1x sb_data_e1x;
5799 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5800 int data_size;
5801 u32 *sb_data_p;
5802
f2e0899f
DK		 5803 if (CHIP_INT_MODE_IS_BC(bp))
5804 igu_seg_id = HC_SEG_ACCESS_NORM;
5805 else
5806 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5807
5808 bnx2x_zero_fp_sb(bp, fw_sb_id);
5809
619c5cb6 5810 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5811 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5812 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5813 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5814 sb_data_e2.common.p_func.vf_id = vfid;
5815 sb_data_e2.common.p_func.vf_valid = vf_valid;
5816 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5817 sb_data_e2.common.same_igu_sb_1b = true;
5818 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5819 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5820 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5821 sb_data_p = (u32 *)&sb_data_e2;
5822 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5823 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5824 } else {
5825 memset(&sb_data_e1x, 0,
5826 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5827 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5828 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5829 sb_data_e1x.common.p_func.vf_id = 0xff;
5830 sb_data_e1x.common.p_func.vf_valid = false;
5831 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5832 sb_data_e1x.common.same_igu_sb_1b = true;
5833 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5834 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5835 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5836 sb_data_p = (u32 *)&sb_data_e1x;
5837 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5838 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5839 }
523224a3
DK		 5840
5841 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5842 igu_sb_id, igu_seg_id);
5843 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5844 igu_sb_id, igu_seg_id);
5845
51c1a580 5846 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 5847
86564c3f 5848 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 5849 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5850}
5851
619c5cb6 5852static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5853 u16 tx_usec, u16 rx_usec)
5854{
6383c0b3 5855 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5856 false, rx_usec);
6383c0b3
AE		 5857 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5858 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5859 tx_usec);
5860 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5861 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5862 tx_usec);
5863 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5864 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5865 tx_usec);
523224a3 5866}
f2e0899f 5867
523224a3
DK		 5868static void bnx2x_init_def_sb(struct bnx2x *bp)
5869{
5870 struct host_sp_status_block *def_sb = bp->def_status_blk;
5871 dma_addr_t mapping = bp->def_status_blk_mapping;
5872 int igu_sp_sb_index;
5873 int igu_seg_id;
34f80b04
EG		 5874 int port = BP_PORT(bp);
5875 int func = BP_FUNC(bp);
f2eaeb58 5876 int reg_offset, reg_offset_en5;
a2fbb9ea 5877 u64 section;
523224a3
DK		 5878 int index;
5879 struct hc_sp_status_block_data sp_sb_data;
5880 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5881
f2e0899f
DK		 5882 if (CHIP_INT_MODE_IS_BC(bp)) {
5883 igu_sp_sb_index = DEF_SB_IGU_ID;
5884 igu_seg_id = HC_SEG_ACCESS_DEF;
5885 } else {
5886 igu_sp_sb_index = bp->igu_dsb_id;
5887 igu_seg_id = IGU_SEG_ACCESS_DEF;
5888 }
a2fbb9ea
ET		 5889
5890 /* ATTN */
523224a3 5891 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5892 atten_status_block);
523224a3 5893 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5894
49d66772
ET		 5895 bp->attn_state = 0;
5896
a2fbb9ea
ET		 5897 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5898 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5899 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5900 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5901 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5902 int sindex;
5903 /* take care of sig[0]..sig[4] */
5904 for (sindex = 0; sindex < 4; sindex++)
5905 bp->attn_group[index].sig[sindex] =
5906 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5907
619c5cb6 5908 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5909 /*
5910 * enable5 is separate from the rest of the registers,
5911 * and therefore the address skip is 4
5912 * and not 16 between the different groups
5913 */
5914 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5915 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5916 else
5917 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5918 }
5919
f2e0899f
DK		 5920 if (bp->common.int_block == INT_BLOCK_HC) {
5921 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5922 HC_REG_ATTN_MSG0_ADDR_L);
5923
5924 REG_WR(bp, reg_offset, U64_LO(section));
5925 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5926 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5927 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5928 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5929 }
a2fbb9ea 5930
523224a3
DK		 5931 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5932 sp_sb);
a2fbb9ea 5933
523224a3 5934 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5935
86564c3f 5936 /* PCI guarantees endianity of regpairs */
619c5cb6 5937 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5938 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5939 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5940 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5941 sp_sb_data.igu_seg_id = igu_seg_id;
5942 sp_sb_data.p_func.pf_id = func;
f2e0899f 5943 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5944 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5945
523224a3 5946 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5947
523224a3 5948 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5949}
5950
9f6c9258 5951void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5952{
a2fbb9ea
ET		 5953 int i;
5954
ec6ba945 5955 for_each_eth_queue(bp, i)
523224a3 5956 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5957 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5958}
5959
a2fbb9ea
ET		 5960static void bnx2x_init_sp_ring(struct bnx2x *bp)
5961{
a2fbb9ea 5962 spin_lock_init(&bp->spq_lock);
6e30dd4e 5963 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5964
a2fbb9ea 5965 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5966 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5967 bp->spq_prod_bd = bp->spq;
5968 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5969}
5970
523224a3 5971static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5972{
5973 int i;
523224a3
DK		 5974 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5975 union event_ring_elem *elem =
5976 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5977
523224a3
DK		 5978 elem->next_page.addr.hi =
5979 cpu_to_le32(U64_HI(bp->eq_mapping +
5980 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5981 elem->next_page.addr.lo =
5982 cpu_to_le32(U64_LO(bp->eq_mapping +
5983 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5984 }
523224a3
DK		 5985 bp->eq_cons = 0;
5986 bp->eq_prod = NUM_EQ_DESC;
5987 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 5988 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 5989 atomic_set(&bp->eq_spq_left,
5990 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5991}
5992
619c5cb6 5993/* called with netif_addr_lock_bh() */
a8f47eb7 5994static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5995 unsigned long rx_mode_flags,
5996 unsigned long rx_accept_flags,
5997 unsigned long tx_accept_flags,
5998 unsigned long ramrod_flags)
ab532cf3 5999{
619c5cb6
VZ		 6000 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6001 int rc;
6002
6003 memset(&ramrod_param, 0, sizeof(ramrod_param));
6004
6005 /* Prepare ramrod parameters */
6006 ramrod_param.cid = 0;
6007 ramrod_param.cl_id = cl_id;
6008 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6009 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 6010
619c5cb6
VZ		 6011 ramrod_param.pstate = &bp->sp_state;
6012 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 6013
619c5cb6
VZ		 6014 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6015 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6016
6017 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6018
6019 ramrod_param.ramrod_flags = ramrod_flags;
6020 ramrod_param.rx_mode_flags = rx_mode_flags;
6021
6022 ramrod_param.rx_accept_flags = rx_accept_flags;
6023 ramrod_param.tx_accept_flags = tx_accept_flags;
6024
6025 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6026 if (rc < 0) {
6027 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 6028 return rc;
619c5cb6 6029 }
924d75ab
YM		 6030
6031 return 0;
a2fbb9ea
ET		 6032}
6033
86564c3f
YM		 6034static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6035 unsigned long *rx_accept_flags,
6036 unsigned long *tx_accept_flags)
471de716 6037{
924d75ab
YM		 6038 /* Clear the flags first */
6039 *rx_accept_flags = 0;
6040 *tx_accept_flags = 0;
619c5cb6 6041
924d75ab 6042 switch (rx_mode) {
619c5cb6
VZ		 6043 case BNX2X_RX_MODE_NONE:
6044 /*
6045 * 'drop all' supersedes any accept flags that may have been
6046 * passed to the function.
6047 */
6048 break;
6049 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 6050 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6051 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6052 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6053
6054 /* internal switching mode */
924d75ab
YM		 6055 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6056 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6057 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6058
6059 break;
6060 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 6061 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6062 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6063 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6064
6065 /* internal switching mode */
924d75ab
YM		 6066 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6067 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6068 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6069
6070 break;
6071 case BNX2X_RX_MODE_PROMISC:
16a5fd92 6072 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 6073 * should receive matched and unmatched (in resolution of port)
6074 * unicast packets.
6075 */
924d75ab
YM		 6076 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6077 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6078 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6079 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6080
6081 /* internal switching mode */
924d75ab
YM		 6082 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6083 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6084
6085 if (IS_MF_SI(bp))
924d75ab 6086 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 6087 else
924d75ab 6088 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6
VZ		 6089
6090 break;
6091 default:
924d75ab
YM		 6092 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6093 return -EINVAL;
619c5cb6 6094 }
de832a55 6095
924d75ab 6096 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
619c5cb6 6097 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
924d75ab
YM		 6098 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6099 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
34f80b04
EG		 6100 }
6101
924d75ab
YM		 6102 return 0;
6103}
6104
6105/* called with netif_addr_lock_bh() */
a8f47eb7 6106static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6107{
6108 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6109 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6110 int rc;
6111
6112 if (!NO_FCOE(bp))
6113 /* Configure rx_mode of FCoE Queue */
6114 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6115
6116 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6117 &tx_accept_flags);
6118 if (rc)
6119 return rc;
6120
619c5cb6
VZ		 6121 __set_bit(RAMROD_RX, &ramrod_flags);
6122 __set_bit(RAMROD_TX, &ramrod_flags);
6123
924d75ab
YM		 6124 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6125 rx_accept_flags, tx_accept_flags,
6126 ramrod_flags);
619c5cb6
VZ		 6127}
6128
6129static void bnx2x_init_internal_common(struct bnx2x *bp)
6130{
6131 int i;
6132
523224a3
DK		 6133 /* Zero this manually as its initialization is
6134 currently missing in the initTool */
6135 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6136 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6137 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6138 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6139 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6140 CHIP_INT_MODE_IS_BC(bp) ?
6141 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6142 }
523224a3 6143}
8a1c38d1 6144
471de716
EG		 6145static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6146{
6147 switch (load_code) {
6148 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6149 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6150 bnx2x_init_internal_common(bp);
6151 /* no break */
6152
6153 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6154 /* nothing to do */
471de716
EG		 6155 /* no break */
6156
6157 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6158 /* internal memory per function is
6159 initialized inside bnx2x_pf_init */
471de716
EG		 6160 break;
6161
6162 default:
6163 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6164 break;
6165 }
6166}
6167
619c5cb6 6168static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6169{
55c11941 6170 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6171}
523224a3 6172
619c5cb6
VZ		 6173static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6174{
55c11941 6175 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6176}
6177
1191cb83 6178static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6179{
6180 if (CHIP_IS_E1x(fp->bp))
6181 return BP_L_ID(fp->bp) + fp->index;
6182 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6183 return bnx2x_fp_igu_sb_id(fp);
6184}
6185
6383c0b3 6186static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6187{
6188 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6189 u8 cos;
619c5cb6 6190 unsigned long q_type = 0;
6383c0b3 6191 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6192 fp->rx_queue = fp_idx;
b3b83c3f 6193 fp->cid = fp_idx;
619c5cb6
VZ		 6194 fp->cl_id = bnx2x_fp_cl_id(fp);
6195 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6196 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6197 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6198 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6199
523224a3 6200 /* init shortcut */
619c5cb6 6201 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6202
16a5fd92 6203 /* Setup SB indices */
523224a3 6204 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6205
619c5cb6
VZ		 6206 /* Configure Queue State object */
6207 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6208 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6209
6210 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6211
6212 /* init tx data */
6213 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6214 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6215 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6216 FP_COS_TO_TXQ(fp, cos, bp),
6217 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6218 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6219 }
6220
ad5afc89
AE		 6221 /* nothing more for vf to do here */
6222 if (IS_VF(bp))
6223 return;
6224
6225 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6226 fp->fw_sb_id, fp->igu_sb_id);
6227 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6228 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6229 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6230 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6231
6232 /**
6233 * Configure classification DBs: Always enable Tx switching
6234 */
6235 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6236
ad5afc89
AE		 6237 DP(NETIF_MSG_IFUP,
6238 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6239 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6240 fp->igu_sb_id);
523224a3
DK		 6241}
6242
1191cb83
ED		 6243static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6244{
6245 int i;
6246
6247 for (i = 1; i <= NUM_TX_RINGS; i++) {
6248 struct eth_tx_next_bd *tx_next_bd =
6249 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6250
6251 tx_next_bd->addr_hi =
6252 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6253 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6254 tx_next_bd->addr_lo =
6255 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6256 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6257 }
6258
639d65b8
YM		 6259 *txdata->tx_cons_sb = cpu_to_le16(0);
6260
1191cb83
ED		 6261 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6262 txdata->tx_db.data.zero_fill1 = 0;
6263 txdata->tx_db.data.prod = 0;
6264
6265 txdata->tx_pkt_prod = 0;
6266 txdata->tx_pkt_cons = 0;
6267 txdata->tx_bd_prod = 0;
6268 txdata->tx_bd_cons = 0;
6269 txdata->tx_pkt = 0;
6270}
6271
55c11941
MS		 6272static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6273{
6274 int i;
6275
6276 for_each_tx_queue_cnic(bp, i)
6277 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6278}
d76a6111 6279
1191cb83
ED		 6280static void bnx2x_init_tx_rings(struct bnx2x *bp)
6281{
6282 int i;
6283 u8 cos;
6284
55c11941 6285 for_each_eth_queue(bp, i)
1191cb83 6286 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6287 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6288}
6289
a8f47eb7 6290static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6291{
6292 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6293 unsigned long q_type = 0;
6294
6295 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6296 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6297 BNX2X_FCOE_ETH_CL_ID_IDX);
6298 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6299 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6300 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6301 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6302 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6303 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6304 fp);
6305
6306 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6307
6308 /* qZone id equals to FW (per path) client id */
6309 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6310 /* init shortcut */
6311 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6312 bnx2x_rx_ustorm_prods_offset(fp);
6313
6314 /* Configure Queue State object */
6315 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6316 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6317
6318 /* No multi-CoS for FCoE L2 client */
6319 BUG_ON(fp->max_cos != 1);
6320
6321 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6322 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6323 bnx2x_sp_mapping(bp, q_rdata), q_type);
6324
6325 DP(NETIF_MSG_IFUP,
6326 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6327 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6328 fp->igu_sb_id);
6329}
6330
55c11941 6331void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6332{
ec6ba945
VZ		 6333 if (!NO_FCOE(bp))
6334 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6335
6336 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6337 BNX2X_VF_ID_INVALID, false,
619c5cb6 6338 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6339
55c11941
MS		 6340 /* ensure status block indices were read */
6341 rmb();
6342 bnx2x_init_rx_rings_cnic(bp);
6343 bnx2x_init_tx_rings_cnic(bp);
6344
6345 /* flush all */
6346 mb();
6347 mmiowb();
6348}
a2fbb9ea 6349
ecf01c22 6350void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6351{
6352 int i;
6353
ecf01c22 6354 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6355 for_each_eth_queue(bp, i)
6356 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6357
6358 /* ensure status block indices were read */
6359 rmb();
6360 bnx2x_init_rx_rings(bp);
6361 bnx2x_init_tx_rings(bp);
6362
ecf01c22
YM		 6363 if (IS_PF(bp)) {
6364 /* Initialize MOD_ABS interrupts */
6365 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6366 bp->common.shmem_base,
6367 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6368
ecf01c22
YM		 6369 /* initialize the default status block and sp ring */
6370 bnx2x_init_def_sb(bp);
6371 bnx2x_update_dsb_idx(bp);
6372 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6373 } else {
6374 bnx2x_memset_stats(bp);
ecf01c22
YM		 6375 }
6376}
16119785 6377
ecf01c22
YM		 6378void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6379{
523224a3 6380 bnx2x_init_eq_ring(bp);
471de716 6381 bnx2x_init_internal(bp, load_code);
523224a3 6382 bnx2x_pf_init(bp);
0ef00459
EG		 6383 bnx2x_stats_init(bp);
6384
0ef00459
EG		 6385 /* flush all before enabling interrupts */
6386 mb();
6387 mmiowb();
6388
615f8fd9 6389 bnx2x_int_enable(bp);
eb8da205
EG		 6390
6391 /* Check for SPIO5 */
6392 bnx2x_attn_int_deasserted0(bp,
6393 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6394 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6395}
6396
ecf01c22 6397/* gzip service functions */
a2fbb9ea
ET		 6398static int bnx2x_gunzip_init(struct bnx2x *bp)
6399{
1a983142
FT		 6400 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6401 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6402 if (bp->gunzip_buf == NULL)
6403 goto gunzip_nomem1;
6404
6405 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6406 if (bp->strm == NULL)
6407 goto gunzip_nomem2;
6408
7ab24bfd 6409 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6410 if (bp->strm->workspace == NULL)
6411 goto gunzip_nomem3;
6412
6413 return 0;
6414
6415gunzip_nomem3:
6416 kfree(bp->strm);
6417 bp->strm = NULL;
6418
6419gunzip_nomem2:
1a983142
FT		 6420 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6421 bp->gunzip_mapping);
a2fbb9ea
ET		 6422 bp->gunzip_buf = NULL;
6423
6424gunzip_nomem1:
51c1a580 6425 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6426 return -ENOMEM;
6427}
6428
6429static void bnx2x_gunzip_end(struct bnx2x *bp)
6430{
b3b83c3f 6431 if (bp->strm) {
7ab24bfd 6432 vfree(bp->strm->workspace);
b3b83c3f
DK		 6433 kfree(bp->strm);
6434 bp->strm = NULL;
6435 }
a2fbb9ea
ET		 6436
6437 if (bp->gunzip_buf) {
1a983142
FT		 6438 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6439 bp->gunzip_mapping);
a2fbb9ea
ET		 6440 bp->gunzip_buf = NULL;
6441 }
6442}
6443
94a78b79 6444static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6445{
6446 int n, rc;
6447
6448 /* check gzip header */
94a78b79
VZ		 6449 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6450 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6451 return -EINVAL;
94a78b79 6452 }
a2fbb9ea
ET		 6453
6454 n = 10;
6455
34f80b04 6456#define FNAME 0x8
a2fbb9ea
ET		 6457
6458 if (zbuf[3] & FNAME)
6459 while ((zbuf[n++] != 0) && (n < len));
6460
94a78b79 6461 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6462 bp->strm->avail_in = len - n;
6463 bp->strm->next_out = bp->gunzip_buf;
6464 bp->strm->avail_out = FW_BUF_SIZE;
6465
6466 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6467 if (rc != Z_OK)
6468 return rc;
6469
6470 rc = zlib_inflate(bp->strm, Z_FINISH);
6471 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6472 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6473 bp->strm->msg);
a2fbb9ea
ET		 6474
6475 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6476 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6477 netdev_err(bp->dev,
6478 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6479 bp->gunzip_outlen);
a2fbb9ea
ET		 6480 bp->gunzip_outlen >>= 2;
6481
6482 zlib_inflateEnd(bp->strm);
6483
6484 if (rc == Z_STREAM_END)
6485 return 0;
6486
6487 return rc;
6488}
6489
6490/* nic load/unload */
6491
6492/*
34f80b04 6493 * General service functions
a2fbb9ea
ET		 6494 */
6495
6496/* send a NIG loopback debug packet */
6497static void bnx2x_lb_pckt(struct bnx2x *bp)
6498{
a2fbb9ea 6499 u32 wb_write[3];
a2fbb9ea
ET		 6500
6501 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6502 wb_write[0] = 0x55555555;
6503 wb_write[1] = 0x55555555;
34f80b04 6504 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6505 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6506
6507 /* NON-IP protocol */
a2fbb9ea
ET		 6508 wb_write[0] = 0x09000000;
6509 wb_write[1] = 0x55555555;
34f80b04 6510 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6511 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6512}
6513
6514/* some of the internal memories
6515 * are not directly readable from the driver
6516 * to test them we send debug packets
6517 */
6518static int bnx2x_int_mem_test(struct bnx2x *bp)
6519{
6520 int factor;
6521 int count, i;
6522 u32 val = 0;
6523
ad8d3948 6524 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6525 factor = 120;
ad8d3948
EG		 6526 else if (CHIP_REV_IS_EMUL(bp))
6527 factor = 200;
6528 else
a2fbb9ea 6529 factor = 1;
a2fbb9ea 6530
a2fbb9ea
ET		 6531 /* Disable inputs of parser neighbor blocks */
6532 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6533 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6534 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6535 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6536
6537 /* Write 0 to parser credits for CFC search request */
6538 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6539
6540 /* send Ethernet packet */
6541 bnx2x_lb_pckt(bp);
6542
6543 /* TODO do i reset NIG statistic? */
6544 /* Wait until NIG register shows 1 packet of size 0x10 */
6545 count = 1000 * factor;
6546 while (count) {
34f80b04 6547
a2fbb9ea
ET		 6548 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6549 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6550 if (val == 0x10)
6551 break;
6552
639d65b8 6553 usleep_range(10000, 20000);
a2fbb9ea
ET		 6554 count--;
6555 }
6556 if (val != 0x10) {
6557 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6558 return -1;
6559 }
6560
6561 /* Wait until PRS register shows 1 packet */
6562 count = 1000 * factor;
6563 while (count) {
6564 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6565 if (val == 1)
6566 break;
6567
639d65b8 6568 usleep_range(10000, 20000);
a2fbb9ea
ET		 6569 count--;
6570 }
6571 if (val != 0x1) {
6572 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6573 return -2;
6574 }
6575
6576 /* Reset and init BRB, PRS */
34f80b04 6577 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6578 msleep(50);
34f80b04 6579 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6580 msleep(50);
619c5cb6
VZ		 6581 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6582 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6583
6584 DP(NETIF_MSG_HW, "part2\n");
6585
6586 /* Disable inputs of parser neighbor blocks */
6587 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6588 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6589 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6590 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6591
6592 /* Write 0 to parser credits for CFC search request */
6593 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6594
6595 /* send 10 Ethernet packets */
6596 for (i = 0; i < 10; i++)
6597 bnx2x_lb_pckt(bp);
6598
6599 /* Wait until NIG register shows 10 + 1
6600 packets of size 11*0x10 = 0xb0 */
6601 count = 1000 * factor;
6602 while (count) {
34f80b04 6603
a2fbb9ea
ET		 6604 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6605 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6606 if (val == 0xb0)
6607 break;
6608
639d65b8 6609 usleep_range(10000, 20000);
a2fbb9ea
ET		 6610 count--;
6611 }
6612 if (val != 0xb0) {
6613 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6614 return -3;
6615 }
6616
6617 /* Wait until PRS register shows 2 packets */
6618 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6619 if (val != 2)
6620 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6621
6622 /* Write 1 to parser credits for CFC search request */
6623 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6624
6625 /* Wait until PRS register shows 3 packets */
6626 msleep(10 * factor);
6627 /* Wait until NIG register shows 1 packet of size 0x10 */
6628 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6629 if (val != 3)
6630 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6631
6632 /* clear NIG EOP FIFO */
6633 for (i = 0; i < 11; i++)
6634 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6635 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6636 if (val != 1) {
6637 BNX2X_ERR("clear of NIG failed\n");
6638 return -4;
6639 }
6640
6641 /* Reset and init BRB, PRS, NIG */
6642 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6643 msleep(50);
6644 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6645 msleep(50);
619c5cb6
VZ		 6646 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6647 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6648 if (!CNIC_SUPPORT(bp))
6649 /* set NIC mode */
6650 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6651
6652 /* Enable inputs of parser neighbor blocks */
6653 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6654 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6655 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6656 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6657
6658 DP(NETIF_MSG_HW, "done\n");
6659
6660 return 0; /* OK */
6661}
6662
4a33bc03 6663static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6664{
b343d002
YM		 6665 u32 val;
6666
a2fbb9ea 6667 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6668 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6669 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6670 else
6671 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6672 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6673 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6674 /*
6675 * mask read length error interrupts in brb for parser
6676 * (parsing unit and 'checksum and crc' unit)
6677 * these errors are legal (PU reads fixed length and CAC can cause
6678 * read length error on truncated packets)
6679 */
6680 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6681 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6682 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6683 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6684 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6685 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6686/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6687/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6688 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6689 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6690 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6691/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6692/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6693 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6694 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6695 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6696 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6697/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6698/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6699
b343d002
YM		 6700 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6701 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6702 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6703 if (!CHIP_IS_E1x(bp))
6704 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6705 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6706 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6707
a2fbb9ea
ET		 6708 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6709 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6710 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6711/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6712
6713 if (!CHIP_IS_E1x(bp))
6714 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6715 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6716
a2fbb9ea
ET		 6717 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6718 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6719/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6720 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6721}
6722
81f75bbf
EG		 6723static void bnx2x_reset_common(struct bnx2x *bp)
6724{
619c5cb6
VZ		 6725 u32 val = 0x1400;
6726
81f75bbf
EG		 6727 /* reset_common */
6728 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6729 0xd3ffff7f);
619c5cb6
VZ		 6730
6731 if (CHIP_IS_E3(bp)) {
6732 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6733 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6734 }
6735
6736 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6737}
6738
6739static void bnx2x_setup_dmae(struct bnx2x *bp)
6740{
6741 bp->dmae_ready = 0;
6742 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6743}
6744
573f2035
EG		 6745static void bnx2x_init_pxp(struct bnx2x *bp)
6746{
6747 u16 devctl;
6748 int r_order, w_order;
6749
2a80eebc 6750 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6751 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6752 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6753 if (bp->mrrs == -1)
6754 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6755 else {
6756 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6757 r_order = bp->mrrs;
6758 }
6759
6760 bnx2x_init_pxp_arb(bp, r_order, w_order);
6761}
fd4ef40d
EG		 6762
6763static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6764{
2145a920 6765 int is_required;
fd4ef40d 6766 u32 val;
2145a920 6767 int port;
fd4ef40d 6768
2145a920
VZ		 6769 if (BP_NOMCP(bp))
6770 return;
6771
6772 is_required = 0;
fd4ef40d
EG		 6773 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6774 SHARED_HW_CFG_FAN_FAILURE_MASK;
6775
6776 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6777 is_required = 1;
6778
6779 /*
6780 * The fan failure mechanism is usually related to the PHY type since
6781 * the power consumption of the board is affected by the PHY. Currently,
6782 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6783 */
6784 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6785 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6786 is_required |=
d90d96ba
YR		 6787 bnx2x_fan_failure_det_req(
6788 bp,
6789 bp->common.shmem_base,
a22f0788 6790 bp->common.shmem2_base,
d90d96ba 6791 port);
fd4ef40d
EG		 6792 }
6793
6794 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6795
6796 if (is_required == 0)
6797 return;
6798
6799 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6800 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6801
6802 /* set to active low mode */
6803 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6804 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6805 REG_WR(bp, MISC_REG_SPIO_INT, val);
6806
6807 /* enable interrupt to signal the IGU */
6808 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6809 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6810 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6811}
6812
c9ee9206 6813void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6814{
6815 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6816 val &= ~IGU_PF_CONF_FUNC_EN;
6817
6818 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6819 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6820 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6821}
6822
1191cb83 6823static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6824{
6825 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6826 /* Avoid common init in case MFW supports LFA */
6827 if (SHMEM2_RD(bp, size) >
6828 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6829 return;
619c5cb6
VZ		 6830 shmem_base[0] = bp->common.shmem_base;
6831 shmem2_base[0] = bp->common.shmem2_base;
6832 if (!CHIP_IS_E1x(bp)) {
6833 shmem_base[1] =
6834 SHMEM2_RD(bp, other_shmem_base_addr);
6835 shmem2_base[1] =
6836 SHMEM2_RD(bp, other_shmem2_base_addr);
6837 }
6838 bnx2x_acquire_phy_lock(bp);
6839 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6840 bp->common.chip_id);
6841 bnx2x_release_phy_lock(bp);
6842}
6843
6844/**
6845 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6846 *
6847 * @bp: driver handle
6848 */
6849static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6850{
619c5cb6 6851 u32 val;
a2fbb9ea 6852
51c1a580 6853 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6854
2031bd3a 6855 /*
2de67439 6856 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 6857 * registers while we're resetting the chip
6858 */
7a06a122 6859 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6860
81f75bbf 6861 bnx2x_reset_common(bp);
34f80b04 6862 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6863
619c5cb6
VZ		 6864 val = 0xfffc;
6865 if (CHIP_IS_E3(bp)) {
6866 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6867 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6868 }
6869 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6870
7a06a122 6871 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6872
619c5cb6 6873 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6874
619c5cb6
VZ		 6875 if (!CHIP_IS_E1x(bp)) {
6876 u8 abs_func_id;
f2e0899f
DK		 6877
6878 /**
6879 * 4-port mode or 2-port mode we need to turn of master-enable
6880 * for everyone, after that, turn it back on for self.
6881 * so, we disregard multi-function or not, and always disable
6882 * for all functions on the given path, this means 0,2,4,6 for
6883 * path 0 and 1,3,5,7 for path 1
6884 */
619c5cb6
VZ		 6885 for (abs_func_id = BP_PATH(bp);
6886 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6887 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6888 REG_WR(bp,
6889 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6890 1);
6891 continue;
6892 }
6893
619c5cb6 6894 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6895 /* clear pf enable */
6896 bnx2x_pf_disable(bp);
6897 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6898 }
6899 }
a2fbb9ea 6900
619c5cb6 6901 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6902 if (CHIP_IS_E1(bp)) {
6903 /* enable HW interrupt from PXP on USDM overflow
6904 bit 16 on INT_MASK_0 */
6905 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6906 }
a2fbb9ea 6907
619c5cb6 6908 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6909 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 6910
6911#ifdef __BIG_ENDIAN
34f80b04
EG		 6912 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6913 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6914 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6915 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6916 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 6917 /* make sure this value is 0 */
6918 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 6919
6920/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6921 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6922 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6923 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6924 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 6925#endif
6926
523224a3
DK		 6927 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6928
34f80b04
EG		 6929 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6930 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6931
34f80b04
EG		 6932 /* let the HW do it's magic ... */
6933 msleep(100);
6934 /* finish PXP init */
6935 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6936 if (val != 1) {
6937 BNX2X_ERR("PXP2 CFG failed\n");
6938 return -EBUSY;
6939 }
6940 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6941 if (val != 1) {
6942 BNX2X_ERR("PXP2 RD_INIT failed\n");
6943 return -EBUSY;
6944 }
a2fbb9ea 6945
f2e0899f
DK		 6946 /* Timers bug workaround E2 only. We need to set the entire ILT to
6947 * have entries with value "0" and valid bit on.
6948 * This needs to be done by the first PF that is loaded in a path
6949 * (i.e. common phase)
6950 */
619c5cb6
VZ		 6951 if (!CHIP_IS_E1x(bp)) {
6952/* In E2 there is a bug in the timers block that can cause function 6 / 7
6953 * (i.e. vnic3) to start even if it is marked as "scan-off".
6954 * This occurs when a different function (func2,3) is being marked
6955 * as "scan-off". Real-life scenario for example: if a driver is being
6956 * load-unloaded while func6,7 are down. This will cause the timer to access
6957 * the ilt, translate to a logical address and send a request to read/write.
6958 * Since the ilt for the function that is down is not valid, this will cause
6959 * a translation error which is unrecoverable.
6960 * The Workaround is intended to make sure that when this happens nothing fatal
6961 * will occur. The workaround:
6962 * 1. First PF driver which loads on a path will:
6963 * a. After taking the chip out of reset, by using pretend,
6964 * it will write "0" to the following registers of
6965 * the other vnics.
6966 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6967 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6968 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6969 * And for itself it will write '1' to
6970 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6971 * dmae-operations (writing to pram for example.)
6972 * note: can be done for only function 6,7 but cleaner this
6973 * way.
6974 * b. Write zero+valid to the entire ILT.
6975 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6976 * VNIC3 (of that port). The range allocated will be the
6977 * entire ILT. This is needed to prevent ILT range error.
6978 * 2. Any PF driver load flow:
6979 * a. ILT update with the physical addresses of the allocated
6980 * logical pages.
6981 * b. Wait 20msec. - note that this timeout is needed to make
6982 * sure there are no requests in one of the PXP internal
6983 * queues with "old" ILT addresses.
6984 * c. PF enable in the PGLC.
6985 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 6986 * occurred while driver was down)
619c5cb6
VZ		 6987 * e. PF enable in the CFC (WEAK + STRONG)
6988 * f. Timers scan enable
6989 * 3. PF driver unload flow:
6990 * a. Clear the Timers scan_en.
6991 * b. Polling for scan_on=0 for that PF.
6992 * c. Clear the PF enable bit in the PXP.
6993 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6994 * e. Write zero+valid to all ILT entries (The valid bit must
6995 * stay set)
6996 * f. If this is VNIC 3 of a port then also init
6997 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 6998 * to the last entry in the ILT.
619c5cb6
VZ		 6999 *
7000 * Notes:
7001 * Currently the PF error in the PGLC is non recoverable.
7002 * In the future the there will be a recovery routine for this error.
7003 * Currently attention is masked.
7004 * Having an MCP lock on the load/unload process does not guarantee that
7005 * there is no Timer disable during Func6/7 enable. This is because the
7006 * Timers scan is currently being cleared by the MCP on FLR.
7007 * Step 2.d can be done only for PF6/7 and the driver can also check if
7008 * there is error before clearing it. But the flow above is simpler and
7009 * more general.
7010 * All ILT entries are written by zero+valid and not just PF6/7
7011 * ILT entries since in the future the ILT entries allocation for
7012 * PF-s might be dynamic.
7013 */
f2e0899f
DK		 7014 struct ilt_client_info ilt_cli;
7015 struct bnx2x_ilt ilt;
7016 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7017 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7018
b595076a 7019 /* initialize dummy TM client */
f2e0899f
DK		 7020 ilt_cli.start = 0;
7021 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7022 ilt_cli.client_num = ILT_CLIENT_TM;
7023
7024 /* Step 1: set zeroes to all ilt page entries with valid bit on
7025 * Step 2: set the timers first/last ilt entry to point
7026 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 7027 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 7028 *
7029 * both steps performed by call to bnx2x_ilt_client_init_op()
7030 * with dummy TM client
7031 *
7032 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7033 * and his brother are split registers
7034 */
7035 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7036 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7037 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7038
7039 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7040 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7041 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7042 }
7043
34f80b04
EG		 7044 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7045 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 7046
619c5cb6 7047 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7048 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7049 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 7050 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 7051
619c5cb6 7052 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 7053
7054 /* let the HW do it's magic ... */
7055 do {
7056 msleep(200);
7057 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7058 } while (factor-- && (val != 1));
7059
7060 if (val != 1) {
7061 BNX2X_ERR("ATC_INIT failed\n");
7062 return -EBUSY;
7063 }
7064 }
7065
619c5cb6 7066 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 7067
b56e9670
AE		 7068 bnx2x_iov_init_dmae(bp);
7069
34f80b04
EG		 7070 /* clean the DMAE memory */
7071 bp->dmae_ready = 1;
619c5cb6
VZ		 7072 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7073
7074 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7075
7076 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7077
7078 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 7079
619c5cb6 7080 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 7081
34f80b04
EG		 7082 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7083 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7084 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7085 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7086
619c5cb6 7087 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 7088
523224a3
DK		 7089 /* QM queues pointers table */
7090 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7091
34f80b04
EG		 7092 /* soft reset pulse */
7093 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7094 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 7095
55c11941
MS		 7096 if (CNIC_SUPPORT(bp))
7097 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 7098
619c5cb6 7099 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 7100
619c5cb6 7101 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7102 /* enable hw interrupt from doorbell Q */
7103 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7104
619c5cb6 7105 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7106
619c5cb6 7107 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7108 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7109
f2e0899f 7110 if (!CHIP_IS_E1(bp))
619c5cb6 7111 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7112
a3348722
BW		 7113 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7114 if (IS_MF_AFEX(bp)) {
7115 /* configure that VNTag and VLAN headers must be
7116 * received in afex mode
7117 */
7118 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7119 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7120 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7121 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7122 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7123 } else {
7124 /* Bit-map indicating which L2 hdrs may appear
7125 * after the basic Ethernet header
7126 */
7127 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7128 bp->path_has_ovlan ? 7 : 6);
7129 }
7130 }
a2fbb9ea 7131
619c5cb6
VZ		 7132 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7133 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7134 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7135 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7136
619c5cb6
VZ		 7137 if (!CHIP_IS_E1x(bp)) {
7138 /* reset VFC memories */
7139 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7140 VFC_MEMORIES_RST_REG_CAM_RST |
7141 VFC_MEMORIES_RST_REG_RAM_RST);
7142 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7143 VFC_MEMORIES_RST_REG_CAM_RST |
7144 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7145
619c5cb6
VZ		 7146 msleep(20);
7147 }
a2fbb9ea 7148
619c5cb6
VZ		 7149 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7150 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7151 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7152 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7153
34f80b04
EG		 7154 /* sync semi rtc */
7155 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7156 0x80000000);
7157 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7158 0x80000000);
a2fbb9ea 7159
619c5cb6
VZ		 7160 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7161 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7162 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7163
a3348722
BW		 7164 if (!CHIP_IS_E1x(bp)) {
7165 if (IS_MF_AFEX(bp)) {
7166 /* configure that VNTag and VLAN headers must be
7167 * sent in afex mode
7168 */
7169 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7170 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7171 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7172 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7173 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7174 } else {
7175 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7176 bp->path_has_ovlan ? 7 : 6);
7177 }
7178 }
f2e0899f 7179
34f80b04 7180 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7181
619c5cb6
VZ		 7182 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7183
55c11941
MS		 7184 if (CNIC_SUPPORT(bp)) {
7185 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7186 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7187 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7188 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7189 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7190 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7191 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7192 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7193 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7194 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7195 }
34f80b04 7196 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7197
34f80b04
EG		 7198 if (sizeof(union cdu_context) != 1024)
7199 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7200 dev_alert(&bp->pdev->dev,
7201 "please adjust the size of cdu_context(%ld)\n",
7202 (long)sizeof(union cdu_context));
a2fbb9ea 7203
619c5cb6 7204 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7205 val = (4 << 24) + (0 << 12) + 1024;
7206 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7207
619c5cb6 7208 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7209 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7210 /* enable context validation interrupt from CFC */
7211 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7212
7213 /* set the thresholds to prevent CFC/CDU race */
7214 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7215
619c5cb6 7216 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7217
619c5cb6 7218 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7219 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7220
619c5cb6
VZ		 7221 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7222 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7223
34f80b04
EG		 7224 /* Reset PCIE errors for debug */
7225 REG_WR(bp, 0x2814, 0xffffffff);
7226 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7227
619c5cb6 7228 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7229 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7230 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7231 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7232 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7233 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7234 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7235 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7236 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7237 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7238 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7239 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7240 }
7241
619c5cb6 7242 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7243 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7244 /* in E3 this done in per-port section */
7245 if (!CHIP_IS_E3(bp))
7246 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7247 }
619c5cb6
VZ		 7248 if (CHIP_IS_E1H(bp))
7249 /* not applicable for E2 (and above ...) */
7250 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7251
7252 if (CHIP_REV_IS_SLOW(bp))
7253 msleep(200);
7254
7255 /* finish CFC init */
7256 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7257 if (val != 1) {
7258 BNX2X_ERR("CFC LL_INIT failed\n");
7259 return -EBUSY;
7260 }
7261 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7262 if (val != 1) {
7263 BNX2X_ERR("CFC AC_INIT failed\n");
7264 return -EBUSY;
7265 }
7266 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7267 if (val != 1) {
7268 BNX2X_ERR("CFC CAM_INIT failed\n");
7269 return -EBUSY;
7270 }
7271 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7272
f2e0899f
DK		 7273 if (CHIP_IS_E1(bp)) {
7274 /* read NIG statistic
7275 to see if this is our first up since powerup */
7276 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7277 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7278
f2e0899f
DK		 7279 /* do internal memory self test */
7280 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7281 BNX2X_ERR("internal mem self test failed\n");
7282 return -EBUSY;
7283 }
34f80b04
EG		 7284 }
7285
fd4ef40d
EG		 7286 bnx2x_setup_fan_failure_detection(bp);
7287
34f80b04
EG		 7288 /* clear PXP2 attentions */
7289 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7290
4a33bc03 7291 bnx2x_enable_blocks_attention(bp);
c9ee9206 7292 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7293
6bbca910 7294 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7295 if (CHIP_IS_E1x(bp))
7296 bnx2x__common_init_phy(bp);
6bbca910
YR		 7297 } else
7298 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7299
34f80b04
EG		 7300 return 0;
7301}
a2fbb9ea 7302
619c5cb6
VZ		 7303/**
7304 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7305 *
7306 * @bp: driver handle
7307 */
7308static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7309{
7310 int rc = bnx2x_init_hw_common(bp);
7311
7312 if (rc)
7313 return rc;
7314
7315 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7316 if (!BP_NOMCP(bp))
7317 bnx2x__common_init_phy(bp);
7318
7319 return 0;
7320}
7321
523224a3 7322static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7323{
7324 int port = BP_PORT(bp);
619c5cb6 7325 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7326 u32 low, high;
4293b9f5 7327 u32 val, reg;
a2fbb9ea 7328
51c1a580 7329 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7330
7331 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7332
619c5cb6
VZ		 7333 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7334 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7335 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7336
f2e0899f
DK		 7337 /* Timers bug workaround: disables the pf_master bit in pglue at
7338 * common phase, we need to enable it here before any dmae access are
7339 * attempted. Therefore we manually added the enable-master to the
7340 * port phase (it also happens in the function phase)
7341 */
619c5cb6 7342 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7343 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7344
619c5cb6
VZ		 7345 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7346 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7347 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7348 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7349
7350 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7351 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7352 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7353 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7354
523224a3
DK		 7355 /* QM cid (connection) count */
7356 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7357
55c11941
MS		 7358 if (CNIC_SUPPORT(bp)) {
7359 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7360 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7361 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7362 }
cdaa7cb8 7363
619c5cb6 7364 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7365
2b674047
DK		 7366 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7367
f2e0899f 7368 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7369
7370 if (IS_MF(bp))
7371 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7372 else if (bp->dev->mtu > 4096) {
7373 if (bp->flags & ONE_PORT_FLAG)
7374 low = 160;
7375 else {
7376 val = bp->dev->mtu;
7377 /* (24*1024 + val*4)/256 */
7378 low = 96 + (val/64) +
7379 ((val % 64) ? 1 : 0);
7380 }
7381 } else
7382 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7383 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7384 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7385 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7386 }
1c06328c 7387
619c5cb6
VZ		 7388 if (CHIP_MODE_IS_4_PORT(bp))
7389 REG_WR(bp, (BP_PORT(bp) ?
7390 BRB1_REG_MAC_GUARANTIED_1 :
7391 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7392
619c5cb6 7393 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7394 if (CHIP_IS_E3B0(bp)) {
7395 if (IS_MF_AFEX(bp)) {
7396 /* configure headers for AFEX mode */
7397 REG_WR(bp, BP_PORT(bp) ?
7398 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7399 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7400 REG_WR(bp, BP_PORT(bp) ?
7401 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7402 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7403 REG_WR(bp, BP_PORT(bp) ?
7404 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7405 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7406 } else {
7407 /* Ovlan exists only if we are in multi-function +
7408 * switch-dependent mode, in switch-independent there
7409 * is no ovlan headers
7410 */
7411 REG_WR(bp, BP_PORT(bp) ?
7412 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7413 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7414 (bp->path_has_ovlan ? 7 : 6));
7415 }
7416 }
356e2385 7417
619c5cb6
VZ		 7418 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7419 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7420 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7421 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7422
619c5cb6
VZ		 7423 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7424 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7425 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7426 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7427
619c5cb6
VZ		 7428 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7429 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7430
619c5cb6
VZ		 7431 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7432
7433 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7434 /* configure PBF to work without PAUSE mtu 9000 */
7435 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7436
f2e0899f
DK		 7437 /* update threshold */
7438 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7439 /* update init credit */
7440 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7441
f2e0899f
DK		 7442 /* probe changes */
7443 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7444 udelay(50);
7445 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7446 }
a2fbb9ea 7447
55c11941
MS		 7448 if (CNIC_SUPPORT(bp))
7449 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7450
619c5cb6
VZ		 7451 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7452 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7453
7454 if (CHIP_IS_E1(bp)) {
7455 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7456 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7457 }
619c5cb6 7458 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7459
619c5cb6 7460 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7461
619c5cb6 7462 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7463 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7464 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7465 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7466 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7467 val = IS_MF(bp) ? 0xF7 : 0x7;
7468 /* Enable DCBX attention for all but E1 */
7469 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7470 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7471
4293b9f5
DK		 7472 /* SCPAD_PARITY should NOT trigger close the gates */
7473 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7474 REG_WR(bp, reg,
7475 REG_RD(bp, reg) &
7476 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7477
7478 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7479 REG_WR(bp, reg,
7480 REG_RD(bp, reg) &
7481 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7482
619c5cb6
VZ		 7483 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7484
7485 if (!CHIP_IS_E1x(bp)) {
7486 /* Bit-map indicating which L2 hdrs may appear after the
7487 * basic Ethernet header
7488 */
a3348722
BW		 7489 if (IS_MF_AFEX(bp))
7490 REG_WR(bp, BP_PORT(bp) ?
7491 NIG_REG_P1_HDRS_AFTER_BASIC :
7492 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7493 else
7494 REG_WR(bp, BP_PORT(bp) ?
7495 NIG_REG_P1_HDRS_AFTER_BASIC :
7496 NIG_REG_P0_HDRS_AFTER_BASIC,
7497 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7498
7499 if (CHIP_IS_E3(bp))
7500 REG_WR(bp, BP_PORT(bp) ?
7501 NIG_REG_LLH1_MF_MODE :
7502 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7503 }
7504 if (!CHIP_IS_E3(bp))
7505 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7506
f2e0899f 7507 if (!CHIP_IS_E1(bp)) {
fb3bff17 7508 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7509 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7510 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7511
619c5cb6 7512 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7513 val = 0;
7514 switch (bp->mf_mode) {
7515 case MULTI_FUNCTION_SD:
7516 val = 1;
7517 break;
7518 case MULTI_FUNCTION_SI:
a3348722 7519 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7520 val = 2;
7521 break;
7522 }
7523
7524 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7525 NIG_REG_LLH0_CLS_TYPE), val);
7526 }
1c06328c
EG		 7527 {
7528 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7529 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7530 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7531 }
34f80b04
EG		 7532 }
7533
619c5cb6
VZ		 7534 /* If SPIO5 is set to generate interrupts, enable it for this port */
7535 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7536 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7537 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7538 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7539 val = REG_RD(bp, reg_addr);
f1410647 7540 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7541 REG_WR(bp, reg_addr, val);
f1410647 7542 }
a2fbb9ea 7543
34f80b04
EG		 7544 return 0;
7545}
7546
34f80b04
EG		 7547static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7548{
7549 int reg;
32d68de1 7550 u32 wb_write[2];
34f80b04 7551
f2e0899f 7552 if (CHIP_IS_E1(bp))
34f80b04 7553 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7554 else
7555 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7556
32d68de1
YM		 7557 wb_write[0] = ONCHIP_ADDR1(addr);
7558 wb_write[1] = ONCHIP_ADDR2(addr);
7559 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7560}
7561
b56e9670 7562void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7563{
7564 u32 data, ctl, cnt = 100;
7565 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7566 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7567 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7568 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7569 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7570 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7571
7572 /* Not supported in BC mode */
7573 if (CHIP_INT_MODE_IS_BC(bp))
7574 return;
7575
7576 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7577 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7578 IGU_REGULAR_CLEANUP_SET |
7579 IGU_REGULAR_BCLEANUP;
7580
7581 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7582 func_encode << IGU_CTRL_REG_FID_SHIFT |
7583 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7584
7585 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7586 data, igu_addr_data);
7587 REG_WR(bp, igu_addr_data, data);
7588 mmiowb();
7589 barrier();
7590 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7591 ctl, igu_addr_ctl);
7592 REG_WR(bp, igu_addr_ctl, ctl);
7593 mmiowb();
7594 barrier();
7595
7596 /* wait for clean up to finish */
7597 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7598 msleep(20);
7599
1191cb83
ED		 7600 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7601 DP(NETIF_MSG_HW,
7602 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7603 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7604 }
7605}
7606
7607static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7608{
619c5cb6 7609 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7610}
7611
1191cb83 7612static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7613{
7614 u32 i, base = FUNC_ILT_BASE(func);
7615 for (i = base; i < base + ILT_PER_FUNC; i++)
7616 bnx2x_ilt_wr(bp, i, 0);
7617}
7618
910cc727 7619static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7620{
7621 int port = BP_PORT(bp);
7622 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7623 /* T1 hash bits value determines the T1 number of entries */
7624 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7625}
7626
7627static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7628{
7629 int rc;
7630 struct bnx2x_func_state_params func_params = {NULL};
7631 struct bnx2x_func_switch_update_params *switch_update_params =
7632 &func_params.params.switch_update;
7633
7634 /* Prepare parameters for function state transitions */
7635 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7636 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7637
7638 func_params.f_obj = &bp->func_obj;
7639 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7640
7641 /* Function parameters */
7642 switch_update_params->suspend = suspend;
7643
7644 rc = bnx2x_func_state_change(bp, &func_params);
7645
7646 return rc;
7647}
7648
910cc727 7649static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7650{
7651 int rc, i, port = BP_PORT(bp);
7652 int vlan_en = 0, mac_en[NUM_MACS];
7653
55c11941
MS		 7654 /* Close input from network */
7655 if (bp->mf_mode == SINGLE_FUNCTION) {
7656 bnx2x_set_rx_filter(&bp->link_params, 0);
7657 } else {
7658 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7659 NIG_REG_LLH0_FUNC_EN);
7660 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7661 NIG_REG_LLH0_FUNC_EN, 0);
7662 for (i = 0; i < NUM_MACS; i++) {
7663 mac_en[i] = REG_RD(bp, port ?
7664 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7665 4 * i) :
7666 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7667 4 * i));
7668 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7669 4 * i) :
7670 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7671 }
7672 }
7673
7674 /* Close BMC to host */
7675 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7676 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7677
7678 /* Suspend Tx switching to the PF. Completion of this ramrod
7679 * further guarantees that all the packets of that PF / child
7680 * VFs in BRB were processed by the Parser, so it is safe to
7681 * change the NIC_MODE register.
7682 */
7683 rc = bnx2x_func_switch_update(bp, 1);
7684 if (rc) {
7685 BNX2X_ERR("Can't suspend tx-switching!\n");
7686 return rc;
7687 }
7688
7689 /* Change NIC_MODE register */
7690 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7691
7692 /* Open input from network */
7693 if (bp->mf_mode == SINGLE_FUNCTION) {
7694 bnx2x_set_rx_filter(&bp->link_params, 1);
7695 } else {
7696 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7697 NIG_REG_LLH0_FUNC_EN, vlan_en);
7698 for (i = 0; i < NUM_MACS; i++) {
7699 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7700 4 * i) :
7701 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7702 mac_en[i]);
7703 }
7704 }
7705
7706 /* Enable BMC to host */
7707 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7708 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7709
7710 /* Resume Tx switching to the PF */
7711 rc = bnx2x_func_switch_update(bp, 0);
7712 if (rc) {
7713 BNX2X_ERR("Can't resume tx-switching!\n");
7714 return rc;
7715 }
7716
7717 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7718 return 0;
7719}
7720
7721int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7722{
7723 int rc;
7724
7725 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7726
7727 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7728 /* Configure searcher as part of function hw init */
55c11941
MS		 7729 bnx2x_init_searcher(bp);
7730
7731 /* Reset NIC mode */
7732 rc = bnx2x_reset_nic_mode(bp);
7733 if (rc)
7734 BNX2X_ERR("Can't change NIC mode!\n");
7735 return rc;
7736 }
7737
7738 return 0;
7739}
7740
523224a3 7741static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7742{
7743 int port = BP_PORT(bp);
7744 int func = BP_FUNC(bp);
619c5cb6 7745 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7746 struct bnx2x_ilt *ilt = BP_ILT(bp);
7747 u16 cdu_ilt_start;
8badd27a 7748 u32 addr, val;
f4a66897 7749 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7750 int i, main_mem_width, rc;
34f80b04 7751
51c1a580 7752 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7753
619c5cb6 7754 /* FLR cleanup - hmmm */
89db4ad8
AE		 7755 if (!CHIP_IS_E1x(bp)) {
7756 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7757 if (rc) {
7758 bnx2x_fw_dump(bp);
89db4ad8 7759 return rc;
04c46736 7760 }
89db4ad8 7761 }
619c5cb6 7762
8badd27a 7763 /* set MSI reconfigure capability */
f2e0899f
DK		 7764 if (bp->common.int_block == INT_BLOCK_HC) {
7765 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7766 val = REG_RD(bp, addr);
7767 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7768 REG_WR(bp, addr, val);
7769 }
8badd27a 7770
619c5cb6
VZ		 7771 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7772 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7773
523224a3
DK		 7774 ilt = BP_ILT(bp);
7775 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7776
290ca2bb
AE		 7777 if (IS_SRIOV(bp))
7778 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7779 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7780
7781 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7782 * those of the VFs, so start line should be reset
7783 */
7784 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7785 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7786 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7787 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7788 bp->context[i].cxt_mapping;
7789 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7790 }
290ca2bb 7791
523224a3 7792 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7793
55c11941
MS		 7794 if (!CONFIGURE_NIC_MODE(bp)) {
7795 bnx2x_init_searcher(bp);
7796 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7797 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7798 } else {
7799 /* Set NIC mode */
7800 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 7801 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 7802 }
37b091ba 7803
619c5cb6 7804 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7805 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7806
7807 /* Turn on a single ISR mode in IGU if driver is going to use
7808 * INT#x or MSI
7809 */
7810 if (!(bp->flags & USING_MSIX_FLAG))
7811 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7812 /*
7813 * Timers workaround bug: function init part.
7814 * Need to wait 20msec after initializing ILT,
7815 * needed to make sure there are no requests in
7816 * one of the PXP internal queues with "old" ILT addresses
7817 */
7818 msleep(20);
7819 /*
7820 * Master enable - Due to WB DMAE writes performed before this
7821 * register is re-initialized as part of the regular function
7822 * init
7823 */
7824 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7825 /* Enable the function in IGU */
7826 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7827 }
7828
523224a3 7829 bp->dmae_ready = 1;
34f80b04 7830
619c5cb6 7831 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 7832
619c5cb6 7833 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7834 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7835
619c5cb6
VZ		 7836 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7837 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7838 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7839 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7840 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7841 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7842 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7843 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7844 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7845 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7846 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7847 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7848 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7849
7850 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7851 REG_WR(bp, QM_REG_PF_EN, 1);
7852
619c5cb6
VZ		 7853 if (!CHIP_IS_E1x(bp)) {
7854 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7855 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7856 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7857 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7858 }
7859 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7860
7861 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7862 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 7863 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 7864
7865 bnx2x_iov_init_dq(bp);
7866
619c5cb6
VZ		 7867 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7868 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7869 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7870 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7871 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7872 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7873 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7874 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7875 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7876 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7877 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7878
619c5cb6 7879 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 7880
619c5cb6 7881 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 7882
619c5cb6 7883 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7884 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7885
fb3bff17 7886 if (IS_MF(bp)) {
34f80b04 7887 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 7888 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 7889 }
7890
619c5cb6 7891 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 7892
34f80b04 7893 /* HC init per function */
f2e0899f
DK		 7894 if (bp->common.int_block == INT_BLOCK_HC) {
7895 if (CHIP_IS_E1H(bp)) {
7896 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7897
7898 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7899 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7900 }
619c5cb6 7901 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 7902
7903 } else {
7904 int num_segs, sb_idx, prod_offset;
7905
34f80b04
EG		 7906 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7907
619c5cb6 7908 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7909 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7910 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7911 }
7912
619c5cb6 7913 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7914
619c5cb6 7915 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7916 int dsb_idx = 0;
7917 /**
7918 * Producer memory:
7919 * E2 mode: address 0-135 match to the mapping memory;
7920 * 136 - PF0 default prod; 137 - PF1 default prod;
7921 * 138 - PF2 default prod; 139 - PF3 default prod;
7922 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7923 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7924 * 144-147 reserved.
7925 *
7926 * E1.5 mode - In backward compatible mode;
7927 * for non default SB; each even line in the memory
7928 * holds the U producer and each odd line hold
7929 * the C producer. The first 128 producers are for
7930 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7931 * producers are for the DSB for each PF.
7932 * Each PF has five segments: (the order inside each
7933 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7934 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7935 * 144-147 attn prods;
7936 */
7937 /* non-default-status-blocks */
7938 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7939 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7940 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7941 prod_offset = (bp->igu_base_sb + sb_idx) *
7942 num_segs;
7943
7944 for (i = 0; i < num_segs; i++) {
7945 addr = IGU_REG_PROD_CONS_MEMORY +
7946 (prod_offset + i) * 4;
7947 REG_WR(bp, addr, 0);
7948 }
7949 /* send consumer update with value 0 */
7950 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7951 USTORM_ID, 0, IGU_INT_NOP, 1);
7952 bnx2x_igu_clear_sb(bp,
7953 bp->igu_base_sb + sb_idx);
7954 }
7955
7956 /* default-status-blocks */
7957 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7958 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7959
7960 if (CHIP_MODE_IS_4_PORT(bp))
7961 dsb_idx = BP_FUNC(bp);
7962 else
3395a033 7963 dsb_idx = BP_VN(bp);
f2e0899f
DK		 7964
7965 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7966 IGU_BC_BASE_DSB_PROD + dsb_idx :
7967 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7968
3395a033
DK		 7969 /*
7970 * igu prods come in chunks of E1HVN_MAX (4) -
7971 * does not matters what is the current chip mode
7972 */
f2e0899f
DK		 7973 for (i = 0; i < (num_segs * E1HVN_MAX);
7974 i += E1HVN_MAX) {
7975 addr = IGU_REG_PROD_CONS_MEMORY +
7976 (prod_offset + i)*4;
7977 REG_WR(bp, addr, 0);
7978 }
7979 /* send consumer update with 0 */
7980 if (CHIP_INT_MODE_IS_BC(bp)) {
7981 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7982 USTORM_ID, 0, IGU_INT_NOP, 1);
7983 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7984 CSTORM_ID, 0, IGU_INT_NOP, 1);
7985 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7986 XSTORM_ID, 0, IGU_INT_NOP, 1);
7987 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7988 TSTORM_ID, 0, IGU_INT_NOP, 1);
7989 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7990 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7991 } else {
7992 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7993 USTORM_ID, 0, IGU_INT_NOP, 1);
7994 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7995 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7996 }
7997 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7998
16a5fd92 7999 /* !!! These should become driver const once
f2e0899f
DK		 8000 rf-tool supports split-68 const */
8001 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8002 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8003 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8004 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8005 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8006 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8007 }
34f80b04 8008 }
34f80b04 8009
c14423fe 8010 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 8011 REG_WR(bp, 0x2114, 0xffffffff);
8012 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 8013
f4a66897
VZ		 8014 if (CHIP_IS_E1x(bp)) {
8015 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8016 main_mem_base = HC_REG_MAIN_MEMORY +
8017 BP_PORT(bp) * (main_mem_size * 4);
8018 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8019 main_mem_width = 8;
8020
8021 val = REG_RD(bp, main_mem_prty_clr);
8022 if (val)
51c1a580
MS		 8023 DP(NETIF_MSG_HW,
8024 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8025 val);
f4a66897
VZ		 8026
8027 /* Clear "false" parity errors in MSI-X table */
8028 for (i = main_mem_base;
8029 i < main_mem_base + main_mem_size * 4;
8030 i += main_mem_width) {
8031 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8032 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8033 i, main_mem_width / 4);
8034 }
8035 /* Clear HC parity attention */
8036 REG_RD(bp, main_mem_prty_clr);
8037 }
8038
619c5cb6
VZ		 8039#ifdef BNX2X_STOP_ON_ERROR
8040 /* Enable STORMs SP logging */
8041 REG_WR8(bp, BAR_USTRORM_INTMEM +
8042 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8043 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8044 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8045 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8046 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8047 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8048 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8049#endif
8050
b7737c9b 8051 bnx2x_phy_probe(&bp->link_params);
f85582f8 8052
34f80b04
EG		 8053 return 0;
8054}
8055
55c11941
MS		 8056void bnx2x_free_mem_cnic(struct bnx2x *bp)
8057{
8058 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8059
8060 if (!CHIP_IS_E1x(bp))
8061 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8062 sizeof(struct host_hc_status_block_e2));
8063 else
8064 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8065 sizeof(struct host_hc_status_block_e1x));
8066
8067 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8068}
8069
9f6c9258 8070void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 8071{
a052997e
MS		 8072 int i;
8073
619c5cb6
VZ		 8074 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8075 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8076
b4cddbd6
AE		 8077 if (IS_VF(bp))
8078 return;
8079
8080 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8081 sizeof(struct host_sp_status_block));
8082
a2fbb9ea 8083 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 8084 sizeof(struct bnx2x_slowpath));
a2fbb9ea 8085
a052997e
MS		 8086 for (i = 0; i < L2_ILT_LINES(bp); i++)
8087 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8088 bp->context[i].size);
523224a3
DK		 8089 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8090
8091 BNX2X_FREE(bp->ilt->lines);
f85582f8 8092
7a9b2557 8093 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 8094
523224a3
DK		 8095 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8096 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 8097
05952246
YM		 8098 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8099
580d9d08 8100 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8101}
8102
55c11941 8103int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8104{
cd2b0389 8105 if (!CHIP_IS_E1x(bp)) {
619c5cb6 8106 /* size = the status block + ramrod buffers */
cd2b0389
JP		 8107 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8108 sizeof(struct host_hc_status_block_e2));
8109 if (!bp->cnic_sb.e2_sb)
8110 goto alloc_mem_err;
8111 } else {
8112 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8113 sizeof(struct host_hc_status_block_e1x));
8114 if (!bp->cnic_sb.e1x_sb)
8115 goto alloc_mem_err;
8116 }
8badd27a 8117
cd2b0389 8118 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
16a5fd92 8119 /* allocate searcher T2 table, as it wasn't allocated before */
cd2b0389
JP		 8120 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8121 if (!bp->t2)
8122 goto alloc_mem_err;
8123 }
55c11941
MS		 8124
8125 /* write address to which L5 should insert its values */
8126 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8127 &bp->slowpath->drv_info_to_mcp;
8128
8129 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8130 goto alloc_mem_err;
8131
8132 return 0;
8133
8134alloc_mem_err:
8135 bnx2x_free_mem_cnic(bp);
8136 BNX2X_ERR("Can't allocate memory\n");
8137 return -ENOMEM;
8138}
8139
8140int bnx2x_alloc_mem(struct bnx2x *bp)
8141{
8142 int i, allocated, context_size;
a2fbb9ea 8143
cd2b0389 8144 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
55c11941 8145 /* allocate searcher T2 table */
cd2b0389
JP		 8146 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8147 if (!bp->t2)
8148 goto alloc_mem_err;
8149 }
8badd27a 8150
cd2b0389
JP		 8151 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8152 sizeof(struct host_sp_status_block));
8153 if (!bp->def_status_blk)
8154 goto alloc_mem_err;
a2fbb9ea 8155
cd2b0389
JP		 8156 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8157 sizeof(struct bnx2x_slowpath));
8158 if (!bp->slowpath)
8159 goto alloc_mem_err;
a2fbb9ea 8160
a052997e
MS		 8161 /* Allocate memory for CDU context:
8162 * This memory is allocated separately and not in the generic ILT
8163 * functions because CDU differs in few aspects:
8164 * 1. There are multiple entities allocating memory for context -
8165 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8166 * its own ILT lines.
8167 * 2. Since CDU page-size is not a single 4KB page (which is the case
8168 * for the other ILT clients), to be efficient we want to support
8169 * allocation of sub-page-size in the last entry.
8170 * 3. Context pointers are used by the driver to pass to FW / update
8171 * the context (for the other ILT clients the pointers are used just to
8172 * free the memory during unload).
8173 */
8174 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8175
a052997e
MS		 8176 for (i = 0, allocated = 0; allocated < context_size; i++) {
8177 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8178 (context_size - allocated));
cd2b0389
JP		 8179 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8180 bp->context[i].size);
8181 if (!bp->context[i].vcxt)
8182 goto alloc_mem_err;
a052997e
MS		 8183 allocated += bp->context[i].size;
8184 }
cd2b0389
JP		 8185 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8186 GFP_KERNEL);
8187 if (!bp->ilt->lines)
8188 goto alloc_mem_err;
65abd74d 8189
523224a3
DK		 8190 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8191 goto alloc_mem_err;
65abd74d 8192
67c431a5
AE		 8193 if (bnx2x_iov_alloc_mem(bp))
8194 goto alloc_mem_err;
8195
9f6c9258 8196 /* Slow path ring */
cd2b0389
JP		 8197 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8198 if (!bp->spq)
8199 goto alloc_mem_err;
65abd74d 8200
523224a3 8201 /* EQ */
cd2b0389
JP		 8202 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8203 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8204 if (!bp->eq_ring)
8205 goto alloc_mem_err;
ab532cf3 8206
9f6c9258 8207 return 0;
e1510706 8208
9f6c9258
DK		 8209alloc_mem_err:
8210 bnx2x_free_mem(bp);
51c1a580 8211 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8212 return -ENOMEM;
65abd74d
YG		 8213}
8214
a2fbb9ea
ET		 8215/*
8216 * Init service functions
8217 */
a2fbb9ea 8218
619c5cb6
VZ		 8219int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8220 struct bnx2x_vlan_mac_obj *obj, bool set,
8221 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8222{
619c5cb6
VZ		 8223 int rc;
8224 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8225
619c5cb6 8226 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8227
619c5cb6
VZ		 8228 /* Fill general parameters */
8229 ramrod_param.vlan_mac_obj = obj;
8230 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8231
619c5cb6
VZ		 8232 /* Fill a user request section if needed */
8233 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8234 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8235
619c5cb6 8236 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8237
619c5cb6
VZ		 8238 /* Set the command: ADD or DEL */
8239 if (set)
8240 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8241 else
8242 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8243 }
8244
619c5cb6 8245 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8246
8247 if (rc == -EEXIST) {
8248 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8249 /* do not treat adding same MAC as error */
8250 rc = 0;
8251 } else if (rc < 0)
619c5cb6 8252 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8253
619c5cb6 8254 return rc;
a2fbb9ea
ET		 8255}
8256
619c5cb6
VZ		 8257int bnx2x_del_all_macs(struct bnx2x *bp,
8258 struct bnx2x_vlan_mac_obj *mac_obj,
8259 int mac_type, bool wait_for_comp)
e665bfda 8260{
619c5cb6
VZ		 8261 int rc;
8262 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8263
619c5cb6
VZ		 8264 /* Wait for completion of requested */
8265 if (wait_for_comp)
8266 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8267
619c5cb6
VZ		 8268 /* Set the mac type of addresses we want to clear */
8269 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8270
619c5cb6
VZ		 8271 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8272 if (rc < 0)
8273 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8274
619c5cb6 8275 return rc;
0793f83f
DK		 8276}
8277
619c5cb6 8278int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8279{
a3348722
BW		 8280 if (is_zero_ether_addr(bp->dev->dev_addr) &&
8281 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
51c1a580
MS		 8282 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8283 "Ignoring Zero MAC for STORAGE SD mode\n");
614c76df
DK		 8284 return 0;
8285 }
614c76df 8286
f8f4f61a
DK		 8287 if (IS_PF(bp)) {
8288 unsigned long ramrod_flags = 0;
0793f83f 8289
f8f4f61a
DK		 8290 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8291 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8292 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8293 &bp->sp_objs->mac_obj, set,
8294 BNX2X_ETH_MAC, &ramrod_flags);
8295 } else { /* vf */
8296 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8297 bp->fp->index, true);
8298 }
e665bfda 8299}
6e30dd4e 8300
619c5cb6 8301int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8302{
60cad4e6
AE		 8303 if (IS_PF(bp))
8304 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8305 else /* VF */
8306 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8307}
a2fbb9ea 8308
d6214d7a 8309/**
e8920674 8310 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8311 *
e8920674 8312 * @bp: driver handle
d6214d7a 8313 *
e8920674 8314 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8315 */
1ab4434c 8316int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8317{
1ab4434c
AE		 8318 int rc = 0;
8319
60cad4e6
AE		 8320 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8321 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8322 return -EINVAL;
60cad4e6 8323 }
1ab4434c 8324
9ee3d37b 8325 switch (int_mode) {
1ab4434c
AE		 8326 case BNX2X_INT_MODE_MSIX:
8327 /* attempt to enable msix */
8328 rc = bnx2x_enable_msix(bp);
8329
8330 /* msix attained */
8331 if (!rc)
8332 return 0;
8333
8334 /* vfs use only msix */
8335 if (rc && IS_VF(bp))
8336 return rc;
8337
8338 /* failed to enable multiple MSI-X */
8339 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8340 bp->num_queues,
8341 1 + bp->num_cnic_queues);
8342
8343 /* falling through... */
8344 case BNX2X_INT_MODE_MSI:
d6214d7a 8345 bnx2x_enable_msi(bp);
1ab4434c 8346
d6214d7a 8347 /* falling through... */
1ab4434c 8348 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8349 bp->num_ethernet_queues = 1;
8350 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8351 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8352 break;
d6214d7a 8353 default:
1ab4434c
AE		 8354 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8355 return -EINVAL;
9f6c9258 8356 }
1ab4434c 8357 return 0;
a2fbb9ea
ET		 8358}
8359
1ab4434c 8360/* must be called prior to any HW initializations */
c2bff63f
DK		 8361static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8362{
290ca2bb
AE		 8363 if (IS_SRIOV(bp))
8364 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8365 return L2_ILT_LINES(bp);
8366}
8367
523224a3
DK		 8368void bnx2x_ilt_set_info(struct bnx2x *bp)
8369{
8370 struct ilt_client_info *ilt_client;
8371 struct bnx2x_ilt *ilt = BP_ILT(bp);
8372 u16 line = 0;
8373
8374 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8375 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8376
8377 /* CDU */
8378 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8379 ilt_client->client_num = ILT_CLIENT_CDU;
8380 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8381 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8382 ilt_client->start = line;
619c5cb6 8383 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8384
8385 if (CNIC_SUPPORT(bp))
8386 line += CNIC_ILT_LINES;
523224a3
DK		 8387 ilt_client->end = line - 1;
8388
51c1a580 8389 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8390 ilt_client->start,
8391 ilt_client->end,
8392 ilt_client->page_size,
8393 ilt_client->flags,
8394 ilog2(ilt_client->page_size >> 12));
8395
8396 /* QM */
8397 if (QM_INIT(bp->qm_cid_count)) {
8398 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8399 ilt_client->client_num = ILT_CLIENT_QM;
8400 ilt_client->page_size = QM_ILT_PAGE_SZ;
8401 ilt_client->flags = 0;
8402 ilt_client->start = line;
8403
8404 /* 4 bytes for each cid */
8405 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8406 QM_ILT_PAGE_SZ);
8407
8408 ilt_client->end = line - 1;
8409
51c1a580
MS		 8410 DP(NETIF_MSG_IFUP,
8411 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8412 ilt_client->start,
8413 ilt_client->end,
8414 ilt_client->page_size,
8415 ilt_client->flags,
8416 ilog2(ilt_client->page_size >> 12));
523224a3 8417 }
523224a3 8418
55c11941
MS		 8419 if (CNIC_SUPPORT(bp)) {
8420 /* SRC */
8421 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8422 ilt_client->client_num = ILT_CLIENT_SRC;
8423 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8424 ilt_client->flags = 0;
8425 ilt_client->start = line;
8426 line += SRC_ILT_LINES;
8427 ilt_client->end = line - 1;
523224a3 8428
55c11941
MS		 8429 DP(NETIF_MSG_IFUP,
8430 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8431 ilt_client->start,
8432 ilt_client->end,
8433 ilt_client->page_size,
8434 ilt_client->flags,
8435 ilog2(ilt_client->page_size >> 12));
9f6c9258 8436
55c11941
MS		 8437 /* TM */
8438 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8439 ilt_client->client_num = ILT_CLIENT_TM;
8440 ilt_client->page_size = TM_ILT_PAGE_SZ;
8441 ilt_client->flags = 0;
8442 ilt_client->start = line;
8443 line += TM_ILT_LINES;
8444 ilt_client->end = line - 1;
523224a3 8445
55c11941
MS		 8446 DP(NETIF_MSG_IFUP,
8447 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8448 ilt_client->start,
8449 ilt_client->end,
8450 ilt_client->page_size,
8451 ilt_client->flags,
8452 ilog2(ilt_client->page_size >> 12));
8453 }
9f6c9258 8454
619c5cb6 8455 BUG_ON(line > ILT_MAX_LINES);
523224a3 8456}
f85582f8 8457
619c5cb6
VZ		 8458/**
8459 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8460 *
8461 * @bp: driver handle
8462 * @fp: pointer to fastpath
8463 * @init_params: pointer to parameters structure
8464 *
8465 * parameters configured:
8466 * - HC configuration
8467 * - Queue's CDU context
8468 */
1191cb83 8469static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8470 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8471{
6383c0b3 8472 u8 cos;
a052997e
MS		 8473 int cxt_index, cxt_offset;
8474
619c5cb6
VZ		 8475 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8476 if (!IS_FCOE_FP(fp)) {
8477 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8478 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8479
16a5fd92 8480 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8481 * to INIT state.
8482 */
8483 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8484 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8485
8486 /* HC rate */
8487 init_params->rx.hc_rate = bp->rx_ticks ?
8488 (1000000 / bp->rx_ticks) : 0;
8489 init_params->tx.hc_rate = bp->tx_ticks ?
8490 (1000000 / bp->tx_ticks) : 0;
8491
8492 /* FW SB ID */
8493 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8494 fp->fw_sb_id;
8495
8496 /*
8497 * CQ index among the SB indices: FCoE clients uses the default
8498 * SB, therefore it's different.
8499 */
6383c0b3
AE		 8500 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8501 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8502 }
8503
6383c0b3
AE		 8504 /* set maximum number of COSs supported by this queue */
8505 init_params->max_cos = fp->max_cos;
8506
51c1a580 8507 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8508 fp->index, init_params->max_cos);
8509
8510 /* set the context pointers queue object */
a052997e 8511 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8512 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8513 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8514 ILT_PAGE_CIDS);
6383c0b3 8515 init_params->cxts[cos] =
a052997e
MS		 8516 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8517 }
619c5cb6
VZ		 8518}
8519
910cc727 8520static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8521 struct bnx2x_queue_state_params *q_params,
8522 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8523 int tx_index, bool leading)
8524{
8525 memset(tx_only_params, 0, sizeof(*tx_only_params));
8526
8527 /* Set the command */
8528 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8529
8530 /* Set tx-only QUEUE flags: don't zero statistics */
8531 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8532
8533 /* choose the index of the cid to send the slow path on */
8534 tx_only_params->cid_index = tx_index;
8535
8536 /* Set general TX_ONLY_SETUP parameters */
8537 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8538
8539 /* Set Tx TX_ONLY_SETUP parameters */
8540 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8541
51c1a580
MS		 8542 DP(NETIF_MSG_IFUP,
8543 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8544 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8545 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8546 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8547
8548 /* send the ramrod */
8549 return bnx2x_queue_state_change(bp, q_params);
8550}
8551
619c5cb6
VZ		 8552/**
8553 * bnx2x_setup_queue - setup queue
8554 *
8555 * @bp: driver handle
8556 * @fp: pointer to fastpath
8557 * @leading: is leading
8558 *
8559 * This function performs 2 steps in a Queue state machine
8560 * actually: 1) RESET->INIT 2) INIT->SETUP
8561 */
8562
8563int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8564 bool leading)
8565{
3b603066 8566 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8567 struct bnx2x_queue_setup_params *setup_params =
8568 &q_params.params.setup;
6383c0b3
AE		 8569 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8570 &q_params.params.tx_only;
a2fbb9ea 8571 int rc;
6383c0b3
AE		 8572 u8 tx_index;
8573
51c1a580 8574 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8575
ec6ba945
VZ		 8576 /* reset IGU state skip FCoE L2 queue */
8577 if (!IS_FCOE_FP(fp))
8578 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8579 IGU_INT_ENABLE, 0);
a2fbb9ea 8580
15192a8c 8581 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8582 /* We want to wait for completion in this context */
8583 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8584
619c5cb6
VZ		 8585 /* Prepare the INIT parameters */
8586 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8587
619c5cb6
VZ		 8588 /* Set the command */
8589 q_params.cmd = BNX2X_Q_CMD_INIT;
8590
8591 /* Change the state to INIT */
8592 rc = bnx2x_queue_state_change(bp, &q_params);
8593 if (rc) {
6383c0b3 8594 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8595 return rc;
8596 }
ec6ba945 8597
51c1a580 8598 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8599
619c5cb6
VZ		 8600 /* Now move the Queue to the SETUP state... */
8601 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8602
619c5cb6
VZ		 8603 /* Set QUEUE flags */
8604 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8605
619c5cb6 8606 /* Set general SETUP parameters */
6383c0b3
AE		 8607 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8608 FIRST_TX_COS_INDEX);
619c5cb6 8609
6383c0b3 8610 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8611 &setup_params->rxq_params);
8612
6383c0b3
AE		 8613 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8614 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8615
8616 /* Set the command */
8617 q_params.cmd = BNX2X_Q_CMD_SETUP;
8618
55c11941
MS		 8619 if (IS_FCOE_FP(fp))
8620 bp->fcoe_init = true;
8621
619c5cb6
VZ		 8622 /* Change the state to SETUP */
8623 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8624 if (rc) {
8625 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8626 return rc;
8627 }
8628
8629 /* loop through the relevant tx-only indices */
8630 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8631 tx_index < fp->max_cos;
8632 tx_index++) {
8633
8634 /* prepare and send tx-only ramrod*/
8635 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8636 tx_only_params, tx_index, leading);
8637 if (rc) {
8638 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8639 fp->index, tx_index);
8640 return rc;
8641 }
8642 }
523224a3 8643
34f80b04 8644 return rc;
a2fbb9ea
ET		 8645}
8646
619c5cb6 8647static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8648{
619c5cb6 8649 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8650 struct bnx2x_fp_txdata *txdata;
3b603066 8651 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8652 int rc, tx_index;
8653
51c1a580 8654 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8655
15192a8c 8656 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8657 /* We want to wait for completion in this context */
8658 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8659
6383c0b3
AE		 8660 /* close tx-only connections */
8661 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8662 tx_index < fp->max_cos;
8663 tx_index++){
8664
8665 /* ascertain this is a normal queue*/
65565884 8666 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8667
51c1a580 8668 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8669 txdata->txq_index);
8670
8671 /* send halt terminate on tx-only connection */
8672 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8673 memset(&q_params.params.terminate, 0,
8674 sizeof(q_params.params.terminate));
8675 q_params.params.terminate.cid_index = tx_index;
8676
8677 rc = bnx2x_queue_state_change(bp, &q_params);
8678 if (rc)
8679 return rc;
8680
8681 /* send halt terminate on tx-only connection */
8682 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8683 memset(&q_params.params.cfc_del, 0,
8684 sizeof(q_params.params.cfc_del));
8685 q_params.params.cfc_del.cid_index = tx_index;
8686 rc = bnx2x_queue_state_change(bp, &q_params);
8687 if (rc)
8688 return rc;
8689 }
8690 /* Stop the primary connection: */
8691 /* ...halt the connection */
619c5cb6
VZ		 8692 q_params.cmd = BNX2X_Q_CMD_HALT;
8693 rc = bnx2x_queue_state_change(bp, &q_params);
8694 if (rc)
da5a662a 8695 return rc;
a2fbb9ea 8696
6383c0b3 8697 /* ...terminate the connection */
619c5cb6 8698 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8699 memset(&q_params.params.terminate, 0,
8700 sizeof(q_params.params.terminate));
8701 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8702 rc = bnx2x_queue_state_change(bp, &q_params);
8703 if (rc)
523224a3 8704 return rc;
6383c0b3 8705 /* ...delete cfc entry */
619c5cb6 8706 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8707 memset(&q_params.params.cfc_del, 0,
8708 sizeof(q_params.params.cfc_del));
8709 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8710 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8711}
8712
34f80b04
EG		 8713static void bnx2x_reset_func(struct bnx2x *bp)
8714{
8715 int port = BP_PORT(bp);
8716 int func = BP_FUNC(bp);
f2e0899f 8717 int i;
523224a3
DK		 8718
8719 /* Disable the function in the FW */
8720 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8721 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8722 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8723 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8724
8725 /* FP SBs */
ec6ba945 8726 for_each_eth_queue(bp, i) {
523224a3 8727 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8728 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8729 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8730 SB_DISABLED);
523224a3
DK		 8731 }
8732
55c11941
MS		 8733 if (CNIC_LOADED(bp))
8734 /* CNIC SB */
8735 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8736 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8737 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8738
523224a3 8739 /* SP SB */
619c5cb6 8740 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8741 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8742 SB_DISABLED);
523224a3
DK		 8743
8744 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8745 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8746 0);
34f80b04
EG		 8747
8748 /* Configure IGU */
f2e0899f
DK		 8749 if (bp->common.int_block == INT_BLOCK_HC) {
8750 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8751 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8752 } else {
8753 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8754 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8755 }
34f80b04 8756
55c11941
MS		 8757 if (CNIC_LOADED(bp)) {
8758 /* Disable Timer scan */
8759 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8760 /*
8761 * Wait for at least 10ms and up to 2 second for the timers
8762 * scan to complete
8763 */
8764 for (i = 0; i < 200; i++) {
639d65b8 8765 usleep_range(10000, 20000);
55c11941
MS		 8766 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8767 break;
8768 }
37b091ba 8769 }
34f80b04 8770 /* Clear ILT */
f2e0899f
DK		 8771 bnx2x_clear_func_ilt(bp, func);
8772
8773 /* Timers workaround bug for E2: if this is vnic-3,
8774 * we need to set the entire ilt range for this timers.
8775 */
619c5cb6 8776 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8777 struct ilt_client_info ilt_cli;
8778 /* use dummy TM client */
8779 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8780 ilt_cli.start = 0;
8781 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8782 ilt_cli.client_num = ILT_CLIENT_TM;
8783
8784 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8785 }
8786
8787 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 8788 if (!CHIP_IS_E1x(bp))
f2e0899f 8789 bnx2x_pf_disable(bp);
523224a3
DK		 8790
8791 bp->dmae_ready = 0;
34f80b04
EG		 8792}
8793
8794static void bnx2x_reset_port(struct bnx2x *bp)
8795{
8796 int port = BP_PORT(bp);
8797 u32 val;
8798
619c5cb6
VZ		 8799 /* Reset physical Link */
8800 bnx2x__link_reset(bp);
8801
34f80b04
EG		 8802 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8803
8804 /* Do not rcv packets to BRB */
8805 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8806 /* Do not direct rcv packets that are not for MCP to the BRB */
8807 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8808 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8809
8810 /* Configure AEU */
8811 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8812
8813 msleep(100);
8814 /* Check for BRB port occupancy */
8815 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8816 if (val)
8817 DP(NETIF_MSG_IFDOWN,
33471629 8818 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 8819
8820 /* TODO: Close Doorbell port? */
8821}
8822
1191cb83 8823static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 8824{
3b603066 8825 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 8826
619c5cb6
VZ		 8827 /* Prepare parameters for function state transitions */
8828 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 8829
619c5cb6
VZ		 8830 func_params.f_obj = &bp->func_obj;
8831 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 8832
619c5cb6 8833 func_params.params.hw_init.load_phase = load_code;
49d66772 8834
619c5cb6 8835 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 8836}
8837
1191cb83 8838static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 8839{
3b603066 8840 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 8841 int rc;
228241eb 8842
619c5cb6
VZ		 8843 /* Prepare parameters for function state transitions */
8844 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8845 func_params.f_obj = &bp->func_obj;
8846 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 8847
619c5cb6
VZ		 8848 /*
8849 * Try to stop the function the 'good way'. If fails (in case
8850 * of a parity error during bnx2x_chip_cleanup()) and we are
8851 * not in a debug mode, perform a state transaction in order to
8852 * enable further HW_RESET transaction.
8853 */
8854 rc = bnx2x_func_state_change(bp, &func_params);
8855 if (rc) {
34f80b04 8856#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 8857 return rc;
34f80b04 8858#else
51c1a580 8859 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 8860 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8861 return bnx2x_func_state_change(bp, &func_params);
34f80b04 8862#endif
228241eb 8863 }
a2fbb9ea 8864
619c5cb6
VZ		 8865 return 0;
8866}
523224a3 8867
619c5cb6
VZ		 8868/**
8869 * bnx2x_send_unload_req - request unload mode from the MCP.
8870 *
8871 * @bp: driver handle
8872 * @unload_mode: requested function's unload mode
8873 *
8874 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8875 */
8876u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8877{
8878 u32 reset_code = 0;
8879 int port = BP_PORT(bp);
3101c2bc 8880
619c5cb6 8881 /* Select the UNLOAD request mode */
65abd74d
YG		 8882 if (unload_mode == UNLOAD_NORMAL)
8883 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8884
7d0446c2 8885 else if (bp->flags & NO_WOL_FLAG)
65abd74d 8886 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 8887
7d0446c2 8888 else if (bp->wol) {
65abd74d
YG		 8889 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8890 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 8891 struct pci_dev *pdev = bp->pdev;
65abd74d 8892 u32 val;
f9977903
DK		 8893 u16 pmc;
8894
65abd74d 8895 /* The mac address is written to entries 1-4 to
f9977903
DK		 8896 * preserve entry 0 which is used by the PMF
8897 */
3395a033 8898 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 8899
8900 val = (mac_addr[0] << 8) | mac_addr[1];
8901 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8902
8903 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8904 (mac_addr[4] << 8) | mac_addr[5];
8905 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8906
f9977903 8907 /* Enable the PME and clear the status */
29ed74c3 8908 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 8909 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 8910 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 8911
65abd74d
YG		 8912 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8913
8914 } else
8915 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 8916
619c5cb6
VZ		 8917 /* Send the request to the MCP */
8918 if (!BP_NOMCP(bp))
8919 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8920 else {
8921 int path = BP_PATH(bp);
8922
51c1a580 8923 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 8924 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8925 bnx2x_load_count[path][2]);
8926 bnx2x_load_count[path][0]--;
8927 bnx2x_load_count[path][1 + port]--;
51c1a580 8928 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 8929 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8930 bnx2x_load_count[path][2]);
8931 if (bnx2x_load_count[path][0] == 0)
619c5cb6 8932 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 8933 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 8934 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8935 else
8936 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8937 }
8938
8939 return reset_code;
8940}
8941
8942/**
8943 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8944 *
8945 * @bp: driver handle
5d07d868 8946 * @keep_link: true iff link should be kept up
619c5cb6 8947 */
5d07d868 8948void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 8949{
5d07d868
YM		 8950 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8951
619c5cb6
VZ		 8952 /* Report UNLOAD_DONE to MCP */
8953 if (!BP_NOMCP(bp))
5d07d868 8954 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 8955}
8956
1191cb83 8957static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 8958{
8959 int tout = 50;
8960 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8961
8962 if (!bp->port.pmf)
8963 return 0;
8964
8965 /*
8966 * (assumption: No Attention from MCP at this stage)
16a5fd92 8967 * PMF probably in the middle of TX disable/enable transaction
6debea87 8968 * 1. Sync IRS for default SB
16a5fd92
YM		 8969 * 2. Sync SP queue - this guarantees us that attention handling started
8970 * 3. Wait, that TX disable/enable transaction completes
6debea87 8971 *
16a5fd92
YM		 8972 * 1+2 guarantee that if DCBx attention was scheduled it already changed
8973 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8974 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 8975 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8976 * transaction.
8977 */
8978
8979 /* make sure default SB ISR is done */
8980 if (msix)
8981 synchronize_irq(bp->msix_table[0].vector);
8982 else
8983 synchronize_irq(bp->pdev->irq);
8984
8985 flush_workqueue(bnx2x_wq);
370d4a26 8986 flush_workqueue(bnx2x_iov_wq);
6debea87
DK		 8987
8988 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8989 BNX2X_F_STATE_STARTED && tout--)
8990 msleep(20);
8991
8992 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8993 BNX2X_F_STATE_STARTED) {
8994#ifdef BNX2X_STOP_ON_ERROR
51c1a580 8995 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 8996 return -EBUSY;
8997#else
8998 /*
8999 * Failed to complete the transaction in a "good way"
9000 * Force both transactions with CLR bit
9001 */
3b603066 9002 struct bnx2x_func_state_params func_params = {NULL};
6debea87 9003
51c1a580 9004 DP(NETIF_MSG_IFDOWN,
6bf07b8e 9005 "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
6debea87
DK		 9006
9007 func_params.f_obj = &bp->func_obj;
9008 __set_bit(RAMROD_DRV_CLR_ONLY,
9009 &func_params.ramrod_flags);
9010
9011 /* STARTED-->TX_ST0PPED */
9012 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9013 bnx2x_func_state_change(bp, &func_params);
9014
9015 /* TX_ST0PPED-->STARTED */
9016 func_params.cmd = BNX2X_F_CMD_TX_START;
9017 return bnx2x_func_state_change(bp, &func_params);
9018#endif
9019 }
9020
9021 return 0;
9022}
9023
5d07d868 9024void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 9025{
9026 int port = BP_PORT(bp);
6383c0b3
AE		 9027 int i, rc = 0;
9028 u8 cos;
3b603066 9029 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 9030 u32 reset_code;
9031
9032 /* Wait until tx fastpath tasks complete */
9033 for_each_tx_queue(bp, i) {
9034 struct bnx2x_fastpath *fp = &bp->fp[i];
9035
6383c0b3 9036 for_each_cos_in_tx_queue(fp, cos)
65565884 9037 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 9038#ifdef BNX2X_STOP_ON_ERROR
9039 if (rc)
9040 return;
9041#endif
9042 }
9043
9044 /* Give HW time to discard old tx messages */
0926d499 9045 usleep_range(1000, 2000);
619c5cb6
VZ		 9046
9047 /* Clean all ETH MACs */
15192a8c
BW		 9048 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9049 false);
619c5cb6
VZ		 9050 if (rc < 0)
9051 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9052
9053 /* Clean up UC list */
15192a8c 9054 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 9055 true);
9056 if (rc < 0)
51c1a580
MS		 9057 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9058 rc);
619c5cb6
VZ		 9059
9060 /* Disable LLH */
9061 if (!CHIP_IS_E1(bp))
9062 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9063
9064 /* Set "drop all" (stop Rx).
9065 * We need to take a netif_addr_lock() here in order to prevent
9066 * a race between the completion code and this code.
9067 */
9068 netif_addr_lock_bh(bp->dev);
9069 /* Schedule the rx_mode command */
9070 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9071 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9072 else
9073 bnx2x_set_storm_rx_mode(bp);
9074
9075 /* Cleanup multicast configuration */
9076 rparam.mcast_obj = &bp->mcast_obj;
9077 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9078 if (rc < 0)
9079 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9080
9081 netif_addr_unlock_bh(bp->dev);
9082
f1929b01 9083 bnx2x_iov_chip_cleanup(bp);
619c5cb6 9084
6debea87
DK		 9085 /*
9086 * Send the UNLOAD_REQUEST to the MCP. This will return if
9087 * this function should perform FUNC, PORT or COMMON HW
9088 * reset.
9089 */
9090 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9091
9092 /*
9093 * (assumption: No Attention from MCP at this stage)
16a5fd92 9094 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 9095 */
9096 rc = bnx2x_func_wait_started(bp);
9097 if (rc) {
9098 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9099#ifdef BNX2X_STOP_ON_ERROR
9100 return;
9101#endif
9102 }
9103
34f80b04 9104 /* Close multi and leading connections
619c5cb6
VZ		 9105 * Completions for ramrods are collected in a synchronous way
9106 */
55c11941 9107 for_each_eth_queue(bp, i)
619c5cb6 9108 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 9109#ifdef BNX2X_STOP_ON_ERROR
9110 return;
9111#else
228241eb 9112 goto unload_error;
523224a3 9113#endif
55c11941
MS		 9114
9115 if (CNIC_LOADED(bp)) {
9116 for_each_cnic_queue(bp, i)
9117 if (bnx2x_stop_queue(bp, i))
9118#ifdef BNX2X_STOP_ON_ERROR
9119 return;
9120#else
9121 goto unload_error;
9122#endif
9123 }
9124
619c5cb6
VZ		 9125 /* If SP settings didn't get completed so far - something
9126 * very wrong has happen.
9127 */
9128 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9129 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9130
619c5cb6
VZ		 9131#ifndef BNX2X_STOP_ON_ERROR
9132unload_error:
9133#endif
523224a3 9134 rc = bnx2x_func_stop(bp);
da5a662a 9135 if (rc) {
523224a3 9136 BNX2X_ERR("Function stop failed!\n");
da5a662a 9137#ifdef BNX2X_STOP_ON_ERROR
523224a3 9138 return;
523224a3 9139#endif
34f80b04 9140 }
a2fbb9ea 9141
523224a3
DK		 9142 /* Disable HW interrupts, NAPI */
9143 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9144 /* Delete all NAPI objects */
9145 bnx2x_del_all_napi(bp);
55c11941
MS		 9146 if (CNIC_LOADED(bp))
9147 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9148
9149 /* Release IRQs */
d6214d7a 9150 bnx2x_free_irq(bp);
523224a3 9151
a2fbb9ea 9152 /* Reset the chip */
619c5cb6
VZ		 9153 rc = bnx2x_reset_hw(bp, reset_code);
9154 if (rc)
9155 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 9156
619c5cb6 9157 /* Report UNLOAD_DONE to MCP */
5d07d868 9158 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9159}
9160
9f6c9258 9161void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9162{
9163 u32 val;
9164
51c1a580 9165 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9166
9167 if (CHIP_IS_E1(bp)) {
9168 int port = BP_PORT(bp);
9169 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9170 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9171
9172 val = REG_RD(bp, addr);
9173 val &= ~(0x300);
9174 REG_WR(bp, addr, val);
619c5cb6 9175 } else {
72fd0718
VZ		 9176 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9177 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9178 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9179 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9180 }
9181}
9182
72fd0718
VZ		 9183/* Close gates #2, #3 and #4: */
9184static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9185{
c9ee9206 9186 u32 val;
72fd0718
VZ		 9187
9188 /* Gates #2 and #4a are closed/opened for "not E1" only */
9189 if (!CHIP_IS_E1(bp)) {
9190 /* #4 */
c9ee9206 9191 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9192 /* #2 */
c9ee9206 9193 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9194 }
9195
9196 /* #3 */
c9ee9206
VZ		 9197 if (CHIP_IS_E1x(bp)) {
9198 /* Prevent interrupts from HC on both ports */
9199 val = REG_RD(bp, HC_REG_CONFIG_1);
9200 REG_WR(bp, HC_REG_CONFIG_1,
9201 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9202 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9203
9204 val = REG_RD(bp, HC_REG_CONFIG_0);
9205 REG_WR(bp, HC_REG_CONFIG_0,
9206 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9207 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9208 } else {
d82603c6 9209 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9210 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9211
9212 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9213 (!close) ?
9214 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9215 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9216 }
72fd0718 9217
51c1a580 9218 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9219 close ? "closing" : "opening");
9220 mmiowb();
9221}
9222
9223#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9224
9225static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9226{
9227 /* Do some magic... */
9228 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9229 *magic_val = val & SHARED_MF_CLP_MAGIC;
9230 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9231}
9232
e8920674
DK		 9233/**
9234 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9235 *
e8920674
DK		 9236 * @bp: driver handle
9237 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9238 */
9239static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9240{
9241 /* Restore the `magic' bit value... */
72fd0718
VZ		 9242 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9243 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9244 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9245}
9246
f85582f8 9247/**
e8920674 9248 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9249 *
e8920674
DK		 9250 * @bp: driver handle
9251 * @magic_val: old value of 'magic' bit.
9252 *
9253 * Takes care of CLP configurations.
72fd0718
VZ		 9254 */
9255static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9256{
9257 u32 shmem;
9258 u32 validity_offset;
9259
51c1a580 9260 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9261
9262 /* Set `magic' bit in order to save MF config */
9263 if (!CHIP_IS_E1(bp))
9264 bnx2x_clp_reset_prep(bp, magic_val);
9265
9266 /* Get shmem offset */
9267 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9268 validity_offset =
9269 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9270
9271 /* Clear validity map flags */
9272 if (shmem > 0)
9273 REG_WR(bp, shmem + validity_offset, 0);
9274}
9275
9276#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9277#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9278
e8920674
DK		 9279/**
9280 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9281 *
e8920674 9282 * @bp: driver handle
72fd0718 9283 */
1191cb83 9284static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9285{
9286 /* special handling for emulation and FPGA,
9287 wait 10 times longer */
9288 if (CHIP_REV_IS_SLOW(bp))
9289 msleep(MCP_ONE_TIMEOUT*10);
9290 else
9291 msleep(MCP_ONE_TIMEOUT);
9292}
9293
1b6e2ceb
DK		 9294/*
9295 * initializes bp->common.shmem_base and waits for validity signature to appear
9296 */
9297static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9298{
1b6e2ceb
DK		 9299 int cnt = 0;
9300 u32 val = 0;
72fd0718 9301
1b6e2ceb
DK		 9302 do {
9303 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9304 if (bp->common.shmem_base) {
9305 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9306 if (val & SHR_MEM_VALIDITY_MB)
9307 return 0;
9308 }
72fd0718 9309
1b6e2ceb 9310 bnx2x_mcp_wait_one(bp);
72fd0718 9311
1b6e2ceb 9312 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9313
1b6e2ceb 9314 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9315
1b6e2ceb
DK		 9316 return -ENODEV;
9317}
72fd0718 9318
1b6e2ceb
DK		 9319static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9320{
9321 int rc = bnx2x_init_shmem(bp);
72fd0718 9322
72fd0718
VZ		 9323 /* Restore the `magic' bit value */
9324 if (!CHIP_IS_E1(bp))
9325 bnx2x_clp_reset_done(bp, magic_val);
9326
9327 return rc;
9328}
9329
9330static void bnx2x_pxp_prep(struct bnx2x *bp)
9331{
9332 if (!CHIP_IS_E1(bp)) {
9333 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9334 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9335 mmiowb();
9336 }
9337}
9338
9339/*
9340 * Reset the whole chip except for:
9341 * - PCIE core
9342 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9343 * one reset bit)
9344 * - IGU
9345 * - MISC (including AEU)
9346 * - GRC
9347 * - RBCN, RBCP
9348 */
c9ee9206 9349static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9350{
9351 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9352 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9353
9354 /*
9355 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9356 * (per chip) blocks.
9357 */
9358 global_bits2 =
9359 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9360 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9361
c55e771b
BW		 9362 /* Don't reset the following blocks.
9363 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9364 * reset, as in 4 port device they might still be owned
9365 * by the MCP (there is only one leader per path).
9366 */
72fd0718
VZ		 9367 not_reset_mask1 =
9368 MISC_REGISTERS_RESET_REG_1_RST_HC |
9369 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9370 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9371
9372 not_reset_mask2 =
c9ee9206 9373 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9374 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9375 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9376 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9377 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9378 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9379 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9380 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9381 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9382 MISC_REGISTERS_RESET_REG_2_PGLC |
9383 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9384 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9385 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9386 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9387 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9388 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9389
8736c826
VZ		 9390 /*
9391 * Keep the following blocks in reset:
9392 * - all xxMACs are handled by the bnx2x_link code.
9393 */
9394 stay_reset2 =
8736c826
VZ		 9395 MISC_REGISTERS_RESET_REG_2_XMAC |
9396 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9397
9398 /* Full reset masks according to the chip */
72fd0718
VZ		 9399 reset_mask1 = 0xffffffff;
9400
9401 if (CHIP_IS_E1(bp))
9402 reset_mask2 = 0xffff;
8736c826 9403 else if (CHIP_IS_E1H(bp))
72fd0718 9404 reset_mask2 = 0x1ffff;
8736c826
VZ		 9405 else if (CHIP_IS_E2(bp))
9406 reset_mask2 = 0xfffff;
9407 else /* CHIP_IS_E3 */
9408 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9409
9410 /* Don't reset global blocks unless we need to */
9411 if (!global)
9412 reset_mask2 &= ~global_bits2;
9413
9414 /*
9415 * In case of attention in the QM, we need to reset PXP
9416 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9417 * because otherwise QM reset would release 'close the gates' shortly
9418 * before resetting the PXP, then the PSWRQ would send a write
9419 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9420 * read the payload data from PSWWR, but PSWWR would not
9421 * respond. The write queue in PGLUE would stuck, dmae commands
9422 * would not return. Therefore it's important to reset the second
9423 * reset register (containing the
9424 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9425 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9426 * bit).
9427 */
72fd0718
VZ		 9428 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9429 reset_mask2 & (~not_reset_mask2));
9430
c9ee9206
VZ		 9431 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9432 reset_mask1 & (~not_reset_mask1));
9433
72fd0718
VZ		 9434 barrier();
9435 mmiowb();
9436
8736c826
VZ		 9437 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9438 reset_mask2 & (~stay_reset2));
9439
9440 barrier();
9441 mmiowb();
9442
c9ee9206 9443 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9444 mmiowb();
9445}
9446
c9ee9206
VZ		 9447/**
9448 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9449 * It should get cleared in no more than 1s.
9450 *
9451 * @bp: driver handle
9452 *
9453 * It should get cleared in no more than 1s. Returns 0 if
9454 * pending writes bit gets cleared.
9455 */
9456static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9457{
9458 u32 cnt = 1000;
9459 u32 pend_bits = 0;
9460
9461 do {
9462 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9463
9464 if (pend_bits == 0)
9465 break;
9466
0926d499 9467 usleep_range(1000, 2000);
c9ee9206
VZ		 9468 } while (cnt-- > 0);
9469
9470 if (cnt <= 0) {
9471 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9472 pend_bits);
9473 return -EBUSY;
9474 }
9475
9476 return 0;
9477}
9478
9479static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9480{
9481 int cnt = 1000;
9482 u32 val = 0;
9483 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9484 u32 tags_63_32 = 0;
72fd0718
VZ		 9485
9486 /* Empty the Tetris buffer, wait for 1s */
9487 do {
9488 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9489 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9490 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9491 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9492 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9493 if (CHIP_IS_E3(bp))
9494 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9495
72fd0718
VZ		 9496 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9497 ((port_is_idle_0 & 0x1) == 0x1) &&
9498 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9499 (pgl_exp_rom2 == 0xffffffff) &&
9500 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9501 break;
0926d499 9502 usleep_range(1000, 2000);
72fd0718
VZ		 9503 } while (cnt-- > 0);
9504
9505 if (cnt <= 0) {
51c1a580
MS		 9506 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9507 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9508 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9509 pgl_exp_rom2);
9510 return -EAGAIN;
9511 }
9512
9513 barrier();
9514
9515 /* Close gates #2, #3 and #4 */
9516 bnx2x_set_234_gates(bp, true);
9517
c9ee9206
VZ		 9518 /* Poll for IGU VQs for 57712 and newer chips */
9519 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9520 return -EAGAIN;
9521
72fd0718
VZ		 9522 /* TBD: Indicate that "process kill" is in progress to MCP */
9523
9524 /* Clear "unprepared" bit */
9525 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9526 barrier();
9527
9528 /* Make sure all is written to the chip before the reset */
9529 mmiowb();
9530
9531 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9532 * PSWHST, GRC and PSWRD Tetris buffer.
9533 */
0926d499 9534 usleep_range(1000, 2000);
72fd0718
VZ		 9535
9536 /* Prepare to chip reset: */
9537 /* MCP */
c9ee9206
VZ		 9538 if (global)
9539 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9540
9541 /* PXP */
9542 bnx2x_pxp_prep(bp);
9543 barrier();
9544
9545 /* reset the chip */
c9ee9206 9546 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9547 barrier();
9548
9dcd9acd
DK		 9549 /* clear errors in PGB */
9550 if (!CHIP_IS_E1x(bp))
9551 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9552
72fd0718
VZ		 9553 /* Recover after reset: */
9554 /* MCP */
c9ee9206 9555 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9556 return -EAGAIN;
9557
c9ee9206
VZ		 9558 /* TBD: Add resetting the NO_MCP mode DB here */
9559
72fd0718
VZ		 9560 /* Open the gates #2, #3 and #4 */
9561 bnx2x_set_234_gates(bp, false);
9562
9563 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9564 * reset state, re-enable attentions. */
9565
a2fbb9ea
ET		 9566 return 0;
9567}
9568
910cc727 9569static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9570{
9571 int rc = 0;
c9ee9206 9572 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9573 u32 load_code;
9574
9575 /* if not going to reset MCP - load "fake" driver to reset HW while
9576 * driver is owner of the HW
9577 */
9578 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9579 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9580 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9581 if (!load_code) {
9582 BNX2X_ERR("MCP response failure, aborting\n");
9583 rc = -EAGAIN;
9584 goto exit_leader_reset;
9585 }
9586 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9587 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9588 BNX2X_ERR("MCP unexpected resp, aborting\n");
9589 rc = -EAGAIN;
9590 goto exit_leader_reset2;
9591 }
9592 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9593 if (!load_code) {
9594 BNX2X_ERR("MCP response failure, aborting\n");
9595 rc = -EAGAIN;
9596 goto exit_leader_reset2;
9597 }
9598 }
c9ee9206 9599
72fd0718 9600 /* Try to recover after the failure */
c9ee9206 9601 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9602 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9603 BP_PATH(bp));
72fd0718 9604 rc = -EAGAIN;
95c6c616 9605 goto exit_leader_reset2;
72fd0718
VZ		 9606 }
9607
c9ee9206
VZ		 9608 /*
9609 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9610 * state.
9611 */
72fd0718 9612 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9613 if (global)
9614 bnx2x_clear_reset_global(bp);
72fd0718 9615
95c6c616
AE		 9616exit_leader_reset2:
9617 /* unload "fake driver" if it was loaded */
9618 if (!global && !BP_NOMCP(bp)) {
9619 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9620 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9621 }
72fd0718
VZ		 9622exit_leader_reset:
9623 bp->is_leader = 0;
c9ee9206
VZ		 9624 bnx2x_release_leader_lock(bp);
9625 smp_mb();
72fd0718
VZ		 9626 return rc;
9627}
9628
1191cb83 9629static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9630{
9631 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9632
9633 /* Disconnect this device */
9634 netif_device_detach(bp->dev);
9635
9636 /*
9637 * Block ifup for all function on this engine until "process kill"
9638 * or power cycle.
9639 */
9640 bnx2x_set_reset_in_progress(bp);
9641
9642 /* Shut down the power */
9643 bnx2x_set_power_state(bp, PCI_D3hot);
9644
9645 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9646
9647 smp_mb();
9648}
9649
9650/*
9651 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9652 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9653 * will never be called when netif_running(bp->dev) is false.
9654 */
9655static void bnx2x_parity_recover(struct bnx2x *bp)
9656{
c9ee9206 9657 bool global = false;
7a752993 9658 u32 error_recovered, error_unrecovered;
95c6c616 9659 bool is_parity;
c9ee9206 9660
72fd0718
VZ		 9661 DP(NETIF_MSG_HW, "Handling parity\n");
9662 while (1) {
9663 switch (bp->recovery_state) {
9664 case BNX2X_RECOVERY_INIT:
9665 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9666 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9667 WARN_ON(!is_parity);
c9ee9206 9668
72fd0718 9669 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9670 if (bnx2x_trylock_leader_lock(bp)) {
9671 bnx2x_set_reset_in_progress(bp);
9672 /*
9673 * Check if there is a global attention and if
9674 * there was a global attention, set the global
9675 * reset bit.
9676 */
9677
9678 if (global)
9679 bnx2x_set_reset_global(bp);
9680
72fd0718 9681 bp->is_leader = 1;
c9ee9206 9682 }
72fd0718
VZ		 9683
9684 /* Stop the driver */
9685 /* If interface has been removed - break */
5d07d868 9686 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9687 return;
9688
9689 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9690
c9ee9206
VZ		 9691 /* Ensure "is_leader", MCP command sequence and
9692 * "recovery_state" update values are seen on other
9693 * CPUs.
72fd0718 9694 */
c9ee9206 9695 smp_mb();
72fd0718
VZ		 9696 break;
9697
9698 case BNX2X_RECOVERY_WAIT:
9699 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9700 if (bp->is_leader) {
c9ee9206 9701 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9702 bool other_load_status =
9703 bnx2x_get_load_status(bp, other_engine);
9704 bool load_status =
9705 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9706 global = bnx2x_reset_is_global(bp);
9707
9708 /*
9709 * In case of a parity in a global block, let
9710 * the first leader that performs a
9711 * leader_reset() reset the global blocks in
9712 * order to clear global attentions. Otherwise
16a5fd92 9713 * the gates will remain closed for that
c9ee9206
VZ		 9714 * engine.
9715 */
889b9af3
AE		 9716 if (load_status ||
9717 (global && other_load_status)) {
72fd0718
VZ		 9718 /* Wait until all other functions get
9719 * down.
9720 */
7be08a72 9721 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9722 HZ/10);
9723 return;
9724 } else {
9725 /* If all other functions got down -
9726 * try to bring the chip back to
9727 * normal. In any case it's an exit
9728 * point for a leader.
9729 */
c9ee9206
VZ		 9730 if (bnx2x_leader_reset(bp)) {
9731 bnx2x_recovery_failed(bp);
72fd0718
VZ		 9732 return;
9733 }
9734
c9ee9206
VZ		 9735 /* If we are here, means that the
9736 * leader has succeeded and doesn't
9737 * want to be a leader any more. Try
9738 * to continue as a none-leader.
9739 */
9740 break;
72fd0718
VZ		 9741 }
9742 } else { /* non-leader */
c9ee9206 9743 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 9744 /* Try to get a LEADER_LOCK HW lock as
9745 * long as a former leader may have
9746 * been unloaded by the user or
9747 * released a leadership by another
9748 * reason.
9749 */
c9ee9206 9750 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 9751 /* I'm a leader now! Restart a
9752 * switch case.
9753 */
9754 bp->is_leader = 1;
9755 break;
9756 }
9757
7be08a72 9758 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9759 HZ/10);
9760 return;
9761
c9ee9206
VZ		 9762 } else {
9763 /*
9764 * If there was a global attention, wait
9765 * for it to be cleared.
9766 */
9767 if (bnx2x_reset_is_global(bp)) {
9768 schedule_delayed_work(
7be08a72
AE		 9769 &bp->sp_rtnl_task,
9770 HZ/10);
c9ee9206
VZ		 9771 return;
9772 }
9773
7a752993
AE		 9774 error_recovered =
9775 bp->eth_stats.recoverable_error;
9776 error_unrecovered =
9777 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 9778 bp->recovery_state =
9779 BNX2X_RECOVERY_NIC_LOADING;
9780 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 9781 error_unrecovered++;
95c6c616 9782 netdev_err(bp->dev,
51c1a580 9783 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 9784 /* Disconnect this device */
9785 netif_device_detach(bp->dev);
9786 /* Shut down the power */
9787 bnx2x_set_power_state(
9788 bp, PCI_D3hot);
9789 smp_mb();
9790 } else {
c9ee9206
VZ		 9791 bp->recovery_state =
9792 BNX2X_RECOVERY_DONE;
7a752993 9793 error_recovered++;
c9ee9206
VZ		 9794 smp_mb();
9795 }
7a752993
AE		 9796 bp->eth_stats.recoverable_error =
9797 error_recovered;
9798 bp->eth_stats.unrecoverable_error =
9799 error_unrecovered;
c9ee9206 9800
72fd0718
VZ		 9801 return;
9802 }
9803 }
9804 default:
9805 return;
9806 }
9807 }
9808}
9809
56ad3152
MS		 9810static int bnx2x_close(struct net_device *dev);
9811
72fd0718
VZ		 9812/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9813 * scheduled on a general queue in order to prevent a dead lock.
9814 */
7be08a72 9815static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 9816{
7be08a72 9817 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 9818
9819 rtnl_lock();
9820
8395be5e
AE		 9821 if (!netif_running(bp->dev)) {
9822 rtnl_unlock();
9823 return;
9824 }
7be08a72 9825
6bf07b8e 9826 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 9827#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 9828 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9829 "you will need to reboot when done\n");
9830 goto sp_rtnl_not_reset;
7be08a72 9831#endif
7be08a72 9832 /*
b1fb8740
VZ		 9833 * Clear all pending SP commands as we are going to reset the
9834 * function anyway.
7be08a72 9835 */
b1fb8740
VZ		 9836 bp->sp_rtnl_state = 0;
9837 smp_mb();
9838
72fd0718 9839 bnx2x_parity_recover(bp);
b1fb8740 9840
8395be5e
AE		 9841 rtnl_unlock();
9842 return;
b1fb8740
VZ		 9843 }
9844
9845 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 9846#ifdef BNX2X_STOP_ON_ERROR
9847 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9848 "you will need to reboot when done\n");
9849 goto sp_rtnl_not_reset;
9850#endif
9851
b1fb8740
VZ		 9852 /*
9853 * Clear all pending SP commands as we are going to reset the
9854 * function anyway.
9855 */
9856 bp->sp_rtnl_state = 0;
9857 smp_mb();
9858
5d07d868 9859 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 9860 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740 9861
8395be5e
AE		 9862 rtnl_unlock();
9863 return;
72fd0718 9864 }
b1fb8740
VZ		 9865#ifdef BNX2X_STOP_ON_ERROR
9866sp_rtnl_not_reset:
9867#endif
9868 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9869 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 9870 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9871 bnx2x_after_function_update(bp);
8304859a
AE		 9872 /*
9873 * in case of fan failure we need to reset id if the "stop on error"
9874 * debug flag is set, since we trying to prevent permanent overheating
9875 * damage
9876 */
9877 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 9878 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 9879 netif_device_detach(bp->dev);
9880 bnx2x_close(bp->dev);
8395be5e
AE		 9881 rtnl_unlock();
9882 return;
8304859a
AE		 9883 }
9884
381ac16b
AE		 9885 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9886 DP(BNX2X_MSG_SP,
9887 "sending set mcast vf pf channel message from rtnl sp-task\n");
9888 bnx2x_vfpf_set_mcast(bp->dev);
9889 }
78c3bcc5
AE		 9890 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9891 &bp->sp_rtnl_state)){
9892 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9893 bnx2x_tx_disable(bp);
9894 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9895 }
9896 }
381ac16b 9897
8b09be5f
YM		 9898 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9899 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9900 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 9901 }
9902
3ec9f9ca
AE		 9903 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9904 &bp->sp_rtnl_state))
9905 bnx2x_pf_set_vfs_vlan(bp);
9906
6ffa39f2 9907 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 9908 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 9909 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 9910 }
07b4eb3b 9911
42f8277f
YM		 9912 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
9913 &bp->sp_rtnl_state))
9914 bnx2x_update_mng_version(bp);
9915
8395be5e
AE		 9916 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9917 * can be called from other contexts as well)
9918 */
34f80b04 9919 rtnl_unlock();
8395be5e 9920
6411280a 9921 /* enable SR-IOV if applicable */
8395be5e 9922 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 9923 &bp->sp_rtnl_state)) {
9924 bnx2x_disable_sriov(bp);
6411280a 9925 bnx2x_enable_sriov(bp);
3c76feff 9926 }
34f80b04
EG		 9927}
9928
3deb8167
YR		 9929static void bnx2x_period_task(struct work_struct *work)
9930{
9931 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9932
9933 if (!netif_running(bp->dev))
9934 goto period_task_exit;
9935
9936 if (CHIP_REV_IS_SLOW(bp)) {
9937 BNX2X_ERR("period task called on emulation, ignoring\n");
9938 goto period_task_exit;
9939 }
9940
9941 bnx2x_acquire_phy_lock(bp);
9942 /*
9943 * The barrier is needed to ensure the ordering between the writing to
9944 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9945 * the reading here.
9946 */
9947 smp_mb();
9948 if (bp->port.pmf) {
9949 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9950
9951 /* Re-queue task in 1 sec */
9952 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9953 }
9954
9955 bnx2x_release_phy_lock(bp);
9956period_task_exit:
9957 return;
9958}
9959
a2fbb9ea
ET		 9960/*
9961 * Init service functions
9962 */
9963
a8f47eb7 9964static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 9965{
9966 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9967 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9968 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 9969}
9970
1ef1d45a
BW		 9971static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9972 struct bnx2x_mac_vals *vals)
34f80b04 9973{
452427b0
YM		 9974 u32 val, base_addr, offset, mask, reset_reg;
9975 bool mac_stopped = false;
9976 u8 port = BP_PORT(bp);
34f80b04 9977
1ef1d45a
BW		 9978 /* reset addresses as they also mark which values were changed */
9979 vals->bmac_addr = 0;
9980 vals->umac_addr = 0;
9981 vals->xmac_addr = 0;
9982 vals->emac_addr = 0;
9983
452427b0 9984 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 9985
452427b0
YM		 9986 if (!CHIP_IS_E3(bp)) {
9987 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9988 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9989 if ((mask & reset_reg) && val) {
9990 u32 wb_data[2];
9991 BNX2X_DEV_INFO("Disable bmac Rx\n");
9992 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9993 : NIG_REG_INGRESS_BMAC0_MEM;
9994 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9995 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 9996
452427b0
YM		 9997 /*
9998 * use rd/wr since we cannot use dmae. This is safe
9999 * since MCP won't access the bus due to the request
10000 * to unload, and no function on the path can be
10001 * loaded at this time.
10002 */
10003 wb_data[0] = REG_RD(bp, base_addr + offset);
10004 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 10005 vals->bmac_addr = base_addr + offset;
10006 vals->bmac_val[0] = wb_data[0];
10007 vals->bmac_val[1] = wb_data[1];
452427b0 10008 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 10009 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10010 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 10011 }
10012 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 10013 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10014 vals->emac_val = REG_RD(bp, vals->emac_addr);
10015 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 10016 mac_stopped = true;
10017 } else {
10018 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10019 BNX2X_DEV_INFO("Disable xmac Rx\n");
10020 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10021 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10022 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10023 val & ~(1 << 1));
10024 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10025 val | (1 << 1));
1ef1d45a
BW		 10026 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10027 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10028 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 10029 mac_stopped = true;
10030 }
10031 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10032 if (mask & reset_reg) {
10033 BNX2X_DEV_INFO("Disable umac Rx\n");
10034 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1ef1d45a
BW		 10035 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10036 vals->umac_val = REG_RD(bp, vals->umac_addr);
10037 REG_WR(bp, vals->umac_addr, 0);
452427b0
YM		 10038 mac_stopped = true;
10039 }
10040 }
10041
10042 if (mac_stopped)
10043 msleep(20);
452427b0
YM		 10044}
10045
10046#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10047#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10048#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10049#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10050
91ebb929
YM		 10051#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10052#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10053#define BCM_5710_UNDI_FW_MF_VERS (0x05)
de682941
YM		 10054#define BNX2X_PREV_UNDI_MF_PORT(p) (BAR_TSTRORM_INTMEM + 0x150c + ((p) << 4))
10055#define BNX2X_PREV_UNDI_MF_FUNC(f) (BAR_TSTRORM_INTMEM + 0x184c + ((f) << 4))
b17b0ca1
YM		 10056
10057static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10058{
10059 /* UNDI marks its presence in DORQ -
10060 * it initializes CID offset for normal bell to 0x7
10061 */
10062 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10063 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10064 return false;
10065
10066 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10067 BNX2X_DEV_INFO("UNDI previously loaded\n");
10068 return true;
10069 }
10070
10071 return false;
10072}
10073
91ebb929
YM		 10074static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
10075{
10076 u8 major, minor, version;
10077 u32 fw;
10078
10079 /* Must check that FW is loaded */
10080 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10081 MISC_REGISTERS_RESET_REG_1_RST_XSEM)) {
10082 BNX2X_DEV_INFO("XSEM is reset - UNDI MF FW is not loaded\n");
10083 return false;
10084 }
10085
10086 /* Read Currently loaded FW version */
10087 fw = REG_RD(bp, XSEM_REG_PRAM);
10088 major = fw & 0xff;
10089 minor = (fw >> 0x8) & 0xff;
10090 version = (fw >> 0x10) & 0xff;
10091 BNX2X_DEV_INFO("Loaded FW: 0x%08x: Major 0x%02x Minor 0x%02x Version 0x%02x\n",
10092 fw, major, minor, version);
10093
10094 if (major > BCM_5710_UNDI_FW_MF_MAJOR)
10095 return true;
10096
10097 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
10098 (minor > BCM_5710_UNDI_FW_MF_MINOR))
10099 return true;
10100
10101 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
10102 (minor == BCM_5710_UNDI_FW_MF_MINOR) &&
10103 (version >= BCM_5710_UNDI_FW_MF_VERS))
10104 return true;
10105
10106 return false;
10107}
10108
10109static void bnx2x_prev_unload_undi_mf(struct bnx2x *bp)
10110{
10111 int i;
10112
10113 /* Due to legacy (FW) code, the first function on each engine has a
10114 * different offset macro from the rest of the functions.
10115 * Setting this for all 8 functions is harmless regardless of whether
10116 * this is actually a multi-function device.
10117 */
10118 for (i = 0; i < 2; i++)
10119 REG_WR(bp, BNX2X_PREV_UNDI_MF_PORT(i), 1);
10120
10121 for (i = 2; i < 8; i++)
10122 REG_WR(bp, BNX2X_PREV_UNDI_MF_FUNC(i - 2), 1);
10123
10124 BNX2X_DEV_INFO("UNDI FW (MF) set to discard\n");
10125}
10126
1dd06ae8 10127static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
452427b0
YM		 10128{
10129 u16 rcq, bd;
10130 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
10131
10132 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10133 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10134
10135 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10136 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
10137
10138 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10139 port, bd, rcq);
10140}
10141
0329aba1 10142static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10143{
5d07d868
YM		 10144 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10145 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10146 if (!rc) {
10147 BNX2X_ERR("MCP response failure, aborting\n");
10148 return -EBUSY;
10149 }
10150
10151 return 0;
10152}
10153
c63da990
BW		 10154static struct bnx2x_prev_path_list *
10155 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10156{
10157 struct bnx2x_prev_path_list *tmp_list;
10158
10159 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10160 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10161 bp->pdev->bus->number == tmp_list->bus &&
10162 BP_PATH(bp) == tmp_list->path)
10163 return tmp_list;
10164
10165 return NULL;
10166}
10167
7fa6f340
YM		 10168static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10169{
10170 struct bnx2x_prev_path_list *tmp_list;
10171 int rc;
10172
10173 rc = down_interruptible(&bnx2x_prev_sem);
10174 if (rc) {
10175 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10176 return rc;
10177 }
10178
10179 tmp_list = bnx2x_prev_path_get_entry(bp);
10180 if (tmp_list) {
10181 tmp_list->aer = 1;
10182 rc = 0;
10183 } else {
10184 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10185 BP_PATH(bp));
10186 }
10187
10188 up(&bnx2x_prev_sem);
10189
10190 return rc;
10191}
10192
0329aba1 10193static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10194{
10195 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10196 bool rc = false;
452427b0
YM		 10197
10198 if (down_trylock(&bnx2x_prev_sem))
10199 return false;
10200
7fa6f340
YM		 10201 tmp_list = bnx2x_prev_path_get_entry(bp);
10202 if (tmp_list) {
10203 if (tmp_list->aer) {
10204 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10205 BP_PATH(bp));
10206 } else {
452427b0
YM		 10207 rc = true;
10208 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10209 BP_PATH(bp));
452427b0
YM		 10210 }
10211 }
10212
10213 up(&bnx2x_prev_sem);
10214
10215 return rc;
10216}
10217
178135c1
DK		 10218bool bnx2x_port_after_undi(struct bnx2x *bp)
10219{
10220 struct bnx2x_prev_path_list *entry;
10221 bool val;
10222
10223 down(&bnx2x_prev_sem);
10224
10225 entry = bnx2x_prev_path_get_entry(bp);
10226 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10227
10228 up(&bnx2x_prev_sem);
10229
10230 return val;
10231}
10232
c63da990 10233static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10234{
10235 struct bnx2x_prev_path_list *tmp_list;
10236 int rc;
10237
7fa6f340
YM		 10238 rc = down_interruptible(&bnx2x_prev_sem);
10239 if (rc) {
10240 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10241 return rc;
10242 }
10243
10244 /* Check whether the entry for this path already exists */
10245 tmp_list = bnx2x_prev_path_get_entry(bp);
10246 if (tmp_list) {
10247 if (!tmp_list->aer) {
10248 BNX2X_ERR("Re-Marking the path.\n");
10249 } else {
10250 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10251 BP_PATH(bp));
10252 tmp_list->aer = 0;
10253 }
10254 up(&bnx2x_prev_sem);
10255 return 0;
10256 }
10257 up(&bnx2x_prev_sem);
10258
10259 /* Create an entry for this path and add it */
ea4b3857 10260 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10261 if (!tmp_list) {
10262 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10263 return -ENOMEM;
10264 }
10265
10266 tmp_list->bus = bp->pdev->bus->number;
10267 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10268 tmp_list->path = BP_PATH(bp);
7fa6f340 10269 tmp_list->aer = 0;
c63da990 10270 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10271
10272 rc = down_interruptible(&bnx2x_prev_sem);
10273 if (rc) {
10274 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10275 kfree(tmp_list);
10276 } else {
7fa6f340
YM		 10277 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10278 BP_PATH(bp));
452427b0
YM		 10279 list_add(&tmp_list->list, &bnx2x_prev_list);
10280 up(&bnx2x_prev_sem);
10281 }
10282
10283 return rc;
10284}
10285
0329aba1 10286static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10287{
452427b0
YM		 10288 struct pci_dev *dev = bp->pdev;
10289
8eee694c
YM		 10290 if (CHIP_IS_E1x(bp)) {
10291 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10292 return -EINVAL;
10293 }
10294
10295 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10296 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10297 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10298 bp->common.bc_ver);
10299 return -EINVAL;
10300 }
452427b0 10301
8903b9eb
CL		 10302 if (!pci_wait_for_pending_transaction(dev))
10303 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10304
8eee694c 10305 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10306 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10307
10308 return 0;
10309}
10310
0329aba1 10311static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10312{
10313 int rc;
10314
10315 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10316
10317 /* Test if previous unload process was already finished for this path */
10318 if (bnx2x_prev_is_path_marked(bp))
10319 return bnx2x_prev_mcp_done(bp);
10320
04c46736
YM		 10321 BNX2X_DEV_INFO("Path is unmarked\n");
10322
b17b0ca1
YM		 10323 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10324 if (bnx2x_prev_is_after_undi(bp))
10325 goto out;
10326
452427b0
YM		 10327 /* If function has FLR capabilities, and existing FW version matches
10328 * the one required, then FLR will be sufficient to clean any residue
10329 * left by previous driver
10330 */
91ebb929 10331 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10332
10333 if (!rc) {
10334 /* fw version is good */
10335 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10336 rc = bnx2x_do_flr(bp);
10337 }
10338
10339 if (!rc) {
10340 /* FLR was performed */
10341 BNX2X_DEV_INFO("FLR successful\n");
10342 return 0;
10343 }
10344
10345 BNX2X_DEV_INFO("Could not FLR\n");
452427b0 10346
b17b0ca1 10347out:
452427b0
YM		 10348 /* Close the MCP request, return failure*/
10349 rc = bnx2x_prev_mcp_done(bp);
10350 if (!rc)
10351 rc = BNX2X_PREV_WAIT_NEEDED;
10352
10353 return rc;
10354}
10355
0329aba1 10356static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10357{
10358 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10359 bool prev_undi = false;
1ef1d45a
BW		 10360 struct bnx2x_mac_vals mac_vals;
10361
452427b0
YM		 10362 /* It is possible a previous function received 'common' answer,
10363 * but hasn't loaded yet, therefore creating a scenario of
10364 * multiple functions receiving 'common' on the same path.
10365 */
10366 BNX2X_DEV_INFO("Common unload Flow\n");
10367
1ef1d45a
BW		 10368 memset(&mac_vals, 0, sizeof(mac_vals));
10369
452427b0
YM		 10370 if (bnx2x_prev_is_path_marked(bp))
10371 return bnx2x_prev_mcp_done(bp);
10372
10373 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10374
10375 /* Reset should be performed after BRB is emptied */
10376 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10377 u32 timer_count = 1000;
de682941 10378 bool need_write = true;
452427b0
YM		 10379
10380 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10381 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10382
10383 /* close LLH filters towards the BRB */
10384 bnx2x_set_rx_filter(&bp->link_params, 0);
452427b0 10385
b17b0ca1
YM		 10386 /* Check if the UNDI driver was previously loaded */
10387 if (bnx2x_prev_is_after_undi(bp)) {
10388 prev_undi = true;
10389 /* clear the UNDI indication */
10390 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10391 /* clear possible idle check errors */
10392 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
452427b0 10393 }
d46f7c4d
DK		 10394 if (!CHIP_IS_E1x(bp))
10395 /* block FW from writing to host */
10396 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10397
452427b0
YM		 10398 /* wait until BRB is empty */
10399 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10400 while (timer_count) {
10401 u32 prev_brb = tmp_reg;
34f80b04 10402
452427b0
YM		 10403 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10404 if (!tmp_reg)
10405 break;
619c5cb6 10406
452427b0 10407 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10408
452427b0
YM		 10409 /* reset timer as long as BRB actually gets emptied */
10410 if (prev_brb > tmp_reg)
10411 timer_count = 1000;
10412 else
10413 timer_count--;
da5a662a 10414
91ebb929
YM		 10415 /* New UNDI FW supports MF and contains better
10416 * cleaning methods - might be redundant but harmless.
10417 */
10418 if (bnx2x_prev_unload_undi_fw_supports_mf(bp)) {
de682941
YM		 10419 if (need_write) {
10420 bnx2x_prev_unload_undi_mf(bp);
10421 need_write = false;
10422 }
91ebb929
YM		 10423 } else if (prev_undi) {
10424 /* If UNDI resides in memory,
10425 * manually increment it
10426 */
452427b0 10427 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
91ebb929 10428 }
452427b0 10429 udelay(10);
7a06a122 10430 }
452427b0
YM		 10431
10432 if (!timer_count)
10433 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10434 }
f16da43b 10435
452427b0
YM		 10436 /* No packets are in the pipeline, path is ready for reset */
10437 bnx2x_reset_common(bp);
10438
1ef1d45a
BW		 10439 if (mac_vals.xmac_addr)
10440 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10441 if (mac_vals.umac_addr)
10442 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10443 if (mac_vals.emac_addr)
10444 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10445 if (mac_vals.bmac_addr) {
10446 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10447 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10448 }
10449
c63da990 10450 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10451 if (rc) {
10452 bnx2x_prev_mcp_done(bp);
10453 return rc;
10454 }
10455
10456 return bnx2x_prev_mcp_done(bp);
10457}
10458
24f06716
AE		 10459/* previous driver DMAE transaction may have occurred when pre-boot stage ended
10460 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10461 * the addresses of the transaction, resulting in was-error bit set in the pci
10462 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10463 * to clear the interrupt which detected this from the pglueb and the was done
10464 * bit
10465 */
0329aba1 10466static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
24f06716 10467{
4a25417c
AE		 10468 if (!CHIP_IS_E1x(bp)) {
10469 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10470 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
04c46736
YM		 10471 DP(BNX2X_MSG_SP,
10472 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
4a25417c
AE		 10473 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10474 1 << BP_FUNC(bp));
10475 }
24f06716
AE		 10476 }
10477}
10478
0329aba1 10479static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10480{
10481 int time_counter = 10;
10482 u32 rc, fw, hw_lock_reg, hw_lock_val;
10483 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10484
24f06716
AE		 10485 /* clear hw from errors which may have resulted from an interrupted
10486 * dmae transaction.
10487 */
10488 bnx2x_prev_interrupted_dmae(bp);
10489
10490 /* Release previously held locks */
452427b0
YM		 10491 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10492 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10493 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10494
3cdeec22 10495 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10496 if (hw_lock_val) {
10497 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10498 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10499 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10500 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10501 }
10502
10503 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10504 REG_WR(bp, hw_lock_reg, 0xffffffff);
10505 } else
10506 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10507
10508 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10509 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10510 bnx2x_release_alr(bp);
452427b0
YM		 10511 }
10512
452427b0 10513 do {
7fa6f340 10514 int aer = 0;
452427b0
YM		 10515 /* Lock MCP using an unload request */
10516 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10517 if (!fw) {
10518 BNX2X_ERR("MCP response failure, aborting\n");
10519 rc = -EBUSY;
10520 break;
10521 }
10522
7fa6f340
YM		 10523 rc = down_interruptible(&bnx2x_prev_sem);
10524 if (rc) {
10525 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10526 rc);
10527 } else {
10528 /* If Path is marked by EEH, ignore unload status */
10529 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10530 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10531 up(&bnx2x_prev_sem);
7fa6f340 10532 }
7fa6f340
YM		 10533
10534 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10535 rc = bnx2x_prev_unload_common(bp);
10536 break;
10537 }
10538
16a5fd92 10539 /* non-common reply from MCP might require looping */
452427b0
YM		 10540 rc = bnx2x_prev_unload_uncommon(bp);
10541 if (rc != BNX2X_PREV_WAIT_NEEDED)
10542 break;
10543
10544 msleep(20);
10545 } while (--time_counter);
10546
10547 if (!time_counter || rc) {
91ebb929
YM		 10548 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10549 rc = -EPROBE_DEFER;
452427b0
YM		 10550 }
10551
c63da990 10552 /* Mark function if its port was used to boot from SAN */
178135c1 10553 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10554 bp->link_params.feature_config_flags |=
10555 FEATURE_CONFIG_BOOT_FROM_SAN;
10556
452427b0
YM		 10557 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10558
10559 return rc;
34f80b04
EG		 10560}
10561
0329aba1 10562static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10563{
1d187b34 10564 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10565 u16 pmc;
34f80b04
EG		 10566
10567 /* Get the chip revision id and number. */
10568 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10569 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10570 id = ((val & 0xffff) << 16);
10571 val = REG_RD(bp, MISC_REG_CHIP_REV);
10572 id |= ((val & 0xf) << 12);
f22fdf25
YM		 10573
10574 /* Metal is read from PCI regs, but we can't access >=0x400 from
10575 * the configuration space (so we need to reg_rd)
10576 */
10577 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10578 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 10579 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10580 id |= (val & 0xf);
10581 bp->common.chip_id = id;
523224a3 10582
7e8e02df
BW		 10583 /* force 57811 according to MISC register */
10584 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10585 if (CHIP_IS_57810(bp))
10586 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10587 (bp->common.chip_id & 0x0000FFFF);
10588 else if (CHIP_IS_57810_MF(bp))
10589 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10590 (bp->common.chip_id & 0x0000FFFF);
10591 bp->common.chip_id |= 0x1;
10592 }
10593
523224a3
DK		 10594 /* Set doorbell size */
10595 bp->db_size = (1 << BNX2X_DB_SHIFT);
10596
619c5cb6 10597 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10598 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10599 if ((val & 1) == 0)
10600 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10601 else
10602 val = (val >> 1) & 1;
10603 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10604 "2_PORT_MODE");
10605 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10606 CHIP_2_PORT_MODE;
10607
10608 if (CHIP_MODE_IS_4_PORT(bp))
10609 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10610 else
10611 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10612 } else {
10613 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10614 bp->pfid = bp->pf_num; /* 0..7 */
10615 }
10616
51c1a580
MS		 10617 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10618
f2e0899f
DK		 10619 bp->link_params.chip_id = bp->common.chip_id;
10620 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10621
1c06328c
EG		 10622 val = (REG_RD(bp, 0x2874) & 0x55);
10623 if ((bp->common.chip_id & 0x1) ||
10624 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10625 bp->flags |= ONE_PORT_FLAG;
10626 BNX2X_DEV_INFO("single port device\n");
10627 }
10628
34f80b04 10629 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 10630 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 10631 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10632 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10633 bp->common.flash_size, bp->common.flash_size);
10634
1b6e2ceb
DK		 10635 bnx2x_init_shmem(bp);
10636
f2e0899f
DK		 10637 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10638 MISC_REG_GENERIC_CR_1 :
10639 MISC_REG_GENERIC_CR_0));
1b6e2ceb 10640
34f80b04 10641 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 10642 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 10643 if (SHMEM2_RD(bp, size) >
10644 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10645 bp->link_params.lfa_base =
10646 REG_RD(bp, bp->common.shmem2_base +
10647 (u32)offsetof(struct shmem2_region,
10648 lfa_host_addr[BP_PORT(bp)]));
10649 else
10650 bp->link_params.lfa_base = 0;
2691d51d
EG		 10651 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10652 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 10653
f2e0899f 10654 if (!bp->common.shmem_base) {
34f80b04
EG		 10655 BNX2X_DEV_INFO("MCP not active\n");
10656 bp->flags |= NO_MCP_FLAG;
10657 return;
10658 }
10659
34f80b04 10660 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 10661 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 10662
10663 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10664 SHARED_HW_CFG_LED_MODE_MASK) >>
10665 SHARED_HW_CFG_LED_MODE_SHIFT);
10666
c2c8b03e
EG		 10667 bp->link_params.feature_config_flags = 0;
10668 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10669 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10670 bp->link_params.feature_config_flags |=
10671 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10672 else
10673 bp->link_params.feature_config_flags &=
10674 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10675
34f80b04
EG		 10676 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10677 bp->common.bc_ver = val;
10678 BNX2X_DEV_INFO("bc_ver %X\n", val);
10679 if (val < BNX2X_BC_VER) {
10680 /* for now only warn
10681 * later we might need to enforce this */
51c1a580
MS		 10682 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10683 BNX2X_BC_VER, val);
34f80b04 10684 }
4d295db0 10685 bp->link_params.feature_config_flags |=
a22f0788 10686 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 10687 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10688
a22f0788
YR		 10689 bp->link_params.feature_config_flags |=
10690 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10691 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 10692 bp->link_params.feature_config_flags |=
10693 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10694 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 10695 bp->link_params.feature_config_flags |=
10696 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10697 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 10698
10699 bp->link_params.feature_config_flags |=
10700 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10701 FEATURE_CONFIG_MT_SUPPORT : 0;
10702
0e898dd7
BW		 10703 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10704 BC_SUPPORTS_PFC_STATS : 0;
85242eea 10705
2e499d3c
BW		 10706 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10707 BC_SUPPORTS_FCOE_FEATURES : 0;
10708
9876879f
BW		 10709 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10710 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 10711
10712 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10713 BC_SUPPORTS_RMMOD_CMD : 0;
10714
1d187b34
BW		 10715 boot_mode = SHMEM_RD(bp,
10716 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10717 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10718 switch (boot_mode) {
10719 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10720 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10721 break;
10722 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10723 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10724 break;
10725 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10726 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10727 break;
10728 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10729 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10730 break;
10731 }
10732
29ed74c3 10733 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 10734 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10735
72ce58c3 10736 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 10737 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 10738
10739 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10740 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10741 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10742 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10743
cdaa7cb8
VZ		 10744 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10745 val, val2, val3, val4);
34f80b04
EG		 10746}
10747
f2e0899f
DK		 10748#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10749#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10750
0329aba1 10751static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 10752{
10753 int pfid = BP_FUNC(bp);
f2e0899f
DK		 10754 int igu_sb_id;
10755 u32 val;
6383c0b3 10756 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 10757
10758 bp->igu_base_sb = 0xff;
f2e0899f 10759 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 10760 int vn = BP_VN(bp);
6383c0b3 10761 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 10762 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10763 FP_SB_MAX_E1x;
10764
10765 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10766 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10767
9b341bb1 10768 return 0;
f2e0899f
DK		 10769 }
10770
10771 /* IGU in normal mode - read CAM */
10772 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10773 igu_sb_id++) {
10774 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10775 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10776 continue;
10777 fid = IGU_FID(val);
10778 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10779 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10780 continue;
10781 if (IGU_VEC(val) == 0)
10782 /* default status block */
10783 bp->igu_dsb_id = igu_sb_id;
10784 else {
10785 if (bp->igu_base_sb == 0xff)
10786 bp->igu_base_sb = igu_sb_id;
6383c0b3 10787 igu_sb_cnt++;
f2e0899f
DK		 10788 }
10789 }
10790 }
619c5cb6 10791
6383c0b3 10792#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 10793 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10794 * optional that number of CAM entries will not be equal to the value
10795 * advertised in PCI.
10796 * Driver should use the minimal value of both as the actual status
10797 * block count
619c5cb6 10798 */
185d4c8b 10799 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 10800#endif
619c5cb6 10801
9b341bb1 10802 if (igu_sb_cnt == 0) {
f2e0899f 10803 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 10804 return -EINVAL;
10805 }
10806
10807 return 0;
f2e0899f
DK		 10808}
10809
1dd06ae8 10810static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 10811{
a22f0788
YR		 10812 int cfg_size = 0, idx, port = BP_PORT(bp);
10813
10814 /* Aggregation of supported attributes of all external phys */
10815 bp->port.supported[0] = 0;
10816 bp->port.supported[1] = 0;
b7737c9b
YR		 10817 switch (bp->link_params.num_phys) {
10818 case 1:
a22f0788
YR		 10819 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10820 cfg_size = 1;
10821 break;
b7737c9b 10822 case 2:
a22f0788
YR		 10823 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10824 cfg_size = 1;
10825 break;
10826 case 3:
10827 if (bp->link_params.multi_phy_config &
10828 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10829 bp->port.supported[1] =
10830 bp->link_params.phy[EXT_PHY1].supported;
10831 bp->port.supported[0] =
10832 bp->link_params.phy[EXT_PHY2].supported;
10833 } else {
10834 bp->port.supported[0] =
10835 bp->link_params.phy[EXT_PHY1].supported;
10836 bp->port.supported[1] =
10837 bp->link_params.phy[EXT_PHY2].supported;
10838 }
10839 cfg_size = 2;
10840 break;
b7737c9b 10841 }
a2fbb9ea 10842
a22f0788 10843 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 10844 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 10845 SHMEM_RD(bp,
a22f0788
YR		 10846 dev_info.port_hw_config[port].external_phy_config),
10847 SHMEM_RD(bp,
10848 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 10849 return;
f85582f8 10850 }
a2fbb9ea 10851
619c5cb6
VZ		 10852 if (CHIP_IS_E3(bp))
10853 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10854 else {
10855 switch (switch_cfg) {
10856 case SWITCH_CFG_1G:
10857 bp->port.phy_addr = REG_RD(
10858 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10859 break;
10860 case SWITCH_CFG_10G:
10861 bp->port.phy_addr = REG_RD(
10862 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10863 break;
10864 default:
10865 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10866 bp->port.link_config[0]);
10867 return;
10868 }
a2fbb9ea 10869 }
619c5cb6 10870 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 10871 /* mask what we support according to speed_cap_mask per configuration */
10872 for (idx = 0; idx < cfg_size; idx++) {
10873 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10874 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 10875 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 10876
a22f0788 10877 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10878 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 10879 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 10880
a22f0788 10881 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10882 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 10883 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 10884
a22f0788 10885 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10886 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 10887 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 10888
a22f0788 10889 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10890 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 10891 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 10892 SUPPORTED_1000baseT_Full);
a2fbb9ea 10893
a22f0788 10894 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10895 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 10896 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 10897
a22f0788 10898 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10899 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 10900 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 10901
10902 if (!(bp->link_params.speed_cap_mask[idx] &
10903 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10904 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 10905 }
a2fbb9ea 10906
a22f0788
YR		 10907 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10908 bp->port.supported[1]);
a2fbb9ea
ET		 10909}
10910
0329aba1 10911static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 10912{
a22f0788
YR		 10913 u32 link_config, idx, cfg_size = 0;
10914 bp->port.advertising[0] = 0;
10915 bp->port.advertising[1] = 0;
10916 switch (bp->link_params.num_phys) {
10917 case 1:
10918 case 2:
10919 cfg_size = 1;
10920 break;
10921 case 3:
10922 cfg_size = 2;
10923 break;
10924 }
10925 for (idx = 0; idx < cfg_size; idx++) {
10926 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10927 link_config = bp->port.link_config[idx];
10928 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 10929 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 10930 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10931 bp->link_params.req_line_speed[idx] =
10932 SPEED_AUTO_NEG;
10933 bp->port.advertising[idx] |=
10934 bp->port.supported[idx];
10bd1f24
MY		 10935 if (bp->link_params.phy[EXT_PHY1].type ==
10936 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10937 bp->port.advertising[idx] |=
10938 (SUPPORTED_100baseT_Half |
10939 SUPPORTED_100baseT_Full);
f85582f8
DK		 10940 } else {
10941 /* force 10G, no AN */
a22f0788
YR		 10942 bp->link_params.req_line_speed[idx] =
10943 SPEED_10000;
10944 bp->port.advertising[idx] |=
10945 (ADVERTISED_10000baseT_Full |
f85582f8 10946 ADVERTISED_FIBRE);
a22f0788 10947 continue;
f85582f8
DK		 10948 }
10949 break;
a2fbb9ea 10950
f85582f8 10951 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 10952 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10953 bp->link_params.req_line_speed[idx] =
10954 SPEED_10;
10955 bp->port.advertising[idx] |=
10956 (ADVERTISED_10baseT_Full |
f85582f8
DK		 10957 ADVERTISED_TP);
10958 } else {
51c1a580 10959 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 10960 link_config,
a22f0788 10961 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10962 return;
10963 }
10964 break;
a2fbb9ea 10965
f85582f8 10966 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 10967 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10968 bp->link_params.req_line_speed[idx] =
10969 SPEED_10;
10970 bp->link_params.req_duplex[idx] =
10971 DUPLEX_HALF;
10972 bp->port.advertising[idx] |=
10973 (ADVERTISED_10baseT_Half |
f85582f8
DK		 10974 ADVERTISED_TP);
10975 } else {
51c1a580 10976 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10977 link_config,
10978 bp->link_params.speed_cap_mask[idx]);
10979 return;
10980 }
10981 break;
a2fbb9ea 10982
f85582f8
DK		 10983 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10984 if (bp->port.supported[idx] &
10985 SUPPORTED_100baseT_Full) {
a22f0788
YR		 10986 bp->link_params.req_line_speed[idx] =
10987 SPEED_100;
10988 bp->port.advertising[idx] |=
10989 (ADVERTISED_100baseT_Full |
f85582f8
DK		 10990 ADVERTISED_TP);
10991 } else {
51c1a580 10992 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10993 link_config,
10994 bp->link_params.speed_cap_mask[idx]);
10995 return;
10996 }
10997 break;
a2fbb9ea 10998
f85582f8
DK		 10999 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11000 if (bp->port.supported[idx] &
11001 SUPPORTED_100baseT_Half) {
11002 bp->link_params.req_line_speed[idx] =
11003 SPEED_100;
11004 bp->link_params.req_duplex[idx] =
11005 DUPLEX_HALF;
a22f0788
YR		 11006 bp->port.advertising[idx] |=
11007 (ADVERTISED_100baseT_Half |
f85582f8
DK		 11008 ADVERTISED_TP);
11009 } else {
51c1a580 11010 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11011 link_config,
11012 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11013 return;
11014 }
11015 break;
a2fbb9ea 11016
f85582f8 11017 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 11018 if (bp->port.supported[idx] &
11019 SUPPORTED_1000baseT_Full) {
11020 bp->link_params.req_line_speed[idx] =
11021 SPEED_1000;
11022 bp->port.advertising[idx] |=
11023 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 11024 ADVERTISED_TP);
11025 } else {
51c1a580 11026 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11027 link_config,
11028 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11029 return;
11030 }
11031 break;
a2fbb9ea 11032
f85582f8 11033 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 11034 if (bp->port.supported[idx] &
11035 SUPPORTED_2500baseX_Full) {
11036 bp->link_params.req_line_speed[idx] =
11037 SPEED_2500;
11038 bp->port.advertising[idx] |=
11039 (ADVERTISED_2500baseX_Full |
34f80b04 11040 ADVERTISED_TP);
f85582f8 11041 } else {
51c1a580 11042 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11043 link_config,
f85582f8
DK		 11044 bp->link_params.speed_cap_mask[idx]);
11045 return;
11046 }
11047 break;
a2fbb9ea 11048
f85582f8 11049 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 11050 if (bp->port.supported[idx] &
11051 SUPPORTED_10000baseT_Full) {
11052 bp->link_params.req_line_speed[idx] =
11053 SPEED_10000;
11054 bp->port.advertising[idx] |=
11055 (ADVERTISED_10000baseT_Full |
34f80b04 11056 ADVERTISED_FIBRE);
f85582f8 11057 } else {
51c1a580 11058 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11059 link_config,
f85582f8
DK		 11060 bp->link_params.speed_cap_mask[idx]);
11061 return;
11062 }
11063 break;
3c9ada22
YR		 11064 case PORT_FEATURE_LINK_SPEED_20G:
11065 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 11066
3c9ada22 11067 break;
f85582f8 11068 default:
51c1a580 11069 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 11070 link_config);
f85582f8
DK		 11071 bp->link_params.req_line_speed[idx] =
11072 SPEED_AUTO_NEG;
11073 bp->port.advertising[idx] =
11074 bp->port.supported[idx];
11075 break;
11076 }
a2fbb9ea 11077
a22f0788 11078 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 11079 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 11080 if (bp->link_params.req_flow_ctrl[idx] ==
11081 BNX2X_FLOW_CTRL_AUTO) {
11082 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11083 bp->link_params.req_flow_ctrl[idx] =
11084 BNX2X_FLOW_CTRL_NONE;
11085 else
11086 bnx2x_set_requested_fc(bp);
a22f0788 11087 }
a2fbb9ea 11088
51c1a580 11089 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 11090 bp->link_params.req_line_speed[idx],
11091 bp->link_params.req_duplex[idx],
11092 bp->link_params.req_flow_ctrl[idx],
11093 bp->port.advertising[idx]);
11094 }
a2fbb9ea
ET		 11095}
11096
0329aba1 11097static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 11098{
86564c3f
YM		 11099 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11100 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11101 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11102 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 11103}
11104
0329aba1 11105static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 11106{
34f80b04 11107 int port = BP_PORT(bp);
589abe3a 11108 u32 config;
c8c60d88 11109 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 11110
c18487ee 11111 bp->link_params.bp = bp;
34f80b04 11112 bp->link_params.port = port;
c18487ee 11113
c18487ee 11114 bp->link_params.lane_config =
a2fbb9ea 11115 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 11116
a22f0788 11117 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 11118 SHMEM_RD(bp,
b0261926
YR		 11119 dev_info.port_hw_config[port].speed_capability_mask) &
11120 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 11121 bp->link_params.speed_cap_mask[1] =
11122 SHMEM_RD(bp,
b0261926
YR		 11123 dev_info.port_hw_config[port].speed_capability_mask2) &
11124 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 11125 bp->port.link_config[0] =
a2fbb9ea
ET		 11126 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11127
a22f0788
YR		 11128 bp->port.link_config[1] =
11129 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 11130
a22f0788
YR		 11131 bp->link_params.multi_phy_config =
11132 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 11133 /* If the device is capable of WoL, set the default state according
11134 * to the HW
11135 */
4d295db0 11136 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 11137 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11138 (config & PORT_FEATURE_WOL_ENABLED));
11139
4ba7699b
YM		 11140 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11141 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11142 bp->flags |= NO_ISCSI_FLAG;
11143 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11144 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11145 bp->flags |= NO_FCOE_FLAG;
11146
51c1a580 11147 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11148 bp->link_params.lane_config,
a22f0788
YR		 11149 bp->link_params.speed_cap_mask[0],
11150 bp->port.link_config[0]);
a2fbb9ea 11151
a22f0788 11152 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11153 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11154 bnx2x_phy_probe(&bp->link_params);
c18487ee 11155 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11156
11157 bnx2x_link_settings_requested(bp);
11158
01cd4528
EG		 11159 /*
11160 * If connected directly, work with the internal PHY, otherwise, work
11161 * with the external PHY
11162 */
b7737c9b
YR		 11163 ext_phy_config =
11164 SHMEM_RD(bp,
11165 dev_info.port_hw_config[port].external_phy_config);
11166 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11167 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11168 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11169
11170 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11171 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11172 bp->mdio.prtad =
b7737c9b 11173 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11174
c8c60d88
YM		 11175 /* Configure link feature according to nvram value */
11176 eee_mode = (((SHMEM_RD(bp, dev_info.
11177 port_feature_config[port].eee_power_mode)) &
11178 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11179 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11180 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11181 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11182 EEE_MODE_ENABLE_LPI |
11183 EEE_MODE_OUTPUT_TIME;
11184 } else {
11185 bp->link_params.eee_mode = 0;
11186 }
0793f83f 11187}
01cd4528 11188
b306f5ed 11189void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11190{
9e62e912 11191 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11192 int port = BP_PORT(bp);
2ba45142 11193 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11194 drv_lic_key[port].max_iscsi_conn);
2ba45142 11195
55c11941
MS		 11196 if (!CNIC_SUPPORT(bp)) {
11197 bp->flags |= no_flags;
11198 return;
11199 }
11200
b306f5ed 11201 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11202 bp->cnic_eth_dev.max_iscsi_conn =
11203 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11204 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11205
b306f5ed
DK		 11206 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11207 bp->cnic_eth_dev.max_iscsi_conn);
11208
11209 /*
11210 * If maximum allowed number of connections is zero -
11211 * disable the feature.
11212 */
11213 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11214 bp->flags |= no_flags;
b306f5ed
DK		 11215}
11216
0329aba1 11217static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11218{
11219 /* Port info */
11220 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11221 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11222 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11223 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11224
11225 /* Node info */
11226 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11227 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11228 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11229 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11230}
86800194
DK		 11231
11232static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11233{
11234 u8 count = 0;
11235
11236 if (IS_MF(bp)) {
11237 u8 fid;
11238
11239 /* iterate over absolute function ids for this path: */
11240 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11241 if (IS_MF_SD(bp)) {
11242 u32 cfg = MF_CFG_RD(bp,
11243 func_mf_config[fid].config);
11244
11245 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11246 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11247 FUNC_MF_CFG_PROTOCOL_FCOE))
11248 count++;
11249 } else {
11250 u32 cfg = MF_CFG_RD(bp,
11251 func_ext_config[fid].
11252 func_cfg);
11253
11254 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11255 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11256 count++;
11257 }
11258 }
11259 } else { /* SF */
11260 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11261
11262 for (port = 0; port < port_cnt; port++) {
11263 u32 lic = SHMEM_RD(bp,
11264 drv_lic_key[port].max_fcoe_conn) ^
11265 FW_ENCODE_32BIT_PATTERN;
11266 if (lic)
11267 count++;
11268 }
11269 }
11270
11271 return count;
11272}
11273
0329aba1 11274static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11275{
11276 int port = BP_PORT(bp);
11277 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11278 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11279 drv_lic_key[port].max_fcoe_conn);
86800194 11280 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11281
55c11941
MS		 11282 if (!CNIC_SUPPORT(bp)) {
11283 bp->flags |= NO_FCOE_FLAG;
11284 return;
11285 }
11286
b306f5ed 11287 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11288 bp->cnic_eth_dev.max_fcoe_conn =
11289 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11290 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11291
0eb43b4b
BPG		 11292 /* Calculate the number of maximum allowed FCoE tasks */
11293 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11294
11295 /* check if FCoE resources must be shared between different functions */
11296 if (num_fcoe_func)
11297 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11298
bf61ee14
VZ		 11299 /* Read the WWN: */
11300 if (!IS_MF(bp)) {
11301 /* Port info */
11302 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11303 SHMEM_RD(bp,
2de67439 11304 dev_info.port_hw_config[port].
bf61ee14
VZ		 11305 fcoe_wwn_port_name_upper);
11306 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11307 SHMEM_RD(bp,
2de67439 11308 dev_info.port_hw_config[port].
bf61ee14
VZ		 11309 fcoe_wwn_port_name_lower);
11310
11311 /* Node info */
11312 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11313 SHMEM_RD(bp,
2de67439 11314 dev_info.port_hw_config[port].
bf61ee14
VZ		 11315 fcoe_wwn_node_name_upper);
11316 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11317 SHMEM_RD(bp,
2de67439 11318 dev_info.port_hw_config[port].
bf61ee14
VZ		 11319 fcoe_wwn_node_name_lower);
11320 } else if (!IS_MF_SD(bp)) {
bf61ee14
VZ		 11321 /*
11322 * Read the WWN info only if the FCoE feature is enabled for
11323 * this function.
11324 */
7b5342d9 11325 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912
DK		 11326 bnx2x_get_ext_wwn_info(bp, func);
11327
382e513a 11328 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
9e62e912 11329 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11330 }
bf61ee14 11331
b306f5ed 11332 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11333
bf61ee14
VZ		 11334 /*
11335 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11336 * disable the feature.
11337 */
2ba45142
VZ		 11338 if (!bp->cnic_eth_dev.max_fcoe_conn)
11339 bp->flags |= NO_FCOE_FLAG;
11340}
b306f5ed 11341
0329aba1 11342static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11343{
11344 /*
11345 * iSCSI may be dynamically disabled but reading
11346 * info here we will decrease memory usage by driver
11347 * if the feature is disabled for good
11348 */
11349 bnx2x_get_iscsi_info(bp);
11350 bnx2x_get_fcoe_info(bp);
11351}
2ba45142 11352
0329aba1 11353static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11354{
11355 u32 val, val2;
11356 int func = BP_ABS_FUNC(bp);
11357 int port = BP_PORT(bp);
2ba45142
VZ		 11358 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11359 u8 *fip_mac = bp->fip_mac;
0793f83f 11360
55c11941
MS		 11361 if (IS_MF(bp)) {
11362 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11363 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11364 * In non SD mode features configuration comes from struct
11365 * func_ext_config.
2ba45142 11366 */
55c11941 11367 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
0793f83f
DK		 11368 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11369 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11370 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11371 iscsi_mac_addr_upper);
0793f83f 11372 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11373 iscsi_mac_addr_lower);
2ba45142 11374 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11375 BNX2X_DEV_INFO
11376 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11377 } else {
2ba45142 11378 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11379 }
2ba45142
VZ		 11380
11381 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11382 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11383 fcoe_mac_addr_upper);
2ba45142 11384 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11385 fcoe_mac_addr_lower);
2ba45142 11386 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11387 BNX2X_DEV_INFO
11388 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11389 } else {
2ba45142 11390 bp->flags |= NO_FCOE_FLAG;
55c11941 11391 }
a3348722
BW		 11392
11393 bp->mf_ext_config = cfg;
11394
9e62e912 11395 } else { /* SD MODE */
55c11941
MS		 11396 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11397 /* use primary mac as iscsi mac */
11398 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11399
11400 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11401 BNX2X_DEV_INFO
11402 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11403 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11404 /* use primary mac as fip mac */
11405 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11406 BNX2X_DEV_INFO("SD FCoE MODE\n");
11407 BNX2X_DEV_INFO
11408 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11409 }
0793f83f 11410 }
a3348722 11411
82594f8f
YM		 11412 /* If this is a storage-only interface, use SAN mac as
11413 * primary MAC. Notice that for SD this is already the case,
11414 * as the SAN mac was copied from the primary MAC.
11415 */
11416 if (IS_MF_FCOE_AFEX(bp))
a3348722 11417 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11418 } else {
0793f83f 11419 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11420 iscsi_mac_upper);
0793f83f 11421 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11422 iscsi_mac_lower);
2ba45142 11423 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11424
11425 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11426 fcoe_fip_mac_upper);
c03bd39c 11427 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11428 fcoe_fip_mac_lower);
c03bd39c 11429 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11430 }
11431
55c11941 11432 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11433 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11434 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
426b9241
DK		 11435 memset(iscsi_mac, 0, ETH_ALEN);
11436 }
11437
55c11941 11438 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11439 if (!is_valid_ether_addr(fip_mac)) {
11440 bp->flags |= NO_FCOE_FLAG;
11441 memset(bp->fip_mac, 0, ETH_ALEN);
11442 }
55c11941
MS		 11443}
11444
0329aba1 11445static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11446{
11447 u32 val, val2;
11448 int func = BP_ABS_FUNC(bp);
11449 int port = BP_PORT(bp);
11450
11451 /* Zero primary MAC configuration */
11452 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11453
11454 if (BP_NOMCP(bp)) {
11455 BNX2X_ERROR("warning: random MAC workaround active\n");
11456 eth_hw_addr_random(bp->dev);
11457 } else if (IS_MF(bp)) {
11458 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11459 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11460 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11461 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11462 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11463
11464 if (CNIC_SUPPORT(bp))
11465 bnx2x_get_cnic_mac_hwinfo(bp);
11466 } else {
11467 /* in SF read MACs from port configuration */
11468 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11469 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11470 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11471
11472 if (CNIC_SUPPORT(bp))
11473 bnx2x_get_cnic_mac_hwinfo(bp);
11474 }
11475
3d7d562c
YM		 11476 if (!BP_NOMCP(bp)) {
11477 /* Read physical port identifier from shmem */
11478 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11479 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11480 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11481 bp->flags |= HAS_PHYS_PORT_ID;
11482 }
11483
55c11941 11484 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11485
614c76df 11486 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6 11487 dev_err(&bp->pdev->dev,
51c1a580
MS		 11488 "bad Ethernet MAC address configuration: %pM\n"
11489 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11490 bp->dev->dev_addr);
7964211d 11491}
51c1a580 11492
0329aba1 11493static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11494{
11495 int tmp;
11496 u32 cfg;
51c1a580 11497
aeeddb8b
YM		 11498 if (IS_VF(bp))
11499 return 0;
11500
7964211d
YM		 11501 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11502 /* Take function: tmp = func */
11503 tmp = BP_ABS_FUNC(bp);
11504 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11505 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11506 } else {
11507 /* Take port: tmp = port */
11508 tmp = BP_PORT(bp);
11509 cfg = SHMEM_RD(bp,
11510 dev_info.port_hw_config[tmp].generic_features);
11511 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11512 }
11513 return cfg;
34f80b04
EG		 11514}
11515
0329aba1 11516static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11517{
0793f83f 11518 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 11519 int vn;
0793f83f 11520 u32 val = 0;
34f80b04 11521 int rc = 0;
a2fbb9ea 11522
34f80b04 11523 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11524
6383c0b3
AE		 11525 /*
11526 * initialize IGU parameters
11527 */
f2e0899f
DK		 11528 if (CHIP_IS_E1x(bp)) {
11529 bp->common.int_block = INT_BLOCK_HC;
11530
11531 bp->igu_dsb_id = DEF_SB_IGU_ID;
11532 bp->igu_base_sb = 0;
f2e0899f
DK		 11533 } else {
11534 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 11535
16a5fd92 11536 /* do not allow device reset during IGU info processing */
7a06a122
DK		 11537 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11538
f2e0899f 11539 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 11540
11541 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11542 int tout = 5000;
11543
11544 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11545
11546 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11547 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11548 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11549
11550 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11551 tout--;
0926d499 11552 usleep_range(1000, 2000);
619c5cb6
VZ		 11553 }
11554
11555 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11556 dev_err(&bp->pdev->dev,
11557 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 11558 bnx2x_release_hw_lock(bp,
11559 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 11560 return -EPERM;
11561 }
11562 }
11563
f2e0899f 11564 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 11565 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 11566 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11567 } else
619c5cb6 11568 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 11569
9b341bb1 11570 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 11571 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 11572 if (rc)
11573 return rc;
f2e0899f 11574 }
619c5cb6
VZ		 11575
11576 /*
11577 * set base FW non-default (fast path) status block id, this value is
11578 * used to initialize the fw_sb_id saved on the fp/queue structure to
11579 * determine the id used by the FW.
11580 */
11581 if (CHIP_IS_E1x(bp))
11582 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11583 else /*
11584 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11585 * the same queue are indicated on the same IGU SB). So we prefer
11586 * FW and IGU SBs to be the same value.
11587 */
11588 bp->base_fw_ndsb = bp->igu_base_sb;
11589
11590 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11591 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11592 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 11593
11594 /*
11595 * Initialize MF configuration
11596 */
523224a3 11597
fb3bff17
DK		 11598 bp->mf_ov = 0;
11599 bp->mf_mode = 0;
3395a033 11600 vn = BP_VN(bp);
0793f83f 11601
f2e0899f 11602 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 11603 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11604 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11605 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11606
f2e0899f
DK		 11607 if (SHMEM2_HAS(bp, mf_cfg_addr))
11608 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11609 else
11610 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 11611 offsetof(struct shmem_region, func_mb) +
11612 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 11613 /*
11614 * get mf configuration:
16a5fd92 11615 * 1. Existence of MF configuration
0793f83f
DK		 11616 * 2. MAC address must be legal (check only upper bytes)
11617 * for Switch-Independent mode;
11618 * OVLAN must be legal for Switch-Dependent mode
11619 * 3. SF_MODE configures specific MF mode
11620 */
11621 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11622 /* get mf configuration */
11623 val = SHMEM_RD(bp,
11624 dev_info.shared_feature_config.config);
11625 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11626
11627 switch (val) {
11628 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11629 val = MF_CFG_RD(bp, func_mf_config[func].
11630 mac_upper);
11631 /* check for legal mac (upper bytes)*/
11632 if (val != 0xffff) {
11633 bp->mf_mode = MULTI_FUNCTION_SI;
11634 bp->mf_config[vn] = MF_CFG_RD(bp,
11635 func_mf_config[func].config);
11636 } else
51c1a580 11637 BNX2X_DEV_INFO("illegal MAC address for SI\n");
0793f83f 11638 break;
a3348722
BW		 11639 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11640 if ((!CHIP_IS_E1x(bp)) &&
11641 (MF_CFG_RD(bp, func_mf_config[func].
11642 mac_upper) != 0xffff) &&
11643 (SHMEM2_HAS(bp,
11644 afex_driver_support))) {
11645 bp->mf_mode = MULTI_FUNCTION_AFEX;
11646 bp->mf_config[vn] = MF_CFG_RD(bp,
11647 func_mf_config[func].config);
11648 } else {
11649 BNX2X_DEV_INFO("can not configure afex mode\n");
11650 }
11651 break;
0793f83f
DK		 11652 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11653 /* get OV configuration */
11654 val = MF_CFG_RD(bp,
11655 func_mf_config[FUNC_0].e1hov_tag);
11656 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11657
11658 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11659 bp->mf_mode = MULTI_FUNCTION_SD;
11660 bp->mf_config[vn] = MF_CFG_RD(bp,
11661 func_mf_config[func].config);
11662 } else
754a2f52 11663 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 11664 break;
3786b942
AE		 11665 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11666 bp->mf_config[vn] = 0;
11667 break;
0793f83f
DK		 11668 default:
11669 /* Unknown configuration: reset mf_config */
11670 bp->mf_config[vn] = 0;
51c1a580 11671 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 11672 }
11673 }
a2fbb9ea 11674
2691d51d 11675 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 11676 IS_MF(bp) ? "multi" : "single");
2691d51d 11677
0793f83f
DK		 11678 switch (bp->mf_mode) {
11679 case MULTI_FUNCTION_SD:
11680 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11681 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 11682 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 11683 bp->mf_ov = val;
619c5cb6
VZ		 11684 bp->path_has_ovlan = true;
11685
51c1a580
MS		 11686 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11687 func, bp->mf_ov, bp->mf_ov);
2691d51d 11688 } else {
619c5cb6 11689 dev_err(&bp->pdev->dev,
51c1a580
MS		 11690 "No valid MF OV for func %d, aborting\n",
11691 func);
619c5cb6 11692 return -EPERM;
34f80b04 11693 }
0793f83f 11694 break;
a3348722
BW		 11695 case MULTI_FUNCTION_AFEX:
11696 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11697 break;
0793f83f 11698 case MULTI_FUNCTION_SI:
51c1a580
MS		 11699 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11700 func);
0793f83f
DK		 11701 break;
11702 default:
11703 if (vn) {
619c5cb6 11704 dev_err(&bp->pdev->dev,
51c1a580
MS		 11705 "VN %d is in a single function mode, aborting\n",
11706 vn);
619c5cb6 11707 return -EPERM;
2691d51d 11708 }
0793f83f 11709 break;
34f80b04 11710 }
0793f83f 11711
619c5cb6
VZ		 11712 /* check if other port on the path needs ovlan:
11713 * Since MF configuration is shared between ports
11714 * Possible mixed modes are only
11715 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11716 */
11717 if (CHIP_MODE_IS_4_PORT(bp) &&
11718 !bp->path_has_ovlan &&
11719 !IS_MF(bp) &&
11720 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11721 u8 other_port = !BP_PORT(bp);
11722 u8 other_func = BP_PATH(bp) + 2*other_port;
11723 val = MF_CFG_RD(bp,
11724 func_mf_config[other_func].e1hov_tag);
11725 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11726 bp->path_has_ovlan = true;
11727 }
34f80b04 11728 }
a2fbb9ea 11729
e848582c
DK		 11730 /* adjust igu_sb_cnt to MF for E1H */
11731 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11732 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 11733
619c5cb6
VZ		 11734 /* port info */
11735 bnx2x_get_port_hwinfo(bp);
f2e0899f 11736
0793f83f
DK		 11737 /* Get MAC addresses */
11738 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 11739
2ba45142 11740 bnx2x_get_cnic_info(bp);
2ba45142 11741
34f80b04
EG		 11742 return rc;
11743}
11744
0329aba1 11745static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 11746{
11747 int cnt, i, block_end, rodi;
fcdf95cb 11748 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 11749 char str_id_reg[VENDOR_ID_LEN+1];
11750 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 11751 char *vpd_data;
11752 char *vpd_extended_data = NULL;
34f24c7f
VZ		 11753 u8 len;
11754
fcdf95cb 11755 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 11756 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11757
11758 if (cnt < BNX2X_VPD_LEN)
11759 goto out_not_found;
11760
fcdf95cb
BW		 11761 /* VPD RO tag should be first tag after identifier string, hence
11762 * we should be able to find it in first BNX2X_VPD_LEN chars
11763 */
11764 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 11765 PCI_VPD_LRDT_RO_DATA);
11766 if (i < 0)
11767 goto out_not_found;
11768
34f24c7f 11769 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 11770 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 11771
11772 i += PCI_VPD_LRDT_TAG_SIZE;
11773
fcdf95cb
BW		 11774 if (block_end > BNX2X_VPD_LEN) {
11775 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11776 if (vpd_extended_data == NULL)
11777 goto out_not_found;
11778
11779 /* read rest of vpd image into vpd_extended_data */
11780 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11781 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11782 block_end - BNX2X_VPD_LEN,
11783 vpd_extended_data + BNX2X_VPD_LEN);
11784 if (cnt < (block_end - BNX2X_VPD_LEN))
11785 goto out_not_found;
11786 vpd_data = vpd_extended_data;
11787 } else
11788 vpd_data = vpd_start;
11789
11790 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 11791
11792 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11793 PCI_VPD_RO_KEYWORD_MFR_ID);
11794 if (rodi < 0)
11795 goto out_not_found;
11796
11797 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11798
11799 if (len != VENDOR_ID_LEN)
11800 goto out_not_found;
11801
11802 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11803
11804 /* vendor specific info */
11805 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11806 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11807 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11808 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11809
11810 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11811 PCI_VPD_RO_KEYWORD_VENDOR0);
11812 if (rodi >= 0) {
11813 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11814
11815 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11816
11817 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11818 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11819 bp->fw_ver[len] = ' ';
11820 }
11821 }
fcdf95cb 11822 kfree(vpd_extended_data);
34f24c7f
VZ		 11823 return;
11824 }
11825out_not_found:
fcdf95cb 11826 kfree(vpd_extended_data);
34f24c7f
VZ		 11827 return;
11828}
11829
0329aba1 11830static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 11831{
11832 u32 flags = 0;
11833
11834 if (CHIP_REV_IS_FPGA(bp))
11835 SET_FLAGS(flags, MODE_FPGA);
11836 else if (CHIP_REV_IS_EMUL(bp))
11837 SET_FLAGS(flags, MODE_EMUL);
11838 else
11839 SET_FLAGS(flags, MODE_ASIC);
11840
11841 if (CHIP_MODE_IS_4_PORT(bp))
11842 SET_FLAGS(flags, MODE_PORT4);
11843 else
11844 SET_FLAGS(flags, MODE_PORT2);
11845
11846 if (CHIP_IS_E2(bp))
11847 SET_FLAGS(flags, MODE_E2);
11848 else if (CHIP_IS_E3(bp)) {
11849 SET_FLAGS(flags, MODE_E3);
11850 if (CHIP_REV(bp) == CHIP_REV_Ax)
11851 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 11852 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11853 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 11854 }
11855
11856 if (IS_MF(bp)) {
11857 SET_FLAGS(flags, MODE_MF);
11858 switch (bp->mf_mode) {
11859 case MULTI_FUNCTION_SD:
11860 SET_FLAGS(flags, MODE_MF_SD);
11861 break;
11862 case MULTI_FUNCTION_SI:
11863 SET_FLAGS(flags, MODE_MF_SI);
11864 break;
a3348722
BW		 11865 case MULTI_FUNCTION_AFEX:
11866 SET_FLAGS(flags, MODE_MF_AFEX);
11867 break;
619c5cb6
VZ		 11868 }
11869 } else
11870 SET_FLAGS(flags, MODE_SF);
11871
11872#if defined(__LITTLE_ENDIAN)
11873 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11874#else /*(__BIG_ENDIAN)*/
11875 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11876#endif
11877 INIT_MODE_FLAGS(bp) = flags;
11878}
11879
0329aba1 11880static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 11881{
f2e0899f 11882 int func;
34f80b04
EG		 11883 int rc;
11884
34f80b04 11885 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 11886 mutex_init(&bp->fw_mb_mutex);
42f8277f
YM		 11887 mutex_init(&bp->drv_info_mutex);
11888 bp->drv_info_mng_owner = false;
bb7e95c8 11889 spin_lock_init(&bp->stats_lock);
507393eb 11890 sema_init(&bp->stats_sema, 1);
55c11941 11891
1cf167f2 11892 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 11893 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 11894 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
370d4a26 11895 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
1ab4434c
AE		 11896 if (IS_PF(bp)) {
11897 rc = bnx2x_get_hwinfo(bp);
11898 if (rc)
11899 return rc;
11900 } else {
e09b74d0 11901 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 11902 }
34f80b04 11903
619c5cb6
VZ		 11904 bnx2x_set_modes_bitmap(bp);
11905
11906 rc = bnx2x_alloc_mem_bp(bp);
11907 if (rc)
11908 return rc;
523224a3 11909
34f24c7f 11910 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 11911
11912 func = BP_FUNC(bp);
11913
34f80b04 11914 /* need to reset chip if undi was active */
1ab4434c 11915 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 11916 /* init fw_seq */
11917 bp->fw_seq =
11918 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11919 DRV_MSG_SEQ_NUMBER_MASK;
11920 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11921
91ebb929
YM		 11922 rc = bnx2x_prev_unload(bp);
11923 if (rc) {
11924 bnx2x_free_mem_bp(bp);
11925 return rc;
11926 }
452427b0
YM		 11927 }
11928
34f80b04 11929 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 11930 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 11931
11932 if (BP_NOMCP(bp) && (func == 0))
51c1a580 11933 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 11934
614c76df 11935 bp->disable_tpa = disable_tpa;
a3348722 11936 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
94d9de3c
MS		 11937 /* Reduce memory usage in kdump environment by disabling TPA */
11938 bp->disable_tpa |= reset_devices;
614c76df 11939
7a9b2557 11940 /* Set TPA flags */
614c76df 11941 if (bp->disable_tpa) {
621b4d66 11942 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11943 bp->dev->features &= ~NETIF_F_LRO;
11944 } else {
621b4d66 11945 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11946 bp->dev->features |= NETIF_F_LRO;
11947 }
11948
a18f5128
EG		 11949 if (CHIP_IS_E1(bp))
11950 bp->dropless_fc = 0;
11951 else
7964211d 11952 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 11953
8d5726c4 11954 bp->mrrs = mrrs;
7a9b2557 11955
a3348722 11956 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 11957 if (IS_VF(bp))
11958 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 11959
7d323bfd 11960 /* make sure that the numbers are in the right granularity */
523224a3
DK		 11961 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11962 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 11963
fc543637 11964 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 11965
11966 init_timer(&bp->timer);
11967 bp->timer.expires = jiffies + bp->current_interval;
11968 bp->timer.data = (unsigned long) bp;
11969 bp->timer.function = bnx2x_timer;
11970
0370cf90
BW		 11971 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11972 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11973 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11974 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11975 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11976 bnx2x_dcbx_init_params(bp);
11977 } else {
11978 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11979 }
e4901dde 11980
619c5cb6
VZ		 11981 if (CHIP_IS_E1x(bp))
11982 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11983 else
11984 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 11985
6383c0b3 11986 /* multiple tx priority */
1ab4434c
AE		 11987 if (IS_VF(bp))
11988 bp->max_cos = 1;
11989 else if (CHIP_IS_E1x(bp))
6383c0b3 11990 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 11991 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 11992 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 11993 else if (CHIP_IS_E3B0(bp))
6383c0b3 11994 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 11995 else
11996 BNX2X_ERR("unknown chip %x revision %x\n",
11997 CHIP_NUM(bp), CHIP_REV(bp));
11998 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 11999
55c11941
MS		 12000 /* We need at least one default status block for slow-path events,
12001 * second status block for the L2 queue, and a third status block for
16a5fd92 12002 * CNIC if supported.
55c11941 12003 */
60cad4e6
AE		 12004 if (IS_VF(bp))
12005 bp->min_msix_vec_cnt = 1;
12006 else if (CNIC_SUPPORT(bp))
55c11941 12007 bp->min_msix_vec_cnt = 3;
60cad4e6 12008 else /* PF w/o cnic */
55c11941
MS		 12009 bp->min_msix_vec_cnt = 2;
12010 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12011
5bb680d6
MS		 12012 bp->dump_preset_idx = 1;
12013
34f80b04 12014 return rc;
a2fbb9ea
ET		 12015}
12016
de0c62db
DK		 12017/****************************************************************************
12018* General service functions
12019****************************************************************************/
a2fbb9ea 12020
619c5cb6
VZ		 12021/*
12022 * net_device service functions
12023 */
12024
bb2a0f7a 12025/* called with rtnl_lock */
a2fbb9ea
ET		 12026static int bnx2x_open(struct net_device *dev)
12027{
12028 struct bnx2x *bp = netdev_priv(dev);
8395be5e 12029 int rc;
a2fbb9ea 12030
1355b704
MY		 12031 bp->stats_init = true;
12032
6eccabb3
EG		 12033 netif_carrier_off(dev);
12034
a2fbb9ea
ET		 12035 bnx2x_set_power_state(bp, PCI_D0);
12036
ad5afc89 12037 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 12038 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12039 * want the first function loaded on the current engine to
12040 * complete the recovery.
ad5afc89 12041 * Parity recovery is only relevant for PF driver.
c9ee9206 12042 */
ad5afc89 12043 if (IS_PF(bp)) {
1a6974b2
YM		 12044 int other_engine = BP_PATH(bp) ? 0 : 1;
12045 bool other_load_status, load_status;
12046 bool global = false;
12047
ad5afc89
AE		 12048 other_load_status = bnx2x_get_load_status(bp, other_engine);
12049 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12050 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12051 bnx2x_chk_parity_attn(bp, &global, true)) {
12052 do {
12053 /* If there are attentions and they are in a
12054 * global blocks, set the GLOBAL_RESET bit
12055 * regardless whether it will be this function
12056 * that will complete the recovery or not.
12057 */
12058 if (global)
12059 bnx2x_set_reset_global(bp);
72fd0718 12060
ad5afc89
AE		 12061 /* Only the first function on the current
12062 * engine should try to recover in open. In case
12063 * of attentions in global blocks only the first
12064 * in the chip should try to recover.
12065 */
12066 if ((!load_status &&
12067 (!global || !other_load_status)) &&
12068 bnx2x_trylock_leader_lock(bp) &&
12069 !bnx2x_leader_reset(bp)) {
12070 netdev_info(bp->dev,
12071 "Recovered in open\n");
12072 break;
12073 }
72fd0718 12074
ad5afc89
AE		 12075 /* recovery has failed... */
12076 bnx2x_set_power_state(bp, PCI_D3hot);
12077 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 12078
ad5afc89
AE		 12079 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12080 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 12081
ad5afc89
AE		 12082 return -EAGAIN;
12083 } while (0);
12084 }
12085 }
72fd0718
VZ		 12086
12087 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 12088 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12089 if (rc)
12090 return rc;
9a8130bc 12091 return 0;
a2fbb9ea
ET		 12092}
12093
bb2a0f7a 12094/* called with rtnl_lock */
56ad3152 12095static int bnx2x_close(struct net_device *dev)
a2fbb9ea 12096{
a2fbb9ea
ET		 12097 struct bnx2x *bp = netdev_priv(dev);
12098
12099 /* Unload the driver, release IRQs */
5d07d868 12100 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 12101
a2fbb9ea
ET		 12102 return 0;
12103}
12104
1191cb83
ED		 12105static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12106 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 12107{
619c5cb6
VZ		 12108 int mc_count = netdev_mc_count(bp->dev);
12109 struct bnx2x_mcast_list_elem *mc_mac =
cd2b0389 12110 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
619c5cb6 12111 struct netdev_hw_addr *ha;
6e30dd4e 12112
619c5cb6
VZ		 12113 if (!mc_mac)
12114 return -ENOMEM;
6e30dd4e 12115
619c5cb6 12116 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 12117
619c5cb6
VZ		 12118 netdev_for_each_mc_addr(ha, bp->dev) {
12119 mc_mac->mac = bnx2x_mc_addr(ha);
12120 list_add_tail(&mc_mac->link, &p->mcast_list);
12121 mc_mac++;
6e30dd4e 12122 }
619c5cb6
VZ		 12123
12124 p->mcast_list_len = mc_count;
12125
12126 return 0;
6e30dd4e
VZ		 12127}
12128
1191cb83 12129static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 12130 struct bnx2x_mcast_ramrod_params *p)
12131{
12132 struct bnx2x_mcast_list_elem *mc_mac =
12133 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12134 link);
12135
12136 WARN_ON(!mc_mac);
12137 kfree(mc_mac);
12138}
12139
12140/**
12141 * bnx2x_set_uc_list - configure a new unicast MACs list.
12142 *
12143 * @bp: driver handle
6e30dd4e 12144 *
619c5cb6 12145 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 12146 */
1191cb83 12147static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12148{
619c5cb6 12149 int rc;
6e30dd4e 12150 struct net_device *dev = bp->dev;
6e30dd4e 12151 struct netdev_hw_addr *ha;
15192a8c 12152 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12153 unsigned long ramrod_flags = 0;
6e30dd4e 12154
619c5cb6
VZ		 12155 /* First schedule a cleanup up of old configuration */
12156 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12157 if (rc < 0) {
12158 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12159 return rc;
12160 }
6e30dd4e
VZ		 12161
12162 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12163 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12164 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12165 if (rc == -EEXIST) {
12166 DP(BNX2X_MSG_SP,
12167 "Failed to schedule ADD operations: %d\n", rc);
12168 /* do not treat adding same MAC as error */
12169 rc = 0;
12170
12171 } else if (rc < 0) {
12172
619c5cb6
VZ		 12173 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12174 rc);
12175 return rc;
6e30dd4e
VZ		 12176 }
12177 }
12178
619c5cb6
VZ		 12179 /* Execute the pending commands */
12180 __set_bit(RAMROD_CONT, &ramrod_flags);
12181 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12182 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12183}
12184
1191cb83 12185static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 12186{
619c5cb6 12187 struct net_device *dev = bp->dev;
3b603066 12188 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12189 int rc = 0;
6e30dd4e 12190
619c5cb6 12191 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12192
619c5cb6
VZ		 12193 /* first, clear all configured multicast MACs */
12194 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12195 if (rc < 0) {
51c1a580 12196 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12197 return rc;
12198 }
6e30dd4e 12199
619c5cb6
VZ		 12200 /* then, configure a new MACs list */
12201 if (netdev_mc_count(dev)) {
12202 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12203 if (rc) {
51c1a580
MS		 12204 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12205 rc);
619c5cb6
VZ		 12206 return rc;
12207 }
6e30dd4e 12208
619c5cb6
VZ		 12209 /* Now add the new MACs */
12210 rc = bnx2x_config_mcast(bp, &rparam,
12211 BNX2X_MCAST_CMD_ADD);
12212 if (rc < 0)
51c1a580
MS		 12213 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12214 rc);
6e30dd4e 12215
619c5cb6
VZ		 12216 bnx2x_free_mcast_macs_list(&rparam);
12217 }
6e30dd4e 12218
619c5cb6 12219 return rc;
6e30dd4e
VZ		 12220}
12221
619c5cb6 12222/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12223static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12224{
12225 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12226
12227 if (bp->state != BNX2X_STATE_OPEN) {
12228 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12229 return;
8b09be5f
YM		 12230 } else {
12231 /* Schedule an SP task to handle rest of change */
230bb0f3
YM		 12232 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12233 NETIF_MSG_IFUP);
34f80b04 12234 }
8b09be5f
YM		 12235}
12236
12237void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12238{
12239 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12240
619c5cb6 12241 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12242
8b09be5f
YM		 12243 netif_addr_lock_bh(bp->dev);
12244
12245 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12246 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12247 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12248 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12249 CHIP_IS_E1(bp))) {
34f80b04 12250 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12251 } else {
381ac16b
AE		 12252 if (IS_PF(bp)) {
12253 /* some multicasts */
12254 if (bnx2x_set_mc_list(bp) < 0)
12255 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12256
8b09be5f
YM		 12257 /* release bh lock, as bnx2x_set_uc_list might sleep */
12258 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12259 if (bnx2x_set_uc_list(bp) < 0)
12260 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12261 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12262 } else {
12263 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12264 * wait for the pf's response).
381ac16b 12265 */
230bb0f3
YM		 12266 bnx2x_schedule_sp_rtnl(bp,
12267 BNX2X_SP_RTNL_VFPF_MCAST, 0);
381ac16b 12268 }
34f80b04
EG		 12269 }
12270
12271 bp->rx_mode = rx_mode;
614c76df
DK		 12272 /* handle ISCSI SD mode */
12273 if (IS_MF_ISCSI_SD(bp))
12274 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12275
12276 /* Schedule the rx_mode command */
12277 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12278 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12279 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12280 return;
12281 }
12282
381ac16b
AE		 12283 if (IS_PF(bp)) {
12284 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12285 netif_addr_unlock_bh(bp->dev);
381ac16b 12286 } else {
8b09be5f
YM		 12287 /* VF will need to request the PF to make this change, and so
12288 * the VF needs to release the bottom-half lock prior to the
12289 * request (as it will likely require sleep on the VF side)
381ac16b 12290 */
8b09be5f
YM		 12291 netif_addr_unlock_bh(bp->dev);
12292 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12293 }
34f80b04
EG		 12294}
12295
c18487ee 12296/* called with rtnl_lock */
01cd4528
EG		 12297static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12298 int devad, u16 addr)
a2fbb9ea 12299{
01cd4528
EG		 12300 struct bnx2x *bp = netdev_priv(netdev);
12301 u16 value;
12302 int rc;
a2fbb9ea 12303
01cd4528
EG		 12304 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12305 prtad, devad, addr);
a2fbb9ea 12306
01cd4528
EG		 12307 /* The HW expects different devad if CL22 is used */
12308 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12309
01cd4528 12310 bnx2x_acquire_phy_lock(bp);
e10bc84d 12311 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12312 bnx2x_release_phy_lock(bp);
12313 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12314
01cd4528
EG		 12315 if (!rc)
12316 rc = value;
12317 return rc;
12318}
a2fbb9ea 12319
01cd4528
EG		 12320/* called with rtnl_lock */
12321static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12322 u16 addr, u16 value)
12323{
12324 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12325 int rc;
12326
51c1a580
MS		 12327 DP(NETIF_MSG_LINK,
12328 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12329 prtad, devad, addr, value);
01cd4528 12330
01cd4528
EG		 12331 /* The HW expects different devad if CL22 is used */
12332 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12333
01cd4528 12334 bnx2x_acquire_phy_lock(bp);
e10bc84d 12335 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12336 bnx2x_release_phy_lock(bp);
12337 return rc;
12338}
c18487ee 12339
01cd4528
EG		 12340/* called with rtnl_lock */
12341static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12342{
12343 struct bnx2x *bp = netdev_priv(dev);
12344 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12345
01cd4528
EG		 12346 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12347 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 12348
01cd4528
EG		 12349 if (!netif_running(dev))
12350 return -EAGAIN;
12351
12352 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 12353}
12354
257ddbda 12355#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 12356static void poll_bnx2x(struct net_device *dev)
12357{
12358 struct bnx2x *bp = netdev_priv(dev);
14a15d61 12359 int i;
a2fbb9ea 12360
14a15d61
MS		 12361 for_each_eth_queue(bp, i) {
12362 struct bnx2x_fastpath *fp = &bp->fp[i];
12363 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12364 }
a2fbb9ea
ET		 12365}
12366#endif
12367
614c76df
DK		 12368static int bnx2x_validate_addr(struct net_device *dev)
12369{
12370 struct bnx2x *bp = netdev_priv(dev);
12371
e09b74d0
AE		 12372 /* query the bulletin board for mac address configured by the PF */
12373 if (IS_VF(bp))
12374 bnx2x_sample_bulletin(bp);
12375
51c1a580
MS		 12376 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12377 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12378 return -EADDRNOTAVAIL;
51c1a580 12379 }
614c76df
DK		 12380 return 0;
12381}
12382
3d7d562c
YM		 12383static int bnx2x_get_phys_port_id(struct net_device *netdev,
12384 struct netdev_phys_port_id *ppid)
12385{
12386 struct bnx2x *bp = netdev_priv(netdev);
12387
12388 if (!(bp->flags & HAS_PHYS_PORT_ID))
12389 return -EOPNOTSUPP;
12390
12391 ppid->id_len = sizeof(bp->phys_port_id);
12392 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12393
12394 return 0;
12395}
12396
c64213cd
SH		 12397static const struct net_device_ops bnx2x_netdev_ops = {
12398 .ndo_open = bnx2x_open,
12399 .ndo_stop = bnx2x_close,
12400 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 12401 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 12402 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 12403 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 12404 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 12405 .ndo_do_ioctl = bnx2x_ioctl,
12406 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 12407 .ndo_fix_features = bnx2x_fix_features,
12408 .ndo_set_features = bnx2x_set_features,
c64213cd 12409 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 12410#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 12411 .ndo_poll_controller = poll_bnx2x,
12412#endif
6383c0b3 12413 .ndo_setup_tc = bnx2x_setup_tc,
6411280a 12414#ifdef CONFIG_BNX2X_SRIOV
abc5a021 12415 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 12416 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 12417 .ndo_get_vf_config = bnx2x_get_vf_config,
6411280a 12418#endif
55c11941 12419#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 12420 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12421#endif
8f20aa57 12422
e0d1095a 12423#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 12424 .ndo_busy_poll = bnx2x_low_latency_recv,
8f20aa57 12425#endif
3d7d562c 12426 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
c64213cd
SH		 12427};
12428
1191cb83 12429static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 12430{
12431 struct device *dev = &bp->pdev->dev;
12432
8ceafbfa
LT		 12433 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12434 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 12435 dev_err(dev, "System does not support DMA, aborting\n");
12436 return -EIO;
12437 }
12438
12439 return 0;
12440}
12441
33d8e6a5
YM		 12442static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12443{
12444 if (bp->flags & AER_ENABLED) {
12445 pci_disable_pcie_error_reporting(bp->pdev);
12446 bp->flags &= ~AER_ENABLED;
12447 }
12448}
12449
1ab4434c
AE		 12450static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12451 struct net_device *dev, unsigned long board_type)
a2fbb9ea 12452{
a2fbb9ea 12453 int rc;
c22610d0 12454 u32 pci_cfg_dword;
65087cfe
AE		 12455 bool chip_is_e1x = (board_type == BCM57710 ||
12456 board_type == BCM57711 ||
12457 board_type == BCM57711E);
a2fbb9ea
ET		 12458
12459 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 12460
34f80b04
EG		 12461 bp->dev = dev;
12462 bp->pdev = pdev;
a2fbb9ea
ET		 12463
12464 rc = pci_enable_device(pdev);
12465 if (rc) {
cdaa7cb8
VZ		 12466 dev_err(&bp->pdev->dev,
12467 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 12468 goto err_out;
12469 }
12470
12471 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 12472 dev_err(&bp->pdev->dev,
12473 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 12474 rc = -ENODEV;
12475 goto err_out_disable;
12476 }
12477
1ab4434c
AE		 12478 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12479 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 12480 rc = -ENODEV;
12481 goto err_out_disable;
12482 }
12483
092a5fc9
YR		 12484 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12485 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12486 PCICFG_REVESION_ID_ERROR_VAL) {
12487 pr_err("PCI device error, probably due to fan failure, aborting\n");
12488 rc = -ENODEV;
12489 goto err_out_disable;
12490 }
12491
34f80b04
EG		 12492 if (atomic_read(&pdev->enable_cnt) == 1) {
12493 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12494 if (rc) {
cdaa7cb8
VZ		 12495 dev_err(&bp->pdev->dev,
12496 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 12497 goto err_out_disable;
12498 }
a2fbb9ea 12499
34f80b04
EG		 12500 pci_set_master(pdev);
12501 pci_save_state(pdev);
12502 }
a2fbb9ea 12503
1ab4434c 12504 if (IS_PF(bp)) {
29ed74c3 12505 if (!pdev->pm_cap) {
1ab4434c
AE		 12506 dev_err(&bp->pdev->dev,
12507 "Cannot find power management capability, aborting\n");
12508 rc = -EIO;
12509 goto err_out_release;
12510 }
a2fbb9ea
ET		 12511 }
12512
77c98e6a 12513 if (!pci_is_pcie(pdev)) {
51c1a580 12514 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 12515 rc = -EIO;
12516 goto err_out_release;
12517 }
12518
619c5cb6
VZ		 12519 rc = bnx2x_set_coherency_mask(bp);
12520 if (rc)
a2fbb9ea 12521 goto err_out_release;
a2fbb9ea 12522
34f80b04
EG		 12523 dev->mem_start = pci_resource_start(pdev, 0);
12524 dev->base_addr = dev->mem_start;
12525 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 12526
12527 dev->irq = pdev->irq;
12528
275f165f 12529 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 12530 if (!bp->regview) {
cdaa7cb8
VZ		 12531 dev_err(&bp->pdev->dev,
12532 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 12533 rc = -ENOMEM;
12534 goto err_out_release;
12535 }
12536
c22610d0
AE		 12537 /* In E1/E1H use pci device function given by kernel.
12538 * In E2/E3 read physical function from ME register since these chips
12539 * support Physical Device Assignment where kernel BDF maybe arbitrary
12540 * (depending on hypervisor).
12541 */
2de67439 12542 if (chip_is_e1x) {
c22610d0 12543 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 12544 } else {
12545 /* chip is E2/3*/
c22610d0
AE		 12546 pci_read_config_dword(bp->pdev,
12547 PCICFG_ME_REGISTER, &pci_cfg_dword);
12548 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 12549 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 12550 }
51c1a580 12551 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 12552
34f80b04
EG		 12553 /* clean indirect addresses */
12554 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12555 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5
YM		 12556
12557 /* AER (Advanced Error reporting) configuration */
12558 rc = pci_enable_pcie_error_reporting(pdev);
12559 if (!rc)
12560 bp->flags |= AER_ENABLED;
12561 else
12562 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12563
a5c53dbc
DK		 12564 /*
12565 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 12566 * is not used by the driver.
12567 */
1ab4434c
AE		 12568 if (IS_PF(bp)) {
12569 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12570 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12571 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12572 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12573
12574 if (chip_is_e1x) {
12575 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12576 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12577 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12578 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12579 }
a5c53dbc 12580
1ab4434c
AE		 12581 /* Enable internal target-read (in case we are probed after PF
12582 * FLR). Must be done prior to any BAR read access. Only for
12583 * 57712 and up
12584 */
12585 if (!chip_is_e1x)
12586 REG_WR(bp,
12587 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 12588 }
a2fbb9ea 12589
34f80b04 12590 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 12591
c64213cd 12592 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 12593 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 12594
01789349
JP		 12595 dev->priv_flags |= IFF_UNICAST_FLT;
12596
66371c44 12597 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 12598 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12599 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
f646968f 12600 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a848ade4 12601 if (!CHIP_IS_E1x(bp)) {
117401ee 12602 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2e3bd6a4 12603 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
a848ade4
DK		 12604 dev->hw_enc_features =
12605 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12606 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
117401ee 12607 NETIF_F_GSO_IPIP |
2e3bd6a4 12608 NETIF_F_GSO_SIT |
65bc0cfe 12609 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
a848ade4 12610 }
66371c44
MM		 12611
12612 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12613 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12614
f646968f 12615 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 12616 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 12617
538dd2e3
MB		 12618 /* Add Loopback capability to the device */
12619 dev->hw_features |= NETIF_F_LOOPBACK;
12620
98507672 12621#ifdef BCM_DCBNL
785b9b1a
SR		 12622 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12623#endif
12624
01cd4528
EG		 12625 /* get_port_hwinfo() will set prtad and mmds properly */
12626 bp->mdio.prtad = MDIO_PRTAD_NONE;
12627 bp->mdio.mmds = 0;
12628 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12629 bp->mdio.dev = dev;
12630 bp->mdio.mdio_read = bnx2x_mdio_read;
12631 bp->mdio.mdio_write = bnx2x_mdio_write;
12632
a2fbb9ea
ET		 12633 return 0;
12634
a2fbb9ea 12635err_out_release:
34f80b04
EG		 12636 if (atomic_read(&pdev->enable_cnt) == 1)
12637 pci_release_regions(pdev);
a2fbb9ea
ET		 12638
12639err_out_disable:
12640 pci_disable_device(pdev);
a2fbb9ea
ET		 12641
12642err_out:
12643 return rc;
12644}
12645
6891dd25 12646static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 12647{
37f9ce62 12648 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 12649 struct bnx2x_fw_file_hdr *fw_hdr;
12650 struct bnx2x_fw_file_section *sections;
94a78b79 12651 u32 offset, len, num_ops;
86564c3f 12652 __be16 *ops_offsets;
94a78b79 12653 int i;
37f9ce62 12654 const u8 *fw_ver;
94a78b79 12655
51c1a580
MS		 12656 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12657 BNX2X_ERR("Wrong FW size\n");
94a78b79 12658 return -EINVAL;
51c1a580 12659 }
94a78b79
VZ		 12660
12661 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12662 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12663
12664 /* Make sure none of the offsets and sizes make us read beyond
12665 * the end of the firmware data */
12666 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12667 offset = be32_to_cpu(sections[i].offset);
12668 len = be32_to_cpu(sections[i].len);
12669 if (offset + len > firmware->size) {
51c1a580 12670 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 12671 return -EINVAL;
12672 }
12673 }
12674
12675 /* Likewise for the init_ops offsets */
12676 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 12677 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 12678 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12679
12680 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12681 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 12682 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 12683 return -EINVAL;
12684 }
12685 }
12686
12687 /* Check FW version */
12688 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12689 fw_ver = firmware->data + offset;
12690 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12691 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12692 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12693 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 12694 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12695 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12696 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 12697 BCM_5710_FW_MINOR_VERSION,
12698 BCM_5710_FW_REVISION_VERSION,
12699 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 12700 return -EINVAL;
94a78b79
VZ		 12701 }
12702
12703 return 0;
12704}
12705
1191cb83 12706static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12707{
ab6ad5a4
EG		 12708 const __be32 *source = (const __be32 *)_source;
12709 u32 *target = (u32 *)_target;
94a78b79 12710 u32 i;
94a78b79
VZ		 12711
12712 for (i = 0; i < n/4; i++)
12713 target[i] = be32_to_cpu(source[i]);
12714}
12715
12716/*
12717 Ops array is stored in the following format:
12718 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12719 */
1191cb83 12720static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 12721{
ab6ad5a4
EG		 12722 const __be32 *source = (const __be32 *)_source;
12723 struct raw_op *target = (struct raw_op *)_target;
94a78b79 12724 u32 i, j, tmp;
94a78b79 12725
ab6ad5a4 12726 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 12727 tmp = be32_to_cpu(source[j]);
12728 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 12729 target[i].offset = tmp & 0xffffff;
12730 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 12731 }
12732}
ab6ad5a4 12733
1aa8b471 12734/* IRO array is stored in the following format:
523224a3
DK		 12735 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12736 */
1191cb83 12737static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 12738{
12739 const __be32 *source = (const __be32 *)_source;
12740 struct iro *target = (struct iro *)_target;
12741 u32 i, j, tmp;
12742
12743 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12744 target[i].base = be32_to_cpu(source[j]);
12745 j++;
12746 tmp = be32_to_cpu(source[j]);
12747 target[i].m1 = (tmp >> 16) & 0xffff;
12748 target[i].m2 = tmp & 0xffff;
12749 j++;
12750 tmp = be32_to_cpu(source[j]);
12751 target[i].m3 = (tmp >> 16) & 0xffff;
12752 target[i].size = tmp & 0xffff;
12753 j++;
12754 }
12755}
12756
1191cb83 12757static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12758{
ab6ad5a4
EG		 12759 const __be16 *source = (const __be16 *)_source;
12760 u16 *target = (u16 *)_target;
94a78b79 12761 u32 i;
94a78b79
VZ		 12762
12763 for (i = 0; i < n/2; i++)
12764 target[i] = be16_to_cpu(source[i]);
12765}
12766
7995c64e
JP		 12767#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12768do { \
12769 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12770 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 12771 if (!bp->arr) \
7995c64e 12772 goto lbl; \
7995c64e
JP		 12773 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12774 (u8 *)bp->arr, len); \
12775} while (0)
94a78b79 12776
3b603066 12777static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 12778{
c0ea452e 12779 const char *fw_file_name;
94a78b79 12780 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 12781 int rc;
94a78b79 12782
c0ea452e
MS		 12783 if (bp->firmware)
12784 return 0;
94a78b79 12785
c0ea452e
MS		 12786 if (CHIP_IS_E1(bp))
12787 fw_file_name = FW_FILE_NAME_E1;
12788 else if (CHIP_IS_E1H(bp))
12789 fw_file_name = FW_FILE_NAME_E1H;
12790 else if (!CHIP_IS_E1x(bp))
12791 fw_file_name = FW_FILE_NAME_E2;
12792 else {
12793 BNX2X_ERR("Unsupported chip revision\n");
12794 return -EINVAL;
12795 }
12796 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 12797
c0ea452e
MS		 12798 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12799 if (rc) {
12800 BNX2X_ERR("Can't load firmware file %s\n",
12801 fw_file_name);
12802 goto request_firmware_exit;
12803 }
eb2afd4a 12804
c0ea452e
MS		 12805 rc = bnx2x_check_firmware(bp);
12806 if (rc) {
12807 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12808 goto request_firmware_exit;
94a78b79
VZ		 12809 }
12810
12811 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12812
12813 /* Initialize the pointers to the init arrays */
12814 /* Blob */
12815 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12816
12817 /* Opcodes */
12818 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12819
12820 /* Offsets */
ab6ad5a4
EG		 12821 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12822 be16_to_cpu_n);
94a78b79
VZ		 12823
12824 /* STORMs firmware */
573f2035
EG		 12825 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12826 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12827 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12828 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12829 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12830 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12831 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12832 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12833 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12834 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12835 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12836 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12837 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12838 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12839 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12840 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 12841 /* IRO */
12842 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 12843
12844 return 0;
ab6ad5a4 12845
523224a3
DK		 12846iro_alloc_err:
12847 kfree(bp->init_ops_offsets);
94a78b79
VZ		 12848init_offsets_alloc_err:
12849 kfree(bp->init_ops);
12850init_ops_alloc_err:
12851 kfree(bp->init_data);
12852request_firmware_exit:
12853 release_firmware(bp->firmware);
127d0a19 12854 bp->firmware = NULL;
94a78b79
VZ		 12855
12856 return rc;
12857}
12858
619c5cb6
VZ		 12859static void bnx2x_release_firmware(struct bnx2x *bp)
12860{
12861 kfree(bp->init_ops_offsets);
12862 kfree(bp->init_ops);
12863 kfree(bp->init_data);
12864 release_firmware(bp->firmware);
eb2afd4a 12865 bp->firmware = NULL;
619c5cb6
VZ		 12866}
12867
619c5cb6
VZ		 12868static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12869 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12870 .init_hw_cmn = bnx2x_init_hw_common,
12871 .init_hw_port = bnx2x_init_hw_port,
12872 .init_hw_func = bnx2x_init_hw_func,
12873
12874 .reset_hw_cmn = bnx2x_reset_common,
12875 .reset_hw_port = bnx2x_reset_port,
12876 .reset_hw_func = bnx2x_reset_func,
12877
12878 .gunzip_init = bnx2x_gunzip_init,
12879 .gunzip_end = bnx2x_gunzip_end,
12880
12881 .init_fw = bnx2x_init_firmware,
12882 .release_fw = bnx2x_release_firmware,
12883};
12884
12885void bnx2x__init_func_obj(struct bnx2x *bp)
12886{
12887 /* Prepare DMAE related driver resources */
12888 bnx2x_setup_dmae(bp);
12889
12890 bnx2x_init_func_obj(bp, &bp->func_obj,
12891 bnx2x_sp(bp, func_rdata),
12892 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 12893 bnx2x_sp(bp, func_afex_rdata),
12894 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 12895 &bnx2x_func_sp_drv);
12896}
12897
12898/* must be called after sriov-enable */
1191cb83 12899static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 12900{
37ae41a9 12901 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 12902
290ca2bb
AE		 12903 if (IS_SRIOV(bp))
12904 cid_count += BNX2X_VF_CIDS;
12905
55c11941
MS		 12906 if (CNIC_SUPPORT(bp))
12907 cid_count += CNIC_CID_MAX;
290ca2bb 12908
523224a3
DK		 12909 return roundup(cid_count, QM_CID_ROUND);
12910}
f85582f8 12911
619c5cb6 12912/**
6383c0b3 12913 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 12914 *
12915 * @dev: pci device
12916 *
12917 */
60cad4e6 12918static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 12919{
ae2104be 12920 int index;
1ab4434c 12921 u16 control = 0;
619c5cb6 12922
6383c0b3
AE		 12923 /*
12924 * If MSI-X is not supported - return number of SBs needed to support
12925 * one fast path queue: one FP queue + SB for CNIC
12926 */
ae2104be 12927 if (!pdev->msix_cap) {
1ab4434c 12928 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 12929 return 1 + cnic_cnt;
1ab4434c
AE		 12930 }
12931 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 12932
6383c0b3
AE		 12933 /*
12934 * The value in the PCI configuration space is the index of the last
12935 * entry, namely one less than the actual size of the table, which is
12936 * exactly what we want to return from this function: number of all SBs
12937 * without the default SB.
1ab4434c 12938 * For VFs there is no default SB, then we return (index+1).
6383c0b3 12939 */
ae2104be 12940 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
619c5cb6 12941
1ab4434c 12942 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 12943
60cad4e6 12944 return index;
1ab4434c 12945}
523224a3 12946
1ab4434c
AE		 12947static int set_max_cos_est(int chip_id)
12948{
12949 switch (chip_id) {
f2e0899f
DK		 12950 case BCM57710:
12951 case BCM57711:
12952 case BCM57711E:
1ab4434c 12953 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 12954 case BCM57712:
619c5cb6 12955 case BCM57712_MF:
1ab4434c 12956 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 12957 case BCM57800:
12958 case BCM57800_MF:
12959 case BCM57810:
12960 case BCM57810_MF:
c3def943
YM		 12961 case BCM57840_4_10:
12962 case BCM57840_2_20:
1ab4434c 12963 case BCM57840_O:
c3def943 12964 case BCM57840_MFO:
619c5cb6 12965 case BCM57840_MF:
7e8e02df
BW		 12966 case BCM57811:
12967 case BCM57811_MF:
1ab4434c 12968 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 12969 case BCM57712_VF:
12970 case BCM57800_VF:
12971 case BCM57810_VF:
12972 case BCM57840_VF:
12973 case BCM57811_VF:
1ab4434c 12974 return 1;
f2e0899f 12975 default:
1ab4434c 12976 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 12977 return -ENODEV;
f2e0899f 12978 }
1ab4434c 12979}
f2e0899f 12980
1ab4434c
AE		 12981static int set_is_vf(int chip_id)
12982{
12983 switch (chip_id) {
12984 case BCM57712_VF:
12985 case BCM57800_VF:
12986 case BCM57810_VF:
12987 case BCM57840_VF:
12988 case BCM57811_VF:
12989 return true;
12990 default:
12991 return false;
12992 }
12993}
6383c0b3 12994
1ab4434c
AE		 12995static int bnx2x_init_one(struct pci_dev *pdev,
12996 const struct pci_device_id *ent)
12997{
12998 struct net_device *dev = NULL;
12999 struct bnx2x *bp;
b91e1a1a
YM		 13000 enum pcie_link_width pcie_width;
13001 enum pci_bus_speed pcie_speed;
1ab4434c
AE		 13002 int rc, max_non_def_sbs;
13003 int rx_count, tx_count, rss_count, doorbell_size;
13004 int max_cos_est;
13005 bool is_vf;
13006 int cnic_cnt;
13007
13008 /* An estimated maximum supported CoS number according to the chip
13009 * version.
13010 * We will try to roughly estimate the maximum number of CoSes this chip
13011 * may support in order to minimize the memory allocated for Tx
13012 * netdev_queue's. This number will be accurately calculated during the
13013 * initialization of bp->max_cos based on the chip versions AND chip
13014 * revision in the bnx2x_init_bp().
13015 */
13016 max_cos_est = set_max_cos_est(ent->driver_data);
13017 if (max_cos_est < 0)
13018 return max_cos_est;
13019 is_vf = set_is_vf(ent->driver_data);
13020 cnic_cnt = is_vf ? 0 : 1;
13021
60cad4e6
AE		 13022 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13023
13024 /* add another SB for VF as it has no default SB */
13025 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 13026
13027 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 13028 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 13029
13030 if (rss_count < 1)
13031 return -EINVAL;
6383c0b3
AE		 13032
13033 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 13034 rx_count = rss_count + cnic_cnt;
6383c0b3 13035
1ab4434c 13036 /* Maximum number of netdev Tx queues:
37ae41a9 13037 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 13038 */
55c11941 13039 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 13040
a2fbb9ea 13041 /* dev zeroed in init_etherdev */
6383c0b3 13042 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 13043 if (!dev)
a2fbb9ea
ET		 13044 return -ENOMEM;
13045
a2fbb9ea 13046 bp = netdev_priv(dev);
a2fbb9ea 13047
1ab4434c
AE		 13048 bp->flags = 0;
13049 if (is_vf)
13050 bp->flags |= IS_VF_FLAG;
13051
6383c0b3 13052 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 13053 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 13054 bp->msg_enable = debug;
55c11941 13055 bp->cnic_support = cnic_cnt;
4bd9b0ff 13056 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 13057
6383c0b3 13058 pci_set_drvdata(pdev, dev);
523224a3 13059
1ab4434c 13060 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 13061 if (rc < 0) {
13062 free_netdev(dev);
13063 return rc;
13064 }
13065
1ab4434c
AE		 13066 BNX2X_DEV_INFO("This is a %s function\n",
13067 IS_PF(bp) ? "physical" : "virtual");
55c11941 13068 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 13069 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 13070 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 13071 tx_count, rx_count);
60aa0509 13072
34f80b04 13073 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 13074 if (rc)
13075 goto init_one_exit;
13076
1ab4434c
AE		 13077 /* Map doorbells here as we need the real value of bp->max_cos which
13078 * is initialized in bnx2x_init_bp() to determine the number of
13079 * l2 connections.
6383c0b3 13080 */
1ab4434c 13081 if (IS_VF(bp)) {
1d6f3cd8 13082 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 13083 rc = bnx2x_vf_pci_alloc(bp);
13084 if (rc)
13085 goto init_one_exit;
1ab4434c
AE		 13086 } else {
13087 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13088 if (doorbell_size > pci_resource_len(pdev, 2)) {
13089 dev_err(&bp->pdev->dev,
13090 "Cannot map doorbells, bar size too small, aborting\n");
13091 rc = -ENOMEM;
13092 goto init_one_exit;
13093 }
13094 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13095 doorbell_size);
37ae41a9 13096 }
6383c0b3
AE		 13097 if (!bp->doorbells) {
13098 dev_err(&bp->pdev->dev,
13099 "Cannot map doorbell space, aborting\n");
13100 rc = -ENOMEM;
13101 goto init_one_exit;
13102 }
13103
be1f1ffa
AE		 13104 if (IS_VF(bp)) {
13105 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13106 if (rc)
13107 goto init_one_exit;
13108 }
13109
3c76feff
AE		 13110 /* Enable SRIOV if capability found in configuration space */
13111 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb
AE		 13112 if (rc)
13113 goto init_one_exit;
13114
523224a3 13115 /* calc qm_cid_count */
6383c0b3 13116 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 13117 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 13118
55c11941 13119 /* disable FCOE L2 queue for E1x*/
62ac0dc9 13120 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 13121 bp->flags |= NO_FCOE_FLAG;
13122
0e8d2ec5
MS		 13123 /* Set bp->num_queues for MSI-X mode*/
13124 bnx2x_set_num_queues(bp);
13125
25985edc 13126 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 13127 * needed.
d6214d7a 13128 */
1ab4434c
AE		 13129 rc = bnx2x_set_int_mode(bp);
13130 if (rc) {
13131 dev_err(&pdev->dev, "Cannot set interrupts\n");
13132 goto init_one_exit;
13133 }
04c46736 13134 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 13135
1ab4434c 13136 /* register the net device */
b340007f
VZ		 13137 rc = register_netdev(dev);
13138 if (rc) {
13139 dev_err(&pdev->dev, "Cannot register net device\n");
13140 goto init_one_exit;
13141 }
1ab4434c 13142 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 13143
ec6ba945
VZ		 13144 if (!NO_FCOE(bp)) {
13145 /* Add storage MAC address */
13146 rtnl_lock();
13147 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13148 rtnl_unlock();
13149 }
b91e1a1a
YM		 13150 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13151 pcie_speed == PCI_SPEED_UNKNOWN ||
13152 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13153 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13154 else
13155 BNX2X_DEV_INFO(
13156 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
ca1ee4b2
DK		 13157 board_info[ent->driver_data].name,
13158 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13159 pcie_width,
b91e1a1a
YM		 13160 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13161 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13162 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
ca1ee4b2
DK		 13163 "Unknown",
13164 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 13165
a2fbb9ea 13166 return 0;
34f80b04
EG		 13167
13168init_one_exit:
33d8e6a5
YM		 13169 bnx2x_disable_pcie_error_reporting(bp);
13170
34f80b04
EG		 13171 if (bp->regview)
13172 iounmap(bp->regview);
13173
1ab4434c 13174 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 13175 iounmap(bp->doorbells);
13176
13177 free_netdev(dev);
13178
13179 if (atomic_read(&pdev->enable_cnt) == 1)
13180 pci_release_regions(pdev);
13181
13182 pci_disable_device(pdev);
34f80b04
EG		 13183
13184 return rc;
a2fbb9ea
ET		 13185}
13186
b030ed2f
YM		 13187static void __bnx2x_remove(struct pci_dev *pdev,
13188 struct net_device *dev,
13189 struct bnx2x *bp,
13190 bool remove_netdev)
a2fbb9ea 13191{
ec6ba945
VZ		 13192 /* Delete storage MAC address */
13193 if (!NO_FCOE(bp)) {
13194 rtnl_lock();
13195 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13196 rtnl_unlock();
13197 }
ec6ba945 13198
98507672
SR		 13199#ifdef BCM_DCBNL
13200 /* Delete app tlvs from dcbnl */
13201 bnx2x_dcbnl_update_applist(bp, true);
13202#endif
13203
a6d3a5ba
BW		 13204 if (IS_PF(bp) &&
13205 !BP_NOMCP(bp) &&
13206 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13207 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13208
b030ed2f
YM		 13209 /* Close the interface - either directly or implicitly */
13210 if (remove_netdev) {
13211 unregister_netdev(dev);
13212 } else {
13213 rtnl_lock();
6ef5a92c 13214 dev_close(dev);
b030ed2f
YM		 13215 rtnl_unlock();
13216 }
a2fbb9ea 13217
78c3bcc5
AE		 13218 bnx2x_iov_remove_one(bp);
13219
084d6cbb 13220 /* Power on: we can't let PCI layer write to us while we are in D3 */
1ab4434c
AE		 13221 if (IS_PF(bp))
13222 bnx2x_set_power_state(bp, PCI_D0);
084d6cbb 13223
d6214d7a
DK		 13224 /* Disable MSI/MSI-X */
13225 bnx2x_disable_msi(bp);
f85582f8 13226
084d6cbb 13227 /* Power off */
1ab4434c
AE		 13228 if (IS_PF(bp))
13229 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 13230
72fd0718 13231 /* Make sure RESET task is not scheduled before continuing */
7be08a72 13232 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 13233
4513f925
AE		 13234 /* send message via vfpf channel to release the resources of this vf */
13235 if (IS_VF(bp))
13236 bnx2x_vfpf_release(bp);
72fd0718 13237
b030ed2f
YM		 13238 /* Assumes no further PCIe PM changes will occur */
13239 if (system_state == SYSTEM_POWER_OFF) {
13240 pci_wake_from_d3(pdev, bp->wol);
13241 pci_set_power_state(pdev, PCI_D3hot);
13242 }
13243
33d8e6a5 13244 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 13245 if (remove_netdev) {
13246 if (bp->regview)
13247 iounmap(bp->regview);
33d8e6a5 13248
d9aee591
YM		 13249 /* For vfs, doorbells are part of the regview and were unmapped
13250 * along with it. FW is only loaded by PF.
13251 */
13252 if (IS_PF(bp)) {
13253 if (bp->doorbells)
13254 iounmap(bp->doorbells);
eb2afd4a 13255
d9aee591 13256 bnx2x_release_firmware(bp);
e2a367f8
YM		 13257 } else {
13258 bnx2x_vf_pci_dealloc(bp);
d9aee591
YM		 13259 }
13260 bnx2x_free_mem_bp(bp);
523224a3 13261
b030ed2f 13262 free_netdev(dev);
34f80b04 13263
d9aee591
YM		 13264 if (atomic_read(&pdev->enable_cnt) == 1)
13265 pci_release_regions(pdev);
34f80b04 13266
5f6db130
YM		 13267 pci_disable_device(pdev);
13268 }
a2fbb9ea
ET		 13269}
13270
b030ed2f
YM		 13271static void bnx2x_remove_one(struct pci_dev *pdev)
13272{
13273 struct net_device *dev = pci_get_drvdata(pdev);
13274 struct bnx2x *bp;
13275
13276 if (!dev) {
13277 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13278 return;
13279 }
13280 bp = netdev_priv(dev);
13281
13282 __bnx2x_remove(pdev, dev, bp, true);
13283}
13284
f8ef6e44
YG		 13285static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13286{
7fa6f340 13287 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 13288
13289 bp->rx_mode = BNX2X_RX_MODE_NONE;
13290
55c11941
MS		 13291 if (CNIC_LOADED(bp))
13292 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13293
619c5cb6
VZ		 13294 /* Stop Tx */
13295 bnx2x_tx_disable(bp);
26614ba5
MS		 13296 /* Delete all NAPI objects */
13297 bnx2x_del_all_napi(bp);
55c11941
MS		 13298 if (CNIC_LOADED(bp))
13299 bnx2x_del_all_napi_cnic(bp);
7fa6f340 13300 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 13301
13302 del_timer_sync(&bp->timer);
0c0e6341 13303 cancel_delayed_work_sync(&bp->sp_task);
13304 cancel_delayed_work_sync(&bp->period_task);
619c5cb6 13305
7fa6f340
YM		 13306 spin_lock_bh(&bp->stats_lock);
13307 bp->stats_state = STATS_STATE_DISABLED;
13308 spin_unlock_bh(&bp->stats_lock);
f8ef6e44 13309
7fa6f340 13310 bnx2x_save_statistics(bp);
f8ef6e44 13311
619c5cb6
VZ		 13312 netif_carrier_off(bp->dev);
13313
f8ef6e44
YG		 13314 return 0;
13315}
13316
493adb1f
WX		 13317/**
13318 * bnx2x_io_error_detected - called when PCI error is detected
13319 * @pdev: Pointer to PCI device
13320 * @state: The current pci connection state
13321 *
13322 * This function is called after a PCI bus error affecting
13323 * this device has been detected.
13324 */
13325static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13326 pci_channel_state_t state)
13327{
13328 struct net_device *dev = pci_get_drvdata(pdev);
13329 struct bnx2x *bp = netdev_priv(dev);
13330
13331 rtnl_lock();
13332
7fa6f340
YM		 13333 BNX2X_ERR("IO error detected\n");
13334
493adb1f
WX		 13335 netif_device_detach(dev);
13336
07ce50e4
DN		 13337 if (state == pci_channel_io_perm_failure) {
13338 rtnl_unlock();
13339 return PCI_ERS_RESULT_DISCONNECT;
13340 }
13341
493adb1f 13342 if (netif_running(dev))
f8ef6e44 13343 bnx2x_eeh_nic_unload(bp);
493adb1f 13344
7fa6f340
YM		 13345 bnx2x_prev_path_mark_eeh(bp);
13346
493adb1f
WX		 13347 pci_disable_device(pdev);
13348
13349 rtnl_unlock();
13350
13351 /* Request a slot reset */
13352 return PCI_ERS_RESULT_NEED_RESET;
13353}
13354
13355/**
13356 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13357 * @pdev: Pointer to PCI device
13358 *
13359 * Restart the card from scratch, as if from a cold-boot.
13360 */
13361static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13362{
13363 struct net_device *dev = pci_get_drvdata(pdev);
13364 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 13365 int i;
493adb1f
WX		 13366
13367 rtnl_lock();
7fa6f340 13368 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 13369 if (pci_enable_device(pdev)) {
13370 dev_err(&pdev->dev,
13371 "Cannot re-enable PCI device after reset\n");
13372 rtnl_unlock();
13373 return PCI_ERS_RESULT_DISCONNECT;
13374 }
13375
13376 pci_set_master(pdev);
13377 pci_restore_state(pdev);
70632d0a 13378 pci_save_state(pdev);
493adb1f
WX		 13379
13380 if (netif_running(dev))
13381 bnx2x_set_power_state(bp, PCI_D0);
13382
7fa6f340
YM		 13383 if (netif_running(dev)) {
13384 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 13385
13386 /* MCP should have been reset; Need to wait for validity */
13387 bnx2x_init_shmem(bp);
13388
7fa6f340
YM		 13389 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13390 u32 v;
13391
13392 v = SHMEM2_RD(bp,
13393 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13394 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13395 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13396 }
13397 bnx2x_drain_tx_queues(bp);
13398 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13399 bnx2x_netif_stop(bp, 1);
13400 bnx2x_free_irq(bp);
13401
13402 /* Report UNLOAD_DONE to MCP */
13403 bnx2x_send_unload_done(bp, true);
13404
13405 bp->sp_state = 0;
13406 bp->port.pmf = 0;
13407
13408 bnx2x_prev_unload(bp);
13409
16a5fd92 13410 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 13411 * assume the FW will no longer write to the bnx2x driver.
13412 */
13413 bnx2x_squeeze_objects(bp);
13414 bnx2x_free_skbs(bp);
13415 for_each_rx_queue(bp, i)
13416 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13417 bnx2x_free_fp_mem(bp);
13418 bnx2x_free_mem(bp);
13419
13420 bp->state = BNX2X_STATE_CLOSED;
13421 }
13422
493adb1f
WX		 13423 rtnl_unlock();
13424
33d8e6a5
YM		 13425 /* If AER, perform cleanup of the PCIe registers */
13426 if (bp->flags & AER_ENABLED) {
13427 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13428 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13429 else
13430 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13431 }
13432
493adb1f
WX		 13433 return PCI_ERS_RESULT_RECOVERED;
13434}
13435
13436/**
13437 * bnx2x_io_resume - called when traffic can start flowing again
13438 * @pdev: Pointer to PCI device
13439 *
13440 * This callback is called when the error recovery driver tells us that
13441 * its OK to resume normal operation.
13442 */
13443static void bnx2x_io_resume(struct pci_dev *pdev)
13444{
13445 struct net_device *dev = pci_get_drvdata(pdev);
13446 struct bnx2x *bp = netdev_priv(dev);
13447
72fd0718 13448 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 13449 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 13450 return;
13451 }
13452
493adb1f
WX		 13453 rtnl_lock();
13454
7fa6f340
YM		 13455 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13456 DRV_MSG_SEQ_NUMBER_MASK;
13457
493adb1f 13458 if (netif_running(dev))
f8ef6e44 13459 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 13460
13461 netif_device_attach(dev);
13462
13463 rtnl_unlock();
13464}
13465
3646f0e5 13466static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 13467 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 13468 .slot_reset = bnx2x_io_slot_reset,
13469 .resume = bnx2x_io_resume,
493adb1f
WX		 13470};
13471
b030ed2f
YM		 13472static void bnx2x_shutdown(struct pci_dev *pdev)
13473{
13474 struct net_device *dev = pci_get_drvdata(pdev);
13475 struct bnx2x *bp;
13476
13477 if (!dev)
13478 return;
13479
13480 bp = netdev_priv(dev);
13481 if (!bp)
13482 return;
13483
13484 rtnl_lock();
13485 netif_device_detach(dev);
13486 rtnl_unlock();
13487
13488 /* Don't remove the netdevice, as there are scenarios which will cause
13489 * the kernel to hang, e.g., when trying to remove bnx2i while the
13490 * rootfs is mounted from SAN.
13491 */
13492 __bnx2x_remove(pdev, dev, bp, false);
13493}
13494
a2fbb9ea 13495static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 13496 .name = DRV_MODULE_NAME,
13497 .id_table = bnx2x_pci_tbl,
13498 .probe = bnx2x_init_one,
0329aba1 13499 .remove = bnx2x_remove_one,
493adb1f
WX		 13500 .suspend = bnx2x_suspend,
13501 .resume = bnx2x_resume,
13502 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 13503#ifdef CONFIG_BNX2X_SRIOV
13504 .sriov_configure = bnx2x_sriov_configure,
13505#endif
b030ed2f 13506 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 13507};
13508
13509static int __init bnx2x_init(void)
13510{
dd21ca6d
SG		 13511 int ret;
13512
7995c64e 13513 pr_info("%s", version);
938cf541 13514
1cf167f2
EG		 13515 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13516 if (bnx2x_wq == NULL) {
7995c64e 13517 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 13518 return -ENOMEM;
13519 }
370d4a26
YM		 13520 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13521 if (!bnx2x_iov_wq) {
13522 pr_err("Cannot create iov workqueue\n");
13523 destroy_workqueue(bnx2x_wq);
13524 return -ENOMEM;
13525 }
1cf167f2 13526
dd21ca6d
SG		 13527 ret = pci_register_driver(&bnx2x_pci_driver);
13528 if (ret) {
7995c64e 13529 pr_err("Cannot register driver\n");
dd21ca6d 13530 destroy_workqueue(bnx2x_wq);
370d4a26 13531 destroy_workqueue(bnx2x_iov_wq);
dd21ca6d
SG		 13532 }
13533 return ret;
a2fbb9ea
ET		 13534}
13535
13536static void __exit bnx2x_cleanup(void)
13537{
452427b0 13538 struct list_head *pos, *q;
d76a6111 13539
a2fbb9ea 13540 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 13541
13542 destroy_workqueue(bnx2x_wq);
370d4a26 13543 destroy_workqueue(bnx2x_iov_wq);
452427b0 13544
16a5fd92 13545 /* Free globally allocated resources */
452427b0
YM		 13546 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13547 struct bnx2x_prev_path_list *tmp =
13548 list_entry(pos, struct bnx2x_prev_path_list, list);
13549 list_del(pos);
13550 kfree(tmp);
13551 }
a2fbb9ea
ET		 13552}
13553
3deb8167
YR		 13554void bnx2x_notify_link_changed(struct bnx2x *bp)
13555{
13556 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13557}
13558
a2fbb9ea
ET		 13559module_init(bnx2x_init);
13560module_exit(bnx2x_cleanup);
13561
619c5cb6
VZ		 13562/**
13563 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13564 *
13565 * @bp: driver handle
13566 * @set: set or clear the CAM entry
13567 *
16a5fd92 13568 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 13569 * Return 0 if success, -ENODEV if ramrod doesn't return.
13570 */
1191cb83 13571static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 13572{
13573 unsigned long ramrod_flags = 0;
13574
13575 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13576 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13577 &bp->iscsi_l2_mac_obj, true,
13578 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13579}
993ac7b5
MC		 13580
13581/* count denotes the number of new completions we have seen */
13582static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13583{
13584 struct eth_spe *spe;
a052997e 13585 int cxt_index, cxt_offset;
993ac7b5
MC		 13586
13587#ifdef BNX2X_STOP_ON_ERROR
13588 if (unlikely(bp->panic))
13589 return;
13590#endif
13591
13592 spin_lock_bh(&bp->spq_lock);
c2bff63f 13593 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 13594 bp->cnic_spq_pending -= count;
13595
c2bff63f
DK		 13596 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13597 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13598 & SPE_HDR_CONN_TYPE) >>
13599 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 13600 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13601 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 13602
13603 /* Set validation for iSCSI L2 client before sending SETUP
13604 * ramrod
13605 */
13606 if (type == ETH_CONNECTION_TYPE) {
a052997e 13607 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 13608 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 13609 ILT_PAGE_CIDS;
37ae41a9 13610 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 13611 (cxt_index * ILT_PAGE_CIDS);
13612 bnx2x_set_ctx_validation(bp,
13613 &bp->context[cxt_index].
13614 vcxt[cxt_offset].eth,
37ae41a9 13615 BNX2X_ISCSI_ETH_CID(bp));
a052997e 13616 }
c2bff63f
DK		 13617 }
13618
619c5cb6
VZ		 13619 /*
13620 * There may be not more than 8 L2, not more than 8 L5 SPEs
13621 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 13622 * COMMON ramrods is not more than the EQ and SPQ can
13623 * accommodate.
c2bff63f 13624 */
6e30dd4e
VZ		 13625 if (type == ETH_CONNECTION_TYPE) {
13626 if (!atomic_read(&bp->cq_spq_left))
13627 break;
13628 else
13629 atomic_dec(&bp->cq_spq_left);
13630 } else if (type == NONE_CONNECTION_TYPE) {
13631 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 13632 break;
13633 else
6e30dd4e 13634 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 13635 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13636 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 13637 if (bp->cnic_spq_pending >=
13638 bp->cnic_eth_dev.max_kwqe_pending)
13639 break;
13640 else
13641 bp->cnic_spq_pending++;
13642 } else {
13643 BNX2X_ERR("Unknown SPE type: %d\n", type);
13644 bnx2x_panic();
993ac7b5 13645 break;
c2bff63f 13646 }
993ac7b5
MC		 13647
13648 spe = bnx2x_sp_get_next(bp);
13649 *spe = *bp->cnic_kwq_cons;
13650
51c1a580 13651 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 13652 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13653
13654 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13655 bp->cnic_kwq_cons = bp->cnic_kwq;
13656 else
13657 bp->cnic_kwq_cons++;
13658 }
13659 bnx2x_sp_prod_update(bp);
13660 spin_unlock_bh(&bp->spq_lock);
13661}
13662
13663static int bnx2x_cnic_sp_queue(struct net_device *dev,
13664 struct kwqe_16 *kwqes[], u32 count)
13665{
13666 struct bnx2x *bp = netdev_priv(dev);
13667 int i;
13668
13669#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 13670 if (unlikely(bp->panic)) {
13671 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 13672 return -EIO;
51c1a580 13673 }
993ac7b5
MC		 13674#endif
13675
95c6c616
AE		 13676 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13677 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 13678 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 13679 return -EAGAIN;
13680 }
13681
993ac7b5
MC		 13682 spin_lock_bh(&bp->spq_lock);
13683
13684 for (i = 0; i < count; i++) {
13685 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13686
13687 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13688 break;
13689
13690 *bp->cnic_kwq_prod = *spe;
13691
13692 bp->cnic_kwq_pending++;
13693
51c1a580 13694 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 13695 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 13696 spe->data.update_data_addr.hi,
13697 spe->data.update_data_addr.lo,
993ac7b5
MC		 13698 bp->cnic_kwq_pending);
13699
13700 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13701 bp->cnic_kwq_prod = bp->cnic_kwq;
13702 else
13703 bp->cnic_kwq_prod++;
13704 }
13705
13706 spin_unlock_bh(&bp->spq_lock);
13707
13708 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13709 bnx2x_cnic_sp_post(bp, 0);
13710
13711 return i;
13712}
13713
13714static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13715{
13716 struct cnic_ops *c_ops;
13717 int rc = 0;
13718
13719 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 13720 c_ops = rcu_dereference_protected(bp->cnic_ops,
13721 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 13722 if (c_ops)
13723 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13724 mutex_unlock(&bp->cnic_mutex);
13725
13726 return rc;
13727}
13728
13729static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13730{
13731 struct cnic_ops *c_ops;
13732 int rc = 0;
13733
13734 rcu_read_lock();
13735 c_ops = rcu_dereference(bp->cnic_ops);
13736 if (c_ops)
13737 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13738 rcu_read_unlock();
13739
13740 return rc;
13741}
13742
13743/*
13744 * for commands that have no data
13745 */
9f6c9258 13746int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 13747{
13748 struct cnic_ctl_info ctl = {0};
13749
13750 ctl.cmd = cmd;
13751
13752 return bnx2x_cnic_ctl_send(bp, &ctl);
13753}
13754
619c5cb6 13755static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 13756{
619c5cb6 13757 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 13758
13759 /* first we tell CNIC and only then we count this as a completion */
13760 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13761 ctl.data.comp.cid = cid;
619c5cb6 13762 ctl.data.comp.error = err;
993ac7b5
MC		 13763
13764 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 13765 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 13766}
13767
619c5cb6
VZ		 13768/* Called with netif_addr_lock_bh() taken.
13769 * Sets an rx_mode config for an iSCSI ETH client.
13770 * Doesn't block.
13771 * Completion should be checked outside.
13772 */
13773static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13774{
13775 unsigned long accept_flags = 0, ramrod_flags = 0;
13776 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13777 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13778
13779 if (start) {
13780 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13781 * because it's the only way for UIO Queue to accept
13782 * multicasts (in non-promiscuous mode only one Queue per
13783 * function will receive multicast packets (leading in our
13784 * case).
13785 */
13786 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13787 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13788 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13789 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13790
13791 /* Clear STOP_PENDING bit if START is requested */
13792 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13793
13794 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13795 } else
13796 /* Clear START_PENDING bit if STOP is requested */
13797 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13798
13799 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13800 set_bit(sched_state, &bp->sp_state);
13801 else {
13802 __set_bit(RAMROD_RX, &ramrod_flags);
13803 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13804 ramrod_flags);
13805 }
13806}
13807
993ac7b5
MC		 13808static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13809{
13810 struct bnx2x *bp = netdev_priv(dev);
13811 int rc = 0;
13812
13813 switch (ctl->cmd) {
13814 case DRV_CTL_CTXTBL_WR_CMD: {
13815 u32 index = ctl->data.io.offset;
13816 dma_addr_t addr = ctl->data.io.dma_addr;
13817
13818 bnx2x_ilt_wr(bp, index, addr);
13819 break;
13820 }
13821
c2bff63f
DK		 13822 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13823 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 13824
13825 bnx2x_cnic_sp_post(bp, count);
13826 break;
13827 }
13828
13829 /* rtnl_lock is held. */
13830 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 13831 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13832 unsigned long sp_bits = 0;
13833
13834 /* Configure the iSCSI classification object */
13835 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13836 cp->iscsi_l2_client_id,
13837 cp->iscsi_l2_cid, BP_FUNC(bp),
13838 bnx2x_sp(bp, mac_rdata),
13839 bnx2x_sp_mapping(bp, mac_rdata),
13840 BNX2X_FILTER_MAC_PENDING,
13841 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13842 &bp->macs_pool);
ec6ba945 13843
523224a3 13844 /* Set iSCSI MAC address */
619c5cb6
VZ		 13845 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13846 if (rc)
13847 break;
523224a3
DK		 13848
13849 mmiowb();
13850 barrier();
13851
619c5cb6
VZ		 13852 /* Start accepting on iSCSI L2 ring */
13853
13854 netif_addr_lock_bh(dev);
13855 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13856 netif_addr_unlock_bh(dev);
13857
13858 /* bits to wait on */
13859 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13860 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13861
13862 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13863 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 13864
993ac7b5
MC		 13865 break;
13866 }
13867
13868 /* rtnl_lock is held. */
13869 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 13870 unsigned long sp_bits = 0;
993ac7b5 13871
523224a3 13872 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 13873 netif_addr_lock_bh(dev);
13874 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13875 netif_addr_unlock_bh(dev);
13876
13877 /* bits to wait on */
13878 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13879 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13880
13881 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13882 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 13883
13884 mmiowb();
13885 barrier();
13886
13887 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 13888 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13889 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 13890 break;
13891 }
c2bff63f
DK		 13892 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13893 int count = ctl->data.credit.credit_count;
13894
4e857c58 13895 smp_mb__before_atomic();
6e30dd4e 13896 atomic_add(count, &bp->cq_spq_left);
4e857c58 13897 smp_mb__after_atomic();
c2bff63f
DK		 13898 break;
13899 }
1d187b34 13900 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 13901 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 13902
13903 if (CHIP_IS_E3(bp)) {
13904 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 13905 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13906 int path = BP_PATH(bp);
13907 int port = BP_PORT(bp);
13908 int i;
13909 u32 scratch_offset;
13910 u32 *host_addr;
1d187b34 13911
2e499d3c 13912 /* first write capability to shmem2 */
1d187b34
BW		 13913 if (ulp_type == CNIC_ULP_ISCSI)
13914 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13915 else if (ulp_type == CNIC_ULP_FCOE)
13916 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13917 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 13918
13919 if ((ulp_type != CNIC_ULP_FCOE) ||
13920 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13921 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13922 break;
13923
13924 /* if reached here - should write fcoe capabilities */
13925 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13926 if (!scratch_offset)
13927 break;
13928 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13929 fcoe_features[path][port]);
13930 host_addr = (u32 *) &(ctl->data.register_data.
13931 fcoe_features);
13932 for (i = 0; i < sizeof(struct fcoe_capabilities);
13933 i += 4)
13934 REG_WR(bp, scratch_offset + i,
13935 *(host_addr + i/4));
1d187b34 13936 }
42f8277f 13937 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 13938 break;
13939 }
2e499d3c 13940
1d187b34
BW		 13941 case DRV_CTL_ULP_UNREGISTER_CMD: {
13942 int ulp_type = ctl->data.ulp_type;
13943
13944 if (CHIP_IS_E3(bp)) {
13945 int idx = BP_FW_MB_IDX(bp);
13946 u32 cap;
13947
13948 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13949 if (ulp_type == CNIC_ULP_ISCSI)
13950 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13951 else if (ulp_type == CNIC_ULP_FCOE)
13952 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13953 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13954 }
42f8277f 13955 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 13956 break;
13957 }
993ac7b5
MC		 13958
13959 default:
13960 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13961 rc = -EINVAL;
13962 }
13963
13964 return rc;
13965}
13966
9f6c9258 13967void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 13968{
13969 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13970
13971 if (bp->flags & USING_MSIX_FLAG) {
13972 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13973 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13974 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13975 } else {
13976 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13977 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13978 }
619c5cb6 13979 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 13980 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13981 else
13982 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13983
619c5cb6
VZ		 13984 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13985 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 13986 cp->irq_arr[1].status_blk = bp->def_status_blk;
13987 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 13988 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 13989
13990 cp->num_irq = 2;
13991}
13992
37ae41a9
MS		 13993void bnx2x_setup_cnic_info(struct bnx2x *bp)
13994{
13995 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13996
37ae41a9
MS		 13997 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13998 bnx2x_cid_ilt_lines(bp);
13999 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14000 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14001 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14002
f78afb35
MC		 14003 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14004 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14005 cp->iscsi_l2_cid);
14006
37ae41a9
MS		 14007 if (NO_ISCSI_OOO(bp))
14008 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14009}
14010
993ac7b5
MC		 14011static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14012 void *data)
14013{
14014 struct bnx2x *bp = netdev_priv(dev);
14015 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 14016 int rc;
14017
14018 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 14019
51c1a580
MS		 14020 if (ops == NULL) {
14021 BNX2X_ERR("NULL ops received\n");
993ac7b5 14022 return -EINVAL;
51c1a580 14023 }
993ac7b5 14024
55c11941
MS		 14025 if (!CNIC_SUPPORT(bp)) {
14026 BNX2X_ERR("Can't register CNIC when not supported\n");
14027 return -EOPNOTSUPP;
14028 }
14029
14030 if (!CNIC_LOADED(bp)) {
14031 rc = bnx2x_load_cnic(bp);
14032 if (rc) {
14033 BNX2X_ERR("CNIC-related load failed\n");
14034 return rc;
14035 }
55c11941
MS		 14036 }
14037
14038 bp->cnic_enabled = true;
14039
993ac7b5
MC		 14040 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14041 if (!bp->cnic_kwq)
14042 return -ENOMEM;
14043
14044 bp->cnic_kwq_cons = bp->cnic_kwq;
14045 bp->cnic_kwq_prod = bp->cnic_kwq;
14046 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14047
14048 bp->cnic_spq_pending = 0;
14049 bp->cnic_kwq_pending = 0;
14050
14051 bp->cnic_data = data;
14052
14053 cp->num_irq = 0;
619c5cb6 14054 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 14055 cp->iro_arr = bp->iro_arr;
993ac7b5 14056
993ac7b5 14057 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 14058
993ac7b5
MC		 14059 rcu_assign_pointer(bp->cnic_ops, ops);
14060
42f8277f
YM		 14061 /* Schedule driver to read CNIC driver versions */
14062 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14063
993ac7b5
MC		 14064 return 0;
14065}
14066
14067static int bnx2x_unregister_cnic(struct net_device *dev)
14068{
14069 struct bnx2x *bp = netdev_priv(dev);
14070 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14071
14072 mutex_lock(&bp->cnic_mutex);
993ac7b5 14073 cp->drv_state = 0;
2cfa5a04 14074 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 14075 mutex_unlock(&bp->cnic_mutex);
14076 synchronize_rcu();
fea75645 14077 bp->cnic_enabled = false;
993ac7b5
MC		 14078 kfree(bp->cnic_kwq);
14079 bp->cnic_kwq = NULL;
14080
14081 return 0;
14082}
14083
a8f47eb7 14084static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 14085{
14086 struct bnx2x *bp = netdev_priv(dev);
14087 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14088
2ba45142
VZ		 14089 /* If both iSCSI and FCoE are disabled - return NULL in
14090 * order to indicate CNIC that it should not try to work
14091 * with this device.
14092 */
14093 if (NO_ISCSI(bp) && NO_FCOE(bp))
14094 return NULL;
14095
993ac7b5
MC		 14096 cp->drv_owner = THIS_MODULE;
14097 cp->chip_id = CHIP_ID(bp);
14098 cp->pdev = bp->pdev;
14099 cp->io_base = bp->regview;
14100 cp->io_base2 = bp->doorbells;
14101 cp->max_kwqe_pending = 8;
523224a3 14102 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 14103 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14104 bnx2x_cid_ilt_lines(bp);
993ac7b5 14105 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 14106 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 14107 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14108 cp->drv_ctl = bnx2x_drv_ctl;
14109 cp->drv_register_cnic = bnx2x_register_cnic;
14110 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 14111 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 14112 cp->iscsi_l2_client_id =
14113 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 14114 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 14115
2ba45142
VZ		 14116 if (NO_ISCSI_OOO(bp))
14117 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14118
14119 if (NO_ISCSI(bp))
14120 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14121
14122 if (NO_FCOE(bp))
14123 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14124
51c1a580
MS		 14125 BNX2X_DEV_INFO(
14126 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 14127 cp->ctx_blk_size,
14128 cp->ctx_tbl_offset,
14129 cp->ctx_tbl_len,
14130 cp->starting_cid);
993ac7b5
MC		 14131 return cp;
14132}
993ac7b5 14133
a8f47eb7 14134static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 14135{
6411280a
AE		 14136 struct bnx2x *bp = fp->bp;
14137 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 14138
6411280a
AE		 14139 if (IS_VF(bp))
14140 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14141 else if (!CHIP_IS_E1x(bp))
14142 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14143 else
14144 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 14145
6411280a 14146 return offset;
8d9ac297 14147}
381ac16b 14148
6411280a
AE		 14149/* called only on E1H or E2.
14150 * When pretending to be PF, the pretend value is the function number 0...7
14151 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14152 * combination
14153 */
14154int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 14155{
6411280a 14156 u32 pretend_reg;
381ac16b 14157
23826850 14158 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 14159 return -1;
381ac16b 14160
6411280a
AE		 14161 /* get my own pretend register */
14162 pretend_reg = bnx2x_get_pretend_reg(bp);
14163 REG_WR(bp, pretend_reg, pretend_func_val);
14164 REG_RD(bp, pretend_reg);
381ac16b
AE		 14165 return 0;
14166}
Linux 6.x block layer and io_uring tree(s)