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mlx4_en: Byte Queue Limit support
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/dma-mapping.h>
35#include <linux/bitops.h>
36#include <linux/irq.h>
37#include <linux/delay.h>
38#include <asm/byteorder.h>
39#include <linux/time.h>
40#include <linux/ethtool.h>
41#include <linux/mii.h>
0c6671b0 42#include <linux/if_vlan.h>
a2fbb9ea 43#include <net/ip.h>
619c5cb6 44#include <net/ipv6.h>
a2fbb9ea
ET		 45#include <net/tcp.h>
46#include <net/checksum.h>
34f80b04 47#include <net/ip6_checksum.h>
a2fbb9ea
ET		 48#include <linux/workqueue.h>
49#include <linux/crc32.h>
34f80b04 50#include <linux/crc32c.h>
a2fbb9ea
ET		 51#include <linux/prefetch.h>
52#include <linux/zlib.h>
a2fbb9ea 53#include <linux/io.h>
452427b0 54#include <linux/semaphore.h>
45229b42 55#include <linux/stringify.h>
7ab24bfd 56#include <linux/vmalloc.h>
a2fbb9ea 57
a2fbb9ea
ET		 58#include "bnx2x.h"
59#include "bnx2x_init.h"
94a78b79 60#include "bnx2x_init_ops.h"
9f6c9258 61#include "bnx2x_cmn.h"
e4901dde 62#include "bnx2x_dcb.h"
042181f5 63#include "bnx2x_sp.h"
a2fbb9ea 64
94a78b79
VZ		 65#include <linux/firmware.h>
66#include "bnx2x_fw_file_hdr.h"
67/* FW files */
45229b42
BH		 68#define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 76
34f80b04
EG		 77/* Time in jiffies before concluding the transmitter is hung */
78#define TX_TIMEOUT (5*HZ)
a2fbb9ea 79
53a10565 80static char version[] __devinitdata =
619c5cb6 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
83
24e3fcef 84MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 85MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
a2fbb9ea
ET		 89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 91MODULE_FIRMWARE(FW_FILE_NAME_E1);
92MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 93MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 94
ca00392c 95
d6214d7a 96int num_queues;
54b9ddaa 97module_param(num_queues, int, 0);
96305234
DK		 98MODULE_PARM_DESC(num_queues,
99 " Set number of queues (default is as a number of CPUs)");
555f6c78 100
19680c48 101static int disable_tpa;
19680c48 102module_param(disable_tpa, int, 0);
9898f86d 103MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 104
9ee3d37b
DK		 105#define INT_MODE_INTx 1
106#define INT_MODE_MSI 2
8badd27a
EG		 107static int int_mode;
108module_param(int_mode, int, 0);
619c5cb6 109MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 110 "(1 INT#x; 2 MSI)");
8badd27a 111
a18f5128
EG		 112static int dropless_fc;
113module_param(dropless_fc, int, 0);
114MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
115
8d5726c4
EG		 116static int mrrs = -1;
117module_param(mrrs, int, 0);
118MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
119
9898f86d 120static int debug;
a2fbb9ea 121module_param(debug, int, 0);
9898f86d
EG		 122MODULE_PARM_DESC(debug, " Default debug msglevel");
123
a2fbb9ea 124
619c5cb6
VZ		 125
126struct workqueue_struct *bnx2x_wq;
ec6ba945 127
a2fbb9ea
ET		 128enum bnx2x_board_type {
129 BCM57710 = 0,
619c5cb6
VZ		 130 BCM57711,
131 BCM57711E,
132 BCM57712,
133 BCM57712_MF,
134 BCM57800,
135 BCM57800_MF,
136 BCM57810,
137 BCM57810_MF,
138 BCM57840,
7e8e02df
BW		 139 BCM57840_MF,
140 BCM57811,
141 BCM57811_MF
a2fbb9ea
ET		 142};
143
34f80b04 144/* indexed by board_type, above */
53a10565 145static struct {
a2fbb9ea
ET		 146 char *name;
147} board_info[] __devinitdata = {
619c5cb6
VZ		 148 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
149 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
150 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
151 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
152 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
153 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
154 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
155 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
156 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
157 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
7e8e02df
BW		 158 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
159 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"},
160 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"},
a2fbb9ea
ET		 161};
162
619c5cb6
VZ		 163#ifndef PCI_DEVICE_ID_NX2_57710
164#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
165#endif
166#ifndef PCI_DEVICE_ID_NX2_57711
167#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
168#endif
169#ifndef PCI_DEVICE_ID_NX2_57711E
170#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
171#endif
172#ifndef PCI_DEVICE_ID_NX2_57712
173#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
174#endif
175#ifndef PCI_DEVICE_ID_NX2_57712_MF
176#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
177#endif
178#ifndef PCI_DEVICE_ID_NX2_57800
179#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
180#endif
181#ifndef PCI_DEVICE_ID_NX2_57800_MF
182#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
183#endif
184#ifndef PCI_DEVICE_ID_NX2_57810
185#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
186#endif
187#ifndef PCI_DEVICE_ID_NX2_57810_MF
188#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
189#endif
190#ifndef PCI_DEVICE_ID_NX2_57840
191#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
192#endif
193#ifndef PCI_DEVICE_ID_NX2_57840_MF
194#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
195#endif
7e8e02df
BW		 196#ifndef PCI_DEVICE_ID_NX2_57811
197#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
198#endif
199#ifndef PCI_DEVICE_ID_NX2_57811_MF
200#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
201#endif
a3aa1884 202static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
213 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
7e8e02df
BW		 214 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
215 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
a2fbb9ea
ET		 216 { 0 }
217};
218
219MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
220
452427b0
YM		 221/* Global resources for unloading a previously loaded device */
222#define BNX2X_PREV_WAIT_NEEDED 1
223static DEFINE_SEMAPHORE(bnx2x_prev_sem);
224static LIST_HEAD(bnx2x_prev_list);
a2fbb9ea
ET		 225/****************************************************************************
226* General service functions
227****************************************************************************/
228
619c5cb6
VZ		 229static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
230 u32 addr, dma_addr_t mapping)
231{
232 REG_WR(bp, addr, U64_LO(mapping));
233 REG_WR(bp, addr + 4, U64_HI(mapping));
234}
235
236static inline void storm_memset_spq_addr(struct bnx2x *bp,
237 dma_addr_t mapping, u16 abs_fid)
238{
239 u32 addr = XSEM_REG_FAST_MEMORY +
240 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
241
242 __storm_memset_dma_mapping(bp, addr, mapping);
243}
244
245static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
246 u16 pf_id)
523224a3 247{
619c5cb6
VZ		 248 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
249 pf_id);
250 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
251 pf_id);
252 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
253 pf_id);
254 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
255 pf_id);
523224a3
DK		 256}
257
619c5cb6
VZ		 258static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
259 u8 enable)
260{
261 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
262 enable);
263 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
264 enable);
265 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
266 enable);
267 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
268 enable);
269}
523224a3
DK		 270
271static inline void storm_memset_eq_data(struct bnx2x *bp,
272 struct event_ring_data *eq_data,
273 u16 pfid)
274{
275 size_t size = sizeof(struct event_ring_data);
276
277 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
278
279 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
280}
281
282static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
283 u16 pfid)
284{
285 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
286 REG_WR16(bp, addr, eq_prod);
287}
288
a2fbb9ea
ET		 289/* used only at init
290 * locking is done by mcp
291 */
8d96286a 292static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 293{
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
298}
299
a2fbb9ea
ET		 300static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
301{
302 u32 val;
303
304 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
305 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
306 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
307 PCICFG_VENDOR_ID_OFFSET);
308
309 return val;
310}
a2fbb9ea 311
f2e0899f
DK		 312#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
313#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
314#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
315#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
316#define DMAE_DP_DST_NONE "dst_addr [none]"
317
f2e0899f 318
a2fbb9ea 319/* copy command into DMAE command memory and set DMAE command go */
6c719d00 320void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 321{
322 u32 cmd_offset;
323 int i;
324
325 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
326 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
327 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 328 }
329 REG_WR(bp, dmae_reg_go_c[idx], 1);
330}
331
f2e0899f 332u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 333{
f2e0899f
DK		 334 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
335 DMAE_CMD_C_ENABLE);
336}
ad8d3948 337
f2e0899f
DK		 338u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
339{
340 return opcode & ~DMAE_CMD_SRC_RESET;
341}
ad8d3948 342
f2e0899f
DK		 343u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
344 bool with_comp, u8 comp_type)
345{
346 u32 opcode = 0;
347
348 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
349 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 350
f2e0899f
DK		 351 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
352
353 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 354 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
355 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 356 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 357
a2fbb9ea 358#ifdef __BIG_ENDIAN
f2e0899f 359 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 360#else
f2e0899f 361 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 362#endif
f2e0899f
DK		 363 if (with_comp)
364 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
365 return opcode;
366}
367
8d96286a 368static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
369 struct dmae_command *dmae,
370 u8 src_type, u8 dst_type)
f2e0899f
DK		 371{
372 memset(dmae, 0, sizeof(struct dmae_command));
373
374 /* set the opcode */
375 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
376 true, DMAE_COMP_PCI);
377
378 /* fill in the completion parameters */
379 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
380 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
381 dmae->comp_val = DMAE_COMP_VAL;
382}
383
384/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 385static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
386 struct dmae_command *dmae)
f2e0899f
DK		 387{
388 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 389 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 390 int rc = 0;
391
619c5cb6
VZ		 392 /*
393 * Lock the dmae channel. Disable BHs to prevent a dead-lock
394 * as long as this code is called both from syscall context and
395 * from ndo_set_rx_mode() flow that may be called from BH.
396 */
6e30dd4e 397 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 398
f2e0899f 399 /* reset completion */
a2fbb9ea
ET		 400 *wb_comp = 0;
401
f2e0899f
DK		 402 /* post the command on the channel used for initializations */
403 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 404
f2e0899f 405 /* wait for completion */
a2fbb9ea 406 udelay(5);
f2e0899f 407 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 408
95c6c616
AE		 409 if (!cnt ||
410 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
411 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 412 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 413 rc = DMAE_TIMEOUT;
414 goto unlock;
a2fbb9ea 415 }
ad8d3948 416 cnt--;
f2e0899f 417 udelay(50);
a2fbb9ea 418 }
f2e0899f
DK		 419 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
420 BNX2X_ERR("DMAE PCI error!\n");
421 rc = DMAE_PCI_ERROR;
422 }
423
f2e0899f 424unlock:
6e30dd4e 425 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 426 return rc;
427}
428
429void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
430 u32 len32)
431{
432 struct dmae_command dmae;
433
434 if (!bp->dmae_ready) {
435 u32 *data = bnx2x_sp(bp, wb_data[0]);
436
127a425e
AE		 437 if (CHIP_IS_E1(bp))
438 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
439 else
440 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 441 return;
442 }
443
444 /* set opcode and fixed command fields */
445 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
446
447 /* fill in addresses and len */
448 dmae.src_addr_lo = U64_LO(dma_addr);
449 dmae.src_addr_hi = U64_HI(dma_addr);
450 dmae.dst_addr_lo = dst_addr >> 2;
451 dmae.dst_addr_hi = 0;
452 dmae.len = len32;
453
f2e0899f
DK		 454 /* issue the command and wait for completion */
455 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 456}
457
c18487ee 458void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 459{
5ff7b6d4 460 struct dmae_command dmae;
ad8d3948
EG		 461
462 if (!bp->dmae_ready) {
463 u32 *data = bnx2x_sp(bp, wb_data[0]);
464 int i;
465
51c1a580 466 if (CHIP_IS_E1(bp))
127a425e
AE		 467 for (i = 0; i < len32; i++)
468 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 469 else
127a425e
AE		 470 for (i = 0; i < len32; i++)
471 data[i] = REG_RD(bp, src_addr + i*4);
472
ad8d3948
EG		 473 return;
474 }
475
f2e0899f
DK		 476 /* set opcode and fixed command fields */
477 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 478
f2e0899f 479 /* fill in addresses and len */
5ff7b6d4
EG		 480 dmae.src_addr_lo = src_addr >> 2;
481 dmae.src_addr_hi = 0;
482 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
483 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
484 dmae.len = len32;
ad8d3948 485
f2e0899f
DK		 486 /* issue the command and wait for completion */
487 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 488}
489
8d96286a 490static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
491 u32 addr, u32 len)
573f2035 492{
02e3c6cb 493 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 494 int offset = 0;
495
02e3c6cb 496 while (len > dmae_wr_max) {
573f2035 497 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 498 addr + offset, dmae_wr_max);
499 offset += dmae_wr_max * 4;
500 len -= dmae_wr_max;
573f2035
EG		 501 }
502
503 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
504}
505
a2fbb9ea
ET		 506static int bnx2x_mc_assert(struct bnx2x *bp)
507{
a2fbb9ea 508 char last_idx;
34f80b04
EG		 509 int i, rc = 0;
510 u32 row0, row1, row2, row3;
511
512 /* XSTORM */
513 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
514 XSTORM_ASSERT_LIST_INDEX_OFFSET);
515 if (last_idx)
516 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
517
518 /* print the asserts */
519 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
520
521 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
522 XSTORM_ASSERT_LIST_OFFSET(i));
523 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
524 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
525 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
526 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
527 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
528 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
529
530 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 531 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 532 i, row3, row2, row1, row0);
533 rc++;
534 } else {
535 break;
536 }
537 }
538
539 /* TSTORM */
540 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
541 TSTORM_ASSERT_LIST_INDEX_OFFSET);
542 if (last_idx)
543 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
544
545 /* print the asserts */
546 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
547
548 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
549 TSTORM_ASSERT_LIST_OFFSET(i));
550 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
551 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
552 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
553 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
554 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
555 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
556
557 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 558 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 559 i, row3, row2, row1, row0);
560 rc++;
561 } else {
562 break;
563 }
564 }
565
566 /* CSTORM */
567 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
568 CSTORM_ASSERT_LIST_INDEX_OFFSET);
569 if (last_idx)
570 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
571
572 /* print the asserts */
573 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
574
575 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
576 CSTORM_ASSERT_LIST_OFFSET(i));
577 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
578 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
579 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
580 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
581 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
582 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
583
584 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 585 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 586 i, row3, row2, row1, row0);
587 rc++;
588 } else {
589 break;
590 }
591 }
592
593 /* USTORM */
594 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
595 USTORM_ASSERT_LIST_INDEX_OFFSET);
596 if (last_idx)
597 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
598
599 /* print the asserts */
600 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
601
602 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
603 USTORM_ASSERT_LIST_OFFSET(i));
604 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
605 USTORM_ASSERT_LIST_OFFSET(i) + 4);
606 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
607 USTORM_ASSERT_LIST_OFFSET(i) + 8);
608 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
609 USTORM_ASSERT_LIST_OFFSET(i) + 12);
610
611 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 612 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 613 i, row3, row2, row1, row0);
614 rc++;
615 } else {
616 break;
a2fbb9ea
ET		 617 }
618 }
34f80b04 619
a2fbb9ea
ET		 620 return rc;
621}
c14423fe 622
7a25cc73 623void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 624{
7a25cc73 625 u32 addr, val;
a2fbb9ea 626 u32 mark, offset;
4781bfad 627 __be32 data[9];
a2fbb9ea 628 int word;
f2e0899f 629 u32 trace_shmem_base;
2145a920
VZ		 630 if (BP_NOMCP(bp)) {
631 BNX2X_ERR("NO MCP - can not dump\n");
632 return;
633 }
7a25cc73
DK		 634 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
635 (bp->common.bc_ver & 0xff0000) >> 16,
636 (bp->common.bc_ver & 0xff00) >> 8,
637 (bp->common.bc_ver & 0xff));
638
639 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
640 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 641 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 642
f2e0899f
DK		 643 if (BP_PATH(bp) == 0)
644 trace_shmem_base = bp->common.shmem_base;
645 else
646 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
de128804
DK		 647 addr = trace_shmem_base - 0x800;
648
649 /* validate TRCB signature */
650 mark = REG_RD(bp, addr);
651 if (mark != MFW_TRACE_SIGNATURE) {
652 BNX2X_ERR("Trace buffer signature is missing.");
653 return ;
654 }
655
656 /* read cyclic buffer pointer */
657 addr += 4;
cdaa7cb8 658 mark = REG_RD(bp, addr);
f2e0899f
DK		 659 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
660 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 661 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 662
7a25cc73 663 printk("%s", lvl);
f2e0899f 664 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 665 for (word = 0; word < 8; word++)
cdaa7cb8 666 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 667 data[8] = 0x0;
7995c64e 668 pr_cont("%s", (char *)data);
a2fbb9ea 669 }
cdaa7cb8 670 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 671 for (word = 0; word < 8; word++)
cdaa7cb8 672 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 673 data[8] = 0x0;
7995c64e 674 pr_cont("%s", (char *)data);
a2fbb9ea 675 }
7a25cc73
DK		 676 printk("%s" "end of fw dump\n", lvl);
677}
678
679static inline void bnx2x_fw_dump(struct bnx2x *bp)
680{
681 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 682}
683
6c719d00 684void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 685{
686 int i;
523224a3
DK		 687 u16 j;
688 struct hc_sp_status_block_data sp_sb_data;
689 int func = BP_FUNC(bp);
690#ifdef BNX2X_STOP_ON_ERROR
691 u16 start = 0, end = 0;
6383c0b3 692 u8 cos;
523224a3 693#endif
a2fbb9ea 694
66e855f3 695 bp->stats_state = STATS_STATE_DISABLED;
7a752993 696 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 697 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
698
a2fbb9ea
ET		 699 BNX2X_ERR("begin crash dump -----------------\n");
700
8440d2b6
EG		 701 /* Indices */
702 /* Common */
51c1a580 703 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
619c5cb6
VZ		 704 bp->def_idx, bp->def_att_idx, bp->attn_state,
705 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 706 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
707 bp->def_status_blk->atten_status_block.attn_bits,
708 bp->def_status_blk->atten_status_block.attn_bits_ack,
709 bp->def_status_blk->atten_status_block.status_block_id,
710 bp->def_status_blk->atten_status_block.attn_bits_index);
711 BNX2X_ERR(" def (");
712 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
713 pr_cont("0x%x%s",
f1deab50
JP		 714 bp->def_status_blk->sp_sb.index_values[i],
715 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
523224a3
DK		 716
717 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
718 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
719 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
720 i*sizeof(u32));
721
f1deab50 722 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
523224a3
DK		 723 sp_sb_data.igu_sb_id,
724 sp_sb_data.igu_seg_id,
725 sp_sb_data.p_func.pf_id,
726 sp_sb_data.p_func.vnic_id,
727 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 728 sp_sb_data.p_func.vf_valid,
729 sp_sb_data.state);
523224a3 730
8440d2b6 731
ec6ba945 732 for_each_eth_queue(bp, i) {
a2fbb9ea 733 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 734 int loop;
f2e0899f 735 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 736 struct hc_status_block_data_e1x sb_data_e1x;
737 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 738 CHIP_IS_E1x(bp) ?
739 sb_data_e1x.common.state_machine :
740 sb_data_e2.common.state_machine;
523224a3 741 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 742 CHIP_IS_E1x(bp) ?
743 sb_data_e1x.index_data :
744 sb_data_e2.index_data;
6383c0b3 745 u8 data_size, cos;
523224a3 746 u32 *sb_data_p;
6383c0b3 747 struct bnx2x_fp_txdata txdata;
523224a3
DK		 748
749 /* Rx */
51c1a580 750 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 751 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 752 fp->rx_comp_prod,
66e855f3 753 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 754 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 755 fp->rx_sge_prod, fp->last_max_sge,
523224a3 756 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 757
523224a3 758 /* Tx */
6383c0b3
AE		 759 for_each_cos_in_tx_queue(fp, cos)
760 {
761 txdata = fp->txdata[cos];
51c1a580 762 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 763 i, txdata.tx_pkt_prod,
764 txdata.tx_pkt_cons, txdata.tx_bd_prod,
765 txdata.tx_bd_cons,
766 le16_to_cpu(*txdata.tx_cons_sb));
767 }
523224a3 768
619c5cb6
VZ		 769 loop = CHIP_IS_E1x(bp) ?
770 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 771
772 /* host sb data */
773
ec6ba945
VZ		 774#ifdef BCM_CNIC
775 if (IS_FCOE_FP(fp))
776 continue;
777#endif
523224a3
DK		 778 BNX2X_ERR(" run indexes (");
779 for (j = 0; j < HC_SB_MAX_SM; j++)
780 pr_cont("0x%x%s",
781 fp->sb_running_index[j],
782 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
783
784 BNX2X_ERR(" indexes (");
785 for (j = 0; j < loop; j++)
786 pr_cont("0x%x%s",
787 fp->sb_index_values[j],
788 (j == loop - 1) ? ")" : " ");
789 /* fw sb data */
619c5cb6
VZ		 790 data_size = CHIP_IS_E1x(bp) ?
791 sizeof(struct hc_status_block_data_e1x) :
792 sizeof(struct hc_status_block_data_e2);
523224a3 793 data_size /= sizeof(u32);
619c5cb6
VZ		 794 sb_data_p = CHIP_IS_E1x(bp) ?
795 (u32 *)&sb_data_e1x :
796 (u32 *)&sb_data_e2;
523224a3
DK		 797 /* copy sb data in here */
798 for (j = 0; j < data_size; j++)
799 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
800 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
801 j * sizeof(u32));
802
619c5cb6 803 if (!CHIP_IS_E1x(bp)) {
51c1a580 804 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 805 sb_data_e2.common.p_func.pf_id,
806 sb_data_e2.common.p_func.vf_id,
807 sb_data_e2.common.p_func.vf_valid,
808 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 809 sb_data_e2.common.same_igu_sb_1b,
810 sb_data_e2.common.state);
f2e0899f 811 } else {
51c1a580 812 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 813 sb_data_e1x.common.p_func.pf_id,
814 sb_data_e1x.common.p_func.vf_id,
815 sb_data_e1x.common.p_func.vf_valid,
816 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 817 sb_data_e1x.common.same_igu_sb_1b,
818 sb_data_e1x.common.state);
f2e0899f 819 }
523224a3
DK		 820
821 /* SB_SMs data */
822 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 823 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
824 j, hc_sm_p[j].__flags,
825 hc_sm_p[j].igu_sb_id,
826 hc_sm_p[j].igu_seg_id,
827 hc_sm_p[j].time_to_expire,
828 hc_sm_p[j].timer_value);
523224a3
DK		 829 }
830
831 /* Indecies data */
832 for (j = 0; j < loop; j++) {
51c1a580 833 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 834 hc_index_p[j].flags,
835 hc_index_p[j].timeout);
836 }
8440d2b6 837 }
a2fbb9ea 838
523224a3 839#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 840 /* Rings */
841 /* Rx */
ec6ba945 842 for_each_rx_queue(bp, i) {
8440d2b6 843 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 844
845 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
846 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 847 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 848 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
849 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
850
c3eefaf6 851 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 852 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 853 }
854
3196a88a
EG		 855 start = RX_SGE(fp->rx_sge_prod);
856 end = RX_SGE(fp->last_max_sge);
8440d2b6 857 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 858 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
859 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
860
c3eefaf6
EG		 861 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
862 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 863 }
864
a2fbb9ea
ET		 865 start = RCQ_BD(fp->rx_comp_cons - 10);
866 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 867 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 868 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
869
c3eefaf6
EG		 870 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
871 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 872 }
873 }
874
8440d2b6 875 /* Tx */
ec6ba945 876 for_each_tx_queue(bp, i) {
8440d2b6 877 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3
AE		 878 for_each_cos_in_tx_queue(fp, cos) {
879 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
880
881 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
882 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
883 for (j = start; j != end; j = TX_BD(j + 1)) {
884 struct sw_tx_bd *sw_bd =
885 &txdata->tx_buf_ring[j];
886
51c1a580 887 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 888 i, cos, j, sw_bd->skb,
889 sw_bd->first_bd);
890 }
8440d2b6 891
6383c0b3
AE		 892 start = TX_BD(txdata->tx_bd_cons - 10);
893 end = TX_BD(txdata->tx_bd_cons + 254);
894 for (j = start; j != end; j = TX_BD(j + 1)) {
895 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 896
51c1a580 897 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 898 i, cos, j, tx_bd[0], tx_bd[1],
899 tx_bd[2], tx_bd[3]);
900 }
8440d2b6
EG		 901 }
902 }
523224a3 903#endif
34f80b04 904 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 905 bnx2x_mc_assert(bp);
906 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 907}
908
619c5cb6
VZ		 909/*
910 * FLR Support for E2
911 *
912 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
913 * initialization.
914 */
915#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
89db4ad8
AE		 916#define FLR_WAIT_INTERVAL 50 /* usec */
917#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 918
919struct pbf_pN_buf_regs {
920 int pN;
921 u32 init_crd;
922 u32 crd;
923 u32 crd_freed;
924};
925
926struct pbf_pN_cmd_regs {
927 int pN;
928 u32 lines_occup;
929 u32 lines_freed;
930};
931
932static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
933 struct pbf_pN_buf_regs *regs,
934 u32 poll_count)
935{
936 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
937 u32 cur_cnt = poll_count;
938
939 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
940 crd = crd_start = REG_RD(bp, regs->crd);
941 init_crd = REG_RD(bp, regs->init_crd);
942
943 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
944 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
945 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
946
947 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
948 (init_crd - crd_start))) {
949 if (cur_cnt--) {
89db4ad8 950 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 951 crd = REG_RD(bp, regs->crd);
952 crd_freed = REG_RD(bp, regs->crd_freed);
953 } else {
954 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
955 regs->pN);
956 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
957 regs->pN, crd);
958 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
959 regs->pN, crd_freed);
960 break;
961 }
962 }
963 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 964 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 965}
966
967static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
968 struct pbf_pN_cmd_regs *regs,
969 u32 poll_count)
970{
971 u32 occup, to_free, freed, freed_start;
972 u32 cur_cnt = poll_count;
973
974 occup = to_free = REG_RD(bp, regs->lines_occup);
975 freed = freed_start = REG_RD(bp, regs->lines_freed);
976
977 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
978 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
979
980 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
981 if (cur_cnt--) {
89db4ad8 982 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 983 occup = REG_RD(bp, regs->lines_occup);
984 freed = REG_RD(bp, regs->lines_freed);
985 } else {
986 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
987 regs->pN);
988 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
989 regs->pN, occup);
990 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
991 regs->pN, freed);
992 break;
993 }
994 }
995 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 996 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 997}
998
999static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1000 u32 expected, u32 poll_count)
1001{
1002 u32 cur_cnt = poll_count;
1003 u32 val;
1004
1005 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1006 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1007
1008 return val;
1009}
1010
1011static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1012 char *msg, u32 poll_cnt)
1013{
1014 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1015 if (val != 0) {
1016 BNX2X_ERR("%s usage count=%d\n", msg, val);
1017 return 1;
1018 }
1019 return 0;
1020}
1021
1022static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1023{
1024 /* adjust polling timeout */
1025 if (CHIP_REV_IS_EMUL(bp))
1026 return FLR_POLL_CNT * 2000;
1027
1028 if (CHIP_REV_IS_FPGA(bp))
1029 return FLR_POLL_CNT * 120;
1030
1031 return FLR_POLL_CNT;
1032}
1033
1034static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1035{
1036 struct pbf_pN_cmd_regs cmd_regs[] = {
1037 {0, (CHIP_IS_E3B0(bp)) ?
1038 PBF_REG_TQ_OCCUPANCY_Q0 :
1039 PBF_REG_P0_TQ_OCCUPANCY,
1040 (CHIP_IS_E3B0(bp)) ?
1041 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1042 PBF_REG_P0_TQ_LINES_FREED_CNT},
1043 {1, (CHIP_IS_E3B0(bp)) ?
1044 PBF_REG_TQ_OCCUPANCY_Q1 :
1045 PBF_REG_P1_TQ_OCCUPANCY,
1046 (CHIP_IS_E3B0(bp)) ?
1047 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1048 PBF_REG_P1_TQ_LINES_FREED_CNT},
1049 {4, (CHIP_IS_E3B0(bp)) ?
1050 PBF_REG_TQ_OCCUPANCY_LB_Q :
1051 PBF_REG_P4_TQ_OCCUPANCY,
1052 (CHIP_IS_E3B0(bp)) ?
1053 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1054 PBF_REG_P4_TQ_LINES_FREED_CNT}
1055 };
1056
1057 struct pbf_pN_buf_regs buf_regs[] = {
1058 {0, (CHIP_IS_E3B0(bp)) ?
1059 PBF_REG_INIT_CRD_Q0 :
1060 PBF_REG_P0_INIT_CRD ,
1061 (CHIP_IS_E3B0(bp)) ?
1062 PBF_REG_CREDIT_Q0 :
1063 PBF_REG_P0_CREDIT,
1064 (CHIP_IS_E3B0(bp)) ?
1065 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1066 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1067 {1, (CHIP_IS_E3B0(bp)) ?
1068 PBF_REG_INIT_CRD_Q1 :
1069 PBF_REG_P1_INIT_CRD,
1070 (CHIP_IS_E3B0(bp)) ?
1071 PBF_REG_CREDIT_Q1 :
1072 PBF_REG_P1_CREDIT,
1073 (CHIP_IS_E3B0(bp)) ?
1074 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1075 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1076 {4, (CHIP_IS_E3B0(bp)) ?
1077 PBF_REG_INIT_CRD_LB_Q :
1078 PBF_REG_P4_INIT_CRD,
1079 (CHIP_IS_E3B0(bp)) ?
1080 PBF_REG_CREDIT_LB_Q :
1081 PBF_REG_P4_CREDIT,
1082 (CHIP_IS_E3B0(bp)) ?
1083 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1084 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1085 };
1086
1087 int i;
1088
1089 /* Verify the command queues are flushed P0, P1, P4 */
1090 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1091 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1092
1093
1094 /* Verify the transmission buffers are flushed P0, P1, P4 */
1095 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1096 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1097}
1098
1099#define OP_GEN_PARAM(param) \
1100 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1101
1102#define OP_GEN_TYPE(type) \
1103 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1104
1105#define OP_GEN_AGG_VECT(index) \
1106 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1107
1108
1109static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1110 u32 poll_cnt)
1111{
1112 struct sdm_op_gen op_gen = {0};
1113
1114 u32 comp_addr = BAR_CSTRORM_INTMEM +
1115 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1116 int ret = 0;
1117
1118 if (REG_RD(bp, comp_addr)) {
89db4ad8 1119 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1120 return 1;
1121 }
1122
1123 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1124 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1125 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1126 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1127
89db4ad8 1128 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
619c5cb6
VZ		 1129 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1130
1131 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1132 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1133 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1134 (REG_RD(bp, comp_addr)));
619c5cb6
VZ		 1135 ret = 1;
1136 }
1137 /* Zero completion for nxt FLR */
1138 REG_WR(bp, comp_addr, 0);
1139
1140 return ret;
1141}
1142
1143static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1144{
1145 int pos;
1146 u16 status;
1147
77c98e6a 1148 pos = pci_pcie_cap(dev);
619c5cb6
VZ		 1149 if (!pos)
1150 return false;
1151
1152 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1153 return status & PCI_EXP_DEVSTA_TRPND;
1154}
1155
1156/* PF FLR specific routines
1157*/
1158static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1159{
1160
1161 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1162 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1163 CFC_REG_NUM_LCIDS_INSIDE_PF,
1164 "CFC PF usage counter timed out",
1165 poll_cnt))
1166 return 1;
1167
1168
1169 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1170 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1171 DORQ_REG_PF_USAGE_CNT,
1172 "DQ PF usage counter timed out",
1173 poll_cnt))
1174 return 1;
1175
1176 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1177 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1178 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1179 "QM PF usage counter timed out",
1180 poll_cnt))
1181 return 1;
1182
1183 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1184 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1185 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1186 "Timers VNIC usage counter timed out",
1187 poll_cnt))
1188 return 1;
1189 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1190 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1191 "Timers NUM_SCANS usage counter timed out",
1192 poll_cnt))
1193 return 1;
1194
1195 /* Wait DMAE PF usage counter to zero */
1196 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1197 dmae_reg_go_c[INIT_DMAE_C(bp)],
1198 "DMAE dommand register timed out",
1199 poll_cnt))
1200 return 1;
1201
1202 return 0;
1203}
1204
1205static void bnx2x_hw_enable_status(struct bnx2x *bp)
1206{
1207 u32 val;
1208
1209 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1210 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1211
1212 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1213 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1214
1215 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1216 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1217
1218 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1219 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1220
1221 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1222 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1223
1224 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1225 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1226
1227 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1228 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1229
1230 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1231 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1232 val);
1233}
1234
1235static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1236{
1237 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1238
1239 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1240
1241 /* Re-enable PF target read access */
1242 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1243
1244 /* Poll HW usage counters */
89db4ad8 1245 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1246 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1247 return -EBUSY;
1248
1249 /* Zero the igu 'trailing edge' and 'leading edge' */
1250
1251 /* Send the FW cleanup command */
1252 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1253 return -EBUSY;
1254
1255 /* ATC cleanup */
1256
1257 /* Verify TX hw is flushed */
1258 bnx2x_tx_hw_flushed(bp, poll_cnt);
1259
1260 /* Wait 100ms (not adjusted according to platform) */
1261 msleep(100);
1262
1263 /* Verify no pending pci transactions */
1264 if (bnx2x_is_pcie_pending(bp->pdev))
1265 BNX2X_ERR("PCIE Transactions still pending\n");
1266
1267 /* Debug */
1268 bnx2x_hw_enable_status(bp);
1269
1270 /*
1271 * Master enable - Due to WB DMAE writes performed before this
1272 * register is re-initialized as part of the regular function init
1273 */
1274 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1275
1276 return 0;
1277}
1278
f2e0899f 1279static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1280{
34f80b04 1281 int port = BP_PORT(bp);
a2fbb9ea
ET		 1282 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1283 u32 val = REG_RD(bp, addr);
1284 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1285 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1286
1287 if (msix) {
8badd27a
EG		 1288 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1289 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1290 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1291 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1292 } else if (msi) {
1293 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1294 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1295 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1296 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1297 } else {
1298 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1299 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1300 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1301 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1302
a0fd065c 1303 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1304 DP(NETIF_MSG_IFUP,
1305 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1306
a0fd065c 1307 REG_WR(bp, addr, val);
615f8fd9 1308
a0fd065c
DK		 1309 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1310 }
a2fbb9ea
ET		 1311 }
1312
a0fd065c
DK		 1313 if (CHIP_IS_E1(bp))
1314 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1315
51c1a580
MS		 1316 DP(NETIF_MSG_IFUP,
1317 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1318 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1319
1320 REG_WR(bp, addr, val);
37dbbf32
EG		 1321 /*
1322 * Ensure that HC_CONFIG is written before leading/trailing edge config
1323 */
1324 mmiowb();
1325 barrier();
34f80b04 1326
f2e0899f 1327 if (!CHIP_IS_E1(bp)) {
34f80b04 1328 /* init leading/trailing edge */
fb3bff17 1329 if (IS_MF(bp)) {
3395a033 1330 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1331 if (bp->port.pmf)
4acac6a5
EG		 1332 /* enable nig and gpio3 attention */
1333 val |= 0x1100;
34f80b04
EG		 1334 } else
1335 val = 0xffff;
1336
1337 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1338 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1339 }
37dbbf32
EG		 1340
1341 /* Make sure that interrupts are indeed enabled from here on */
1342 mmiowb();
a2fbb9ea
ET		 1343}
1344
f2e0899f
DK		 1345static void bnx2x_igu_int_enable(struct bnx2x *bp)
1346{
1347 u32 val;
30a5de77
DK		 1348 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1349 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1350 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1351
1352 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1353
1354 if (msix) {
1355 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1356 IGU_PF_CONF_SINGLE_ISR_EN);
1357 val |= (IGU_PF_CONF_FUNC_EN |
1358 IGU_PF_CONF_MSI_MSIX_EN |
1359 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1360
1361 if (single_msix)
1362 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1363 } else if (msi) {
1364 val &= ~IGU_PF_CONF_INT_LINE_EN;
1365 val |= (IGU_PF_CONF_FUNC_EN |
1366 IGU_PF_CONF_MSI_MSIX_EN |
1367 IGU_PF_CONF_ATTN_BIT_EN |
1368 IGU_PF_CONF_SINGLE_ISR_EN);
1369 } else {
1370 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1371 val |= (IGU_PF_CONF_FUNC_EN |
1372 IGU_PF_CONF_INT_LINE_EN |
1373 IGU_PF_CONF_ATTN_BIT_EN |
1374 IGU_PF_CONF_SINGLE_ISR_EN);
1375 }
1376
51c1a580 1377 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1378 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1379
1380 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1381
79a8557a
YM		 1382 if (val & IGU_PF_CONF_INT_LINE_EN)
1383 pci_intx(bp->pdev, true);
1384
f2e0899f
DK		 1385 barrier();
1386
1387 /* init leading/trailing edge */
1388 if (IS_MF(bp)) {
3395a033 1389 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1390 if (bp->port.pmf)
1391 /* enable nig and gpio3 attention */
1392 val |= 0x1100;
1393 } else
1394 val = 0xffff;
1395
1396 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1397 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1398
1399 /* Make sure that interrupts are indeed enabled from here on */
1400 mmiowb();
1401}
1402
1403void bnx2x_int_enable(struct bnx2x *bp)
1404{
1405 if (bp->common.int_block == INT_BLOCK_HC)
1406 bnx2x_hc_int_enable(bp);
1407 else
1408 bnx2x_igu_int_enable(bp);
1409}
1410
1411static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1412{
34f80b04 1413 int port = BP_PORT(bp);
a2fbb9ea
ET		 1414 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1415 u32 val = REG_RD(bp, addr);
1416
a0fd065c
DK		 1417 /*
1418 * in E1 we must use only PCI configuration space to disable
1419 * MSI/MSIX capablility
1420 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1421 */
1422 if (CHIP_IS_E1(bp)) {
1423 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1424 * Use mask register to prevent from HC sending interrupts
1425 * after we exit the function
1426 */
1427 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1428
1429 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1430 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1431 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1432 } else
1433 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1434 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1435 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1436 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea 1437
51c1a580
MS		 1438 DP(NETIF_MSG_IFDOWN,
1439 "write %x to HC %d (addr 0x%x)\n",
a2fbb9ea
ET		 1440 val, port, addr);
1441
8badd27a
EG		 1442 /* flush all outstanding writes */
1443 mmiowb();
1444
a2fbb9ea
ET		 1445 REG_WR(bp, addr, val);
1446 if (REG_RD(bp, addr) != val)
1447 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1448}
1449
f2e0899f
DK		 1450static void bnx2x_igu_int_disable(struct bnx2x *bp)
1451{
1452 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1453
1454 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1455 IGU_PF_CONF_INT_LINE_EN |
1456 IGU_PF_CONF_ATTN_BIT_EN);
1457
51c1a580 1458 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
f2e0899f
DK		 1459
1460 /* flush all outstanding writes */
1461 mmiowb();
1462
1463 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1464 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1465 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1466}
1467
6383c0b3 1468void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1469{
1470 if (bp->common.int_block == INT_BLOCK_HC)
1471 bnx2x_hc_int_disable(bp);
1472 else
1473 bnx2x_igu_int_disable(bp);
1474}
1475
9f6c9258 1476void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1477{
a2fbb9ea 1478 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1479 int i, offset;
a2fbb9ea 1480
f8ef6e44
YG		 1481 if (disable_hw)
1482 /* prevent the HW from sending interrupts */
1483 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1484
1485 /* make sure all ISRs are done */
1486 if (msix) {
8badd27a
EG		 1487 synchronize_irq(bp->msix_table[0].vector);
1488 offset = 1;
37b091ba
MC		 1489#ifdef BCM_CNIC
1490 offset++;
1491#endif
ec6ba945 1492 for_each_eth_queue(bp, i)
754a2f52 1493 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1494 } else
1495 synchronize_irq(bp->pdev->irq);
1496
1497 /* make sure sp_task is not running */
1cf167f2 1498 cancel_delayed_work(&bp->sp_task);
3deb8167 1499 cancel_delayed_work(&bp->period_task);
1cf167f2 1500 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1501}
1502
34f80b04 1503/* fast path */
a2fbb9ea
ET		 1504
1505/*
34f80b04 1506 * General service functions
a2fbb9ea
ET		 1507 */
1508
72fd0718
VZ		 1509/* Return true if succeeded to acquire the lock */
1510static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1511{
1512 u32 lock_status;
1513 u32 resource_bit = (1 << resource);
1514 int func = BP_FUNC(bp);
1515 u32 hw_lock_control_reg;
1516
51c1a580
MS		 1517 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1518 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1519
1520 /* Validating that the resource is within range */
1521 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1522 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1523 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1524 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1525 return false;
72fd0718
VZ		 1526 }
1527
1528 if (func <= 5)
1529 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1530 else
1531 hw_lock_control_reg =
1532 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1533
1534 /* Try to acquire the lock */
1535 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1536 lock_status = REG_RD(bp, hw_lock_control_reg);
1537 if (lock_status & resource_bit)
1538 return true;
1539
51c1a580
MS		 1540 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1541 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1542 return false;
1543}
1544
c9ee9206
VZ		 1545/**
1546 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1547 *
1548 * @bp: driver handle
1549 *
1550 * Returns the recovery leader resource id according to the engine this function
1551 * belongs to. Currently only only 2 engines is supported.
1552 */
1553static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1554{
1555 if (BP_PATH(bp))
1556 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1557 else
1558 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1559}
1560
1561/**
1562 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1563 *
1564 * @bp: driver handle
1565 *
1566 * Tries to aquire a leader lock for cuurent engine.
1567 */
1568static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1569{
1570 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1571}
1572
993ac7b5 1573#ifdef BCM_CNIC
619c5cb6 1574static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
993ac7b5 1575#endif
3196a88a 1576
619c5cb6 1577void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1578{
1579 struct bnx2x *bp = fp->bp;
1580 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1581 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6
VZ		 1582 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1583 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
a2fbb9ea 1584
34f80b04 1585 DP(BNX2X_MSG_SP,
a2fbb9ea 1586 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1587 fp->index, cid, command, bp->state,
34f80b04 1588 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1589
619c5cb6
VZ		 1590 switch (command) {
1591 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1592 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1593 drv_cmd = BNX2X_Q_CMD_UPDATE;
1594 break;
d6cae238 1595
619c5cb6 1596 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1597 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1598 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1599 break;
1600
6383c0b3 1601 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1602 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1603 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1604 break;
1605
619c5cb6 1606 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1607 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1608 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1609 break;
1610
619c5cb6 1611 case (RAMROD_CMD_ID_ETH_TERMINATE):
d6cae238 1612 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1613 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1614 break;
1615
619c5cb6 1616 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1617 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1618 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1619 break;
619c5cb6
VZ		 1620
1621 default:
1622 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1623 command, fp->index);
1624 return;
523224a3 1625 }
3196a88a 1626
619c5cb6
VZ		 1627 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1628 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1629 /* q_obj->complete_cmd() failure means that this was
1630 * an unexpected completion.
1631 *
1632 * In this case we don't want to increase the bp->spq_left
1633 * because apparently we haven't sent this command the first
1634 * place.
1635 */
1636#ifdef BNX2X_STOP_ON_ERROR
1637 bnx2x_panic();
1638#else
1639 return;
1640#endif
1641
8fe23fbd 1642 smp_mb__before_atomic_inc();
6e30dd4e 1643 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1644 /* push the change in bp->spq_left and towards the memory */
1645 smp_mb__after_atomic_inc();
49d66772 1646
d6cae238
VZ		 1647 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1648
523224a3 1649 return;
a2fbb9ea
ET		 1650}
1651
619c5cb6
VZ		 1652void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1653 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1654{
1655 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1656
1657 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1658 start);
1659}
1660
9f6c9258 1661irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1662{
555f6c78 1663 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1664 u16 status = bnx2x_ack_int(bp);
34f80b04 1665 u16 mask;
ca00392c 1666 int i;
6383c0b3 1667 u8 cos;
a2fbb9ea 1668
34f80b04 1669 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1670 if (unlikely(status == 0)) {
1671 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1672 return IRQ_NONE;
1673 }
f5372251 1674 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1675
3196a88a
EG		 1676#ifdef BNX2X_STOP_ON_ERROR
1677 if (unlikely(bp->panic))
1678 return IRQ_HANDLED;
1679#endif
1680
ec6ba945 1681 for_each_eth_queue(bp, i) {
ca00392c 1682 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1683
6383c0b3 1684 mask = 0x2 << (fp->index + CNIC_PRESENT);
ca00392c 1685 if (status & mask) {
619c5cb6 1686 /* Handle Rx or Tx according to SB id */
54b9ddaa 1687 prefetch(fp->rx_cons_sb);
6383c0b3
AE		 1688 for_each_cos_in_tx_queue(fp, cos)
1689 prefetch(fp->txdata[cos].tx_cons_sb);
523224a3 1690 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1691 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1692 status &= ~mask;
1693 }
a2fbb9ea
ET		 1694 }
1695
993ac7b5 1696#ifdef BCM_CNIC
523224a3 1697 mask = 0x2;
993ac7b5
MC		 1698 if (status & (mask | 0x1)) {
1699 struct cnic_ops *c_ops = NULL;
1700
619c5cb6
VZ		 1701 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1702 rcu_read_lock();
1703 c_ops = rcu_dereference(bp->cnic_ops);
1704 if (c_ops)
1705 c_ops->cnic_handler(bp->cnic_data, NULL);
1706 rcu_read_unlock();
1707 }
993ac7b5
MC		 1708
1709 status &= ~mask;
1710 }
1711#endif
a2fbb9ea 1712
34f80b04 1713 if (unlikely(status & 0x1)) {
1cf167f2 1714 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1715
1716 status &= ~0x1;
1717 if (!status)
1718 return IRQ_HANDLED;
1719 }
1720
cdaa7cb8
VZ		 1721 if (unlikely(status))
1722 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1723 status);
a2fbb9ea 1724
c18487ee 1725 return IRQ_HANDLED;
a2fbb9ea
ET		 1726}
1727
c18487ee
YR		 1728/* Link */
1729
1730/*
1731 * General service functions
1732 */
a2fbb9ea 1733
9f6c9258 1734int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1735{
1736 u32 lock_status;
1737 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1738 int func = BP_FUNC(bp);
1739 u32 hw_lock_control_reg;
c18487ee 1740 int cnt;
a2fbb9ea 1741
c18487ee
YR		 1742 /* Validating that the resource is within range */
1743 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1744 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1745 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1746 return -EINVAL;
1747 }
a2fbb9ea 1748
4a37fb66
YG		 1749 if (func <= 5) {
1750 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1751 } else {
1752 hw_lock_control_reg =
1753 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1754 }
1755
c18487ee 1756 /* Validating that the resource is not already taken */
4a37fb66 1757 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1758 if (lock_status & resource_bit) {
51c1a580 1759 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 1760 lock_status, resource_bit);
1761 return -EEXIST;
1762 }
a2fbb9ea 1763
46230476
EG		 1764 /* Try for 5 second every 5ms */
1765 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1766 /* Try to acquire the lock */
4a37fb66
YG		 1767 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1768 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1769 if (lock_status & resource_bit)
1770 return 0;
a2fbb9ea 1771
c18487ee 1772 msleep(5);
a2fbb9ea 1773 }
51c1a580 1774 BNX2X_ERR("Timeout\n");
c18487ee
YR		 1775 return -EAGAIN;
1776}
a2fbb9ea 1777
c9ee9206
VZ		 1778int bnx2x_release_leader_lock(struct bnx2x *bp)
1779{
1780 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1781}
1782
9f6c9258 1783int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1784{
1785 u32 lock_status;
1786 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1787 int func = BP_FUNC(bp);
1788 u32 hw_lock_control_reg;
a2fbb9ea 1789
c18487ee
YR		 1790 /* Validating that the resource is within range */
1791 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1792 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1793 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1794 return -EINVAL;
1795 }
1796
4a37fb66
YG		 1797 if (func <= 5) {
1798 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1799 } else {
1800 hw_lock_control_reg =
1801 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1802 }
1803
c18487ee 1804 /* Validating that the resource is currently taken */
4a37fb66 1805 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1806 if (!(lock_status & resource_bit)) {
51c1a580 1807 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
c18487ee
YR		 1808 lock_status, resource_bit);
1809 return -EFAULT;
a2fbb9ea
ET		 1810 }
1811
9f6c9258
DK		 1812 REG_WR(bp, hw_lock_control_reg, resource_bit);
1813 return 0;
c18487ee 1814}
a2fbb9ea 1815
9f6c9258 1816
4acac6a5
EG		 1817int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1818{
1819 /* The GPIO should be swapped if swap register is set and active */
1820 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1821 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1822 int gpio_shift = gpio_num +
1823 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1824 u32 gpio_mask = (1 << gpio_shift);
1825 u32 gpio_reg;
1826 int value;
1827
1828 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1829 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1830 return -EINVAL;
1831 }
1832
1833 /* read GPIO value */
1834 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1835
1836 /* get the requested pin value */
1837 if ((gpio_reg & gpio_mask) == gpio_mask)
1838 value = 1;
1839 else
1840 value = 0;
1841
1842 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1843
1844 return value;
1845}
1846
17de50b7 1847int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1848{
1849 /* The GPIO should be swapped if swap register is set and active */
1850 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1851 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1852 int gpio_shift = gpio_num +
1853 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1854 u32 gpio_mask = (1 << gpio_shift);
1855 u32 gpio_reg;
a2fbb9ea 1856
c18487ee
YR		 1857 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1858 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1859 return -EINVAL;
1860 }
a2fbb9ea 1861
4a37fb66 1862 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1863 /* read GPIO and mask except the float bits */
1864 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1865
c18487ee
YR		 1866 switch (mode) {
1867 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 1868 DP(NETIF_MSG_LINK,
1869 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 1870 gpio_num, gpio_shift);
1871 /* clear FLOAT and set CLR */
1872 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1873 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1874 break;
a2fbb9ea 1875
c18487ee 1876 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 1877 DP(NETIF_MSG_LINK,
1878 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 1879 gpio_num, gpio_shift);
1880 /* clear FLOAT and set SET */
1881 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1882 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1883 break;
a2fbb9ea 1884
17de50b7 1885 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 1886 DP(NETIF_MSG_LINK,
1887 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 1888 gpio_num, gpio_shift);
1889 /* set FLOAT */
1890 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1891 break;
a2fbb9ea 1892
c18487ee
YR		 1893 default:
1894 break;
a2fbb9ea
ET		 1895 }
1896
c18487ee 1897 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1898 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1899
c18487ee 1900 return 0;
a2fbb9ea
ET		 1901}
1902
0d40f0d4
YR		 1903int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1904{
1905 u32 gpio_reg = 0;
1906 int rc = 0;
1907
1908 /* Any port swapping should be handled by caller. */
1909
1910 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1911 /* read GPIO and mask except the float bits */
1912 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1913 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1914 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1915 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1916
1917 switch (mode) {
1918 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1919 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1920 /* set CLR */
1921 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1922 break;
1923
1924 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1925 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1926 /* set SET */
1927 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1928 break;
1929
1930 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1931 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1932 /* set FLOAT */
1933 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1934 break;
1935
1936 default:
1937 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1938 rc = -EINVAL;
1939 break;
1940 }
1941
1942 if (rc == 0)
1943 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1944
1945 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1946
1947 return rc;
1948}
1949
4acac6a5
EG		 1950int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1951{
1952 /* The GPIO should be swapped if swap register is set and active */
1953 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1954 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1955 int gpio_shift = gpio_num +
1956 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1957 u32 gpio_mask = (1 << gpio_shift);
1958 u32 gpio_reg;
1959
1960 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1961 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1962 return -EINVAL;
1963 }
1964
1965 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1966 /* read GPIO int */
1967 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1968
1969 switch (mode) {
1970 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 1971 DP(NETIF_MSG_LINK,
1972 "Clear GPIO INT %d (shift %d) -> output low\n",
1973 gpio_num, gpio_shift);
4acac6a5
EG		 1974 /* clear SET and set CLR */
1975 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1976 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1977 break;
1978
1979 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 1980 DP(NETIF_MSG_LINK,
1981 "Set GPIO INT %d (shift %d) -> output high\n",
1982 gpio_num, gpio_shift);
4acac6a5
EG		 1983 /* clear CLR and set SET */
1984 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1985 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1986 break;
1987
1988 default:
1989 break;
1990 }
1991
1992 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1993 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1994
1995 return 0;
1996}
1997
c18487ee 1998static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 1999{
c18487ee
YR		 2000 u32 spio_mask = (1 << spio_num);
2001 u32 spio_reg;
a2fbb9ea 2002
c18487ee
YR		 2003 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2004 (spio_num > MISC_REGISTERS_SPIO_7)) {
2005 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2006 return -EINVAL;
a2fbb9ea
ET		 2007 }
2008
4a37fb66 2009 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 2010 /* read SPIO and mask except the float bits */
2011 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 2012
c18487ee 2013 switch (mode) {
6378c025 2014 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
51c1a580 2015 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
c18487ee
YR		 2016 /* clear FLOAT and set CLR */
2017 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2018 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2019 break;
a2fbb9ea 2020
6378c025 2021 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
51c1a580 2022 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
c18487ee
YR		 2023 /* clear FLOAT and set SET */
2024 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2025 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2026 break;
a2fbb9ea 2027
c18487ee 2028 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
51c1a580 2029 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
c18487ee
YR		 2030 /* set FLOAT */
2031 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2032 break;
a2fbb9ea 2033
c18487ee
YR		 2034 default:
2035 break;
a2fbb9ea
ET		 2036 }
2037
c18487ee 2038 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2039 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2040
a2fbb9ea
ET		 2041 return 0;
2042}
2043
9f6c9258 2044void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2045{
a22f0788 2046 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2047 switch (bp->link_vars.ieee_fc &
2048 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2049 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2050 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2051 ADVERTISED_Pause);
c18487ee 2052 break;
356e2385 2053
c18487ee 2054 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2055 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2056 ADVERTISED_Pause);
c18487ee 2057 break;
356e2385 2058
c18487ee 2059 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2060 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2061 break;
356e2385 2062
c18487ee 2063 default:
a22f0788 2064 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2065 ADVERTISED_Pause);
c18487ee
YR		 2066 break;
2067 }
2068}
f1410647 2069
9f6c9258 2070u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 2071{
19680c48
EG		 2072 if (!BP_NOMCP(bp)) {
2073 u8 rc;
a22f0788
YR		 2074 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2075 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1cb0c788
YR		 2076 /*
2077 * Initialize link parameters structure variables
2078 * It is recommended to turn off RX FC for jumbo frames
2079 * for better performance
2080 */
2081 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
c0700f90 2082 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 2083 else
c0700f90 2084 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 2085
4a37fb66 2086 bnx2x_acquire_phy_lock(bp);
b5bf9068 2087
a22f0788 2088 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2089 struct link_params *lp = &bp->link_params;
2090 lp->loopback_mode = LOOPBACK_XGXS;
2091 /* do PHY loopback at 10G speed, if possible */
2092 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2093 if (lp->speed_cap_mask[cfx_idx] &
2094 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2095 lp->req_line_speed[cfx_idx] =
2096 SPEED_10000;
2097 else
2098 lp->req_line_speed[cfx_idx] =
2099 SPEED_1000;
2100 }
a22f0788 2101 }
b5bf9068 2102
19680c48 2103 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2104
4a37fb66 2105 bnx2x_release_phy_lock(bp);
a2fbb9ea 2106
3c96c68b
EG		 2107 bnx2x_calc_fc_adv(bp);
2108
b5bf9068
EG		 2109 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2110 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2111 bnx2x_link_report(bp);
3deb8167
YR		 2112 } else
2113 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2114 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2115 return rc;
2116 }
f5372251 2117 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2118 return -EINVAL;
a2fbb9ea
ET		 2119}
2120
9f6c9258 2121void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2122{
19680c48 2123 if (!BP_NOMCP(bp)) {
4a37fb66 2124 bnx2x_acquire_phy_lock(bp);
54c2fb78 2125 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 2126 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2127 bnx2x_release_phy_lock(bp);
a2fbb9ea 2128
19680c48
EG		 2129 bnx2x_calc_fc_adv(bp);
2130 } else
f5372251 2131 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2132}
a2fbb9ea 2133
c18487ee
YR		 2134static void bnx2x__link_reset(struct bnx2x *bp)
2135{
19680c48 2136 if (!BP_NOMCP(bp)) {
4a37fb66 2137 bnx2x_acquire_phy_lock(bp);
589abe3a 2138 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 2139 bnx2x_release_phy_lock(bp);
19680c48 2140 } else
f5372251 2141 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2142}
a2fbb9ea 2143
a22f0788 2144u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2145{
2145a920 2146 u8 rc = 0;
a2fbb9ea 2147
2145a920
VZ		 2148 if (!BP_NOMCP(bp)) {
2149 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2150 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2151 is_serdes);
2145a920
VZ		 2152 bnx2x_release_phy_lock(bp);
2153 } else
2154 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2155
c18487ee
YR		 2156 return rc;
2157}
a2fbb9ea 2158
34f80b04 2159
2691d51d
EG		 2160/* Calculates the sum of vn_min_rates.
2161 It's needed for further normalizing of the min_rates.
2162 Returns:
2163 sum of vn_min_rates.
2164 or
2165 0 - if all the min_rates are 0.
2166 In the later case fainess algorithm should be deactivated.
2167 If not all min_rates are zero then those that are zeroes will be set to 1.
2168 */
b475d78f
YM		 2169static void bnx2x_calc_vn_min(struct bnx2x *bp,
2170 struct cmng_init_input *input)
2691d51d
EG		 2171{
2172 int all_zero = 1;
2691d51d
EG		 2173 int vn;
2174
3395a033 2175 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2176 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2177 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2178 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2179
2180 /* Skip hidden vns */
2181 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2182 vn_min_rate = 0;
2691d51d 2183 /* If min rate is zero - set it to 1 */
b475d78f 2184 else if (!vn_min_rate)
2691d51d
EG		 2185 vn_min_rate = DEF_MIN_RATE;
2186 else
2187 all_zero = 0;
2188
b475d78f 2189 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2190 }
2191
30ae438b
DK		 2192 /* if ETS or all min rates are zeros - disable fairness */
2193 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2194 input->flags.cmng_enables &=
30ae438b
DK		 2195 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2196 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2197 } else if (all_zero) {
b475d78f 2198 input->flags.cmng_enables &=
b015e3d1 2199 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2200 DP(NETIF_MSG_IFUP,
2201 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2202 } else
b475d78f 2203 input->flags.cmng_enables |=
b015e3d1 2204 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2205}
2206
b475d78f
YM		 2207static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2208 struct cmng_init_input *input)
34f80b04 2209{
b475d78f 2210 u16 vn_max_rate;
f2e0899f 2211 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2212
b475d78f 2213 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2214 vn_max_rate = 0;
b475d78f 2215 else {
faa6fcbb
DK		 2216 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2217
b475d78f 2218 if (IS_MF_SI(bp)) {
faa6fcbb
DK		 2219 /* maxCfg in percents of linkspeed */
2220 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2221 } else /* SD modes */
faa6fcbb
DK		 2222 /* maxCfg is absolute in 100Mb units */
2223 vn_max_rate = maxCfg * 100;
34f80b04 2224 }
f85582f8 2225
b475d78f 2226 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2227
b475d78f 2228 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2229}
f85582f8 2230
b475d78f 2231
523224a3
DK		 2232static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2233{
2234 if (CHIP_REV_IS_SLOW(bp))
2235 return CMNG_FNS_NONE;
fb3bff17 2236 if (IS_MF(bp))
523224a3
DK		 2237 return CMNG_FNS_MINMAX;
2238
2239 return CMNG_FNS_NONE;
2240}
2241
2ae17f66 2242void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2243{
0793f83f 2244 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2245
2246 if (BP_NOMCP(bp))
2247 return; /* what should be the default bvalue in this case */
2248
0793f83f
DK		 2249 /* For 2 port configuration the absolute function number formula
2250 * is:
2251 * abs_func = 2 * vn + BP_PORT + BP_PATH
2252 *
2253 * and there are 4 functions per port
2254 *
2255 * For 4 port configuration it is
2256 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2257 *
2258 * and there are 2 functions per port
2259 */
3395a033 2260 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2261 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2262
2263 if (func >= E1H_FUNC_MAX)
2264 break;
2265
f2e0899f 2266 bp->mf_config[vn] =
523224a3
DK		 2267 MF_CFG_RD(bp, func_mf_config[func].config);
2268 }
2269}
2270
2271static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2272{
b475d78f
YM		 2273 struct cmng_init_input input;
2274 memset(&input, 0, sizeof(struct cmng_init_input));
2275
2276 input.port_rate = bp->link_vars.line_speed;
523224a3
DK		 2277
2278 if (cmng_type == CMNG_FNS_MINMAX) {
2279 int vn;
2280
523224a3
DK		 2281 /* read mf conf from shmem */
2282 if (read_cfg)
2283 bnx2x_read_mf_cfg(bp);
2284
523224a3 2285 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2286 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2287
2288 /* calculate and set min-max rate for each vn */
c4154f25 2289 if (bp->port.pmf)
3395a033 2290 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2291 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2292
2293 /* always enable rate shaping and fairness */
b475d78f 2294 input.flags.cmng_enables |=
523224a3 2295 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2296
2297 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2298 return;
2299 }
2300
2301 /* rate shaping and fairness are disabled */
2302 DP(NETIF_MSG_IFUP,
2303 "rate shaping and fairness are disabled\n");
2304}
34f80b04 2305
c18487ee
YR		 2306/* This function is called upon link interrupt */
2307static void bnx2x_link_attn(struct bnx2x *bp)
2308{
bb2a0f7a
YG		 2309 /* Make sure that we are synced with the current statistics */
2310 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2311
c18487ee 2312 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2313
bb2a0f7a
YG		 2314 if (bp->link_vars.link_up) {
2315
1c06328c 2316 /* dropless flow control */
f2e0899f 2317 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2318 int port = BP_PORT(bp);
2319 u32 pause_enabled = 0;
2320
2321 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2322 pause_enabled = 1;
2323
2324 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2325 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2326 pause_enabled);
2327 }
2328
619c5cb6 2329 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2330 struct host_port_stats *pstats;
2331
2332 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2333 /* reset old mac stats */
bb2a0f7a
YG		 2334 memset(&(pstats->mac_stx[0]), 0,
2335 sizeof(struct mac_stx));
2336 }
f34d28ea 2337 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2338 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2339 }
2340
f2e0899f
DK		 2341 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2342 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2343
f2e0899f
DK		 2344 if (cmng_fns != CMNG_FNS_NONE) {
2345 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2346 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2347 } else
2348 /* rate shaping and fairness are disabled */
2349 DP(NETIF_MSG_IFUP,
2350 "single function mode without fairness\n");
34f80b04 2351 }
9fdc3e95 2352
2ae17f66
VZ		 2353 __bnx2x_link_report(bp);
2354
9fdc3e95
DK		 2355 if (IS_MF(bp))
2356 bnx2x_link_sync_notify(bp);
c18487ee 2357}
a2fbb9ea 2358
9f6c9258 2359void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2360{
2ae17f66 2361 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2362 return;
a2fbb9ea 2363
00253a8c
DK		 2364 /* read updated dcb configuration */
2365 bnx2x_dcbx_pmf_update(bp);
2366
c18487ee 2367 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2368
bb2a0f7a
YG		 2369 if (bp->link_vars.link_up)
2370 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2371 else
2372 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2373
c18487ee
YR		 2374 /* indicate link status */
2375 bnx2x_link_report(bp);
a2fbb9ea 2376}
a2fbb9ea 2377
34f80b04
EG		 2378static void bnx2x_pmf_update(struct bnx2x *bp)
2379{
2380 int port = BP_PORT(bp);
2381 u32 val;
2382
2383 bp->port.pmf = 1;
51c1a580 2384 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2385
3deb8167
YR		 2386 /*
2387 * We need the mb() to ensure the ordering between the writing to
2388 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2389 */
2390 smp_mb();
2391
2392 /* queue a periodic task */
2393 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2394
ef01854e
DK		 2395 bnx2x_dcbx_pmf_update(bp);
2396
34f80b04 2397 /* enable nig attention */
3395a033 2398 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2399 if (bp->common.int_block == INT_BLOCK_HC) {
2400 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2401 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2402 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2403 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2404 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2405 }
bb2a0f7a
YG		 2406
2407 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2408}
2409
c18487ee 2410/* end of Link */
a2fbb9ea
ET		 2411
2412/* slow path */
2413
2414/*
2415 * General service functions
2416 */
2417
2691d51d 2418/* send the MCP a request, block until there is a reply */
a22f0788 2419u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2420{
f2e0899f 2421 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2422 u32 seq;
2691d51d
EG		 2423 u32 rc = 0;
2424 u32 cnt = 1;
2425 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2426
c4ff7cbf 2427 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2428 seq = ++bp->fw_seq;
f2e0899f
DK		 2429 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2430 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2431
754a2f52
DK		 2432 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2433 (command | seq), param);
2691d51d
EG		 2434
2435 do {
2436 /* let the FW do it's magic ... */
2437 msleep(delay);
2438
f2e0899f 2439 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2440
c4ff7cbf
EG		 2441 /* Give the FW up to 5 second (500*10ms) */
2442 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2443
2444 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2445 cnt*delay, rc, seq);
2446
2447 /* is this a reply to our command? */
2448 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2449 rc &= FW_MSG_CODE_MASK;
2450 else {
2451 /* FW BUG! */
2452 BNX2X_ERR("FW failed to respond!\n");
2453 bnx2x_fw_dump(bp);
2454 rc = 0;
2455 }
c4ff7cbf 2456 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2457
2458 return rc;
2459}
2460
ec6ba945 2461
619c5cb6
VZ		 2462void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2463{
2464 if (CHIP_IS_E1x(bp)) {
2465 struct tstorm_eth_function_common_config tcfg = {0};
2466
2467 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2468 }
2469
2470 /* Enable the function in the FW */
2471 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2472 storm_memset_func_en(bp, p->func_id, 1);
2473
2474 /* spq */
2475 if (p->func_flgs & FUNC_FLG_SPQ) {
2476 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2477 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2478 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2479 }
2480}
2481
6383c0b3
AE		 2482/**
2483 * bnx2x_get_tx_only_flags - Return common flags
2484 *
2485 * @bp device handle
2486 * @fp queue handle
2487 * @zero_stats TRUE if statistics zeroing is needed
2488 *
2489 * Return the flags that are common for the Tx-only and not normal connections.
2490 */
2491static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2492 struct bnx2x_fastpath *fp,
2493 bool zero_stats)
28912902 2494{
619c5cb6
VZ		 2495 unsigned long flags = 0;
2496
2497 /* PF driver will always initialize the Queue to an ACTIVE state */
2498 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2499
6383c0b3
AE		 2500 /* tx only connections collect statistics (on the same index as the
2501 * parent connection). The statistics are zeroed when the parent
2502 * connection is initialized.
2503 */
50f0a562
BW		 2504
2505 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2506 if (zero_stats)
2507 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2508
6383c0b3
AE		 2509
2510 return flags;
2511}
2512
2513static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2514 struct bnx2x_fastpath *fp,
2515 bool leading)
2516{
2517 unsigned long flags = 0;
2518
619c5cb6
VZ		 2519 /* calculate other queue flags */
2520 if (IS_MF_SD(bp))
2521 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2522
619c5cb6
VZ		 2523 if (IS_FCOE_FP(fp))
2524 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
523224a3 2525
f5219d8e 2526 if (!fp->disable_tpa) {
619c5cb6 2527 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 2528 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 2529 if (fp->mode == TPA_MODE_GRO)
2530 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 2531 }
619c5cb6 2532
619c5cb6
VZ		 2533 if (leading) {
2534 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2535 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2536 }
523224a3 2537
619c5cb6
VZ		 2538 /* Always set HW VLAN stripping */
2539 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 2540
6383c0b3
AE		 2541
2542 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 2543}
2544
619c5cb6 2545static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 2546 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2547 u8 cos)
619c5cb6
VZ		 2548{
2549 gen_init->stat_id = bnx2x_stats_id(fp);
2550 gen_init->spcl_id = fp->cl_id;
2551
2552 /* Always use mini-jumbo MTU for FCoE L2 ring */
2553 if (IS_FCOE_FP(fp))
2554 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2555 else
2556 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 2557
2558 gen_init->cos = cos;
619c5cb6
VZ		 2559}
2560
2561static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2562 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2563 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2564{
619c5cb6 2565 u8 max_sge = 0;
523224a3
DK		 2566 u16 sge_sz = 0;
2567 u16 tpa_agg_size = 0;
2568
523224a3 2569 if (!fp->disable_tpa) {
dfacf138
DK		 2570 pause->sge_th_lo = SGE_TH_LO(bp);
2571 pause->sge_th_hi = SGE_TH_HI(bp);
2572
2573 /* validate SGE ring has enough to cross high threshold */
2574 WARN_ON(bp->dropless_fc &&
2575 pause->sge_th_hi + FW_PREFETCH_CNT >
2576 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2577
523224a3
DK		 2578 tpa_agg_size = min_t(u32,
2579 (min_t(u32, 8, MAX_SKB_FRAGS) *
2580 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2581 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2582 SGE_PAGE_SHIFT;
2583 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2584 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2585 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2586 0xffff);
2587 }
2588
2589 /* pause - not for e1 */
2590 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 2591 pause->bd_th_lo = BD_TH_LO(bp);
2592 pause->bd_th_hi = BD_TH_HI(bp);
2593
2594 pause->rcq_th_lo = RCQ_TH_LO(bp);
2595 pause->rcq_th_hi = RCQ_TH_HI(bp);
2596 /*
2597 * validate that rings have enough entries to cross
2598 * high thresholds
2599 */
2600 WARN_ON(bp->dropless_fc &&
2601 pause->bd_th_hi + FW_PREFETCH_CNT >
2602 bp->rx_ring_size);
2603 WARN_ON(bp->dropless_fc &&
2604 pause->rcq_th_hi + FW_PREFETCH_CNT >
2605 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 2606
523224a3
DK		 2607 pause->pri_map = 1;
2608 }
2609
2610 /* rxq setup */
523224a3
DK		 2611 rxq_init->dscr_map = fp->rx_desc_mapping;
2612 rxq_init->sge_map = fp->rx_sge_mapping;
2613 rxq_init->rcq_map = fp->rx_comp_mapping;
2614 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 2615
619c5cb6
VZ		 2616 /* This should be a maximum number of data bytes that may be
2617 * placed on the BD (not including paddings).
2618 */
e52fcb24
ED		 2619 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2620 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 2621
523224a3 2622 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 2623 rxq_init->tpa_agg_sz = tpa_agg_size;
2624 rxq_init->sge_buf_sz = sge_sz;
2625 rxq_init->max_sges_pkt = max_sge;
619c5cb6 2626 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 2627 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 2628
2629 /* Maximum number or simultaneous TPA aggregation for this Queue.
2630 *
2631 * For PF Clients it should be the maximum avaliable number.
2632 * VF driver(s) may want to define it to a smaller value.
2633 */
dfacf138 2634 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 2635
523224a3
DK		 2636 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2637 rxq_init->fw_sb_id = fp->fw_sb_id;
2638
ec6ba945
VZ		 2639 if (IS_FCOE_FP(fp))
2640 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2641 else
6383c0b3 2642 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
523224a3
DK		 2643}
2644
619c5cb6 2645static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 2646 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2647 u8 cos)
523224a3 2648{
6383c0b3
AE		 2649 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2650 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 2651 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2652 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 2653
619c5cb6
VZ		 2654 /*
2655 * set the tss leading client id for TX classfication ==
2656 * leading RSS client id
2657 */
2658 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2659
ec6ba945
VZ		 2660 if (IS_FCOE_FP(fp)) {
2661 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2662 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2663 }
523224a3
DK		 2664}
2665
8d96286a 2666static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2667{
2668 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 2669 struct event_ring_data eq_data = { {0} };
2670 u16 flags;
2671
619c5cb6 2672 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2673 /* reset IGU PF statistics: MSIX + ATTN */
2674 /* PF */
2675 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2676 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2677 (CHIP_MODE_IS_4_PORT(bp) ?
2678 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2679 /* ATTN */
2680 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2681 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2682 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2683 (CHIP_MODE_IS_4_PORT(bp) ?
2684 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2685 }
2686
523224a3
DK		 2687 /* function setup flags */
2688 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2689
619c5cb6
VZ		 2690 /* This flag is relevant for E1x only.
2691 * E2 doesn't have a TPA configuration in a function level.
523224a3 2692 */
619c5cb6 2693 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 2694
2695 func_init.func_flgs = flags;
2696 func_init.pf_id = BP_FUNC(bp);
2697 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 2698 func_init.spq_map = bp->spq_mapping;
2699 func_init.spq_prod = bp->spq_prod_idx;
2700
2701 bnx2x_func_init(bp, &func_init);
2702
2703 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2704
2705 /*
619c5cb6
VZ		 2706 * Congestion management values depend on the link rate
2707 * There is no active link so initial link rate is set to 10 Gbps.
2708 * When the link comes up The congestion management values are
2709 * re-calculated according to the actual link rate.
2710 */
523224a3
DK		 2711 bp->link_vars.line_speed = SPEED_10000;
2712 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2713
2714 /* Only the PMF sets the HW */
2715 if (bp->port.pmf)
2716 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2717
523224a3
DK		 2718 /* init Event Queue */
2719 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2720 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2721 eq_data.producer = bp->eq_prod;
2722 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2723 eq_data.sb_id = DEF_SB_ID;
2724 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2725}
2726
2727
2728static void bnx2x_e1h_disable(struct bnx2x *bp)
2729{
2730 int port = BP_PORT(bp);
2731
619c5cb6 2732 bnx2x_tx_disable(bp);
523224a3
DK		 2733
2734 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 2735}
2736
2737static void bnx2x_e1h_enable(struct bnx2x *bp)
2738{
2739 int port = BP_PORT(bp);
2740
2741 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2742
2743 /* Tx queue should be only reenabled */
2744 netif_tx_wake_all_queues(bp->dev);
2745
2746 /*
2747 * Should not call netif_carrier_on since it will be called if the link
2748 * is up when checking for link state
2749 */
2750}
2751
1d187b34
BW		 2752#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
2753
2754static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
2755{
2756 struct eth_stats_info *ether_stat =
2757 &bp->slowpath->drv_info_to_mcp.ether_stat;
2758
2759 /* leave last char as NULL */
2760 memcpy(ether_stat->version, DRV_MODULE_VERSION,
2761 ETH_STAT_INFO_VERSION_LEN - 1);
2762
2763 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj,
2764 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
2765 ether_stat->mac_local);
2766
2767 ether_stat->mtu_size = bp->dev->mtu;
2768
2769 if (bp->dev->features & NETIF_F_RXCSUM)
2770 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
2771 if (bp->dev->features & NETIF_F_TSO)
2772 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
2773 ether_stat->feature_flags |= bp->common.boot_mode;
2774
2775 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
2776
2777 ether_stat->txq_size = bp->tx_ring_size;
2778 ether_stat->rxq_size = bp->rx_ring_size;
2779}
2780
2781static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
2782{
f2fd5c34 2783#ifdef BCM_CNIC
1d187b34
BW		 2784 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
2785 struct fcoe_stats_info *fcoe_stat =
2786 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
2787
2788 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN);
2789
2790 fcoe_stat->qos_priority =
2791 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
2792
2793 /* insert FCoE stats from ramrod response */
2794 if (!NO_FCOE(bp)) {
2795 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
2796 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2797 tstorm_queue_statistics;
2798
2799 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
2800 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2801 xstorm_queue_statistics;
2802
2803 struct fcoe_statistics_params *fw_fcoe_stat =
2804 &bp->fw_stats_data->fcoe;
2805
2806 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
2807 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
2808
2809 ADD_64(fcoe_stat->rx_bytes_hi,
2810 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
2811 fcoe_stat->rx_bytes_lo,
2812 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
2813
2814 ADD_64(fcoe_stat->rx_bytes_hi,
2815 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
2816 fcoe_stat->rx_bytes_lo,
2817 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
2818
2819 ADD_64(fcoe_stat->rx_bytes_hi,
2820 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
2821 fcoe_stat->rx_bytes_lo,
2822 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
2823
2824 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2825 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
2826
2827 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2828 fcoe_q_tstorm_stats->rcv_ucast_pkts);
2829
2830 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2831 fcoe_q_tstorm_stats->rcv_bcast_pkts);
2832
2833 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
f33f1fcc 2834 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34
BW		 2835
2836 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
2837 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
2838
2839 ADD_64(fcoe_stat->tx_bytes_hi,
2840 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
2841 fcoe_stat->tx_bytes_lo,
2842 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
2843
2844 ADD_64(fcoe_stat->tx_bytes_hi,
2845 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
2846 fcoe_stat->tx_bytes_lo,
2847 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
2848
2849 ADD_64(fcoe_stat->tx_bytes_hi,
2850 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
2851 fcoe_stat->tx_bytes_lo,
2852 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
2853
2854 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
2855 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
2856
2857 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
2858 fcoe_q_xstorm_stats->ucast_pkts_sent);
2859
2860 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
2861 fcoe_q_xstorm_stats->bcast_pkts_sent);
2862
2863 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
2864 fcoe_q_xstorm_stats->mcast_pkts_sent);
2865 }
2866
1d187b34
BW		 2867 /* ask L5 driver to add data to the struct */
2868 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
2869#endif
2870}
2871
2872static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
2873{
f2fd5c34 2874#ifdef BCM_CNIC
1d187b34
BW		 2875 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
2876 struct iscsi_stats_info *iscsi_stat =
2877 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
2878
2879 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
2880
2881 iscsi_stat->qos_priority =
2882 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
2883
1d187b34
BW		 2884 /* ask L5 driver to add data to the struct */
2885 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
2886#endif
2887}
2888
0793f83f
DK		 2889/* called due to MCP event (on pmf):
2890 * reread new bandwidth configuration
2891 * configure FW
2892 * notify others function about the change
2893 */
2894static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2895{
2896 if (bp->link_vars.link_up) {
2897 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2898 bnx2x_link_sync_notify(bp);
2899 }
2900 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2901}
2902
2903static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2904{
2905 bnx2x_config_mf_bw(bp);
2906 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2907}
2908
1d187b34
BW		 2909static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
2910{
2911 enum drv_info_opcode op_code;
2912 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
2913
2914 /* if drv_info version supported by MFW doesn't match - send NACK */
2915 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
2916 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
2917 return;
2918 }
2919
2920 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
2921 DRV_INFO_CONTROL_OP_CODE_SHIFT;
2922
2923 memset(&bp->slowpath->drv_info_to_mcp, 0,
2924 sizeof(union drv_info_to_mcp));
2925
2926 switch (op_code) {
2927 case ETH_STATS_OPCODE:
2928 bnx2x_drv_info_ether_stat(bp);
2929 break;
2930 case FCOE_STATS_OPCODE:
2931 bnx2x_drv_info_fcoe_stat(bp);
2932 break;
2933 case ISCSI_STATS_OPCODE:
2934 bnx2x_drv_info_iscsi_stat(bp);
2935 break;
2936 default:
2937 /* if op code isn't supported - send NACK */
2938 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
2939 return;
2940 }
2941
2942 /* if we got drv_info attn from MFW then these fields are defined in
2943 * shmem2 for sure
2944 */
2945 SHMEM2_WR(bp, drv_info_host_addr_lo,
2946 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
2947 SHMEM2_WR(bp, drv_info_host_addr_hi,
2948 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
2949
2950 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
2951}
2952
523224a3
DK		 2953static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2954{
2955 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2956
2957 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2958
2959 /*
2960 * This is the only place besides the function initialization
2961 * where the bp->flags can change so it is done without any
2962 * locks
2963 */
f2e0899f 2964 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 2965 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 2966 bp->flags |= MF_FUNC_DIS;
2967
2968 bnx2x_e1h_disable(bp);
2969 } else {
51c1a580 2970 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 2971 bp->flags &= ~MF_FUNC_DIS;
2972
2973 bnx2x_e1h_enable(bp);
2974 }
2975 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2976 }
2977 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2978 bnx2x_config_mf_bw(bp);
523224a3
DK		 2979 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2980 }
2981
2982 /* Report results to MCP */
2983 if (dcc_event)
2984 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2985 else
2986 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2987}
2988
2989/* must be called under the spq lock */
2990static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2991{
2992 struct eth_spe *next_spe = bp->spq_prod_bd;
2993
2994 if (bp->spq_prod_bd == bp->spq_last_bd) {
2995 bp->spq_prod_bd = bp->spq;
2996 bp->spq_prod_idx = 0;
51c1a580 2997 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 2998 } else {
2999 bp->spq_prod_bd++;
3000 bp->spq_prod_idx++;
3001 }
3002 return next_spe;
3003}
3004
3005/* must be called under the spq lock */
28912902
MC		 3006static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3007{
3008 int func = BP_FUNC(bp);
3009
53e51e2f
VZ		 3010 /*
3011 * Make sure that BD data is updated before writing the producer:
3012 * BD data is written to the memory, the producer is read from the
3013 * memory, thus we need a full memory barrier to ensure the ordering.
3014 */
3015 mb();
28912902 3016
523224a3 3017 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3018 bp->spq_prod_idx);
28912902
MC		 3019 mmiowb();
3020}
3021
619c5cb6
VZ		 3022/**
3023 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3024 *
3025 * @cmd: command to check
3026 * @cmd_type: command type
3027 */
3028static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3029{
3030 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3031 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3032 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3033 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3034 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3035 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3036 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3037 return true;
3038 else
3039 return false;
3040
3041}
3042
3043
3044/**
3045 * bnx2x_sp_post - place a single command on an SP ring
3046 *
3047 * @bp: driver handle
3048 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3049 * @cid: SW CID the command is related to
3050 * @data_hi: command private data address (high 32 bits)
3051 * @data_lo: command private data address (low 32 bits)
3052 * @cmd_type: command type (e.g. NONE, ETH)
3053 *
3054 * SP data is handled as if it's always an address pair, thus data fields are
3055 * not swapped to little endian in upper functions. Instead this function swaps
3056 * data as if it's two u32 fields.
3057 */
9f6c9258 3058int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3059 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3060{
28912902 3061 struct eth_spe *spe;
523224a3 3062 u16 type;
619c5cb6 3063 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3064
a2fbb9ea 3065#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3066 if (unlikely(bp->panic)) {
3067 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3068 return -EIO;
51c1a580 3069 }
a2fbb9ea
ET		 3070#endif
3071
34f80b04 3072 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3073
6e30dd4e
VZ		 3074 if (common) {
3075 if (!atomic_read(&bp->eq_spq_left)) {
3076 BNX2X_ERR("BUG! EQ ring full!\n");
3077 spin_unlock_bh(&bp->spq_lock);
3078 bnx2x_panic();
3079 return -EBUSY;
3080 }
3081 } else if (!atomic_read(&bp->cq_spq_left)) {
3082 BNX2X_ERR("BUG! SPQ ring full!\n");
3083 spin_unlock_bh(&bp->spq_lock);
3084 bnx2x_panic();
3085 return -EBUSY;
a2fbb9ea 3086 }
f1410647 3087
28912902
MC		 3088 spe = bnx2x_sp_get_next(bp);
3089
a2fbb9ea 3090 /* CID needs port number to be encoded int it */
28912902 3091 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3092 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3093 HW_CID(bp, cid));
523224a3 3094
619c5cb6 3095 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 3096
523224a3
DK		 3097 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3098 SPE_HDR_FUNCTION_ID);
a2fbb9ea 3099
523224a3
DK		 3100 spe->hdr.type = cpu_to_le16(type);
3101
3102 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3103 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3104
d6cae238
VZ		 3105 /*
3106 * It's ok if the actual decrement is issued towards the memory
3107 * somewhere between the spin_lock and spin_unlock. Thus no
3108 * more explict memory barrier is needed.
3109 */
3110 if (common)
3111 atomic_dec(&bp->eq_spq_left);
3112 else
3113 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3114
a2fbb9ea 3115
51c1a580
MS		 3116 DP(BNX2X_MSG_SP,
3117 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3118 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3119 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3120 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3121 HW_CID(bp, cid), data_hi, data_lo, type,
3122 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3123
28912902 3124 bnx2x_sp_prod_update(bp);
34f80b04 3125 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3126 return 0;
3127}
3128
3129/* acquire split MCP access lock register */
4a37fb66 3130static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3131{
72fd0718 3132 u32 j, val;
34f80b04 3133 int rc = 0;
a2fbb9ea
ET		 3134
3135 might_sleep();
72fd0718 3136 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 3137 val = (1UL << 31);
3138 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3139 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3140 if (val & (1L << 31))
3141 break;
3142
3143 msleep(5);
3144 }
a2fbb9ea 3145 if (!(val & (1L << 31))) {
19680c48 3146 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3147 rc = -EBUSY;
3148 }
3149
3150 return rc;
3151}
3152
4a37fb66
YG		 3153/* release split MCP access lock register */
3154static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3155{
72fd0718 3156 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 3157}
3158
523224a3
DK		 3159#define BNX2X_DEF_SB_ATT_IDX 0x0001
3160#define BNX2X_DEF_SB_IDX 0x0002
3161
a2fbb9ea
ET		 3162static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3163{
523224a3 3164 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3165 u16 rc = 0;
3166
3167 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3168 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3169 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3170 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3171 }
523224a3
DK		 3172
3173 if (bp->def_idx != def_sb->sp_sb.running_index) {
3174 bp->def_idx = def_sb->sp_sb.running_index;
3175 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3176 }
523224a3
DK		 3177
3178 /* Do not reorder: indecies reading should complete before handling */
3179 barrier();
a2fbb9ea
ET		 3180 return rc;
3181}
3182
3183/*
3184 * slow path service functions
3185 */
3186
3187static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3188{
34f80b04 3189 int port = BP_PORT(bp);
a2fbb9ea
ET		 3190 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3191 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3192 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3193 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3194 u32 aeu_mask;
87942b46 3195 u32 nig_mask = 0;
f2e0899f 3196 u32 reg_addr;
a2fbb9ea 3197
a2fbb9ea
ET		 3198 if (bp->attn_state & asserted)
3199 BNX2X_ERR("IGU ERROR\n");
3200
3fcaf2e5
EG		 3201 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3202 aeu_mask = REG_RD(bp, aeu_addr);
3203
a2fbb9ea 3204 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3205 aeu_mask, asserted);
72fd0718 3206 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3207 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3208
3fcaf2e5
EG		 3209 REG_WR(bp, aeu_addr, aeu_mask);
3210 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3211
3fcaf2e5 3212 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3213 bp->attn_state |= asserted;
3fcaf2e5 3214 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3215
3216 if (asserted & ATTN_HARD_WIRED_MASK) {
3217 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3218
a5e9a7cf
EG		 3219 bnx2x_acquire_phy_lock(bp);
3220
877e9aa4 3221 /* save nig interrupt mask */
87942b46 3222 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3223
361c391e
YR		 3224 /* If nig_mask is not set, no need to call the update
3225 * function.
3226 */
3227 if (nig_mask) {
3228 REG_WR(bp, nig_int_mask_addr, 0);
3229
3230 bnx2x_link_attn(bp);
3231 }
a2fbb9ea
ET		 3232
3233 /* handle unicore attn? */
3234 }
3235 if (asserted & ATTN_SW_TIMER_4_FUNC)
3236 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3237
3238 if (asserted & GPIO_2_FUNC)
3239 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3240
3241 if (asserted & GPIO_3_FUNC)
3242 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3243
3244 if (asserted & GPIO_4_FUNC)
3245 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3246
3247 if (port == 0) {
3248 if (asserted & ATTN_GENERAL_ATTN_1) {
3249 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3250 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3251 }
3252 if (asserted & ATTN_GENERAL_ATTN_2) {
3253 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3254 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3255 }
3256 if (asserted & ATTN_GENERAL_ATTN_3) {
3257 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3258 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3259 }
3260 } else {
3261 if (asserted & ATTN_GENERAL_ATTN_4) {
3262 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3263 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3264 }
3265 if (asserted & ATTN_GENERAL_ATTN_5) {
3266 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3267 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3268 }
3269 if (asserted & ATTN_GENERAL_ATTN_6) {
3270 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3271 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3272 }
3273 }
3274
3275 } /* if hardwired */
3276
f2e0899f
DK		 3277 if (bp->common.int_block == INT_BLOCK_HC)
3278 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3279 COMMAND_REG_ATTN_BITS_SET);
3280 else
3281 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3282
3283 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3284 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3285 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3286
3287 /* now set back the mask */
a5e9a7cf 3288 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 3289 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3290 bnx2x_release_phy_lock(bp);
3291 }
a2fbb9ea
ET		 3292}
3293
fd4ef40d
EG		 3294static inline void bnx2x_fan_failure(struct bnx2x *bp)
3295{
3296 int port = BP_PORT(bp);
b7737c9b 3297 u32 ext_phy_config;
fd4ef40d 3298 /* mark the failure */
b7737c9b
YR		 3299 ext_phy_config =
3300 SHMEM_RD(bp,
3301 dev_info.port_hw_config[port].external_phy_config);
3302
3303 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3304 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3305 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3306 ext_phy_config);
fd4ef40d
EG		 3307
3308 /* log the failure */
51c1a580
MS		 3309 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3310 "Please contact OEM Support for assistance\n");
8304859a
AE		 3311
3312 /*
3313 * Scheudle device reset (unload)
3314 * This is due to some boards consuming sufficient power when driver is
3315 * up to overheat if fan fails.
3316 */
3317 smp_mb__before_clear_bit();
3318 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3319 smp_mb__after_clear_bit();
3320 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3321
fd4ef40d 3322}
ab6ad5a4 3323
877e9aa4 3324static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3325{
34f80b04 3326 int port = BP_PORT(bp);
877e9aa4 3327 int reg_offset;
d90d96ba 3328 u32 val;
877e9aa4 3329
34f80b04
EG		 3330 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3331 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3332
34f80b04 3333 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3334
3335 val = REG_RD(bp, reg_offset);
3336 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3337 REG_WR(bp, reg_offset, val);
3338
3339 BNX2X_ERR("SPIO5 hw attention\n");
3340
fd4ef40d 3341 /* Fan failure attention */
d90d96ba 3342 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3343 bnx2x_fan_failure(bp);
877e9aa4 3344 }
34f80b04 3345
3deb8167 3346 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3347 bnx2x_acquire_phy_lock(bp);
3348 bnx2x_handle_module_detect_int(&bp->link_params);
3349 bnx2x_release_phy_lock(bp);
3350 }
3351
34f80b04
EG		 3352 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3353
3354 val = REG_RD(bp, reg_offset);
3355 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3356 REG_WR(bp, reg_offset, val);
3357
3358 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3359 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3360 bnx2x_panic();
3361 }
877e9aa4
ET		 3362}
3363
3364static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3365{
3366 u32 val;
3367
0626b899 3368 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3369
3370 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3371 BNX2X_ERR("DB hw attention 0x%x\n", val);
3372 /* DORQ discard attention */
3373 if (val & 0x2)
3374 BNX2X_ERR("FATAL error from DORQ\n");
3375 }
34f80b04
EG		 3376
3377 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3378
3379 int port = BP_PORT(bp);
3380 int reg_offset;
3381
3382 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3383 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3384
3385 val = REG_RD(bp, reg_offset);
3386 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3387 REG_WR(bp, reg_offset, val);
3388
3389 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3390 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3391 bnx2x_panic();
3392 }
877e9aa4
ET		 3393}
3394
3395static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3396{
3397 u32 val;
3398
3399 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3400
3401 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3402 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3403 /* CFC error attention */
3404 if (val & 0x2)
3405 BNX2X_ERR("FATAL error from CFC\n");
3406 }
3407
3408 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3409 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3410 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3411 /* RQ_USDMDP_FIFO_OVERFLOW */
3412 if (val & 0x18000)
3413 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3414
3415 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3416 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3417 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3418 }
877e9aa4 3419 }
34f80b04
EG		 3420
3421 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3422
3423 int port = BP_PORT(bp);
3424 int reg_offset;
3425
3426 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3427 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3428
3429 val = REG_RD(bp, reg_offset);
3430 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3431 REG_WR(bp, reg_offset, val);
3432
3433 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3434 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3435 bnx2x_panic();
3436 }
877e9aa4
ET		 3437}
3438
3439static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3440{
34f80b04
EG		 3441 u32 val;
3442
877e9aa4
ET		 3443 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3444
34f80b04
EG		 3445 if (attn & BNX2X_PMF_LINK_ASSERT) {
3446 int func = BP_FUNC(bp);
3447
3448 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3449 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3450 func_mf_config[BP_ABS_FUNC(bp)].config);
3451 val = SHMEM_RD(bp,
3452 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3453 if (val & DRV_STATUS_DCC_EVENT_MASK)
3454 bnx2x_dcc_event(bp,
3455 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3456
3457 if (val & DRV_STATUS_SET_MF_BW)
3458 bnx2x_set_mf_bw(bp);
3459
1d187b34
BW		 3460 if (val & DRV_STATUS_DRV_INFO_REQ)
3461 bnx2x_handle_drv_info_req(bp);
2691d51d 3462 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3463 bnx2x_pmf_update(bp);
3464
e4901dde 3465 if (bp->port.pmf &&
785b9b1a
SR		 3466 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3467 bp->dcbx_enabled > 0)
e4901dde
VZ		 3468 /* start dcbx state machine */
3469 bnx2x_dcbx_set_params(bp,
3470 BNX2X_DCBX_STATE_NEG_RECEIVED);
3deb8167
YR		 3471 if (bp->link_vars.periodic_flags &
3472 PERIODIC_FLAGS_LINK_EVENT) {
3473 /* sync with link */
3474 bnx2x_acquire_phy_lock(bp);
3475 bp->link_vars.periodic_flags &=
3476 ~PERIODIC_FLAGS_LINK_EVENT;
3477 bnx2x_release_phy_lock(bp);
3478 if (IS_MF(bp))
3479 bnx2x_link_sync_notify(bp);
3480 bnx2x_link_report(bp);
3481 }
3482 /* Always call it here: bnx2x_link_report() will
3483 * prevent the link indication duplication.
3484 */
3485 bnx2x__link_status_update(bp);
34f80b04 3486 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3487
3488 BNX2X_ERR("MC assert!\n");
d6cae238 3489 bnx2x_mc_assert(bp);
877e9aa4
ET		 3490 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3491 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3492 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3493 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3494 bnx2x_panic();
3495
3496 } else if (attn & BNX2X_MCP_ASSERT) {
3497
3498 BNX2X_ERR("MCP assert!\n");
3499 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3500 bnx2x_fw_dump(bp);
877e9aa4
ET		 3501
3502 } else
3503 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3504 }
3505
3506 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3507 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3508 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3509 val = CHIP_IS_E1(bp) ? 0 :
3510 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3511 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3512 }
3513 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3514 val = CHIP_IS_E1(bp) ? 0 :
3515 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3516 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3517 }
877e9aa4 3518 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3519 }
3520}
3521
c9ee9206
VZ		 3522/*
3523 * Bits map:
3524 * 0-7 - Engine0 load counter.
3525 * 8-15 - Engine1 load counter.
3526 * 16 - Engine0 RESET_IN_PROGRESS bit.
3527 * 17 - Engine1 RESET_IN_PROGRESS bit.
3528 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3529 * on the engine
3530 * 19 - Engine1 ONE_IS_LOADED.
3531 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3532 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3533 * just the one belonging to its engine).
3534 *
3535 */
3536#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3537
3538#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3539#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3540#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3541#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3542#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3543#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3544#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3545
3546/*
3547 * Set the GLOBAL_RESET bit.
3548 *
3549 * Should be run under rtnl lock
3550 */
3551void bnx2x_set_reset_global(struct bnx2x *bp)
3552{
f16da43b
AE		 3553 u32 val;
3554 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3555 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 3556 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 3557 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 3558}
3559
3560/*
3561 * Clear the GLOBAL_RESET bit.
3562 *
3563 * Should be run under rtnl lock
3564 */
3565static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3566{
f16da43b
AE		 3567 u32 val;
3568 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3569 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 3570 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 3571 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 3572}
f85582f8 3573
72fd0718 3574/*
c9ee9206
VZ		 3575 * Checks the GLOBAL_RESET bit.
3576 *
72fd0718
VZ		 3577 * should be run under rtnl lock
3578 */
c9ee9206
VZ		 3579static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3580{
3581 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3582
3583 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3584 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3585}
3586
3587/*
3588 * Clear RESET_IN_PROGRESS bit for the current engine.
3589 *
3590 * Should be run under rtnl lock
3591 */
72fd0718
VZ		 3592static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3593{
f16da43b 3594 u32 val;
c9ee9206
VZ		 3595 u32 bit = BP_PATH(bp) ?
3596 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 3597 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3598 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 3599
3600 /* Clear the bit */
3601 val &= ~bit;
3602 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 3603
3604 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 3605}
3606
3607/*
c9ee9206
VZ		 3608 * Set RESET_IN_PROGRESS for the current engine.
3609 *
72fd0718
VZ		 3610 * should be run under rtnl lock
3611 */
c9ee9206 3612void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 3613{
f16da43b 3614 u32 val;
c9ee9206
VZ		 3615 u32 bit = BP_PATH(bp) ?
3616 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 3617 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3618 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 3619
3620 /* Set the bit */
3621 val |= bit;
3622 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 3623 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 3624}
3625
3626/*
c9ee9206 3627 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 3628 * should be run under rtnl lock
3629 */
c9ee9206 3630bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 3631{
c9ee9206
VZ		 3632 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3633 u32 bit = engine ?
3634 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3635
3636 /* return false if bit is set */
3637 return (val & bit) ? false : true;
72fd0718
VZ		 3638}
3639
3640/*
889b9af3 3641 * set pf load for the current pf.
c9ee9206 3642 *
72fd0718
VZ		 3643 * should be run under rtnl lock
3644 */
889b9af3 3645void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 3646{
f16da43b 3647 u32 val1, val;
c9ee9206
VZ		 3648 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3649 BNX2X_PATH0_LOAD_CNT_MASK;
3650 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3651 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 3652
f16da43b
AE		 3653 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3654 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3655
51c1a580 3656 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 3657
c9ee9206
VZ		 3658 /* get the current counter value */
3659 val1 = (val & mask) >> shift;
3660
889b9af3
AE		 3661 /* set bit of that PF */
3662 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 3663
3664 /* clear the old value */
3665 val &= ~mask;
3666
3667 /* set the new one */
3668 val |= ((val1 << shift) & mask);
3669
3670 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 3671 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 3672}
3673
c9ee9206 3674/**
889b9af3 3675 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 3676 *
3677 * @bp: driver handle
3678 *
3679 * Should be run under rtnl lock.
3680 * Decrements the load counter for the current engine. Returns
889b9af3 3681 * whether other functions are still loaded
72fd0718 3682 */
889b9af3 3683bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 3684{
f16da43b 3685 u32 val1, val;
c9ee9206
VZ		 3686 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3687 BNX2X_PATH0_LOAD_CNT_MASK;
3688 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3689 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 3690
f16da43b
AE		 3691 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3692 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 3693 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 3694
c9ee9206
VZ		 3695 /* get the current counter value */
3696 val1 = (val & mask) >> shift;
3697
889b9af3
AE		 3698 /* clear bit of that PF */
3699 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 3700
3701 /* clear the old value */
3702 val &= ~mask;
3703
3704 /* set the new one */
3705 val |= ((val1 << shift) & mask);
3706
3707 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 3708 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3709 return val1 != 0;
72fd0718
VZ		 3710}
3711
3712/*
889b9af3 3713 * Read the load status for the current engine.
c9ee9206 3714 *
72fd0718
VZ		 3715 * should be run under rtnl lock
3716 */
889b9af3 3717static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 3718{
c9ee9206
VZ		 3719 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3720 BNX2X_PATH0_LOAD_CNT_MASK);
3721 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3722 BNX2X_PATH0_LOAD_CNT_SHIFT);
3723 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3724
51c1a580 3725 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 3726
3727 val = (val & mask) >> shift;
3728
51c1a580
MS		 3729 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
3730 engine, val);
c9ee9206 3731
889b9af3 3732 return val != 0;
72fd0718
VZ		 3733}
3734
c9ee9206 3735/*
889b9af3 3736 * Reset the load status for the current engine.
c9ee9206 3737 */
889b9af3 3738static inline void bnx2x_clear_load_status(struct bnx2x *bp)
72fd0718 3739{
f16da43b 3740 u32 val;
c9ee9206 3741 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
f16da43b
AE		 3742 BNX2X_PATH0_LOAD_CNT_MASK);
3743 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3744 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 3745 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
f16da43b 3746 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 3747}
3748
3749static inline void _print_next_block(int idx, const char *blk)
3750{
f1deab50 3751 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 3752}
3753
c9ee9206
VZ		 3754static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3755 bool print)
72fd0718
VZ		 3756{
3757 int i = 0;
3758 u32 cur_bit = 0;
3759 for (i = 0; sig; i++) {
3760 cur_bit = ((u32)0x1 << i);
3761 if (sig & cur_bit) {
3762 switch (cur_bit) {
3763 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
c9ee9206
VZ		 3764 if (print)
3765 _print_next_block(par_num++, "BRB");
72fd0718
VZ		 3766 break;
3767 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
c9ee9206
VZ		 3768 if (print)
3769 _print_next_block(par_num++, "PARSER");
72fd0718
VZ		 3770 break;
3771 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
c9ee9206
VZ		 3772 if (print)
3773 _print_next_block(par_num++, "TSDM");
72fd0718
VZ		 3774 break;
3775 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
c9ee9206
VZ		 3776 if (print)
3777 _print_next_block(par_num++,
3778 "SEARCHER");
3779 break;
3780 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3781 if (print)
3782 _print_next_block(par_num++, "TCM");
72fd0718
VZ		 3783 break;
3784 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
c9ee9206
VZ		 3785 if (print)
3786 _print_next_block(par_num++, "TSEMI");
3787 break;
3788 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3789 if (print)
3790 _print_next_block(par_num++, "XPB");
72fd0718
VZ		 3791 break;
3792 }
3793
3794 /* Clear the bit */
3795 sig &= ~cur_bit;
3796 }
3797 }
3798
3799 return par_num;
3800}
3801
c9ee9206
VZ		 3802static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3803 bool *global, bool print)
72fd0718
VZ		 3804{
3805 int i = 0;
3806 u32 cur_bit = 0;
3807 for (i = 0; sig; i++) {
3808 cur_bit = ((u32)0x1 << i);
3809 if (sig & cur_bit) {
3810 switch (cur_bit) {
c9ee9206
VZ		 3811 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3812 if (print)
3813 _print_next_block(par_num++, "PBF");
72fd0718
VZ		 3814 break;
3815 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
c9ee9206
VZ		 3816 if (print)
3817 _print_next_block(par_num++, "QM");
3818 break;
3819 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3820 if (print)
3821 _print_next_block(par_num++, "TM");
72fd0718
VZ		 3822 break;
3823 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
c9ee9206
VZ		 3824 if (print)
3825 _print_next_block(par_num++, "XSDM");
3826 break;
3827 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3828 if (print)
3829 _print_next_block(par_num++, "XCM");
72fd0718
VZ		 3830 break;
3831 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
c9ee9206
VZ		 3832 if (print)
3833 _print_next_block(par_num++, "XSEMI");
72fd0718
VZ		 3834 break;
3835 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
c9ee9206
VZ		 3836 if (print)
3837 _print_next_block(par_num++,
3838 "DOORBELLQ");
3839 break;
3840 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3841 if (print)
3842 _print_next_block(par_num++, "NIG");
72fd0718
VZ		 3843 break;
3844 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206
VZ		 3845 if (print)
3846 _print_next_block(par_num++,
3847 "VAUX PCI CORE");
3848 *global = true;
72fd0718
VZ		 3849 break;
3850 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
c9ee9206
VZ		 3851 if (print)
3852 _print_next_block(par_num++, "DEBUG");
72fd0718
VZ		 3853 break;
3854 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
c9ee9206
VZ		 3855 if (print)
3856 _print_next_block(par_num++, "USDM");
72fd0718 3857 break;
8736c826
VZ		 3858 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3859 if (print)
3860 _print_next_block(par_num++, "UCM");
3861 break;
72fd0718 3862 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
c9ee9206
VZ		 3863 if (print)
3864 _print_next_block(par_num++, "USEMI");
72fd0718
VZ		 3865 break;
3866 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
c9ee9206
VZ		 3867 if (print)
3868 _print_next_block(par_num++, "UPB");
72fd0718
VZ		 3869 break;
3870 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
c9ee9206
VZ		 3871 if (print)
3872 _print_next_block(par_num++, "CSDM");
72fd0718 3873 break;
8736c826
VZ		 3874 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3875 if (print)
3876 _print_next_block(par_num++, "CCM");
3877 break;
72fd0718
VZ		 3878 }
3879
3880 /* Clear the bit */
3881 sig &= ~cur_bit;
3882 }
3883 }
3884
3885 return par_num;
3886}
3887
c9ee9206
VZ		 3888static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3889 bool print)
72fd0718
VZ		 3890{
3891 int i = 0;
3892 u32 cur_bit = 0;
3893 for (i = 0; sig; i++) {
3894 cur_bit = ((u32)0x1 << i);
3895 if (sig & cur_bit) {
3896 switch (cur_bit) {
3897 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
c9ee9206
VZ		 3898 if (print)
3899 _print_next_block(par_num++, "CSEMI");
72fd0718
VZ		 3900 break;
3901 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
c9ee9206
VZ		 3902 if (print)
3903 _print_next_block(par_num++, "PXP");
72fd0718
VZ		 3904 break;
3905 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
c9ee9206
VZ		 3906 if (print)
3907 _print_next_block(par_num++,
72fd0718
VZ		 3908 "PXPPCICLOCKCLIENT");
3909 break;
3910 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
c9ee9206
VZ		 3911 if (print)
3912 _print_next_block(par_num++, "CFC");
72fd0718
VZ		 3913 break;
3914 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
c9ee9206
VZ		 3915 if (print)
3916 _print_next_block(par_num++, "CDU");
3917 break;
3918 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3919 if (print)
3920 _print_next_block(par_num++, "DMAE");
72fd0718
VZ		 3921 break;
3922 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
c9ee9206
VZ		 3923 if (print)
3924 _print_next_block(par_num++, "IGU");
72fd0718
VZ		 3925 break;
3926 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
c9ee9206
VZ		 3927 if (print)
3928 _print_next_block(par_num++, "MISC");
72fd0718
VZ		 3929 break;
3930 }
3931
3932 /* Clear the bit */
3933 sig &= ~cur_bit;
3934 }
3935 }
3936
3937 return par_num;
3938}
3939
c9ee9206
VZ		 3940static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3941 bool *global, bool print)
72fd0718
VZ		 3942{
3943 int i = 0;
3944 u32 cur_bit = 0;
3945 for (i = 0; sig; i++) {
3946 cur_bit = ((u32)0x1 << i);
3947 if (sig & cur_bit) {
3948 switch (cur_bit) {
3949 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206
VZ		 3950 if (print)
3951 _print_next_block(par_num++, "MCP ROM");
3952 *global = true;
72fd0718
VZ		 3953 break;
3954 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206
VZ		 3955 if (print)
3956 _print_next_block(par_num++,
3957 "MCP UMP RX");
3958 *global = true;
72fd0718
VZ		 3959 break;
3960 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206
VZ		 3961 if (print)
3962 _print_next_block(par_num++,
3963 "MCP UMP TX");
3964 *global = true;
72fd0718
VZ		 3965 break;
3966 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206
VZ		 3967 if (print)
3968 _print_next_block(par_num++,
3969 "MCP SCPAD");
3970 *global = true;
72fd0718
VZ		 3971 break;
3972 }
3973
3974 /* Clear the bit */
3975 sig &= ~cur_bit;
3976 }
3977 }
3978
3979 return par_num;
3980}
3981
8736c826
VZ		 3982static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3983 bool print)
3984{
3985 int i = 0;
3986 u32 cur_bit = 0;
3987 for (i = 0; sig; i++) {
3988 cur_bit = ((u32)0x1 << i);
3989 if (sig & cur_bit) {
3990 switch (cur_bit) {
3991 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3992 if (print)
3993 _print_next_block(par_num++, "PGLUE_B");
3994 break;
3995 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3996 if (print)
3997 _print_next_block(par_num++, "ATC");
3998 break;
3999 }
4000
4001 /* Clear the bit */
4002 sig &= ~cur_bit;
4003 }
4004 }
4005
4006 return par_num;
4007}
4008
c9ee9206 4009static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
8736c826 4010 u32 *sig)
72fd0718 4011{
8736c826
VZ		 4012 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4013 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4014 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4015 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4016 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4017 int par_num = 0;
51c1a580
MS		 4018 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4019 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4020 sig[0] & HW_PRTY_ASSERT_SET_0,
4021 sig[1] & HW_PRTY_ASSERT_SET_1,
4022 sig[2] & HW_PRTY_ASSERT_SET_2,
4023 sig[3] & HW_PRTY_ASSERT_SET_3,
4024 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4025 if (print)
4026 netdev_err(bp->dev,
4027 "Parity errors detected in blocks: ");
4028 par_num = bnx2x_check_blocks_with_parity0(
8736c826 4029 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
c9ee9206 4030 par_num = bnx2x_check_blocks_with_parity1(
8736c826 4031 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
c9ee9206 4032 par_num = bnx2x_check_blocks_with_parity2(
8736c826 4033 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
c9ee9206 4034 par_num = bnx2x_check_blocks_with_parity3(
8736c826
VZ		 4035 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4036 par_num = bnx2x_check_blocks_with_parity4(
4037 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4038
c9ee9206
VZ		 4039 if (print)
4040 pr_cont("\n");
8736c826 4041
72fd0718
VZ		 4042 return true;
4043 } else
4044 return false;
4045}
4046
c9ee9206
VZ		 4047/**
4048 * bnx2x_chk_parity_attn - checks for parity attentions.
4049 *
4050 * @bp: driver handle
4051 * @global: true if there was a global attention
4052 * @print: show parity attention in syslog
4053 */
4054bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4055{
8736c826 4056 struct attn_route attn = { {0} };
72fd0718
VZ		 4057 int port = BP_PORT(bp);
4058
4059 attn.sig[0] = REG_RD(bp,
4060 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4061 port*4);
4062 attn.sig[1] = REG_RD(bp,
4063 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4064 port*4);
4065 attn.sig[2] = REG_RD(bp,
4066 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4067 port*4);
4068 attn.sig[3] = REG_RD(bp,
4069 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4070 port*4);
4071
8736c826
VZ		 4072 if (!CHIP_IS_E1x(bp))
4073 attn.sig[4] = REG_RD(bp,
4074 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4075 port*4);
4076
4077 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4078}
4079
f2e0899f
DK		 4080
4081static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4082{
4083 u32 val;
4084 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4085
4086 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4087 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4088 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 4089 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 4090 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 4091 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 4092 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 4093 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 4094 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 4095 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 4096 if (val &
4097 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 4098 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 4099 if (val &
4100 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 4101 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 4102 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 4103 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 4104 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 4105 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 4106 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 4107 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 4108 }
4109 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4110 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4111 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4112 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4113 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4114 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 4115 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 4116 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 4117 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 4118 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 4119 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 4120 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4121 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4122 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 4123 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 4124 }
4125
4126 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4127 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4128 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4129 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4130 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4131 }
4132
4133}
4134
72fd0718
VZ		 4135static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4136{
4137 struct attn_route attn, *group_mask;
34f80b04 4138 int port = BP_PORT(bp);
877e9aa4 4139 int index;
a2fbb9ea
ET		 4140 u32 reg_addr;
4141 u32 val;
3fcaf2e5 4142 u32 aeu_mask;
c9ee9206 4143 bool global = false;
a2fbb9ea
ET		 4144
4145 /* need to take HW lock because MCP or other port might also
4146 try to handle this event */
4a37fb66 4147 bnx2x_acquire_alr(bp);
a2fbb9ea 4148
c9ee9206
VZ		 4149 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4150#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4151 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4152 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4153 /* Disable HW interrupts */
4154 bnx2x_int_disable(bp);
72fd0718
VZ		 4155 /* In case of parity errors don't handle attentions so that
4156 * other function would "see" parity errors.
4157 */
c9ee9206
VZ		 4158#else
4159 bnx2x_panic();
4160#endif
4161 bnx2x_release_alr(bp);
72fd0718
VZ		 4162 return;
4163 }
4164
a2fbb9ea
ET		 4165 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4166 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4167 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4168 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4169 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4170 attn.sig[4] =
4171 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4172 else
4173 attn.sig[4] = 0;
4174
4175 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4176 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4177
4178 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4179 if (deasserted & (1 << index)) {
72fd0718 4180 group_mask = &bp->attn_group[index];
a2fbb9ea 4181
51c1a580 4182 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 4183 index,
4184 group_mask->sig[0], group_mask->sig[1],
4185 group_mask->sig[2], group_mask->sig[3],
4186 group_mask->sig[4]);
a2fbb9ea 4187
f2e0899f
DK		 4188 bnx2x_attn_int_deasserted4(bp,
4189 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4190 bnx2x_attn_int_deasserted3(bp,
72fd0718 4191 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4192 bnx2x_attn_int_deasserted1(bp,
72fd0718 4193 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4194 bnx2x_attn_int_deasserted2(bp,
72fd0718 4195 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4196 bnx2x_attn_int_deasserted0(bp,
72fd0718 4197 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4198 }
4199 }
4200
4a37fb66 4201 bnx2x_release_alr(bp);
a2fbb9ea 4202
f2e0899f
DK		 4203 if (bp->common.int_block == INT_BLOCK_HC)
4204 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4205 COMMAND_REG_ATTN_BITS_CLR);
4206 else
4207 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4208
4209 val = ~deasserted;
f2e0899f
DK		 4210 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4211 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4212 REG_WR(bp, reg_addr, val);
a2fbb9ea 4213
a2fbb9ea 4214 if (~bp->attn_state & deasserted)
3fcaf2e5 4215 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4216
4217 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4218 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4219
3fcaf2e5
EG		 4220 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4221 aeu_mask = REG_RD(bp, reg_addr);
4222
4223 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4224 aeu_mask, deasserted);
72fd0718 4225 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4226 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4227
3fcaf2e5
EG		 4228 REG_WR(bp, reg_addr, aeu_mask);
4229 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4230
4231 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4232 bp->attn_state &= ~deasserted;
4233 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4234}
4235
4236static void bnx2x_attn_int(struct bnx2x *bp)
4237{
4238 /* read local copy of bits */
68d59484
EG		 4239 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4240 attn_bits);
4241 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4242 attn_bits_ack);
a2fbb9ea
ET		 4243 u32 attn_state = bp->attn_state;
4244
4245 /* look for changed bits */
4246 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4247 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4248
4249 DP(NETIF_MSG_HW,
4250 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4251 attn_bits, attn_ack, asserted, deasserted);
4252
4253 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4254 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4255
4256 /* handle bits that were raised */
4257 if (asserted)
4258 bnx2x_attn_int_asserted(bp, asserted);
4259
4260 if (deasserted)
4261 bnx2x_attn_int_deasserted(bp, deasserted);
4262}
4263
619c5cb6
VZ		 4264void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4265 u16 index, u8 op, u8 update)
4266{
4267 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4268
4269 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4270 igu_addr);
4271}
4272
523224a3
DK		 4273static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4274{
4275 /* No memory barriers */
4276 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4277 mmiowb(); /* keep prod updates ordered */
4278}
4279
4280#ifdef BCM_CNIC
4281static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4282 union event_ring_elem *elem)
4283{
619c5cb6
VZ		 4284 u8 err = elem->message.error;
4285
523224a3 4286 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4287 (cid < bp->cnic_eth_dev.starting_cid &&
4288 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 4289 return 1;
4290
4291 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4292
619c5cb6
VZ		 4293 if (unlikely(err)) {
4294
523224a3
DK		 4295 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4296 cid);
4297 bnx2x_panic_dump(bp);
4298 }
619c5cb6 4299 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 4300 return 0;
4301}
4302#endif
4303
619c5cb6
VZ		 4304static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4305{
4306 struct bnx2x_mcast_ramrod_params rparam;
4307 int rc;
4308
4309 memset(&rparam, 0, sizeof(rparam));
4310
4311 rparam.mcast_obj = &bp->mcast_obj;
4312
4313 netif_addr_lock_bh(bp->dev);
4314
4315 /* Clear pending state for the last command */
4316 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4317
4318 /* If there are pending mcast commands - send them */
4319 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4320 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4321 if (rc < 0)
4322 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4323 rc);
4324 }
4325
4326 netif_addr_unlock_bh(bp->dev);
4327}
4328
4329static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4330 union event_ring_elem *elem)
4331{
4332 unsigned long ramrod_flags = 0;
4333 int rc = 0;
4334 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4335 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4336
4337 /* Always push next commands out, don't wait here */
4338 __set_bit(RAMROD_CONT, &ramrod_flags);
4339
4340 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4341 case BNX2X_FILTER_MAC_PENDING:
51c1a580 4342 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
619c5cb6
VZ		 4343#ifdef BCM_CNIC
4344 if (cid == BNX2X_ISCSI_ETH_CID)
4345 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4346 else
4347#endif
4348 vlan_mac_obj = &bp->fp[cid].mac_obj;
4349
4350 break;
619c5cb6 4351 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 4352 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 4353 /* This is only relevant for 57710 where multicast MACs are
4354 * configured as unicast MACs using the same ramrod.
4355 */
4356 bnx2x_handle_mcast_eqe(bp);
4357 return;
4358 default:
4359 BNX2X_ERR("Unsupported classification command: %d\n",
4360 elem->message.data.eth_event.echo);
4361 return;
4362 }
4363
4364 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4365
4366 if (rc < 0)
4367 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4368 else if (rc > 0)
4369 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4370
4371}
4372
4373#ifdef BCM_CNIC
4374static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4375#endif
4376
4377static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4378{
4379 netif_addr_lock_bh(bp->dev);
4380
4381 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4382
4383 /* Send rx_mode command again if was requested */
4384 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4385 bnx2x_set_storm_rx_mode(bp);
4386#ifdef BCM_CNIC
4387 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4388 &bp->sp_state))
4389 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4390 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4391 &bp->sp_state))
4392 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4393#endif
4394
4395 netif_addr_unlock_bh(bp->dev);
4396}
4397
4398static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4399 struct bnx2x *bp, u32 cid)
4400{
94f05b0f 4401 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
619c5cb6
VZ		 4402#ifdef BCM_CNIC
4403 if (cid == BNX2X_FCOE_ETH_CID)
4404 return &bnx2x_fcoe(bp, q_obj);
4405 else
4406#endif
6383c0b3 4407 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
619c5cb6
VZ		 4408}
4409
523224a3
DK		 4410static void bnx2x_eq_int(struct bnx2x *bp)
4411{
4412 u16 hw_cons, sw_cons, sw_prod;
4413 union event_ring_elem *elem;
4414 u32 cid;
4415 u8 opcode;
4416 int spqe_cnt = 0;
619c5cb6
VZ		 4417 struct bnx2x_queue_sp_obj *q_obj;
4418 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4419 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 4420
4421 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4422
4423 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4424 * when we get the the next-page we nned to adjust so the loop
4425 * condition below will be met. The next element is the size of a
4426 * regular element and hence incrementing by 1
4427 */
4428 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4429 hw_cons++;
4430
25985edc 4431 /* This function may never run in parallel with itself for a
523224a3
DK		 4432 * specific bp, thus there is no need in "paired" read memory
4433 * barrier here.
4434 */
4435 sw_cons = bp->eq_cons;
4436 sw_prod = bp->eq_prod;
4437
d6cae238 4438 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 4439 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 4440
4441 for (; sw_cons != hw_cons;
4442 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4443
4444
4445 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4446
4447 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4448 opcode = elem->message.opcode;
4449
4450
4451 /* handle eq element */
4452 switch (opcode) {
4453 case EVENT_RING_OPCODE_STAT_QUERY:
51c1a580
MS		 4454 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4455 "got statistics comp event %d\n",
619c5cb6 4456 bp->stats_comp++);
523224a3 4457 /* nothing to do with stats comp */
d6cae238 4458 goto next_spqe;
523224a3
DK		 4459
4460 case EVENT_RING_OPCODE_CFC_DEL:
4461 /* handle according to cid range */
4462 /*
4463 * we may want to verify here that the bp state is
4464 * HALTING
4465 */
d6cae238 4466 DP(BNX2X_MSG_SP,
523224a3
DK		 4467 "got delete ramrod for MULTI[%d]\n", cid);
4468#ifdef BCM_CNIC
4469 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4470 goto next_spqe;
4471#endif
619c5cb6
VZ		 4472 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4473
4474 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4475 break;
4476
4477
523224a3
DK		 4478
4479 goto next_spqe;
e4901dde
VZ		 4480
4481 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 4482 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6debea87
DK		 4483 if (f_obj->complete_cmd(bp, f_obj,
4484 BNX2X_F_CMD_TX_STOP))
4485 break;
e4901dde
VZ		 4486 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4487 goto next_spqe;
619c5cb6 4488
e4901dde 4489 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 4490 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6debea87
DK		 4491 if (f_obj->complete_cmd(bp, f_obj,
4492 BNX2X_F_CMD_TX_START))
4493 break;
e4901dde
VZ		 4494 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4495 goto next_spqe;
619c5cb6 4496 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 4497 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4498 "got FUNC_START ramrod\n");
619c5cb6
VZ		 4499 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4500 break;
4501
4502 goto next_spqe;
4503
4504 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 4505 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4506 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 4507 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4508 break;
4509
4510 goto next_spqe;
523224a3
DK		 4511 }
4512
4513 switch (opcode | bp->state) {
619c5cb6
VZ		 4514 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4515 BNX2X_STATE_OPEN):
4516 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 4517 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 4518 cid = elem->message.data.eth_event.echo &
4519 BNX2X_SWCID_MASK;
d6cae238 4520 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 4521 cid);
4522 rss_raw->clear_pending(rss_raw);
523224a3
DK		 4523 break;
4524
619c5cb6
VZ		 4525 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4526 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4527 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 4528 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4529 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4530 BNX2X_STATE_OPEN):
4531 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4532 BNX2X_STATE_DIAG):
4533 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4534 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4535 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 4536 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 4537 break;
4538
619c5cb6
VZ		 4539 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4540 BNX2X_STATE_OPEN):
4541 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4542 BNX2X_STATE_DIAG):
4543 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4544 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4545 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 4546 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 4547 break;
4548
619c5cb6
VZ		 4549 case (EVENT_RING_OPCODE_FILTERS_RULES |
4550 BNX2X_STATE_OPEN):
4551 case (EVENT_RING_OPCODE_FILTERS_RULES |
4552 BNX2X_STATE_DIAG):
4553 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 4554 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4555 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 4556 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 4557 break;
4558 default:
4559 /* unknown event log error and continue */
619c5cb6
VZ		 4560 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4561 elem->message.opcode, bp->state);
523224a3
DK		 4562 }
4563next_spqe:
4564 spqe_cnt++;
4565 } /* for */
4566
8fe23fbd 4567 smp_mb__before_atomic_inc();
6e30dd4e 4568 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 4569
4570 bp->eq_cons = sw_cons;
4571 bp->eq_prod = sw_prod;
4572 /* Make sure that above mem writes were issued towards the memory */
4573 smp_wmb();
4574
4575 /* update producer */
4576 bnx2x_update_eq_prod(bp, bp->eq_prod);
4577}
4578
a2fbb9ea
ET		 4579static void bnx2x_sp_task(struct work_struct *work)
4580{
1cf167f2 4581 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 4582 u16 status;
4583
a2fbb9ea 4584 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 4585/* if (status == 0) */
4586/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 4587
51c1a580 4588 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 4589
877e9aa4 4590 /* HW attentions */
523224a3 4591 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 4592 bnx2x_attn_int(bp);
523224a3 4593 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 4594 }
4595
523224a3
DK		 4596 /* SP events: STAT_QUERY and others */
4597 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 4598#ifdef BCM_CNIC
4599 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 4600
ec6ba945 4601 if ((!NO_FCOE(bp)) &&
019dbb4c
VZ		 4602 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4603 /*
4604 * Prevent local bottom-halves from running as
4605 * we are going to change the local NAPI list.
4606 */
4607 local_bh_disable();
ec6ba945 4608 napi_schedule(&bnx2x_fcoe(bp, napi));
019dbb4c
VZ		 4609 local_bh_enable();
4610 }
ec6ba945 4611#endif
523224a3
DK		 4612 /* Handle EQ completions */
4613 bnx2x_eq_int(bp);
4614
4615 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4616 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4617
4618 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 4619 }
4620
4621 if (unlikely(status))
51c1a580 4622 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
cdaa7cb8 4623 status);
a2fbb9ea 4624
523224a3
DK		 4625 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4626 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 4627}
4628
9f6c9258 4629irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 4630{
4631 struct net_device *dev = dev_instance;
4632 struct bnx2x *bp = netdev_priv(dev);
4633
523224a3
DK		 4634 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4635 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 4636
4637#ifdef BNX2X_STOP_ON_ERROR
4638 if (unlikely(bp->panic))
4639 return IRQ_HANDLED;
4640#endif
4641
993ac7b5
MC		 4642#ifdef BCM_CNIC
4643 {
4644 struct cnic_ops *c_ops;
4645
4646 rcu_read_lock();
4647 c_ops = rcu_dereference(bp->cnic_ops);
4648 if (c_ops)
4649 c_ops->cnic_handler(bp->cnic_data, NULL);
4650 rcu_read_unlock();
4651 }
4652#endif
1cf167f2 4653 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 4654
4655 return IRQ_HANDLED;
4656}
4657
4658/* end of slow path */
4659
619c5cb6
VZ		 4660
4661void bnx2x_drv_pulse(struct bnx2x *bp)
4662{
4663 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4664 bp->fw_drv_pulse_wr_seq);
4665}
4666
4667
a2fbb9ea
ET		 4668static void bnx2x_timer(unsigned long data)
4669{
4670 struct bnx2x *bp = (struct bnx2x *) data;
4671
4672 if (!netif_running(bp->dev))
4673 return;
4674
34f80b04 4675 if (!BP_NOMCP(bp)) {
f2e0899f 4676 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 4677 u32 drv_pulse;
4678 u32 mcp_pulse;
4679
4680 ++bp->fw_drv_pulse_wr_seq;
4681 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4682 /* TBD - add SYSTEM_TIME */
4683 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 4684 bnx2x_drv_pulse(bp);
a2fbb9ea 4685
f2e0899f 4686 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 4687 MCP_PULSE_SEQ_MASK);
4688 /* The delta between driver pulse and mcp response
4689 * should be 1 (before mcp response) or 0 (after mcp response)
4690 */
4691 if ((drv_pulse != mcp_pulse) &&
4692 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4693 /* someone lost a heartbeat... */
4694 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4695 drv_pulse, mcp_pulse);
4696 }
4697 }
4698
f34d28ea 4699 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 4700 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 4701
a2fbb9ea
ET		 4702 mod_timer(&bp->timer, jiffies + bp->current_interval);
4703}
4704
4705/* end of Statistics */
4706
4707/* nic init */
4708
4709/*
4710 * nic init service functions
4711 */
4712
523224a3 4713static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 4714{
523224a3
DK		 4715 u32 i;
4716 if (!(len%4) && !(addr%4))
4717 for (i = 0; i < len; i += 4)
4718 REG_WR(bp, addr + i, fill);
4719 else
4720 for (i = 0; i < len; i++)
4721 REG_WR8(bp, addr + i, fill);
34f80b04 4722
34f80b04
EG		 4723}
4724
523224a3
DK		 4725/* helper: writes FP SP data to FW - data_size in dwords */
4726static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4727 int fw_sb_id,
4728 u32 *sb_data_p,
4729 u32 data_size)
34f80b04 4730{
a2fbb9ea 4731 int index;
523224a3
DK		 4732 for (index = 0; index < data_size; index++)
4733 REG_WR(bp, BAR_CSTRORM_INTMEM +
4734 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4735 sizeof(u32)*index,
4736 *(sb_data_p + index));
4737}
a2fbb9ea 4738
523224a3
DK		 4739static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4740{
4741 u32 *sb_data_p;
4742 u32 data_size = 0;
f2e0899f 4743 struct hc_status_block_data_e2 sb_data_e2;
523224a3 4744 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 4745
523224a3 4746 /* disable the function first */
619c5cb6 4747 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4748 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4749 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 4750 sb_data_e2.common.p_func.vf_valid = false;
4751 sb_data_p = (u32 *)&sb_data_e2;
4752 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4753 } else {
4754 memset(&sb_data_e1x, 0,
4755 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4756 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 4757 sb_data_e1x.common.p_func.vf_valid = false;
4758 sb_data_p = (u32 *)&sb_data_e1x;
4759 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4760 }
523224a3 4761 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 4762
523224a3
DK		 4763 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4764 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4765 CSTORM_STATUS_BLOCK_SIZE);
4766 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4767 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4768 CSTORM_SYNC_BLOCK_SIZE);
4769}
34f80b04 4770
523224a3
DK		 4771/* helper: writes SP SB data to FW */
4772static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4773 struct hc_sp_status_block_data *sp_sb_data)
4774{
4775 int func = BP_FUNC(bp);
4776 int i;
4777 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4778 REG_WR(bp, BAR_CSTRORM_INTMEM +
4779 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4780 i*sizeof(u32),
4781 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4782}
4783
523224a3 4784static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4785{
4786 int func = BP_FUNC(bp);
523224a3
DK		 4787 struct hc_sp_status_block_data sp_sb_data;
4788 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4789
619c5cb6 4790 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 4791 sp_sb_data.p_func.vf_valid = false;
4792
4793 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4794
4795 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4796 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4797 CSTORM_SP_STATUS_BLOCK_SIZE);
4798 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4799 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4800 CSTORM_SP_SYNC_BLOCK_SIZE);
4801
4802}
4803
4804
4805static inline
4806void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4807 int igu_sb_id, int igu_seg_id)
4808{
4809 hc_sm->igu_sb_id = igu_sb_id;
4810 hc_sm->igu_seg_id = igu_seg_id;
4811 hc_sm->timer_value = 0xFF;
4812 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4813}
4814
150966ad
AE		 4815
4816/* allocates state machine ids. */
4817static inline
4818void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4819{
4820 /* zero out state machine indices */
4821 /* rx indices */
4822 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4823
4824 /* tx indices */
4825 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4826 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4827 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4828 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4829
4830 /* map indices */
4831 /* rx indices */
4832 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4833 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4834
4835 /* tx indices */
4836 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4837 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4838 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4839 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4840 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4841 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4842 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4843 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4844}
4845
8d96286a 4846static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4847 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4848{
523224a3
DK		 4849 int igu_seg_id;
4850
f2e0899f 4851 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4852 struct hc_status_block_data_e1x sb_data_e1x;
4853 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 4854 int data_size;
4855 u32 *sb_data_p;
4856
f2e0899f
DK		 4857 if (CHIP_INT_MODE_IS_BC(bp))
4858 igu_seg_id = HC_SEG_ACCESS_NORM;
4859 else
4860 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4861
4862 bnx2x_zero_fp_sb(bp, fw_sb_id);
4863
619c5cb6 4864 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4865 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4866 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 4867 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4868 sb_data_e2.common.p_func.vf_id = vfid;
4869 sb_data_e2.common.p_func.vf_valid = vf_valid;
4870 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4871 sb_data_e2.common.same_igu_sb_1b = true;
4872 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4873 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4874 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 4875 sb_data_p = (u32 *)&sb_data_e2;
4876 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 4877 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 4878 } else {
4879 memset(&sb_data_e1x, 0,
4880 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4881 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 4882 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4883 sb_data_e1x.common.p_func.vf_id = 0xff;
4884 sb_data_e1x.common.p_func.vf_valid = false;
4885 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4886 sb_data_e1x.common.same_igu_sb_1b = true;
4887 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4888 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4889 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 4890 sb_data_p = (u32 *)&sb_data_e1x;
4891 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 4892 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 4893 }
523224a3
DK		 4894
4895 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4896 igu_sb_id, igu_seg_id);
4897 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4898 igu_sb_id, igu_seg_id);
4899
51c1a580 4900 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3
DK		 4901
4902 /* write indecies to HW */
4903 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4904}
4905
619c5cb6 4906static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 4907 u16 tx_usec, u16 rx_usec)
4908{
6383c0b3 4909 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 4910 false, rx_usec);
6383c0b3
AE		 4911 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4912 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4913 tx_usec);
4914 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4915 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4916 tx_usec);
4917 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4918 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4919 tx_usec);
523224a3 4920}
f2e0899f 4921
523224a3
DK		 4922static void bnx2x_init_def_sb(struct bnx2x *bp)
4923{
4924 struct host_sp_status_block *def_sb = bp->def_status_blk;
4925 dma_addr_t mapping = bp->def_status_blk_mapping;
4926 int igu_sp_sb_index;
4927 int igu_seg_id;
34f80b04
EG		 4928 int port = BP_PORT(bp);
4929 int func = BP_FUNC(bp);
f2eaeb58 4930 int reg_offset, reg_offset_en5;
a2fbb9ea 4931 u64 section;
523224a3
DK		 4932 int index;
4933 struct hc_sp_status_block_data sp_sb_data;
4934 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4935
f2e0899f
DK		 4936 if (CHIP_INT_MODE_IS_BC(bp)) {
4937 igu_sp_sb_index = DEF_SB_IGU_ID;
4938 igu_seg_id = HC_SEG_ACCESS_DEF;
4939 } else {
4940 igu_sp_sb_index = bp->igu_dsb_id;
4941 igu_seg_id = IGU_SEG_ACCESS_DEF;
4942 }
a2fbb9ea
ET		 4943
4944 /* ATTN */
523224a3 4945 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4946 atten_status_block);
523224a3 4947 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4948
49d66772
ET		 4949 bp->attn_state = 0;
4950
a2fbb9ea
ET		 4951 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4952 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 4953 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
4954 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 4955 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4956 int sindex;
4957 /* take care of sig[0]..sig[4] */
4958 for (sindex = 0; sindex < 4; sindex++)
4959 bp->attn_group[index].sig[sindex] =
4960 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 4961
619c5cb6 4962 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4963 /*
4964 * enable5 is separate from the rest of the registers,
4965 * and therefore the address skip is 4
4966 * and not 16 between the different groups
4967 */
4968 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 4969 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 4970 else
4971 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4972 }
4973
f2e0899f
DK		 4974 if (bp->common.int_block == INT_BLOCK_HC) {
4975 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4976 HC_REG_ATTN_MSG0_ADDR_L);
4977
4978 REG_WR(bp, reg_offset, U64_LO(section));
4979 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 4980 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4981 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4982 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4983 }
a2fbb9ea 4984
523224a3
DK		 4985 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4986 sp_sb);
a2fbb9ea 4987
523224a3 4988 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4989
619c5cb6 4990 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 4991 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4992 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4993 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4994 sp_sb_data.igu_seg_id = igu_seg_id;
4995 sp_sb_data.p_func.pf_id = func;
f2e0899f 4996 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4997 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4998
523224a3 4999 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5000
523224a3 5001 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5002}
5003
9f6c9258 5004void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5005{
a2fbb9ea
ET		 5006 int i;
5007
ec6ba945 5008 for_each_eth_queue(bp, i)
523224a3 5009 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5010 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5011}
5012
a2fbb9ea
ET		 5013static void bnx2x_init_sp_ring(struct bnx2x *bp)
5014{
a2fbb9ea 5015 spin_lock_init(&bp->spq_lock);
6e30dd4e 5016 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5017
a2fbb9ea 5018 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5019 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5020 bp->spq_prod_bd = bp->spq;
5021 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5022}
5023
523224a3 5024static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5025{
5026 int i;
523224a3
DK		 5027 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5028 union event_ring_elem *elem =
5029 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5030
523224a3
DK		 5031 elem->next_page.addr.hi =
5032 cpu_to_le32(U64_HI(bp->eq_mapping +
5033 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5034 elem->next_page.addr.lo =
5035 cpu_to_le32(U64_LO(bp->eq_mapping +
5036 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5037 }
523224a3
DK		 5038 bp->eq_cons = 0;
5039 bp->eq_prod = NUM_EQ_DESC;
5040 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 5041 /* we want a warning message before it gets rought... */
5042 atomic_set(&bp->eq_spq_left,
5043 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5044}
5045
619c5cb6
VZ		 5046
5047/* called with netif_addr_lock_bh() */
5048void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5049 unsigned long rx_mode_flags,
5050 unsigned long rx_accept_flags,
5051 unsigned long tx_accept_flags,
5052 unsigned long ramrod_flags)
ab532cf3 5053{
619c5cb6
VZ		 5054 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5055 int rc;
5056
5057 memset(&ramrod_param, 0, sizeof(ramrod_param));
5058
5059 /* Prepare ramrod parameters */
5060 ramrod_param.cid = 0;
5061 ramrod_param.cl_id = cl_id;
5062 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5063 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5064
619c5cb6
VZ		 5065 ramrod_param.pstate = &bp->sp_state;
5066 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5067
619c5cb6
VZ		 5068 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5069 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5070
5071 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5072
5073 ramrod_param.ramrod_flags = ramrod_flags;
5074 ramrod_param.rx_mode_flags = rx_mode_flags;
5075
5076 ramrod_param.rx_accept_flags = rx_accept_flags;
5077 ramrod_param.tx_accept_flags = tx_accept_flags;
5078
5079 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5080 if (rc < 0) {
5081 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5082 return;
5083 }
a2fbb9ea
ET		 5084}
5085
619c5cb6
VZ		 5086/* called with netif_addr_lock_bh() */
5087void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 5088{
619c5cb6
VZ		 5089 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5090 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 5091
619c5cb6
VZ		 5092#ifdef BCM_CNIC
5093 if (!NO_FCOE(bp))
5094
5095 /* Configure rx_mode of FCoE Queue */
5096 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5097#endif
5098
5099 switch (bp->rx_mode) {
5100 case BNX2X_RX_MODE_NONE:
5101 /*
5102 * 'drop all' supersedes any accept flags that may have been
5103 * passed to the function.
5104 */
5105 break;
5106 case BNX2X_RX_MODE_NORMAL:
5107 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5108 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5109 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5110
5111 /* internal switching mode */
5112 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5113 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5114 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5115
5116 break;
5117 case BNX2X_RX_MODE_ALLMULTI:
5118 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5119 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5120 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5121
5122 /* internal switching mode */
5123 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5124 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5125 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5126
5127 break;
5128 case BNX2X_RX_MODE_PROMISC:
5129 /* According to deffinition of SI mode, iface in promisc mode
5130 * should receive matched and unmatched (in resolution of port)
5131 * unicast packets.
5132 */
5133 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5134 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5135 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5136 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5137
5138 /* internal switching mode */
5139 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5140 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5141
5142 if (IS_MF_SI(bp))
5143 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5144 else
5145 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5146
5147 break;
5148 default:
5149 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5150 return;
5151 }
de832a55 5152
619c5cb6
VZ		 5153 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5154 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5155 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 5156 }
5157
619c5cb6
VZ		 5158 __set_bit(RAMROD_RX, &ramrod_flags);
5159 __set_bit(RAMROD_TX, &ramrod_flags);
5160
5161 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5162 tx_accept_flags, ramrod_flags);
5163}
5164
5165static void bnx2x_init_internal_common(struct bnx2x *bp)
5166{
5167 int i;
5168
0793f83f
DK		 5169 if (IS_MF_SI(bp))
5170 /*
5171 * In switch independent mode, the TSTORM needs to accept
5172 * packets that failed classification, since approximate match
5173 * mac addresses aren't written to NIG LLH
5174 */
5175 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5176 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 5177 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5178 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5179 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 5180
523224a3
DK		 5181 /* Zero this manually as its initialization is
5182 currently missing in the initTool */
5183 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 5184 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 5185 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 5186 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5187 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5188 CHIP_INT_MODE_IS_BC(bp) ?
5189 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5190 }
523224a3 5191}
8a1c38d1 5192
471de716
EG		 5193static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5194{
5195 switch (load_code) {
5196 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5197 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 5198 bnx2x_init_internal_common(bp);
5199 /* no break */
5200
5201 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 5202 /* nothing to do */
471de716
EG		 5203 /* no break */
5204
5205 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 5206 /* internal memory per function is
5207 initialized inside bnx2x_pf_init */
471de716
EG		 5208 break;
5209
5210 default:
5211 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5212 break;
5213 }
5214}
5215
619c5cb6 5216static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 5217{
6383c0b3 5218 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
619c5cb6 5219}
523224a3 5220
619c5cb6
VZ		 5221static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5222{
6383c0b3 5223 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
619c5cb6
VZ		 5224}
5225
5226static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5227{
5228 if (CHIP_IS_E1x(fp->bp))
5229 return BP_L_ID(fp->bp) + fp->index;
5230 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5231 return bnx2x_fp_igu_sb_id(fp);
5232}
5233
6383c0b3 5234static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 5235{
5236 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 5237 u8 cos;
619c5cb6 5238 unsigned long q_type = 0;
6383c0b3 5239 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 5240 fp->rx_queue = fp_idx;
b3b83c3f 5241 fp->cid = fp_idx;
619c5cb6
VZ		 5242 fp->cl_id = bnx2x_fp_cl_id(fp);
5243 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5244 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 5245 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 5246 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5247
523224a3 5248 /* init shortcut */
619c5cb6 5249 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 5250
523224a3
DK		 5251 /* Setup SB indicies */
5252 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 5253
619c5cb6
VZ		 5254 /* Configure Queue State object */
5255 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5256 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 5257
5258 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5259
5260 /* init tx data */
5261 for_each_cos_in_tx_queue(fp, cos) {
5262 bnx2x_init_txdata(bp, &fp->txdata[cos],
5263 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5264 FP_COS_TO_TXQ(fp, cos),
5265 BNX2X_TX_SB_INDEX_BASE + cos);
5266 cids[cos] = fp->txdata[cos].cid;
5267 }
5268
5269 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5270 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5271 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 5272
5273 /**
5274 * Configure classification DBs: Always enable Tx switching
5275 */
5276 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5277
51c1a580 5278 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
619c5cb6 5279 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
523224a3
DK		 5280 fp->igu_sb_id);
5281 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5282 fp->fw_sb_id, fp->igu_sb_id);
5283
5284 bnx2x_update_fpsb_idx(fp);
5285}
5286
9f6c9258 5287void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 5288{
5289 int i;
5290
ec6ba945 5291 for_each_eth_queue(bp, i)
6383c0b3 5292 bnx2x_init_eth_fp(bp, i);
37b091ba 5293#ifdef BCM_CNIC
ec6ba945
VZ		 5294 if (!NO_FCOE(bp))
5295 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 5296
5297 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5298 BNX2X_VF_ID_INVALID, false,
619c5cb6 5299 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 5300
37b091ba 5301#endif
a2fbb9ea 5302
020c7e3f
YR		 5303 /* Initialize MOD_ABS interrupts */
5304 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5305 bp->common.shmem_base, bp->common.shmem2_base,
5306 BP_PORT(bp));
16119785
EG		 5307 /* ensure status block indices were read */
5308 rmb();
5309
523224a3 5310 bnx2x_init_def_sb(bp);
5c862848 5311 bnx2x_update_dsb_idx(bp);
a2fbb9ea 5312 bnx2x_init_rx_rings(bp);
523224a3 5313 bnx2x_init_tx_rings(bp);
a2fbb9ea 5314 bnx2x_init_sp_ring(bp);
523224a3 5315 bnx2x_init_eq_ring(bp);
471de716 5316 bnx2x_init_internal(bp, load_code);
523224a3 5317 bnx2x_pf_init(bp);
0ef00459
EG		 5318 bnx2x_stats_init(bp);
5319
0ef00459
EG		 5320 /* flush all before enabling interrupts */
5321 mb();
5322 mmiowb();
5323
615f8fd9 5324 bnx2x_int_enable(bp);
eb8da205
EG		 5325
5326 /* Check for SPIO5 */
5327 bnx2x_attn_int_deasserted0(bp,
5328 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5329 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 5330}
5331
5332/* end of nic init */
5333
5334/*
5335 * gzip service functions
5336 */
5337
5338static int bnx2x_gunzip_init(struct bnx2x *bp)
5339{
1a983142
FT		 5340 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5341 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 5342 if (bp->gunzip_buf == NULL)
5343 goto gunzip_nomem1;
5344
5345 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5346 if (bp->strm == NULL)
5347 goto gunzip_nomem2;
5348
7ab24bfd 5349 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 5350 if (bp->strm->workspace == NULL)
5351 goto gunzip_nomem3;
5352
5353 return 0;
5354
5355gunzip_nomem3:
5356 kfree(bp->strm);
5357 bp->strm = NULL;
5358
5359gunzip_nomem2:
1a983142
FT		 5360 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5361 bp->gunzip_mapping);
a2fbb9ea
ET		 5362 bp->gunzip_buf = NULL;
5363
5364gunzip_nomem1:
51c1a580 5365 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 5366 return -ENOMEM;
5367}
5368
5369static void bnx2x_gunzip_end(struct bnx2x *bp)
5370{
b3b83c3f 5371 if (bp->strm) {
7ab24bfd 5372 vfree(bp->strm->workspace);
b3b83c3f
DK		 5373 kfree(bp->strm);
5374 bp->strm = NULL;
5375 }
a2fbb9ea
ET		 5376
5377 if (bp->gunzip_buf) {
1a983142
FT		 5378 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5379 bp->gunzip_mapping);
a2fbb9ea
ET		 5380 bp->gunzip_buf = NULL;
5381 }
5382}
5383
94a78b79 5384static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 5385{
5386 int n, rc;
5387
5388 /* check gzip header */
94a78b79
VZ		 5389 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5390 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 5391 return -EINVAL;
94a78b79 5392 }
a2fbb9ea
ET		 5393
5394 n = 10;
5395
34f80b04 5396#define FNAME 0x8
a2fbb9ea
ET		 5397
5398 if (zbuf[3] & FNAME)
5399 while ((zbuf[n++] != 0) && (n < len));
5400
94a78b79 5401 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 5402 bp->strm->avail_in = len - n;
5403 bp->strm->next_out = bp->gunzip_buf;
5404 bp->strm->avail_out = FW_BUF_SIZE;
5405
5406 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5407 if (rc != Z_OK)
5408 return rc;
5409
5410 rc = zlib_inflate(bp->strm, Z_FINISH);
5411 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 5412 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5413 bp->strm->msg);
a2fbb9ea
ET		 5414
5415 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5416 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 5417 netdev_err(bp->dev,
5418 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 5419 bp->gunzip_outlen);
a2fbb9ea
ET		 5420 bp->gunzip_outlen >>= 2;
5421
5422 zlib_inflateEnd(bp->strm);
5423
5424 if (rc == Z_STREAM_END)
5425 return 0;
5426
5427 return rc;
5428}
5429
5430/* nic load/unload */
5431
5432/*
34f80b04 5433 * General service functions
a2fbb9ea
ET		 5434 */
5435
5436/* send a NIG loopback debug packet */
5437static void bnx2x_lb_pckt(struct bnx2x *bp)
5438{
a2fbb9ea 5439 u32 wb_write[3];
a2fbb9ea
ET		 5440
5441 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 5442 wb_write[0] = 0x55555555;
5443 wb_write[1] = 0x55555555;
34f80b04 5444 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 5445 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5446
5447 /* NON-IP protocol */
a2fbb9ea
ET		 5448 wb_write[0] = 0x09000000;
5449 wb_write[1] = 0x55555555;
34f80b04 5450 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 5451 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5452}
5453
5454/* some of the internal memories
5455 * are not directly readable from the driver
5456 * to test them we send debug packets
5457 */
5458static int bnx2x_int_mem_test(struct bnx2x *bp)
5459{
5460 int factor;
5461 int count, i;
5462 u32 val = 0;
5463
ad8d3948 5464 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 5465 factor = 120;
ad8d3948
EG		 5466 else if (CHIP_REV_IS_EMUL(bp))
5467 factor = 200;
5468 else
a2fbb9ea 5469 factor = 1;
a2fbb9ea 5470
a2fbb9ea
ET		 5471 /* Disable inputs of parser neighbor blocks */
5472 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5473 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5474 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5475 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5476
5477 /* Write 0 to parser credits for CFC search request */
5478 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5479
5480 /* send Ethernet packet */
5481 bnx2x_lb_pckt(bp);
5482
5483 /* TODO do i reset NIG statistic? */
5484 /* Wait until NIG register shows 1 packet of size 0x10 */
5485 count = 1000 * factor;
5486 while (count) {
34f80b04 5487
a2fbb9ea
ET		 5488 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5489 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5490 if (val == 0x10)
5491 break;
5492
5493 msleep(10);
5494 count--;
5495 }
5496 if (val != 0x10) {
5497 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5498 return -1;
5499 }
5500
5501 /* Wait until PRS register shows 1 packet */
5502 count = 1000 * factor;
5503 while (count) {
5504 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 5505 if (val == 1)
5506 break;
5507
5508 msleep(10);
5509 count--;
5510 }
5511 if (val != 0x1) {
5512 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5513 return -2;
5514 }
5515
5516 /* Reset and init BRB, PRS */
34f80b04 5517 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 5518 msleep(50);
34f80b04 5519 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 5520 msleep(50);
619c5cb6
VZ		 5521 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5522 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 5523
5524 DP(NETIF_MSG_HW, "part2\n");
5525
5526 /* Disable inputs of parser neighbor blocks */
5527 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5528 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5529 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5530 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5531
5532 /* Write 0 to parser credits for CFC search request */
5533 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5534
5535 /* send 10 Ethernet packets */
5536 for (i = 0; i < 10; i++)
5537 bnx2x_lb_pckt(bp);
5538
5539 /* Wait until NIG register shows 10 + 1
5540 packets of size 11*0x10 = 0xb0 */
5541 count = 1000 * factor;
5542 while (count) {
34f80b04 5543
a2fbb9ea
ET		 5544 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5545 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5546 if (val == 0xb0)
5547 break;
5548
5549 msleep(10);
5550 count--;
5551 }
5552 if (val != 0xb0) {
5553 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5554 return -3;
5555 }
5556
5557 /* Wait until PRS register shows 2 packets */
5558 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5559 if (val != 2)
5560 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5561
5562 /* Write 1 to parser credits for CFC search request */
5563 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5564
5565 /* Wait until PRS register shows 3 packets */
5566 msleep(10 * factor);
5567 /* Wait until NIG register shows 1 packet of size 0x10 */
5568 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5569 if (val != 3)
5570 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5571
5572 /* clear NIG EOP FIFO */
5573 for (i = 0; i < 11; i++)
5574 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5575 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5576 if (val != 1) {
5577 BNX2X_ERR("clear of NIG failed\n");
5578 return -4;
5579 }
5580
5581 /* Reset and init BRB, PRS, NIG */
5582 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5583 msleep(50);
5584 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5585 msleep(50);
619c5cb6
VZ		 5586 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5587 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
37b091ba 5588#ifndef BCM_CNIC
a2fbb9ea
ET		 5589 /* set NIC mode */
5590 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5591#endif
5592
5593 /* Enable inputs of parser neighbor blocks */
5594 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5595 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5596 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 5597 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 5598
5599 DP(NETIF_MSG_HW, "done\n");
5600
5601 return 0; /* OK */
5602}
5603
4a33bc03 5604static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 5605{
5606 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 5607 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5608 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5609 else
5610 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 5611 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5612 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 5613 /*
5614 * mask read length error interrupts in brb for parser
5615 * (parsing unit and 'checksum and crc' unit)
5616 * these errors are legal (PU reads fixed length and CAC can cause
5617 * read length error on truncated packets)
5618 */
5619 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 5620 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5621 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5622 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5623 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5624 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 5625/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5626/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5627 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5628 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5629 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 5630/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5631/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5632 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5633 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5634 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5635 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 5636/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5637/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 5638
34f80b04
EG		 5639 if (CHIP_REV_IS_FPGA(bp))
5640 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
619c5cb6 5641 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5642 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5643 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5644 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5645 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5646 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5647 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 5648 else
5649 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 5650 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5651 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5652 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 5653/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 5654
5655 if (!CHIP_IS_E1x(bp))
5656 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5657 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5658
a2fbb9ea
ET		 5659 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5660 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 5661/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 5662 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 5663}
5664
81f75bbf
EG		 5665static void bnx2x_reset_common(struct bnx2x *bp)
5666{
619c5cb6
VZ		 5667 u32 val = 0x1400;
5668
81f75bbf
EG		 5669 /* reset_common */
5670 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5671 0xd3ffff7f);
619c5cb6
VZ		 5672
5673 if (CHIP_IS_E3(bp)) {
5674 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5675 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5676 }
5677
5678 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5679}
5680
5681static void bnx2x_setup_dmae(struct bnx2x *bp)
5682{
5683 bp->dmae_ready = 0;
5684 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 5685}
5686
573f2035
EG		 5687static void bnx2x_init_pxp(struct bnx2x *bp)
5688{
5689 u16 devctl;
5690 int r_order, w_order;
5691
5692 pci_read_config_word(bp->pdev,
b6c2f86e 5693 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 5694 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5695 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5696 if (bp->mrrs == -1)
5697 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5698 else {
5699 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5700 r_order = bp->mrrs;
5701 }
5702
5703 bnx2x_init_pxp_arb(bp, r_order, w_order);
5704}
fd4ef40d
EG		 5705
5706static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5707{
2145a920 5708 int is_required;
fd4ef40d 5709 u32 val;
2145a920 5710 int port;
fd4ef40d 5711
2145a920
VZ		 5712 if (BP_NOMCP(bp))
5713 return;
5714
5715 is_required = 0;
fd4ef40d
EG		 5716 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5717 SHARED_HW_CFG_FAN_FAILURE_MASK;
5718
5719 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5720 is_required = 1;
5721
5722 /*
5723 * The fan failure mechanism is usually related to the PHY type since
5724 * the power consumption of the board is affected by the PHY. Currently,
5725 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5726 */
5727 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5728 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 5729 is_required |=
d90d96ba
YR		 5730 bnx2x_fan_failure_det_req(
5731 bp,
5732 bp->common.shmem_base,
a22f0788 5733 bp->common.shmem2_base,
d90d96ba 5734 port);
fd4ef40d
EG		 5735 }
5736
5737 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5738
5739 if (is_required == 0)
5740 return;
5741
5742 /* Fan failure is indicated by SPIO 5 */
5743 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5744 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5745
5746 /* set to active low mode */
5747 val = REG_RD(bp, MISC_REG_SPIO_INT);
5748 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 5749 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 5750 REG_WR(bp, MISC_REG_SPIO_INT, val);
5751
5752 /* enable interrupt to signal the IGU */
5753 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5754 val |= (1 << MISC_REGISTERS_SPIO_5);
5755 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5756}
5757
f2e0899f
DK		 5758static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5759{
5760 u32 offset = 0;
5761
5762 if (CHIP_IS_E1(bp))
5763 return;
5764 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5765 return;
5766
5767 switch (BP_ABS_FUNC(bp)) {
5768 case 0:
5769 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5770 break;
5771 case 1:
5772 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5773 break;
5774 case 2:
5775 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5776 break;
5777 case 3:
5778 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5779 break;
5780 case 4:
5781 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5782 break;
5783 case 5:
5784 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5785 break;
5786 case 6:
5787 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5788 break;
5789 case 7:
5790 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5791 break;
5792 default:
5793 return;
5794 }
5795
5796 REG_WR(bp, offset, pretend_func_num);
5797 REG_RD(bp, offset);
5798 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5799}
5800
c9ee9206 5801void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 5802{
5803 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5804 val &= ~IGU_PF_CONF_FUNC_EN;
5805
5806 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5807 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5808 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5809}
5810
619c5cb6
VZ		 5811static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5812{
5813 u32 shmem_base[2], shmem2_base[2];
5814 shmem_base[0] = bp->common.shmem_base;
5815 shmem2_base[0] = bp->common.shmem2_base;
5816 if (!CHIP_IS_E1x(bp)) {
5817 shmem_base[1] =
5818 SHMEM2_RD(bp, other_shmem_base_addr);
5819 shmem2_base[1] =
5820 SHMEM2_RD(bp, other_shmem2_base_addr);
5821 }
5822 bnx2x_acquire_phy_lock(bp);
5823 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5824 bp->common.chip_id);
5825 bnx2x_release_phy_lock(bp);
5826}
5827
5828/**
5829 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5830 *
5831 * @bp: driver handle
5832 */
5833static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 5834{
619c5cb6 5835 u32 val;
a2fbb9ea 5836
51c1a580 5837 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 5838
2031bd3a
DK		 5839 /*
5840 * take the UNDI lock to protect undi_unload flow from accessing
5841 * registers while we're resetting the chip
5842 */
7a06a122 5843 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 5844
81f75bbf 5845 bnx2x_reset_common(bp);
34f80b04 5846 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 5847
619c5cb6
VZ		 5848 val = 0xfffc;
5849 if (CHIP_IS_E3(bp)) {
5850 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5851 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5852 }
5853 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5854
7a06a122 5855 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 5856
619c5cb6 5857 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 5858
619c5cb6
VZ		 5859 if (!CHIP_IS_E1x(bp)) {
5860 u8 abs_func_id;
f2e0899f
DK		 5861
5862 /**
5863 * 4-port mode or 2-port mode we need to turn of master-enable
5864 * for everyone, after that, turn it back on for self.
5865 * so, we disregard multi-function or not, and always disable
5866 * for all functions on the given path, this means 0,2,4,6 for
5867 * path 0 and 1,3,5,7 for path 1
5868 */
619c5cb6
VZ		 5869 for (abs_func_id = BP_PATH(bp);
5870 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5871 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 5872 REG_WR(bp,
5873 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5874 1);
5875 continue;
5876 }
5877
619c5cb6 5878 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 5879 /* clear pf enable */
5880 bnx2x_pf_disable(bp);
5881 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5882 }
5883 }
a2fbb9ea 5884
619c5cb6 5885 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 5886 if (CHIP_IS_E1(bp)) {
5887 /* enable HW interrupt from PXP on USDM overflow
5888 bit 16 on INT_MASK_0 */
5889 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5890 }
a2fbb9ea 5891
619c5cb6 5892 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 5893 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 5894
5895#ifdef __BIG_ENDIAN
34f80b04
EG		 5896 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5897 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5898 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5899 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5900 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5901 /* make sure this value is 0 */
5902 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5903
5904/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5905 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5906 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5907 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5908 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5909#endif
5910
523224a3
DK		 5911 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5912
34f80b04
EG		 5913 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5914 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5915
34f80b04
EG		 5916 /* let the HW do it's magic ... */
5917 msleep(100);
5918 /* finish PXP init */
5919 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5920 if (val != 1) {
5921 BNX2X_ERR("PXP2 CFG failed\n");
5922 return -EBUSY;
5923 }
5924 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5925 if (val != 1) {
5926 BNX2X_ERR("PXP2 RD_INIT failed\n");
5927 return -EBUSY;
5928 }
a2fbb9ea 5929
f2e0899f
DK		 5930 /* Timers bug workaround E2 only. We need to set the entire ILT to
5931 * have entries with value "0" and valid bit on.
5932 * This needs to be done by the first PF that is loaded in a path
5933 * (i.e. common phase)
5934 */
619c5cb6
VZ		 5935 if (!CHIP_IS_E1x(bp)) {
5936/* In E2 there is a bug in the timers block that can cause function 6 / 7
5937 * (i.e. vnic3) to start even if it is marked as "scan-off".
5938 * This occurs when a different function (func2,3) is being marked
5939 * as "scan-off". Real-life scenario for example: if a driver is being
5940 * load-unloaded while func6,7 are down. This will cause the timer to access
5941 * the ilt, translate to a logical address and send a request to read/write.
5942 * Since the ilt for the function that is down is not valid, this will cause
5943 * a translation error which is unrecoverable.
5944 * The Workaround is intended to make sure that when this happens nothing fatal
5945 * will occur. The workaround:
5946 * 1. First PF driver which loads on a path will:
5947 * a. After taking the chip out of reset, by using pretend,
5948 * it will write "0" to the following registers of
5949 * the other vnics.
5950 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5951 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5952 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5953 * And for itself it will write '1' to
5954 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5955 * dmae-operations (writing to pram for example.)
5956 * note: can be done for only function 6,7 but cleaner this
5957 * way.
5958 * b. Write zero+valid to the entire ILT.
5959 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5960 * VNIC3 (of that port). The range allocated will be the
5961 * entire ILT. This is needed to prevent ILT range error.
5962 * 2. Any PF driver load flow:
5963 * a. ILT update with the physical addresses of the allocated
5964 * logical pages.
5965 * b. Wait 20msec. - note that this timeout is needed to make
5966 * sure there are no requests in one of the PXP internal
5967 * queues with "old" ILT addresses.
5968 * c. PF enable in the PGLC.
5969 * d. Clear the was_error of the PF in the PGLC. (could have
5970 * occured while driver was down)
5971 * e. PF enable in the CFC (WEAK + STRONG)
5972 * f. Timers scan enable
5973 * 3. PF driver unload flow:
5974 * a. Clear the Timers scan_en.
5975 * b. Polling for scan_on=0 for that PF.
5976 * c. Clear the PF enable bit in the PXP.
5977 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5978 * e. Write zero+valid to all ILT entries (The valid bit must
5979 * stay set)
5980 * f. If this is VNIC 3 of a port then also init
5981 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5982 * to the last enrty in the ILT.
5983 *
5984 * Notes:
5985 * Currently the PF error in the PGLC is non recoverable.
5986 * In the future the there will be a recovery routine for this error.
5987 * Currently attention is masked.
5988 * Having an MCP lock on the load/unload process does not guarantee that
5989 * there is no Timer disable during Func6/7 enable. This is because the
5990 * Timers scan is currently being cleared by the MCP on FLR.
5991 * Step 2.d can be done only for PF6/7 and the driver can also check if
5992 * there is error before clearing it. But the flow above is simpler and
5993 * more general.
5994 * All ILT entries are written by zero+valid and not just PF6/7
5995 * ILT entries since in the future the ILT entries allocation for
5996 * PF-s might be dynamic.
5997 */
f2e0899f
DK		 5998 struct ilt_client_info ilt_cli;
5999 struct bnx2x_ilt ilt;
6000 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6001 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6002
b595076a 6003 /* initialize dummy TM client */
f2e0899f
DK		 6004 ilt_cli.start = 0;
6005 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6006 ilt_cli.client_num = ILT_CLIENT_TM;
6007
6008 /* Step 1: set zeroes to all ilt page entries with valid bit on
6009 * Step 2: set the timers first/last ilt entry to point
6010 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 6011 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 6012 *
6013 * both steps performed by call to bnx2x_ilt_client_init_op()
6014 * with dummy TM client
6015 *
6016 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6017 * and his brother are split registers
6018 */
6019 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6020 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6021 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6022
6023 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6024 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6025 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6026 }
6027
6028
34f80b04
EG		 6029 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6030 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 6031
619c5cb6 6032 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6033 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6034 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 6035 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 6036
619c5cb6 6037 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 6038
6039 /* let the HW do it's magic ... */
6040 do {
6041 msleep(200);
6042 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6043 } while (factor-- && (val != 1));
6044
6045 if (val != 1) {
6046 BNX2X_ERR("ATC_INIT failed\n");
6047 return -EBUSY;
6048 }
6049 }
6050
619c5cb6 6051 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 6052
34f80b04
EG		 6053 /* clean the DMAE memory */
6054 bp->dmae_ready = 1;
619c5cb6
VZ		 6055 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6056
6057 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6058
6059 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6060
6061 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6062
619c5cb6 6063 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6064
34f80b04
EG		 6065 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6066 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6067 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6068 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6069
619c5cb6 6070 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6071
f85582f8 6072
523224a3
DK		 6073 /* QM queues pointers table */
6074 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6075
34f80b04
EG		 6076 /* soft reset pulse */
6077 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6078 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 6079
37b091ba 6080#ifdef BCM_CNIC
619c5cb6 6081 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 6082#endif
a2fbb9ea 6083
619c5cb6 6084 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 6085 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 6086 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 6087 /* enable hw interrupt from doorbell Q */
6088 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 6089
619c5cb6 6090 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 6091
619c5cb6 6092 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 6093 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 6094
f2e0899f 6095 if (!CHIP_IS_E1(bp))
619c5cb6 6096 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 6097
619c5cb6
VZ		 6098 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6099 /* Bit-map indicating which L2 hdrs may appear
6100 * after the basic Ethernet header
6101 */
6102 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6103 bp->path_has_ovlan ? 7 : 6);
a2fbb9ea 6104
619c5cb6
VZ		 6105 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6106 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6107 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6108 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 6109
619c5cb6
VZ		 6110 if (!CHIP_IS_E1x(bp)) {
6111 /* reset VFC memories */
6112 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6113 VFC_MEMORIES_RST_REG_CAM_RST |
6114 VFC_MEMORIES_RST_REG_RAM_RST);
6115 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6116 VFC_MEMORIES_RST_REG_CAM_RST |
6117 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 6118
619c5cb6
VZ		 6119 msleep(20);
6120 }
a2fbb9ea 6121
619c5cb6
VZ		 6122 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6123 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6124 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6125 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 6126
34f80b04
EG		 6127 /* sync semi rtc */
6128 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6129 0x80000000);
6130 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6131 0x80000000);
a2fbb9ea 6132
619c5cb6
VZ		 6133 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6134 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6135 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 6136
619c5cb6
VZ		 6137 if (!CHIP_IS_E1x(bp))
6138 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6139 bp->path_has_ovlan ? 7 : 6);
f2e0899f 6140
34f80b04 6141 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 6142
619c5cb6
VZ		 6143 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6144
37b091ba
MC		 6145#ifdef BCM_CNIC
6146 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6147 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6148 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6149 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6150 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6151 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6152 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6153 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6154 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6155 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6156#endif
34f80b04 6157 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 6158
34f80b04
EG		 6159 if (sizeof(union cdu_context) != 1024)
6160 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 6161 dev_alert(&bp->pdev->dev,
6162 "please adjust the size of cdu_context(%ld)\n",
6163 (long)sizeof(union cdu_context));
a2fbb9ea 6164
619c5cb6 6165 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 6166 val = (4 << 24) + (0 << 12) + 1024;
6167 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 6168
619c5cb6 6169 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 6170 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 6171 /* enable context validation interrupt from CFC */
6172 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6173
6174 /* set the thresholds to prevent CFC/CDU race */
6175 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 6176
619c5cb6 6177 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 6178
619c5cb6 6179 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 6180 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6181
619c5cb6
VZ		 6182 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6183 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 6184
34f80b04
EG		 6185 /* Reset PCIE errors for debug */
6186 REG_WR(bp, 0x2814, 0xffffffff);
6187 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 6188
619c5cb6 6189 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6190 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6191 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6192 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6193 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6194 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6195 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6196 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6197 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6198 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6199 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6200 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6201 }
6202
619c5cb6 6203 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 6204 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 6205 /* in E3 this done in per-port section */
6206 if (!CHIP_IS_E3(bp))
6207 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 6208 }
619c5cb6
VZ		 6209 if (CHIP_IS_E1H(bp))
6210 /* not applicable for E2 (and above ...) */
6211 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 6212
6213 if (CHIP_REV_IS_SLOW(bp))
6214 msleep(200);
6215
6216 /* finish CFC init */
6217 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6218 if (val != 1) {
6219 BNX2X_ERR("CFC LL_INIT failed\n");
6220 return -EBUSY;
6221 }
6222 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6223 if (val != 1) {
6224 BNX2X_ERR("CFC AC_INIT failed\n");
6225 return -EBUSY;
6226 }
6227 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6228 if (val != 1) {
6229 BNX2X_ERR("CFC CAM_INIT failed\n");
6230 return -EBUSY;
6231 }
6232 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 6233
f2e0899f
DK		 6234 if (CHIP_IS_E1(bp)) {
6235 /* read NIG statistic
6236 to see if this is our first up since powerup */
6237 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6238 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 6239
f2e0899f
DK		 6240 /* do internal memory self test */
6241 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6242 BNX2X_ERR("internal mem self test failed\n");
6243 return -EBUSY;
6244 }
34f80b04
EG		 6245 }
6246
fd4ef40d
EG		 6247 bnx2x_setup_fan_failure_detection(bp);
6248
34f80b04
EG		 6249 /* clear PXP2 attentions */
6250 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 6251
4a33bc03 6252 bnx2x_enable_blocks_attention(bp);
c9ee9206 6253 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 6254
6bbca910 6255 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 6256 if (CHIP_IS_E1x(bp))
6257 bnx2x__common_init_phy(bp);
6bbca910
YR		 6258 } else
6259 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6260
34f80b04
EG		 6261 return 0;
6262}
a2fbb9ea 6263
619c5cb6
VZ		 6264/**
6265 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6266 *
6267 * @bp: driver handle
6268 */
6269static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6270{
6271 int rc = bnx2x_init_hw_common(bp);
6272
6273 if (rc)
6274 return rc;
6275
6276 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6277 if (!BP_NOMCP(bp))
6278 bnx2x__common_init_phy(bp);
6279
6280 return 0;
6281}
6282
523224a3 6283static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 6284{
6285 int port = BP_PORT(bp);
619c5cb6 6286 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 6287 u32 low, high;
34f80b04 6288 u32 val;
a2fbb9ea 6289
619c5cb6
VZ		 6290 bnx2x__link_reset(bp);
6291
51c1a580 6292 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 6293
6294 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 6295
619c5cb6
VZ		 6296 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6297 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6298 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 6299
f2e0899f
DK		 6300 /* Timers bug workaround: disables the pf_master bit in pglue at
6301 * common phase, we need to enable it here before any dmae access are
6302 * attempted. Therefore we manually added the enable-master to the
6303 * port phase (it also happens in the function phase)
6304 */
619c5cb6 6305 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6306 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6307
619c5cb6
VZ		 6308 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6309 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6310 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6311 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6312
6313 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6314 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6315 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6316 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 6317
523224a3
DK		 6318 /* QM cid (connection) count */
6319 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 6320
523224a3 6321#ifdef BCM_CNIC
619c5cb6 6322 bnx2x_init_block(bp, BLOCK_TM, init_phase);
37b091ba
MC		 6323 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6324 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 6325#endif
cdaa7cb8 6326
619c5cb6 6327 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f
DK		 6328
6329 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 6330 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6331
6332 if (IS_MF(bp))
6333 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6334 else if (bp->dev->mtu > 4096) {
6335 if (bp->flags & ONE_PORT_FLAG)
6336 low = 160;
6337 else {
6338 val = bp->dev->mtu;
6339 /* (24*1024 + val*4)/256 */
6340 low = 96 + (val/64) +
6341 ((val % 64) ? 1 : 0);
6342 }
6343 } else
6344 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6345 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 6346 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6347 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 6348 }
1c06328c 6349
619c5cb6
VZ		 6350 if (CHIP_MODE_IS_4_PORT(bp))
6351 REG_WR(bp, (BP_PORT(bp) ?
6352 BRB1_REG_MAC_GUARANTIED_1 :
6353 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 6354
ca00392c 6355
619c5cb6
VZ		 6356 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6357 if (CHIP_IS_E3B0(bp))
6358 /* Ovlan exists only if we are in multi-function +
6359 * switch-dependent mode, in switch-independent there
6360 * is no ovlan headers
6361 */
6362 REG_WR(bp, BP_PORT(bp) ?
6363 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6364 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6365 (bp->path_has_ovlan ? 7 : 6));
356e2385 6366
619c5cb6
VZ		 6367 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6368 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6369 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6370 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 6371
619c5cb6
VZ		 6372 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6373 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6374 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6375 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 6376
619c5cb6
VZ		 6377 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6378 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 6379
619c5cb6
VZ		 6380 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6381
6382 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6383 /* configure PBF to work without PAUSE mtu 9000 */
6384 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 6385
f2e0899f
DK		 6386 /* update threshold */
6387 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6388 /* update init credit */
6389 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 6390
f2e0899f
DK		 6391 /* probe changes */
6392 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6393 udelay(50);
6394 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6395 }
a2fbb9ea 6396
37b091ba 6397#ifdef BCM_CNIC
619c5cb6 6398 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
a2fbb9ea 6399#endif
619c5cb6
VZ		 6400 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6401 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 6402
6403 if (CHIP_IS_E1(bp)) {
6404 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6405 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6406 }
619c5cb6 6407 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 6408
619c5cb6 6409 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6410
619c5cb6 6411 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 6412 /* init aeu_mask_attn_func_0/1:
6413 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6414 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6415 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 6416 val = IS_MF(bp) ? 0xF7 : 0x7;
6417 /* Enable DCBX attention for all but E1 */
6418 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6419 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 6420
619c5cb6
VZ		 6421 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6422
6423 if (!CHIP_IS_E1x(bp)) {
6424 /* Bit-map indicating which L2 hdrs may appear after the
6425 * basic Ethernet header
6426 */
6427 REG_WR(bp, BP_PORT(bp) ?
6428 NIG_REG_P1_HDRS_AFTER_BASIC :
6429 NIG_REG_P0_HDRS_AFTER_BASIC,
6430 IS_MF_SD(bp) ? 7 : 6);
6431
6432 if (CHIP_IS_E3(bp))
6433 REG_WR(bp, BP_PORT(bp) ?
6434 NIG_REG_LLH1_MF_MODE :
6435 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6436 }
6437 if (!CHIP_IS_E3(bp))
6438 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 6439
f2e0899f 6440 if (!CHIP_IS_E1(bp)) {
fb3bff17 6441 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 6442 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 6443 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 6444
619c5cb6 6445 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6446 val = 0;
6447 switch (bp->mf_mode) {
6448 case MULTI_FUNCTION_SD:
6449 val = 1;
6450 break;
6451 case MULTI_FUNCTION_SI:
6452 val = 2;
6453 break;
6454 }
6455
6456 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6457 NIG_REG_LLH0_CLS_TYPE), val);
6458 }
1c06328c
EG		 6459 {
6460 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6461 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6462 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6463 }
34f80b04
EG		 6464 }
6465
619c5cb6
VZ		 6466
6467 /* If SPIO5 is set to generate interrupts, enable it for this port */
6468 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6469 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
4d295db0
EG		 6470 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6471 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6472 val = REG_RD(bp, reg_addr);
f1410647 6473 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 6474 REG_WR(bp, reg_addr, val);
f1410647 6475 }
a2fbb9ea 6476
34f80b04
EG		 6477 return 0;
6478}
6479
34f80b04
EG		 6480static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6481{
6482 int reg;
32d68de1 6483 u32 wb_write[2];
34f80b04 6484
f2e0899f 6485 if (CHIP_IS_E1(bp))
34f80b04 6486 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 6487 else
6488 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 6489
32d68de1
YM		 6490 wb_write[0] = ONCHIP_ADDR1(addr);
6491 wb_write[1] = ONCHIP_ADDR2(addr);
6492 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 6493}
6494
f2e0899f
DK		 6495static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6496{
619c5cb6 6497 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 6498}
6499
6500static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6501{
6502 u32 i, base = FUNC_ILT_BASE(func);
6503 for (i = base; i < base + ILT_PER_FUNC; i++)
6504 bnx2x_ilt_wr(bp, i, 0);
6505}
6506
523224a3 6507static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 6508{
6509 int port = BP_PORT(bp);
6510 int func = BP_FUNC(bp);
619c5cb6 6511 int init_phase = PHASE_PF0 + func;
523224a3
DK		 6512 struct bnx2x_ilt *ilt = BP_ILT(bp);
6513 u16 cdu_ilt_start;
8badd27a 6514 u32 addr, val;
f4a66897 6515 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 6516 int i, main_mem_width, rc;
34f80b04 6517
51c1a580 6518 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 6519
619c5cb6 6520 /* FLR cleanup - hmmm */
89db4ad8
AE		 6521 if (!CHIP_IS_E1x(bp)) {
6522 rc = bnx2x_pf_flr_clnup(bp);
6523 if (rc)
6524 return rc;
6525 }
619c5cb6 6526
8badd27a 6527 /* set MSI reconfigure capability */
f2e0899f
DK		 6528 if (bp->common.int_block == INT_BLOCK_HC) {
6529 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6530 val = REG_RD(bp, addr);
6531 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6532 REG_WR(bp, addr, val);
6533 }
8badd27a 6534
619c5cb6
VZ		 6535 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6536 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6537
523224a3
DK		 6538 ilt = BP_ILT(bp);
6539 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 6540
523224a3
DK		 6541 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6542 ilt->lines[cdu_ilt_start + i].page =
6543 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6544 ilt->lines[cdu_ilt_start + i].page_mapping =
6545 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6546 /* cdu ilt pages are allocated manually so there's no need to
6547 set the size */
37b091ba 6548 }
523224a3 6549 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 6550
523224a3
DK		 6551#ifdef BCM_CNIC
6552 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 6553
523224a3
DK		 6554 /* T1 hash bits value determines the T1 number of entries */
6555 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6556#endif
37b091ba 6557
523224a3
DK		 6558#ifndef BCM_CNIC
6559 /* set NIC mode */
6560 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6561#endif /* BCM_CNIC */
37b091ba 6562
619c5cb6 6563 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6564 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6565
6566 /* Turn on a single ISR mode in IGU if driver is going to use
6567 * INT#x or MSI
6568 */
6569 if (!(bp->flags & USING_MSIX_FLAG))
6570 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6571 /*
6572 * Timers workaround bug: function init part.
6573 * Need to wait 20msec after initializing ILT,
6574 * needed to make sure there are no requests in
6575 * one of the PXP internal queues with "old" ILT addresses
6576 */
6577 msleep(20);
6578 /*
6579 * Master enable - Due to WB DMAE writes performed before this
6580 * register is re-initialized as part of the regular function
6581 * init
6582 */
6583 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6584 /* Enable the function in IGU */
6585 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6586 }
6587
523224a3 6588 bp->dmae_ready = 1;
34f80b04 6589
619c5cb6 6590 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 6591
619c5cb6 6592 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6593 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6594
619c5cb6
VZ		 6595 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6596 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6597 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6598 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6599 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6600 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6601 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6602 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6603 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6604 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6605 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6606 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6607 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6608
6609 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6610 REG_WR(bp, QM_REG_PF_EN, 1);
6611
619c5cb6
VZ		 6612 if (!CHIP_IS_E1x(bp)) {
6613 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6614 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6615 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6616 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6617 }
6618 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6619
6620 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6621 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6622 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6623 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6624 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6625 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6626 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6627 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6628 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6629 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6630 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6631 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6632 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6633
619c5cb6 6634 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 6635
619c5cb6 6636 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 6637
619c5cb6 6638 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6639 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6640
fb3bff17 6641 if (IS_MF(bp)) {
34f80b04 6642 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 6643 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 6644 }
6645
619c5cb6 6646 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 6647
34f80b04 6648 /* HC init per function */
f2e0899f
DK		 6649 if (bp->common.int_block == INT_BLOCK_HC) {
6650 if (CHIP_IS_E1H(bp)) {
6651 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6652
6653 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6654 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6655 }
619c5cb6 6656 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 6657
6658 } else {
6659 int num_segs, sb_idx, prod_offset;
6660
34f80b04
EG		 6661 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6662
619c5cb6 6663 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6664 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6665 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6666 }
6667
619c5cb6 6668 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6669
619c5cb6 6670 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6671 int dsb_idx = 0;
6672 /**
6673 * Producer memory:
6674 * E2 mode: address 0-135 match to the mapping memory;
6675 * 136 - PF0 default prod; 137 - PF1 default prod;
6676 * 138 - PF2 default prod; 139 - PF3 default prod;
6677 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6678 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6679 * 144-147 reserved.
6680 *
6681 * E1.5 mode - In backward compatible mode;
6682 * for non default SB; each even line in the memory
6683 * holds the U producer and each odd line hold
6684 * the C producer. The first 128 producers are for
6685 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6686 * producers are for the DSB for each PF.
6687 * Each PF has five segments: (the order inside each
6688 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6689 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6690 * 144-147 attn prods;
6691 */
6692 /* non-default-status-blocks */
6693 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6694 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6695 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6696 prod_offset = (bp->igu_base_sb + sb_idx) *
6697 num_segs;
6698
6699 for (i = 0; i < num_segs; i++) {
6700 addr = IGU_REG_PROD_CONS_MEMORY +
6701 (prod_offset + i) * 4;
6702 REG_WR(bp, addr, 0);
6703 }
6704 /* send consumer update with value 0 */
6705 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6706 USTORM_ID, 0, IGU_INT_NOP, 1);
6707 bnx2x_igu_clear_sb(bp,
6708 bp->igu_base_sb + sb_idx);
6709 }
6710
6711 /* default-status-blocks */
6712 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6713 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6714
6715 if (CHIP_MODE_IS_4_PORT(bp))
6716 dsb_idx = BP_FUNC(bp);
6717 else
3395a033 6718 dsb_idx = BP_VN(bp);
f2e0899f
DK		 6719
6720 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6721 IGU_BC_BASE_DSB_PROD + dsb_idx :
6722 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6723
3395a033
DK		 6724 /*
6725 * igu prods come in chunks of E1HVN_MAX (4) -
6726 * does not matters what is the current chip mode
6727 */
f2e0899f
DK		 6728 for (i = 0; i < (num_segs * E1HVN_MAX);
6729 i += E1HVN_MAX) {
6730 addr = IGU_REG_PROD_CONS_MEMORY +
6731 (prod_offset + i)*4;
6732 REG_WR(bp, addr, 0);
6733 }
6734 /* send consumer update with 0 */
6735 if (CHIP_INT_MODE_IS_BC(bp)) {
6736 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6737 USTORM_ID, 0, IGU_INT_NOP, 1);
6738 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6739 CSTORM_ID, 0, IGU_INT_NOP, 1);
6740 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6741 XSTORM_ID, 0, IGU_INT_NOP, 1);
6742 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6743 TSTORM_ID, 0, IGU_INT_NOP, 1);
6744 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6745 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6746 } else {
6747 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6748 USTORM_ID, 0, IGU_INT_NOP, 1);
6749 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6750 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6751 }
6752 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6753
6754 /* !!! these should become driver const once
6755 rf-tool supports split-68 const */
6756 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6757 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6758 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6759 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6760 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6761 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6762 }
34f80b04 6763 }
34f80b04 6764
c14423fe 6765 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 6766 REG_WR(bp, 0x2114, 0xffffffff);
6767 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 6768
f4a66897
VZ		 6769 if (CHIP_IS_E1x(bp)) {
6770 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6771 main_mem_base = HC_REG_MAIN_MEMORY +
6772 BP_PORT(bp) * (main_mem_size * 4);
6773 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6774 main_mem_width = 8;
6775
6776 val = REG_RD(bp, main_mem_prty_clr);
6777 if (val)
51c1a580
MS		 6778 DP(NETIF_MSG_HW,
6779 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
6780 val);
f4a66897
VZ		 6781
6782 /* Clear "false" parity errors in MSI-X table */
6783 for (i = main_mem_base;
6784 i < main_mem_base + main_mem_size * 4;
6785 i += main_mem_width) {
6786 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6787 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6788 i, main_mem_width / 4);
6789 }
6790 /* Clear HC parity attention */
6791 REG_RD(bp, main_mem_prty_clr);
6792 }
6793
619c5cb6
VZ		 6794#ifdef BNX2X_STOP_ON_ERROR
6795 /* Enable STORMs SP logging */
6796 REG_WR8(bp, BAR_USTRORM_INTMEM +
6797 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6798 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6799 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6800 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6801 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6802 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6803 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6804#endif
6805
b7737c9b 6806 bnx2x_phy_probe(&bp->link_params);
f85582f8 6807
34f80b04
EG		 6808 return 0;
6809}
6810
a2fbb9ea 6811
9f6c9258 6812void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 6813{
a2fbb9ea 6814 /* fastpath */
b3b83c3f 6815 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 6816 /* end of fastpath */
6817
6818 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 6819 sizeof(struct host_sp_status_block));
a2fbb9ea 6820
619c5cb6
VZ		 6821 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6822 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6823
a2fbb9ea 6824 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 6825 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6826
523224a3
DK		 6827 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6828 bp->context.size);
6829
6830 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6831
6832 BNX2X_FREE(bp->ilt->lines);
f85582f8 6833
37b091ba 6834#ifdef BCM_CNIC
619c5cb6 6835 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6836 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6837 sizeof(struct host_hc_status_block_e2));
6838 else
6839 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6840 sizeof(struct host_hc_status_block_e1x));
f85582f8 6841
523224a3 6842 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 6843#endif
f85582f8 6844
7a9b2557 6845 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 6846
523224a3
DK		 6847 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6848 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 6849}
6850
6851static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6852{
6853 int num_groups;
50f0a562 6854 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
619c5cb6 6855
50f0a562
BW		 6856 /* number of queues for statistics is number of eth queues + FCoE */
6857 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
619c5cb6
VZ		 6858
6859 /* Total number of FW statistics requests =
50f0a562
BW		 6860 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
6861 * num of queues
6862 */
6863 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
523224a3 6864
619c5cb6
VZ		 6865
6866 /* Request is built from stats_query_header and an array of
6867 * stats_query_cmd_group each of which contains
6868 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6869 * configured in the stats_query_header.
6870 */
50f0a562
BW		 6871 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
6872 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
619c5cb6
VZ		 6873
6874 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6875 num_groups * sizeof(struct stats_query_cmd_group);
6876
6877 /* Data for statistics requests + stats_conter
6878 *
6879 * stats_counter holds per-STORM counters that are incremented
6880 * when STORM has finished with the current request.
50f0a562
BW		 6881 *
6882 * memory for FCoE offloaded statistics are counted anyway,
6883 * even if they will not be sent.
619c5cb6
VZ		 6884 */
6885 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6886 sizeof(struct per_pf_stats) +
50f0a562 6887 sizeof(struct fcoe_statistics_params) +
619c5cb6
VZ		 6888 sizeof(struct per_queue_stats) * num_queue_stats +
6889 sizeof(struct stats_counter);
6890
6891 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6892 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6893
6894 /* Set shortcuts */
6895 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6896 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6897
6898 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6899 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6900
6901 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6902 bp->fw_stats_req_sz;
6903 return 0;
6904
6905alloc_mem_err:
6906 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6907 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
51c1a580 6908 BNX2X_ERR("Can't allocate memory\n");
619c5cb6 6909 return -ENOMEM;
a2fbb9ea
ET		 6910}
6911
f2e0899f 6912
9f6c9258 6913int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 6914{
523224a3 6915#ifdef BCM_CNIC
619c5cb6
VZ		 6916 if (!CHIP_IS_E1x(bp))
6917 /* size = the status block + ramrod buffers */
f2e0899f
DK		 6918 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6919 sizeof(struct host_hc_status_block_e2));
6920 else
6921 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6922 sizeof(struct host_hc_status_block_e1x));
8badd27a 6923
523224a3
DK		 6924 /* allocate searcher T2 table */
6925 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6926#endif
a2fbb9ea 6927
8badd27a 6928
523224a3
DK		 6929 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6930 sizeof(struct host_sp_status_block));
a2fbb9ea 6931
523224a3
DK		 6932 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6933 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6934
82fa848c
MY		 6935#ifdef BCM_CNIC
6936 /* write address to which L5 should insert its values */
6937 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp;
6938#endif
6939
619c5cb6
VZ		 6940 /* Allocated memory for FW statistics */
6941 if (bnx2x_alloc_fw_stats_mem(bp))
6942 goto alloc_mem_err;
6943
6383c0b3 6944 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
f85582f8 6945
523224a3
DK		 6946 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6947 bp->context.size);
65abd74d 6948
523224a3 6949 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 6950
523224a3
DK		 6951 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6952 goto alloc_mem_err;
65abd74d 6953
9f6c9258
DK		 6954 /* Slow path ring */
6955 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 6956
523224a3
DK		 6957 /* EQ */
6958 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6959 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 6960
b3b83c3f
DK		 6961
6962 /* fastpath */
6963 /* need to be done at the end, since it's self adjusting to amount
6964 * of memory available for RSS queues
6965 */
6966 if (bnx2x_alloc_fp_mem(bp))
6967 goto alloc_mem_err;
9f6c9258 6968 return 0;
e1510706 6969
9f6c9258
DK		 6970alloc_mem_err:
6971 bnx2x_free_mem(bp);
51c1a580 6972 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 6973 return -ENOMEM;
65abd74d
YG		 6974}
6975
a2fbb9ea
ET		 6976/*
6977 * Init service functions
6978 */
a2fbb9ea 6979
619c5cb6
VZ		 6980int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6981 struct bnx2x_vlan_mac_obj *obj, bool set,
6982 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 6983{
619c5cb6
VZ		 6984 int rc;
6985 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 6986
619c5cb6 6987 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 6988
619c5cb6
VZ		 6989 /* Fill general parameters */
6990 ramrod_param.vlan_mac_obj = obj;
6991 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 6992
619c5cb6
VZ		 6993 /* Fill a user request section if needed */
6994 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6995 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 6996
619c5cb6 6997 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 6998
619c5cb6
VZ		 6999 /* Set the command: ADD or DEL */
7000 if (set)
7001 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7002 else
7003 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 7004 }
7005
619c5cb6
VZ		 7006 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7007 if (rc < 0)
7008 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7009 return rc;
a2fbb9ea
ET		 7010}
7011
619c5cb6
VZ		 7012int bnx2x_del_all_macs(struct bnx2x *bp,
7013 struct bnx2x_vlan_mac_obj *mac_obj,
7014 int mac_type, bool wait_for_comp)
e665bfda 7015{
619c5cb6
VZ		 7016 int rc;
7017 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 7018
619c5cb6
VZ		 7019 /* Wait for completion of requested */
7020 if (wait_for_comp)
7021 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 7022
619c5cb6
VZ		 7023 /* Set the mac type of addresses we want to clear */
7024 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 7025
619c5cb6
VZ		 7026 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7027 if (rc < 0)
7028 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 7029
619c5cb6 7030 return rc;
0793f83f
DK		 7031}
7032
619c5cb6 7033int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 7034{
619c5cb6 7035 unsigned long ramrod_flags = 0;
e665bfda 7036
614c76df 7037#ifdef BCM_CNIC
9e62e912 7038 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_STORAGE_SD(bp)) {
51c1a580
MS		 7039 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7040 "Ignoring Zero MAC for STORAGE SD mode\n");
614c76df
DK		 7041 return 0;
7042 }
7043#endif
7044
619c5cb6 7045 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 7046
619c5cb6
VZ		 7047 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7048 /* Eth MAC is set on RSS leading client (fp[0]) */
7049 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7050 BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 7051}
6e30dd4e 7052
619c5cb6 7053int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 7054{
619c5cb6 7055 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 7056}
a2fbb9ea 7057
d6214d7a 7058/**
e8920674 7059 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 7060 *
e8920674 7061 * @bp: driver handle
d6214d7a 7062 *
e8920674 7063 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 7064 */
9ee3d37b 7065static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 7066{
9ee3d37b 7067 switch (int_mode) {
d6214d7a
DK		 7068 case INT_MODE_MSI:
7069 bnx2x_enable_msi(bp);
7070 /* falling through... */
7071 case INT_MODE_INTx:
6383c0b3 7072 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
51c1a580 7073 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 7074 break;
d6214d7a 7075 default:
30a5de77 7076 /* Set number of queues for MSI-X mode */
d6214d7a 7077 bnx2x_set_num_queues(bp);
ca00392c 7078
51c1a580 7079 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
ca00392c 7080
d6214d7a
DK		 7081 /* if we can't use MSI-X we only need one fp,
7082 * so try to enable MSI-X with the requested number of fp's
7083 * and fallback to MSI or legacy INTx with one fp
7084 */
30a5de77
DK		 7085 if (bnx2x_enable_msix(bp) ||
7086 bp->flags & USING_SINGLE_MSIX_FLAG) {
7087 /* failed to enable multiple MSI-X */
7088 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
51c1a580
MS		 7089 bp->num_queues, 1 + NON_ETH_CONTEXT_USE);
7090
6383c0b3 7091 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7092
9ee3d37b 7093 /* Try to enable MSI */
30a5de77
DK		 7094 if (!(bp->flags & USING_SINGLE_MSIX_FLAG) &&
7095 !(bp->flags & DISABLE_MSI_FLAG))
d6214d7a
DK		 7096 bnx2x_enable_msi(bp);
7097 }
9f6c9258
DK		 7098 break;
7099 }
a2fbb9ea
ET		 7100}
7101
c2bff63f
DK		 7102/* must be called prioir to any HW initializations */
7103static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7104{
7105 return L2_ILT_LINES(bp);
7106}
7107
523224a3
DK		 7108void bnx2x_ilt_set_info(struct bnx2x *bp)
7109{
7110 struct ilt_client_info *ilt_client;
7111 struct bnx2x_ilt *ilt = BP_ILT(bp);
7112 u16 line = 0;
7113
7114 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7115 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7116
7117 /* CDU */
7118 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7119 ilt_client->client_num = ILT_CLIENT_CDU;
7120 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7121 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7122 ilt_client->start = line;
619c5cb6 7123 line += bnx2x_cid_ilt_lines(bp);
523224a3
DK		 7124#ifdef BCM_CNIC
7125 line += CNIC_ILT_LINES;
7126#endif
7127 ilt_client->end = line - 1;
7128
51c1a580 7129 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 7130 ilt_client->start,
7131 ilt_client->end,
7132 ilt_client->page_size,
7133 ilt_client->flags,
7134 ilog2(ilt_client->page_size >> 12));
7135
7136 /* QM */
7137 if (QM_INIT(bp->qm_cid_count)) {
7138 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7139 ilt_client->client_num = ILT_CLIENT_QM;
7140 ilt_client->page_size = QM_ILT_PAGE_SZ;
7141 ilt_client->flags = 0;
7142 ilt_client->start = line;
7143
7144 /* 4 bytes for each cid */
7145 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7146 QM_ILT_PAGE_SZ);
7147
7148 ilt_client->end = line - 1;
7149
51c1a580
MS		 7150 DP(NETIF_MSG_IFUP,
7151 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 7152 ilt_client->start,
7153 ilt_client->end,
7154 ilt_client->page_size,
7155 ilt_client->flags,
7156 ilog2(ilt_client->page_size >> 12));
7157
7158 }
7159 /* SRC */
7160 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7161#ifdef BCM_CNIC
7162 ilt_client->client_num = ILT_CLIENT_SRC;
7163 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7164 ilt_client->flags = 0;
7165 ilt_client->start = line;
7166 line += SRC_ILT_LINES;
7167 ilt_client->end = line - 1;
7168
51c1a580
MS		 7169 DP(NETIF_MSG_IFUP,
7170 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 7171 ilt_client->start,
7172 ilt_client->end,
7173 ilt_client->page_size,
7174 ilt_client->flags,
7175 ilog2(ilt_client->page_size >> 12));
7176
7177#else
7178 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7179#endif
9f6c9258 7180
523224a3
DK		 7181 /* TM */
7182 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7183#ifdef BCM_CNIC
7184 ilt_client->client_num = ILT_CLIENT_TM;
7185 ilt_client->page_size = TM_ILT_PAGE_SZ;
7186 ilt_client->flags = 0;
7187 ilt_client->start = line;
7188 line += TM_ILT_LINES;
7189 ilt_client->end = line - 1;
7190
51c1a580
MS		 7191 DP(NETIF_MSG_IFUP,
7192 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 7193 ilt_client->start,
7194 ilt_client->end,
7195 ilt_client->page_size,
7196 ilt_client->flags,
7197 ilog2(ilt_client->page_size >> 12));
9f6c9258 7198
523224a3
DK		 7199#else
7200 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7201#endif
619c5cb6 7202 BUG_ON(line > ILT_MAX_LINES);
523224a3 7203}
f85582f8 7204
619c5cb6
VZ		 7205/**
7206 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7207 *
7208 * @bp: driver handle
7209 * @fp: pointer to fastpath
7210 * @init_params: pointer to parameters structure
7211 *
7212 * parameters configured:
7213 * - HC configuration
7214 * - Queue's CDU context
7215 */
7216static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7217 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 7218{
6383c0b3
AE		 7219
7220 u8 cos;
619c5cb6
VZ		 7221 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7222 if (!IS_FCOE_FP(fp)) {
7223 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7224 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7225
7226 /* If HC is supporterd, enable host coalescing in the transition
7227 * to INIT state.
7228 */
7229 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7230 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7231
7232 /* HC rate */
7233 init_params->rx.hc_rate = bp->rx_ticks ?
7234 (1000000 / bp->rx_ticks) : 0;
7235 init_params->tx.hc_rate = bp->tx_ticks ?
7236 (1000000 / bp->tx_ticks) : 0;
7237
7238 /* FW SB ID */
7239 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7240 fp->fw_sb_id;
7241
7242 /*
7243 * CQ index among the SB indices: FCoE clients uses the default
7244 * SB, therefore it's different.
7245 */
6383c0b3
AE		 7246 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7247 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 7248 }
7249
6383c0b3
AE		 7250 /* set maximum number of COSs supported by this queue */
7251 init_params->max_cos = fp->max_cos;
7252
51c1a580 7253 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 7254 fp->index, init_params->max_cos);
7255
7256 /* set the context pointers queue object */
7257 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7258 init_params->cxts[cos] =
7259 &bp->context.vcxt[fp->txdata[cos].cid].eth;
619c5cb6
VZ		 7260}
7261
6383c0b3
AE		 7262int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7263 struct bnx2x_queue_state_params *q_params,
7264 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7265 int tx_index, bool leading)
7266{
7267 memset(tx_only_params, 0, sizeof(*tx_only_params));
7268
7269 /* Set the command */
7270 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7271
7272 /* Set tx-only QUEUE flags: don't zero statistics */
7273 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7274
7275 /* choose the index of the cid to send the slow path on */
7276 tx_only_params->cid_index = tx_index;
7277
7278 /* Set general TX_ONLY_SETUP parameters */
7279 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7280
7281 /* Set Tx TX_ONLY_SETUP parameters */
7282 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7283
51c1a580
MS		 7284 DP(NETIF_MSG_IFUP,
7285 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 7286 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7287 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7288 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7289
7290 /* send the ramrod */
7291 return bnx2x_queue_state_change(bp, q_params);
7292}
7293
7294
619c5cb6
VZ		 7295/**
7296 * bnx2x_setup_queue - setup queue
7297 *
7298 * @bp: driver handle
7299 * @fp: pointer to fastpath
7300 * @leading: is leading
7301 *
7302 * This function performs 2 steps in a Queue state machine
7303 * actually: 1) RESET->INIT 2) INIT->SETUP
7304 */
7305
7306int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7307 bool leading)
7308{
3b603066 7309 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 7310 struct bnx2x_queue_setup_params *setup_params =
7311 &q_params.params.setup;
6383c0b3
AE		 7312 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7313 &q_params.params.tx_only;
a2fbb9ea 7314 int rc;
6383c0b3
AE		 7315 u8 tx_index;
7316
51c1a580 7317 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 7318
ec6ba945
VZ		 7319 /* reset IGU state skip FCoE L2 queue */
7320 if (!IS_FCOE_FP(fp))
7321 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 7322 IGU_INT_ENABLE, 0);
a2fbb9ea 7323
619c5cb6
VZ		 7324 q_params.q_obj = &fp->q_obj;
7325 /* We want to wait for completion in this context */
7326 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7327
619c5cb6
VZ		 7328 /* Prepare the INIT parameters */
7329 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 7330
619c5cb6
VZ		 7331 /* Set the command */
7332 q_params.cmd = BNX2X_Q_CMD_INIT;
7333
7334 /* Change the state to INIT */
7335 rc = bnx2x_queue_state_change(bp, &q_params);
7336 if (rc) {
6383c0b3 7337 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 7338 return rc;
7339 }
ec6ba945 7340
51c1a580 7341 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3
AE		 7342
7343
619c5cb6
VZ		 7344 /* Now move the Queue to the SETUP state... */
7345 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 7346
619c5cb6
VZ		 7347 /* Set QUEUE flags */
7348 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 7349
619c5cb6 7350 /* Set general SETUP parameters */
6383c0b3
AE		 7351 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7352 FIRST_TX_COS_INDEX);
619c5cb6 7353
6383c0b3 7354 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 7355 &setup_params->rxq_params);
7356
6383c0b3
AE		 7357 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7358 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 7359
7360 /* Set the command */
7361 q_params.cmd = BNX2X_Q_CMD_SETUP;
7362
7363 /* Change the state to SETUP */
7364 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 7365 if (rc) {
7366 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7367 return rc;
7368 }
7369
7370 /* loop through the relevant tx-only indices */
7371 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7372 tx_index < fp->max_cos;
7373 tx_index++) {
7374
7375 /* prepare and send tx-only ramrod*/
7376 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7377 tx_only_params, tx_index, leading);
7378 if (rc) {
7379 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7380 fp->index, tx_index);
7381 return rc;
7382 }
7383 }
523224a3 7384
34f80b04 7385 return rc;
a2fbb9ea
ET		 7386}
7387
619c5cb6 7388static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 7389{
619c5cb6 7390 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 7391 struct bnx2x_fp_txdata *txdata;
3b603066 7392 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 7393 int rc, tx_index;
7394
51c1a580 7395 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 7396
619c5cb6
VZ		 7397 q_params.q_obj = &fp->q_obj;
7398 /* We want to wait for completion in this context */
7399 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7400
6383c0b3
AE		 7401
7402 /* close tx-only connections */
7403 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7404 tx_index < fp->max_cos;
7405 tx_index++){
7406
7407 /* ascertain this is a normal queue*/
7408 txdata = &fp->txdata[tx_index];
7409
51c1a580 7410 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 7411 txdata->txq_index);
7412
7413 /* send halt terminate on tx-only connection */
7414 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7415 memset(&q_params.params.terminate, 0,
7416 sizeof(q_params.params.terminate));
7417 q_params.params.terminate.cid_index = tx_index;
7418
7419 rc = bnx2x_queue_state_change(bp, &q_params);
7420 if (rc)
7421 return rc;
7422
7423 /* send halt terminate on tx-only connection */
7424 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7425 memset(&q_params.params.cfc_del, 0,
7426 sizeof(q_params.params.cfc_del));
7427 q_params.params.cfc_del.cid_index = tx_index;
7428 rc = bnx2x_queue_state_change(bp, &q_params);
7429 if (rc)
7430 return rc;
7431 }
7432 /* Stop the primary connection: */
7433 /* ...halt the connection */
619c5cb6
VZ		 7434 q_params.cmd = BNX2X_Q_CMD_HALT;
7435 rc = bnx2x_queue_state_change(bp, &q_params);
7436 if (rc)
da5a662a 7437 return rc;
a2fbb9ea 7438
6383c0b3 7439 /* ...terminate the connection */
619c5cb6 7440 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 7441 memset(&q_params.params.terminate, 0,
7442 sizeof(q_params.params.terminate));
7443 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 7444 rc = bnx2x_queue_state_change(bp, &q_params);
7445 if (rc)
523224a3 7446 return rc;
6383c0b3 7447 /* ...delete cfc entry */
619c5cb6 7448 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 7449 memset(&q_params.params.cfc_del, 0,
7450 sizeof(q_params.params.cfc_del));
7451 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 7452 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 7453}
7454
7455
34f80b04
EG		 7456static void bnx2x_reset_func(struct bnx2x *bp)
7457{
7458 int port = BP_PORT(bp);
7459 int func = BP_FUNC(bp);
f2e0899f 7460 int i;
523224a3
DK		 7461
7462 /* Disable the function in the FW */
7463 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7464 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7465 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7466 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7467
7468 /* FP SBs */
ec6ba945 7469 for_each_eth_queue(bp, i) {
523224a3 7470 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 7471 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7472 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7473 SB_DISABLED);
523224a3
DK		 7474 }
7475
619c5cb6
VZ		 7476#ifdef BCM_CNIC
7477 /* CNIC SB */
7478 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7479 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7480 SB_DISABLED);
7481#endif
523224a3 7482 /* SP SB */
619c5cb6 7483 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7484 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7485 SB_DISABLED);
523224a3
DK		 7486
7487 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7488 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7489 0);
34f80b04
EG		 7490
7491 /* Configure IGU */
f2e0899f
DK		 7492 if (bp->common.int_block == INT_BLOCK_HC) {
7493 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7494 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7495 } else {
7496 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7497 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7498 }
34f80b04 7499
37b091ba
MC		 7500#ifdef BCM_CNIC
7501 /* Disable Timer scan */
7502 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7503 /*
7504 * Wait for at least 10ms and up to 2 second for the timers scan to
7505 * complete
7506 */
7507 for (i = 0; i < 200; i++) {
7508 msleep(10);
7509 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7510 break;
7511 }
7512#endif
34f80b04 7513 /* Clear ILT */
f2e0899f
DK		 7514 bnx2x_clear_func_ilt(bp, func);
7515
7516 /* Timers workaround bug for E2: if this is vnic-3,
7517 * we need to set the entire ilt range for this timers.
7518 */
619c5cb6 7519 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 7520 struct ilt_client_info ilt_cli;
7521 /* use dummy TM client */
7522 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7523 ilt_cli.start = 0;
7524 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7525 ilt_cli.client_num = ILT_CLIENT_TM;
7526
7527 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7528 }
7529
7530 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 7531 if (!CHIP_IS_E1x(bp))
f2e0899f 7532 bnx2x_pf_disable(bp);
523224a3
DK		 7533
7534 bp->dmae_ready = 0;
34f80b04
EG		 7535}
7536
7537static void bnx2x_reset_port(struct bnx2x *bp)
7538{
7539 int port = BP_PORT(bp);
7540 u32 val;
7541
619c5cb6
VZ		 7542 /* Reset physical Link */
7543 bnx2x__link_reset(bp);
7544
34f80b04
EG		 7545 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7546
7547 /* Do not rcv packets to BRB */
7548 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7549 /* Do not direct rcv packets that are not for MCP to the BRB */
7550 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7551 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7552
7553 /* Configure AEU */
7554 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7555
7556 msleep(100);
7557 /* Check for BRB port occupancy */
7558 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7559 if (val)
7560 DP(NETIF_MSG_IFDOWN,
33471629 7561 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 7562
7563 /* TODO: Close Doorbell port? */
7564}
7565
619c5cb6 7566static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 7567{
3b603066 7568 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 7569
619c5cb6
VZ		 7570 /* Prepare parameters for function state transitions */
7571 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 7572
619c5cb6
VZ		 7573 func_params.f_obj = &bp->func_obj;
7574 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 7575
619c5cb6 7576 func_params.params.hw_init.load_phase = load_code;
49d66772 7577
619c5cb6 7578 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 7579}
7580
619c5cb6 7581static inline int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 7582{
3b603066 7583 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 7584 int rc;
228241eb 7585
619c5cb6
VZ		 7586 /* Prepare parameters for function state transitions */
7587 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7588 func_params.f_obj = &bp->func_obj;
7589 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 7590
619c5cb6
VZ		 7591 /*
7592 * Try to stop the function the 'good way'. If fails (in case
7593 * of a parity error during bnx2x_chip_cleanup()) and we are
7594 * not in a debug mode, perform a state transaction in order to
7595 * enable further HW_RESET transaction.
7596 */
7597 rc = bnx2x_func_state_change(bp, &func_params);
7598 if (rc) {
34f80b04 7599#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 7600 return rc;
34f80b04 7601#else
51c1a580 7602 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 7603 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7604 return bnx2x_func_state_change(bp, &func_params);
34f80b04 7605#endif
228241eb 7606 }
a2fbb9ea 7607
619c5cb6
VZ		 7608 return 0;
7609}
523224a3 7610
619c5cb6
VZ		 7611/**
7612 * bnx2x_send_unload_req - request unload mode from the MCP.
7613 *
7614 * @bp: driver handle
7615 * @unload_mode: requested function's unload mode
7616 *
7617 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7618 */
7619u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7620{
7621 u32 reset_code = 0;
7622 int port = BP_PORT(bp);
3101c2bc 7623
619c5cb6 7624 /* Select the UNLOAD request mode */
65abd74d
YG		 7625 if (unload_mode == UNLOAD_NORMAL)
7626 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7627
7d0446c2 7628 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7629 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7630
7d0446c2 7631 else if (bp->wol) {
65abd74d
YG		 7632 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7633 u8 *mac_addr = bp->dev->dev_addr;
7634 u32 val;
f9977903
DK		 7635 u16 pmc;
7636
65abd74d 7637 /* The mac address is written to entries 1-4 to
f9977903
DK		 7638 * preserve entry 0 which is used by the PMF
7639 */
3395a033 7640 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 7641
7642 val = (mac_addr[0] << 8) | mac_addr[1];
7643 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7644
7645 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7646 (mac_addr[4] << 8) | mac_addr[5];
7647 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7648
f9977903
DK		 7649 /* Enable the PME and clear the status */
7650 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
7651 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
7652 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
7653
65abd74d
YG		 7654 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7655
7656 } else
7657 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7658
619c5cb6
VZ		 7659 /* Send the request to the MCP */
7660 if (!BP_NOMCP(bp))
7661 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7662 else {
7663 int path = BP_PATH(bp);
7664
51c1a580 7665 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
619c5cb6
VZ		 7666 path, load_count[path][0], load_count[path][1],
7667 load_count[path][2]);
7668 load_count[path][0]--;
7669 load_count[path][1 + port]--;
51c1a580 7670 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
619c5cb6
VZ		 7671 path, load_count[path][0], load_count[path][1],
7672 load_count[path][2]);
7673 if (load_count[path][0] == 0)
7674 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7675 else if (load_count[path][1 + port] == 0)
7676 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7677 else
7678 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7679 }
7680
7681 return reset_code;
7682}
7683
7684/**
7685 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7686 *
7687 * @bp: driver handle
7688 */
7689void bnx2x_send_unload_done(struct bnx2x *bp)
7690{
7691 /* Report UNLOAD_DONE to MCP */
7692 if (!BP_NOMCP(bp))
7693 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7694}
7695
6debea87
DK		 7696static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7697{
7698 int tout = 50;
7699 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7700
7701 if (!bp->port.pmf)
7702 return 0;
7703
7704 /*
7705 * (assumption: No Attention from MCP at this stage)
7706 * PMF probably in the middle of TXdisable/enable transaction
7707 * 1. Sync IRS for default SB
7708 * 2. Sync SP queue - this guarantes us that attention handling started
7709 * 3. Wait, that TXdisable/enable transaction completes
7710 *
7711 * 1+2 guranty that if DCBx attention was scheduled it already changed
7712 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7713 * received complettion for the transaction the state is TX_STOPPED.
7714 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7715 * transaction.
7716 */
7717
7718 /* make sure default SB ISR is done */
7719 if (msix)
7720 synchronize_irq(bp->msix_table[0].vector);
7721 else
7722 synchronize_irq(bp->pdev->irq);
7723
7724 flush_workqueue(bnx2x_wq);
7725
7726 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7727 BNX2X_F_STATE_STARTED && tout--)
7728 msleep(20);
7729
7730 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7731 BNX2X_F_STATE_STARTED) {
7732#ifdef BNX2X_STOP_ON_ERROR
51c1a580 7733 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 7734 return -EBUSY;
7735#else
7736 /*
7737 * Failed to complete the transaction in a "good way"
7738 * Force both transactions with CLR bit
7739 */
3b603066 7740 struct bnx2x_func_state_params func_params = {NULL};
6debea87 7741
51c1a580
MS		 7742 DP(NETIF_MSG_IFDOWN,
7743 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
6debea87
DK		 7744
7745 func_params.f_obj = &bp->func_obj;
7746 __set_bit(RAMROD_DRV_CLR_ONLY,
7747 &func_params.ramrod_flags);
7748
7749 /* STARTED-->TX_ST0PPED */
7750 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7751 bnx2x_func_state_change(bp, &func_params);
7752
7753 /* TX_ST0PPED-->STARTED */
7754 func_params.cmd = BNX2X_F_CMD_TX_START;
7755 return bnx2x_func_state_change(bp, &func_params);
7756#endif
7757 }
7758
7759 return 0;
7760}
7761
619c5cb6
VZ		 7762void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7763{
7764 int port = BP_PORT(bp);
6383c0b3
AE		 7765 int i, rc = 0;
7766 u8 cos;
3b603066 7767 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 7768 u32 reset_code;
7769
7770 /* Wait until tx fastpath tasks complete */
7771 for_each_tx_queue(bp, i) {
7772 struct bnx2x_fastpath *fp = &bp->fp[i];
7773
6383c0b3
AE		 7774 for_each_cos_in_tx_queue(fp, cos)
7775 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
619c5cb6
VZ		 7776#ifdef BNX2X_STOP_ON_ERROR
7777 if (rc)
7778 return;
7779#endif
7780 }
7781
7782 /* Give HW time to discard old tx messages */
7783 usleep_range(1000, 1000);
7784
7785 /* Clean all ETH MACs */
7786 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7787 if (rc < 0)
7788 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7789
7790 /* Clean up UC list */
7791 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7792 true);
7793 if (rc < 0)
51c1a580
MS		 7794 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
7795 rc);
619c5cb6
VZ		 7796
7797 /* Disable LLH */
7798 if (!CHIP_IS_E1(bp))
7799 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7800
7801 /* Set "drop all" (stop Rx).
7802 * We need to take a netif_addr_lock() here in order to prevent
7803 * a race between the completion code and this code.
7804 */
7805 netif_addr_lock_bh(bp->dev);
7806 /* Schedule the rx_mode command */
7807 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7808 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7809 else
7810 bnx2x_set_storm_rx_mode(bp);
7811
7812 /* Cleanup multicast configuration */
7813 rparam.mcast_obj = &bp->mcast_obj;
7814 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7815 if (rc < 0)
7816 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7817
7818 netif_addr_unlock_bh(bp->dev);
7819
7820
6debea87
DK		 7821
7822 /*
7823 * Send the UNLOAD_REQUEST to the MCP. This will return if
7824 * this function should perform FUNC, PORT or COMMON HW
7825 * reset.
7826 */
7827 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7828
7829 /*
7830 * (assumption: No Attention from MCP at this stage)
7831 * PMF probably in the middle of TXdisable/enable transaction
7832 */
7833 rc = bnx2x_func_wait_started(bp);
7834 if (rc) {
7835 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7836#ifdef BNX2X_STOP_ON_ERROR
7837 return;
7838#endif
7839 }
7840
34f80b04 7841 /* Close multi and leading connections
619c5cb6
VZ		 7842 * Completions for ramrods are collected in a synchronous way
7843 */
523224a3 7844 for_each_queue(bp, i)
619c5cb6 7845 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 7846#ifdef BNX2X_STOP_ON_ERROR
7847 return;
7848#else
228241eb 7849 goto unload_error;
523224a3 7850#endif
619c5cb6
VZ		 7851 /* If SP settings didn't get completed so far - something
7852 * very wrong has happen.
7853 */
7854 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7855 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 7856
619c5cb6
VZ		 7857#ifndef BNX2X_STOP_ON_ERROR
7858unload_error:
7859#endif
523224a3 7860 rc = bnx2x_func_stop(bp);
da5a662a 7861 if (rc) {
523224a3 7862 BNX2X_ERR("Function stop failed!\n");
da5a662a 7863#ifdef BNX2X_STOP_ON_ERROR
523224a3 7864 return;
523224a3 7865#endif
34f80b04 7866 }
a2fbb9ea 7867
523224a3
DK		 7868 /* Disable HW interrupts, NAPI */
7869 bnx2x_netif_stop(bp, 1);
7870
7871 /* Release IRQs */
d6214d7a 7872 bnx2x_free_irq(bp);
523224a3 7873
a2fbb9ea 7874 /* Reset the chip */
619c5cb6
VZ		 7875 rc = bnx2x_reset_hw(bp, reset_code);
7876 if (rc)
7877 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 7878
356e2385 7879
619c5cb6
VZ		 7880 /* Report UNLOAD_DONE to MCP */
7881 bnx2x_send_unload_done(bp);
72fd0718
VZ		 7882}
7883
9f6c9258 7884void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7885{
7886 u32 val;
7887
51c1a580 7888 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 7889
7890 if (CHIP_IS_E1(bp)) {
7891 int port = BP_PORT(bp);
7892 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7893 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7894
7895 val = REG_RD(bp, addr);
7896 val &= ~(0x300);
7897 REG_WR(bp, addr, val);
619c5cb6 7898 } else {
72fd0718
VZ		 7899 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7900 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7901 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7902 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7903 }
7904}
7905
72fd0718
VZ		 7906/* Close gates #2, #3 and #4: */
7907static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7908{
c9ee9206 7909 u32 val;
72fd0718
VZ		 7910
7911 /* Gates #2 and #4a are closed/opened for "not E1" only */
7912 if (!CHIP_IS_E1(bp)) {
7913 /* #4 */
c9ee9206 7914 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 7915 /* #2 */
c9ee9206 7916 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 7917 }
7918
7919 /* #3 */
c9ee9206
VZ		 7920 if (CHIP_IS_E1x(bp)) {
7921 /* Prevent interrupts from HC on both ports */
7922 val = REG_RD(bp, HC_REG_CONFIG_1);
7923 REG_WR(bp, HC_REG_CONFIG_1,
7924 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7925 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7926
7927 val = REG_RD(bp, HC_REG_CONFIG_0);
7928 REG_WR(bp, HC_REG_CONFIG_0,
7929 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7930 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7931 } else {
7932 /* Prevent incomming interrupts in IGU */
7933 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7934
7935 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7936 (!close) ?
7937 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7938 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7939 }
72fd0718 7940
51c1a580 7941 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 7942 close ? "closing" : "opening");
7943 mmiowb();
7944}
7945
7946#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7947
7948static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7949{
7950 /* Do some magic... */
7951 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7952 *magic_val = val & SHARED_MF_CLP_MAGIC;
7953 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7954}
7955
e8920674
DK		 7956/**
7957 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 7958 *
e8920674
DK		 7959 * @bp: driver handle
7960 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 7961 */
7962static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7963{
7964 /* Restore the `magic' bit value... */
72fd0718
VZ		 7965 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7966 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7967 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7968}
7969
f85582f8 7970/**
e8920674 7971 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 7972 *
e8920674
DK		 7973 * @bp: driver handle
7974 * @magic_val: old value of 'magic' bit.
7975 *
7976 * Takes care of CLP configurations.
72fd0718
VZ		 7977 */
7978static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7979{
7980 u32 shmem;
7981 u32 validity_offset;
7982
51c1a580 7983 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 7984
7985 /* Set `magic' bit in order to save MF config */
7986 if (!CHIP_IS_E1(bp))
7987 bnx2x_clp_reset_prep(bp, magic_val);
7988
7989 /* Get shmem offset */
7990 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7991 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7992
7993 /* Clear validity map flags */
7994 if (shmem > 0)
7995 REG_WR(bp, shmem + validity_offset, 0);
7996}
7997
7998#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7999#define MCP_ONE_TIMEOUT 100 /* 100 ms */
8000
e8920674
DK		 8001/**
8002 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 8003 *
e8920674 8004 * @bp: driver handle
72fd0718
VZ		 8005 */
8006static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
8007{
8008 /* special handling for emulation and FPGA,
8009 wait 10 times longer */
8010 if (CHIP_REV_IS_SLOW(bp))
8011 msleep(MCP_ONE_TIMEOUT*10);
8012 else
8013 msleep(MCP_ONE_TIMEOUT);
8014}
8015
1b6e2ceb
DK		 8016/*
8017 * initializes bp->common.shmem_base and waits for validity signature to appear
8018 */
8019static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 8020{
1b6e2ceb
DK		 8021 int cnt = 0;
8022 u32 val = 0;
72fd0718 8023
1b6e2ceb
DK		 8024 do {
8025 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8026 if (bp->common.shmem_base) {
8027 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8028 if (val & SHR_MEM_VALIDITY_MB)
8029 return 0;
8030 }
72fd0718 8031
1b6e2ceb 8032 bnx2x_mcp_wait_one(bp);
72fd0718 8033
1b6e2ceb 8034 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 8035
1b6e2ceb 8036 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 8037
1b6e2ceb
DK		 8038 return -ENODEV;
8039}
72fd0718 8040
1b6e2ceb
DK		 8041static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8042{
8043 int rc = bnx2x_init_shmem(bp);
72fd0718 8044
72fd0718
VZ		 8045 /* Restore the `magic' bit value */
8046 if (!CHIP_IS_E1(bp))
8047 bnx2x_clp_reset_done(bp, magic_val);
8048
8049 return rc;
8050}
8051
8052static void bnx2x_pxp_prep(struct bnx2x *bp)
8053{
8054 if (!CHIP_IS_E1(bp)) {
8055 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8056 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 8057 mmiowb();
8058 }
8059}
8060
8061/*
8062 * Reset the whole chip except for:
8063 * - PCIE core
8064 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8065 * one reset bit)
8066 * - IGU
8067 * - MISC (including AEU)
8068 * - GRC
8069 * - RBCN, RBCP
8070 */
c9ee9206 8071static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 8072{
8073 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 8074 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 8075
8076 /*
8077 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8078 * (per chip) blocks.
8079 */
8080 global_bits2 =
8081 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8082 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 8083
8736c826 8084 /* Don't reset the following blocks */
72fd0718
VZ		 8085 not_reset_mask1 =
8086 MISC_REGISTERS_RESET_REG_1_RST_HC |
8087 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8088 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8089
8090 not_reset_mask2 =
c9ee9206 8091 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 8092 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8093 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8094 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8095 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8096 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8097 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 8098 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8099 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8100 MISC_REGISTERS_RESET_REG_2_PGLC;
72fd0718 8101
8736c826
VZ		 8102 /*
8103 * Keep the following blocks in reset:
8104 * - all xxMACs are handled by the bnx2x_link code.
8105 */
8106 stay_reset2 =
8107 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8108 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8109 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8110 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8111 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8112 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8113 MISC_REGISTERS_RESET_REG_2_XMAC |
8114 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8115
8116 /* Full reset masks according to the chip */
72fd0718
VZ		 8117 reset_mask1 = 0xffffffff;
8118
8119 if (CHIP_IS_E1(bp))
8120 reset_mask2 = 0xffff;
8736c826 8121 else if (CHIP_IS_E1H(bp))
72fd0718 8122 reset_mask2 = 0x1ffff;
8736c826
VZ		 8123 else if (CHIP_IS_E2(bp))
8124 reset_mask2 = 0xfffff;
8125 else /* CHIP_IS_E3 */
8126 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 8127
8128 /* Don't reset global blocks unless we need to */
8129 if (!global)
8130 reset_mask2 &= ~global_bits2;
8131
8132 /*
8133 * In case of attention in the QM, we need to reset PXP
8134 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8135 * because otherwise QM reset would release 'close the gates' shortly
8136 * before resetting the PXP, then the PSWRQ would send a write
8137 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8138 * read the payload data from PSWWR, but PSWWR would not
8139 * respond. The write queue in PGLUE would stuck, dmae commands
8140 * would not return. Therefore it's important to reset the second
8141 * reset register (containing the
8142 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8143 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8144 * bit).
8145 */
72fd0718
VZ		 8146 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8147 reset_mask2 & (~not_reset_mask2));
8148
c9ee9206
VZ		 8149 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8150 reset_mask1 & (~not_reset_mask1));
8151
72fd0718
VZ		 8152 barrier();
8153 mmiowb();
8154
8736c826
VZ		 8155 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8156 reset_mask2 & (~stay_reset2));
8157
8158 barrier();
8159 mmiowb();
8160
c9ee9206 8161 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 8162 mmiowb();
8163}
8164
c9ee9206
VZ		 8165/**
8166 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8167 * It should get cleared in no more than 1s.
8168 *
8169 * @bp: driver handle
8170 *
8171 * It should get cleared in no more than 1s. Returns 0 if
8172 * pending writes bit gets cleared.
8173 */
8174static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8175{
8176 u32 cnt = 1000;
8177 u32 pend_bits = 0;
8178
8179 do {
8180 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8181
8182 if (pend_bits == 0)
8183 break;
8184
8185 usleep_range(1000, 1000);
8186 } while (cnt-- > 0);
8187
8188 if (cnt <= 0) {
8189 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8190 pend_bits);
8191 return -EBUSY;
8192 }
8193
8194 return 0;
8195}
8196
8197static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 8198{
8199 int cnt = 1000;
8200 u32 val = 0;
8201 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8202
8203
8204 /* Empty the Tetris buffer, wait for 1s */
8205 do {
8206 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8207 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8208 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8209 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8210 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8211 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8212 ((port_is_idle_0 & 0x1) == 0x1) &&
8213 ((port_is_idle_1 & 0x1) == 0x1) &&
8214 (pgl_exp_rom2 == 0xffffffff))
8215 break;
c9ee9206 8216 usleep_range(1000, 1000);
72fd0718
VZ		 8217 } while (cnt-- > 0);
8218
8219 if (cnt <= 0) {
51c1a580
MS		 8220 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8221 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 8222 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8223 pgl_exp_rom2);
8224 return -EAGAIN;
8225 }
8226
8227 barrier();
8228
8229 /* Close gates #2, #3 and #4 */
8230 bnx2x_set_234_gates(bp, true);
8231
c9ee9206
VZ		 8232 /* Poll for IGU VQs for 57712 and newer chips */
8233 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8234 return -EAGAIN;
8235
8236
72fd0718
VZ		 8237 /* TBD: Indicate that "process kill" is in progress to MCP */
8238
8239 /* Clear "unprepared" bit */
8240 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8241 barrier();
8242
8243 /* Make sure all is written to the chip before the reset */
8244 mmiowb();
8245
8246 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8247 * PSWHST, GRC and PSWRD Tetris buffer.
8248 */
c9ee9206 8249 usleep_range(1000, 1000);
72fd0718
VZ		 8250
8251 /* Prepare to chip reset: */
8252 /* MCP */
c9ee9206
VZ		 8253 if (global)
8254 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 8255
8256 /* PXP */
8257 bnx2x_pxp_prep(bp);
8258 barrier();
8259
8260 /* reset the chip */
c9ee9206 8261 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 8262 barrier();
8263
8264 /* Recover after reset: */
8265 /* MCP */
c9ee9206 8266 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 8267 return -EAGAIN;
8268
c9ee9206
VZ		 8269 /* TBD: Add resetting the NO_MCP mode DB here */
8270
72fd0718
VZ		 8271 /* PXP */
8272 bnx2x_pxp_prep(bp);
8273
8274 /* Open the gates #2, #3 and #4 */
8275 bnx2x_set_234_gates(bp, false);
8276
8277 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8278 * reset state, re-enable attentions. */
8279
a2fbb9ea
ET		 8280 return 0;
8281}
8282
c9ee9206 8283int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 8284{
8285 int rc = 0;
c9ee9206 8286 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 8287 u32 load_code;
8288
8289 /* if not going to reset MCP - load "fake" driver to reset HW while
8290 * driver is owner of the HW
8291 */
8292 if (!global && !BP_NOMCP(bp)) {
8293 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0);
8294 if (!load_code) {
8295 BNX2X_ERR("MCP response failure, aborting\n");
8296 rc = -EAGAIN;
8297 goto exit_leader_reset;
8298 }
8299 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
8300 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
8301 BNX2X_ERR("MCP unexpected resp, aborting\n");
8302 rc = -EAGAIN;
8303 goto exit_leader_reset2;
8304 }
8305 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
8306 if (!load_code) {
8307 BNX2X_ERR("MCP response failure, aborting\n");
8308 rc = -EAGAIN;
8309 goto exit_leader_reset2;
8310 }
8311 }
c9ee9206 8312
72fd0718 8313 /* Try to recover after the failure */
c9ee9206 8314 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 8315 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
8316 BP_PATH(bp));
72fd0718 8317 rc = -EAGAIN;
95c6c616 8318 goto exit_leader_reset2;
72fd0718
VZ		 8319 }
8320
c9ee9206
VZ		 8321 /*
8322 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8323 * state.
8324 */
72fd0718 8325 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 8326 if (global)
8327 bnx2x_clear_reset_global(bp);
72fd0718 8328
95c6c616
AE		 8329exit_leader_reset2:
8330 /* unload "fake driver" if it was loaded */
8331 if (!global && !BP_NOMCP(bp)) {
8332 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
8333 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8334 }
72fd0718
VZ		 8335exit_leader_reset:
8336 bp->is_leader = 0;
c9ee9206
VZ		 8337 bnx2x_release_leader_lock(bp);
8338 smp_mb();
72fd0718
VZ		 8339 return rc;
8340}
8341
c9ee9206
VZ		 8342static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8343{
8344 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8345
8346 /* Disconnect this device */
8347 netif_device_detach(bp->dev);
8348
8349 /*
8350 * Block ifup for all function on this engine until "process kill"
8351 * or power cycle.
8352 */
8353 bnx2x_set_reset_in_progress(bp);
8354
8355 /* Shut down the power */
8356 bnx2x_set_power_state(bp, PCI_D3hot);
8357
8358 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8359
8360 smp_mb();
8361}
8362
8363/*
8364 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 8365 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 8366 * will never be called when netif_running(bp->dev) is false.
8367 */
8368static void bnx2x_parity_recover(struct bnx2x *bp)
8369{
c9ee9206 8370 bool global = false;
7a752993 8371 u32 error_recovered, error_unrecovered;
95c6c616 8372 bool is_parity;
c9ee9206 8373
72fd0718
VZ		 8374 DP(NETIF_MSG_HW, "Handling parity\n");
8375 while (1) {
8376 switch (bp->recovery_state) {
8377 case BNX2X_RECOVERY_INIT:
8378 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 8379 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
8380 WARN_ON(!is_parity);
c9ee9206 8381
72fd0718 8382 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 8383 if (bnx2x_trylock_leader_lock(bp)) {
8384 bnx2x_set_reset_in_progress(bp);
8385 /*
8386 * Check if there is a global attention and if
8387 * there was a global attention, set the global
8388 * reset bit.
8389 */
8390
8391 if (global)
8392 bnx2x_set_reset_global(bp);
8393
72fd0718 8394 bp->is_leader = 1;
c9ee9206 8395 }
72fd0718
VZ		 8396
8397 /* Stop the driver */
8398 /* If interface has been removed - break */
8399 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8400 return;
8401
8402 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 8403
c9ee9206
VZ		 8404 /* Ensure "is_leader", MCP command sequence and
8405 * "recovery_state" update values are seen on other
8406 * CPUs.
72fd0718 8407 */
c9ee9206 8408 smp_mb();
72fd0718
VZ		 8409 break;
8410
8411 case BNX2X_RECOVERY_WAIT:
8412 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8413 if (bp->is_leader) {
c9ee9206 8414 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 8415 bool other_load_status =
8416 bnx2x_get_load_status(bp, other_engine);
8417 bool load_status =
8418 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 8419 global = bnx2x_reset_is_global(bp);
8420
8421 /*
8422 * In case of a parity in a global block, let
8423 * the first leader that performs a
8424 * leader_reset() reset the global blocks in
8425 * order to clear global attentions. Otherwise
8426 * the the gates will remain closed for that
8427 * engine.
8428 */
889b9af3
AE		 8429 if (load_status ||
8430 (global && other_load_status)) {
72fd0718
VZ		 8431 /* Wait until all other functions get
8432 * down.
8433 */
7be08a72 8434 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8435 HZ/10);
8436 return;
8437 } else {
8438 /* If all other functions got down -
8439 * try to bring the chip back to
8440 * normal. In any case it's an exit
8441 * point for a leader.
8442 */
c9ee9206
VZ		 8443 if (bnx2x_leader_reset(bp)) {
8444 bnx2x_recovery_failed(bp);
72fd0718
VZ		 8445 return;
8446 }
8447
c9ee9206
VZ		 8448 /* If we are here, means that the
8449 * leader has succeeded and doesn't
8450 * want to be a leader any more. Try
8451 * to continue as a none-leader.
8452 */
8453 break;
72fd0718
VZ		 8454 }
8455 } else { /* non-leader */
c9ee9206 8456 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 8457 /* Try to get a LEADER_LOCK HW lock as
8458 * long as a former leader may have
8459 * been unloaded by the user or
8460 * released a leadership by another
8461 * reason.
8462 */
c9ee9206 8463 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 8464 /* I'm a leader now! Restart a
8465 * switch case.
8466 */
8467 bp->is_leader = 1;
8468 break;
8469 }
8470
7be08a72 8471 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8472 HZ/10);
8473 return;
8474
c9ee9206
VZ		 8475 } else {
8476 /*
8477 * If there was a global attention, wait
8478 * for it to be cleared.
8479 */
8480 if (bnx2x_reset_is_global(bp)) {
8481 schedule_delayed_work(
7be08a72
AE		 8482 &bp->sp_rtnl_task,
8483 HZ/10);
c9ee9206
VZ		 8484 return;
8485 }
8486
7a752993
AE		 8487 error_recovered =
8488 bp->eth_stats.recoverable_error;
8489 error_unrecovered =
8490 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 8491 bp->recovery_state =
8492 BNX2X_RECOVERY_NIC_LOADING;
8493 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 8494 error_unrecovered++;
95c6c616 8495 netdev_err(bp->dev,
51c1a580 8496 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 8497 /* Disconnect this device */
8498 netif_device_detach(bp->dev);
8499 /* Shut down the power */
8500 bnx2x_set_power_state(
8501 bp, PCI_D3hot);
8502 smp_mb();
8503 } else {
c9ee9206
VZ		 8504 bp->recovery_state =
8505 BNX2X_RECOVERY_DONE;
7a752993 8506 error_recovered++;
c9ee9206
VZ		 8507 smp_mb();
8508 }
7a752993
AE		 8509 bp->eth_stats.recoverable_error =
8510 error_recovered;
8511 bp->eth_stats.unrecoverable_error =
8512 error_unrecovered;
c9ee9206 8513
72fd0718
VZ		 8514 return;
8515 }
8516 }
8517 default:
8518 return;
8519 }
8520 }
8521}
8522
56ad3152
MS		 8523static int bnx2x_close(struct net_device *dev);
8524
72fd0718
VZ		 8525/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8526 * scheduled on a general queue in order to prevent a dead lock.
8527 */
7be08a72 8528static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 8529{
7be08a72 8530 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 8531
8532 rtnl_lock();
8533
8534 if (!netif_running(bp->dev))
7be08a72
AE		 8535 goto sp_rtnl_exit;
8536
8537 /* if stop on error is defined no recovery flows should be executed */
8538#ifdef BNX2X_STOP_ON_ERROR
51c1a580 8539 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
7be08a72 8540 "you will need to reboot when done\n");
b1fb8740 8541 goto sp_rtnl_not_reset;
7be08a72 8542#endif
34f80b04 8543
7be08a72
AE		 8544 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8545 /*
b1fb8740
VZ		 8546 * Clear all pending SP commands as we are going to reset the
8547 * function anyway.
7be08a72 8548 */
b1fb8740
VZ		 8549 bp->sp_rtnl_state = 0;
8550 smp_mb();
8551
72fd0718 8552 bnx2x_parity_recover(bp);
b1fb8740
VZ		 8553
8554 goto sp_rtnl_exit;
8555 }
8556
8557 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8558 /*
8559 * Clear all pending SP commands as we are going to reset the
8560 * function anyway.
8561 */
8562 bp->sp_rtnl_state = 0;
8563 smp_mb();
8564
72fd0718
VZ		 8565 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8566 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740
VZ		 8567
8568 goto sp_rtnl_exit;
72fd0718 8569 }
b1fb8740
VZ		 8570#ifdef BNX2X_STOP_ON_ERROR
8571sp_rtnl_not_reset:
8572#endif
8573 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8574 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
34f80b04 8575
8304859a
AE		 8576 /*
8577 * in case of fan failure we need to reset id if the "stop on error"
8578 * debug flag is set, since we trying to prevent permanent overheating
8579 * damage
8580 */
8581 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 8582 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 8583 netif_device_detach(bp->dev);
8584 bnx2x_close(bp->dev);
8585 }
8586
7be08a72 8587sp_rtnl_exit:
34f80b04
EG		 8588 rtnl_unlock();
8589}
8590
a2fbb9ea
ET		 8591/* end of nic load/unload */
8592
3deb8167
YR		 8593static void bnx2x_period_task(struct work_struct *work)
8594{
8595 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8596
8597 if (!netif_running(bp->dev))
8598 goto period_task_exit;
8599
8600 if (CHIP_REV_IS_SLOW(bp)) {
8601 BNX2X_ERR("period task called on emulation, ignoring\n");
8602 goto period_task_exit;
8603 }
8604
8605 bnx2x_acquire_phy_lock(bp);
8606 /*
8607 * The barrier is needed to ensure the ordering between the writing to
8608 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8609 * the reading here.
8610 */
8611 smp_mb();
8612 if (bp->port.pmf) {
8613 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8614
8615 /* Re-queue task in 1 sec */
8616 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8617 }
8618
8619 bnx2x_release_phy_lock(bp);
8620period_task_exit:
8621 return;
8622}
8623
a2fbb9ea
ET		 8624/*
8625 * Init service functions
8626 */
8627
8d96286a 8628static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 8629{
8630 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8631 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8632 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 8633}
8634
f2e0899f 8635static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 8636{
f2e0899f 8637 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 8638
8639 /* Flush all outstanding writes */
8640 mmiowb();
8641
8642 /* Pretend to be function 0 */
8643 REG_WR(bp, reg, 0);
f2e0899f 8644 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 8645
8646 /* From now we are in the "like-E1" mode */
8647 bnx2x_int_disable(bp);
8648
8649 /* Flush all outstanding writes */
8650 mmiowb();
8651
f2e0899f
DK		 8652 /* Restore the original function */
8653 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8654 REG_RD(bp, reg);
f1ef27ef
EG		 8655}
8656
f2e0899f 8657static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 8658{
f2e0899f 8659 if (CHIP_IS_E1(bp))
f1ef27ef 8660 bnx2x_int_disable(bp);
f2e0899f
DK		 8661 else
8662 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 8663}
8664
452427b0 8665static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp)
34f80b04 8666{
452427b0
YM		 8667 u32 val, base_addr, offset, mask, reset_reg;
8668 bool mac_stopped = false;
8669 u8 port = BP_PORT(bp);
34f80b04 8670
452427b0 8671 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 8672
452427b0
YM		 8673 if (!CHIP_IS_E3(bp)) {
8674 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
8675 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
8676 if ((mask & reset_reg) && val) {
8677 u32 wb_data[2];
8678 BNX2X_DEV_INFO("Disable bmac Rx\n");
8679 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
8680 : NIG_REG_INGRESS_BMAC0_MEM;
8681 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
8682 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 8683
452427b0
YM		 8684 /*
8685 * use rd/wr since we cannot use dmae. This is safe
8686 * since MCP won't access the bus due to the request
8687 * to unload, and no function on the path can be
8688 * loaded at this time.
8689 */
8690 wb_data[0] = REG_RD(bp, base_addr + offset);
8691 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
8692 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
8693 REG_WR(bp, base_addr + offset, wb_data[0]);
8694 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
8695
8696 }
8697 BNX2X_DEV_INFO("Disable emac Rx\n");
8698 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
8699
8700 mac_stopped = true;
8701 } else {
8702 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
8703 BNX2X_DEV_INFO("Disable xmac Rx\n");
8704 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
8705 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
8706 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
8707 val & ~(1 << 1));
8708 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
8709 val | (1 << 1));
8710 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
8711 mac_stopped = true;
8712 }
8713 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
8714 if (mask & reset_reg) {
8715 BNX2X_DEV_INFO("Disable umac Rx\n");
8716 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
8717 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
8718 mac_stopped = true;
8719 }
8720 }
8721
8722 if (mac_stopped)
8723 msleep(20);
8724
8725}
8726
8727#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
8728#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
8729#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
8730#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
8731
8732static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port,
8733 u8 inc)
8734{
8735 u16 rcq, bd;
8736 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
8737
8738 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
8739 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
8740
8741 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
8742 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
8743
8744 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
8745 port, bd, rcq);
8746}
8747
8748static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp)
8749{
8750 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8751 if (!rc) {
8752 BNX2X_ERR("MCP response failure, aborting\n");
8753 return -EBUSY;
8754 }
8755
8756 return 0;
8757}
8758
8759static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp)
8760{
8761 struct bnx2x_prev_path_list *tmp_list;
8762 int rc = false;
8763
8764 if (down_trylock(&bnx2x_prev_sem))
8765 return false;
8766
8767 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
8768 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
8769 bp->pdev->bus->number == tmp_list->bus &&
8770 BP_PATH(bp) == tmp_list->path) {
8771 rc = true;
8772 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
8773 BP_PATH(bp));
8774 break;
8775 }
8776 }
8777
8778 up(&bnx2x_prev_sem);
8779
8780 return rc;
8781}
8782
8783static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
8784{
8785 struct bnx2x_prev_path_list *tmp_list;
8786 int rc;
8787
8788 tmp_list = (struct bnx2x_prev_path_list *)
8789 kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
8790 if (!tmp_list) {
8791 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
8792 return -ENOMEM;
8793 }
8794
8795 tmp_list->bus = bp->pdev->bus->number;
8796 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
8797 tmp_list->path = BP_PATH(bp);
8798
8799 rc = down_interruptible(&bnx2x_prev_sem);
8800 if (rc) {
8801 BNX2X_ERR("Received %d when tried to take lock\n", rc);
8802 kfree(tmp_list);
8803 } else {
8804 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
8805 BP_PATH(bp));
8806 list_add(&tmp_list->list, &bnx2x_prev_list);
8807 up(&bnx2x_prev_sem);
8808 }
8809
8810 return rc;
8811}
8812
8813static bool __devinit bnx2x_can_flr(struct bnx2x *bp)
8814{
8815 int pos;
8816 u32 cap;
8817 struct pci_dev *dev = bp->pdev;
8818
8819 pos = pci_pcie_cap(dev);
8820 if (!pos)
8821 return false;
8822
8823 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
8824 if (!(cap & PCI_EXP_DEVCAP_FLR))
8825 return false;
8826
8827 return true;
8828}
8829
8830static int __devinit bnx2x_do_flr(struct bnx2x *bp)
8831{
8832 int i, pos;
8833 u16 status;
8834 struct pci_dev *dev = bp->pdev;
8835
8836 /* probe the capability first */
8837 if (bnx2x_can_flr(bp))
8838 return -ENOTTY;
8839
8840 pos = pci_pcie_cap(dev);
8841 if (!pos)
8842 return -ENOTTY;
8843
8844 /* Wait for Transaction Pending bit clean */
8845 for (i = 0; i < 4; i++) {
8846 if (i)
8847 msleep((1 << (i - 1)) * 100);
8848
8849 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
8850 if (!(status & PCI_EXP_DEVSTA_TRPND))
8851 goto clear;
8852 }
8853
8854 dev_err(&dev->dev,
8855 "transaction is not cleared; proceeding with reset anyway\n");
8856
8857clear:
8858 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
8859 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
8860 bp->common.bc_ver);
8861 return -EINVAL;
8862 }
8863
8864 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
8865
8866 return 0;
8867}
8868
8869static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
8870{
8871 int rc;
8872
8873 BNX2X_DEV_INFO("Uncommon unload Flow\n");
8874
8875 /* Test if previous unload process was already finished for this path */
8876 if (bnx2x_prev_is_path_marked(bp))
8877 return bnx2x_prev_mcp_done(bp);
8878
8879 /* If function has FLR capabilities, and existing FW version matches
8880 * the one required, then FLR will be sufficient to clean any residue
8881 * left by previous driver
8882 */
8883 if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp))
8884 return bnx2x_do_flr(bp);
8885
8886 /* Close the MCP request, return failure*/
8887 rc = bnx2x_prev_mcp_done(bp);
8888 if (!rc)
8889 rc = BNX2X_PREV_WAIT_NEEDED;
8890
8891 return rc;
8892}
8893
8894static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp)
8895{
8896 u32 reset_reg, tmp_reg = 0, rc;
8897 /* It is possible a previous function received 'common' answer,
8898 * but hasn't loaded yet, therefore creating a scenario of
8899 * multiple functions receiving 'common' on the same path.
8900 */
8901 BNX2X_DEV_INFO("Common unload Flow\n");
8902
8903 if (bnx2x_prev_is_path_marked(bp))
8904 return bnx2x_prev_mcp_done(bp);
8905
8906 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
8907
8908 /* Reset should be performed after BRB is emptied */
8909 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
8910 u32 timer_count = 1000;
8911 bool prev_undi = false;
8912
8913 /* Close the MAC Rx to prevent BRB from filling up */
8914 bnx2x_prev_unload_close_mac(bp);
8915
8916 /* Check if the UNDI driver was previously loaded
34f80b04
EG		 8917 * UNDI driver initializes CID offset for normal bell to 0x7
8918 */
452427b0
YM		 8919 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
8920 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
8921 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8922 if (tmp_reg == 0x7) {
8923 BNX2X_DEV_INFO("UNDI previously loaded\n");
8924 prev_undi = true;
8925 /* clear the UNDI indication */
8926 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
34f80b04 8927 }
452427b0
YM		 8928 }
8929 /* wait until BRB is empty */
8930 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
8931 while (timer_count) {
8932 u32 prev_brb = tmp_reg;
34f80b04 8933
452427b0
YM		 8934 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
8935 if (!tmp_reg)
8936 break;
619c5cb6 8937
452427b0 8938 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 8939
452427b0
YM		 8940 /* reset timer as long as BRB actually gets emptied */
8941 if (prev_brb > tmp_reg)
8942 timer_count = 1000;
8943 else
8944 timer_count--;
da5a662a 8945
452427b0
YM		 8946 /* If UNDI resides in memory, manually increment it */
8947 if (prev_undi)
8948 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
da5a662a 8949
452427b0 8950 udelay(10);
7a06a122 8951 }
452427b0
YM		 8952
8953 if (!timer_count)
8954 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
8955
34f80b04 8956 }
f16da43b 8957
452427b0
YM		 8958 /* No packets are in the pipeline, path is ready for reset */
8959 bnx2x_reset_common(bp);
8960
8961 rc = bnx2x_prev_mark_path(bp);
8962 if (rc) {
8963 bnx2x_prev_mcp_done(bp);
8964 return rc;
8965 }
8966
8967 return bnx2x_prev_mcp_done(bp);
8968}
8969
8970static int __devinit bnx2x_prev_unload(struct bnx2x *bp)
8971{
8972 int time_counter = 10;
8973 u32 rc, fw, hw_lock_reg, hw_lock_val;
8974 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
8975
8976 /* Release previously held locks */
8977 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
8978 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
8979 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
8980
8981 hw_lock_val = (REG_RD(bp, hw_lock_reg));
8982 if (hw_lock_val) {
8983 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
8984 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
8985 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
8986 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
8987 }
8988
8989 BNX2X_DEV_INFO("Release Previously held hw lock\n");
8990 REG_WR(bp, hw_lock_reg, 0xffffffff);
8991 } else
8992 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
8993
8994 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
8995 BNX2X_DEV_INFO("Release previously held alr\n");
8996 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
8997 }
8998
8999
9000 do {
9001 /* Lock MCP using an unload request */
9002 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9003 if (!fw) {
9004 BNX2X_ERR("MCP response failure, aborting\n");
9005 rc = -EBUSY;
9006 break;
9007 }
9008
9009 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9010 rc = bnx2x_prev_unload_common(bp);
9011 break;
9012 }
9013
9014 /* non-common reply from MCP night require looping */
9015 rc = bnx2x_prev_unload_uncommon(bp);
9016 if (rc != BNX2X_PREV_WAIT_NEEDED)
9017 break;
9018
9019 msleep(20);
9020 } while (--time_counter);
9021
9022 if (!time_counter || rc) {
9023 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9024 rc = -EBUSY;
9025 }
9026
9027 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9028
9029 return rc;
34f80b04
EG		 9030}
9031
9032static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9033{
1d187b34 9034 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 9035 u16 pmc;
34f80b04
EG		 9036
9037 /* Get the chip revision id and number. */
9038 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9039 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9040 id = ((val & 0xffff) << 16);
9041 val = REG_RD(bp, MISC_REG_CHIP_REV);
9042 id |= ((val & 0xf) << 12);
9043 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9044 id |= ((val & 0xff) << 4);
5a40e08e 9045 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 9046 id |= (val & 0xf);
9047 bp->common.chip_id = id;
523224a3 9048
7e8e02df
BW		 9049 /* force 57811 according to MISC register */
9050 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9051 if (CHIP_IS_57810(bp))
9052 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9053 (bp->common.chip_id & 0x0000FFFF);
9054 else if (CHIP_IS_57810_MF(bp))
9055 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9056 (bp->common.chip_id & 0x0000FFFF);
9057 bp->common.chip_id |= 0x1;
9058 }
9059
523224a3
DK		 9060 /* Set doorbell size */
9061 bp->db_size = (1 << BNX2X_DB_SHIFT);
9062
619c5cb6 9063 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 9064 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9065 if ((val & 1) == 0)
9066 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9067 else
9068 val = (val >> 1) & 1;
9069 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9070 "2_PORT_MODE");
9071 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9072 CHIP_2_PORT_MODE;
9073
9074 if (CHIP_MODE_IS_4_PORT(bp))
9075 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
9076 else
9077 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
9078 } else {
9079 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9080 bp->pfid = bp->pf_num; /* 0..7 */
9081 }
9082
51c1a580
MS		 9083 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9084
f2e0899f
DK		 9085 bp->link_params.chip_id = bp->common.chip_id;
9086 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 9087
1c06328c
EG		 9088 val = (REG_RD(bp, 0x2874) & 0x55);
9089 if ((bp->common.chip_id & 0x1) ||
9090 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9091 bp->flags |= ONE_PORT_FLAG;
9092 BNX2X_DEV_INFO("single port device\n");
9093 }
9094
34f80b04 9095 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 9096 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 9097 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9098 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9099 bp->common.flash_size, bp->common.flash_size);
9100
1b6e2ceb
DK		 9101 bnx2x_init_shmem(bp);
9102
619c5cb6
VZ		 9103
9104
f2e0899f
DK		 9105 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9106 MISC_REG_GENERIC_CR_1 :
9107 MISC_REG_GENERIC_CR_0));
1b6e2ceb 9108
34f80b04 9109 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 9110 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 9111 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9112 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 9113
f2e0899f 9114 if (!bp->common.shmem_base) {
34f80b04
EG		 9115 BNX2X_DEV_INFO("MCP not active\n");
9116 bp->flags |= NO_MCP_FLAG;
9117 return;
9118 }
9119
34f80b04 9120 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 9121 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 9122
9123 bp->link_params.hw_led_mode = ((bp->common.hw_config &
9124 SHARED_HW_CFG_LED_MODE_MASK) >>
9125 SHARED_HW_CFG_LED_MODE_SHIFT);
9126
c2c8b03e
EG		 9127 bp->link_params.feature_config_flags = 0;
9128 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9129 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9130 bp->link_params.feature_config_flags |=
9131 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9132 else
9133 bp->link_params.feature_config_flags &=
9134 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9135
34f80b04
EG		 9136 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9137 bp->common.bc_ver = val;
9138 BNX2X_DEV_INFO("bc_ver %X\n", val);
9139 if (val < BNX2X_BC_VER) {
9140 /* for now only warn
9141 * later we might need to enforce this */
51c1a580
MS		 9142 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9143 BNX2X_BC_VER, val);
34f80b04 9144 }
4d295db0 9145 bp->link_params.feature_config_flags |=
a22f0788 9146 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 9147 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9148
a22f0788
YR		 9149 bp->link_params.feature_config_flags |=
9150 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9151 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 9152
85242eea
YR		 9153 bp->link_params.feature_config_flags |=
9154 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9155 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
0e898dd7
BW		 9156 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9157 BC_SUPPORTS_PFC_STATS : 0;
85242eea 9158
1d187b34
BW		 9159 boot_mode = SHMEM_RD(bp,
9160 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9161 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9162 switch (boot_mode) {
9163 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9164 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9165 break;
9166 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9167 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9168 break;
9169 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9170 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9171 break;
9172 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9173 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9174 break;
9175 }
9176
f9a3ebbe
DK		 9177 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9178 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9179
72ce58c3 9180 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 9181 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 9182
9183 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9184 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9185 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9186 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9187
cdaa7cb8
VZ		 9188 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9189 val, val2, val3, val4);
34f80b04
EG		 9190}
9191
f2e0899f
DK		 9192#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9193#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9194
9195static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9196{
9197 int pfid = BP_FUNC(bp);
f2e0899f
DK		 9198 int igu_sb_id;
9199 u32 val;
6383c0b3 9200 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 9201
9202 bp->igu_base_sb = 0xff;
f2e0899f 9203 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 9204 int vn = BP_VN(bp);
6383c0b3 9205 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 9206 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9207 FP_SB_MAX_E1x;
9208
9209 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9210 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9211
9212 return;
9213 }
9214
9215 /* IGU in normal mode - read CAM */
9216 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9217 igu_sb_id++) {
9218 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9219 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9220 continue;
9221 fid = IGU_FID(val);
9222 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9223 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9224 continue;
9225 if (IGU_VEC(val) == 0)
9226 /* default status block */
9227 bp->igu_dsb_id = igu_sb_id;
9228 else {
9229 if (bp->igu_base_sb == 0xff)
9230 bp->igu_base_sb = igu_sb_id;
6383c0b3 9231 igu_sb_cnt++;
f2e0899f
DK		 9232 }
9233 }
9234 }
619c5cb6 9235
6383c0b3
AE		 9236#ifdef CONFIG_PCI_MSI
9237 /*
9238 * It's expected that number of CAM entries for this functions is equal
9239 * to the number evaluated based on the MSI-X table size. We want a
9240 * harsh warning if these values are different!
619c5cb6 9241 */
6383c0b3
AE		 9242 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
9243#endif
619c5cb6 9244
6383c0b3 9245 if (igu_sb_cnt == 0)
f2e0899f
DK		 9246 BNX2X_ERR("CAM configuration error\n");
9247}
9248
34f80b04
EG		 9249static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9250 u32 switch_cfg)
a2fbb9ea 9251{
a22f0788
YR		 9252 int cfg_size = 0, idx, port = BP_PORT(bp);
9253
9254 /* Aggregation of supported attributes of all external phys */
9255 bp->port.supported[0] = 0;
9256 bp->port.supported[1] = 0;
b7737c9b
YR		 9257 switch (bp->link_params.num_phys) {
9258 case 1:
a22f0788
YR		 9259 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9260 cfg_size = 1;
9261 break;
b7737c9b 9262 case 2:
a22f0788
YR		 9263 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9264 cfg_size = 1;
9265 break;
9266 case 3:
9267 if (bp->link_params.multi_phy_config &
9268 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
9269 bp->port.supported[1] =
9270 bp->link_params.phy[EXT_PHY1].supported;
9271 bp->port.supported[0] =
9272 bp->link_params.phy[EXT_PHY2].supported;
9273 } else {
9274 bp->port.supported[0] =
9275 bp->link_params.phy[EXT_PHY1].supported;
9276 bp->port.supported[1] =
9277 bp->link_params.phy[EXT_PHY2].supported;
9278 }
9279 cfg_size = 2;
9280 break;
b7737c9b 9281 }
a2fbb9ea 9282
a22f0788 9283 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 9284 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 9285 SHMEM_RD(bp,
a22f0788
YR		 9286 dev_info.port_hw_config[port].external_phy_config),
9287 SHMEM_RD(bp,
9288 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 9289 return;
f85582f8 9290 }
a2fbb9ea 9291
619c5cb6
VZ		 9292 if (CHIP_IS_E3(bp))
9293 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9294 else {
9295 switch (switch_cfg) {
9296 case SWITCH_CFG_1G:
9297 bp->port.phy_addr = REG_RD(
9298 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9299 break;
9300 case SWITCH_CFG_10G:
9301 bp->port.phy_addr = REG_RD(
9302 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9303 break;
9304 default:
9305 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9306 bp->port.link_config[0]);
9307 return;
9308 }
a2fbb9ea 9309 }
619c5cb6 9310 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 9311 /* mask what we support according to speed_cap_mask per configuration */
9312 for (idx = 0; idx < cfg_size; idx++) {
9313 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9314 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 9315 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 9316
a22f0788 9317 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9318 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 9319 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 9320
a22f0788 9321 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9322 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 9323 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 9324
a22f0788 9325 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9326 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 9327 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 9328
a22f0788 9329 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9330 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 9331 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 9332 SUPPORTED_1000baseT_Full);
a2fbb9ea 9333
a22f0788 9334 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9335 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 9336 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 9337
a22f0788 9338 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9339 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 9340 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9341
9342 }
a2fbb9ea 9343
a22f0788
YR		 9344 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9345 bp->port.supported[1]);
a2fbb9ea
ET		 9346}
9347
34f80b04 9348static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 9349{
a22f0788
YR		 9350 u32 link_config, idx, cfg_size = 0;
9351 bp->port.advertising[0] = 0;
9352 bp->port.advertising[1] = 0;
9353 switch (bp->link_params.num_phys) {
9354 case 1:
9355 case 2:
9356 cfg_size = 1;
9357 break;
9358 case 3:
9359 cfg_size = 2;
9360 break;
9361 }
9362 for (idx = 0; idx < cfg_size; idx++) {
9363 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9364 link_config = bp->port.link_config[idx];
9365 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 9366 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 9367 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9368 bp->link_params.req_line_speed[idx] =
9369 SPEED_AUTO_NEG;
9370 bp->port.advertising[idx] |=
9371 bp->port.supported[idx];
10bd1f24
MY		 9372 if (bp->link_params.phy[EXT_PHY1].type ==
9373 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9374 bp->port.advertising[idx] |=
9375 (SUPPORTED_100baseT_Half |
9376 SUPPORTED_100baseT_Full);
f85582f8
DK		 9377 } else {
9378 /* force 10G, no AN */
a22f0788
YR		 9379 bp->link_params.req_line_speed[idx] =
9380 SPEED_10000;
9381 bp->port.advertising[idx] |=
9382 (ADVERTISED_10000baseT_Full |
f85582f8 9383 ADVERTISED_FIBRE);
a22f0788 9384 continue;
f85582f8
DK		 9385 }
9386 break;
a2fbb9ea 9387
f85582f8 9388 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 9389 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9390 bp->link_params.req_line_speed[idx] =
9391 SPEED_10;
9392 bp->port.advertising[idx] |=
9393 (ADVERTISED_10baseT_Full |
f85582f8
DK		 9394 ADVERTISED_TP);
9395 } else {
51c1a580 9396 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 9397 link_config,
a22f0788 9398 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9399 return;
9400 }
9401 break;
a2fbb9ea 9402
f85582f8 9403 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 9404 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9405 bp->link_params.req_line_speed[idx] =
9406 SPEED_10;
9407 bp->link_params.req_duplex[idx] =
9408 DUPLEX_HALF;
9409 bp->port.advertising[idx] |=
9410 (ADVERTISED_10baseT_Half |
f85582f8
DK		 9411 ADVERTISED_TP);
9412 } else {
51c1a580 9413 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 9414 link_config,
9415 bp->link_params.speed_cap_mask[idx]);
9416 return;
9417 }
9418 break;
a2fbb9ea 9419
f85582f8
DK		 9420 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9421 if (bp->port.supported[idx] &
9422 SUPPORTED_100baseT_Full) {
a22f0788
YR		 9423 bp->link_params.req_line_speed[idx] =
9424 SPEED_100;
9425 bp->port.advertising[idx] |=
9426 (ADVERTISED_100baseT_Full |
f85582f8
DK		 9427 ADVERTISED_TP);
9428 } else {
51c1a580 9429 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 9430 link_config,
9431 bp->link_params.speed_cap_mask[idx]);
9432 return;
9433 }
9434 break;
a2fbb9ea 9435
f85582f8
DK		 9436 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9437 if (bp->port.supported[idx] &
9438 SUPPORTED_100baseT_Half) {
9439 bp->link_params.req_line_speed[idx] =
9440 SPEED_100;
9441 bp->link_params.req_duplex[idx] =
9442 DUPLEX_HALF;
a22f0788
YR		 9443 bp->port.advertising[idx] |=
9444 (ADVERTISED_100baseT_Half |
f85582f8
DK		 9445 ADVERTISED_TP);
9446 } else {
51c1a580 9447 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 9448 link_config,
9449 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9450 return;
9451 }
9452 break;
a2fbb9ea 9453
f85582f8 9454 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 9455 if (bp->port.supported[idx] &
9456 SUPPORTED_1000baseT_Full) {
9457 bp->link_params.req_line_speed[idx] =
9458 SPEED_1000;
9459 bp->port.advertising[idx] |=
9460 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 9461 ADVERTISED_TP);
9462 } else {
51c1a580 9463 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 9464 link_config,
9465 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9466 return;
9467 }
9468 break;
a2fbb9ea 9469
f85582f8 9470 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 9471 if (bp->port.supported[idx] &
9472 SUPPORTED_2500baseX_Full) {
9473 bp->link_params.req_line_speed[idx] =
9474 SPEED_2500;
9475 bp->port.advertising[idx] |=
9476 (ADVERTISED_2500baseX_Full |
34f80b04 9477 ADVERTISED_TP);
f85582f8 9478 } else {
51c1a580 9479 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 9480 link_config,
f85582f8
DK		 9481 bp->link_params.speed_cap_mask[idx]);
9482 return;
9483 }
9484 break;
a2fbb9ea 9485
f85582f8 9486 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 9487 if (bp->port.supported[idx] &
9488 SUPPORTED_10000baseT_Full) {
9489 bp->link_params.req_line_speed[idx] =
9490 SPEED_10000;
9491 bp->port.advertising[idx] |=
9492 (ADVERTISED_10000baseT_Full |
34f80b04 9493 ADVERTISED_FIBRE);
f85582f8 9494 } else {
51c1a580 9495 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 9496 link_config,
f85582f8
DK		 9497 bp->link_params.speed_cap_mask[idx]);
9498 return;
9499 }
9500 break;
3c9ada22
YR		 9501 case PORT_FEATURE_LINK_SPEED_20G:
9502 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 9503
3c9ada22 9504 break;
f85582f8 9505 default:
51c1a580 9506 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 9507 link_config);
f85582f8
DK		 9508 bp->link_params.req_line_speed[idx] =
9509 SPEED_AUTO_NEG;
9510 bp->port.advertising[idx] =
9511 bp->port.supported[idx];
9512 break;
9513 }
a2fbb9ea 9514
a22f0788 9515 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 9516 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 9517 if ((bp->link_params.req_flow_ctrl[idx] ==
9518 BNX2X_FLOW_CTRL_AUTO) &&
9519 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9520 bp->link_params.req_flow_ctrl[idx] =
9521 BNX2X_FLOW_CTRL_NONE;
9522 }
a2fbb9ea 9523
51c1a580 9524 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 9525 bp->link_params.req_line_speed[idx],
9526 bp->link_params.req_duplex[idx],
9527 bp->link_params.req_flow_ctrl[idx],
9528 bp->port.advertising[idx]);
9529 }
a2fbb9ea
ET		 9530}
9531
e665bfda
MC		 9532static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9533{
9534 mac_hi = cpu_to_be16(mac_hi);
9535 mac_lo = cpu_to_be32(mac_lo);
9536 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9537 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9538}
9539
34f80b04 9540static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 9541{
34f80b04 9542 int port = BP_PORT(bp);
589abe3a 9543 u32 config;
6f38ad93 9544 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 9545
c18487ee 9546 bp->link_params.bp = bp;
34f80b04 9547 bp->link_params.port = port;
c18487ee 9548
c18487ee 9549 bp->link_params.lane_config =
a2fbb9ea 9550 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 9551
a22f0788 9552 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 9553 SHMEM_RD(bp,
9554 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 9555 bp->link_params.speed_cap_mask[1] =
9556 SHMEM_RD(bp,
9557 dev_info.port_hw_config[port].speed_capability_mask2);
9558 bp->port.link_config[0] =
a2fbb9ea
ET		 9559 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9560
a22f0788
YR		 9561 bp->port.link_config[1] =
9562 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 9563
a22f0788
YR		 9564 bp->link_params.multi_phy_config =
9565 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 9566 /* If the device is capable of WoL, set the default state according
9567 * to the HW
9568 */
4d295db0 9569 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 9570 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9571 (config & PORT_FEATURE_WOL_ENABLED));
9572
51c1a580 9573 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 9574 bp->link_params.lane_config,
a22f0788
YR		 9575 bp->link_params.speed_cap_mask[0],
9576 bp->port.link_config[0]);
a2fbb9ea 9577
a22f0788 9578 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 9579 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 9580 bnx2x_phy_probe(&bp->link_params);
c18487ee 9581 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 9582
9583 bnx2x_link_settings_requested(bp);
9584
01cd4528
EG		 9585 /*
9586 * If connected directly, work with the internal PHY, otherwise, work
9587 * with the external PHY
9588 */
b7737c9b
YR		 9589 ext_phy_config =
9590 SHMEM_RD(bp,
9591 dev_info.port_hw_config[port].external_phy_config);
9592 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 9593 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 9594 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 9595
9596 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9597 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9598 bp->mdio.prtad =
b7737c9b 9599 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 9600
9601 /*
9602 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9603 * In MF mode, it is set to cover self test cases
9604 */
9605 if (IS_MF(bp))
9606 bp->port.need_hw_lock = 1;
9607 else
9608 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9609 bp->common.shmem_base,
9610 bp->common.shmem2_base);
0793f83f 9611}
01cd4528 9612
b306f5ed 9613void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 9614{
9e62e912 9615 u32 no_flags = NO_ISCSI_FLAG;
7185bb33 9616#ifdef BCM_CNIC
bf61ee14 9617 int port = BP_PORT(bp);
bf61ee14 9618
2ba45142 9619 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 9620 drv_lic_key[port].max_iscsi_conn);
2ba45142 9621
b306f5ed 9622 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 9623 bp->cnic_eth_dev.max_iscsi_conn =
9624 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9625 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9626
b306f5ed
DK		 9627 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
9628 bp->cnic_eth_dev.max_iscsi_conn);
9629
9630 /*
9631 * If maximum allowed number of connections is zero -
9632 * disable the feature.
9633 */
9634 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 9635 bp->flags |= no_flags;
7185bb33 9636#else
9e62e912 9637 bp->flags |= no_flags;
7185bb33 9638#endif
b306f5ed
DK		 9639}
9640
9e62e912
DK		 9641#ifdef BCM_CNIC
9642static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9643{
9644 /* Port info */
9645 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9646 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
9647 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9648 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
9649
9650 /* Node info */
9651 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9652 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
9653 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9654 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
9655}
9656#endif
b306f5ed
DK		 9657static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
9658{
7185bb33 9659#ifdef BCM_CNIC
b306f5ed
DK		 9660 int port = BP_PORT(bp);
9661 int func = BP_ABS_FUNC(bp);
9662
9663 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9664 drv_lic_key[port].max_fcoe_conn);
9665
9666 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 9667 bp->cnic_eth_dev.max_fcoe_conn =
9668 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9669 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9670
bf61ee14
VZ		 9671 /* Read the WWN: */
9672 if (!IS_MF(bp)) {
9673 /* Port info */
9674 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9675 SHMEM_RD(bp,
9676 dev_info.port_hw_config[port].
9677 fcoe_wwn_port_name_upper);
9678 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9679 SHMEM_RD(bp,
9680 dev_info.port_hw_config[port].
9681 fcoe_wwn_port_name_lower);
9682
9683 /* Node info */
9684 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9685 SHMEM_RD(bp,
9686 dev_info.port_hw_config[port].
9687 fcoe_wwn_node_name_upper);
9688 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9689 SHMEM_RD(bp,
9690 dev_info.port_hw_config[port].
9691 fcoe_wwn_node_name_lower);
9692 } else if (!IS_MF_SD(bp)) {
9693 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9694
9695 /*
9696 * Read the WWN info only if the FCoE feature is enabled for
9697 * this function.
9698 */
9e62e912
DK		 9699 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
9700 bnx2x_get_ext_wwn_info(bp, func);
9701
9702 } else if (IS_MF_FCOE_SD(bp))
9703 bnx2x_get_ext_wwn_info(bp, func);
bf61ee14 9704
b306f5ed 9705 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 9706
bf61ee14
VZ		 9707 /*
9708 * If maximum allowed number of connections is zero -
2ba45142
VZ		 9709 * disable the feature.
9710 */
2ba45142
VZ		 9711 if (!bp->cnic_eth_dev.max_fcoe_conn)
9712 bp->flags |= NO_FCOE_FLAG;
7185bb33
DK		 9713#else
9714 bp->flags |= NO_FCOE_FLAG;
9715#endif
2ba45142 9716}
b306f5ed
DK		 9717
9718static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9719{
9720 /*
9721 * iSCSI may be dynamically disabled but reading
9722 * info here we will decrease memory usage by driver
9723 * if the feature is disabled for good
9724 */
9725 bnx2x_get_iscsi_info(bp);
9726 bnx2x_get_fcoe_info(bp);
9727}
2ba45142 9728
0793f83f
DK		 9729static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9730{
9731 u32 val, val2;
9732 int func = BP_ABS_FUNC(bp);
9733 int port = BP_PORT(bp);
2ba45142
VZ		 9734#ifdef BCM_CNIC
9735 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9736 u8 *fip_mac = bp->fip_mac;
9737#endif
0793f83f 9738
619c5cb6
VZ		 9739 /* Zero primary MAC configuration */
9740 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9741
0793f83f
DK		 9742 if (BP_NOMCP(bp)) {
9743 BNX2X_ERROR("warning: random MAC workaround active\n");
7ce5d222 9744 eth_hw_addr_random(bp->dev);
0793f83f
DK		 9745 } else if (IS_MF(bp)) {
9746 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9747 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9748 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9749 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9750 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 9751
9752#ifdef BCM_CNIC
614c76df
DK		 9753 /*
9754 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 9755 * FCoE MAC then the appropriate feature should be disabled.
9e62e912
DK		 9756 *
9757 * In non SD mode features configuration comes from
9758 * struct func_ext_config.
2ba45142 9759 */
9e62e912 9760 if (!IS_MF_SD(bp)) {
0793f83f
DK		 9761 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9762 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9763 val2 = MF_CFG_RD(bp, func_ext_config[func].
9764 iscsi_mac_addr_upper);
9765 val = MF_CFG_RD(bp, func_ext_config[func].
9766 iscsi_mac_addr_lower);
2ba45142 9767 bnx2x_set_mac_buf(iscsi_mac, val, val2);
0f9dad10
JP		 9768 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9769 iscsi_mac);
2ba45142
VZ		 9770 } else
9771 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9772
9773 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9774 val2 = MF_CFG_RD(bp, func_ext_config[func].
9775 fcoe_mac_addr_upper);
9776 val = MF_CFG_RD(bp, func_ext_config[func].
9777 fcoe_mac_addr_lower);
2ba45142 9778 bnx2x_set_mac_buf(fip_mac, val, val2);
614c76df 9779 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
0f9dad10 9780 fip_mac);
2ba45142 9781
2ba45142
VZ		 9782 } else
9783 bp->flags |= NO_FCOE_FLAG;
9e62e912
DK		 9784 } else { /* SD MODE */
9785 if (IS_MF_STORAGE_SD(bp)) {
9786 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
9787 /* use primary mac as iscsi mac */
9788 memcpy(iscsi_mac, bp->dev->dev_addr,
9789 ETH_ALEN);
9790
9791 BNX2X_DEV_INFO("SD ISCSI MODE\n");
9792 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9793 iscsi_mac);
9794 } else { /* FCoE */
9795 memcpy(fip_mac, bp->dev->dev_addr,
9796 ETH_ALEN);
9797 BNX2X_DEV_INFO("SD FCoE MODE\n");
9798 BNX2X_DEV_INFO("Read FIP MAC: %pM\n",
9799 fip_mac);
9800 }
614c76df
DK		 9801 /* Zero primary MAC configuration */
9802 memset(bp->dev->dev_addr, 0, ETH_ALEN);
614c76df 9803 }
0793f83f 9804 }
37b091ba 9805#endif
0793f83f
DK		 9806 } else {
9807 /* in SF read MACs from port configuration */
9808 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9809 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9810 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9811
9812#ifdef BCM_CNIC
9813 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9814 iscsi_mac_upper);
9815 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9816 iscsi_mac_lower);
2ba45142 9817 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 9818
9819 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9820 fcoe_fip_mac_upper);
9821 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9822 fcoe_fip_mac_lower);
9823 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 9824#endif
9825 }
9826
9827 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9828 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9829
ec6ba945 9830#ifdef BCM_CNIC
426b9241
DK		 9831 /* Disable iSCSI if MAC configuration is
9832 * invalid.
9833 */
9834 if (!is_valid_ether_addr(iscsi_mac)) {
9835 bp->flags |= NO_ISCSI_FLAG;
9836 memset(iscsi_mac, 0, ETH_ALEN);
9837 }
9838
9839 /* Disable FCoE if MAC configuration is
9840 * invalid.
9841 */
9842 if (!is_valid_ether_addr(fip_mac)) {
9843 bp->flags |= NO_FCOE_FLAG;
9844 memset(bp->fip_mac, 0, ETH_ALEN);
9845 }
ec6ba945 9846#endif
619c5cb6 9847
614c76df 9848 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6 9849 dev_err(&bp->pdev->dev,
51c1a580
MS		 9850 "bad Ethernet MAC address configuration: %pM\n"
9851 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 9852 bp->dev->dev_addr);
51c1a580
MS		 9853
9854
34f80b04
EG		 9855}
9856
9857static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9858{
0793f83f 9859 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 9860 int vn;
0793f83f 9861 u32 val = 0;
34f80b04 9862 int rc = 0;
a2fbb9ea 9863
34f80b04 9864 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 9865
6383c0b3
AE		 9866 /*
9867 * initialize IGU parameters
9868 */
f2e0899f
DK		 9869 if (CHIP_IS_E1x(bp)) {
9870 bp->common.int_block = INT_BLOCK_HC;
9871
9872 bp->igu_dsb_id = DEF_SB_IGU_ID;
9873 bp->igu_base_sb = 0;
f2e0899f
DK		 9874 } else {
9875 bp->common.int_block = INT_BLOCK_IGU;
7a06a122
DK		 9876
9877 /* do not allow device reset during IGU info preocessing */
9878 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9879
f2e0899f 9880 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 9881
9882 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9883 int tout = 5000;
9884
9885 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9886
9887 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9888 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9889 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9890
9891 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9892 tout--;
9893 usleep_range(1000, 1000);
9894 }
9895
9896 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9897 dev_err(&bp->pdev->dev,
9898 "FORCING Normal Mode failed!!!\n");
9899 return -EPERM;
9900 }
9901 }
9902
f2e0899f 9903 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 9904 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 9905 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9906 } else
619c5cb6 9907 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 9908
f2e0899f
DK		 9909 bnx2x_get_igu_cam_info(bp);
9910
7a06a122 9911 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
f2e0899f 9912 }
619c5cb6
VZ		 9913
9914 /*
9915 * set base FW non-default (fast path) status block id, this value is
9916 * used to initialize the fw_sb_id saved on the fp/queue structure to
9917 * determine the id used by the FW.
9918 */
9919 if (CHIP_IS_E1x(bp))
9920 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9921 else /*
9922 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9923 * the same queue are indicated on the same IGU SB). So we prefer
9924 * FW and IGU SBs to be the same value.
9925 */
9926 bp->base_fw_ndsb = bp->igu_base_sb;
9927
9928 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9929 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9930 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 9931
9932 /*
9933 * Initialize MF configuration
9934 */
523224a3 9935
fb3bff17
DK		 9936 bp->mf_ov = 0;
9937 bp->mf_mode = 0;
3395a033 9938 vn = BP_VN(bp);
0793f83f 9939
f2e0899f 9940 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 9941 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9942 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9943 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9944
f2e0899f
DK		 9945 if (SHMEM2_HAS(bp, mf_cfg_addr))
9946 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9947 else
9948 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 9949 offsetof(struct shmem_region, func_mb) +
9950 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 9951 /*
9952 * get mf configuration:
25985edc 9953 * 1. existence of MF configuration
0793f83f
DK		 9954 * 2. MAC address must be legal (check only upper bytes)
9955 * for Switch-Independent mode;
9956 * OVLAN must be legal for Switch-Dependent mode
9957 * 3. SF_MODE configures specific MF mode
9958 */
9959 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9960 /* get mf configuration */
9961 val = SHMEM_RD(bp,
9962 dev_info.shared_feature_config.config);
9963 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9964
9965 switch (val) {
9966 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9967 val = MF_CFG_RD(bp, func_mf_config[func].
9968 mac_upper);
9969 /* check for legal mac (upper bytes)*/
9970 if (val != 0xffff) {
9971 bp->mf_mode = MULTI_FUNCTION_SI;
9972 bp->mf_config[vn] = MF_CFG_RD(bp,
9973 func_mf_config[func].config);
9974 } else
51c1a580 9975 BNX2X_DEV_INFO("illegal MAC address for SI\n");
0793f83f
DK		 9976 break;
9977 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9978 /* get OV configuration */
9979 val = MF_CFG_RD(bp,
9980 func_mf_config[FUNC_0].e1hov_tag);
9981 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9982
9983 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9984 bp->mf_mode = MULTI_FUNCTION_SD;
9985 bp->mf_config[vn] = MF_CFG_RD(bp,
9986 func_mf_config[func].config);
9987 } else
754a2f52 9988 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f
DK		 9989 break;
9990 default:
9991 /* Unknown configuration: reset mf_config */
9992 bp->mf_config[vn] = 0;
51c1a580 9993 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 9994 }
9995 }
a2fbb9ea 9996
2691d51d 9997 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 9998 IS_MF(bp) ? "multi" : "single");
2691d51d 9999
0793f83f
DK		 10000 switch (bp->mf_mode) {
10001 case MULTI_FUNCTION_SD:
10002 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10003 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 10004 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 10005 bp->mf_ov = val;
619c5cb6
VZ		 10006 bp->path_has_ovlan = true;
10007
51c1a580
MS		 10008 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10009 func, bp->mf_ov, bp->mf_ov);
2691d51d 10010 } else {
619c5cb6 10011 dev_err(&bp->pdev->dev,
51c1a580
MS		 10012 "No valid MF OV for func %d, aborting\n",
10013 func);
619c5cb6 10014 return -EPERM;
34f80b04 10015 }
0793f83f
DK		 10016 break;
10017 case MULTI_FUNCTION_SI:
51c1a580
MS		 10018 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10019 func);
0793f83f
DK		 10020 break;
10021 default:
10022 if (vn) {
619c5cb6 10023 dev_err(&bp->pdev->dev,
51c1a580
MS		 10024 "VN %d is in a single function mode, aborting\n",
10025 vn);
619c5cb6 10026 return -EPERM;
2691d51d 10027 }
0793f83f 10028 break;
34f80b04 10029 }
0793f83f 10030
619c5cb6
VZ		 10031 /* check if other port on the path needs ovlan:
10032 * Since MF configuration is shared between ports
10033 * Possible mixed modes are only
10034 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10035 */
10036 if (CHIP_MODE_IS_4_PORT(bp) &&
10037 !bp->path_has_ovlan &&
10038 !IS_MF(bp) &&
10039 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10040 u8 other_port = !BP_PORT(bp);
10041 u8 other_func = BP_PATH(bp) + 2*other_port;
10042 val = MF_CFG_RD(bp,
10043 func_mf_config[other_func].e1hov_tag);
10044 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10045 bp->path_has_ovlan = true;
10046 }
34f80b04 10047 }
a2fbb9ea 10048
f2e0899f
DK		 10049 /* adjust igu_sb_cnt to MF for E1x */
10050 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 10051 bp->igu_sb_cnt /= E1HVN_MAX;
10052
619c5cb6
VZ		 10053 /* port info */
10054 bnx2x_get_port_hwinfo(bp);
f2e0899f 10055
0793f83f
DK		 10056 /* Get MAC addresses */
10057 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 10058
2ba45142 10059 bnx2x_get_cnic_info(bp);
2ba45142 10060
34f80b04
EG		 10061 return rc;
10062}
10063
34f24c7f
VZ		 10064static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
10065{
10066 int cnt, i, block_end, rodi;
fcdf95cb 10067 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 10068 char str_id_reg[VENDOR_ID_LEN+1];
10069 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 10070 char *vpd_data;
10071 char *vpd_extended_data = NULL;
34f24c7f
VZ		 10072 u8 len;
10073
fcdf95cb 10074 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 10075 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
10076
10077 if (cnt < BNX2X_VPD_LEN)
10078 goto out_not_found;
10079
fcdf95cb
BW		 10080 /* VPD RO tag should be first tag after identifier string, hence
10081 * we should be able to find it in first BNX2X_VPD_LEN chars
10082 */
10083 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 10084 PCI_VPD_LRDT_RO_DATA);
10085 if (i < 0)
10086 goto out_not_found;
10087
34f24c7f 10088 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 10089 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 10090
10091 i += PCI_VPD_LRDT_TAG_SIZE;
10092
fcdf95cb
BW		 10093 if (block_end > BNX2X_VPD_LEN) {
10094 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10095 if (vpd_extended_data == NULL)
10096 goto out_not_found;
10097
10098 /* read rest of vpd image into vpd_extended_data */
10099 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10100 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10101 block_end - BNX2X_VPD_LEN,
10102 vpd_extended_data + BNX2X_VPD_LEN);
10103 if (cnt < (block_end - BNX2X_VPD_LEN))
10104 goto out_not_found;
10105 vpd_data = vpd_extended_data;
10106 } else
10107 vpd_data = vpd_start;
10108
10109 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 10110
10111 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10112 PCI_VPD_RO_KEYWORD_MFR_ID);
10113 if (rodi < 0)
10114 goto out_not_found;
10115
10116 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10117
10118 if (len != VENDOR_ID_LEN)
10119 goto out_not_found;
10120
10121 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10122
10123 /* vendor specific info */
10124 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10125 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10126 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10127 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
10128
10129 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10130 PCI_VPD_RO_KEYWORD_VENDOR0);
10131 if (rodi >= 0) {
10132 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10133
10134 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10135
10136 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
10137 memcpy(bp->fw_ver, &vpd_data[rodi], len);
10138 bp->fw_ver[len] = ' ';
10139 }
10140 }
fcdf95cb 10141 kfree(vpd_extended_data);
34f24c7f
VZ		 10142 return;
10143 }
10144out_not_found:
fcdf95cb 10145 kfree(vpd_extended_data);
34f24c7f
VZ		 10146 return;
10147}
10148
619c5cb6
VZ		 10149static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10150{
10151 u32 flags = 0;
10152
10153 if (CHIP_REV_IS_FPGA(bp))
10154 SET_FLAGS(flags, MODE_FPGA);
10155 else if (CHIP_REV_IS_EMUL(bp))
10156 SET_FLAGS(flags, MODE_EMUL);
10157 else
10158 SET_FLAGS(flags, MODE_ASIC);
10159
10160 if (CHIP_MODE_IS_4_PORT(bp))
10161 SET_FLAGS(flags, MODE_PORT4);
10162 else
10163 SET_FLAGS(flags, MODE_PORT2);
10164
10165 if (CHIP_IS_E2(bp))
10166 SET_FLAGS(flags, MODE_E2);
10167 else if (CHIP_IS_E3(bp)) {
10168 SET_FLAGS(flags, MODE_E3);
10169 if (CHIP_REV(bp) == CHIP_REV_Ax)
10170 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 10171 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10172 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 10173 }
10174
10175 if (IS_MF(bp)) {
10176 SET_FLAGS(flags, MODE_MF);
10177 switch (bp->mf_mode) {
10178 case MULTI_FUNCTION_SD:
10179 SET_FLAGS(flags, MODE_MF_SD);
10180 break;
10181 case MULTI_FUNCTION_SI:
10182 SET_FLAGS(flags, MODE_MF_SI);
10183 break;
10184 }
10185 } else
10186 SET_FLAGS(flags, MODE_SF);
10187
10188#if defined(__LITTLE_ENDIAN)
10189 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10190#else /*(__BIG_ENDIAN)*/
10191 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10192#endif
10193 INIT_MODE_FLAGS(bp) = flags;
10194}
10195
34f80b04
EG		 10196static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10197{
f2e0899f 10198 int func;
34f80b04
EG		 10199 int rc;
10200
34f80b04 10201 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 10202 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 10203 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 10204#ifdef BCM_CNIC
10205 mutex_init(&bp->cnic_mutex);
10206#endif
a2fbb9ea 10207
1cf167f2 10208 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 10209 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 10210 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
34f80b04 10211 rc = bnx2x_get_hwinfo(bp);
619c5cb6
VZ		 10212 if (rc)
10213 return rc;
34f80b04 10214
619c5cb6
VZ		 10215 bnx2x_set_modes_bitmap(bp);
10216
10217 rc = bnx2x_alloc_mem_bp(bp);
10218 if (rc)
10219 return rc;
523224a3 10220
34f24c7f 10221 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 10222
10223 func = BP_FUNC(bp);
10224
34f80b04 10225 /* need to reset chip if undi was active */
452427b0
YM		 10226 if (!BP_NOMCP(bp)) {
10227 /* init fw_seq */
10228 bp->fw_seq =
10229 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10230 DRV_MSG_SEQ_NUMBER_MASK;
10231 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10232
10233 bnx2x_prev_unload(bp);
10234 }
10235
34f80b04
EG		 10236
10237 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 10238 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 10239
10240 if (BP_NOMCP(bp) && (func == 0))
51c1a580 10241 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 10242
614c76df
DK		 10243 bp->disable_tpa = disable_tpa;
10244
10245#ifdef BCM_CNIC
9e62e912 10246 bp->disable_tpa |= IS_MF_STORAGE_SD(bp);
614c76df
DK		 10247#endif
10248
7a9b2557 10249 /* Set TPA flags */
614c76df 10250 if (bp->disable_tpa) {
621b4d66 10251 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 10252 bp->dev->features &= ~NETIF_F_LRO;
10253 } else {
621b4d66 10254 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 10255 bp->dev->features |= NETIF_F_LRO;
10256 }
10257
a18f5128
EG		 10258 if (CHIP_IS_E1(bp))
10259 bp->dropless_fc = 0;
10260 else
10261 bp->dropless_fc = dropless_fc;
10262
8d5726c4 10263 bp->mrrs = mrrs;
7a9b2557 10264
34f80b04 10265 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 10266
7d323bfd 10267 /* make sure that the numbers are in the right granularity */
523224a3
DK		 10268 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10269 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 10270
fc543637 10271 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 10272
10273 init_timer(&bp->timer);
10274 bp->timer.expires = jiffies + bp->current_interval;
10275 bp->timer.data = (unsigned long) bp;
10276 bp->timer.function = bnx2x_timer;
10277
785b9b1a 10278 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 10279 bnx2x_dcbx_init_params(bp);
10280
619c5cb6
VZ		 10281#ifdef BCM_CNIC
10282 if (CHIP_IS_E1x(bp))
10283 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10284 else
10285 bp->cnic_base_cl_id = FP_SB_MAX_E2;
10286#endif
10287
6383c0b3
AE		 10288 /* multiple tx priority */
10289 if (CHIP_IS_E1x(bp))
10290 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
10291 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10292 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
10293 if (CHIP_IS_E3B0(bp))
10294 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
10295
fe603b4d
DK		 10296 bp->gro_check = bnx2x_need_gro_check(bp->dev->mtu);
10297
34f80b04 10298 return rc;
a2fbb9ea
ET		 10299}
10300
a2fbb9ea 10301
de0c62db
DK		 10302/****************************************************************************
10303* General service functions
10304****************************************************************************/
a2fbb9ea 10305
619c5cb6
VZ		 10306/*
10307 * net_device service functions
10308 */
10309
bb2a0f7a 10310/* called with rtnl_lock */
a2fbb9ea
ET		 10311static int bnx2x_open(struct net_device *dev)
10312{
10313 struct bnx2x *bp = netdev_priv(dev);
c9ee9206
VZ		 10314 bool global = false;
10315 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3 10316 bool other_load_status, load_status;
a2fbb9ea 10317
1355b704
MY		 10318 bp->stats_init = true;
10319
6eccabb3
EG		 10320 netif_carrier_off(dev);
10321
a2fbb9ea
ET		 10322 bnx2x_set_power_state(bp, PCI_D0);
10323
889b9af3
AE		 10324 other_load_status = bnx2x_get_load_status(bp, other_engine);
10325 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 10326
10327 /*
10328 * If parity had happen during the unload, then attentions
10329 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10330 * want the first function loaded on the current engine to
10331 * complete the recovery.
10332 */
10333 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10334 bnx2x_chk_parity_attn(bp, &global, true))
72fd0718 10335 do {
c9ee9206
VZ		 10336 /*
10337 * If there are attentions and they are in a global
10338 * blocks, set the GLOBAL_RESET bit regardless whether
10339 * it will be this function that will complete the
10340 * recovery or not.
72fd0718 10341 */
c9ee9206
VZ		 10342 if (global)
10343 bnx2x_set_reset_global(bp);
72fd0718 10344
c9ee9206
VZ		 10345 /*
10346 * Only the first function on the current engine should
10347 * try to recover in open. In case of attentions in
10348 * global blocks only the first in the chip should try
10349 * to recover.
72fd0718 10350 */
889b9af3
AE		 10351 if ((!load_status &&
10352 (!global || !other_load_status)) &&
c9ee9206
VZ		 10353 bnx2x_trylock_leader_lock(bp) &&
10354 !bnx2x_leader_reset(bp)) {
10355 netdev_info(bp->dev, "Recovered in open\n");
72fd0718
VZ		 10356 break;
10357 }
10358
c9ee9206 10359 /* recovery has failed... */
72fd0718 10360 bnx2x_set_power_state(bp, PCI_D3hot);
c9ee9206 10361 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 10362
51c1a580
MS		 10363 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
10364 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718
VZ		 10365
10366 return -EAGAIN;
10367 } while (0);
72fd0718
VZ		 10368
10369 bp->recovery_state = BNX2X_RECOVERY_DONE;
bb2a0f7a 10370 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 10371}
10372
bb2a0f7a 10373/* called with rtnl_lock */
56ad3152 10374static int bnx2x_close(struct net_device *dev)
a2fbb9ea 10375{
a2fbb9ea
ET		 10376 struct bnx2x *bp = netdev_priv(dev);
10377
10378 /* Unload the driver, release IRQs */
bb2a0f7a 10379 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
c9ee9206
VZ		 10380
10381 /* Power off */
d3dbfee0 10382 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 10383
10384 return 0;
10385}
10386
619c5cb6
VZ		 10387static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
10388 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 10389{
619c5cb6
VZ		 10390 int mc_count = netdev_mc_count(bp->dev);
10391 struct bnx2x_mcast_list_elem *mc_mac =
10392 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
10393 struct netdev_hw_addr *ha;
6e30dd4e 10394
619c5cb6
VZ		 10395 if (!mc_mac)
10396 return -ENOMEM;
6e30dd4e 10397
619c5cb6 10398 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 10399
619c5cb6
VZ		 10400 netdev_for_each_mc_addr(ha, bp->dev) {
10401 mc_mac->mac = bnx2x_mc_addr(ha);
10402 list_add_tail(&mc_mac->link, &p->mcast_list);
10403 mc_mac++;
6e30dd4e 10404 }
619c5cb6
VZ		 10405
10406 p->mcast_list_len = mc_count;
10407
10408 return 0;
6e30dd4e
VZ		 10409}
10410
619c5cb6
VZ		 10411static inline void bnx2x_free_mcast_macs_list(
10412 struct bnx2x_mcast_ramrod_params *p)
10413{
10414 struct bnx2x_mcast_list_elem *mc_mac =
10415 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
10416 link);
10417
10418 WARN_ON(!mc_mac);
10419 kfree(mc_mac);
10420}
10421
10422/**
10423 * bnx2x_set_uc_list - configure a new unicast MACs list.
10424 *
10425 * @bp: driver handle
6e30dd4e 10426 *
619c5cb6 10427 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 10428 */
619c5cb6 10429static inline int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 10430{
619c5cb6 10431 int rc;
6e30dd4e 10432 struct net_device *dev = bp->dev;
6e30dd4e 10433 struct netdev_hw_addr *ha;
619c5cb6
VZ		 10434 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
10435 unsigned long ramrod_flags = 0;
6e30dd4e 10436
619c5cb6
VZ		 10437 /* First schedule a cleanup up of old configuration */
10438 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
10439 if (rc < 0) {
10440 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10441 return rc;
10442 }
6e30dd4e
VZ		 10443
10444 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 10445 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10446 BNX2X_UC_LIST_MAC, &ramrod_flags);
10447 if (rc < 0) {
10448 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10449 rc);
10450 return rc;
6e30dd4e
VZ		 10451 }
10452 }
10453
619c5cb6
VZ		 10454 /* Execute the pending commands */
10455 __set_bit(RAMROD_CONT, &ramrod_flags);
10456 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10457 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 10458}
10459
619c5cb6 10460static inline int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 10461{
619c5cb6 10462 struct net_device *dev = bp->dev;
3b603066 10463 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 10464 int rc = 0;
6e30dd4e 10465
619c5cb6 10466 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 10467
619c5cb6
VZ		 10468 /* first, clear all configured multicast MACs */
10469 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10470 if (rc < 0) {
51c1a580 10471 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 10472 return rc;
10473 }
6e30dd4e 10474
619c5cb6
VZ		 10475 /* then, configure a new MACs list */
10476 if (netdev_mc_count(dev)) {
10477 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10478 if (rc) {
51c1a580
MS		 10479 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
10480 rc);
619c5cb6
VZ		 10481 return rc;
10482 }
6e30dd4e 10483
619c5cb6
VZ		 10484 /* Now add the new MACs */
10485 rc = bnx2x_config_mcast(bp, &rparam,
10486 BNX2X_MCAST_CMD_ADD);
10487 if (rc < 0)
51c1a580
MS		 10488 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
10489 rc);
6e30dd4e 10490
619c5cb6
VZ		 10491 bnx2x_free_mcast_macs_list(&rparam);
10492 }
6e30dd4e 10493
619c5cb6 10494 return rc;
6e30dd4e
VZ		 10495}
10496
6e30dd4e 10497
619c5cb6 10498/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 10499void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 10500{
10501 struct bnx2x *bp = netdev_priv(dev);
10502 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 10503
10504 if (bp->state != BNX2X_STATE_OPEN) {
10505 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10506 return;
10507 }
10508
619c5cb6 10509 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 10510
10511 if (dev->flags & IFF_PROMISC)
10512 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 10513 else if ((dev->flags & IFF_ALLMULTI) ||
10514 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10515 CHIP_IS_E1(bp)))
34f80b04 10516 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 10517 else {
10518 /* some multicasts */
619c5cb6 10519 if (bnx2x_set_mc_list(bp) < 0)
6e30dd4e 10520 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 10521
619c5cb6 10522 if (bnx2x_set_uc_list(bp) < 0)
6e30dd4e 10523 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 10524 }
10525
10526 bp->rx_mode = rx_mode;
614c76df
DK		 10527#ifdef BCM_CNIC
10528 /* handle ISCSI SD mode */
10529 if (IS_MF_ISCSI_SD(bp))
10530 bp->rx_mode = BNX2X_RX_MODE_NONE;
10531#endif
619c5cb6
VZ		 10532
10533 /* Schedule the rx_mode command */
10534 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10535 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10536 return;
10537 }
10538
34f80b04
EG		 10539 bnx2x_set_storm_rx_mode(bp);
10540}
10541
c18487ee 10542/* called with rtnl_lock */
01cd4528
EG		 10543static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10544 int devad, u16 addr)
a2fbb9ea 10545{
01cd4528
EG		 10546 struct bnx2x *bp = netdev_priv(netdev);
10547 u16 value;
10548 int rc;
a2fbb9ea 10549
01cd4528
EG		 10550 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10551 prtad, devad, addr);
a2fbb9ea 10552
01cd4528
EG		 10553 /* The HW expects different devad if CL22 is used */
10554 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 10555
01cd4528 10556 bnx2x_acquire_phy_lock(bp);
e10bc84d 10557 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 10558 bnx2x_release_phy_lock(bp);
10559 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 10560
01cd4528
EG		 10561 if (!rc)
10562 rc = value;
10563 return rc;
10564}
a2fbb9ea 10565
01cd4528
EG		 10566/* called with rtnl_lock */
10567static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10568 u16 addr, u16 value)
10569{
10570 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 10571 int rc;
10572
51c1a580
MS		 10573 DP(NETIF_MSG_LINK,
10574 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
10575 prtad, devad, addr, value);
01cd4528 10576
01cd4528
EG		 10577 /* The HW expects different devad if CL22 is used */
10578 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 10579
01cd4528 10580 bnx2x_acquire_phy_lock(bp);
e10bc84d 10581 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 10582 bnx2x_release_phy_lock(bp);
10583 return rc;
10584}
c18487ee 10585
01cd4528
EG		 10586/* called with rtnl_lock */
10587static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10588{
10589 struct bnx2x *bp = netdev_priv(dev);
10590 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 10591
01cd4528
EG		 10592 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10593 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 10594
01cd4528
EG		 10595 if (!netif_running(dev))
10596 return -EAGAIN;
10597
10598 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 10599}
10600
257ddbda 10601#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 10602static void poll_bnx2x(struct net_device *dev)
10603{
10604 struct bnx2x *bp = netdev_priv(dev);
10605
10606 disable_irq(bp->pdev->irq);
10607 bnx2x_interrupt(bp->pdev->irq, dev);
10608 enable_irq(bp->pdev->irq);
10609}
10610#endif
10611
614c76df
DK		 10612static int bnx2x_validate_addr(struct net_device *dev)
10613{
10614 struct bnx2x *bp = netdev_priv(dev);
10615
51c1a580
MS		 10616 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
10617 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 10618 return -EADDRNOTAVAIL;
51c1a580 10619 }
614c76df
DK		 10620 return 0;
10621}
10622
c64213cd
SH		 10623static const struct net_device_ops bnx2x_netdev_ops = {
10624 .ndo_open = bnx2x_open,
10625 .ndo_stop = bnx2x_close,
10626 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 10627 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 10628 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 10629 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 10630 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 10631 .ndo_do_ioctl = bnx2x_ioctl,
10632 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 10633 .ndo_fix_features = bnx2x_fix_features,
10634 .ndo_set_features = bnx2x_set_features,
c64213cd 10635 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 10636#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 10637 .ndo_poll_controller = poll_bnx2x,
10638#endif
6383c0b3
AE		 10639 .ndo_setup_tc = bnx2x_setup_tc,
10640
bf61ee14
VZ		 10641#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10642 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10643#endif
c64213cd
SH		 10644};
10645
619c5cb6
VZ		 10646static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10647{
10648 struct device *dev = &bp->pdev->dev;
10649
10650 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10651 bp->flags |= USING_DAC_FLAG;
10652 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
51c1a580 10653 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
619c5cb6
VZ		 10654 return -EIO;
10655 }
10656 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10657 dev_err(dev, "System does not support DMA, aborting\n");
10658 return -EIO;
10659 }
10660
10661 return 0;
10662}
10663
34f80b04 10664static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
619c5cb6
VZ		 10665 struct net_device *dev,
10666 unsigned long board_type)
a2fbb9ea
ET		 10667{
10668 struct bnx2x *bp;
10669 int rc;
c22610d0 10670 u32 pci_cfg_dword;
65087cfe
AE		 10671 bool chip_is_e1x = (board_type == BCM57710 ||
10672 board_type == BCM57711 ||
10673 board_type == BCM57711E);
a2fbb9ea
ET		 10674
10675 SET_NETDEV_DEV(dev, &pdev->dev);
10676 bp = netdev_priv(dev);
10677
34f80b04
EG		 10678 bp->dev = dev;
10679 bp->pdev = pdev;
a2fbb9ea 10680 bp->flags = 0;
a2fbb9ea
ET		 10681
10682 rc = pci_enable_device(pdev);
10683 if (rc) {
cdaa7cb8
VZ		 10684 dev_err(&bp->pdev->dev,
10685 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 10686 goto err_out;
10687 }
10688
10689 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10690 dev_err(&bp->pdev->dev,
10691 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 10692 rc = -ENODEV;
10693 goto err_out_disable;
10694 }
10695
10696 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10697 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10698 " base address, aborting\n");
a2fbb9ea
ET		 10699 rc = -ENODEV;
10700 goto err_out_disable;
10701 }
10702
34f80b04
EG		 10703 if (atomic_read(&pdev->enable_cnt) == 1) {
10704 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10705 if (rc) {
cdaa7cb8
VZ		 10706 dev_err(&bp->pdev->dev,
10707 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 10708 goto err_out_disable;
10709 }
a2fbb9ea 10710
34f80b04
EG		 10711 pci_set_master(pdev);
10712 pci_save_state(pdev);
10713 }
a2fbb9ea
ET		 10714
10715 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10716 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 10717 dev_err(&bp->pdev->dev,
10718 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 10719 rc = -EIO;
10720 goto err_out_release;
10721 }
10722
77c98e6a 10723 if (!pci_is_pcie(pdev)) {
51c1a580 10724 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 10725 rc = -EIO;
10726 goto err_out_release;
10727 }
10728
619c5cb6
VZ		 10729 rc = bnx2x_set_coherency_mask(bp);
10730 if (rc)
a2fbb9ea 10731 goto err_out_release;
a2fbb9ea 10732
34f80b04
EG		 10733 dev->mem_start = pci_resource_start(pdev, 0);
10734 dev->base_addr = dev->mem_start;
10735 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 10736
10737 dev->irq = pdev->irq;
10738
275f165f 10739 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 10740 if (!bp->regview) {
cdaa7cb8
VZ		 10741 dev_err(&bp->pdev->dev,
10742 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 10743 rc = -ENOMEM;
10744 goto err_out_release;
10745 }
10746
c22610d0
AE		 10747 /* In E1/E1H use pci device function given by kernel.
10748 * In E2/E3 read physical function from ME register since these chips
10749 * support Physical Device Assignment where kernel BDF maybe arbitrary
10750 * (depending on hypervisor).
10751 */
10752 if (chip_is_e1x)
10753 bp->pf_num = PCI_FUNC(pdev->devfn);
10754 else {/* chip is E2/3*/
10755 pci_read_config_dword(bp->pdev,
10756 PCICFG_ME_REGISTER, &pci_cfg_dword);
10757 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
10758 ME_REG_ABS_PF_NUM_SHIFT);
10759 }
51c1a580 10760 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 10761
a2fbb9ea
ET		 10762 bnx2x_set_power_state(bp, PCI_D0);
10763
34f80b04
EG		 10764 /* clean indirect addresses */
10765 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10766 PCICFG_VENDOR_ID_OFFSET);
a5c53dbc
DK		 10767 /*
10768 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 10769 * is not used by the driver.
10770 */
10771 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10772 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10773 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10774 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
a5c53dbc 10775
65087cfe 10776 if (chip_is_e1x) {
a5c53dbc
DK		 10777 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10778 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10779 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10780 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10781 }
a2fbb9ea 10782
2189400b 10783 /*
619c5cb6 10784 * Enable internal target-read (in case we are probed after PF FLR).
2189400b 10785 * Must be done prior to any BAR read access. Only for 57712 and up
619c5cb6 10786 */
65087cfe 10787 if (!chip_is_e1x)
2189400b 10788 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
619c5cb6 10789
72fd0718 10790 /* Reset the load counter */
889b9af3 10791 bnx2x_clear_load_status(bp);
72fd0718 10792
34f80b04 10793 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 10794
c64213cd 10795 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 10796 bnx2x_set_ethtool_ops(dev);
5316bc0b 10797
01789349
JP		 10798 dev->priv_flags |= IFF_UNICAST_FLT;
10799
66371c44 10800 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 10801 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10802 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
10803 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
66371c44
MM		 10804
10805 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10806 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10807
10808 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 10809 if (bp->flags & USING_DAC_FLAG)
66371c44 10810 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 10811
538dd2e3
MB		 10812 /* Add Loopback capability to the device */
10813 dev->hw_features |= NETIF_F_LOOPBACK;
10814
98507672 10815#ifdef BCM_DCBNL
785b9b1a
SR		 10816 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10817#endif
10818
01cd4528
EG		 10819 /* get_port_hwinfo() will set prtad and mmds properly */
10820 bp->mdio.prtad = MDIO_PRTAD_NONE;
10821 bp->mdio.mmds = 0;
10822 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10823 bp->mdio.dev = dev;
10824 bp->mdio.mdio_read = bnx2x_mdio_read;
10825 bp->mdio.mdio_write = bnx2x_mdio_write;
10826
a2fbb9ea
ET		 10827 return 0;
10828
a2fbb9ea 10829err_out_release:
34f80b04
EG		 10830 if (atomic_read(&pdev->enable_cnt) == 1)
10831 pci_release_regions(pdev);
a2fbb9ea
ET		 10832
10833err_out_disable:
10834 pci_disable_device(pdev);
10835 pci_set_drvdata(pdev, NULL);
10836
10837err_out:
10838 return rc;
10839}
10840
37f9ce62
EG		 10841static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10842 int *width, int *speed)
25047950
ET		 10843{
10844 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10845
37f9ce62 10846 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 10847
37f9ce62
EG		 10848 /* return value of 1=2.5GHz 2=5GHz */
10849 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 10850}
37f9ce62 10851
6891dd25 10852static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 10853{
37f9ce62 10854 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 10855 struct bnx2x_fw_file_hdr *fw_hdr;
10856 struct bnx2x_fw_file_section *sections;
94a78b79 10857 u32 offset, len, num_ops;
37f9ce62 10858 u16 *ops_offsets;
94a78b79 10859 int i;
37f9ce62 10860 const u8 *fw_ver;
94a78b79 10861
51c1a580
MS		 10862 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
10863 BNX2X_ERR("Wrong FW size\n");
94a78b79 10864 return -EINVAL;
51c1a580 10865 }
94a78b79
VZ		 10866
10867 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10868 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10869
10870 /* Make sure none of the offsets and sizes make us read beyond
10871 * the end of the firmware data */
10872 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10873 offset = be32_to_cpu(sections[i].offset);
10874 len = be32_to_cpu(sections[i].len);
10875 if (offset + len > firmware->size) {
51c1a580 10876 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 10877 return -EINVAL;
10878 }
10879 }
10880
10881 /* Likewise for the init_ops offsets */
10882 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10883 ops_offsets = (u16 *)(firmware->data + offset);
10884 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10885
10886 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10887 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 10888 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 10889 return -EINVAL;
10890 }
10891 }
10892
10893 /* Check FW version */
10894 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10895 fw_ver = firmware->data + offset;
10896 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10897 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10898 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10899 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 10900 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10901 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
10902 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 10903 BCM_5710_FW_MINOR_VERSION,
10904 BCM_5710_FW_REVISION_VERSION,
10905 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 10906 return -EINVAL;
94a78b79
VZ		 10907 }
10908
10909 return 0;
10910}
10911
ab6ad5a4 10912static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10913{
ab6ad5a4
EG		 10914 const __be32 *source = (const __be32 *)_source;
10915 u32 *target = (u32 *)_target;
94a78b79 10916 u32 i;
94a78b79
VZ		 10917
10918 for (i = 0; i < n/4; i++)
10919 target[i] = be32_to_cpu(source[i]);
10920}
10921
10922/*
10923 Ops array is stored in the following format:
10924 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10925 */
ab6ad5a4 10926static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 10927{
ab6ad5a4
EG		 10928 const __be32 *source = (const __be32 *)_source;
10929 struct raw_op *target = (struct raw_op *)_target;
94a78b79 10930 u32 i, j, tmp;
94a78b79 10931
ab6ad5a4 10932 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 10933 tmp = be32_to_cpu(source[j]);
10934 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 10935 target[i].offset = tmp & 0xffffff;
10936 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 10937 }
10938}
ab6ad5a4 10939
523224a3
DK		 10940/**
10941 * IRO array is stored in the following format:
10942 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10943 */
10944static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10945{
10946 const __be32 *source = (const __be32 *)_source;
10947 struct iro *target = (struct iro *)_target;
10948 u32 i, j, tmp;
10949
10950 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10951 target[i].base = be32_to_cpu(source[j]);
10952 j++;
10953 tmp = be32_to_cpu(source[j]);
10954 target[i].m1 = (tmp >> 16) & 0xffff;
10955 target[i].m2 = tmp & 0xffff;
10956 j++;
10957 tmp = be32_to_cpu(source[j]);
10958 target[i].m3 = (tmp >> 16) & 0xffff;
10959 target[i].size = tmp & 0xffff;
10960 j++;
10961 }
10962}
10963
ab6ad5a4 10964static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10965{
ab6ad5a4
EG		 10966 const __be16 *source = (const __be16 *)_source;
10967 u16 *target = (u16 *)_target;
94a78b79 10968 u32 i;
94a78b79
VZ		 10969
10970 for (i = 0; i < n/2; i++)
10971 target[i] = be16_to_cpu(source[i]);
10972}
10973
7995c64e
JP		 10974#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10975do { \
10976 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10977 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 10978 if (!bp->arr) \
7995c64e 10979 goto lbl; \
7995c64e
JP		 10980 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10981 (u8 *)bp->arr, len); \
10982} while (0)
94a78b79 10983
3b603066 10984static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 10985{
c0ea452e 10986 const char *fw_file_name;
94a78b79 10987 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 10988 int rc;
94a78b79 10989
c0ea452e
MS		 10990 if (bp->firmware)
10991 return 0;
94a78b79 10992
c0ea452e
MS		 10993 if (CHIP_IS_E1(bp))
10994 fw_file_name = FW_FILE_NAME_E1;
10995 else if (CHIP_IS_E1H(bp))
10996 fw_file_name = FW_FILE_NAME_E1H;
10997 else if (!CHIP_IS_E1x(bp))
10998 fw_file_name = FW_FILE_NAME_E2;
10999 else {
11000 BNX2X_ERR("Unsupported chip revision\n");
11001 return -EINVAL;
11002 }
11003 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 11004
c0ea452e
MS		 11005 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
11006 if (rc) {
11007 BNX2X_ERR("Can't load firmware file %s\n",
11008 fw_file_name);
11009 goto request_firmware_exit;
11010 }
eb2afd4a 11011
c0ea452e
MS		 11012 rc = bnx2x_check_firmware(bp);
11013 if (rc) {
11014 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
11015 goto request_firmware_exit;
94a78b79
VZ		 11016 }
11017
11018 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11019
11020 /* Initialize the pointers to the init arrays */
11021 /* Blob */
11022 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11023
11024 /* Opcodes */
11025 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11026
11027 /* Offsets */
ab6ad5a4
EG		 11028 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
11029 be16_to_cpu_n);
94a78b79
VZ		 11030
11031 /* STORMs firmware */
573f2035
EG		 11032 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11033 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11034 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
11035 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11036 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11037 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11038 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
11039 be32_to_cpu(fw_hdr->usem_pram_data.offset);
11040 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11041 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11042 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
11043 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11044 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11045 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11046 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
11047 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 11048 /* IRO */
11049 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 11050
11051 return 0;
ab6ad5a4 11052
523224a3
DK		 11053iro_alloc_err:
11054 kfree(bp->init_ops_offsets);
94a78b79
VZ		 11055init_offsets_alloc_err:
11056 kfree(bp->init_ops);
11057init_ops_alloc_err:
11058 kfree(bp->init_data);
11059request_firmware_exit:
11060 release_firmware(bp->firmware);
127d0a19 11061 bp->firmware = NULL;
94a78b79
VZ		 11062
11063 return rc;
11064}
11065
619c5cb6
VZ		 11066static void bnx2x_release_firmware(struct bnx2x *bp)
11067{
11068 kfree(bp->init_ops_offsets);
11069 kfree(bp->init_ops);
11070 kfree(bp->init_data);
11071 release_firmware(bp->firmware);
eb2afd4a 11072 bp->firmware = NULL;
619c5cb6
VZ		 11073}
11074
11075
11076static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
11077 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
11078 .init_hw_cmn = bnx2x_init_hw_common,
11079 .init_hw_port = bnx2x_init_hw_port,
11080 .init_hw_func = bnx2x_init_hw_func,
11081
11082 .reset_hw_cmn = bnx2x_reset_common,
11083 .reset_hw_port = bnx2x_reset_port,
11084 .reset_hw_func = bnx2x_reset_func,
11085
11086 .gunzip_init = bnx2x_gunzip_init,
11087 .gunzip_end = bnx2x_gunzip_end,
11088
11089 .init_fw = bnx2x_init_firmware,
11090 .release_fw = bnx2x_release_firmware,
11091};
11092
11093void bnx2x__init_func_obj(struct bnx2x *bp)
11094{
11095 /* Prepare DMAE related driver resources */
11096 bnx2x_setup_dmae(bp);
11097
11098 bnx2x_init_func_obj(bp, &bp->func_obj,
11099 bnx2x_sp(bp, func_rdata),
11100 bnx2x_sp_mapping(bp, func_rdata),
11101 &bnx2x_func_sp_drv);
11102}
11103
11104/* must be called after sriov-enable */
6383c0b3 11105static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 11106{
6383c0b3 11107 int cid_count = BNX2X_L2_CID_COUNT(bp);
94a78b79 11108
523224a3
DK		 11109#ifdef BCM_CNIC
11110 cid_count += CNIC_CID_MAX;
11111#endif
11112 return roundup(cid_count, QM_CID_ROUND);
11113}
f85582f8 11114
619c5cb6 11115/**
6383c0b3 11116 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 11117 *
11118 * @dev: pci device
11119 *
11120 */
6383c0b3 11121static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
619c5cb6
VZ		 11122{
11123 int pos;
11124 u16 control;
11125
11126 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
6383c0b3
AE		 11127
11128 /*
11129 * If MSI-X is not supported - return number of SBs needed to support
11130 * one fast path queue: one FP queue + SB for CNIC
11131 */
619c5cb6 11132 if (!pos)
6383c0b3 11133 return 1 + CNIC_PRESENT;
619c5cb6 11134
6383c0b3
AE		 11135 /*
11136 * The value in the PCI configuration space is the index of the last
11137 * entry, namely one less than the actual size of the table, which is
11138 * exactly what we want to return from this function: number of all SBs
11139 * without the default SB.
11140 */
619c5cb6 11141 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
6383c0b3 11142 return control & PCI_MSIX_FLAGS_QSIZE;
619c5cb6
VZ		 11143}
11144
a2fbb9ea
ET		 11145static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11146 const struct pci_device_id *ent)
11147{
a2fbb9ea
ET		 11148 struct net_device *dev = NULL;
11149 struct bnx2x *bp;
37f9ce62 11150 int pcie_width, pcie_speed;
6383c0b3
AE		 11151 int rc, max_non_def_sbs;
11152 int rx_count, tx_count, rss_count;
11153 /*
11154 * An estimated maximum supported CoS number according to the chip
11155 * version.
11156 * We will try to roughly estimate the maximum number of CoSes this chip
11157 * may support in order to minimize the memory allocated for Tx
11158 * netdev_queue's. This number will be accurately calculated during the
11159 * initialization of bp->max_cos based on the chip versions AND chip
11160 * revision in the bnx2x_init_bp().
11161 */
11162 u8 max_cos_est = 0;
523224a3 11163
f2e0899f
DK		 11164 switch (ent->driver_data) {
11165 case BCM57710:
11166 case BCM57711:
11167 case BCM57711E:
6383c0b3
AE		 11168 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11169 break;
11170
f2e0899f 11171 case BCM57712:
619c5cb6 11172 case BCM57712_MF:
6383c0b3
AE		 11173 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11174 break;
11175
619c5cb6
VZ		 11176 case BCM57800:
11177 case BCM57800_MF:
11178 case BCM57810:
11179 case BCM57810_MF:
11180 case BCM57840:
11181 case BCM57840_MF:
7e8e02df
BW		 11182 case BCM57811:
11183 case BCM57811_MF:
6383c0b3 11184 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
f2e0899f 11185 break;
a2fbb9ea 11186
f2e0899f
DK		 11187 default:
11188 pr_err("Unknown board_type (%ld), aborting\n",
11189 ent->driver_data);
870634b0 11190 return -ENODEV;
f2e0899f
DK		 11191 }
11192
6383c0b3
AE		 11193 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11194
11195 /* !!! FIXME !!!
11196 * Do not allow the maximum SB count to grow above 16
11197 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
11198 * We will use the FP_SB_MAX_E1x macro for this matter.
11199 */
11200 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
11201
11202 WARN_ON(!max_non_def_sbs);
11203
11204 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11205 rss_count = max_non_def_sbs - CNIC_PRESENT;
11206
11207 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11208 rx_count = rss_count + FCOE_PRESENT;
11209
11210 /*
11211 * Maximum number of netdev Tx queues:
11212 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11213 */
11214 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
f85582f8 11215
a2fbb9ea 11216 /* dev zeroed in init_etherdev */
6383c0b3 11217 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 11218 if (!dev)
a2fbb9ea
ET		 11219 return -ENOMEM;
11220
a2fbb9ea 11221 bp = netdev_priv(dev);
a2fbb9ea 11222
51c1a580 11223 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
6383c0b3 11224 tx_count, rx_count);
df4770de 11225
6383c0b3
AE		 11226 bp->igu_sb_cnt = max_non_def_sbs;
11227 bp->msg_enable = debug;
11228 pci_set_drvdata(pdev, dev);
523224a3 11229
619c5cb6 11230 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
a2fbb9ea
ET		 11231 if (rc < 0) {
11232 free_netdev(dev);
11233 return rc;
11234 }
11235
51c1a580 11236 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
619c5cb6 11237
34f80b04 11238 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 11239 if (rc)
11240 goto init_one_exit;
11241
6383c0b3
AE		 11242 /*
11243 * Map doorbels here as we need the real value of bp->max_cos which
11244 * is initialized in bnx2x_init_bp().
11245 */
11246 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11247 min_t(u64, BNX2X_DB_SIZE(bp),
11248 pci_resource_len(pdev, 2)));
11249 if (!bp->doorbells) {
11250 dev_err(&bp->pdev->dev,
11251 "Cannot map doorbell space, aborting\n");
11252 rc = -ENOMEM;
11253 goto init_one_exit;
11254 }
11255
523224a3 11256 /* calc qm_cid_count */
6383c0b3 11257 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
523224a3 11258
ec6ba945 11259#ifdef BCM_CNIC
62ac0dc9
DK		 11260 /* disable FCOE L2 queue for E1x */
11261 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 11262 bp->flags |= NO_FCOE_FLAG;
11263
11264#endif
11265
25985edc 11266 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 11267 * needed, set bp->num_queues appropriately.
11268 */
11269 bnx2x_set_int_mode(bp);
11270
11271 /* Add all NAPI objects */
11272 bnx2x_add_all_napi(bp);
11273
b340007f
VZ		 11274 rc = register_netdev(dev);
11275 if (rc) {
11276 dev_err(&pdev->dev, "Cannot register net device\n");
11277 goto init_one_exit;
11278 }
11279
ec6ba945
VZ		 11280#ifdef BCM_CNIC
11281 if (!NO_FCOE(bp)) {
11282 /* Add storage MAC address */
11283 rtnl_lock();
11284 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11285 rtnl_unlock();
11286 }
11287#endif
11288
37f9ce62 11289 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 11290
51c1a580
MS		 11291 BNX2X_DEV_INFO(
11292 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
94f05b0f
JP		 11293 board_info[ent->driver_data].name,
11294 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11295 pcie_width,
11296 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11297 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11298 "5GHz (Gen2)" : "2.5GHz",
11299 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 11300
a2fbb9ea 11301 return 0;
34f80b04
EG		 11302
11303init_one_exit:
11304 if (bp->regview)
11305 iounmap(bp->regview);
11306
11307 if (bp->doorbells)
11308 iounmap(bp->doorbells);
11309
11310 free_netdev(dev);
11311
11312 if (atomic_read(&pdev->enable_cnt) == 1)
11313 pci_release_regions(pdev);
11314
11315 pci_disable_device(pdev);
11316 pci_set_drvdata(pdev, NULL);
11317
11318 return rc;
a2fbb9ea
ET		 11319}
11320
11321static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11322{
11323 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 11324 struct bnx2x *bp;
11325
11326 if (!dev) {
cdaa7cb8 11327 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 11328 return;
11329 }
228241eb 11330 bp = netdev_priv(dev);
a2fbb9ea 11331
ec6ba945
VZ		 11332#ifdef BCM_CNIC
11333 /* Delete storage MAC address */
11334 if (!NO_FCOE(bp)) {
11335 rtnl_lock();
11336 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11337 rtnl_unlock();
11338 }
11339#endif
11340
98507672
SR		 11341#ifdef BCM_DCBNL
11342 /* Delete app tlvs from dcbnl */
11343 bnx2x_dcbnl_update_applist(bp, true);
11344#endif
11345
a2fbb9ea
ET		 11346 unregister_netdev(dev);
11347
d6214d7a
DK		 11348 /* Delete all NAPI objects */
11349 bnx2x_del_all_napi(bp);
11350
084d6cbb
VZ		 11351 /* Power on: we can't let PCI layer write to us while we are in D3 */
11352 bnx2x_set_power_state(bp, PCI_D0);
11353
d6214d7a
DK		 11354 /* Disable MSI/MSI-X */
11355 bnx2x_disable_msi(bp);
f85582f8 11356
084d6cbb
VZ		 11357 /* Power off */
11358 bnx2x_set_power_state(bp, PCI_D3hot);
11359
72fd0718 11360 /* Make sure RESET task is not scheduled before continuing */
7be08a72 11361 cancel_delayed_work_sync(&bp->sp_rtnl_task);
72fd0718 11362
a2fbb9ea
ET		 11363 if (bp->regview)
11364 iounmap(bp->regview);
11365
11366 if (bp->doorbells)
11367 iounmap(bp->doorbells);
11368
eb2afd4a
DK		 11369 bnx2x_release_firmware(bp);
11370
523224a3
DK		 11371 bnx2x_free_mem_bp(bp);
11372
a2fbb9ea 11373 free_netdev(dev);
34f80b04
EG		 11374
11375 if (atomic_read(&pdev->enable_cnt) == 1)
11376 pci_release_regions(pdev);
11377
a2fbb9ea
ET		 11378 pci_disable_device(pdev);
11379 pci_set_drvdata(pdev, NULL);
11380}
11381
f8ef6e44
YG		 11382static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
11383{
11384 int i;
11385
11386 bp->state = BNX2X_STATE_ERROR;
11387
11388 bp->rx_mode = BNX2X_RX_MODE_NONE;
11389
619c5cb6
VZ		 11390#ifdef BCM_CNIC
11391 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
11392#endif
11393 /* Stop Tx */
11394 bnx2x_tx_disable(bp);
11395
f8ef6e44
YG		 11396 bnx2x_netif_stop(bp, 0);
11397
11398 del_timer_sync(&bp->timer);
619c5cb6
VZ		 11399
11400 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 11401
11402 /* Release IRQs */
d6214d7a 11403 bnx2x_free_irq(bp);
f8ef6e44 11404
f8ef6e44
YG		 11405 /* Free SKBs, SGEs, TPA pool and driver internals */
11406 bnx2x_free_skbs(bp);
523224a3 11407
ec6ba945 11408 for_each_rx_queue(bp, i)
f8ef6e44 11409 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 11410
f8ef6e44
YG		 11411 bnx2x_free_mem(bp);
11412
11413 bp->state = BNX2X_STATE_CLOSED;
11414
619c5cb6
VZ		 11415 netif_carrier_off(bp->dev);
11416
f8ef6e44
YG		 11417 return 0;
11418}
11419
11420static void bnx2x_eeh_recover(struct bnx2x *bp)
11421{
11422 u32 val;
11423
11424 mutex_init(&bp->port.phy_mutex);
11425
f8ef6e44
YG		 11426
11427 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
11428 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11429 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11430 BNX2X_ERR("BAD MCP validity signature\n");
f8ef6e44
YG		 11431}
11432
493adb1f
WX		 11433/**
11434 * bnx2x_io_error_detected - called when PCI error is detected
11435 * @pdev: Pointer to PCI device
11436 * @state: The current pci connection state
11437 *
11438 * This function is called after a PCI bus error affecting
11439 * this device has been detected.
11440 */
11441static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11442 pci_channel_state_t state)
11443{
11444 struct net_device *dev = pci_get_drvdata(pdev);
11445 struct bnx2x *bp = netdev_priv(dev);
11446
11447 rtnl_lock();
11448
11449 netif_device_detach(dev);
11450
07ce50e4
DN		 11451 if (state == pci_channel_io_perm_failure) {
11452 rtnl_unlock();
11453 return PCI_ERS_RESULT_DISCONNECT;
11454 }
11455
493adb1f 11456 if (netif_running(dev))
f8ef6e44 11457 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 11458
11459 pci_disable_device(pdev);
11460
11461 rtnl_unlock();
11462
11463 /* Request a slot reset */
11464 return PCI_ERS_RESULT_NEED_RESET;
11465}
11466
11467/**
11468 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11469 * @pdev: Pointer to PCI device
11470 *
11471 * Restart the card from scratch, as if from a cold-boot.
11472 */
11473static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11474{
11475 struct net_device *dev = pci_get_drvdata(pdev);
11476 struct bnx2x *bp = netdev_priv(dev);
11477
11478 rtnl_lock();
11479
11480 if (pci_enable_device(pdev)) {
11481 dev_err(&pdev->dev,
11482 "Cannot re-enable PCI device after reset\n");
11483 rtnl_unlock();
11484 return PCI_ERS_RESULT_DISCONNECT;
11485 }
11486
11487 pci_set_master(pdev);
11488 pci_restore_state(pdev);
11489
11490 if (netif_running(dev))
11491 bnx2x_set_power_state(bp, PCI_D0);
11492
11493 rtnl_unlock();
11494
11495 return PCI_ERS_RESULT_RECOVERED;
11496}
11497
11498/**
11499 * bnx2x_io_resume - called when traffic can start flowing again
11500 * @pdev: Pointer to PCI device
11501 *
11502 * This callback is called when the error recovery driver tells us that
11503 * its OK to resume normal operation.
11504 */
11505static void bnx2x_io_resume(struct pci_dev *pdev)
11506{
11507 struct net_device *dev = pci_get_drvdata(pdev);
11508 struct bnx2x *bp = netdev_priv(dev);
11509
72fd0718 11510 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 11511 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 11512 return;
11513 }
11514
493adb1f
WX		 11515 rtnl_lock();
11516
f8ef6e44
YG		 11517 bnx2x_eeh_recover(bp);
11518
493adb1f 11519 if (netif_running(dev))
f8ef6e44 11520 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 11521
11522 netif_device_attach(dev);
11523
11524 rtnl_unlock();
11525}
11526
11527static struct pci_error_handlers bnx2x_err_handler = {
11528 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 11529 .slot_reset = bnx2x_io_slot_reset,
11530 .resume = bnx2x_io_resume,
493adb1f
WX		 11531};
11532
a2fbb9ea 11533static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 11534 .name = DRV_MODULE_NAME,
11535 .id_table = bnx2x_pci_tbl,
11536 .probe = bnx2x_init_one,
11537 .remove = __devexit_p(bnx2x_remove_one),
11538 .suspend = bnx2x_suspend,
11539 .resume = bnx2x_resume,
11540 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 11541};
11542
11543static int __init bnx2x_init(void)
11544{
dd21ca6d
SG		 11545 int ret;
11546
7995c64e 11547 pr_info("%s", version);
938cf541 11548
1cf167f2
EG		 11549 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11550 if (bnx2x_wq == NULL) {
7995c64e 11551 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 11552 return -ENOMEM;
11553 }
11554
dd21ca6d
SG		 11555 ret = pci_register_driver(&bnx2x_pci_driver);
11556 if (ret) {
7995c64e 11557 pr_err("Cannot register driver\n");
dd21ca6d
SG		 11558 destroy_workqueue(bnx2x_wq);
11559 }
11560 return ret;
a2fbb9ea
ET		 11561}
11562
11563static void __exit bnx2x_cleanup(void)
11564{
452427b0 11565 struct list_head *pos, *q;
a2fbb9ea 11566 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 11567
11568 destroy_workqueue(bnx2x_wq);
452427b0
YM		 11569
11570 /* Free globablly allocated resources */
11571 list_for_each_safe(pos, q, &bnx2x_prev_list) {
11572 struct bnx2x_prev_path_list *tmp =
11573 list_entry(pos, struct bnx2x_prev_path_list, list);
11574 list_del(pos);
11575 kfree(tmp);
11576 }
a2fbb9ea
ET		 11577}
11578
3deb8167
YR		 11579void bnx2x_notify_link_changed(struct bnx2x *bp)
11580{
11581 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11582}
11583
a2fbb9ea
ET		 11584module_init(bnx2x_init);
11585module_exit(bnx2x_cleanup);
11586
993ac7b5 11587#ifdef BCM_CNIC
619c5cb6
VZ		 11588/**
11589 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11590 *
11591 * @bp: driver handle
11592 * @set: set or clear the CAM entry
11593 *
11594 * This function will wait until the ramdord completion returns.
11595 * Return 0 if success, -ENODEV if ramrod doesn't return.
11596 */
11597static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11598{
11599 unsigned long ramrod_flags = 0;
11600
11601 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11602 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11603 &bp->iscsi_l2_mac_obj, true,
11604 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11605}
993ac7b5
MC		 11606
11607/* count denotes the number of new completions we have seen */
11608static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11609{
11610 struct eth_spe *spe;
11611
11612#ifdef BNX2X_STOP_ON_ERROR
11613 if (unlikely(bp->panic))
11614 return;
11615#endif
11616
11617 spin_lock_bh(&bp->spq_lock);
c2bff63f 11618 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 11619 bp->cnic_spq_pending -= count;
11620
993ac7b5 11621
c2bff63f
DK		 11622 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11623 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11624 & SPE_HDR_CONN_TYPE) >>
11625 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 11626 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11627 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 11628
11629 /* Set validation for iSCSI L2 client before sending SETUP
11630 * ramrod
11631 */
11632 if (type == ETH_CONNECTION_TYPE) {
c2bff63f 11633 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
619c5cb6
VZ		 11634 bnx2x_set_ctx_validation(bp, &bp->context.
11635 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11636 BNX2X_ISCSI_ETH_CID);
c2bff63f
DK		 11637 }
11638
619c5cb6
VZ		 11639 /*
11640 * There may be not more than 8 L2, not more than 8 L5 SPEs
11641 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 11642 * COMMON ramrods is not more than the EQ and SPQ can
11643 * accommodate.
c2bff63f 11644 */
6e30dd4e
VZ		 11645 if (type == ETH_CONNECTION_TYPE) {
11646 if (!atomic_read(&bp->cq_spq_left))
11647 break;
11648 else
11649 atomic_dec(&bp->cq_spq_left);
11650 } else if (type == NONE_CONNECTION_TYPE) {
11651 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 11652 break;
11653 else
6e30dd4e 11654 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 11655 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11656 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 11657 if (bp->cnic_spq_pending >=
11658 bp->cnic_eth_dev.max_kwqe_pending)
11659 break;
11660 else
11661 bp->cnic_spq_pending++;
11662 } else {
11663 BNX2X_ERR("Unknown SPE type: %d\n", type);
11664 bnx2x_panic();
993ac7b5 11665 break;
c2bff63f 11666 }
993ac7b5
MC		 11667
11668 spe = bnx2x_sp_get_next(bp);
11669 *spe = *bp->cnic_kwq_cons;
11670
51c1a580 11671 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 11672 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11673
11674 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11675 bp->cnic_kwq_cons = bp->cnic_kwq;
11676 else
11677 bp->cnic_kwq_cons++;
11678 }
11679 bnx2x_sp_prod_update(bp);
11680 spin_unlock_bh(&bp->spq_lock);
11681}
11682
11683static int bnx2x_cnic_sp_queue(struct net_device *dev,
11684 struct kwqe_16 *kwqes[], u32 count)
11685{
11686 struct bnx2x *bp = netdev_priv(dev);
11687 int i;
11688
11689#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 11690 if (unlikely(bp->panic)) {
11691 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 11692 return -EIO;
51c1a580 11693 }
993ac7b5
MC		 11694#endif
11695
95c6c616
AE		 11696 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
11697 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 11698 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 11699 return -EAGAIN;
11700 }
11701
993ac7b5
MC		 11702 spin_lock_bh(&bp->spq_lock);
11703
11704 for (i = 0; i < count; i++) {
11705 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11706
11707 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11708 break;
11709
11710 *bp->cnic_kwq_prod = *spe;
11711
11712 bp->cnic_kwq_pending++;
11713
51c1a580 11714 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 11715 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 11716 spe->data.update_data_addr.hi,
11717 spe->data.update_data_addr.lo,
993ac7b5
MC		 11718 bp->cnic_kwq_pending);
11719
11720 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11721 bp->cnic_kwq_prod = bp->cnic_kwq;
11722 else
11723 bp->cnic_kwq_prod++;
11724 }
11725
11726 spin_unlock_bh(&bp->spq_lock);
11727
11728 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11729 bnx2x_cnic_sp_post(bp, 0);
11730
11731 return i;
11732}
11733
11734static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11735{
11736 struct cnic_ops *c_ops;
11737 int rc = 0;
11738
11739 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 11740 c_ops = rcu_dereference_protected(bp->cnic_ops,
11741 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 11742 if (c_ops)
11743 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11744 mutex_unlock(&bp->cnic_mutex);
11745
11746 return rc;
11747}
11748
11749static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11750{
11751 struct cnic_ops *c_ops;
11752 int rc = 0;
11753
11754 rcu_read_lock();
11755 c_ops = rcu_dereference(bp->cnic_ops);
11756 if (c_ops)
11757 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11758 rcu_read_unlock();
11759
11760 return rc;
11761}
11762
11763/*
11764 * for commands that have no data
11765 */
9f6c9258 11766int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 11767{
11768 struct cnic_ctl_info ctl = {0};
11769
11770 ctl.cmd = cmd;
11771
11772 return bnx2x_cnic_ctl_send(bp, &ctl);
11773}
11774
619c5cb6 11775static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 11776{
619c5cb6 11777 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 11778
11779 /* first we tell CNIC and only then we count this as a completion */
11780 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11781 ctl.data.comp.cid = cid;
619c5cb6 11782 ctl.data.comp.error = err;
993ac7b5
MC		 11783
11784 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 11785 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 11786}
11787
619c5cb6
VZ		 11788
11789/* Called with netif_addr_lock_bh() taken.
11790 * Sets an rx_mode config for an iSCSI ETH client.
11791 * Doesn't block.
11792 * Completion should be checked outside.
11793 */
11794static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11795{
11796 unsigned long accept_flags = 0, ramrod_flags = 0;
11797 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11798 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11799
11800 if (start) {
11801 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11802 * because it's the only way for UIO Queue to accept
11803 * multicasts (in non-promiscuous mode only one Queue per
11804 * function will receive multicast packets (leading in our
11805 * case).
11806 */
11807 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11808 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11809 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11810 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11811
11812 /* Clear STOP_PENDING bit if START is requested */
11813 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11814
11815 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11816 } else
11817 /* Clear START_PENDING bit if STOP is requested */
11818 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11819
11820 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11821 set_bit(sched_state, &bp->sp_state);
11822 else {
11823 __set_bit(RAMROD_RX, &ramrod_flags);
11824 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11825 ramrod_flags);
11826 }
11827}
11828
11829
993ac7b5
MC		 11830static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11831{
11832 struct bnx2x *bp = netdev_priv(dev);
11833 int rc = 0;
11834
11835 switch (ctl->cmd) {
11836 case DRV_CTL_CTXTBL_WR_CMD: {
11837 u32 index = ctl->data.io.offset;
11838 dma_addr_t addr = ctl->data.io.dma_addr;
11839
11840 bnx2x_ilt_wr(bp, index, addr);
11841 break;
11842 }
11843
c2bff63f
DK		 11844 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11845 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 11846
11847 bnx2x_cnic_sp_post(bp, count);
11848 break;
11849 }
11850
11851 /* rtnl_lock is held. */
11852 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 11853 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11854 unsigned long sp_bits = 0;
11855
11856 /* Configure the iSCSI classification object */
11857 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11858 cp->iscsi_l2_client_id,
11859 cp->iscsi_l2_cid, BP_FUNC(bp),
11860 bnx2x_sp(bp, mac_rdata),
11861 bnx2x_sp_mapping(bp, mac_rdata),
11862 BNX2X_FILTER_MAC_PENDING,
11863 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11864 &bp->macs_pool);
ec6ba945 11865
523224a3 11866 /* Set iSCSI MAC address */
619c5cb6
VZ		 11867 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11868 if (rc)
11869 break;
523224a3
DK		 11870
11871 mmiowb();
11872 barrier();
11873
619c5cb6
VZ		 11874 /* Start accepting on iSCSI L2 ring */
11875
11876 netif_addr_lock_bh(dev);
11877 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11878 netif_addr_unlock_bh(dev);
11879
11880 /* bits to wait on */
11881 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11882 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11883
11884 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11885 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 11886
993ac7b5
MC		 11887 break;
11888 }
11889
11890 /* rtnl_lock is held. */
11891 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 11892 unsigned long sp_bits = 0;
993ac7b5 11893
523224a3 11894 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 11895 netif_addr_lock_bh(dev);
11896 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11897 netif_addr_unlock_bh(dev);
11898
11899 /* bits to wait on */
11900 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11901 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11902
11903 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11904 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 11905
11906 mmiowb();
11907 barrier();
11908
11909 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 11910 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11911 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 11912 break;
11913 }
c2bff63f
DK		 11914 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11915 int count = ctl->data.credit.credit_count;
11916
11917 smp_mb__before_atomic_inc();
6e30dd4e 11918 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 11919 smp_mb__after_atomic_inc();
11920 break;
11921 }
1d187b34
BW		 11922 case DRV_CTL_ULP_REGISTER_CMD: {
11923 int ulp_type = ctl->data.ulp_type;
11924
11925 if (CHIP_IS_E3(bp)) {
11926 int idx = BP_FW_MB_IDX(bp);
11927 u32 cap;
11928
11929 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
11930 if (ulp_type == CNIC_ULP_ISCSI)
11931 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
11932 else if (ulp_type == CNIC_ULP_FCOE)
11933 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
11934 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
11935 }
11936 break;
11937 }
11938 case DRV_CTL_ULP_UNREGISTER_CMD: {
11939 int ulp_type = ctl->data.ulp_type;
11940
11941 if (CHIP_IS_E3(bp)) {
11942 int idx = BP_FW_MB_IDX(bp);
11943 u32 cap;
11944
11945 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
11946 if (ulp_type == CNIC_ULP_ISCSI)
11947 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
11948 else if (ulp_type == CNIC_ULP_FCOE)
11949 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
11950 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
11951 }
11952 break;
11953 }
993ac7b5
MC		 11954
11955 default:
11956 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11957 rc = -EINVAL;
11958 }
11959
11960 return rc;
11961}
11962
9f6c9258 11963void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 11964{
11965 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11966
11967 if (bp->flags & USING_MSIX_FLAG) {
11968 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11969 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11970 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11971 } else {
11972 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11973 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11974 }
619c5cb6 11975 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 11976 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11977 else
11978 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11979
619c5cb6
VZ		 11980 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11981 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 11982 cp->irq_arr[1].status_blk = bp->def_status_blk;
11983 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 11984 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 11985
11986 cp->num_irq = 2;
11987}
11988
11989static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11990 void *data)
11991{
11992 struct bnx2x *bp = netdev_priv(dev);
11993 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11994
51c1a580
MS		 11995 if (ops == NULL) {
11996 BNX2X_ERR("NULL ops received\n");
993ac7b5 11997 return -EINVAL;
51c1a580 11998 }
993ac7b5 11999
993ac7b5
MC		 12000 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
12001 if (!bp->cnic_kwq)
12002 return -ENOMEM;
12003
12004 bp->cnic_kwq_cons = bp->cnic_kwq;
12005 bp->cnic_kwq_prod = bp->cnic_kwq;
12006 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
12007
12008 bp->cnic_spq_pending = 0;
12009 bp->cnic_kwq_pending = 0;
12010
12011 bp->cnic_data = data;
12012
12013 cp->num_irq = 0;
619c5cb6 12014 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 12015 cp->iro_arr = bp->iro_arr;
993ac7b5 12016
993ac7b5 12017 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 12018
993ac7b5
MC		 12019 rcu_assign_pointer(bp->cnic_ops, ops);
12020
12021 return 0;
12022}
12023
12024static int bnx2x_unregister_cnic(struct net_device *dev)
12025{
12026 struct bnx2x *bp = netdev_priv(dev);
12027 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12028
12029 mutex_lock(&bp->cnic_mutex);
993ac7b5 12030 cp->drv_state = 0;
2cfa5a04 12031 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 12032 mutex_unlock(&bp->cnic_mutex);
12033 synchronize_rcu();
12034 kfree(bp->cnic_kwq);
12035 bp->cnic_kwq = NULL;
12036
12037 return 0;
12038}
12039
12040struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
12041{
12042 struct bnx2x *bp = netdev_priv(dev);
12043 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12044
2ba45142
VZ		 12045 /* If both iSCSI and FCoE are disabled - return NULL in
12046 * order to indicate CNIC that it should not try to work
12047 * with this device.
12048 */
12049 if (NO_ISCSI(bp) && NO_FCOE(bp))
12050 return NULL;
12051
993ac7b5
MC		 12052 cp->drv_owner = THIS_MODULE;
12053 cp->chip_id = CHIP_ID(bp);
12054 cp->pdev = bp->pdev;
12055 cp->io_base = bp->regview;
12056 cp->io_base2 = bp->doorbells;
12057 cp->max_kwqe_pending = 8;
523224a3 12058 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 12059 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12060 bnx2x_cid_ilt_lines(bp);
993ac7b5 12061 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 12062 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 12063 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
12064 cp->drv_ctl = bnx2x_drv_ctl;
12065 cp->drv_register_cnic = bnx2x_register_cnic;
12066 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945 12067 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
619c5cb6
VZ		 12068 cp->iscsi_l2_client_id =
12069 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
c2bff63f
DK		 12070 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
12071
2ba45142
VZ		 12072 if (NO_ISCSI_OOO(bp))
12073 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12074
12075 if (NO_ISCSI(bp))
12076 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
12077
12078 if (NO_FCOE(bp))
12079 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
12080
51c1a580
MS		 12081 BNX2X_DEV_INFO(
12082 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 12083 cp->ctx_blk_size,
12084 cp->ctx_tbl_offset,
12085 cp->ctx_tbl_len,
12086 cp->starting_cid);
993ac7b5
MC		 12087 return cp;
12088}
12089EXPORT_SYMBOL(bnx2x_cnic_probe);
12090
12091#endif /* BCM_CNIC */
94a78b79 12092
Linux 6.x block layer and io_uring tree(s)