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bnx2x: Support mng. request for driver version
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
33d8e6a5 30#include <linux/aer.h>
a2fbb9ea
ET		 31#include <linux/init.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/dma-mapping.h>
36#include <linux/bitops.h>
37#include <linux/irq.h>
38#include <linux/delay.h>
39#include <asm/byteorder.h>
40#include <linux/time.h>
41#include <linux/ethtool.h>
42#include <linux/mii.h>
0c6671b0 43#include <linux/if_vlan.h>
a2fbb9ea 44#include <net/ip.h>
619c5cb6 45#include <net/ipv6.h>
a2fbb9ea
ET		 46#include <net/tcp.h>
47#include <net/checksum.h>
34f80b04 48#include <net/ip6_checksum.h>
a2fbb9ea
ET		 49#include <linux/workqueue.h>
50#include <linux/crc32.h>
34f80b04 51#include <linux/crc32c.h>
a2fbb9ea
ET		 52#include <linux/prefetch.h>
53#include <linux/zlib.h>
a2fbb9ea 54#include <linux/io.h>
452427b0 55#include <linux/semaphore.h>
45229b42 56#include <linux/stringify.h>
7ab24bfd 57#include <linux/vmalloc.h>
a2fbb9ea 58
a2fbb9ea
ET		 59#include "bnx2x.h"
60#include "bnx2x_init.h"
94a78b79 61#include "bnx2x_init_ops.h"
9f6c9258 62#include "bnx2x_cmn.h"
1ab4434c 63#include "bnx2x_vfpf.h"
e4901dde 64#include "bnx2x_dcb.h"
042181f5 65#include "bnx2x_sp.h"
a2fbb9ea 66
94a78b79
VZ		 67#include <linux/firmware.h>
68#include "bnx2x_fw_file_hdr.h"
69/* FW files */
45229b42
BH		 70#define FW_FILE_VERSION \
71 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
72 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
73 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
74 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 75#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
76#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 77#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 78
34f80b04
EG		 79/* Time in jiffies before concluding the transmitter is hung */
80#define TX_TIMEOUT (5*HZ)
a2fbb9ea 81
0329aba1 82static char version[] =
619c5cb6 83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85
24e3fcef 86MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 87MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
a2fbb9ea
ET		 91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 93MODULE_FIRMWARE(FW_FILE_NAME_E1);
94MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 95MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 96
a8f47eb7 97int bnx2x_num_queues;
1c8bb760 98module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
96305234
DK		 99MODULE_PARM_DESC(num_queues,
100 " Set number of queues (default is as a number of CPUs)");
555f6c78 101
19680c48 102static int disable_tpa;
1c8bb760 103module_param(disable_tpa, int, S_IRUGO);
9898f86d 104MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 105
a8f47eb7 106static int int_mode;
1c8bb760 107module_param(int_mode, int, S_IRUGO);
619c5cb6 108MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 109 "(1 INT#x; 2 MSI)");
8badd27a 110
a18f5128 111static int dropless_fc;
1c8bb760 112module_param(dropless_fc, int, S_IRUGO);
a18f5128
EG		 113MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114
8d5726c4 115static int mrrs = -1;
1c8bb760 116module_param(mrrs, int, S_IRUGO);
8d5726c4
EG		 117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
9898f86d 119static int debug;
1c8bb760 120module_param(debug, int, S_IRUGO);
9898f86d
EG		 121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
619c5cb6 123struct workqueue_struct *bnx2x_wq;
ec6ba945 124
1ef1d45a
BW		 125struct bnx2x_mac_vals {
126 u32 xmac_addr;
127 u32 xmac_val;
128 u32 emac_addr;
129 u32 emac_val;
130 u32 umac_addr;
131 u32 umac_val;
132 u32 bmac_addr;
133 u32 bmac_val[2];
134};
135
a2fbb9ea
ET		 136enum bnx2x_board_type {
137 BCM57710 = 0,
619c5cb6
VZ		 138 BCM57711,
139 BCM57711E,
140 BCM57712,
141 BCM57712_MF,
1ab4434c 142 BCM57712_VF,
619c5cb6
VZ		 143 BCM57800,
144 BCM57800_MF,
1ab4434c 145 BCM57800_VF,
619c5cb6
VZ		 146 BCM57810,
147 BCM57810_MF,
1ab4434c 148 BCM57810_VF,
c3def943
YM		 149 BCM57840_4_10,
150 BCM57840_2_20,
7e8e02df 151 BCM57840_MF,
1ab4434c 152 BCM57840_VF,
7e8e02df 153 BCM57811,
1ab4434c
AE		 154 BCM57811_MF,
155 BCM57840_O,
156 BCM57840_MFO,
157 BCM57811_VF
a2fbb9ea
ET		 158};
159
34f80b04 160/* indexed by board_type, above */
53a10565 161static struct {
a2fbb9ea 162 char *name;
0329aba1 163} board_info[] = {
1ab4434c
AE		 164 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
165 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
166 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
167 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
168 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
169 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
170 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
171 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
172 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
173 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
174 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
175 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
176 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
177 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
178 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
179 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
180 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
181 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
182 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
183 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
184 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 185};
186
619c5cb6
VZ		 187#ifndef PCI_DEVICE_ID_NX2_57710
188#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
189#endif
190#ifndef PCI_DEVICE_ID_NX2_57711
191#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
192#endif
193#ifndef PCI_DEVICE_ID_NX2_57711E
194#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
195#endif
196#ifndef PCI_DEVICE_ID_NX2_57712
197#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
198#endif
199#ifndef PCI_DEVICE_ID_NX2_57712_MF
200#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
201#endif
8395be5e
AE		 202#ifndef PCI_DEVICE_ID_NX2_57712_VF
203#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
204#endif
619c5cb6
VZ		 205#ifndef PCI_DEVICE_ID_NX2_57800
206#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
207#endif
208#ifndef PCI_DEVICE_ID_NX2_57800_MF
209#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
210#endif
8395be5e
AE		 211#ifndef PCI_DEVICE_ID_NX2_57800_VF
212#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
213#endif
619c5cb6
VZ		 214#ifndef PCI_DEVICE_ID_NX2_57810
215#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
216#endif
217#ifndef PCI_DEVICE_ID_NX2_57810_MF
218#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
219#endif
c3def943
YM		 220#ifndef PCI_DEVICE_ID_NX2_57840_O
221#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
222#endif
8395be5e
AE		 223#ifndef PCI_DEVICE_ID_NX2_57810_VF
224#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
225#endif
c3def943
YM		 226#ifndef PCI_DEVICE_ID_NX2_57840_4_10
227#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
228#endif
229#ifndef PCI_DEVICE_ID_NX2_57840_2_20
230#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
231#endif
232#ifndef PCI_DEVICE_ID_NX2_57840_MFO
233#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 234#endif
235#ifndef PCI_DEVICE_ID_NX2_57840_MF
236#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
237#endif
8395be5e
AE		 238#ifndef PCI_DEVICE_ID_NX2_57840_VF
239#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
240#endif
7e8e02df
BW		 241#ifndef PCI_DEVICE_ID_NX2_57811
242#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
243#endif
244#ifndef PCI_DEVICE_ID_NX2_57811_MF
245#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
246#endif
8395be5e
AE		 247#ifndef PCI_DEVICE_ID_NX2_57811_VF
248#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
249#endif
250
a3aa1884 251static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 273 { 0 }
274};
275
276MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
277
452427b0
YM		 278/* Global resources for unloading a previously loaded device */
279#define BNX2X_PREV_WAIT_NEEDED 1
280static DEFINE_SEMAPHORE(bnx2x_prev_sem);
281static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 282
283/* Forward declaration */
284static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
285static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
286static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
287
a2fbb9ea
ET		 288/****************************************************************************
289* General service functions
290****************************************************************************/
291
1191cb83 292static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 293 u32 addr, dma_addr_t mapping)
294{
295 REG_WR(bp, addr, U64_LO(mapping));
296 REG_WR(bp, addr + 4, U64_HI(mapping));
297}
298
1191cb83
ED		 299static void storm_memset_spq_addr(struct bnx2x *bp,
300 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 301{
302 u32 addr = XSEM_REG_FAST_MEMORY +
303 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
304
305 __storm_memset_dma_mapping(bp, addr, mapping);
306}
307
1191cb83
ED		 308static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
309 u16 pf_id)
523224a3 310{
619c5cb6
VZ		 311 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
312 pf_id);
313 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
314 pf_id);
315 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
316 pf_id);
317 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
318 pf_id);
523224a3
DK		 319}
320
1191cb83
ED		 321static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
322 u8 enable)
619c5cb6
VZ		 323{
324 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
325 enable);
326 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
327 enable);
328 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
329 enable);
330 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
331 enable);
332}
523224a3 333
1191cb83
ED		 334static void storm_memset_eq_data(struct bnx2x *bp,
335 struct event_ring_data *eq_data,
523224a3
DK		 336 u16 pfid)
337{
338 size_t size = sizeof(struct event_ring_data);
339
340 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
341
342 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
343}
344
1191cb83
ED		 345static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
346 u16 pfid)
523224a3
DK		 347{
348 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
349 REG_WR16(bp, addr, eq_prod);
350}
351
a2fbb9ea
ET		 352/* used only at init
353 * locking is done by mcp
354 */
8d96286a 355static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 356{
357 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
358 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
359 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
360 PCICFG_VENDOR_ID_OFFSET);
361}
362
a2fbb9ea
ET		 363static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
364{
365 u32 val;
366
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
368 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
369 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
370 PCICFG_VENDOR_ID_OFFSET);
371
372 return val;
373}
a2fbb9ea 374
f2e0899f
DK		 375#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
376#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
377#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
378#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
379#define DMAE_DP_DST_NONE "dst_addr [none]"
380
6bf07b8e
YM		 381static void bnx2x_dp_dmae(struct bnx2x *bp,
382 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 383{
384 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 385 int i;
fd1fc79d
AE		 386
387 switch (dmae->opcode & DMAE_COMMAND_DST) {
388 case DMAE_CMD_DST_PCI:
389 if (src_type == DMAE_CMD_SRC_PCI)
390 DP(msglvl, "DMAE: opcode 0x%08x\n"
391 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
392 "comp_addr [%x:%08x], comp_val 0x%08x\n",
393 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
394 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
395 dmae->comp_addr_hi, dmae->comp_addr_lo,
396 dmae->comp_val);
397 else
398 DP(msglvl, "DMAE: opcode 0x%08x\n"
399 "src [%08x], len [%d*4], dst [%x:%08x]\n"
400 "comp_addr [%x:%08x], comp_val 0x%08x\n",
401 dmae->opcode, dmae->src_addr_lo >> 2,
402 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
403 dmae->comp_addr_hi, dmae->comp_addr_lo,
404 dmae->comp_val);
405 break;
406 case DMAE_CMD_DST_GRC:
407 if (src_type == DMAE_CMD_SRC_PCI)
408 DP(msglvl, "DMAE: opcode 0x%08x\n"
409 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
410 "comp_addr [%x:%08x], comp_val 0x%08x\n",
411 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
412 dmae->len, dmae->dst_addr_lo >> 2,
413 dmae->comp_addr_hi, dmae->comp_addr_lo,
414 dmae->comp_val);
415 else
416 DP(msglvl, "DMAE: opcode 0x%08x\n"
417 "src [%08x], len [%d*4], dst [%08x]\n"
418 "comp_addr [%x:%08x], comp_val 0x%08x\n",
419 dmae->opcode, dmae->src_addr_lo >> 2,
420 dmae->len, dmae->dst_addr_lo >> 2,
421 dmae->comp_addr_hi, dmae->comp_addr_lo,
422 dmae->comp_val);
423 break;
424 default:
425 if (src_type == DMAE_CMD_SRC_PCI)
426 DP(msglvl, "DMAE: opcode 0x%08x\n"
427 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
428 "comp_addr [%x:%08x] comp_val 0x%08x\n",
429 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
430 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
431 dmae->comp_val);
432 else
433 DP(msglvl, "DMAE: opcode 0x%08x\n"
434 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
435 "comp_addr [%x:%08x] comp_val 0x%08x\n",
436 dmae->opcode, dmae->src_addr_lo >> 2,
437 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
438 dmae->comp_val);
439 break;
440 }
6bf07b8e
YM		 441
442 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
443 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
444 i, *(((u32 *)dmae) + i));
fd1fc79d 445}
f2e0899f 446
a2fbb9ea 447/* copy command into DMAE command memory and set DMAE command go */
6c719d00 448void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 449{
450 u32 cmd_offset;
451 int i;
452
453 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
454 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
455 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 456 }
457 REG_WR(bp, dmae_reg_go_c[idx], 1);
458}
459
f2e0899f 460u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 461{
f2e0899f
DK		 462 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
463 DMAE_CMD_C_ENABLE);
464}
ad8d3948 465
f2e0899f
DK		 466u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
467{
468 return opcode & ~DMAE_CMD_SRC_RESET;
469}
ad8d3948 470
f2e0899f
DK		 471u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
472 bool with_comp, u8 comp_type)
473{
474 u32 opcode = 0;
475
476 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
477 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 478
f2e0899f
DK		 479 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
480
481 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 482 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
483 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 484 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 485
a2fbb9ea 486#ifdef __BIG_ENDIAN
f2e0899f 487 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 488#else
f2e0899f 489 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 490#endif
f2e0899f
DK		 491 if (with_comp)
492 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
493 return opcode;
494}
495
fd1fc79d 496void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 497 struct dmae_command *dmae,
498 u8 src_type, u8 dst_type)
f2e0899f
DK		 499{
500 memset(dmae, 0, sizeof(struct dmae_command));
501
502 /* set the opcode */
503 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
504 true, DMAE_COMP_PCI);
505
506 /* fill in the completion parameters */
507 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
508 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
509 dmae->comp_val = DMAE_COMP_VAL;
510}
511
fd1fc79d 512/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 513int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
514 u32 *comp)
f2e0899f 515{
5e374b5a 516 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 517 int rc = 0;
518
6bf07b8e
YM		 519 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
520
521 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 522 * as long as this code is called both from syscall context and
523 * from ndo_set_rx_mode() flow that may be called from BH.
524 */
6e30dd4e 525 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 526
f2e0899f 527 /* reset completion */
32316a46 528 *comp = 0;
a2fbb9ea 529
f2e0899f
DK		 530 /* post the command on the channel used for initializations */
531 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 532
f2e0899f 533 /* wait for completion */
a2fbb9ea 534 udelay(5);
32316a46 535 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 536
95c6c616
AE		 537 if (!cnt ||
538 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
539 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 540 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 541 rc = DMAE_TIMEOUT;
542 goto unlock;
a2fbb9ea 543 }
ad8d3948 544 cnt--;
f2e0899f 545 udelay(50);
a2fbb9ea 546 }
32316a46 547 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 548 BNX2X_ERR("DMAE PCI error!\n");
549 rc = DMAE_PCI_ERROR;
550 }
551
f2e0899f 552unlock:
6e30dd4e 553 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 554 return rc;
555}
556
557void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
558 u32 len32)
559{
6bf07b8e 560 int rc;
f2e0899f
DK		 561 struct dmae_command dmae;
562
563 if (!bp->dmae_ready) {
564 u32 *data = bnx2x_sp(bp, wb_data[0]);
565
127a425e
AE		 566 if (CHIP_IS_E1(bp))
567 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
568 else
569 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 570 return;
571 }
572
573 /* set opcode and fixed command fields */
574 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
575
576 /* fill in addresses and len */
577 dmae.src_addr_lo = U64_LO(dma_addr);
578 dmae.src_addr_hi = U64_HI(dma_addr);
579 dmae.dst_addr_lo = dst_addr >> 2;
580 dmae.dst_addr_hi = 0;
581 dmae.len = len32;
582
f2e0899f 583 /* issue the command and wait for completion */
32316a46 584 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 585 if (rc) {
586 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 587#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 588 bnx2x_panic();
9dcd9acd 589#endif
6bf07b8e 590 }
a2fbb9ea
ET		 591}
592
c18487ee 593void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 594{
6bf07b8e 595 int rc;
5ff7b6d4 596 struct dmae_command dmae;
ad8d3948
EG		 597
598 if (!bp->dmae_ready) {
599 u32 *data = bnx2x_sp(bp, wb_data[0]);
600 int i;
601
51c1a580 602 if (CHIP_IS_E1(bp))
127a425e
AE		 603 for (i = 0; i < len32; i++)
604 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 605 else
127a425e
AE		 606 for (i = 0; i < len32; i++)
607 data[i] = REG_RD(bp, src_addr + i*4);
608
ad8d3948
EG		 609 return;
610 }
611
f2e0899f
DK		 612 /* set opcode and fixed command fields */
613 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 614
f2e0899f 615 /* fill in addresses and len */
5ff7b6d4
EG		 616 dmae.src_addr_lo = src_addr >> 2;
617 dmae.src_addr_hi = 0;
618 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
619 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
620 dmae.len = len32;
ad8d3948 621
f2e0899f 622 /* issue the command and wait for completion */
32316a46 623 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 624 if (rc) {
625 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 626#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 627 bnx2x_panic();
9dcd9acd 628#endif
c957d09f 629 }
ad8d3948
EG		 630}
631
8d96286a 632static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
633 u32 addr, u32 len)
573f2035 634{
02e3c6cb 635 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 636 int offset = 0;
637
02e3c6cb 638 while (len > dmae_wr_max) {
573f2035 639 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 640 addr + offset, dmae_wr_max);
641 offset += dmae_wr_max * 4;
642 len -= dmae_wr_max;
573f2035
EG		 643 }
644
645 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
646}
647
a2fbb9ea
ET		 648static int bnx2x_mc_assert(struct bnx2x *bp)
649{
a2fbb9ea 650 char last_idx;
34f80b04
EG		 651 int i, rc = 0;
652 u32 row0, row1, row2, row3;
653
654 /* XSTORM */
655 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
656 XSTORM_ASSERT_LIST_INDEX_OFFSET);
657 if (last_idx)
658 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
659
660 /* print the asserts */
661 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
662
663 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
664 XSTORM_ASSERT_LIST_OFFSET(i));
665 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
666 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
667 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
668 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
669 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
670 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
671
672 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 673 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 674 i, row3, row2, row1, row0);
675 rc++;
676 } else {
677 break;
678 }
679 }
680
681 /* TSTORM */
682 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
683 TSTORM_ASSERT_LIST_INDEX_OFFSET);
684 if (last_idx)
685 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
686
687 /* print the asserts */
688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
689
690 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
691 TSTORM_ASSERT_LIST_OFFSET(i));
692 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
693 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
694 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
695 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
696 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
697 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
698
699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 700 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 701 i, row3, row2, row1, row0);
702 rc++;
703 } else {
704 break;
705 }
706 }
707
708 /* CSTORM */
709 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
710 CSTORM_ASSERT_LIST_INDEX_OFFSET);
711 if (last_idx)
712 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
713
714 /* print the asserts */
715 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
716
717 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
718 CSTORM_ASSERT_LIST_OFFSET(i));
719 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
720 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
721 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
722 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
723 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
724 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
725
726 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 727 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 728 i, row3, row2, row1, row0);
729 rc++;
730 } else {
731 break;
732 }
733 }
734
735 /* USTORM */
736 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
737 USTORM_ASSERT_LIST_INDEX_OFFSET);
738 if (last_idx)
739 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
740
741 /* print the asserts */
742 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
743
744 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
745 USTORM_ASSERT_LIST_OFFSET(i));
746 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
747 USTORM_ASSERT_LIST_OFFSET(i) + 4);
748 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
749 USTORM_ASSERT_LIST_OFFSET(i) + 8);
750 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
751 USTORM_ASSERT_LIST_OFFSET(i) + 12);
752
753 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 754 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 755 i, row3, row2, row1, row0);
756 rc++;
757 } else {
758 break;
a2fbb9ea
ET		 759 }
760 }
34f80b04 761
a2fbb9ea
ET		 762 return rc;
763}
c14423fe 764
1a6974b2
YM		 765#define MCPR_TRACE_BUFFER_SIZE (0x800)
766#define SCRATCH_BUFFER_SIZE(bp) \
767 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
768
7a25cc73 769void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 770{
7a25cc73 771 u32 addr, val;
a2fbb9ea 772 u32 mark, offset;
4781bfad 773 __be32 data[9];
a2fbb9ea 774 int word;
f2e0899f 775 u32 trace_shmem_base;
2145a920
VZ		 776 if (BP_NOMCP(bp)) {
777 BNX2X_ERR("NO MCP - can not dump\n");
778 return;
779 }
7a25cc73
DK		 780 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
781 (bp->common.bc_ver & 0xff0000) >> 16,
782 (bp->common.bc_ver & 0xff00) >> 8,
783 (bp->common.bc_ver & 0xff));
784
785 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
786 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 787 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 788
f2e0899f
DK		 789 if (BP_PATH(bp) == 0)
790 trace_shmem_base = bp->common.shmem_base;
791 else
792 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 793
794 /* sanity */
795 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
796 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
797 SCRATCH_BUFFER_SIZE(bp)) {
798 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
799 trace_shmem_base);
800 return;
801 }
802
803 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 804
805 /* validate TRCB signature */
806 mark = REG_RD(bp, addr);
807 if (mark != MFW_TRACE_SIGNATURE) {
808 BNX2X_ERR("Trace buffer signature is missing.");
809 return ;
810 }
811
812 /* read cyclic buffer pointer */
813 addr += 4;
cdaa7cb8 814 mark = REG_RD(bp, addr);
1a6974b2
YM		 815 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
816 if (mark >= trace_shmem_base || mark < addr + 4) {
817 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
818 return;
819 }
7a25cc73 820 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 821
7a25cc73 822 printk("%s", lvl);
2de67439
YM		 823
824 /* dump buffer after the mark */
1a6974b2 825 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 826 for (word = 0; word < 8; word++)
cdaa7cb8 827 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 828 data[8] = 0x0;
7995c64e 829 pr_cont("%s", (char *)data);
a2fbb9ea 830 }
2de67439
YM		 831
832 /* dump buffer before the mark */
cdaa7cb8 833 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 834 for (word = 0; word < 8; word++)
cdaa7cb8 835 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 836 data[8] = 0x0;
7995c64e 837 pr_cont("%s", (char *)data);
a2fbb9ea 838 }
7a25cc73
DK		 839 printk("%s" "end of fw dump\n", lvl);
840}
841
1191cb83 842static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 843{
844 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 845}
846
823e1d90
YM		 847static void bnx2x_hc_int_disable(struct bnx2x *bp)
848{
849 int port = BP_PORT(bp);
850 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
851 u32 val = REG_RD(bp, addr);
852
853 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 854 * MSI/MSIX capability
855 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 856 */
857 if (CHIP_IS_E1(bp)) {
858 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
859 * Use mask register to prevent from HC sending interrupts
860 * after we exit the function
861 */
862 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
863
864 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
865 HC_CONFIG_0_REG_INT_LINE_EN_0 |
866 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
867 } else
868 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
869 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
870 HC_CONFIG_0_REG_INT_LINE_EN_0 |
871 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
872
873 DP(NETIF_MSG_IFDOWN,
874 "write %x to HC %d (addr 0x%x)\n",
875 val, port, addr);
876
877 /* flush all outstanding writes */
878 mmiowb();
879
880 REG_WR(bp, addr, val);
881 if (REG_RD(bp, addr) != val)
6bf07b8e 882 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 883}
884
885static void bnx2x_igu_int_disable(struct bnx2x *bp)
886{
887 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
888
889 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
890 IGU_PF_CONF_INT_LINE_EN |
891 IGU_PF_CONF_ATTN_BIT_EN);
892
893 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
894
895 /* flush all outstanding writes */
896 mmiowb();
897
898 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
899 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 900 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 901}
902
903static void bnx2x_int_disable(struct bnx2x *bp)
904{
905 if (bp->common.int_block == INT_BLOCK_HC)
906 bnx2x_hc_int_disable(bp);
907 else
908 bnx2x_igu_int_disable(bp);
909}
910
911void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 912{
913 int i;
523224a3
DK		 914 u16 j;
915 struct hc_sp_status_block_data sp_sb_data;
916 int func = BP_FUNC(bp);
917#ifdef BNX2X_STOP_ON_ERROR
918 u16 start = 0, end = 0;
6383c0b3 919 u8 cos;
523224a3 920#endif
0155a27c 921 if (IS_PF(bp) && disable_int)
823e1d90 922 bnx2x_int_disable(bp);
a2fbb9ea 923
66e855f3 924 bp->stats_state = STATS_STATE_DISABLED;
7a752993 925 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 926 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
927
a2fbb9ea
ET		 928 BNX2X_ERR("begin crash dump -----------------\n");
929
8440d2b6
EG		 930 /* Indices */
931 /* Common */
0155a27c
YM		 932 if (IS_PF(bp)) {
933 struct host_sp_status_block *def_sb = bp->def_status_blk;
934 int data_size, cstorm_offset;
935
936 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
937 bp->def_idx, bp->def_att_idx, bp->attn_state,
938 bp->spq_prod_idx, bp->stats_counter);
939 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
940 def_sb->atten_status_block.attn_bits,
941 def_sb->atten_status_block.attn_bits_ack,
942 def_sb->atten_status_block.status_block_id,
943 def_sb->atten_status_block.attn_bits_index);
944 BNX2X_ERR(" def (");
945 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
946 pr_cont("0x%x%s",
947 def_sb->sp_sb.index_values[i],
948 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
949
950 data_size = sizeof(struct hc_sp_status_block_data) /
951 sizeof(u32);
952 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
953 for (i = 0; i < data_size; i++)
954 *((u32 *)&sp_sb_data + i) =
955 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
956 i * sizeof(u32));
957
958 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
959 sp_sb_data.igu_sb_id,
960 sp_sb_data.igu_seg_id,
961 sp_sb_data.p_func.pf_id,
962 sp_sb_data.p_func.vnic_id,
963 sp_sb_data.p_func.vf_id,
964 sp_sb_data.p_func.vf_valid,
965 sp_sb_data.state);
966 }
523224a3 967
ec6ba945 968 for_each_eth_queue(bp, i) {
a2fbb9ea 969 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 970 int loop;
f2e0899f 971 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 972 struct hc_status_block_data_e1x sb_data_e1x;
973 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 974 CHIP_IS_E1x(bp) ?
975 sb_data_e1x.common.state_machine :
976 sb_data_e2.common.state_machine;
523224a3 977 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 978 CHIP_IS_E1x(bp) ?
979 sb_data_e1x.index_data :
980 sb_data_e2.index_data;
6383c0b3 981 u8 data_size, cos;
523224a3 982 u32 *sb_data_p;
6383c0b3 983 struct bnx2x_fp_txdata txdata;
523224a3
DK		 984
985 /* Rx */
51c1a580 986 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 987 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 988 fp->rx_comp_prod,
66e855f3 989 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 990 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 991 fp->rx_sge_prod, fp->last_max_sge,
523224a3 992 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 993
523224a3 994 /* Tx */
6383c0b3
AE		 995 for_each_cos_in_tx_queue(fp, cos)
996 {
65565884 997 txdata = *fp->txdata_ptr[cos];
51c1a580 998 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 999 i, txdata.tx_pkt_prod,
1000 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1001 txdata.tx_bd_cons,
1002 le16_to_cpu(*txdata.tx_cons_sb));
1003 }
523224a3 1004
619c5cb6
VZ		 1005 loop = CHIP_IS_E1x(bp) ?
1006 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1007
1008 /* host sb data */
1009
ec6ba945
VZ		 1010 if (IS_FCOE_FP(fp))
1011 continue;
55c11941 1012
523224a3
DK		 1013 BNX2X_ERR(" run indexes (");
1014 for (j = 0; j < HC_SB_MAX_SM; j++)
1015 pr_cont("0x%x%s",
1016 fp->sb_running_index[j],
1017 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1018
1019 BNX2X_ERR(" indexes (");
1020 for (j = 0; j < loop; j++)
1021 pr_cont("0x%x%s",
1022 fp->sb_index_values[j],
1023 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1024
1025 /* VF cannot access FW refelection for status block */
1026 if (IS_VF(bp))
1027 continue;
1028
523224a3 1029 /* fw sb data */
619c5cb6
VZ		 1030 data_size = CHIP_IS_E1x(bp) ?
1031 sizeof(struct hc_status_block_data_e1x) :
1032 sizeof(struct hc_status_block_data_e2);
523224a3 1033 data_size /= sizeof(u32);
619c5cb6
VZ		 1034 sb_data_p = CHIP_IS_E1x(bp) ?
1035 (u32 *)&sb_data_e1x :
1036 (u32 *)&sb_data_e2;
523224a3
DK		 1037 /* copy sb data in here */
1038 for (j = 0; j < data_size; j++)
1039 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1040 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1041 j * sizeof(u32));
1042
619c5cb6 1043 if (!CHIP_IS_E1x(bp)) {
51c1a580 1044 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1045 sb_data_e2.common.p_func.pf_id,
1046 sb_data_e2.common.p_func.vf_id,
1047 sb_data_e2.common.p_func.vf_valid,
1048 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1049 sb_data_e2.common.same_igu_sb_1b,
1050 sb_data_e2.common.state);
f2e0899f 1051 } else {
51c1a580 1052 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1053 sb_data_e1x.common.p_func.pf_id,
1054 sb_data_e1x.common.p_func.vf_id,
1055 sb_data_e1x.common.p_func.vf_valid,
1056 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1057 sb_data_e1x.common.same_igu_sb_1b,
1058 sb_data_e1x.common.state);
f2e0899f 1059 }
523224a3
DK		 1060
1061 /* SB_SMs data */
1062 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1063 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1064 j, hc_sm_p[j].__flags,
1065 hc_sm_p[j].igu_sb_id,
1066 hc_sm_p[j].igu_seg_id,
1067 hc_sm_p[j].time_to_expire,
1068 hc_sm_p[j].timer_value);
523224a3
DK		 1069 }
1070
16a5fd92 1071 /* Indices data */
523224a3 1072 for (j = 0; j < loop; j++) {
51c1a580 1073 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1074 hc_index_p[j].flags,
1075 hc_index_p[j].timeout);
1076 }
8440d2b6 1077 }
a2fbb9ea 1078
523224a3 1079#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1080 if (IS_PF(bp)) {
1081 /* event queue */
1082 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1083 for (i = 0; i < NUM_EQ_DESC; i++) {
1084 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1085
1086 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1087 i, bp->eq_ring[i].message.opcode,
1088 bp->eq_ring[i].message.error);
1089 BNX2X_ERR("data: %x %x %x\n",
1090 data[0], data[1], data[2]);
1091 }
04c46736
YM		 1092 }
1093
8440d2b6
EG		 1094 /* Rings */
1095 /* Rx */
55c11941 1096 for_each_valid_rx_queue(bp, i) {
8440d2b6 1097 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 1098
1099 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1100 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1101 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1102 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1103 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1104
c3eefaf6 1105 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1106 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1107 }
1108
3196a88a
EG		 1109 start = RX_SGE(fp->rx_sge_prod);
1110 end = RX_SGE(fp->last_max_sge);
8440d2b6 1111 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1112 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1113 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1114
c3eefaf6
EG		 1115 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1116 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1117 }
1118
a2fbb9ea
ET		 1119 start = RCQ_BD(fp->rx_comp_cons - 10);
1120 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1121 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1122 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1123
c3eefaf6
EG		 1124 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1125 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1126 }
1127 }
1128
8440d2b6 1129 /* Tx */
55c11941 1130 for_each_valid_tx_queue(bp, i) {
8440d2b6 1131 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3 1132 for_each_cos_in_tx_queue(fp, cos) {
65565884 1133 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3
AE		 1134
1135 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1136 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1137 for (j = start; j != end; j = TX_BD(j + 1)) {
1138 struct sw_tx_bd *sw_bd =
1139 &txdata->tx_buf_ring[j];
1140
51c1a580 1141 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1142 i, cos, j, sw_bd->skb,
1143 sw_bd->first_bd);
1144 }
8440d2b6 1145
6383c0b3
AE		 1146 start = TX_BD(txdata->tx_bd_cons - 10);
1147 end = TX_BD(txdata->tx_bd_cons + 254);
1148 for (j = start; j != end; j = TX_BD(j + 1)) {
1149 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1150
51c1a580 1151 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1152 i, cos, j, tx_bd[0], tx_bd[1],
1153 tx_bd[2], tx_bd[3]);
1154 }
8440d2b6
EG		 1155 }
1156 }
523224a3 1157#endif
0155a27c
YM		 1158 if (IS_PF(bp)) {
1159 bnx2x_fw_dump(bp);
1160 bnx2x_mc_assert(bp);
1161 }
a2fbb9ea 1162 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1163}
1164
619c5cb6
VZ		 1165/*
1166 * FLR Support for E2
1167 *
1168 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1169 * initialization.
1170 */
16a5fd92 1171#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1172#define FLR_WAIT_INTERVAL 50 /* usec */
1173#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1174
1175struct pbf_pN_buf_regs {
1176 int pN;
1177 u32 init_crd;
1178 u32 crd;
1179 u32 crd_freed;
1180};
1181
1182struct pbf_pN_cmd_regs {
1183 int pN;
1184 u32 lines_occup;
1185 u32 lines_freed;
1186};
1187
1188static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1189 struct pbf_pN_buf_regs *regs,
1190 u32 poll_count)
1191{
1192 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1193 u32 cur_cnt = poll_count;
1194
1195 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1196 crd = crd_start = REG_RD(bp, regs->crd);
1197 init_crd = REG_RD(bp, regs->init_crd);
1198
1199 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1200 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1201 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1202
1203 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1204 (init_crd - crd_start))) {
1205 if (cur_cnt--) {
89db4ad8 1206 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1207 crd = REG_RD(bp, regs->crd);
1208 crd_freed = REG_RD(bp, regs->crd_freed);
1209 } else {
1210 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1211 regs->pN);
1212 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1213 regs->pN, crd);
1214 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1215 regs->pN, crd_freed);
1216 break;
1217 }
1218 }
1219 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1220 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1221}
1222
1223static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1224 struct pbf_pN_cmd_regs *regs,
1225 u32 poll_count)
1226{
1227 u32 occup, to_free, freed, freed_start;
1228 u32 cur_cnt = poll_count;
1229
1230 occup = to_free = REG_RD(bp, regs->lines_occup);
1231 freed = freed_start = REG_RD(bp, regs->lines_freed);
1232
1233 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1234 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1235
1236 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1237 if (cur_cnt--) {
89db4ad8 1238 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1239 occup = REG_RD(bp, regs->lines_occup);
1240 freed = REG_RD(bp, regs->lines_freed);
1241 } else {
1242 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1243 regs->pN);
1244 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1245 regs->pN, occup);
1246 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1247 regs->pN, freed);
1248 break;
1249 }
1250 }
1251 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1252 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1253}
1254
1191cb83
ED		 1255static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1256 u32 expected, u32 poll_count)
619c5cb6
VZ		 1257{
1258 u32 cur_cnt = poll_count;
1259 u32 val;
1260
1261 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1262 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1263
1264 return val;
1265}
1266
d16132ce
AE		 1267int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1268 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1269{
1270 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1271 if (val != 0) {
1272 BNX2X_ERR("%s usage count=%d\n", msg, val);
1273 return 1;
1274 }
1275 return 0;
1276}
1277
d16132ce
AE		 1278/* Common routines with VF FLR cleanup */
1279u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1280{
1281 /* adjust polling timeout */
1282 if (CHIP_REV_IS_EMUL(bp))
1283 return FLR_POLL_CNT * 2000;
1284
1285 if (CHIP_REV_IS_FPGA(bp))
1286 return FLR_POLL_CNT * 120;
1287
1288 return FLR_POLL_CNT;
1289}
1290
d16132ce 1291void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1292{
1293 struct pbf_pN_cmd_regs cmd_regs[] = {
1294 {0, (CHIP_IS_E3B0(bp)) ?
1295 PBF_REG_TQ_OCCUPANCY_Q0 :
1296 PBF_REG_P0_TQ_OCCUPANCY,
1297 (CHIP_IS_E3B0(bp)) ?
1298 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1299 PBF_REG_P0_TQ_LINES_FREED_CNT},
1300 {1, (CHIP_IS_E3B0(bp)) ?
1301 PBF_REG_TQ_OCCUPANCY_Q1 :
1302 PBF_REG_P1_TQ_OCCUPANCY,
1303 (CHIP_IS_E3B0(bp)) ?
1304 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1305 PBF_REG_P1_TQ_LINES_FREED_CNT},
1306 {4, (CHIP_IS_E3B0(bp)) ?
1307 PBF_REG_TQ_OCCUPANCY_LB_Q :
1308 PBF_REG_P4_TQ_OCCUPANCY,
1309 (CHIP_IS_E3B0(bp)) ?
1310 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1311 PBF_REG_P4_TQ_LINES_FREED_CNT}
1312 };
1313
1314 struct pbf_pN_buf_regs buf_regs[] = {
1315 {0, (CHIP_IS_E3B0(bp)) ?
1316 PBF_REG_INIT_CRD_Q0 :
1317 PBF_REG_P0_INIT_CRD ,
1318 (CHIP_IS_E3B0(bp)) ?
1319 PBF_REG_CREDIT_Q0 :
1320 PBF_REG_P0_CREDIT,
1321 (CHIP_IS_E3B0(bp)) ?
1322 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1323 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1324 {1, (CHIP_IS_E3B0(bp)) ?
1325 PBF_REG_INIT_CRD_Q1 :
1326 PBF_REG_P1_INIT_CRD,
1327 (CHIP_IS_E3B0(bp)) ?
1328 PBF_REG_CREDIT_Q1 :
1329 PBF_REG_P1_CREDIT,
1330 (CHIP_IS_E3B0(bp)) ?
1331 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1332 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1333 {4, (CHIP_IS_E3B0(bp)) ?
1334 PBF_REG_INIT_CRD_LB_Q :
1335 PBF_REG_P4_INIT_CRD,
1336 (CHIP_IS_E3B0(bp)) ?
1337 PBF_REG_CREDIT_LB_Q :
1338 PBF_REG_P4_CREDIT,
1339 (CHIP_IS_E3B0(bp)) ?
1340 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1341 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1342 };
1343
1344 int i;
1345
1346 /* Verify the command queues are flushed P0, P1, P4 */
1347 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1348 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1349
619c5cb6
VZ		 1350 /* Verify the transmission buffers are flushed P0, P1, P4 */
1351 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1352 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1353}
1354
1355#define OP_GEN_PARAM(param) \
1356 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1357
1358#define OP_GEN_TYPE(type) \
1359 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1360
1361#define OP_GEN_AGG_VECT(index) \
1362 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1363
d16132ce 1364int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1365{
86564c3f 1366 u32 op_gen_command = 0;
619c5cb6
VZ		 1367 u32 comp_addr = BAR_CSTRORM_INTMEM +
1368 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1369 int ret = 0;
1370
1371 if (REG_RD(bp, comp_addr)) {
89db4ad8 1372 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1373 return 1;
1374 }
1375
86564c3f
YM		 1376 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1377 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1378 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1379 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1380
89db4ad8 1381 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1382 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1383
1384 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1385 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1386 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1387 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1388 bnx2x_panic();
1389 return 1;
619c5cb6 1390 }
16a5fd92 1391 /* Zero completion for next FLR */
619c5cb6
VZ		 1392 REG_WR(bp, comp_addr, 0);
1393
1394 return ret;
1395}
1396
b56e9670 1397u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1398{
619c5cb6
VZ		 1399 u16 status;
1400
2a80eebc 1401 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1402 return status & PCI_EXP_DEVSTA_TRPND;
1403}
1404
1405/* PF FLR specific routines
1406*/
1407static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1408{
619c5cb6
VZ		 1409 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1410 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1411 CFC_REG_NUM_LCIDS_INSIDE_PF,
1412 "CFC PF usage counter timed out",
1413 poll_cnt))
1414 return 1;
1415
619c5cb6
VZ		 1416 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1417 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1418 DORQ_REG_PF_USAGE_CNT,
1419 "DQ PF usage counter timed out",
1420 poll_cnt))
1421 return 1;
1422
1423 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1424 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1425 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1426 "QM PF usage counter timed out",
1427 poll_cnt))
1428 return 1;
1429
1430 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1431 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1432 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1433 "Timers VNIC usage counter timed out",
1434 poll_cnt))
1435 return 1;
1436 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1437 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1438 "Timers NUM_SCANS usage counter timed out",
1439 poll_cnt))
1440 return 1;
1441
1442 /* Wait DMAE PF usage counter to zero */
1443 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1444 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1445 "DMAE command register timed out",
619c5cb6
VZ		 1446 poll_cnt))
1447 return 1;
1448
1449 return 0;
1450}
1451
1452static void bnx2x_hw_enable_status(struct bnx2x *bp)
1453{
1454 u32 val;
1455
1456 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1457 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1458
1459 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1460 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1461
1462 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1463 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1464
1465 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1466 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1467
1468 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1469 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1470
1471 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1472 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1473
1474 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1475 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1476
1477 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1478 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1479 val);
1480}
1481
1482static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1483{
1484 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1485
1486 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1487
1488 /* Re-enable PF target read access */
1489 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1490
1491 /* Poll HW usage counters */
89db4ad8 1492 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1493 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1494 return -EBUSY;
1495
1496 /* Zero the igu 'trailing edge' and 'leading edge' */
1497
1498 /* Send the FW cleanup command */
1499 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1500 return -EBUSY;
1501
1502 /* ATC cleanup */
1503
1504 /* Verify TX hw is flushed */
1505 bnx2x_tx_hw_flushed(bp, poll_cnt);
1506
1507 /* Wait 100ms (not adjusted according to platform) */
1508 msleep(100);
1509
1510 /* Verify no pending pci transactions */
1511 if (bnx2x_is_pcie_pending(bp->pdev))
1512 BNX2X_ERR("PCIE Transactions still pending\n");
1513
1514 /* Debug */
1515 bnx2x_hw_enable_status(bp);
1516
1517 /*
1518 * Master enable - Due to WB DMAE writes performed before this
1519 * register is re-initialized as part of the regular function init
1520 */
1521 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1522
1523 return 0;
1524}
1525
f2e0899f 1526static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1527{
34f80b04 1528 int port = BP_PORT(bp);
a2fbb9ea
ET		 1529 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1530 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1531 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1532 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1533 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1534
1535 if (msix) {
8badd27a
EG		 1536 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1537 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1538 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1539 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1540 if (single_msix)
1541 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1542 } else if (msi) {
1543 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1544 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1545 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1546 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1547 } else {
1548 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1549 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1550 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1551 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1552
a0fd065c 1553 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1554 DP(NETIF_MSG_IFUP,
1555 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1556
a0fd065c 1557 REG_WR(bp, addr, val);
615f8fd9 1558
a0fd065c
DK		 1559 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1560 }
a2fbb9ea
ET		 1561 }
1562
a0fd065c
DK		 1563 if (CHIP_IS_E1(bp))
1564 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1565
51c1a580
MS		 1566 DP(NETIF_MSG_IFUP,
1567 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1568 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1569
1570 REG_WR(bp, addr, val);
37dbbf32
EG		 1571 /*
1572 * Ensure that HC_CONFIG is written before leading/trailing edge config
1573 */
1574 mmiowb();
1575 barrier();
34f80b04 1576
f2e0899f 1577 if (!CHIP_IS_E1(bp)) {
34f80b04 1578 /* init leading/trailing edge */
fb3bff17 1579 if (IS_MF(bp)) {
3395a033 1580 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1581 if (bp->port.pmf)
4acac6a5
EG		 1582 /* enable nig and gpio3 attention */
1583 val |= 0x1100;
34f80b04
EG		 1584 } else
1585 val = 0xffff;
1586
1587 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1588 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1589 }
37dbbf32
EG		 1590
1591 /* Make sure that interrupts are indeed enabled from here on */
1592 mmiowb();
a2fbb9ea
ET		 1593}
1594
f2e0899f
DK		 1595static void bnx2x_igu_int_enable(struct bnx2x *bp)
1596{
1597 u32 val;
30a5de77
DK		 1598 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1599 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1600 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1601
1602 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1603
1604 if (msix) {
1605 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1606 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1607 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1608 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1609
1610 if (single_msix)
1611 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1612 } else if (msi) {
1613 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1614 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1615 IGU_PF_CONF_ATTN_BIT_EN |
1616 IGU_PF_CONF_SINGLE_ISR_EN);
1617 } else {
1618 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1619 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1620 IGU_PF_CONF_ATTN_BIT_EN |
1621 IGU_PF_CONF_SINGLE_ISR_EN);
1622 }
1623
ebe61d80
YM		 1624 /* Clean previous status - need to configure igu prior to ack*/
1625 if ((!msix) || single_msix) {
1626 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1627 bnx2x_ack_int(bp);
1628 }
1629
1630 val |= IGU_PF_CONF_FUNC_EN;
1631
51c1a580 1632 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1633 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1634
1635 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1636
79a8557a
YM		 1637 if (val & IGU_PF_CONF_INT_LINE_EN)
1638 pci_intx(bp->pdev, true);
1639
f2e0899f
DK		 1640 barrier();
1641
1642 /* init leading/trailing edge */
1643 if (IS_MF(bp)) {
3395a033 1644 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1645 if (bp->port.pmf)
1646 /* enable nig and gpio3 attention */
1647 val |= 0x1100;
1648 } else
1649 val = 0xffff;
1650
1651 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1652 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1653
1654 /* Make sure that interrupts are indeed enabled from here on */
1655 mmiowb();
1656}
1657
1658void bnx2x_int_enable(struct bnx2x *bp)
1659{
1660 if (bp->common.int_block == INT_BLOCK_HC)
1661 bnx2x_hc_int_enable(bp);
1662 else
1663 bnx2x_igu_int_enable(bp);
1664}
1665
9f6c9258 1666void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1667{
a2fbb9ea 1668 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1669 int i, offset;
a2fbb9ea 1670
f8ef6e44
YG		 1671 if (disable_hw)
1672 /* prevent the HW from sending interrupts */
1673 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1674
1675 /* make sure all ISRs are done */
1676 if (msix) {
8badd27a
EG		 1677 synchronize_irq(bp->msix_table[0].vector);
1678 offset = 1;
55c11941
MS		 1679 if (CNIC_SUPPORT(bp))
1680 offset++;
ec6ba945 1681 for_each_eth_queue(bp, i)
754a2f52 1682 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1683 } else
1684 synchronize_irq(bp->pdev->irq);
1685
1686 /* make sure sp_task is not running */
1cf167f2 1687 cancel_delayed_work(&bp->sp_task);
3deb8167 1688 cancel_delayed_work(&bp->period_task);
1cf167f2 1689 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1690}
1691
34f80b04 1692/* fast path */
a2fbb9ea
ET		 1693
1694/*
34f80b04 1695 * General service functions
a2fbb9ea
ET		 1696 */
1697
72fd0718
VZ		 1698/* Return true if succeeded to acquire the lock */
1699static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1700{
1701 u32 lock_status;
1702 u32 resource_bit = (1 << resource);
1703 int func = BP_FUNC(bp);
1704 u32 hw_lock_control_reg;
1705
51c1a580
MS		 1706 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1707 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1708
1709 /* Validating that the resource is within range */
1710 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1711 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1712 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1713 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1714 return false;
72fd0718
VZ		 1715 }
1716
1717 if (func <= 5)
1718 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1719 else
1720 hw_lock_control_reg =
1721 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1722
1723 /* Try to acquire the lock */
1724 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1725 lock_status = REG_RD(bp, hw_lock_control_reg);
1726 if (lock_status & resource_bit)
1727 return true;
1728
51c1a580
MS		 1729 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1730 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1731 return false;
1732}
1733
c9ee9206
VZ		 1734/**
1735 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1736 *
1737 * @bp: driver handle
1738 *
1739 * Returns the recovery leader resource id according to the engine this function
1740 * belongs to. Currently only only 2 engines is supported.
1741 */
1191cb83 1742static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1743{
1744 if (BP_PATH(bp))
1745 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1746 else
1747 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1748}
1749
1750/**
2de67439 1751 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1752 *
1753 * @bp: driver handle
1754 *
2de67439 1755 * Tries to acquire a leader lock for current engine.
c9ee9206 1756 */
1191cb83 1757static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1758{
1759 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1760}
1761
619c5cb6 1762static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1763
fd1fc79d
AE		 1764/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1765static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1766{
1767 /* Set the interrupt occurred bit for the sp-task to recognize it
1768 * must ack the interrupt and transition according to the IGU
1769 * state machine.
1770 */
1771 atomic_set(&bp->interrupt_occurred, 1);
1772
1773 /* The sp_task must execute only after this bit
1774 * is set, otherwise we will get out of sync and miss all
1775 * further interrupts. Hence, the barrier.
1776 */
1777 smp_wmb();
1778
1779 /* schedule sp_task to workqueue */
1780 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1781}
3196a88a 1782
619c5cb6 1783void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1784{
1785 struct bnx2x *bp = fp->bp;
1786 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1787 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1788 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1789 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1790
34f80b04 1791 DP(BNX2X_MSG_SP,
a2fbb9ea 1792 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1793 fp->index, cid, command, bp->state,
34f80b04 1794 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1795
fd1fc79d
AE		 1796 /* If cid is within VF range, replace the slowpath object with the
1797 * one corresponding to this VF
1798 */
1799 if (cid >= BNX2X_FIRST_VF_CID &&
1800 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1801 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1802
619c5cb6
VZ		 1803 switch (command) {
1804 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1805 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1806 drv_cmd = BNX2X_Q_CMD_UPDATE;
1807 break;
d6cae238 1808
619c5cb6 1809 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1810 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1811 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1812 break;
1813
6383c0b3 1814 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1815 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1816 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1817 break;
1818
619c5cb6 1819 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1820 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1821 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1822 break;
1823
619c5cb6 1824 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1825 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1826 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1827 break;
1828
619c5cb6 1829 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1830 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1831 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1832 break;
619c5cb6 1833
14a94ebd
MK		 1834 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1835 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1836 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1837 break;
1838
619c5cb6
VZ		 1839 default:
1840 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1841 command, fp->index);
1842 return;
523224a3 1843 }
3196a88a 1844
619c5cb6
VZ		 1845 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1846 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1847 /* q_obj->complete_cmd() failure means that this was
1848 * an unexpected completion.
1849 *
1850 * In this case we don't want to increase the bp->spq_left
1851 * because apparently we haven't sent this command the first
1852 * place.
1853 */
1854#ifdef BNX2X_STOP_ON_ERROR
1855 bnx2x_panic();
1856#else
1857 return;
1858#endif
fd1fc79d
AE		 1859 /* SRIOV: reschedule any 'in_progress' operations */
1860 bnx2x_iov_sp_event(bp, cid, true);
619c5cb6 1861
8fe23fbd 1862 smp_mb__before_atomic_inc();
6e30dd4e 1863 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1864 /* push the change in bp->spq_left and towards the memory */
1865 smp_mb__after_atomic_inc();
49d66772 1866
d6cae238
VZ		 1867 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1868
a3348722
BW		 1869 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1870 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1871 /* if Q update ramrod is completed for last Q in AFEX vif set
1872 * flow, then ACK MCP at the end
1873 *
1874 * mark pending ACK to MCP bit.
1875 * prevent case that both bits are cleared.
1876 * At the end of load/unload driver checks that
2de67439 1877 * sp_state is cleared, and this order prevents
a3348722
BW		 1878 * races
1879 */
1880 smp_mb__before_clear_bit();
1881 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1882 wmb();
1883 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1884 smp_mb__after_clear_bit();
1885
fd1fc79d
AE		 1886 /* schedule the sp task as mcp ack is required */
1887 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1888 }
1889
523224a3 1890 return;
a2fbb9ea
ET		 1891}
1892
9f6c9258 1893irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1894{
555f6c78 1895 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1896 u16 status = bnx2x_ack_int(bp);
34f80b04 1897 u16 mask;
ca00392c 1898 int i;
6383c0b3 1899 u8 cos;
a2fbb9ea 1900
34f80b04 1901 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1902 if (unlikely(status == 0)) {
1903 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1904 return IRQ_NONE;
1905 }
f5372251 1906 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1907
3196a88a
EG		 1908#ifdef BNX2X_STOP_ON_ERROR
1909 if (unlikely(bp->panic))
1910 return IRQ_HANDLED;
1911#endif
1912
ec6ba945 1913 for_each_eth_queue(bp, i) {
ca00392c 1914 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1915
55c11941 1916 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1917 if (status & mask) {
619c5cb6 1918 /* Handle Rx or Tx according to SB id */
6383c0b3 1919 for_each_cos_in_tx_queue(fp, cos)
65565884 1920 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1921 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1922 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1923 status &= ~mask;
1924 }
a2fbb9ea
ET		 1925 }
1926
55c11941
MS		 1927 if (CNIC_SUPPORT(bp)) {
1928 mask = 0x2;
1929 if (status & (mask | 0x1)) {
1930 struct cnic_ops *c_ops = NULL;
993ac7b5 1931
ad9b4359
MC		 1932 rcu_read_lock();
1933 c_ops = rcu_dereference(bp->cnic_ops);
1934 if (c_ops && (bp->cnic_eth_dev.drv_state &
1935 CNIC_DRV_STATE_HANDLES_IRQ))
1936 c_ops->cnic_handler(bp->cnic_data, NULL);
1937 rcu_read_unlock();
993ac7b5 1938
55c11941
MS		 1939 status &= ~mask;
1940 }
993ac7b5 1941 }
a2fbb9ea 1942
34f80b04 1943 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1944
1945 /* schedule sp task to perform default status block work, ack
1946 * attentions and enable interrupts.
1947 */
1948 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1949
1950 status &= ~0x1;
1951 if (!status)
1952 return IRQ_HANDLED;
1953 }
1954
cdaa7cb8
VZ		 1955 if (unlikely(status))
1956 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1957 status);
a2fbb9ea 1958
c18487ee 1959 return IRQ_HANDLED;
a2fbb9ea
ET		 1960}
1961
c18487ee
YR		 1962/* Link */
1963
1964/*
1965 * General service functions
1966 */
a2fbb9ea 1967
9f6c9258 1968int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1969{
1970 u32 lock_status;
1971 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1972 int func = BP_FUNC(bp);
1973 u32 hw_lock_control_reg;
c18487ee 1974 int cnt;
a2fbb9ea 1975
c18487ee
YR		 1976 /* Validating that the resource is within range */
1977 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1978 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1979 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1980 return -EINVAL;
1981 }
a2fbb9ea 1982
4a37fb66
YG		 1983 if (func <= 5) {
1984 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1985 } else {
1986 hw_lock_control_reg =
1987 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1988 }
1989
c18487ee 1990 /* Validating that the resource is not already taken */
4a37fb66 1991 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1992 if (lock_status & resource_bit) {
51c1a580 1993 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 1994 lock_status, resource_bit);
1995 return -EEXIST;
1996 }
a2fbb9ea 1997
46230476
EG		 1998 /* Try for 5 second every 5ms */
1999 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 2000 /* Try to acquire the lock */
4a37fb66
YG		 2001 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2002 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2003 if (lock_status & resource_bit)
2004 return 0;
a2fbb9ea 2005
639d65b8 2006 usleep_range(5000, 10000);
a2fbb9ea 2007 }
51c1a580 2008 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2009 return -EAGAIN;
2010}
a2fbb9ea 2011
c9ee9206
VZ		 2012int bnx2x_release_leader_lock(struct bnx2x *bp)
2013{
2014 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2015}
2016
9f6c9258 2017int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2018{
2019 u32 lock_status;
2020 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2021 int func = BP_FUNC(bp);
2022 u32 hw_lock_control_reg;
a2fbb9ea 2023
c18487ee
YR		 2024 /* Validating that the resource is within range */
2025 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2026 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2027 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2028 return -EINVAL;
2029 }
2030
4a37fb66
YG		 2031 if (func <= 5) {
2032 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2033 } else {
2034 hw_lock_control_reg =
2035 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2036 }
2037
c18487ee 2038 /* Validating that the resource is currently taken */
4a37fb66 2039 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2040 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2041 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2042 lock_status, resource_bit);
c18487ee 2043 return -EFAULT;
a2fbb9ea
ET		 2044 }
2045
9f6c9258
DK		 2046 REG_WR(bp, hw_lock_control_reg, resource_bit);
2047 return 0;
c18487ee 2048}
a2fbb9ea 2049
4acac6a5
EG		 2050int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2051{
2052 /* The GPIO should be swapped if swap register is set and active */
2053 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2054 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2055 int gpio_shift = gpio_num +
2056 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2057 u32 gpio_mask = (1 << gpio_shift);
2058 u32 gpio_reg;
2059 int value;
2060
2061 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2062 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2063 return -EINVAL;
2064 }
2065
2066 /* read GPIO value */
2067 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2068
2069 /* get the requested pin value */
2070 if ((gpio_reg & gpio_mask) == gpio_mask)
2071 value = 1;
2072 else
2073 value = 0;
2074
2075 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2076
2077 return value;
2078}
2079
17de50b7 2080int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2081{
2082 /* The GPIO should be swapped if swap register is set and active */
2083 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2084 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2085 int gpio_shift = gpio_num +
2086 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2087 u32 gpio_mask = (1 << gpio_shift);
2088 u32 gpio_reg;
a2fbb9ea 2089
c18487ee
YR		 2090 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2091 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2092 return -EINVAL;
2093 }
a2fbb9ea 2094
4a37fb66 2095 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2096 /* read GPIO and mask except the float bits */
2097 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2098
c18487ee
YR		 2099 switch (mode) {
2100 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2101 DP(NETIF_MSG_LINK,
2102 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2103 gpio_num, gpio_shift);
2104 /* clear FLOAT and set CLR */
2105 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2106 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2107 break;
a2fbb9ea 2108
c18487ee 2109 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2110 DP(NETIF_MSG_LINK,
2111 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2112 gpio_num, gpio_shift);
2113 /* clear FLOAT and set SET */
2114 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2115 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2116 break;
a2fbb9ea 2117
17de50b7 2118 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2119 DP(NETIF_MSG_LINK,
2120 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2121 gpio_num, gpio_shift);
2122 /* set FLOAT */
2123 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2124 break;
a2fbb9ea 2125
c18487ee
YR		 2126 default:
2127 break;
a2fbb9ea
ET		 2128 }
2129
c18487ee 2130 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2131 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2132
c18487ee 2133 return 0;
a2fbb9ea
ET		 2134}
2135
0d40f0d4
YR		 2136int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2137{
2138 u32 gpio_reg = 0;
2139 int rc = 0;
2140
2141 /* Any port swapping should be handled by caller. */
2142
2143 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2144 /* read GPIO and mask except the float bits */
2145 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2146 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2147 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2148 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2149
2150 switch (mode) {
2151 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2152 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2153 /* set CLR */
2154 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2155 break;
2156
2157 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2158 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2159 /* set SET */
2160 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2161 break;
2162
2163 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2164 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2165 /* set FLOAT */
2166 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2167 break;
2168
2169 default:
2170 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2171 rc = -EINVAL;
2172 break;
2173 }
2174
2175 if (rc == 0)
2176 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2177
2178 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2179
2180 return rc;
2181}
2182
4acac6a5
EG		 2183int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2184{
2185 /* The GPIO should be swapped if swap register is set and active */
2186 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2187 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2188 int gpio_shift = gpio_num +
2189 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2190 u32 gpio_mask = (1 << gpio_shift);
2191 u32 gpio_reg;
2192
2193 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2194 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2195 return -EINVAL;
2196 }
2197
2198 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2199 /* read GPIO int */
2200 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2201
2202 switch (mode) {
2203 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2204 DP(NETIF_MSG_LINK,
2205 "Clear GPIO INT %d (shift %d) -> output low\n",
2206 gpio_num, gpio_shift);
4acac6a5
EG		 2207 /* clear SET and set CLR */
2208 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2209 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2210 break;
2211
2212 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2213 DP(NETIF_MSG_LINK,
2214 "Set GPIO INT %d (shift %d) -> output high\n",
2215 gpio_num, gpio_shift);
4acac6a5
EG		 2216 /* clear CLR and set SET */
2217 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2218 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2219 break;
2220
2221 default:
2222 break;
2223 }
2224
2225 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2226 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2227
2228 return 0;
2229}
2230
d6d99a3f 2231static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2232{
c18487ee 2233 u32 spio_reg;
a2fbb9ea 2234
d6d99a3f
YM		 2235 /* Only 2 SPIOs are configurable */
2236 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2237 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2238 return -EINVAL;
a2fbb9ea
ET		 2239 }
2240
4a37fb66 2241 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2242 /* read SPIO and mask except the float bits */
d6d99a3f 2243 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2244
c18487ee 2245 switch (mode) {
d6d99a3f
YM		 2246 case MISC_SPIO_OUTPUT_LOW:
2247 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2248 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2249 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2250 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2251 break;
a2fbb9ea 2252
d6d99a3f
YM		 2253 case MISC_SPIO_OUTPUT_HIGH:
2254 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2255 /* clear FLOAT and set SET */
d6d99a3f
YM		 2256 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2257 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2258 break;
a2fbb9ea 2259
d6d99a3f
YM		 2260 case MISC_SPIO_INPUT_HI_Z:
2261 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2262 /* set FLOAT */
d6d99a3f 2263 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2264 break;
a2fbb9ea 2265
c18487ee
YR		 2266 default:
2267 break;
a2fbb9ea
ET		 2268 }
2269
c18487ee 2270 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2271 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2272
a2fbb9ea
ET		 2273 return 0;
2274}
2275
9f6c9258 2276void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2277{
a22f0788 2278 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2279 switch (bp->link_vars.ieee_fc &
2280 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2281 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2282 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2283 ADVERTISED_Pause);
c18487ee 2284 break;
356e2385 2285
c18487ee 2286 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2287 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2288 ADVERTISED_Pause);
c18487ee 2289 break;
356e2385 2290
c18487ee 2291 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2292 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2293 break;
356e2385 2294
c18487ee 2295 default:
a22f0788 2296 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2297 ADVERTISED_Pause);
c18487ee
YR		 2298 break;
2299 }
2300}
f1410647 2301
cd1dfce2 2302static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2303{
cd1dfce2
YM		 2304 /* Initialize link parameters structure variables
2305 * It is recommended to turn off RX FC for jumbo frames
2306 * for better performance
2307 */
2308 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2309 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2310 else
2311 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2312}
a2fbb9ea 2313
9156b30b
DK		 2314static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2315{
2316 u32 pause_enabled = 0;
2317
2318 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2319 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2320 pause_enabled = 1;
2321
2322 REG_WR(bp, BAR_USTRORM_INTMEM +
2323 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2324 pause_enabled);
2325 }
2326
2327 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2328 pause_enabled ? "enabled" : "disabled");
2329}
2330
cd1dfce2
YM		 2331int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2332{
2333 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2334 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2335
2336 if (!BP_NOMCP(bp)) {
2337 bnx2x_set_requested_fc(bp);
4a37fb66 2338 bnx2x_acquire_phy_lock(bp);
b5bf9068 2339
a22f0788 2340 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2341 struct link_params *lp = &bp->link_params;
2342 lp->loopback_mode = LOOPBACK_XGXS;
2343 /* do PHY loopback at 10G speed, if possible */
2344 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2345 if (lp->speed_cap_mask[cfx_idx] &
2346 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2347 lp->req_line_speed[cfx_idx] =
2348 SPEED_10000;
2349 else
2350 lp->req_line_speed[cfx_idx] =
2351 SPEED_1000;
2352 }
a22f0788 2353 }
b5bf9068 2354
8970b2e4
MS		 2355 if (load_mode == LOAD_LOOPBACK_EXT) {
2356 struct link_params *lp = &bp->link_params;
2357 lp->loopback_mode = LOOPBACK_EXT;
2358 }
2359
19680c48 2360 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2361
4a37fb66 2362 bnx2x_release_phy_lock(bp);
a2fbb9ea 2363
9156b30b
DK		 2364 bnx2x_init_dropless_fc(bp);
2365
3c96c68b
EG		 2366 bnx2x_calc_fc_adv(bp);
2367
cd1dfce2 2368 if (bp->link_vars.link_up) {
b5bf9068 2369 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2370 bnx2x_link_report(bp);
cd1dfce2
YM		 2371 }
2372 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2373 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2374 return rc;
2375 }
f5372251 2376 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2377 return -EINVAL;
a2fbb9ea
ET		 2378}
2379
9f6c9258 2380void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2381{
19680c48 2382 if (!BP_NOMCP(bp)) {
4a37fb66 2383 bnx2x_acquire_phy_lock(bp);
19680c48 2384 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2385 bnx2x_release_phy_lock(bp);
a2fbb9ea 2386
9156b30b
DK		 2387 bnx2x_init_dropless_fc(bp);
2388
19680c48
EG		 2389 bnx2x_calc_fc_adv(bp);
2390 } else
f5372251 2391 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2392}
a2fbb9ea 2393
c18487ee
YR		 2394static void bnx2x__link_reset(struct bnx2x *bp)
2395{
19680c48 2396 if (!BP_NOMCP(bp)) {
4a37fb66 2397 bnx2x_acquire_phy_lock(bp);
5d07d868 2398 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2399 bnx2x_release_phy_lock(bp);
19680c48 2400 } else
f5372251 2401 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2402}
a2fbb9ea 2403
5d07d868
YM		 2404void bnx2x_force_link_reset(struct bnx2x *bp)
2405{
2406 bnx2x_acquire_phy_lock(bp);
2407 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2408 bnx2x_release_phy_lock(bp);
2409}
2410
a22f0788 2411u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2412{
2145a920 2413 u8 rc = 0;
a2fbb9ea 2414
2145a920
VZ		 2415 if (!BP_NOMCP(bp)) {
2416 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2417 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2418 is_serdes);
2145a920
VZ		 2419 bnx2x_release_phy_lock(bp);
2420 } else
2421 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2422
c18487ee
YR		 2423 return rc;
2424}
a2fbb9ea 2425
2691d51d
EG		 2426/* Calculates the sum of vn_min_rates.
2427 It's needed for further normalizing of the min_rates.
2428 Returns:
2429 sum of vn_min_rates.
2430 or
2431 0 - if all the min_rates are 0.
16a5fd92 2432 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2433 If not all min_rates are zero then those that are zeroes will be set to 1.
2434 */
b475d78f
YM		 2435static void bnx2x_calc_vn_min(struct bnx2x *bp,
2436 struct cmng_init_input *input)
2691d51d
EG		 2437{
2438 int all_zero = 1;
2691d51d
EG		 2439 int vn;
2440
3395a033 2441 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2442 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2443 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2444 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2445
2446 /* Skip hidden vns */
2447 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2448 vn_min_rate = 0;
2691d51d 2449 /* If min rate is zero - set it to 1 */
b475d78f 2450 else if (!vn_min_rate)
2691d51d
EG		 2451 vn_min_rate = DEF_MIN_RATE;
2452 else
2453 all_zero = 0;
2454
b475d78f 2455 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2456 }
2457
30ae438b
DK		 2458 /* if ETS or all min rates are zeros - disable fairness */
2459 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2460 input->flags.cmng_enables &=
30ae438b
DK		 2461 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2462 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2463 } else if (all_zero) {
b475d78f 2464 input->flags.cmng_enables &=
b015e3d1 2465 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2466 DP(NETIF_MSG_IFUP,
2467 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2468 } else
b475d78f 2469 input->flags.cmng_enables |=
b015e3d1 2470 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2471}
2472
b475d78f
YM		 2473static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2474 struct cmng_init_input *input)
34f80b04 2475{
b475d78f 2476 u16 vn_max_rate;
f2e0899f 2477 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2478
b475d78f 2479 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2480 vn_max_rate = 0;
b475d78f 2481 else {
faa6fcbb
DK		 2482 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2483
b475d78f 2484 if (IS_MF_SI(bp)) {
faa6fcbb
DK		 2485 /* maxCfg in percents of linkspeed */
2486 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2487 } else /* SD modes */
faa6fcbb
DK		 2488 /* maxCfg is absolute in 100Mb units */
2489 vn_max_rate = maxCfg * 100;
34f80b04 2490 }
f85582f8 2491
b475d78f 2492 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2493
b475d78f 2494 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2495}
f85582f8 2496
523224a3
DK		 2497static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2498{
2499 if (CHIP_REV_IS_SLOW(bp))
2500 return CMNG_FNS_NONE;
fb3bff17 2501 if (IS_MF(bp))
523224a3
DK		 2502 return CMNG_FNS_MINMAX;
2503
2504 return CMNG_FNS_NONE;
2505}
2506
2ae17f66 2507void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2508{
0793f83f 2509 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2510
2511 if (BP_NOMCP(bp))
16a5fd92 2512 return; /* what should be the default value in this case */
523224a3 2513
0793f83f
DK		 2514 /* For 2 port configuration the absolute function number formula
2515 * is:
2516 * abs_func = 2 * vn + BP_PORT + BP_PATH
2517 *
2518 * and there are 4 functions per port
2519 *
2520 * For 4 port configuration it is
2521 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2522 *
2523 * and there are 2 functions per port
2524 */
3395a033 2525 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2526 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2527
2528 if (func >= E1H_FUNC_MAX)
2529 break;
2530
f2e0899f 2531 bp->mf_config[vn] =
523224a3
DK		 2532 MF_CFG_RD(bp, func_mf_config[func].config);
2533 }
a3348722
BW		 2534 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2535 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2536 bp->flags |= MF_FUNC_DIS;
2537 } else {
2538 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2539 bp->flags &= ~MF_FUNC_DIS;
2540 }
523224a3
DK		 2541}
2542
2543static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2544{
b475d78f
YM		 2545 struct cmng_init_input input;
2546 memset(&input, 0, sizeof(struct cmng_init_input));
2547
2548 input.port_rate = bp->link_vars.line_speed;
523224a3 2549
568e2426 2550 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2551 int vn;
2552
523224a3
DK		 2553 /* read mf conf from shmem */
2554 if (read_cfg)
2555 bnx2x_read_mf_cfg(bp);
2556
523224a3 2557 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2558 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2559
2560 /* calculate and set min-max rate for each vn */
c4154f25 2561 if (bp->port.pmf)
3395a033 2562 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2563 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2564
2565 /* always enable rate shaping and fairness */
b475d78f 2566 input.flags.cmng_enables |=
523224a3 2567 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2568
2569 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2570 return;
2571 }
2572
2573 /* rate shaping and fairness are disabled */
2574 DP(NETIF_MSG_IFUP,
2575 "rate shaping and fairness are disabled\n");
2576}
34f80b04 2577
1191cb83
ED		 2578static void storm_memset_cmng(struct bnx2x *bp,
2579 struct cmng_init *cmng,
2580 u8 port)
2581{
2582 int vn;
2583 size_t size = sizeof(struct cmng_struct_per_port);
2584
2585 u32 addr = BAR_XSTRORM_INTMEM +
2586 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2587
2588 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2589
2590 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2591 int func = func_by_vn(bp, vn);
2592
2593 addr = BAR_XSTRORM_INTMEM +
2594 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2595 size = sizeof(struct rate_shaping_vars_per_vn);
2596 __storm_memset_struct(bp, addr, size,
2597 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2598
2599 addr = BAR_XSTRORM_INTMEM +
2600 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2601 size = sizeof(struct fairness_vars_per_vn);
2602 __storm_memset_struct(bp, addr, size,
2603 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2604 }
2605}
2606
568e2426
DK		 2607/* init cmng mode in HW according to local configuration */
2608void bnx2x_set_local_cmng(struct bnx2x *bp)
2609{
2610 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2611
2612 if (cmng_fns != CMNG_FNS_NONE) {
2613 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2614 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2615 } else {
2616 /* rate shaping and fairness are disabled */
2617 DP(NETIF_MSG_IFUP,
2618 "single function mode without fairness\n");
2619 }
2620}
2621
c18487ee
YR		 2622/* This function is called upon link interrupt */
2623static void bnx2x_link_attn(struct bnx2x *bp)
2624{
bb2a0f7a
YG		 2625 /* Make sure that we are synced with the current statistics */
2626 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2627
c18487ee 2628 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2629
9156b30b 2630 bnx2x_init_dropless_fc(bp);
1c06328c 2631
9156b30b 2632 if (bp->link_vars.link_up) {
1c06328c 2633
619c5cb6 2634 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2635 struct host_port_stats *pstats;
2636
2637 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2638 /* reset old mac stats */
bb2a0f7a
YG		 2639 memset(&(pstats->mac_stx[0]), 0,
2640 sizeof(struct mac_stx));
2641 }
f34d28ea 2642 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2643 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2644 }
2645
568e2426
DK		 2646 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2647 bnx2x_set_local_cmng(bp);
9fdc3e95 2648
2ae17f66
VZ		 2649 __bnx2x_link_report(bp);
2650
9fdc3e95
DK		 2651 if (IS_MF(bp))
2652 bnx2x_link_sync_notify(bp);
c18487ee 2653}
a2fbb9ea 2654
9f6c9258 2655void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2656{
2ae17f66 2657 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2658 return;
a2fbb9ea 2659
00253a8c 2660 /* read updated dcb configuration */
ad5afc89
AE		 2661 if (IS_PF(bp)) {
2662 bnx2x_dcbx_pmf_update(bp);
2663 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2664 if (bp->link_vars.link_up)
2665 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2666 else
2667 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2668 /* indicate link status */
2669 bnx2x_link_report(bp);
a2fbb9ea 2670
ad5afc89
AE		 2671 } else { /* VF */
2672 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2673 SUPPORTED_10baseT_Full |
2674 SUPPORTED_100baseT_Half |
2675 SUPPORTED_100baseT_Full |
2676 SUPPORTED_1000baseT_Full |
2677 SUPPORTED_2500baseX_Full |
2678 SUPPORTED_10000baseT_Full |
2679 SUPPORTED_TP |
2680 SUPPORTED_FIBRE |
2681 SUPPORTED_Autoneg |
2682 SUPPORTED_Pause |
2683 SUPPORTED_Asym_Pause);
2684 bp->port.advertising[0] = bp->port.supported[0];
2685
2686 bp->link_params.bp = bp;
2687 bp->link_params.port = BP_PORT(bp);
2688 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2689 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2690 bp->link_params.req_line_speed[0] = SPEED_10000;
2691 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2692 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2693 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2694 bp->link_vars.line_speed = SPEED_10000;
2695 bp->link_vars.link_status =
2696 (LINK_STATUS_LINK_UP |
2697 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2698 bp->link_vars.link_up = 1;
2699 bp->link_vars.duplex = DUPLEX_FULL;
2700 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2701 __bnx2x_link_report(bp);
bb2a0f7a 2702 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2703 }
a2fbb9ea 2704}
a2fbb9ea 2705
a3348722
BW		 2706static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2707 u16 vlan_val, u8 allowed_prio)
2708{
86564c3f 2709 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2710 struct bnx2x_func_afex_update_params *f_update_params =
2711 &func_params.params.afex_update;
2712
2713 func_params.f_obj = &bp->func_obj;
2714 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2715
2716 /* no need to wait for RAMROD completion, so don't
2717 * set RAMROD_COMP_WAIT flag
2718 */
2719
2720 f_update_params->vif_id = vifid;
2721 f_update_params->afex_default_vlan = vlan_val;
2722 f_update_params->allowed_priorities = allowed_prio;
2723
2724 /* if ramrod can not be sent, response to MCP immediately */
2725 if (bnx2x_func_state_change(bp, &func_params) < 0)
2726 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2727
2728 return 0;
2729}
2730
2731static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2732 u16 vif_index, u8 func_bit_map)
2733{
86564c3f 2734 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2735 struct bnx2x_func_afex_viflists_params *update_params =
2736 &func_params.params.afex_viflists;
2737 int rc;
2738 u32 drv_msg_code;
2739
2740 /* validate only LIST_SET and LIST_GET are received from switch */
2741 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2742 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2743 cmd_type);
2744
2745 func_params.f_obj = &bp->func_obj;
2746 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2747
2748 /* set parameters according to cmd_type */
2749 update_params->afex_vif_list_command = cmd_type;
86564c3f 2750 update_params->vif_list_index = vif_index;
a3348722
BW		 2751 update_params->func_bit_map =
2752 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2753 update_params->func_to_clear = 0;
2754 drv_msg_code =
2755 (cmd_type == VIF_LIST_RULE_GET) ?
2756 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2757 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2758
2759 /* if ramrod can not be sent, respond to MCP immediately for
2760 * SET and GET requests (other are not triggered from MCP)
2761 */
2762 rc = bnx2x_func_state_change(bp, &func_params);
2763 if (rc < 0)
2764 bnx2x_fw_command(bp, drv_msg_code, 0);
2765
2766 return 0;
2767}
2768
2769static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2770{
2771 struct afex_stats afex_stats;
2772 u32 func = BP_ABS_FUNC(bp);
2773 u32 mf_config;
2774 u16 vlan_val;
2775 u32 vlan_prio;
2776 u16 vif_id;
2777 u8 allowed_prio;
2778 u8 vlan_mode;
2779 u32 addr_to_write, vifid, addrs, stats_type, i;
2780
2781 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2782 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2783 DP(BNX2X_MSG_MCP,
2784 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2785 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2786 }
2787
2788 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2789 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2790 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2791 DP(BNX2X_MSG_MCP,
2792 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2793 vifid, addrs);
2794 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2795 addrs);
2796 }
2797
2798 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2799 addr_to_write = SHMEM2_RD(bp,
2800 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2801 stats_type = SHMEM2_RD(bp,
2802 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2803
2804 DP(BNX2X_MSG_MCP,
2805 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2806 addr_to_write);
2807
2808 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2809
2810 /* write response to scratchpad, for MCP */
2811 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2812 REG_WR(bp, addr_to_write + i*sizeof(u32),
2813 *(((u32 *)(&afex_stats))+i));
2814
2815 /* send ack message to MCP */
2816 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2817 }
2818
2819 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2820 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2821 bp->mf_config[BP_VN(bp)] = mf_config;
2822 DP(BNX2X_MSG_MCP,
2823 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2824 mf_config);
2825
2826 /* if VIF_SET is "enabled" */
2827 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2828 /* set rate limit directly to internal RAM */
2829 struct cmng_init_input cmng_input;
2830 struct rate_shaping_vars_per_vn m_rs_vn;
2831 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2832 u32 addr = BAR_XSTRORM_INTMEM +
2833 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2834
2835 bp->mf_config[BP_VN(bp)] = mf_config;
2836
2837 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2838 m_rs_vn.vn_counter.rate =
2839 cmng_input.vnic_max_rate[BP_VN(bp)];
2840 m_rs_vn.vn_counter.quota =
2841 (m_rs_vn.vn_counter.rate *
2842 RS_PERIODIC_TIMEOUT_USEC) / 8;
2843
2844 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2845
2846 /* read relevant values from mf_cfg struct in shmem */
2847 vif_id =
2848 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2849 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2850 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2851 vlan_val =
2852 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2853 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2854 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2855 vlan_prio = (mf_config &
2856 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2857 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2858 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2859 vlan_mode =
2860 (MF_CFG_RD(bp,
2861 func_mf_config[func].afex_config) &
2862 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2863 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2864 allowed_prio =
2865 (MF_CFG_RD(bp,
2866 func_mf_config[func].afex_config) &
2867 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2868 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2869
2870 /* send ramrod to FW, return in case of failure */
2871 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2872 allowed_prio))
2873 return;
2874
2875 bp->afex_def_vlan_tag = vlan_val;
2876 bp->afex_vlan_mode = vlan_mode;
2877 } else {
2878 /* notify link down because BP->flags is disabled */
2879 bnx2x_link_report(bp);
2880
2881 /* send INVALID VIF ramrod to FW */
2882 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2883
2884 /* Reset the default afex VLAN */
2885 bp->afex_def_vlan_tag = -1;
2886 }
2887 }
2888}
2889
34f80b04
EG		 2890static void bnx2x_pmf_update(struct bnx2x *bp)
2891{
2892 int port = BP_PORT(bp);
2893 u32 val;
2894
2895 bp->port.pmf = 1;
51c1a580 2896 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2897
3deb8167
YR		 2898 /*
2899 * We need the mb() to ensure the ordering between the writing to
2900 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2901 */
2902 smp_mb();
2903
2904 /* queue a periodic task */
2905 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2906
ef01854e
DK		 2907 bnx2x_dcbx_pmf_update(bp);
2908
34f80b04 2909 /* enable nig attention */
3395a033 2910 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2911 if (bp->common.int_block == INT_BLOCK_HC) {
2912 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2913 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2914 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2915 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2916 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2917 }
bb2a0f7a
YG		 2918
2919 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2920}
2921
c18487ee 2922/* end of Link */
a2fbb9ea
ET		 2923
2924/* slow path */
2925
2926/*
2927 * General service functions
2928 */
2929
2691d51d 2930/* send the MCP a request, block until there is a reply */
a22f0788 2931u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2932{
f2e0899f 2933 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2934 u32 seq;
2691d51d
EG		 2935 u32 rc = 0;
2936 u32 cnt = 1;
2937 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2938
c4ff7cbf 2939 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2940 seq = ++bp->fw_seq;
f2e0899f
DK		 2941 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2942 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2943
754a2f52
DK		 2944 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2945 (command | seq), param);
2691d51d
EG		 2946
2947 do {
2948 /* let the FW do it's magic ... */
2949 msleep(delay);
2950
f2e0899f 2951 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2952
c4ff7cbf
EG		 2953 /* Give the FW up to 5 second (500*10ms) */
2954 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2955
2956 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2957 cnt*delay, rc, seq);
2958
2959 /* is this a reply to our command? */
2960 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2961 rc &= FW_MSG_CODE_MASK;
2962 else {
2963 /* FW BUG! */
2964 BNX2X_ERR("FW failed to respond!\n");
2965 bnx2x_fw_dump(bp);
2966 rc = 0;
2967 }
c4ff7cbf 2968 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2969
2970 return rc;
2971}
2972
1191cb83
ED		 2973static void storm_memset_func_cfg(struct bnx2x *bp,
2974 struct tstorm_eth_function_common_config *tcfg,
2975 u16 abs_fid)
2976{
2977 size_t size = sizeof(struct tstorm_eth_function_common_config);
2978
2979 u32 addr = BAR_TSTRORM_INTMEM +
2980 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2981
2982 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2983}
2984
619c5cb6
VZ		 2985void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2986{
2987 if (CHIP_IS_E1x(bp)) {
2988 struct tstorm_eth_function_common_config tcfg = {0};
2989
2990 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2991 }
2992
2993 /* Enable the function in the FW */
2994 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2995 storm_memset_func_en(bp, p->func_id, 1);
2996
2997 /* spq */
2998 if (p->func_flgs & FUNC_FLG_SPQ) {
2999 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3000 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3001 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3002 }
3003}
3004
6383c0b3 3005/**
16a5fd92 3006 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3007 *
3008 * @bp device handle
3009 * @fp queue handle
3010 * @zero_stats TRUE if statistics zeroing is needed
3011 *
3012 * Return the flags that are common for the Tx-only and not normal connections.
3013 */
1191cb83
ED		 3014static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3015 struct bnx2x_fastpath *fp,
3016 bool zero_stats)
28912902 3017{
619c5cb6
VZ		 3018 unsigned long flags = 0;
3019
3020 /* PF driver will always initialize the Queue to an ACTIVE state */
3021 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3022
6383c0b3 3023 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3024 * parent connection). The statistics are zeroed when the parent
3025 * connection is initialized.
6383c0b3 3026 */
50f0a562
BW		 3027
3028 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3029 if (zero_stats)
3030 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3031
c14db202
YM		 3032 if (bp->flags & TX_SWITCHING)
3033 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3034
91226790 3035 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3036 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3037
823e1d90
YM		 3038#ifdef BNX2X_STOP_ON_ERROR
3039 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3040#endif
3041
6383c0b3
AE		 3042 return flags;
3043}
3044
1191cb83
ED		 3045static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3046 struct bnx2x_fastpath *fp,
3047 bool leading)
6383c0b3
AE		 3048{
3049 unsigned long flags = 0;
3050
619c5cb6
VZ		 3051 /* calculate other queue flags */
3052 if (IS_MF_SD(bp))
3053 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3054
a3348722 3055 if (IS_FCOE_FP(fp)) {
619c5cb6 3056 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3057 /* For FCoE - force usage of default priority (for afex) */
3058 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3059 }
523224a3 3060
f5219d8e 3061 if (!fp->disable_tpa) {
619c5cb6 3062 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3063 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3064 if (fp->mode == TPA_MODE_GRO)
3065 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3066 }
619c5cb6 3067
619c5cb6
VZ		 3068 if (leading) {
3069 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3070 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3071 }
523224a3 3072
619c5cb6
VZ		 3073 /* Always set HW VLAN stripping */
3074 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3075
a3348722
BW		 3076 /* configure silent vlan removal */
3077 if (IS_MF_AFEX(bp))
3078 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3079
6383c0b3 3080 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3081}
3082
619c5cb6 3083static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3084 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3085 u8 cos)
619c5cb6
VZ		 3086{
3087 gen_init->stat_id = bnx2x_stats_id(fp);
3088 gen_init->spcl_id = fp->cl_id;
3089
3090 /* Always use mini-jumbo MTU for FCoE L2 ring */
3091 if (IS_FCOE_FP(fp))
3092 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3093 else
3094 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3095
3096 gen_init->cos = cos;
619c5cb6
VZ		 3097}
3098
3099static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3100 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3101 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3102{
619c5cb6 3103 u8 max_sge = 0;
523224a3
DK		 3104 u16 sge_sz = 0;
3105 u16 tpa_agg_size = 0;
3106
523224a3 3107 if (!fp->disable_tpa) {
dfacf138
DK		 3108 pause->sge_th_lo = SGE_TH_LO(bp);
3109 pause->sge_th_hi = SGE_TH_HI(bp);
3110
3111 /* validate SGE ring has enough to cross high threshold */
3112 WARN_ON(bp->dropless_fc &&
3113 pause->sge_th_hi + FW_PREFETCH_CNT >
3114 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3115
924d75ab 3116 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3117 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3118 SGE_PAGE_SHIFT;
3119 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3120 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3121 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3122 }
3123
3124 /* pause - not for e1 */
3125 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3126 pause->bd_th_lo = BD_TH_LO(bp);
3127 pause->bd_th_hi = BD_TH_HI(bp);
3128
3129 pause->rcq_th_lo = RCQ_TH_LO(bp);
3130 pause->rcq_th_hi = RCQ_TH_HI(bp);
3131 /*
3132 * validate that rings have enough entries to cross
3133 * high thresholds
3134 */
3135 WARN_ON(bp->dropless_fc &&
3136 pause->bd_th_hi + FW_PREFETCH_CNT >
3137 bp->rx_ring_size);
3138 WARN_ON(bp->dropless_fc &&
3139 pause->rcq_th_hi + FW_PREFETCH_CNT >
3140 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3141
523224a3
DK		 3142 pause->pri_map = 1;
3143 }
3144
3145 /* rxq setup */
523224a3
DK		 3146 rxq_init->dscr_map = fp->rx_desc_mapping;
3147 rxq_init->sge_map = fp->rx_sge_mapping;
3148 rxq_init->rcq_map = fp->rx_comp_mapping;
3149 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3150
619c5cb6
VZ		 3151 /* This should be a maximum number of data bytes that may be
3152 * placed on the BD (not including paddings).
3153 */
e52fcb24 3154 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3155 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3156
523224a3 3157 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3158 rxq_init->tpa_agg_sz = tpa_agg_size;
3159 rxq_init->sge_buf_sz = sge_sz;
3160 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3161 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3162 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3163
3164 /* Maximum number or simultaneous TPA aggregation for this Queue.
3165 *
2de67439 3166 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3167 * VF driver(s) may want to define it to a smaller value.
3168 */
dfacf138 3169 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3170
523224a3
DK		 3171 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3172 rxq_init->fw_sb_id = fp->fw_sb_id;
3173
ec6ba945
VZ		 3174 if (IS_FCOE_FP(fp))
3175 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3176 else
6383c0b3 3177 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3178 /* configure silent vlan removal
3179 * if multi function mode is afex, then mask default vlan
3180 */
3181 if (IS_MF_AFEX(bp)) {
3182 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3183 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3184 }
523224a3
DK		 3185}
3186
619c5cb6 3187static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3188 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3189 u8 cos)
523224a3 3190{
65565884 3191 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3192 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3193 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3194 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3195
619c5cb6 3196 /*
16a5fd92 3197 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3198 * leading RSS client id
3199 */
3200 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3201
ec6ba945
VZ		 3202 if (IS_FCOE_FP(fp)) {
3203 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3204 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3205 }
523224a3
DK		 3206}
3207
8d96286a 3208static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3209{
3210 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 3211 struct event_ring_data eq_data = { {0} };
3212 u16 flags;
3213
619c5cb6 3214 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3215 /* reset IGU PF statistics: MSIX + ATTN */
3216 /* PF */
3217 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3218 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3219 (CHIP_MODE_IS_4_PORT(bp) ?
3220 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3221 /* ATTN */
3222 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3223 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3224 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3225 (CHIP_MODE_IS_4_PORT(bp) ?
3226 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3227 }
3228
523224a3
DK		 3229 /* function setup flags */
3230 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3231
619c5cb6
VZ		 3232 /* This flag is relevant for E1x only.
3233 * E2 doesn't have a TPA configuration in a function level.
523224a3 3234 */
619c5cb6 3235 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 3236
3237 func_init.func_flgs = flags;
3238 func_init.pf_id = BP_FUNC(bp);
3239 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3240 func_init.spq_map = bp->spq_mapping;
3241 func_init.spq_prod = bp->spq_prod_idx;
3242
3243 bnx2x_func_init(bp, &func_init);
3244
3245 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3246
3247 /*
619c5cb6
VZ		 3248 * Congestion management values depend on the link rate
3249 * There is no active link so initial link rate is set to 10 Gbps.
3250 * When the link comes up The congestion management values are
3251 * re-calculated according to the actual link rate.
3252 */
523224a3
DK		 3253 bp->link_vars.line_speed = SPEED_10000;
3254 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3255
3256 /* Only the PMF sets the HW */
3257 if (bp->port.pmf)
3258 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3259
86564c3f 3260 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3261 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3262 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3263 eq_data.producer = bp->eq_prod;
3264 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3265 eq_data.sb_id = DEF_SB_ID;
3266 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3267}
3268
523224a3
DK		 3269static void bnx2x_e1h_disable(struct bnx2x *bp)
3270{
3271 int port = BP_PORT(bp);
3272
619c5cb6 3273 bnx2x_tx_disable(bp);
523224a3
DK		 3274
3275 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3276}
3277
3278static void bnx2x_e1h_enable(struct bnx2x *bp)
3279{
3280 int port = BP_PORT(bp);
3281
3282 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3283
16a5fd92 3284 /* Tx queue should be only re-enabled */
523224a3
DK		 3285 netif_tx_wake_all_queues(bp->dev);
3286
3287 /*
3288 * Should not call netif_carrier_on since it will be called if the link
3289 * is up when checking for link state
3290 */
3291}
3292
1d187b34
BW		 3293#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3294
3295static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3296{
3297 struct eth_stats_info *ether_stat =
3298 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3299 struct bnx2x_vlan_mac_obj *mac_obj =
3300 &bp->sp_objs->mac_obj;
3301 int i;
1d187b34 3302
786fdf0b
DC		 3303 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3304 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3305
3ec9f9ca
AE		 3306 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3307 * mac_local field in ether_stat struct. The base address is offset by 2
3308 * bytes to account for the field being 8 bytes but a mac address is
3309 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3310 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3311 * allocated by the ether_stat struct, so the macs will land in their
3312 * proper positions.
3313 */
3314 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3315 memset(ether_stat->mac_local + i, 0,
3316 sizeof(ether_stat->mac_local[0]));
3317 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3318 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3319 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3320 ETH_ALEN);
1d187b34 3321 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3322 if (bp->dev->features & NETIF_F_RXCSUM)
3323 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3324 if (bp->dev->features & NETIF_F_TSO)
3325 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3326 ether_stat->feature_flags |= bp->common.boot_mode;
3327
3328 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3329
3330 ether_stat->txq_size = bp->tx_ring_size;
3331 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3332
fcf93a0a 3333#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3334 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3335#endif
1d187b34
BW		 3336}
3337
3338static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3339{
3340 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3341 struct fcoe_stats_info *fcoe_stat =
3342 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3343
55c11941
MS		 3344 if (!CNIC_LOADED(bp))
3345 return;
3346
3ec9f9ca 3347 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3348
3349 fcoe_stat->qos_priority =
3350 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3351
3352 /* insert FCoE stats from ramrod response */
3353 if (!NO_FCOE(bp)) {
3354 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3355 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3356 tstorm_queue_statistics;
3357
3358 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3359 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3360 xstorm_queue_statistics;
3361
3362 struct fcoe_statistics_params *fw_fcoe_stat =
3363 &bp->fw_stats_data->fcoe;
3364
86564c3f
YM		 3365 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3366 fcoe_stat->rx_bytes_lo,
3367 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3368
86564c3f
YM		 3369 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3370 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3371 fcoe_stat->rx_bytes_lo,
3372 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3373
86564c3f
YM		 3374 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3375 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3376 fcoe_stat->rx_bytes_lo,
3377 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3378
86564c3f
YM		 3379 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3380 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3381 fcoe_stat->rx_bytes_lo,
3382 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3383
86564c3f
YM		 3384 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3385 fcoe_stat->rx_frames_lo,
3386 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3387
86564c3f
YM		 3388 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3389 fcoe_stat->rx_frames_lo,
3390 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3391
86564c3f
YM		 3392 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3393 fcoe_stat->rx_frames_lo,
3394 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3395
86564c3f
YM		 3396 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3397 fcoe_stat->rx_frames_lo,
3398 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3399
86564c3f
YM		 3400 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3401 fcoe_stat->tx_bytes_lo,
3402 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3403
86564c3f
YM		 3404 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3405 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3406 fcoe_stat->tx_bytes_lo,
3407 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3408
86564c3f
YM		 3409 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3410 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3411 fcoe_stat->tx_bytes_lo,
3412 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3413
86564c3f
YM		 3414 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3415 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3416 fcoe_stat->tx_bytes_lo,
3417 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3418
86564c3f
YM		 3419 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3420 fcoe_stat->tx_frames_lo,
3421 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3422
86564c3f
YM		 3423 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3424 fcoe_stat->tx_frames_lo,
3425 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3426
86564c3f
YM		 3427 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3428 fcoe_stat->tx_frames_lo,
3429 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3430
86564c3f
YM		 3431 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3432 fcoe_stat->tx_frames_lo,
3433 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3434 }
3435
1d187b34
BW		 3436 /* ask L5 driver to add data to the struct */
3437 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3438}
3439
3440static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3441{
3442 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3443 struct iscsi_stats_info *iscsi_stat =
3444 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3445
55c11941
MS		 3446 if (!CNIC_LOADED(bp))
3447 return;
3448
3ec9f9ca
AE		 3449 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3450 ETH_ALEN);
1d187b34
BW		 3451
3452 iscsi_stat->qos_priority =
3453 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3454
1d187b34
BW		 3455 /* ask L5 driver to add data to the struct */
3456 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3457}
3458
0793f83f
DK		 3459/* called due to MCP event (on pmf):
3460 * reread new bandwidth configuration
3461 * configure FW
3462 * notify others function about the change
3463 */
1191cb83 3464static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3465{
3466 if (bp->link_vars.link_up) {
3467 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3468 bnx2x_link_sync_notify(bp);
3469 }
3470 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3471}
3472
1191cb83 3473static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3474{
3475 bnx2x_config_mf_bw(bp);
3476 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3477}
3478
c8c60d88
YM		 3479static void bnx2x_handle_eee_event(struct bnx2x *bp)
3480{
3481 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3482 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3483}
3484
42f8277f
YM		 3485#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3486#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3487
1d187b34
BW		 3488static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3489{
3490 enum drv_info_opcode op_code;
3491 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
42f8277f
YM		 3492 bool release = false;
3493 int wait;
1d187b34
BW		 3494
3495 /* if drv_info version supported by MFW doesn't match - send NACK */
3496 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3497 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3498 return;
3499 }
3500
3501 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3502 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3503
42f8277f
YM		 3504 /* Must prevent other flows from accessing drv_info_to_mcp */
3505 mutex_lock(&bp->drv_info_mutex);
3506
1d187b34
BW		 3507 memset(&bp->slowpath->drv_info_to_mcp, 0,
3508 sizeof(union drv_info_to_mcp));
3509
3510 switch (op_code) {
3511 case ETH_STATS_OPCODE:
3512 bnx2x_drv_info_ether_stat(bp);
3513 break;
3514 case FCOE_STATS_OPCODE:
3515 bnx2x_drv_info_fcoe_stat(bp);
3516 break;
3517 case ISCSI_STATS_OPCODE:
3518 bnx2x_drv_info_iscsi_stat(bp);
3519 break;
3520 default:
3521 /* if op code isn't supported - send NACK */
3522 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
42f8277f 3523 goto out;
1d187b34
BW		 3524 }
3525
3526 /* if we got drv_info attn from MFW then these fields are defined in
3527 * shmem2 for sure
3528 */
3529 SHMEM2_WR(bp, drv_info_host_addr_lo,
3530 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3531 SHMEM2_WR(bp, drv_info_host_addr_hi,
3532 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3533
3534 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
42f8277f
YM		 3535
3536 /* Since possible management wants both this and get_driver_version
3537 * need to wait until management notifies us it finished utilizing
3538 * the buffer.
3539 */
3540 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3541 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3542 } else if (!bp->drv_info_mng_owner) {
3543 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3544
3545 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3546 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3547
3548 /* Management is done; need to clear indication */
3549 if (indication & bit) {
3550 SHMEM2_WR(bp, mfw_drv_indication,
3551 indication & ~bit);
3552 release = true;
3553 break;
3554 }
3555
3556 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3557 }
3558 }
3559 if (!release) {
3560 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3561 bp->drv_info_mng_owner = true;
3562 }
3563
3564out:
3565 mutex_unlock(&bp->drv_info_mutex);
3566}
3567
3568static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3569{
3570 u8 vals[4];
3571 int i = 0;
3572
3573 if (bnx2x_format) {
3574 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3575 &vals[0], &vals[1], &vals[2], &vals[3]);
3576 if (i > 0)
3577 vals[0] -= '0';
3578 } else {
3579 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3580 &vals[0], &vals[1], &vals[2], &vals[3]);
3581 }
3582
3583 while (i < 4)
3584 vals[i++] = 0;
3585
3586 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3587}
3588
3589void bnx2x_update_mng_version(struct bnx2x *bp)
3590{
3591 u32 iscsiver = DRV_VER_NOT_LOADED;
3592 u32 fcoever = DRV_VER_NOT_LOADED;
3593 u32 ethver = DRV_VER_NOT_LOADED;
3594 int idx = BP_FW_MB_IDX(bp);
3595 u8 *version;
3596
3597 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3598 return;
3599
3600 mutex_lock(&bp->drv_info_mutex);
3601 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3602 if (bp->drv_info_mng_owner)
3603 goto out;
3604
3605 if (bp->state != BNX2X_STATE_OPEN)
3606 goto out;
3607
3608 /* Parse ethernet driver version */
3609 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3610 if (!CNIC_LOADED(bp))
3611 goto out;
3612
3613 /* Try getting storage driver version via cnic */
3614 memset(&bp->slowpath->drv_info_to_mcp, 0,
3615 sizeof(union drv_info_to_mcp));
3616 bnx2x_drv_info_iscsi_stat(bp);
3617 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3618 iscsiver = bnx2x_update_mng_version_utility(version, false);
3619
3620 memset(&bp->slowpath->drv_info_to_mcp, 0,
3621 sizeof(union drv_info_to_mcp));
3622 bnx2x_drv_info_fcoe_stat(bp);
3623 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3624 fcoever = bnx2x_update_mng_version_utility(version, false);
3625
3626out:
3627 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3628 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3629 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3630
3631 mutex_unlock(&bp->drv_info_mutex);
3632
3633 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3634 ethver, iscsiver, fcoever);
1d187b34
BW		 3635}
3636
523224a3
DK		 3637static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3638{
3639 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3640
3641 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3642
3643 /*
3644 * This is the only place besides the function initialization
3645 * where the bp->flags can change so it is done without any
3646 * locks
3647 */
f2e0899f 3648 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3649 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3650 bp->flags |= MF_FUNC_DIS;
3651
3652 bnx2x_e1h_disable(bp);
3653 } else {
51c1a580 3654 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3655 bp->flags &= ~MF_FUNC_DIS;
3656
3657 bnx2x_e1h_enable(bp);
3658 }
3659 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3660 }
3661 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3662 bnx2x_config_mf_bw(bp);
523224a3
DK		 3663 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3664 }
3665
3666 /* Report results to MCP */
3667 if (dcc_event)
3668 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3669 else
3670 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3671}
3672
3673/* must be called under the spq lock */
1191cb83 3674static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3675{
3676 struct eth_spe *next_spe = bp->spq_prod_bd;
3677
3678 if (bp->spq_prod_bd == bp->spq_last_bd) {
3679 bp->spq_prod_bd = bp->spq;
3680 bp->spq_prod_idx = 0;
51c1a580 3681 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3682 } else {
3683 bp->spq_prod_bd++;
3684 bp->spq_prod_idx++;
3685 }
3686 return next_spe;
3687}
3688
3689/* must be called under the spq lock */
1191cb83 3690static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3691{
3692 int func = BP_FUNC(bp);
3693
53e51e2f
VZ		 3694 /*
3695 * Make sure that BD data is updated before writing the producer:
3696 * BD data is written to the memory, the producer is read from the
3697 * memory, thus we need a full memory barrier to ensure the ordering.
3698 */
3699 mb();
28912902 3700
523224a3 3701 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3702 bp->spq_prod_idx);
28912902
MC		 3703 mmiowb();
3704}
3705
619c5cb6
VZ		 3706/**
3707 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3708 *
3709 * @cmd: command to check
3710 * @cmd_type: command type
3711 */
1191cb83 3712static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3713{
3714 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3715 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3716 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3717 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3718 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3719 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3720 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3721 return true;
3722 else
3723 return false;
619c5cb6
VZ		 3724}
3725
619c5cb6
VZ		 3726/**
3727 * bnx2x_sp_post - place a single command on an SP ring
3728 *
3729 * @bp: driver handle
3730 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3731 * @cid: SW CID the command is related to
3732 * @data_hi: command private data address (high 32 bits)
3733 * @data_lo: command private data address (low 32 bits)
3734 * @cmd_type: command type (e.g. NONE, ETH)
3735 *
3736 * SP data is handled as if it's always an address pair, thus data fields are
3737 * not swapped to little endian in upper functions. Instead this function swaps
3738 * data as if it's two u32 fields.
3739 */
9f6c9258 3740int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3741 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3742{
28912902 3743 struct eth_spe *spe;
523224a3 3744 u16 type;
619c5cb6 3745 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3746
a2fbb9ea 3747#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3748 if (unlikely(bp->panic)) {
3749 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3750 return -EIO;
51c1a580 3751 }
a2fbb9ea
ET		 3752#endif
3753
34f80b04 3754 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3755
6e30dd4e
VZ		 3756 if (common) {
3757 if (!atomic_read(&bp->eq_spq_left)) {
3758 BNX2X_ERR("BUG! EQ ring full!\n");
3759 spin_unlock_bh(&bp->spq_lock);
3760 bnx2x_panic();
3761 return -EBUSY;
3762 }
3763 } else if (!atomic_read(&bp->cq_spq_left)) {
3764 BNX2X_ERR("BUG! SPQ ring full!\n");
3765 spin_unlock_bh(&bp->spq_lock);
3766 bnx2x_panic();
3767 return -EBUSY;
a2fbb9ea 3768 }
f1410647 3769
28912902
MC		 3770 spe = bnx2x_sp_get_next(bp);
3771
a2fbb9ea 3772 /* CID needs port number to be encoded int it */
28912902 3773 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3774 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3775 HW_CID(bp, cid));
523224a3 3776
14a94ebd
MK		 3777 /* In some cases, type may already contain the func-id
3778 * mainly in SRIOV related use cases, so we add it here only
3779 * if it's not already set.
3780 */
3781 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3782 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3783 SPE_HDR_CONN_TYPE;
3784 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3785 SPE_HDR_FUNCTION_ID);
3786 } else {
3787 type = cmd_type;
3788 }
a2fbb9ea 3789
523224a3
DK		 3790 spe->hdr.type = cpu_to_le16(type);
3791
3792 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3793 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3794
d6cae238
VZ		 3795 /*
3796 * It's ok if the actual decrement is issued towards the memory
3797 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3798 * more explicit memory barrier is needed.
d6cae238
VZ		 3799 */
3800 if (common)
3801 atomic_dec(&bp->eq_spq_left);
3802 else
3803 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3804
51c1a580
MS		 3805 DP(BNX2X_MSG_SP,
3806 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3807 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3808 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3809 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3810 HW_CID(bp, cid), data_hi, data_lo, type,
3811 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3812
28912902 3813 bnx2x_sp_prod_update(bp);
34f80b04 3814 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3815 return 0;
3816}
3817
3818/* acquire split MCP access lock register */
4a37fb66 3819static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3820{
72fd0718 3821 u32 j, val;
34f80b04 3822 int rc = 0;
a2fbb9ea
ET		 3823
3824 might_sleep();
72fd0718 3825 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3826 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3827 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3828 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3829 break;
3830
639d65b8 3831 usleep_range(5000, 10000);
a2fbb9ea 3832 }
3cdeec22 3833 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3834 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3835 rc = -EBUSY;
3836 }
3837
3838 return rc;
3839}
3840
4a37fb66
YG		 3841/* release split MCP access lock register */
3842static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3843{
3cdeec22 3844 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3845}
3846
523224a3
DK		 3847#define BNX2X_DEF_SB_ATT_IDX 0x0001
3848#define BNX2X_DEF_SB_IDX 0x0002
3849
1191cb83 3850static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3851{
523224a3 3852 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3853 u16 rc = 0;
3854
3855 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3856 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3857 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3858 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3859 }
523224a3
DK		 3860
3861 if (bp->def_idx != def_sb->sp_sb.running_index) {
3862 bp->def_idx = def_sb->sp_sb.running_index;
3863 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3864 }
523224a3 3865
16a5fd92 3866 /* Do not reorder: indices reading should complete before handling */
523224a3 3867 barrier();
a2fbb9ea
ET		 3868 return rc;
3869}
3870
3871/*
3872 * slow path service functions
3873 */
3874
3875static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3876{
34f80b04 3877 int port = BP_PORT(bp);
a2fbb9ea
ET		 3878 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3879 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3880 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3881 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3882 u32 aeu_mask;
87942b46 3883 u32 nig_mask = 0;
f2e0899f 3884 u32 reg_addr;
a2fbb9ea 3885
a2fbb9ea
ET		 3886 if (bp->attn_state & asserted)
3887 BNX2X_ERR("IGU ERROR\n");
3888
3fcaf2e5
EG		 3889 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3890 aeu_mask = REG_RD(bp, aeu_addr);
3891
a2fbb9ea 3892 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3893 aeu_mask, asserted);
72fd0718 3894 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3895 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3896
3fcaf2e5
EG		 3897 REG_WR(bp, aeu_addr, aeu_mask);
3898 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3899
3fcaf2e5 3900 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3901 bp->attn_state |= asserted;
3fcaf2e5 3902 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3903
3904 if (asserted & ATTN_HARD_WIRED_MASK) {
3905 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3906
a5e9a7cf
EG		 3907 bnx2x_acquire_phy_lock(bp);
3908
877e9aa4 3909 /* save nig interrupt mask */
87942b46 3910 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3911
361c391e
YR		 3912 /* If nig_mask is not set, no need to call the update
3913 * function.
3914 */
3915 if (nig_mask) {
3916 REG_WR(bp, nig_int_mask_addr, 0);
3917
3918 bnx2x_link_attn(bp);
3919 }
a2fbb9ea
ET		 3920
3921 /* handle unicore attn? */
3922 }
3923 if (asserted & ATTN_SW_TIMER_4_FUNC)
3924 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3925
3926 if (asserted & GPIO_2_FUNC)
3927 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3928
3929 if (asserted & GPIO_3_FUNC)
3930 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3931
3932 if (asserted & GPIO_4_FUNC)
3933 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3934
3935 if (port == 0) {
3936 if (asserted & ATTN_GENERAL_ATTN_1) {
3937 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3938 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3939 }
3940 if (asserted & ATTN_GENERAL_ATTN_2) {
3941 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3942 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3943 }
3944 if (asserted & ATTN_GENERAL_ATTN_3) {
3945 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3946 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3947 }
3948 } else {
3949 if (asserted & ATTN_GENERAL_ATTN_4) {
3950 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3951 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3952 }
3953 if (asserted & ATTN_GENERAL_ATTN_5) {
3954 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3955 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3956 }
3957 if (asserted & ATTN_GENERAL_ATTN_6) {
3958 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3959 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3960 }
3961 }
3962
3963 } /* if hardwired */
3964
f2e0899f
DK		 3965 if (bp->common.int_block == INT_BLOCK_HC)
3966 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3967 COMMAND_REG_ATTN_BITS_SET);
3968 else
3969 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3970
3971 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3972 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3973 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3974
3975 /* now set back the mask */
a5e9a7cf 3976 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 3977 /* Verify that IGU ack through BAR was written before restoring
3978 * NIG mask. This loop should exit after 2-3 iterations max.
3979 */
3980 if (bp->common.int_block != INT_BLOCK_HC) {
3981 u32 cnt = 0, igu_acked;
3982 do {
3983 igu_acked = REG_RD(bp,
3984 IGU_REG_ATTENTION_ACK_BITS);
3985 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3986 (++cnt < MAX_IGU_ATTN_ACK_TO));
3987 if (!igu_acked)
3988 DP(NETIF_MSG_HW,
3989 "Failed to verify IGU ack on time\n");
3990 barrier();
3991 }
87942b46 3992 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3993 bnx2x_release_phy_lock(bp);
3994 }
a2fbb9ea
ET		 3995}
3996
1191cb83 3997static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 3998{
3999 int port = BP_PORT(bp);
b7737c9b 4000 u32 ext_phy_config;
fd4ef40d 4001 /* mark the failure */
b7737c9b
YR		 4002 ext_phy_config =
4003 SHMEM_RD(bp,
4004 dev_info.port_hw_config[port].external_phy_config);
4005
4006 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4007 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 4008 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 4009 ext_phy_config);
fd4ef40d
EG		 4010
4011 /* log the failure */
51c1a580
MS		 4012 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4013 "Please contact OEM Support for assistance\n");
8304859a 4014
16a5fd92 4015 /* Schedule device reset (unload)
8304859a
AE		 4016 * This is due to some boards consuming sufficient power when driver is
4017 * up to overheat if fan fails.
4018 */
230bb0f3 4019 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
fd4ef40d 4020}
ab6ad5a4 4021
1191cb83 4022static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 4023{
34f80b04 4024 int port = BP_PORT(bp);
877e9aa4 4025 int reg_offset;
d90d96ba 4026 u32 val;
877e9aa4 4027
34f80b04
EG		 4028 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4029 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 4030
34f80b04 4031 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 4032
4033 val = REG_RD(bp, reg_offset);
4034 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4035 REG_WR(bp, reg_offset, val);
4036
4037 BNX2X_ERR("SPIO5 hw attention\n");
4038
fd4ef40d 4039 /* Fan failure attention */
d90d96ba 4040 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 4041 bnx2x_fan_failure(bp);
877e9aa4 4042 }
34f80b04 4043
3deb8167 4044 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 4045 bnx2x_acquire_phy_lock(bp);
4046 bnx2x_handle_module_detect_int(&bp->link_params);
4047 bnx2x_release_phy_lock(bp);
4048 }
4049
34f80b04
EG		 4050 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4051
4052 val = REG_RD(bp, reg_offset);
4053 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4054 REG_WR(bp, reg_offset, val);
4055
4056 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 4057 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 4058 bnx2x_panic();
4059 }
877e9aa4
ET		 4060}
4061
1191cb83 4062static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4063{
4064 u32 val;
4065
0626b899 4066 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 4067
4068 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4069 BNX2X_ERR("DB hw attention 0x%x\n", val);
4070 /* DORQ discard attention */
4071 if (val & 0x2)
4072 BNX2X_ERR("FATAL error from DORQ\n");
4073 }
34f80b04
EG		 4074
4075 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4076
4077 int port = BP_PORT(bp);
4078 int reg_offset;
4079
4080 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4081 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4082
4083 val = REG_RD(bp, reg_offset);
4084 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4085 REG_WR(bp, reg_offset, val);
4086
4087 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 4088 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 4089 bnx2x_panic();
4090 }
877e9aa4
ET		 4091}
4092
1191cb83 4093static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4094{
4095 u32 val;
4096
4097 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4098
4099 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4100 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4101 /* CFC error attention */
4102 if (val & 0x2)
4103 BNX2X_ERR("FATAL error from CFC\n");
4104 }
4105
4106 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 4107 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4108 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4109 /* RQ_USDMDP_FIFO_OVERFLOW */
4110 if (val & 0x18000)
4111 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4112
4113 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4114 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4115 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4116 }
877e9aa4 4117 }
34f80b04
EG		 4118
4119 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4120
4121 int port = BP_PORT(bp);
4122 int reg_offset;
4123
4124 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4125 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4126
4127 val = REG_RD(bp, reg_offset);
4128 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4129 REG_WR(bp, reg_offset, val);
4130
4131 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 4132 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 4133 bnx2x_panic();
4134 }
877e9aa4
ET		 4135}
4136
1191cb83 4137static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4138{
34f80b04
EG		 4139 u32 val;
4140
877e9aa4
ET		 4141 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4142
34f80b04
EG		 4143 if (attn & BNX2X_PMF_LINK_ASSERT) {
4144 int func = BP_FUNC(bp);
4145
4146 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4147 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4148 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4149 func_mf_config[BP_ABS_FUNC(bp)].config);
4150 val = SHMEM_RD(bp,
4151 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 4152 if (val & DRV_STATUS_DCC_EVENT_MASK)
4153 bnx2x_dcc_event(bp,
4154 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 4155
4156 if (val & DRV_STATUS_SET_MF_BW)
4157 bnx2x_set_mf_bw(bp);
4158
1d187b34
BW		 4159 if (val & DRV_STATUS_DRV_INFO_REQ)
4160 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4161
4162 if (val & DRV_STATUS_VF_DISABLED)
4163 bnx2x_vf_handle_flr_event(bp);
4164
2691d51d 4165 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4166 bnx2x_pmf_update(bp);
4167
e4901dde 4168 if (bp->port.pmf &&
785b9b1a
SR		 4169 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4170 bp->dcbx_enabled > 0)
e4901dde
VZ		 4171 /* start dcbx state machine */
4172 bnx2x_dcbx_set_params(bp,
4173 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4174 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4175 bnx2x_handle_afex_cmd(bp,
4176 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4177 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4178 bnx2x_handle_eee_event(bp);
3deb8167
YR		 4179 if (bp->link_vars.periodic_flags &
4180 PERIODIC_FLAGS_LINK_EVENT) {
4181 /* sync with link */
4182 bnx2x_acquire_phy_lock(bp);
4183 bp->link_vars.periodic_flags &=
4184 ~PERIODIC_FLAGS_LINK_EVENT;
4185 bnx2x_release_phy_lock(bp);
4186 if (IS_MF(bp))
4187 bnx2x_link_sync_notify(bp);
4188 bnx2x_link_report(bp);
4189 }
4190 /* Always call it here: bnx2x_link_report() will
4191 * prevent the link indication duplication.
4192 */
4193 bnx2x__link_status_update(bp);
34f80b04 4194 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4195
4196 BNX2X_ERR("MC assert!\n");
d6cae238 4197 bnx2x_mc_assert(bp);
877e9aa4
ET		 4198 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4199 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4200 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4201 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4202 bnx2x_panic();
4203
4204 } else if (attn & BNX2X_MCP_ASSERT) {
4205
4206 BNX2X_ERR("MCP assert!\n");
4207 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4208 bnx2x_fw_dump(bp);
877e9aa4
ET		 4209
4210 } else
4211 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4212 }
4213
4214 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4215 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4216 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4217 val = CHIP_IS_E1(bp) ? 0 :
4218 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4219 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4220 }
4221 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4222 val = CHIP_IS_E1(bp) ? 0 :
4223 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4224 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4225 }
877e9aa4 4226 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4227 }
4228}
4229
c9ee9206
VZ		 4230/*
4231 * Bits map:
4232 * 0-7 - Engine0 load counter.
4233 * 8-15 - Engine1 load counter.
4234 * 16 - Engine0 RESET_IN_PROGRESS bit.
4235 * 17 - Engine1 RESET_IN_PROGRESS bit.
4236 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4237 * on the engine
4238 * 19 - Engine1 ONE_IS_LOADED.
4239 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4240 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4241 * just the one belonging to its engine).
4242 *
4243 */
4244#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4245
4246#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4247#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4248#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4249#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4250#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4251#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4252#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4253
4254/*
4255 * Set the GLOBAL_RESET bit.
4256 *
4257 * Should be run under rtnl lock
4258 */
4259void bnx2x_set_reset_global(struct bnx2x *bp)
4260{
f16da43b
AE		 4261 u32 val;
4262 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4263 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4264 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4265 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4266}
4267
4268/*
4269 * Clear the GLOBAL_RESET bit.
4270 *
4271 * Should be run under rtnl lock
4272 */
1191cb83 4273static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4274{
f16da43b
AE		 4275 u32 val;
4276 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4277 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4278 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4279 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4280}
f85582f8 4281
72fd0718 4282/*
c9ee9206
VZ		 4283 * Checks the GLOBAL_RESET bit.
4284 *
72fd0718
VZ		 4285 * should be run under rtnl lock
4286 */
1191cb83 4287static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4288{
3cdeec22 4289 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4290
4291 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4292 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4293}
4294
4295/*
4296 * Clear RESET_IN_PROGRESS bit for the current engine.
4297 *
4298 * Should be run under rtnl lock
4299 */
1191cb83 4300static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4301{
f16da43b 4302 u32 val;
c9ee9206
VZ		 4303 u32 bit = BP_PATH(bp) ?
4304 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4305 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4306 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4307
4308 /* Clear the bit */
4309 val &= ~bit;
4310 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4311
4312 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4313}
4314
4315/*
c9ee9206
VZ		 4316 * Set RESET_IN_PROGRESS for the current engine.
4317 *
72fd0718
VZ		 4318 * should be run under rtnl lock
4319 */
c9ee9206 4320void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4321{
f16da43b 4322 u32 val;
c9ee9206
VZ		 4323 u32 bit = BP_PATH(bp) ?
4324 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4325 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4326 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4327
4328 /* Set the bit */
4329 val |= bit;
4330 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4331 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4332}
4333
4334/*
c9ee9206 4335 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4336 * should be run under rtnl lock
4337 */
c9ee9206 4338bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4339{
3cdeec22 4340 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4341 u32 bit = engine ?
4342 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4343
4344 /* return false if bit is set */
4345 return (val & bit) ? false : true;
72fd0718
VZ		 4346}
4347
4348/*
889b9af3 4349 * set pf load for the current pf.
c9ee9206 4350 *
72fd0718
VZ		 4351 * should be run under rtnl lock
4352 */
889b9af3 4353void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4354{
f16da43b 4355 u32 val1, val;
c9ee9206
VZ		 4356 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4357 BNX2X_PATH0_LOAD_CNT_MASK;
4358 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4359 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4360
f16da43b
AE		 4361 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4362 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4363
51c1a580 4364 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4365
c9ee9206
VZ		 4366 /* get the current counter value */
4367 val1 = (val & mask) >> shift;
4368
889b9af3
AE		 4369 /* set bit of that PF */
4370 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4371
4372 /* clear the old value */
4373 val &= ~mask;
4374
4375 /* set the new one */
4376 val |= ((val1 << shift) & mask);
4377
4378 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4379 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4380}
4381
c9ee9206 4382/**
889b9af3 4383 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4384 *
4385 * @bp: driver handle
4386 *
4387 * Should be run under rtnl lock.
4388 * Decrements the load counter for the current engine. Returns
889b9af3 4389 * whether other functions are still loaded
72fd0718 4390 */
889b9af3 4391bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4392{
f16da43b 4393 u32 val1, val;
c9ee9206
VZ		 4394 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4395 BNX2X_PATH0_LOAD_CNT_MASK;
4396 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4397 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4398
f16da43b
AE		 4399 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4400 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4401 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4402
c9ee9206
VZ		 4403 /* get the current counter value */
4404 val1 = (val & mask) >> shift;
4405
889b9af3
AE		 4406 /* clear bit of that PF */
4407 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4408
4409 /* clear the old value */
4410 val &= ~mask;
4411
4412 /* set the new one */
4413 val |= ((val1 << shift) & mask);
4414
4415 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4416 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4417 return val1 != 0;
72fd0718
VZ		 4418}
4419
4420/*
889b9af3 4421 * Read the load status for the current engine.
c9ee9206 4422 *
72fd0718
VZ		 4423 * should be run under rtnl lock
4424 */
1191cb83 4425static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4426{
c9ee9206
VZ		 4427 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4428 BNX2X_PATH0_LOAD_CNT_MASK);
4429 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4430 BNX2X_PATH0_LOAD_CNT_SHIFT);
4431 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4432
51c1a580 4433 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4434
4435 val = (val & mask) >> shift;
4436
51c1a580
MS		 4437 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4438 engine, val);
c9ee9206 4439
889b9af3 4440 return val != 0;
72fd0718
VZ		 4441}
4442
6bf07b8e
YM		 4443static void _print_parity(struct bnx2x *bp, u32 reg)
4444{
4445 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4446}
4447
1191cb83 4448static void _print_next_block(int idx, const char *blk)
72fd0718 4449{
f1deab50 4450 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4451}
4452
4293b9f5
DK		 4453static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4454 int *par_num, bool print)
72fd0718 4455{
4293b9f5
DK		 4456 u32 cur_bit;
4457 bool res;
4458 int i;
4459
4460 res = false;
4461
72fd0718 4462 for (i = 0; sig; i++) {
4293b9f5 4463 cur_bit = (0x1UL << i);
72fd0718 4464 if (sig & cur_bit) {
4293b9f5
DK		 4465 res |= true; /* Each bit is real error! */
4466
4467 if (print) {
4468 switch (cur_bit) {
4469 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4470 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4471 _print_parity(bp,
4472 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4473 break;
4474 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4475 _print_next_block((*par_num)++,
4476 "PARSER");
6bf07b8e 4477 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4478 break;
4479 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4480 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4481 _print_parity(bp,
4482 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4483 break;
4484 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4485 _print_next_block((*par_num)++,
c9ee9206 4486 "SEARCHER");
6bf07b8e 4487 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4488 break;
4489 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4490 _print_next_block((*par_num)++, "TCM");
4491 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4492 break;
4493 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4494 _print_next_block((*par_num)++,
4495 "TSEMI");
6bf07b8e
YM		 4496 _print_parity(bp,
4497 TSEM_REG_TSEM_PRTY_STS_0);
4498 _print_parity(bp,
4499 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4500 break;
4501 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4502 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4503 _print_parity(bp, GRCBASE_XPB +
4504 PB_REG_PB_PRTY_STS);
4293b9f5 4505 break;
6bf07b8e 4506 }
72fd0718
VZ		 4507 }
4508
4509 /* Clear the bit */
4510 sig &= ~cur_bit;
4511 }
4512 }
4513
4293b9f5 4514 return res;
72fd0718
VZ		 4515}
4516
4293b9f5
DK		 4517static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4518 int *par_num, bool *global,
6bf07b8e 4519 bool print)
72fd0718 4520{
4293b9f5
DK		 4521 u32 cur_bit;
4522 bool res;
4523 int i;
4524
4525 res = false;
4526
72fd0718 4527 for (i = 0; sig; i++) {
4293b9f5 4528 cur_bit = (0x1UL << i);
72fd0718 4529 if (sig & cur_bit) {
4293b9f5 4530 res |= true; /* Each bit is real error! */
72fd0718 4531 switch (cur_bit) {
c9ee9206 4532 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4533 if (print) {
4293b9f5 4534 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4535 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4536 }
72fd0718
VZ		 4537 break;
4538 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4539 if (print) {
4293b9f5 4540 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4541 _print_parity(bp, QM_REG_QM_PRTY_STS);
4542 }
c9ee9206
VZ		 4543 break;
4544 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4545 if (print) {
4293b9f5 4546 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4547 _print_parity(bp, TM_REG_TM_PRTY_STS);
4548 }
72fd0718
VZ		 4549 break;
4550 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4551 if (print) {
4293b9f5 4552 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4553 _print_parity(bp,
4554 XSDM_REG_XSDM_PRTY_STS);
4555 }
c9ee9206
VZ		 4556 break;
4557 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4558 if (print) {
4293b9f5 4559 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4560 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4561 }
72fd0718
VZ		 4562 break;
4563 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4564 if (print) {
4293b9f5
DK		 4565 _print_next_block((*par_num)++,
4566 "XSEMI");
6bf07b8e
YM		 4567 _print_parity(bp,
4568 XSEM_REG_XSEM_PRTY_STS_0);
4569 _print_parity(bp,
4570 XSEM_REG_XSEM_PRTY_STS_1);
4571 }
72fd0718
VZ		 4572 break;
4573 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4574 if (print) {
4293b9f5 4575 _print_next_block((*par_num)++,
c9ee9206 4576 "DOORBELLQ");
6bf07b8e
YM		 4577 _print_parity(bp,
4578 DORQ_REG_DORQ_PRTY_STS);
4579 }
c9ee9206
VZ		 4580 break;
4581 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4582 if (print) {
4293b9f5 4583 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4584 if (CHIP_IS_E1x(bp)) {
4585 _print_parity(bp,
4586 NIG_REG_NIG_PRTY_STS);
4587 } else {
4588 _print_parity(bp,
4589 NIG_REG_NIG_PRTY_STS_0);
4590 _print_parity(bp,
4591 NIG_REG_NIG_PRTY_STS_1);
4592 }
4593 }
72fd0718
VZ		 4594 break;
4595 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4596 if (print)
4293b9f5 4597 _print_next_block((*par_num)++,
c9ee9206
VZ		 4598 "VAUX PCI CORE");
4599 *global = true;
72fd0718
VZ		 4600 break;
4601 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4602 if (print) {
4293b9f5
DK		 4603 _print_next_block((*par_num)++,
4604 "DEBUG");
6bf07b8e
YM		 4605 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4606 }
72fd0718
VZ		 4607 break;
4608 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4609 if (print) {
4293b9f5 4610 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4611 _print_parity(bp,
4612 USDM_REG_USDM_PRTY_STS);
4613 }
72fd0718 4614 break;
8736c826 4615 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4616 if (print) {
4293b9f5 4617 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4618 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4619 }
8736c826 4620 break;
72fd0718 4621 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4622 if (print) {
4293b9f5
DK		 4623 _print_next_block((*par_num)++,
4624 "USEMI");
6bf07b8e
YM		 4625 _print_parity(bp,
4626 USEM_REG_USEM_PRTY_STS_0);
4627 _print_parity(bp,
4628 USEM_REG_USEM_PRTY_STS_1);
4629 }
72fd0718
VZ		 4630 break;
4631 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4632 if (print) {
4293b9f5 4633 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4634 _print_parity(bp, GRCBASE_UPB +
4635 PB_REG_PB_PRTY_STS);
4636 }
72fd0718
VZ		 4637 break;
4638 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4639 if (print) {
4293b9f5 4640 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4641 _print_parity(bp,
4642 CSDM_REG_CSDM_PRTY_STS);
4643 }
72fd0718 4644 break;
8736c826 4645 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4646 if (print) {
4293b9f5 4647 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4648 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4649 }
8736c826 4650 break;
72fd0718
VZ		 4651 }
4652
4653 /* Clear the bit */
4654 sig &= ~cur_bit;
4655 }
4656 }
4657
4293b9f5 4658 return res;
72fd0718
VZ		 4659}
4660
4293b9f5
DK		 4661static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4662 int *par_num, bool print)
72fd0718 4663{
4293b9f5
DK		 4664 u32 cur_bit;
4665 bool res;
4666 int i;
4667
4668 res = false;
4669
72fd0718 4670 for (i = 0; sig; i++) {
4293b9f5 4671 cur_bit = (0x1UL << i);
72fd0718 4672 if (sig & cur_bit) {
4293b9f5
DK		 4673 res |= true; /* Each bit is real error! */
4674 if (print) {
4675 switch (cur_bit) {
4676 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4677 _print_next_block((*par_num)++,
4678 "CSEMI");
6bf07b8e
YM		 4679 _print_parity(bp,
4680 CSEM_REG_CSEM_PRTY_STS_0);
4681 _print_parity(bp,
4682 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4683 break;
4684 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4685 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4686 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4687 _print_parity(bp,
4688 PXP2_REG_PXP2_PRTY_STS_0);
4689 _print_parity(bp,
4690 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4691 break;
4692 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4693 _print_next_block((*par_num)++,
4694 "PXPPCICLOCKCLIENT");
4695 break;
4696 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4697 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4698 _print_parity(bp,
4699 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4700 break;
4701 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4702 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4703 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4704 break;
4705 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4706 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4707 _print_parity(bp,
4708 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4709 break;
4710 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4711 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4712 if (CHIP_IS_E1x(bp))
4713 _print_parity(bp,
4714 HC_REG_HC_PRTY_STS);
4715 else
4716 _print_parity(bp,
4717 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4718 break;
4719 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4720 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4721 _print_parity(bp,
4722 MISC_REG_MISC_PRTY_STS);
4293b9f5 4723 break;
6bf07b8e 4724 }
72fd0718
VZ		 4725 }
4726
4727 /* Clear the bit */
4728 sig &= ~cur_bit;
4729 }
4730 }
4731
4293b9f5 4732 return res;
72fd0718
VZ		 4733}
4734
4293b9f5
DK		 4735static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4736 int *par_num, bool *global,
4737 bool print)
72fd0718 4738{
4293b9f5
DK		 4739 bool res = false;
4740 u32 cur_bit;
4741 int i;
4742
72fd0718 4743 for (i = 0; sig; i++) {
4293b9f5 4744 cur_bit = (0x1UL << i);
72fd0718
VZ		 4745 if (sig & cur_bit) {
4746 switch (cur_bit) {
4747 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4748 if (print)
4293b9f5
DK		 4749 _print_next_block((*par_num)++,
4750 "MCP ROM");
c9ee9206 4751 *global = true;
4293b9f5 4752 res |= true;
72fd0718
VZ		 4753 break;
4754 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4755 if (print)
4293b9f5 4756 _print_next_block((*par_num)++,
c9ee9206
VZ		 4757 "MCP UMP RX");
4758 *global = true;
4293b9f5 4759 res |= true;
72fd0718
VZ		 4760 break;
4761 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4762 if (print)
4293b9f5 4763 _print_next_block((*par_num)++,
c9ee9206
VZ		 4764 "MCP UMP TX");
4765 *global = true;
4293b9f5 4766 res |= true;
72fd0718
VZ		 4767 break;
4768 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206 4769 if (print)
4293b9f5 4770 _print_next_block((*par_num)++,
c9ee9206 4771 "MCP SCPAD");
4293b9f5
DK		 4772 /* clear latched SCPAD PATIRY from MCP */
4773 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4774 1UL << 10);
72fd0718
VZ		 4775 break;
4776 }
4777
4778 /* Clear the bit */
4779 sig &= ~cur_bit;
4780 }
4781 }
4782
4293b9f5 4783 return res;
72fd0718
VZ		 4784}
4785
4293b9f5
DK		 4786static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4787 int *par_num, bool print)
8736c826 4788{
4293b9f5
DK		 4789 u32 cur_bit;
4790 bool res;
4791 int i;
4792
4793 res = false;
4794
8736c826 4795 for (i = 0; sig; i++) {
4293b9f5 4796 cur_bit = (0x1UL << i);
8736c826 4797 if (sig & cur_bit) {
4293b9f5
DK		 4798 res |= true; /* Each bit is real error! */
4799 if (print) {
4800 switch (cur_bit) {
4801 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4802 _print_next_block((*par_num)++,
4803 "PGLUE_B");
6bf07b8e 4804 _print_parity(bp,
4293b9f5
DK		 4805 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4806 break;
4807 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4808 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4809 _print_parity(bp,
4810 ATC_REG_ATC_PRTY_STS);
4293b9f5 4811 break;
6bf07b8e 4812 }
8736c826 4813 }
8736c826
VZ		 4814 /* Clear the bit */
4815 sig &= ~cur_bit;
4816 }
4817 }
4818
4293b9f5 4819 return res;
8736c826
VZ		 4820}
4821
1191cb83
ED		 4822static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4823 u32 *sig)
72fd0718 4824{
4293b9f5
DK		 4825 bool res = false;
4826
8736c826
VZ		 4827 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4828 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4829 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4830 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4831 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4832 int par_num = 0;
51c1a580
MS		 4833 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4834 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4835 sig[0] & HW_PRTY_ASSERT_SET_0,
4836 sig[1] & HW_PRTY_ASSERT_SET_1,
4837 sig[2] & HW_PRTY_ASSERT_SET_2,
4838 sig[3] & HW_PRTY_ASSERT_SET_3,
4839 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4840 if (print)
4841 netdev_err(bp->dev,
4842 "Parity errors detected in blocks: ");
4293b9f5
DK		 4843 res |= bnx2x_check_blocks_with_parity0(bp,
4844 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4845 res |= bnx2x_check_blocks_with_parity1(bp,
4846 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4847 res |= bnx2x_check_blocks_with_parity2(bp,
4848 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4849 res |= bnx2x_check_blocks_with_parity3(bp,
4850 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4851 res |= bnx2x_check_blocks_with_parity4(bp,
4852 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4853
c9ee9206
VZ		 4854 if (print)
4855 pr_cont("\n");
4293b9f5 4856 }
8736c826 4857
4293b9f5 4858 return res;
72fd0718
VZ		 4859}
4860
c9ee9206
VZ		 4861/**
4862 * bnx2x_chk_parity_attn - checks for parity attentions.
4863 *
4864 * @bp: driver handle
4865 * @global: true if there was a global attention
4866 * @print: show parity attention in syslog
4867 */
4868bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4869{
8736c826 4870 struct attn_route attn = { {0} };
72fd0718
VZ		 4871 int port = BP_PORT(bp);
4872
4873 attn.sig[0] = REG_RD(bp,
4874 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4875 port*4);
4876 attn.sig[1] = REG_RD(bp,
4877 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4878 port*4);
4879 attn.sig[2] = REG_RD(bp,
4880 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4881 port*4);
4882 attn.sig[3] = REG_RD(bp,
4883 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4884 port*4);
0a5ccb75
YM		 4885 /* Since MCP attentions can't be disabled inside the block, we need to
4886 * read AEU registers to see whether they're currently disabled
4887 */
4888 attn.sig[3] &= ((REG_RD(bp,
4889 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4890 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4891 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4892 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 4893
8736c826
VZ		 4894 if (!CHIP_IS_E1x(bp))
4895 attn.sig[4] = REG_RD(bp,
4896 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4897 port*4);
4898
4899 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4900}
4901
1191cb83 4902static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 4903{
4904 u32 val;
4905 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4906
4907 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4908 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4909 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 4910 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 4911 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 4912 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 4913 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 4914 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 4915 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 4916 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 4917 if (val &
4918 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 4919 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 4920 if (val &
4921 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 4922 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 4923 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 4924 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 4925 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 4926 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 4927 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 4928 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 4929 }
4930 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4931 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4932 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4933 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4934 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4935 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 4936 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 4937 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 4938 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 4939 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 4940 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 4941 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4942 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4943 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 4944 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 4945 }
4946
4947 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4948 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4949 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4950 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4951 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4952 }
f2e0899f
DK		 4953}
4954
72fd0718
VZ		 4955static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4956{
4957 struct attn_route attn, *group_mask;
34f80b04 4958 int port = BP_PORT(bp);
877e9aa4 4959 int index;
a2fbb9ea
ET		 4960 u32 reg_addr;
4961 u32 val;
3fcaf2e5 4962 u32 aeu_mask;
c9ee9206 4963 bool global = false;
a2fbb9ea
ET		 4964
4965 /* need to take HW lock because MCP or other port might also
4966 try to handle this event */
4a37fb66 4967 bnx2x_acquire_alr(bp);
a2fbb9ea 4968
c9ee9206
VZ		 4969 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4970#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4971 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4972 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4973 /* Disable HW interrupts */
4974 bnx2x_int_disable(bp);
72fd0718
VZ		 4975 /* In case of parity errors don't handle attentions so that
4976 * other function would "see" parity errors.
4977 */
c9ee9206
VZ		 4978#else
4979 bnx2x_panic();
4980#endif
4981 bnx2x_release_alr(bp);
72fd0718
VZ		 4982 return;
4983 }
4984
a2fbb9ea
ET		 4985 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4986 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4987 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4988 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4989 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4990 attn.sig[4] =
4991 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4992 else
4993 attn.sig[4] = 0;
4994
4995 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4996 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4997
4998 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4999 if (deasserted & (1 << index)) {
72fd0718 5000 group_mask = &bp->attn_group[index];
a2fbb9ea 5001
51c1a580 5002 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 5003 index,
5004 group_mask->sig[0], group_mask->sig[1],
5005 group_mask->sig[2], group_mask->sig[3],
5006 group_mask->sig[4]);
a2fbb9ea 5007
f2e0899f
DK		 5008 bnx2x_attn_int_deasserted4(bp,
5009 attn.sig[4] & group_mask->sig[4]);
877e9aa4 5010 bnx2x_attn_int_deasserted3(bp,
72fd0718 5011 attn.sig[3] & group_mask->sig[3]);
877e9aa4 5012 bnx2x_attn_int_deasserted1(bp,
72fd0718 5013 attn.sig[1] & group_mask->sig[1]);
877e9aa4 5014 bnx2x_attn_int_deasserted2(bp,
72fd0718 5015 attn.sig[2] & group_mask->sig[2]);
877e9aa4 5016 bnx2x_attn_int_deasserted0(bp,
72fd0718 5017 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 5018 }
5019 }
5020
4a37fb66 5021 bnx2x_release_alr(bp);
a2fbb9ea 5022
f2e0899f
DK		 5023 if (bp->common.int_block == INT_BLOCK_HC)
5024 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5025 COMMAND_REG_ATTN_BITS_CLR);
5026 else
5027 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 5028
5029 val = ~deasserted;
f2e0899f
DK		 5030 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5031 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 5032 REG_WR(bp, reg_addr, val);
a2fbb9ea 5033
a2fbb9ea 5034 if (~bp->attn_state & deasserted)
3fcaf2e5 5035 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 5036
5037 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5038 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5039
3fcaf2e5
EG		 5040 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5041 aeu_mask = REG_RD(bp, reg_addr);
5042
5043 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5044 aeu_mask, deasserted);
72fd0718 5045 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 5046 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 5047
3fcaf2e5
EG		 5048 REG_WR(bp, reg_addr, aeu_mask);
5049 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 5050
5051 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5052 bp->attn_state &= ~deasserted;
5053 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5054}
5055
5056static void bnx2x_attn_int(struct bnx2x *bp)
5057{
5058 /* read local copy of bits */
68d59484
EG		 5059 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5060 attn_bits);
5061 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5062 attn_bits_ack);
a2fbb9ea
ET		 5063 u32 attn_state = bp->attn_state;
5064
5065 /* look for changed bits */
5066 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5067 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5068
5069 DP(NETIF_MSG_HW,
5070 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5071 attn_bits, attn_ack, asserted, deasserted);
5072
5073 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 5074 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 5075
5076 /* handle bits that were raised */
5077 if (asserted)
5078 bnx2x_attn_int_asserted(bp, asserted);
5079
5080 if (deasserted)
5081 bnx2x_attn_int_deasserted(bp, deasserted);
5082}
5083
619c5cb6
VZ		 5084void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5085 u16 index, u8 op, u8 update)
5086{
dc1ba591
AE		 5087 u32 igu_addr = bp->igu_base_addr;
5088 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 5089 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5090 igu_addr);
5091}
5092
1191cb83 5093static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 5094{
5095 /* No memory barriers */
5096 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5097 mmiowb(); /* keep prod updates ordered */
5098}
5099
523224a3
DK		 5100static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5101 union event_ring_elem *elem)
5102{
619c5cb6
VZ		 5103 u8 err = elem->message.error;
5104
523224a3 5105 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 5106 (cid < bp->cnic_eth_dev.starting_cid &&
5107 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5108 return 1;
5109
5110 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5111
619c5cb6
VZ		 5112 if (unlikely(err)) {
5113
523224a3
DK		 5114 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5115 cid);
823e1d90 5116 bnx2x_panic_dump(bp, false);
523224a3 5117 }
619c5cb6 5118 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5119 return 0;
5120}
523224a3 5121
1191cb83 5122static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5123{
5124 struct bnx2x_mcast_ramrod_params rparam;
5125 int rc;
5126
5127 memset(&rparam, 0, sizeof(rparam));
5128
5129 rparam.mcast_obj = &bp->mcast_obj;
5130
5131 netif_addr_lock_bh(bp->dev);
5132
5133 /* Clear pending state for the last command */
5134 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5135
5136 /* If there are pending mcast commands - send them */
5137 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5138 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5139 if (rc < 0)
5140 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5141 rc);
5142 }
5143
5144 netif_addr_unlock_bh(bp->dev);
5145}
5146
1191cb83
ED		 5147static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5148 union event_ring_elem *elem)
619c5cb6
VZ		 5149{
5150 unsigned long ramrod_flags = 0;
5151 int rc = 0;
5152 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5153 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5154
5155 /* Always push next commands out, don't wait here */
5156 __set_bit(RAMROD_CONT, &ramrod_flags);
5157
86564c3f
YM		 5158 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5159 >> BNX2X_SWCID_SHIFT) {
619c5cb6 5160 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5161 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5162 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5163 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5164 else
15192a8c 5165 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6
VZ		 5166
5167 break;
619c5cb6 5168 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5169 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5170 /* This is only relevant for 57710 where multicast MACs are
5171 * configured as unicast MACs using the same ramrod.
5172 */
5173 bnx2x_handle_mcast_eqe(bp);
5174 return;
5175 default:
5176 BNX2X_ERR("Unsupported classification command: %d\n",
5177 elem->message.data.eth_event.echo);
5178 return;
5179 }
5180
5181 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5182
5183 if (rc < 0)
5184 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5185 else if (rc > 0)
5186 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5187}
5188
619c5cb6 5189static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5190
1191cb83 5191static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5192{
5193 netif_addr_lock_bh(bp->dev);
5194
5195 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5196
5197 /* Send rx_mode command again if was requested */
5198 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5199 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5200 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5201 &bp->sp_state))
5202 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5203 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5204 &bp->sp_state))
5205 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5206
5207 netif_addr_unlock_bh(bp->dev);
5208}
5209
1191cb83 5210static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5211 union event_ring_elem *elem)
5212{
5213 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5214 DP(BNX2X_MSG_SP,
5215 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5216 elem->message.data.vif_list_event.func_bit_map);
5217 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5218 elem->message.data.vif_list_event.func_bit_map);
5219 } else if (elem->message.data.vif_list_event.echo ==
5220 VIF_LIST_RULE_SET) {
5221 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5222 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5223 }
5224}
5225
5226/* called with rtnl_lock */
1191cb83 5227static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5228{
5229 int q, rc;
5230 struct bnx2x_fastpath *fp;
5231 struct bnx2x_queue_state_params queue_params = {NULL};
5232 struct bnx2x_queue_update_params *q_update_params =
5233 &queue_params.params.update;
5234
2de67439 5235 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5236 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5237
5238 /* set silent vlan removal values according to vlan mode */
5239 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5240 &q_update_params->update_flags);
5241 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5242 &q_update_params->update_flags);
5243 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5244
5245 /* in access mode mark mask and value are 0 to strip all vlans */
5246 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5247 q_update_params->silent_removal_value = 0;
5248 q_update_params->silent_removal_mask = 0;
5249 } else {
5250 q_update_params->silent_removal_value =
5251 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5252 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5253 }
5254
5255 for_each_eth_queue(bp, q) {
5256 /* Set the appropriate Queue object */
5257 fp = &bp->fp[q];
15192a8c 5258 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5259
5260 /* send the ramrod */
5261 rc = bnx2x_queue_state_change(bp, &queue_params);
5262 if (rc < 0)
5263 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5264 q);
5265 }
5266
fea75645 5267 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5268 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5269 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5270
5271 /* clear pending completion bit */
5272 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5273
5274 /* mark latest Q bit */
5275 smp_mb__before_clear_bit();
5276 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5277 smp_mb__after_clear_bit();
5278
5279 /* send Q update ramrod for FCoE Q */
5280 rc = bnx2x_queue_state_change(bp, &queue_params);
5281 if (rc < 0)
5282 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5283 q);
5284 } else {
5285 /* If no FCoE ring - ACK MCP now */
5286 bnx2x_link_report(bp);
5287 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5288 }
a3348722
BW		 5289}
5290
1191cb83 5291static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5292 struct bnx2x *bp, u32 cid)
5293{
94f05b0f 5294 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5295
5296 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5297 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5298 else
15192a8c 5299 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5300}
5301
523224a3
DK		 5302static void bnx2x_eq_int(struct bnx2x *bp)
5303{
5304 u16 hw_cons, sw_cons, sw_prod;
5305 union event_ring_elem *elem;
55c11941 5306 u8 echo;
523224a3
DK		 5307 u32 cid;
5308 u8 opcode;
fd1fc79d 5309 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5310 struct bnx2x_queue_sp_obj *q_obj;
5311 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5312 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5313
5314 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5315
5316 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5317 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5318 * condition below will be met. The next element is the size of a
5319 * regular element and hence incrementing by 1
5320 */
5321 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5322 hw_cons++;
5323
25985edc 5324 /* This function may never run in parallel with itself for a
523224a3
DK		 5325 * specific bp, thus there is no need in "paired" read memory
5326 * barrier here.
5327 */
5328 sw_cons = bp->eq_cons;
5329 sw_prod = bp->eq_prod;
5330
d6cae238 5331 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5332 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5333
5334 for (; sw_cons != hw_cons;
5335 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5336
523224a3
DK		 5337 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5338
fd1fc79d
AE		 5339 rc = bnx2x_iov_eq_sp_event(bp, elem);
5340 if (!rc) {
5341 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5342 rc);
5343 goto next_spqe;
5344 }
523224a3 5345
86564c3f
YM		 5346 /* elem CID originates from FW; actually LE */
5347 cid = SW_CID((__force __le32)
5348 elem->message.data.cfc_del_event.cid);
5349 opcode = elem->message.opcode;
523224a3
DK		 5350
5351 /* handle eq element */
5352 switch (opcode) {
fd1fc79d
AE		 5353 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5354 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5355 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5356 continue;
5357
523224a3 5358 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5359 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5360 "got statistics comp event %d\n",
5361 bp->stats_comp++);
523224a3 5362 /* nothing to do with stats comp */
d6cae238 5363 goto next_spqe;
523224a3
DK		 5364
5365 case EVENT_RING_OPCODE_CFC_DEL:
5366 /* handle according to cid range */
5367 /*
5368 * we may want to verify here that the bp state is
5369 * HALTING
5370 */
d6cae238 5371 DP(BNX2X_MSG_SP,
523224a3 5372 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5373
5374 if (CNIC_LOADED(bp) &&
5375 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5376 goto next_spqe;
55c11941 5377
619c5cb6
VZ		 5378 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5379
5380 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5381 break;
5382
523224a3 5383 goto next_spqe;
e4901dde
VZ		 5384
5385 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5386 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5387 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5388 if (f_obj->complete_cmd(bp, f_obj,
5389 BNX2X_F_CMD_TX_STOP))
5390 break;
e4901dde 5391 goto next_spqe;
619c5cb6 5392
e4901dde 5393 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5394 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5395 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5396 if (f_obj->complete_cmd(bp, f_obj,
5397 BNX2X_F_CMD_TX_START))
5398 break;
e4901dde 5399 goto next_spqe;
55c11941 5400
a3348722 5401 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5402 echo = elem->message.data.function_update_event.echo;
5403 if (echo == SWITCH_UPDATE) {
5404 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5405 "got FUNC_SWITCH_UPDATE ramrod\n");
5406 if (f_obj->complete_cmd(
5407 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5408 break;
a3348722 5409
55c11941 5410 } else {
230bb0f3
YM		 5411 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5412
55c11941
MS		 5413 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5414 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5415 f_obj->complete_cmd(bp, f_obj,
5416 BNX2X_F_CMD_AFEX_UPDATE);
5417
5418 /* We will perform the Queues update from
5419 * sp_rtnl task as all Queue SP operations
5420 * should run under rtnl_lock.
5421 */
230bb0f3 5422 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
55c11941 5423 }
a3348722 5424
a3348722
BW		 5425 goto next_spqe;
5426
5427 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5428 f_obj->complete_cmd(bp, f_obj,
5429 BNX2X_F_CMD_AFEX_VIFLISTS);
5430 bnx2x_after_afex_vif_lists(bp, elem);
5431 goto next_spqe;
619c5cb6 5432 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5433 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5434 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5435 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5436 break;
5437
5438 goto next_spqe;
5439
5440 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5441 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5442 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5443 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5444 break;
5445
5446 goto next_spqe;
523224a3
DK		 5447 }
5448
5449 switch (opcode | bp->state) {
619c5cb6
VZ		 5450 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5451 BNX2X_STATE_OPEN):
5452 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5453 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 5454 cid = elem->message.data.eth_event.echo &
5455 BNX2X_SWCID_MASK;
d6cae238 5456 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 5457 cid);
5458 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5459 break;
5460
619c5cb6
VZ		 5461 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5462 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5463 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5464 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5465 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5466 BNX2X_STATE_OPEN):
5467 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5468 BNX2X_STATE_DIAG):
5469 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5470 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5471 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 5472 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5473 break;
5474
619c5cb6
VZ		 5475 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5476 BNX2X_STATE_OPEN):
5477 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5478 BNX2X_STATE_DIAG):
5479 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5480 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5481 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5482 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5483 break;
5484
619c5cb6
VZ		 5485 case (EVENT_RING_OPCODE_FILTERS_RULES |
5486 BNX2X_STATE_OPEN):
5487 case (EVENT_RING_OPCODE_FILTERS_RULES |
5488 BNX2X_STATE_DIAG):
5489 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5490 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5491 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5492 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5493 break;
5494 default:
5495 /* unknown event log error and continue */
619c5cb6
VZ		 5496 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5497 elem->message.opcode, bp->state);
523224a3
DK		 5498 }
5499next_spqe:
5500 spqe_cnt++;
5501 } /* for */
5502
8fe23fbd 5503 smp_mb__before_atomic_inc();
6e30dd4e 5504 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5505
5506 bp->eq_cons = sw_cons;
5507 bp->eq_prod = sw_prod;
5508 /* Make sure that above mem writes were issued towards the memory */
5509 smp_wmb();
5510
5511 /* update producer */
5512 bnx2x_update_eq_prod(bp, bp->eq_prod);
5513}
5514
a2fbb9ea
ET		 5515static void bnx2x_sp_task(struct work_struct *work)
5516{
1cf167f2 5517 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5518
fd1fc79d 5519 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5520
16a5fd92 5521 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5522 smp_rmb();
5523 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5524
fd1fc79d
AE		 5525 /* what work needs to be performed? */
5526 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5527
fd1fc79d
AE		 5528 DP(BNX2X_MSG_SP, "status %x\n", status);
5529 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5530 atomic_set(&bp->interrupt_occurred, 0);
5531
5532 /* HW attentions */
5533 if (status & BNX2X_DEF_SB_ATT_IDX) {
5534 bnx2x_attn_int(bp);
5535 status &= ~BNX2X_DEF_SB_ATT_IDX;
5536 }
5537
5538 /* SP events: STAT_QUERY and others */
5539 if (status & BNX2X_DEF_SB_IDX) {
5540 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5541
55c11941 5542 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5543 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5544 /* Prevent local bottom-halves from running as
5545 * we are going to change the local NAPI list.
5546 */
5547 local_bh_disable();
5548 napi_schedule(&bnx2x_fcoe(bp, napi));
5549 local_bh_enable();
5550 }
5551
5552 /* Handle EQ completions */
5553 bnx2x_eq_int(bp);
5554 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5555 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5556
5557 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5558 }
55c11941 5559
fd1fc79d
AE		 5560 /* if status is non zero then perhaps something went wrong */
5561 if (unlikely(status))
5562 DP(BNX2X_MSG_SP,
5563 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5564
fd1fc79d
AE		 5565 /* ack status block only if something was actually handled */
5566 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5567 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5568 }
5569
fd1fc79d
AE		 5570 /* must be called after the EQ processing (since eq leads to sriov
5571 * ramrod completion flows).
5572 * This flow may have been scheduled by the arrival of a ramrod
5573 * completion, or by the sriov code rescheduling itself.
5574 */
5575 bnx2x_iov_sp_task(bp);
a3348722
BW		 5576
5577 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5578 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5579 &bp->sp_state)) {
5580 bnx2x_link_report(bp);
5581 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5582 }
a2fbb9ea
ET		 5583}
5584
9f6c9258 5585irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5586{
5587 struct net_device *dev = dev_instance;
5588 struct bnx2x *bp = netdev_priv(dev);
5589
523224a3
DK		 5590 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5591 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5592
5593#ifdef BNX2X_STOP_ON_ERROR
5594 if (unlikely(bp->panic))
5595 return IRQ_HANDLED;
5596#endif
5597
55c11941 5598 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5599 struct cnic_ops *c_ops;
5600
5601 rcu_read_lock();
5602 c_ops = rcu_dereference(bp->cnic_ops);
5603 if (c_ops)
5604 c_ops->cnic_handler(bp->cnic_data, NULL);
5605 rcu_read_unlock();
5606 }
55c11941 5607
fd1fc79d
AE		 5608 /* schedule sp task to perform default status block work, ack
5609 * attentions and enable interrupts.
5610 */
5611 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5612
5613 return IRQ_HANDLED;
5614}
5615
5616/* end of slow path */
5617
619c5cb6
VZ		 5618void bnx2x_drv_pulse(struct bnx2x *bp)
5619{
5620 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5621 bp->fw_drv_pulse_wr_seq);
5622}
5623
a2fbb9ea
ET		 5624static void bnx2x_timer(unsigned long data)
5625{
5626 struct bnx2x *bp = (struct bnx2x *) data;
5627
5628 if (!netif_running(bp->dev))
5629 return;
5630
67c431a5
AE		 5631 if (IS_PF(bp) &&
5632 !BP_NOMCP(bp)) {
f2e0899f 5633 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5634 u16 drv_pulse;
5635 u16 mcp_pulse;
a2fbb9ea
ET		 5636
5637 ++bp->fw_drv_pulse_wr_seq;
5638 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5639 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5640 bnx2x_drv_pulse(bp);
a2fbb9ea 5641
f2e0899f 5642 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5643 MCP_PULSE_SEQ_MASK);
5644 /* The delta between driver pulse and mcp response
4c868664
EG		 5645 * should not get too big. If the MFW is more than 5 pulses
5646 * behind, we should worry about it enough to generate an error
5647 * log.
a2fbb9ea 5648 */
4c868664
EG		 5649 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5650 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5651 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5652 }
5653
f34d28ea 5654 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5655 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5656
abc5a021 5657 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5658 if (IS_VF(bp))
5659 bnx2x_timer_sriov(bp);
78c3bcc5 5660
a2fbb9ea
ET		 5661 mod_timer(&bp->timer, jiffies + bp->current_interval);
5662}
5663
5664/* end of Statistics */
5665
5666/* nic init */
5667
5668/*
5669 * nic init service functions
5670 */
5671
1191cb83 5672static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5673{
523224a3
DK		 5674 u32 i;
5675 if (!(len%4) && !(addr%4))
5676 for (i = 0; i < len; i += 4)
5677 REG_WR(bp, addr + i, fill);
5678 else
5679 for (i = 0; i < len; i++)
5680 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5681}
5682
523224a3 5683/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5684static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5685 int fw_sb_id,
5686 u32 *sb_data_p,
5687 u32 data_size)
34f80b04 5688{
a2fbb9ea 5689 int index;
523224a3
DK		 5690 for (index = 0; index < data_size; index++)
5691 REG_WR(bp, BAR_CSTRORM_INTMEM +
5692 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5693 sizeof(u32)*index,
5694 *(sb_data_p + index));
5695}
a2fbb9ea 5696
1191cb83 5697static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5698{
5699 u32 *sb_data_p;
5700 u32 data_size = 0;
f2e0899f 5701 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5702 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5703
523224a3 5704 /* disable the function first */
619c5cb6 5705 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5706 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5707 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5708 sb_data_e2.common.p_func.vf_valid = false;
5709 sb_data_p = (u32 *)&sb_data_e2;
5710 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5711 } else {
5712 memset(&sb_data_e1x, 0,
5713 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5714 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5715 sb_data_e1x.common.p_func.vf_valid = false;
5716 sb_data_p = (u32 *)&sb_data_e1x;
5717 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5718 }
523224a3 5719 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5720
523224a3
DK		 5721 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5722 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5723 CSTORM_STATUS_BLOCK_SIZE);
5724 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5725 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5726 CSTORM_SYNC_BLOCK_SIZE);
5727}
34f80b04 5728
523224a3 5729/* helper: writes SP SB data to FW */
1191cb83 5730static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5731 struct hc_sp_status_block_data *sp_sb_data)
5732{
5733 int func = BP_FUNC(bp);
5734 int i;
5735 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5736 REG_WR(bp, BAR_CSTRORM_INTMEM +
5737 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5738 i*sizeof(u32),
5739 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5740}
5741
1191cb83 5742static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5743{
5744 int func = BP_FUNC(bp);
523224a3
DK		 5745 struct hc_sp_status_block_data sp_sb_data;
5746 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5747
619c5cb6 5748 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5749 sp_sb_data.p_func.vf_valid = false;
5750
5751 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5752
5753 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5754 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5755 CSTORM_SP_STATUS_BLOCK_SIZE);
5756 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5757 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5758 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5759}
5760
1191cb83 5761static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5762 int igu_sb_id, int igu_seg_id)
5763{
5764 hc_sm->igu_sb_id = igu_sb_id;
5765 hc_sm->igu_seg_id = igu_seg_id;
5766 hc_sm->timer_value = 0xFF;
5767 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5768}
5769
150966ad 5770/* allocates state machine ids. */
1191cb83 5771static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5772{
5773 /* zero out state machine indices */
5774 /* rx indices */
5775 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5776
5777 /* tx indices */
5778 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5779 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5780 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5781 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5782
5783 /* map indices */
5784 /* rx indices */
5785 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5786 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5787
5788 /* tx indices */
5789 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5790 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5791 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5792 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5793 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5794 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5795 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5796 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5797}
5798
b93288d5 5799void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5800 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5801{
523224a3
DK		 5802 int igu_seg_id;
5803
f2e0899f 5804 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5805 struct hc_status_block_data_e1x sb_data_e1x;
5806 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5807 int data_size;
5808 u32 *sb_data_p;
5809
f2e0899f
DK		 5810 if (CHIP_INT_MODE_IS_BC(bp))
5811 igu_seg_id = HC_SEG_ACCESS_NORM;
5812 else
5813 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5814
5815 bnx2x_zero_fp_sb(bp, fw_sb_id);
5816
619c5cb6 5817 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5818 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5819 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5820 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5821 sb_data_e2.common.p_func.vf_id = vfid;
5822 sb_data_e2.common.p_func.vf_valid = vf_valid;
5823 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5824 sb_data_e2.common.same_igu_sb_1b = true;
5825 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5826 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5827 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5828 sb_data_p = (u32 *)&sb_data_e2;
5829 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5830 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5831 } else {
5832 memset(&sb_data_e1x, 0,
5833 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5834 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5835 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5836 sb_data_e1x.common.p_func.vf_id = 0xff;
5837 sb_data_e1x.common.p_func.vf_valid = false;
5838 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5839 sb_data_e1x.common.same_igu_sb_1b = true;
5840 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5841 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5842 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5843 sb_data_p = (u32 *)&sb_data_e1x;
5844 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5845 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5846 }
523224a3
DK		 5847
5848 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5849 igu_sb_id, igu_seg_id);
5850 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5851 igu_sb_id, igu_seg_id);
5852
51c1a580 5853 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 5854
86564c3f 5855 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 5856 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5857}
5858
619c5cb6 5859static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5860 u16 tx_usec, u16 rx_usec)
5861{
6383c0b3 5862 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5863 false, rx_usec);
6383c0b3
AE		 5864 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5865 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5866 tx_usec);
5867 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5868 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5869 tx_usec);
5870 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5871 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5872 tx_usec);
523224a3 5873}
f2e0899f 5874
523224a3
DK		 5875static void bnx2x_init_def_sb(struct bnx2x *bp)
5876{
5877 struct host_sp_status_block *def_sb = bp->def_status_blk;
5878 dma_addr_t mapping = bp->def_status_blk_mapping;
5879 int igu_sp_sb_index;
5880 int igu_seg_id;
34f80b04
EG		 5881 int port = BP_PORT(bp);
5882 int func = BP_FUNC(bp);
f2eaeb58 5883 int reg_offset, reg_offset_en5;
a2fbb9ea 5884 u64 section;
523224a3
DK		 5885 int index;
5886 struct hc_sp_status_block_data sp_sb_data;
5887 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5888
f2e0899f
DK		 5889 if (CHIP_INT_MODE_IS_BC(bp)) {
5890 igu_sp_sb_index = DEF_SB_IGU_ID;
5891 igu_seg_id = HC_SEG_ACCESS_DEF;
5892 } else {
5893 igu_sp_sb_index = bp->igu_dsb_id;
5894 igu_seg_id = IGU_SEG_ACCESS_DEF;
5895 }
a2fbb9ea
ET		 5896
5897 /* ATTN */
523224a3 5898 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5899 atten_status_block);
523224a3 5900 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5901
49d66772
ET		 5902 bp->attn_state = 0;
5903
a2fbb9ea
ET		 5904 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5905 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5906 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5907 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5908 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5909 int sindex;
5910 /* take care of sig[0]..sig[4] */
5911 for (sindex = 0; sindex < 4; sindex++)
5912 bp->attn_group[index].sig[sindex] =
5913 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5914
619c5cb6 5915 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5916 /*
5917 * enable5 is separate from the rest of the registers,
5918 * and therefore the address skip is 4
5919 * and not 16 between the different groups
5920 */
5921 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5922 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5923 else
5924 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5925 }
5926
f2e0899f
DK		 5927 if (bp->common.int_block == INT_BLOCK_HC) {
5928 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5929 HC_REG_ATTN_MSG0_ADDR_L);
5930
5931 REG_WR(bp, reg_offset, U64_LO(section));
5932 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5933 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5934 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5935 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5936 }
a2fbb9ea 5937
523224a3
DK		 5938 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5939 sp_sb);
a2fbb9ea 5940
523224a3 5941 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5942
86564c3f 5943 /* PCI guarantees endianity of regpairs */
619c5cb6 5944 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5945 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5946 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5947 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5948 sp_sb_data.igu_seg_id = igu_seg_id;
5949 sp_sb_data.p_func.pf_id = func;
f2e0899f 5950 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5951 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5952
523224a3 5953 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5954
523224a3 5955 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5956}
5957
9f6c9258 5958void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5959{
a2fbb9ea
ET		 5960 int i;
5961
ec6ba945 5962 for_each_eth_queue(bp, i)
523224a3 5963 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5964 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5965}
5966
a2fbb9ea
ET		 5967static void bnx2x_init_sp_ring(struct bnx2x *bp)
5968{
a2fbb9ea 5969 spin_lock_init(&bp->spq_lock);
6e30dd4e 5970 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5971
a2fbb9ea 5972 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5973 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5974 bp->spq_prod_bd = bp->spq;
5975 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5976}
5977
523224a3 5978static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5979{
5980 int i;
523224a3
DK		 5981 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5982 union event_ring_elem *elem =
5983 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5984
523224a3
DK		 5985 elem->next_page.addr.hi =
5986 cpu_to_le32(U64_HI(bp->eq_mapping +
5987 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5988 elem->next_page.addr.lo =
5989 cpu_to_le32(U64_LO(bp->eq_mapping +
5990 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5991 }
523224a3
DK		 5992 bp->eq_cons = 0;
5993 bp->eq_prod = NUM_EQ_DESC;
5994 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 5995 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 5996 atomic_set(&bp->eq_spq_left,
5997 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5998}
5999
619c5cb6 6000/* called with netif_addr_lock_bh() */
a8f47eb7 6001static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6002 unsigned long rx_mode_flags,
6003 unsigned long rx_accept_flags,
6004 unsigned long tx_accept_flags,
6005 unsigned long ramrod_flags)
ab532cf3 6006{
619c5cb6
VZ		 6007 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6008 int rc;
6009
6010 memset(&ramrod_param, 0, sizeof(ramrod_param));
6011
6012 /* Prepare ramrod parameters */
6013 ramrod_param.cid = 0;
6014 ramrod_param.cl_id = cl_id;
6015 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6016 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 6017
619c5cb6
VZ		 6018 ramrod_param.pstate = &bp->sp_state;
6019 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 6020
619c5cb6
VZ		 6021 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6022 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6023
6024 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6025
6026 ramrod_param.ramrod_flags = ramrod_flags;
6027 ramrod_param.rx_mode_flags = rx_mode_flags;
6028
6029 ramrod_param.rx_accept_flags = rx_accept_flags;
6030 ramrod_param.tx_accept_flags = tx_accept_flags;
6031
6032 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6033 if (rc < 0) {
6034 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 6035 return rc;
619c5cb6 6036 }
924d75ab
YM		 6037
6038 return 0;
a2fbb9ea
ET		 6039}
6040
86564c3f
YM		 6041static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6042 unsigned long *rx_accept_flags,
6043 unsigned long *tx_accept_flags)
471de716 6044{
924d75ab
YM		 6045 /* Clear the flags first */
6046 *rx_accept_flags = 0;
6047 *tx_accept_flags = 0;
619c5cb6 6048
924d75ab 6049 switch (rx_mode) {
619c5cb6
VZ		 6050 case BNX2X_RX_MODE_NONE:
6051 /*
6052 * 'drop all' supersedes any accept flags that may have been
6053 * passed to the function.
6054 */
6055 break;
6056 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 6057 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6058 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6059 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6060
6061 /* internal switching mode */
924d75ab
YM		 6062 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6063 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6064 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6065
6066 break;
6067 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 6068 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6069 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6070 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6071
6072 /* internal switching mode */
924d75ab
YM		 6073 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6074 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6075 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6076
6077 break;
6078 case BNX2X_RX_MODE_PROMISC:
16a5fd92 6079 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 6080 * should receive matched and unmatched (in resolution of port)
6081 * unicast packets.
6082 */
924d75ab
YM		 6083 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6084 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6085 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6086 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6087
6088 /* internal switching mode */
924d75ab
YM		 6089 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6090 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6091
6092 if (IS_MF_SI(bp))
924d75ab 6093 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 6094 else
924d75ab 6095 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6
VZ		 6096
6097 break;
6098 default:
924d75ab
YM		 6099 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6100 return -EINVAL;
619c5cb6 6101 }
de832a55 6102
924d75ab 6103 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
619c5cb6 6104 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
924d75ab
YM		 6105 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6106 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
34f80b04
EG		 6107 }
6108
924d75ab
YM		 6109 return 0;
6110}
6111
6112/* called with netif_addr_lock_bh() */
a8f47eb7 6113static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6114{
6115 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6116 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6117 int rc;
6118
6119 if (!NO_FCOE(bp))
6120 /* Configure rx_mode of FCoE Queue */
6121 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6122
6123 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6124 &tx_accept_flags);
6125 if (rc)
6126 return rc;
6127
619c5cb6
VZ		 6128 __set_bit(RAMROD_RX, &ramrod_flags);
6129 __set_bit(RAMROD_TX, &ramrod_flags);
6130
924d75ab
YM		 6131 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6132 rx_accept_flags, tx_accept_flags,
6133 ramrod_flags);
619c5cb6
VZ		 6134}
6135
6136static void bnx2x_init_internal_common(struct bnx2x *bp)
6137{
6138 int i;
6139
523224a3
DK		 6140 /* Zero this manually as its initialization is
6141 currently missing in the initTool */
6142 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6143 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6144 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6145 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6146 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6147 CHIP_INT_MODE_IS_BC(bp) ?
6148 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6149 }
523224a3 6150}
8a1c38d1 6151
471de716
EG		 6152static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6153{
6154 switch (load_code) {
6155 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6156 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6157 bnx2x_init_internal_common(bp);
6158 /* no break */
6159
6160 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6161 /* nothing to do */
471de716
EG		 6162 /* no break */
6163
6164 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6165 /* internal memory per function is
6166 initialized inside bnx2x_pf_init */
471de716
EG		 6167 break;
6168
6169 default:
6170 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6171 break;
6172 }
6173}
6174
619c5cb6 6175static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6176{
55c11941 6177 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6178}
523224a3 6179
619c5cb6
VZ		 6180static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6181{
55c11941 6182 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6183}
6184
1191cb83 6185static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6186{
6187 if (CHIP_IS_E1x(fp->bp))
6188 return BP_L_ID(fp->bp) + fp->index;
6189 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6190 return bnx2x_fp_igu_sb_id(fp);
6191}
6192
6383c0b3 6193static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6194{
6195 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6196 u8 cos;
619c5cb6 6197 unsigned long q_type = 0;
6383c0b3 6198 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6199 fp->rx_queue = fp_idx;
b3b83c3f 6200 fp->cid = fp_idx;
619c5cb6
VZ		 6201 fp->cl_id = bnx2x_fp_cl_id(fp);
6202 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6203 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6204 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6205 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6206
523224a3 6207 /* init shortcut */
619c5cb6 6208 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6209
16a5fd92 6210 /* Setup SB indices */
523224a3 6211 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6212
619c5cb6
VZ		 6213 /* Configure Queue State object */
6214 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6215 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6216
6217 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6218
6219 /* init tx data */
6220 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6221 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6222 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6223 FP_COS_TO_TXQ(fp, cos, bp),
6224 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6225 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6226 }
6227
ad5afc89
AE		 6228 /* nothing more for vf to do here */
6229 if (IS_VF(bp))
6230 return;
6231
6232 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6233 fp->fw_sb_id, fp->igu_sb_id);
6234 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6235 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6236 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6237 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6238
6239 /**
6240 * Configure classification DBs: Always enable Tx switching
6241 */
6242 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6243
ad5afc89
AE		 6244 DP(NETIF_MSG_IFUP,
6245 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6246 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6247 fp->igu_sb_id);
523224a3
DK		 6248}
6249
1191cb83
ED		 6250static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6251{
6252 int i;
6253
6254 for (i = 1; i <= NUM_TX_RINGS; i++) {
6255 struct eth_tx_next_bd *tx_next_bd =
6256 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6257
6258 tx_next_bd->addr_hi =
6259 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6260 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6261 tx_next_bd->addr_lo =
6262 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6263 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6264 }
6265
639d65b8
YM		 6266 *txdata->tx_cons_sb = cpu_to_le16(0);
6267
1191cb83
ED		 6268 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6269 txdata->tx_db.data.zero_fill1 = 0;
6270 txdata->tx_db.data.prod = 0;
6271
6272 txdata->tx_pkt_prod = 0;
6273 txdata->tx_pkt_cons = 0;
6274 txdata->tx_bd_prod = 0;
6275 txdata->tx_bd_cons = 0;
6276 txdata->tx_pkt = 0;
6277}
6278
55c11941
MS		 6279static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6280{
6281 int i;
6282
6283 for_each_tx_queue_cnic(bp, i)
6284 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6285}
d76a6111 6286
1191cb83
ED		 6287static void bnx2x_init_tx_rings(struct bnx2x *bp)
6288{
6289 int i;
6290 u8 cos;
6291
55c11941 6292 for_each_eth_queue(bp, i)
1191cb83 6293 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6294 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6295}
6296
a8f47eb7 6297static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6298{
6299 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6300 unsigned long q_type = 0;
6301
6302 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6303 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6304 BNX2X_FCOE_ETH_CL_ID_IDX);
6305 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6306 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6307 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6308 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6309 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6310 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6311 fp);
6312
6313 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6314
6315 /* qZone id equals to FW (per path) client id */
6316 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6317 /* init shortcut */
6318 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6319 bnx2x_rx_ustorm_prods_offset(fp);
6320
6321 /* Configure Queue State object */
6322 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6323 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6324
6325 /* No multi-CoS for FCoE L2 client */
6326 BUG_ON(fp->max_cos != 1);
6327
6328 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6329 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6330 bnx2x_sp_mapping(bp, q_rdata), q_type);
6331
6332 DP(NETIF_MSG_IFUP,
6333 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6334 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6335 fp->igu_sb_id);
6336}
6337
55c11941 6338void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6339{
ec6ba945
VZ		 6340 if (!NO_FCOE(bp))
6341 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6342
6343 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6344 BNX2X_VF_ID_INVALID, false,
619c5cb6 6345 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6346
55c11941
MS		 6347 /* ensure status block indices were read */
6348 rmb();
6349 bnx2x_init_rx_rings_cnic(bp);
6350 bnx2x_init_tx_rings_cnic(bp);
6351
6352 /* flush all */
6353 mb();
6354 mmiowb();
6355}
a2fbb9ea 6356
ecf01c22 6357void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6358{
6359 int i;
6360
ecf01c22 6361 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6362 for_each_eth_queue(bp, i)
6363 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6364
6365 /* ensure status block indices were read */
6366 rmb();
6367 bnx2x_init_rx_rings(bp);
6368 bnx2x_init_tx_rings(bp);
6369
ecf01c22
YM		 6370 if (IS_PF(bp)) {
6371 /* Initialize MOD_ABS interrupts */
6372 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6373 bp->common.shmem_base,
6374 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6375
ecf01c22
YM		 6376 /* initialize the default status block and sp ring */
6377 bnx2x_init_def_sb(bp);
6378 bnx2x_update_dsb_idx(bp);
6379 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6380 } else {
6381 bnx2x_memset_stats(bp);
ecf01c22
YM		 6382 }
6383}
16119785 6384
ecf01c22
YM		 6385void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6386{
523224a3 6387 bnx2x_init_eq_ring(bp);
471de716 6388 bnx2x_init_internal(bp, load_code);
523224a3 6389 bnx2x_pf_init(bp);
0ef00459
EG		 6390 bnx2x_stats_init(bp);
6391
0ef00459
EG		 6392 /* flush all before enabling interrupts */
6393 mb();
6394 mmiowb();
6395
615f8fd9 6396 bnx2x_int_enable(bp);
eb8da205
EG		 6397
6398 /* Check for SPIO5 */
6399 bnx2x_attn_int_deasserted0(bp,
6400 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6401 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6402}
6403
ecf01c22 6404/* gzip service functions */
a2fbb9ea
ET		 6405static int bnx2x_gunzip_init(struct bnx2x *bp)
6406{
1a983142
FT		 6407 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6408 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6409 if (bp->gunzip_buf == NULL)
6410 goto gunzip_nomem1;
6411
6412 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6413 if (bp->strm == NULL)
6414 goto gunzip_nomem2;
6415
7ab24bfd 6416 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6417 if (bp->strm->workspace == NULL)
6418 goto gunzip_nomem3;
6419
6420 return 0;
6421
6422gunzip_nomem3:
6423 kfree(bp->strm);
6424 bp->strm = NULL;
6425
6426gunzip_nomem2:
1a983142
FT		 6427 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6428 bp->gunzip_mapping);
a2fbb9ea
ET		 6429 bp->gunzip_buf = NULL;
6430
6431gunzip_nomem1:
51c1a580 6432 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6433 return -ENOMEM;
6434}
6435
6436static void bnx2x_gunzip_end(struct bnx2x *bp)
6437{
b3b83c3f 6438 if (bp->strm) {
7ab24bfd 6439 vfree(bp->strm->workspace);
b3b83c3f
DK		 6440 kfree(bp->strm);
6441 bp->strm = NULL;
6442 }
a2fbb9ea
ET		 6443
6444 if (bp->gunzip_buf) {
1a983142
FT		 6445 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6446 bp->gunzip_mapping);
a2fbb9ea
ET		 6447 bp->gunzip_buf = NULL;
6448 }
6449}
6450
94a78b79 6451static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6452{
6453 int n, rc;
6454
6455 /* check gzip header */
94a78b79
VZ		 6456 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6457 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6458 return -EINVAL;
94a78b79 6459 }
a2fbb9ea
ET		 6460
6461 n = 10;
6462
34f80b04 6463#define FNAME 0x8
a2fbb9ea
ET		 6464
6465 if (zbuf[3] & FNAME)
6466 while ((zbuf[n++] != 0) && (n < len));
6467
94a78b79 6468 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6469 bp->strm->avail_in = len - n;
6470 bp->strm->next_out = bp->gunzip_buf;
6471 bp->strm->avail_out = FW_BUF_SIZE;
6472
6473 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6474 if (rc != Z_OK)
6475 return rc;
6476
6477 rc = zlib_inflate(bp->strm, Z_FINISH);
6478 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6479 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6480 bp->strm->msg);
a2fbb9ea
ET		 6481
6482 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6483 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6484 netdev_err(bp->dev,
6485 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6486 bp->gunzip_outlen);
a2fbb9ea
ET		 6487 bp->gunzip_outlen >>= 2;
6488
6489 zlib_inflateEnd(bp->strm);
6490
6491 if (rc == Z_STREAM_END)
6492 return 0;
6493
6494 return rc;
6495}
6496
6497/* nic load/unload */
6498
6499/*
34f80b04 6500 * General service functions
a2fbb9ea
ET		 6501 */
6502
6503/* send a NIG loopback debug packet */
6504static void bnx2x_lb_pckt(struct bnx2x *bp)
6505{
a2fbb9ea 6506 u32 wb_write[3];
a2fbb9ea
ET		 6507
6508 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6509 wb_write[0] = 0x55555555;
6510 wb_write[1] = 0x55555555;
34f80b04 6511 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6512 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6513
6514 /* NON-IP protocol */
a2fbb9ea
ET		 6515 wb_write[0] = 0x09000000;
6516 wb_write[1] = 0x55555555;
34f80b04 6517 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6518 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6519}
6520
6521/* some of the internal memories
6522 * are not directly readable from the driver
6523 * to test them we send debug packets
6524 */
6525static int bnx2x_int_mem_test(struct bnx2x *bp)
6526{
6527 int factor;
6528 int count, i;
6529 u32 val = 0;
6530
ad8d3948 6531 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6532 factor = 120;
ad8d3948
EG		 6533 else if (CHIP_REV_IS_EMUL(bp))
6534 factor = 200;
6535 else
a2fbb9ea 6536 factor = 1;
a2fbb9ea 6537
a2fbb9ea
ET		 6538 /* Disable inputs of parser neighbor blocks */
6539 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6540 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6541 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6542 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6543
6544 /* Write 0 to parser credits for CFC search request */
6545 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6546
6547 /* send Ethernet packet */
6548 bnx2x_lb_pckt(bp);
6549
6550 /* TODO do i reset NIG statistic? */
6551 /* Wait until NIG register shows 1 packet of size 0x10 */
6552 count = 1000 * factor;
6553 while (count) {
34f80b04 6554
a2fbb9ea
ET		 6555 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6556 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6557 if (val == 0x10)
6558 break;
6559
639d65b8 6560 usleep_range(10000, 20000);
a2fbb9ea
ET		 6561 count--;
6562 }
6563 if (val != 0x10) {
6564 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6565 return -1;
6566 }
6567
6568 /* Wait until PRS register shows 1 packet */
6569 count = 1000 * factor;
6570 while (count) {
6571 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6572 if (val == 1)
6573 break;
6574
639d65b8 6575 usleep_range(10000, 20000);
a2fbb9ea
ET		 6576 count--;
6577 }
6578 if (val != 0x1) {
6579 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6580 return -2;
6581 }
6582
6583 /* Reset and init BRB, PRS */
34f80b04 6584 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6585 msleep(50);
34f80b04 6586 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6587 msleep(50);
619c5cb6
VZ		 6588 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6589 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6590
6591 DP(NETIF_MSG_HW, "part2\n");
6592
6593 /* Disable inputs of parser neighbor blocks */
6594 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6595 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6596 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6597 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6598
6599 /* Write 0 to parser credits for CFC search request */
6600 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6601
6602 /* send 10 Ethernet packets */
6603 for (i = 0; i < 10; i++)
6604 bnx2x_lb_pckt(bp);
6605
6606 /* Wait until NIG register shows 10 + 1
6607 packets of size 11*0x10 = 0xb0 */
6608 count = 1000 * factor;
6609 while (count) {
34f80b04 6610
a2fbb9ea
ET		 6611 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6612 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6613 if (val == 0xb0)
6614 break;
6615
639d65b8 6616 usleep_range(10000, 20000);
a2fbb9ea
ET		 6617 count--;
6618 }
6619 if (val != 0xb0) {
6620 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6621 return -3;
6622 }
6623
6624 /* Wait until PRS register shows 2 packets */
6625 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6626 if (val != 2)
6627 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6628
6629 /* Write 1 to parser credits for CFC search request */
6630 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6631
6632 /* Wait until PRS register shows 3 packets */
6633 msleep(10 * factor);
6634 /* Wait until NIG register shows 1 packet of size 0x10 */
6635 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6636 if (val != 3)
6637 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6638
6639 /* clear NIG EOP FIFO */
6640 for (i = 0; i < 11; i++)
6641 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6642 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6643 if (val != 1) {
6644 BNX2X_ERR("clear of NIG failed\n");
6645 return -4;
6646 }
6647
6648 /* Reset and init BRB, PRS, NIG */
6649 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6650 msleep(50);
6651 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6652 msleep(50);
619c5cb6
VZ		 6653 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6654 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6655 if (!CNIC_SUPPORT(bp))
6656 /* set NIC mode */
6657 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6658
6659 /* Enable inputs of parser neighbor blocks */
6660 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6661 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6662 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6663 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6664
6665 DP(NETIF_MSG_HW, "done\n");
6666
6667 return 0; /* OK */
6668}
6669
4a33bc03 6670static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6671{
b343d002
YM		 6672 u32 val;
6673
a2fbb9ea 6674 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6675 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6676 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6677 else
6678 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6679 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6680 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6681 /*
6682 * mask read length error interrupts in brb for parser
6683 * (parsing unit and 'checksum and crc' unit)
6684 * these errors are legal (PU reads fixed length and CAC can cause
6685 * read length error on truncated packets)
6686 */
6687 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6688 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6689 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6690 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6691 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6692 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6693/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6694/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6695 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6696 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6697 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6698/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6699/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6700 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6701 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6702 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6703 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6704/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6705/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6706
b343d002
YM		 6707 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6708 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6709 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6710 if (!CHIP_IS_E1x(bp))
6711 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6712 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6713 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6714
a2fbb9ea
ET		 6715 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6716 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6717 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6718/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6719
6720 if (!CHIP_IS_E1x(bp))
6721 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6722 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6723
a2fbb9ea
ET		 6724 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6725 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6726/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6727 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6728}
6729
81f75bbf
EG		 6730static void bnx2x_reset_common(struct bnx2x *bp)
6731{
619c5cb6
VZ		 6732 u32 val = 0x1400;
6733
81f75bbf
EG		 6734 /* reset_common */
6735 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6736 0xd3ffff7f);
619c5cb6
VZ		 6737
6738 if (CHIP_IS_E3(bp)) {
6739 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6740 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6741 }
6742
6743 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6744}
6745
6746static void bnx2x_setup_dmae(struct bnx2x *bp)
6747{
6748 bp->dmae_ready = 0;
6749 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6750}
6751
573f2035
EG		 6752static void bnx2x_init_pxp(struct bnx2x *bp)
6753{
6754 u16 devctl;
6755 int r_order, w_order;
6756
2a80eebc 6757 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6758 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6759 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6760 if (bp->mrrs == -1)
6761 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6762 else {
6763 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6764 r_order = bp->mrrs;
6765 }
6766
6767 bnx2x_init_pxp_arb(bp, r_order, w_order);
6768}
fd4ef40d
EG		 6769
6770static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6771{
2145a920 6772 int is_required;
fd4ef40d 6773 u32 val;
2145a920 6774 int port;
fd4ef40d 6775
2145a920
VZ		 6776 if (BP_NOMCP(bp))
6777 return;
6778
6779 is_required = 0;
fd4ef40d
EG		 6780 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6781 SHARED_HW_CFG_FAN_FAILURE_MASK;
6782
6783 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6784 is_required = 1;
6785
6786 /*
6787 * The fan failure mechanism is usually related to the PHY type since
6788 * the power consumption of the board is affected by the PHY. Currently,
6789 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6790 */
6791 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6792 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6793 is_required |=
d90d96ba
YR		 6794 bnx2x_fan_failure_det_req(
6795 bp,
6796 bp->common.shmem_base,
a22f0788 6797 bp->common.shmem2_base,
d90d96ba 6798 port);
fd4ef40d
EG		 6799 }
6800
6801 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6802
6803 if (is_required == 0)
6804 return;
6805
6806 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6807 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6808
6809 /* set to active low mode */
6810 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6811 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6812 REG_WR(bp, MISC_REG_SPIO_INT, val);
6813
6814 /* enable interrupt to signal the IGU */
6815 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6816 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6817 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6818}
6819
c9ee9206 6820void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6821{
6822 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6823 val &= ~IGU_PF_CONF_FUNC_EN;
6824
6825 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6826 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6827 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6828}
6829
1191cb83 6830static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6831{
6832 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6833 /* Avoid common init in case MFW supports LFA */
6834 if (SHMEM2_RD(bp, size) >
6835 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6836 return;
619c5cb6
VZ		 6837 shmem_base[0] = bp->common.shmem_base;
6838 shmem2_base[0] = bp->common.shmem2_base;
6839 if (!CHIP_IS_E1x(bp)) {
6840 shmem_base[1] =
6841 SHMEM2_RD(bp, other_shmem_base_addr);
6842 shmem2_base[1] =
6843 SHMEM2_RD(bp, other_shmem2_base_addr);
6844 }
6845 bnx2x_acquire_phy_lock(bp);
6846 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6847 bp->common.chip_id);
6848 bnx2x_release_phy_lock(bp);
6849}
6850
6851/**
6852 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6853 *
6854 * @bp: driver handle
6855 */
6856static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6857{
619c5cb6 6858 u32 val;
a2fbb9ea 6859
51c1a580 6860 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6861
2031bd3a 6862 /*
2de67439 6863 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 6864 * registers while we're resetting the chip
6865 */
7a06a122 6866 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6867
81f75bbf 6868 bnx2x_reset_common(bp);
34f80b04 6869 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6870
619c5cb6
VZ		 6871 val = 0xfffc;
6872 if (CHIP_IS_E3(bp)) {
6873 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6874 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6875 }
6876 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6877
7a06a122 6878 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6879
619c5cb6 6880 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6881
619c5cb6
VZ		 6882 if (!CHIP_IS_E1x(bp)) {
6883 u8 abs_func_id;
f2e0899f
DK		 6884
6885 /**
6886 * 4-port mode or 2-port mode we need to turn of master-enable
6887 * for everyone, after that, turn it back on for self.
6888 * so, we disregard multi-function or not, and always disable
6889 * for all functions on the given path, this means 0,2,4,6 for
6890 * path 0 and 1,3,5,7 for path 1
6891 */
619c5cb6
VZ		 6892 for (abs_func_id = BP_PATH(bp);
6893 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6894 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6895 REG_WR(bp,
6896 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6897 1);
6898 continue;
6899 }
6900
619c5cb6 6901 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6902 /* clear pf enable */
6903 bnx2x_pf_disable(bp);
6904 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6905 }
6906 }
a2fbb9ea 6907
619c5cb6 6908 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6909 if (CHIP_IS_E1(bp)) {
6910 /* enable HW interrupt from PXP on USDM overflow
6911 bit 16 on INT_MASK_0 */
6912 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6913 }
a2fbb9ea 6914
619c5cb6 6915 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6916 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 6917
6918#ifdef __BIG_ENDIAN
34f80b04
EG		 6919 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6920 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6921 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6922 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6923 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 6924 /* make sure this value is 0 */
6925 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 6926
6927/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6928 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6929 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6930 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6931 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 6932#endif
6933
523224a3
DK		 6934 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6935
34f80b04
EG		 6936 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6937 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6938
34f80b04
EG		 6939 /* let the HW do it's magic ... */
6940 msleep(100);
6941 /* finish PXP init */
6942 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6943 if (val != 1) {
6944 BNX2X_ERR("PXP2 CFG failed\n");
6945 return -EBUSY;
6946 }
6947 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6948 if (val != 1) {
6949 BNX2X_ERR("PXP2 RD_INIT failed\n");
6950 return -EBUSY;
6951 }
a2fbb9ea 6952
f2e0899f
DK		 6953 /* Timers bug workaround E2 only. We need to set the entire ILT to
6954 * have entries with value "0" and valid bit on.
6955 * This needs to be done by the first PF that is loaded in a path
6956 * (i.e. common phase)
6957 */
619c5cb6
VZ		 6958 if (!CHIP_IS_E1x(bp)) {
6959/* In E2 there is a bug in the timers block that can cause function 6 / 7
6960 * (i.e. vnic3) to start even if it is marked as "scan-off".
6961 * This occurs when a different function (func2,3) is being marked
6962 * as "scan-off". Real-life scenario for example: if a driver is being
6963 * load-unloaded while func6,7 are down. This will cause the timer to access
6964 * the ilt, translate to a logical address and send a request to read/write.
6965 * Since the ilt for the function that is down is not valid, this will cause
6966 * a translation error which is unrecoverable.
6967 * The Workaround is intended to make sure that when this happens nothing fatal
6968 * will occur. The workaround:
6969 * 1. First PF driver which loads on a path will:
6970 * a. After taking the chip out of reset, by using pretend,
6971 * it will write "0" to the following registers of
6972 * the other vnics.
6973 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6974 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6975 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6976 * And for itself it will write '1' to
6977 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6978 * dmae-operations (writing to pram for example.)
6979 * note: can be done for only function 6,7 but cleaner this
6980 * way.
6981 * b. Write zero+valid to the entire ILT.
6982 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6983 * VNIC3 (of that port). The range allocated will be the
6984 * entire ILT. This is needed to prevent ILT range error.
6985 * 2. Any PF driver load flow:
6986 * a. ILT update with the physical addresses of the allocated
6987 * logical pages.
6988 * b. Wait 20msec. - note that this timeout is needed to make
6989 * sure there are no requests in one of the PXP internal
6990 * queues with "old" ILT addresses.
6991 * c. PF enable in the PGLC.
6992 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 6993 * occurred while driver was down)
619c5cb6
VZ		 6994 * e. PF enable in the CFC (WEAK + STRONG)
6995 * f. Timers scan enable
6996 * 3. PF driver unload flow:
6997 * a. Clear the Timers scan_en.
6998 * b. Polling for scan_on=0 for that PF.
6999 * c. Clear the PF enable bit in the PXP.
7000 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7001 * e. Write zero+valid to all ILT entries (The valid bit must
7002 * stay set)
7003 * f. If this is VNIC 3 of a port then also init
7004 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 7005 * to the last entry in the ILT.
619c5cb6
VZ		 7006 *
7007 * Notes:
7008 * Currently the PF error in the PGLC is non recoverable.
7009 * In the future the there will be a recovery routine for this error.
7010 * Currently attention is masked.
7011 * Having an MCP lock on the load/unload process does not guarantee that
7012 * there is no Timer disable during Func6/7 enable. This is because the
7013 * Timers scan is currently being cleared by the MCP on FLR.
7014 * Step 2.d can be done only for PF6/7 and the driver can also check if
7015 * there is error before clearing it. But the flow above is simpler and
7016 * more general.
7017 * All ILT entries are written by zero+valid and not just PF6/7
7018 * ILT entries since in the future the ILT entries allocation for
7019 * PF-s might be dynamic.
7020 */
f2e0899f
DK		 7021 struct ilt_client_info ilt_cli;
7022 struct bnx2x_ilt ilt;
7023 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7024 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7025
b595076a 7026 /* initialize dummy TM client */
f2e0899f
DK		 7027 ilt_cli.start = 0;
7028 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7029 ilt_cli.client_num = ILT_CLIENT_TM;
7030
7031 /* Step 1: set zeroes to all ilt page entries with valid bit on
7032 * Step 2: set the timers first/last ilt entry to point
7033 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 7034 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 7035 *
7036 * both steps performed by call to bnx2x_ilt_client_init_op()
7037 * with dummy TM client
7038 *
7039 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7040 * and his brother are split registers
7041 */
7042 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7043 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7044 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7045
7046 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7047 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7048 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7049 }
7050
34f80b04
EG		 7051 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7052 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 7053
619c5cb6 7054 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7055 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7056 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 7057 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 7058
619c5cb6 7059 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 7060
7061 /* let the HW do it's magic ... */
7062 do {
7063 msleep(200);
7064 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7065 } while (factor-- && (val != 1));
7066
7067 if (val != 1) {
7068 BNX2X_ERR("ATC_INIT failed\n");
7069 return -EBUSY;
7070 }
7071 }
7072
619c5cb6 7073 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 7074
b56e9670
AE		 7075 bnx2x_iov_init_dmae(bp);
7076
34f80b04
EG		 7077 /* clean the DMAE memory */
7078 bp->dmae_ready = 1;
619c5cb6
VZ		 7079 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7080
7081 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7082
7083 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7084
7085 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 7086
619c5cb6 7087 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 7088
34f80b04
EG		 7089 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7090 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7091 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7092 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7093
619c5cb6 7094 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 7095
523224a3
DK		 7096 /* QM queues pointers table */
7097 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7098
34f80b04
EG		 7099 /* soft reset pulse */
7100 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7101 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 7102
55c11941
MS		 7103 if (CNIC_SUPPORT(bp))
7104 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 7105
619c5cb6 7106 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 7107
619c5cb6 7108 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7109 /* enable hw interrupt from doorbell Q */
7110 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7111
619c5cb6 7112 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7113
619c5cb6 7114 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7115 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7116
f2e0899f 7117 if (!CHIP_IS_E1(bp))
619c5cb6 7118 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7119
a3348722
BW		 7120 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7121 if (IS_MF_AFEX(bp)) {
7122 /* configure that VNTag and VLAN headers must be
7123 * received in afex mode
7124 */
7125 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7126 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7127 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7128 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7129 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7130 } else {
7131 /* Bit-map indicating which L2 hdrs may appear
7132 * after the basic Ethernet header
7133 */
7134 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7135 bp->path_has_ovlan ? 7 : 6);
7136 }
7137 }
a2fbb9ea 7138
619c5cb6
VZ		 7139 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7140 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7141 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7142 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7143
619c5cb6
VZ		 7144 if (!CHIP_IS_E1x(bp)) {
7145 /* reset VFC memories */
7146 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7147 VFC_MEMORIES_RST_REG_CAM_RST |
7148 VFC_MEMORIES_RST_REG_RAM_RST);
7149 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7150 VFC_MEMORIES_RST_REG_CAM_RST |
7151 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7152
619c5cb6
VZ		 7153 msleep(20);
7154 }
a2fbb9ea 7155
619c5cb6
VZ		 7156 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7157 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7158 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7159 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7160
34f80b04
EG		 7161 /* sync semi rtc */
7162 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7163 0x80000000);
7164 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7165 0x80000000);
a2fbb9ea 7166
619c5cb6
VZ		 7167 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7168 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7169 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7170
a3348722
BW		 7171 if (!CHIP_IS_E1x(bp)) {
7172 if (IS_MF_AFEX(bp)) {
7173 /* configure that VNTag and VLAN headers must be
7174 * sent in afex mode
7175 */
7176 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7177 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7178 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7179 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7180 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7181 } else {
7182 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7183 bp->path_has_ovlan ? 7 : 6);
7184 }
7185 }
f2e0899f 7186
34f80b04 7187 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7188
619c5cb6
VZ		 7189 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7190
55c11941
MS		 7191 if (CNIC_SUPPORT(bp)) {
7192 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7193 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7194 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7195 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7196 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7197 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7198 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7199 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7200 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7201 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7202 }
34f80b04 7203 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7204
34f80b04
EG		 7205 if (sizeof(union cdu_context) != 1024)
7206 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7207 dev_alert(&bp->pdev->dev,
7208 "please adjust the size of cdu_context(%ld)\n",
7209 (long)sizeof(union cdu_context));
a2fbb9ea 7210
619c5cb6 7211 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7212 val = (4 << 24) + (0 << 12) + 1024;
7213 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7214
619c5cb6 7215 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7216 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7217 /* enable context validation interrupt from CFC */
7218 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7219
7220 /* set the thresholds to prevent CFC/CDU race */
7221 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7222
619c5cb6 7223 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7224
619c5cb6 7225 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7226 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7227
619c5cb6
VZ		 7228 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7229 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7230
34f80b04
EG		 7231 /* Reset PCIE errors for debug */
7232 REG_WR(bp, 0x2814, 0xffffffff);
7233 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7234
619c5cb6 7235 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7236 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7237 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7238 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7239 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7240 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7241 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7242 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7243 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7244 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7245 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7246 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7247 }
7248
619c5cb6 7249 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7250 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7251 /* in E3 this done in per-port section */
7252 if (!CHIP_IS_E3(bp))
7253 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7254 }
619c5cb6
VZ		 7255 if (CHIP_IS_E1H(bp))
7256 /* not applicable for E2 (and above ...) */
7257 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7258
7259 if (CHIP_REV_IS_SLOW(bp))
7260 msleep(200);
7261
7262 /* finish CFC init */
7263 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7264 if (val != 1) {
7265 BNX2X_ERR("CFC LL_INIT failed\n");
7266 return -EBUSY;
7267 }
7268 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7269 if (val != 1) {
7270 BNX2X_ERR("CFC AC_INIT failed\n");
7271 return -EBUSY;
7272 }
7273 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7274 if (val != 1) {
7275 BNX2X_ERR("CFC CAM_INIT failed\n");
7276 return -EBUSY;
7277 }
7278 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7279
f2e0899f
DK		 7280 if (CHIP_IS_E1(bp)) {
7281 /* read NIG statistic
7282 to see if this is our first up since powerup */
7283 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7284 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7285
f2e0899f
DK		 7286 /* do internal memory self test */
7287 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7288 BNX2X_ERR("internal mem self test failed\n");
7289 return -EBUSY;
7290 }
34f80b04
EG		 7291 }
7292
fd4ef40d
EG		 7293 bnx2x_setup_fan_failure_detection(bp);
7294
34f80b04
EG		 7295 /* clear PXP2 attentions */
7296 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7297
4a33bc03 7298 bnx2x_enable_blocks_attention(bp);
c9ee9206 7299 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7300
6bbca910 7301 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7302 if (CHIP_IS_E1x(bp))
7303 bnx2x__common_init_phy(bp);
6bbca910
YR		 7304 } else
7305 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7306
34f80b04
EG		 7307 return 0;
7308}
a2fbb9ea 7309
619c5cb6
VZ		 7310/**
7311 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7312 *
7313 * @bp: driver handle
7314 */
7315static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7316{
7317 int rc = bnx2x_init_hw_common(bp);
7318
7319 if (rc)
7320 return rc;
7321
7322 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7323 if (!BP_NOMCP(bp))
7324 bnx2x__common_init_phy(bp);
7325
7326 return 0;
7327}
7328
523224a3 7329static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7330{
7331 int port = BP_PORT(bp);
619c5cb6 7332 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7333 u32 low, high;
4293b9f5 7334 u32 val, reg;
a2fbb9ea 7335
51c1a580 7336 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7337
7338 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7339
619c5cb6
VZ		 7340 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7341 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7342 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7343
f2e0899f
DK		 7344 /* Timers bug workaround: disables the pf_master bit in pglue at
7345 * common phase, we need to enable it here before any dmae access are
7346 * attempted. Therefore we manually added the enable-master to the
7347 * port phase (it also happens in the function phase)
7348 */
619c5cb6 7349 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7350 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7351
619c5cb6
VZ		 7352 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7353 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7354 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7355 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7356
7357 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7358 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7359 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7360 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7361
523224a3
DK		 7362 /* QM cid (connection) count */
7363 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7364
55c11941
MS		 7365 if (CNIC_SUPPORT(bp)) {
7366 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7367 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7368 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7369 }
cdaa7cb8 7370
619c5cb6 7371 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7372
2b674047
DK		 7373 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7374
f2e0899f 7375 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7376
7377 if (IS_MF(bp))
7378 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7379 else if (bp->dev->mtu > 4096) {
7380 if (bp->flags & ONE_PORT_FLAG)
7381 low = 160;
7382 else {
7383 val = bp->dev->mtu;
7384 /* (24*1024 + val*4)/256 */
7385 low = 96 + (val/64) +
7386 ((val % 64) ? 1 : 0);
7387 }
7388 } else
7389 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7390 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7391 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7392 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7393 }
1c06328c 7394
619c5cb6
VZ		 7395 if (CHIP_MODE_IS_4_PORT(bp))
7396 REG_WR(bp, (BP_PORT(bp) ?
7397 BRB1_REG_MAC_GUARANTIED_1 :
7398 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7399
619c5cb6 7400 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7401 if (CHIP_IS_E3B0(bp)) {
7402 if (IS_MF_AFEX(bp)) {
7403 /* configure headers for AFEX mode */
7404 REG_WR(bp, BP_PORT(bp) ?
7405 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7406 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7407 REG_WR(bp, BP_PORT(bp) ?
7408 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7409 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7410 REG_WR(bp, BP_PORT(bp) ?
7411 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7412 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7413 } else {
7414 /* Ovlan exists only if we are in multi-function +
7415 * switch-dependent mode, in switch-independent there
7416 * is no ovlan headers
7417 */
7418 REG_WR(bp, BP_PORT(bp) ?
7419 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7420 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7421 (bp->path_has_ovlan ? 7 : 6));
7422 }
7423 }
356e2385 7424
619c5cb6
VZ		 7425 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7426 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7427 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7428 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7429
619c5cb6
VZ		 7430 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7431 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7432 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7433 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7434
619c5cb6
VZ		 7435 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7436 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7437
619c5cb6
VZ		 7438 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7439
7440 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7441 /* configure PBF to work without PAUSE mtu 9000 */
7442 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7443
f2e0899f
DK		 7444 /* update threshold */
7445 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7446 /* update init credit */
7447 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7448
f2e0899f
DK		 7449 /* probe changes */
7450 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7451 udelay(50);
7452 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7453 }
a2fbb9ea 7454
55c11941
MS		 7455 if (CNIC_SUPPORT(bp))
7456 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7457
619c5cb6
VZ		 7458 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7459 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7460
7461 if (CHIP_IS_E1(bp)) {
7462 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7463 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7464 }
619c5cb6 7465 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7466
619c5cb6 7467 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7468
619c5cb6 7469 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7470 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7471 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7472 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7473 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7474 val = IS_MF(bp) ? 0xF7 : 0x7;
7475 /* Enable DCBX attention for all but E1 */
7476 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7477 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7478
4293b9f5
DK		 7479 /* SCPAD_PARITY should NOT trigger close the gates */
7480 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7481 REG_WR(bp, reg,
7482 REG_RD(bp, reg) &
7483 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7484
7485 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7486 REG_WR(bp, reg,
7487 REG_RD(bp, reg) &
7488 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7489
619c5cb6
VZ		 7490 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7491
7492 if (!CHIP_IS_E1x(bp)) {
7493 /* Bit-map indicating which L2 hdrs may appear after the
7494 * basic Ethernet header
7495 */
a3348722
BW		 7496 if (IS_MF_AFEX(bp))
7497 REG_WR(bp, BP_PORT(bp) ?
7498 NIG_REG_P1_HDRS_AFTER_BASIC :
7499 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7500 else
7501 REG_WR(bp, BP_PORT(bp) ?
7502 NIG_REG_P1_HDRS_AFTER_BASIC :
7503 NIG_REG_P0_HDRS_AFTER_BASIC,
7504 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7505
7506 if (CHIP_IS_E3(bp))
7507 REG_WR(bp, BP_PORT(bp) ?
7508 NIG_REG_LLH1_MF_MODE :
7509 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7510 }
7511 if (!CHIP_IS_E3(bp))
7512 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7513
f2e0899f 7514 if (!CHIP_IS_E1(bp)) {
fb3bff17 7515 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7516 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7517 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7518
619c5cb6 7519 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7520 val = 0;
7521 switch (bp->mf_mode) {
7522 case MULTI_FUNCTION_SD:
7523 val = 1;
7524 break;
7525 case MULTI_FUNCTION_SI:
a3348722 7526 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7527 val = 2;
7528 break;
7529 }
7530
7531 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7532 NIG_REG_LLH0_CLS_TYPE), val);
7533 }
1c06328c
EG		 7534 {
7535 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7536 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7537 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7538 }
34f80b04
EG		 7539 }
7540
619c5cb6
VZ		 7541 /* If SPIO5 is set to generate interrupts, enable it for this port */
7542 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7543 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7544 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7545 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7546 val = REG_RD(bp, reg_addr);
f1410647 7547 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7548 REG_WR(bp, reg_addr, val);
f1410647 7549 }
a2fbb9ea 7550
34f80b04
EG		 7551 return 0;
7552}
7553
34f80b04
EG		 7554static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7555{
7556 int reg;
32d68de1 7557 u32 wb_write[2];
34f80b04 7558
f2e0899f 7559 if (CHIP_IS_E1(bp))
34f80b04 7560 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7561 else
7562 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7563
32d68de1
YM		 7564 wb_write[0] = ONCHIP_ADDR1(addr);
7565 wb_write[1] = ONCHIP_ADDR2(addr);
7566 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7567}
7568
b56e9670 7569void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7570{
7571 u32 data, ctl, cnt = 100;
7572 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7573 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7574 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7575 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7576 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7577 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7578
7579 /* Not supported in BC mode */
7580 if (CHIP_INT_MODE_IS_BC(bp))
7581 return;
7582
7583 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7584 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7585 IGU_REGULAR_CLEANUP_SET |
7586 IGU_REGULAR_BCLEANUP;
7587
7588 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7589 func_encode << IGU_CTRL_REG_FID_SHIFT |
7590 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7591
7592 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7593 data, igu_addr_data);
7594 REG_WR(bp, igu_addr_data, data);
7595 mmiowb();
7596 barrier();
7597 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7598 ctl, igu_addr_ctl);
7599 REG_WR(bp, igu_addr_ctl, ctl);
7600 mmiowb();
7601 barrier();
7602
7603 /* wait for clean up to finish */
7604 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7605 msleep(20);
7606
1191cb83
ED		 7607 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7608 DP(NETIF_MSG_HW,
7609 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7610 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7611 }
7612}
7613
7614static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7615{
619c5cb6 7616 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7617}
7618
1191cb83 7619static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7620{
7621 u32 i, base = FUNC_ILT_BASE(func);
7622 for (i = base; i < base + ILT_PER_FUNC; i++)
7623 bnx2x_ilt_wr(bp, i, 0);
7624}
7625
910cc727 7626static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7627{
7628 int port = BP_PORT(bp);
7629 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7630 /* T1 hash bits value determines the T1 number of entries */
7631 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7632}
7633
7634static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7635{
7636 int rc;
7637 struct bnx2x_func_state_params func_params = {NULL};
7638 struct bnx2x_func_switch_update_params *switch_update_params =
7639 &func_params.params.switch_update;
7640
7641 /* Prepare parameters for function state transitions */
7642 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7643 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7644
7645 func_params.f_obj = &bp->func_obj;
7646 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7647
7648 /* Function parameters */
7649 switch_update_params->suspend = suspend;
7650
7651 rc = bnx2x_func_state_change(bp, &func_params);
7652
7653 return rc;
7654}
7655
910cc727 7656static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7657{
7658 int rc, i, port = BP_PORT(bp);
7659 int vlan_en = 0, mac_en[NUM_MACS];
7660
55c11941
MS		 7661 /* Close input from network */
7662 if (bp->mf_mode == SINGLE_FUNCTION) {
7663 bnx2x_set_rx_filter(&bp->link_params, 0);
7664 } else {
7665 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7666 NIG_REG_LLH0_FUNC_EN);
7667 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7668 NIG_REG_LLH0_FUNC_EN, 0);
7669 for (i = 0; i < NUM_MACS; i++) {
7670 mac_en[i] = REG_RD(bp, port ?
7671 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7672 4 * i) :
7673 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7674 4 * i));
7675 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7676 4 * i) :
7677 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7678 }
7679 }
7680
7681 /* Close BMC to host */
7682 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7683 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7684
7685 /* Suspend Tx switching to the PF. Completion of this ramrod
7686 * further guarantees that all the packets of that PF / child
7687 * VFs in BRB were processed by the Parser, so it is safe to
7688 * change the NIC_MODE register.
7689 */
7690 rc = bnx2x_func_switch_update(bp, 1);
7691 if (rc) {
7692 BNX2X_ERR("Can't suspend tx-switching!\n");
7693 return rc;
7694 }
7695
7696 /* Change NIC_MODE register */
7697 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7698
7699 /* Open input from network */
7700 if (bp->mf_mode == SINGLE_FUNCTION) {
7701 bnx2x_set_rx_filter(&bp->link_params, 1);
7702 } else {
7703 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7704 NIG_REG_LLH0_FUNC_EN, vlan_en);
7705 for (i = 0; i < NUM_MACS; i++) {
7706 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7707 4 * i) :
7708 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7709 mac_en[i]);
7710 }
7711 }
7712
7713 /* Enable BMC to host */
7714 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7715 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7716
7717 /* Resume Tx switching to the PF */
7718 rc = bnx2x_func_switch_update(bp, 0);
7719 if (rc) {
7720 BNX2X_ERR("Can't resume tx-switching!\n");
7721 return rc;
7722 }
7723
7724 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7725 return 0;
7726}
7727
7728int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7729{
7730 int rc;
7731
7732 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7733
7734 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7735 /* Configure searcher as part of function hw init */
55c11941
MS		 7736 bnx2x_init_searcher(bp);
7737
7738 /* Reset NIC mode */
7739 rc = bnx2x_reset_nic_mode(bp);
7740 if (rc)
7741 BNX2X_ERR("Can't change NIC mode!\n");
7742 return rc;
7743 }
7744
7745 return 0;
7746}
7747
523224a3 7748static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7749{
7750 int port = BP_PORT(bp);
7751 int func = BP_FUNC(bp);
619c5cb6 7752 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7753 struct bnx2x_ilt *ilt = BP_ILT(bp);
7754 u16 cdu_ilt_start;
8badd27a 7755 u32 addr, val;
f4a66897 7756 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7757 int i, main_mem_width, rc;
34f80b04 7758
51c1a580 7759 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7760
619c5cb6 7761 /* FLR cleanup - hmmm */
89db4ad8
AE		 7762 if (!CHIP_IS_E1x(bp)) {
7763 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7764 if (rc) {
7765 bnx2x_fw_dump(bp);
89db4ad8 7766 return rc;
04c46736 7767 }
89db4ad8 7768 }
619c5cb6 7769
8badd27a 7770 /* set MSI reconfigure capability */
f2e0899f
DK		 7771 if (bp->common.int_block == INT_BLOCK_HC) {
7772 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7773 val = REG_RD(bp, addr);
7774 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7775 REG_WR(bp, addr, val);
7776 }
8badd27a 7777
619c5cb6
VZ		 7778 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7779 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7780
523224a3
DK		 7781 ilt = BP_ILT(bp);
7782 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7783
290ca2bb
AE		 7784 if (IS_SRIOV(bp))
7785 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7786 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7787
7788 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7789 * those of the VFs, so start line should be reset
7790 */
7791 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7792 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7793 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7794 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7795 bp->context[i].cxt_mapping;
7796 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7797 }
290ca2bb 7798
523224a3 7799 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7800
55c11941
MS		 7801 if (!CONFIGURE_NIC_MODE(bp)) {
7802 bnx2x_init_searcher(bp);
7803 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7804 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7805 } else {
7806 /* Set NIC mode */
7807 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 7808 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 7809 }
37b091ba 7810
619c5cb6 7811 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7812 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7813
7814 /* Turn on a single ISR mode in IGU if driver is going to use
7815 * INT#x or MSI
7816 */
7817 if (!(bp->flags & USING_MSIX_FLAG))
7818 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7819 /*
7820 * Timers workaround bug: function init part.
7821 * Need to wait 20msec after initializing ILT,
7822 * needed to make sure there are no requests in
7823 * one of the PXP internal queues with "old" ILT addresses
7824 */
7825 msleep(20);
7826 /*
7827 * Master enable - Due to WB DMAE writes performed before this
7828 * register is re-initialized as part of the regular function
7829 * init
7830 */
7831 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7832 /* Enable the function in IGU */
7833 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7834 }
7835
523224a3 7836 bp->dmae_ready = 1;
34f80b04 7837
619c5cb6 7838 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 7839
619c5cb6 7840 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7841 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7842
619c5cb6
VZ		 7843 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7844 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7845 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7846 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7847 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7848 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7849 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7850 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7851 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7852 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7853 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7854 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7855 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7856
7857 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7858 REG_WR(bp, QM_REG_PF_EN, 1);
7859
619c5cb6
VZ		 7860 if (!CHIP_IS_E1x(bp)) {
7861 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7862 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7863 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7864 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7865 }
7866 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7867
7868 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7869 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 7870 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 7871
7872 bnx2x_iov_init_dq(bp);
7873
619c5cb6
VZ		 7874 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7875 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7876 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7877 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7878 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7879 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7880 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7881 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7882 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7883 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7884 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7885
619c5cb6 7886 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 7887
619c5cb6 7888 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 7889
619c5cb6 7890 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7891 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7892
fb3bff17 7893 if (IS_MF(bp)) {
34f80b04 7894 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 7895 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 7896 }
7897
619c5cb6 7898 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 7899
34f80b04 7900 /* HC init per function */
f2e0899f
DK		 7901 if (bp->common.int_block == INT_BLOCK_HC) {
7902 if (CHIP_IS_E1H(bp)) {
7903 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7904
7905 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7906 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7907 }
619c5cb6 7908 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 7909
7910 } else {
7911 int num_segs, sb_idx, prod_offset;
7912
34f80b04
EG		 7913 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7914
619c5cb6 7915 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7916 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7917 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7918 }
7919
619c5cb6 7920 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7921
619c5cb6 7922 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7923 int dsb_idx = 0;
7924 /**
7925 * Producer memory:
7926 * E2 mode: address 0-135 match to the mapping memory;
7927 * 136 - PF0 default prod; 137 - PF1 default prod;
7928 * 138 - PF2 default prod; 139 - PF3 default prod;
7929 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7930 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7931 * 144-147 reserved.
7932 *
7933 * E1.5 mode - In backward compatible mode;
7934 * for non default SB; each even line in the memory
7935 * holds the U producer and each odd line hold
7936 * the C producer. The first 128 producers are for
7937 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7938 * producers are for the DSB for each PF.
7939 * Each PF has five segments: (the order inside each
7940 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7941 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7942 * 144-147 attn prods;
7943 */
7944 /* non-default-status-blocks */
7945 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7946 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7947 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7948 prod_offset = (bp->igu_base_sb + sb_idx) *
7949 num_segs;
7950
7951 for (i = 0; i < num_segs; i++) {
7952 addr = IGU_REG_PROD_CONS_MEMORY +
7953 (prod_offset + i) * 4;
7954 REG_WR(bp, addr, 0);
7955 }
7956 /* send consumer update with value 0 */
7957 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7958 USTORM_ID, 0, IGU_INT_NOP, 1);
7959 bnx2x_igu_clear_sb(bp,
7960 bp->igu_base_sb + sb_idx);
7961 }
7962
7963 /* default-status-blocks */
7964 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7965 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7966
7967 if (CHIP_MODE_IS_4_PORT(bp))
7968 dsb_idx = BP_FUNC(bp);
7969 else
3395a033 7970 dsb_idx = BP_VN(bp);
f2e0899f
DK		 7971
7972 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7973 IGU_BC_BASE_DSB_PROD + dsb_idx :
7974 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7975
3395a033
DK		 7976 /*
7977 * igu prods come in chunks of E1HVN_MAX (4) -
7978 * does not matters what is the current chip mode
7979 */
f2e0899f
DK		 7980 for (i = 0; i < (num_segs * E1HVN_MAX);
7981 i += E1HVN_MAX) {
7982 addr = IGU_REG_PROD_CONS_MEMORY +
7983 (prod_offset + i)*4;
7984 REG_WR(bp, addr, 0);
7985 }
7986 /* send consumer update with 0 */
7987 if (CHIP_INT_MODE_IS_BC(bp)) {
7988 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7989 USTORM_ID, 0, IGU_INT_NOP, 1);
7990 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7991 CSTORM_ID, 0, IGU_INT_NOP, 1);
7992 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7993 XSTORM_ID, 0, IGU_INT_NOP, 1);
7994 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7995 TSTORM_ID, 0, IGU_INT_NOP, 1);
7996 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7997 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7998 } else {
7999 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8000 USTORM_ID, 0, IGU_INT_NOP, 1);
8001 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8002 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8003 }
8004 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8005
16a5fd92 8006 /* !!! These should become driver const once
f2e0899f
DK		 8007 rf-tool supports split-68 const */
8008 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8009 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8010 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8011 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8012 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8013 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8014 }
34f80b04 8015 }
34f80b04 8016
c14423fe 8017 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 8018 REG_WR(bp, 0x2114, 0xffffffff);
8019 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 8020
f4a66897
VZ		 8021 if (CHIP_IS_E1x(bp)) {
8022 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8023 main_mem_base = HC_REG_MAIN_MEMORY +
8024 BP_PORT(bp) * (main_mem_size * 4);
8025 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8026 main_mem_width = 8;
8027
8028 val = REG_RD(bp, main_mem_prty_clr);
8029 if (val)
51c1a580
MS		 8030 DP(NETIF_MSG_HW,
8031 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8032 val);
f4a66897
VZ		 8033
8034 /* Clear "false" parity errors in MSI-X table */
8035 for (i = main_mem_base;
8036 i < main_mem_base + main_mem_size * 4;
8037 i += main_mem_width) {
8038 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8039 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8040 i, main_mem_width / 4);
8041 }
8042 /* Clear HC parity attention */
8043 REG_RD(bp, main_mem_prty_clr);
8044 }
8045
619c5cb6
VZ		 8046#ifdef BNX2X_STOP_ON_ERROR
8047 /* Enable STORMs SP logging */
8048 REG_WR8(bp, BAR_USTRORM_INTMEM +
8049 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8050 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8051 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8052 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8053 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8054 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8055 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8056#endif
8057
b7737c9b 8058 bnx2x_phy_probe(&bp->link_params);
f85582f8 8059
34f80b04
EG		 8060 return 0;
8061}
8062
55c11941
MS		 8063void bnx2x_free_mem_cnic(struct bnx2x *bp)
8064{
8065 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8066
8067 if (!CHIP_IS_E1x(bp))
8068 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8069 sizeof(struct host_hc_status_block_e2));
8070 else
8071 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8072 sizeof(struct host_hc_status_block_e1x));
8073
8074 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8075}
8076
9f6c9258 8077void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 8078{
a052997e
MS		 8079 int i;
8080
619c5cb6
VZ		 8081 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8082 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8083
b4cddbd6
AE		 8084 if (IS_VF(bp))
8085 return;
8086
8087 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8088 sizeof(struct host_sp_status_block));
8089
a2fbb9ea 8090 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 8091 sizeof(struct bnx2x_slowpath));
a2fbb9ea 8092
a052997e
MS		 8093 for (i = 0; i < L2_ILT_LINES(bp); i++)
8094 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8095 bp->context[i].size);
523224a3
DK		 8096 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8097
8098 BNX2X_FREE(bp->ilt->lines);
f85582f8 8099
7a9b2557 8100 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 8101
523224a3
DK		 8102 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8103 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 8104
05952246
YM		 8105 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8106
580d9d08 8107 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8108}
8109
55c11941 8110int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8111{
cd2b0389 8112 if (!CHIP_IS_E1x(bp)) {
619c5cb6 8113 /* size = the status block + ramrod buffers */
cd2b0389
JP		 8114 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8115 sizeof(struct host_hc_status_block_e2));
8116 if (!bp->cnic_sb.e2_sb)
8117 goto alloc_mem_err;
8118 } else {
8119 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8120 sizeof(struct host_hc_status_block_e1x));
8121 if (!bp->cnic_sb.e1x_sb)
8122 goto alloc_mem_err;
8123 }
8badd27a 8124
cd2b0389 8125 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
16a5fd92 8126 /* allocate searcher T2 table, as it wasn't allocated before */
cd2b0389
JP		 8127 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8128 if (!bp->t2)
8129 goto alloc_mem_err;
8130 }
55c11941
MS		 8131
8132 /* write address to which L5 should insert its values */
8133 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8134 &bp->slowpath->drv_info_to_mcp;
8135
8136 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8137 goto alloc_mem_err;
8138
8139 return 0;
8140
8141alloc_mem_err:
8142 bnx2x_free_mem_cnic(bp);
8143 BNX2X_ERR("Can't allocate memory\n");
8144 return -ENOMEM;
8145}
8146
8147int bnx2x_alloc_mem(struct bnx2x *bp)
8148{
8149 int i, allocated, context_size;
a2fbb9ea 8150
cd2b0389 8151 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
55c11941 8152 /* allocate searcher T2 table */
cd2b0389
JP		 8153 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8154 if (!bp->t2)
8155 goto alloc_mem_err;
8156 }
8badd27a 8157
cd2b0389
JP		 8158 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8159 sizeof(struct host_sp_status_block));
8160 if (!bp->def_status_blk)
8161 goto alloc_mem_err;
a2fbb9ea 8162
cd2b0389
JP		 8163 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8164 sizeof(struct bnx2x_slowpath));
8165 if (!bp->slowpath)
8166 goto alloc_mem_err;
a2fbb9ea 8167
a052997e
MS		 8168 /* Allocate memory for CDU context:
8169 * This memory is allocated separately and not in the generic ILT
8170 * functions because CDU differs in few aspects:
8171 * 1. There are multiple entities allocating memory for context -
8172 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8173 * its own ILT lines.
8174 * 2. Since CDU page-size is not a single 4KB page (which is the case
8175 * for the other ILT clients), to be efficient we want to support
8176 * allocation of sub-page-size in the last entry.
8177 * 3. Context pointers are used by the driver to pass to FW / update
8178 * the context (for the other ILT clients the pointers are used just to
8179 * free the memory during unload).
8180 */
8181 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8182
a052997e
MS		 8183 for (i = 0, allocated = 0; allocated < context_size; i++) {
8184 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8185 (context_size - allocated));
cd2b0389
JP		 8186 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8187 bp->context[i].size);
8188 if (!bp->context[i].vcxt)
8189 goto alloc_mem_err;
a052997e
MS		 8190 allocated += bp->context[i].size;
8191 }
cd2b0389
JP		 8192 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8193 GFP_KERNEL);
8194 if (!bp->ilt->lines)
8195 goto alloc_mem_err;
65abd74d 8196
523224a3
DK		 8197 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8198 goto alloc_mem_err;
65abd74d 8199
67c431a5
AE		 8200 if (bnx2x_iov_alloc_mem(bp))
8201 goto alloc_mem_err;
8202
9f6c9258 8203 /* Slow path ring */
cd2b0389
JP		 8204 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8205 if (!bp->spq)
8206 goto alloc_mem_err;
65abd74d 8207
523224a3 8208 /* EQ */
cd2b0389
JP		 8209 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8210 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8211 if (!bp->eq_ring)
8212 goto alloc_mem_err;
ab532cf3 8213
9f6c9258 8214 return 0;
e1510706 8215
9f6c9258
DK		 8216alloc_mem_err:
8217 bnx2x_free_mem(bp);
51c1a580 8218 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8219 return -ENOMEM;
65abd74d
YG		 8220}
8221
a2fbb9ea
ET		 8222/*
8223 * Init service functions
8224 */
a2fbb9ea 8225
619c5cb6
VZ		 8226int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8227 struct bnx2x_vlan_mac_obj *obj, bool set,
8228 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8229{
619c5cb6
VZ		 8230 int rc;
8231 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8232
619c5cb6 8233 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8234
619c5cb6
VZ		 8235 /* Fill general parameters */
8236 ramrod_param.vlan_mac_obj = obj;
8237 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8238
619c5cb6
VZ		 8239 /* Fill a user request section if needed */
8240 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8241 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8242
619c5cb6 8243 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8244
619c5cb6
VZ		 8245 /* Set the command: ADD or DEL */
8246 if (set)
8247 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8248 else
8249 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8250 }
8251
619c5cb6 8252 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8253
8254 if (rc == -EEXIST) {
8255 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8256 /* do not treat adding same MAC as error */
8257 rc = 0;
8258 } else if (rc < 0)
619c5cb6 8259 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8260
619c5cb6 8261 return rc;
a2fbb9ea
ET		 8262}
8263
619c5cb6
VZ		 8264int bnx2x_del_all_macs(struct bnx2x *bp,
8265 struct bnx2x_vlan_mac_obj *mac_obj,
8266 int mac_type, bool wait_for_comp)
e665bfda 8267{
619c5cb6
VZ		 8268 int rc;
8269 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8270
619c5cb6
VZ		 8271 /* Wait for completion of requested */
8272 if (wait_for_comp)
8273 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8274
619c5cb6
VZ		 8275 /* Set the mac type of addresses we want to clear */
8276 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8277
619c5cb6
VZ		 8278 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8279 if (rc < 0)
8280 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8281
619c5cb6 8282 return rc;
0793f83f
DK		 8283}
8284
619c5cb6 8285int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8286{
a3348722
BW		 8287 if (is_zero_ether_addr(bp->dev->dev_addr) &&
8288 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
51c1a580
MS		 8289 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8290 "Ignoring Zero MAC for STORAGE SD mode\n");
614c76df
DK		 8291 return 0;
8292 }
614c76df 8293
f8f4f61a
DK		 8294 if (IS_PF(bp)) {
8295 unsigned long ramrod_flags = 0;
0793f83f 8296
f8f4f61a
DK		 8297 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8298 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8299 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8300 &bp->sp_objs->mac_obj, set,
8301 BNX2X_ETH_MAC, &ramrod_flags);
8302 } else { /* vf */
8303 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8304 bp->fp->index, true);
8305 }
e665bfda 8306}
6e30dd4e 8307
619c5cb6 8308int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8309{
60cad4e6
AE		 8310 if (IS_PF(bp))
8311 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8312 else /* VF */
8313 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8314}
a2fbb9ea 8315
d6214d7a 8316/**
e8920674 8317 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8318 *
e8920674 8319 * @bp: driver handle
d6214d7a 8320 *
e8920674 8321 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8322 */
1ab4434c 8323int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8324{
1ab4434c
AE		 8325 int rc = 0;
8326
60cad4e6
AE		 8327 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8328 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8329 return -EINVAL;
60cad4e6 8330 }
1ab4434c 8331
9ee3d37b 8332 switch (int_mode) {
1ab4434c
AE		 8333 case BNX2X_INT_MODE_MSIX:
8334 /* attempt to enable msix */
8335 rc = bnx2x_enable_msix(bp);
8336
8337 /* msix attained */
8338 if (!rc)
8339 return 0;
8340
8341 /* vfs use only msix */
8342 if (rc && IS_VF(bp))
8343 return rc;
8344
8345 /* failed to enable multiple MSI-X */
8346 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8347 bp->num_queues,
8348 1 + bp->num_cnic_queues);
8349
8350 /* falling through... */
8351 case BNX2X_INT_MODE_MSI:
d6214d7a 8352 bnx2x_enable_msi(bp);
1ab4434c 8353
d6214d7a 8354 /* falling through... */
1ab4434c 8355 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8356 bp->num_ethernet_queues = 1;
8357 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8358 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8359 break;
d6214d7a 8360 default:
1ab4434c
AE		 8361 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8362 return -EINVAL;
9f6c9258 8363 }
1ab4434c 8364 return 0;
a2fbb9ea
ET		 8365}
8366
1ab4434c 8367/* must be called prior to any HW initializations */
c2bff63f
DK		 8368static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8369{
290ca2bb
AE		 8370 if (IS_SRIOV(bp))
8371 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8372 return L2_ILT_LINES(bp);
8373}
8374
523224a3
DK		 8375void bnx2x_ilt_set_info(struct bnx2x *bp)
8376{
8377 struct ilt_client_info *ilt_client;
8378 struct bnx2x_ilt *ilt = BP_ILT(bp);
8379 u16 line = 0;
8380
8381 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8382 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8383
8384 /* CDU */
8385 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8386 ilt_client->client_num = ILT_CLIENT_CDU;
8387 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8388 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8389 ilt_client->start = line;
619c5cb6 8390 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8391
8392 if (CNIC_SUPPORT(bp))
8393 line += CNIC_ILT_LINES;
523224a3
DK		 8394 ilt_client->end = line - 1;
8395
51c1a580 8396 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8397 ilt_client->start,
8398 ilt_client->end,
8399 ilt_client->page_size,
8400 ilt_client->flags,
8401 ilog2(ilt_client->page_size >> 12));
8402
8403 /* QM */
8404 if (QM_INIT(bp->qm_cid_count)) {
8405 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8406 ilt_client->client_num = ILT_CLIENT_QM;
8407 ilt_client->page_size = QM_ILT_PAGE_SZ;
8408 ilt_client->flags = 0;
8409 ilt_client->start = line;
8410
8411 /* 4 bytes for each cid */
8412 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8413 QM_ILT_PAGE_SZ);
8414
8415 ilt_client->end = line - 1;
8416
51c1a580
MS		 8417 DP(NETIF_MSG_IFUP,
8418 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8419 ilt_client->start,
8420 ilt_client->end,
8421 ilt_client->page_size,
8422 ilt_client->flags,
8423 ilog2(ilt_client->page_size >> 12));
523224a3 8424 }
523224a3 8425
55c11941
MS		 8426 if (CNIC_SUPPORT(bp)) {
8427 /* SRC */
8428 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8429 ilt_client->client_num = ILT_CLIENT_SRC;
8430 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8431 ilt_client->flags = 0;
8432 ilt_client->start = line;
8433 line += SRC_ILT_LINES;
8434 ilt_client->end = line - 1;
523224a3 8435
55c11941
MS		 8436 DP(NETIF_MSG_IFUP,
8437 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8438 ilt_client->start,
8439 ilt_client->end,
8440 ilt_client->page_size,
8441 ilt_client->flags,
8442 ilog2(ilt_client->page_size >> 12));
9f6c9258 8443
55c11941
MS		 8444 /* TM */
8445 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8446 ilt_client->client_num = ILT_CLIENT_TM;
8447 ilt_client->page_size = TM_ILT_PAGE_SZ;
8448 ilt_client->flags = 0;
8449 ilt_client->start = line;
8450 line += TM_ILT_LINES;
8451 ilt_client->end = line - 1;
523224a3 8452
55c11941
MS		 8453 DP(NETIF_MSG_IFUP,
8454 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8455 ilt_client->start,
8456 ilt_client->end,
8457 ilt_client->page_size,
8458 ilt_client->flags,
8459 ilog2(ilt_client->page_size >> 12));
8460 }
9f6c9258 8461
619c5cb6 8462 BUG_ON(line > ILT_MAX_LINES);
523224a3 8463}
f85582f8 8464
619c5cb6
VZ		 8465/**
8466 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8467 *
8468 * @bp: driver handle
8469 * @fp: pointer to fastpath
8470 * @init_params: pointer to parameters structure
8471 *
8472 * parameters configured:
8473 * - HC configuration
8474 * - Queue's CDU context
8475 */
1191cb83 8476static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8477 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8478{
6383c0b3 8479 u8 cos;
a052997e
MS		 8480 int cxt_index, cxt_offset;
8481
619c5cb6
VZ		 8482 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8483 if (!IS_FCOE_FP(fp)) {
8484 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8485 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8486
16a5fd92 8487 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8488 * to INIT state.
8489 */
8490 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8491 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8492
8493 /* HC rate */
8494 init_params->rx.hc_rate = bp->rx_ticks ?
8495 (1000000 / bp->rx_ticks) : 0;
8496 init_params->tx.hc_rate = bp->tx_ticks ?
8497 (1000000 / bp->tx_ticks) : 0;
8498
8499 /* FW SB ID */
8500 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8501 fp->fw_sb_id;
8502
8503 /*
8504 * CQ index among the SB indices: FCoE clients uses the default
8505 * SB, therefore it's different.
8506 */
6383c0b3
AE		 8507 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8508 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8509 }
8510
6383c0b3
AE		 8511 /* set maximum number of COSs supported by this queue */
8512 init_params->max_cos = fp->max_cos;
8513
51c1a580 8514 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8515 fp->index, init_params->max_cos);
8516
8517 /* set the context pointers queue object */
a052997e 8518 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8519 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8520 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8521 ILT_PAGE_CIDS);
6383c0b3 8522 init_params->cxts[cos] =
a052997e
MS		 8523 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8524 }
619c5cb6
VZ		 8525}
8526
910cc727 8527static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8528 struct bnx2x_queue_state_params *q_params,
8529 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8530 int tx_index, bool leading)
8531{
8532 memset(tx_only_params, 0, sizeof(*tx_only_params));
8533
8534 /* Set the command */
8535 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8536
8537 /* Set tx-only QUEUE flags: don't zero statistics */
8538 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8539
8540 /* choose the index of the cid to send the slow path on */
8541 tx_only_params->cid_index = tx_index;
8542
8543 /* Set general TX_ONLY_SETUP parameters */
8544 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8545
8546 /* Set Tx TX_ONLY_SETUP parameters */
8547 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8548
51c1a580
MS		 8549 DP(NETIF_MSG_IFUP,
8550 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8551 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8552 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8553 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8554
8555 /* send the ramrod */
8556 return bnx2x_queue_state_change(bp, q_params);
8557}
8558
619c5cb6
VZ		 8559/**
8560 * bnx2x_setup_queue - setup queue
8561 *
8562 * @bp: driver handle
8563 * @fp: pointer to fastpath
8564 * @leading: is leading
8565 *
8566 * This function performs 2 steps in a Queue state machine
8567 * actually: 1) RESET->INIT 2) INIT->SETUP
8568 */
8569
8570int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8571 bool leading)
8572{
3b603066 8573 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8574 struct bnx2x_queue_setup_params *setup_params =
8575 &q_params.params.setup;
6383c0b3
AE		 8576 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8577 &q_params.params.tx_only;
a2fbb9ea 8578 int rc;
6383c0b3
AE		 8579 u8 tx_index;
8580
51c1a580 8581 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8582
ec6ba945
VZ		 8583 /* reset IGU state skip FCoE L2 queue */
8584 if (!IS_FCOE_FP(fp))
8585 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8586 IGU_INT_ENABLE, 0);
a2fbb9ea 8587
15192a8c 8588 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8589 /* We want to wait for completion in this context */
8590 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8591
619c5cb6
VZ		 8592 /* Prepare the INIT parameters */
8593 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8594
619c5cb6
VZ		 8595 /* Set the command */
8596 q_params.cmd = BNX2X_Q_CMD_INIT;
8597
8598 /* Change the state to INIT */
8599 rc = bnx2x_queue_state_change(bp, &q_params);
8600 if (rc) {
6383c0b3 8601 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8602 return rc;
8603 }
ec6ba945 8604
51c1a580 8605 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8606
619c5cb6
VZ		 8607 /* Now move the Queue to the SETUP state... */
8608 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8609
619c5cb6
VZ		 8610 /* Set QUEUE flags */
8611 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8612
619c5cb6 8613 /* Set general SETUP parameters */
6383c0b3
AE		 8614 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8615 FIRST_TX_COS_INDEX);
619c5cb6 8616
6383c0b3 8617 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8618 &setup_params->rxq_params);
8619
6383c0b3
AE		 8620 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8621 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8622
8623 /* Set the command */
8624 q_params.cmd = BNX2X_Q_CMD_SETUP;
8625
55c11941
MS		 8626 if (IS_FCOE_FP(fp))
8627 bp->fcoe_init = true;
8628
619c5cb6
VZ		 8629 /* Change the state to SETUP */
8630 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8631 if (rc) {
8632 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8633 return rc;
8634 }
8635
8636 /* loop through the relevant tx-only indices */
8637 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8638 tx_index < fp->max_cos;
8639 tx_index++) {
8640
8641 /* prepare and send tx-only ramrod*/
8642 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8643 tx_only_params, tx_index, leading);
8644 if (rc) {
8645 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8646 fp->index, tx_index);
8647 return rc;
8648 }
8649 }
523224a3 8650
34f80b04 8651 return rc;
a2fbb9ea
ET		 8652}
8653
619c5cb6 8654static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8655{
619c5cb6 8656 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8657 struct bnx2x_fp_txdata *txdata;
3b603066 8658 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8659 int rc, tx_index;
8660
51c1a580 8661 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8662
15192a8c 8663 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8664 /* We want to wait for completion in this context */
8665 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8666
6383c0b3
AE		 8667 /* close tx-only connections */
8668 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8669 tx_index < fp->max_cos;
8670 tx_index++){
8671
8672 /* ascertain this is a normal queue*/
65565884 8673 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8674
51c1a580 8675 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8676 txdata->txq_index);
8677
8678 /* send halt terminate on tx-only connection */
8679 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8680 memset(&q_params.params.terminate, 0,
8681 sizeof(q_params.params.terminate));
8682 q_params.params.terminate.cid_index = tx_index;
8683
8684 rc = bnx2x_queue_state_change(bp, &q_params);
8685 if (rc)
8686 return rc;
8687
8688 /* send halt terminate on tx-only connection */
8689 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8690 memset(&q_params.params.cfc_del, 0,
8691 sizeof(q_params.params.cfc_del));
8692 q_params.params.cfc_del.cid_index = tx_index;
8693 rc = bnx2x_queue_state_change(bp, &q_params);
8694 if (rc)
8695 return rc;
8696 }
8697 /* Stop the primary connection: */
8698 /* ...halt the connection */
619c5cb6
VZ		 8699 q_params.cmd = BNX2X_Q_CMD_HALT;
8700 rc = bnx2x_queue_state_change(bp, &q_params);
8701 if (rc)
da5a662a 8702 return rc;
a2fbb9ea 8703
6383c0b3 8704 /* ...terminate the connection */
619c5cb6 8705 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8706 memset(&q_params.params.terminate, 0,
8707 sizeof(q_params.params.terminate));
8708 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8709 rc = bnx2x_queue_state_change(bp, &q_params);
8710 if (rc)
523224a3 8711 return rc;
6383c0b3 8712 /* ...delete cfc entry */
619c5cb6 8713 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8714 memset(&q_params.params.cfc_del, 0,
8715 sizeof(q_params.params.cfc_del));
8716 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8717 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8718}
8719
34f80b04
EG		 8720static void bnx2x_reset_func(struct bnx2x *bp)
8721{
8722 int port = BP_PORT(bp);
8723 int func = BP_FUNC(bp);
f2e0899f 8724 int i;
523224a3
DK		 8725
8726 /* Disable the function in the FW */
8727 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8728 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8729 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8730 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8731
8732 /* FP SBs */
ec6ba945 8733 for_each_eth_queue(bp, i) {
523224a3 8734 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8735 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8736 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8737 SB_DISABLED);
523224a3
DK		 8738 }
8739
55c11941
MS		 8740 if (CNIC_LOADED(bp))
8741 /* CNIC SB */
8742 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8743 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8744 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8745
523224a3 8746 /* SP SB */
619c5cb6 8747 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8748 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8749 SB_DISABLED);
523224a3
DK		 8750
8751 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8752 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8753 0);
34f80b04
EG		 8754
8755 /* Configure IGU */
f2e0899f
DK		 8756 if (bp->common.int_block == INT_BLOCK_HC) {
8757 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8758 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8759 } else {
8760 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8761 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8762 }
34f80b04 8763
55c11941
MS		 8764 if (CNIC_LOADED(bp)) {
8765 /* Disable Timer scan */
8766 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8767 /*
8768 * Wait for at least 10ms and up to 2 second for the timers
8769 * scan to complete
8770 */
8771 for (i = 0; i < 200; i++) {
639d65b8 8772 usleep_range(10000, 20000);
55c11941
MS		 8773 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8774 break;
8775 }
37b091ba 8776 }
34f80b04 8777 /* Clear ILT */
f2e0899f
DK		 8778 bnx2x_clear_func_ilt(bp, func);
8779
8780 /* Timers workaround bug for E2: if this is vnic-3,
8781 * we need to set the entire ilt range for this timers.
8782 */
619c5cb6 8783 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8784 struct ilt_client_info ilt_cli;
8785 /* use dummy TM client */
8786 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8787 ilt_cli.start = 0;
8788 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8789 ilt_cli.client_num = ILT_CLIENT_TM;
8790
8791 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8792 }
8793
8794 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 8795 if (!CHIP_IS_E1x(bp))
f2e0899f 8796 bnx2x_pf_disable(bp);
523224a3
DK		 8797
8798 bp->dmae_ready = 0;
34f80b04
EG		 8799}
8800
8801static void bnx2x_reset_port(struct bnx2x *bp)
8802{
8803 int port = BP_PORT(bp);
8804 u32 val;
8805
619c5cb6
VZ		 8806 /* Reset physical Link */
8807 bnx2x__link_reset(bp);
8808
34f80b04
EG		 8809 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8810
8811 /* Do not rcv packets to BRB */
8812 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8813 /* Do not direct rcv packets that are not for MCP to the BRB */
8814 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8815 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8816
8817 /* Configure AEU */
8818 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8819
8820 msleep(100);
8821 /* Check for BRB port occupancy */
8822 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8823 if (val)
8824 DP(NETIF_MSG_IFDOWN,
33471629 8825 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 8826
8827 /* TODO: Close Doorbell port? */
8828}
8829
1191cb83 8830static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 8831{
3b603066 8832 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 8833
619c5cb6
VZ		 8834 /* Prepare parameters for function state transitions */
8835 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 8836
619c5cb6
VZ		 8837 func_params.f_obj = &bp->func_obj;
8838 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 8839
619c5cb6 8840 func_params.params.hw_init.load_phase = load_code;
49d66772 8841
619c5cb6 8842 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 8843}
8844
1191cb83 8845static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 8846{
3b603066 8847 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 8848 int rc;
228241eb 8849
619c5cb6
VZ		 8850 /* Prepare parameters for function state transitions */
8851 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8852 func_params.f_obj = &bp->func_obj;
8853 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 8854
619c5cb6
VZ		 8855 /*
8856 * Try to stop the function the 'good way'. If fails (in case
8857 * of a parity error during bnx2x_chip_cleanup()) and we are
8858 * not in a debug mode, perform a state transaction in order to
8859 * enable further HW_RESET transaction.
8860 */
8861 rc = bnx2x_func_state_change(bp, &func_params);
8862 if (rc) {
34f80b04 8863#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 8864 return rc;
34f80b04 8865#else
51c1a580 8866 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 8867 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8868 return bnx2x_func_state_change(bp, &func_params);
34f80b04 8869#endif
228241eb 8870 }
a2fbb9ea 8871
619c5cb6
VZ		 8872 return 0;
8873}
523224a3 8874
619c5cb6
VZ		 8875/**
8876 * bnx2x_send_unload_req - request unload mode from the MCP.
8877 *
8878 * @bp: driver handle
8879 * @unload_mode: requested function's unload mode
8880 *
8881 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8882 */
8883u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8884{
8885 u32 reset_code = 0;
8886 int port = BP_PORT(bp);
3101c2bc 8887
619c5cb6 8888 /* Select the UNLOAD request mode */
65abd74d
YG		 8889 if (unload_mode == UNLOAD_NORMAL)
8890 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8891
7d0446c2 8892 else if (bp->flags & NO_WOL_FLAG)
65abd74d 8893 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 8894
7d0446c2 8895 else if (bp->wol) {
65abd74d
YG		 8896 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8897 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 8898 struct pci_dev *pdev = bp->pdev;
65abd74d 8899 u32 val;
f9977903
DK		 8900 u16 pmc;
8901
65abd74d 8902 /* The mac address is written to entries 1-4 to
f9977903
DK		 8903 * preserve entry 0 which is used by the PMF
8904 */
3395a033 8905 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 8906
8907 val = (mac_addr[0] << 8) | mac_addr[1];
8908 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8909
8910 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8911 (mac_addr[4] << 8) | mac_addr[5];
8912 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8913
f9977903 8914 /* Enable the PME and clear the status */
29ed74c3 8915 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 8916 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 8917 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 8918
65abd74d
YG		 8919 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8920
8921 } else
8922 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 8923
619c5cb6
VZ		 8924 /* Send the request to the MCP */
8925 if (!BP_NOMCP(bp))
8926 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8927 else {
8928 int path = BP_PATH(bp);
8929
51c1a580 8930 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 8931 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8932 bnx2x_load_count[path][2]);
8933 bnx2x_load_count[path][0]--;
8934 bnx2x_load_count[path][1 + port]--;
51c1a580 8935 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 8936 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8937 bnx2x_load_count[path][2]);
8938 if (bnx2x_load_count[path][0] == 0)
619c5cb6 8939 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 8940 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 8941 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8942 else
8943 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8944 }
8945
8946 return reset_code;
8947}
8948
8949/**
8950 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8951 *
8952 * @bp: driver handle
5d07d868 8953 * @keep_link: true iff link should be kept up
619c5cb6 8954 */
5d07d868 8955void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 8956{
5d07d868
YM		 8957 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8958
619c5cb6
VZ		 8959 /* Report UNLOAD_DONE to MCP */
8960 if (!BP_NOMCP(bp))
5d07d868 8961 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 8962}
8963
1191cb83 8964static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 8965{
8966 int tout = 50;
8967 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8968
8969 if (!bp->port.pmf)
8970 return 0;
8971
8972 /*
8973 * (assumption: No Attention from MCP at this stage)
16a5fd92 8974 * PMF probably in the middle of TX disable/enable transaction
6debea87 8975 * 1. Sync IRS for default SB
16a5fd92
YM		 8976 * 2. Sync SP queue - this guarantees us that attention handling started
8977 * 3. Wait, that TX disable/enable transaction completes
6debea87 8978 *
16a5fd92
YM		 8979 * 1+2 guarantee that if DCBx attention was scheduled it already changed
8980 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8981 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 8982 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8983 * transaction.
8984 */
8985
8986 /* make sure default SB ISR is done */
8987 if (msix)
8988 synchronize_irq(bp->msix_table[0].vector);
8989 else
8990 synchronize_irq(bp->pdev->irq);
8991
8992 flush_workqueue(bnx2x_wq);
8993
8994 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8995 BNX2X_F_STATE_STARTED && tout--)
8996 msleep(20);
8997
8998 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8999 BNX2X_F_STATE_STARTED) {
9000#ifdef BNX2X_STOP_ON_ERROR
51c1a580 9001 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 9002 return -EBUSY;
9003#else
9004 /*
9005 * Failed to complete the transaction in a "good way"
9006 * Force both transactions with CLR bit
9007 */
3b603066 9008 struct bnx2x_func_state_params func_params = {NULL};
6debea87 9009
51c1a580 9010 DP(NETIF_MSG_IFDOWN,
6bf07b8e 9011 "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
6debea87
DK		 9012
9013 func_params.f_obj = &bp->func_obj;
9014 __set_bit(RAMROD_DRV_CLR_ONLY,
9015 &func_params.ramrod_flags);
9016
9017 /* STARTED-->TX_ST0PPED */
9018 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9019 bnx2x_func_state_change(bp, &func_params);
9020
9021 /* TX_ST0PPED-->STARTED */
9022 func_params.cmd = BNX2X_F_CMD_TX_START;
9023 return bnx2x_func_state_change(bp, &func_params);
9024#endif
9025 }
9026
9027 return 0;
9028}
9029
5d07d868 9030void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 9031{
9032 int port = BP_PORT(bp);
6383c0b3
AE		 9033 int i, rc = 0;
9034 u8 cos;
3b603066 9035 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 9036 u32 reset_code;
9037
9038 /* Wait until tx fastpath tasks complete */
9039 for_each_tx_queue(bp, i) {
9040 struct bnx2x_fastpath *fp = &bp->fp[i];
9041
6383c0b3 9042 for_each_cos_in_tx_queue(fp, cos)
65565884 9043 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 9044#ifdef BNX2X_STOP_ON_ERROR
9045 if (rc)
9046 return;
9047#endif
9048 }
9049
9050 /* Give HW time to discard old tx messages */
0926d499 9051 usleep_range(1000, 2000);
619c5cb6
VZ		 9052
9053 /* Clean all ETH MACs */
15192a8c
BW		 9054 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9055 false);
619c5cb6
VZ		 9056 if (rc < 0)
9057 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9058
9059 /* Clean up UC list */
15192a8c 9060 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 9061 true);
9062 if (rc < 0)
51c1a580
MS		 9063 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9064 rc);
619c5cb6
VZ		 9065
9066 /* Disable LLH */
9067 if (!CHIP_IS_E1(bp))
9068 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9069
9070 /* Set "drop all" (stop Rx).
9071 * We need to take a netif_addr_lock() here in order to prevent
9072 * a race between the completion code and this code.
9073 */
9074 netif_addr_lock_bh(bp->dev);
9075 /* Schedule the rx_mode command */
9076 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9077 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9078 else
9079 bnx2x_set_storm_rx_mode(bp);
9080
9081 /* Cleanup multicast configuration */
9082 rparam.mcast_obj = &bp->mcast_obj;
9083 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9084 if (rc < 0)
9085 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9086
9087 netif_addr_unlock_bh(bp->dev);
9088
f1929b01 9089 bnx2x_iov_chip_cleanup(bp);
619c5cb6 9090
6debea87
DK		 9091 /*
9092 * Send the UNLOAD_REQUEST to the MCP. This will return if
9093 * this function should perform FUNC, PORT or COMMON HW
9094 * reset.
9095 */
9096 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9097
9098 /*
9099 * (assumption: No Attention from MCP at this stage)
16a5fd92 9100 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 9101 */
9102 rc = bnx2x_func_wait_started(bp);
9103 if (rc) {
9104 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9105#ifdef BNX2X_STOP_ON_ERROR
9106 return;
9107#endif
9108 }
9109
34f80b04 9110 /* Close multi and leading connections
619c5cb6
VZ		 9111 * Completions for ramrods are collected in a synchronous way
9112 */
55c11941 9113 for_each_eth_queue(bp, i)
619c5cb6 9114 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 9115#ifdef BNX2X_STOP_ON_ERROR
9116 return;
9117#else
228241eb 9118 goto unload_error;
523224a3 9119#endif
55c11941
MS		 9120
9121 if (CNIC_LOADED(bp)) {
9122 for_each_cnic_queue(bp, i)
9123 if (bnx2x_stop_queue(bp, i))
9124#ifdef BNX2X_STOP_ON_ERROR
9125 return;
9126#else
9127 goto unload_error;
9128#endif
9129 }
9130
619c5cb6
VZ		 9131 /* If SP settings didn't get completed so far - something
9132 * very wrong has happen.
9133 */
9134 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9135 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9136
619c5cb6
VZ		 9137#ifndef BNX2X_STOP_ON_ERROR
9138unload_error:
9139#endif
523224a3 9140 rc = bnx2x_func_stop(bp);
da5a662a 9141 if (rc) {
523224a3 9142 BNX2X_ERR("Function stop failed!\n");
da5a662a 9143#ifdef BNX2X_STOP_ON_ERROR
523224a3 9144 return;
523224a3 9145#endif
34f80b04 9146 }
a2fbb9ea 9147
523224a3
DK		 9148 /* Disable HW interrupts, NAPI */
9149 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9150 /* Delete all NAPI objects */
9151 bnx2x_del_all_napi(bp);
55c11941
MS		 9152 if (CNIC_LOADED(bp))
9153 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9154
9155 /* Release IRQs */
d6214d7a 9156 bnx2x_free_irq(bp);
523224a3 9157
a2fbb9ea 9158 /* Reset the chip */
619c5cb6
VZ		 9159 rc = bnx2x_reset_hw(bp, reset_code);
9160 if (rc)
9161 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 9162
619c5cb6 9163 /* Report UNLOAD_DONE to MCP */
5d07d868 9164 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9165}
9166
9f6c9258 9167void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9168{
9169 u32 val;
9170
51c1a580 9171 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9172
9173 if (CHIP_IS_E1(bp)) {
9174 int port = BP_PORT(bp);
9175 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9176 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9177
9178 val = REG_RD(bp, addr);
9179 val &= ~(0x300);
9180 REG_WR(bp, addr, val);
619c5cb6 9181 } else {
72fd0718
VZ		 9182 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9183 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9184 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9185 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9186 }
9187}
9188
72fd0718
VZ		 9189/* Close gates #2, #3 and #4: */
9190static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9191{
c9ee9206 9192 u32 val;
72fd0718
VZ		 9193
9194 /* Gates #2 and #4a are closed/opened for "not E1" only */
9195 if (!CHIP_IS_E1(bp)) {
9196 /* #4 */
c9ee9206 9197 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9198 /* #2 */
c9ee9206 9199 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9200 }
9201
9202 /* #3 */
c9ee9206
VZ		 9203 if (CHIP_IS_E1x(bp)) {
9204 /* Prevent interrupts from HC on both ports */
9205 val = REG_RD(bp, HC_REG_CONFIG_1);
9206 REG_WR(bp, HC_REG_CONFIG_1,
9207 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9208 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9209
9210 val = REG_RD(bp, HC_REG_CONFIG_0);
9211 REG_WR(bp, HC_REG_CONFIG_0,
9212 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9213 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9214 } else {
d82603c6 9215 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9216 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9217
9218 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9219 (!close) ?
9220 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9221 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9222 }
72fd0718 9223
51c1a580 9224 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9225 close ? "closing" : "opening");
9226 mmiowb();
9227}
9228
9229#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9230
9231static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9232{
9233 /* Do some magic... */
9234 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9235 *magic_val = val & SHARED_MF_CLP_MAGIC;
9236 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9237}
9238
e8920674
DK		 9239/**
9240 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9241 *
e8920674
DK		 9242 * @bp: driver handle
9243 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9244 */
9245static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9246{
9247 /* Restore the `magic' bit value... */
72fd0718
VZ		 9248 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9249 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9250 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9251}
9252
f85582f8 9253/**
e8920674 9254 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9255 *
e8920674
DK		 9256 * @bp: driver handle
9257 * @magic_val: old value of 'magic' bit.
9258 *
9259 * Takes care of CLP configurations.
72fd0718
VZ		 9260 */
9261static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9262{
9263 u32 shmem;
9264 u32 validity_offset;
9265
51c1a580 9266 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9267
9268 /* Set `magic' bit in order to save MF config */
9269 if (!CHIP_IS_E1(bp))
9270 bnx2x_clp_reset_prep(bp, magic_val);
9271
9272 /* Get shmem offset */
9273 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9274 validity_offset =
9275 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9276
9277 /* Clear validity map flags */
9278 if (shmem > 0)
9279 REG_WR(bp, shmem + validity_offset, 0);
9280}
9281
9282#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9283#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9284
e8920674
DK		 9285/**
9286 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9287 *
e8920674 9288 * @bp: driver handle
72fd0718 9289 */
1191cb83 9290static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9291{
9292 /* special handling for emulation and FPGA,
9293 wait 10 times longer */
9294 if (CHIP_REV_IS_SLOW(bp))
9295 msleep(MCP_ONE_TIMEOUT*10);
9296 else
9297 msleep(MCP_ONE_TIMEOUT);
9298}
9299
1b6e2ceb
DK		 9300/*
9301 * initializes bp->common.shmem_base and waits for validity signature to appear
9302 */
9303static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9304{
1b6e2ceb
DK		 9305 int cnt = 0;
9306 u32 val = 0;
72fd0718 9307
1b6e2ceb
DK		 9308 do {
9309 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9310 if (bp->common.shmem_base) {
9311 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9312 if (val & SHR_MEM_VALIDITY_MB)
9313 return 0;
9314 }
72fd0718 9315
1b6e2ceb 9316 bnx2x_mcp_wait_one(bp);
72fd0718 9317
1b6e2ceb 9318 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9319
1b6e2ceb 9320 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9321
1b6e2ceb
DK		 9322 return -ENODEV;
9323}
72fd0718 9324
1b6e2ceb
DK		 9325static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9326{
9327 int rc = bnx2x_init_shmem(bp);
72fd0718 9328
72fd0718
VZ		 9329 /* Restore the `magic' bit value */
9330 if (!CHIP_IS_E1(bp))
9331 bnx2x_clp_reset_done(bp, magic_val);
9332
9333 return rc;
9334}
9335
9336static void bnx2x_pxp_prep(struct bnx2x *bp)
9337{
9338 if (!CHIP_IS_E1(bp)) {
9339 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9340 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9341 mmiowb();
9342 }
9343}
9344
9345/*
9346 * Reset the whole chip except for:
9347 * - PCIE core
9348 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9349 * one reset bit)
9350 * - IGU
9351 * - MISC (including AEU)
9352 * - GRC
9353 * - RBCN, RBCP
9354 */
c9ee9206 9355static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9356{
9357 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9358 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9359
9360 /*
9361 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9362 * (per chip) blocks.
9363 */
9364 global_bits2 =
9365 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9366 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9367
c55e771b
BW		 9368 /* Don't reset the following blocks.
9369 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9370 * reset, as in 4 port device they might still be owned
9371 * by the MCP (there is only one leader per path).
9372 */
72fd0718
VZ		 9373 not_reset_mask1 =
9374 MISC_REGISTERS_RESET_REG_1_RST_HC |
9375 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9376 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9377
9378 not_reset_mask2 =
c9ee9206 9379 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9380 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9381 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9382 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9383 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9384 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9385 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9386 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9387 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9388 MISC_REGISTERS_RESET_REG_2_PGLC |
9389 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9390 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9391 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9392 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9393 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9394 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9395
8736c826
VZ		 9396 /*
9397 * Keep the following blocks in reset:
9398 * - all xxMACs are handled by the bnx2x_link code.
9399 */
9400 stay_reset2 =
8736c826
VZ		 9401 MISC_REGISTERS_RESET_REG_2_XMAC |
9402 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9403
9404 /* Full reset masks according to the chip */
72fd0718
VZ		 9405 reset_mask1 = 0xffffffff;
9406
9407 if (CHIP_IS_E1(bp))
9408 reset_mask2 = 0xffff;
8736c826 9409 else if (CHIP_IS_E1H(bp))
72fd0718 9410 reset_mask2 = 0x1ffff;
8736c826
VZ		 9411 else if (CHIP_IS_E2(bp))
9412 reset_mask2 = 0xfffff;
9413 else /* CHIP_IS_E3 */
9414 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9415
9416 /* Don't reset global blocks unless we need to */
9417 if (!global)
9418 reset_mask2 &= ~global_bits2;
9419
9420 /*
9421 * In case of attention in the QM, we need to reset PXP
9422 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9423 * because otherwise QM reset would release 'close the gates' shortly
9424 * before resetting the PXP, then the PSWRQ would send a write
9425 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9426 * read the payload data from PSWWR, but PSWWR would not
9427 * respond. The write queue in PGLUE would stuck, dmae commands
9428 * would not return. Therefore it's important to reset the second
9429 * reset register (containing the
9430 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9431 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9432 * bit).
9433 */
72fd0718
VZ		 9434 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9435 reset_mask2 & (~not_reset_mask2));
9436
c9ee9206
VZ		 9437 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9438 reset_mask1 & (~not_reset_mask1));
9439
72fd0718
VZ		 9440 barrier();
9441 mmiowb();
9442
8736c826
VZ		 9443 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9444 reset_mask2 & (~stay_reset2));
9445
9446 barrier();
9447 mmiowb();
9448
c9ee9206 9449 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9450 mmiowb();
9451}
9452
c9ee9206
VZ		 9453/**
9454 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9455 * It should get cleared in no more than 1s.
9456 *
9457 * @bp: driver handle
9458 *
9459 * It should get cleared in no more than 1s. Returns 0 if
9460 * pending writes bit gets cleared.
9461 */
9462static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9463{
9464 u32 cnt = 1000;
9465 u32 pend_bits = 0;
9466
9467 do {
9468 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9469
9470 if (pend_bits == 0)
9471 break;
9472
0926d499 9473 usleep_range(1000, 2000);
c9ee9206
VZ		 9474 } while (cnt-- > 0);
9475
9476 if (cnt <= 0) {
9477 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9478 pend_bits);
9479 return -EBUSY;
9480 }
9481
9482 return 0;
9483}
9484
9485static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9486{
9487 int cnt = 1000;
9488 u32 val = 0;
9489 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9490 u32 tags_63_32 = 0;
72fd0718
VZ		 9491
9492 /* Empty the Tetris buffer, wait for 1s */
9493 do {
9494 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9495 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9496 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9497 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9498 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9499 if (CHIP_IS_E3(bp))
9500 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9501
72fd0718
VZ		 9502 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9503 ((port_is_idle_0 & 0x1) == 0x1) &&
9504 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9505 (pgl_exp_rom2 == 0xffffffff) &&
9506 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9507 break;
0926d499 9508 usleep_range(1000, 2000);
72fd0718
VZ		 9509 } while (cnt-- > 0);
9510
9511 if (cnt <= 0) {
51c1a580
MS		 9512 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9513 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9514 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9515 pgl_exp_rom2);
9516 return -EAGAIN;
9517 }
9518
9519 barrier();
9520
9521 /* Close gates #2, #3 and #4 */
9522 bnx2x_set_234_gates(bp, true);
9523
c9ee9206
VZ		 9524 /* Poll for IGU VQs for 57712 and newer chips */
9525 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9526 return -EAGAIN;
9527
72fd0718
VZ		 9528 /* TBD: Indicate that "process kill" is in progress to MCP */
9529
9530 /* Clear "unprepared" bit */
9531 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9532 barrier();
9533
9534 /* Make sure all is written to the chip before the reset */
9535 mmiowb();
9536
9537 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9538 * PSWHST, GRC and PSWRD Tetris buffer.
9539 */
0926d499 9540 usleep_range(1000, 2000);
72fd0718
VZ		 9541
9542 /* Prepare to chip reset: */
9543 /* MCP */
c9ee9206
VZ		 9544 if (global)
9545 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9546
9547 /* PXP */
9548 bnx2x_pxp_prep(bp);
9549 barrier();
9550
9551 /* reset the chip */
c9ee9206 9552 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9553 barrier();
9554
9dcd9acd
DK		 9555 /* clear errors in PGB */
9556 if (!CHIP_IS_E1x(bp))
9557 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9558
72fd0718
VZ		 9559 /* Recover after reset: */
9560 /* MCP */
c9ee9206 9561 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9562 return -EAGAIN;
9563
c9ee9206
VZ		 9564 /* TBD: Add resetting the NO_MCP mode DB here */
9565
72fd0718
VZ		 9566 /* Open the gates #2, #3 and #4 */
9567 bnx2x_set_234_gates(bp, false);
9568
9569 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9570 * reset state, re-enable attentions. */
9571
a2fbb9ea
ET		 9572 return 0;
9573}
9574
910cc727 9575static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9576{
9577 int rc = 0;
c9ee9206 9578 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9579 u32 load_code;
9580
9581 /* if not going to reset MCP - load "fake" driver to reset HW while
9582 * driver is owner of the HW
9583 */
9584 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9585 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9586 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9587 if (!load_code) {
9588 BNX2X_ERR("MCP response failure, aborting\n");
9589 rc = -EAGAIN;
9590 goto exit_leader_reset;
9591 }
9592 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9593 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9594 BNX2X_ERR("MCP unexpected resp, aborting\n");
9595 rc = -EAGAIN;
9596 goto exit_leader_reset2;
9597 }
9598 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9599 if (!load_code) {
9600 BNX2X_ERR("MCP response failure, aborting\n");
9601 rc = -EAGAIN;
9602 goto exit_leader_reset2;
9603 }
9604 }
c9ee9206 9605
72fd0718 9606 /* Try to recover after the failure */
c9ee9206 9607 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9608 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9609 BP_PATH(bp));
72fd0718 9610 rc = -EAGAIN;
95c6c616 9611 goto exit_leader_reset2;
72fd0718
VZ		 9612 }
9613
c9ee9206
VZ		 9614 /*
9615 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9616 * state.
9617 */
72fd0718 9618 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9619 if (global)
9620 bnx2x_clear_reset_global(bp);
72fd0718 9621
95c6c616
AE		 9622exit_leader_reset2:
9623 /* unload "fake driver" if it was loaded */
9624 if (!global && !BP_NOMCP(bp)) {
9625 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9626 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9627 }
72fd0718
VZ		 9628exit_leader_reset:
9629 bp->is_leader = 0;
c9ee9206
VZ		 9630 bnx2x_release_leader_lock(bp);
9631 smp_mb();
72fd0718
VZ		 9632 return rc;
9633}
9634
1191cb83 9635static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9636{
9637 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9638
9639 /* Disconnect this device */
9640 netif_device_detach(bp->dev);
9641
9642 /*
9643 * Block ifup for all function on this engine until "process kill"
9644 * or power cycle.
9645 */
9646 bnx2x_set_reset_in_progress(bp);
9647
9648 /* Shut down the power */
9649 bnx2x_set_power_state(bp, PCI_D3hot);
9650
9651 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9652
9653 smp_mb();
9654}
9655
9656/*
9657 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9658 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9659 * will never be called when netif_running(bp->dev) is false.
9660 */
9661static void bnx2x_parity_recover(struct bnx2x *bp)
9662{
c9ee9206 9663 bool global = false;
7a752993 9664 u32 error_recovered, error_unrecovered;
95c6c616 9665 bool is_parity;
c9ee9206 9666
72fd0718
VZ		 9667 DP(NETIF_MSG_HW, "Handling parity\n");
9668 while (1) {
9669 switch (bp->recovery_state) {
9670 case BNX2X_RECOVERY_INIT:
9671 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9672 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9673 WARN_ON(!is_parity);
c9ee9206 9674
72fd0718 9675 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9676 if (bnx2x_trylock_leader_lock(bp)) {
9677 bnx2x_set_reset_in_progress(bp);
9678 /*
9679 * Check if there is a global attention and if
9680 * there was a global attention, set the global
9681 * reset bit.
9682 */
9683
9684 if (global)
9685 bnx2x_set_reset_global(bp);
9686
72fd0718 9687 bp->is_leader = 1;
c9ee9206 9688 }
72fd0718
VZ		 9689
9690 /* Stop the driver */
9691 /* If interface has been removed - break */
5d07d868 9692 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9693 return;
9694
9695 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9696
c9ee9206
VZ		 9697 /* Ensure "is_leader", MCP command sequence and
9698 * "recovery_state" update values are seen on other
9699 * CPUs.
72fd0718 9700 */
c9ee9206 9701 smp_mb();
72fd0718
VZ		 9702 break;
9703
9704 case BNX2X_RECOVERY_WAIT:
9705 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9706 if (bp->is_leader) {
c9ee9206 9707 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9708 bool other_load_status =
9709 bnx2x_get_load_status(bp, other_engine);
9710 bool load_status =
9711 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9712 global = bnx2x_reset_is_global(bp);
9713
9714 /*
9715 * In case of a parity in a global block, let
9716 * the first leader that performs a
9717 * leader_reset() reset the global blocks in
9718 * order to clear global attentions. Otherwise
16a5fd92 9719 * the gates will remain closed for that
c9ee9206
VZ		 9720 * engine.
9721 */
889b9af3
AE		 9722 if (load_status ||
9723 (global && other_load_status)) {
72fd0718
VZ		 9724 /* Wait until all other functions get
9725 * down.
9726 */
7be08a72 9727 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9728 HZ/10);
9729 return;
9730 } else {
9731 /* If all other functions got down -
9732 * try to bring the chip back to
9733 * normal. In any case it's an exit
9734 * point for a leader.
9735 */
c9ee9206
VZ		 9736 if (bnx2x_leader_reset(bp)) {
9737 bnx2x_recovery_failed(bp);
72fd0718
VZ		 9738 return;
9739 }
9740
c9ee9206
VZ		 9741 /* If we are here, means that the
9742 * leader has succeeded and doesn't
9743 * want to be a leader any more. Try
9744 * to continue as a none-leader.
9745 */
9746 break;
72fd0718
VZ		 9747 }
9748 } else { /* non-leader */
c9ee9206 9749 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 9750 /* Try to get a LEADER_LOCK HW lock as
9751 * long as a former leader may have
9752 * been unloaded by the user or
9753 * released a leadership by another
9754 * reason.
9755 */
c9ee9206 9756 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 9757 /* I'm a leader now! Restart a
9758 * switch case.
9759 */
9760 bp->is_leader = 1;
9761 break;
9762 }
9763
7be08a72 9764 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9765 HZ/10);
9766 return;
9767
c9ee9206
VZ		 9768 } else {
9769 /*
9770 * If there was a global attention, wait
9771 * for it to be cleared.
9772 */
9773 if (bnx2x_reset_is_global(bp)) {
9774 schedule_delayed_work(
7be08a72
AE		 9775 &bp->sp_rtnl_task,
9776 HZ/10);
c9ee9206
VZ		 9777 return;
9778 }
9779
7a752993
AE		 9780 error_recovered =
9781 bp->eth_stats.recoverable_error;
9782 error_unrecovered =
9783 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 9784 bp->recovery_state =
9785 BNX2X_RECOVERY_NIC_LOADING;
9786 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 9787 error_unrecovered++;
95c6c616 9788 netdev_err(bp->dev,
51c1a580 9789 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 9790 /* Disconnect this device */
9791 netif_device_detach(bp->dev);
9792 /* Shut down the power */
9793 bnx2x_set_power_state(
9794 bp, PCI_D3hot);
9795 smp_mb();
9796 } else {
c9ee9206
VZ		 9797 bp->recovery_state =
9798 BNX2X_RECOVERY_DONE;
7a752993 9799 error_recovered++;
c9ee9206
VZ		 9800 smp_mb();
9801 }
7a752993
AE		 9802 bp->eth_stats.recoverable_error =
9803 error_recovered;
9804 bp->eth_stats.unrecoverable_error =
9805 error_unrecovered;
c9ee9206 9806
72fd0718
VZ		 9807 return;
9808 }
9809 }
9810 default:
9811 return;
9812 }
9813 }
9814}
9815
56ad3152
MS		 9816static int bnx2x_close(struct net_device *dev);
9817
72fd0718
VZ		 9818/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9819 * scheduled on a general queue in order to prevent a dead lock.
9820 */
7be08a72 9821static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 9822{
7be08a72 9823 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 9824
9825 rtnl_lock();
9826
8395be5e
AE		 9827 if (!netif_running(bp->dev)) {
9828 rtnl_unlock();
9829 return;
9830 }
7be08a72 9831
6bf07b8e 9832 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 9833#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 9834 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9835 "you will need to reboot when done\n");
9836 goto sp_rtnl_not_reset;
7be08a72 9837#endif
7be08a72 9838 /*
b1fb8740
VZ		 9839 * Clear all pending SP commands as we are going to reset the
9840 * function anyway.
7be08a72 9841 */
b1fb8740
VZ		 9842 bp->sp_rtnl_state = 0;
9843 smp_mb();
9844
72fd0718 9845 bnx2x_parity_recover(bp);
b1fb8740 9846
8395be5e
AE		 9847 rtnl_unlock();
9848 return;
b1fb8740
VZ		 9849 }
9850
9851 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 9852#ifdef BNX2X_STOP_ON_ERROR
9853 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9854 "you will need to reboot when done\n");
9855 goto sp_rtnl_not_reset;
9856#endif
9857
b1fb8740
VZ		 9858 /*
9859 * Clear all pending SP commands as we are going to reset the
9860 * function anyway.
9861 */
9862 bp->sp_rtnl_state = 0;
9863 smp_mb();
9864
5d07d868 9865 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 9866 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740 9867
8395be5e
AE		 9868 rtnl_unlock();
9869 return;
72fd0718 9870 }
b1fb8740
VZ		 9871#ifdef BNX2X_STOP_ON_ERROR
9872sp_rtnl_not_reset:
9873#endif
9874 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9875 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 9876 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9877 bnx2x_after_function_update(bp);
8304859a
AE		 9878 /*
9879 * in case of fan failure we need to reset id if the "stop on error"
9880 * debug flag is set, since we trying to prevent permanent overheating
9881 * damage
9882 */
9883 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 9884 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 9885 netif_device_detach(bp->dev);
9886 bnx2x_close(bp->dev);
8395be5e
AE		 9887 rtnl_unlock();
9888 return;
8304859a
AE		 9889 }
9890
381ac16b
AE		 9891 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9892 DP(BNX2X_MSG_SP,
9893 "sending set mcast vf pf channel message from rtnl sp-task\n");
9894 bnx2x_vfpf_set_mcast(bp->dev);
9895 }
78c3bcc5
AE		 9896 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9897 &bp->sp_rtnl_state)){
9898 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9899 bnx2x_tx_disable(bp);
9900 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9901 }
9902 }
381ac16b 9903
8b09be5f
YM		 9904 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9905 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9906 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 9907 }
9908
3ec9f9ca
AE		 9909 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9910 &bp->sp_rtnl_state))
9911 bnx2x_pf_set_vfs_vlan(bp);
9912
6ffa39f2 9913 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 9914 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 9915 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 9916 }
07b4eb3b 9917
42f8277f
YM		 9918 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
9919 &bp->sp_rtnl_state))
9920 bnx2x_update_mng_version(bp);
9921
8395be5e
AE		 9922 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9923 * can be called from other contexts as well)
9924 */
34f80b04 9925 rtnl_unlock();
8395be5e 9926
6411280a 9927 /* enable SR-IOV if applicable */
8395be5e 9928 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 9929 &bp->sp_rtnl_state)) {
9930 bnx2x_disable_sriov(bp);
6411280a 9931 bnx2x_enable_sriov(bp);
3c76feff 9932 }
34f80b04
EG		 9933}
9934
3deb8167
YR		 9935static void bnx2x_period_task(struct work_struct *work)
9936{
9937 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9938
9939 if (!netif_running(bp->dev))
9940 goto period_task_exit;
9941
9942 if (CHIP_REV_IS_SLOW(bp)) {
9943 BNX2X_ERR("period task called on emulation, ignoring\n");
9944 goto period_task_exit;
9945 }
9946
9947 bnx2x_acquire_phy_lock(bp);
9948 /*
9949 * The barrier is needed to ensure the ordering between the writing to
9950 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9951 * the reading here.
9952 */
9953 smp_mb();
9954 if (bp->port.pmf) {
9955 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9956
9957 /* Re-queue task in 1 sec */
9958 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9959 }
9960
9961 bnx2x_release_phy_lock(bp);
9962period_task_exit:
9963 return;
9964}
9965
a2fbb9ea
ET		 9966/*
9967 * Init service functions
9968 */
9969
a8f47eb7 9970static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 9971{
9972 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9973 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9974 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 9975}
9976
1ef1d45a
BW		 9977static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9978 struct bnx2x_mac_vals *vals)
34f80b04 9979{
452427b0
YM		 9980 u32 val, base_addr, offset, mask, reset_reg;
9981 bool mac_stopped = false;
9982 u8 port = BP_PORT(bp);
34f80b04 9983
1ef1d45a
BW		 9984 /* reset addresses as they also mark which values were changed */
9985 vals->bmac_addr = 0;
9986 vals->umac_addr = 0;
9987 vals->xmac_addr = 0;
9988 vals->emac_addr = 0;
9989
452427b0 9990 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 9991
452427b0
YM		 9992 if (!CHIP_IS_E3(bp)) {
9993 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9994 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9995 if ((mask & reset_reg) && val) {
9996 u32 wb_data[2];
9997 BNX2X_DEV_INFO("Disable bmac Rx\n");
9998 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9999 : NIG_REG_INGRESS_BMAC0_MEM;
10000 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10001 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 10002
452427b0
YM		 10003 /*
10004 * use rd/wr since we cannot use dmae. This is safe
10005 * since MCP won't access the bus due to the request
10006 * to unload, and no function on the path can be
10007 * loaded at this time.
10008 */
10009 wb_data[0] = REG_RD(bp, base_addr + offset);
10010 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 10011 vals->bmac_addr = base_addr + offset;
10012 vals->bmac_val[0] = wb_data[0];
10013 vals->bmac_val[1] = wb_data[1];
452427b0 10014 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 10015 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10016 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 10017 }
10018 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 10019 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10020 vals->emac_val = REG_RD(bp, vals->emac_addr);
10021 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 10022 mac_stopped = true;
10023 } else {
10024 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10025 BNX2X_DEV_INFO("Disable xmac Rx\n");
10026 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10027 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10028 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10029 val & ~(1 << 1));
10030 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10031 val | (1 << 1));
1ef1d45a
BW		 10032 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10033 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10034 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 10035 mac_stopped = true;
10036 }
10037 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10038 if (mask & reset_reg) {
10039 BNX2X_DEV_INFO("Disable umac Rx\n");
10040 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1ef1d45a
BW		 10041 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10042 vals->umac_val = REG_RD(bp, vals->umac_addr);
10043 REG_WR(bp, vals->umac_addr, 0);
452427b0
YM		 10044 mac_stopped = true;
10045 }
10046 }
10047
10048 if (mac_stopped)
10049 msleep(20);
452427b0
YM		 10050}
10051
10052#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10053#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10054#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10055#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10056
91ebb929
YM		 10057#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10058#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10059#define BCM_5710_UNDI_FW_MF_VERS (0x05)
10060#define BNX2X_PREV_UNDI_MF_PORT(p) (0x1a150c + ((p) << 4))
10061#define BNX2X_PREV_UNDI_MF_FUNC(f) (0x1a184c + ((f) << 4))
10062static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
10063{
10064 u8 major, minor, version;
10065 u32 fw;
10066
10067 /* Must check that FW is loaded */
10068 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10069 MISC_REGISTERS_RESET_REG_1_RST_XSEM)) {
10070 BNX2X_DEV_INFO("XSEM is reset - UNDI MF FW is not loaded\n");
10071 return false;
10072 }
10073
10074 /* Read Currently loaded FW version */
10075 fw = REG_RD(bp, XSEM_REG_PRAM);
10076 major = fw & 0xff;
10077 minor = (fw >> 0x8) & 0xff;
10078 version = (fw >> 0x10) & 0xff;
10079 BNX2X_DEV_INFO("Loaded FW: 0x%08x: Major 0x%02x Minor 0x%02x Version 0x%02x\n",
10080 fw, major, minor, version);
10081
10082 if (major > BCM_5710_UNDI_FW_MF_MAJOR)
10083 return true;
10084
10085 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
10086 (minor > BCM_5710_UNDI_FW_MF_MINOR))
10087 return true;
10088
10089 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
10090 (minor == BCM_5710_UNDI_FW_MF_MINOR) &&
10091 (version >= BCM_5710_UNDI_FW_MF_VERS))
10092 return true;
10093
10094 return false;
10095}
10096
10097static void bnx2x_prev_unload_undi_mf(struct bnx2x *bp)
10098{
10099 int i;
10100
10101 /* Due to legacy (FW) code, the first function on each engine has a
10102 * different offset macro from the rest of the functions.
10103 * Setting this for all 8 functions is harmless regardless of whether
10104 * this is actually a multi-function device.
10105 */
10106 for (i = 0; i < 2; i++)
10107 REG_WR(bp, BNX2X_PREV_UNDI_MF_PORT(i), 1);
10108
10109 for (i = 2; i < 8; i++)
10110 REG_WR(bp, BNX2X_PREV_UNDI_MF_FUNC(i - 2), 1);
10111
10112 BNX2X_DEV_INFO("UNDI FW (MF) set to discard\n");
10113}
10114
1dd06ae8 10115static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
452427b0
YM		 10116{
10117 u16 rcq, bd;
10118 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
10119
10120 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10121 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10122
10123 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10124 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
10125
10126 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10127 port, bd, rcq);
10128}
10129
0329aba1 10130static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10131{
5d07d868
YM		 10132 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10133 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10134 if (!rc) {
10135 BNX2X_ERR("MCP response failure, aborting\n");
10136 return -EBUSY;
10137 }
10138
10139 return 0;
10140}
10141
c63da990
BW		 10142static struct bnx2x_prev_path_list *
10143 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10144{
10145 struct bnx2x_prev_path_list *tmp_list;
10146
10147 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10148 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10149 bp->pdev->bus->number == tmp_list->bus &&
10150 BP_PATH(bp) == tmp_list->path)
10151 return tmp_list;
10152
10153 return NULL;
10154}
10155
7fa6f340
YM		 10156static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10157{
10158 struct bnx2x_prev_path_list *tmp_list;
10159 int rc;
10160
10161 rc = down_interruptible(&bnx2x_prev_sem);
10162 if (rc) {
10163 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10164 return rc;
10165 }
10166
10167 tmp_list = bnx2x_prev_path_get_entry(bp);
10168 if (tmp_list) {
10169 tmp_list->aer = 1;
10170 rc = 0;
10171 } else {
10172 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10173 BP_PATH(bp));
10174 }
10175
10176 up(&bnx2x_prev_sem);
10177
10178 return rc;
10179}
10180
0329aba1 10181static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10182{
10183 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10184 bool rc = false;
452427b0
YM		 10185
10186 if (down_trylock(&bnx2x_prev_sem))
10187 return false;
10188
7fa6f340
YM		 10189 tmp_list = bnx2x_prev_path_get_entry(bp);
10190 if (tmp_list) {
10191 if (tmp_list->aer) {
10192 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10193 BP_PATH(bp));
10194 } else {
452427b0
YM		 10195 rc = true;
10196 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10197 BP_PATH(bp));
452427b0
YM		 10198 }
10199 }
10200
10201 up(&bnx2x_prev_sem);
10202
10203 return rc;
10204}
10205
178135c1
DK		 10206bool bnx2x_port_after_undi(struct bnx2x *bp)
10207{
10208 struct bnx2x_prev_path_list *entry;
10209 bool val;
10210
10211 down(&bnx2x_prev_sem);
10212
10213 entry = bnx2x_prev_path_get_entry(bp);
10214 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10215
10216 up(&bnx2x_prev_sem);
10217
10218 return val;
10219}
10220
c63da990 10221static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10222{
10223 struct bnx2x_prev_path_list *tmp_list;
10224 int rc;
10225
7fa6f340
YM		 10226 rc = down_interruptible(&bnx2x_prev_sem);
10227 if (rc) {
10228 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10229 return rc;
10230 }
10231
10232 /* Check whether the entry for this path already exists */
10233 tmp_list = bnx2x_prev_path_get_entry(bp);
10234 if (tmp_list) {
10235 if (!tmp_list->aer) {
10236 BNX2X_ERR("Re-Marking the path.\n");
10237 } else {
10238 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10239 BP_PATH(bp));
10240 tmp_list->aer = 0;
10241 }
10242 up(&bnx2x_prev_sem);
10243 return 0;
10244 }
10245 up(&bnx2x_prev_sem);
10246
10247 /* Create an entry for this path and add it */
ea4b3857 10248 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10249 if (!tmp_list) {
10250 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10251 return -ENOMEM;
10252 }
10253
10254 tmp_list->bus = bp->pdev->bus->number;
10255 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10256 tmp_list->path = BP_PATH(bp);
7fa6f340 10257 tmp_list->aer = 0;
c63da990 10258 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10259
10260 rc = down_interruptible(&bnx2x_prev_sem);
10261 if (rc) {
10262 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10263 kfree(tmp_list);
10264 } else {
7fa6f340
YM		 10265 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10266 BP_PATH(bp));
452427b0
YM		 10267 list_add(&tmp_list->list, &bnx2x_prev_list);
10268 up(&bnx2x_prev_sem);
10269 }
10270
10271 return rc;
10272}
10273
0329aba1 10274static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10275{
452427b0
YM		 10276 struct pci_dev *dev = bp->pdev;
10277
8eee694c
YM		 10278 if (CHIP_IS_E1x(bp)) {
10279 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10280 return -EINVAL;
10281 }
10282
10283 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10284 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10285 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10286 bp->common.bc_ver);
10287 return -EINVAL;
10288 }
452427b0 10289
8903b9eb
CL		 10290 if (!pci_wait_for_pending_transaction(dev))
10291 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10292
8eee694c 10293 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10294 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10295
10296 return 0;
10297}
10298
0329aba1 10299static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10300{
10301 int rc;
10302
10303 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10304
10305 /* Test if previous unload process was already finished for this path */
10306 if (bnx2x_prev_is_path_marked(bp))
10307 return bnx2x_prev_mcp_done(bp);
10308
04c46736
YM		 10309 BNX2X_DEV_INFO("Path is unmarked\n");
10310
452427b0
YM		 10311 /* If function has FLR capabilities, and existing FW version matches
10312 * the one required, then FLR will be sufficient to clean any residue
10313 * left by previous driver
10314 */
91ebb929 10315 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10316
10317 if (!rc) {
10318 /* fw version is good */
10319 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10320 rc = bnx2x_do_flr(bp);
10321 }
10322
10323 if (!rc) {
10324 /* FLR was performed */
10325 BNX2X_DEV_INFO("FLR successful\n");
10326 return 0;
10327 }
10328
10329 BNX2X_DEV_INFO("Could not FLR\n");
452427b0
YM		 10330
10331 /* Close the MCP request, return failure*/
10332 rc = bnx2x_prev_mcp_done(bp);
10333 if (!rc)
10334 rc = BNX2X_PREV_WAIT_NEEDED;
10335
10336 return rc;
10337}
10338
0329aba1 10339static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10340{
10341 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10342 bool prev_undi = false;
1ef1d45a
BW		 10343 struct bnx2x_mac_vals mac_vals;
10344
452427b0
YM		 10345 /* It is possible a previous function received 'common' answer,
10346 * but hasn't loaded yet, therefore creating a scenario of
10347 * multiple functions receiving 'common' on the same path.
10348 */
10349 BNX2X_DEV_INFO("Common unload Flow\n");
10350
1ef1d45a
BW		 10351 memset(&mac_vals, 0, sizeof(mac_vals));
10352
452427b0
YM		 10353 if (bnx2x_prev_is_path_marked(bp))
10354 return bnx2x_prev_mcp_done(bp);
10355
10356 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10357
10358 /* Reset should be performed after BRB is emptied */
10359 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10360 u32 timer_count = 1000;
452427b0
YM		 10361
10362 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10363 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10364
10365 /* close LLH filters towards the BRB */
10366 bnx2x_set_rx_filter(&bp->link_params, 0);
452427b0
YM		 10367
10368 /* Check if the UNDI driver was previously loaded
34f80b04
EG		 10369 * UNDI driver initializes CID offset for normal bell to 0x7
10370 */
452427b0
YM		 10371 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10372 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10373 if (tmp_reg == 0x7) {
10374 BNX2X_DEV_INFO("UNDI previously loaded\n");
10375 prev_undi = true;
10376 /* clear the UNDI indication */
10377 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
a74801c5
YM		 10378 /* clear possible idle check errors */
10379 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
34f80b04 10380 }
452427b0 10381 }
d46f7c4d
DK		 10382 if (!CHIP_IS_E1x(bp))
10383 /* block FW from writing to host */
10384 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10385
452427b0
YM		 10386 /* wait until BRB is empty */
10387 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10388 while (timer_count) {
10389 u32 prev_brb = tmp_reg;
34f80b04 10390
452427b0
YM		 10391 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10392 if (!tmp_reg)
10393 break;
619c5cb6 10394
452427b0 10395 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10396
452427b0
YM		 10397 /* reset timer as long as BRB actually gets emptied */
10398 if (prev_brb > tmp_reg)
10399 timer_count = 1000;
10400 else
10401 timer_count--;
da5a662a 10402
91ebb929
YM		 10403 /* New UNDI FW supports MF and contains better
10404 * cleaning methods - might be redundant but harmless.
10405 */
10406 if (bnx2x_prev_unload_undi_fw_supports_mf(bp)) {
10407 bnx2x_prev_unload_undi_mf(bp);
10408 } else if (prev_undi) {
10409 /* If UNDI resides in memory,
10410 * manually increment it
10411 */
452427b0 10412 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
91ebb929 10413 }
452427b0 10414 udelay(10);
7a06a122 10415 }
452427b0
YM		 10416
10417 if (!timer_count)
10418 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10419 }
f16da43b 10420
452427b0
YM		 10421 /* No packets are in the pipeline, path is ready for reset */
10422 bnx2x_reset_common(bp);
10423
1ef1d45a
BW		 10424 if (mac_vals.xmac_addr)
10425 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10426 if (mac_vals.umac_addr)
10427 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10428 if (mac_vals.emac_addr)
10429 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10430 if (mac_vals.bmac_addr) {
10431 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10432 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10433 }
10434
c63da990 10435 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10436 if (rc) {
10437 bnx2x_prev_mcp_done(bp);
10438 return rc;
10439 }
10440
10441 return bnx2x_prev_mcp_done(bp);
10442}
10443
24f06716
AE		 10444/* previous driver DMAE transaction may have occurred when pre-boot stage ended
10445 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10446 * the addresses of the transaction, resulting in was-error bit set in the pci
10447 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10448 * to clear the interrupt which detected this from the pglueb and the was done
10449 * bit
10450 */
0329aba1 10451static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
24f06716 10452{
4a25417c
AE		 10453 if (!CHIP_IS_E1x(bp)) {
10454 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10455 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
04c46736
YM		 10456 DP(BNX2X_MSG_SP,
10457 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
4a25417c
AE		 10458 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10459 1 << BP_FUNC(bp));
10460 }
24f06716
AE		 10461 }
10462}
10463
0329aba1 10464static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10465{
10466 int time_counter = 10;
10467 u32 rc, fw, hw_lock_reg, hw_lock_val;
10468 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10469
24f06716
AE		 10470 /* clear hw from errors which may have resulted from an interrupted
10471 * dmae transaction.
10472 */
10473 bnx2x_prev_interrupted_dmae(bp);
10474
10475 /* Release previously held locks */
452427b0
YM		 10476 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10477 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10478 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10479
3cdeec22 10480 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10481 if (hw_lock_val) {
10482 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10483 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10484 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10485 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10486 }
10487
10488 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10489 REG_WR(bp, hw_lock_reg, 0xffffffff);
10490 } else
10491 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10492
10493 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10494 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10495 bnx2x_release_alr(bp);
452427b0
YM		 10496 }
10497
452427b0 10498 do {
7fa6f340 10499 int aer = 0;
452427b0
YM		 10500 /* Lock MCP using an unload request */
10501 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10502 if (!fw) {
10503 BNX2X_ERR("MCP response failure, aborting\n");
10504 rc = -EBUSY;
10505 break;
10506 }
10507
7fa6f340
YM		 10508 rc = down_interruptible(&bnx2x_prev_sem);
10509 if (rc) {
10510 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10511 rc);
10512 } else {
10513 /* If Path is marked by EEH, ignore unload status */
10514 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10515 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10516 up(&bnx2x_prev_sem);
7fa6f340 10517 }
7fa6f340
YM		 10518
10519 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10520 rc = bnx2x_prev_unload_common(bp);
10521 break;
10522 }
10523
16a5fd92 10524 /* non-common reply from MCP might require looping */
452427b0
YM		 10525 rc = bnx2x_prev_unload_uncommon(bp);
10526 if (rc != BNX2X_PREV_WAIT_NEEDED)
10527 break;
10528
10529 msleep(20);
10530 } while (--time_counter);
10531
10532 if (!time_counter || rc) {
91ebb929
YM		 10533 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10534 rc = -EPROBE_DEFER;
452427b0
YM		 10535 }
10536
c63da990 10537 /* Mark function if its port was used to boot from SAN */
178135c1 10538 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10539 bp->link_params.feature_config_flags |=
10540 FEATURE_CONFIG_BOOT_FROM_SAN;
10541
452427b0
YM		 10542 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10543
10544 return rc;
34f80b04
EG		 10545}
10546
0329aba1 10547static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10548{
1d187b34 10549 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10550 u16 pmc;
34f80b04
EG		 10551
10552 /* Get the chip revision id and number. */
10553 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10554 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10555 id = ((val & 0xffff) << 16);
10556 val = REG_RD(bp, MISC_REG_CHIP_REV);
10557 id |= ((val & 0xf) << 12);
f22fdf25
YM		 10558
10559 /* Metal is read from PCI regs, but we can't access >=0x400 from
10560 * the configuration space (so we need to reg_rd)
10561 */
10562 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10563 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 10564 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10565 id |= (val & 0xf);
10566 bp->common.chip_id = id;
523224a3 10567
7e8e02df
BW		 10568 /* force 57811 according to MISC register */
10569 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10570 if (CHIP_IS_57810(bp))
10571 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10572 (bp->common.chip_id & 0x0000FFFF);
10573 else if (CHIP_IS_57810_MF(bp))
10574 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10575 (bp->common.chip_id & 0x0000FFFF);
10576 bp->common.chip_id |= 0x1;
10577 }
10578
523224a3
DK		 10579 /* Set doorbell size */
10580 bp->db_size = (1 << BNX2X_DB_SHIFT);
10581
619c5cb6 10582 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10583 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10584 if ((val & 1) == 0)
10585 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10586 else
10587 val = (val >> 1) & 1;
10588 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10589 "2_PORT_MODE");
10590 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10591 CHIP_2_PORT_MODE;
10592
10593 if (CHIP_MODE_IS_4_PORT(bp))
10594 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10595 else
10596 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10597 } else {
10598 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10599 bp->pfid = bp->pf_num; /* 0..7 */
10600 }
10601
51c1a580
MS		 10602 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10603
f2e0899f
DK		 10604 bp->link_params.chip_id = bp->common.chip_id;
10605 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10606
1c06328c
EG		 10607 val = (REG_RD(bp, 0x2874) & 0x55);
10608 if ((bp->common.chip_id & 0x1) ||
10609 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10610 bp->flags |= ONE_PORT_FLAG;
10611 BNX2X_DEV_INFO("single port device\n");
10612 }
10613
34f80b04 10614 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 10615 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 10616 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10617 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10618 bp->common.flash_size, bp->common.flash_size);
10619
1b6e2ceb
DK		 10620 bnx2x_init_shmem(bp);
10621
f2e0899f
DK		 10622 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10623 MISC_REG_GENERIC_CR_1 :
10624 MISC_REG_GENERIC_CR_0));
1b6e2ceb 10625
34f80b04 10626 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 10627 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 10628 if (SHMEM2_RD(bp, size) >
10629 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10630 bp->link_params.lfa_base =
10631 REG_RD(bp, bp->common.shmem2_base +
10632 (u32)offsetof(struct shmem2_region,
10633 lfa_host_addr[BP_PORT(bp)]));
10634 else
10635 bp->link_params.lfa_base = 0;
2691d51d
EG		 10636 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10637 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 10638
f2e0899f 10639 if (!bp->common.shmem_base) {
34f80b04
EG		 10640 BNX2X_DEV_INFO("MCP not active\n");
10641 bp->flags |= NO_MCP_FLAG;
10642 return;
10643 }
10644
34f80b04 10645 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 10646 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 10647
10648 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10649 SHARED_HW_CFG_LED_MODE_MASK) >>
10650 SHARED_HW_CFG_LED_MODE_SHIFT);
10651
c2c8b03e
EG		 10652 bp->link_params.feature_config_flags = 0;
10653 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10654 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10655 bp->link_params.feature_config_flags |=
10656 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10657 else
10658 bp->link_params.feature_config_flags &=
10659 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10660
34f80b04
EG		 10661 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10662 bp->common.bc_ver = val;
10663 BNX2X_DEV_INFO("bc_ver %X\n", val);
10664 if (val < BNX2X_BC_VER) {
10665 /* for now only warn
10666 * later we might need to enforce this */
51c1a580
MS		 10667 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10668 BNX2X_BC_VER, val);
34f80b04 10669 }
4d295db0 10670 bp->link_params.feature_config_flags |=
a22f0788 10671 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 10672 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10673
a22f0788
YR		 10674 bp->link_params.feature_config_flags |=
10675 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10676 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 10677 bp->link_params.feature_config_flags |=
10678 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10679 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 10680 bp->link_params.feature_config_flags |=
10681 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10682 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 10683
10684 bp->link_params.feature_config_flags |=
10685 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10686 FEATURE_CONFIG_MT_SUPPORT : 0;
10687
0e898dd7
BW		 10688 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10689 BC_SUPPORTS_PFC_STATS : 0;
85242eea 10690
2e499d3c
BW		 10691 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10692 BC_SUPPORTS_FCOE_FEATURES : 0;
10693
9876879f
BW		 10694 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10695 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 10696
10697 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10698 BC_SUPPORTS_RMMOD_CMD : 0;
10699
1d187b34
BW		 10700 boot_mode = SHMEM_RD(bp,
10701 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10702 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10703 switch (boot_mode) {
10704 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10705 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10706 break;
10707 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10708 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10709 break;
10710 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10711 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10712 break;
10713 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10714 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10715 break;
10716 }
10717
29ed74c3 10718 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 10719 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10720
72ce58c3 10721 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 10722 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 10723
10724 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10725 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10726 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10727 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10728
cdaa7cb8
VZ		 10729 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10730 val, val2, val3, val4);
34f80b04
EG		 10731}
10732
f2e0899f
DK		 10733#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10734#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10735
0329aba1 10736static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 10737{
10738 int pfid = BP_FUNC(bp);
f2e0899f
DK		 10739 int igu_sb_id;
10740 u32 val;
6383c0b3 10741 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 10742
10743 bp->igu_base_sb = 0xff;
f2e0899f 10744 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 10745 int vn = BP_VN(bp);
6383c0b3 10746 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 10747 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10748 FP_SB_MAX_E1x;
10749
10750 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10751 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10752
9b341bb1 10753 return 0;
f2e0899f
DK		 10754 }
10755
10756 /* IGU in normal mode - read CAM */
10757 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10758 igu_sb_id++) {
10759 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10760 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10761 continue;
10762 fid = IGU_FID(val);
10763 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10764 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10765 continue;
10766 if (IGU_VEC(val) == 0)
10767 /* default status block */
10768 bp->igu_dsb_id = igu_sb_id;
10769 else {
10770 if (bp->igu_base_sb == 0xff)
10771 bp->igu_base_sb = igu_sb_id;
6383c0b3 10772 igu_sb_cnt++;
f2e0899f
DK		 10773 }
10774 }
10775 }
619c5cb6 10776
6383c0b3 10777#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 10778 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10779 * optional that number of CAM entries will not be equal to the value
10780 * advertised in PCI.
10781 * Driver should use the minimal value of both as the actual status
10782 * block count
619c5cb6 10783 */
185d4c8b 10784 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 10785#endif
619c5cb6 10786
9b341bb1 10787 if (igu_sb_cnt == 0) {
f2e0899f 10788 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 10789 return -EINVAL;
10790 }
10791
10792 return 0;
f2e0899f
DK		 10793}
10794
1dd06ae8 10795static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 10796{
a22f0788
YR		 10797 int cfg_size = 0, idx, port = BP_PORT(bp);
10798
10799 /* Aggregation of supported attributes of all external phys */
10800 bp->port.supported[0] = 0;
10801 bp->port.supported[1] = 0;
b7737c9b
YR		 10802 switch (bp->link_params.num_phys) {
10803 case 1:
a22f0788
YR		 10804 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10805 cfg_size = 1;
10806 break;
b7737c9b 10807 case 2:
a22f0788
YR		 10808 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10809 cfg_size = 1;
10810 break;
10811 case 3:
10812 if (bp->link_params.multi_phy_config &
10813 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10814 bp->port.supported[1] =
10815 bp->link_params.phy[EXT_PHY1].supported;
10816 bp->port.supported[0] =
10817 bp->link_params.phy[EXT_PHY2].supported;
10818 } else {
10819 bp->port.supported[0] =
10820 bp->link_params.phy[EXT_PHY1].supported;
10821 bp->port.supported[1] =
10822 bp->link_params.phy[EXT_PHY2].supported;
10823 }
10824 cfg_size = 2;
10825 break;
b7737c9b 10826 }
a2fbb9ea 10827
a22f0788 10828 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 10829 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 10830 SHMEM_RD(bp,
a22f0788
YR		 10831 dev_info.port_hw_config[port].external_phy_config),
10832 SHMEM_RD(bp,
10833 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 10834 return;
f85582f8 10835 }
a2fbb9ea 10836
619c5cb6
VZ		 10837 if (CHIP_IS_E3(bp))
10838 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10839 else {
10840 switch (switch_cfg) {
10841 case SWITCH_CFG_1G:
10842 bp->port.phy_addr = REG_RD(
10843 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10844 break;
10845 case SWITCH_CFG_10G:
10846 bp->port.phy_addr = REG_RD(
10847 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10848 break;
10849 default:
10850 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10851 bp->port.link_config[0]);
10852 return;
10853 }
a2fbb9ea 10854 }
619c5cb6 10855 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 10856 /* mask what we support according to speed_cap_mask per configuration */
10857 for (idx = 0; idx < cfg_size; idx++) {
10858 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10859 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 10860 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 10861
a22f0788 10862 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10863 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 10864 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 10865
a22f0788 10866 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10867 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 10868 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 10869
a22f0788 10870 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10871 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 10872 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 10873
a22f0788 10874 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10875 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 10876 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 10877 SUPPORTED_1000baseT_Full);
a2fbb9ea 10878
a22f0788 10879 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10880 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 10881 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 10882
a22f0788 10883 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10884 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 10885 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 10886
10887 if (!(bp->link_params.speed_cap_mask[idx] &
10888 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10889 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 10890 }
a2fbb9ea 10891
a22f0788
YR		 10892 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10893 bp->port.supported[1]);
a2fbb9ea
ET		 10894}
10895
0329aba1 10896static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 10897{
a22f0788
YR		 10898 u32 link_config, idx, cfg_size = 0;
10899 bp->port.advertising[0] = 0;
10900 bp->port.advertising[1] = 0;
10901 switch (bp->link_params.num_phys) {
10902 case 1:
10903 case 2:
10904 cfg_size = 1;
10905 break;
10906 case 3:
10907 cfg_size = 2;
10908 break;
10909 }
10910 for (idx = 0; idx < cfg_size; idx++) {
10911 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10912 link_config = bp->port.link_config[idx];
10913 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 10914 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 10915 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10916 bp->link_params.req_line_speed[idx] =
10917 SPEED_AUTO_NEG;
10918 bp->port.advertising[idx] |=
10919 bp->port.supported[idx];
10bd1f24
MY		 10920 if (bp->link_params.phy[EXT_PHY1].type ==
10921 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10922 bp->port.advertising[idx] |=
10923 (SUPPORTED_100baseT_Half |
10924 SUPPORTED_100baseT_Full);
f85582f8
DK		 10925 } else {
10926 /* force 10G, no AN */
a22f0788
YR		 10927 bp->link_params.req_line_speed[idx] =
10928 SPEED_10000;
10929 bp->port.advertising[idx] |=
10930 (ADVERTISED_10000baseT_Full |
f85582f8 10931 ADVERTISED_FIBRE);
a22f0788 10932 continue;
f85582f8
DK		 10933 }
10934 break;
a2fbb9ea 10935
f85582f8 10936 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 10937 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10938 bp->link_params.req_line_speed[idx] =
10939 SPEED_10;
10940 bp->port.advertising[idx] |=
10941 (ADVERTISED_10baseT_Full |
f85582f8
DK		 10942 ADVERTISED_TP);
10943 } else {
51c1a580 10944 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 10945 link_config,
a22f0788 10946 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10947 return;
10948 }
10949 break;
a2fbb9ea 10950
f85582f8 10951 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 10952 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10953 bp->link_params.req_line_speed[idx] =
10954 SPEED_10;
10955 bp->link_params.req_duplex[idx] =
10956 DUPLEX_HALF;
10957 bp->port.advertising[idx] |=
10958 (ADVERTISED_10baseT_Half |
f85582f8
DK		 10959 ADVERTISED_TP);
10960 } else {
51c1a580 10961 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10962 link_config,
10963 bp->link_params.speed_cap_mask[idx]);
10964 return;
10965 }
10966 break;
a2fbb9ea 10967
f85582f8
DK		 10968 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10969 if (bp->port.supported[idx] &
10970 SUPPORTED_100baseT_Full) {
a22f0788
YR		 10971 bp->link_params.req_line_speed[idx] =
10972 SPEED_100;
10973 bp->port.advertising[idx] |=
10974 (ADVERTISED_100baseT_Full |
f85582f8
DK		 10975 ADVERTISED_TP);
10976 } else {
51c1a580 10977 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10978 link_config,
10979 bp->link_params.speed_cap_mask[idx]);
10980 return;
10981 }
10982 break;
a2fbb9ea 10983
f85582f8
DK		 10984 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10985 if (bp->port.supported[idx] &
10986 SUPPORTED_100baseT_Half) {
10987 bp->link_params.req_line_speed[idx] =
10988 SPEED_100;
10989 bp->link_params.req_duplex[idx] =
10990 DUPLEX_HALF;
a22f0788
YR		 10991 bp->port.advertising[idx] |=
10992 (ADVERTISED_100baseT_Half |
f85582f8
DK		 10993 ADVERTISED_TP);
10994 } else {
51c1a580 10995 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 10996 link_config,
10997 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10998 return;
10999 }
11000 break;
a2fbb9ea 11001
f85582f8 11002 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 11003 if (bp->port.supported[idx] &
11004 SUPPORTED_1000baseT_Full) {
11005 bp->link_params.req_line_speed[idx] =
11006 SPEED_1000;
11007 bp->port.advertising[idx] |=
11008 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 11009 ADVERTISED_TP);
11010 } else {
51c1a580 11011 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11012 link_config,
11013 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11014 return;
11015 }
11016 break;
a2fbb9ea 11017
f85582f8 11018 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 11019 if (bp->port.supported[idx] &
11020 SUPPORTED_2500baseX_Full) {
11021 bp->link_params.req_line_speed[idx] =
11022 SPEED_2500;
11023 bp->port.advertising[idx] |=
11024 (ADVERTISED_2500baseX_Full |
34f80b04 11025 ADVERTISED_TP);
f85582f8 11026 } else {
51c1a580 11027 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11028 link_config,
f85582f8
DK		 11029 bp->link_params.speed_cap_mask[idx]);
11030 return;
11031 }
11032 break;
a2fbb9ea 11033
f85582f8 11034 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 11035 if (bp->port.supported[idx] &
11036 SUPPORTED_10000baseT_Full) {
11037 bp->link_params.req_line_speed[idx] =
11038 SPEED_10000;
11039 bp->port.advertising[idx] |=
11040 (ADVERTISED_10000baseT_Full |
34f80b04 11041 ADVERTISED_FIBRE);
f85582f8 11042 } else {
51c1a580 11043 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11044 link_config,
f85582f8
DK		 11045 bp->link_params.speed_cap_mask[idx]);
11046 return;
11047 }
11048 break;
3c9ada22
YR		 11049 case PORT_FEATURE_LINK_SPEED_20G:
11050 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 11051
3c9ada22 11052 break;
f85582f8 11053 default:
51c1a580 11054 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 11055 link_config);
f85582f8
DK		 11056 bp->link_params.req_line_speed[idx] =
11057 SPEED_AUTO_NEG;
11058 bp->port.advertising[idx] =
11059 bp->port.supported[idx];
11060 break;
11061 }
a2fbb9ea 11062
a22f0788 11063 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 11064 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 11065 if (bp->link_params.req_flow_ctrl[idx] ==
11066 BNX2X_FLOW_CTRL_AUTO) {
11067 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11068 bp->link_params.req_flow_ctrl[idx] =
11069 BNX2X_FLOW_CTRL_NONE;
11070 else
11071 bnx2x_set_requested_fc(bp);
a22f0788 11072 }
a2fbb9ea 11073
51c1a580 11074 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 11075 bp->link_params.req_line_speed[idx],
11076 bp->link_params.req_duplex[idx],
11077 bp->link_params.req_flow_ctrl[idx],
11078 bp->port.advertising[idx]);
11079 }
a2fbb9ea
ET		 11080}
11081
0329aba1 11082static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 11083{
86564c3f
YM		 11084 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11085 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11086 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11087 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 11088}
11089
0329aba1 11090static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 11091{
34f80b04 11092 int port = BP_PORT(bp);
589abe3a 11093 u32 config;
c8c60d88 11094 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 11095
c18487ee 11096 bp->link_params.bp = bp;
34f80b04 11097 bp->link_params.port = port;
c18487ee 11098
c18487ee 11099 bp->link_params.lane_config =
a2fbb9ea 11100 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 11101
a22f0788 11102 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 11103 SHMEM_RD(bp,
b0261926
YR		 11104 dev_info.port_hw_config[port].speed_capability_mask) &
11105 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 11106 bp->link_params.speed_cap_mask[1] =
11107 SHMEM_RD(bp,
b0261926
YR		 11108 dev_info.port_hw_config[port].speed_capability_mask2) &
11109 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 11110 bp->port.link_config[0] =
a2fbb9ea
ET		 11111 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11112
a22f0788
YR		 11113 bp->port.link_config[1] =
11114 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 11115
a22f0788
YR		 11116 bp->link_params.multi_phy_config =
11117 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 11118 /* If the device is capable of WoL, set the default state according
11119 * to the HW
11120 */
4d295db0 11121 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 11122 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11123 (config & PORT_FEATURE_WOL_ENABLED));
11124
4ba7699b
YM		 11125 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11126 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11127 bp->flags |= NO_ISCSI_FLAG;
11128 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11129 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11130 bp->flags |= NO_FCOE_FLAG;
11131
51c1a580 11132 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11133 bp->link_params.lane_config,
a22f0788
YR		 11134 bp->link_params.speed_cap_mask[0],
11135 bp->port.link_config[0]);
a2fbb9ea 11136
a22f0788 11137 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11138 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11139 bnx2x_phy_probe(&bp->link_params);
c18487ee 11140 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11141
11142 bnx2x_link_settings_requested(bp);
11143
01cd4528
EG		 11144 /*
11145 * If connected directly, work with the internal PHY, otherwise, work
11146 * with the external PHY
11147 */
b7737c9b
YR		 11148 ext_phy_config =
11149 SHMEM_RD(bp,
11150 dev_info.port_hw_config[port].external_phy_config);
11151 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11152 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11153 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11154
11155 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11156 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11157 bp->mdio.prtad =
b7737c9b 11158 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11159
c8c60d88
YM		 11160 /* Configure link feature according to nvram value */
11161 eee_mode = (((SHMEM_RD(bp, dev_info.
11162 port_feature_config[port].eee_power_mode)) &
11163 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11164 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11165 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11166 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11167 EEE_MODE_ENABLE_LPI |
11168 EEE_MODE_OUTPUT_TIME;
11169 } else {
11170 bp->link_params.eee_mode = 0;
11171 }
0793f83f 11172}
01cd4528 11173
b306f5ed 11174void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11175{
9e62e912 11176 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11177 int port = BP_PORT(bp);
2ba45142 11178 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11179 drv_lic_key[port].max_iscsi_conn);
2ba45142 11180
55c11941
MS		 11181 if (!CNIC_SUPPORT(bp)) {
11182 bp->flags |= no_flags;
11183 return;
11184 }
11185
b306f5ed 11186 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11187 bp->cnic_eth_dev.max_iscsi_conn =
11188 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11189 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11190
b306f5ed
DK		 11191 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11192 bp->cnic_eth_dev.max_iscsi_conn);
11193
11194 /*
11195 * If maximum allowed number of connections is zero -
11196 * disable the feature.
11197 */
11198 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11199 bp->flags |= no_flags;
b306f5ed
DK		 11200}
11201
0329aba1 11202static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11203{
11204 /* Port info */
11205 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11206 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11207 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11208 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11209
11210 /* Node info */
11211 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11212 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11213 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11214 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11215}
86800194
DK		 11216
11217static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11218{
11219 u8 count = 0;
11220
11221 if (IS_MF(bp)) {
11222 u8 fid;
11223
11224 /* iterate over absolute function ids for this path: */
11225 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11226 if (IS_MF_SD(bp)) {
11227 u32 cfg = MF_CFG_RD(bp,
11228 func_mf_config[fid].config);
11229
11230 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11231 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11232 FUNC_MF_CFG_PROTOCOL_FCOE))
11233 count++;
11234 } else {
11235 u32 cfg = MF_CFG_RD(bp,
11236 func_ext_config[fid].
11237 func_cfg);
11238
11239 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11240 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11241 count++;
11242 }
11243 }
11244 } else { /* SF */
11245 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11246
11247 for (port = 0; port < port_cnt; port++) {
11248 u32 lic = SHMEM_RD(bp,
11249 drv_lic_key[port].max_fcoe_conn) ^
11250 FW_ENCODE_32BIT_PATTERN;
11251 if (lic)
11252 count++;
11253 }
11254 }
11255
11256 return count;
11257}
11258
0329aba1 11259static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11260{
11261 int port = BP_PORT(bp);
11262 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11263 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11264 drv_lic_key[port].max_fcoe_conn);
86800194 11265 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11266
55c11941
MS		 11267 if (!CNIC_SUPPORT(bp)) {
11268 bp->flags |= NO_FCOE_FLAG;
11269 return;
11270 }
11271
b306f5ed 11272 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11273 bp->cnic_eth_dev.max_fcoe_conn =
11274 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11275 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11276
0eb43b4b
BPG		 11277 /* Calculate the number of maximum allowed FCoE tasks */
11278 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11279
11280 /* check if FCoE resources must be shared between different functions */
11281 if (num_fcoe_func)
11282 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11283
bf61ee14
VZ		 11284 /* Read the WWN: */
11285 if (!IS_MF(bp)) {
11286 /* Port info */
11287 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11288 SHMEM_RD(bp,
2de67439 11289 dev_info.port_hw_config[port].
bf61ee14
VZ		 11290 fcoe_wwn_port_name_upper);
11291 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11292 SHMEM_RD(bp,
2de67439 11293 dev_info.port_hw_config[port].
bf61ee14
VZ		 11294 fcoe_wwn_port_name_lower);
11295
11296 /* Node info */
11297 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11298 SHMEM_RD(bp,
2de67439 11299 dev_info.port_hw_config[port].
bf61ee14
VZ		 11300 fcoe_wwn_node_name_upper);
11301 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11302 SHMEM_RD(bp,
2de67439 11303 dev_info.port_hw_config[port].
bf61ee14
VZ		 11304 fcoe_wwn_node_name_lower);
11305 } else if (!IS_MF_SD(bp)) {
bf61ee14
VZ		 11306 /*
11307 * Read the WWN info only if the FCoE feature is enabled for
11308 * this function.
11309 */
7b5342d9 11310 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912
DK		 11311 bnx2x_get_ext_wwn_info(bp, func);
11312
382e513a 11313 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
9e62e912 11314 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11315 }
bf61ee14 11316
b306f5ed 11317 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11318
bf61ee14
VZ		 11319 /*
11320 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11321 * disable the feature.
11322 */
2ba45142
VZ		 11323 if (!bp->cnic_eth_dev.max_fcoe_conn)
11324 bp->flags |= NO_FCOE_FLAG;
11325}
b306f5ed 11326
0329aba1 11327static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11328{
11329 /*
11330 * iSCSI may be dynamically disabled but reading
11331 * info here we will decrease memory usage by driver
11332 * if the feature is disabled for good
11333 */
11334 bnx2x_get_iscsi_info(bp);
11335 bnx2x_get_fcoe_info(bp);
11336}
2ba45142 11337
0329aba1 11338static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11339{
11340 u32 val, val2;
11341 int func = BP_ABS_FUNC(bp);
11342 int port = BP_PORT(bp);
2ba45142
VZ		 11343 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11344 u8 *fip_mac = bp->fip_mac;
0793f83f 11345
55c11941
MS		 11346 if (IS_MF(bp)) {
11347 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11348 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11349 * In non SD mode features configuration comes from struct
11350 * func_ext_config.
2ba45142 11351 */
55c11941 11352 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
0793f83f
DK		 11353 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11354 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11355 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11356 iscsi_mac_addr_upper);
0793f83f 11357 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11358 iscsi_mac_addr_lower);
2ba45142 11359 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11360 BNX2X_DEV_INFO
11361 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11362 } else {
2ba45142 11363 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11364 }
2ba45142
VZ		 11365
11366 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11367 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11368 fcoe_mac_addr_upper);
2ba45142 11369 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11370 fcoe_mac_addr_lower);
2ba45142 11371 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11372 BNX2X_DEV_INFO
11373 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11374 } else {
2ba45142 11375 bp->flags |= NO_FCOE_FLAG;
55c11941 11376 }
a3348722
BW		 11377
11378 bp->mf_ext_config = cfg;
11379
9e62e912 11380 } else { /* SD MODE */
55c11941
MS		 11381 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11382 /* use primary mac as iscsi mac */
11383 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11384
11385 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11386 BNX2X_DEV_INFO
11387 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11388 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11389 /* use primary mac as fip mac */
11390 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11391 BNX2X_DEV_INFO("SD FCoE MODE\n");
11392 BNX2X_DEV_INFO
11393 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11394 }
0793f83f 11395 }
a3348722 11396
82594f8f
YM		 11397 /* If this is a storage-only interface, use SAN mac as
11398 * primary MAC. Notice that for SD this is already the case,
11399 * as the SAN mac was copied from the primary MAC.
11400 */
11401 if (IS_MF_FCOE_AFEX(bp))
a3348722 11402 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11403 } else {
0793f83f 11404 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11405 iscsi_mac_upper);
0793f83f 11406 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11407 iscsi_mac_lower);
2ba45142 11408 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11409
11410 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11411 fcoe_fip_mac_upper);
c03bd39c 11412 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11413 fcoe_fip_mac_lower);
c03bd39c 11414 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11415 }
11416
55c11941 11417 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11418 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11419 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
426b9241
DK		 11420 memset(iscsi_mac, 0, ETH_ALEN);
11421 }
11422
55c11941 11423 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11424 if (!is_valid_ether_addr(fip_mac)) {
11425 bp->flags |= NO_FCOE_FLAG;
11426 memset(bp->fip_mac, 0, ETH_ALEN);
11427 }
55c11941
MS		 11428}
11429
0329aba1 11430static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11431{
11432 u32 val, val2;
11433 int func = BP_ABS_FUNC(bp);
11434 int port = BP_PORT(bp);
11435
11436 /* Zero primary MAC configuration */
11437 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11438
11439 if (BP_NOMCP(bp)) {
11440 BNX2X_ERROR("warning: random MAC workaround active\n");
11441 eth_hw_addr_random(bp->dev);
11442 } else if (IS_MF(bp)) {
11443 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11444 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11445 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11446 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11447 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11448
11449 if (CNIC_SUPPORT(bp))
11450 bnx2x_get_cnic_mac_hwinfo(bp);
11451 } else {
11452 /* in SF read MACs from port configuration */
11453 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11454 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11455 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11456
11457 if (CNIC_SUPPORT(bp))
11458 bnx2x_get_cnic_mac_hwinfo(bp);
11459 }
11460
3d7d562c
YM		 11461 if (!BP_NOMCP(bp)) {
11462 /* Read physical port identifier from shmem */
11463 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11464 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11465 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11466 bp->flags |= HAS_PHYS_PORT_ID;
11467 }
11468
55c11941 11469 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11470
614c76df 11471 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6 11472 dev_err(&bp->pdev->dev,
51c1a580
MS		 11473 "bad Ethernet MAC address configuration: %pM\n"
11474 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11475 bp->dev->dev_addr);
7964211d 11476}
51c1a580 11477
0329aba1 11478static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11479{
11480 int tmp;
11481 u32 cfg;
51c1a580 11482
aeeddb8b
YM		 11483 if (IS_VF(bp))
11484 return 0;
11485
7964211d
YM		 11486 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11487 /* Take function: tmp = func */
11488 tmp = BP_ABS_FUNC(bp);
11489 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11490 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11491 } else {
11492 /* Take port: tmp = port */
11493 tmp = BP_PORT(bp);
11494 cfg = SHMEM_RD(bp,
11495 dev_info.port_hw_config[tmp].generic_features);
11496 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11497 }
11498 return cfg;
34f80b04
EG		 11499}
11500
0329aba1 11501static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11502{
0793f83f 11503 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 11504 int vn;
0793f83f 11505 u32 val = 0;
34f80b04 11506 int rc = 0;
a2fbb9ea 11507
34f80b04 11508 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11509
6383c0b3
AE		 11510 /*
11511 * initialize IGU parameters
11512 */
f2e0899f
DK		 11513 if (CHIP_IS_E1x(bp)) {
11514 bp->common.int_block = INT_BLOCK_HC;
11515
11516 bp->igu_dsb_id = DEF_SB_IGU_ID;
11517 bp->igu_base_sb = 0;
f2e0899f
DK		 11518 } else {
11519 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 11520
16a5fd92 11521 /* do not allow device reset during IGU info processing */
7a06a122
DK		 11522 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11523
f2e0899f 11524 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 11525
11526 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11527 int tout = 5000;
11528
11529 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11530
11531 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11532 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11533 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11534
11535 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11536 tout--;
0926d499 11537 usleep_range(1000, 2000);
619c5cb6
VZ		 11538 }
11539
11540 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11541 dev_err(&bp->pdev->dev,
11542 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 11543 bnx2x_release_hw_lock(bp,
11544 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 11545 return -EPERM;
11546 }
11547 }
11548
f2e0899f 11549 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 11550 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 11551 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11552 } else
619c5cb6 11553 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 11554
9b341bb1 11555 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 11556 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 11557 if (rc)
11558 return rc;
f2e0899f 11559 }
619c5cb6
VZ		 11560
11561 /*
11562 * set base FW non-default (fast path) status block id, this value is
11563 * used to initialize the fw_sb_id saved on the fp/queue structure to
11564 * determine the id used by the FW.
11565 */
11566 if (CHIP_IS_E1x(bp))
11567 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11568 else /*
11569 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11570 * the same queue are indicated on the same IGU SB). So we prefer
11571 * FW and IGU SBs to be the same value.
11572 */
11573 bp->base_fw_ndsb = bp->igu_base_sb;
11574
11575 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11576 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11577 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 11578
11579 /*
11580 * Initialize MF configuration
11581 */
523224a3 11582
fb3bff17
DK		 11583 bp->mf_ov = 0;
11584 bp->mf_mode = 0;
3395a033 11585 vn = BP_VN(bp);
0793f83f 11586
f2e0899f 11587 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 11588 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11589 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11590 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11591
f2e0899f
DK		 11592 if (SHMEM2_HAS(bp, mf_cfg_addr))
11593 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11594 else
11595 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 11596 offsetof(struct shmem_region, func_mb) +
11597 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 11598 /*
11599 * get mf configuration:
16a5fd92 11600 * 1. Existence of MF configuration
0793f83f
DK		 11601 * 2. MAC address must be legal (check only upper bytes)
11602 * for Switch-Independent mode;
11603 * OVLAN must be legal for Switch-Dependent mode
11604 * 3. SF_MODE configures specific MF mode
11605 */
11606 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11607 /* get mf configuration */
11608 val = SHMEM_RD(bp,
11609 dev_info.shared_feature_config.config);
11610 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11611
11612 switch (val) {
11613 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11614 val = MF_CFG_RD(bp, func_mf_config[func].
11615 mac_upper);
11616 /* check for legal mac (upper bytes)*/
11617 if (val != 0xffff) {
11618 bp->mf_mode = MULTI_FUNCTION_SI;
11619 bp->mf_config[vn] = MF_CFG_RD(bp,
11620 func_mf_config[func].config);
11621 } else
51c1a580 11622 BNX2X_DEV_INFO("illegal MAC address for SI\n");
0793f83f 11623 break;
a3348722
BW		 11624 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11625 if ((!CHIP_IS_E1x(bp)) &&
11626 (MF_CFG_RD(bp, func_mf_config[func].
11627 mac_upper) != 0xffff) &&
11628 (SHMEM2_HAS(bp,
11629 afex_driver_support))) {
11630 bp->mf_mode = MULTI_FUNCTION_AFEX;
11631 bp->mf_config[vn] = MF_CFG_RD(bp,
11632 func_mf_config[func].config);
11633 } else {
11634 BNX2X_DEV_INFO("can not configure afex mode\n");
11635 }
11636 break;
0793f83f
DK		 11637 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11638 /* get OV configuration */
11639 val = MF_CFG_RD(bp,
11640 func_mf_config[FUNC_0].e1hov_tag);
11641 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11642
11643 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11644 bp->mf_mode = MULTI_FUNCTION_SD;
11645 bp->mf_config[vn] = MF_CFG_RD(bp,
11646 func_mf_config[func].config);
11647 } else
754a2f52 11648 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 11649 break;
3786b942
AE		 11650 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11651 bp->mf_config[vn] = 0;
11652 break;
0793f83f
DK		 11653 default:
11654 /* Unknown configuration: reset mf_config */
11655 bp->mf_config[vn] = 0;
51c1a580 11656 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 11657 }
11658 }
a2fbb9ea 11659
2691d51d 11660 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 11661 IS_MF(bp) ? "multi" : "single");
2691d51d 11662
0793f83f
DK		 11663 switch (bp->mf_mode) {
11664 case MULTI_FUNCTION_SD:
11665 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11666 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 11667 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 11668 bp->mf_ov = val;
619c5cb6
VZ		 11669 bp->path_has_ovlan = true;
11670
51c1a580
MS		 11671 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11672 func, bp->mf_ov, bp->mf_ov);
2691d51d 11673 } else {
619c5cb6 11674 dev_err(&bp->pdev->dev,
51c1a580
MS		 11675 "No valid MF OV for func %d, aborting\n",
11676 func);
619c5cb6 11677 return -EPERM;
34f80b04 11678 }
0793f83f 11679 break;
a3348722
BW		 11680 case MULTI_FUNCTION_AFEX:
11681 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11682 break;
0793f83f 11683 case MULTI_FUNCTION_SI:
51c1a580
MS		 11684 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11685 func);
0793f83f
DK		 11686 break;
11687 default:
11688 if (vn) {
619c5cb6 11689 dev_err(&bp->pdev->dev,
51c1a580
MS		 11690 "VN %d is in a single function mode, aborting\n",
11691 vn);
619c5cb6 11692 return -EPERM;
2691d51d 11693 }
0793f83f 11694 break;
34f80b04 11695 }
0793f83f 11696
619c5cb6
VZ		 11697 /* check if other port on the path needs ovlan:
11698 * Since MF configuration is shared between ports
11699 * Possible mixed modes are only
11700 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11701 */
11702 if (CHIP_MODE_IS_4_PORT(bp) &&
11703 !bp->path_has_ovlan &&
11704 !IS_MF(bp) &&
11705 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11706 u8 other_port = !BP_PORT(bp);
11707 u8 other_func = BP_PATH(bp) + 2*other_port;
11708 val = MF_CFG_RD(bp,
11709 func_mf_config[other_func].e1hov_tag);
11710 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11711 bp->path_has_ovlan = true;
11712 }
34f80b04 11713 }
a2fbb9ea 11714
e848582c
DK		 11715 /* adjust igu_sb_cnt to MF for E1H */
11716 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11717 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 11718
619c5cb6
VZ		 11719 /* port info */
11720 bnx2x_get_port_hwinfo(bp);
f2e0899f 11721
0793f83f
DK		 11722 /* Get MAC addresses */
11723 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 11724
2ba45142 11725 bnx2x_get_cnic_info(bp);
2ba45142 11726
34f80b04
EG		 11727 return rc;
11728}
11729
0329aba1 11730static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 11731{
11732 int cnt, i, block_end, rodi;
fcdf95cb 11733 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 11734 char str_id_reg[VENDOR_ID_LEN+1];
11735 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 11736 char *vpd_data;
11737 char *vpd_extended_data = NULL;
34f24c7f
VZ		 11738 u8 len;
11739
fcdf95cb 11740 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 11741 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11742
11743 if (cnt < BNX2X_VPD_LEN)
11744 goto out_not_found;
11745
fcdf95cb
BW		 11746 /* VPD RO tag should be first tag after identifier string, hence
11747 * we should be able to find it in first BNX2X_VPD_LEN chars
11748 */
11749 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 11750 PCI_VPD_LRDT_RO_DATA);
11751 if (i < 0)
11752 goto out_not_found;
11753
34f24c7f 11754 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 11755 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 11756
11757 i += PCI_VPD_LRDT_TAG_SIZE;
11758
fcdf95cb
BW		 11759 if (block_end > BNX2X_VPD_LEN) {
11760 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11761 if (vpd_extended_data == NULL)
11762 goto out_not_found;
11763
11764 /* read rest of vpd image into vpd_extended_data */
11765 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11766 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11767 block_end - BNX2X_VPD_LEN,
11768 vpd_extended_data + BNX2X_VPD_LEN);
11769 if (cnt < (block_end - BNX2X_VPD_LEN))
11770 goto out_not_found;
11771 vpd_data = vpd_extended_data;
11772 } else
11773 vpd_data = vpd_start;
11774
11775 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 11776
11777 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11778 PCI_VPD_RO_KEYWORD_MFR_ID);
11779 if (rodi < 0)
11780 goto out_not_found;
11781
11782 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11783
11784 if (len != VENDOR_ID_LEN)
11785 goto out_not_found;
11786
11787 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11788
11789 /* vendor specific info */
11790 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11791 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11792 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11793 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11794
11795 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11796 PCI_VPD_RO_KEYWORD_VENDOR0);
11797 if (rodi >= 0) {
11798 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11799
11800 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11801
11802 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11803 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11804 bp->fw_ver[len] = ' ';
11805 }
11806 }
fcdf95cb 11807 kfree(vpd_extended_data);
34f24c7f
VZ		 11808 return;
11809 }
11810out_not_found:
fcdf95cb 11811 kfree(vpd_extended_data);
34f24c7f
VZ		 11812 return;
11813}
11814
0329aba1 11815static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 11816{
11817 u32 flags = 0;
11818
11819 if (CHIP_REV_IS_FPGA(bp))
11820 SET_FLAGS(flags, MODE_FPGA);
11821 else if (CHIP_REV_IS_EMUL(bp))
11822 SET_FLAGS(flags, MODE_EMUL);
11823 else
11824 SET_FLAGS(flags, MODE_ASIC);
11825
11826 if (CHIP_MODE_IS_4_PORT(bp))
11827 SET_FLAGS(flags, MODE_PORT4);
11828 else
11829 SET_FLAGS(flags, MODE_PORT2);
11830
11831 if (CHIP_IS_E2(bp))
11832 SET_FLAGS(flags, MODE_E2);
11833 else if (CHIP_IS_E3(bp)) {
11834 SET_FLAGS(flags, MODE_E3);
11835 if (CHIP_REV(bp) == CHIP_REV_Ax)
11836 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 11837 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11838 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 11839 }
11840
11841 if (IS_MF(bp)) {
11842 SET_FLAGS(flags, MODE_MF);
11843 switch (bp->mf_mode) {
11844 case MULTI_FUNCTION_SD:
11845 SET_FLAGS(flags, MODE_MF_SD);
11846 break;
11847 case MULTI_FUNCTION_SI:
11848 SET_FLAGS(flags, MODE_MF_SI);
11849 break;
a3348722
BW		 11850 case MULTI_FUNCTION_AFEX:
11851 SET_FLAGS(flags, MODE_MF_AFEX);
11852 break;
619c5cb6
VZ		 11853 }
11854 } else
11855 SET_FLAGS(flags, MODE_SF);
11856
11857#if defined(__LITTLE_ENDIAN)
11858 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11859#else /*(__BIG_ENDIAN)*/
11860 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11861#endif
11862 INIT_MODE_FLAGS(bp) = flags;
11863}
11864
0329aba1 11865static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 11866{
f2e0899f 11867 int func;
34f80b04
EG		 11868 int rc;
11869
34f80b04 11870 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 11871 mutex_init(&bp->fw_mb_mutex);
42f8277f
YM		 11872 mutex_init(&bp->drv_info_mutex);
11873 bp->drv_info_mng_owner = false;
bb7e95c8 11874 spin_lock_init(&bp->stats_lock);
507393eb 11875 sema_init(&bp->stats_sema, 1);
55c11941 11876
1cf167f2 11877 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 11878 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 11879 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
1ab4434c
AE		 11880 if (IS_PF(bp)) {
11881 rc = bnx2x_get_hwinfo(bp);
11882 if (rc)
11883 return rc;
11884 } else {
e09b74d0 11885 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 11886 }
34f80b04 11887
619c5cb6
VZ		 11888 bnx2x_set_modes_bitmap(bp);
11889
11890 rc = bnx2x_alloc_mem_bp(bp);
11891 if (rc)
11892 return rc;
523224a3 11893
34f24c7f 11894 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 11895
11896 func = BP_FUNC(bp);
11897
34f80b04 11898 /* need to reset chip if undi was active */
1ab4434c 11899 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 11900 /* init fw_seq */
11901 bp->fw_seq =
11902 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11903 DRV_MSG_SEQ_NUMBER_MASK;
11904 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11905
91ebb929
YM		 11906 rc = bnx2x_prev_unload(bp);
11907 if (rc) {
11908 bnx2x_free_mem_bp(bp);
11909 return rc;
11910 }
452427b0
YM		 11911 }
11912
34f80b04 11913 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 11914 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 11915
11916 if (BP_NOMCP(bp) && (func == 0))
51c1a580 11917 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 11918
614c76df 11919 bp->disable_tpa = disable_tpa;
a3348722 11920 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
94d9de3c
MS		 11921 /* Reduce memory usage in kdump environment by disabling TPA */
11922 bp->disable_tpa |= reset_devices;
614c76df 11923
7a9b2557 11924 /* Set TPA flags */
614c76df 11925 if (bp->disable_tpa) {
621b4d66 11926 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11927 bp->dev->features &= ~NETIF_F_LRO;
11928 } else {
621b4d66 11929 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11930 bp->dev->features |= NETIF_F_LRO;
11931 }
11932
a18f5128
EG		 11933 if (CHIP_IS_E1(bp))
11934 bp->dropless_fc = 0;
11935 else
7964211d 11936 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 11937
8d5726c4 11938 bp->mrrs = mrrs;
7a9b2557 11939
a3348722 11940 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 11941 if (IS_VF(bp))
11942 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 11943
7d323bfd 11944 /* make sure that the numbers are in the right granularity */
523224a3
DK		 11945 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11946 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 11947
fc543637 11948 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 11949
11950 init_timer(&bp->timer);
11951 bp->timer.expires = jiffies + bp->current_interval;
11952 bp->timer.data = (unsigned long) bp;
11953 bp->timer.function = bnx2x_timer;
11954
0370cf90
BW		 11955 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11956 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11957 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11958 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11959 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11960 bnx2x_dcbx_init_params(bp);
11961 } else {
11962 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11963 }
e4901dde 11964
619c5cb6
VZ		 11965 if (CHIP_IS_E1x(bp))
11966 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11967 else
11968 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 11969
6383c0b3 11970 /* multiple tx priority */
1ab4434c
AE		 11971 if (IS_VF(bp))
11972 bp->max_cos = 1;
11973 else if (CHIP_IS_E1x(bp))
6383c0b3 11974 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 11975 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 11976 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 11977 else if (CHIP_IS_E3B0(bp))
6383c0b3 11978 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 11979 else
11980 BNX2X_ERR("unknown chip %x revision %x\n",
11981 CHIP_NUM(bp), CHIP_REV(bp));
11982 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 11983
55c11941
MS		 11984 /* We need at least one default status block for slow-path events,
11985 * second status block for the L2 queue, and a third status block for
16a5fd92 11986 * CNIC if supported.
55c11941 11987 */
60cad4e6
AE		 11988 if (IS_VF(bp))
11989 bp->min_msix_vec_cnt = 1;
11990 else if (CNIC_SUPPORT(bp))
55c11941 11991 bp->min_msix_vec_cnt = 3;
60cad4e6 11992 else /* PF w/o cnic */
55c11941
MS		 11993 bp->min_msix_vec_cnt = 2;
11994 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11995
5bb680d6
MS		 11996 bp->dump_preset_idx = 1;
11997
34f80b04 11998 return rc;
a2fbb9ea
ET		 11999}
12000
de0c62db
DK		 12001/****************************************************************************
12002* General service functions
12003****************************************************************************/
a2fbb9ea 12004
619c5cb6
VZ		 12005/*
12006 * net_device service functions
12007 */
12008
bb2a0f7a 12009/* called with rtnl_lock */
a2fbb9ea
ET		 12010static int bnx2x_open(struct net_device *dev)
12011{
12012 struct bnx2x *bp = netdev_priv(dev);
8395be5e 12013 int rc;
a2fbb9ea 12014
1355b704
MY		 12015 bp->stats_init = true;
12016
6eccabb3
EG		 12017 netif_carrier_off(dev);
12018
a2fbb9ea
ET		 12019 bnx2x_set_power_state(bp, PCI_D0);
12020
ad5afc89 12021 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 12022 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12023 * want the first function loaded on the current engine to
12024 * complete the recovery.
ad5afc89 12025 * Parity recovery is only relevant for PF driver.
c9ee9206 12026 */
ad5afc89 12027 if (IS_PF(bp)) {
1a6974b2
YM		 12028 int other_engine = BP_PATH(bp) ? 0 : 1;
12029 bool other_load_status, load_status;
12030 bool global = false;
12031
ad5afc89
AE		 12032 other_load_status = bnx2x_get_load_status(bp, other_engine);
12033 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12034 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12035 bnx2x_chk_parity_attn(bp, &global, true)) {
12036 do {
12037 /* If there are attentions and they are in a
12038 * global blocks, set the GLOBAL_RESET bit
12039 * regardless whether it will be this function
12040 * that will complete the recovery or not.
12041 */
12042 if (global)
12043 bnx2x_set_reset_global(bp);
72fd0718 12044
ad5afc89
AE		 12045 /* Only the first function on the current
12046 * engine should try to recover in open. In case
12047 * of attentions in global blocks only the first
12048 * in the chip should try to recover.
12049 */
12050 if ((!load_status &&
12051 (!global || !other_load_status)) &&
12052 bnx2x_trylock_leader_lock(bp) &&
12053 !bnx2x_leader_reset(bp)) {
12054 netdev_info(bp->dev,
12055 "Recovered in open\n");
12056 break;
12057 }
72fd0718 12058
ad5afc89
AE		 12059 /* recovery has failed... */
12060 bnx2x_set_power_state(bp, PCI_D3hot);
12061 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 12062
ad5afc89
AE		 12063 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12064 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 12065
ad5afc89
AE		 12066 return -EAGAIN;
12067 } while (0);
12068 }
12069 }
72fd0718
VZ		 12070
12071 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 12072 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12073 if (rc)
12074 return rc;
9a8130bc 12075 return 0;
a2fbb9ea
ET		 12076}
12077
bb2a0f7a 12078/* called with rtnl_lock */
56ad3152 12079static int bnx2x_close(struct net_device *dev)
a2fbb9ea 12080{
a2fbb9ea
ET		 12081 struct bnx2x *bp = netdev_priv(dev);
12082
12083 /* Unload the driver, release IRQs */
5d07d868 12084 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 12085
a2fbb9ea
ET		 12086 return 0;
12087}
12088
1191cb83
ED		 12089static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12090 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 12091{
619c5cb6
VZ		 12092 int mc_count = netdev_mc_count(bp->dev);
12093 struct bnx2x_mcast_list_elem *mc_mac =
cd2b0389 12094 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
619c5cb6 12095 struct netdev_hw_addr *ha;
6e30dd4e 12096
619c5cb6
VZ		 12097 if (!mc_mac)
12098 return -ENOMEM;
6e30dd4e 12099
619c5cb6 12100 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 12101
619c5cb6
VZ		 12102 netdev_for_each_mc_addr(ha, bp->dev) {
12103 mc_mac->mac = bnx2x_mc_addr(ha);
12104 list_add_tail(&mc_mac->link, &p->mcast_list);
12105 mc_mac++;
6e30dd4e 12106 }
619c5cb6
VZ		 12107
12108 p->mcast_list_len = mc_count;
12109
12110 return 0;
6e30dd4e
VZ		 12111}
12112
1191cb83 12113static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 12114 struct bnx2x_mcast_ramrod_params *p)
12115{
12116 struct bnx2x_mcast_list_elem *mc_mac =
12117 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12118 link);
12119
12120 WARN_ON(!mc_mac);
12121 kfree(mc_mac);
12122}
12123
12124/**
12125 * bnx2x_set_uc_list - configure a new unicast MACs list.
12126 *
12127 * @bp: driver handle
6e30dd4e 12128 *
619c5cb6 12129 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 12130 */
1191cb83 12131static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12132{
619c5cb6 12133 int rc;
6e30dd4e 12134 struct net_device *dev = bp->dev;
6e30dd4e 12135 struct netdev_hw_addr *ha;
15192a8c 12136 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12137 unsigned long ramrod_flags = 0;
6e30dd4e 12138
619c5cb6
VZ		 12139 /* First schedule a cleanup up of old configuration */
12140 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12141 if (rc < 0) {
12142 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12143 return rc;
12144 }
6e30dd4e
VZ		 12145
12146 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12147 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12148 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12149 if (rc == -EEXIST) {
12150 DP(BNX2X_MSG_SP,
12151 "Failed to schedule ADD operations: %d\n", rc);
12152 /* do not treat adding same MAC as error */
12153 rc = 0;
12154
12155 } else if (rc < 0) {
12156
619c5cb6
VZ		 12157 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12158 rc);
12159 return rc;
6e30dd4e
VZ		 12160 }
12161 }
12162
619c5cb6
VZ		 12163 /* Execute the pending commands */
12164 __set_bit(RAMROD_CONT, &ramrod_flags);
12165 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12166 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12167}
12168
1191cb83 12169static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 12170{
619c5cb6 12171 struct net_device *dev = bp->dev;
3b603066 12172 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12173 int rc = 0;
6e30dd4e 12174
619c5cb6 12175 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12176
619c5cb6
VZ		 12177 /* first, clear all configured multicast MACs */
12178 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12179 if (rc < 0) {
51c1a580 12180 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12181 return rc;
12182 }
6e30dd4e 12183
619c5cb6
VZ		 12184 /* then, configure a new MACs list */
12185 if (netdev_mc_count(dev)) {
12186 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12187 if (rc) {
51c1a580
MS		 12188 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12189 rc);
619c5cb6
VZ		 12190 return rc;
12191 }
6e30dd4e 12192
619c5cb6
VZ		 12193 /* Now add the new MACs */
12194 rc = bnx2x_config_mcast(bp, &rparam,
12195 BNX2X_MCAST_CMD_ADD);
12196 if (rc < 0)
51c1a580
MS		 12197 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12198 rc);
6e30dd4e 12199
619c5cb6
VZ		 12200 bnx2x_free_mcast_macs_list(&rparam);
12201 }
6e30dd4e 12202
619c5cb6 12203 return rc;
6e30dd4e
VZ		 12204}
12205
619c5cb6 12206/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12207static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12208{
12209 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12210
12211 if (bp->state != BNX2X_STATE_OPEN) {
12212 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12213 return;
8b09be5f
YM		 12214 } else {
12215 /* Schedule an SP task to handle rest of change */
230bb0f3
YM		 12216 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12217 NETIF_MSG_IFUP);
34f80b04 12218 }
8b09be5f
YM		 12219}
12220
12221void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12222{
12223 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12224
619c5cb6 12225 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12226
8b09be5f
YM		 12227 netif_addr_lock_bh(bp->dev);
12228
12229 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12230 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12231 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12232 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12233 CHIP_IS_E1(bp))) {
34f80b04 12234 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12235 } else {
381ac16b
AE		 12236 if (IS_PF(bp)) {
12237 /* some multicasts */
12238 if (bnx2x_set_mc_list(bp) < 0)
12239 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12240
8b09be5f
YM		 12241 /* release bh lock, as bnx2x_set_uc_list might sleep */
12242 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12243 if (bnx2x_set_uc_list(bp) < 0)
12244 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12245 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12246 } else {
12247 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12248 * wait for the pf's response).
381ac16b 12249 */
230bb0f3
YM		 12250 bnx2x_schedule_sp_rtnl(bp,
12251 BNX2X_SP_RTNL_VFPF_MCAST, 0);
381ac16b 12252 }
34f80b04
EG		 12253 }
12254
12255 bp->rx_mode = rx_mode;
614c76df
DK		 12256 /* handle ISCSI SD mode */
12257 if (IS_MF_ISCSI_SD(bp))
12258 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12259
12260 /* Schedule the rx_mode command */
12261 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12262 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12263 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12264 return;
12265 }
12266
381ac16b
AE		 12267 if (IS_PF(bp)) {
12268 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12269 netif_addr_unlock_bh(bp->dev);
381ac16b 12270 } else {
8b09be5f
YM		 12271 /* VF will need to request the PF to make this change, and so
12272 * the VF needs to release the bottom-half lock prior to the
12273 * request (as it will likely require sleep on the VF side)
381ac16b 12274 */
8b09be5f
YM		 12275 netif_addr_unlock_bh(bp->dev);
12276 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12277 }
34f80b04
EG		 12278}
12279
c18487ee 12280/* called with rtnl_lock */
01cd4528
EG		 12281static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12282 int devad, u16 addr)
a2fbb9ea 12283{
01cd4528
EG		 12284 struct bnx2x *bp = netdev_priv(netdev);
12285 u16 value;
12286 int rc;
a2fbb9ea 12287
01cd4528
EG		 12288 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12289 prtad, devad, addr);
a2fbb9ea 12290
01cd4528
EG		 12291 /* The HW expects different devad if CL22 is used */
12292 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12293
01cd4528 12294 bnx2x_acquire_phy_lock(bp);
e10bc84d 12295 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12296 bnx2x_release_phy_lock(bp);
12297 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12298
01cd4528
EG		 12299 if (!rc)
12300 rc = value;
12301 return rc;
12302}
a2fbb9ea 12303
01cd4528
EG		 12304/* called with rtnl_lock */
12305static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12306 u16 addr, u16 value)
12307{
12308 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12309 int rc;
12310
51c1a580
MS		 12311 DP(NETIF_MSG_LINK,
12312 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12313 prtad, devad, addr, value);
01cd4528 12314
01cd4528
EG		 12315 /* The HW expects different devad if CL22 is used */
12316 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12317
01cd4528 12318 bnx2x_acquire_phy_lock(bp);
e10bc84d 12319 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12320 bnx2x_release_phy_lock(bp);
12321 return rc;
12322}
c18487ee 12323
01cd4528
EG		 12324/* called with rtnl_lock */
12325static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12326{
12327 struct bnx2x *bp = netdev_priv(dev);
12328 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12329
01cd4528
EG		 12330 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12331 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 12332
01cd4528
EG		 12333 if (!netif_running(dev))
12334 return -EAGAIN;
12335
12336 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 12337}
12338
257ddbda 12339#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 12340static void poll_bnx2x(struct net_device *dev)
12341{
12342 struct bnx2x *bp = netdev_priv(dev);
14a15d61 12343 int i;
a2fbb9ea 12344
14a15d61
MS		 12345 for_each_eth_queue(bp, i) {
12346 struct bnx2x_fastpath *fp = &bp->fp[i];
12347 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12348 }
a2fbb9ea
ET		 12349}
12350#endif
12351
614c76df
DK		 12352static int bnx2x_validate_addr(struct net_device *dev)
12353{
12354 struct bnx2x *bp = netdev_priv(dev);
12355
e09b74d0
AE		 12356 /* query the bulletin board for mac address configured by the PF */
12357 if (IS_VF(bp))
12358 bnx2x_sample_bulletin(bp);
12359
51c1a580
MS		 12360 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12361 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12362 return -EADDRNOTAVAIL;
51c1a580 12363 }
614c76df
DK		 12364 return 0;
12365}
12366
3d7d562c
YM		 12367static int bnx2x_get_phys_port_id(struct net_device *netdev,
12368 struct netdev_phys_port_id *ppid)
12369{
12370 struct bnx2x *bp = netdev_priv(netdev);
12371
12372 if (!(bp->flags & HAS_PHYS_PORT_ID))
12373 return -EOPNOTSUPP;
12374
12375 ppid->id_len = sizeof(bp->phys_port_id);
12376 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12377
12378 return 0;
12379}
12380
c64213cd
SH		 12381static const struct net_device_ops bnx2x_netdev_ops = {
12382 .ndo_open = bnx2x_open,
12383 .ndo_stop = bnx2x_close,
12384 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 12385 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 12386 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 12387 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 12388 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 12389 .ndo_do_ioctl = bnx2x_ioctl,
12390 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 12391 .ndo_fix_features = bnx2x_fix_features,
12392 .ndo_set_features = bnx2x_set_features,
c64213cd 12393 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 12394#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 12395 .ndo_poll_controller = poll_bnx2x,
12396#endif
6383c0b3 12397 .ndo_setup_tc = bnx2x_setup_tc,
6411280a 12398#ifdef CONFIG_BNX2X_SRIOV
abc5a021 12399 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 12400 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 12401 .ndo_get_vf_config = bnx2x_get_vf_config,
6411280a 12402#endif
55c11941 12403#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 12404 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12405#endif
8f20aa57 12406
e0d1095a 12407#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 12408 .ndo_busy_poll = bnx2x_low_latency_recv,
8f20aa57 12409#endif
3d7d562c 12410 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
c64213cd
SH		 12411};
12412
1191cb83 12413static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 12414{
12415 struct device *dev = &bp->pdev->dev;
12416
8ceafbfa
LT		 12417 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12418 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 12419 dev_err(dev, "System does not support DMA, aborting\n");
12420 return -EIO;
12421 }
12422
12423 return 0;
12424}
12425
33d8e6a5
YM		 12426static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12427{
12428 if (bp->flags & AER_ENABLED) {
12429 pci_disable_pcie_error_reporting(bp->pdev);
12430 bp->flags &= ~AER_ENABLED;
12431 }
12432}
12433
1ab4434c
AE		 12434static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12435 struct net_device *dev, unsigned long board_type)
a2fbb9ea 12436{
a2fbb9ea 12437 int rc;
c22610d0 12438 u32 pci_cfg_dword;
65087cfe
AE		 12439 bool chip_is_e1x = (board_type == BCM57710 ||
12440 board_type == BCM57711 ||
12441 board_type == BCM57711E);
a2fbb9ea
ET		 12442
12443 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 12444
34f80b04
EG		 12445 bp->dev = dev;
12446 bp->pdev = pdev;
a2fbb9ea
ET		 12447
12448 rc = pci_enable_device(pdev);
12449 if (rc) {
cdaa7cb8
VZ		 12450 dev_err(&bp->pdev->dev,
12451 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 12452 goto err_out;
12453 }
12454
12455 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 12456 dev_err(&bp->pdev->dev,
12457 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 12458 rc = -ENODEV;
12459 goto err_out_disable;
12460 }
12461
1ab4434c
AE		 12462 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12463 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 12464 rc = -ENODEV;
12465 goto err_out_disable;
12466 }
12467
092a5fc9
YR		 12468 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12469 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12470 PCICFG_REVESION_ID_ERROR_VAL) {
12471 pr_err("PCI device error, probably due to fan failure, aborting\n");
12472 rc = -ENODEV;
12473 goto err_out_disable;
12474 }
12475
34f80b04
EG		 12476 if (atomic_read(&pdev->enable_cnt) == 1) {
12477 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12478 if (rc) {
cdaa7cb8
VZ		 12479 dev_err(&bp->pdev->dev,
12480 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 12481 goto err_out_disable;
12482 }
a2fbb9ea 12483
34f80b04
EG		 12484 pci_set_master(pdev);
12485 pci_save_state(pdev);
12486 }
a2fbb9ea 12487
1ab4434c 12488 if (IS_PF(bp)) {
29ed74c3 12489 if (!pdev->pm_cap) {
1ab4434c
AE		 12490 dev_err(&bp->pdev->dev,
12491 "Cannot find power management capability, aborting\n");
12492 rc = -EIO;
12493 goto err_out_release;
12494 }
a2fbb9ea
ET		 12495 }
12496
77c98e6a 12497 if (!pci_is_pcie(pdev)) {
51c1a580 12498 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 12499 rc = -EIO;
12500 goto err_out_release;
12501 }
12502
619c5cb6
VZ		 12503 rc = bnx2x_set_coherency_mask(bp);
12504 if (rc)
a2fbb9ea 12505 goto err_out_release;
a2fbb9ea 12506
34f80b04
EG		 12507 dev->mem_start = pci_resource_start(pdev, 0);
12508 dev->base_addr = dev->mem_start;
12509 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 12510
12511 dev->irq = pdev->irq;
12512
275f165f 12513 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 12514 if (!bp->regview) {
cdaa7cb8
VZ		 12515 dev_err(&bp->pdev->dev,
12516 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 12517 rc = -ENOMEM;
12518 goto err_out_release;
12519 }
12520
c22610d0
AE		 12521 /* In E1/E1H use pci device function given by kernel.
12522 * In E2/E3 read physical function from ME register since these chips
12523 * support Physical Device Assignment where kernel BDF maybe arbitrary
12524 * (depending on hypervisor).
12525 */
2de67439 12526 if (chip_is_e1x) {
c22610d0 12527 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 12528 } else {
12529 /* chip is E2/3*/
c22610d0
AE		 12530 pci_read_config_dword(bp->pdev,
12531 PCICFG_ME_REGISTER, &pci_cfg_dword);
12532 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 12533 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 12534 }
51c1a580 12535 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 12536
34f80b04
EG		 12537 /* clean indirect addresses */
12538 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12539 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5
YM		 12540
12541 /* AER (Advanced Error reporting) configuration */
12542 rc = pci_enable_pcie_error_reporting(pdev);
12543 if (!rc)
12544 bp->flags |= AER_ENABLED;
12545 else
12546 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12547
a5c53dbc
DK		 12548 /*
12549 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 12550 * is not used by the driver.
12551 */
1ab4434c
AE		 12552 if (IS_PF(bp)) {
12553 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12554 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12555 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12556 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12557
12558 if (chip_is_e1x) {
12559 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12560 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12561 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12562 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12563 }
a5c53dbc 12564
1ab4434c
AE		 12565 /* Enable internal target-read (in case we are probed after PF
12566 * FLR). Must be done prior to any BAR read access. Only for
12567 * 57712 and up
12568 */
12569 if (!chip_is_e1x)
12570 REG_WR(bp,
12571 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 12572 }
a2fbb9ea 12573
34f80b04 12574 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 12575
c64213cd 12576 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 12577 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 12578
01789349
JP		 12579 dev->priv_flags |= IFF_UNICAST_FLT;
12580
66371c44 12581 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 12582 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12583 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
f646968f 12584 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a848ade4 12585 if (!CHIP_IS_E1x(bp)) {
117401ee 12586 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2e3bd6a4 12587 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
a848ade4
DK		 12588 dev->hw_enc_features =
12589 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12590 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
117401ee 12591 NETIF_F_GSO_IPIP |
2e3bd6a4 12592 NETIF_F_GSO_SIT |
65bc0cfe 12593 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
a848ade4 12594 }
66371c44
MM		 12595
12596 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12597 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12598
f646968f 12599 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 12600 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 12601
538dd2e3
MB		 12602 /* Add Loopback capability to the device */
12603 dev->hw_features |= NETIF_F_LOOPBACK;
12604
98507672 12605#ifdef BCM_DCBNL
785b9b1a
SR		 12606 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12607#endif
12608
01cd4528
EG		 12609 /* get_port_hwinfo() will set prtad and mmds properly */
12610 bp->mdio.prtad = MDIO_PRTAD_NONE;
12611 bp->mdio.mmds = 0;
12612 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12613 bp->mdio.dev = dev;
12614 bp->mdio.mdio_read = bnx2x_mdio_read;
12615 bp->mdio.mdio_write = bnx2x_mdio_write;
12616
a2fbb9ea
ET		 12617 return 0;
12618
a2fbb9ea 12619err_out_release:
34f80b04
EG		 12620 if (atomic_read(&pdev->enable_cnt) == 1)
12621 pci_release_regions(pdev);
a2fbb9ea
ET		 12622
12623err_out_disable:
12624 pci_disable_device(pdev);
a2fbb9ea
ET		 12625
12626err_out:
12627 return rc;
12628}
12629
6891dd25 12630static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 12631{
37f9ce62 12632 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 12633 struct bnx2x_fw_file_hdr *fw_hdr;
12634 struct bnx2x_fw_file_section *sections;
94a78b79 12635 u32 offset, len, num_ops;
86564c3f 12636 __be16 *ops_offsets;
94a78b79 12637 int i;
37f9ce62 12638 const u8 *fw_ver;
94a78b79 12639
51c1a580
MS		 12640 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12641 BNX2X_ERR("Wrong FW size\n");
94a78b79 12642 return -EINVAL;
51c1a580 12643 }
94a78b79
VZ		 12644
12645 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12646 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12647
12648 /* Make sure none of the offsets and sizes make us read beyond
12649 * the end of the firmware data */
12650 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12651 offset = be32_to_cpu(sections[i].offset);
12652 len = be32_to_cpu(sections[i].len);
12653 if (offset + len > firmware->size) {
51c1a580 12654 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 12655 return -EINVAL;
12656 }
12657 }
12658
12659 /* Likewise for the init_ops offsets */
12660 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 12661 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 12662 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12663
12664 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12665 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 12666 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 12667 return -EINVAL;
12668 }
12669 }
12670
12671 /* Check FW version */
12672 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12673 fw_ver = firmware->data + offset;
12674 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12675 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12676 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12677 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 12678 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12679 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12680 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 12681 BCM_5710_FW_MINOR_VERSION,
12682 BCM_5710_FW_REVISION_VERSION,
12683 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 12684 return -EINVAL;
94a78b79
VZ		 12685 }
12686
12687 return 0;
12688}
12689
1191cb83 12690static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12691{
ab6ad5a4
EG		 12692 const __be32 *source = (const __be32 *)_source;
12693 u32 *target = (u32 *)_target;
94a78b79 12694 u32 i;
94a78b79
VZ		 12695
12696 for (i = 0; i < n/4; i++)
12697 target[i] = be32_to_cpu(source[i]);
12698}
12699
12700/*
12701 Ops array is stored in the following format:
12702 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12703 */
1191cb83 12704static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 12705{
ab6ad5a4
EG		 12706 const __be32 *source = (const __be32 *)_source;
12707 struct raw_op *target = (struct raw_op *)_target;
94a78b79 12708 u32 i, j, tmp;
94a78b79 12709
ab6ad5a4 12710 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 12711 tmp = be32_to_cpu(source[j]);
12712 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 12713 target[i].offset = tmp & 0xffffff;
12714 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 12715 }
12716}
ab6ad5a4 12717
1aa8b471 12718/* IRO array is stored in the following format:
523224a3
DK		 12719 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12720 */
1191cb83 12721static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 12722{
12723 const __be32 *source = (const __be32 *)_source;
12724 struct iro *target = (struct iro *)_target;
12725 u32 i, j, tmp;
12726
12727 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12728 target[i].base = be32_to_cpu(source[j]);
12729 j++;
12730 tmp = be32_to_cpu(source[j]);
12731 target[i].m1 = (tmp >> 16) & 0xffff;
12732 target[i].m2 = tmp & 0xffff;
12733 j++;
12734 tmp = be32_to_cpu(source[j]);
12735 target[i].m3 = (tmp >> 16) & 0xffff;
12736 target[i].size = tmp & 0xffff;
12737 j++;
12738 }
12739}
12740
1191cb83 12741static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12742{
ab6ad5a4
EG		 12743 const __be16 *source = (const __be16 *)_source;
12744 u16 *target = (u16 *)_target;
94a78b79 12745 u32 i;
94a78b79
VZ		 12746
12747 for (i = 0; i < n/2; i++)
12748 target[i] = be16_to_cpu(source[i]);
12749}
12750
7995c64e
JP		 12751#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12752do { \
12753 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12754 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 12755 if (!bp->arr) \
7995c64e 12756 goto lbl; \
7995c64e
JP		 12757 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12758 (u8 *)bp->arr, len); \
12759} while (0)
94a78b79 12760
3b603066 12761static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 12762{
c0ea452e 12763 const char *fw_file_name;
94a78b79 12764 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 12765 int rc;
94a78b79 12766
c0ea452e
MS		 12767 if (bp->firmware)
12768 return 0;
94a78b79 12769
c0ea452e
MS		 12770 if (CHIP_IS_E1(bp))
12771 fw_file_name = FW_FILE_NAME_E1;
12772 else if (CHIP_IS_E1H(bp))
12773 fw_file_name = FW_FILE_NAME_E1H;
12774 else if (!CHIP_IS_E1x(bp))
12775 fw_file_name = FW_FILE_NAME_E2;
12776 else {
12777 BNX2X_ERR("Unsupported chip revision\n");
12778 return -EINVAL;
12779 }
12780 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 12781
c0ea452e
MS		 12782 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12783 if (rc) {
12784 BNX2X_ERR("Can't load firmware file %s\n",
12785 fw_file_name);
12786 goto request_firmware_exit;
12787 }
eb2afd4a 12788
c0ea452e
MS		 12789 rc = bnx2x_check_firmware(bp);
12790 if (rc) {
12791 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12792 goto request_firmware_exit;
94a78b79
VZ		 12793 }
12794
12795 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12796
12797 /* Initialize the pointers to the init arrays */
12798 /* Blob */
12799 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12800
12801 /* Opcodes */
12802 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12803
12804 /* Offsets */
ab6ad5a4
EG		 12805 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12806 be16_to_cpu_n);
94a78b79
VZ		 12807
12808 /* STORMs firmware */
573f2035
EG		 12809 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12810 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12811 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12812 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12813 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12814 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12815 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12816 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12817 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12818 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12819 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12820 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12821 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12822 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12823 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12824 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 12825 /* IRO */
12826 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 12827
12828 return 0;
ab6ad5a4 12829
523224a3
DK		 12830iro_alloc_err:
12831 kfree(bp->init_ops_offsets);
94a78b79
VZ		 12832init_offsets_alloc_err:
12833 kfree(bp->init_ops);
12834init_ops_alloc_err:
12835 kfree(bp->init_data);
12836request_firmware_exit:
12837 release_firmware(bp->firmware);
127d0a19 12838 bp->firmware = NULL;
94a78b79
VZ		 12839
12840 return rc;
12841}
12842
619c5cb6
VZ		 12843static void bnx2x_release_firmware(struct bnx2x *bp)
12844{
12845 kfree(bp->init_ops_offsets);
12846 kfree(bp->init_ops);
12847 kfree(bp->init_data);
12848 release_firmware(bp->firmware);
eb2afd4a 12849 bp->firmware = NULL;
619c5cb6
VZ		 12850}
12851
619c5cb6
VZ		 12852static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12853 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12854 .init_hw_cmn = bnx2x_init_hw_common,
12855 .init_hw_port = bnx2x_init_hw_port,
12856 .init_hw_func = bnx2x_init_hw_func,
12857
12858 .reset_hw_cmn = bnx2x_reset_common,
12859 .reset_hw_port = bnx2x_reset_port,
12860 .reset_hw_func = bnx2x_reset_func,
12861
12862 .gunzip_init = bnx2x_gunzip_init,
12863 .gunzip_end = bnx2x_gunzip_end,
12864
12865 .init_fw = bnx2x_init_firmware,
12866 .release_fw = bnx2x_release_firmware,
12867};
12868
12869void bnx2x__init_func_obj(struct bnx2x *bp)
12870{
12871 /* Prepare DMAE related driver resources */
12872 bnx2x_setup_dmae(bp);
12873
12874 bnx2x_init_func_obj(bp, &bp->func_obj,
12875 bnx2x_sp(bp, func_rdata),
12876 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 12877 bnx2x_sp(bp, func_afex_rdata),
12878 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 12879 &bnx2x_func_sp_drv);
12880}
12881
12882/* must be called after sriov-enable */
1191cb83 12883static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 12884{
37ae41a9 12885 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 12886
290ca2bb
AE		 12887 if (IS_SRIOV(bp))
12888 cid_count += BNX2X_VF_CIDS;
12889
55c11941
MS		 12890 if (CNIC_SUPPORT(bp))
12891 cid_count += CNIC_CID_MAX;
290ca2bb 12892
523224a3
DK		 12893 return roundup(cid_count, QM_CID_ROUND);
12894}
f85582f8 12895
619c5cb6 12896/**
6383c0b3 12897 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 12898 *
12899 * @dev: pci device
12900 *
12901 */
60cad4e6 12902static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 12903{
ae2104be 12904 int index;
1ab4434c 12905 u16 control = 0;
619c5cb6 12906
6383c0b3
AE		 12907 /*
12908 * If MSI-X is not supported - return number of SBs needed to support
12909 * one fast path queue: one FP queue + SB for CNIC
12910 */
ae2104be 12911 if (!pdev->msix_cap) {
1ab4434c 12912 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 12913 return 1 + cnic_cnt;
1ab4434c
AE		 12914 }
12915 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 12916
6383c0b3
AE		 12917 /*
12918 * The value in the PCI configuration space is the index of the last
12919 * entry, namely one less than the actual size of the table, which is
12920 * exactly what we want to return from this function: number of all SBs
12921 * without the default SB.
1ab4434c 12922 * For VFs there is no default SB, then we return (index+1).
6383c0b3 12923 */
ae2104be 12924 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
619c5cb6 12925
1ab4434c 12926 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 12927
60cad4e6 12928 return index;
1ab4434c 12929}
523224a3 12930
1ab4434c
AE		 12931static int set_max_cos_est(int chip_id)
12932{
12933 switch (chip_id) {
f2e0899f
DK		 12934 case BCM57710:
12935 case BCM57711:
12936 case BCM57711E:
1ab4434c 12937 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 12938 case BCM57712:
619c5cb6 12939 case BCM57712_MF:
1ab4434c 12940 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 12941 case BCM57800:
12942 case BCM57800_MF:
12943 case BCM57810:
12944 case BCM57810_MF:
c3def943
YM		 12945 case BCM57840_4_10:
12946 case BCM57840_2_20:
1ab4434c 12947 case BCM57840_O:
c3def943 12948 case BCM57840_MFO:
619c5cb6 12949 case BCM57840_MF:
7e8e02df
BW		 12950 case BCM57811:
12951 case BCM57811_MF:
1ab4434c 12952 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 12953 case BCM57712_VF:
12954 case BCM57800_VF:
12955 case BCM57810_VF:
12956 case BCM57840_VF:
12957 case BCM57811_VF:
1ab4434c 12958 return 1;
f2e0899f 12959 default:
1ab4434c 12960 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 12961 return -ENODEV;
f2e0899f 12962 }
1ab4434c 12963}
f2e0899f 12964
1ab4434c
AE		 12965static int set_is_vf(int chip_id)
12966{
12967 switch (chip_id) {
12968 case BCM57712_VF:
12969 case BCM57800_VF:
12970 case BCM57810_VF:
12971 case BCM57840_VF:
12972 case BCM57811_VF:
12973 return true;
12974 default:
12975 return false;
12976 }
12977}
6383c0b3 12978
1ab4434c
AE		 12979static int bnx2x_init_one(struct pci_dev *pdev,
12980 const struct pci_device_id *ent)
12981{
12982 struct net_device *dev = NULL;
12983 struct bnx2x *bp;
b91e1a1a
YM		 12984 enum pcie_link_width pcie_width;
12985 enum pci_bus_speed pcie_speed;
1ab4434c
AE		 12986 int rc, max_non_def_sbs;
12987 int rx_count, tx_count, rss_count, doorbell_size;
12988 int max_cos_est;
12989 bool is_vf;
12990 int cnic_cnt;
12991
12992 /* An estimated maximum supported CoS number according to the chip
12993 * version.
12994 * We will try to roughly estimate the maximum number of CoSes this chip
12995 * may support in order to minimize the memory allocated for Tx
12996 * netdev_queue's. This number will be accurately calculated during the
12997 * initialization of bp->max_cos based on the chip versions AND chip
12998 * revision in the bnx2x_init_bp().
12999 */
13000 max_cos_est = set_max_cos_est(ent->driver_data);
13001 if (max_cos_est < 0)
13002 return max_cos_est;
13003 is_vf = set_is_vf(ent->driver_data);
13004 cnic_cnt = is_vf ? 0 : 1;
13005
60cad4e6
AE		 13006 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13007
13008 /* add another SB for VF as it has no default SB */
13009 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 13010
13011 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 13012 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 13013
13014 if (rss_count < 1)
13015 return -EINVAL;
6383c0b3
AE		 13016
13017 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 13018 rx_count = rss_count + cnic_cnt;
6383c0b3 13019
1ab4434c 13020 /* Maximum number of netdev Tx queues:
37ae41a9 13021 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 13022 */
55c11941 13023 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 13024
a2fbb9ea 13025 /* dev zeroed in init_etherdev */
6383c0b3 13026 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 13027 if (!dev)
a2fbb9ea
ET		 13028 return -ENOMEM;
13029
a2fbb9ea 13030 bp = netdev_priv(dev);
a2fbb9ea 13031
1ab4434c
AE		 13032 bp->flags = 0;
13033 if (is_vf)
13034 bp->flags |= IS_VF_FLAG;
13035
6383c0b3 13036 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 13037 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 13038 bp->msg_enable = debug;
55c11941 13039 bp->cnic_support = cnic_cnt;
4bd9b0ff 13040 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 13041
6383c0b3 13042 pci_set_drvdata(pdev, dev);
523224a3 13043
1ab4434c 13044 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 13045 if (rc < 0) {
13046 free_netdev(dev);
13047 return rc;
13048 }
13049
1ab4434c
AE		 13050 BNX2X_DEV_INFO("This is a %s function\n",
13051 IS_PF(bp) ? "physical" : "virtual");
55c11941 13052 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 13053 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 13054 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 13055 tx_count, rx_count);
60aa0509 13056
34f80b04 13057 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 13058 if (rc)
13059 goto init_one_exit;
13060
1ab4434c
AE		 13061 /* Map doorbells here as we need the real value of bp->max_cos which
13062 * is initialized in bnx2x_init_bp() to determine the number of
13063 * l2 connections.
6383c0b3 13064 */
1ab4434c 13065 if (IS_VF(bp)) {
1d6f3cd8 13066 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 13067 rc = bnx2x_vf_pci_alloc(bp);
13068 if (rc)
13069 goto init_one_exit;
1ab4434c
AE		 13070 } else {
13071 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13072 if (doorbell_size > pci_resource_len(pdev, 2)) {
13073 dev_err(&bp->pdev->dev,
13074 "Cannot map doorbells, bar size too small, aborting\n");
13075 rc = -ENOMEM;
13076 goto init_one_exit;
13077 }
13078 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13079 doorbell_size);
37ae41a9 13080 }
6383c0b3
AE		 13081 if (!bp->doorbells) {
13082 dev_err(&bp->pdev->dev,
13083 "Cannot map doorbell space, aborting\n");
13084 rc = -ENOMEM;
13085 goto init_one_exit;
13086 }
13087
be1f1ffa
AE		 13088 if (IS_VF(bp)) {
13089 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13090 if (rc)
13091 goto init_one_exit;
13092 }
13093
3c76feff
AE		 13094 /* Enable SRIOV if capability found in configuration space */
13095 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb
AE		 13096 if (rc)
13097 goto init_one_exit;
13098
523224a3 13099 /* calc qm_cid_count */
6383c0b3 13100 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 13101 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 13102
55c11941 13103 /* disable FCOE L2 queue for E1x*/
62ac0dc9 13104 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 13105 bp->flags |= NO_FCOE_FLAG;
13106
0e8d2ec5
MS		 13107 /* Set bp->num_queues for MSI-X mode*/
13108 bnx2x_set_num_queues(bp);
13109
25985edc 13110 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 13111 * needed.
d6214d7a 13112 */
1ab4434c
AE		 13113 rc = bnx2x_set_int_mode(bp);
13114 if (rc) {
13115 dev_err(&pdev->dev, "Cannot set interrupts\n");
13116 goto init_one_exit;
13117 }
04c46736 13118 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 13119
1ab4434c 13120 /* register the net device */
b340007f
VZ		 13121 rc = register_netdev(dev);
13122 if (rc) {
13123 dev_err(&pdev->dev, "Cannot register net device\n");
13124 goto init_one_exit;
13125 }
1ab4434c 13126 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 13127
ec6ba945
VZ		 13128 if (!NO_FCOE(bp)) {
13129 /* Add storage MAC address */
13130 rtnl_lock();
13131 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13132 rtnl_unlock();
13133 }
b91e1a1a
YM		 13134 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13135 pcie_speed == PCI_SPEED_UNKNOWN ||
13136 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13137 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13138 else
13139 BNX2X_DEV_INFO(
13140 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
ca1ee4b2
DK		 13141 board_info[ent->driver_data].name,
13142 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13143 pcie_width,
b91e1a1a
YM		 13144 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13145 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13146 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
ca1ee4b2
DK		 13147 "Unknown",
13148 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 13149
a2fbb9ea 13150 return 0;
34f80b04
EG		 13151
13152init_one_exit:
33d8e6a5
YM		 13153 bnx2x_disable_pcie_error_reporting(bp);
13154
34f80b04
EG		 13155 if (bp->regview)
13156 iounmap(bp->regview);
13157
1ab4434c 13158 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 13159 iounmap(bp->doorbells);
13160
13161 free_netdev(dev);
13162
13163 if (atomic_read(&pdev->enable_cnt) == 1)
13164 pci_release_regions(pdev);
13165
13166 pci_disable_device(pdev);
34f80b04
EG		 13167
13168 return rc;
a2fbb9ea
ET		 13169}
13170
b030ed2f
YM		 13171static void __bnx2x_remove(struct pci_dev *pdev,
13172 struct net_device *dev,
13173 struct bnx2x *bp,
13174 bool remove_netdev)
a2fbb9ea 13175{
ec6ba945
VZ		 13176 /* Delete storage MAC address */
13177 if (!NO_FCOE(bp)) {
13178 rtnl_lock();
13179 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13180 rtnl_unlock();
13181 }
ec6ba945 13182
98507672
SR		 13183#ifdef BCM_DCBNL
13184 /* Delete app tlvs from dcbnl */
13185 bnx2x_dcbnl_update_applist(bp, true);
13186#endif
13187
a6d3a5ba
BW		 13188 if (IS_PF(bp) &&
13189 !BP_NOMCP(bp) &&
13190 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13191 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13192
b030ed2f
YM		 13193 /* Close the interface - either directly or implicitly */
13194 if (remove_netdev) {
13195 unregister_netdev(dev);
13196 } else {
13197 rtnl_lock();
6ef5a92c 13198 dev_close(dev);
b030ed2f
YM		 13199 rtnl_unlock();
13200 }
a2fbb9ea 13201
78c3bcc5
AE		 13202 bnx2x_iov_remove_one(bp);
13203
084d6cbb 13204 /* Power on: we can't let PCI layer write to us while we are in D3 */
1ab4434c
AE		 13205 if (IS_PF(bp))
13206 bnx2x_set_power_state(bp, PCI_D0);
084d6cbb 13207
d6214d7a
DK		 13208 /* Disable MSI/MSI-X */
13209 bnx2x_disable_msi(bp);
f85582f8 13210
084d6cbb 13211 /* Power off */
1ab4434c
AE		 13212 if (IS_PF(bp))
13213 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 13214
72fd0718 13215 /* Make sure RESET task is not scheduled before continuing */
7be08a72 13216 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 13217
4513f925
AE		 13218 /* send message via vfpf channel to release the resources of this vf */
13219 if (IS_VF(bp))
13220 bnx2x_vfpf_release(bp);
72fd0718 13221
b030ed2f
YM		 13222 /* Assumes no further PCIe PM changes will occur */
13223 if (system_state == SYSTEM_POWER_OFF) {
13224 pci_wake_from_d3(pdev, bp->wol);
13225 pci_set_power_state(pdev, PCI_D3hot);
13226 }
13227
33d8e6a5 13228 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 13229 if (remove_netdev) {
13230 if (bp->regview)
13231 iounmap(bp->regview);
33d8e6a5 13232
d9aee591
YM		 13233 /* For vfs, doorbells are part of the regview and were unmapped
13234 * along with it. FW is only loaded by PF.
13235 */
13236 if (IS_PF(bp)) {
13237 if (bp->doorbells)
13238 iounmap(bp->doorbells);
eb2afd4a 13239
d9aee591
YM		 13240 bnx2x_release_firmware(bp);
13241 }
13242 bnx2x_free_mem_bp(bp);
523224a3 13243
b030ed2f 13244 free_netdev(dev);
34f80b04 13245
d9aee591
YM		 13246 if (atomic_read(&pdev->enable_cnt) == 1)
13247 pci_release_regions(pdev);
34f80b04 13248
5f6db130
YM		 13249 pci_disable_device(pdev);
13250 }
a2fbb9ea
ET		 13251}
13252
b030ed2f
YM		 13253static void bnx2x_remove_one(struct pci_dev *pdev)
13254{
13255 struct net_device *dev = pci_get_drvdata(pdev);
13256 struct bnx2x *bp;
13257
13258 if (!dev) {
13259 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13260 return;
13261 }
13262 bp = netdev_priv(dev);
13263
13264 __bnx2x_remove(pdev, dev, bp, true);
13265}
13266
f8ef6e44
YG		 13267static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13268{
7fa6f340 13269 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 13270
13271 bp->rx_mode = BNX2X_RX_MODE_NONE;
13272
55c11941
MS		 13273 if (CNIC_LOADED(bp))
13274 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13275
619c5cb6
VZ		 13276 /* Stop Tx */
13277 bnx2x_tx_disable(bp);
26614ba5
MS		 13278 /* Delete all NAPI objects */
13279 bnx2x_del_all_napi(bp);
55c11941
MS		 13280 if (CNIC_LOADED(bp))
13281 bnx2x_del_all_napi_cnic(bp);
7fa6f340 13282 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 13283
13284 del_timer_sync(&bp->timer);
7fa6f340
YM		 13285 cancel_delayed_work(&bp->sp_task);
13286 cancel_delayed_work(&bp->period_task);
619c5cb6 13287
7fa6f340
YM		 13288 spin_lock_bh(&bp->stats_lock);
13289 bp->stats_state = STATS_STATE_DISABLED;
13290 spin_unlock_bh(&bp->stats_lock);
f8ef6e44 13291
7fa6f340 13292 bnx2x_save_statistics(bp);
f8ef6e44 13293
619c5cb6
VZ		 13294 netif_carrier_off(bp->dev);
13295
f8ef6e44
YG		 13296 return 0;
13297}
13298
493adb1f
WX		 13299/**
13300 * bnx2x_io_error_detected - called when PCI error is detected
13301 * @pdev: Pointer to PCI device
13302 * @state: The current pci connection state
13303 *
13304 * This function is called after a PCI bus error affecting
13305 * this device has been detected.
13306 */
13307static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13308 pci_channel_state_t state)
13309{
13310 struct net_device *dev = pci_get_drvdata(pdev);
13311 struct bnx2x *bp = netdev_priv(dev);
13312
13313 rtnl_lock();
13314
7fa6f340
YM		 13315 BNX2X_ERR("IO error detected\n");
13316
493adb1f
WX		 13317 netif_device_detach(dev);
13318
07ce50e4
DN		 13319 if (state == pci_channel_io_perm_failure) {
13320 rtnl_unlock();
13321 return PCI_ERS_RESULT_DISCONNECT;
13322 }
13323
493adb1f 13324 if (netif_running(dev))
f8ef6e44 13325 bnx2x_eeh_nic_unload(bp);
493adb1f 13326
7fa6f340
YM		 13327 bnx2x_prev_path_mark_eeh(bp);
13328
493adb1f
WX		 13329 pci_disable_device(pdev);
13330
13331 rtnl_unlock();
13332
13333 /* Request a slot reset */
13334 return PCI_ERS_RESULT_NEED_RESET;
13335}
13336
13337/**
13338 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13339 * @pdev: Pointer to PCI device
13340 *
13341 * Restart the card from scratch, as if from a cold-boot.
13342 */
13343static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13344{
13345 struct net_device *dev = pci_get_drvdata(pdev);
13346 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 13347 int i;
493adb1f
WX		 13348
13349 rtnl_lock();
7fa6f340 13350 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 13351 if (pci_enable_device(pdev)) {
13352 dev_err(&pdev->dev,
13353 "Cannot re-enable PCI device after reset\n");
13354 rtnl_unlock();
13355 return PCI_ERS_RESULT_DISCONNECT;
13356 }
13357
13358 pci_set_master(pdev);
13359 pci_restore_state(pdev);
70632d0a 13360 pci_save_state(pdev);
493adb1f
WX		 13361
13362 if (netif_running(dev))
13363 bnx2x_set_power_state(bp, PCI_D0);
13364
7fa6f340
YM		 13365 if (netif_running(dev)) {
13366 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 13367
13368 /* MCP should have been reset; Need to wait for validity */
13369 bnx2x_init_shmem(bp);
13370
7fa6f340
YM		 13371 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13372 u32 v;
13373
13374 v = SHMEM2_RD(bp,
13375 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13376 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13377 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13378 }
13379 bnx2x_drain_tx_queues(bp);
13380 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13381 bnx2x_netif_stop(bp, 1);
13382 bnx2x_free_irq(bp);
13383
13384 /* Report UNLOAD_DONE to MCP */
13385 bnx2x_send_unload_done(bp, true);
13386
13387 bp->sp_state = 0;
13388 bp->port.pmf = 0;
13389
13390 bnx2x_prev_unload(bp);
13391
16a5fd92 13392 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 13393 * assume the FW will no longer write to the bnx2x driver.
13394 */
13395 bnx2x_squeeze_objects(bp);
13396 bnx2x_free_skbs(bp);
13397 for_each_rx_queue(bp, i)
13398 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13399 bnx2x_free_fp_mem(bp);
13400 bnx2x_free_mem(bp);
13401
13402 bp->state = BNX2X_STATE_CLOSED;
13403 }
13404
493adb1f
WX		 13405 rtnl_unlock();
13406
33d8e6a5
YM		 13407 /* If AER, perform cleanup of the PCIe registers */
13408 if (bp->flags & AER_ENABLED) {
13409 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13410 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13411 else
13412 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13413 }
13414
493adb1f
WX		 13415 return PCI_ERS_RESULT_RECOVERED;
13416}
13417
13418/**
13419 * bnx2x_io_resume - called when traffic can start flowing again
13420 * @pdev: Pointer to PCI device
13421 *
13422 * This callback is called when the error recovery driver tells us that
13423 * its OK to resume normal operation.
13424 */
13425static void bnx2x_io_resume(struct pci_dev *pdev)
13426{
13427 struct net_device *dev = pci_get_drvdata(pdev);
13428 struct bnx2x *bp = netdev_priv(dev);
13429
72fd0718 13430 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 13431 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 13432 return;
13433 }
13434
493adb1f
WX		 13435 rtnl_lock();
13436
7fa6f340
YM		 13437 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13438 DRV_MSG_SEQ_NUMBER_MASK;
13439
493adb1f 13440 if (netif_running(dev))
f8ef6e44 13441 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 13442
13443 netif_device_attach(dev);
13444
13445 rtnl_unlock();
13446}
13447
3646f0e5 13448static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 13449 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 13450 .slot_reset = bnx2x_io_slot_reset,
13451 .resume = bnx2x_io_resume,
493adb1f
WX		 13452};
13453
b030ed2f
YM		 13454static void bnx2x_shutdown(struct pci_dev *pdev)
13455{
13456 struct net_device *dev = pci_get_drvdata(pdev);
13457 struct bnx2x *bp;
13458
13459 if (!dev)
13460 return;
13461
13462 bp = netdev_priv(dev);
13463 if (!bp)
13464 return;
13465
13466 rtnl_lock();
13467 netif_device_detach(dev);
13468 rtnl_unlock();
13469
13470 /* Don't remove the netdevice, as there are scenarios which will cause
13471 * the kernel to hang, e.g., when trying to remove bnx2i while the
13472 * rootfs is mounted from SAN.
13473 */
13474 __bnx2x_remove(pdev, dev, bp, false);
13475}
13476
a2fbb9ea 13477static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 13478 .name = DRV_MODULE_NAME,
13479 .id_table = bnx2x_pci_tbl,
13480 .probe = bnx2x_init_one,
0329aba1 13481 .remove = bnx2x_remove_one,
493adb1f
WX		 13482 .suspend = bnx2x_suspend,
13483 .resume = bnx2x_resume,
13484 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 13485#ifdef CONFIG_BNX2X_SRIOV
13486 .sriov_configure = bnx2x_sriov_configure,
13487#endif
b030ed2f 13488 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 13489};
13490
13491static int __init bnx2x_init(void)
13492{
dd21ca6d
SG		 13493 int ret;
13494
7995c64e 13495 pr_info("%s", version);
938cf541 13496
1cf167f2
EG		 13497 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13498 if (bnx2x_wq == NULL) {
7995c64e 13499 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 13500 return -ENOMEM;
13501 }
13502
dd21ca6d
SG		 13503 ret = pci_register_driver(&bnx2x_pci_driver);
13504 if (ret) {
7995c64e 13505 pr_err("Cannot register driver\n");
dd21ca6d
SG		 13506 destroy_workqueue(bnx2x_wq);
13507 }
13508 return ret;
a2fbb9ea
ET		 13509}
13510
13511static void __exit bnx2x_cleanup(void)
13512{
452427b0 13513 struct list_head *pos, *q;
d76a6111 13514
a2fbb9ea 13515 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 13516
13517 destroy_workqueue(bnx2x_wq);
452427b0 13518
16a5fd92 13519 /* Free globally allocated resources */
452427b0
YM		 13520 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13521 struct bnx2x_prev_path_list *tmp =
13522 list_entry(pos, struct bnx2x_prev_path_list, list);
13523 list_del(pos);
13524 kfree(tmp);
13525 }
a2fbb9ea
ET		 13526}
13527
3deb8167
YR		 13528void bnx2x_notify_link_changed(struct bnx2x *bp)
13529{
13530 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13531}
13532
a2fbb9ea
ET		 13533module_init(bnx2x_init);
13534module_exit(bnx2x_cleanup);
13535
619c5cb6
VZ		 13536/**
13537 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13538 *
13539 * @bp: driver handle
13540 * @set: set or clear the CAM entry
13541 *
16a5fd92 13542 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 13543 * Return 0 if success, -ENODEV if ramrod doesn't return.
13544 */
1191cb83 13545static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 13546{
13547 unsigned long ramrod_flags = 0;
13548
13549 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13550 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13551 &bp->iscsi_l2_mac_obj, true,
13552 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13553}
993ac7b5
MC		 13554
13555/* count denotes the number of new completions we have seen */
13556static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13557{
13558 struct eth_spe *spe;
a052997e 13559 int cxt_index, cxt_offset;
993ac7b5
MC		 13560
13561#ifdef BNX2X_STOP_ON_ERROR
13562 if (unlikely(bp->panic))
13563 return;
13564#endif
13565
13566 spin_lock_bh(&bp->spq_lock);
c2bff63f 13567 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 13568 bp->cnic_spq_pending -= count;
13569
c2bff63f
DK		 13570 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13571 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13572 & SPE_HDR_CONN_TYPE) >>
13573 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 13574 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13575 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 13576
13577 /* Set validation for iSCSI L2 client before sending SETUP
13578 * ramrod
13579 */
13580 if (type == ETH_CONNECTION_TYPE) {
a052997e 13581 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 13582 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 13583 ILT_PAGE_CIDS;
37ae41a9 13584 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 13585 (cxt_index * ILT_PAGE_CIDS);
13586 bnx2x_set_ctx_validation(bp,
13587 &bp->context[cxt_index].
13588 vcxt[cxt_offset].eth,
37ae41a9 13589 BNX2X_ISCSI_ETH_CID(bp));
a052997e 13590 }
c2bff63f
DK		 13591 }
13592
619c5cb6
VZ		 13593 /*
13594 * There may be not more than 8 L2, not more than 8 L5 SPEs
13595 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 13596 * COMMON ramrods is not more than the EQ and SPQ can
13597 * accommodate.
c2bff63f 13598 */
6e30dd4e
VZ		 13599 if (type == ETH_CONNECTION_TYPE) {
13600 if (!atomic_read(&bp->cq_spq_left))
13601 break;
13602 else
13603 atomic_dec(&bp->cq_spq_left);
13604 } else if (type == NONE_CONNECTION_TYPE) {
13605 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 13606 break;
13607 else
6e30dd4e 13608 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 13609 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13610 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 13611 if (bp->cnic_spq_pending >=
13612 bp->cnic_eth_dev.max_kwqe_pending)
13613 break;
13614 else
13615 bp->cnic_spq_pending++;
13616 } else {
13617 BNX2X_ERR("Unknown SPE type: %d\n", type);
13618 bnx2x_panic();
993ac7b5 13619 break;
c2bff63f 13620 }
993ac7b5
MC		 13621
13622 spe = bnx2x_sp_get_next(bp);
13623 *spe = *bp->cnic_kwq_cons;
13624
51c1a580 13625 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 13626 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13627
13628 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13629 bp->cnic_kwq_cons = bp->cnic_kwq;
13630 else
13631 bp->cnic_kwq_cons++;
13632 }
13633 bnx2x_sp_prod_update(bp);
13634 spin_unlock_bh(&bp->spq_lock);
13635}
13636
13637static int bnx2x_cnic_sp_queue(struct net_device *dev,
13638 struct kwqe_16 *kwqes[], u32 count)
13639{
13640 struct bnx2x *bp = netdev_priv(dev);
13641 int i;
13642
13643#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 13644 if (unlikely(bp->panic)) {
13645 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 13646 return -EIO;
51c1a580 13647 }
993ac7b5
MC		 13648#endif
13649
95c6c616
AE		 13650 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13651 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 13652 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 13653 return -EAGAIN;
13654 }
13655
993ac7b5
MC		 13656 spin_lock_bh(&bp->spq_lock);
13657
13658 for (i = 0; i < count; i++) {
13659 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13660
13661 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13662 break;
13663
13664 *bp->cnic_kwq_prod = *spe;
13665
13666 bp->cnic_kwq_pending++;
13667
51c1a580 13668 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 13669 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 13670 spe->data.update_data_addr.hi,
13671 spe->data.update_data_addr.lo,
993ac7b5
MC		 13672 bp->cnic_kwq_pending);
13673
13674 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13675 bp->cnic_kwq_prod = bp->cnic_kwq;
13676 else
13677 bp->cnic_kwq_prod++;
13678 }
13679
13680 spin_unlock_bh(&bp->spq_lock);
13681
13682 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13683 bnx2x_cnic_sp_post(bp, 0);
13684
13685 return i;
13686}
13687
13688static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13689{
13690 struct cnic_ops *c_ops;
13691 int rc = 0;
13692
13693 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 13694 c_ops = rcu_dereference_protected(bp->cnic_ops,
13695 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 13696 if (c_ops)
13697 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13698 mutex_unlock(&bp->cnic_mutex);
13699
13700 return rc;
13701}
13702
13703static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13704{
13705 struct cnic_ops *c_ops;
13706 int rc = 0;
13707
13708 rcu_read_lock();
13709 c_ops = rcu_dereference(bp->cnic_ops);
13710 if (c_ops)
13711 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13712 rcu_read_unlock();
13713
13714 return rc;
13715}
13716
13717/*
13718 * for commands that have no data
13719 */
9f6c9258 13720int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 13721{
13722 struct cnic_ctl_info ctl = {0};
13723
13724 ctl.cmd = cmd;
13725
13726 return bnx2x_cnic_ctl_send(bp, &ctl);
13727}
13728
619c5cb6 13729static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 13730{
619c5cb6 13731 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 13732
13733 /* first we tell CNIC and only then we count this as a completion */
13734 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13735 ctl.data.comp.cid = cid;
619c5cb6 13736 ctl.data.comp.error = err;
993ac7b5
MC		 13737
13738 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 13739 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 13740}
13741
619c5cb6
VZ		 13742/* Called with netif_addr_lock_bh() taken.
13743 * Sets an rx_mode config for an iSCSI ETH client.
13744 * Doesn't block.
13745 * Completion should be checked outside.
13746 */
13747static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13748{
13749 unsigned long accept_flags = 0, ramrod_flags = 0;
13750 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13751 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13752
13753 if (start) {
13754 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13755 * because it's the only way for UIO Queue to accept
13756 * multicasts (in non-promiscuous mode only one Queue per
13757 * function will receive multicast packets (leading in our
13758 * case).
13759 */
13760 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13761 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13762 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13763 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13764
13765 /* Clear STOP_PENDING bit if START is requested */
13766 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13767
13768 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13769 } else
13770 /* Clear START_PENDING bit if STOP is requested */
13771 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13772
13773 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13774 set_bit(sched_state, &bp->sp_state);
13775 else {
13776 __set_bit(RAMROD_RX, &ramrod_flags);
13777 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13778 ramrod_flags);
13779 }
13780}
13781
993ac7b5
MC		 13782static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13783{
13784 struct bnx2x *bp = netdev_priv(dev);
13785 int rc = 0;
13786
13787 switch (ctl->cmd) {
13788 case DRV_CTL_CTXTBL_WR_CMD: {
13789 u32 index = ctl->data.io.offset;
13790 dma_addr_t addr = ctl->data.io.dma_addr;
13791
13792 bnx2x_ilt_wr(bp, index, addr);
13793 break;
13794 }
13795
c2bff63f
DK		 13796 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13797 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 13798
13799 bnx2x_cnic_sp_post(bp, count);
13800 break;
13801 }
13802
13803 /* rtnl_lock is held. */
13804 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 13805 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13806 unsigned long sp_bits = 0;
13807
13808 /* Configure the iSCSI classification object */
13809 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13810 cp->iscsi_l2_client_id,
13811 cp->iscsi_l2_cid, BP_FUNC(bp),
13812 bnx2x_sp(bp, mac_rdata),
13813 bnx2x_sp_mapping(bp, mac_rdata),
13814 BNX2X_FILTER_MAC_PENDING,
13815 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13816 &bp->macs_pool);
ec6ba945 13817
523224a3 13818 /* Set iSCSI MAC address */
619c5cb6
VZ		 13819 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13820 if (rc)
13821 break;
523224a3
DK		 13822
13823 mmiowb();
13824 barrier();
13825
619c5cb6
VZ		 13826 /* Start accepting on iSCSI L2 ring */
13827
13828 netif_addr_lock_bh(dev);
13829 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13830 netif_addr_unlock_bh(dev);
13831
13832 /* bits to wait on */
13833 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13834 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13835
13836 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13837 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 13838
993ac7b5
MC		 13839 break;
13840 }
13841
13842 /* rtnl_lock is held. */
13843 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 13844 unsigned long sp_bits = 0;
993ac7b5 13845
523224a3 13846 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 13847 netif_addr_lock_bh(dev);
13848 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13849 netif_addr_unlock_bh(dev);
13850
13851 /* bits to wait on */
13852 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13853 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13854
13855 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13856 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 13857
13858 mmiowb();
13859 barrier();
13860
13861 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 13862 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13863 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 13864 break;
13865 }
c2bff63f
DK		 13866 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13867 int count = ctl->data.credit.credit_count;
13868
13869 smp_mb__before_atomic_inc();
6e30dd4e 13870 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 13871 smp_mb__after_atomic_inc();
13872 break;
13873 }
1d187b34 13874 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 13875 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 13876
13877 if (CHIP_IS_E3(bp)) {
13878 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 13879 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13880 int path = BP_PATH(bp);
13881 int port = BP_PORT(bp);
13882 int i;
13883 u32 scratch_offset;
13884 u32 *host_addr;
1d187b34 13885
2e499d3c 13886 /* first write capability to shmem2 */
1d187b34
BW		 13887 if (ulp_type == CNIC_ULP_ISCSI)
13888 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13889 else if (ulp_type == CNIC_ULP_FCOE)
13890 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13891 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 13892
13893 if ((ulp_type != CNIC_ULP_FCOE) ||
13894 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13895 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13896 break;
13897
13898 /* if reached here - should write fcoe capabilities */
13899 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13900 if (!scratch_offset)
13901 break;
13902 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13903 fcoe_features[path][port]);
13904 host_addr = (u32 *) &(ctl->data.register_data.
13905 fcoe_features);
13906 for (i = 0; i < sizeof(struct fcoe_capabilities);
13907 i += 4)
13908 REG_WR(bp, scratch_offset + i,
13909 *(host_addr + i/4));
1d187b34 13910 }
42f8277f 13911 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 13912 break;
13913 }
2e499d3c 13914
1d187b34
BW		 13915 case DRV_CTL_ULP_UNREGISTER_CMD: {
13916 int ulp_type = ctl->data.ulp_type;
13917
13918 if (CHIP_IS_E3(bp)) {
13919 int idx = BP_FW_MB_IDX(bp);
13920 u32 cap;
13921
13922 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13923 if (ulp_type == CNIC_ULP_ISCSI)
13924 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13925 else if (ulp_type == CNIC_ULP_FCOE)
13926 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13927 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13928 }
42f8277f 13929 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 13930 break;
13931 }
993ac7b5
MC		 13932
13933 default:
13934 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13935 rc = -EINVAL;
13936 }
13937
13938 return rc;
13939}
13940
9f6c9258 13941void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 13942{
13943 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13944
13945 if (bp->flags & USING_MSIX_FLAG) {
13946 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13947 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13948 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13949 } else {
13950 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13951 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13952 }
619c5cb6 13953 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 13954 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13955 else
13956 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13957
619c5cb6
VZ		 13958 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13959 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 13960 cp->irq_arr[1].status_blk = bp->def_status_blk;
13961 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 13962 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 13963
13964 cp->num_irq = 2;
13965}
13966
37ae41a9
MS		 13967void bnx2x_setup_cnic_info(struct bnx2x *bp)
13968{
13969 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13970
37ae41a9
MS		 13971 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13972 bnx2x_cid_ilt_lines(bp);
13973 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13974 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13975 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13976
f78afb35
MC		 13977 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
13978 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
13979 cp->iscsi_l2_cid);
13980
37ae41a9
MS		 13981 if (NO_ISCSI_OOO(bp))
13982 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13983}
13984
993ac7b5
MC		 13985static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13986 void *data)
13987{
13988 struct bnx2x *bp = netdev_priv(dev);
13989 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 13990 int rc;
13991
13992 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 13993
51c1a580
MS		 13994 if (ops == NULL) {
13995 BNX2X_ERR("NULL ops received\n");
993ac7b5 13996 return -EINVAL;
51c1a580 13997 }
993ac7b5 13998
55c11941
MS		 13999 if (!CNIC_SUPPORT(bp)) {
14000 BNX2X_ERR("Can't register CNIC when not supported\n");
14001 return -EOPNOTSUPP;
14002 }
14003
14004 if (!CNIC_LOADED(bp)) {
14005 rc = bnx2x_load_cnic(bp);
14006 if (rc) {
14007 BNX2X_ERR("CNIC-related load failed\n");
14008 return rc;
14009 }
55c11941
MS		 14010 }
14011
14012 bp->cnic_enabled = true;
14013
993ac7b5
MC		 14014 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14015 if (!bp->cnic_kwq)
14016 return -ENOMEM;
14017
14018 bp->cnic_kwq_cons = bp->cnic_kwq;
14019 bp->cnic_kwq_prod = bp->cnic_kwq;
14020 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14021
14022 bp->cnic_spq_pending = 0;
14023 bp->cnic_kwq_pending = 0;
14024
14025 bp->cnic_data = data;
14026
14027 cp->num_irq = 0;
619c5cb6 14028 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 14029 cp->iro_arr = bp->iro_arr;
993ac7b5 14030
993ac7b5 14031 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 14032
993ac7b5
MC		 14033 rcu_assign_pointer(bp->cnic_ops, ops);
14034
42f8277f
YM		 14035 /* Schedule driver to read CNIC driver versions */
14036 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14037
993ac7b5
MC		 14038 return 0;
14039}
14040
14041static int bnx2x_unregister_cnic(struct net_device *dev)
14042{
14043 struct bnx2x *bp = netdev_priv(dev);
14044 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14045
14046 mutex_lock(&bp->cnic_mutex);
993ac7b5 14047 cp->drv_state = 0;
2cfa5a04 14048 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 14049 mutex_unlock(&bp->cnic_mutex);
14050 synchronize_rcu();
fea75645 14051 bp->cnic_enabled = false;
993ac7b5
MC		 14052 kfree(bp->cnic_kwq);
14053 bp->cnic_kwq = NULL;
14054
14055 return 0;
14056}
14057
a8f47eb7 14058static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 14059{
14060 struct bnx2x *bp = netdev_priv(dev);
14061 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14062
2ba45142
VZ		 14063 /* If both iSCSI and FCoE are disabled - return NULL in
14064 * order to indicate CNIC that it should not try to work
14065 * with this device.
14066 */
14067 if (NO_ISCSI(bp) && NO_FCOE(bp))
14068 return NULL;
14069
993ac7b5
MC		 14070 cp->drv_owner = THIS_MODULE;
14071 cp->chip_id = CHIP_ID(bp);
14072 cp->pdev = bp->pdev;
14073 cp->io_base = bp->regview;
14074 cp->io_base2 = bp->doorbells;
14075 cp->max_kwqe_pending = 8;
523224a3 14076 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 14077 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14078 bnx2x_cid_ilt_lines(bp);
993ac7b5 14079 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 14080 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 14081 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14082 cp->drv_ctl = bnx2x_drv_ctl;
14083 cp->drv_register_cnic = bnx2x_register_cnic;
14084 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 14085 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 14086 cp->iscsi_l2_client_id =
14087 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 14088 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 14089
2ba45142
VZ		 14090 if (NO_ISCSI_OOO(bp))
14091 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14092
14093 if (NO_ISCSI(bp))
14094 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14095
14096 if (NO_FCOE(bp))
14097 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14098
51c1a580
MS		 14099 BNX2X_DEV_INFO(
14100 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 14101 cp->ctx_blk_size,
14102 cp->ctx_tbl_offset,
14103 cp->ctx_tbl_len,
14104 cp->starting_cid);
993ac7b5
MC		 14105 return cp;
14106}
993ac7b5 14107
a8f47eb7 14108static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 14109{
6411280a
AE		 14110 struct bnx2x *bp = fp->bp;
14111 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 14112
6411280a
AE		 14113 if (IS_VF(bp))
14114 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14115 else if (!CHIP_IS_E1x(bp))
14116 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14117 else
14118 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 14119
6411280a 14120 return offset;
8d9ac297 14121}
381ac16b 14122
6411280a
AE		 14123/* called only on E1H or E2.
14124 * When pretending to be PF, the pretend value is the function number 0...7
14125 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14126 * combination
14127 */
14128int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 14129{
6411280a 14130 u32 pretend_reg;
381ac16b 14131
23826850 14132 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 14133 return -1;
381ac16b 14134
6411280a
AE		 14135 /* get my own pretend register */
14136 pretend_reg = bnx2x_get_pretend_reg(bp);
14137 REG_WR(bp, pretend_reg, pretend_func_val);
14138 REG_RD(bp, pretend_reg);
381ac16b
AE		 14139 return 0;
14140}
Linux 6.x block layer and io_uring tree(s)