Commit | Line | Data |
---|---|---|
34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
f1deab50 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
a2fbb9ea ET |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> /* for dev_info() */ | |
24 | #include <linux/timer.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
a2fbb9ea ET |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/bitops.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/byteorder.h> | |
39 | #include <linux/time.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
0c6671b0 | 42 | #include <linux/if_vlan.h> |
a2fbb9ea | 43 | #include <net/ip.h> |
619c5cb6 | 44 | #include <net/ipv6.h> |
a2fbb9ea ET |
45 | #include <net/tcp.h> |
46 | #include <net/checksum.h> | |
34f80b04 | 47 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
48 | #include <linux/workqueue.h> |
49 | #include <linux/crc32.h> | |
34f80b04 | 50 | #include <linux/crc32c.h> |
a2fbb9ea ET |
51 | #include <linux/prefetch.h> |
52 | #include <linux/zlib.h> | |
a2fbb9ea | 53 | #include <linux/io.h> |
452427b0 | 54 | #include <linux/semaphore.h> |
45229b42 | 55 | #include <linux/stringify.h> |
7ab24bfd | 56 | #include <linux/vmalloc.h> |
a2fbb9ea | 57 | |
a2fbb9ea ET |
58 | #include "bnx2x.h" |
59 | #include "bnx2x_init.h" | |
94a78b79 | 60 | #include "bnx2x_init_ops.h" |
9f6c9258 | 61 | #include "bnx2x_cmn.h" |
1ab4434c AE |
62 | #include "bnx2x_vfpf.h" |
63 | #include "bnx2x_sriov.h" | |
e4901dde | 64 | #include "bnx2x_dcb.h" |
042181f5 | 65 | #include "bnx2x_sp.h" |
a2fbb9ea | 66 | |
94a78b79 VZ |
67 | #include <linux/firmware.h> |
68 | #include "bnx2x_fw_file_hdr.h" | |
69 | /* FW files */ | |
45229b42 BH |
70 | #define FW_FILE_VERSION \ |
71 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
72 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
73 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
74 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
75 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
76 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 77 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 78 | |
2e499d3c BW |
79 | #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) |
80 | ||
34f80b04 EG |
81 | /* Time in jiffies before concluding the transmitter is hung */ |
82 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 83 | |
0329aba1 | 84 | static char version[] = |
619c5cb6 | 85 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
86 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
87 | ||
24e3fcef | 88 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 89 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
90 | "BCM57710/57711/57711E/" |
91 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
92 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
93 | MODULE_LICENSE("GPL"); |
94 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
95 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
96 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 97 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 98 | |
ca00392c | 99 | |
d6214d7a | 100 | int num_queues; |
54b9ddaa | 101 | module_param(num_queues, int, 0); |
96305234 DK |
102 | MODULE_PARM_DESC(num_queues, |
103 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 104 | |
19680c48 | 105 | static int disable_tpa; |
19680c48 | 106 | module_param(disable_tpa, int, 0); |
9898f86d | 107 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 108 | |
9ee3d37b DK |
109 | #define INT_MODE_INTx 1 |
110 | #define INT_MODE_MSI 2 | |
0e8d2ec5 | 111 | int int_mode; |
8badd27a | 112 | module_param(int_mode, int, 0); |
619c5cb6 | 113 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 114 | "(1 INT#x; 2 MSI)"); |
8badd27a | 115 | |
a18f5128 EG |
116 | static int dropless_fc; |
117 | module_param(dropless_fc, int, 0); | |
118 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
119 | ||
8d5726c4 EG |
120 | static int mrrs = -1; |
121 | module_param(mrrs, int, 0); | |
122 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
123 | ||
9898f86d | 124 | static int debug; |
a2fbb9ea | 125 | module_param(debug, int, 0); |
9898f86d EG |
126 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
127 | ||
a2fbb9ea | 128 | |
619c5cb6 VZ |
129 | |
130 | struct workqueue_struct *bnx2x_wq; | |
ec6ba945 | 131 | |
a2fbb9ea ET |
132 | enum bnx2x_board_type { |
133 | BCM57710 = 0, | |
619c5cb6 VZ |
134 | BCM57711, |
135 | BCM57711E, | |
136 | BCM57712, | |
137 | BCM57712_MF, | |
1ab4434c | 138 | BCM57712_VF, |
619c5cb6 VZ |
139 | BCM57800, |
140 | BCM57800_MF, | |
1ab4434c | 141 | BCM57800_VF, |
619c5cb6 VZ |
142 | BCM57810, |
143 | BCM57810_MF, | |
1ab4434c | 144 | BCM57810_VF, |
c3def943 YM |
145 | BCM57840_4_10, |
146 | BCM57840_2_20, | |
7e8e02df | 147 | BCM57840_MF, |
1ab4434c | 148 | BCM57840_VF, |
7e8e02df | 149 | BCM57811, |
1ab4434c AE |
150 | BCM57811_MF, |
151 | BCM57840_O, | |
152 | BCM57840_MFO, | |
153 | BCM57811_VF | |
a2fbb9ea ET |
154 | }; |
155 | ||
34f80b04 | 156 | /* indexed by board_type, above */ |
53a10565 | 157 | static struct { |
a2fbb9ea | 158 | char *name; |
0329aba1 | 159 | } board_info[] = { |
1ab4434c AE |
160 | [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
161 | [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
162 | [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
163 | [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
164 | [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
165 | [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" }, | |
166 | [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
167 | [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
168 | [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" }, | |
169 | [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
170 | [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
171 | [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" }, | |
172 | [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" }, | |
173 | [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" }, | |
174 | [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
175 | [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }, | |
176 | [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" }, | |
177 | [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" }, | |
178 | [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
179 | [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
180 | [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" } | |
a2fbb9ea ET |
181 | }; |
182 | ||
619c5cb6 VZ |
183 | #ifndef PCI_DEVICE_ID_NX2_57710 |
184 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
185 | #endif | |
186 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
187 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
188 | #endif | |
189 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
190 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
191 | #endif | |
192 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
193 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
194 | #endif | |
195 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
196 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
197 | #endif | |
198 | #ifndef PCI_DEVICE_ID_NX2_57800 | |
199 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
200 | #endif | |
201 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
202 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
203 | #endif | |
204 | #ifndef PCI_DEVICE_ID_NX2_57810 | |
205 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
206 | #endif | |
207 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
208 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
209 | #endif | |
c3def943 YM |
210 | #ifndef PCI_DEVICE_ID_NX2_57840_O |
211 | #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE | |
212 | #endif | |
213 | #ifndef PCI_DEVICE_ID_NX2_57840_4_10 | |
214 | #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 | |
215 | #endif | |
216 | #ifndef PCI_DEVICE_ID_NX2_57840_2_20 | |
217 | #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 | |
218 | #endif | |
219 | #ifndef PCI_DEVICE_ID_NX2_57840_MFO | |
220 | #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE | |
619c5cb6 VZ |
221 | #endif |
222 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
223 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
224 | #endif | |
7e8e02df BW |
225 | #ifndef PCI_DEVICE_ID_NX2_57811 |
226 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
227 | #endif | |
228 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
229 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
230 | #endif | |
a3aa1884 | 231 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
232 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
233 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
234 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 235 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 VZ |
236 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
237 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, | |
238 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
239 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, | |
240 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
c3def943 YM |
241 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, |
242 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, | |
243 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, | |
244 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, | |
619c5cb6 | 245 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
7e8e02df BW |
246 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
247 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
a2fbb9ea ET |
248 | { 0 } |
249 | }; | |
250 | ||
251 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
252 | ||
452427b0 YM |
253 | /* Global resources for unloading a previously loaded device */ |
254 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
255 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
256 | static LIST_HEAD(bnx2x_prev_list); | |
a2fbb9ea ET |
257 | /**************************************************************************** |
258 | * General service functions | |
259 | ****************************************************************************/ | |
260 | ||
1191cb83 | 261 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
619c5cb6 VZ |
262 | u32 addr, dma_addr_t mapping) |
263 | { | |
264 | REG_WR(bp, addr, U64_LO(mapping)); | |
265 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
266 | } | |
267 | ||
1191cb83 ED |
268 | static void storm_memset_spq_addr(struct bnx2x *bp, |
269 | dma_addr_t mapping, u16 abs_fid) | |
619c5cb6 VZ |
270 | { |
271 | u32 addr = XSEM_REG_FAST_MEMORY + | |
272 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
273 | ||
274 | __storm_memset_dma_mapping(bp, addr, mapping); | |
275 | } | |
276 | ||
1191cb83 ED |
277 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
278 | u16 pf_id) | |
523224a3 | 279 | { |
619c5cb6 VZ |
280 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
281 | pf_id); | |
282 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
283 | pf_id); | |
284 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
285 | pf_id); | |
286 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
287 | pf_id); | |
523224a3 DK |
288 | } |
289 | ||
1191cb83 ED |
290 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
291 | u8 enable) | |
619c5cb6 VZ |
292 | { |
293 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
294 | enable); | |
295 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
296 | enable); | |
297 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
298 | enable); | |
299 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
300 | enable); | |
301 | } | |
523224a3 | 302 | |
1191cb83 ED |
303 | static void storm_memset_eq_data(struct bnx2x *bp, |
304 | struct event_ring_data *eq_data, | |
523224a3 DK |
305 | u16 pfid) |
306 | { | |
307 | size_t size = sizeof(struct event_ring_data); | |
308 | ||
309 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
310 | ||
311 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
312 | } | |
313 | ||
1191cb83 ED |
314 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
315 | u16 pfid) | |
523224a3 DK |
316 | { |
317 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
318 | REG_WR16(bp, addr, eq_prod); | |
319 | } | |
320 | ||
a2fbb9ea ET |
321 | /* used only at init |
322 | * locking is done by mcp | |
323 | */ | |
8d96286a | 324 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
325 | { |
326 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
327 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
328 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
329 | PCICFG_VENDOR_ID_OFFSET); | |
330 | } | |
331 | ||
a2fbb9ea ET |
332 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
333 | { | |
334 | u32 val; | |
335 | ||
336 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
337 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
338 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
339 | PCICFG_VENDOR_ID_OFFSET); | |
340 | ||
341 | return val; | |
342 | } | |
a2fbb9ea | 343 | |
f2e0899f DK |
344 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
345 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
346 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
347 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
348 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
349 | ||
f2e0899f | 350 | |
a2fbb9ea | 351 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 352 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
353 | { |
354 | u32 cmd_offset; | |
355 | int i; | |
356 | ||
357 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
358 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
359 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
360 | } |
361 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
362 | } | |
363 | ||
f2e0899f | 364 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 365 | { |
f2e0899f DK |
366 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
367 | DMAE_CMD_C_ENABLE); | |
368 | } | |
ad8d3948 | 369 | |
f2e0899f DK |
370 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
371 | { | |
372 | return opcode & ~DMAE_CMD_SRC_RESET; | |
373 | } | |
ad8d3948 | 374 | |
f2e0899f DK |
375 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
376 | bool with_comp, u8 comp_type) | |
377 | { | |
378 | u32 opcode = 0; | |
379 | ||
380 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
381 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 382 | |
f2e0899f DK |
383 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
384 | ||
385 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
386 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
387 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 388 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 389 | |
a2fbb9ea | 390 | #ifdef __BIG_ENDIAN |
f2e0899f | 391 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 392 | #else |
f2e0899f | 393 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 394 | #endif |
f2e0899f DK |
395 | if (with_comp) |
396 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
397 | return opcode; | |
398 | } | |
399 | ||
8d96286a | 400 | static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
401 | struct dmae_command *dmae, | |
402 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
403 | { |
404 | memset(dmae, 0, sizeof(struct dmae_command)); | |
405 | ||
406 | /* set the opcode */ | |
407 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
408 | true, DMAE_COMP_PCI); | |
409 | ||
410 | /* fill in the completion parameters */ | |
411 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
412 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
413 | dmae->comp_val = DMAE_COMP_VAL; | |
414 | } | |
415 | ||
416 | /* issue a dmae command over the init-channel and wailt for completion */ | |
8d96286a | 417 | static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, |
418 | struct dmae_command *dmae) | |
f2e0899f DK |
419 | { |
420 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 421 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
422 | int rc = 0; |
423 | ||
619c5cb6 VZ |
424 | /* |
425 | * Lock the dmae channel. Disable BHs to prevent a dead-lock | |
426 | * as long as this code is called both from syscall context and | |
427 | * from ndo_set_rx_mode() flow that may be called from BH. | |
428 | */ | |
6e30dd4e | 429 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 430 | |
f2e0899f | 431 | /* reset completion */ |
a2fbb9ea ET |
432 | *wb_comp = 0; |
433 | ||
f2e0899f DK |
434 | /* post the command on the channel used for initializations */ |
435 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 436 | |
f2e0899f | 437 | /* wait for completion */ |
a2fbb9ea | 438 | udelay(5); |
f2e0899f | 439 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 440 | |
95c6c616 AE |
441 | if (!cnt || |
442 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
443 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 444 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
445 | rc = DMAE_TIMEOUT; |
446 | goto unlock; | |
a2fbb9ea | 447 | } |
ad8d3948 | 448 | cnt--; |
f2e0899f | 449 | udelay(50); |
a2fbb9ea | 450 | } |
f2e0899f DK |
451 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
452 | BNX2X_ERR("DMAE PCI error!\n"); | |
453 | rc = DMAE_PCI_ERROR; | |
454 | } | |
455 | ||
f2e0899f | 456 | unlock: |
6e30dd4e | 457 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
458 | return rc; |
459 | } | |
460 | ||
461 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
462 | u32 len32) | |
463 | { | |
464 | struct dmae_command dmae; | |
465 | ||
466 | if (!bp->dmae_ready) { | |
467 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
468 | ||
127a425e AE |
469 | if (CHIP_IS_E1(bp)) |
470 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
471 | else | |
472 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
473 | return; |
474 | } | |
475 | ||
476 | /* set opcode and fixed command fields */ | |
477 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
478 | ||
479 | /* fill in addresses and len */ | |
480 | dmae.src_addr_lo = U64_LO(dma_addr); | |
481 | dmae.src_addr_hi = U64_HI(dma_addr); | |
482 | dmae.dst_addr_lo = dst_addr >> 2; | |
483 | dmae.dst_addr_hi = 0; | |
484 | dmae.len = len32; | |
485 | ||
f2e0899f DK |
486 | /* issue the command and wait for completion */ |
487 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
a2fbb9ea ET |
488 | } |
489 | ||
c18487ee | 490 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 491 | { |
5ff7b6d4 | 492 | struct dmae_command dmae; |
ad8d3948 EG |
493 | |
494 | if (!bp->dmae_ready) { | |
495 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
496 | int i; | |
497 | ||
51c1a580 | 498 | if (CHIP_IS_E1(bp)) |
127a425e AE |
499 | for (i = 0; i < len32; i++) |
500 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 501 | else |
127a425e AE |
502 | for (i = 0; i < len32; i++) |
503 | data[i] = REG_RD(bp, src_addr + i*4); | |
504 | ||
ad8d3948 EG |
505 | return; |
506 | } | |
507 | ||
f2e0899f DK |
508 | /* set opcode and fixed command fields */ |
509 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 510 | |
f2e0899f | 511 | /* fill in addresses and len */ |
5ff7b6d4 EG |
512 | dmae.src_addr_lo = src_addr >> 2; |
513 | dmae.src_addr_hi = 0; | |
514 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
515 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
516 | dmae.len = len32; | |
ad8d3948 | 517 | |
f2e0899f DK |
518 | /* issue the command and wait for completion */ |
519 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
ad8d3948 EG |
520 | } |
521 | ||
8d96286a | 522 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
523 | u32 addr, u32 len) | |
573f2035 | 524 | { |
02e3c6cb | 525 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
526 | int offset = 0; |
527 | ||
02e3c6cb | 528 | while (len > dmae_wr_max) { |
573f2035 | 529 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
530 | addr + offset, dmae_wr_max); |
531 | offset += dmae_wr_max * 4; | |
532 | len -= dmae_wr_max; | |
573f2035 EG |
533 | } |
534 | ||
535 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
536 | } | |
537 | ||
a2fbb9ea ET |
538 | static int bnx2x_mc_assert(struct bnx2x *bp) |
539 | { | |
a2fbb9ea | 540 | char last_idx; |
34f80b04 EG |
541 | int i, rc = 0; |
542 | u32 row0, row1, row2, row3; | |
543 | ||
544 | /* XSTORM */ | |
545 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
546 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
547 | if (last_idx) | |
548 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
549 | ||
550 | /* print the asserts */ | |
551 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
552 | ||
553 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
554 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
555 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
556 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
557 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
558 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
559 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
560 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
561 | ||
562 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 563 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
564 | i, row3, row2, row1, row0); |
565 | rc++; | |
566 | } else { | |
567 | break; | |
568 | } | |
569 | } | |
570 | ||
571 | /* TSTORM */ | |
572 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
573 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
574 | if (last_idx) | |
575 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
576 | ||
577 | /* print the asserts */ | |
578 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
579 | ||
580 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
581 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
582 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
583 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
584 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
585 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
586 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
587 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
588 | ||
589 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 590 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
591 | i, row3, row2, row1, row0); |
592 | rc++; | |
593 | } else { | |
594 | break; | |
595 | } | |
596 | } | |
597 | ||
598 | /* CSTORM */ | |
599 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
600 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
601 | if (last_idx) | |
602 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
603 | ||
604 | /* print the asserts */ | |
605 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
606 | ||
607 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
608 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
609 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
610 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
611 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
612 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
613 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
614 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
615 | ||
616 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 617 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
618 | i, row3, row2, row1, row0); |
619 | rc++; | |
620 | } else { | |
621 | break; | |
622 | } | |
623 | } | |
624 | ||
625 | /* USTORM */ | |
626 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
627 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
628 | if (last_idx) | |
629 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
630 | ||
631 | /* print the asserts */ | |
632 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
633 | ||
634 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
635 | USTORM_ASSERT_LIST_OFFSET(i)); | |
636 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
637 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
638 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
639 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
640 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
641 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
642 | ||
643 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 644 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
645 | i, row3, row2, row1, row0); |
646 | rc++; | |
647 | } else { | |
648 | break; | |
a2fbb9ea ET |
649 | } |
650 | } | |
34f80b04 | 651 | |
a2fbb9ea ET |
652 | return rc; |
653 | } | |
c14423fe | 654 | |
7a25cc73 | 655 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 656 | { |
7a25cc73 | 657 | u32 addr, val; |
a2fbb9ea | 658 | u32 mark, offset; |
4781bfad | 659 | __be32 data[9]; |
a2fbb9ea | 660 | int word; |
f2e0899f | 661 | u32 trace_shmem_base; |
2145a920 VZ |
662 | if (BP_NOMCP(bp)) { |
663 | BNX2X_ERR("NO MCP - can not dump\n"); | |
664 | return; | |
665 | } | |
7a25cc73 DK |
666 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
667 | (bp->common.bc_ver & 0xff0000) >> 16, | |
668 | (bp->common.bc_ver & 0xff00) >> 8, | |
669 | (bp->common.bc_ver & 0xff)); | |
670 | ||
671 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
672 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 673 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 674 | |
f2e0899f DK |
675 | if (BP_PATH(bp) == 0) |
676 | trace_shmem_base = bp->common.shmem_base; | |
677 | else | |
678 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
de128804 DK |
679 | addr = trace_shmem_base - 0x800; |
680 | ||
681 | /* validate TRCB signature */ | |
682 | mark = REG_RD(bp, addr); | |
683 | if (mark != MFW_TRACE_SIGNATURE) { | |
684 | BNX2X_ERR("Trace buffer signature is missing."); | |
685 | return ; | |
686 | } | |
687 | ||
688 | /* read cyclic buffer pointer */ | |
689 | addr += 4; | |
cdaa7cb8 | 690 | mark = REG_RD(bp, addr); |
f2e0899f DK |
691 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
692 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 693 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 694 | |
7a25cc73 | 695 | printk("%s", lvl); |
f2e0899f | 696 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 697 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 698 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 699 | data[8] = 0x0; |
7995c64e | 700 | pr_cont("%s", (char *)data); |
a2fbb9ea | 701 | } |
cdaa7cb8 | 702 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 703 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 704 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 705 | data[8] = 0x0; |
7995c64e | 706 | pr_cont("%s", (char *)data); |
a2fbb9ea | 707 | } |
7a25cc73 DK |
708 | printk("%s" "end of fw dump\n", lvl); |
709 | } | |
710 | ||
1191cb83 | 711 | static void bnx2x_fw_dump(struct bnx2x *bp) |
7a25cc73 DK |
712 | { |
713 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
714 | } |
715 | ||
6c719d00 | 716 | void bnx2x_panic_dump(struct bnx2x *bp) |
a2fbb9ea ET |
717 | { |
718 | int i; | |
523224a3 DK |
719 | u16 j; |
720 | struct hc_sp_status_block_data sp_sb_data; | |
721 | int func = BP_FUNC(bp); | |
722 | #ifdef BNX2X_STOP_ON_ERROR | |
723 | u16 start = 0, end = 0; | |
6383c0b3 | 724 | u8 cos; |
523224a3 | 725 | #endif |
a2fbb9ea | 726 | |
66e855f3 | 727 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 728 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
729 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
730 | ||
a2fbb9ea ET |
731 | BNX2X_ERR("begin crash dump -----------------\n"); |
732 | ||
8440d2b6 EG |
733 | /* Indices */ |
734 | /* Common */ | |
51c1a580 | 735 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
619c5cb6 VZ |
736 | bp->def_idx, bp->def_att_idx, bp->attn_state, |
737 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
738 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
739 | bp->def_status_blk->atten_status_block.attn_bits, | |
740 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
741 | bp->def_status_blk->atten_status_block.status_block_id, | |
742 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
743 | BNX2X_ERR(" def ("); | |
744 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
745 | pr_cont("0x%x%s", | |
f1deab50 JP |
746 | bp->def_status_blk->sp_sb.index_values[i], |
747 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
523224a3 DK |
748 | |
749 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
750 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
751 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
752 | i*sizeof(u32)); | |
753 | ||
f1deab50 | 754 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", |
523224a3 DK |
755 | sp_sb_data.igu_sb_id, |
756 | sp_sb_data.igu_seg_id, | |
757 | sp_sb_data.p_func.pf_id, | |
758 | sp_sb_data.p_func.vnic_id, | |
759 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
760 | sp_sb_data.p_func.vf_valid, |
761 | sp_sb_data.state); | |
523224a3 | 762 | |
8440d2b6 | 763 | |
ec6ba945 | 764 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 765 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 766 | int loop; |
f2e0899f | 767 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
768 | struct hc_status_block_data_e1x sb_data_e1x; |
769 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
770 | CHIP_IS_E1x(bp) ? |
771 | sb_data_e1x.common.state_machine : | |
772 | sb_data_e2.common.state_machine; | |
523224a3 | 773 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
774 | CHIP_IS_E1x(bp) ? |
775 | sb_data_e1x.index_data : | |
776 | sb_data_e2.index_data; | |
6383c0b3 | 777 | u8 data_size, cos; |
523224a3 | 778 | u32 *sb_data_p; |
6383c0b3 | 779 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
780 | |
781 | /* Rx */ | |
51c1a580 | 782 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 783 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 784 | fp->rx_comp_prod, |
66e855f3 | 785 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 786 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 787 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 788 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 789 | |
523224a3 | 790 | /* Tx */ |
6383c0b3 AE |
791 | for_each_cos_in_tx_queue(fp, cos) |
792 | { | |
65565884 | 793 | txdata = *fp->txdata_ptr[cos]; |
51c1a580 | 794 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
795 | i, txdata.tx_pkt_prod, |
796 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
797 | txdata.tx_bd_cons, | |
798 | le16_to_cpu(*txdata.tx_cons_sb)); | |
799 | } | |
523224a3 | 800 | |
619c5cb6 VZ |
801 | loop = CHIP_IS_E1x(bp) ? |
802 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
803 | |
804 | /* host sb data */ | |
805 | ||
ec6ba945 VZ |
806 | if (IS_FCOE_FP(fp)) |
807 | continue; | |
55c11941 | 808 | |
523224a3 DK |
809 | BNX2X_ERR(" run indexes ("); |
810 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
811 | pr_cont("0x%x%s", | |
812 | fp->sb_running_index[j], | |
813 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
814 | ||
815 | BNX2X_ERR(" indexes ("); | |
816 | for (j = 0; j < loop; j++) | |
817 | pr_cont("0x%x%s", | |
818 | fp->sb_index_values[j], | |
819 | (j == loop - 1) ? ")" : " "); | |
820 | /* fw sb data */ | |
619c5cb6 VZ |
821 | data_size = CHIP_IS_E1x(bp) ? |
822 | sizeof(struct hc_status_block_data_e1x) : | |
823 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 824 | data_size /= sizeof(u32); |
619c5cb6 VZ |
825 | sb_data_p = CHIP_IS_E1x(bp) ? |
826 | (u32 *)&sb_data_e1x : | |
827 | (u32 *)&sb_data_e2; | |
523224a3 DK |
828 | /* copy sb data in here */ |
829 | for (j = 0; j < data_size; j++) | |
830 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
831 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
832 | j * sizeof(u32)); | |
833 | ||
619c5cb6 | 834 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 835 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
836 | sb_data_e2.common.p_func.pf_id, |
837 | sb_data_e2.common.p_func.vf_id, | |
838 | sb_data_e2.common.p_func.vf_valid, | |
839 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
840 | sb_data_e2.common.same_igu_sb_1b, |
841 | sb_data_e2.common.state); | |
f2e0899f | 842 | } else { |
51c1a580 | 843 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
844 | sb_data_e1x.common.p_func.pf_id, |
845 | sb_data_e1x.common.p_func.vf_id, | |
846 | sb_data_e1x.common.p_func.vf_valid, | |
847 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
848 | sb_data_e1x.common.same_igu_sb_1b, |
849 | sb_data_e1x.common.state); | |
f2e0899f | 850 | } |
523224a3 DK |
851 | |
852 | /* SB_SMs data */ | |
853 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
854 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
855 | j, hc_sm_p[j].__flags, | |
856 | hc_sm_p[j].igu_sb_id, | |
857 | hc_sm_p[j].igu_seg_id, | |
858 | hc_sm_p[j].time_to_expire, | |
859 | hc_sm_p[j].timer_value); | |
523224a3 DK |
860 | } |
861 | ||
862 | /* Indecies data */ | |
863 | for (j = 0; j < loop; j++) { | |
51c1a580 | 864 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
865 | hc_index_p[j].flags, |
866 | hc_index_p[j].timeout); | |
867 | } | |
8440d2b6 | 868 | } |
a2fbb9ea | 869 | |
523224a3 | 870 | #ifdef BNX2X_STOP_ON_ERROR |
8440d2b6 EG |
871 | /* Rings */ |
872 | /* Rx */ | |
55c11941 | 873 | for_each_valid_rx_queue(bp, i) { |
8440d2b6 | 874 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
875 | |
876 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
877 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 878 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
879 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
880 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
881 | ||
c3eefaf6 | 882 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 883 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
884 | } |
885 | ||
3196a88a EG |
886 | start = RX_SGE(fp->rx_sge_prod); |
887 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 888 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
889 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
890 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
891 | ||
c3eefaf6 EG |
892 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
893 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
894 | } |
895 | ||
a2fbb9ea ET |
896 | start = RCQ_BD(fp->rx_comp_cons - 10); |
897 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 898 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
899 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
900 | ||
c3eefaf6 EG |
901 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
902 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
903 | } |
904 | } | |
905 | ||
8440d2b6 | 906 | /* Tx */ |
55c11941 | 907 | for_each_valid_tx_queue(bp, i) { |
8440d2b6 | 908 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 | 909 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 910 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 AE |
911 | |
912 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
913 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
914 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
915 | struct sw_tx_bd *sw_bd = | |
916 | &txdata->tx_buf_ring[j]; | |
917 | ||
51c1a580 | 918 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
919 | i, cos, j, sw_bd->skb, |
920 | sw_bd->first_bd); | |
921 | } | |
8440d2b6 | 922 | |
6383c0b3 AE |
923 | start = TX_BD(txdata->tx_bd_cons - 10); |
924 | end = TX_BD(txdata->tx_bd_cons + 254); | |
925 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
926 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 927 | |
51c1a580 | 928 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
929 | i, cos, j, tx_bd[0], tx_bd[1], |
930 | tx_bd[2], tx_bd[3]); | |
931 | } | |
8440d2b6 EG |
932 | } |
933 | } | |
523224a3 | 934 | #endif |
34f80b04 | 935 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
936 | bnx2x_mc_assert(bp); |
937 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
938 | } |
939 | ||
619c5cb6 VZ |
940 | /* |
941 | * FLR Support for E2 | |
942 | * | |
943 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
944 | * initialization. | |
945 | */ | |
946 | #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ | |
89db4ad8 AE |
947 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
948 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
949 | |
950 | struct pbf_pN_buf_regs { | |
951 | int pN; | |
952 | u32 init_crd; | |
953 | u32 crd; | |
954 | u32 crd_freed; | |
955 | }; | |
956 | ||
957 | struct pbf_pN_cmd_regs { | |
958 | int pN; | |
959 | u32 lines_occup; | |
960 | u32 lines_freed; | |
961 | }; | |
962 | ||
963 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
964 | struct pbf_pN_buf_regs *regs, | |
965 | u32 poll_count) | |
966 | { | |
967 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
968 | u32 cur_cnt = poll_count; | |
969 | ||
970 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
971 | crd = crd_start = REG_RD(bp, regs->crd); | |
972 | init_crd = REG_RD(bp, regs->init_crd); | |
973 | ||
974 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
975 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
976 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
977 | ||
978 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
979 | (init_crd - crd_start))) { | |
980 | if (cur_cnt--) { | |
89db4ad8 | 981 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
982 | crd = REG_RD(bp, regs->crd); |
983 | crd_freed = REG_RD(bp, regs->crd_freed); | |
984 | } else { | |
985 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
986 | regs->pN); | |
987 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
988 | regs->pN, crd); | |
989 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
990 | regs->pN, crd_freed); | |
991 | break; | |
992 | } | |
993 | } | |
994 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 995 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
996 | } |
997 | ||
998 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
999 | struct pbf_pN_cmd_regs *regs, | |
1000 | u32 poll_count) | |
1001 | { | |
1002 | u32 occup, to_free, freed, freed_start; | |
1003 | u32 cur_cnt = poll_count; | |
1004 | ||
1005 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1006 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1007 | ||
1008 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1009 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1010 | ||
1011 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1012 | if (cur_cnt--) { | |
89db4ad8 | 1013 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1014 | occup = REG_RD(bp, regs->lines_occup); |
1015 | freed = REG_RD(bp, regs->lines_freed); | |
1016 | } else { | |
1017 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1018 | regs->pN); | |
1019 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1020 | regs->pN, occup); | |
1021 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1022 | regs->pN, freed); | |
1023 | break; | |
1024 | } | |
1025 | } | |
1026 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 1027 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1028 | } |
1029 | ||
1191cb83 ED |
1030 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
1031 | u32 expected, u32 poll_count) | |
619c5cb6 VZ |
1032 | { |
1033 | u32 cur_cnt = poll_count; | |
1034 | u32 val; | |
1035 | ||
1036 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1037 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1038 | |
1039 | return val; | |
1040 | } | |
1041 | ||
1191cb83 ED |
1042 | static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1043 | char *msg, u32 poll_cnt) | |
619c5cb6 VZ |
1044 | { |
1045 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1046 | if (val != 0) { | |
1047 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1048 | return 1; | |
1049 | } | |
1050 | return 0; | |
1051 | } | |
1052 | ||
1053 | static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
1054 | { | |
1055 | /* adjust polling timeout */ | |
1056 | if (CHIP_REV_IS_EMUL(bp)) | |
1057 | return FLR_POLL_CNT * 2000; | |
1058 | ||
1059 | if (CHIP_REV_IS_FPGA(bp)) | |
1060 | return FLR_POLL_CNT * 120; | |
1061 | ||
1062 | return FLR_POLL_CNT; | |
1063 | } | |
1064 | ||
1065 | static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) | |
1066 | { | |
1067 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1068 | {0, (CHIP_IS_E3B0(bp)) ? | |
1069 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1070 | PBF_REG_P0_TQ_OCCUPANCY, | |
1071 | (CHIP_IS_E3B0(bp)) ? | |
1072 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1073 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1074 | {1, (CHIP_IS_E3B0(bp)) ? | |
1075 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1076 | PBF_REG_P1_TQ_OCCUPANCY, | |
1077 | (CHIP_IS_E3B0(bp)) ? | |
1078 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1079 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1080 | {4, (CHIP_IS_E3B0(bp)) ? | |
1081 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1082 | PBF_REG_P4_TQ_OCCUPANCY, | |
1083 | (CHIP_IS_E3B0(bp)) ? | |
1084 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1085 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1086 | }; | |
1087 | ||
1088 | struct pbf_pN_buf_regs buf_regs[] = { | |
1089 | {0, (CHIP_IS_E3B0(bp)) ? | |
1090 | PBF_REG_INIT_CRD_Q0 : | |
1091 | PBF_REG_P0_INIT_CRD , | |
1092 | (CHIP_IS_E3B0(bp)) ? | |
1093 | PBF_REG_CREDIT_Q0 : | |
1094 | PBF_REG_P0_CREDIT, | |
1095 | (CHIP_IS_E3B0(bp)) ? | |
1096 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1097 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1098 | {1, (CHIP_IS_E3B0(bp)) ? | |
1099 | PBF_REG_INIT_CRD_Q1 : | |
1100 | PBF_REG_P1_INIT_CRD, | |
1101 | (CHIP_IS_E3B0(bp)) ? | |
1102 | PBF_REG_CREDIT_Q1 : | |
1103 | PBF_REG_P1_CREDIT, | |
1104 | (CHIP_IS_E3B0(bp)) ? | |
1105 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1106 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1107 | {4, (CHIP_IS_E3B0(bp)) ? | |
1108 | PBF_REG_INIT_CRD_LB_Q : | |
1109 | PBF_REG_P4_INIT_CRD, | |
1110 | (CHIP_IS_E3B0(bp)) ? | |
1111 | PBF_REG_CREDIT_LB_Q : | |
1112 | PBF_REG_P4_CREDIT, | |
1113 | (CHIP_IS_E3B0(bp)) ? | |
1114 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1115 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1116 | }; | |
1117 | ||
1118 | int i; | |
1119 | ||
1120 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1121 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1122 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1123 | ||
1124 | ||
1125 | /* Verify the transmission buffers are flushed P0, P1, P4 */ | |
1126 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1127 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1128 | } | |
1129 | ||
1130 | #define OP_GEN_PARAM(param) \ | |
1131 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1132 | ||
1133 | #define OP_GEN_TYPE(type) \ | |
1134 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1135 | ||
1136 | #define OP_GEN_AGG_VECT(index) \ | |
1137 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1138 | ||
1139 | ||
1191cb83 | 1140 | static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, |
619c5cb6 VZ |
1141 | u32 poll_cnt) |
1142 | { | |
1143 | struct sdm_op_gen op_gen = {0}; | |
1144 | ||
1145 | u32 comp_addr = BAR_CSTRORM_INTMEM + | |
1146 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1147 | int ret = 0; | |
1148 | ||
1149 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1150 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1151 | return 1; |
1152 | } | |
1153 | ||
1154 | op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); | |
1155 | op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1156 | op_gen.command |= OP_GEN_AGG_VECT(clnup_func); | |
1157 | op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
1158 | ||
89db4ad8 | 1159 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
619c5cb6 VZ |
1160 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); |
1161 | ||
1162 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1163 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1164 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1165 | (REG_RD(bp, comp_addr))); | |
619c5cb6 VZ |
1166 | ret = 1; |
1167 | } | |
1168 | /* Zero completion for nxt FLR */ | |
1169 | REG_WR(bp, comp_addr, 0); | |
1170 | ||
1171 | return ret; | |
1172 | } | |
1173 | ||
1191cb83 | 1174 | static u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
619c5cb6 | 1175 | { |
619c5cb6 VZ |
1176 | u16 status; |
1177 | ||
2a80eebc | 1178 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
619c5cb6 VZ |
1179 | return status & PCI_EXP_DEVSTA_TRPND; |
1180 | } | |
1181 | ||
1182 | /* PF FLR specific routines | |
1183 | */ | |
1184 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1185 | { | |
1186 | ||
1187 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ | |
1188 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1189 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1190 | "CFC PF usage counter timed out", | |
1191 | poll_cnt)) | |
1192 | return 1; | |
1193 | ||
1194 | ||
1195 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ | |
1196 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1197 | DORQ_REG_PF_USAGE_CNT, | |
1198 | "DQ PF usage counter timed out", | |
1199 | poll_cnt)) | |
1200 | return 1; | |
1201 | ||
1202 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1203 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1204 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1205 | "QM PF usage counter timed out", | |
1206 | poll_cnt)) | |
1207 | return 1; | |
1208 | ||
1209 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1210 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1211 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1212 | "Timers VNIC usage counter timed out", | |
1213 | poll_cnt)) | |
1214 | return 1; | |
1215 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1216 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1217 | "Timers NUM_SCANS usage counter timed out", | |
1218 | poll_cnt)) | |
1219 | return 1; | |
1220 | ||
1221 | /* Wait DMAE PF usage counter to zero */ | |
1222 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1223 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
1224 | "DMAE dommand register timed out", | |
1225 | poll_cnt)) | |
1226 | return 1; | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
1231 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1232 | { | |
1233 | u32 val; | |
1234 | ||
1235 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1236 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1237 | ||
1238 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1239 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1240 | ||
1241 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1242 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1243 | ||
1244 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1245 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1246 | ||
1247 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1248 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1249 | ||
1250 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1251 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1252 | ||
1253 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1254 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1255 | ||
1256 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1257 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1258 | val); | |
1259 | } | |
1260 | ||
1261 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1262 | { | |
1263 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1264 | ||
1265 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1266 | ||
1267 | /* Re-enable PF target read access */ | |
1268 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1269 | ||
1270 | /* Poll HW usage counters */ | |
89db4ad8 | 1271 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1272 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1273 | return -EBUSY; | |
1274 | ||
1275 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1276 | ||
1277 | /* Send the FW cleanup command */ | |
1278 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1279 | return -EBUSY; | |
1280 | ||
1281 | /* ATC cleanup */ | |
1282 | ||
1283 | /* Verify TX hw is flushed */ | |
1284 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1285 | ||
1286 | /* Wait 100ms (not adjusted according to platform) */ | |
1287 | msleep(100); | |
1288 | ||
1289 | /* Verify no pending pci transactions */ | |
1290 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1291 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1292 | ||
1293 | /* Debug */ | |
1294 | bnx2x_hw_enable_status(bp); | |
1295 | ||
1296 | /* | |
1297 | * Master enable - Due to WB DMAE writes performed before this | |
1298 | * register is re-initialized as part of the regular function init | |
1299 | */ | |
1300 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1301 | ||
1302 | return 0; | |
1303 | } | |
1304 | ||
f2e0899f | 1305 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1306 | { |
34f80b04 | 1307 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1308 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1309 | u32 val = REG_RD(bp, addr); | |
69c326b3 DK |
1310 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1311 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1312 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
a2fbb9ea ET |
1313 | |
1314 | if (msix) { | |
8badd27a EG |
1315 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1316 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1317 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1318 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
69c326b3 DK |
1319 | if (single_msix) |
1320 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; | |
8badd27a EG |
1321 | } else if (msi) { |
1322 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1323 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1324 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1325 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1326 | } else { |
1327 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1328 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1329 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1330 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1331 | |
a0fd065c | 1332 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1333 | DP(NETIF_MSG_IFUP, |
1334 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1335 | |
a0fd065c | 1336 | REG_WR(bp, addr, val); |
615f8fd9 | 1337 | |
a0fd065c DK |
1338 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1339 | } | |
a2fbb9ea ET |
1340 | } |
1341 | ||
a0fd065c DK |
1342 | if (CHIP_IS_E1(bp)) |
1343 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1344 | ||
51c1a580 MS |
1345 | DP(NETIF_MSG_IFUP, |
1346 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1347 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1348 | |
1349 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1350 | /* |
1351 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1352 | */ | |
1353 | mmiowb(); | |
1354 | barrier(); | |
34f80b04 | 1355 | |
f2e0899f | 1356 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1357 | /* init leading/trailing edge */ |
fb3bff17 | 1358 | if (IS_MF(bp)) { |
3395a033 | 1359 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1360 | if (bp->port.pmf) |
4acac6a5 EG |
1361 | /* enable nig and gpio3 attention */ |
1362 | val |= 0x1100; | |
34f80b04 EG |
1363 | } else |
1364 | val = 0xffff; | |
1365 | ||
1366 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1367 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1368 | } | |
37dbbf32 EG |
1369 | |
1370 | /* Make sure that interrupts are indeed enabled from here on */ | |
1371 | mmiowb(); | |
a2fbb9ea ET |
1372 | } |
1373 | ||
f2e0899f DK |
1374 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1375 | { | |
1376 | u32 val; | |
30a5de77 DK |
1377 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1378 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1379 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1380 | |
1381 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1382 | ||
1383 | if (msix) { | |
1384 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1385 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1386 | val |= (IGU_PF_CONF_FUNC_EN | | |
1387 | IGU_PF_CONF_MSI_MSIX_EN | | |
1388 | IGU_PF_CONF_ATTN_BIT_EN); | |
30a5de77 DK |
1389 | |
1390 | if (single_msix) | |
1391 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1392 | } else if (msi) { |
1393 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
1394 | val |= (IGU_PF_CONF_FUNC_EN | | |
1395 | IGU_PF_CONF_MSI_MSIX_EN | | |
1396 | IGU_PF_CONF_ATTN_BIT_EN | | |
1397 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1398 | } else { | |
1399 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
1400 | val |= (IGU_PF_CONF_FUNC_EN | | |
1401 | IGU_PF_CONF_INT_LINE_EN | | |
1402 | IGU_PF_CONF_ATTN_BIT_EN | | |
1403 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1404 | } | |
1405 | ||
51c1a580 | 1406 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1407 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1408 | ||
1409 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1410 | ||
79a8557a YM |
1411 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1412 | pci_intx(bp->pdev, true); | |
1413 | ||
f2e0899f DK |
1414 | barrier(); |
1415 | ||
1416 | /* init leading/trailing edge */ | |
1417 | if (IS_MF(bp)) { | |
3395a033 | 1418 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1419 | if (bp->port.pmf) |
1420 | /* enable nig and gpio3 attention */ | |
1421 | val |= 0x1100; | |
1422 | } else | |
1423 | val = 0xffff; | |
1424 | ||
1425 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1426 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1427 | ||
1428 | /* Make sure that interrupts are indeed enabled from here on */ | |
1429 | mmiowb(); | |
1430 | } | |
1431 | ||
1432 | void bnx2x_int_enable(struct bnx2x *bp) | |
1433 | { | |
1434 | if (bp->common.int_block == INT_BLOCK_HC) | |
1435 | bnx2x_hc_int_enable(bp); | |
1436 | else | |
1437 | bnx2x_igu_int_enable(bp); | |
1438 | } | |
1439 | ||
1440 | static void bnx2x_hc_int_disable(struct bnx2x *bp) | |
a2fbb9ea | 1441 | { |
34f80b04 | 1442 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1443 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1444 | u32 val = REG_RD(bp, addr); | |
1445 | ||
a0fd065c DK |
1446 | /* |
1447 | * in E1 we must use only PCI configuration space to disable | |
1448 | * MSI/MSIX capablility | |
1449 | * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
1450 | */ | |
1451 | if (CHIP_IS_E1(bp)) { | |
1452 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
1453 | * Use mask register to prevent from HC sending interrupts | |
1454 | * after we exit the function | |
1455 | */ | |
1456 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
1457 | ||
1458 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1459 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1460 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
1461 | } else | |
1462 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1463 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1464 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1465 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea | 1466 | |
51c1a580 MS |
1467 | DP(NETIF_MSG_IFDOWN, |
1468 | "write %x to HC %d (addr 0x%x)\n", | |
a2fbb9ea ET |
1469 | val, port, addr); |
1470 | ||
8badd27a EG |
1471 | /* flush all outstanding writes */ |
1472 | mmiowb(); | |
1473 | ||
a2fbb9ea ET |
1474 | REG_WR(bp, addr, val); |
1475 | if (REG_RD(bp, addr) != val) | |
1476 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1477 | } | |
1478 | ||
f2e0899f DK |
1479 | static void bnx2x_igu_int_disable(struct bnx2x *bp) |
1480 | { | |
1481 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1482 | ||
1483 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
1484 | IGU_PF_CONF_INT_LINE_EN | | |
1485 | IGU_PF_CONF_ATTN_BIT_EN); | |
1486 | ||
51c1a580 | 1487 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); |
f2e0899f DK |
1488 | |
1489 | /* flush all outstanding writes */ | |
1490 | mmiowb(); | |
1491 | ||
1492 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1493 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
1494 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1495 | } | |
1496 | ||
910cc727 | 1497 | static void bnx2x_int_disable(struct bnx2x *bp) |
f2e0899f DK |
1498 | { |
1499 | if (bp->common.int_block == INT_BLOCK_HC) | |
1500 | bnx2x_hc_int_disable(bp); | |
1501 | else | |
1502 | bnx2x_igu_int_disable(bp); | |
1503 | } | |
1504 | ||
9f6c9258 | 1505 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1506 | { |
a2fbb9ea | 1507 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1508 | int i, offset; |
a2fbb9ea | 1509 | |
f8ef6e44 YG |
1510 | if (disable_hw) |
1511 | /* prevent the HW from sending interrupts */ | |
1512 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1513 | |
1514 | /* make sure all ISRs are done */ | |
1515 | if (msix) { | |
8badd27a EG |
1516 | synchronize_irq(bp->msix_table[0].vector); |
1517 | offset = 1; | |
55c11941 MS |
1518 | if (CNIC_SUPPORT(bp)) |
1519 | offset++; | |
ec6ba945 | 1520 | for_each_eth_queue(bp, i) |
754a2f52 | 1521 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1522 | } else |
1523 | synchronize_irq(bp->pdev->irq); | |
1524 | ||
1525 | /* make sure sp_task is not running */ | |
1cf167f2 | 1526 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1527 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1528 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1529 | } |
1530 | ||
34f80b04 | 1531 | /* fast path */ |
a2fbb9ea ET |
1532 | |
1533 | /* | |
34f80b04 | 1534 | * General service functions |
a2fbb9ea ET |
1535 | */ |
1536 | ||
72fd0718 VZ |
1537 | /* Return true if succeeded to acquire the lock */ |
1538 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1539 | { | |
1540 | u32 lock_status; | |
1541 | u32 resource_bit = (1 << resource); | |
1542 | int func = BP_FUNC(bp); | |
1543 | u32 hw_lock_control_reg; | |
1544 | ||
51c1a580 MS |
1545 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1546 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1547 | |
1548 | /* Validating that the resource is within range */ | |
1549 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1550 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1551 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1552 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1553 | return false; |
72fd0718 VZ |
1554 | } |
1555 | ||
1556 | if (func <= 5) | |
1557 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1558 | else | |
1559 | hw_lock_control_reg = | |
1560 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1561 | ||
1562 | /* Try to acquire the lock */ | |
1563 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1564 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1565 | if (lock_status & resource_bit) | |
1566 | return true; | |
1567 | ||
51c1a580 MS |
1568 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1569 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1570 | return false; |
1571 | } | |
1572 | ||
c9ee9206 VZ |
1573 | /** |
1574 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1575 | * | |
1576 | * @bp: driver handle | |
1577 | * | |
1578 | * Returns the recovery leader resource id according to the engine this function | |
1579 | * belongs to. Currently only only 2 engines is supported. | |
1580 | */ | |
1191cb83 | 1581 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
c9ee9206 VZ |
1582 | { |
1583 | if (BP_PATH(bp)) | |
1584 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1585 | else | |
1586 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1587 | } | |
1588 | ||
1589 | /** | |
1590 | * bnx2x_trylock_leader_lock- try to aquire a leader lock. | |
1591 | * | |
1592 | * @bp: driver handle | |
1593 | * | |
1191cb83 | 1594 | * Tries to aquire a leader lock for current engine. |
c9ee9206 | 1595 | */ |
1191cb83 | 1596 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
c9ee9206 VZ |
1597 | { |
1598 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1599 | } | |
1600 | ||
619c5cb6 | 1601 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
55c11941 | 1602 | |
3196a88a | 1603 | |
619c5cb6 | 1604 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1605 | { |
1606 | struct bnx2x *bp = fp->bp; | |
1607 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1608 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 | 1609 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
15192a8c | 1610 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a2fbb9ea | 1611 | |
34f80b04 | 1612 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1613 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1614 | fp->index, cid, command, bp->state, |
34f80b04 | 1615 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1616 | |
619c5cb6 VZ |
1617 | switch (command) { |
1618 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1619 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1620 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1621 | break; | |
d6cae238 | 1622 | |
619c5cb6 | 1623 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1624 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1625 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1626 | break; |
1627 | ||
6383c0b3 | 1628 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1629 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1630 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1631 | break; | |
1632 | ||
619c5cb6 | 1633 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1634 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1635 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1636 | break; |
1637 | ||
619c5cb6 | 1638 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
d6cae238 | 1639 | DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); |
619c5cb6 | 1640 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1641 | break; |
1642 | ||
619c5cb6 | 1643 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1644 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1645 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1646 | break; |
619c5cb6 VZ |
1647 | |
1648 | default: | |
1649 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1650 | command, fp->index); | |
1651 | return; | |
523224a3 | 1652 | } |
3196a88a | 1653 | |
619c5cb6 VZ |
1654 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1655 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1656 | /* q_obj->complete_cmd() failure means that this was | |
1657 | * an unexpected completion. | |
1658 | * | |
1659 | * In this case we don't want to increase the bp->spq_left | |
1660 | * because apparently we haven't sent this command the first | |
1661 | * place. | |
1662 | */ | |
1663 | #ifdef BNX2X_STOP_ON_ERROR | |
1664 | bnx2x_panic(); | |
1665 | #else | |
1666 | return; | |
1667 | #endif | |
1668 | ||
8fe23fbd | 1669 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1670 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1671 | /* push the change in bp->spq_left and towards the memory */ |
1672 | smp_mb__after_atomic_inc(); | |
49d66772 | 1673 | |
d6cae238 VZ |
1674 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1675 | ||
a3348722 BW |
1676 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1677 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1678 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1679 | * flow, then ACK MCP at the end | |
1680 | * | |
1681 | * mark pending ACK to MCP bit. | |
1682 | * prevent case that both bits are cleared. | |
1683 | * At the end of load/unload driver checks that | |
1684 | * sp_state is cleaerd, and this order prevents | |
1685 | * races | |
1686 | */ | |
1687 | smp_mb__before_clear_bit(); | |
1688 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); | |
1689 | wmb(); | |
1690 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
1691 | smp_mb__after_clear_bit(); | |
1692 | ||
1693 | /* schedule workqueue to send ack to MCP */ | |
1694 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1695 | } | |
1696 | ||
523224a3 | 1697 | return; |
a2fbb9ea ET |
1698 | } |
1699 | ||
619c5cb6 VZ |
1700 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
1701 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod) | |
1702 | { | |
1703 | u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset; | |
1704 | ||
1705 | bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod, | |
1706 | start); | |
1707 | } | |
1708 | ||
9f6c9258 | 1709 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1710 | { |
555f6c78 | 1711 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1712 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1713 | u16 mask; |
ca00392c | 1714 | int i; |
6383c0b3 | 1715 | u8 cos; |
a2fbb9ea | 1716 | |
34f80b04 | 1717 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1718 | if (unlikely(status == 0)) { |
1719 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1720 | return IRQ_NONE; | |
1721 | } | |
f5372251 | 1722 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1723 | |
3196a88a EG |
1724 | #ifdef BNX2X_STOP_ON_ERROR |
1725 | if (unlikely(bp->panic)) | |
1726 | return IRQ_HANDLED; | |
1727 | #endif | |
1728 | ||
ec6ba945 | 1729 | for_each_eth_queue(bp, i) { |
ca00392c | 1730 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1731 | |
55c11941 | 1732 | mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); |
ca00392c | 1733 | if (status & mask) { |
619c5cb6 | 1734 | /* Handle Rx or Tx according to SB id */ |
54b9ddaa | 1735 | prefetch(fp->rx_cons_sb); |
6383c0b3 | 1736 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1737 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
523224a3 | 1738 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1739 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1740 | status &= ~mask; |
1741 | } | |
a2fbb9ea ET |
1742 | } |
1743 | ||
55c11941 MS |
1744 | if (CNIC_SUPPORT(bp)) { |
1745 | mask = 0x2; | |
1746 | if (status & (mask | 0x1)) { | |
1747 | struct cnic_ops *c_ops = NULL; | |
993ac7b5 | 1748 | |
55c11941 MS |
1749 | if (likely(bp->state == BNX2X_STATE_OPEN)) { |
1750 | rcu_read_lock(); | |
1751 | c_ops = rcu_dereference(bp->cnic_ops); | |
1752 | if (c_ops) | |
1753 | c_ops->cnic_handler(bp->cnic_data, | |
1754 | NULL); | |
1755 | rcu_read_unlock(); | |
1756 | } | |
993ac7b5 | 1757 | |
55c11941 MS |
1758 | status &= ~mask; |
1759 | } | |
993ac7b5 | 1760 | } |
a2fbb9ea | 1761 | |
34f80b04 | 1762 | if (unlikely(status & 0x1)) { |
1cf167f2 | 1763 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
1764 | |
1765 | status &= ~0x1; | |
1766 | if (!status) | |
1767 | return IRQ_HANDLED; | |
1768 | } | |
1769 | ||
cdaa7cb8 VZ |
1770 | if (unlikely(status)) |
1771 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1772 | status); |
a2fbb9ea | 1773 | |
c18487ee | 1774 | return IRQ_HANDLED; |
a2fbb9ea ET |
1775 | } |
1776 | ||
c18487ee YR |
1777 | /* Link */ |
1778 | ||
1779 | /* | |
1780 | * General service functions | |
1781 | */ | |
a2fbb9ea | 1782 | |
9f6c9258 | 1783 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1784 | { |
1785 | u32 lock_status; | |
1786 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1787 | int func = BP_FUNC(bp); |
1788 | u32 hw_lock_control_reg; | |
c18487ee | 1789 | int cnt; |
a2fbb9ea | 1790 | |
c18487ee YR |
1791 | /* Validating that the resource is within range */ |
1792 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1793 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1794 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1795 | return -EINVAL; | |
1796 | } | |
a2fbb9ea | 1797 | |
4a37fb66 YG |
1798 | if (func <= 5) { |
1799 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1800 | } else { | |
1801 | hw_lock_control_reg = | |
1802 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1803 | } | |
1804 | ||
c18487ee | 1805 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1806 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1807 | if (lock_status & resource_bit) { |
51c1a580 | 1808 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
1809 | lock_status, resource_bit); |
1810 | return -EEXIST; | |
1811 | } | |
a2fbb9ea | 1812 | |
46230476 EG |
1813 | /* Try for 5 second every 5ms */ |
1814 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1815 | /* Try to acquire the lock */ |
4a37fb66 YG |
1816 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1817 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1818 | if (lock_status & resource_bit) |
1819 | return 0; | |
a2fbb9ea | 1820 | |
c18487ee | 1821 | msleep(5); |
a2fbb9ea | 1822 | } |
51c1a580 | 1823 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
1824 | return -EAGAIN; |
1825 | } | |
a2fbb9ea | 1826 | |
c9ee9206 VZ |
1827 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1828 | { | |
1829 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1830 | } | |
1831 | ||
9f6c9258 | 1832 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1833 | { |
1834 | u32 lock_status; | |
1835 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1836 | int func = BP_FUNC(bp); |
1837 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1838 | |
c18487ee YR |
1839 | /* Validating that the resource is within range */ |
1840 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1841 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1842 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1843 | return -EINVAL; | |
1844 | } | |
1845 | ||
4a37fb66 YG |
1846 | if (func <= 5) { |
1847 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1848 | } else { | |
1849 | hw_lock_control_reg = | |
1850 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1851 | } | |
1852 | ||
c18487ee | 1853 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1854 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1855 | if (!(lock_status & resource_bit)) { |
51c1a580 | 1856 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", |
c18487ee YR |
1857 | lock_status, resource_bit); |
1858 | return -EFAULT; | |
a2fbb9ea ET |
1859 | } |
1860 | ||
9f6c9258 DK |
1861 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1862 | return 0; | |
c18487ee | 1863 | } |
a2fbb9ea | 1864 | |
9f6c9258 | 1865 | |
4acac6a5 EG |
1866 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
1867 | { | |
1868 | /* The GPIO should be swapped if swap register is set and active */ | |
1869 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1870 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1871 | int gpio_shift = gpio_num + | |
1872 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1873 | u32 gpio_mask = (1 << gpio_shift); | |
1874 | u32 gpio_reg; | |
1875 | int value; | |
1876 | ||
1877 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1878 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1879 | return -EINVAL; | |
1880 | } | |
1881 | ||
1882 | /* read GPIO value */ | |
1883 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1884 | ||
1885 | /* get the requested pin value */ | |
1886 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
1887 | value = 1; | |
1888 | else | |
1889 | value = 0; | |
1890 | ||
1891 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
1892 | ||
1893 | return value; | |
1894 | } | |
1895 | ||
17de50b7 | 1896 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
1897 | { |
1898 | /* The GPIO should be swapped if swap register is set and active */ | |
1899 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 1900 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
1901 | int gpio_shift = gpio_num + |
1902 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1903 | u32 gpio_mask = (1 << gpio_shift); | |
1904 | u32 gpio_reg; | |
a2fbb9ea | 1905 | |
c18487ee YR |
1906 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
1907 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1908 | return -EINVAL; | |
1909 | } | |
a2fbb9ea | 1910 | |
4a37fb66 | 1911 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
1912 | /* read GPIO and mask except the float bits */ |
1913 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 1914 | |
c18487ee YR |
1915 | switch (mode) { |
1916 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
1917 | DP(NETIF_MSG_LINK, |
1918 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
1919 | gpio_num, gpio_shift); |
1920 | /* clear FLOAT and set CLR */ | |
1921 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1922 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
1923 | break; | |
a2fbb9ea | 1924 | |
c18487ee | 1925 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
1926 | DP(NETIF_MSG_LINK, |
1927 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
1928 | gpio_num, gpio_shift); |
1929 | /* clear FLOAT and set SET */ | |
1930 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1931 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
1932 | break; | |
a2fbb9ea | 1933 | |
17de50b7 | 1934 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
1935 | DP(NETIF_MSG_LINK, |
1936 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
1937 | gpio_num, gpio_shift); |
1938 | /* set FLOAT */ | |
1939 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1940 | break; | |
a2fbb9ea | 1941 | |
c18487ee YR |
1942 | default: |
1943 | break; | |
a2fbb9ea ET |
1944 | } |
1945 | ||
c18487ee | 1946 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 1947 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 1948 | |
c18487ee | 1949 | return 0; |
a2fbb9ea ET |
1950 | } |
1951 | ||
0d40f0d4 YR |
1952 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
1953 | { | |
1954 | u32 gpio_reg = 0; | |
1955 | int rc = 0; | |
1956 | ||
1957 | /* Any port swapping should be handled by caller. */ | |
1958 | ||
1959 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1960 | /* read GPIO and mask except the float bits */ | |
1961 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1962 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1963 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1964 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
1965 | ||
1966 | switch (mode) { | |
1967 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
1968 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
1969 | /* set CLR */ | |
1970 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
1971 | break; | |
1972 | ||
1973 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
1974 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
1975 | /* set SET */ | |
1976 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
1977 | break; | |
1978 | ||
1979 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
1980 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
1981 | /* set FLOAT */ | |
1982 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
1983 | break; | |
1984 | ||
1985 | default: | |
1986 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
1987 | rc = -EINVAL; | |
1988 | break; | |
1989 | } | |
1990 | ||
1991 | if (rc == 0) | |
1992 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
1993 | ||
1994 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
1995 | ||
1996 | return rc; | |
1997 | } | |
1998 | ||
4acac6a5 EG |
1999 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2000 | { | |
2001 | /* The GPIO should be swapped if swap register is set and active */ | |
2002 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2003 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2004 | int gpio_shift = gpio_num + | |
2005 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2006 | u32 gpio_mask = (1 << gpio_shift); | |
2007 | u32 gpio_reg; | |
2008 | ||
2009 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2010 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2011 | return -EINVAL; | |
2012 | } | |
2013 | ||
2014 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2015 | /* read GPIO int */ | |
2016 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2017 | ||
2018 | switch (mode) { | |
2019 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
2020 | DP(NETIF_MSG_LINK, |
2021 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
2022 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2023 | /* clear SET and set CLR */ |
2024 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2025 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2026 | break; | |
2027 | ||
2028 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2029 | DP(NETIF_MSG_LINK, |
2030 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2031 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2032 | /* clear CLR and set SET */ |
2033 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2034 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2035 | break; | |
2036 | ||
2037 | default: | |
2038 | break; | |
2039 | } | |
2040 | ||
2041 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2042 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2043 | ||
2044 | return 0; | |
2045 | } | |
2046 | ||
d6d99a3f | 2047 | static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) |
a2fbb9ea | 2048 | { |
c18487ee | 2049 | u32 spio_reg; |
a2fbb9ea | 2050 | |
d6d99a3f YM |
2051 | /* Only 2 SPIOs are configurable */ |
2052 | if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { | |
2053 | BNX2X_ERR("Invalid SPIO 0x%x\n", spio); | |
c18487ee | 2054 | return -EINVAL; |
a2fbb9ea ET |
2055 | } |
2056 | ||
4a37fb66 | 2057 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2058 | /* read SPIO and mask except the float bits */ |
d6d99a3f | 2059 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); |
a2fbb9ea | 2060 | |
c18487ee | 2061 | switch (mode) { |
d6d99a3f YM |
2062 | case MISC_SPIO_OUTPUT_LOW: |
2063 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); | |
c18487ee | 2064 | /* clear FLOAT and set CLR */ |
d6d99a3f YM |
2065 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2066 | spio_reg |= (spio << MISC_SPIO_CLR_POS); | |
c18487ee | 2067 | break; |
a2fbb9ea | 2068 | |
d6d99a3f YM |
2069 | case MISC_SPIO_OUTPUT_HIGH: |
2070 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); | |
c18487ee | 2071 | /* clear FLOAT and set SET */ |
d6d99a3f YM |
2072 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2073 | spio_reg |= (spio << MISC_SPIO_SET_POS); | |
c18487ee | 2074 | break; |
a2fbb9ea | 2075 | |
d6d99a3f YM |
2076 | case MISC_SPIO_INPUT_HI_Z: |
2077 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); | |
c18487ee | 2078 | /* set FLOAT */ |
d6d99a3f | 2079 | spio_reg |= (spio << MISC_SPIO_FLOAT_POS); |
c18487ee | 2080 | break; |
a2fbb9ea | 2081 | |
c18487ee YR |
2082 | default: |
2083 | break; | |
a2fbb9ea ET |
2084 | } |
2085 | ||
c18487ee | 2086 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2087 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2088 | |
a2fbb9ea ET |
2089 | return 0; |
2090 | } | |
2091 | ||
9f6c9258 | 2092 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2093 | { |
a22f0788 | 2094 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2095 | switch (bp->link_vars.ieee_fc & |
2096 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2097 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2098 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2099 | ADVERTISED_Pause); |
c18487ee | 2100 | break; |
356e2385 | 2101 | |
c18487ee | 2102 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2103 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2104 | ADVERTISED_Pause); |
c18487ee | 2105 | break; |
356e2385 | 2106 | |
c18487ee | 2107 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2108 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2109 | break; |
356e2385 | 2110 | |
c18487ee | 2111 | default: |
a22f0788 | 2112 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2113 | ADVERTISED_Pause); |
c18487ee YR |
2114 | break; |
2115 | } | |
2116 | } | |
f1410647 | 2117 | |
cd1dfce2 | 2118 | static void bnx2x_set_requested_fc(struct bnx2x *bp) |
c18487ee | 2119 | { |
cd1dfce2 YM |
2120 | /* Initialize link parameters structure variables |
2121 | * It is recommended to turn off RX FC for jumbo frames | |
2122 | * for better performance | |
2123 | */ | |
2124 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
2125 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; | |
2126 | else | |
2127 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; | |
2128 | } | |
a2fbb9ea | 2129 | |
cd1dfce2 YM |
2130 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
2131 | { | |
2132 | int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); | |
2133 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
2134 | ||
2135 | if (!BP_NOMCP(bp)) { | |
2136 | bnx2x_set_requested_fc(bp); | |
4a37fb66 | 2137 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2138 | |
a22f0788 | 2139 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2140 | struct link_params *lp = &bp->link_params; |
2141 | lp->loopback_mode = LOOPBACK_XGXS; | |
2142 | /* do PHY loopback at 10G speed, if possible */ | |
2143 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2144 | if (lp->speed_cap_mask[cfx_idx] & | |
2145 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2146 | lp->req_line_speed[cfx_idx] = | |
2147 | SPEED_10000; | |
2148 | else | |
2149 | lp->req_line_speed[cfx_idx] = | |
2150 | SPEED_1000; | |
2151 | } | |
a22f0788 | 2152 | } |
b5bf9068 | 2153 | |
8970b2e4 MS |
2154 | if (load_mode == LOAD_LOOPBACK_EXT) { |
2155 | struct link_params *lp = &bp->link_params; | |
2156 | lp->loopback_mode = LOOPBACK_EXT; | |
2157 | } | |
2158 | ||
19680c48 | 2159 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2160 | |
4a37fb66 | 2161 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2162 | |
3c96c68b EG |
2163 | bnx2x_calc_fc_adv(bp); |
2164 | ||
cd1dfce2 | 2165 | if (bp->link_vars.link_up) { |
b5bf9068 | 2166 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
19680c48 | 2167 | bnx2x_link_report(bp); |
cd1dfce2 YM |
2168 | } |
2169 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2170 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2171 | return rc; |
2172 | } | |
f5372251 | 2173 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2174 | return -EINVAL; |
a2fbb9ea ET |
2175 | } |
2176 | ||
9f6c9258 | 2177 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2178 | { |
19680c48 | 2179 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2180 | bnx2x_acquire_phy_lock(bp); |
19680c48 | 2181 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2182 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2183 | |
19680c48 EG |
2184 | bnx2x_calc_fc_adv(bp); |
2185 | } else | |
f5372251 | 2186 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2187 | } |
a2fbb9ea | 2188 | |
c18487ee YR |
2189 | static void bnx2x__link_reset(struct bnx2x *bp) |
2190 | { | |
19680c48 | 2191 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2192 | bnx2x_acquire_phy_lock(bp); |
5d07d868 | 2193 | bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2194 | bnx2x_release_phy_lock(bp); |
19680c48 | 2195 | } else |
f5372251 | 2196 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2197 | } |
a2fbb9ea | 2198 | |
5d07d868 YM |
2199 | void bnx2x_force_link_reset(struct bnx2x *bp) |
2200 | { | |
2201 | bnx2x_acquire_phy_lock(bp); | |
2202 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); | |
2203 | bnx2x_release_phy_lock(bp); | |
2204 | } | |
2205 | ||
a22f0788 | 2206 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2207 | { |
2145a920 | 2208 | u8 rc = 0; |
a2fbb9ea | 2209 | |
2145a920 VZ |
2210 | if (!BP_NOMCP(bp)) { |
2211 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2212 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2213 | is_serdes); | |
2145a920 VZ |
2214 | bnx2x_release_phy_lock(bp); |
2215 | } else | |
2216 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2217 | |
c18487ee YR |
2218 | return rc; |
2219 | } | |
a2fbb9ea | 2220 | |
34f80b04 | 2221 | |
2691d51d EG |
2222 | /* Calculates the sum of vn_min_rates. |
2223 | It's needed for further normalizing of the min_rates. | |
2224 | Returns: | |
2225 | sum of vn_min_rates. | |
2226 | or | |
2227 | 0 - if all the min_rates are 0. | |
2228 | In the later case fainess algorithm should be deactivated. | |
2229 | If not all min_rates are zero then those that are zeroes will be set to 1. | |
2230 | */ | |
b475d78f YM |
2231 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2232 | struct cmng_init_input *input) | |
2691d51d EG |
2233 | { |
2234 | int all_zero = 1; | |
2691d51d EG |
2235 | int vn; |
2236 | ||
3395a033 | 2237 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2238 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2239 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2240 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2241 | ||
2242 | /* Skip hidden vns */ | |
2243 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2244 | vn_min_rate = 0; |
2691d51d | 2245 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2246 | else if (!vn_min_rate) |
2691d51d EG |
2247 | vn_min_rate = DEF_MIN_RATE; |
2248 | else | |
2249 | all_zero = 0; | |
2250 | ||
b475d78f | 2251 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2252 | } |
2253 | ||
30ae438b DK |
2254 | /* if ETS or all min rates are zeros - disable fairness */ |
2255 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2256 | input->flags.cmng_enables &= |
30ae438b DK |
2257 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2258 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2259 | } else if (all_zero) { | |
b475d78f | 2260 | input->flags.cmng_enables &= |
b015e3d1 | 2261 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2262 | DP(NETIF_MSG_IFUP, |
2263 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2264 | } else |
b475d78f | 2265 | input->flags.cmng_enables |= |
b015e3d1 | 2266 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2267 | } |
2268 | ||
b475d78f YM |
2269 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2270 | struct cmng_init_input *input) | |
34f80b04 | 2271 | { |
b475d78f | 2272 | u16 vn_max_rate; |
f2e0899f | 2273 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2274 | |
b475d78f | 2275 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2276 | vn_max_rate = 0; |
b475d78f | 2277 | else { |
faa6fcbb DK |
2278 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2279 | ||
b475d78f | 2280 | if (IS_MF_SI(bp)) { |
faa6fcbb DK |
2281 | /* maxCfg in percents of linkspeed */ |
2282 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2283 | } else /* SD modes */ |
faa6fcbb DK |
2284 | /* maxCfg is absolute in 100Mb units */ |
2285 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2286 | } |
f85582f8 | 2287 | |
b475d78f | 2288 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2289 | |
b475d78f | 2290 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2291 | } |
f85582f8 | 2292 | |
b475d78f | 2293 | |
523224a3 DK |
2294 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2295 | { | |
2296 | if (CHIP_REV_IS_SLOW(bp)) | |
2297 | return CMNG_FNS_NONE; | |
fb3bff17 | 2298 | if (IS_MF(bp)) |
523224a3 DK |
2299 | return CMNG_FNS_MINMAX; |
2300 | ||
2301 | return CMNG_FNS_NONE; | |
2302 | } | |
2303 | ||
2ae17f66 | 2304 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2305 | { |
0793f83f | 2306 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2307 | |
2308 | if (BP_NOMCP(bp)) | |
2309 | return; /* what should be the default bvalue in this case */ | |
2310 | ||
0793f83f DK |
2311 | /* For 2 port configuration the absolute function number formula |
2312 | * is: | |
2313 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2314 | * | |
2315 | * and there are 4 functions per port | |
2316 | * | |
2317 | * For 4 port configuration it is | |
2318 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2319 | * | |
2320 | * and there are 2 functions per port | |
2321 | */ | |
3395a033 | 2322 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2323 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2324 | ||
2325 | if (func >= E1H_FUNC_MAX) | |
2326 | break; | |
2327 | ||
f2e0899f | 2328 | bp->mf_config[vn] = |
523224a3 DK |
2329 | MF_CFG_RD(bp, func_mf_config[func].config); |
2330 | } | |
a3348722 BW |
2331 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2332 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2333 | bp->flags |= MF_FUNC_DIS; | |
2334 | } else { | |
2335 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2336 | bp->flags &= ~MF_FUNC_DIS; | |
2337 | } | |
523224a3 DK |
2338 | } |
2339 | ||
2340 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2341 | { | |
b475d78f YM |
2342 | struct cmng_init_input input; |
2343 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2344 | ||
2345 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 DK |
2346 | |
2347 | if (cmng_type == CMNG_FNS_MINMAX) { | |
2348 | int vn; | |
2349 | ||
523224a3 DK |
2350 | /* read mf conf from shmem */ |
2351 | if (read_cfg) | |
2352 | bnx2x_read_mf_cfg(bp); | |
2353 | ||
523224a3 | 2354 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2355 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2356 | |
2357 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2358 | if (bp->port.pmf) |
3395a033 | 2359 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2360 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2361 | |
2362 | /* always enable rate shaping and fairness */ | |
b475d78f | 2363 | input.flags.cmng_enables |= |
523224a3 | 2364 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2365 | |
2366 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2367 | return; |
2368 | } | |
2369 | ||
2370 | /* rate shaping and fairness are disabled */ | |
2371 | DP(NETIF_MSG_IFUP, | |
2372 | "rate shaping and fairness are disabled\n"); | |
2373 | } | |
34f80b04 | 2374 | |
1191cb83 ED |
2375 | static void storm_memset_cmng(struct bnx2x *bp, |
2376 | struct cmng_init *cmng, | |
2377 | u8 port) | |
2378 | { | |
2379 | int vn; | |
2380 | size_t size = sizeof(struct cmng_struct_per_port); | |
2381 | ||
2382 | u32 addr = BAR_XSTRORM_INTMEM + | |
2383 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
2384 | ||
2385 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); | |
2386 | ||
2387 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
2388 | int func = func_by_vn(bp, vn); | |
2389 | ||
2390 | addr = BAR_XSTRORM_INTMEM + | |
2391 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); | |
2392 | size = sizeof(struct rate_shaping_vars_per_vn); | |
2393 | __storm_memset_struct(bp, addr, size, | |
2394 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); | |
2395 | ||
2396 | addr = BAR_XSTRORM_INTMEM + | |
2397 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); | |
2398 | size = sizeof(struct fairness_vars_per_vn); | |
2399 | __storm_memset_struct(bp, addr, size, | |
2400 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); | |
2401 | } | |
2402 | } | |
2403 | ||
c18487ee YR |
2404 | /* This function is called upon link interrupt */ |
2405 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2406 | { | |
bb2a0f7a YG |
2407 | /* Make sure that we are synced with the current statistics */ |
2408 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2409 | ||
c18487ee | 2410 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2411 | |
bb2a0f7a YG |
2412 | if (bp->link_vars.link_up) { |
2413 | ||
1c06328c | 2414 | /* dropless flow control */ |
f2e0899f | 2415 | if (!CHIP_IS_E1(bp) && bp->dropless_fc) { |
1c06328c EG |
2416 | int port = BP_PORT(bp); |
2417 | u32 pause_enabled = 0; | |
2418 | ||
2419 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2420 | pause_enabled = 1; | |
2421 | ||
2422 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
ca00392c | 2423 | USTORM_ETH_PAUSE_ENABLED_OFFSET(port), |
1c06328c EG |
2424 | pause_enabled); |
2425 | } | |
2426 | ||
619c5cb6 | 2427 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2428 | struct host_port_stats *pstats; |
2429 | ||
2430 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2431 | /* reset old mac stats */ |
bb2a0f7a YG |
2432 | memset(&(pstats->mac_stx[0]), 0, |
2433 | sizeof(struct mac_stx)); | |
2434 | } | |
f34d28ea | 2435 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2436 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2437 | } | |
2438 | ||
f2e0899f DK |
2439 | if (bp->link_vars.link_up && bp->link_vars.line_speed) { |
2440 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
8a1c38d1 | 2441 | |
f2e0899f DK |
2442 | if (cmng_fns != CMNG_FNS_NONE) { |
2443 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2444 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2445 | } else | |
2446 | /* rate shaping and fairness are disabled */ | |
2447 | DP(NETIF_MSG_IFUP, | |
2448 | "single function mode without fairness\n"); | |
34f80b04 | 2449 | } |
9fdc3e95 | 2450 | |
2ae17f66 VZ |
2451 | __bnx2x_link_report(bp); |
2452 | ||
9fdc3e95 DK |
2453 | if (IS_MF(bp)) |
2454 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2455 | } |
a2fbb9ea | 2456 | |
9f6c9258 | 2457 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2458 | { |
2ae17f66 | 2459 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2460 | return; |
a2fbb9ea | 2461 | |
00253a8c | 2462 | /* read updated dcb configuration */ |
ad5afc89 AE |
2463 | if (IS_PF(bp)) { |
2464 | bnx2x_dcbx_pmf_update(bp); | |
2465 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); | |
2466 | if (bp->link_vars.link_up) | |
2467 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2468 | else | |
2469 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2470 | /* indicate link status */ | |
2471 | bnx2x_link_report(bp); | |
a2fbb9ea | 2472 | |
ad5afc89 AE |
2473 | } else { /* VF */ |
2474 | bp->port.supported[0] |= (SUPPORTED_10baseT_Half | | |
2475 | SUPPORTED_10baseT_Full | | |
2476 | SUPPORTED_100baseT_Half | | |
2477 | SUPPORTED_100baseT_Full | | |
2478 | SUPPORTED_1000baseT_Full | | |
2479 | SUPPORTED_2500baseX_Full | | |
2480 | SUPPORTED_10000baseT_Full | | |
2481 | SUPPORTED_TP | | |
2482 | SUPPORTED_FIBRE | | |
2483 | SUPPORTED_Autoneg | | |
2484 | SUPPORTED_Pause | | |
2485 | SUPPORTED_Asym_Pause); | |
2486 | bp->port.advertising[0] = bp->port.supported[0]; | |
2487 | ||
2488 | bp->link_params.bp = bp; | |
2489 | bp->link_params.port = BP_PORT(bp); | |
2490 | bp->link_params.req_duplex[0] = DUPLEX_FULL; | |
2491 | bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; | |
2492 | bp->link_params.req_line_speed[0] = SPEED_10000; | |
2493 | bp->link_params.speed_cap_mask[0] = 0x7f0000; | |
2494 | bp->link_params.switch_cfg = SWITCH_CFG_10G; | |
2495 | bp->link_vars.mac_type = MAC_TYPE_BMAC; | |
2496 | bp->link_vars.line_speed = SPEED_10000; | |
2497 | bp->link_vars.link_status = | |
2498 | (LINK_STATUS_LINK_UP | | |
2499 | LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); | |
2500 | bp->link_vars.link_up = 1; | |
2501 | bp->link_vars.duplex = DUPLEX_FULL; | |
2502 | bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
2503 | __bnx2x_link_report(bp); | |
bb2a0f7a | 2504 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
ad5afc89 | 2505 | } |
a2fbb9ea | 2506 | } |
a2fbb9ea | 2507 | |
a3348722 BW |
2508 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2509 | u16 vlan_val, u8 allowed_prio) | |
2510 | { | |
2511 | struct bnx2x_func_state_params func_params = {0}; | |
2512 | struct bnx2x_func_afex_update_params *f_update_params = | |
2513 | &func_params.params.afex_update; | |
2514 | ||
2515 | func_params.f_obj = &bp->func_obj; | |
2516 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2517 | ||
2518 | /* no need to wait for RAMROD completion, so don't | |
2519 | * set RAMROD_COMP_WAIT flag | |
2520 | */ | |
2521 | ||
2522 | f_update_params->vif_id = vifid; | |
2523 | f_update_params->afex_default_vlan = vlan_val; | |
2524 | f_update_params->allowed_priorities = allowed_prio; | |
2525 | ||
2526 | /* if ramrod can not be sent, response to MCP immediately */ | |
2527 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2528 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2529 | ||
2530 | return 0; | |
2531 | } | |
2532 | ||
2533 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2534 | u16 vif_index, u8 func_bit_map) | |
2535 | { | |
2536 | struct bnx2x_func_state_params func_params = {0}; | |
2537 | struct bnx2x_func_afex_viflists_params *update_params = | |
2538 | &func_params.params.afex_viflists; | |
2539 | int rc; | |
2540 | u32 drv_msg_code; | |
2541 | ||
2542 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2543 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2544 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2545 | cmd_type); | |
2546 | ||
2547 | func_params.f_obj = &bp->func_obj; | |
2548 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2549 | ||
2550 | /* set parameters according to cmd_type */ | |
2551 | update_params->afex_vif_list_command = cmd_type; | |
2552 | update_params->vif_list_index = cpu_to_le16(vif_index); | |
2553 | update_params->func_bit_map = | |
2554 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2555 | update_params->func_to_clear = 0; | |
2556 | drv_msg_code = | |
2557 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2558 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2559 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2560 | ||
2561 | /* if ramrod can not be sent, respond to MCP immediately for | |
2562 | * SET and GET requests (other are not triggered from MCP) | |
2563 | */ | |
2564 | rc = bnx2x_func_state_change(bp, &func_params); | |
2565 | if (rc < 0) | |
2566 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2567 | ||
2568 | return 0; | |
2569 | } | |
2570 | ||
2571 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2572 | { | |
2573 | struct afex_stats afex_stats; | |
2574 | u32 func = BP_ABS_FUNC(bp); | |
2575 | u32 mf_config; | |
2576 | u16 vlan_val; | |
2577 | u32 vlan_prio; | |
2578 | u16 vif_id; | |
2579 | u8 allowed_prio; | |
2580 | u8 vlan_mode; | |
2581 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2582 | ||
2583 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2584 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2585 | DP(BNX2X_MSG_MCP, | |
2586 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2587 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2588 | } | |
2589 | ||
2590 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2591 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2592 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2593 | DP(BNX2X_MSG_MCP, | |
2594 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2595 | vifid, addrs); | |
2596 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2597 | addrs); | |
2598 | } | |
2599 | ||
2600 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2601 | addr_to_write = SHMEM2_RD(bp, | |
2602 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2603 | stats_type = SHMEM2_RD(bp, | |
2604 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2605 | ||
2606 | DP(BNX2X_MSG_MCP, | |
2607 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2608 | addr_to_write); | |
2609 | ||
2610 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2611 | ||
2612 | /* write response to scratchpad, for MCP */ | |
2613 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2614 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2615 | *(((u32 *)(&afex_stats))+i)); | |
2616 | ||
2617 | /* send ack message to MCP */ | |
2618 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2619 | } | |
2620 | ||
2621 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2622 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2623 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2624 | DP(BNX2X_MSG_MCP, | |
2625 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2626 | mf_config); | |
2627 | ||
2628 | /* if VIF_SET is "enabled" */ | |
2629 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2630 | /* set rate limit directly to internal RAM */ | |
2631 | struct cmng_init_input cmng_input; | |
2632 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2633 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2634 | u32 addr = BAR_XSTRORM_INTMEM + | |
2635 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2636 | ||
2637 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2638 | ||
2639 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2640 | m_rs_vn.vn_counter.rate = | |
2641 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2642 | m_rs_vn.vn_counter.quota = | |
2643 | (m_rs_vn.vn_counter.rate * | |
2644 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2645 | ||
2646 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2647 | ||
2648 | /* read relevant values from mf_cfg struct in shmem */ | |
2649 | vif_id = | |
2650 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2651 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2652 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2653 | vlan_val = | |
2654 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2655 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2656 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2657 | vlan_prio = (mf_config & | |
2658 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2659 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2660 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2661 | vlan_mode = | |
2662 | (MF_CFG_RD(bp, | |
2663 | func_mf_config[func].afex_config) & | |
2664 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2665 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2666 | allowed_prio = | |
2667 | (MF_CFG_RD(bp, | |
2668 | func_mf_config[func].afex_config) & | |
2669 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2670 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2671 | ||
2672 | /* send ramrod to FW, return in case of failure */ | |
2673 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2674 | allowed_prio)) | |
2675 | return; | |
2676 | ||
2677 | bp->afex_def_vlan_tag = vlan_val; | |
2678 | bp->afex_vlan_mode = vlan_mode; | |
2679 | } else { | |
2680 | /* notify link down because BP->flags is disabled */ | |
2681 | bnx2x_link_report(bp); | |
2682 | ||
2683 | /* send INVALID VIF ramrod to FW */ | |
2684 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2685 | ||
2686 | /* Reset the default afex VLAN */ | |
2687 | bp->afex_def_vlan_tag = -1; | |
2688 | } | |
2689 | } | |
2690 | } | |
2691 | ||
34f80b04 EG |
2692 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2693 | { | |
2694 | int port = BP_PORT(bp); | |
2695 | u32 val; | |
2696 | ||
2697 | bp->port.pmf = 1; | |
51c1a580 | 2698 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2699 | |
3deb8167 YR |
2700 | /* |
2701 | * We need the mb() to ensure the ordering between the writing to | |
2702 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2703 | */ | |
2704 | smp_mb(); | |
2705 | ||
2706 | /* queue a periodic task */ | |
2707 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2708 | ||
ef01854e DK |
2709 | bnx2x_dcbx_pmf_update(bp); |
2710 | ||
34f80b04 | 2711 | /* enable nig attention */ |
3395a033 | 2712 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2713 | if (bp->common.int_block == INT_BLOCK_HC) { |
2714 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2715 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2716 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2717 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2718 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2719 | } | |
bb2a0f7a YG |
2720 | |
2721 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2722 | } |
2723 | ||
c18487ee | 2724 | /* end of Link */ |
a2fbb9ea ET |
2725 | |
2726 | /* slow path */ | |
2727 | ||
2728 | /* | |
2729 | * General service functions | |
2730 | */ | |
2731 | ||
2691d51d | 2732 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2733 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2734 | { |
f2e0899f | 2735 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2736 | u32 seq; |
2691d51d EG |
2737 | u32 rc = 0; |
2738 | u32 cnt = 1; | |
2739 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2740 | ||
c4ff7cbf | 2741 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2742 | seq = ++bp->fw_seq; |
f2e0899f DK |
2743 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2744 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2745 | ||
754a2f52 DK |
2746 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2747 | (command | seq), param); | |
2691d51d EG |
2748 | |
2749 | do { | |
2750 | /* let the FW do it's magic ... */ | |
2751 | msleep(delay); | |
2752 | ||
f2e0899f | 2753 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2754 | |
c4ff7cbf EG |
2755 | /* Give the FW up to 5 second (500*10ms) */ |
2756 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2757 | |
2758 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2759 | cnt*delay, rc, seq); | |
2760 | ||
2761 | /* is this a reply to our command? */ | |
2762 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2763 | rc &= FW_MSG_CODE_MASK; | |
2764 | else { | |
2765 | /* FW BUG! */ | |
2766 | BNX2X_ERR("FW failed to respond!\n"); | |
2767 | bnx2x_fw_dump(bp); | |
2768 | rc = 0; | |
2769 | } | |
c4ff7cbf | 2770 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2771 | |
2772 | return rc; | |
2773 | } | |
2774 | ||
ec6ba945 | 2775 | |
1191cb83 ED |
2776 | static void storm_memset_func_cfg(struct bnx2x *bp, |
2777 | struct tstorm_eth_function_common_config *tcfg, | |
2778 | u16 abs_fid) | |
2779 | { | |
2780 | size_t size = sizeof(struct tstorm_eth_function_common_config); | |
2781 | ||
2782 | u32 addr = BAR_TSTRORM_INTMEM + | |
2783 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); | |
2784 | ||
2785 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); | |
2786 | } | |
2787 | ||
619c5cb6 VZ |
2788 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2789 | { | |
2790 | if (CHIP_IS_E1x(bp)) { | |
2791 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2792 | ||
2793 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2794 | } | |
2795 | ||
2796 | /* Enable the function in the FW */ | |
2797 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2798 | storm_memset_func_en(bp, p->func_id, 1); | |
2799 | ||
2800 | /* spq */ | |
2801 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2802 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2803 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2804 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2805 | } | |
2806 | } | |
2807 | ||
6383c0b3 AE |
2808 | /** |
2809 | * bnx2x_get_tx_only_flags - Return common flags | |
2810 | * | |
2811 | * @bp device handle | |
2812 | * @fp queue handle | |
2813 | * @zero_stats TRUE if statistics zeroing is needed | |
2814 | * | |
2815 | * Return the flags that are common for the Tx-only and not normal connections. | |
2816 | */ | |
1191cb83 ED |
2817 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
2818 | struct bnx2x_fastpath *fp, | |
2819 | bool zero_stats) | |
28912902 | 2820 | { |
619c5cb6 VZ |
2821 | unsigned long flags = 0; |
2822 | ||
2823 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2824 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2825 | |
6383c0b3 AE |
2826 | /* tx only connections collect statistics (on the same index as the |
2827 | * parent connection). The statistics are zeroed when the parent | |
2828 | * connection is initialized. | |
2829 | */ | |
50f0a562 BW |
2830 | |
2831 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2832 | if (zero_stats) | |
2833 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2834 | ||
6383c0b3 AE |
2835 | |
2836 | return flags; | |
2837 | } | |
2838 | ||
1191cb83 ED |
2839 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
2840 | struct bnx2x_fastpath *fp, | |
2841 | bool leading) | |
6383c0b3 AE |
2842 | { |
2843 | unsigned long flags = 0; | |
2844 | ||
619c5cb6 VZ |
2845 | /* calculate other queue flags */ |
2846 | if (IS_MF_SD(bp)) | |
2847 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 2848 | |
a3348722 | 2849 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 2850 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
2851 | /* For FCoE - force usage of default priority (for afex) */ |
2852 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
2853 | } | |
523224a3 | 2854 | |
f5219d8e | 2855 | if (!fp->disable_tpa) { |
619c5cb6 | 2856 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 2857 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
2858 | if (fp->mode == TPA_MODE_GRO) |
2859 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 2860 | } |
619c5cb6 | 2861 | |
619c5cb6 VZ |
2862 | if (leading) { |
2863 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
2864 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
2865 | } | |
523224a3 | 2866 | |
619c5cb6 VZ |
2867 | /* Always set HW VLAN stripping */ |
2868 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 2869 | |
a3348722 BW |
2870 | /* configure silent vlan removal */ |
2871 | if (IS_MF_AFEX(bp)) | |
2872 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
2873 | ||
6383c0b3 AE |
2874 | |
2875 | return flags | bnx2x_get_common_flags(bp, fp, true); | |
523224a3 DK |
2876 | } |
2877 | ||
619c5cb6 | 2878 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
2879 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
2880 | u8 cos) | |
619c5cb6 VZ |
2881 | { |
2882 | gen_init->stat_id = bnx2x_stats_id(fp); | |
2883 | gen_init->spcl_id = fp->cl_id; | |
2884 | ||
2885 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
2886 | if (IS_FCOE_FP(fp)) | |
2887 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
2888 | else | |
2889 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
2890 | |
2891 | gen_init->cos = cos; | |
619c5cb6 VZ |
2892 | } |
2893 | ||
2894 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 2895 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 2896 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 2897 | { |
619c5cb6 | 2898 | u8 max_sge = 0; |
523224a3 DK |
2899 | u16 sge_sz = 0; |
2900 | u16 tpa_agg_size = 0; | |
2901 | ||
523224a3 | 2902 | if (!fp->disable_tpa) { |
dfacf138 DK |
2903 | pause->sge_th_lo = SGE_TH_LO(bp); |
2904 | pause->sge_th_hi = SGE_TH_HI(bp); | |
2905 | ||
2906 | /* validate SGE ring has enough to cross high threshold */ | |
2907 | WARN_ON(bp->dropless_fc && | |
2908 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
2909 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
2910 | ||
523224a3 DK |
2911 | tpa_agg_size = min_t(u32, |
2912 | (min_t(u32, 8, MAX_SKB_FRAGS) * | |
2913 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); | |
2914 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> | |
2915 | SGE_PAGE_SHIFT; | |
2916 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
2917 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
2918 | sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, | |
2919 | 0xffff); | |
2920 | } | |
2921 | ||
2922 | /* pause - not for e1 */ | |
2923 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
2924 | pause->bd_th_lo = BD_TH_LO(bp); |
2925 | pause->bd_th_hi = BD_TH_HI(bp); | |
2926 | ||
2927 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
2928 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
2929 | /* | |
2930 | * validate that rings have enough entries to cross | |
2931 | * high thresholds | |
2932 | */ | |
2933 | WARN_ON(bp->dropless_fc && | |
2934 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
2935 | bp->rx_ring_size); | |
2936 | WARN_ON(bp->dropless_fc && | |
2937 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
2938 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 2939 | |
523224a3 DK |
2940 | pause->pri_map = 1; |
2941 | } | |
2942 | ||
2943 | /* rxq setup */ | |
523224a3 DK |
2944 | rxq_init->dscr_map = fp->rx_desc_mapping; |
2945 | rxq_init->sge_map = fp->rx_sge_mapping; | |
2946 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
2947 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 2948 | |
619c5cb6 VZ |
2949 | /* This should be a maximum number of data bytes that may be |
2950 | * placed on the BD (not including paddings). | |
2951 | */ | |
e52fcb24 ED |
2952 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
2953 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; | |
a8c94b91 | 2954 | |
523224a3 | 2955 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
2956 | rxq_init->tpa_agg_sz = tpa_agg_size; |
2957 | rxq_init->sge_buf_sz = sge_sz; | |
2958 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 2959 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 2960 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
2961 | |
2962 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
2963 | * | |
2964 | * For PF Clients it should be the maximum avaliable number. | |
2965 | * VF driver(s) may want to define it to a smaller value. | |
2966 | */ | |
dfacf138 | 2967 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 2968 | |
523224a3 DK |
2969 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
2970 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
2971 | ||
ec6ba945 VZ |
2972 | if (IS_FCOE_FP(fp)) |
2973 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
2974 | else | |
6383c0b3 | 2975 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
2976 | /* configure silent vlan removal |
2977 | * if multi function mode is afex, then mask default vlan | |
2978 | */ | |
2979 | if (IS_MF_AFEX(bp)) { | |
2980 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
2981 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
2982 | } | |
523224a3 DK |
2983 | } |
2984 | ||
619c5cb6 | 2985 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
2986 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
2987 | u8 cos) | |
523224a3 | 2988 | { |
65565884 | 2989 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
6383c0b3 | 2990 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
523224a3 DK |
2991 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
2992 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 2993 | |
619c5cb6 VZ |
2994 | /* |
2995 | * set the tss leading client id for TX classfication == | |
2996 | * leading RSS client id | |
2997 | */ | |
2998 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
2999 | ||
ec6ba945 VZ |
3000 | if (IS_FCOE_FP(fp)) { |
3001 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
3002 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
3003 | } | |
523224a3 DK |
3004 | } |
3005 | ||
8d96286a | 3006 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
3007 | { |
3008 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
3009 | struct event_ring_data eq_data = { {0} }; |
3010 | u16 flags; | |
3011 | ||
619c5cb6 | 3012 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
3013 | /* reset IGU PF statistics: MSIX + ATTN */ |
3014 | /* PF */ | |
3015 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3016 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3017 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3018 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3019 | /* ATTN */ | |
3020 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3021 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3022 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
3023 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3024 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3025 | } | |
3026 | ||
523224a3 DK |
3027 | /* function setup flags */ |
3028 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
3029 | ||
619c5cb6 VZ |
3030 | /* This flag is relevant for E1x only. |
3031 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 3032 | */ |
619c5cb6 | 3033 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
3034 | |
3035 | func_init.func_flgs = flags; | |
3036 | func_init.pf_id = BP_FUNC(bp); | |
3037 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
3038 | func_init.spq_map = bp->spq_mapping; |
3039 | func_init.spq_prod = bp->spq_prod_idx; | |
3040 | ||
3041 | bnx2x_func_init(bp, &func_init); | |
3042 | ||
3043 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
3044 | ||
3045 | /* | |
619c5cb6 VZ |
3046 | * Congestion management values depend on the link rate |
3047 | * There is no active link so initial link rate is set to 10 Gbps. | |
3048 | * When the link comes up The congestion management values are | |
3049 | * re-calculated according to the actual link rate. | |
3050 | */ | |
523224a3 DK |
3051 | bp->link_vars.line_speed = SPEED_10000; |
3052 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
3053 | ||
3054 | /* Only the PMF sets the HW */ | |
3055 | if (bp->port.pmf) | |
3056 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3057 | ||
523224a3 DK |
3058 | /* init Event Queue */ |
3059 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); | |
3060 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
3061 | eq_data.producer = bp->eq_prod; | |
3062 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
3063 | eq_data.sb_id = DEF_SB_ID; | |
3064 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
3065 | } | |
3066 | ||
3067 | ||
3068 | static void bnx2x_e1h_disable(struct bnx2x *bp) | |
3069 | { | |
3070 | int port = BP_PORT(bp); | |
3071 | ||
619c5cb6 | 3072 | bnx2x_tx_disable(bp); |
523224a3 DK |
3073 | |
3074 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
3075 | } |
3076 | ||
3077 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
3078 | { | |
3079 | int port = BP_PORT(bp); | |
3080 | ||
3081 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
3082 | ||
3083 | /* Tx queue should be only reenabled */ | |
3084 | netif_tx_wake_all_queues(bp->dev); | |
3085 | ||
3086 | /* | |
3087 | * Should not call netif_carrier_on since it will be called if the link | |
3088 | * is up when checking for link state | |
3089 | */ | |
3090 | } | |
3091 | ||
1d187b34 BW |
3092 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
3093 | ||
3094 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
3095 | { | |
3096 | struct eth_stats_info *ether_stat = | |
3097 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
3098 | ||
786fdf0b DC |
3099 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, |
3100 | ETH_STAT_INFO_VERSION_LEN); | |
1d187b34 | 3101 | |
15192a8c BW |
3102 | bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj, |
3103 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
3104 | ether_stat->mac_local); | |
1d187b34 BW |
3105 | |
3106 | ether_stat->mtu_size = bp->dev->mtu; | |
3107 | ||
3108 | if (bp->dev->features & NETIF_F_RXCSUM) | |
3109 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
3110 | if (bp->dev->features & NETIF_F_TSO) | |
3111 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
3112 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3113 | ||
3114 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3115 | ||
3116 | ether_stat->txq_size = bp->tx_ring_size; | |
3117 | ether_stat->rxq_size = bp->rx_ring_size; | |
3118 | } | |
3119 | ||
3120 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3121 | { | |
3122 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3123 | struct fcoe_stats_info *fcoe_stat = | |
3124 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3125 | ||
55c11941 MS |
3126 | if (!CNIC_LOADED(bp)) |
3127 | return; | |
3128 | ||
2e499d3c BW |
3129 | memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT, |
3130 | bp->fip_mac, ETH_ALEN); | |
1d187b34 BW |
3131 | |
3132 | fcoe_stat->qos_priority = | |
3133 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3134 | ||
3135 | /* insert FCoE stats from ramrod response */ | |
3136 | if (!NO_FCOE(bp)) { | |
3137 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
65565884 | 3138 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3139 | tstorm_queue_statistics; |
3140 | ||
3141 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
65565884 | 3142 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3143 | xstorm_queue_statistics; |
3144 | ||
3145 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3146 | &bp->fw_stats_data->fcoe; | |
3147 | ||
3148 | ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, | |
3149 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
3150 | ||
3151 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3152 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3153 | fcoe_stat->rx_bytes_lo, | |
3154 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
3155 | ||
3156 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3157 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3158 | fcoe_stat->rx_bytes_lo, | |
3159 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
3160 | ||
3161 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3162 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3163 | fcoe_stat->rx_bytes_lo, | |
3164 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
3165 | ||
3166 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3167 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
3168 | ||
3169 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3170 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
3171 | ||
3172 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3173 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
3174 | ||
3175 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
f33f1fcc | 3176 | fcoe_q_tstorm_stats->rcv_mcast_pkts); |
1d187b34 BW |
3177 | |
3178 | ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, | |
3179 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
3180 | ||
3181 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3182 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3183 | fcoe_stat->tx_bytes_lo, | |
3184 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
3185 | ||
3186 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3187 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3188 | fcoe_stat->tx_bytes_lo, | |
3189 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
3190 | ||
3191 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3192 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3193 | fcoe_stat->tx_bytes_lo, | |
3194 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
3195 | ||
3196 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3197 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
3198 | ||
3199 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3200 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
3201 | ||
3202 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3203 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
3204 | ||
3205 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3206 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
3207 | } | |
3208 | ||
1d187b34 BW |
3209 | /* ask L5 driver to add data to the struct */ |
3210 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
1d187b34 BW |
3211 | } |
3212 | ||
3213 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3214 | { | |
3215 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3216 | struct iscsi_stats_info *iscsi_stat = | |
3217 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3218 | ||
55c11941 MS |
3219 | if (!CNIC_LOADED(bp)) |
3220 | return; | |
3221 | ||
2e499d3c BW |
3222 | memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT, |
3223 | bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); | |
1d187b34 BW |
3224 | |
3225 | iscsi_stat->qos_priority = | |
3226 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3227 | ||
1d187b34 BW |
3228 | /* ask L5 driver to add data to the struct */ |
3229 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
1d187b34 BW |
3230 | } |
3231 | ||
0793f83f DK |
3232 | /* called due to MCP event (on pmf): |
3233 | * reread new bandwidth configuration | |
3234 | * configure FW | |
3235 | * notify others function about the change | |
3236 | */ | |
1191cb83 | 3237 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3238 | { |
3239 | if (bp->link_vars.link_up) { | |
3240 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3241 | bnx2x_link_sync_notify(bp); | |
3242 | } | |
3243 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3244 | } | |
3245 | ||
1191cb83 | 3246 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3247 | { |
3248 | bnx2x_config_mf_bw(bp); | |
3249 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3250 | } | |
3251 | ||
c8c60d88 YM |
3252 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
3253 | { | |
3254 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); | |
3255 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); | |
3256 | } | |
3257 | ||
1d187b34 BW |
3258 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3259 | { | |
3260 | enum drv_info_opcode op_code; | |
3261 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
3262 | ||
3263 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3264 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3265 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3266 | return; | |
3267 | } | |
3268 | ||
3269 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3270 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3271 | ||
3272 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3273 | sizeof(union drv_info_to_mcp)); | |
3274 | ||
3275 | switch (op_code) { | |
3276 | case ETH_STATS_OPCODE: | |
3277 | bnx2x_drv_info_ether_stat(bp); | |
3278 | break; | |
3279 | case FCOE_STATS_OPCODE: | |
3280 | bnx2x_drv_info_fcoe_stat(bp); | |
3281 | break; | |
3282 | case ISCSI_STATS_OPCODE: | |
3283 | bnx2x_drv_info_iscsi_stat(bp); | |
3284 | break; | |
3285 | default: | |
3286 | /* if op code isn't supported - send NACK */ | |
3287 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3288 | return; | |
3289 | } | |
3290 | ||
3291 | /* if we got drv_info attn from MFW then these fields are defined in | |
3292 | * shmem2 for sure | |
3293 | */ | |
3294 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3295 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3296 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3297 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3298 | ||
3299 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
3300 | } | |
3301 | ||
523224a3 DK |
3302 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
3303 | { | |
3304 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
3305 | ||
3306 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
3307 | ||
3308 | /* | |
3309 | * This is the only place besides the function initialization | |
3310 | * where the bp->flags can change so it is done without any | |
3311 | * locks | |
3312 | */ | |
f2e0899f | 3313 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3314 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3315 | bp->flags |= MF_FUNC_DIS; |
3316 | ||
3317 | bnx2x_e1h_disable(bp); | |
3318 | } else { | |
51c1a580 | 3319 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3320 | bp->flags &= ~MF_FUNC_DIS; |
3321 | ||
3322 | bnx2x_e1h_enable(bp); | |
3323 | } | |
3324 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
3325 | } | |
3326 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 3327 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
3328 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
3329 | } | |
3330 | ||
3331 | /* Report results to MCP */ | |
3332 | if (dcc_event) | |
3333 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
3334 | else | |
3335 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
3336 | } | |
3337 | ||
3338 | /* must be called under the spq lock */ | |
1191cb83 | 3339 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
523224a3 DK |
3340 | { |
3341 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3342 | ||
3343 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3344 | bp->spq_prod_bd = bp->spq; | |
3345 | bp->spq_prod_idx = 0; | |
51c1a580 | 3346 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3347 | } else { |
3348 | bp->spq_prod_bd++; | |
3349 | bp->spq_prod_idx++; | |
3350 | } | |
3351 | return next_spe; | |
3352 | } | |
3353 | ||
3354 | /* must be called under the spq lock */ | |
1191cb83 | 3355 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
28912902 MC |
3356 | { |
3357 | int func = BP_FUNC(bp); | |
3358 | ||
53e51e2f VZ |
3359 | /* |
3360 | * Make sure that BD data is updated before writing the producer: | |
3361 | * BD data is written to the memory, the producer is read from the | |
3362 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3363 | */ | |
3364 | mb(); | |
28912902 | 3365 | |
523224a3 | 3366 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3367 | bp->spq_prod_idx); |
28912902 MC |
3368 | mmiowb(); |
3369 | } | |
3370 | ||
619c5cb6 VZ |
3371 | /** |
3372 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3373 | * | |
3374 | * @cmd: command to check | |
3375 | * @cmd_type: command type | |
3376 | */ | |
1191cb83 | 3377 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
619c5cb6 VZ |
3378 | { |
3379 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3380 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3381 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3382 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3383 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3384 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3385 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3386 | return true; | |
3387 | else | |
3388 | return false; | |
3389 | ||
3390 | } | |
3391 | ||
3392 | ||
3393 | /** | |
3394 | * bnx2x_sp_post - place a single command on an SP ring | |
3395 | * | |
3396 | * @bp: driver handle | |
3397 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3398 | * @cid: SW CID the command is related to | |
3399 | * @data_hi: command private data address (high 32 bits) | |
3400 | * @data_lo: command private data address (low 32 bits) | |
3401 | * @cmd_type: command type (e.g. NONE, ETH) | |
3402 | * | |
3403 | * SP data is handled as if it's always an address pair, thus data fields are | |
3404 | * not swapped to little endian in upper functions. Instead this function swaps | |
3405 | * data as if it's two u32 fields. | |
3406 | */ | |
9f6c9258 | 3407 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3408 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3409 | { |
28912902 | 3410 | struct eth_spe *spe; |
523224a3 | 3411 | u16 type; |
619c5cb6 | 3412 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3413 | |
a2fbb9ea | 3414 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3415 | if (unlikely(bp->panic)) { |
3416 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3417 | return -EIO; |
51c1a580 | 3418 | } |
a2fbb9ea ET |
3419 | #endif |
3420 | ||
34f80b04 | 3421 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3422 | |
6e30dd4e VZ |
3423 | if (common) { |
3424 | if (!atomic_read(&bp->eq_spq_left)) { | |
3425 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3426 | spin_unlock_bh(&bp->spq_lock); | |
3427 | bnx2x_panic(); | |
3428 | return -EBUSY; | |
3429 | } | |
3430 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3431 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3432 | spin_unlock_bh(&bp->spq_lock); | |
3433 | bnx2x_panic(); | |
3434 | return -EBUSY; | |
a2fbb9ea | 3435 | } |
f1410647 | 3436 | |
28912902 MC |
3437 | spe = bnx2x_sp_get_next(bp); |
3438 | ||
a2fbb9ea | 3439 | /* CID needs port number to be encoded int it */ |
28912902 | 3440 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3441 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3442 | HW_CID(bp, cid)); | |
523224a3 | 3443 | |
619c5cb6 | 3444 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3445 | |
523224a3 DK |
3446 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3447 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3448 | |
523224a3 DK |
3449 | spe->hdr.type = cpu_to_le16(type); |
3450 | ||
3451 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3452 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3453 | ||
d6cae238 VZ |
3454 | /* |
3455 | * It's ok if the actual decrement is issued towards the memory | |
3456 | * somewhere between the spin_lock and spin_unlock. Thus no | |
3457 | * more explict memory barrier is needed. | |
3458 | */ | |
3459 | if (common) | |
3460 | atomic_dec(&bp->eq_spq_left); | |
3461 | else | |
3462 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3463 | |
a2fbb9ea | 3464 | |
51c1a580 MS |
3465 | DP(BNX2X_MSG_SP, |
3466 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3467 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3468 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3469 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3470 | HW_CID(bp, cid), data_hi, data_lo, type, |
3471 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3472 | |
28912902 | 3473 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3474 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3475 | return 0; |
3476 | } | |
3477 | ||
3478 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3479 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3480 | { |
72fd0718 | 3481 | u32 j, val; |
34f80b04 | 3482 | int rc = 0; |
a2fbb9ea ET |
3483 | |
3484 | might_sleep(); | |
72fd0718 | 3485 | for (j = 0; j < 1000; j++) { |
a2fbb9ea ET |
3486 | val = (1UL << 31); |
3487 | REG_WR(bp, GRCBASE_MCP + 0x9c, val); | |
3488 | val = REG_RD(bp, GRCBASE_MCP + 0x9c); | |
3489 | if (val & (1L << 31)) | |
3490 | break; | |
3491 | ||
3492 | msleep(5); | |
3493 | } | |
a2fbb9ea | 3494 | if (!(val & (1L << 31))) { |
19680c48 | 3495 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3496 | rc = -EBUSY; |
3497 | } | |
3498 | ||
3499 | return rc; | |
3500 | } | |
3501 | ||
4a37fb66 YG |
3502 | /* release split MCP access lock register */ |
3503 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3504 | { |
72fd0718 | 3505 | REG_WR(bp, GRCBASE_MCP + 0x9c, 0); |
a2fbb9ea ET |
3506 | } |
3507 | ||
523224a3 DK |
3508 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3509 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3510 | ||
1191cb83 | 3511 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
a2fbb9ea | 3512 | { |
523224a3 | 3513 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3514 | u16 rc = 0; |
3515 | ||
3516 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3517 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3518 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3519 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3520 | } |
523224a3 DK |
3521 | |
3522 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3523 | bp->def_idx = def_sb->sp_sb.running_index; | |
3524 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3525 | } |
523224a3 DK |
3526 | |
3527 | /* Do not reorder: indecies reading should complete before handling */ | |
3528 | barrier(); | |
a2fbb9ea ET |
3529 | return rc; |
3530 | } | |
3531 | ||
3532 | /* | |
3533 | * slow path service functions | |
3534 | */ | |
3535 | ||
3536 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3537 | { | |
34f80b04 | 3538 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3539 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3540 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3541 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3542 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3543 | u32 aeu_mask; |
87942b46 | 3544 | u32 nig_mask = 0; |
f2e0899f | 3545 | u32 reg_addr; |
a2fbb9ea | 3546 | |
a2fbb9ea ET |
3547 | if (bp->attn_state & asserted) |
3548 | BNX2X_ERR("IGU ERROR\n"); | |
3549 | ||
3fcaf2e5 EG |
3550 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3551 | aeu_mask = REG_RD(bp, aeu_addr); | |
3552 | ||
a2fbb9ea | 3553 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3554 | aeu_mask, asserted); |
72fd0718 | 3555 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3556 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3557 | |
3fcaf2e5 EG |
3558 | REG_WR(bp, aeu_addr, aeu_mask); |
3559 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3560 | |
3fcaf2e5 | 3561 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3562 | bp->attn_state |= asserted; |
3fcaf2e5 | 3563 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3564 | |
3565 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3566 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3567 | |
a5e9a7cf EG |
3568 | bnx2x_acquire_phy_lock(bp); |
3569 | ||
877e9aa4 | 3570 | /* save nig interrupt mask */ |
87942b46 | 3571 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3572 | |
361c391e YR |
3573 | /* If nig_mask is not set, no need to call the update |
3574 | * function. | |
3575 | */ | |
3576 | if (nig_mask) { | |
3577 | REG_WR(bp, nig_int_mask_addr, 0); | |
3578 | ||
3579 | bnx2x_link_attn(bp); | |
3580 | } | |
a2fbb9ea ET |
3581 | |
3582 | /* handle unicore attn? */ | |
3583 | } | |
3584 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3585 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3586 | ||
3587 | if (asserted & GPIO_2_FUNC) | |
3588 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3589 | ||
3590 | if (asserted & GPIO_3_FUNC) | |
3591 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3592 | ||
3593 | if (asserted & GPIO_4_FUNC) | |
3594 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3595 | ||
3596 | if (port == 0) { | |
3597 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3598 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3599 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3600 | } | |
3601 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3602 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3603 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3604 | } | |
3605 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3606 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3607 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3608 | } | |
3609 | } else { | |
3610 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3611 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3612 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3613 | } | |
3614 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3615 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3616 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3617 | } | |
3618 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3619 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3620 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3621 | } | |
3622 | } | |
3623 | ||
3624 | } /* if hardwired */ | |
3625 | ||
f2e0899f DK |
3626 | if (bp->common.int_block == INT_BLOCK_HC) |
3627 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3628 | COMMAND_REG_ATTN_BITS_SET); | |
3629 | else | |
3630 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3631 | ||
3632 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3633 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3634 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3635 | |
3636 | /* now set back the mask */ | |
a5e9a7cf | 3637 | if (asserted & ATTN_NIG_FOR_FUNC) { |
27c1151c YR |
3638 | /* Verify that IGU ack through BAR was written before restoring |
3639 | * NIG mask. This loop should exit after 2-3 iterations max. | |
3640 | */ | |
3641 | if (bp->common.int_block != INT_BLOCK_HC) { | |
3642 | u32 cnt = 0, igu_acked; | |
3643 | do { | |
3644 | igu_acked = REG_RD(bp, | |
3645 | IGU_REG_ATTENTION_ACK_BITS); | |
3646 | } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && | |
3647 | (++cnt < MAX_IGU_ATTN_ACK_TO)); | |
3648 | if (!igu_acked) | |
3649 | DP(NETIF_MSG_HW, | |
3650 | "Failed to verify IGU ack on time\n"); | |
3651 | barrier(); | |
3652 | } | |
87942b46 | 3653 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3654 | bnx2x_release_phy_lock(bp); |
3655 | } | |
a2fbb9ea ET |
3656 | } |
3657 | ||
1191cb83 | 3658 | static void bnx2x_fan_failure(struct bnx2x *bp) |
fd4ef40d EG |
3659 | { |
3660 | int port = BP_PORT(bp); | |
b7737c9b | 3661 | u32 ext_phy_config; |
fd4ef40d | 3662 | /* mark the failure */ |
b7737c9b YR |
3663 | ext_phy_config = |
3664 | SHMEM_RD(bp, | |
3665 | dev_info.port_hw_config[port].external_phy_config); | |
3666 | ||
3667 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3668 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3669 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3670 | ext_phy_config); |
fd4ef40d EG |
3671 | |
3672 | /* log the failure */ | |
51c1a580 MS |
3673 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
3674 | "Please contact OEM Support for assistance\n"); | |
8304859a AE |
3675 | |
3676 | /* | |
3677 | * Scheudle device reset (unload) | |
3678 | * This is due to some boards consuming sufficient power when driver is | |
3679 | * up to overheat if fan fails. | |
3680 | */ | |
3681 | smp_mb__before_clear_bit(); | |
3682 | set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); | |
3683 | smp_mb__after_clear_bit(); | |
3684 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
3685 | ||
fd4ef40d | 3686 | } |
ab6ad5a4 | 3687 | |
1191cb83 | 3688 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3689 | { |
34f80b04 | 3690 | int port = BP_PORT(bp); |
877e9aa4 | 3691 | int reg_offset; |
d90d96ba | 3692 | u32 val; |
877e9aa4 | 3693 | |
34f80b04 EG |
3694 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3695 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3696 | |
34f80b04 | 3697 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3698 | |
3699 | val = REG_RD(bp, reg_offset); | |
3700 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3701 | REG_WR(bp, reg_offset, val); | |
3702 | ||
3703 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3704 | ||
fd4ef40d | 3705 | /* Fan failure attention */ |
d90d96ba | 3706 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3707 | bnx2x_fan_failure(bp); |
877e9aa4 | 3708 | } |
34f80b04 | 3709 | |
3deb8167 | 3710 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3711 | bnx2x_acquire_phy_lock(bp); |
3712 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3713 | bnx2x_release_phy_lock(bp); | |
3714 | } | |
3715 | ||
34f80b04 EG |
3716 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3717 | ||
3718 | val = REG_RD(bp, reg_offset); | |
3719 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3720 | REG_WR(bp, reg_offset, val); | |
3721 | ||
3722 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3723 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3724 | bnx2x_panic(); |
3725 | } | |
877e9aa4 ET |
3726 | } |
3727 | ||
1191cb83 | 3728 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3729 | { |
3730 | u32 val; | |
3731 | ||
0626b899 | 3732 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3733 | |
3734 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3735 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3736 | /* DORQ discard attention */ | |
3737 | if (val & 0x2) | |
3738 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3739 | } | |
34f80b04 EG |
3740 | |
3741 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3742 | ||
3743 | int port = BP_PORT(bp); | |
3744 | int reg_offset; | |
3745 | ||
3746 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3747 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3748 | ||
3749 | val = REG_RD(bp, reg_offset); | |
3750 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3751 | REG_WR(bp, reg_offset, val); | |
3752 | ||
3753 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3754 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3755 | bnx2x_panic(); |
3756 | } | |
877e9aa4 ET |
3757 | } |
3758 | ||
1191cb83 | 3759 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3760 | { |
3761 | u32 val; | |
3762 | ||
3763 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3764 | ||
3765 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3766 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3767 | /* CFC error attention */ | |
3768 | if (val & 0x2) | |
3769 | BNX2X_ERR("FATAL error from CFC\n"); | |
3770 | } | |
3771 | ||
3772 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3773 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3774 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3775 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3776 | if (val & 0x18000) | |
3777 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3778 | |
3779 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3780 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3781 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3782 | } | |
877e9aa4 | 3783 | } |
34f80b04 EG |
3784 | |
3785 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3786 | ||
3787 | int port = BP_PORT(bp); | |
3788 | int reg_offset; | |
3789 | ||
3790 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3791 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3792 | ||
3793 | val = REG_RD(bp, reg_offset); | |
3794 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3795 | REG_WR(bp, reg_offset, val); | |
3796 | ||
3797 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3798 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3799 | bnx2x_panic(); |
3800 | } | |
877e9aa4 ET |
3801 | } |
3802 | ||
1191cb83 | 3803 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
877e9aa4 | 3804 | { |
34f80b04 EG |
3805 | u32 val; |
3806 | ||
877e9aa4 ET |
3807 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3808 | ||
34f80b04 EG |
3809 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3810 | int func = BP_FUNC(bp); | |
3811 | ||
3812 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 3813 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
3814 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3815 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3816 | val = SHMEM_RD(bp, | |
3817 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3818 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3819 | bnx2x_dcc_event(bp, | |
3820 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3821 | |
3822 | if (val & DRV_STATUS_SET_MF_BW) | |
3823 | bnx2x_set_mf_bw(bp); | |
3824 | ||
1d187b34 BW |
3825 | if (val & DRV_STATUS_DRV_INFO_REQ) |
3826 | bnx2x_handle_drv_info_req(bp); | |
2691d51d | 3827 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3828 | bnx2x_pmf_update(bp); |
3829 | ||
e4901dde | 3830 | if (bp->port.pmf && |
785b9b1a SR |
3831 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
3832 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
3833 | /* start dcbx state machine */ |
3834 | bnx2x_dcbx_set_params(bp, | |
3835 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
3836 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
3837 | bnx2x_handle_afex_cmd(bp, | |
3838 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
c8c60d88 YM |
3839 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
3840 | bnx2x_handle_eee_event(bp); | |
3deb8167 YR |
3841 | if (bp->link_vars.periodic_flags & |
3842 | PERIODIC_FLAGS_LINK_EVENT) { | |
3843 | /* sync with link */ | |
3844 | bnx2x_acquire_phy_lock(bp); | |
3845 | bp->link_vars.periodic_flags &= | |
3846 | ~PERIODIC_FLAGS_LINK_EVENT; | |
3847 | bnx2x_release_phy_lock(bp); | |
3848 | if (IS_MF(bp)) | |
3849 | bnx2x_link_sync_notify(bp); | |
3850 | bnx2x_link_report(bp); | |
3851 | } | |
3852 | /* Always call it here: bnx2x_link_report() will | |
3853 | * prevent the link indication duplication. | |
3854 | */ | |
3855 | bnx2x__link_status_update(bp); | |
34f80b04 | 3856 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
3857 | |
3858 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 3859 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
3860 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
3861 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
3862 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
3863 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
3864 | bnx2x_panic(); | |
3865 | ||
3866 | } else if (attn & BNX2X_MCP_ASSERT) { | |
3867 | ||
3868 | BNX2X_ERR("MCP assert!\n"); | |
3869 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 3870 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
3871 | |
3872 | } else | |
3873 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
3874 | } | |
3875 | ||
3876 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
3877 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
3878 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
3879 | val = CHIP_IS_E1(bp) ? 0 : |
3880 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
3881 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
3882 | } | |
3883 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
3884 | val = CHIP_IS_E1(bp) ? 0 : |
3885 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
3886 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
3887 | } | |
877e9aa4 | 3888 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
3889 | } |
3890 | } | |
3891 | ||
c9ee9206 VZ |
3892 | /* |
3893 | * Bits map: | |
3894 | * 0-7 - Engine0 load counter. | |
3895 | * 8-15 - Engine1 load counter. | |
3896 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
3897 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
3898 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
3899 | * on the engine | |
3900 | * 19 - Engine1 ONE_IS_LOADED. | |
3901 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
3902 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
3903 | * just the one belonging to its engine). | |
3904 | * | |
3905 | */ | |
3906 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
3907 | ||
3908 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
3909 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
3910 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
3911 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
3912 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
3913 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
3914 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
3915 | ||
3916 | /* | |
3917 | * Set the GLOBAL_RESET bit. | |
3918 | * | |
3919 | * Should be run under rtnl lock | |
3920 | */ | |
3921 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
3922 | { | |
f16da43b AE |
3923 | u32 val; |
3924 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3925 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3926 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 3927 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
3928 | } |
3929 | ||
3930 | /* | |
3931 | * Clear the GLOBAL_RESET bit. | |
3932 | * | |
3933 | * Should be run under rtnl lock | |
3934 | */ | |
1191cb83 | 3935 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
c9ee9206 | 3936 | { |
f16da43b AE |
3937 | u32 val; |
3938 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
3939 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 3940 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 3941 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 3942 | } |
f85582f8 | 3943 | |
72fd0718 | 3944 | /* |
c9ee9206 VZ |
3945 | * Checks the GLOBAL_RESET bit. |
3946 | * | |
72fd0718 VZ |
3947 | * should be run under rtnl lock |
3948 | */ | |
1191cb83 | 3949 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
c9ee9206 VZ |
3950 | { |
3951 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
3952 | ||
3953 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
3954 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
3955 | } | |
3956 | ||
3957 | /* | |
3958 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
3959 | * | |
3960 | * Should be run under rtnl lock | |
3961 | */ | |
1191cb83 | 3962 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
72fd0718 | 3963 | { |
f16da43b | 3964 | u32 val; |
c9ee9206 VZ |
3965 | u32 bit = BP_PATH(bp) ? |
3966 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
3967 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3968 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
3969 | |
3970 | /* Clear the bit */ | |
3971 | val &= ~bit; | |
3972 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
3973 | |
3974 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
3975 | } |
3976 | ||
3977 | /* | |
c9ee9206 VZ |
3978 | * Set RESET_IN_PROGRESS for the current engine. |
3979 | * | |
72fd0718 VZ |
3980 | * should be run under rtnl lock |
3981 | */ | |
c9ee9206 | 3982 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 3983 | { |
f16da43b | 3984 | u32 val; |
c9ee9206 VZ |
3985 | u32 bit = BP_PATH(bp) ? |
3986 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
3987 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
3988 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
3989 | |
3990 | /* Set the bit */ | |
3991 | val |= bit; | |
3992 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 3993 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
3994 | } |
3995 | ||
3996 | /* | |
c9ee9206 | 3997 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
3998 | * should be run under rtnl lock |
3999 | */ | |
c9ee9206 | 4000 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 4001 | { |
c9ee9206 VZ |
4002 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
4003 | u32 bit = engine ? | |
4004 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
4005 | ||
4006 | /* return false if bit is set */ | |
4007 | return (val & bit) ? false : true; | |
72fd0718 VZ |
4008 | } |
4009 | ||
4010 | /* | |
889b9af3 | 4011 | * set pf load for the current pf. |
c9ee9206 | 4012 | * |
72fd0718 VZ |
4013 | * should be run under rtnl lock |
4014 | */ | |
889b9af3 | 4015 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 4016 | { |
f16da43b | 4017 | u32 val1, val; |
c9ee9206 VZ |
4018 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4019 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4020 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4021 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4022 | |
f16da43b AE |
4023 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4024 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4025 | ||
51c1a580 | 4026 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4027 | |
c9ee9206 VZ |
4028 | /* get the current counter value */ |
4029 | val1 = (val & mask) >> shift; | |
4030 | ||
889b9af3 AE |
4031 | /* set bit of that PF */ |
4032 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
4033 | |
4034 | /* clear the old value */ | |
4035 | val &= ~mask; | |
4036 | ||
4037 | /* set the new one */ | |
4038 | val |= ((val1 << shift) & mask); | |
4039 | ||
4040 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4041 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4042 | } |
4043 | ||
c9ee9206 | 4044 | /** |
889b9af3 | 4045 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
4046 | * |
4047 | * @bp: driver handle | |
4048 | * | |
4049 | * Should be run under rtnl lock. | |
4050 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 4051 | * whether other functions are still loaded |
72fd0718 | 4052 | */ |
889b9af3 | 4053 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 4054 | { |
f16da43b | 4055 | u32 val1, val; |
c9ee9206 VZ |
4056 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4057 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4058 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4059 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4060 | |
f16da43b AE |
4061 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4062 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 4063 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4064 | |
c9ee9206 VZ |
4065 | /* get the current counter value */ |
4066 | val1 = (val & mask) >> shift; | |
4067 | ||
889b9af3 AE |
4068 | /* clear bit of that PF */ |
4069 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
4070 | |
4071 | /* clear the old value */ | |
4072 | val &= ~mask; | |
4073 | ||
4074 | /* set the new one */ | |
4075 | val |= ((val1 << shift) & mask); | |
4076 | ||
4077 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4078 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4079 | return val1 != 0; | |
72fd0718 VZ |
4080 | } |
4081 | ||
4082 | /* | |
889b9af3 | 4083 | * Read the load status for the current engine. |
c9ee9206 | 4084 | * |
72fd0718 VZ |
4085 | * should be run under rtnl lock |
4086 | */ | |
1191cb83 | 4087 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 4088 | { |
c9ee9206 VZ |
4089 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
4090 | BNX2X_PATH0_LOAD_CNT_MASK); | |
4091 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4092 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
4093 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4094 | ||
51c1a580 | 4095 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
4096 | |
4097 | val = (val & mask) >> shift; | |
4098 | ||
51c1a580 MS |
4099 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
4100 | engine, val); | |
c9ee9206 | 4101 | |
889b9af3 | 4102 | return val != 0; |
72fd0718 VZ |
4103 | } |
4104 | ||
1191cb83 | 4105 | static void _print_next_block(int idx, const char *blk) |
72fd0718 | 4106 | { |
f1deab50 | 4107 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
4108 | } |
4109 | ||
1191cb83 ED |
4110 | static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, |
4111 | bool print) | |
72fd0718 VZ |
4112 | { |
4113 | int i = 0; | |
4114 | u32 cur_bit = 0; | |
4115 | for (i = 0; sig; i++) { | |
4116 | cur_bit = ((u32)0x1 << i); | |
4117 | if (sig & cur_bit) { | |
4118 | switch (cur_bit) { | |
4119 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
c9ee9206 VZ |
4120 | if (print) |
4121 | _print_next_block(par_num++, "BRB"); | |
72fd0718 VZ |
4122 | break; |
4123 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
c9ee9206 VZ |
4124 | if (print) |
4125 | _print_next_block(par_num++, "PARSER"); | |
72fd0718 VZ |
4126 | break; |
4127 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4128 | if (print) |
4129 | _print_next_block(par_num++, "TSDM"); | |
72fd0718 VZ |
4130 | break; |
4131 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
c9ee9206 VZ |
4132 | if (print) |
4133 | _print_next_block(par_num++, | |
4134 | "SEARCHER"); | |
4135 | break; | |
4136 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
4137 | if (print) | |
4138 | _print_next_block(par_num++, "TCM"); | |
72fd0718 VZ |
4139 | break; |
4140 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4141 | if (print) |
4142 | _print_next_block(par_num++, "TSEMI"); | |
4143 | break; | |
4144 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
4145 | if (print) | |
4146 | _print_next_block(par_num++, "XPB"); | |
72fd0718 VZ |
4147 | break; |
4148 | } | |
4149 | ||
4150 | /* Clear the bit */ | |
4151 | sig &= ~cur_bit; | |
4152 | } | |
4153 | } | |
4154 | ||
4155 | return par_num; | |
4156 | } | |
4157 | ||
1191cb83 ED |
4158 | static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, |
4159 | bool *global, bool print) | |
72fd0718 VZ |
4160 | { |
4161 | int i = 0; | |
4162 | u32 cur_bit = 0; | |
4163 | for (i = 0; sig; i++) { | |
4164 | cur_bit = ((u32)0x1 << i); | |
4165 | if (sig & cur_bit) { | |
4166 | switch (cur_bit) { | |
c9ee9206 VZ |
4167 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
4168 | if (print) | |
4169 | _print_next_block(par_num++, "PBF"); | |
72fd0718 VZ |
4170 | break; |
4171 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
c9ee9206 VZ |
4172 | if (print) |
4173 | _print_next_block(par_num++, "QM"); | |
4174 | break; | |
4175 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
4176 | if (print) | |
4177 | _print_next_block(par_num++, "TM"); | |
72fd0718 VZ |
4178 | break; |
4179 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4180 | if (print) |
4181 | _print_next_block(par_num++, "XSDM"); | |
4182 | break; | |
4183 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
4184 | if (print) | |
4185 | _print_next_block(par_num++, "XCM"); | |
72fd0718 VZ |
4186 | break; |
4187 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4188 | if (print) |
4189 | _print_next_block(par_num++, "XSEMI"); | |
72fd0718 VZ |
4190 | break; |
4191 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
c9ee9206 VZ |
4192 | if (print) |
4193 | _print_next_block(par_num++, | |
4194 | "DOORBELLQ"); | |
4195 | break; | |
4196 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
4197 | if (print) | |
4198 | _print_next_block(par_num++, "NIG"); | |
72fd0718 VZ |
4199 | break; |
4200 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
4201 | if (print) |
4202 | _print_next_block(par_num++, | |
4203 | "VAUX PCI CORE"); | |
4204 | *global = true; | |
72fd0718 VZ |
4205 | break; |
4206 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
c9ee9206 VZ |
4207 | if (print) |
4208 | _print_next_block(par_num++, "DEBUG"); | |
72fd0718 VZ |
4209 | break; |
4210 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
c9ee9206 VZ |
4211 | if (print) |
4212 | _print_next_block(par_num++, "USDM"); | |
72fd0718 | 4213 | break; |
8736c826 VZ |
4214 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
4215 | if (print) | |
4216 | _print_next_block(par_num++, "UCM"); | |
4217 | break; | |
72fd0718 | 4218 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
c9ee9206 VZ |
4219 | if (print) |
4220 | _print_next_block(par_num++, "USEMI"); | |
72fd0718 VZ |
4221 | break; |
4222 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
c9ee9206 VZ |
4223 | if (print) |
4224 | _print_next_block(par_num++, "UPB"); | |
72fd0718 VZ |
4225 | break; |
4226 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4227 | if (print) |
4228 | _print_next_block(par_num++, "CSDM"); | |
72fd0718 | 4229 | break; |
8736c826 VZ |
4230 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
4231 | if (print) | |
4232 | _print_next_block(par_num++, "CCM"); | |
4233 | break; | |
72fd0718 VZ |
4234 | } |
4235 | ||
4236 | /* Clear the bit */ | |
4237 | sig &= ~cur_bit; | |
4238 | } | |
4239 | } | |
4240 | ||
4241 | return par_num; | |
4242 | } | |
4243 | ||
1191cb83 ED |
4244 | static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, |
4245 | bool print) | |
72fd0718 VZ |
4246 | { |
4247 | int i = 0; | |
4248 | u32 cur_bit = 0; | |
4249 | for (i = 0; sig; i++) { | |
4250 | cur_bit = ((u32)0x1 << i); | |
4251 | if (sig & cur_bit) { | |
4252 | switch (cur_bit) { | |
4253 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4254 | if (print) |
4255 | _print_next_block(par_num++, "CSEMI"); | |
72fd0718 VZ |
4256 | break; |
4257 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
c9ee9206 VZ |
4258 | if (print) |
4259 | _print_next_block(par_num++, "PXP"); | |
72fd0718 VZ |
4260 | break; |
4261 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
4262 | if (print) |
4263 | _print_next_block(par_num++, | |
72fd0718 VZ |
4264 | "PXPPCICLOCKCLIENT"); |
4265 | break; | |
4266 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
c9ee9206 VZ |
4267 | if (print) |
4268 | _print_next_block(par_num++, "CFC"); | |
72fd0718 VZ |
4269 | break; |
4270 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
c9ee9206 VZ |
4271 | if (print) |
4272 | _print_next_block(par_num++, "CDU"); | |
4273 | break; | |
4274 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
4275 | if (print) | |
4276 | _print_next_block(par_num++, "DMAE"); | |
72fd0718 VZ |
4277 | break; |
4278 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
c9ee9206 VZ |
4279 | if (print) |
4280 | _print_next_block(par_num++, "IGU"); | |
72fd0718 VZ |
4281 | break; |
4282 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
c9ee9206 VZ |
4283 | if (print) |
4284 | _print_next_block(par_num++, "MISC"); | |
72fd0718 VZ |
4285 | break; |
4286 | } | |
4287 | ||
4288 | /* Clear the bit */ | |
4289 | sig &= ~cur_bit; | |
4290 | } | |
4291 | } | |
4292 | ||
4293 | return par_num; | |
4294 | } | |
4295 | ||
1191cb83 ED |
4296 | static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
4297 | bool *global, bool print) | |
72fd0718 VZ |
4298 | { |
4299 | int i = 0; | |
4300 | u32 cur_bit = 0; | |
4301 | for (i = 0; sig; i++) { | |
4302 | cur_bit = ((u32)0x1 << i); | |
4303 | if (sig & cur_bit) { | |
4304 | switch (cur_bit) { | |
4305 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
4306 | if (print) |
4307 | _print_next_block(par_num++, "MCP ROM"); | |
4308 | *global = true; | |
72fd0718 VZ |
4309 | break; |
4310 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
4311 | if (print) |
4312 | _print_next_block(par_num++, | |
4313 | "MCP UMP RX"); | |
4314 | *global = true; | |
72fd0718 VZ |
4315 | break; |
4316 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
4317 | if (print) |
4318 | _print_next_block(par_num++, | |
4319 | "MCP UMP TX"); | |
4320 | *global = true; | |
72fd0718 VZ |
4321 | break; |
4322 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
4323 | if (print) |
4324 | _print_next_block(par_num++, | |
4325 | "MCP SCPAD"); | |
4326 | *global = true; | |
72fd0718 VZ |
4327 | break; |
4328 | } | |
4329 | ||
4330 | /* Clear the bit */ | |
4331 | sig &= ~cur_bit; | |
4332 | } | |
4333 | } | |
4334 | ||
4335 | return par_num; | |
4336 | } | |
4337 | ||
1191cb83 ED |
4338 | static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, |
4339 | bool print) | |
8736c826 VZ |
4340 | { |
4341 | int i = 0; | |
4342 | u32 cur_bit = 0; | |
4343 | for (i = 0; sig; i++) { | |
4344 | cur_bit = ((u32)0x1 << i); | |
4345 | if (sig & cur_bit) { | |
4346 | switch (cur_bit) { | |
4347 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
4348 | if (print) | |
4349 | _print_next_block(par_num++, "PGLUE_B"); | |
4350 | break; | |
4351 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
4352 | if (print) | |
4353 | _print_next_block(par_num++, "ATC"); | |
4354 | break; | |
4355 | } | |
4356 | ||
4357 | /* Clear the bit */ | |
4358 | sig &= ~cur_bit; | |
4359 | } | |
4360 | } | |
4361 | ||
4362 | return par_num; | |
4363 | } | |
4364 | ||
1191cb83 ED |
4365 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
4366 | u32 *sig) | |
72fd0718 | 4367 | { |
8736c826 VZ |
4368 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4369 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4370 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4371 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4372 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4373 | int par_num = 0; |
51c1a580 MS |
4374 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4375 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4376 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4377 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4378 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4379 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4380 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4381 | if (print) |
4382 | netdev_err(bp->dev, | |
4383 | "Parity errors detected in blocks: "); | |
4384 | par_num = bnx2x_check_blocks_with_parity0( | |
8736c826 | 4385 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
c9ee9206 | 4386 | par_num = bnx2x_check_blocks_with_parity1( |
8736c826 | 4387 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
c9ee9206 | 4388 | par_num = bnx2x_check_blocks_with_parity2( |
8736c826 | 4389 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
c9ee9206 | 4390 | par_num = bnx2x_check_blocks_with_parity3( |
8736c826 VZ |
4391 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
4392 | par_num = bnx2x_check_blocks_with_parity4( | |
4393 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); | |
4394 | ||
c9ee9206 VZ |
4395 | if (print) |
4396 | pr_cont("\n"); | |
8736c826 | 4397 | |
72fd0718 VZ |
4398 | return true; |
4399 | } else | |
4400 | return false; | |
4401 | } | |
4402 | ||
c9ee9206 VZ |
4403 | /** |
4404 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4405 | * | |
4406 | * @bp: driver handle | |
4407 | * @global: true if there was a global attention | |
4408 | * @print: show parity attention in syslog | |
4409 | */ | |
4410 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4411 | { |
8736c826 | 4412 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4413 | int port = BP_PORT(bp); |
4414 | ||
4415 | attn.sig[0] = REG_RD(bp, | |
4416 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4417 | port*4); | |
4418 | attn.sig[1] = REG_RD(bp, | |
4419 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4420 | port*4); | |
4421 | attn.sig[2] = REG_RD(bp, | |
4422 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4423 | port*4); | |
4424 | attn.sig[3] = REG_RD(bp, | |
4425 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4426 | port*4); | |
4427 | ||
8736c826 VZ |
4428 | if (!CHIP_IS_E1x(bp)) |
4429 | attn.sig[4] = REG_RD(bp, | |
4430 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4431 | port*4); | |
4432 | ||
4433 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4434 | } |
4435 | ||
f2e0899f | 4436 | |
1191cb83 | 4437 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
f2e0899f DK |
4438 | { |
4439 | u32 val; | |
4440 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
4441 | ||
4442 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
4443 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
4444 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 4445 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 4446 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 4447 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 4448 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 4449 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 4450 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 4451 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
4452 | if (val & |
4453 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 4454 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
4455 | if (val & |
4456 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 4457 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 4458 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 4459 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 4460 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 4461 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 4462 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 4463 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
4464 | } |
4465 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4466 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4467 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4468 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4469 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4470 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 4471 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 4472 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 4473 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 4474 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 4475 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
4476 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
4477 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4478 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 4479 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
4480 | } |
4481 | ||
4482 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4483 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4484 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4485 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4486 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4487 | } | |
4488 | ||
4489 | } | |
4490 | ||
72fd0718 VZ |
4491 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4492 | { | |
4493 | struct attn_route attn, *group_mask; | |
34f80b04 | 4494 | int port = BP_PORT(bp); |
877e9aa4 | 4495 | int index; |
a2fbb9ea ET |
4496 | u32 reg_addr; |
4497 | u32 val; | |
3fcaf2e5 | 4498 | u32 aeu_mask; |
c9ee9206 | 4499 | bool global = false; |
a2fbb9ea ET |
4500 | |
4501 | /* need to take HW lock because MCP or other port might also | |
4502 | try to handle this event */ | |
4a37fb66 | 4503 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4504 | |
c9ee9206 VZ |
4505 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4506 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4507 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4508 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4509 | /* Disable HW interrupts */ |
4510 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4511 | /* In case of parity errors don't handle attentions so that |
4512 | * other function would "see" parity errors. | |
4513 | */ | |
c9ee9206 VZ |
4514 | #else |
4515 | bnx2x_panic(); | |
4516 | #endif | |
4517 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4518 | return; |
4519 | } | |
4520 | ||
a2fbb9ea ET |
4521 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4522 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4523 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4524 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4525 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4526 | attn.sig[4] = |
4527 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4528 | else | |
4529 | attn.sig[4] = 0; | |
4530 | ||
4531 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4532 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4533 | |
4534 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4535 | if (deasserted & (1 << index)) { | |
72fd0718 | 4536 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4537 | |
51c1a580 | 4538 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
4539 | index, |
4540 | group_mask->sig[0], group_mask->sig[1], | |
4541 | group_mask->sig[2], group_mask->sig[3], | |
4542 | group_mask->sig[4]); | |
a2fbb9ea | 4543 | |
f2e0899f DK |
4544 | bnx2x_attn_int_deasserted4(bp, |
4545 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4546 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4547 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4548 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4549 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4550 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4551 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4552 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4553 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4554 | } |
4555 | } | |
4556 | ||
4a37fb66 | 4557 | bnx2x_release_alr(bp); |
a2fbb9ea | 4558 | |
f2e0899f DK |
4559 | if (bp->common.int_block == INT_BLOCK_HC) |
4560 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4561 | COMMAND_REG_ATTN_BITS_CLR); | |
4562 | else | |
4563 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4564 | |
4565 | val = ~deasserted; | |
f2e0899f DK |
4566 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4567 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4568 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4569 | |
a2fbb9ea | 4570 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4571 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4572 | |
4573 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4574 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4575 | ||
3fcaf2e5 EG |
4576 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4577 | aeu_mask = REG_RD(bp, reg_addr); | |
4578 | ||
4579 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4580 | aeu_mask, deasserted); | |
72fd0718 | 4581 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4582 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4583 | |
3fcaf2e5 EG |
4584 | REG_WR(bp, reg_addr, aeu_mask); |
4585 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4586 | |
4587 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4588 | bp->attn_state &= ~deasserted; | |
4589 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4590 | } | |
4591 | ||
4592 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4593 | { | |
4594 | /* read local copy of bits */ | |
68d59484 EG |
4595 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4596 | attn_bits); | |
4597 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4598 | attn_bits_ack); | |
a2fbb9ea ET |
4599 | u32 attn_state = bp->attn_state; |
4600 | ||
4601 | /* look for changed bits */ | |
4602 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4603 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4604 | ||
4605 | DP(NETIF_MSG_HW, | |
4606 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4607 | attn_bits, attn_ack, asserted, deasserted); | |
4608 | ||
4609 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4610 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4611 | |
4612 | /* handle bits that were raised */ | |
4613 | if (asserted) | |
4614 | bnx2x_attn_int_asserted(bp, asserted); | |
4615 | ||
4616 | if (deasserted) | |
4617 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4618 | } | |
4619 | ||
619c5cb6 VZ |
4620 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4621 | u16 index, u8 op, u8 update) | |
4622 | { | |
4623 | u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
4624 | ||
4625 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, | |
4626 | igu_addr); | |
4627 | } | |
4628 | ||
1191cb83 | 4629 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
523224a3 DK |
4630 | { |
4631 | /* No memory barriers */ | |
4632 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4633 | mmiowb(); /* keep prod updates ordered */ | |
4634 | } | |
4635 | ||
523224a3 DK |
4636 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, |
4637 | union event_ring_elem *elem) | |
4638 | { | |
619c5cb6 VZ |
4639 | u8 err = elem->message.error; |
4640 | ||
523224a3 | 4641 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4642 | (cid < bp->cnic_eth_dev.starting_cid && |
4643 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4644 | return 1; |
4645 | ||
4646 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4647 | ||
619c5cb6 VZ |
4648 | if (unlikely(err)) { |
4649 | ||
523224a3 DK |
4650 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4651 | cid); | |
4652 | bnx2x_panic_dump(bp); | |
4653 | } | |
619c5cb6 | 4654 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4655 | return 0; |
4656 | } | |
523224a3 | 4657 | |
1191cb83 | 4658 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
4659 | { |
4660 | struct bnx2x_mcast_ramrod_params rparam; | |
4661 | int rc; | |
4662 | ||
4663 | memset(&rparam, 0, sizeof(rparam)); | |
4664 | ||
4665 | rparam.mcast_obj = &bp->mcast_obj; | |
4666 | ||
4667 | netif_addr_lock_bh(bp->dev); | |
4668 | ||
4669 | /* Clear pending state for the last command */ | |
4670 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4671 | ||
4672 | /* If there are pending mcast commands - send them */ | |
4673 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4674 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4675 | if (rc < 0) | |
4676 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4677 | rc); | |
4678 | } | |
4679 | ||
4680 | netif_addr_unlock_bh(bp->dev); | |
4681 | } | |
4682 | ||
1191cb83 ED |
4683 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
4684 | union event_ring_elem *elem) | |
619c5cb6 VZ |
4685 | { |
4686 | unsigned long ramrod_flags = 0; | |
4687 | int rc = 0; | |
4688 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4689 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4690 | ||
4691 | /* Always push next commands out, don't wait here */ | |
4692 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4693 | ||
4694 | switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { | |
4695 | case BNX2X_FILTER_MAC_PENDING: | |
51c1a580 | 4696 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
55c11941 | 4697 | if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) |
619c5cb6 VZ |
4698 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
4699 | else | |
15192a8c | 4700 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
619c5cb6 VZ |
4701 | |
4702 | break; | |
619c5cb6 | 4703 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 4704 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
4705 | /* This is only relevant for 57710 where multicast MACs are |
4706 | * configured as unicast MACs using the same ramrod. | |
4707 | */ | |
4708 | bnx2x_handle_mcast_eqe(bp); | |
4709 | return; | |
4710 | default: | |
4711 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4712 | elem->message.data.eth_event.echo); | |
4713 | return; | |
4714 | } | |
4715 | ||
4716 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4717 | ||
4718 | if (rc < 0) | |
4719 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4720 | else if (rc > 0) | |
4721 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
4722 | ||
4723 | } | |
4724 | ||
619c5cb6 | 4725 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); |
619c5cb6 | 4726 | |
1191cb83 | 4727 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
4728 | { |
4729 | netif_addr_lock_bh(bp->dev); | |
4730 | ||
4731 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
4732 | ||
4733 | /* Send rx_mode command again if was requested */ | |
4734 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
4735 | bnx2x_set_storm_rx_mode(bp); | |
619c5cb6 VZ |
4736 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, |
4737 | &bp->sp_state)) | |
4738 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
4739 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
4740 | &bp->sp_state)) | |
4741 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
619c5cb6 VZ |
4742 | |
4743 | netif_addr_unlock_bh(bp->dev); | |
4744 | } | |
4745 | ||
1191cb83 | 4746 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
a3348722 BW |
4747 | union event_ring_elem *elem) |
4748 | { | |
4749 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
4750 | DP(BNX2X_MSG_SP, | |
4751 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
4752 | elem->message.data.vif_list_event.func_bit_map); | |
4753 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
4754 | elem->message.data.vif_list_event.func_bit_map); | |
4755 | } else if (elem->message.data.vif_list_event.echo == | |
4756 | VIF_LIST_RULE_SET) { | |
4757 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
4758 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
4759 | } | |
4760 | } | |
4761 | ||
4762 | /* called with rtnl_lock */ | |
1191cb83 | 4763 | static void bnx2x_after_function_update(struct bnx2x *bp) |
a3348722 BW |
4764 | { |
4765 | int q, rc; | |
4766 | struct bnx2x_fastpath *fp; | |
4767 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
4768 | struct bnx2x_queue_update_params *q_update_params = | |
4769 | &queue_params.params.update; | |
4770 | ||
4771 | /* Send Q update command with afex vlan removal values for all Qs */ | |
4772 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; | |
4773 | ||
4774 | /* set silent vlan removal values according to vlan mode */ | |
4775 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
4776 | &q_update_params->update_flags); | |
4777 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
4778 | &q_update_params->update_flags); | |
4779 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
4780 | ||
4781 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
4782 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
4783 | q_update_params->silent_removal_value = 0; | |
4784 | q_update_params->silent_removal_mask = 0; | |
4785 | } else { | |
4786 | q_update_params->silent_removal_value = | |
4787 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
4788 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
4789 | } | |
4790 | ||
4791 | for_each_eth_queue(bp, q) { | |
4792 | /* Set the appropriate Queue object */ | |
4793 | fp = &bp->fp[q]; | |
15192a8c | 4794 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
4795 | |
4796 | /* send the ramrod */ | |
4797 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
4798 | if (rc < 0) | |
4799 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
4800 | q); | |
4801 | } | |
4802 | ||
a3348722 | 4803 | if (!NO_FCOE(bp)) { |
65565884 | 4804 | fp = &bp->fp[FCOE_IDX(bp)]; |
15192a8c | 4805 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
4806 | |
4807 | /* clear pending completion bit */ | |
4808 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
4809 | ||
4810 | /* mark latest Q bit */ | |
4811 | smp_mb__before_clear_bit(); | |
4812 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
4813 | smp_mb__after_clear_bit(); | |
4814 | ||
4815 | /* send Q update ramrod for FCoE Q */ | |
4816 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
4817 | if (rc < 0) | |
4818 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
4819 | q); | |
4820 | } else { | |
4821 | /* If no FCoE ring - ACK MCP now */ | |
4822 | bnx2x_link_report(bp); | |
4823 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
4824 | } | |
a3348722 BW |
4825 | } |
4826 | ||
1191cb83 | 4827 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
619c5cb6 VZ |
4828 | struct bnx2x *bp, u32 cid) |
4829 | { | |
94f05b0f | 4830 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
55c11941 MS |
4831 | |
4832 | if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) | |
15192a8c | 4833 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
619c5cb6 | 4834 | else |
15192a8c | 4835 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
619c5cb6 VZ |
4836 | } |
4837 | ||
523224a3 DK |
4838 | static void bnx2x_eq_int(struct bnx2x *bp) |
4839 | { | |
4840 | u16 hw_cons, sw_cons, sw_prod; | |
4841 | union event_ring_elem *elem; | |
55c11941 | 4842 | u8 echo; |
523224a3 DK |
4843 | u32 cid; |
4844 | u8 opcode; | |
4845 | int spqe_cnt = 0; | |
619c5cb6 VZ |
4846 | struct bnx2x_queue_sp_obj *q_obj; |
4847 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
4848 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
4849 | |
4850 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
4851 | ||
4852 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
4853 | * when we get the the next-page we nned to adjust so the loop | |
4854 | * condition below will be met. The next element is the size of a | |
4855 | * regular element and hence incrementing by 1 | |
4856 | */ | |
4857 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
4858 | hw_cons++; | |
4859 | ||
25985edc | 4860 | /* This function may never run in parallel with itself for a |
523224a3 DK |
4861 | * specific bp, thus there is no need in "paired" read memory |
4862 | * barrier here. | |
4863 | */ | |
4864 | sw_cons = bp->eq_cons; | |
4865 | sw_prod = bp->eq_prod; | |
4866 | ||
d6cae238 | 4867 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 4868 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
4869 | |
4870 | for (; sw_cons != hw_cons; | |
4871 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
4872 | ||
4873 | ||
4874 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; | |
4875 | ||
4876 | cid = SW_CID(elem->message.data.cfc_del_event.cid); | |
4877 | opcode = elem->message.opcode; | |
4878 | ||
4879 | ||
4880 | /* handle eq element */ | |
4881 | switch (opcode) { | |
4882 | case EVENT_RING_OPCODE_STAT_QUERY: | |
51c1a580 MS |
4883 | DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, |
4884 | "got statistics comp event %d\n", | |
619c5cb6 | 4885 | bp->stats_comp++); |
523224a3 | 4886 | /* nothing to do with stats comp */ |
d6cae238 | 4887 | goto next_spqe; |
523224a3 DK |
4888 | |
4889 | case EVENT_RING_OPCODE_CFC_DEL: | |
4890 | /* handle according to cid range */ | |
4891 | /* | |
4892 | * we may want to verify here that the bp state is | |
4893 | * HALTING | |
4894 | */ | |
d6cae238 | 4895 | DP(BNX2X_MSG_SP, |
523224a3 | 4896 | "got delete ramrod for MULTI[%d]\n", cid); |
55c11941 MS |
4897 | |
4898 | if (CNIC_LOADED(bp) && | |
4899 | !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
523224a3 | 4900 | goto next_spqe; |
55c11941 | 4901 | |
619c5cb6 VZ |
4902 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
4903 | ||
4904 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
4905 | break; | |
4906 | ||
4907 | ||
523224a3 DK |
4908 | |
4909 | goto next_spqe; | |
e4901dde VZ |
4910 | |
4911 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 4912 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6debea87 DK |
4913 | if (f_obj->complete_cmd(bp, f_obj, |
4914 | BNX2X_F_CMD_TX_STOP)) | |
4915 | break; | |
e4901dde VZ |
4916 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
4917 | goto next_spqe; | |
619c5cb6 | 4918 | |
e4901dde | 4919 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 4920 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6debea87 DK |
4921 | if (f_obj->complete_cmd(bp, f_obj, |
4922 | BNX2X_F_CMD_TX_START)) | |
4923 | break; | |
e4901dde VZ |
4924 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
4925 | goto next_spqe; | |
55c11941 | 4926 | |
a3348722 | 4927 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
55c11941 MS |
4928 | echo = elem->message.data.function_update_event.echo; |
4929 | if (echo == SWITCH_UPDATE) { | |
4930 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, | |
4931 | "got FUNC_SWITCH_UPDATE ramrod\n"); | |
4932 | if (f_obj->complete_cmd( | |
4933 | bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) | |
4934 | break; | |
a3348722 | 4935 | |
55c11941 MS |
4936 | } else { |
4937 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, | |
4938 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
4939 | f_obj->complete_cmd(bp, f_obj, | |
4940 | BNX2X_F_CMD_AFEX_UPDATE); | |
4941 | ||
4942 | /* We will perform the Queues update from | |
4943 | * sp_rtnl task as all Queue SP operations | |
4944 | * should run under rtnl_lock. | |
4945 | */ | |
4946 | smp_mb__before_clear_bit(); | |
4947 | set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, | |
4948 | &bp->sp_rtnl_state); | |
4949 | smp_mb__after_clear_bit(); | |
4950 | ||
4951 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
4952 | } | |
a3348722 | 4953 | |
a3348722 BW |
4954 | goto next_spqe; |
4955 | ||
4956 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
4957 | f_obj->complete_cmd(bp, f_obj, | |
4958 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
4959 | bnx2x_after_afex_vif_lists(bp, elem); | |
4960 | goto next_spqe; | |
619c5cb6 | 4961 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
4962 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4963 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
4964 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
4965 | break; | |
4966 | ||
4967 | goto next_spqe; | |
4968 | ||
4969 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
4970 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
4971 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
4972 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
4973 | break; | |
4974 | ||
4975 | goto next_spqe; | |
523224a3 DK |
4976 | } |
4977 | ||
4978 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
4979 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
4980 | BNX2X_STATE_OPEN): | |
4981 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 4982 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
4983 | cid = elem->message.data.eth_event.echo & |
4984 | BNX2X_SWCID_MASK; | |
d6cae238 | 4985 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
4986 | cid); |
4987 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
4988 | break; |
4989 | ||
619c5cb6 VZ |
4990 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
4991 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
4992 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 4993 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
4994 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
4995 | BNX2X_STATE_OPEN): | |
4996 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4997 | BNX2X_STATE_DIAG): | |
4998 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
4999 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5000 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 5001 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
5002 | break; |
5003 | ||
619c5cb6 VZ |
5004 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
5005 | BNX2X_STATE_OPEN): | |
5006 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5007 | BNX2X_STATE_DIAG): | |
5008 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5009 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5010 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 5011 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
5012 | break; |
5013 | ||
619c5cb6 VZ |
5014 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
5015 | BNX2X_STATE_OPEN): | |
5016 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
5017 | BNX2X_STATE_DIAG): | |
5018 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 5019 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 5020 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 5021 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
5022 | break; |
5023 | default: | |
5024 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
5025 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
5026 | elem->message.opcode, bp->state); | |
523224a3 DK |
5027 | } |
5028 | next_spqe: | |
5029 | spqe_cnt++; | |
5030 | } /* for */ | |
5031 | ||
8fe23fbd | 5032 | smp_mb__before_atomic_inc(); |
6e30dd4e | 5033 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
5034 | |
5035 | bp->eq_cons = sw_cons; | |
5036 | bp->eq_prod = sw_prod; | |
5037 | /* Make sure that above mem writes were issued towards the memory */ | |
5038 | smp_wmb(); | |
5039 | ||
5040 | /* update producer */ | |
5041 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
5042 | } | |
5043 | ||
a2fbb9ea ET |
5044 | static void bnx2x_sp_task(struct work_struct *work) |
5045 | { | |
1cf167f2 | 5046 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea ET |
5047 | u16 status; |
5048 | ||
a2fbb9ea | 5049 | status = bnx2x_update_dsb_idx(bp); |
34f80b04 EG |
5050 | /* if (status == 0) */ |
5051 | /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ | |
a2fbb9ea | 5052 | |
51c1a580 | 5053 | DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status); |
a2fbb9ea | 5054 | |
877e9aa4 | 5055 | /* HW attentions */ |
523224a3 | 5056 | if (status & BNX2X_DEF_SB_ATT_IDX) { |
a2fbb9ea | 5057 | bnx2x_attn_int(bp); |
523224a3 | 5058 | status &= ~BNX2X_DEF_SB_ATT_IDX; |
cdaa7cb8 VZ |
5059 | } |
5060 | ||
523224a3 DK |
5061 | /* SP events: STAT_QUERY and others */ |
5062 | if (status & BNX2X_DEF_SB_IDX) { | |
ec6ba945 | 5063 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); |
523224a3 | 5064 | |
55c11941 MS |
5065 | if (FCOE_INIT(bp) && |
5066 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { | |
019dbb4c VZ |
5067 | /* |
5068 | * Prevent local bottom-halves from running as | |
5069 | * we are going to change the local NAPI list. | |
5070 | */ | |
5071 | local_bh_disable(); | |
ec6ba945 | 5072 | napi_schedule(&bnx2x_fcoe(bp, napi)); |
019dbb4c VZ |
5073 | local_bh_enable(); |
5074 | } | |
55c11941 | 5075 | |
523224a3 DK |
5076 | /* Handle EQ completions */ |
5077 | bnx2x_eq_int(bp); | |
5078 | ||
5079 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
5080 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
5081 | ||
5082 | status &= ~BNX2X_DEF_SB_IDX; | |
cdaa7cb8 VZ |
5083 | } |
5084 | ||
5085 | if (unlikely(status)) | |
51c1a580 | 5086 | DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n", |
cdaa7cb8 | 5087 | status); |
a2fbb9ea | 5088 | |
523224a3 DK |
5089 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, |
5090 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
a3348722 BW |
5091 | |
5092 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ | |
5093 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
5094 | &bp->sp_state)) { | |
5095 | bnx2x_link_report(bp); | |
5096 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5097 | } | |
a2fbb9ea ET |
5098 | } |
5099 | ||
9f6c9258 | 5100 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
5101 | { |
5102 | struct net_device *dev = dev_instance; | |
5103 | struct bnx2x *bp = netdev_priv(dev); | |
5104 | ||
523224a3 DK |
5105 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
5106 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
5107 | |
5108 | #ifdef BNX2X_STOP_ON_ERROR | |
5109 | if (unlikely(bp->panic)) | |
5110 | return IRQ_HANDLED; | |
5111 | #endif | |
5112 | ||
55c11941 | 5113 | if (CNIC_LOADED(bp)) { |
993ac7b5 MC |
5114 | struct cnic_ops *c_ops; |
5115 | ||
5116 | rcu_read_lock(); | |
5117 | c_ops = rcu_dereference(bp->cnic_ops); | |
5118 | if (c_ops) | |
5119 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
5120 | rcu_read_unlock(); | |
5121 | } | |
55c11941 | 5122 | |
1cf167f2 | 5123 | queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); |
a2fbb9ea ET |
5124 | |
5125 | return IRQ_HANDLED; | |
5126 | } | |
5127 | ||
5128 | /* end of slow path */ | |
5129 | ||
619c5cb6 VZ |
5130 | |
5131 | void bnx2x_drv_pulse(struct bnx2x *bp) | |
5132 | { | |
5133 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5134 | bp->fw_drv_pulse_wr_seq); | |
5135 | } | |
5136 | ||
5137 | ||
a2fbb9ea ET |
5138 | static void bnx2x_timer(unsigned long data) |
5139 | { | |
5140 | struct bnx2x *bp = (struct bnx2x *) data; | |
5141 | ||
5142 | if (!netif_running(bp->dev)) | |
5143 | return; | |
5144 | ||
34f80b04 | 5145 | if (!BP_NOMCP(bp)) { |
f2e0899f | 5146 | int mb_idx = BP_FW_MB_IDX(bp); |
a2fbb9ea ET |
5147 | u32 drv_pulse; |
5148 | u32 mcp_pulse; | |
5149 | ||
5150 | ++bp->fw_drv_pulse_wr_seq; | |
5151 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
5152 | /* TBD - add SYSTEM_TIME */ | |
5153 | drv_pulse = bp->fw_drv_pulse_wr_seq; | |
619c5cb6 | 5154 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5155 | |
f2e0899f | 5156 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5157 | MCP_PULSE_SEQ_MASK); |
5158 | /* The delta between driver pulse and mcp response | |
5159 | * should be 1 (before mcp response) or 0 (after mcp response) | |
5160 | */ | |
5161 | if ((drv_pulse != mcp_pulse) && | |
5162 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { | |
5163 | /* someone lost a heartbeat... */ | |
5164 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
5165 | drv_pulse, mcp_pulse); | |
5166 | } | |
5167 | } | |
5168 | ||
f34d28ea | 5169 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5170 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5171 | |
a2fbb9ea ET |
5172 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5173 | } | |
5174 | ||
5175 | /* end of Statistics */ | |
5176 | ||
5177 | /* nic init */ | |
5178 | ||
5179 | /* | |
5180 | * nic init service functions | |
5181 | */ | |
5182 | ||
1191cb83 | 5183 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5184 | { |
523224a3 DK |
5185 | u32 i; |
5186 | if (!(len%4) && !(addr%4)) | |
5187 | for (i = 0; i < len; i += 4) | |
5188 | REG_WR(bp, addr + i, fill); | |
5189 | else | |
5190 | for (i = 0; i < len; i++) | |
5191 | REG_WR8(bp, addr + i, fill); | |
34f80b04 | 5192 | |
34f80b04 EG |
5193 | } |
5194 | ||
523224a3 | 5195 | /* helper: writes FP SP data to FW - data_size in dwords */ |
1191cb83 ED |
5196 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
5197 | int fw_sb_id, | |
5198 | u32 *sb_data_p, | |
5199 | u32 data_size) | |
34f80b04 | 5200 | { |
a2fbb9ea | 5201 | int index; |
523224a3 DK |
5202 | for (index = 0; index < data_size; index++) |
5203 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5204 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5205 | sizeof(u32)*index, | |
5206 | *(sb_data_p + index)); | |
5207 | } | |
a2fbb9ea | 5208 | |
1191cb83 | 5209 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
523224a3 DK |
5210 | { |
5211 | u32 *sb_data_p; | |
5212 | u32 data_size = 0; | |
f2e0899f | 5213 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5214 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5215 | |
523224a3 | 5216 | /* disable the function first */ |
619c5cb6 | 5217 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5218 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5219 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5220 | sb_data_e2.common.p_func.vf_valid = false; |
5221 | sb_data_p = (u32 *)&sb_data_e2; | |
5222 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5223 | } else { | |
5224 | memset(&sb_data_e1x, 0, | |
5225 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5226 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5227 | sb_data_e1x.common.p_func.vf_valid = false; |
5228 | sb_data_p = (u32 *)&sb_data_e1x; | |
5229 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5230 | } | |
523224a3 | 5231 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5232 | |
523224a3 DK |
5233 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5234 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5235 | CSTORM_STATUS_BLOCK_SIZE); | |
5236 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5237 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5238 | CSTORM_SYNC_BLOCK_SIZE); | |
5239 | } | |
34f80b04 | 5240 | |
523224a3 | 5241 | /* helper: writes SP SB data to FW */ |
1191cb83 | 5242 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
523224a3 DK |
5243 | struct hc_sp_status_block_data *sp_sb_data) |
5244 | { | |
5245 | int func = BP_FUNC(bp); | |
5246 | int i; | |
5247 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5248 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5249 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5250 | i*sizeof(u32), | |
5251 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5252 | } |
5253 | ||
1191cb83 | 5254 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5255 | { |
5256 | int func = BP_FUNC(bp); | |
523224a3 DK |
5257 | struct hc_sp_status_block_data sp_sb_data; |
5258 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5259 | |
619c5cb6 | 5260 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5261 | sp_sb_data.p_func.vf_valid = false; |
5262 | ||
5263 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5264 | ||
5265 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5266 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5267 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5268 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5269 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5270 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
5271 | ||
5272 | } | |
5273 | ||
5274 | ||
1191cb83 | 5275 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
523224a3 DK |
5276 | int igu_sb_id, int igu_seg_id) |
5277 | { | |
5278 | hc_sm->igu_sb_id = igu_sb_id; | |
5279 | hc_sm->igu_seg_id = igu_seg_id; | |
5280 | hc_sm->timer_value = 0xFF; | |
5281 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5282 | } |
5283 | ||
150966ad AE |
5284 | |
5285 | /* allocates state machine ids. */ | |
1191cb83 | 5286 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
150966ad AE |
5287 | { |
5288 | /* zero out state machine indices */ | |
5289 | /* rx indices */ | |
5290 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5291 | ||
5292 | /* tx indices */ | |
5293 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5294 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5295 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5296 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5297 | ||
5298 | /* map indices */ | |
5299 | /* rx indices */ | |
5300 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5301 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5302 | ||
5303 | /* tx indices */ | |
5304 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5305 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5306 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5307 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5308 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5309 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5310 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5311 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5312 | } | |
5313 | ||
8d96286a | 5314 | static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5315 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5316 | { |
523224a3 DK |
5317 | int igu_seg_id; |
5318 | ||
f2e0899f | 5319 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5320 | struct hc_status_block_data_e1x sb_data_e1x; |
5321 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5322 | int data_size; |
5323 | u32 *sb_data_p; | |
5324 | ||
f2e0899f DK |
5325 | if (CHIP_INT_MODE_IS_BC(bp)) |
5326 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5327 | else | |
5328 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5329 | |
5330 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5331 | ||
619c5cb6 | 5332 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5333 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5334 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5335 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5336 | sb_data_e2.common.p_func.vf_id = vfid; | |
5337 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5338 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5339 | sb_data_e2.common.same_igu_sb_1b = true; | |
5340 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5341 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5342 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5343 | sb_data_p = (u32 *)&sb_data_e2; |
5344 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5345 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5346 | } else { |
5347 | memset(&sb_data_e1x, 0, | |
5348 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5349 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5350 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5351 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5352 | sb_data_e1x.common.p_func.vf_valid = false; | |
5353 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
5354 | sb_data_e1x.common.same_igu_sb_1b = true; | |
5355 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
5356 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
5357 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
5358 | sb_data_p = (u32 *)&sb_data_e1x; |
5359 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 5360 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 5361 | } |
523224a3 DK |
5362 | |
5363 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
5364 | igu_sb_id, igu_seg_id); | |
5365 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
5366 | igu_sb_id, igu_seg_id); | |
5367 | ||
51c1a580 | 5368 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 DK |
5369 | |
5370 | /* write indecies to HW */ | |
5371 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); | |
5372 | } | |
5373 | ||
619c5cb6 | 5374 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
5375 | u16 tx_usec, u16 rx_usec) |
5376 | { | |
6383c0b3 | 5377 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 5378 | false, rx_usec); |
6383c0b3 AE |
5379 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
5380 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
5381 | tx_usec); | |
5382 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5383 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
5384 | tx_usec); | |
5385 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5386 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
5387 | tx_usec); | |
523224a3 | 5388 | } |
f2e0899f | 5389 | |
523224a3 DK |
5390 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
5391 | { | |
5392 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
5393 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
5394 | int igu_sp_sb_index; | |
5395 | int igu_seg_id; | |
34f80b04 EG |
5396 | int port = BP_PORT(bp); |
5397 | int func = BP_FUNC(bp); | |
f2eaeb58 | 5398 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 5399 | u64 section; |
523224a3 DK |
5400 | int index; |
5401 | struct hc_sp_status_block_data sp_sb_data; | |
5402 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
5403 | ||
f2e0899f DK |
5404 | if (CHIP_INT_MODE_IS_BC(bp)) { |
5405 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
5406 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
5407 | } else { | |
5408 | igu_sp_sb_index = bp->igu_dsb_id; | |
5409 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
5410 | } | |
a2fbb9ea ET |
5411 | |
5412 | /* ATTN */ | |
523224a3 | 5413 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 5414 | atten_status_block); |
523224a3 | 5415 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 5416 | |
49d66772 ET |
5417 | bp->attn_state = 0; |
5418 | ||
a2fbb9ea ET |
5419 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
5420 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
5421 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
5422 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 5423 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
5424 | int sindex; |
5425 | /* take care of sig[0]..sig[4] */ | |
5426 | for (sindex = 0; sindex < 4; sindex++) | |
5427 | bp->attn_group[index].sig[sindex] = | |
5428 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 5429 | |
619c5cb6 | 5430 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5431 | /* |
5432 | * enable5 is separate from the rest of the registers, | |
5433 | * and therefore the address skip is 4 | |
5434 | * and not 16 between the different groups | |
5435 | */ | |
5436 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 5437 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
5438 | else |
5439 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
5440 | } |
5441 | ||
f2e0899f DK |
5442 | if (bp->common.int_block == INT_BLOCK_HC) { |
5443 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
5444 | HC_REG_ATTN_MSG0_ADDR_L); | |
5445 | ||
5446 | REG_WR(bp, reg_offset, U64_LO(section)); | |
5447 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 5448 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5449 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
5450 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
5451 | } | |
a2fbb9ea | 5452 | |
523224a3 DK |
5453 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
5454 | sp_sb); | |
a2fbb9ea | 5455 | |
523224a3 | 5456 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 5457 | |
619c5cb6 | 5458 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
5459 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
5460 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
5461 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
5462 | sp_sb_data.igu_seg_id = igu_seg_id; | |
5463 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 5464 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 5465 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 5466 | |
523224a3 | 5467 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 5468 | |
523224a3 | 5469 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
5470 | } |
5471 | ||
9f6c9258 | 5472 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 5473 | { |
a2fbb9ea ET |
5474 | int i; |
5475 | ||
ec6ba945 | 5476 | for_each_eth_queue(bp, i) |
523224a3 | 5477 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 5478 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
5479 | } |
5480 | ||
a2fbb9ea ET |
5481 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
5482 | { | |
a2fbb9ea | 5483 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 5484 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 5485 | |
a2fbb9ea | 5486 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
5487 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
5488 | bp->spq_prod_bd = bp->spq; | |
5489 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
5490 | } |
5491 | ||
523224a3 | 5492 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
5493 | { |
5494 | int i; | |
523224a3 DK |
5495 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
5496 | union event_ring_elem *elem = | |
5497 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 5498 | |
523224a3 DK |
5499 | elem->next_page.addr.hi = |
5500 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
5501 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
5502 | elem->next_page.addr.lo = | |
5503 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
5504 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 5505 | } |
523224a3 DK |
5506 | bp->eq_cons = 0; |
5507 | bp->eq_prod = NUM_EQ_DESC; | |
5508 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
6e30dd4e VZ |
5509 | /* we want a warning message before it gets rought... */ |
5510 | atomic_set(&bp->eq_spq_left, | |
5511 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
5512 | } |
5513 | ||
619c5cb6 VZ |
5514 | |
5515 | /* called with netif_addr_lock_bh() */ | |
5516 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, | |
5517 | unsigned long rx_mode_flags, | |
5518 | unsigned long rx_accept_flags, | |
5519 | unsigned long tx_accept_flags, | |
5520 | unsigned long ramrod_flags) | |
ab532cf3 | 5521 | { |
619c5cb6 VZ |
5522 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
5523 | int rc; | |
5524 | ||
5525 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
5526 | ||
5527 | /* Prepare ramrod parameters */ | |
5528 | ramrod_param.cid = 0; | |
5529 | ramrod_param.cl_id = cl_id; | |
5530 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
5531 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 5532 | |
619c5cb6 VZ |
5533 | ramrod_param.pstate = &bp->sp_state; |
5534 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 5535 | |
619c5cb6 VZ |
5536 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
5537 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
5538 | ||
5539 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5540 | ||
5541 | ramrod_param.ramrod_flags = ramrod_flags; | |
5542 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
5543 | ||
5544 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
5545 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
5546 | ||
5547 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
5548 | if (rc < 0) { | |
5549 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
5550 | return; | |
5551 | } | |
a2fbb9ea ET |
5552 | } |
5553 | ||
619c5cb6 VZ |
5554 | /* called with netif_addr_lock_bh() */ |
5555 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
471de716 | 5556 | { |
619c5cb6 VZ |
5557 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; |
5558 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
471de716 | 5559 | |
619c5cb6 VZ |
5560 | if (!NO_FCOE(bp)) |
5561 | ||
5562 | /* Configure rx_mode of FCoE Queue */ | |
5563 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
619c5cb6 VZ |
5564 | |
5565 | switch (bp->rx_mode) { | |
5566 | case BNX2X_RX_MODE_NONE: | |
5567 | /* | |
5568 | * 'drop all' supersedes any accept flags that may have been | |
5569 | * passed to the function. | |
5570 | */ | |
5571 | break; | |
5572 | case BNX2X_RX_MODE_NORMAL: | |
5573 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5574 | __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); | |
5575 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5576 | ||
5577 | /* internal switching mode */ | |
5578 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5579 | __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); | |
5580 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5581 | ||
5582 | break; | |
5583 | case BNX2X_RX_MODE_ALLMULTI: | |
5584 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5585 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5586 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5587 | ||
5588 | /* internal switching mode */ | |
5589 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5590 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5591 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5592 | ||
5593 | break; | |
5594 | case BNX2X_RX_MODE_PROMISC: | |
5595 | /* According to deffinition of SI mode, iface in promisc mode | |
5596 | * should receive matched and unmatched (in resolution of port) | |
5597 | * unicast packets. | |
5598 | */ | |
5599 | __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); | |
5600 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5601 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5602 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5603 | ||
5604 | /* internal switching mode */ | |
5605 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5606 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5607 | ||
5608 | if (IS_MF_SI(bp)) | |
5609 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); | |
5610 | else | |
5611 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5612 | ||
5613 | break; | |
5614 | default: | |
5615 | BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); | |
5616 | return; | |
5617 | } | |
de832a55 | 5618 | |
619c5cb6 VZ |
5619 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
5620 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); | |
5621 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); | |
34f80b04 EG |
5622 | } |
5623 | ||
619c5cb6 VZ |
5624 | __set_bit(RAMROD_RX, &ramrod_flags); |
5625 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5626 | ||
5627 | bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, | |
5628 | tx_accept_flags, ramrod_flags); | |
5629 | } | |
5630 | ||
5631 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5632 | { | |
5633 | int i; | |
5634 | ||
0793f83f DK |
5635 | if (IS_MF_SI(bp)) |
5636 | /* | |
5637 | * In switch independent mode, the TSTORM needs to accept | |
5638 | * packets that failed classification, since approximate match | |
5639 | * mac addresses aren't written to NIG LLH | |
5640 | */ | |
5641 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5642 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5643 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5644 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5645 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5646 | |
523224a3 DK |
5647 | /* Zero this manually as its initialization is |
5648 | currently missing in the initTool */ | |
5649 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5650 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5651 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5652 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5653 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5654 | CHIP_INT_MODE_IS_BC(bp) ? | |
5655 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5656 | } | |
523224a3 | 5657 | } |
8a1c38d1 | 5658 | |
471de716 EG |
5659 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5660 | { | |
5661 | switch (load_code) { | |
5662 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5663 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5664 | bnx2x_init_internal_common(bp); |
5665 | /* no break */ | |
5666 | ||
5667 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5668 | /* nothing to do */ |
471de716 EG |
5669 | /* no break */ |
5670 | ||
5671 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5672 | /* internal memory per function is |
5673 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5674 | break; |
5675 | ||
5676 | default: | |
5677 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
5678 | break; | |
5679 | } | |
5680 | } | |
5681 | ||
619c5cb6 | 5682 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 5683 | { |
55c11941 | 5684 | return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 | 5685 | } |
523224a3 | 5686 | |
619c5cb6 VZ |
5687 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
5688 | { | |
55c11941 | 5689 | return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 VZ |
5690 | } |
5691 | ||
1191cb83 | 5692 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
619c5cb6 VZ |
5693 | { |
5694 | if (CHIP_IS_E1x(fp->bp)) | |
5695 | return BP_L_ID(fp->bp) + fp->index; | |
5696 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
5697 | return bnx2x_fp_igu_sb_id(fp); | |
5698 | } | |
5699 | ||
6383c0b3 | 5700 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
5701 | { |
5702 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 5703 | u8 cos; |
619c5cb6 | 5704 | unsigned long q_type = 0; |
6383c0b3 | 5705 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 5706 | fp->rx_queue = fp_idx; |
b3b83c3f | 5707 | fp->cid = fp_idx; |
619c5cb6 VZ |
5708 | fp->cl_id = bnx2x_fp_cl_id(fp); |
5709 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
5710 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 5711 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
5712 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
5713 | ||
523224a3 | 5714 | /* init shortcut */ |
619c5cb6 | 5715 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 5716 | |
523224a3 DK |
5717 | /* Setup SB indicies */ |
5718 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; | |
523224a3 | 5719 | |
619c5cb6 VZ |
5720 | /* Configure Queue State object */ |
5721 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
5722 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
5723 | |
5724 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
5725 | ||
5726 | /* init tx data */ | |
5727 | for_each_cos_in_tx_queue(fp, cos) { | |
65565884 MS |
5728 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
5729 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), | |
5730 | FP_COS_TO_TXQ(fp, cos, bp), | |
5731 | BNX2X_TX_SB_INDEX_BASE + cos, fp); | |
5732 | cids[cos] = fp->txdata_ptr[cos]->cid; | |
6383c0b3 AE |
5733 | } |
5734 | ||
ad5afc89 AE |
5735 | /* nothing more for vf to do here */ |
5736 | if (IS_VF(bp)) | |
5737 | return; | |
5738 | ||
5739 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
5740 | fp->fw_sb_id, fp->igu_sb_id); | |
5741 | bnx2x_update_fpsb_idx(fp); | |
15192a8c BW |
5742 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
5743 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 5744 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 VZ |
5745 | |
5746 | /** | |
5747 | * Configure classification DBs: Always enable Tx switching | |
5748 | */ | |
5749 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
5750 | ||
ad5afc89 AE |
5751 | DP(NETIF_MSG_IFUP, |
5752 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
5753 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
5754 | fp->igu_sb_id); | |
523224a3 DK |
5755 | } |
5756 | ||
1191cb83 ED |
5757 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
5758 | { | |
5759 | int i; | |
5760 | ||
5761 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
5762 | struct eth_tx_next_bd *tx_next_bd = | |
5763 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
5764 | ||
5765 | tx_next_bd->addr_hi = | |
5766 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + | |
5767 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
5768 | tx_next_bd->addr_lo = | |
5769 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + | |
5770 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
5771 | } | |
5772 | ||
5773 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); | |
5774 | txdata->tx_db.data.zero_fill1 = 0; | |
5775 | txdata->tx_db.data.prod = 0; | |
5776 | ||
5777 | txdata->tx_pkt_prod = 0; | |
5778 | txdata->tx_pkt_cons = 0; | |
5779 | txdata->tx_bd_prod = 0; | |
5780 | txdata->tx_bd_cons = 0; | |
5781 | txdata->tx_pkt = 0; | |
5782 | } | |
5783 | ||
55c11941 MS |
5784 | static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) |
5785 | { | |
5786 | int i; | |
5787 | ||
5788 | for_each_tx_queue_cnic(bp, i) | |
5789 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); | |
5790 | } | |
1191cb83 ED |
5791 | static void bnx2x_init_tx_rings(struct bnx2x *bp) |
5792 | { | |
5793 | int i; | |
5794 | u8 cos; | |
5795 | ||
55c11941 | 5796 | for_each_eth_queue(bp, i) |
1191cb83 | 5797 | for_each_cos_in_tx_queue(&bp->fp[i], cos) |
65565884 | 5798 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
1191cb83 ED |
5799 | } |
5800 | ||
55c11941 | 5801 | void bnx2x_nic_init_cnic(struct bnx2x *bp) |
a2fbb9ea | 5802 | { |
ec6ba945 VZ |
5803 | if (!NO_FCOE(bp)) |
5804 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
5805 | |
5806 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
5807 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 5808 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 5809 | |
55c11941 MS |
5810 | /* ensure status block indices were read */ |
5811 | rmb(); | |
5812 | bnx2x_init_rx_rings_cnic(bp); | |
5813 | bnx2x_init_tx_rings_cnic(bp); | |
5814 | ||
5815 | /* flush all */ | |
5816 | mb(); | |
5817 | mmiowb(); | |
5818 | } | |
a2fbb9ea | 5819 | |
55c11941 MS |
5820 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) |
5821 | { | |
5822 | int i; | |
5823 | ||
5824 | for_each_eth_queue(bp, i) | |
5825 | bnx2x_init_eth_fp(bp, i); | |
ad5afc89 AE |
5826 | |
5827 | /* ensure status block indices were read */ | |
5828 | rmb(); | |
5829 | bnx2x_init_rx_rings(bp); | |
5830 | bnx2x_init_tx_rings(bp); | |
5831 | ||
5832 | if (IS_VF(bp)) | |
5833 | return; | |
5834 | ||
020c7e3f YR |
5835 | /* Initialize MOD_ABS interrupts */ |
5836 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
5837 | bp->common.shmem_base, bp->common.shmem2_base, | |
5838 | BP_PORT(bp)); | |
16119785 | 5839 | |
523224a3 | 5840 | bnx2x_init_def_sb(bp); |
5c862848 | 5841 | bnx2x_update_dsb_idx(bp); |
a2fbb9ea | 5842 | bnx2x_init_sp_ring(bp); |
523224a3 | 5843 | bnx2x_init_eq_ring(bp); |
471de716 | 5844 | bnx2x_init_internal(bp, load_code); |
523224a3 | 5845 | bnx2x_pf_init(bp); |
0ef00459 EG |
5846 | bnx2x_stats_init(bp); |
5847 | ||
0ef00459 EG |
5848 | /* flush all before enabling interrupts */ |
5849 | mb(); | |
5850 | mmiowb(); | |
5851 | ||
615f8fd9 | 5852 | bnx2x_int_enable(bp); |
eb8da205 EG |
5853 | |
5854 | /* Check for SPIO5 */ | |
5855 | bnx2x_attn_int_deasserted0(bp, | |
5856 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
5857 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
5858 | } |
5859 | ||
5860 | /* end of nic init */ | |
5861 | ||
5862 | /* | |
5863 | * gzip service functions | |
5864 | */ | |
5865 | ||
5866 | static int bnx2x_gunzip_init(struct bnx2x *bp) | |
5867 | { | |
1a983142 FT |
5868 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
5869 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
5870 | if (bp->gunzip_buf == NULL) |
5871 | goto gunzip_nomem1; | |
5872 | ||
5873 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
5874 | if (bp->strm == NULL) | |
5875 | goto gunzip_nomem2; | |
5876 | ||
7ab24bfd | 5877 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
5878 | if (bp->strm->workspace == NULL) |
5879 | goto gunzip_nomem3; | |
5880 | ||
5881 | return 0; | |
5882 | ||
5883 | gunzip_nomem3: | |
5884 | kfree(bp->strm); | |
5885 | bp->strm = NULL; | |
5886 | ||
5887 | gunzip_nomem2: | |
1a983142 FT |
5888 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5889 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5890 | bp->gunzip_buf = NULL; |
5891 | ||
5892 | gunzip_nomem1: | |
51c1a580 | 5893 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
5894 | return -ENOMEM; |
5895 | } | |
5896 | ||
5897 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
5898 | { | |
b3b83c3f | 5899 | if (bp->strm) { |
7ab24bfd | 5900 | vfree(bp->strm->workspace); |
b3b83c3f DK |
5901 | kfree(bp->strm); |
5902 | bp->strm = NULL; | |
5903 | } | |
a2fbb9ea ET |
5904 | |
5905 | if (bp->gunzip_buf) { | |
1a983142 FT |
5906 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
5907 | bp->gunzip_mapping); | |
a2fbb9ea ET |
5908 | bp->gunzip_buf = NULL; |
5909 | } | |
5910 | } | |
5911 | ||
94a78b79 | 5912 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
5913 | { |
5914 | int n, rc; | |
5915 | ||
5916 | /* check gzip header */ | |
94a78b79 VZ |
5917 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
5918 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 5919 | return -EINVAL; |
94a78b79 | 5920 | } |
a2fbb9ea ET |
5921 | |
5922 | n = 10; | |
5923 | ||
34f80b04 | 5924 | #define FNAME 0x8 |
a2fbb9ea ET |
5925 | |
5926 | if (zbuf[3] & FNAME) | |
5927 | while ((zbuf[n++] != 0) && (n < len)); | |
5928 | ||
94a78b79 | 5929 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
5930 | bp->strm->avail_in = len - n; |
5931 | bp->strm->next_out = bp->gunzip_buf; | |
5932 | bp->strm->avail_out = FW_BUF_SIZE; | |
5933 | ||
5934 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
5935 | if (rc != Z_OK) | |
5936 | return rc; | |
5937 | ||
5938 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
5939 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
5940 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
5941 | bp->strm->msg); | |
a2fbb9ea ET |
5942 | |
5943 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
5944 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
5945 | netdev_err(bp->dev, |
5946 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 5947 | bp->gunzip_outlen); |
a2fbb9ea ET |
5948 | bp->gunzip_outlen >>= 2; |
5949 | ||
5950 | zlib_inflateEnd(bp->strm); | |
5951 | ||
5952 | if (rc == Z_STREAM_END) | |
5953 | return 0; | |
5954 | ||
5955 | return rc; | |
5956 | } | |
5957 | ||
5958 | /* nic load/unload */ | |
5959 | ||
5960 | /* | |
34f80b04 | 5961 | * General service functions |
a2fbb9ea ET |
5962 | */ |
5963 | ||
5964 | /* send a NIG loopback debug packet */ | |
5965 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
5966 | { | |
a2fbb9ea | 5967 | u32 wb_write[3]; |
a2fbb9ea ET |
5968 | |
5969 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
5970 | wb_write[0] = 0x55555555; |
5971 | wb_write[1] = 0x55555555; | |
34f80b04 | 5972 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 5973 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5974 | |
5975 | /* NON-IP protocol */ | |
a2fbb9ea ET |
5976 | wb_write[0] = 0x09000000; |
5977 | wb_write[1] = 0x55555555; | |
34f80b04 | 5978 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 5979 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
5980 | } |
5981 | ||
5982 | /* some of the internal memories | |
5983 | * are not directly readable from the driver | |
5984 | * to test them we send debug packets | |
5985 | */ | |
5986 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
5987 | { | |
5988 | int factor; | |
5989 | int count, i; | |
5990 | u32 val = 0; | |
5991 | ||
ad8d3948 | 5992 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 5993 | factor = 120; |
ad8d3948 EG |
5994 | else if (CHIP_REV_IS_EMUL(bp)) |
5995 | factor = 200; | |
5996 | else | |
a2fbb9ea | 5997 | factor = 1; |
a2fbb9ea | 5998 | |
a2fbb9ea ET |
5999 | /* Disable inputs of parser neighbor blocks */ |
6000 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6001 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6002 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6003 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6004 | |
6005 | /* Write 0 to parser credits for CFC search request */ | |
6006 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6007 | ||
6008 | /* send Ethernet packet */ | |
6009 | bnx2x_lb_pckt(bp); | |
6010 | ||
6011 | /* TODO do i reset NIG statistic? */ | |
6012 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6013 | count = 1000 * factor; | |
6014 | while (count) { | |
34f80b04 | 6015 | |
a2fbb9ea ET |
6016 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6017 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6018 | if (val == 0x10) |
6019 | break; | |
6020 | ||
6021 | msleep(10); | |
6022 | count--; | |
6023 | } | |
6024 | if (val != 0x10) { | |
6025 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6026 | return -1; | |
6027 | } | |
6028 | ||
6029 | /* Wait until PRS register shows 1 packet */ | |
6030 | count = 1000 * factor; | |
6031 | while (count) { | |
6032 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
6033 | if (val == 1) |
6034 | break; | |
6035 | ||
6036 | msleep(10); | |
6037 | count--; | |
6038 | } | |
6039 | if (val != 0x1) { | |
6040 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6041 | return -2; | |
6042 | } | |
6043 | ||
6044 | /* Reset and init BRB, PRS */ | |
34f80b04 | 6045 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 6046 | msleep(50); |
34f80b04 | 6047 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 6048 | msleep(50); |
619c5cb6 VZ |
6049 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6050 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
6051 | |
6052 | DP(NETIF_MSG_HW, "part2\n"); | |
6053 | ||
6054 | /* Disable inputs of parser neighbor blocks */ | |
6055 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6056 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6057 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6058 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6059 | |
6060 | /* Write 0 to parser credits for CFC search request */ | |
6061 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6062 | ||
6063 | /* send 10 Ethernet packets */ | |
6064 | for (i = 0; i < 10; i++) | |
6065 | bnx2x_lb_pckt(bp); | |
6066 | ||
6067 | /* Wait until NIG register shows 10 + 1 | |
6068 | packets of size 11*0x10 = 0xb0 */ | |
6069 | count = 1000 * factor; | |
6070 | while (count) { | |
34f80b04 | 6071 | |
a2fbb9ea ET |
6072 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6073 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6074 | if (val == 0xb0) |
6075 | break; | |
6076 | ||
6077 | msleep(10); | |
6078 | count--; | |
6079 | } | |
6080 | if (val != 0xb0) { | |
6081 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6082 | return -3; | |
6083 | } | |
6084 | ||
6085 | /* Wait until PRS register shows 2 packets */ | |
6086 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6087 | if (val != 2) | |
6088 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6089 | ||
6090 | /* Write 1 to parser credits for CFC search request */ | |
6091 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
6092 | ||
6093 | /* Wait until PRS register shows 3 packets */ | |
6094 | msleep(10 * factor); | |
6095 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6096 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6097 | if (val != 3) | |
6098 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6099 | ||
6100 | /* clear NIG EOP FIFO */ | |
6101 | for (i = 0; i < 11; i++) | |
6102 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
6103 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
6104 | if (val != 1) { | |
6105 | BNX2X_ERR("clear of NIG failed\n"); | |
6106 | return -4; | |
6107 | } | |
6108 | ||
6109 | /* Reset and init BRB, PRS, NIG */ | |
6110 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
6111 | msleep(50); | |
6112 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
6113 | msleep(50); | |
619c5cb6 VZ |
6114 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6115 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
55c11941 MS |
6116 | if (!CNIC_SUPPORT(bp)) |
6117 | /* set NIC mode */ | |
6118 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
a2fbb9ea ET |
6119 | |
6120 | /* Enable inputs of parser neighbor blocks */ | |
6121 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
6122 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
6123 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 6124 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
6125 | |
6126 | DP(NETIF_MSG_HW, "done\n"); | |
6127 | ||
6128 | return 0; /* OK */ | |
6129 | } | |
6130 | ||
4a33bc03 | 6131 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea | 6132 | { |
b343d002 YM |
6133 | u32 val; |
6134 | ||
a2fbb9ea | 6135 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); |
619c5cb6 | 6136 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6137 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
6138 | else | |
6139 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
6140 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
6141 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
6142 | /* |
6143 | * mask read length error interrupts in brb for parser | |
6144 | * (parsing unit and 'checksum and crc' unit) | |
6145 | * these errors are legal (PU reads fixed length and CAC can cause | |
6146 | * read length error on truncated packets) | |
6147 | */ | |
6148 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
6149 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
6150 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
6151 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
6152 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
6153 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
6154 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
6155 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6156 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
6157 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
6158 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
6159 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
6160 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6161 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
6162 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
6163 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
6164 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
6165 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
6166 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 6167 | |
b343d002 YM |
6168 | val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
6169 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | | |
6170 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; | |
6171 | if (!CHIP_IS_E1x(bp)) | |
6172 | val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | | |
6173 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; | |
6174 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); | |
6175 | ||
a2fbb9ea ET |
6176 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
6177 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
6178 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 6179 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6180 | |
6181 | if (!CHIP_IS_E1x(bp)) | |
6182 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6183 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6184 | ||
a2fbb9ea ET |
6185 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6186 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6187 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6188 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6189 | } |
6190 | ||
81f75bbf EG |
6191 | static void bnx2x_reset_common(struct bnx2x *bp) |
6192 | { | |
619c5cb6 VZ |
6193 | u32 val = 0x1400; |
6194 | ||
81f75bbf EG |
6195 | /* reset_common */ |
6196 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6197 | 0xd3ffff7f); | |
619c5cb6 VZ |
6198 | |
6199 | if (CHIP_IS_E3(bp)) { | |
6200 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6201 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6202 | } | |
6203 | ||
6204 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6205 | } | |
6206 | ||
6207 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6208 | { | |
6209 | bp->dmae_ready = 0; | |
6210 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6211 | } |
6212 | ||
573f2035 EG |
6213 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6214 | { | |
6215 | u16 devctl; | |
6216 | int r_order, w_order; | |
6217 | ||
2a80eebc | 6218 | pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6219 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6220 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6221 | if (bp->mrrs == -1) | |
6222 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6223 | else { | |
6224 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6225 | r_order = bp->mrrs; | |
6226 | } | |
6227 | ||
6228 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6229 | } | |
fd4ef40d EG |
6230 | |
6231 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6232 | { | |
2145a920 | 6233 | int is_required; |
fd4ef40d | 6234 | u32 val; |
2145a920 | 6235 | int port; |
fd4ef40d | 6236 | |
2145a920 VZ |
6237 | if (BP_NOMCP(bp)) |
6238 | return; | |
6239 | ||
6240 | is_required = 0; | |
fd4ef40d EG |
6241 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6242 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6243 | ||
6244 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6245 | is_required = 1; | |
6246 | ||
6247 | /* | |
6248 | * The fan failure mechanism is usually related to the PHY type since | |
6249 | * the power consumption of the board is affected by the PHY. Currently, | |
6250 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6251 | */ | |
6252 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6253 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6254 | is_required |= |
d90d96ba YR |
6255 | bnx2x_fan_failure_det_req( |
6256 | bp, | |
6257 | bp->common.shmem_base, | |
a22f0788 | 6258 | bp->common.shmem2_base, |
d90d96ba | 6259 | port); |
fd4ef40d EG |
6260 | } |
6261 | ||
6262 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6263 | ||
6264 | if (is_required == 0) | |
6265 | return; | |
6266 | ||
6267 | /* Fan failure is indicated by SPIO 5 */ | |
d6d99a3f | 6268 | bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); |
fd4ef40d EG |
6269 | |
6270 | /* set to active low mode */ | |
6271 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
d6d99a3f | 6272 | val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6273 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6274 | ||
6275 | /* enable interrupt to signal the IGU */ | |
6276 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 6277 | val |= MISC_SPIO_SPIO5; |
fd4ef40d EG |
6278 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); |
6279 | } | |
6280 | ||
f2e0899f DK |
6281 | static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num) |
6282 | { | |
6283 | u32 offset = 0; | |
6284 | ||
6285 | if (CHIP_IS_E1(bp)) | |
6286 | return; | |
6287 | if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX)) | |
6288 | return; | |
6289 | ||
6290 | switch (BP_ABS_FUNC(bp)) { | |
6291 | case 0: | |
6292 | offset = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
6293 | break; | |
6294 | case 1: | |
6295 | offset = PXP2_REG_PGL_PRETEND_FUNC_F1; | |
6296 | break; | |
6297 | case 2: | |
6298 | offset = PXP2_REG_PGL_PRETEND_FUNC_F2; | |
6299 | break; | |
6300 | case 3: | |
6301 | offset = PXP2_REG_PGL_PRETEND_FUNC_F3; | |
6302 | break; | |
6303 | case 4: | |
6304 | offset = PXP2_REG_PGL_PRETEND_FUNC_F4; | |
6305 | break; | |
6306 | case 5: | |
6307 | offset = PXP2_REG_PGL_PRETEND_FUNC_F5; | |
6308 | break; | |
6309 | case 6: | |
6310 | offset = PXP2_REG_PGL_PRETEND_FUNC_F6; | |
6311 | break; | |
6312 | case 7: | |
6313 | offset = PXP2_REG_PGL_PRETEND_FUNC_F7; | |
6314 | break; | |
6315 | default: | |
6316 | return; | |
6317 | } | |
6318 | ||
6319 | REG_WR(bp, offset, pretend_func_num); | |
6320 | REG_RD(bp, offset); | |
6321 | DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); | |
6322 | } | |
6323 | ||
c9ee9206 | 6324 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6325 | { |
6326 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6327 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6328 | ||
6329 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6330 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6331 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6332 | } | |
6333 | ||
1191cb83 | 6334 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
619c5cb6 VZ |
6335 | { |
6336 | u32 shmem_base[2], shmem2_base[2]; | |
b884d95b YR |
6337 | /* Avoid common init in case MFW supports LFA */ |
6338 | if (SHMEM2_RD(bp, size) > | |
6339 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
6340 | return; | |
619c5cb6 VZ |
6341 | shmem_base[0] = bp->common.shmem_base; |
6342 | shmem2_base[0] = bp->common.shmem2_base; | |
6343 | if (!CHIP_IS_E1x(bp)) { | |
6344 | shmem_base[1] = | |
6345 | SHMEM2_RD(bp, other_shmem_base_addr); | |
6346 | shmem2_base[1] = | |
6347 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
6348 | } | |
6349 | bnx2x_acquire_phy_lock(bp); | |
6350 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
6351 | bp->common.chip_id); | |
6352 | bnx2x_release_phy_lock(bp); | |
6353 | } | |
6354 | ||
6355 | /** | |
6356 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
6357 | * | |
6358 | * @bp: driver handle | |
6359 | */ | |
6360 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 6361 | { |
619c5cb6 | 6362 | u32 val; |
a2fbb9ea | 6363 | |
51c1a580 | 6364 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 6365 | |
2031bd3a DK |
6366 | /* |
6367 | * take the UNDI lock to protect undi_unload flow from accessing | |
6368 | * registers while we're resetting the chip | |
6369 | */ | |
7a06a122 | 6370 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6371 | |
81f75bbf | 6372 | bnx2x_reset_common(bp); |
34f80b04 | 6373 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 6374 | |
619c5cb6 VZ |
6375 | val = 0xfffc; |
6376 | if (CHIP_IS_E3(bp)) { | |
6377 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6378 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6379 | } | |
6380 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
6381 | ||
7a06a122 | 6382 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6383 | |
619c5cb6 | 6384 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 6385 | |
619c5cb6 VZ |
6386 | if (!CHIP_IS_E1x(bp)) { |
6387 | u8 abs_func_id; | |
f2e0899f DK |
6388 | |
6389 | /** | |
6390 | * 4-port mode or 2-port mode we need to turn of master-enable | |
6391 | * for everyone, after that, turn it back on for self. | |
6392 | * so, we disregard multi-function or not, and always disable | |
6393 | * for all functions on the given path, this means 0,2,4,6 for | |
6394 | * path 0 and 1,3,5,7 for path 1 | |
6395 | */ | |
619c5cb6 VZ |
6396 | for (abs_func_id = BP_PATH(bp); |
6397 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
6398 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
6399 | REG_WR(bp, |
6400 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
6401 | 1); | |
6402 | continue; | |
6403 | } | |
6404 | ||
619c5cb6 | 6405 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
6406 | /* clear pf enable */ |
6407 | bnx2x_pf_disable(bp); | |
6408 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6409 | } | |
6410 | } | |
a2fbb9ea | 6411 | |
619c5cb6 | 6412 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
6413 | if (CHIP_IS_E1(bp)) { |
6414 | /* enable HW interrupt from PXP on USDM overflow | |
6415 | bit 16 on INT_MASK_0 */ | |
6416 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
6417 | } | |
a2fbb9ea | 6418 | |
619c5cb6 | 6419 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 6420 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
6421 | |
6422 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
6423 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
6424 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
6425 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
6426 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
6427 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
6428 | /* make sure this value is 0 */ |
6429 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
6430 | |
6431 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
6432 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
6433 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
6434 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
6435 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
6436 | #endif |
6437 | ||
523224a3 DK |
6438 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
6439 | ||
34f80b04 EG |
6440 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
6441 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 6442 | |
34f80b04 EG |
6443 | /* let the HW do it's magic ... */ |
6444 | msleep(100); | |
6445 | /* finish PXP init */ | |
6446 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
6447 | if (val != 1) { | |
6448 | BNX2X_ERR("PXP2 CFG failed\n"); | |
6449 | return -EBUSY; | |
6450 | } | |
6451 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
6452 | if (val != 1) { | |
6453 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
6454 | return -EBUSY; | |
6455 | } | |
a2fbb9ea | 6456 | |
f2e0899f DK |
6457 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
6458 | * have entries with value "0" and valid bit on. | |
6459 | * This needs to be done by the first PF that is loaded in a path | |
6460 | * (i.e. common phase) | |
6461 | */ | |
619c5cb6 VZ |
6462 | if (!CHIP_IS_E1x(bp)) { |
6463 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
6464 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
6465 | * This occurs when a different function (func2,3) is being marked | |
6466 | * as "scan-off". Real-life scenario for example: if a driver is being | |
6467 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
6468 | * the ilt, translate to a logical address and send a request to read/write. | |
6469 | * Since the ilt for the function that is down is not valid, this will cause | |
6470 | * a translation error which is unrecoverable. | |
6471 | * The Workaround is intended to make sure that when this happens nothing fatal | |
6472 | * will occur. The workaround: | |
6473 | * 1. First PF driver which loads on a path will: | |
6474 | * a. After taking the chip out of reset, by using pretend, | |
6475 | * it will write "0" to the following registers of | |
6476 | * the other vnics. | |
6477 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6478 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
6479 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
6480 | * And for itself it will write '1' to | |
6481 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
6482 | * dmae-operations (writing to pram for example.) | |
6483 | * note: can be done for only function 6,7 but cleaner this | |
6484 | * way. | |
6485 | * b. Write zero+valid to the entire ILT. | |
6486 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
6487 | * VNIC3 (of that port). The range allocated will be the | |
6488 | * entire ILT. This is needed to prevent ILT range error. | |
6489 | * 2. Any PF driver load flow: | |
6490 | * a. ILT update with the physical addresses of the allocated | |
6491 | * logical pages. | |
6492 | * b. Wait 20msec. - note that this timeout is needed to make | |
6493 | * sure there are no requests in one of the PXP internal | |
6494 | * queues with "old" ILT addresses. | |
6495 | * c. PF enable in the PGLC. | |
6496 | * d. Clear the was_error of the PF in the PGLC. (could have | |
6497 | * occured while driver was down) | |
6498 | * e. PF enable in the CFC (WEAK + STRONG) | |
6499 | * f. Timers scan enable | |
6500 | * 3. PF driver unload flow: | |
6501 | * a. Clear the Timers scan_en. | |
6502 | * b. Polling for scan_on=0 for that PF. | |
6503 | * c. Clear the PF enable bit in the PXP. | |
6504 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
6505 | * e. Write zero+valid to all ILT entries (The valid bit must | |
6506 | * stay set) | |
6507 | * f. If this is VNIC 3 of a port then also init | |
6508 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
6509 | * to the last enrty in the ILT. | |
6510 | * | |
6511 | * Notes: | |
6512 | * Currently the PF error in the PGLC is non recoverable. | |
6513 | * In the future the there will be a recovery routine for this error. | |
6514 | * Currently attention is masked. | |
6515 | * Having an MCP lock on the load/unload process does not guarantee that | |
6516 | * there is no Timer disable during Func6/7 enable. This is because the | |
6517 | * Timers scan is currently being cleared by the MCP on FLR. | |
6518 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
6519 | * there is error before clearing it. But the flow above is simpler and | |
6520 | * more general. | |
6521 | * All ILT entries are written by zero+valid and not just PF6/7 | |
6522 | * ILT entries since in the future the ILT entries allocation for | |
6523 | * PF-s might be dynamic. | |
6524 | */ | |
f2e0899f DK |
6525 | struct ilt_client_info ilt_cli; |
6526 | struct bnx2x_ilt ilt; | |
6527 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
6528 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
6529 | ||
b595076a | 6530 | /* initialize dummy TM client */ |
f2e0899f DK |
6531 | ilt_cli.start = 0; |
6532 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
6533 | ilt_cli.client_num = ILT_CLIENT_TM; | |
6534 | ||
6535 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
6536 | * Step 2: set the timers first/last ilt entry to point | |
6537 | * to the entire range to prevent ILT range error for 3rd/4th | |
619c5cb6 | 6538 | * vnic (this code assumes existance of the vnic) |
f2e0899f DK |
6539 | * |
6540 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
6541 | * with dummy TM client | |
6542 | * | |
6543 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
6544 | * and his brother are split registers | |
6545 | */ | |
6546 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
6547 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
6548 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6549 | ||
6550 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
6551 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
6552 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
6553 | } | |
6554 | ||
6555 | ||
34f80b04 EG |
6556 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
6557 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 6558 | |
619c5cb6 | 6559 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6560 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
6561 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 6562 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 6563 | |
619c5cb6 | 6564 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
6565 | |
6566 | /* let the HW do it's magic ... */ | |
6567 | do { | |
6568 | msleep(200); | |
6569 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
6570 | } while (factor-- && (val != 1)); | |
6571 | ||
6572 | if (val != 1) { | |
6573 | BNX2X_ERR("ATC_INIT failed\n"); | |
6574 | return -EBUSY; | |
6575 | } | |
6576 | } | |
6577 | ||
619c5cb6 | 6578 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 6579 | |
34f80b04 EG |
6580 | /* clean the DMAE memory */ |
6581 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
6582 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
6583 | ||
6584 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
6585 | ||
6586 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
6587 | ||
6588 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 6589 | |
619c5cb6 | 6590 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 6591 | |
34f80b04 EG |
6592 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
6593 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
6594 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
6595 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
6596 | ||
619c5cb6 | 6597 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 6598 | |
f85582f8 | 6599 | |
523224a3 DK |
6600 | /* QM queues pointers table */ |
6601 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
6602 | ||
34f80b04 EG |
6603 | /* soft reset pulse */ |
6604 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
6605 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 6606 | |
55c11941 MS |
6607 | if (CNIC_SUPPORT(bp)) |
6608 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); | |
a2fbb9ea | 6609 | |
619c5cb6 | 6610 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
523224a3 | 6611 | REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); |
619c5cb6 | 6612 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
6613 | /* enable hw interrupt from doorbell Q */ |
6614 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 6615 | |
619c5cb6 | 6616 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 6617 | |
619c5cb6 | 6618 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 6619 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 6620 | |
f2e0899f | 6621 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 6622 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 6623 | |
a3348722 BW |
6624 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
6625 | if (IS_MF_AFEX(bp)) { | |
6626 | /* configure that VNTag and VLAN headers must be | |
6627 | * received in afex mode | |
6628 | */ | |
6629 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
6630 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
6631 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
6632 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
6633 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
6634 | } else { | |
6635 | /* Bit-map indicating which L2 hdrs may appear | |
6636 | * after the basic Ethernet header | |
6637 | */ | |
6638 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
6639 | bp->path_has_ovlan ? 7 : 6); | |
6640 | } | |
6641 | } | |
a2fbb9ea | 6642 | |
619c5cb6 VZ |
6643 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
6644 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
6645 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
6646 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 6647 | |
619c5cb6 VZ |
6648 | if (!CHIP_IS_E1x(bp)) { |
6649 | /* reset VFC memories */ | |
6650 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6651 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6652 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6653 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6654 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6655 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6656 | |
619c5cb6 VZ |
6657 | msleep(20); |
6658 | } | |
a2fbb9ea | 6659 | |
619c5cb6 VZ |
6660 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6661 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6662 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6663 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6664 | |
34f80b04 EG |
6665 | /* sync semi rtc */ |
6666 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6667 | 0x80000000); | |
6668 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6669 | 0x80000000); | |
a2fbb9ea | 6670 | |
619c5cb6 VZ |
6671 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6672 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6673 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6674 | |
a3348722 BW |
6675 | if (!CHIP_IS_E1x(bp)) { |
6676 | if (IS_MF_AFEX(bp)) { | |
6677 | /* configure that VNTag and VLAN headers must be | |
6678 | * sent in afex mode | |
6679 | */ | |
6680 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
6681 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
6682 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
6683 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
6684 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
6685 | } else { | |
6686 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6687 | bp->path_has_ovlan ? 7 : 6); | |
6688 | } | |
6689 | } | |
f2e0899f | 6690 | |
34f80b04 | 6691 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6692 | |
619c5cb6 VZ |
6693 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6694 | ||
55c11941 MS |
6695 | if (CNIC_SUPPORT(bp)) { |
6696 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6697 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6698 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6699 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6700 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6701 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6702 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6703 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6704 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6705 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6706 | } | |
34f80b04 | 6707 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6708 | |
34f80b04 EG |
6709 | if (sizeof(union cdu_context) != 1024) |
6710 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
6711 | dev_alert(&bp->pdev->dev, |
6712 | "please adjust the size of cdu_context(%ld)\n", | |
6713 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 6714 | |
619c5cb6 | 6715 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
6716 | val = (4 << 24) + (0 << 12) + 1024; |
6717 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 6718 | |
619c5cb6 | 6719 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 6720 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
6721 | /* enable context validation interrupt from CFC */ |
6722 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
6723 | ||
6724 | /* set the thresholds to prevent CFC/CDU race */ | |
6725 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 6726 | |
619c5cb6 | 6727 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 6728 | |
619c5cb6 | 6729 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
6730 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
6731 | ||
619c5cb6 VZ |
6732 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
6733 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 6734 | |
34f80b04 EG |
6735 | /* Reset PCIE errors for debug */ |
6736 | REG_WR(bp, 0x2814, 0xffffffff); | |
6737 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 6738 | |
619c5cb6 | 6739 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6740 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
6741 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
6742 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
6743 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
6744 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
6745 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
6746 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
6747 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
6748 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
6749 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
6750 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
6751 | } | |
6752 | ||
619c5cb6 | 6753 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 6754 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
6755 | /* in E3 this done in per-port section */ |
6756 | if (!CHIP_IS_E3(bp)) | |
6757 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 6758 | } |
619c5cb6 VZ |
6759 | if (CHIP_IS_E1H(bp)) |
6760 | /* not applicable for E2 (and above ...) */ | |
6761 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
6762 | |
6763 | if (CHIP_REV_IS_SLOW(bp)) | |
6764 | msleep(200); | |
6765 | ||
6766 | /* finish CFC init */ | |
6767 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
6768 | if (val != 1) { | |
6769 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
6770 | return -EBUSY; | |
6771 | } | |
6772 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
6773 | if (val != 1) { | |
6774 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
6775 | return -EBUSY; | |
6776 | } | |
6777 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
6778 | if (val != 1) { | |
6779 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
6780 | return -EBUSY; | |
6781 | } | |
6782 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 6783 | |
f2e0899f DK |
6784 | if (CHIP_IS_E1(bp)) { |
6785 | /* read NIG statistic | |
6786 | to see if this is our first up since powerup */ | |
6787 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
6788 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 6789 | |
f2e0899f DK |
6790 | /* do internal memory self test */ |
6791 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
6792 | BNX2X_ERR("internal mem self test failed\n"); | |
6793 | return -EBUSY; | |
6794 | } | |
34f80b04 EG |
6795 | } |
6796 | ||
fd4ef40d EG |
6797 | bnx2x_setup_fan_failure_detection(bp); |
6798 | ||
34f80b04 EG |
6799 | /* clear PXP2 attentions */ |
6800 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 6801 | |
4a33bc03 | 6802 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 6803 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 6804 | |
6bbca910 | 6805 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
6806 | if (CHIP_IS_E1x(bp)) |
6807 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
6808 | } else |
6809 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
6810 | ||
34f80b04 EG |
6811 | return 0; |
6812 | } | |
a2fbb9ea | 6813 | |
619c5cb6 VZ |
6814 | /** |
6815 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
6816 | * | |
6817 | * @bp: driver handle | |
6818 | */ | |
6819 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
6820 | { | |
6821 | int rc = bnx2x_init_hw_common(bp); | |
6822 | ||
6823 | if (rc) | |
6824 | return rc; | |
6825 | ||
6826 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
6827 | if (!BP_NOMCP(bp)) | |
6828 | bnx2x__common_init_phy(bp); | |
6829 | ||
6830 | return 0; | |
6831 | } | |
6832 | ||
523224a3 | 6833 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
6834 | { |
6835 | int port = BP_PORT(bp); | |
619c5cb6 | 6836 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 6837 | u32 low, high; |
34f80b04 | 6838 | u32 val; |
a2fbb9ea | 6839 | |
619c5cb6 | 6840 | |
51c1a580 | 6841 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
6842 | |
6843 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 6844 | |
619c5cb6 VZ |
6845 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
6846 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
6847 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 6848 | |
f2e0899f DK |
6849 | /* Timers bug workaround: disables the pf_master bit in pglue at |
6850 | * common phase, we need to enable it here before any dmae access are | |
6851 | * attempted. Therefore we manually added the enable-master to the | |
6852 | * port phase (it also happens in the function phase) | |
6853 | */ | |
619c5cb6 | 6854 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6855 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
6856 | ||
619c5cb6 VZ |
6857 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6858 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6859 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
6860 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6861 | ||
6862 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6863 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6864 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6865 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 6866 | |
523224a3 DK |
6867 | /* QM cid (connection) count */ |
6868 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 6869 | |
55c11941 MS |
6870 | if (CNIC_SUPPORT(bp)) { |
6871 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
6872 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); | |
6873 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
6874 | } | |
cdaa7cb8 | 6875 | |
619c5cb6 | 6876 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f | 6877 | |
2b674047 DK |
6878 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
6879 | ||
f2e0899f | 6880 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { |
619c5cb6 VZ |
6881 | |
6882 | if (IS_MF(bp)) | |
6883 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
6884 | else if (bp->dev->mtu > 4096) { | |
6885 | if (bp->flags & ONE_PORT_FLAG) | |
6886 | low = 160; | |
6887 | else { | |
6888 | val = bp->dev->mtu; | |
6889 | /* (24*1024 + val*4)/256 */ | |
6890 | low = 96 + (val/64) + | |
6891 | ((val % 64) ? 1 : 0); | |
6892 | } | |
6893 | } else | |
6894 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
6895 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
6896 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
6897 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 6898 | } |
1c06328c | 6899 | |
619c5cb6 VZ |
6900 | if (CHIP_MODE_IS_4_PORT(bp)) |
6901 | REG_WR(bp, (BP_PORT(bp) ? | |
6902 | BRB1_REG_MAC_GUARANTIED_1 : | |
6903 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 6904 | |
ca00392c | 6905 | |
619c5cb6 | 6906 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
6907 | if (CHIP_IS_E3B0(bp)) { |
6908 | if (IS_MF_AFEX(bp)) { | |
6909 | /* configure headers for AFEX mode */ | |
6910 | REG_WR(bp, BP_PORT(bp) ? | |
6911 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6912 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
6913 | REG_WR(bp, BP_PORT(bp) ? | |
6914 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
6915 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
6916 | REG_WR(bp, BP_PORT(bp) ? | |
6917 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
6918 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
6919 | } else { | |
6920 | /* Ovlan exists only if we are in multi-function + | |
6921 | * switch-dependent mode, in switch-independent there | |
6922 | * is no ovlan headers | |
6923 | */ | |
6924 | REG_WR(bp, BP_PORT(bp) ? | |
6925 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
6926 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
6927 | (bp->path_has_ovlan ? 7 : 6)); | |
6928 | } | |
6929 | } | |
356e2385 | 6930 | |
619c5cb6 VZ |
6931 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
6932 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
6933 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
6934 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 6935 | |
619c5cb6 VZ |
6936 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
6937 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
6938 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
6939 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 6940 | |
619c5cb6 VZ |
6941 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
6942 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 6943 | |
619c5cb6 VZ |
6944 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
6945 | ||
6946 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
6947 | /* configure PBF to work without PAUSE mtu 9000 */ |
6948 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 6949 | |
f2e0899f DK |
6950 | /* update threshold */ |
6951 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
6952 | /* update init credit */ | |
6953 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 6954 | |
f2e0899f DK |
6955 | /* probe changes */ |
6956 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
6957 | udelay(50); | |
6958 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
6959 | } | |
a2fbb9ea | 6960 | |
55c11941 MS |
6961 | if (CNIC_SUPPORT(bp)) |
6962 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
6963 | ||
619c5cb6 VZ |
6964 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
6965 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
6966 | |
6967 | if (CHIP_IS_E1(bp)) { | |
6968 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
6969 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
6970 | } | |
619c5cb6 | 6971 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 6972 | |
619c5cb6 | 6973 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 6974 | |
619c5cb6 | 6975 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 EG |
6976 | /* init aeu_mask_attn_func_0/1: |
6977 | * - SF mode: bits 3-7 are masked. only bits 0-2 are in use | |
6978 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF | |
6979 | * bits 4-7 are used for "per vn group attention" */ | |
e4901dde VZ |
6980 | val = IS_MF(bp) ? 0xF7 : 0x7; |
6981 | /* Enable DCBX attention for all but E1 */ | |
6982 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
6983 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 6984 | |
619c5cb6 VZ |
6985 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
6986 | ||
6987 | if (!CHIP_IS_E1x(bp)) { | |
6988 | /* Bit-map indicating which L2 hdrs may appear after the | |
6989 | * basic Ethernet header | |
6990 | */ | |
a3348722 BW |
6991 | if (IS_MF_AFEX(bp)) |
6992 | REG_WR(bp, BP_PORT(bp) ? | |
6993 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6994 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
6995 | else | |
6996 | REG_WR(bp, BP_PORT(bp) ? | |
6997 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
6998 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
6999 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
7000 | |
7001 | if (CHIP_IS_E3(bp)) | |
7002 | REG_WR(bp, BP_PORT(bp) ? | |
7003 | NIG_REG_LLH1_MF_MODE : | |
7004 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
7005 | } | |
7006 | if (!CHIP_IS_E3(bp)) | |
7007 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 7008 | |
f2e0899f | 7009 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 7010 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 7011 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 7012 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 7013 | |
619c5cb6 | 7014 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7015 | val = 0; |
7016 | switch (bp->mf_mode) { | |
7017 | case MULTI_FUNCTION_SD: | |
7018 | val = 1; | |
7019 | break; | |
7020 | case MULTI_FUNCTION_SI: | |
a3348722 | 7021 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
7022 | val = 2; |
7023 | break; | |
7024 | } | |
7025 | ||
7026 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
7027 | NIG_REG_LLH0_CLS_TYPE), val); | |
7028 | } | |
1c06328c EG |
7029 | { |
7030 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
7031 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
7032 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
7033 | } | |
34f80b04 EG |
7034 | } |
7035 | ||
619c5cb6 VZ |
7036 | |
7037 | /* If SPIO5 is set to generate interrupts, enable it for this port */ | |
7038 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 7039 | if (val & MISC_SPIO_SPIO5) { |
4d295db0 EG |
7040 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
7041 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
7042 | val = REG_RD(bp, reg_addr); | |
f1410647 | 7043 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 7044 | REG_WR(bp, reg_addr, val); |
f1410647 | 7045 | } |
a2fbb9ea | 7046 | |
34f80b04 EG |
7047 | return 0; |
7048 | } | |
7049 | ||
34f80b04 EG |
7050 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
7051 | { | |
7052 | int reg; | |
32d68de1 | 7053 | u32 wb_write[2]; |
34f80b04 | 7054 | |
f2e0899f | 7055 | if (CHIP_IS_E1(bp)) |
34f80b04 | 7056 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
7057 | else |
7058 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 7059 | |
32d68de1 YM |
7060 | wb_write[0] = ONCHIP_ADDR1(addr); |
7061 | wb_write[1] = ONCHIP_ADDR2(addr); | |
7062 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
7063 | } |
7064 | ||
1191cb83 ED |
7065 | static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, |
7066 | u8 idu_sb_id, bool is_Pf) | |
7067 | { | |
7068 | u32 data, ctl, cnt = 100; | |
7069 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
7070 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
7071 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
7072 | u32 sb_bit = 1 << (idu_sb_id%32); | |
7073 | u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; | |
7074 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; | |
7075 | ||
7076 | /* Not supported in BC mode */ | |
7077 | if (CHIP_INT_MODE_IS_BC(bp)) | |
7078 | return; | |
7079 | ||
7080 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
7081 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
7082 | IGU_REGULAR_CLEANUP_SET | | |
7083 | IGU_REGULAR_BCLEANUP; | |
7084 | ||
7085 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
7086 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
7087 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
7088 | ||
7089 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7090 | data, igu_addr_data); | |
7091 | REG_WR(bp, igu_addr_data, data); | |
7092 | mmiowb(); | |
7093 | barrier(); | |
7094 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7095 | ctl, igu_addr_ctl); | |
7096 | REG_WR(bp, igu_addr_ctl, ctl); | |
7097 | mmiowb(); | |
7098 | barrier(); | |
7099 | ||
7100 | /* wait for clean up to finish */ | |
7101 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
7102 | msleep(20); | |
7103 | ||
7104 | ||
7105 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { | |
7106 | DP(NETIF_MSG_HW, | |
7107 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
7108 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
7109 | } | |
7110 | } | |
7111 | ||
7112 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) | |
f2e0899f | 7113 | { |
619c5cb6 | 7114 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
7115 | } |
7116 | ||
1191cb83 | 7117 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
f2e0899f DK |
7118 | { |
7119 | u32 i, base = FUNC_ILT_BASE(func); | |
7120 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
7121 | bnx2x_ilt_wr(bp, i, 0); | |
7122 | } | |
7123 | ||
55c11941 | 7124 | |
910cc727 | 7125 | static void bnx2x_init_searcher(struct bnx2x *bp) |
55c11941 MS |
7126 | { |
7127 | int port = BP_PORT(bp); | |
7128 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
7129 | /* T1 hash bits value determines the T1 number of entries */ | |
7130 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
7131 | } | |
7132 | ||
7133 | static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) | |
7134 | { | |
7135 | int rc; | |
7136 | struct bnx2x_func_state_params func_params = {NULL}; | |
7137 | struct bnx2x_func_switch_update_params *switch_update_params = | |
7138 | &func_params.params.switch_update; | |
7139 | ||
7140 | /* Prepare parameters for function state transitions */ | |
7141 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7142 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
7143 | ||
7144 | func_params.f_obj = &bp->func_obj; | |
7145 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
7146 | ||
7147 | /* Function parameters */ | |
7148 | switch_update_params->suspend = suspend; | |
7149 | ||
7150 | rc = bnx2x_func_state_change(bp, &func_params); | |
7151 | ||
7152 | return rc; | |
7153 | } | |
7154 | ||
910cc727 | 7155 | static int bnx2x_reset_nic_mode(struct bnx2x *bp) |
55c11941 MS |
7156 | { |
7157 | int rc, i, port = BP_PORT(bp); | |
7158 | int vlan_en = 0, mac_en[NUM_MACS]; | |
7159 | ||
7160 | ||
7161 | /* Close input from network */ | |
7162 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7163 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
7164 | } else { | |
7165 | vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7166 | NIG_REG_LLH0_FUNC_EN); | |
7167 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7168 | NIG_REG_LLH0_FUNC_EN, 0); | |
7169 | for (i = 0; i < NUM_MACS; i++) { | |
7170 | mac_en[i] = REG_RD(bp, port ? | |
7171 | (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7172 | 4 * i) : | |
7173 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + | |
7174 | 4 * i)); | |
7175 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7176 | 4 * i) : | |
7177 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); | |
7178 | } | |
7179 | } | |
7180 | ||
7181 | /* Close BMC to host */ | |
7182 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7183 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); | |
7184 | ||
7185 | /* Suspend Tx switching to the PF. Completion of this ramrod | |
7186 | * further guarantees that all the packets of that PF / child | |
7187 | * VFs in BRB were processed by the Parser, so it is safe to | |
7188 | * change the NIC_MODE register. | |
7189 | */ | |
7190 | rc = bnx2x_func_switch_update(bp, 1); | |
7191 | if (rc) { | |
7192 | BNX2X_ERR("Can't suspend tx-switching!\n"); | |
7193 | return rc; | |
7194 | } | |
7195 | ||
7196 | /* Change NIC_MODE register */ | |
7197 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7198 | ||
7199 | /* Open input from network */ | |
7200 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7201 | bnx2x_set_rx_filter(&bp->link_params, 1); | |
7202 | } else { | |
7203 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7204 | NIG_REG_LLH0_FUNC_EN, vlan_en); | |
7205 | for (i = 0; i < NUM_MACS; i++) { | |
7206 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7207 | 4 * i) : | |
7208 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), | |
7209 | mac_en[i]); | |
7210 | } | |
7211 | } | |
7212 | ||
7213 | /* Enable BMC to host */ | |
7214 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7215 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); | |
7216 | ||
7217 | /* Resume Tx switching to the PF */ | |
7218 | rc = bnx2x_func_switch_update(bp, 0); | |
7219 | if (rc) { | |
7220 | BNX2X_ERR("Can't resume tx-switching!\n"); | |
7221 | return rc; | |
7222 | } | |
7223 | ||
7224 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7225 | return 0; | |
7226 | } | |
7227 | ||
7228 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp) | |
7229 | { | |
7230 | int rc; | |
7231 | ||
7232 | bnx2x_ilt_init_op_cnic(bp, INITOP_SET); | |
7233 | ||
7234 | if (CONFIGURE_NIC_MODE(bp)) { | |
7235 | /* Configrue searcher as part of function hw init */ | |
7236 | bnx2x_init_searcher(bp); | |
7237 | ||
7238 | /* Reset NIC mode */ | |
7239 | rc = bnx2x_reset_nic_mode(bp); | |
7240 | if (rc) | |
7241 | BNX2X_ERR("Can't change NIC mode!\n"); | |
7242 | return rc; | |
7243 | } | |
7244 | ||
7245 | return 0; | |
7246 | } | |
7247 | ||
523224a3 | 7248 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
7249 | { |
7250 | int port = BP_PORT(bp); | |
7251 | int func = BP_FUNC(bp); | |
619c5cb6 | 7252 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
7253 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
7254 | u16 cdu_ilt_start; | |
8badd27a | 7255 | u32 addr, val; |
f4a66897 | 7256 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 7257 | int i, main_mem_width, rc; |
34f80b04 | 7258 | |
51c1a580 | 7259 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 7260 | |
619c5cb6 | 7261 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
7262 | if (!CHIP_IS_E1x(bp)) { |
7263 | rc = bnx2x_pf_flr_clnup(bp); | |
7264 | if (rc) | |
7265 | return rc; | |
7266 | } | |
619c5cb6 | 7267 | |
8badd27a | 7268 | /* set MSI reconfigure capability */ |
f2e0899f DK |
7269 | if (bp->common.int_block == INT_BLOCK_HC) { |
7270 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
7271 | val = REG_RD(bp, addr); | |
7272 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
7273 | REG_WR(bp, addr, val); | |
7274 | } | |
8badd27a | 7275 | |
619c5cb6 VZ |
7276 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
7277 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
7278 | ||
523224a3 DK |
7279 | ilt = BP_ILT(bp); |
7280 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 7281 | |
523224a3 | 7282 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
a052997e | 7283 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
523224a3 | 7284 | ilt->lines[cdu_ilt_start + i].page_mapping = |
a052997e MS |
7285 | bp->context[i].cxt_mapping; |
7286 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; | |
37b091ba | 7287 | } |
523224a3 | 7288 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 7289 | |
55c11941 MS |
7290 | if (!CONFIGURE_NIC_MODE(bp)) { |
7291 | bnx2x_init_searcher(bp); | |
7292 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7293 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7294 | } else { | |
7295 | /* Set NIC mode */ | |
7296 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
7297 | DP(NETIF_MSG_IFUP, "NIC MODE configrued\n"); | |
37b091ba | 7298 | |
55c11941 | 7299 | } |
37b091ba | 7300 | |
619c5cb6 | 7301 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7302 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
7303 | ||
7304 | /* Turn on a single ISR mode in IGU if driver is going to use | |
7305 | * INT#x or MSI | |
7306 | */ | |
7307 | if (!(bp->flags & USING_MSIX_FLAG)) | |
7308 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
7309 | /* | |
7310 | * Timers workaround bug: function init part. | |
7311 | * Need to wait 20msec after initializing ILT, | |
7312 | * needed to make sure there are no requests in | |
7313 | * one of the PXP internal queues with "old" ILT addresses | |
7314 | */ | |
7315 | msleep(20); | |
7316 | /* | |
7317 | * Master enable - Due to WB DMAE writes performed before this | |
7318 | * register is re-initialized as part of the regular function | |
7319 | * init | |
7320 | */ | |
7321 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
7322 | /* Enable the function in IGU */ | |
7323 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
7324 | } | |
7325 | ||
523224a3 | 7326 | bp->dmae_ready = 1; |
34f80b04 | 7327 | |
619c5cb6 | 7328 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 7329 | |
619c5cb6 | 7330 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7331 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
7332 | ||
619c5cb6 VZ |
7333 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7334 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7335 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
7336 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7337 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
7338 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7339 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7340 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7341 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
7342 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
7343 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7344 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7345 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
7346 | ||
7347 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7348 | REG_WR(bp, QM_REG_PF_EN, 1); |
7349 | ||
619c5cb6 VZ |
7350 | if (!CHIP_IS_E1x(bp)) { |
7351 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7352 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7353 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7354 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7355 | } | |
7356 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7357 | ||
7358 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7359 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
7360 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); | |
7361 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
7362 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
7363 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7364 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7365 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
7366 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
7367 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
7368 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
7369 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7370 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
7371 | ||
619c5cb6 | 7372 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 7373 | |
619c5cb6 | 7374 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 7375 | |
619c5cb6 | 7376 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7377 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
7378 | ||
fb3bff17 | 7379 | if (IS_MF(bp)) { |
34f80b04 | 7380 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 7381 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
7382 | } |
7383 | ||
619c5cb6 | 7384 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 7385 | |
34f80b04 | 7386 | /* HC init per function */ |
f2e0899f DK |
7387 | if (bp->common.int_block == INT_BLOCK_HC) { |
7388 | if (CHIP_IS_E1H(bp)) { | |
7389 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
7390 | ||
7391 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7392 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7393 | } | |
619c5cb6 | 7394 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
7395 | |
7396 | } else { | |
7397 | int num_segs, sb_idx, prod_offset; | |
7398 | ||
34f80b04 EG |
7399 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
7400 | ||
619c5cb6 | 7401 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7402 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
7403 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7404 | } | |
7405 | ||
619c5cb6 | 7406 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7407 | |
619c5cb6 | 7408 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7409 | int dsb_idx = 0; |
7410 | /** | |
7411 | * Producer memory: | |
7412 | * E2 mode: address 0-135 match to the mapping memory; | |
7413 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
7414 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
7415 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
7416 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
7417 | * 144-147 reserved. | |
7418 | * | |
7419 | * E1.5 mode - In backward compatible mode; | |
7420 | * for non default SB; each even line in the memory | |
7421 | * holds the U producer and each odd line hold | |
7422 | * the C producer. The first 128 producers are for | |
7423 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
7424 | * producers are for the DSB for each PF. | |
7425 | * Each PF has five segments: (the order inside each | |
7426 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
7427 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
7428 | * 144-147 attn prods; | |
7429 | */ | |
7430 | /* non-default-status-blocks */ | |
7431 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7432 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
7433 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
7434 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
7435 | num_segs; | |
7436 | ||
7437 | for (i = 0; i < num_segs; i++) { | |
7438 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7439 | (prod_offset + i) * 4; | |
7440 | REG_WR(bp, addr, 0); | |
7441 | } | |
7442 | /* send consumer update with value 0 */ | |
7443 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
7444 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7445 | bnx2x_igu_clear_sb(bp, | |
7446 | bp->igu_base_sb + sb_idx); | |
7447 | } | |
7448 | ||
7449 | /* default-status-blocks */ | |
7450 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7451 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
7452 | ||
7453 | if (CHIP_MODE_IS_4_PORT(bp)) | |
7454 | dsb_idx = BP_FUNC(bp); | |
7455 | else | |
3395a033 | 7456 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
7457 | |
7458 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
7459 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
7460 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
7461 | ||
3395a033 DK |
7462 | /* |
7463 | * igu prods come in chunks of E1HVN_MAX (4) - | |
7464 | * does not matters what is the current chip mode | |
7465 | */ | |
f2e0899f DK |
7466 | for (i = 0; i < (num_segs * E1HVN_MAX); |
7467 | i += E1HVN_MAX) { | |
7468 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7469 | (prod_offset + i)*4; | |
7470 | REG_WR(bp, addr, 0); | |
7471 | } | |
7472 | /* send consumer update with 0 */ | |
7473 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
7474 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7475 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7476 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7477 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
7478 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7479 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
7480 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7481 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
7482 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7483 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7484 | } else { | |
7485 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7486 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7487 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7488 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7489 | } | |
7490 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
7491 | ||
7492 | /* !!! these should become driver const once | |
7493 | rf-tool supports split-68 const */ | |
7494 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
7495 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
7496 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
7497 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
7498 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
7499 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
7500 | } | |
34f80b04 | 7501 | } |
34f80b04 | 7502 | |
c14423fe | 7503 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
7504 | REG_WR(bp, 0x2114, 0xffffffff); |
7505 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 7506 | |
f4a66897 VZ |
7507 | if (CHIP_IS_E1x(bp)) { |
7508 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
7509 | main_mem_base = HC_REG_MAIN_MEMORY + | |
7510 | BP_PORT(bp) * (main_mem_size * 4); | |
7511 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
7512 | main_mem_width = 8; | |
7513 | ||
7514 | val = REG_RD(bp, main_mem_prty_clr); | |
7515 | if (val) | |
51c1a580 MS |
7516 | DP(NETIF_MSG_HW, |
7517 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
7518 | val); | |
f4a66897 VZ |
7519 | |
7520 | /* Clear "false" parity errors in MSI-X table */ | |
7521 | for (i = main_mem_base; | |
7522 | i < main_mem_base + main_mem_size * 4; | |
7523 | i += main_mem_width) { | |
7524 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
7525 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
7526 | i, main_mem_width / 4); | |
7527 | } | |
7528 | /* Clear HC parity attention */ | |
7529 | REG_RD(bp, main_mem_prty_clr); | |
7530 | } | |
7531 | ||
619c5cb6 VZ |
7532 | #ifdef BNX2X_STOP_ON_ERROR |
7533 | /* Enable STORMs SP logging */ | |
7534 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
7535 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7536 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
7537 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7538 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7539 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7540 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
7541 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7542 | #endif | |
7543 | ||
b7737c9b | 7544 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 7545 | |
34f80b04 EG |
7546 | return 0; |
7547 | } | |
7548 | ||
a2fbb9ea | 7549 | |
55c11941 MS |
7550 | void bnx2x_free_mem_cnic(struct bnx2x *bp) |
7551 | { | |
7552 | bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); | |
7553 | ||
7554 | if (!CHIP_IS_E1x(bp)) | |
7555 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, | |
7556 | sizeof(struct host_hc_status_block_e2)); | |
7557 | else | |
7558 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
7559 | sizeof(struct host_hc_status_block_e1x)); | |
7560 | ||
7561 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); | |
7562 | } | |
7563 | ||
9f6c9258 | 7564 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 7565 | { |
a052997e MS |
7566 | int i; |
7567 | ||
a2fbb9ea | 7568 | /* fastpath */ |
b3b83c3f | 7569 | bnx2x_free_fp_mem(bp); |
a2fbb9ea ET |
7570 | /* end of fastpath */ |
7571 | ||
7572 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
523224a3 | 7573 | sizeof(struct host_sp_status_block)); |
a2fbb9ea | 7574 | |
619c5cb6 VZ |
7575 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
7576 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7577 | ||
a2fbb9ea | 7578 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 7579 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 7580 | |
a052997e MS |
7581 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
7582 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, | |
7583 | bp->context[i].size); | |
523224a3 DK |
7584 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
7585 | ||
7586 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 7587 | |
7a9b2557 | 7588 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 7589 | |
523224a3 DK |
7590 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
7591 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
619c5cb6 VZ |
7592 | } |
7593 | ||
1191cb83 | 7594 | static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp) |
619c5cb6 VZ |
7595 | { |
7596 | int num_groups; | |
50f0a562 | 7597 | int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1; |
619c5cb6 | 7598 | |
50f0a562 BW |
7599 | /* number of queues for statistics is number of eth queues + FCoE */ |
7600 | u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats; | |
619c5cb6 VZ |
7601 | |
7602 | /* Total number of FW statistics requests = | |
50f0a562 BW |
7603 | * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats + |
7604 | * num of queues | |
7605 | */ | |
7606 | bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats; | |
523224a3 | 7607 | |
619c5cb6 VZ |
7608 | |
7609 | /* Request is built from stats_query_header and an array of | |
7610 | * stats_query_cmd_group each of which contains | |
7611 | * STATS_QUERY_CMD_COUNT rules. The real number or requests is | |
7612 | * configured in the stats_query_header. | |
7613 | */ | |
50f0a562 BW |
7614 | num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) + |
7615 | (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0); | |
619c5cb6 VZ |
7616 | |
7617 | bp->fw_stats_req_sz = sizeof(struct stats_query_header) + | |
7618 | num_groups * sizeof(struct stats_query_cmd_group); | |
7619 | ||
7620 | /* Data for statistics requests + stats_conter | |
7621 | * | |
7622 | * stats_counter holds per-STORM counters that are incremented | |
7623 | * when STORM has finished with the current request. | |
50f0a562 BW |
7624 | * |
7625 | * memory for FCoE offloaded statistics are counted anyway, | |
7626 | * even if they will not be sent. | |
619c5cb6 VZ |
7627 | */ |
7628 | bp->fw_stats_data_sz = sizeof(struct per_port_stats) + | |
7629 | sizeof(struct per_pf_stats) + | |
50f0a562 | 7630 | sizeof(struct fcoe_statistics_params) + |
619c5cb6 VZ |
7631 | sizeof(struct per_queue_stats) * num_queue_stats + |
7632 | sizeof(struct stats_counter); | |
7633 | ||
7634 | BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping, | |
7635 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7636 | ||
7637 | /* Set shortcuts */ | |
7638 | bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats; | |
7639 | bp->fw_stats_req_mapping = bp->fw_stats_mapping; | |
7640 | ||
7641 | bp->fw_stats_data = (struct bnx2x_fw_stats_data *) | |
7642 | ((u8 *)bp->fw_stats + bp->fw_stats_req_sz); | |
7643 | ||
7644 | bp->fw_stats_data_mapping = bp->fw_stats_mapping + | |
7645 | bp->fw_stats_req_sz; | |
7646 | return 0; | |
7647 | ||
7648 | alloc_mem_err: | |
7649 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, | |
7650 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
51c1a580 | 7651 | BNX2X_ERR("Can't allocate memory\n"); |
619c5cb6 | 7652 | return -ENOMEM; |
a2fbb9ea ET |
7653 | } |
7654 | ||
55c11941 | 7655 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp) |
a2fbb9ea | 7656 | { |
619c5cb6 VZ |
7657 | if (!CHIP_IS_E1x(bp)) |
7658 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
7659 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
7660 | sizeof(struct host_hc_status_block_e2)); | |
7661 | else | |
55c11941 MS |
7662 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, |
7663 | &bp->cnic_sb_mapping, | |
7664 | sizeof(struct | |
7665 | host_hc_status_block_e1x)); | |
8badd27a | 7666 | |
55c11941 MS |
7667 | if (CONFIGURE_NIC_MODE(bp)) |
7668 | /* allocate searcher T2 table, as it wan't allocated before */ | |
7669 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
7670 | ||
7671 | /* write address to which L5 should insert its values */ | |
7672 | bp->cnic_eth_dev.addr_drv_info_to_mcp = | |
7673 | &bp->slowpath->drv_info_to_mcp; | |
7674 | ||
7675 | if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) | |
7676 | goto alloc_mem_err; | |
7677 | ||
7678 | return 0; | |
7679 | ||
7680 | alloc_mem_err: | |
7681 | bnx2x_free_mem_cnic(bp); | |
7682 | BNX2X_ERR("Can't allocate memory\n"); | |
7683 | return -ENOMEM; | |
7684 | } | |
7685 | ||
7686 | int bnx2x_alloc_mem(struct bnx2x *bp) | |
7687 | { | |
7688 | int i, allocated, context_size; | |
a2fbb9ea | 7689 | |
55c11941 MS |
7690 | if (!CONFIGURE_NIC_MODE(bp)) |
7691 | /* allocate searcher T2 table */ | |
7692 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
8badd27a | 7693 | |
523224a3 DK |
7694 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
7695 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 7696 | |
523224a3 DK |
7697 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
7698 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 7699 | |
619c5cb6 VZ |
7700 | /* Allocated memory for FW statistics */ |
7701 | if (bnx2x_alloc_fw_stats_mem(bp)) | |
7702 | goto alloc_mem_err; | |
7703 | ||
a052997e MS |
7704 | /* Allocate memory for CDU context: |
7705 | * This memory is allocated separately and not in the generic ILT | |
7706 | * functions because CDU differs in few aspects: | |
7707 | * 1. There are multiple entities allocating memory for context - | |
7708 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls | |
7709 | * its own ILT lines. | |
7710 | * 2. Since CDU page-size is not a single 4KB page (which is the case | |
7711 | * for the other ILT clients), to be efficient we want to support | |
7712 | * allocation of sub-page-size in the last entry. | |
7713 | * 3. Context pointers are used by the driver to pass to FW / update | |
7714 | * the context (for the other ILT clients the pointers are used just to | |
7715 | * free the memory during unload). | |
7716 | */ | |
7717 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); | |
65abd74d | 7718 | |
a052997e MS |
7719 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
7720 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, | |
7721 | (context_size - allocated)); | |
7722 | BNX2X_PCI_ALLOC(bp->context[i].vcxt, | |
7723 | &bp->context[i].cxt_mapping, | |
7724 | bp->context[i].size); | |
7725 | allocated += bp->context[i].size; | |
7726 | } | |
523224a3 | 7727 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 7728 | |
523224a3 DK |
7729 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
7730 | goto alloc_mem_err; | |
65abd74d | 7731 | |
9f6c9258 DK |
7732 | /* Slow path ring */ |
7733 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 7734 | |
523224a3 DK |
7735 | /* EQ */ |
7736 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
7737 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 7738 | |
b3b83c3f DK |
7739 | |
7740 | /* fastpath */ | |
7741 | /* need to be done at the end, since it's self adjusting to amount | |
7742 | * of memory available for RSS queues | |
7743 | */ | |
7744 | if (bnx2x_alloc_fp_mem(bp)) | |
7745 | goto alloc_mem_err; | |
9f6c9258 | 7746 | return 0; |
e1510706 | 7747 | |
9f6c9258 DK |
7748 | alloc_mem_err: |
7749 | bnx2x_free_mem(bp); | |
51c1a580 | 7750 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 7751 | return -ENOMEM; |
65abd74d YG |
7752 | } |
7753 | ||
a2fbb9ea ET |
7754 | /* |
7755 | * Init service functions | |
7756 | */ | |
a2fbb9ea | 7757 | |
619c5cb6 VZ |
7758 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
7759 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
7760 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 7761 | { |
619c5cb6 VZ |
7762 | int rc; |
7763 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 7764 | |
619c5cb6 | 7765 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 7766 | |
619c5cb6 VZ |
7767 | /* Fill general parameters */ |
7768 | ramrod_param.vlan_mac_obj = obj; | |
7769 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 7770 | |
619c5cb6 VZ |
7771 | /* Fill a user request section if needed */ |
7772 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
7773 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 7774 | |
619c5cb6 | 7775 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 7776 | |
619c5cb6 VZ |
7777 | /* Set the command: ADD or DEL */ |
7778 | if (set) | |
7779 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
7780 | else | |
7781 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
7782 | } |
7783 | ||
619c5cb6 | 7784 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7b5342d9 YM |
7785 | |
7786 | if (rc == -EEXIST) { | |
7787 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
7788 | /* do not treat adding same MAC as error */ | |
7789 | rc = 0; | |
7790 | } else if (rc < 0) | |
619c5cb6 | 7791 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); |
7b5342d9 | 7792 | |
619c5cb6 | 7793 | return rc; |
a2fbb9ea ET |
7794 | } |
7795 | ||
619c5cb6 VZ |
7796 | int bnx2x_del_all_macs(struct bnx2x *bp, |
7797 | struct bnx2x_vlan_mac_obj *mac_obj, | |
7798 | int mac_type, bool wait_for_comp) | |
e665bfda | 7799 | { |
619c5cb6 VZ |
7800 | int rc; |
7801 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 7802 | |
619c5cb6 VZ |
7803 | /* Wait for completion of requested */ |
7804 | if (wait_for_comp) | |
7805 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 7806 | |
619c5cb6 VZ |
7807 | /* Set the mac type of addresses we want to clear */ |
7808 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 7809 | |
619c5cb6 VZ |
7810 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
7811 | if (rc < 0) | |
7812 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 7813 | |
619c5cb6 | 7814 | return rc; |
0793f83f DK |
7815 | } |
7816 | ||
619c5cb6 | 7817 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 7818 | { |
619c5cb6 | 7819 | unsigned long ramrod_flags = 0; |
e665bfda | 7820 | |
a3348722 BW |
7821 | if (is_zero_ether_addr(bp->dev->dev_addr) && |
7822 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { | |
51c1a580 MS |
7823 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, |
7824 | "Ignoring Zero MAC for STORAGE SD mode\n"); | |
614c76df DK |
7825 | return 0; |
7826 | } | |
614c76df | 7827 | |
619c5cb6 | 7828 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
0793f83f | 7829 | |
619c5cb6 VZ |
7830 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
7831 | /* Eth MAC is set on RSS leading client (fp[0]) */ | |
15192a8c BW |
7832 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj, |
7833 | set, BNX2X_ETH_MAC, &ramrod_flags); | |
e665bfda | 7834 | } |
6e30dd4e | 7835 | |
619c5cb6 | 7836 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 7837 | { |
619c5cb6 | 7838 | return bnx2x_setup_queue(bp, &bp->fp[0], 1); |
993ac7b5 | 7839 | } |
a2fbb9ea | 7840 | |
d6214d7a | 7841 | /** |
e8920674 | 7842 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 7843 | * |
e8920674 | 7844 | * @bp: driver handle |
d6214d7a | 7845 | * |
e8920674 | 7846 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 7847 | */ |
1ab4434c | 7848 | int bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 7849 | { |
1ab4434c AE |
7850 | int rc = 0; |
7851 | ||
7852 | if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) | |
7853 | return -EINVAL; | |
7854 | ||
9ee3d37b | 7855 | switch (int_mode) { |
1ab4434c AE |
7856 | case BNX2X_INT_MODE_MSIX: |
7857 | /* attempt to enable msix */ | |
7858 | rc = bnx2x_enable_msix(bp); | |
7859 | ||
7860 | /* msix attained */ | |
7861 | if (!rc) | |
7862 | return 0; | |
7863 | ||
7864 | /* vfs use only msix */ | |
7865 | if (rc && IS_VF(bp)) | |
7866 | return rc; | |
7867 | ||
7868 | /* failed to enable multiple MSI-X */ | |
7869 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
7870 | bp->num_queues, | |
7871 | 1 + bp->num_cnic_queues); | |
7872 | ||
7873 | /* falling through... */ | |
7874 | case BNX2X_INT_MODE_MSI: | |
d6214d7a | 7875 | bnx2x_enable_msi(bp); |
1ab4434c | 7876 | |
d6214d7a | 7877 | /* falling through... */ |
1ab4434c | 7878 | case BNX2X_INT_MODE_INTX: |
55c11941 MS |
7879 | bp->num_ethernet_queues = 1; |
7880 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
51c1a580 | 7881 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 7882 | break; |
d6214d7a | 7883 | default: |
1ab4434c AE |
7884 | BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); |
7885 | return -EINVAL; | |
9f6c9258 | 7886 | } |
1ab4434c | 7887 | return 0; |
a2fbb9ea ET |
7888 | } |
7889 | ||
1ab4434c | 7890 | /* must be called prior to any HW initializations */ |
c2bff63f DK |
7891 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) |
7892 | { | |
7893 | return L2_ILT_LINES(bp); | |
7894 | } | |
7895 | ||
523224a3 DK |
7896 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
7897 | { | |
7898 | struct ilt_client_info *ilt_client; | |
7899 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
7900 | u16 line = 0; | |
7901 | ||
7902 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
7903 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
7904 | ||
7905 | /* CDU */ | |
7906 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
7907 | ilt_client->client_num = ILT_CLIENT_CDU; | |
7908 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
7909 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
7910 | ilt_client->start = line; | |
619c5cb6 | 7911 | line += bnx2x_cid_ilt_lines(bp); |
55c11941 MS |
7912 | |
7913 | if (CNIC_SUPPORT(bp)) | |
7914 | line += CNIC_ILT_LINES; | |
523224a3 DK |
7915 | ilt_client->end = line - 1; |
7916 | ||
51c1a580 | 7917 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
7918 | ilt_client->start, |
7919 | ilt_client->end, | |
7920 | ilt_client->page_size, | |
7921 | ilt_client->flags, | |
7922 | ilog2(ilt_client->page_size >> 12)); | |
7923 | ||
7924 | /* QM */ | |
7925 | if (QM_INIT(bp->qm_cid_count)) { | |
7926 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
7927 | ilt_client->client_num = ILT_CLIENT_QM; | |
7928 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
7929 | ilt_client->flags = 0; | |
7930 | ilt_client->start = line; | |
7931 | ||
7932 | /* 4 bytes for each cid */ | |
7933 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
7934 | QM_ILT_PAGE_SZ); | |
7935 | ||
7936 | ilt_client->end = line - 1; | |
7937 | ||
51c1a580 MS |
7938 | DP(NETIF_MSG_IFUP, |
7939 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7940 | ilt_client->start, |
7941 | ilt_client->end, | |
7942 | ilt_client->page_size, | |
7943 | ilt_client->flags, | |
7944 | ilog2(ilt_client->page_size >> 12)); | |
7945 | ||
7946 | } | |
523224a3 | 7947 | |
55c11941 MS |
7948 | if (CNIC_SUPPORT(bp)) { |
7949 | /* SRC */ | |
7950 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
7951 | ilt_client->client_num = ILT_CLIENT_SRC; | |
7952 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
7953 | ilt_client->flags = 0; | |
7954 | ilt_client->start = line; | |
7955 | line += SRC_ILT_LINES; | |
7956 | ilt_client->end = line - 1; | |
523224a3 | 7957 | |
55c11941 MS |
7958 | DP(NETIF_MSG_IFUP, |
7959 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
7960 | ilt_client->start, | |
7961 | ilt_client->end, | |
7962 | ilt_client->page_size, | |
7963 | ilt_client->flags, | |
7964 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 7965 | |
55c11941 MS |
7966 | /* TM */ |
7967 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
7968 | ilt_client->client_num = ILT_CLIENT_TM; | |
7969 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
7970 | ilt_client->flags = 0; | |
7971 | ilt_client->start = line; | |
7972 | line += TM_ILT_LINES; | |
7973 | ilt_client->end = line - 1; | |
523224a3 | 7974 | |
55c11941 MS |
7975 | DP(NETIF_MSG_IFUP, |
7976 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
7977 | ilt_client->start, | |
7978 | ilt_client->end, | |
7979 | ilt_client->page_size, | |
7980 | ilt_client->flags, | |
7981 | ilog2(ilt_client->page_size >> 12)); | |
7982 | } | |
9f6c9258 | 7983 | |
619c5cb6 | 7984 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 7985 | } |
f85582f8 | 7986 | |
619c5cb6 VZ |
7987 | /** |
7988 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
7989 | * | |
7990 | * @bp: driver handle | |
7991 | * @fp: pointer to fastpath | |
7992 | * @init_params: pointer to parameters structure | |
7993 | * | |
7994 | * parameters configured: | |
7995 | * - HC configuration | |
7996 | * - Queue's CDU context | |
7997 | */ | |
1191cb83 | 7998 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
619c5cb6 | 7999 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
a2fbb9ea | 8000 | { |
6383c0b3 AE |
8001 | |
8002 | u8 cos; | |
a052997e MS |
8003 | int cxt_index, cxt_offset; |
8004 | ||
619c5cb6 VZ |
8005 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
8006 | if (!IS_FCOE_FP(fp)) { | |
8007 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
8008 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
8009 | ||
8010 | /* If HC is supporterd, enable host coalescing in the transition | |
8011 | * to INIT state. | |
8012 | */ | |
8013 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
8014 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
8015 | ||
8016 | /* HC rate */ | |
8017 | init_params->rx.hc_rate = bp->rx_ticks ? | |
8018 | (1000000 / bp->rx_ticks) : 0; | |
8019 | init_params->tx.hc_rate = bp->tx_ticks ? | |
8020 | (1000000 / bp->tx_ticks) : 0; | |
8021 | ||
8022 | /* FW SB ID */ | |
8023 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
8024 | fp->fw_sb_id; | |
8025 | ||
8026 | /* | |
8027 | * CQ index among the SB indices: FCoE clients uses the default | |
8028 | * SB, therefore it's different. | |
8029 | */ | |
6383c0b3 AE |
8030 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
8031 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
8032 | } |
8033 | ||
6383c0b3 AE |
8034 | /* set maximum number of COSs supported by this queue */ |
8035 | init_params->max_cos = fp->max_cos; | |
8036 | ||
51c1a580 | 8037 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
8038 | fp->index, init_params->max_cos); |
8039 | ||
8040 | /* set the context pointers queue object */ | |
a052997e | 8041 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
65565884 MS |
8042 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
8043 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * | |
a052997e | 8044 | ILT_PAGE_CIDS); |
6383c0b3 | 8045 | init_params->cxts[cos] = |
a052997e MS |
8046 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
8047 | } | |
619c5cb6 VZ |
8048 | } |
8049 | ||
910cc727 | 8050 | static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
6383c0b3 AE |
8051 | struct bnx2x_queue_state_params *q_params, |
8052 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
8053 | int tx_index, bool leading) | |
8054 | { | |
8055 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
8056 | ||
8057 | /* Set the command */ | |
8058 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
8059 | ||
8060 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
8061 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
8062 | ||
8063 | /* choose the index of the cid to send the slow path on */ | |
8064 | tx_only_params->cid_index = tx_index; | |
8065 | ||
8066 | /* Set general TX_ONLY_SETUP parameters */ | |
8067 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
8068 | ||
8069 | /* Set Tx TX_ONLY_SETUP parameters */ | |
8070 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
8071 | ||
51c1a580 MS |
8072 | DP(NETIF_MSG_IFUP, |
8073 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
8074 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
8075 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
8076 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
8077 | ||
8078 | /* send the ramrod */ | |
8079 | return bnx2x_queue_state_change(bp, q_params); | |
8080 | } | |
8081 | ||
8082 | ||
619c5cb6 VZ |
8083 | /** |
8084 | * bnx2x_setup_queue - setup queue | |
8085 | * | |
8086 | * @bp: driver handle | |
8087 | * @fp: pointer to fastpath | |
8088 | * @leading: is leading | |
8089 | * | |
8090 | * This function performs 2 steps in a Queue state machine | |
8091 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
8092 | */ | |
8093 | ||
8094 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
8095 | bool leading) | |
8096 | { | |
3b603066 | 8097 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
8098 | struct bnx2x_queue_setup_params *setup_params = |
8099 | &q_params.params.setup; | |
6383c0b3 AE |
8100 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
8101 | &q_params.params.tx_only; | |
a2fbb9ea | 8102 | int rc; |
6383c0b3 AE |
8103 | u8 tx_index; |
8104 | ||
51c1a580 | 8105 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 8106 | |
ec6ba945 VZ |
8107 | /* reset IGU state skip FCoE L2 queue */ |
8108 | if (!IS_FCOE_FP(fp)) | |
8109 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 8110 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 8111 | |
15192a8c | 8112 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8113 | /* We want to wait for completion in this context */ |
8114 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8115 | |
619c5cb6 VZ |
8116 | /* Prepare the INIT parameters */ |
8117 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 8118 | |
619c5cb6 VZ |
8119 | /* Set the command */ |
8120 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
8121 | ||
8122 | /* Change the state to INIT */ | |
8123 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8124 | if (rc) { | |
6383c0b3 | 8125 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
8126 | return rc; |
8127 | } | |
ec6ba945 | 8128 | |
51c1a580 | 8129 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 AE |
8130 | |
8131 | ||
619c5cb6 VZ |
8132 | /* Now move the Queue to the SETUP state... */ |
8133 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 8134 | |
619c5cb6 VZ |
8135 | /* Set QUEUE flags */ |
8136 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 8137 | |
619c5cb6 | 8138 | /* Set general SETUP parameters */ |
6383c0b3 AE |
8139 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
8140 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 8141 | |
6383c0b3 | 8142 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
8143 | &setup_params->rxq_params); |
8144 | ||
6383c0b3 AE |
8145 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
8146 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
8147 | |
8148 | /* Set the command */ | |
8149 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
8150 | ||
55c11941 MS |
8151 | if (IS_FCOE_FP(fp)) |
8152 | bp->fcoe_init = true; | |
8153 | ||
619c5cb6 VZ |
8154 | /* Change the state to SETUP */ |
8155 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
8156 | if (rc) { |
8157 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
8158 | return rc; | |
8159 | } | |
8160 | ||
8161 | /* loop through the relevant tx-only indices */ | |
8162 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8163 | tx_index < fp->max_cos; | |
8164 | tx_index++) { | |
8165 | ||
8166 | /* prepare and send tx-only ramrod*/ | |
8167 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
8168 | tx_only_params, tx_index, leading); | |
8169 | if (rc) { | |
8170 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
8171 | fp->index, tx_index); | |
8172 | return rc; | |
8173 | } | |
8174 | } | |
523224a3 | 8175 | |
34f80b04 | 8176 | return rc; |
a2fbb9ea ET |
8177 | } |
8178 | ||
619c5cb6 | 8179 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 8180 | { |
619c5cb6 | 8181 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 8182 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 8183 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
8184 | int rc, tx_index; |
8185 | ||
51c1a580 | 8186 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 8187 | |
15192a8c | 8188 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8189 | /* We want to wait for completion in this context */ |
8190 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8191 | |
6383c0b3 AE |
8192 | |
8193 | /* close tx-only connections */ | |
8194 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8195 | tx_index < fp->max_cos; | |
8196 | tx_index++){ | |
8197 | ||
8198 | /* ascertain this is a normal queue*/ | |
65565884 | 8199 | txdata = fp->txdata_ptr[tx_index]; |
6383c0b3 | 8200 | |
51c1a580 | 8201 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
8202 | txdata->txq_index); |
8203 | ||
8204 | /* send halt terminate on tx-only connection */ | |
8205 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
8206 | memset(&q_params.params.terminate, 0, | |
8207 | sizeof(q_params.params.terminate)); | |
8208 | q_params.params.terminate.cid_index = tx_index; | |
8209 | ||
8210 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8211 | if (rc) | |
8212 | return rc; | |
8213 | ||
8214 | /* send halt terminate on tx-only connection */ | |
8215 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
8216 | memset(&q_params.params.cfc_del, 0, | |
8217 | sizeof(q_params.params.cfc_del)); | |
8218 | q_params.params.cfc_del.cid_index = tx_index; | |
8219 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8220 | if (rc) | |
8221 | return rc; | |
8222 | } | |
8223 | /* Stop the primary connection: */ | |
8224 | /* ...halt the connection */ | |
619c5cb6 VZ |
8225 | q_params.cmd = BNX2X_Q_CMD_HALT; |
8226 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8227 | if (rc) | |
da5a662a | 8228 | return rc; |
a2fbb9ea | 8229 | |
6383c0b3 | 8230 | /* ...terminate the connection */ |
619c5cb6 | 8231 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
8232 | memset(&q_params.params.terminate, 0, |
8233 | sizeof(q_params.params.terminate)); | |
8234 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
8235 | rc = bnx2x_queue_state_change(bp, &q_params); |
8236 | if (rc) | |
523224a3 | 8237 | return rc; |
6383c0b3 | 8238 | /* ...delete cfc entry */ |
619c5cb6 | 8239 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
8240 | memset(&q_params.params.cfc_del, 0, |
8241 | sizeof(q_params.params.cfc_del)); | |
8242 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 8243 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
8244 | } |
8245 | ||
8246 | ||
34f80b04 EG |
8247 | static void bnx2x_reset_func(struct bnx2x *bp) |
8248 | { | |
8249 | int port = BP_PORT(bp); | |
8250 | int func = BP_FUNC(bp); | |
f2e0899f | 8251 | int i; |
523224a3 DK |
8252 | |
8253 | /* Disable the function in the FW */ | |
8254 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
8255 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
8256 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
8257 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
8258 | ||
8259 | /* FP SBs */ | |
ec6ba945 | 8260 | for_each_eth_queue(bp, i) { |
523224a3 | 8261 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 8262 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8263 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
8264 | SB_DISABLED); | |
523224a3 DK |
8265 | } |
8266 | ||
55c11941 MS |
8267 | if (CNIC_LOADED(bp)) |
8268 | /* CNIC SB */ | |
8269 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8270 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET | |
8271 | (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); | |
8272 | ||
523224a3 | 8273 | /* SP SB */ |
619c5cb6 | 8274 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8275 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
8276 | SB_DISABLED); | |
523224a3 DK |
8277 | |
8278 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
8279 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
8280 | 0); | |
34f80b04 EG |
8281 | |
8282 | /* Configure IGU */ | |
f2e0899f DK |
8283 | if (bp->common.int_block == INT_BLOCK_HC) { |
8284 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8285 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8286 | } else { | |
8287 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
8288 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8289 | } | |
34f80b04 | 8290 | |
55c11941 MS |
8291 | if (CNIC_LOADED(bp)) { |
8292 | /* Disable Timer scan */ | |
8293 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
8294 | /* | |
8295 | * Wait for at least 10ms and up to 2 second for the timers | |
8296 | * scan to complete | |
8297 | */ | |
8298 | for (i = 0; i < 200; i++) { | |
8299 | msleep(10); | |
8300 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) | |
8301 | break; | |
8302 | } | |
37b091ba | 8303 | } |
34f80b04 | 8304 | /* Clear ILT */ |
f2e0899f DK |
8305 | bnx2x_clear_func_ilt(bp, func); |
8306 | ||
8307 | /* Timers workaround bug for E2: if this is vnic-3, | |
8308 | * we need to set the entire ilt range for this timers. | |
8309 | */ | |
619c5cb6 | 8310 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
8311 | struct ilt_client_info ilt_cli; |
8312 | /* use dummy TM client */ | |
8313 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
8314 | ilt_cli.start = 0; | |
8315 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
8316 | ilt_cli.client_num = ILT_CLIENT_TM; | |
8317 | ||
8318 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
8319 | } | |
8320 | ||
8321 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 8322 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 8323 | bnx2x_pf_disable(bp); |
523224a3 DK |
8324 | |
8325 | bp->dmae_ready = 0; | |
34f80b04 EG |
8326 | } |
8327 | ||
8328 | static void bnx2x_reset_port(struct bnx2x *bp) | |
8329 | { | |
8330 | int port = BP_PORT(bp); | |
8331 | u32 val; | |
8332 | ||
619c5cb6 VZ |
8333 | /* Reset physical Link */ |
8334 | bnx2x__link_reset(bp); | |
8335 | ||
34f80b04 EG |
8336 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
8337 | ||
8338 | /* Do not rcv packets to BRB */ | |
8339 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
8340 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
8341 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
8342 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
8343 | ||
8344 | /* Configure AEU */ | |
8345 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
8346 | ||
8347 | msleep(100); | |
8348 | /* Check for BRB port occupancy */ | |
8349 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
8350 | if (val) | |
8351 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 8352 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
8353 | |
8354 | /* TODO: Close Doorbell port? */ | |
8355 | } | |
8356 | ||
1191cb83 | 8357 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 8358 | { |
3b603066 | 8359 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 8360 | |
619c5cb6 VZ |
8361 | /* Prepare parameters for function state transitions */ |
8362 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 8363 | |
619c5cb6 VZ |
8364 | func_params.f_obj = &bp->func_obj; |
8365 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 8366 | |
619c5cb6 | 8367 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 8368 | |
619c5cb6 | 8369 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
8370 | } |
8371 | ||
1191cb83 | 8372 | static int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 8373 | { |
3b603066 | 8374 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 8375 | int rc; |
228241eb | 8376 | |
619c5cb6 VZ |
8377 | /* Prepare parameters for function state transitions */ |
8378 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
8379 | func_params.f_obj = &bp->func_obj; | |
8380 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 8381 | |
619c5cb6 VZ |
8382 | /* |
8383 | * Try to stop the function the 'good way'. If fails (in case | |
8384 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
8385 | * not in a debug mode, perform a state transaction in order to | |
8386 | * enable further HW_RESET transaction. | |
8387 | */ | |
8388 | rc = bnx2x_func_state_change(bp, &func_params); | |
8389 | if (rc) { | |
34f80b04 | 8390 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 8391 | return rc; |
34f80b04 | 8392 | #else |
51c1a580 | 8393 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
8394 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
8395 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 8396 | #endif |
228241eb | 8397 | } |
a2fbb9ea | 8398 | |
619c5cb6 VZ |
8399 | return 0; |
8400 | } | |
523224a3 | 8401 | |
619c5cb6 VZ |
8402 | /** |
8403 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
8404 | * | |
8405 | * @bp: driver handle | |
8406 | * @unload_mode: requested function's unload mode | |
8407 | * | |
8408 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
8409 | */ | |
8410 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
8411 | { | |
8412 | u32 reset_code = 0; | |
8413 | int port = BP_PORT(bp); | |
3101c2bc | 8414 | |
619c5cb6 | 8415 | /* Select the UNLOAD request mode */ |
65abd74d YG |
8416 | if (unload_mode == UNLOAD_NORMAL) |
8417 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
8418 | ||
7d0446c2 | 8419 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 8420 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 8421 | |
7d0446c2 | 8422 | else if (bp->wol) { |
65abd74d YG |
8423 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
8424 | u8 *mac_addr = bp->dev->dev_addr; | |
8425 | u32 val; | |
f9977903 DK |
8426 | u16 pmc; |
8427 | ||
65abd74d | 8428 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
8429 | * preserve entry 0 which is used by the PMF |
8430 | */ | |
3395a033 | 8431 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
8432 | |
8433 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
8434 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
8435 | ||
8436 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
8437 | (mac_addr[4] << 8) | mac_addr[5]; | |
8438 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
8439 | ||
f9977903 DK |
8440 | /* Enable the PME and clear the status */ |
8441 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); | |
8442 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; | |
8443 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); | |
8444 | ||
65abd74d YG |
8445 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
8446 | ||
8447 | } else | |
8448 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 8449 | |
619c5cb6 VZ |
8450 | /* Send the request to the MCP */ |
8451 | if (!BP_NOMCP(bp)) | |
8452 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
8453 | else { | |
8454 | int path = BP_PATH(bp); | |
8455 | ||
51c1a580 | 8456 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8457 | path, load_count[path][0], load_count[path][1], |
8458 | load_count[path][2]); | |
8459 | load_count[path][0]--; | |
8460 | load_count[path][1 + port]--; | |
51c1a580 | 8461 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8462 | path, load_count[path][0], load_count[path][1], |
8463 | load_count[path][2]); | |
8464 | if (load_count[path][0] == 0) | |
8465 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
8466 | else if (load_count[path][1 + port] == 0) | |
8467 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
8468 | else | |
8469 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
8470 | } | |
8471 | ||
8472 | return reset_code; | |
8473 | } | |
8474 | ||
8475 | /** | |
8476 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
8477 | * | |
8478 | * @bp: driver handle | |
5d07d868 | 8479 | * @keep_link: true iff link should be kept up |
619c5cb6 | 8480 | */ |
5d07d868 | 8481 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) |
619c5cb6 | 8482 | { |
5d07d868 YM |
8483 | u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; |
8484 | ||
619c5cb6 VZ |
8485 | /* Report UNLOAD_DONE to MCP */ |
8486 | if (!BP_NOMCP(bp)) | |
5d07d868 | 8487 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); |
619c5cb6 VZ |
8488 | } |
8489 | ||
1191cb83 | 8490 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
6debea87 DK |
8491 | { |
8492 | int tout = 50; | |
8493 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8494 | ||
8495 | if (!bp->port.pmf) | |
8496 | return 0; | |
8497 | ||
8498 | /* | |
8499 | * (assumption: No Attention from MCP at this stage) | |
8500 | * PMF probably in the middle of TXdisable/enable transaction | |
8501 | * 1. Sync IRS for default SB | |
8502 | * 2. Sync SP queue - this guarantes us that attention handling started | |
8503 | * 3. Wait, that TXdisable/enable transaction completes | |
8504 | * | |
8505 | * 1+2 guranty that if DCBx attention was scheduled it already changed | |
8506 | * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy | |
8507 | * received complettion for the transaction the state is TX_STOPPED. | |
8508 | * State will return to STARTED after completion of TX_STOPPED-->STARTED | |
8509 | * transaction. | |
8510 | */ | |
8511 | ||
8512 | /* make sure default SB ISR is done */ | |
8513 | if (msix) | |
8514 | synchronize_irq(bp->msix_table[0].vector); | |
8515 | else | |
8516 | synchronize_irq(bp->pdev->irq); | |
8517 | ||
8518 | flush_workqueue(bnx2x_wq); | |
8519 | ||
8520 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8521 | BNX2X_F_STATE_STARTED && tout--) | |
8522 | msleep(20); | |
8523 | ||
8524 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8525 | BNX2X_F_STATE_STARTED) { | |
8526 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 8527 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
8528 | return -EBUSY; |
8529 | #else | |
8530 | /* | |
8531 | * Failed to complete the transaction in a "good way" | |
8532 | * Force both transactions with CLR bit | |
8533 | */ | |
3b603066 | 8534 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 8535 | |
51c1a580 MS |
8536 | DP(NETIF_MSG_IFDOWN, |
8537 | "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); | |
6debea87 DK |
8538 | |
8539 | func_params.f_obj = &bp->func_obj; | |
8540 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
8541 | &func_params.ramrod_flags); | |
8542 | ||
8543 | /* STARTED-->TX_ST0PPED */ | |
8544 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
8545 | bnx2x_func_state_change(bp, &func_params); | |
8546 | ||
8547 | /* TX_ST0PPED-->STARTED */ | |
8548 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
8549 | return bnx2x_func_state_change(bp, &func_params); | |
8550 | #endif | |
8551 | } | |
8552 | ||
8553 | return 0; | |
8554 | } | |
8555 | ||
5d07d868 | 8556 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) |
619c5cb6 VZ |
8557 | { |
8558 | int port = BP_PORT(bp); | |
6383c0b3 AE |
8559 | int i, rc = 0; |
8560 | u8 cos; | |
3b603066 | 8561 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
8562 | u32 reset_code; |
8563 | ||
8564 | /* Wait until tx fastpath tasks complete */ | |
8565 | for_each_tx_queue(bp, i) { | |
8566 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
8567 | ||
6383c0b3 | 8568 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 8569 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
619c5cb6 VZ |
8570 | #ifdef BNX2X_STOP_ON_ERROR |
8571 | if (rc) | |
8572 | return; | |
8573 | #endif | |
8574 | } | |
8575 | ||
8576 | /* Give HW time to discard old tx messages */ | |
8577 | usleep_range(1000, 1000); | |
8578 | ||
8579 | /* Clean all ETH MACs */ | |
15192a8c BW |
8580 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
8581 | false); | |
619c5cb6 VZ |
8582 | if (rc < 0) |
8583 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
8584 | ||
8585 | /* Clean up UC list */ | |
15192a8c | 8586 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
619c5cb6 VZ |
8587 | true); |
8588 | if (rc < 0) | |
51c1a580 MS |
8589 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
8590 | rc); | |
619c5cb6 VZ |
8591 | |
8592 | /* Disable LLH */ | |
8593 | if (!CHIP_IS_E1(bp)) | |
8594 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
8595 | ||
8596 | /* Set "drop all" (stop Rx). | |
8597 | * We need to take a netif_addr_lock() here in order to prevent | |
8598 | * a race between the completion code and this code. | |
8599 | */ | |
8600 | netif_addr_lock_bh(bp->dev); | |
8601 | /* Schedule the rx_mode command */ | |
8602 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
8603 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8604 | else | |
8605 | bnx2x_set_storm_rx_mode(bp); | |
8606 | ||
8607 | /* Cleanup multicast configuration */ | |
8608 | rparam.mcast_obj = &bp->mcast_obj; | |
8609 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
8610 | if (rc < 0) | |
8611 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
8612 | ||
8613 | netif_addr_unlock_bh(bp->dev); | |
8614 | ||
8615 | ||
6debea87 DK |
8616 | |
8617 | /* | |
8618 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
8619 | * this function should perform FUNC, PORT or COMMON HW | |
8620 | * reset. | |
8621 | */ | |
8622 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
8623 | ||
8624 | /* | |
8625 | * (assumption: No Attention from MCP at this stage) | |
8626 | * PMF probably in the middle of TXdisable/enable transaction | |
8627 | */ | |
8628 | rc = bnx2x_func_wait_started(bp); | |
8629 | if (rc) { | |
8630 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
8631 | #ifdef BNX2X_STOP_ON_ERROR | |
8632 | return; | |
8633 | #endif | |
8634 | } | |
8635 | ||
34f80b04 | 8636 | /* Close multi and leading connections |
619c5cb6 VZ |
8637 | * Completions for ramrods are collected in a synchronous way |
8638 | */ | |
55c11941 | 8639 | for_each_eth_queue(bp, i) |
619c5cb6 | 8640 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
8641 | #ifdef BNX2X_STOP_ON_ERROR |
8642 | return; | |
8643 | #else | |
228241eb | 8644 | goto unload_error; |
523224a3 | 8645 | #endif |
55c11941 MS |
8646 | |
8647 | if (CNIC_LOADED(bp)) { | |
8648 | for_each_cnic_queue(bp, i) | |
8649 | if (bnx2x_stop_queue(bp, i)) | |
8650 | #ifdef BNX2X_STOP_ON_ERROR | |
8651 | return; | |
8652 | #else | |
8653 | goto unload_error; | |
8654 | #endif | |
8655 | } | |
8656 | ||
619c5cb6 VZ |
8657 | /* If SP settings didn't get completed so far - something |
8658 | * very wrong has happen. | |
8659 | */ | |
8660 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
8661 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 8662 | |
619c5cb6 VZ |
8663 | #ifndef BNX2X_STOP_ON_ERROR |
8664 | unload_error: | |
8665 | #endif | |
523224a3 | 8666 | rc = bnx2x_func_stop(bp); |
da5a662a | 8667 | if (rc) { |
523224a3 | 8668 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 8669 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 8670 | return; |
523224a3 | 8671 | #endif |
34f80b04 | 8672 | } |
a2fbb9ea | 8673 | |
523224a3 DK |
8674 | /* Disable HW interrupts, NAPI */ |
8675 | bnx2x_netif_stop(bp, 1); | |
26614ba5 MS |
8676 | /* Delete all NAPI objects */ |
8677 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
8678 | if (CNIC_LOADED(bp)) |
8679 | bnx2x_del_all_napi_cnic(bp); | |
523224a3 DK |
8680 | |
8681 | /* Release IRQs */ | |
d6214d7a | 8682 | bnx2x_free_irq(bp); |
523224a3 | 8683 | |
a2fbb9ea | 8684 | /* Reset the chip */ |
619c5cb6 VZ |
8685 | rc = bnx2x_reset_hw(bp, reset_code); |
8686 | if (rc) | |
8687 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 8688 | |
356e2385 | 8689 | |
619c5cb6 | 8690 | /* Report UNLOAD_DONE to MCP */ |
5d07d868 | 8691 | bnx2x_send_unload_done(bp, keep_link); |
72fd0718 VZ |
8692 | } |
8693 | ||
9f6c9258 | 8694 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
8695 | { |
8696 | u32 val; | |
8697 | ||
51c1a580 | 8698 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
8699 | |
8700 | if (CHIP_IS_E1(bp)) { | |
8701 | int port = BP_PORT(bp); | |
8702 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
8703 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
8704 | ||
8705 | val = REG_RD(bp, addr); | |
8706 | val &= ~(0x300); | |
8707 | REG_WR(bp, addr, val); | |
619c5cb6 | 8708 | } else { |
72fd0718 VZ |
8709 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
8710 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
8711 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
8712 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
8713 | } | |
8714 | } | |
8715 | ||
72fd0718 VZ |
8716 | /* Close gates #2, #3 and #4: */ |
8717 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
8718 | { | |
c9ee9206 | 8719 | u32 val; |
72fd0718 VZ |
8720 | |
8721 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
8722 | if (!CHIP_IS_E1(bp)) { | |
8723 | /* #4 */ | |
c9ee9206 | 8724 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 8725 | /* #2 */ |
c9ee9206 | 8726 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
8727 | } |
8728 | ||
8729 | /* #3 */ | |
c9ee9206 VZ |
8730 | if (CHIP_IS_E1x(bp)) { |
8731 | /* Prevent interrupts from HC on both ports */ | |
8732 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
8733 | REG_WR(bp, HC_REG_CONFIG_1, | |
8734 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
8735 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
8736 | ||
8737 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
8738 | REG_WR(bp, HC_REG_CONFIG_0, | |
8739 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
8740 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
8741 | } else { | |
8742 | /* Prevent incomming interrupts in IGU */ | |
8743 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
8744 | ||
8745 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
8746 | (!close) ? | |
8747 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
8748 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
8749 | } | |
72fd0718 | 8750 | |
51c1a580 | 8751 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
8752 | close ? "closing" : "opening"); |
8753 | mmiowb(); | |
8754 | } | |
8755 | ||
8756 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
8757 | ||
8758 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
8759 | { | |
8760 | /* Do some magic... */ | |
8761 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
8762 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
8763 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
8764 | } | |
8765 | ||
e8920674 DK |
8766 | /** |
8767 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 8768 | * |
e8920674 DK |
8769 | * @bp: driver handle |
8770 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
8771 | */ |
8772 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
8773 | { | |
8774 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
8775 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
8776 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
8777 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
8778 | } | |
8779 | ||
f85582f8 | 8780 | /** |
e8920674 | 8781 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 8782 | * |
e8920674 DK |
8783 | * @bp: driver handle |
8784 | * @magic_val: old value of 'magic' bit. | |
8785 | * | |
8786 | * Takes care of CLP configurations. | |
72fd0718 VZ |
8787 | */ |
8788 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
8789 | { | |
8790 | u32 shmem; | |
8791 | u32 validity_offset; | |
8792 | ||
51c1a580 | 8793 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
8794 | |
8795 | /* Set `magic' bit in order to save MF config */ | |
8796 | if (!CHIP_IS_E1(bp)) | |
8797 | bnx2x_clp_reset_prep(bp, magic_val); | |
8798 | ||
8799 | /* Get shmem offset */ | |
8800 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
c55e771b BW |
8801 | validity_offset = |
8802 | offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); | |
72fd0718 VZ |
8803 | |
8804 | /* Clear validity map flags */ | |
8805 | if (shmem > 0) | |
8806 | REG_WR(bp, shmem + validity_offset, 0); | |
8807 | } | |
8808 | ||
8809 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
8810 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
8811 | ||
e8920674 DK |
8812 | /** |
8813 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 8814 | * |
e8920674 | 8815 | * @bp: driver handle |
72fd0718 | 8816 | */ |
1191cb83 | 8817 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
72fd0718 VZ |
8818 | { |
8819 | /* special handling for emulation and FPGA, | |
8820 | wait 10 times longer */ | |
8821 | if (CHIP_REV_IS_SLOW(bp)) | |
8822 | msleep(MCP_ONE_TIMEOUT*10); | |
8823 | else | |
8824 | msleep(MCP_ONE_TIMEOUT); | |
8825 | } | |
8826 | ||
1b6e2ceb DK |
8827 | /* |
8828 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
8829 | */ | |
8830 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 8831 | { |
1b6e2ceb DK |
8832 | int cnt = 0; |
8833 | u32 val = 0; | |
72fd0718 | 8834 | |
1b6e2ceb DK |
8835 | do { |
8836 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8837 | if (bp->common.shmem_base) { | |
8838 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
8839 | if (val & SHR_MEM_VALIDITY_MB) | |
8840 | return 0; | |
8841 | } | |
72fd0718 | 8842 | |
1b6e2ceb | 8843 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 8844 | |
1b6e2ceb | 8845 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 8846 | |
1b6e2ceb | 8847 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 8848 | |
1b6e2ceb DK |
8849 | return -ENODEV; |
8850 | } | |
72fd0718 | 8851 | |
1b6e2ceb DK |
8852 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
8853 | { | |
8854 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 8855 | |
72fd0718 VZ |
8856 | /* Restore the `magic' bit value */ |
8857 | if (!CHIP_IS_E1(bp)) | |
8858 | bnx2x_clp_reset_done(bp, magic_val); | |
8859 | ||
8860 | return rc; | |
8861 | } | |
8862 | ||
8863 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
8864 | { | |
8865 | if (!CHIP_IS_E1(bp)) { | |
8866 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
8867 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
8868 | mmiowb(); |
8869 | } | |
8870 | } | |
8871 | ||
8872 | /* | |
8873 | * Reset the whole chip except for: | |
8874 | * - PCIE core | |
8875 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
8876 | * one reset bit) | |
8877 | * - IGU | |
8878 | * - MISC (including AEU) | |
8879 | * - GRC | |
8880 | * - RBCN, RBCP | |
8881 | */ | |
c9ee9206 | 8882 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
8883 | { |
8884 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 8885 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
8886 | |
8887 | /* | |
8888 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
8889 | * (per chip) blocks. | |
8890 | */ | |
8891 | global_bits2 = | |
8892 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
8893 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 8894 | |
c55e771b BW |
8895 | /* Don't reset the following blocks. |
8896 | * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be | |
8897 | * reset, as in 4 port device they might still be owned | |
8898 | * by the MCP (there is only one leader per path). | |
8899 | */ | |
72fd0718 VZ |
8900 | not_reset_mask1 = |
8901 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
8902 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
8903 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
8904 | ||
8905 | not_reset_mask2 = | |
c9ee9206 | 8906 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
8907 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
8908 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
8909 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
8910 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
8911 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
8912 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
8913 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
8914 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
c55e771b BW |
8915 | MISC_REGISTERS_RESET_REG_2_PGLC | |
8916 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
8917 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
8918 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
8919 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
8920 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
8921 | MISC_REGISTERS_RESET_REG_2_UMAC1; | |
72fd0718 | 8922 | |
8736c826 VZ |
8923 | /* |
8924 | * Keep the following blocks in reset: | |
8925 | * - all xxMACs are handled by the bnx2x_link code. | |
8926 | */ | |
8927 | stay_reset2 = | |
8736c826 VZ |
8928 | MISC_REGISTERS_RESET_REG_2_XMAC | |
8929 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
8930 | ||
8931 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
8932 | reset_mask1 = 0xffffffff; |
8933 | ||
8934 | if (CHIP_IS_E1(bp)) | |
8935 | reset_mask2 = 0xffff; | |
8736c826 | 8936 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 8937 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
8938 | else if (CHIP_IS_E2(bp)) |
8939 | reset_mask2 = 0xfffff; | |
8940 | else /* CHIP_IS_E3 */ | |
8941 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
8942 | |
8943 | /* Don't reset global blocks unless we need to */ | |
8944 | if (!global) | |
8945 | reset_mask2 &= ~global_bits2; | |
8946 | ||
8947 | /* | |
8948 | * In case of attention in the QM, we need to reset PXP | |
8949 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
8950 | * because otherwise QM reset would release 'close the gates' shortly | |
8951 | * before resetting the PXP, then the PSWRQ would send a write | |
8952 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
8953 | * read the payload data from PSWWR, but PSWWR would not | |
8954 | * respond. The write queue in PGLUE would stuck, dmae commands | |
8955 | * would not return. Therefore it's important to reset the second | |
8956 | * reset register (containing the | |
8957 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
8958 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
8959 | * bit). | |
8960 | */ | |
72fd0718 VZ |
8961 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
8962 | reset_mask2 & (~not_reset_mask2)); | |
8963 | ||
c9ee9206 VZ |
8964 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
8965 | reset_mask1 & (~not_reset_mask1)); | |
8966 | ||
72fd0718 VZ |
8967 | barrier(); |
8968 | mmiowb(); | |
8969 | ||
8736c826 VZ |
8970 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
8971 | reset_mask2 & (~stay_reset2)); | |
8972 | ||
8973 | barrier(); | |
8974 | mmiowb(); | |
8975 | ||
c9ee9206 | 8976 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
8977 | mmiowb(); |
8978 | } | |
8979 | ||
c9ee9206 VZ |
8980 | /** |
8981 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
8982 | * It should get cleared in no more than 1s. | |
8983 | * | |
8984 | * @bp: driver handle | |
8985 | * | |
8986 | * It should get cleared in no more than 1s. Returns 0 if | |
8987 | * pending writes bit gets cleared. | |
8988 | */ | |
8989 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
8990 | { | |
8991 | u32 cnt = 1000; | |
8992 | u32 pend_bits = 0; | |
8993 | ||
8994 | do { | |
8995 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
8996 | ||
8997 | if (pend_bits == 0) | |
8998 | break; | |
8999 | ||
9000 | usleep_range(1000, 1000); | |
9001 | } while (cnt-- > 0); | |
9002 | ||
9003 | if (cnt <= 0) { | |
9004 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
9005 | pend_bits); | |
9006 | return -EBUSY; | |
9007 | } | |
9008 | ||
9009 | return 0; | |
9010 | } | |
9011 | ||
9012 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
9013 | { |
9014 | int cnt = 1000; | |
9015 | u32 val = 0; | |
9016 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
c55e771b | 9017 | u32 tags_63_32 = 0; |
72fd0718 VZ |
9018 | |
9019 | ||
9020 | /* Empty the Tetris buffer, wait for 1s */ | |
9021 | do { | |
9022 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
9023 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
9024 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
9025 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
9026 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
c55e771b BW |
9027 | if (CHIP_IS_E3(bp)) |
9028 | tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); | |
9029 | ||
72fd0718 VZ |
9030 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && |
9031 | ((port_is_idle_0 & 0x1) == 0x1) && | |
9032 | ((port_is_idle_1 & 0x1) == 0x1) && | |
c55e771b BW |
9033 | (pgl_exp_rom2 == 0xffffffff) && |
9034 | (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) | |
72fd0718 | 9035 | break; |
c9ee9206 | 9036 | usleep_range(1000, 1000); |
72fd0718 VZ |
9037 | } while (cnt-- > 0); |
9038 | ||
9039 | if (cnt <= 0) { | |
51c1a580 MS |
9040 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
9041 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
9042 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
9043 | pgl_exp_rom2); | |
9044 | return -EAGAIN; | |
9045 | } | |
9046 | ||
9047 | barrier(); | |
9048 | ||
9049 | /* Close gates #2, #3 and #4 */ | |
9050 | bnx2x_set_234_gates(bp, true); | |
9051 | ||
c9ee9206 VZ |
9052 | /* Poll for IGU VQs for 57712 and newer chips */ |
9053 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
9054 | return -EAGAIN; | |
9055 | ||
9056 | ||
72fd0718 VZ |
9057 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
9058 | ||
9059 | /* Clear "unprepared" bit */ | |
9060 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
9061 | barrier(); | |
9062 | ||
9063 | /* Make sure all is written to the chip before the reset */ | |
9064 | mmiowb(); | |
9065 | ||
9066 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
9067 | * PSWHST, GRC and PSWRD Tetris buffer. | |
9068 | */ | |
c9ee9206 | 9069 | usleep_range(1000, 1000); |
72fd0718 VZ |
9070 | |
9071 | /* Prepare to chip reset: */ | |
9072 | /* MCP */ | |
c9ee9206 VZ |
9073 | if (global) |
9074 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
9075 | |
9076 | /* PXP */ | |
9077 | bnx2x_pxp_prep(bp); | |
9078 | barrier(); | |
9079 | ||
9080 | /* reset the chip */ | |
c9ee9206 | 9081 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
9082 | barrier(); |
9083 | ||
9084 | /* Recover after reset: */ | |
9085 | /* MCP */ | |
c9ee9206 | 9086 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
9087 | return -EAGAIN; |
9088 | ||
c9ee9206 VZ |
9089 | /* TBD: Add resetting the NO_MCP mode DB here */ |
9090 | ||
72fd0718 VZ |
9091 | /* Open the gates #2, #3 and #4 */ |
9092 | bnx2x_set_234_gates(bp, false); | |
9093 | ||
9094 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
9095 | * reset state, re-enable attentions. */ | |
9096 | ||
a2fbb9ea ET |
9097 | return 0; |
9098 | } | |
9099 | ||
910cc727 | 9100 | static int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
9101 | { |
9102 | int rc = 0; | |
c9ee9206 | 9103 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
9104 | u32 load_code; |
9105 | ||
9106 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
9107 | * driver is owner of the HW | |
9108 | */ | |
9109 | if (!global && !BP_NOMCP(bp)) { | |
5d07d868 YM |
9110 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, |
9111 | DRV_MSG_CODE_LOAD_REQ_WITH_LFA); | |
95c6c616 AE |
9112 | if (!load_code) { |
9113 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9114 | rc = -EAGAIN; | |
9115 | goto exit_leader_reset; | |
9116 | } | |
9117 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
9118 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
9119 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
9120 | rc = -EAGAIN; | |
9121 | goto exit_leader_reset2; | |
9122 | } | |
9123 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
9124 | if (!load_code) { | |
9125 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9126 | rc = -EAGAIN; | |
9127 | goto exit_leader_reset2; | |
9128 | } | |
9129 | } | |
c9ee9206 | 9130 | |
72fd0718 | 9131 | /* Try to recover after the failure */ |
c9ee9206 | 9132 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
9133 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
9134 | BP_PATH(bp)); | |
72fd0718 | 9135 | rc = -EAGAIN; |
95c6c616 | 9136 | goto exit_leader_reset2; |
72fd0718 VZ |
9137 | } |
9138 | ||
c9ee9206 VZ |
9139 | /* |
9140 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
9141 | * state. | |
9142 | */ | |
72fd0718 | 9143 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
9144 | if (global) |
9145 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 9146 | |
95c6c616 AE |
9147 | exit_leader_reset2: |
9148 | /* unload "fake driver" if it was loaded */ | |
9149 | if (!global && !BP_NOMCP(bp)) { | |
9150 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
9151 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9152 | } | |
72fd0718 VZ |
9153 | exit_leader_reset: |
9154 | bp->is_leader = 0; | |
c9ee9206 VZ |
9155 | bnx2x_release_leader_lock(bp); |
9156 | smp_mb(); | |
72fd0718 VZ |
9157 | return rc; |
9158 | } | |
9159 | ||
1191cb83 | 9160 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
c9ee9206 VZ |
9161 | { |
9162 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
9163 | ||
9164 | /* Disconnect this device */ | |
9165 | netif_device_detach(bp->dev); | |
9166 | ||
9167 | /* | |
9168 | * Block ifup for all function on this engine until "process kill" | |
9169 | * or power cycle. | |
9170 | */ | |
9171 | bnx2x_set_reset_in_progress(bp); | |
9172 | ||
9173 | /* Shut down the power */ | |
9174 | bnx2x_set_power_state(bp, PCI_D3hot); | |
9175 | ||
9176 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
9177 | ||
9178 | smp_mb(); | |
9179 | } | |
9180 | ||
9181 | /* | |
9182 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 9183 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
9184 | * will never be called when netif_running(bp->dev) is false. |
9185 | */ | |
9186 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
9187 | { | |
c9ee9206 | 9188 | bool global = false; |
7a752993 | 9189 | u32 error_recovered, error_unrecovered; |
95c6c616 | 9190 | bool is_parity; |
c9ee9206 | 9191 | |
72fd0718 VZ |
9192 | DP(NETIF_MSG_HW, "Handling parity\n"); |
9193 | while (1) { | |
9194 | switch (bp->recovery_state) { | |
9195 | case BNX2X_RECOVERY_INIT: | |
9196 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
9197 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
9198 | WARN_ON(!is_parity); | |
c9ee9206 | 9199 | |
72fd0718 | 9200 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
9201 | if (bnx2x_trylock_leader_lock(bp)) { |
9202 | bnx2x_set_reset_in_progress(bp); | |
9203 | /* | |
9204 | * Check if there is a global attention and if | |
9205 | * there was a global attention, set the global | |
9206 | * reset bit. | |
9207 | */ | |
9208 | ||
9209 | if (global) | |
9210 | bnx2x_set_reset_global(bp); | |
9211 | ||
72fd0718 | 9212 | bp->is_leader = 1; |
c9ee9206 | 9213 | } |
72fd0718 VZ |
9214 | |
9215 | /* Stop the driver */ | |
9216 | /* If interface has been removed - break */ | |
5d07d868 | 9217 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) |
72fd0718 VZ |
9218 | return; |
9219 | ||
9220 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 9221 | |
c9ee9206 VZ |
9222 | /* Ensure "is_leader", MCP command sequence and |
9223 | * "recovery_state" update values are seen on other | |
9224 | * CPUs. | |
72fd0718 | 9225 | */ |
c9ee9206 | 9226 | smp_mb(); |
72fd0718 VZ |
9227 | break; |
9228 | ||
9229 | case BNX2X_RECOVERY_WAIT: | |
9230 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
9231 | if (bp->is_leader) { | |
c9ee9206 | 9232 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
9233 | bool other_load_status = |
9234 | bnx2x_get_load_status(bp, other_engine); | |
9235 | bool load_status = | |
9236 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
9237 | global = bnx2x_reset_is_global(bp); |
9238 | ||
9239 | /* | |
9240 | * In case of a parity in a global block, let | |
9241 | * the first leader that performs a | |
9242 | * leader_reset() reset the global blocks in | |
9243 | * order to clear global attentions. Otherwise | |
9244 | * the the gates will remain closed for that | |
9245 | * engine. | |
9246 | */ | |
889b9af3 AE |
9247 | if (load_status || |
9248 | (global && other_load_status)) { | |
72fd0718 VZ |
9249 | /* Wait until all other functions get |
9250 | * down. | |
9251 | */ | |
7be08a72 | 9252 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9253 | HZ/10); |
9254 | return; | |
9255 | } else { | |
9256 | /* If all other functions got down - | |
9257 | * try to bring the chip back to | |
9258 | * normal. In any case it's an exit | |
9259 | * point for a leader. | |
9260 | */ | |
c9ee9206 VZ |
9261 | if (bnx2x_leader_reset(bp)) { |
9262 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
9263 | return; |
9264 | } | |
9265 | ||
c9ee9206 VZ |
9266 | /* If we are here, means that the |
9267 | * leader has succeeded and doesn't | |
9268 | * want to be a leader any more. Try | |
9269 | * to continue as a none-leader. | |
9270 | */ | |
9271 | break; | |
72fd0718 VZ |
9272 | } |
9273 | } else { /* non-leader */ | |
c9ee9206 | 9274 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
9275 | /* Try to get a LEADER_LOCK HW lock as |
9276 | * long as a former leader may have | |
9277 | * been unloaded by the user or | |
9278 | * released a leadership by another | |
9279 | * reason. | |
9280 | */ | |
c9ee9206 | 9281 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
9282 | /* I'm a leader now! Restart a |
9283 | * switch case. | |
9284 | */ | |
9285 | bp->is_leader = 1; | |
9286 | break; | |
9287 | } | |
9288 | ||
7be08a72 | 9289 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9290 | HZ/10); |
9291 | return; | |
9292 | ||
c9ee9206 VZ |
9293 | } else { |
9294 | /* | |
9295 | * If there was a global attention, wait | |
9296 | * for it to be cleared. | |
9297 | */ | |
9298 | if (bnx2x_reset_is_global(bp)) { | |
9299 | schedule_delayed_work( | |
7be08a72 AE |
9300 | &bp->sp_rtnl_task, |
9301 | HZ/10); | |
c9ee9206 VZ |
9302 | return; |
9303 | } | |
9304 | ||
7a752993 AE |
9305 | error_recovered = |
9306 | bp->eth_stats.recoverable_error; | |
9307 | error_unrecovered = | |
9308 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
9309 | bp->recovery_state = |
9310 | BNX2X_RECOVERY_NIC_LOADING; | |
9311 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 9312 | error_unrecovered++; |
95c6c616 | 9313 | netdev_err(bp->dev, |
51c1a580 | 9314 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
9315 | /* Disconnect this device */ |
9316 | netif_device_detach(bp->dev); | |
9317 | /* Shut down the power */ | |
9318 | bnx2x_set_power_state( | |
9319 | bp, PCI_D3hot); | |
9320 | smp_mb(); | |
9321 | } else { | |
c9ee9206 VZ |
9322 | bp->recovery_state = |
9323 | BNX2X_RECOVERY_DONE; | |
7a752993 | 9324 | error_recovered++; |
c9ee9206 VZ |
9325 | smp_mb(); |
9326 | } | |
7a752993 AE |
9327 | bp->eth_stats.recoverable_error = |
9328 | error_recovered; | |
9329 | bp->eth_stats.unrecoverable_error = | |
9330 | error_unrecovered; | |
c9ee9206 | 9331 | |
72fd0718 VZ |
9332 | return; |
9333 | } | |
9334 | } | |
9335 | default: | |
9336 | return; | |
9337 | } | |
9338 | } | |
9339 | } | |
9340 | ||
56ad3152 MS |
9341 | static int bnx2x_close(struct net_device *dev); |
9342 | ||
72fd0718 VZ |
9343 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
9344 | * scheduled on a general queue in order to prevent a dead lock. | |
9345 | */ | |
7be08a72 | 9346 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 9347 | { |
7be08a72 | 9348 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
9349 | |
9350 | rtnl_lock(); | |
9351 | ||
9352 | if (!netif_running(bp->dev)) | |
7be08a72 AE |
9353 | goto sp_rtnl_exit; |
9354 | ||
9355 | /* if stop on error is defined no recovery flows should be executed */ | |
9356 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 9357 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
7be08a72 | 9358 | "you will need to reboot when done\n"); |
b1fb8740 | 9359 | goto sp_rtnl_not_reset; |
7be08a72 | 9360 | #endif |
34f80b04 | 9361 | |
7be08a72 AE |
9362 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
9363 | /* | |
b1fb8740 VZ |
9364 | * Clear all pending SP commands as we are going to reset the |
9365 | * function anyway. | |
7be08a72 | 9366 | */ |
b1fb8740 VZ |
9367 | bp->sp_rtnl_state = 0; |
9368 | smp_mb(); | |
9369 | ||
72fd0718 | 9370 | bnx2x_parity_recover(bp); |
b1fb8740 VZ |
9371 | |
9372 | goto sp_rtnl_exit; | |
9373 | } | |
9374 | ||
9375 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
9376 | /* | |
9377 | * Clear all pending SP commands as we are going to reset the | |
9378 | * function anyway. | |
9379 | */ | |
9380 | bp->sp_rtnl_state = 0; | |
9381 | smp_mb(); | |
9382 | ||
5d07d868 | 9383 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
72fd0718 | 9384 | bnx2x_nic_load(bp, LOAD_NORMAL); |
b1fb8740 VZ |
9385 | |
9386 | goto sp_rtnl_exit; | |
72fd0718 | 9387 | } |
b1fb8740 VZ |
9388 | #ifdef BNX2X_STOP_ON_ERROR |
9389 | sp_rtnl_not_reset: | |
9390 | #endif | |
9391 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
9392 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
9393 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
9394 | bnx2x_after_function_update(bp); | |
8304859a AE |
9395 | /* |
9396 | * in case of fan failure we need to reset id if the "stop on error" | |
9397 | * debug flag is set, since we trying to prevent permanent overheating | |
9398 | * damage | |
9399 | */ | |
9400 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 9401 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
9402 | netif_device_detach(bp->dev); |
9403 | bnx2x_close(bp->dev); | |
9404 | } | |
9405 | ||
381ac16b AE |
9406 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { |
9407 | DP(BNX2X_MSG_SP, | |
9408 | "sending set mcast vf pf channel message from rtnl sp-task\n"); | |
9409 | bnx2x_vfpf_set_mcast(bp->dev); | |
9410 | } | |
9411 | ||
9412 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, | |
9413 | &bp->sp_rtnl_state)) { | |
9414 | DP(BNX2X_MSG_SP, | |
9415 | "sending set storm rx mode vf pf channel message from rtnl sp-task\n"); | |
9416 | bnx2x_vfpf_storm_rx_mode(bp); | |
9417 | } | |
9418 | ||
7be08a72 | 9419 | sp_rtnl_exit: |
34f80b04 EG |
9420 | rtnl_unlock(); |
9421 | } | |
9422 | ||
a2fbb9ea ET |
9423 | /* end of nic load/unload */ |
9424 | ||
3deb8167 YR |
9425 | static void bnx2x_period_task(struct work_struct *work) |
9426 | { | |
9427 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
9428 | ||
9429 | if (!netif_running(bp->dev)) | |
9430 | goto period_task_exit; | |
9431 | ||
9432 | if (CHIP_REV_IS_SLOW(bp)) { | |
9433 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
9434 | goto period_task_exit; | |
9435 | } | |
9436 | ||
9437 | bnx2x_acquire_phy_lock(bp); | |
9438 | /* | |
9439 | * The barrier is needed to ensure the ordering between the writing to | |
9440 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
9441 | * the reading here. | |
9442 | */ | |
9443 | smp_mb(); | |
9444 | if (bp->port.pmf) { | |
9445 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
9446 | ||
9447 | /* Re-queue task in 1 sec */ | |
9448 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
9449 | } | |
9450 | ||
9451 | bnx2x_release_phy_lock(bp); | |
9452 | period_task_exit: | |
9453 | return; | |
9454 | } | |
9455 | ||
a2fbb9ea ET |
9456 | /* |
9457 | * Init service functions | |
9458 | */ | |
9459 | ||
8d96286a | 9460 | static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
9461 | { |
9462 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
9463 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
9464 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
9465 | } |
9466 | ||
f2e0899f | 9467 | static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) |
f1ef27ef | 9468 | { |
f2e0899f | 9469 | u32 reg = bnx2x_get_pretend_reg(bp); |
f1ef27ef EG |
9470 | |
9471 | /* Flush all outstanding writes */ | |
9472 | mmiowb(); | |
9473 | ||
9474 | /* Pretend to be function 0 */ | |
9475 | REG_WR(bp, reg, 0); | |
f2e0899f | 9476 | REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ |
f1ef27ef EG |
9477 | |
9478 | /* From now we are in the "like-E1" mode */ | |
9479 | bnx2x_int_disable(bp); | |
9480 | ||
9481 | /* Flush all outstanding writes */ | |
9482 | mmiowb(); | |
9483 | ||
f2e0899f DK |
9484 | /* Restore the original function */ |
9485 | REG_WR(bp, reg, BP_ABS_FUNC(bp)); | |
9486 | REG_RD(bp, reg); | |
f1ef27ef EG |
9487 | } |
9488 | ||
f2e0899f | 9489 | static inline void bnx2x_undi_int_disable(struct bnx2x *bp) |
f1ef27ef | 9490 | { |
f2e0899f | 9491 | if (CHIP_IS_E1(bp)) |
f1ef27ef | 9492 | bnx2x_int_disable(bp); |
f2e0899f DK |
9493 | else |
9494 | bnx2x_undi_int_disable_e1h(bp); | |
f1ef27ef EG |
9495 | } |
9496 | ||
0329aba1 | 9497 | static void bnx2x_prev_unload_close_mac(struct bnx2x *bp) |
34f80b04 | 9498 | { |
452427b0 YM |
9499 | u32 val, base_addr, offset, mask, reset_reg; |
9500 | bool mac_stopped = false; | |
9501 | u8 port = BP_PORT(bp); | |
34f80b04 | 9502 | |
452427b0 | 9503 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 9504 | |
452427b0 YM |
9505 | if (!CHIP_IS_E3(bp)) { |
9506 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
9507 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
9508 | if ((mask & reset_reg) && val) { | |
9509 | u32 wb_data[2]; | |
9510 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
9511 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
9512 | : NIG_REG_INGRESS_BMAC0_MEM; | |
9513 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
9514 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 9515 | |
452427b0 YM |
9516 | /* |
9517 | * use rd/wr since we cannot use dmae. This is safe | |
9518 | * since MCP won't access the bus due to the request | |
9519 | * to unload, and no function on the path can be | |
9520 | * loaded at this time. | |
9521 | */ | |
9522 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
9523 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
9524 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
9525 | REG_WR(bp, base_addr + offset, wb_data[0]); | |
9526 | REG_WR(bp, base_addr + offset + 0x4, wb_data[1]); | |
9527 | ||
9528 | } | |
9529 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
9530 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0); | |
9531 | ||
9532 | mac_stopped = true; | |
9533 | } else { | |
9534 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
9535 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
9536 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
9537 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
9538 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9539 | val & ~(1 << 1)); | |
9540 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9541 | val | (1 << 1)); | |
9542 | REG_WR(bp, base_addr + XMAC_REG_CTRL, 0); | |
9543 | mac_stopped = true; | |
9544 | } | |
9545 | mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
9546 | if (mask & reset_reg) { | |
9547 | BNX2X_DEV_INFO("Disable umac Rx\n"); | |
9548 | base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
9549 | REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0); | |
9550 | mac_stopped = true; | |
9551 | } | |
9552 | } | |
9553 | ||
9554 | if (mac_stopped) | |
9555 | msleep(20); | |
9556 | ||
9557 | } | |
9558 | ||
9559 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
9560 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) | |
9561 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
9562 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
9563 | ||
1dd06ae8 | 9564 | static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc) |
452427b0 YM |
9565 | { |
9566 | u16 rcq, bd; | |
9567 | u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); | |
9568 | ||
9569 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; | |
9570 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
9571 | ||
9572 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
9573 | REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); | |
9574 | ||
9575 | BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", | |
9576 | port, bd, rcq); | |
9577 | } | |
9578 | ||
0329aba1 | 9579 | static int bnx2x_prev_mcp_done(struct bnx2x *bp) |
452427b0 | 9580 | { |
5d07d868 YM |
9581 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, |
9582 | DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); | |
452427b0 YM |
9583 | if (!rc) { |
9584 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9585 | return -EBUSY; | |
9586 | } | |
9587 | ||
9588 | return 0; | |
9589 | } | |
9590 | ||
c63da990 BW |
9591 | static struct bnx2x_prev_path_list * |
9592 | bnx2x_prev_path_get_entry(struct bnx2x *bp) | |
9593 | { | |
9594 | struct bnx2x_prev_path_list *tmp_list; | |
9595 | ||
9596 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) | |
9597 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
9598 | bp->pdev->bus->number == tmp_list->bus && | |
9599 | BP_PATH(bp) == tmp_list->path) | |
9600 | return tmp_list; | |
9601 | ||
9602 | return NULL; | |
9603 | } | |
9604 | ||
0329aba1 | 9605 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) |
452427b0 YM |
9606 | { |
9607 | struct bnx2x_prev_path_list *tmp_list; | |
9608 | int rc = false; | |
9609 | ||
9610 | if (down_trylock(&bnx2x_prev_sem)) | |
9611 | return false; | |
9612 | ||
9613 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) { | |
9614 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
9615 | bp->pdev->bus->number == tmp_list->bus && | |
9616 | BP_PATH(bp) == tmp_list->path) { | |
9617 | rc = true; | |
9618 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
9619 | BP_PATH(bp)); | |
9620 | break; | |
9621 | } | |
9622 | } | |
9623 | ||
9624 | up(&bnx2x_prev_sem); | |
9625 | ||
9626 | return rc; | |
9627 | } | |
9628 | ||
c63da990 | 9629 | static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) |
452427b0 YM |
9630 | { |
9631 | struct bnx2x_prev_path_list *tmp_list; | |
9632 | int rc; | |
9633 | ||
ea4b3857 | 9634 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); |
452427b0 YM |
9635 | if (!tmp_list) { |
9636 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
9637 | return -ENOMEM; | |
9638 | } | |
9639 | ||
9640 | tmp_list->bus = bp->pdev->bus->number; | |
9641 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
9642 | tmp_list->path = BP_PATH(bp); | |
c63da990 | 9643 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; |
452427b0 YM |
9644 | |
9645 | rc = down_interruptible(&bnx2x_prev_sem); | |
9646 | if (rc) { | |
9647 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9648 | kfree(tmp_list); | |
9649 | } else { | |
9650 | BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n", | |
9651 | BP_PATH(bp)); | |
9652 | list_add(&tmp_list->list, &bnx2x_prev_list); | |
9653 | up(&bnx2x_prev_sem); | |
9654 | } | |
9655 | ||
9656 | return rc; | |
9657 | } | |
9658 | ||
0329aba1 | 9659 | static int bnx2x_do_flr(struct bnx2x *bp) |
452427b0 | 9660 | { |
2a80eebc | 9661 | int i; |
452427b0 YM |
9662 | u16 status; |
9663 | struct pci_dev *dev = bp->pdev; | |
9664 | ||
8eee694c YM |
9665 | |
9666 | if (CHIP_IS_E1x(bp)) { | |
9667 | BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); | |
9668 | return -EINVAL; | |
9669 | } | |
9670 | ||
9671 | /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ | |
9672 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
9673 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
9674 | bp->common.bc_ver); | |
9675 | return -EINVAL; | |
9676 | } | |
452427b0 | 9677 | |
452427b0 YM |
9678 | /* Wait for Transaction Pending bit clean */ |
9679 | for (i = 0; i < 4; i++) { | |
9680 | if (i) | |
9681 | msleep((1 << (i - 1)) * 100); | |
9682 | ||
2a80eebc | 9683 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
452427b0 YM |
9684 | if (!(status & PCI_EXP_DEVSTA_TRPND)) |
9685 | goto clear; | |
9686 | } | |
9687 | ||
9688 | dev_err(&dev->dev, | |
9689 | "transaction is not cleared; proceeding with reset anyway\n"); | |
9690 | ||
9691 | clear: | |
452427b0 | 9692 | |
8eee694c | 9693 | BNX2X_DEV_INFO("Initiating FLR\n"); |
452427b0 YM |
9694 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); |
9695 | ||
9696 | return 0; | |
9697 | } | |
9698 | ||
0329aba1 | 9699 | static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) |
452427b0 YM |
9700 | { |
9701 | int rc; | |
9702 | ||
9703 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
9704 | ||
9705 | /* Test if previous unload process was already finished for this path */ | |
9706 | if (bnx2x_prev_is_path_marked(bp)) | |
9707 | return bnx2x_prev_mcp_done(bp); | |
9708 | ||
9709 | /* If function has FLR capabilities, and existing FW version matches | |
9710 | * the one required, then FLR will be sufficient to clean any residue | |
9711 | * left by previous driver | |
9712 | */ | |
ad5afc89 | 9713 | rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION); |
8eee694c YM |
9714 | |
9715 | if (!rc) { | |
9716 | /* fw version is good */ | |
9717 | BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); | |
9718 | rc = bnx2x_do_flr(bp); | |
9719 | } | |
9720 | ||
9721 | if (!rc) { | |
9722 | /* FLR was performed */ | |
9723 | BNX2X_DEV_INFO("FLR successful\n"); | |
9724 | return 0; | |
9725 | } | |
9726 | ||
9727 | BNX2X_DEV_INFO("Could not FLR\n"); | |
452427b0 YM |
9728 | |
9729 | /* Close the MCP request, return failure*/ | |
9730 | rc = bnx2x_prev_mcp_done(bp); | |
9731 | if (!rc) | |
9732 | rc = BNX2X_PREV_WAIT_NEEDED; | |
9733 | ||
9734 | return rc; | |
9735 | } | |
9736 | ||
0329aba1 | 9737 | static int bnx2x_prev_unload_common(struct bnx2x *bp) |
452427b0 YM |
9738 | { |
9739 | u32 reset_reg, tmp_reg = 0, rc; | |
c63da990 | 9740 | bool prev_undi = false; |
452427b0 YM |
9741 | /* It is possible a previous function received 'common' answer, |
9742 | * but hasn't loaded yet, therefore creating a scenario of | |
9743 | * multiple functions receiving 'common' on the same path. | |
9744 | */ | |
9745 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
9746 | ||
9747 | if (bnx2x_prev_is_path_marked(bp)) | |
9748 | return bnx2x_prev_mcp_done(bp); | |
9749 | ||
9750 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
9751 | ||
9752 | /* Reset should be performed after BRB is emptied */ | |
9753 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
9754 | u32 timer_count = 1000; | |
452427b0 YM |
9755 | |
9756 | /* Close the MAC Rx to prevent BRB from filling up */ | |
9757 | bnx2x_prev_unload_close_mac(bp); | |
9758 | ||
9759 | /* Check if the UNDI driver was previously loaded | |
34f80b04 EG |
9760 | * UNDI driver initializes CID offset for normal bell to 0x7 |
9761 | */ | |
452427b0 YM |
9762 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); |
9763 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { | |
9764 | tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); | |
9765 | if (tmp_reg == 0x7) { | |
9766 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
9767 | prev_undi = true; | |
9768 | /* clear the UNDI indication */ | |
9769 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
34f80b04 | 9770 | } |
452427b0 YM |
9771 | } |
9772 | /* wait until BRB is empty */ | |
9773 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
9774 | while (timer_count) { | |
9775 | u32 prev_brb = tmp_reg; | |
34f80b04 | 9776 | |
452427b0 YM |
9777 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
9778 | if (!tmp_reg) | |
9779 | break; | |
619c5cb6 | 9780 | |
452427b0 | 9781 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 9782 | |
452427b0 YM |
9783 | /* reset timer as long as BRB actually gets emptied */ |
9784 | if (prev_brb > tmp_reg) | |
9785 | timer_count = 1000; | |
9786 | else | |
9787 | timer_count--; | |
da5a662a | 9788 | |
452427b0 YM |
9789 | /* If UNDI resides in memory, manually increment it */ |
9790 | if (prev_undi) | |
9791 | bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); | |
da5a662a | 9792 | |
452427b0 | 9793 | udelay(10); |
7a06a122 | 9794 | } |
452427b0 YM |
9795 | |
9796 | if (!timer_count) | |
9797 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
9798 | ||
34f80b04 | 9799 | } |
f16da43b | 9800 | |
452427b0 YM |
9801 | /* No packets are in the pipeline, path is ready for reset */ |
9802 | bnx2x_reset_common(bp); | |
9803 | ||
c63da990 | 9804 | rc = bnx2x_prev_mark_path(bp, prev_undi); |
452427b0 YM |
9805 | if (rc) { |
9806 | bnx2x_prev_mcp_done(bp); | |
9807 | return rc; | |
9808 | } | |
9809 | ||
9810 | return bnx2x_prev_mcp_done(bp); | |
9811 | } | |
9812 | ||
24f06716 AE |
9813 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
9814 | * and boot began, or when kdump kernel was loaded. Either case would invalidate | |
9815 | * the addresses of the transaction, resulting in was-error bit set in the pci | |
9816 | * causing all hw-to-host pcie transactions to timeout. If this happened we want | |
9817 | * to clear the interrupt which detected this from the pglueb and the was done | |
9818 | * bit | |
9819 | */ | |
0329aba1 | 9820 | static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp) |
24f06716 | 9821 | { |
4a25417c AE |
9822 | if (!CHIP_IS_E1x(bp)) { |
9823 | u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS); | |
9824 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { | |
9825 | BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing"); | |
9826 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, | |
9827 | 1 << BP_FUNC(bp)); | |
9828 | } | |
24f06716 AE |
9829 | } |
9830 | } | |
9831 | ||
0329aba1 | 9832 | static int bnx2x_prev_unload(struct bnx2x *bp) |
452427b0 YM |
9833 | { |
9834 | int time_counter = 10; | |
9835 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
c63da990 | 9836 | struct bnx2x_prev_path_list *prev_list; |
452427b0 YM |
9837 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); |
9838 | ||
24f06716 AE |
9839 | /* clear hw from errors which may have resulted from an interrupted |
9840 | * dmae transaction. | |
9841 | */ | |
9842 | bnx2x_prev_interrupted_dmae(bp); | |
9843 | ||
9844 | /* Release previously held locks */ | |
452427b0 YM |
9845 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
9846 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
9847 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
9848 | ||
9849 | hw_lock_val = (REG_RD(bp, hw_lock_reg)); | |
9850 | if (hw_lock_val) { | |
9851 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
9852 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
9853 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
9854 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
9855 | } | |
9856 | ||
9857 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
9858 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
9859 | } else | |
9860 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
9861 | ||
9862 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
9863 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
9864 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); | |
9865 | } | |
9866 | ||
9867 | ||
9868 | do { | |
9869 | /* Lock MCP using an unload request */ | |
9870 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
9871 | if (!fw) { | |
9872 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9873 | rc = -EBUSY; | |
9874 | break; | |
9875 | } | |
9876 | ||
9877 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { | |
9878 | rc = bnx2x_prev_unload_common(bp); | |
9879 | break; | |
9880 | } | |
9881 | ||
9882 | /* non-common reply from MCP night require looping */ | |
9883 | rc = bnx2x_prev_unload_uncommon(bp); | |
9884 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
9885 | break; | |
9886 | ||
9887 | msleep(20); | |
9888 | } while (--time_counter); | |
9889 | ||
9890 | if (!time_counter || rc) { | |
9891 | BNX2X_ERR("Failed unloading previous driver, aborting\n"); | |
9892 | rc = -EBUSY; | |
9893 | } | |
9894 | ||
c63da990 BW |
9895 | /* Mark function if its port was used to boot from SAN */ |
9896 | prev_list = bnx2x_prev_path_get_entry(bp); | |
9897 | if (prev_list && (prev_list->undi & (1 << BP_PORT(bp)))) | |
9898 | bp->link_params.feature_config_flags |= | |
9899 | FEATURE_CONFIG_BOOT_FROM_SAN; | |
9900 | ||
452427b0 YM |
9901 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); |
9902 | ||
9903 | return rc; | |
34f80b04 EG |
9904 | } |
9905 | ||
0329aba1 | 9906 | static void bnx2x_get_common_hwinfo(struct bnx2x *bp) |
34f80b04 | 9907 | { |
1d187b34 | 9908 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 9909 | u16 pmc; |
34f80b04 EG |
9910 | |
9911 | /* Get the chip revision id and number. */ | |
9912 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
9913 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
9914 | id = ((val & 0xffff) << 16); | |
9915 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
9916 | id |= ((val & 0xf) << 12); | |
9917 | val = REG_RD(bp, MISC_REG_CHIP_METAL); | |
9918 | id |= ((val & 0xff) << 4); | |
5a40e08e | 9919 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
9920 | id |= (val & 0xf); |
9921 | bp->common.chip_id = id; | |
523224a3 | 9922 | |
7e8e02df BW |
9923 | /* force 57811 according to MISC register */ |
9924 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
9925 | if (CHIP_IS_57810(bp)) | |
9926 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
9927 | (bp->common.chip_id & 0x0000FFFF); | |
9928 | else if (CHIP_IS_57810_MF(bp)) | |
9929 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
9930 | (bp->common.chip_id & 0x0000FFFF); | |
9931 | bp->common.chip_id |= 0x1; | |
9932 | } | |
9933 | ||
523224a3 DK |
9934 | /* Set doorbell size */ |
9935 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
9936 | ||
619c5cb6 | 9937 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
9938 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
9939 | if ((val & 1) == 0) | |
9940 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
9941 | else | |
9942 | val = (val >> 1) & 1; | |
9943 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
9944 | "2_PORT_MODE"); | |
9945 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
9946 | CHIP_2_PORT_MODE; | |
9947 | ||
9948 | if (CHIP_MODE_IS_4_PORT(bp)) | |
9949 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
9950 | else | |
9951 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
9952 | } else { | |
9953 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
9954 | bp->pfid = bp->pf_num; /* 0..7 */ | |
9955 | } | |
9956 | ||
51c1a580 MS |
9957 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
9958 | ||
f2e0899f DK |
9959 | bp->link_params.chip_id = bp->common.chip_id; |
9960 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 9961 | |
1c06328c EG |
9962 | val = (REG_RD(bp, 0x2874) & 0x55); |
9963 | if ((bp->common.chip_id & 0x1) || | |
9964 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
9965 | bp->flags |= ONE_PORT_FLAG; | |
9966 | BNX2X_DEV_INFO("single port device\n"); | |
9967 | } | |
9968 | ||
34f80b04 | 9969 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 9970 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
9971 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
9972 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
9973 | bp->common.flash_size, bp->common.flash_size); | |
9974 | ||
1b6e2ceb DK |
9975 | bnx2x_init_shmem(bp); |
9976 | ||
619c5cb6 VZ |
9977 | |
9978 | ||
f2e0899f DK |
9979 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
9980 | MISC_REG_GENERIC_CR_1 : | |
9981 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 9982 | |
34f80b04 | 9983 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 9984 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
b884d95b YR |
9985 | if (SHMEM2_RD(bp, size) > |
9986 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
9987 | bp->link_params.lfa_base = | |
9988 | REG_RD(bp, bp->common.shmem2_base + | |
9989 | (u32)offsetof(struct shmem2_region, | |
9990 | lfa_host_addr[BP_PORT(bp)])); | |
9991 | else | |
9992 | bp->link_params.lfa_base = 0; | |
2691d51d EG |
9993 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
9994 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 9995 | |
f2e0899f | 9996 | if (!bp->common.shmem_base) { |
34f80b04 EG |
9997 | BNX2X_DEV_INFO("MCP not active\n"); |
9998 | bp->flags |= NO_MCP_FLAG; | |
9999 | return; | |
10000 | } | |
10001 | ||
34f80b04 | 10002 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 10003 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
10004 | |
10005 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
10006 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
10007 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
10008 | ||
c2c8b03e EG |
10009 | bp->link_params.feature_config_flags = 0; |
10010 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
10011 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
10012 | bp->link_params.feature_config_flags |= | |
10013 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
10014 | else | |
10015 | bp->link_params.feature_config_flags &= | |
10016 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
10017 | ||
34f80b04 EG |
10018 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
10019 | bp->common.bc_ver = val; | |
10020 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
10021 | if (val < BNX2X_BC_VER) { | |
10022 | /* for now only warn | |
10023 | * later we might need to enforce this */ | |
51c1a580 MS |
10024 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
10025 | BNX2X_BC_VER, val); | |
34f80b04 | 10026 | } |
4d295db0 | 10027 | bp->link_params.feature_config_flags |= |
a22f0788 | 10028 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
10029 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
10030 | ||
a22f0788 YR |
10031 | bp->link_params.feature_config_flags |= |
10032 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
10033 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
10034 | bp->link_params.feature_config_flags |= |
10035 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
10036 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
10037 | bp->link_params.feature_config_flags |= |
10038 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
10039 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
55386fe8 YR |
10040 | |
10041 | bp->link_params.feature_config_flags |= | |
10042 | (val >= REQ_BC_VER_4_MT_SUPPORTED) ? | |
10043 | FEATURE_CONFIG_MT_SUPPORT : 0; | |
10044 | ||
0e898dd7 BW |
10045 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
10046 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 10047 | |
2e499d3c BW |
10048 | bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? |
10049 | BC_SUPPORTS_FCOE_FEATURES : 0; | |
10050 | ||
9876879f BW |
10051 | bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? |
10052 | BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; | |
1d187b34 BW |
10053 | boot_mode = SHMEM_RD(bp, |
10054 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
10055 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
10056 | switch (boot_mode) { | |
10057 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
10058 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
10059 | break; | |
10060 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
10061 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
10062 | break; | |
10063 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
10064 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
10065 | break; | |
10066 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
10067 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
10068 | break; | |
10069 | } | |
10070 | ||
f9a3ebbe DK |
10071 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
10072 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; | |
10073 | ||
72ce58c3 | 10074 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 10075 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
10076 | |
10077 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
10078 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
10079 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
10080 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
10081 | ||
cdaa7cb8 VZ |
10082 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
10083 | val, val2, val3, val4); | |
34f80b04 EG |
10084 | } |
10085 | ||
f2e0899f DK |
10086 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
10087 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
10088 | ||
0329aba1 | 10089 | static int bnx2x_get_igu_cam_info(struct bnx2x *bp) |
f2e0899f DK |
10090 | { |
10091 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
10092 | int igu_sb_id; |
10093 | u32 val; | |
6383c0b3 | 10094 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
10095 | |
10096 | bp->igu_base_sb = 0xff; | |
f2e0899f | 10097 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 10098 | int vn = BP_VN(bp); |
6383c0b3 | 10099 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
10100 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
10101 | FP_SB_MAX_E1x; | |
10102 | ||
10103 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
10104 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
10105 | ||
9b341bb1 | 10106 | return 0; |
f2e0899f DK |
10107 | } |
10108 | ||
10109 | /* IGU in normal mode - read CAM */ | |
10110 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
10111 | igu_sb_id++) { | |
10112 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
10113 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
10114 | continue; | |
10115 | fid = IGU_FID(val); | |
10116 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
10117 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
10118 | continue; | |
10119 | if (IGU_VEC(val) == 0) | |
10120 | /* default status block */ | |
10121 | bp->igu_dsb_id = igu_sb_id; | |
10122 | else { | |
10123 | if (bp->igu_base_sb == 0xff) | |
10124 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 10125 | igu_sb_cnt++; |
f2e0899f DK |
10126 | } |
10127 | } | |
10128 | } | |
619c5cb6 | 10129 | |
6383c0b3 | 10130 | #ifdef CONFIG_PCI_MSI |
185d4c8b AE |
10131 | /* Due to new PF resource allocation by MFW T7.4 and above, it's |
10132 | * optional that number of CAM entries will not be equal to the value | |
10133 | * advertised in PCI. | |
10134 | * Driver should use the minimal value of both as the actual status | |
10135 | * block count | |
619c5cb6 | 10136 | */ |
185d4c8b | 10137 | bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); |
6383c0b3 | 10138 | #endif |
619c5cb6 | 10139 | |
9b341bb1 | 10140 | if (igu_sb_cnt == 0) { |
f2e0899f | 10141 | BNX2X_ERR("CAM configuration error\n"); |
9b341bb1 BW |
10142 | return -EINVAL; |
10143 | } | |
10144 | ||
10145 | return 0; | |
f2e0899f DK |
10146 | } |
10147 | ||
1dd06ae8 | 10148 | static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) |
a2fbb9ea | 10149 | { |
a22f0788 YR |
10150 | int cfg_size = 0, idx, port = BP_PORT(bp); |
10151 | ||
10152 | /* Aggregation of supported attributes of all external phys */ | |
10153 | bp->port.supported[0] = 0; | |
10154 | bp->port.supported[1] = 0; | |
b7737c9b YR |
10155 | switch (bp->link_params.num_phys) { |
10156 | case 1: | |
a22f0788 YR |
10157 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
10158 | cfg_size = 1; | |
10159 | break; | |
b7737c9b | 10160 | case 2: |
a22f0788 YR |
10161 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
10162 | cfg_size = 1; | |
10163 | break; | |
10164 | case 3: | |
10165 | if (bp->link_params.multi_phy_config & | |
10166 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
10167 | bp->port.supported[1] = | |
10168 | bp->link_params.phy[EXT_PHY1].supported; | |
10169 | bp->port.supported[0] = | |
10170 | bp->link_params.phy[EXT_PHY2].supported; | |
10171 | } else { | |
10172 | bp->port.supported[0] = | |
10173 | bp->link_params.phy[EXT_PHY1].supported; | |
10174 | bp->port.supported[1] = | |
10175 | bp->link_params.phy[EXT_PHY2].supported; | |
10176 | } | |
10177 | cfg_size = 2; | |
10178 | break; | |
b7737c9b | 10179 | } |
a2fbb9ea | 10180 | |
a22f0788 | 10181 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 10182 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 10183 | SHMEM_RD(bp, |
a22f0788 YR |
10184 | dev_info.port_hw_config[port].external_phy_config), |
10185 | SHMEM_RD(bp, | |
10186 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 10187 | return; |
f85582f8 | 10188 | } |
a2fbb9ea | 10189 | |
619c5cb6 VZ |
10190 | if (CHIP_IS_E3(bp)) |
10191 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
10192 | else { | |
10193 | switch (switch_cfg) { | |
10194 | case SWITCH_CFG_1G: | |
10195 | bp->port.phy_addr = REG_RD( | |
10196 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
10197 | break; | |
10198 | case SWITCH_CFG_10G: | |
10199 | bp->port.phy_addr = REG_RD( | |
10200 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
10201 | break; | |
10202 | default: | |
10203 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
10204 | bp->port.link_config[0]); | |
10205 | return; | |
10206 | } | |
a2fbb9ea | 10207 | } |
619c5cb6 | 10208 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
10209 | /* mask what we support according to speed_cap_mask per configuration */ |
10210 | for (idx = 0; idx < cfg_size; idx++) { | |
10211 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 10212 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 10213 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 10214 | |
a22f0788 | 10215 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10216 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 10217 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 10218 | |
a22f0788 | 10219 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10220 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 10221 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 10222 | |
a22f0788 | 10223 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10224 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 10225 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 10226 | |
a22f0788 | 10227 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10228 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 10229 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 10230 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 10231 | |
a22f0788 | 10232 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10233 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 10234 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 10235 | |
a22f0788 | 10236 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10237 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 YR |
10238 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
10239 | ||
10240 | } | |
a2fbb9ea | 10241 | |
a22f0788 YR |
10242 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
10243 | bp->port.supported[1]); | |
a2fbb9ea ET |
10244 | } |
10245 | ||
0329aba1 | 10246 | static void bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 10247 | { |
a22f0788 YR |
10248 | u32 link_config, idx, cfg_size = 0; |
10249 | bp->port.advertising[0] = 0; | |
10250 | bp->port.advertising[1] = 0; | |
10251 | switch (bp->link_params.num_phys) { | |
10252 | case 1: | |
10253 | case 2: | |
10254 | cfg_size = 1; | |
10255 | break; | |
10256 | case 3: | |
10257 | cfg_size = 2; | |
10258 | break; | |
10259 | } | |
10260 | for (idx = 0; idx < cfg_size; idx++) { | |
10261 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
10262 | link_config = bp->port.link_config[idx]; | |
10263 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 10264 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
10265 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
10266 | bp->link_params.req_line_speed[idx] = | |
10267 | SPEED_AUTO_NEG; | |
10268 | bp->port.advertising[idx] |= | |
10269 | bp->port.supported[idx]; | |
10bd1f24 MY |
10270 | if (bp->link_params.phy[EXT_PHY1].type == |
10271 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
10272 | bp->port.advertising[idx] |= | |
10273 | (SUPPORTED_100baseT_Half | | |
10274 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
10275 | } else { |
10276 | /* force 10G, no AN */ | |
a22f0788 YR |
10277 | bp->link_params.req_line_speed[idx] = |
10278 | SPEED_10000; | |
10279 | bp->port.advertising[idx] |= | |
10280 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 10281 | ADVERTISED_FIBRE); |
a22f0788 | 10282 | continue; |
f85582f8 DK |
10283 | } |
10284 | break; | |
a2fbb9ea | 10285 | |
f85582f8 | 10286 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
10287 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
10288 | bp->link_params.req_line_speed[idx] = | |
10289 | SPEED_10; | |
10290 | bp->port.advertising[idx] |= | |
10291 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
10292 | ADVERTISED_TP); |
10293 | } else { | |
51c1a580 | 10294 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 10295 | link_config, |
a22f0788 | 10296 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
10297 | return; |
10298 | } | |
10299 | break; | |
a2fbb9ea | 10300 | |
f85582f8 | 10301 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
10302 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
10303 | bp->link_params.req_line_speed[idx] = | |
10304 | SPEED_10; | |
10305 | bp->link_params.req_duplex[idx] = | |
10306 | DUPLEX_HALF; | |
10307 | bp->port.advertising[idx] |= | |
10308 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
10309 | ADVERTISED_TP); |
10310 | } else { | |
51c1a580 | 10311 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
10312 | link_config, |
10313 | bp->link_params.speed_cap_mask[idx]); | |
10314 | return; | |
10315 | } | |
10316 | break; | |
a2fbb9ea | 10317 | |
f85582f8 DK |
10318 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
10319 | if (bp->port.supported[idx] & | |
10320 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
10321 | bp->link_params.req_line_speed[idx] = |
10322 | SPEED_100; | |
10323 | bp->port.advertising[idx] |= | |
10324 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
10325 | ADVERTISED_TP); |
10326 | } else { | |
51c1a580 | 10327 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
10328 | link_config, |
10329 | bp->link_params.speed_cap_mask[idx]); | |
10330 | return; | |
10331 | } | |
10332 | break; | |
a2fbb9ea | 10333 | |
f85582f8 DK |
10334 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
10335 | if (bp->port.supported[idx] & | |
10336 | SUPPORTED_100baseT_Half) { | |
10337 | bp->link_params.req_line_speed[idx] = | |
10338 | SPEED_100; | |
10339 | bp->link_params.req_duplex[idx] = | |
10340 | DUPLEX_HALF; | |
a22f0788 YR |
10341 | bp->port.advertising[idx] |= |
10342 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
10343 | ADVERTISED_TP); |
10344 | } else { | |
51c1a580 | 10345 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10346 | link_config, |
10347 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10348 | return; |
10349 | } | |
10350 | break; | |
a2fbb9ea | 10351 | |
f85582f8 | 10352 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
10353 | if (bp->port.supported[idx] & |
10354 | SUPPORTED_1000baseT_Full) { | |
10355 | bp->link_params.req_line_speed[idx] = | |
10356 | SPEED_1000; | |
10357 | bp->port.advertising[idx] |= | |
10358 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
10359 | ADVERTISED_TP); |
10360 | } else { | |
51c1a580 | 10361 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10362 | link_config, |
10363 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10364 | return; |
10365 | } | |
10366 | break; | |
a2fbb9ea | 10367 | |
f85582f8 | 10368 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
10369 | if (bp->port.supported[idx] & |
10370 | SUPPORTED_2500baseX_Full) { | |
10371 | bp->link_params.req_line_speed[idx] = | |
10372 | SPEED_2500; | |
10373 | bp->port.advertising[idx] |= | |
10374 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 10375 | ADVERTISED_TP); |
f85582f8 | 10376 | } else { |
51c1a580 | 10377 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10378 | link_config, |
f85582f8 DK |
10379 | bp->link_params.speed_cap_mask[idx]); |
10380 | return; | |
10381 | } | |
10382 | break; | |
a2fbb9ea | 10383 | |
f85582f8 | 10384 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
10385 | if (bp->port.supported[idx] & |
10386 | SUPPORTED_10000baseT_Full) { | |
10387 | bp->link_params.req_line_speed[idx] = | |
10388 | SPEED_10000; | |
10389 | bp->port.advertising[idx] |= | |
10390 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 10391 | ADVERTISED_FIBRE); |
f85582f8 | 10392 | } else { |
51c1a580 | 10393 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10394 | link_config, |
f85582f8 DK |
10395 | bp->link_params.speed_cap_mask[idx]); |
10396 | return; | |
10397 | } | |
10398 | break; | |
3c9ada22 YR |
10399 | case PORT_FEATURE_LINK_SPEED_20G: |
10400 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 10401 | |
3c9ada22 | 10402 | break; |
f85582f8 | 10403 | default: |
51c1a580 | 10404 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 10405 | link_config); |
f85582f8 DK |
10406 | bp->link_params.req_line_speed[idx] = |
10407 | SPEED_AUTO_NEG; | |
10408 | bp->port.advertising[idx] = | |
10409 | bp->port.supported[idx]; | |
10410 | break; | |
10411 | } | |
a2fbb9ea | 10412 | |
a22f0788 | 10413 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 10414 | PORT_FEATURE_FLOW_CONTROL_MASK); |
cd1dfce2 YM |
10415 | if (bp->link_params.req_flow_ctrl[idx] == |
10416 | BNX2X_FLOW_CTRL_AUTO) { | |
10417 | if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) | |
10418 | bp->link_params.req_flow_ctrl[idx] = | |
10419 | BNX2X_FLOW_CTRL_NONE; | |
10420 | else | |
10421 | bnx2x_set_requested_fc(bp); | |
a22f0788 | 10422 | } |
a2fbb9ea | 10423 | |
51c1a580 | 10424 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
10425 | bp->link_params.req_line_speed[idx], |
10426 | bp->link_params.req_duplex[idx], | |
10427 | bp->link_params.req_flow_ctrl[idx], | |
10428 | bp->port.advertising[idx]); | |
10429 | } | |
a2fbb9ea ET |
10430 | } |
10431 | ||
0329aba1 | 10432 | static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
e665bfda MC |
10433 | { |
10434 | mac_hi = cpu_to_be16(mac_hi); | |
10435 | mac_lo = cpu_to_be32(mac_lo); | |
10436 | memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); | |
10437 | memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); | |
10438 | } | |
10439 | ||
0329aba1 | 10440 | static void bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 10441 | { |
34f80b04 | 10442 | int port = BP_PORT(bp); |
589abe3a | 10443 | u32 config; |
c8c60d88 | 10444 | u32 ext_phy_type, ext_phy_config, eee_mode; |
a2fbb9ea | 10445 | |
c18487ee | 10446 | bp->link_params.bp = bp; |
34f80b04 | 10447 | bp->link_params.port = port; |
c18487ee | 10448 | |
c18487ee | 10449 | bp->link_params.lane_config = |
a2fbb9ea | 10450 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 10451 | |
a22f0788 | 10452 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea ET |
10453 | SHMEM_RD(bp, |
10454 | dev_info.port_hw_config[port].speed_capability_mask); | |
a22f0788 YR |
10455 | bp->link_params.speed_cap_mask[1] = |
10456 | SHMEM_RD(bp, | |
10457 | dev_info.port_hw_config[port].speed_capability_mask2); | |
10458 | bp->port.link_config[0] = | |
a2fbb9ea ET |
10459 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
10460 | ||
a22f0788 YR |
10461 | bp->port.link_config[1] = |
10462 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 10463 | |
a22f0788 YR |
10464 | bp->link_params.multi_phy_config = |
10465 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
10466 | /* If the device is capable of WoL, set the default state according |
10467 | * to the HW | |
10468 | */ | |
4d295db0 | 10469 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
10470 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
10471 | (config & PORT_FEATURE_WOL_ENABLED)); | |
10472 | ||
51c1a580 | 10473 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 10474 | bp->link_params.lane_config, |
a22f0788 YR |
10475 | bp->link_params.speed_cap_mask[0], |
10476 | bp->port.link_config[0]); | |
a2fbb9ea | 10477 | |
a22f0788 | 10478 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 10479 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 10480 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 10481 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
10482 | |
10483 | bnx2x_link_settings_requested(bp); | |
10484 | ||
01cd4528 EG |
10485 | /* |
10486 | * If connected directly, work with the internal PHY, otherwise, work | |
10487 | * with the external PHY | |
10488 | */ | |
b7737c9b YR |
10489 | ext_phy_config = |
10490 | SHMEM_RD(bp, | |
10491 | dev_info.port_hw_config[port].external_phy_config); | |
10492 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 10493 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 10494 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
10495 | |
10496 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
10497 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
10498 | bp->mdio.prtad = | |
b7737c9b | 10499 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d | 10500 | |
c8c60d88 YM |
10501 | /* Configure link feature according to nvram value */ |
10502 | eee_mode = (((SHMEM_RD(bp, dev_info. | |
10503 | port_feature_config[port].eee_power_mode)) & | |
10504 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
10505 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
10506 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { | |
10507 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | | |
10508 | EEE_MODE_ENABLE_LPI | | |
10509 | EEE_MODE_OUTPUT_TIME; | |
10510 | } else { | |
10511 | bp->link_params.eee_mode = 0; | |
10512 | } | |
0793f83f | 10513 | } |
01cd4528 | 10514 | |
b306f5ed | 10515 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 10516 | { |
9e62e912 | 10517 | u32 no_flags = NO_ISCSI_FLAG; |
bf61ee14 | 10518 | int port = BP_PORT(bp); |
2ba45142 | 10519 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 10520 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 10521 | |
55c11941 MS |
10522 | if (!CNIC_SUPPORT(bp)) { |
10523 | bp->flags |= no_flags; | |
10524 | return; | |
10525 | } | |
10526 | ||
b306f5ed | 10527 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
10528 | bp->cnic_eth_dev.max_iscsi_conn = |
10529 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
10530 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
10531 | ||
b306f5ed DK |
10532 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
10533 | bp->cnic_eth_dev.max_iscsi_conn); | |
10534 | ||
10535 | /* | |
10536 | * If maximum allowed number of connections is zero - | |
10537 | * disable the feature. | |
10538 | */ | |
10539 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 10540 | bp->flags |= no_flags; |
55c11941 | 10541 | |
b306f5ed DK |
10542 | } |
10543 | ||
0329aba1 | 10544 | static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) |
9e62e912 DK |
10545 | { |
10546 | /* Port info */ | |
10547 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10548 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
10549 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10550 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
10551 | ||
10552 | /* Node info */ | |
10553 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10554 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
10555 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10556 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
10557 | } | |
0329aba1 | 10558 | static void bnx2x_get_fcoe_info(struct bnx2x *bp) |
b306f5ed DK |
10559 | { |
10560 | int port = BP_PORT(bp); | |
10561 | int func = BP_ABS_FUNC(bp); | |
b306f5ed DK |
10562 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
10563 | drv_lic_key[port].max_fcoe_conn); | |
10564 | ||
55c11941 MS |
10565 | if (!CNIC_SUPPORT(bp)) { |
10566 | bp->flags |= NO_FCOE_FLAG; | |
10567 | return; | |
10568 | } | |
10569 | ||
b306f5ed | 10570 | /* Get the number of maximum allowed FCoE connections */ |
2ba45142 VZ |
10571 | bp->cnic_eth_dev.max_fcoe_conn = |
10572 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
10573 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
10574 | ||
bf61ee14 VZ |
10575 | /* Read the WWN: */ |
10576 | if (!IS_MF(bp)) { | |
10577 | /* Port info */ | |
10578 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10579 | SHMEM_RD(bp, | |
10580 | dev_info.port_hw_config[port]. | |
10581 | fcoe_wwn_port_name_upper); | |
10582 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10583 | SHMEM_RD(bp, | |
10584 | dev_info.port_hw_config[port]. | |
10585 | fcoe_wwn_port_name_lower); | |
10586 | ||
10587 | /* Node info */ | |
10588 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10589 | SHMEM_RD(bp, | |
10590 | dev_info.port_hw_config[port]. | |
10591 | fcoe_wwn_node_name_upper); | |
10592 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10593 | SHMEM_RD(bp, | |
10594 | dev_info.port_hw_config[port]. | |
10595 | fcoe_wwn_node_name_lower); | |
10596 | } else if (!IS_MF_SD(bp)) { | |
bf61ee14 VZ |
10597 | /* |
10598 | * Read the WWN info only if the FCoE feature is enabled for | |
10599 | * this function. | |
10600 | */ | |
7b5342d9 | 10601 | if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) |
9e62e912 DK |
10602 | bnx2x_get_ext_wwn_info(bp, func); |
10603 | ||
382e513a | 10604 | } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) { |
9e62e912 | 10605 | bnx2x_get_ext_wwn_info(bp, func); |
382e513a | 10606 | } |
bf61ee14 | 10607 | |
b306f5ed | 10608 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 10609 | |
bf61ee14 VZ |
10610 | /* |
10611 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
10612 | * disable the feature. |
10613 | */ | |
2ba45142 VZ |
10614 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
10615 | bp->flags |= NO_FCOE_FLAG; | |
10616 | } | |
b306f5ed | 10617 | |
0329aba1 | 10618 | static void bnx2x_get_cnic_info(struct bnx2x *bp) |
b306f5ed DK |
10619 | { |
10620 | /* | |
10621 | * iSCSI may be dynamically disabled but reading | |
10622 | * info here we will decrease memory usage by driver | |
10623 | * if the feature is disabled for good | |
10624 | */ | |
10625 | bnx2x_get_iscsi_info(bp); | |
10626 | bnx2x_get_fcoe_info(bp); | |
10627 | } | |
2ba45142 | 10628 | |
0329aba1 | 10629 | static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) |
0793f83f DK |
10630 | { |
10631 | u32 val, val2; | |
10632 | int func = BP_ABS_FUNC(bp); | |
10633 | int port = BP_PORT(bp); | |
2ba45142 VZ |
10634 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; |
10635 | u8 *fip_mac = bp->fip_mac; | |
0793f83f | 10636 | |
55c11941 MS |
10637 | if (IS_MF(bp)) { |
10638 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 10639 | * FCoE MAC then the appropriate feature should be disabled. |
55c11941 MS |
10640 | * In non SD mode features configuration comes from struct |
10641 | * func_ext_config. | |
2ba45142 | 10642 | */ |
55c11941 | 10643 | if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) { |
0793f83f DK |
10644 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
10645 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
10646 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 10647 | iscsi_mac_addr_upper); |
0793f83f | 10648 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 10649 | iscsi_mac_addr_lower); |
2ba45142 | 10650 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
55c11941 MS |
10651 | BNX2X_DEV_INFO |
10652 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
10653 | } else { | |
2ba45142 | 10654 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
55c11941 | 10655 | } |
2ba45142 VZ |
10656 | |
10657 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
10658 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 10659 | fcoe_mac_addr_upper); |
2ba45142 | 10660 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 10661 | fcoe_mac_addr_lower); |
2ba45142 | 10662 | bnx2x_set_mac_buf(fip_mac, val, val2); |
55c11941 MS |
10663 | BNX2X_DEV_INFO |
10664 | ("Read FCoE L2 MAC: %pM\n", fip_mac); | |
10665 | } else { | |
2ba45142 | 10666 | bp->flags |= NO_FCOE_FLAG; |
55c11941 | 10667 | } |
a3348722 BW |
10668 | |
10669 | bp->mf_ext_config = cfg; | |
10670 | ||
9e62e912 | 10671 | } else { /* SD MODE */ |
55c11941 MS |
10672 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { |
10673 | /* use primary mac as iscsi mac */ | |
10674 | memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); | |
10675 | ||
10676 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
10677 | BNX2X_DEV_INFO | |
10678 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
10679 | } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { | |
10680 | /* use primary mac as fip mac */ | |
10681 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); | |
10682 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
10683 | BNX2X_DEV_INFO | |
10684 | ("Read FIP MAC: %pM\n", fip_mac); | |
614c76df | 10685 | } |
0793f83f | 10686 | } |
a3348722 | 10687 | |
55c11941 MS |
10688 | if (IS_MF_STORAGE_SD(bp)) |
10689 | /* Zero primary MAC configuration */ | |
10690 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
10691 | ||
a3348722 BW |
10692 | if (IS_MF_FCOE_AFEX(bp)) |
10693 | /* use FIP MAC as primary MAC */ | |
10694 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); | |
10695 | ||
0793f83f | 10696 | } else { |
0793f83f | 10697 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 10698 | iscsi_mac_upper); |
0793f83f | 10699 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 10700 | iscsi_mac_lower); |
2ba45142 | 10701 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
10702 | |
10703 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
55c11941 | 10704 | fcoe_fip_mac_upper); |
c03bd39c | 10705 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 10706 | fcoe_fip_mac_lower); |
c03bd39c | 10707 | bnx2x_set_mac_buf(fip_mac, val, val2); |
0793f83f DK |
10708 | } |
10709 | ||
55c11941 | 10710 | /* Disable iSCSI OOO if MAC configuration is invalid. */ |
426b9241 | 10711 | if (!is_valid_ether_addr(iscsi_mac)) { |
55c11941 | 10712 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
426b9241 DK |
10713 | memset(iscsi_mac, 0, ETH_ALEN); |
10714 | } | |
10715 | ||
55c11941 | 10716 | /* Disable FCoE if MAC configuration is invalid. */ |
426b9241 DK |
10717 | if (!is_valid_ether_addr(fip_mac)) { |
10718 | bp->flags |= NO_FCOE_FLAG; | |
10719 | memset(bp->fip_mac, 0, ETH_ALEN); | |
10720 | } | |
55c11941 MS |
10721 | } |
10722 | ||
0329aba1 | 10723 | static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
55c11941 MS |
10724 | { |
10725 | u32 val, val2; | |
10726 | int func = BP_ABS_FUNC(bp); | |
10727 | int port = BP_PORT(bp); | |
10728 | ||
10729 | /* Zero primary MAC configuration */ | |
10730 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
10731 | ||
10732 | if (BP_NOMCP(bp)) { | |
10733 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
10734 | eth_hw_addr_random(bp->dev); | |
10735 | } else if (IS_MF(bp)) { | |
10736 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
10737 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
10738 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
10739 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
10740 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
10741 | ||
10742 | if (CNIC_SUPPORT(bp)) | |
10743 | bnx2x_get_cnic_mac_hwinfo(bp); | |
10744 | } else { | |
10745 | /* in SF read MACs from port configuration */ | |
10746 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
10747 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
10748 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
10749 | ||
10750 | if (CNIC_SUPPORT(bp)) | |
10751 | bnx2x_get_cnic_mac_hwinfo(bp); | |
10752 | } | |
10753 | ||
10754 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
10755 | memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); | |
619c5cb6 | 10756 | |
614c76df | 10757 | if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) |
619c5cb6 | 10758 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10759 | "bad Ethernet MAC address configuration: %pM\n" |
10760 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 10761 | bp->dev->dev_addr); |
7964211d | 10762 | } |
51c1a580 | 10763 | |
0329aba1 | 10764 | static bool bnx2x_get_dropless_info(struct bnx2x *bp) |
7964211d YM |
10765 | { |
10766 | int tmp; | |
10767 | u32 cfg; | |
51c1a580 | 10768 | |
7964211d YM |
10769 | if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { |
10770 | /* Take function: tmp = func */ | |
10771 | tmp = BP_ABS_FUNC(bp); | |
10772 | cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); | |
10773 | cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); | |
10774 | } else { | |
10775 | /* Take port: tmp = port */ | |
10776 | tmp = BP_PORT(bp); | |
10777 | cfg = SHMEM_RD(bp, | |
10778 | dev_info.port_hw_config[tmp].generic_features); | |
10779 | cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); | |
10780 | } | |
10781 | return cfg; | |
34f80b04 EG |
10782 | } |
10783 | ||
0329aba1 | 10784 | static int bnx2x_get_hwinfo(struct bnx2x *bp) |
34f80b04 | 10785 | { |
0793f83f | 10786 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 10787 | int vn; |
0793f83f | 10788 | u32 val = 0; |
34f80b04 | 10789 | int rc = 0; |
a2fbb9ea | 10790 | |
34f80b04 | 10791 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 10792 | |
6383c0b3 AE |
10793 | /* |
10794 | * initialize IGU parameters | |
10795 | */ | |
f2e0899f DK |
10796 | if (CHIP_IS_E1x(bp)) { |
10797 | bp->common.int_block = INT_BLOCK_HC; | |
10798 | ||
10799 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
10800 | bp->igu_base_sb = 0; | |
f2e0899f DK |
10801 | } else { |
10802 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 DK |
10803 | |
10804 | /* do not allow device reset during IGU info preocessing */ | |
10805 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | |
10806 | ||
f2e0899f | 10807 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
10808 | |
10809 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
10810 | int tout = 5000; | |
10811 | ||
10812 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
10813 | ||
10814 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
10815 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
10816 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
10817 | ||
10818 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
10819 | tout--; | |
10820 | usleep_range(1000, 1000); | |
10821 | } | |
10822 | ||
10823 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
10824 | dev_err(&bp->pdev->dev, | |
10825 | "FORCING Normal Mode failed!!!\n"); | |
9b341bb1 BW |
10826 | bnx2x_release_hw_lock(bp, |
10827 | HW_LOCK_RESOURCE_RESET); | |
619c5cb6 VZ |
10828 | return -EPERM; |
10829 | } | |
10830 | } | |
10831 | ||
f2e0899f | 10832 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 10833 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
10834 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
10835 | } else | |
619c5cb6 | 10836 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 10837 | |
9b341bb1 | 10838 | rc = bnx2x_get_igu_cam_info(bp); |
7a06a122 | 10839 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
9b341bb1 BW |
10840 | if (rc) |
10841 | return rc; | |
f2e0899f | 10842 | } |
619c5cb6 VZ |
10843 | |
10844 | /* | |
10845 | * set base FW non-default (fast path) status block id, this value is | |
10846 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
10847 | * determine the id used by the FW. | |
10848 | */ | |
10849 | if (CHIP_IS_E1x(bp)) | |
10850 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
10851 | else /* | |
10852 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
10853 | * the same queue are indicated on the same IGU SB). So we prefer | |
10854 | * FW and IGU SBs to be the same value. | |
10855 | */ | |
10856 | bp->base_fw_ndsb = bp->igu_base_sb; | |
10857 | ||
10858 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
10859 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
10860 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
10861 | |
10862 | /* | |
10863 | * Initialize MF configuration | |
10864 | */ | |
523224a3 | 10865 | |
fb3bff17 DK |
10866 | bp->mf_ov = 0; |
10867 | bp->mf_mode = 0; | |
3395a033 | 10868 | vn = BP_VN(bp); |
0793f83f | 10869 | |
f2e0899f | 10870 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
10871 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
10872 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
10873 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
10874 | ||
f2e0899f DK |
10875 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
10876 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
10877 | else | |
10878 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
10879 | offsetof(struct shmem_region, func_mb) + |
10880 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
10881 | /* |
10882 | * get mf configuration: | |
25985edc | 10883 | * 1. existence of MF configuration |
0793f83f DK |
10884 | * 2. MAC address must be legal (check only upper bytes) |
10885 | * for Switch-Independent mode; | |
10886 | * OVLAN must be legal for Switch-Dependent mode | |
10887 | * 3. SF_MODE configures specific MF mode | |
10888 | */ | |
10889 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10890 | /* get mf configuration */ | |
10891 | val = SHMEM_RD(bp, | |
10892 | dev_info.shared_feature_config.config); | |
10893 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
10894 | ||
10895 | switch (val) { | |
10896 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
10897 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
10898 | mac_upper); | |
10899 | /* check for legal mac (upper bytes)*/ | |
10900 | if (val != 0xffff) { | |
10901 | bp->mf_mode = MULTI_FUNCTION_SI; | |
10902 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10903 | func_mf_config[func].config); | |
10904 | } else | |
51c1a580 | 10905 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); |
0793f83f | 10906 | break; |
a3348722 BW |
10907 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
10908 | if ((!CHIP_IS_E1x(bp)) && | |
10909 | (MF_CFG_RD(bp, func_mf_config[func]. | |
10910 | mac_upper) != 0xffff) && | |
10911 | (SHMEM2_HAS(bp, | |
10912 | afex_driver_support))) { | |
10913 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
10914 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10915 | func_mf_config[func].config); | |
10916 | } else { | |
10917 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
10918 | } | |
10919 | break; | |
0793f83f DK |
10920 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
10921 | /* get OV configuration */ | |
10922 | val = MF_CFG_RD(bp, | |
10923 | func_mf_config[FUNC_0].e1hov_tag); | |
10924 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
10925 | ||
10926 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
10927 | bp->mf_mode = MULTI_FUNCTION_SD; | |
10928 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
10929 | func_mf_config[func].config); | |
10930 | } else | |
754a2f52 | 10931 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f DK |
10932 | break; |
10933 | default: | |
10934 | /* Unknown configuration: reset mf_config */ | |
10935 | bp->mf_config[vn] = 0; | |
51c1a580 | 10936 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
10937 | } |
10938 | } | |
a2fbb9ea | 10939 | |
2691d51d | 10940 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 10941 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 10942 | |
0793f83f DK |
10943 | switch (bp->mf_mode) { |
10944 | case MULTI_FUNCTION_SD: | |
10945 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
10946 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 10947 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 10948 | bp->mf_ov = val; |
619c5cb6 VZ |
10949 | bp->path_has_ovlan = true; |
10950 | ||
51c1a580 MS |
10951 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
10952 | func, bp->mf_ov, bp->mf_ov); | |
2691d51d | 10953 | } else { |
619c5cb6 | 10954 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10955 | "No valid MF OV for func %d, aborting\n", |
10956 | func); | |
619c5cb6 | 10957 | return -EPERM; |
34f80b04 | 10958 | } |
0793f83f | 10959 | break; |
a3348722 BW |
10960 | case MULTI_FUNCTION_AFEX: |
10961 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
10962 | break; | |
0793f83f | 10963 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
10964 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
10965 | func); | |
0793f83f DK |
10966 | break; |
10967 | default: | |
10968 | if (vn) { | |
619c5cb6 | 10969 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10970 | "VN %d is in a single function mode, aborting\n", |
10971 | vn); | |
619c5cb6 | 10972 | return -EPERM; |
2691d51d | 10973 | } |
0793f83f | 10974 | break; |
34f80b04 | 10975 | } |
0793f83f | 10976 | |
619c5cb6 VZ |
10977 | /* check if other port on the path needs ovlan: |
10978 | * Since MF configuration is shared between ports | |
10979 | * Possible mixed modes are only | |
10980 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
10981 | */ | |
10982 | if (CHIP_MODE_IS_4_PORT(bp) && | |
10983 | !bp->path_has_ovlan && | |
10984 | !IS_MF(bp) && | |
10985 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10986 | u8 other_port = !BP_PORT(bp); | |
10987 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
10988 | val = MF_CFG_RD(bp, | |
10989 | func_mf_config[other_func].e1hov_tag); | |
10990 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
10991 | bp->path_has_ovlan = true; | |
10992 | } | |
34f80b04 | 10993 | } |
a2fbb9ea | 10994 | |
f2e0899f DK |
10995 | /* adjust igu_sb_cnt to MF for E1x */ |
10996 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
10997 | bp->igu_sb_cnt /= E1HVN_MAX; |
10998 | ||
619c5cb6 VZ |
10999 | /* port info */ |
11000 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 11001 | |
0793f83f DK |
11002 | /* Get MAC addresses */ |
11003 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 11004 | |
2ba45142 | 11005 | bnx2x_get_cnic_info(bp); |
2ba45142 | 11006 | |
34f80b04 EG |
11007 | return rc; |
11008 | } | |
11009 | ||
0329aba1 | 11010 | static void bnx2x_read_fwinfo(struct bnx2x *bp) |
34f24c7f VZ |
11011 | { |
11012 | int cnt, i, block_end, rodi; | |
fcdf95cb | 11013 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
11014 | char str_id_reg[VENDOR_ID_LEN+1]; |
11015 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
11016 | char *vpd_data; |
11017 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
11018 | u8 len; |
11019 | ||
fcdf95cb | 11020 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
11021 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
11022 | ||
11023 | if (cnt < BNX2X_VPD_LEN) | |
11024 | goto out_not_found; | |
11025 | ||
fcdf95cb BW |
11026 | /* VPD RO tag should be first tag after identifier string, hence |
11027 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
11028 | */ | |
11029 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
11030 | PCI_VPD_LRDT_RO_DATA); |
11031 | if (i < 0) | |
11032 | goto out_not_found; | |
11033 | ||
34f24c7f | 11034 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 11035 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
11036 | |
11037 | i += PCI_VPD_LRDT_TAG_SIZE; | |
11038 | ||
fcdf95cb BW |
11039 | if (block_end > BNX2X_VPD_LEN) { |
11040 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
11041 | if (vpd_extended_data == NULL) | |
11042 | goto out_not_found; | |
11043 | ||
11044 | /* read rest of vpd image into vpd_extended_data */ | |
11045 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
11046 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
11047 | block_end - BNX2X_VPD_LEN, | |
11048 | vpd_extended_data + BNX2X_VPD_LEN); | |
11049 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
11050 | goto out_not_found; | |
11051 | vpd_data = vpd_extended_data; | |
11052 | } else | |
11053 | vpd_data = vpd_start; | |
11054 | ||
11055 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
11056 | |
11057 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
11058 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
11059 | if (rodi < 0) | |
11060 | goto out_not_found; | |
11061 | ||
11062 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
11063 | ||
11064 | if (len != VENDOR_ID_LEN) | |
11065 | goto out_not_found; | |
11066 | ||
11067 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11068 | ||
11069 | /* vendor specific info */ | |
11070 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
11071 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
11072 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
11073 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
11074 | ||
11075 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
11076 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
11077 | if (rodi >= 0) { | |
11078 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
11079 | ||
11080 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11081 | ||
11082 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
11083 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
11084 | bp->fw_ver[len] = ' '; | |
11085 | } | |
11086 | } | |
fcdf95cb | 11087 | kfree(vpd_extended_data); |
34f24c7f VZ |
11088 | return; |
11089 | } | |
11090 | out_not_found: | |
fcdf95cb | 11091 | kfree(vpd_extended_data); |
34f24c7f VZ |
11092 | return; |
11093 | } | |
11094 | ||
0329aba1 | 11095 | static void bnx2x_set_modes_bitmap(struct bnx2x *bp) |
619c5cb6 VZ |
11096 | { |
11097 | u32 flags = 0; | |
11098 | ||
11099 | if (CHIP_REV_IS_FPGA(bp)) | |
11100 | SET_FLAGS(flags, MODE_FPGA); | |
11101 | else if (CHIP_REV_IS_EMUL(bp)) | |
11102 | SET_FLAGS(flags, MODE_EMUL); | |
11103 | else | |
11104 | SET_FLAGS(flags, MODE_ASIC); | |
11105 | ||
11106 | if (CHIP_MODE_IS_4_PORT(bp)) | |
11107 | SET_FLAGS(flags, MODE_PORT4); | |
11108 | else | |
11109 | SET_FLAGS(flags, MODE_PORT2); | |
11110 | ||
11111 | if (CHIP_IS_E2(bp)) | |
11112 | SET_FLAGS(flags, MODE_E2); | |
11113 | else if (CHIP_IS_E3(bp)) { | |
11114 | SET_FLAGS(flags, MODE_E3); | |
11115 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
11116 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
11117 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
11118 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
11119 | } |
11120 | ||
11121 | if (IS_MF(bp)) { | |
11122 | SET_FLAGS(flags, MODE_MF); | |
11123 | switch (bp->mf_mode) { | |
11124 | case MULTI_FUNCTION_SD: | |
11125 | SET_FLAGS(flags, MODE_MF_SD); | |
11126 | break; | |
11127 | case MULTI_FUNCTION_SI: | |
11128 | SET_FLAGS(flags, MODE_MF_SI); | |
11129 | break; | |
a3348722 BW |
11130 | case MULTI_FUNCTION_AFEX: |
11131 | SET_FLAGS(flags, MODE_MF_AFEX); | |
11132 | break; | |
619c5cb6 VZ |
11133 | } |
11134 | } else | |
11135 | SET_FLAGS(flags, MODE_SF); | |
11136 | ||
11137 | #if defined(__LITTLE_ENDIAN) | |
11138 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
11139 | #else /*(__BIG_ENDIAN)*/ | |
11140 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
11141 | #endif | |
11142 | INIT_MODE_FLAGS(bp) = flags; | |
11143 | } | |
11144 | ||
0329aba1 | 11145 | static int bnx2x_init_bp(struct bnx2x *bp) |
34f80b04 | 11146 | { |
f2e0899f | 11147 | int func; |
34f80b04 EG |
11148 | int rc; |
11149 | ||
34f80b04 | 11150 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 11151 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 11152 | spin_lock_init(&bp->stats_lock); |
55c11941 | 11153 | |
a2fbb9ea | 11154 | |
1cf167f2 | 11155 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 11156 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 11157 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
1ab4434c AE |
11158 | if (IS_PF(bp)) { |
11159 | rc = bnx2x_get_hwinfo(bp); | |
11160 | if (rc) | |
11161 | return rc; | |
11162 | } else { | |
11163 | random_ether_addr(bp->dev->dev_addr); | |
11164 | } | |
34f80b04 | 11165 | |
619c5cb6 VZ |
11166 | bnx2x_set_modes_bitmap(bp); |
11167 | ||
11168 | rc = bnx2x_alloc_mem_bp(bp); | |
11169 | if (rc) | |
11170 | return rc; | |
523224a3 | 11171 | |
34f24c7f | 11172 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
11173 | |
11174 | func = BP_FUNC(bp); | |
11175 | ||
34f80b04 | 11176 | /* need to reset chip if undi was active */ |
1ab4434c | 11177 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
452427b0 YM |
11178 | /* init fw_seq */ |
11179 | bp->fw_seq = | |
11180 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
11181 | DRV_MSG_SEQ_NUMBER_MASK; | |
11182 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
11183 | ||
11184 | bnx2x_prev_unload(bp); | |
11185 | } | |
11186 | ||
34f80b04 EG |
11187 | |
11188 | if (CHIP_REV_IS_FPGA(bp)) | |
cdaa7cb8 | 11189 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
11190 | |
11191 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 11192 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 11193 | |
614c76df | 11194 | bp->disable_tpa = disable_tpa; |
a3348722 | 11195 | bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp); |
614c76df | 11196 | |
7a9b2557 | 11197 | /* Set TPA flags */ |
614c76df | 11198 | if (bp->disable_tpa) { |
621b4d66 | 11199 | bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
11200 | bp->dev->features &= ~NETIF_F_LRO; |
11201 | } else { | |
621b4d66 | 11202 | bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
11203 | bp->dev->features |= NETIF_F_LRO; |
11204 | } | |
11205 | ||
a18f5128 EG |
11206 | if (CHIP_IS_E1(bp)) |
11207 | bp->dropless_fc = 0; | |
11208 | else | |
7964211d | 11209 | bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); |
a18f5128 | 11210 | |
8d5726c4 | 11211 | bp->mrrs = mrrs; |
7a9b2557 | 11212 | |
a3348722 | 11213 | bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; |
1ab4434c AE |
11214 | if (IS_VF(bp)) |
11215 | bp->rx_ring_size = MAX_RX_AVAIL; | |
34f80b04 | 11216 | |
7d323bfd | 11217 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
11218 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
11219 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 11220 | |
fc543637 | 11221 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 EG |
11222 | |
11223 | init_timer(&bp->timer); | |
11224 | bp->timer.expires = jiffies + bp->current_interval; | |
11225 | bp->timer.data = (unsigned long) bp; | |
11226 | bp->timer.function = bnx2x_timer; | |
11227 | ||
0370cf90 BW |
11228 | if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && |
11229 | SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && | |
11230 | SHMEM2_RD(bp, dcbx_lldp_params_offset) && | |
11231 | SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) { | |
11232 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); | |
11233 | bnx2x_dcbx_init_params(bp); | |
11234 | } else { | |
11235 | bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); | |
11236 | } | |
e4901dde | 11237 | |
619c5cb6 VZ |
11238 | if (CHIP_IS_E1x(bp)) |
11239 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
11240 | else | |
11241 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
619c5cb6 | 11242 | |
6383c0b3 | 11243 | /* multiple tx priority */ |
1ab4434c AE |
11244 | if (IS_VF(bp)) |
11245 | bp->max_cos = 1; | |
11246 | else if (CHIP_IS_E1x(bp)) | |
6383c0b3 | 11247 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; |
1ab4434c | 11248 | else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) |
6383c0b3 | 11249 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; |
1ab4434c | 11250 | else if (CHIP_IS_E3B0(bp)) |
6383c0b3 | 11251 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; |
1ab4434c AE |
11252 | else |
11253 | BNX2X_ERR("unknown chip %x revision %x\n", | |
11254 | CHIP_NUM(bp), CHIP_REV(bp)); | |
11255 | BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); | |
6383c0b3 | 11256 | |
55c11941 MS |
11257 | /* We need at least one default status block for slow-path events, |
11258 | * second status block for the L2 queue, and a third status block for | |
11259 | * CNIC if supproted. | |
11260 | */ | |
11261 | if (CNIC_SUPPORT(bp)) | |
11262 | bp->min_msix_vec_cnt = 3; | |
11263 | else | |
11264 | bp->min_msix_vec_cnt = 2; | |
11265 | BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); | |
11266 | ||
34f80b04 | 11267 | return rc; |
a2fbb9ea ET |
11268 | } |
11269 | ||
a2fbb9ea | 11270 | |
de0c62db DK |
11271 | /**************************************************************************** |
11272 | * General service functions | |
11273 | ****************************************************************************/ | |
a2fbb9ea | 11274 | |
619c5cb6 VZ |
11275 | /* |
11276 | * net_device service functions | |
11277 | */ | |
11278 | ||
bb2a0f7a | 11279 | /* called with rtnl_lock */ |
a2fbb9ea ET |
11280 | static int bnx2x_open(struct net_device *dev) |
11281 | { | |
11282 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
11283 | bool global = false; |
11284 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
889b9af3 | 11285 | bool other_load_status, load_status; |
a2fbb9ea | 11286 | |
1355b704 MY |
11287 | bp->stats_init = true; |
11288 | ||
6eccabb3 EG |
11289 | netif_carrier_off(dev); |
11290 | ||
a2fbb9ea ET |
11291 | bnx2x_set_power_state(bp, PCI_D0); |
11292 | ||
ad5afc89 | 11293 | /* If parity had happen during the unload, then attentions |
c9ee9206 VZ |
11294 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we |
11295 | * want the first function loaded on the current engine to | |
11296 | * complete the recovery. | |
ad5afc89 | 11297 | * Parity recovery is only relevant for PF driver. |
c9ee9206 | 11298 | */ |
ad5afc89 AE |
11299 | if (IS_PF(bp)) { |
11300 | other_load_status = bnx2x_get_load_status(bp, other_engine); | |
11301 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
11302 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
11303 | bnx2x_chk_parity_attn(bp, &global, true)) { | |
11304 | do { | |
11305 | /* If there are attentions and they are in a | |
11306 | * global blocks, set the GLOBAL_RESET bit | |
11307 | * regardless whether it will be this function | |
11308 | * that will complete the recovery or not. | |
11309 | */ | |
11310 | if (global) | |
11311 | bnx2x_set_reset_global(bp); | |
72fd0718 | 11312 | |
ad5afc89 AE |
11313 | /* Only the first function on the current |
11314 | * engine should try to recover in open. In case | |
11315 | * of attentions in global blocks only the first | |
11316 | * in the chip should try to recover. | |
11317 | */ | |
11318 | if ((!load_status && | |
11319 | (!global || !other_load_status)) && | |
11320 | bnx2x_trylock_leader_lock(bp) && | |
11321 | !bnx2x_leader_reset(bp)) { | |
11322 | netdev_info(bp->dev, | |
11323 | "Recovered in open\n"); | |
11324 | break; | |
11325 | } | |
72fd0718 | 11326 | |
ad5afc89 AE |
11327 | /* recovery has failed... */ |
11328 | bnx2x_set_power_state(bp, PCI_D3hot); | |
11329 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
72fd0718 | 11330 | |
ad5afc89 AE |
11331 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
11332 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 | 11333 | |
ad5afc89 AE |
11334 | return -EAGAIN; |
11335 | } while (0); | |
11336 | } | |
11337 | } | |
72fd0718 VZ |
11338 | |
11339 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
bb2a0f7a | 11340 | return bnx2x_nic_load(bp, LOAD_OPEN); |
a2fbb9ea ET |
11341 | } |
11342 | ||
bb2a0f7a | 11343 | /* called with rtnl_lock */ |
56ad3152 | 11344 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 11345 | { |
a2fbb9ea ET |
11346 | struct bnx2x *bp = netdev_priv(dev); |
11347 | ||
11348 | /* Unload the driver, release IRQs */ | |
5d07d868 | 11349 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
c9ee9206 VZ |
11350 | |
11351 | /* Power off */ | |
d3dbfee0 | 11352 | bnx2x_set_power_state(bp, PCI_D3hot); |
a2fbb9ea ET |
11353 | |
11354 | return 0; | |
11355 | } | |
11356 | ||
1191cb83 ED |
11357 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
11358 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 11359 | { |
619c5cb6 VZ |
11360 | int mc_count = netdev_mc_count(bp->dev); |
11361 | struct bnx2x_mcast_list_elem *mc_mac = | |
11362 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
11363 | struct netdev_hw_addr *ha; | |
6e30dd4e | 11364 | |
619c5cb6 VZ |
11365 | if (!mc_mac) |
11366 | return -ENOMEM; | |
6e30dd4e | 11367 | |
619c5cb6 | 11368 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 11369 | |
619c5cb6 VZ |
11370 | netdev_for_each_mc_addr(ha, bp->dev) { |
11371 | mc_mac->mac = bnx2x_mc_addr(ha); | |
11372 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
11373 | mc_mac++; | |
6e30dd4e | 11374 | } |
619c5cb6 VZ |
11375 | |
11376 | p->mcast_list_len = mc_count; | |
11377 | ||
11378 | return 0; | |
6e30dd4e VZ |
11379 | } |
11380 | ||
1191cb83 | 11381 | static void bnx2x_free_mcast_macs_list( |
619c5cb6 VZ |
11382 | struct bnx2x_mcast_ramrod_params *p) |
11383 | { | |
11384 | struct bnx2x_mcast_list_elem *mc_mac = | |
11385 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
11386 | link); | |
11387 | ||
11388 | WARN_ON(!mc_mac); | |
11389 | kfree(mc_mac); | |
11390 | } | |
11391 | ||
11392 | /** | |
11393 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
11394 | * | |
11395 | * @bp: driver handle | |
6e30dd4e | 11396 | * |
619c5cb6 | 11397 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 11398 | */ |
1191cb83 | 11399 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 11400 | { |
619c5cb6 | 11401 | int rc; |
6e30dd4e | 11402 | struct net_device *dev = bp->dev; |
6e30dd4e | 11403 | struct netdev_hw_addr *ha; |
15192a8c | 11404 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 | 11405 | unsigned long ramrod_flags = 0; |
6e30dd4e | 11406 | |
619c5cb6 VZ |
11407 | /* First schedule a cleanup up of old configuration */ |
11408 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
11409 | if (rc < 0) { | |
11410 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
11411 | return rc; | |
11412 | } | |
6e30dd4e VZ |
11413 | |
11414 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
11415 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
11416 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
7b5342d9 YM |
11417 | if (rc == -EEXIST) { |
11418 | DP(BNX2X_MSG_SP, | |
11419 | "Failed to schedule ADD operations: %d\n", rc); | |
11420 | /* do not treat adding same MAC as error */ | |
11421 | rc = 0; | |
11422 | ||
11423 | } else if (rc < 0) { | |
11424 | ||
619c5cb6 VZ |
11425 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", |
11426 | rc); | |
11427 | return rc; | |
6e30dd4e VZ |
11428 | } |
11429 | } | |
11430 | ||
619c5cb6 VZ |
11431 | /* Execute the pending commands */ |
11432 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
11433 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
11434 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
11435 | } |
11436 | ||
1191cb83 | 11437 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 11438 | { |
619c5cb6 | 11439 | struct net_device *dev = bp->dev; |
3b603066 | 11440 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 11441 | int rc = 0; |
6e30dd4e | 11442 | |
619c5cb6 | 11443 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 11444 | |
619c5cb6 VZ |
11445 | /* first, clear all configured multicast MACs */ |
11446 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
11447 | if (rc < 0) { | |
51c1a580 | 11448 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
11449 | return rc; |
11450 | } | |
6e30dd4e | 11451 | |
619c5cb6 VZ |
11452 | /* then, configure a new MACs list */ |
11453 | if (netdev_mc_count(dev)) { | |
11454 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
11455 | if (rc) { | |
51c1a580 MS |
11456 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
11457 | rc); | |
619c5cb6 VZ |
11458 | return rc; |
11459 | } | |
6e30dd4e | 11460 | |
619c5cb6 VZ |
11461 | /* Now add the new MACs */ |
11462 | rc = bnx2x_config_mcast(bp, &rparam, | |
11463 | BNX2X_MCAST_CMD_ADD); | |
11464 | if (rc < 0) | |
51c1a580 MS |
11465 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
11466 | rc); | |
6e30dd4e | 11467 | |
619c5cb6 VZ |
11468 | bnx2x_free_mcast_macs_list(&rparam); |
11469 | } | |
6e30dd4e | 11470 | |
619c5cb6 | 11471 | return rc; |
6e30dd4e VZ |
11472 | } |
11473 | ||
6e30dd4e | 11474 | |
619c5cb6 | 11475 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 11476 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
11477 | { |
11478 | struct bnx2x *bp = netdev_priv(dev); | |
11479 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 EG |
11480 | |
11481 | if (bp->state != BNX2X_STATE_OPEN) { | |
11482 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
11483 | return; | |
11484 | } | |
11485 | ||
619c5cb6 | 11486 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 EG |
11487 | |
11488 | if (dev->flags & IFF_PROMISC) | |
11489 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
619c5cb6 VZ |
11490 | else if ((dev->flags & IFF_ALLMULTI) || |
11491 | ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && | |
11492 | CHIP_IS_E1(bp))) | |
34f80b04 | 11493 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
6e30dd4e | 11494 | else { |
381ac16b AE |
11495 | if (IS_PF(bp)) { |
11496 | /* some multicasts */ | |
11497 | if (bnx2x_set_mc_list(bp) < 0) | |
11498 | rx_mode = BNX2X_RX_MODE_ALLMULTI; | |
34f80b04 | 11499 | |
381ac16b AE |
11500 | if (bnx2x_set_uc_list(bp) < 0) |
11501 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
11502 | } else { | |
11503 | /* configuring mcast to a vf involves sleeping (when we | |
11504 | * wait for the pf's response). Since this function is | |
11505 | * called from non sleepable context we must schedule | |
11506 | * a work item for this purpose | |
11507 | */ | |
11508 | smp_mb__before_clear_bit(); | |
11509 | set_bit(BNX2X_SP_RTNL_VFPF_MCAST, | |
11510 | &bp->sp_rtnl_state); | |
11511 | smp_mb__after_clear_bit(); | |
11512 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
11513 | } | |
34f80b04 EG |
11514 | } |
11515 | ||
11516 | bp->rx_mode = rx_mode; | |
614c76df DK |
11517 | /* handle ISCSI SD mode */ |
11518 | if (IS_MF_ISCSI_SD(bp)) | |
11519 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
619c5cb6 VZ |
11520 | |
11521 | /* Schedule the rx_mode command */ | |
11522 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
11523 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
11524 | return; | |
11525 | } | |
11526 | ||
381ac16b AE |
11527 | if (IS_PF(bp)) { |
11528 | bnx2x_set_storm_rx_mode(bp); | |
11529 | } else { | |
11530 | /* configuring rx mode to storms in a vf involves sleeping (when | |
11531 | * we wait for the pf's response). Since this function is | |
11532 | * called from non sleepable context we must schedule | |
11533 | * a work item for this purpose | |
11534 | */ | |
11535 | smp_mb__before_clear_bit(); | |
11536 | set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, | |
11537 | &bp->sp_rtnl_state); | |
11538 | smp_mb__after_clear_bit(); | |
11539 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
11540 | } | |
34f80b04 EG |
11541 | } |
11542 | ||
c18487ee | 11543 | /* called with rtnl_lock */ |
01cd4528 EG |
11544 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
11545 | int devad, u16 addr) | |
a2fbb9ea | 11546 | { |
01cd4528 EG |
11547 | struct bnx2x *bp = netdev_priv(netdev); |
11548 | u16 value; | |
11549 | int rc; | |
a2fbb9ea | 11550 | |
01cd4528 EG |
11551 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
11552 | prtad, devad, addr); | |
a2fbb9ea | 11553 | |
01cd4528 EG |
11554 | /* The HW expects different devad if CL22 is used */ |
11555 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 11556 | |
01cd4528 | 11557 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11558 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
11559 | bnx2x_release_phy_lock(bp); |
11560 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 11561 | |
01cd4528 EG |
11562 | if (!rc) |
11563 | rc = value; | |
11564 | return rc; | |
11565 | } | |
a2fbb9ea | 11566 | |
01cd4528 EG |
11567 | /* called with rtnl_lock */ |
11568 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
11569 | u16 addr, u16 value) | |
11570 | { | |
11571 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
11572 | int rc; |
11573 | ||
51c1a580 MS |
11574 | DP(NETIF_MSG_LINK, |
11575 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
11576 | prtad, devad, addr, value); | |
01cd4528 | 11577 | |
01cd4528 EG |
11578 | /* The HW expects different devad if CL22 is used */ |
11579 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 11580 | |
01cd4528 | 11581 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11582 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
11583 | bnx2x_release_phy_lock(bp); |
11584 | return rc; | |
11585 | } | |
c18487ee | 11586 | |
01cd4528 EG |
11587 | /* called with rtnl_lock */ |
11588 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
11589 | { | |
11590 | struct bnx2x *bp = netdev_priv(dev); | |
11591 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 11592 | |
01cd4528 EG |
11593 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
11594 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 11595 | |
01cd4528 EG |
11596 | if (!netif_running(dev)) |
11597 | return -EAGAIN; | |
11598 | ||
11599 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
11600 | } |
11601 | ||
257ddbda | 11602 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
11603 | static void poll_bnx2x(struct net_device *dev) |
11604 | { | |
11605 | struct bnx2x *bp = netdev_priv(dev); | |
14a15d61 | 11606 | int i; |
a2fbb9ea | 11607 | |
14a15d61 MS |
11608 | for_each_eth_queue(bp, i) { |
11609 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
11610 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); | |
11611 | } | |
a2fbb9ea ET |
11612 | } |
11613 | #endif | |
11614 | ||
614c76df DK |
11615 | static int bnx2x_validate_addr(struct net_device *dev) |
11616 | { | |
11617 | struct bnx2x *bp = netdev_priv(dev); | |
11618 | ||
51c1a580 MS |
11619 | if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { |
11620 | BNX2X_ERR("Non-valid Ethernet address\n"); | |
614c76df | 11621 | return -EADDRNOTAVAIL; |
51c1a580 | 11622 | } |
614c76df DK |
11623 | return 0; |
11624 | } | |
11625 | ||
c64213cd SH |
11626 | static const struct net_device_ops bnx2x_netdev_ops = { |
11627 | .ndo_open = bnx2x_open, | |
11628 | .ndo_stop = bnx2x_close, | |
11629 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 11630 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 11631 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 11632 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 11633 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
11634 | .ndo_do_ioctl = bnx2x_ioctl, |
11635 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
11636 | .ndo_fix_features = bnx2x_fix_features, |
11637 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 11638 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 11639 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
11640 | .ndo_poll_controller = poll_bnx2x, |
11641 | #endif | |
6383c0b3 AE |
11642 | .ndo_setup_tc = bnx2x_setup_tc, |
11643 | ||
55c11941 | 11644 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
11645 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
11646 | #endif | |
c64213cd SH |
11647 | }; |
11648 | ||
1191cb83 | 11649 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
619c5cb6 VZ |
11650 | { |
11651 | struct device *dev = &bp->pdev->dev; | |
11652 | ||
11653 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
11654 | bp->flags |= USING_DAC_FLAG; | |
11655 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
51c1a580 | 11656 | dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); |
619c5cb6 VZ |
11657 | return -EIO; |
11658 | } | |
11659 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
11660 | dev_err(dev, "System does not support DMA, aborting\n"); | |
11661 | return -EIO; | |
11662 | } | |
11663 | ||
11664 | return 0; | |
11665 | } | |
11666 | ||
1ab4434c AE |
11667 | static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, |
11668 | struct net_device *dev, unsigned long board_type) | |
a2fbb9ea | 11669 | { |
a2fbb9ea | 11670 | int rc; |
c22610d0 | 11671 | u32 pci_cfg_dword; |
65087cfe AE |
11672 | bool chip_is_e1x = (board_type == BCM57710 || |
11673 | board_type == BCM57711 || | |
11674 | board_type == BCM57711E); | |
a2fbb9ea ET |
11675 | |
11676 | SET_NETDEV_DEV(dev, &pdev->dev); | |
a2fbb9ea | 11677 | |
34f80b04 EG |
11678 | bp->dev = dev; |
11679 | bp->pdev = pdev; | |
a2fbb9ea ET |
11680 | |
11681 | rc = pci_enable_device(pdev); | |
11682 | if (rc) { | |
cdaa7cb8 VZ |
11683 | dev_err(&bp->pdev->dev, |
11684 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
11685 | goto err_out; |
11686 | } | |
11687 | ||
11688 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
11689 | dev_err(&bp->pdev->dev, |
11690 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
11691 | rc = -ENODEV; |
11692 | goto err_out_disable; | |
11693 | } | |
11694 | ||
1ab4434c AE |
11695 | if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
11696 | dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); | |
a2fbb9ea ET |
11697 | rc = -ENODEV; |
11698 | goto err_out_disable; | |
11699 | } | |
11700 | ||
092a5fc9 YR |
11701 | pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); |
11702 | if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == | |
11703 | PCICFG_REVESION_ID_ERROR_VAL) { | |
11704 | pr_err("PCI device error, probably due to fan failure, aborting\n"); | |
11705 | rc = -ENODEV; | |
11706 | goto err_out_disable; | |
11707 | } | |
11708 | ||
34f80b04 EG |
11709 | if (atomic_read(&pdev->enable_cnt) == 1) { |
11710 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
11711 | if (rc) { | |
cdaa7cb8 VZ |
11712 | dev_err(&bp->pdev->dev, |
11713 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
11714 | goto err_out_disable; |
11715 | } | |
a2fbb9ea | 11716 | |
34f80b04 EG |
11717 | pci_set_master(pdev); |
11718 | pci_save_state(pdev); | |
11719 | } | |
a2fbb9ea | 11720 | |
1ab4434c AE |
11721 | if (IS_PF(bp)) { |
11722 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
11723 | if (bp->pm_cap == 0) { | |
11724 | dev_err(&bp->pdev->dev, | |
11725 | "Cannot find power management capability, aborting\n"); | |
11726 | rc = -EIO; | |
11727 | goto err_out_release; | |
11728 | } | |
a2fbb9ea ET |
11729 | } |
11730 | ||
77c98e6a | 11731 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 11732 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
11733 | rc = -EIO; |
11734 | goto err_out_release; | |
11735 | } | |
11736 | ||
619c5cb6 VZ |
11737 | rc = bnx2x_set_coherency_mask(bp); |
11738 | if (rc) | |
a2fbb9ea | 11739 | goto err_out_release; |
a2fbb9ea | 11740 | |
34f80b04 EG |
11741 | dev->mem_start = pci_resource_start(pdev, 0); |
11742 | dev->base_addr = dev->mem_start; | |
11743 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
11744 | |
11745 | dev->irq = pdev->irq; | |
11746 | ||
275f165f | 11747 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 11748 | if (!bp->regview) { |
cdaa7cb8 VZ |
11749 | dev_err(&bp->pdev->dev, |
11750 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
11751 | rc = -ENOMEM; |
11752 | goto err_out_release; | |
11753 | } | |
11754 | ||
c22610d0 AE |
11755 | /* In E1/E1H use pci device function given by kernel. |
11756 | * In E2/E3 read physical function from ME register since these chips | |
11757 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
11758 | * (depending on hypervisor). | |
11759 | */ | |
11760 | if (chip_is_e1x) | |
11761 | bp->pf_num = PCI_FUNC(pdev->devfn); | |
11762 | else {/* chip is E2/3*/ | |
11763 | pci_read_config_dword(bp->pdev, | |
11764 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
11765 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
11766 | ME_REG_ABS_PF_NUM_SHIFT); | |
11767 | } | |
51c1a580 | 11768 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 11769 | |
a2fbb9ea ET |
11770 | bnx2x_set_power_state(bp, PCI_D0); |
11771 | ||
34f80b04 EG |
11772 | /* clean indirect addresses */ |
11773 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
11774 | PCICFG_VENDOR_ID_OFFSET); | |
a5c53dbc DK |
11775 | /* |
11776 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
11777 | * is not used by the driver. |
11778 | */ | |
1ab4434c AE |
11779 | if (IS_PF(bp)) { |
11780 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
11781 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
11782 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
11783 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
11784 | ||
11785 | if (chip_is_e1x) { | |
11786 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); | |
11787 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
11788 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
11789 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
11790 | } | |
a5c53dbc | 11791 | |
1ab4434c AE |
11792 | /* Enable internal target-read (in case we are probed after PF |
11793 | * FLR). Must be done prior to any BAR read access. Only for | |
11794 | * 57712 and up | |
11795 | */ | |
11796 | if (!chip_is_e1x) | |
11797 | REG_WR(bp, | |
11798 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
a5c53dbc | 11799 | } |
a2fbb9ea | 11800 | |
34f80b04 | 11801 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 11802 | |
c64213cd | 11803 | dev->netdev_ops = &bnx2x_netdev_ops; |
de0c62db | 11804 | bnx2x_set_ethtool_ops(dev); |
5316bc0b | 11805 | |
01789349 JP |
11806 | dev->priv_flags |= IFF_UNICAST_FLT; |
11807 | ||
66371c44 | 11808 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
11809 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
11810 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
11811 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; | |
66371c44 MM |
11812 | |
11813 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
11814 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
11815 | ||
11816 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; | |
5316bc0b | 11817 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 11818 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 11819 | |
538dd2e3 MB |
11820 | /* Add Loopback capability to the device */ |
11821 | dev->hw_features |= NETIF_F_LOOPBACK; | |
11822 | ||
98507672 | 11823 | #ifdef BCM_DCBNL |
785b9b1a SR |
11824 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
11825 | #endif | |
11826 | ||
01cd4528 EG |
11827 | /* get_port_hwinfo() will set prtad and mmds properly */ |
11828 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
11829 | bp->mdio.mmds = 0; | |
11830 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
11831 | bp->mdio.dev = dev; | |
11832 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
11833 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
11834 | ||
a2fbb9ea ET |
11835 | return 0; |
11836 | ||
a2fbb9ea | 11837 | err_out_release: |
34f80b04 EG |
11838 | if (atomic_read(&pdev->enable_cnt) == 1) |
11839 | pci_release_regions(pdev); | |
a2fbb9ea ET |
11840 | |
11841 | err_out_disable: | |
11842 | pci_disable_device(pdev); | |
11843 | pci_set_drvdata(pdev, NULL); | |
11844 | ||
11845 | err_out: | |
11846 | return rc; | |
11847 | } | |
11848 | ||
1dd06ae8 | 11849 | static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed) |
25047950 | 11850 | { |
1ab4434c | 11851 | u32 val = 0; |
25047950 | 11852 | |
1ab4434c | 11853 | pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val); |
37f9ce62 | 11854 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 11855 | |
37f9ce62 EG |
11856 | /* return value of 1=2.5GHz 2=5GHz */ |
11857 | *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; | |
25047950 | 11858 | } |
37f9ce62 | 11859 | |
6891dd25 | 11860 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 11861 | { |
37f9ce62 | 11862 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
11863 | struct bnx2x_fw_file_hdr *fw_hdr; |
11864 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 11865 | u32 offset, len, num_ops; |
37f9ce62 | 11866 | u16 *ops_offsets; |
94a78b79 | 11867 | int i; |
37f9ce62 | 11868 | const u8 *fw_ver; |
94a78b79 | 11869 | |
51c1a580 MS |
11870 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
11871 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 11872 | return -EINVAL; |
51c1a580 | 11873 | } |
94a78b79 VZ |
11874 | |
11875 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
11876 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
11877 | ||
11878 | /* Make sure none of the offsets and sizes make us read beyond | |
11879 | * the end of the firmware data */ | |
11880 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
11881 | offset = be32_to_cpu(sections[i].offset); | |
11882 | len = be32_to_cpu(sections[i].len); | |
11883 | if (offset + len > firmware->size) { | |
51c1a580 | 11884 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
11885 | return -EINVAL; |
11886 | } | |
11887 | } | |
11888 | ||
11889 | /* Likewise for the init_ops offsets */ | |
11890 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
11891 | ops_offsets = (u16 *)(firmware->data + offset); | |
11892 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); | |
11893 | ||
11894 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
11895 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 11896 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
11897 | return -EINVAL; |
11898 | } | |
11899 | } | |
11900 | ||
11901 | /* Check FW version */ | |
11902 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
11903 | fw_ver = firmware->data + offset; | |
11904 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
11905 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
11906 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
11907 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
11908 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
11909 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
11910 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
11911 | BCM_5710_FW_MINOR_VERSION, |
11912 | BCM_5710_FW_REVISION_VERSION, | |
11913 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 11914 | return -EINVAL; |
94a78b79 VZ |
11915 | } |
11916 | ||
11917 | return 0; | |
11918 | } | |
11919 | ||
1191cb83 | 11920 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11921 | { |
ab6ad5a4 EG |
11922 | const __be32 *source = (const __be32 *)_source; |
11923 | u32 *target = (u32 *)_target; | |
94a78b79 | 11924 | u32 i; |
94a78b79 VZ |
11925 | |
11926 | for (i = 0; i < n/4; i++) | |
11927 | target[i] = be32_to_cpu(source[i]); | |
11928 | } | |
11929 | ||
11930 | /* | |
11931 | Ops array is stored in the following format: | |
11932 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
11933 | */ | |
1191cb83 | 11934 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11935 | { |
ab6ad5a4 EG |
11936 | const __be32 *source = (const __be32 *)_source; |
11937 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 11938 | u32 i, j, tmp; |
94a78b79 | 11939 | |
ab6ad5a4 | 11940 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
11941 | tmp = be32_to_cpu(source[j]); |
11942 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
11943 | target[i].offset = tmp & 0xffffff; |
11944 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
11945 | } |
11946 | } | |
ab6ad5a4 | 11947 | |
1aa8b471 | 11948 | /* IRO array is stored in the following format: |
523224a3 DK |
11949 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } |
11950 | */ | |
1191cb83 | 11951 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
523224a3 DK |
11952 | { |
11953 | const __be32 *source = (const __be32 *)_source; | |
11954 | struct iro *target = (struct iro *)_target; | |
11955 | u32 i, j, tmp; | |
11956 | ||
11957 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
11958 | target[i].base = be32_to_cpu(source[j]); | |
11959 | j++; | |
11960 | tmp = be32_to_cpu(source[j]); | |
11961 | target[i].m1 = (tmp >> 16) & 0xffff; | |
11962 | target[i].m2 = tmp & 0xffff; | |
11963 | j++; | |
11964 | tmp = be32_to_cpu(source[j]); | |
11965 | target[i].m3 = (tmp >> 16) & 0xffff; | |
11966 | target[i].size = tmp & 0xffff; | |
11967 | j++; | |
11968 | } | |
11969 | } | |
11970 | ||
1191cb83 | 11971 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 11972 | { |
ab6ad5a4 EG |
11973 | const __be16 *source = (const __be16 *)_source; |
11974 | u16 *target = (u16 *)_target; | |
94a78b79 | 11975 | u32 i; |
94a78b79 VZ |
11976 | |
11977 | for (i = 0; i < n/2; i++) | |
11978 | target[i] = be16_to_cpu(source[i]); | |
11979 | } | |
11980 | ||
7995c64e JP |
11981 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
11982 | do { \ | |
11983 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
11984 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 11985 | if (!bp->arr) \ |
7995c64e | 11986 | goto lbl; \ |
7995c64e JP |
11987 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
11988 | (u8 *)bp->arr, len); \ | |
11989 | } while (0) | |
94a78b79 | 11990 | |
3b603066 | 11991 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 11992 | { |
c0ea452e | 11993 | const char *fw_file_name; |
94a78b79 | 11994 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 11995 | int rc; |
94a78b79 | 11996 | |
c0ea452e MS |
11997 | if (bp->firmware) |
11998 | return 0; | |
94a78b79 | 11999 | |
c0ea452e MS |
12000 | if (CHIP_IS_E1(bp)) |
12001 | fw_file_name = FW_FILE_NAME_E1; | |
12002 | else if (CHIP_IS_E1H(bp)) | |
12003 | fw_file_name = FW_FILE_NAME_E1H; | |
12004 | else if (!CHIP_IS_E1x(bp)) | |
12005 | fw_file_name = FW_FILE_NAME_E2; | |
12006 | else { | |
12007 | BNX2X_ERR("Unsupported chip revision\n"); | |
12008 | return -EINVAL; | |
12009 | } | |
12010 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 12011 | |
c0ea452e MS |
12012 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
12013 | if (rc) { | |
12014 | BNX2X_ERR("Can't load firmware file %s\n", | |
12015 | fw_file_name); | |
12016 | goto request_firmware_exit; | |
12017 | } | |
eb2afd4a | 12018 | |
c0ea452e MS |
12019 | rc = bnx2x_check_firmware(bp); |
12020 | if (rc) { | |
12021 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
12022 | goto request_firmware_exit; | |
94a78b79 VZ |
12023 | } |
12024 | ||
12025 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
12026 | ||
12027 | /* Initialize the pointers to the init arrays */ | |
12028 | /* Blob */ | |
12029 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
12030 | ||
12031 | /* Opcodes */ | |
12032 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
12033 | ||
12034 | /* Offsets */ | |
ab6ad5a4 EG |
12035 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
12036 | be16_to_cpu_n); | |
94a78b79 VZ |
12037 | |
12038 | /* STORMs firmware */ | |
573f2035 EG |
12039 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
12040 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
12041 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12042 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
12043 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12044 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
12045 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
12046 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
12047 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12048 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
12049 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12050 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
12051 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12052 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
12053 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12054 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
12055 | /* IRO */ |
12056 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
12057 | |
12058 | return 0; | |
ab6ad5a4 | 12059 | |
523224a3 DK |
12060 | iro_alloc_err: |
12061 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
12062 | init_offsets_alloc_err: |
12063 | kfree(bp->init_ops); | |
12064 | init_ops_alloc_err: | |
12065 | kfree(bp->init_data); | |
12066 | request_firmware_exit: | |
12067 | release_firmware(bp->firmware); | |
127d0a19 | 12068 | bp->firmware = NULL; |
94a78b79 VZ |
12069 | |
12070 | return rc; | |
12071 | } | |
12072 | ||
619c5cb6 VZ |
12073 | static void bnx2x_release_firmware(struct bnx2x *bp) |
12074 | { | |
12075 | kfree(bp->init_ops_offsets); | |
12076 | kfree(bp->init_ops); | |
12077 | kfree(bp->init_data); | |
12078 | release_firmware(bp->firmware); | |
eb2afd4a | 12079 | bp->firmware = NULL; |
619c5cb6 VZ |
12080 | } |
12081 | ||
12082 | ||
12083 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { | |
12084 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
12085 | .init_hw_cmn = bnx2x_init_hw_common, | |
12086 | .init_hw_port = bnx2x_init_hw_port, | |
12087 | .init_hw_func = bnx2x_init_hw_func, | |
12088 | ||
12089 | .reset_hw_cmn = bnx2x_reset_common, | |
12090 | .reset_hw_port = bnx2x_reset_port, | |
12091 | .reset_hw_func = bnx2x_reset_func, | |
12092 | ||
12093 | .gunzip_init = bnx2x_gunzip_init, | |
12094 | .gunzip_end = bnx2x_gunzip_end, | |
12095 | ||
12096 | .init_fw = bnx2x_init_firmware, | |
12097 | .release_fw = bnx2x_release_firmware, | |
12098 | }; | |
12099 | ||
12100 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
12101 | { | |
12102 | /* Prepare DMAE related driver resources */ | |
12103 | bnx2x_setup_dmae(bp); | |
12104 | ||
12105 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
12106 | bnx2x_sp(bp, func_rdata), | |
12107 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
12108 | bnx2x_sp(bp, func_afex_rdata), |
12109 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
12110 | &bnx2x_func_sp_drv); |
12111 | } | |
12112 | ||
12113 | /* must be called after sriov-enable */ | |
1191cb83 | 12114 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 12115 | { |
37ae41a9 | 12116 | int cid_count = BNX2X_L2_MAX_CID(bp); |
94a78b79 | 12117 | |
55c11941 MS |
12118 | if (CNIC_SUPPORT(bp)) |
12119 | cid_count += CNIC_CID_MAX; | |
523224a3 DK |
12120 | return roundup(cid_count, QM_CID_ROUND); |
12121 | } | |
f85582f8 | 12122 | |
619c5cb6 | 12123 | /** |
6383c0b3 | 12124 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
12125 | * |
12126 | * @dev: pci device | |
12127 | * | |
12128 | */ | |
55c11941 | 12129 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, |
1ab4434c | 12130 | int cnic_cnt, bool is_vf) |
619c5cb6 | 12131 | { |
1ab4434c AE |
12132 | int pos, index; |
12133 | u16 control = 0; | |
619c5cb6 VZ |
12134 | |
12135 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); | |
6383c0b3 AE |
12136 | |
12137 | /* | |
12138 | * If MSI-X is not supported - return number of SBs needed to support | |
12139 | * one fast path queue: one FP queue + SB for CNIC | |
12140 | */ | |
1ab4434c AE |
12141 | if (!pos) { |
12142 | dev_info(&pdev->dev, "no msix capability found\n"); | |
55c11941 | 12143 | return 1 + cnic_cnt; |
1ab4434c AE |
12144 | } |
12145 | dev_info(&pdev->dev, "msix capability found\n"); | |
619c5cb6 | 12146 | |
6383c0b3 AE |
12147 | /* |
12148 | * The value in the PCI configuration space is the index of the last | |
12149 | * entry, namely one less than the actual size of the table, which is | |
12150 | * exactly what we want to return from this function: number of all SBs | |
12151 | * without the default SB. | |
1ab4434c | 12152 | * For VFs there is no default SB, then we return (index+1). |
6383c0b3 | 12153 | */ |
619c5cb6 | 12154 | pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); |
619c5cb6 | 12155 | |
1ab4434c | 12156 | index = control & PCI_MSIX_FLAGS_QSIZE; |
4bd9b0ff | 12157 | |
1ab4434c AE |
12158 | return is_vf ? index + 1 : index; |
12159 | } | |
523224a3 | 12160 | |
1ab4434c AE |
12161 | static int set_max_cos_est(int chip_id) |
12162 | { | |
12163 | switch (chip_id) { | |
f2e0899f DK |
12164 | case BCM57710: |
12165 | case BCM57711: | |
12166 | case BCM57711E: | |
1ab4434c | 12167 | return BNX2X_MULTI_TX_COS_E1X; |
f2e0899f | 12168 | case BCM57712: |
619c5cb6 | 12169 | case BCM57712_MF: |
1ab4434c AE |
12170 | case BCM57712_VF: |
12171 | return BNX2X_MULTI_TX_COS_E2_E3A0; | |
619c5cb6 VZ |
12172 | case BCM57800: |
12173 | case BCM57800_MF: | |
1ab4434c | 12174 | case BCM57800_VF: |
619c5cb6 VZ |
12175 | case BCM57810: |
12176 | case BCM57810_MF: | |
c3def943 YM |
12177 | case BCM57840_4_10: |
12178 | case BCM57840_2_20: | |
1ab4434c | 12179 | case BCM57840_O: |
c3def943 | 12180 | case BCM57840_MFO: |
1ab4434c | 12181 | case BCM57810_VF: |
619c5cb6 | 12182 | case BCM57840_MF: |
1ab4434c | 12183 | case BCM57840_VF: |
7e8e02df BW |
12184 | case BCM57811: |
12185 | case BCM57811_MF: | |
1ab4434c AE |
12186 | case BCM57811_VF: |
12187 | return BNX2X_MULTI_TX_COS_E3B0; | |
12188 | return 1; | |
f2e0899f | 12189 | default: |
1ab4434c | 12190 | pr_err("Unknown board_type (%d), aborting\n", chip_id); |
870634b0 | 12191 | return -ENODEV; |
f2e0899f | 12192 | } |
1ab4434c | 12193 | } |
f2e0899f | 12194 | |
1ab4434c AE |
12195 | static int set_is_vf(int chip_id) |
12196 | { | |
12197 | switch (chip_id) { | |
12198 | case BCM57712_VF: | |
12199 | case BCM57800_VF: | |
12200 | case BCM57810_VF: | |
12201 | case BCM57840_VF: | |
12202 | case BCM57811_VF: | |
12203 | return true; | |
12204 | default: | |
12205 | return false; | |
12206 | } | |
12207 | } | |
6383c0b3 | 12208 | |
1ab4434c AE |
12209 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); |
12210 | ||
12211 | static int bnx2x_init_one(struct pci_dev *pdev, | |
12212 | const struct pci_device_id *ent) | |
12213 | { | |
12214 | struct net_device *dev = NULL; | |
12215 | struct bnx2x *bp; | |
12216 | int pcie_width, pcie_speed; | |
12217 | int rc, max_non_def_sbs; | |
12218 | int rx_count, tx_count, rss_count, doorbell_size; | |
12219 | int max_cos_est; | |
12220 | bool is_vf; | |
12221 | int cnic_cnt; | |
12222 | ||
12223 | /* An estimated maximum supported CoS number according to the chip | |
12224 | * version. | |
12225 | * We will try to roughly estimate the maximum number of CoSes this chip | |
12226 | * may support in order to minimize the memory allocated for Tx | |
12227 | * netdev_queue's. This number will be accurately calculated during the | |
12228 | * initialization of bp->max_cos based on the chip versions AND chip | |
12229 | * revision in the bnx2x_init_bp(). | |
12230 | */ | |
12231 | max_cos_est = set_max_cos_est(ent->driver_data); | |
12232 | if (max_cos_est < 0) | |
12233 | return max_cos_est; | |
12234 | is_vf = set_is_vf(ent->driver_data); | |
12235 | cnic_cnt = is_vf ? 0 : 1; | |
12236 | ||
12237 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf); | |
6383c0b3 AE |
12238 | |
12239 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
1ab4434c AE |
12240 | rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt; |
12241 | ||
12242 | if (rss_count < 1) | |
12243 | return -EINVAL; | |
6383c0b3 AE |
12244 | |
12245 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
55c11941 | 12246 | rx_count = rss_count + cnic_cnt; |
6383c0b3 | 12247 | |
1ab4434c | 12248 | /* Maximum number of netdev Tx queues: |
37ae41a9 | 12249 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
6383c0b3 | 12250 | */ |
55c11941 | 12251 | tx_count = rss_count * max_cos_est + cnic_cnt; |
f85582f8 | 12252 | |
a2fbb9ea | 12253 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 12254 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 12255 | if (!dev) |
a2fbb9ea ET |
12256 | return -ENOMEM; |
12257 | ||
a2fbb9ea | 12258 | bp = netdev_priv(dev); |
a2fbb9ea | 12259 | |
1ab4434c AE |
12260 | bp->flags = 0; |
12261 | if (is_vf) | |
12262 | bp->flags |= IS_VF_FLAG; | |
12263 | ||
6383c0b3 | 12264 | bp->igu_sb_cnt = max_non_def_sbs; |
1ab4434c | 12265 | bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; |
6383c0b3 | 12266 | bp->msg_enable = debug; |
55c11941 | 12267 | bp->cnic_support = cnic_cnt; |
4bd9b0ff | 12268 | bp->cnic_probe = bnx2x_cnic_probe; |
55c11941 | 12269 | |
6383c0b3 | 12270 | pci_set_drvdata(pdev, dev); |
523224a3 | 12271 | |
1ab4434c | 12272 | rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); |
a2fbb9ea ET |
12273 | if (rc < 0) { |
12274 | free_netdev(dev); | |
12275 | return rc; | |
12276 | } | |
12277 | ||
1ab4434c AE |
12278 | BNX2X_DEV_INFO("This is a %s function\n", |
12279 | IS_PF(bp) ? "physical" : "virtual"); | |
55c11941 | 12280 | BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); |
1ab4434c | 12281 | BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); |
60aa0509 MS |
12282 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
12283 | tx_count, rx_count); | |
12284 | ||
34f80b04 | 12285 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
12286 | if (rc) |
12287 | goto init_one_exit; | |
12288 | ||
1ab4434c AE |
12289 | /* Map doorbells here as we need the real value of bp->max_cos which |
12290 | * is initialized in bnx2x_init_bp() to determine the number of | |
12291 | * l2 connections. | |
6383c0b3 | 12292 | */ |
1ab4434c AE |
12293 | if (IS_VF(bp)) { |
12294 | /* vf doorbells are embedded within the regview */ | |
12295 | bp->doorbells = bp->regview + PXP_VF_ADDR_DB_START; | |
12296 | ||
12297 | /* allocate vf2pf mailbox for vf to pf channel */ | |
12298 | BNX2X_PCI_ALLOC(bp->vf2pf_mbox, &bp->vf2pf_mbox_mapping, | |
12299 | sizeof(struct bnx2x_vf_mbx_msg)); | |
12300 | } else { | |
12301 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); | |
12302 | if (doorbell_size > pci_resource_len(pdev, 2)) { | |
12303 | dev_err(&bp->pdev->dev, | |
12304 | "Cannot map doorbells, bar size too small, aborting\n"); | |
12305 | rc = -ENOMEM; | |
12306 | goto init_one_exit; | |
12307 | } | |
12308 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
12309 | doorbell_size); | |
37ae41a9 | 12310 | } |
6383c0b3 AE |
12311 | if (!bp->doorbells) { |
12312 | dev_err(&bp->pdev->dev, | |
12313 | "Cannot map doorbell space, aborting\n"); | |
12314 | rc = -ENOMEM; | |
12315 | goto init_one_exit; | |
12316 | } | |
12317 | ||
be1f1ffa AE |
12318 | if (IS_VF(bp)) { |
12319 | rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); | |
12320 | if (rc) | |
12321 | goto init_one_exit; | |
12322 | } | |
12323 | ||
523224a3 | 12324 | /* calc qm_cid_count */ |
6383c0b3 | 12325 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
1ab4434c | 12326 | BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); |
523224a3 | 12327 | |
55c11941 | 12328 | /* disable FCOE L2 queue for E1x*/ |
62ac0dc9 | 12329 | if (CHIP_IS_E1x(bp)) |
ec6ba945 VZ |
12330 | bp->flags |= NO_FCOE_FLAG; |
12331 | ||
477864dd DK |
12332 | /* disable FCOE for 57840 device, until FW supports it */ |
12333 | switch (ent->driver_data) { | |
12334 | case BCM57840_O: | |
12335 | case BCM57840_4_10: | |
12336 | case BCM57840_2_20: | |
12337 | case BCM57840_MFO: | |
12338 | case BCM57840_MF: | |
12339 | bp->flags |= NO_FCOE_FLAG; | |
12340 | } | |
0e8d2ec5 MS |
12341 | |
12342 | /* Set bp->num_queues for MSI-X mode*/ | |
12343 | bnx2x_set_num_queues(bp); | |
12344 | ||
25985edc | 12345 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
0e8d2ec5 | 12346 | * needed. |
d6214d7a | 12347 | */ |
1ab4434c AE |
12348 | rc = bnx2x_set_int_mode(bp); |
12349 | if (rc) { | |
12350 | dev_err(&pdev->dev, "Cannot set interrupts\n"); | |
12351 | goto init_one_exit; | |
12352 | } | |
d6214d7a | 12353 | |
1ab4434c | 12354 | /* register the net device */ |
b340007f VZ |
12355 | rc = register_netdev(dev); |
12356 | if (rc) { | |
12357 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
12358 | goto init_one_exit; | |
12359 | } | |
1ab4434c | 12360 | BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); |
b340007f | 12361 | |
55c11941 | 12362 | |
ec6ba945 VZ |
12363 | if (!NO_FCOE(bp)) { |
12364 | /* Add storage MAC address */ | |
12365 | rtnl_lock(); | |
12366 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
12367 | rtnl_unlock(); | |
12368 | } | |
ec6ba945 | 12369 | |
37f9ce62 | 12370 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
1ab4434c AE |
12371 | BNX2X_DEV_INFO("got pcie width %d and speed %d\n", |
12372 | pcie_width, pcie_speed); | |
d6214d7a | 12373 | |
51c1a580 MS |
12374 | BNX2X_DEV_INFO( |
12375 | "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", | |
94f05b0f JP |
12376 | board_info[ent->driver_data].name, |
12377 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
12378 | pcie_width, | |
12379 | ((!CHIP_IS_E2(bp) && pcie_speed == 2) || | |
12380 | (CHIP_IS_E2(bp) && pcie_speed == 1)) ? | |
12381 | "5GHz (Gen2)" : "2.5GHz", | |
12382 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 12383 | |
a2fbb9ea | 12384 | return 0; |
34f80b04 | 12385 | |
1ab4434c AE |
12386 | alloc_mem_err: |
12387 | BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping, | |
12388 | sizeof(struct bnx2x_vf_mbx_msg)); | |
12389 | rc = -ENOMEM; | |
12390 | ||
34f80b04 EG |
12391 | init_one_exit: |
12392 | if (bp->regview) | |
12393 | iounmap(bp->regview); | |
12394 | ||
1ab4434c | 12395 | if (IS_PF(bp) && bp->doorbells) |
34f80b04 EG |
12396 | iounmap(bp->doorbells); |
12397 | ||
12398 | free_netdev(dev); | |
12399 | ||
12400 | if (atomic_read(&pdev->enable_cnt) == 1) | |
12401 | pci_release_regions(pdev); | |
12402 | ||
12403 | pci_disable_device(pdev); | |
12404 | pci_set_drvdata(pdev, NULL); | |
12405 | ||
12406 | return rc; | |
a2fbb9ea ET |
12407 | } |
12408 | ||
0329aba1 | 12409 | static void bnx2x_remove_one(struct pci_dev *pdev) |
a2fbb9ea ET |
12410 | { |
12411 | struct net_device *dev = pci_get_drvdata(pdev); | |
228241eb ET |
12412 | struct bnx2x *bp; |
12413 | ||
12414 | if (!dev) { | |
cdaa7cb8 | 12415 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); |
228241eb ET |
12416 | return; |
12417 | } | |
228241eb | 12418 | bp = netdev_priv(dev); |
a2fbb9ea | 12419 | |
ec6ba945 VZ |
12420 | /* Delete storage MAC address */ |
12421 | if (!NO_FCOE(bp)) { | |
12422 | rtnl_lock(); | |
12423 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
12424 | rtnl_unlock(); | |
12425 | } | |
ec6ba945 | 12426 | |
98507672 SR |
12427 | #ifdef BCM_DCBNL |
12428 | /* Delete app tlvs from dcbnl */ | |
12429 | bnx2x_dcbnl_update_applist(bp, true); | |
12430 | #endif | |
12431 | ||
a2fbb9ea ET |
12432 | unregister_netdev(dev); |
12433 | ||
084d6cbb | 12434 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
1ab4434c AE |
12435 | if (IS_PF(bp)) |
12436 | bnx2x_set_power_state(bp, PCI_D0); | |
084d6cbb | 12437 | |
d6214d7a DK |
12438 | /* Disable MSI/MSI-X */ |
12439 | bnx2x_disable_msi(bp); | |
f85582f8 | 12440 | |
084d6cbb | 12441 | /* Power off */ |
1ab4434c AE |
12442 | if (IS_PF(bp)) |
12443 | bnx2x_set_power_state(bp, PCI_D3hot); | |
084d6cbb | 12444 | |
72fd0718 | 12445 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 12446 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
4513f925 AE |
12447 | /* send message via vfpf channel to release the resources of this vf */ |
12448 | if (IS_VF(bp)) | |
12449 | bnx2x_vfpf_release(bp); | |
72fd0718 | 12450 | |
a2fbb9ea ET |
12451 | if (bp->regview) |
12452 | iounmap(bp->regview); | |
12453 | ||
1ab4434c AE |
12454 | /* for vf doorbells are part of the regview and were unmapped along with |
12455 | * it. FW is only loaded by PF. | |
12456 | */ | |
12457 | if (IS_PF(bp)) { | |
12458 | if (bp->doorbells) | |
12459 | iounmap(bp->doorbells); | |
eb2afd4a | 12460 | |
1ab4434c AE |
12461 | bnx2x_release_firmware(bp); |
12462 | } | |
523224a3 DK |
12463 | bnx2x_free_mem_bp(bp); |
12464 | ||
a2fbb9ea | 12465 | free_netdev(dev); |
34f80b04 EG |
12466 | |
12467 | if (atomic_read(&pdev->enable_cnt) == 1) | |
12468 | pci_release_regions(pdev); | |
12469 | ||
a2fbb9ea ET |
12470 | pci_disable_device(pdev); |
12471 | pci_set_drvdata(pdev, NULL); | |
12472 | } | |
12473 | ||
f8ef6e44 YG |
12474 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
12475 | { | |
12476 | int i; | |
12477 | ||
12478 | bp->state = BNX2X_STATE_ERROR; | |
12479 | ||
12480 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
12481 | ||
55c11941 MS |
12482 | if (CNIC_LOADED(bp)) |
12483 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
12484 | ||
619c5cb6 VZ |
12485 | /* Stop Tx */ |
12486 | bnx2x_tx_disable(bp); | |
12487 | ||
f8ef6e44 | 12488 | bnx2x_netif_stop(bp, 0); |
26614ba5 MS |
12489 | /* Delete all NAPI objects */ |
12490 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
12491 | if (CNIC_LOADED(bp)) |
12492 | bnx2x_del_all_napi_cnic(bp); | |
f8ef6e44 YG |
12493 | |
12494 | del_timer_sync(&bp->timer); | |
619c5cb6 VZ |
12495 | |
12496 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
f8ef6e44 YG |
12497 | |
12498 | /* Release IRQs */ | |
d6214d7a | 12499 | bnx2x_free_irq(bp); |
f8ef6e44 | 12500 | |
f8ef6e44 YG |
12501 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
12502 | bnx2x_free_skbs(bp); | |
523224a3 | 12503 | |
ec6ba945 | 12504 | for_each_rx_queue(bp, i) |
f8ef6e44 | 12505 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 12506 | |
f8ef6e44 YG |
12507 | bnx2x_free_mem(bp); |
12508 | ||
12509 | bp->state = BNX2X_STATE_CLOSED; | |
12510 | ||
619c5cb6 VZ |
12511 | netif_carrier_off(bp->dev); |
12512 | ||
f8ef6e44 YG |
12513 | return 0; |
12514 | } | |
12515 | ||
12516 | static void bnx2x_eeh_recover(struct bnx2x *bp) | |
12517 | { | |
12518 | u32 val; | |
12519 | ||
12520 | mutex_init(&bp->port.phy_mutex); | |
12521 | ||
f8ef6e44 YG |
12522 | |
12523 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
12524 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
12525 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
12526 | BNX2X_ERR("BAD MCP validity signature\n"); | |
f8ef6e44 YG |
12527 | } |
12528 | ||
493adb1f WX |
12529 | /** |
12530 | * bnx2x_io_error_detected - called when PCI error is detected | |
12531 | * @pdev: Pointer to PCI device | |
12532 | * @state: The current pci connection state | |
12533 | * | |
12534 | * This function is called after a PCI bus error affecting | |
12535 | * this device has been detected. | |
12536 | */ | |
12537 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
12538 | pci_channel_state_t state) | |
12539 | { | |
12540 | struct net_device *dev = pci_get_drvdata(pdev); | |
12541 | struct bnx2x *bp = netdev_priv(dev); | |
12542 | ||
12543 | rtnl_lock(); | |
12544 | ||
12545 | netif_device_detach(dev); | |
12546 | ||
07ce50e4 DN |
12547 | if (state == pci_channel_io_perm_failure) { |
12548 | rtnl_unlock(); | |
12549 | return PCI_ERS_RESULT_DISCONNECT; | |
12550 | } | |
12551 | ||
493adb1f | 12552 | if (netif_running(dev)) |
f8ef6e44 | 12553 | bnx2x_eeh_nic_unload(bp); |
493adb1f WX |
12554 | |
12555 | pci_disable_device(pdev); | |
12556 | ||
12557 | rtnl_unlock(); | |
12558 | ||
12559 | /* Request a slot reset */ | |
12560 | return PCI_ERS_RESULT_NEED_RESET; | |
12561 | } | |
12562 | ||
12563 | /** | |
12564 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
12565 | * @pdev: Pointer to PCI device | |
12566 | * | |
12567 | * Restart the card from scratch, as if from a cold-boot. | |
12568 | */ | |
12569 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
12570 | { | |
12571 | struct net_device *dev = pci_get_drvdata(pdev); | |
12572 | struct bnx2x *bp = netdev_priv(dev); | |
12573 | ||
12574 | rtnl_lock(); | |
12575 | ||
12576 | if (pci_enable_device(pdev)) { | |
12577 | dev_err(&pdev->dev, | |
12578 | "Cannot re-enable PCI device after reset\n"); | |
12579 | rtnl_unlock(); | |
12580 | return PCI_ERS_RESULT_DISCONNECT; | |
12581 | } | |
12582 | ||
12583 | pci_set_master(pdev); | |
12584 | pci_restore_state(pdev); | |
12585 | ||
12586 | if (netif_running(dev)) | |
12587 | bnx2x_set_power_state(bp, PCI_D0); | |
12588 | ||
12589 | rtnl_unlock(); | |
12590 | ||
12591 | return PCI_ERS_RESULT_RECOVERED; | |
12592 | } | |
12593 | ||
12594 | /** | |
12595 | * bnx2x_io_resume - called when traffic can start flowing again | |
12596 | * @pdev: Pointer to PCI device | |
12597 | * | |
12598 | * This callback is called when the error recovery driver tells us that | |
12599 | * its OK to resume normal operation. | |
12600 | */ | |
12601 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
12602 | { | |
12603 | struct net_device *dev = pci_get_drvdata(pdev); | |
12604 | struct bnx2x *bp = netdev_priv(dev); | |
12605 | ||
72fd0718 | 12606 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 12607 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
12608 | return; |
12609 | } | |
12610 | ||
493adb1f WX |
12611 | rtnl_lock(); |
12612 | ||
f8ef6e44 YG |
12613 | bnx2x_eeh_recover(bp); |
12614 | ||
493adb1f | 12615 | if (netif_running(dev)) |
f8ef6e44 | 12616 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
12617 | |
12618 | netif_device_attach(dev); | |
12619 | ||
12620 | rtnl_unlock(); | |
12621 | } | |
12622 | ||
3646f0e5 | 12623 | static const struct pci_error_handlers bnx2x_err_handler = { |
493adb1f | 12624 | .error_detected = bnx2x_io_error_detected, |
356e2385 EG |
12625 | .slot_reset = bnx2x_io_slot_reset, |
12626 | .resume = bnx2x_io_resume, | |
493adb1f WX |
12627 | }; |
12628 | ||
a2fbb9ea | 12629 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
12630 | .name = DRV_MODULE_NAME, |
12631 | .id_table = bnx2x_pci_tbl, | |
12632 | .probe = bnx2x_init_one, | |
0329aba1 | 12633 | .remove = bnx2x_remove_one, |
493adb1f WX |
12634 | .suspend = bnx2x_suspend, |
12635 | .resume = bnx2x_resume, | |
12636 | .err_handler = &bnx2x_err_handler, | |
a2fbb9ea ET |
12637 | }; |
12638 | ||
12639 | static int __init bnx2x_init(void) | |
12640 | { | |
dd21ca6d SG |
12641 | int ret; |
12642 | ||
7995c64e | 12643 | pr_info("%s", version); |
938cf541 | 12644 | |
1cf167f2 EG |
12645 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
12646 | if (bnx2x_wq == NULL) { | |
7995c64e | 12647 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
12648 | return -ENOMEM; |
12649 | } | |
12650 | ||
dd21ca6d SG |
12651 | ret = pci_register_driver(&bnx2x_pci_driver); |
12652 | if (ret) { | |
7995c64e | 12653 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
12654 | destroy_workqueue(bnx2x_wq); |
12655 | } | |
12656 | return ret; | |
a2fbb9ea ET |
12657 | } |
12658 | ||
12659 | static void __exit bnx2x_cleanup(void) | |
12660 | { | |
452427b0 | 12661 | struct list_head *pos, *q; |
a2fbb9ea | 12662 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
12663 | |
12664 | destroy_workqueue(bnx2x_wq); | |
452427b0 YM |
12665 | |
12666 | /* Free globablly allocated resources */ | |
12667 | list_for_each_safe(pos, q, &bnx2x_prev_list) { | |
12668 | struct bnx2x_prev_path_list *tmp = | |
12669 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
12670 | list_del(pos); | |
12671 | kfree(tmp); | |
12672 | } | |
a2fbb9ea ET |
12673 | } |
12674 | ||
3deb8167 YR |
12675 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
12676 | { | |
12677 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
12678 | } | |
12679 | ||
a2fbb9ea ET |
12680 | module_init(bnx2x_init); |
12681 | module_exit(bnx2x_cleanup); | |
12682 | ||
619c5cb6 VZ |
12683 | /** |
12684 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
12685 | * | |
12686 | * @bp: driver handle | |
12687 | * @set: set or clear the CAM entry | |
12688 | * | |
12689 | * This function will wait until the ramdord completion returns. | |
12690 | * Return 0 if success, -ENODEV if ramrod doesn't return. | |
12691 | */ | |
1191cb83 | 12692 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
619c5cb6 VZ |
12693 | { |
12694 | unsigned long ramrod_flags = 0; | |
12695 | ||
12696 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
12697 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
12698 | &bp->iscsi_l2_mac_obj, true, | |
12699 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
12700 | } | |
993ac7b5 MC |
12701 | |
12702 | /* count denotes the number of new completions we have seen */ | |
12703 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
12704 | { | |
12705 | struct eth_spe *spe; | |
a052997e | 12706 | int cxt_index, cxt_offset; |
993ac7b5 MC |
12707 | |
12708 | #ifdef BNX2X_STOP_ON_ERROR | |
12709 | if (unlikely(bp->panic)) | |
12710 | return; | |
12711 | #endif | |
12712 | ||
12713 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 12714 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
12715 | bp->cnic_spq_pending -= count; |
12716 | ||
993ac7b5 | 12717 | |
c2bff63f DK |
12718 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
12719 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
12720 | & SPE_HDR_CONN_TYPE) >> | |
12721 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
12722 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
12723 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
12724 | |
12725 | /* Set validation for iSCSI L2 client before sending SETUP | |
12726 | * ramrod | |
12727 | */ | |
12728 | if (type == ETH_CONNECTION_TYPE) { | |
a052997e | 12729 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
37ae41a9 | 12730 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
a052997e | 12731 | ILT_PAGE_CIDS; |
37ae41a9 | 12732 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
a052997e MS |
12733 | (cxt_index * ILT_PAGE_CIDS); |
12734 | bnx2x_set_ctx_validation(bp, | |
12735 | &bp->context[cxt_index]. | |
12736 | vcxt[cxt_offset].eth, | |
37ae41a9 | 12737 | BNX2X_ISCSI_ETH_CID(bp)); |
a052997e | 12738 | } |
c2bff63f DK |
12739 | } |
12740 | ||
619c5cb6 VZ |
12741 | /* |
12742 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
12743 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
12744 | * COMMON ramrods is not more than the EQ and SPQ can |
12745 | * accommodate. | |
c2bff63f | 12746 | */ |
6e30dd4e VZ |
12747 | if (type == ETH_CONNECTION_TYPE) { |
12748 | if (!atomic_read(&bp->cq_spq_left)) | |
12749 | break; | |
12750 | else | |
12751 | atomic_dec(&bp->cq_spq_left); | |
12752 | } else if (type == NONE_CONNECTION_TYPE) { | |
12753 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
12754 | break; |
12755 | else | |
6e30dd4e | 12756 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
12757 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
12758 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
12759 | if (bp->cnic_spq_pending >= |
12760 | bp->cnic_eth_dev.max_kwqe_pending) | |
12761 | break; | |
12762 | else | |
12763 | bp->cnic_spq_pending++; | |
12764 | } else { | |
12765 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
12766 | bnx2x_panic(); | |
993ac7b5 | 12767 | break; |
c2bff63f | 12768 | } |
993ac7b5 MC |
12769 | |
12770 | spe = bnx2x_sp_get_next(bp); | |
12771 | *spe = *bp->cnic_kwq_cons; | |
12772 | ||
51c1a580 | 12773 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
12774 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
12775 | ||
12776 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
12777 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
12778 | else | |
12779 | bp->cnic_kwq_cons++; | |
12780 | } | |
12781 | bnx2x_sp_prod_update(bp); | |
12782 | spin_unlock_bh(&bp->spq_lock); | |
12783 | } | |
12784 | ||
12785 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
12786 | struct kwqe_16 *kwqes[], u32 count) | |
12787 | { | |
12788 | struct bnx2x *bp = netdev_priv(dev); | |
12789 | int i; | |
12790 | ||
12791 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
12792 | if (unlikely(bp->panic)) { |
12793 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 12794 | return -EIO; |
51c1a580 | 12795 | } |
993ac7b5 MC |
12796 | #endif |
12797 | ||
95c6c616 AE |
12798 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
12799 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 12800 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
12801 | return -EAGAIN; |
12802 | } | |
12803 | ||
993ac7b5 MC |
12804 | spin_lock_bh(&bp->spq_lock); |
12805 | ||
12806 | for (i = 0; i < count; i++) { | |
12807 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
12808 | ||
12809 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
12810 | break; | |
12811 | ||
12812 | *bp->cnic_kwq_prod = *spe; | |
12813 | ||
12814 | bp->cnic_kwq_pending++; | |
12815 | ||
51c1a580 | 12816 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 12817 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
12818 | spe->data.update_data_addr.hi, |
12819 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
12820 | bp->cnic_kwq_pending); |
12821 | ||
12822 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
12823 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
12824 | else | |
12825 | bp->cnic_kwq_prod++; | |
12826 | } | |
12827 | ||
12828 | spin_unlock_bh(&bp->spq_lock); | |
12829 | ||
12830 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
12831 | bnx2x_cnic_sp_post(bp, 0); | |
12832 | ||
12833 | return i; | |
12834 | } | |
12835 | ||
12836 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
12837 | { | |
12838 | struct cnic_ops *c_ops; | |
12839 | int rc = 0; | |
12840 | ||
12841 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
12842 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
12843 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
12844 | if (c_ops) |
12845 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
12846 | mutex_unlock(&bp->cnic_mutex); | |
12847 | ||
12848 | return rc; | |
12849 | } | |
12850 | ||
12851 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
12852 | { | |
12853 | struct cnic_ops *c_ops; | |
12854 | int rc = 0; | |
12855 | ||
12856 | rcu_read_lock(); | |
12857 | c_ops = rcu_dereference(bp->cnic_ops); | |
12858 | if (c_ops) | |
12859 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
12860 | rcu_read_unlock(); | |
12861 | ||
12862 | return rc; | |
12863 | } | |
12864 | ||
12865 | /* | |
12866 | * for commands that have no data | |
12867 | */ | |
9f6c9258 | 12868 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
12869 | { |
12870 | struct cnic_ctl_info ctl = {0}; | |
12871 | ||
12872 | ctl.cmd = cmd; | |
12873 | ||
12874 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
12875 | } | |
12876 | ||
619c5cb6 | 12877 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 12878 | { |
619c5cb6 | 12879 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
12880 | |
12881 | /* first we tell CNIC and only then we count this as a completion */ | |
12882 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
12883 | ctl.data.comp.cid = cid; | |
619c5cb6 | 12884 | ctl.data.comp.error = err; |
993ac7b5 MC |
12885 | |
12886 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 12887 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
12888 | } |
12889 | ||
619c5cb6 VZ |
12890 | |
12891 | /* Called with netif_addr_lock_bh() taken. | |
12892 | * Sets an rx_mode config for an iSCSI ETH client. | |
12893 | * Doesn't block. | |
12894 | * Completion should be checked outside. | |
12895 | */ | |
12896 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
12897 | { | |
12898 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
12899 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
12900 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
12901 | ||
12902 | if (start) { | |
12903 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
12904 | * because it's the only way for UIO Queue to accept | |
12905 | * multicasts (in non-promiscuous mode only one Queue per | |
12906 | * function will receive multicast packets (leading in our | |
12907 | * case). | |
12908 | */ | |
12909 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
12910 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
12911 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
12912 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
12913 | ||
12914 | /* Clear STOP_PENDING bit if START is requested */ | |
12915 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
12916 | ||
12917 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
12918 | } else | |
12919 | /* Clear START_PENDING bit if STOP is requested */ | |
12920 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
12921 | ||
12922 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
12923 | set_bit(sched_state, &bp->sp_state); | |
12924 | else { | |
12925 | __set_bit(RAMROD_RX, &ramrod_flags); | |
12926 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
12927 | ramrod_flags); | |
12928 | } | |
12929 | } | |
12930 | ||
12931 | ||
993ac7b5 MC |
12932 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
12933 | { | |
12934 | struct bnx2x *bp = netdev_priv(dev); | |
12935 | int rc = 0; | |
12936 | ||
12937 | switch (ctl->cmd) { | |
12938 | case DRV_CTL_CTXTBL_WR_CMD: { | |
12939 | u32 index = ctl->data.io.offset; | |
12940 | dma_addr_t addr = ctl->data.io.dma_addr; | |
12941 | ||
12942 | bnx2x_ilt_wr(bp, index, addr); | |
12943 | break; | |
12944 | } | |
12945 | ||
c2bff63f DK |
12946 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
12947 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
12948 | |
12949 | bnx2x_cnic_sp_post(bp, count); | |
12950 | break; | |
12951 | } | |
12952 | ||
12953 | /* rtnl_lock is held. */ | |
12954 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
12955 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
12956 | unsigned long sp_bits = 0; | |
12957 | ||
12958 | /* Configure the iSCSI classification object */ | |
12959 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
12960 | cp->iscsi_l2_client_id, | |
12961 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
12962 | bnx2x_sp(bp, mac_rdata), | |
12963 | bnx2x_sp_mapping(bp, mac_rdata), | |
12964 | BNX2X_FILTER_MAC_PENDING, | |
12965 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
12966 | &bp->macs_pool); | |
ec6ba945 | 12967 | |
523224a3 | 12968 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
12969 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
12970 | if (rc) | |
12971 | break; | |
523224a3 DK |
12972 | |
12973 | mmiowb(); | |
12974 | barrier(); | |
12975 | ||
619c5cb6 VZ |
12976 | /* Start accepting on iSCSI L2 ring */ |
12977 | ||
12978 | netif_addr_lock_bh(dev); | |
12979 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
12980 | netif_addr_unlock_bh(dev); | |
12981 | ||
12982 | /* bits to wait on */ | |
12983 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
12984 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
12985 | ||
12986 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
12987 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 12988 | |
993ac7b5 MC |
12989 | break; |
12990 | } | |
12991 | ||
12992 | /* rtnl_lock is held. */ | |
12993 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 12994 | unsigned long sp_bits = 0; |
993ac7b5 | 12995 | |
523224a3 | 12996 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
12997 | netif_addr_lock_bh(dev); |
12998 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
12999 | netif_addr_unlock_bh(dev); | |
13000 | ||
13001 | /* bits to wait on */ | |
13002 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
13003 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
13004 | ||
13005 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
13006 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
13007 | |
13008 | mmiowb(); | |
13009 | barrier(); | |
13010 | ||
13011 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
13012 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
13013 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
13014 | break; |
13015 | } | |
c2bff63f DK |
13016 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
13017 | int count = ctl->data.credit.credit_count; | |
13018 | ||
13019 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 13020 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
13021 | smp_mb__after_atomic_inc(); |
13022 | break; | |
13023 | } | |
1d187b34 | 13024 | case DRV_CTL_ULP_REGISTER_CMD: { |
2e499d3c | 13025 | int ulp_type = ctl->data.register_data.ulp_type; |
1d187b34 BW |
13026 | |
13027 | if (CHIP_IS_E3(bp)) { | |
13028 | int idx = BP_FW_MB_IDX(bp); | |
2e499d3c BW |
13029 | u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
13030 | int path = BP_PATH(bp); | |
13031 | int port = BP_PORT(bp); | |
13032 | int i; | |
13033 | u32 scratch_offset; | |
13034 | u32 *host_addr; | |
1d187b34 | 13035 | |
2e499d3c | 13036 | /* first write capability to shmem2 */ |
1d187b34 BW |
13037 | if (ulp_type == CNIC_ULP_ISCSI) |
13038 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
13039 | else if (ulp_type == CNIC_ULP_FCOE) | |
13040 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
13041 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
2e499d3c BW |
13042 | |
13043 | if ((ulp_type != CNIC_ULP_FCOE) || | |
13044 | (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || | |
13045 | (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) | |
13046 | break; | |
13047 | ||
13048 | /* if reached here - should write fcoe capabilities */ | |
13049 | scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); | |
13050 | if (!scratch_offset) | |
13051 | break; | |
13052 | scratch_offset += offsetof(struct glob_ncsi_oem_data, | |
13053 | fcoe_features[path][port]); | |
13054 | host_addr = (u32 *) &(ctl->data.register_data. | |
13055 | fcoe_features); | |
13056 | for (i = 0; i < sizeof(struct fcoe_capabilities); | |
13057 | i += 4) | |
13058 | REG_WR(bp, scratch_offset + i, | |
13059 | *(host_addr + i/4)); | |
1d187b34 BW |
13060 | } |
13061 | break; | |
13062 | } | |
2e499d3c | 13063 | |
1d187b34 BW |
13064 | case DRV_CTL_ULP_UNREGISTER_CMD: { |
13065 | int ulp_type = ctl->data.ulp_type; | |
13066 | ||
13067 | if (CHIP_IS_E3(bp)) { | |
13068 | int idx = BP_FW_MB_IDX(bp); | |
13069 | u32 cap; | |
13070 | ||
13071 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
13072 | if (ulp_type == CNIC_ULP_ISCSI) | |
13073 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
13074 | else if (ulp_type == CNIC_ULP_FCOE) | |
13075 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
13076 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
13077 | } | |
13078 | break; | |
13079 | } | |
993ac7b5 MC |
13080 | |
13081 | default: | |
13082 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
13083 | rc = -EINVAL; | |
13084 | } | |
13085 | ||
13086 | return rc; | |
13087 | } | |
13088 | ||
9f6c9258 | 13089 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
13090 | { |
13091 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13092 | ||
13093 | if (bp->flags & USING_MSIX_FLAG) { | |
13094 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
13095 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
13096 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
13097 | } else { | |
13098 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
13099 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
13100 | } | |
619c5cb6 | 13101 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
13102 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
13103 | else | |
13104 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
13105 | ||
619c5cb6 VZ |
13106 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
13107 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
13108 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
13109 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 13110 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
13111 | |
13112 | cp->num_irq = 2; | |
13113 | } | |
13114 | ||
37ae41a9 MS |
13115 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
13116 | { | |
13117 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13118 | ||
13119 | ||
13120 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + | |
13121 | bnx2x_cid_ilt_lines(bp); | |
13122 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; | |
13123 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); | |
13124 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); | |
13125 | ||
13126 | if (NO_ISCSI_OOO(bp)) | |
13127 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
13128 | } | |
13129 | ||
993ac7b5 MC |
13130 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
13131 | void *data) | |
13132 | { | |
13133 | struct bnx2x *bp = netdev_priv(dev); | |
13134 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
55c11941 MS |
13135 | int rc; |
13136 | ||
13137 | DP(NETIF_MSG_IFUP, "Register_cnic called\n"); | |
993ac7b5 | 13138 | |
51c1a580 MS |
13139 | if (ops == NULL) { |
13140 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 13141 | return -EINVAL; |
51c1a580 | 13142 | } |
993ac7b5 | 13143 | |
55c11941 MS |
13144 | if (!CNIC_SUPPORT(bp)) { |
13145 | BNX2X_ERR("Can't register CNIC when not supported\n"); | |
13146 | return -EOPNOTSUPP; | |
13147 | } | |
13148 | ||
13149 | if (!CNIC_LOADED(bp)) { | |
13150 | rc = bnx2x_load_cnic(bp); | |
13151 | if (rc) { | |
13152 | BNX2X_ERR("CNIC-related load failed\n"); | |
13153 | return rc; | |
13154 | } | |
13155 | ||
13156 | } | |
13157 | ||
13158 | bp->cnic_enabled = true; | |
13159 | ||
993ac7b5 MC |
13160 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
13161 | if (!bp->cnic_kwq) | |
13162 | return -ENOMEM; | |
13163 | ||
13164 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
13165 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
13166 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
13167 | ||
13168 | bp->cnic_spq_pending = 0; | |
13169 | bp->cnic_kwq_pending = 0; | |
13170 | ||
13171 | bp->cnic_data = data; | |
13172 | ||
13173 | cp->num_irq = 0; | |
619c5cb6 | 13174 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 13175 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 13176 | |
993ac7b5 | 13177 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 13178 | |
993ac7b5 MC |
13179 | rcu_assign_pointer(bp->cnic_ops, ops); |
13180 | ||
13181 | return 0; | |
13182 | } | |
13183 | ||
13184 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
13185 | { | |
13186 | struct bnx2x *bp = netdev_priv(dev); | |
13187 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13188 | ||
13189 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 13190 | cp->drv_state = 0; |
2cfa5a04 | 13191 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
13192 | mutex_unlock(&bp->cnic_mutex); |
13193 | synchronize_rcu(); | |
13194 | kfree(bp->cnic_kwq); | |
13195 | bp->cnic_kwq = NULL; | |
13196 | ||
13197 | return 0; | |
13198 | } | |
13199 | ||
13200 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
13201 | { | |
13202 | struct bnx2x *bp = netdev_priv(dev); | |
13203 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13204 | ||
2ba45142 VZ |
13205 | /* If both iSCSI and FCoE are disabled - return NULL in |
13206 | * order to indicate CNIC that it should not try to work | |
13207 | * with this device. | |
13208 | */ | |
13209 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
13210 | return NULL; | |
13211 | ||
993ac7b5 MC |
13212 | cp->drv_owner = THIS_MODULE; |
13213 | cp->chip_id = CHIP_ID(bp); | |
13214 | cp->pdev = bp->pdev; | |
13215 | cp->io_base = bp->regview; | |
13216 | cp->io_base2 = bp->doorbells; | |
13217 | cp->max_kwqe_pending = 8; | |
523224a3 | 13218 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
13219 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
13220 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 13221 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 13222 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
13223 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
13224 | cp->drv_ctl = bnx2x_drv_ctl; | |
13225 | cp->drv_register_cnic = bnx2x_register_cnic; | |
13226 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
37ae41a9 | 13227 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
619c5cb6 VZ |
13228 | cp->iscsi_l2_client_id = |
13229 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
37ae41a9 | 13230 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
c2bff63f | 13231 | |
2ba45142 VZ |
13232 | if (NO_ISCSI_OOO(bp)) |
13233 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
13234 | ||
13235 | if (NO_ISCSI(bp)) | |
13236 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
13237 | ||
13238 | if (NO_FCOE(bp)) | |
13239 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
13240 | ||
51c1a580 MS |
13241 | BNX2X_DEV_INFO( |
13242 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
13243 | cp->ctx_blk_size, |
13244 | cp->ctx_tbl_offset, | |
13245 | cp->ctx_tbl_len, | |
13246 | cp->starting_cid); | |
993ac7b5 MC |
13247 | return cp; |
13248 | } | |
993ac7b5 | 13249 | |
be1f1ffa AE |
13250 | int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping) |
13251 | { | |
13252 | struct cstorm_vf_zone_data __iomem *zone_data = | |
13253 | REG_ADDR(bp, PXP_VF_ADDR_CSDM_GLOBAL_START); | |
13254 | int tout = 600, interval = 100; /* wait for 60 seconds */ | |
13255 | ||
13256 | if (*done) { | |
13257 | BNX2X_ERR("done was non zero before message to pf was sent\n"); | |
13258 | WARN_ON(true); | |
13259 | return -EINVAL; | |
13260 | } | |
13261 | ||
13262 | /* Write message address */ | |
13263 | writel(U64_LO(msg_mapping), | |
13264 | &zone_data->non_trigger.vf_pf_channel.msg_addr_lo); | |
13265 | writel(U64_HI(msg_mapping), | |
13266 | &zone_data->non_trigger.vf_pf_channel.msg_addr_hi); | |
13267 | ||
13268 | /* make sure the address is written before FW accesses it */ | |
13269 | wmb(); | |
13270 | ||
13271 | /* Trigger the PF FW */ | |
13272 | writeb(1, &zone_data->trigger.vf_pf_channel.addr_valid); | |
13273 | ||
13274 | /* Wait for PF to complete */ | |
13275 | while ((tout >= 0) && (!*done)) { | |
13276 | msleep(interval); | |
13277 | tout -= 1; | |
13278 | ||
13279 | /* progress indicator - HV can take its own sweet time in | |
13280 | * answering VFs... | |
13281 | */ | |
13282 | DP_CONT(BNX2X_MSG_IOV, "."); | |
13283 | } | |
13284 | ||
13285 | if (!*done) { | |
13286 | BNX2X_ERR("PF response has timed out\n"); | |
13287 | return -EAGAIN; | |
13288 | } | |
13289 | DP(BNX2X_MSG_SP, "Got a response from PF\n"); | |
13290 | return 0; | |
13291 | } | |
13292 | ||
13293 | int bnx2x_get_vf_id(struct bnx2x *bp, u32 *vf_id) | |
13294 | { | |
13295 | u32 me_reg; | |
13296 | int tout = 10, interval = 100; /* Wait for 1 sec */ | |
13297 | ||
13298 | do { | |
13299 | /* pxp traps vf read of doorbells and returns me reg value */ | |
13300 | me_reg = readl(bp->doorbells); | |
13301 | if (GOOD_ME_REG(me_reg)) | |
13302 | break; | |
13303 | ||
13304 | msleep(interval); | |
13305 | ||
13306 | BNX2X_ERR("Invalid ME register value: 0x%08x\n. Is pf driver up?", | |
13307 | me_reg); | |
13308 | } while (tout-- > 0); | |
13309 | ||
13310 | if (!GOOD_ME_REG(me_reg)) { | |
13311 | BNX2X_ERR("Invalid ME register value: 0x%08x\n", me_reg); | |
13312 | return -EINVAL; | |
13313 | } | |
13314 | ||
13315 | BNX2X_ERR("valid ME register value: 0x%08x\n", me_reg); | |
13316 | ||
13317 | *vf_id = (me_reg & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT; | |
94a78b79 | 13318 | |
be1f1ffa AE |
13319 | return 0; |
13320 | } | |
13321 | ||
13322 | int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count) | |
13323 | { | |
13324 | int rc = 0, attempts = 0; | |
13325 | struct vfpf_acquire_tlv *req = &bp->vf2pf_mbox->req.acquire; | |
13326 | struct pfvf_acquire_resp_tlv *resp = &bp->vf2pf_mbox->resp.acquire_resp; | |
13327 | u32 vf_id; | |
13328 | bool resources_acquired = false; | |
13329 | ||
13330 | /* clear mailbox and prep first tlv */ | |
13331 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_ACQUIRE, sizeof(*req)); | |
13332 | ||
13333 | if (bnx2x_get_vf_id(bp, &vf_id)) | |
13334 | return -EAGAIN; | |
13335 | ||
13336 | req->vfdev_info.vf_id = vf_id; | |
13337 | req->vfdev_info.vf_os = 0; | |
13338 | ||
13339 | req->resc_request.num_rxqs = rx_count; | |
13340 | req->resc_request.num_txqs = tx_count; | |
13341 | req->resc_request.num_sbs = bp->igu_sb_cnt; | |
13342 | req->resc_request.num_mac_filters = VF_ACQUIRE_MAC_FILTERS; | |
13343 | req->resc_request.num_mc_filters = VF_ACQUIRE_MC_FILTERS; | |
13344 | ||
13345 | /* add list termination tlv */ | |
13346 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, | |
13347 | sizeof(struct channel_list_end_tlv)); | |
13348 | ||
13349 | /* output tlvs list */ | |
13350 | bnx2x_dp_tlv_list(bp, req); | |
13351 | ||
13352 | while (!resources_acquired) { | |
13353 | DP(BNX2X_MSG_SP, "attempting to acquire resources\n"); | |
13354 | ||
13355 | /* send acquire request */ | |
13356 | rc = bnx2x_send_msg2pf(bp, | |
13357 | &resp->hdr.status, | |
13358 | bp->vf2pf_mbox_mapping); | |
13359 | ||
13360 | /* PF timeout */ | |
13361 | if (rc) | |
13362 | return rc; | |
13363 | ||
13364 | /* copy acquire response from buffer to bp */ | |
13365 | memcpy(&bp->acquire_resp, resp, sizeof(bp->acquire_resp)); | |
13366 | ||
13367 | attempts++; | |
13368 | ||
13369 | /* test whether the PF accepted our request. If not, humble the | |
13370 | * the request and try again. | |
13371 | */ | |
13372 | if (bp->acquire_resp.hdr.status == PFVF_STATUS_SUCCESS) { | |
13373 | DP(BNX2X_MSG_SP, "resources acquired\n"); | |
13374 | resources_acquired = true; | |
13375 | } else if (bp->acquire_resp.hdr.status == | |
13376 | PFVF_STATUS_NO_RESOURCE && | |
13377 | attempts < VF_ACQUIRE_THRESH) { | |
13378 | DP(BNX2X_MSG_SP, | |
13379 | "PF unwilling to fulfill resource request. Try PF recommended amount\n"); | |
13380 | ||
13381 | /* humble our request */ | |
13382 | req->resc_request.num_txqs = | |
13383 | bp->acquire_resp.resc.num_txqs; | |
13384 | req->resc_request.num_rxqs = | |
13385 | bp->acquire_resp.resc.num_rxqs; | |
13386 | req->resc_request.num_sbs = | |
13387 | bp->acquire_resp.resc.num_sbs; | |
13388 | req->resc_request.num_mac_filters = | |
13389 | bp->acquire_resp.resc.num_mac_filters; | |
13390 | req->resc_request.num_vlan_filters = | |
13391 | bp->acquire_resp.resc.num_vlan_filters; | |
13392 | req->resc_request.num_mc_filters = | |
13393 | bp->acquire_resp.resc.num_mc_filters; | |
13394 | ||
13395 | /* Clear response buffer */ | |
13396 | memset(&bp->vf2pf_mbox->resp, 0, | |
13397 | sizeof(union pfvf_tlvs)); | |
13398 | } else { | |
13399 | /* PF reports error */ | |
13400 | BNX2X_ERR("Failed to get the requested amount of resources: %d. Breaking...\n", | |
13401 | bp->acquire_resp.hdr.status); | |
13402 | return -EAGAIN; | |
13403 | } | |
13404 | } | |
13405 | ||
13406 | /* get HW info */ | |
13407 | bp->common.chip_id |= (bp->acquire_resp.pfdev_info.chip_num & 0xffff); | |
13408 | bp->link_params.chip_id = bp->common.chip_id; | |
13409 | bp->db_size = bp->acquire_resp.pfdev_info.db_size; | |
13410 | bp->common.int_block = INT_BLOCK_IGU; | |
13411 | bp->common.chip_port_mode = CHIP_2_PORT_MODE; | |
13412 | bp->igu_dsb_id = -1; | |
13413 | bp->mf_ov = 0; | |
13414 | bp->mf_mode = 0; | |
13415 | bp->common.flash_size = 0; | |
13416 | bp->flags |= | |
13417 | NO_WOL_FLAG | NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG | NO_FCOE_FLAG; | |
13418 | bp->igu_sb_cnt = 1; | |
13419 | bp->igu_base_sb = bp->acquire_resp.resc.hw_sbs[0].hw_sb_id; | |
13420 | strlcpy(bp->fw_ver, bp->acquire_resp.pfdev_info.fw_ver, | |
13421 | sizeof(bp->fw_ver)); | |
13422 | ||
13423 | if (is_valid_ether_addr(bp->acquire_resp.resc.current_mac_addr)) | |
13424 | memcpy(bp->dev->dev_addr, | |
13425 | bp->acquire_resp.resc.current_mac_addr, | |
13426 | ETH_ALEN); | |
13427 | ||
13428 | return 0; | |
13429 | } | |
4513f925 AE |
13430 | |
13431 | int bnx2x_vfpf_release(struct bnx2x *bp) | |
13432 | { | |
13433 | struct vfpf_release_tlv *req = &bp->vf2pf_mbox->req.release; | |
13434 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; | |
13435 | u32 rc = 0, vf_id; | |
13436 | ||
13437 | /* clear mailbox and prep first tlv */ | |
13438 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_RELEASE, sizeof(*req)); | |
13439 | ||
13440 | if (bnx2x_get_vf_id(bp, &vf_id)) | |
13441 | return -EAGAIN; | |
13442 | ||
13443 | req->vf_id = vf_id; | |
13444 | ||
13445 | /* add list termination tlv */ | |
13446 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, | |
13447 | sizeof(struct channel_list_end_tlv)); | |
13448 | ||
13449 | /* output tlvs list */ | |
13450 | bnx2x_dp_tlv_list(bp, req); | |
13451 | ||
13452 | /* send release request */ | |
13453 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | |
13454 | ||
13455 | if (rc) | |
13456 | /* PF timeout */ | |
13457 | return rc; | |
13458 | if (resp->hdr.status == PFVF_STATUS_SUCCESS) { | |
13459 | /* PF released us */ | |
13460 | DP(BNX2X_MSG_SP, "vf released\n"); | |
13461 | } else { | |
13462 | /* PF reports error */ | |
13463 | BNX2X_ERR("PF failed our release request - are we out of sync? response status: %d\n", | |
13464 | resp->hdr.status); | |
13465 | return -EAGAIN; | |
13466 | } | |
13467 | ||
13468 | return 0; | |
13469 | } | |
8d9ac297 AE |
13470 | |
13471 | /* Tell PF about SB addresses */ | |
13472 | int bnx2x_vfpf_init(struct bnx2x *bp) | |
13473 | { | |
13474 | struct vfpf_init_tlv *req = &bp->vf2pf_mbox->req.init; | |
13475 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; | |
13476 | int rc, i; | |
13477 | ||
13478 | /* clear mailbox and prep first tlv */ | |
13479 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_INIT, sizeof(*req)); | |
13480 | ||
13481 | /* status blocks */ | |
13482 | for_each_eth_queue(bp, i) | |
13483 | req->sb_addr[i] = (dma_addr_t)bnx2x_fp(bp, i, | |
13484 | status_blk_mapping); | |
13485 | ||
13486 | /* statistics - requests only supports single queue for now */ | |
13487 | req->stats_addr = bp->fw_stats_data_mapping + | |
13488 | offsetof(struct bnx2x_fw_stats_data, queue_stats); | |
13489 | ||
13490 | /* add list termination tlv */ | |
13491 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, | |
13492 | sizeof(struct channel_list_end_tlv)); | |
13493 | ||
13494 | /* output tlvs list */ | |
13495 | bnx2x_dp_tlv_list(bp, req); | |
13496 | ||
13497 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | |
13498 | if (rc) | |
13499 | return rc; | |
13500 | ||
13501 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | |
13502 | BNX2X_ERR("INIT VF failed: %d. Breaking...\n", | |
13503 | resp->hdr.status); | |
13504 | return -EAGAIN; | |
13505 | } | |
13506 | ||
13507 | DP(BNX2X_MSG_SP, "INIT VF Succeeded\n"); | |
13508 | return 0; | |
13509 | } | |
13510 | ||
9b176b6b AE |
13511 | /* CLOSE VF - opposite to INIT_VF */ |
13512 | void bnx2x_vfpf_close_vf(struct bnx2x *bp) | |
13513 | { | |
13514 | struct vfpf_close_tlv *req = &bp->vf2pf_mbox->req.close; | |
13515 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; | |
13516 | int i, rc; | |
13517 | u32 vf_id; | |
13518 | ||
13519 | /* If we haven't got a valid VF id, there is no sense to | |
13520 | * continue with sending messages | |
13521 | */ | |
13522 | if (bnx2x_get_vf_id(bp, &vf_id)) | |
13523 | goto free_irq; | |
13524 | ||
13525 | /* Close the queues */ | |
13526 | for_each_queue(bp, i) | |
13527 | bnx2x_vfpf_teardown_queue(bp, i); | |
13528 | ||
13529 | /* clear mailbox and prep first tlv */ | |
13530 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_CLOSE, sizeof(*req)); | |
13531 | ||
13532 | req->vf_id = vf_id; | |
13533 | ||
13534 | /* add list termination tlv */ | |
13535 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, | |
13536 | sizeof(struct channel_list_end_tlv)); | |
13537 | ||
13538 | /* output tlvs list */ | |
13539 | bnx2x_dp_tlv_list(bp, req); | |
13540 | ||
13541 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | |
13542 | ||
13543 | if (rc) | |
13544 | BNX2X_ERR("Sending CLOSE failed. rc was: %d\n", rc); | |
13545 | ||
13546 | else if (resp->hdr.status != PFVF_STATUS_SUCCESS) | |
13547 | BNX2X_ERR("Sending CLOSE failed: pf response was %d\n", | |
13548 | resp->hdr.status); | |
13549 | ||
13550 | free_irq: | |
13551 | /* Disable HW interrupts, NAPI */ | |
13552 | bnx2x_netif_stop(bp, 0); | |
13553 | /* Delete all NAPI objects */ | |
13554 | bnx2x_del_all_napi(bp); | |
13555 | ||
13556 | /* Release IRQs */ | |
13557 | bnx2x_free_irq(bp); | |
13558 | } | |
13559 | ||
8d9ac297 AE |
13560 | /* ask the pf to open a queue for the vf */ |
13561 | int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx) | |
13562 | { | |
13563 | struct vfpf_setup_q_tlv *req = &bp->vf2pf_mbox->req.setup_q; | |
13564 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; | |
13565 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
13566 | u16 tpa_agg_size = 0, flags = 0; | |
13567 | int rc; | |
13568 | ||
13569 | /* clear mailbox and prep first tlv */ | |
13570 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SETUP_Q, sizeof(*req)); | |
13571 | ||
13572 | /* select tpa mode to request */ | |
13573 | if (!fp->disable_tpa) { | |
13574 | flags |= VFPF_QUEUE_FLG_TPA; | |
13575 | flags |= VFPF_QUEUE_FLG_TPA_IPV6; | |
13576 | if (fp->mode == TPA_MODE_GRO) | |
13577 | flags |= VFPF_QUEUE_FLG_TPA_GRO; | |
13578 | tpa_agg_size = TPA_AGG_SIZE; | |
13579 | } | |
13580 | ||
13581 | /* calculate queue flags */ | |
13582 | flags |= VFPF_QUEUE_FLG_STATS; | |
13583 | flags |= VFPF_QUEUE_FLG_CACHE_ALIGN; | |
13584 | flags |= IS_MF_SD(bp) ? VFPF_QUEUE_FLG_OV : 0; | |
13585 | flags |= VFPF_QUEUE_FLG_VLAN; | |
13586 | DP(NETIF_MSG_IFUP, "vlan removal enabled\n"); | |
13587 | ||
13588 | /* Common */ | |
13589 | req->vf_qid = fp_idx; | |
13590 | req->param_valid = VFPF_RXQ_VALID | VFPF_TXQ_VALID; | |
13591 | ||
13592 | /* Rx */ | |
13593 | req->rxq.rcq_addr = fp->rx_comp_mapping; | |
13594 | req->rxq.rcq_np_addr = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
13595 | req->rxq.rxq_addr = fp->rx_desc_mapping; | |
13596 | req->rxq.sge_addr = fp->rx_sge_mapping; | |
13597 | req->rxq.vf_sb = fp_idx; | |
13598 | req->rxq.sb_index = HC_INDEX_ETH_RX_CQ_CONS; | |
13599 | req->rxq.hc_rate = bp->rx_ticks ? 1000000/bp->rx_ticks : 0; | |
13600 | req->rxq.mtu = bp->dev->mtu; | |
13601 | req->rxq.buf_sz = fp->rx_buf_size; | |
13602 | req->rxq.sge_buf_sz = BCM_PAGE_SIZE * PAGES_PER_SGE; | |
13603 | req->rxq.tpa_agg_sz = tpa_agg_size; | |
13604 | req->rxq.max_sge_pkt = SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT; | |
13605 | req->rxq.max_sge_pkt = ((req->rxq.max_sge_pkt + PAGES_PER_SGE - 1) & | |
13606 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
13607 | req->rxq.flags = flags; | |
13608 | req->rxq.drop_flags = 0; | |
13609 | req->rxq.cache_line_log = BNX2X_RX_ALIGN_SHIFT; | |
13610 | req->rxq.stat_id = -1; /* No stats at the moment */ | |
13611 | ||
13612 | /* Tx */ | |
13613 | req->txq.txq_addr = fp->txdata_ptr[FIRST_TX_COS_INDEX]->tx_desc_mapping; | |
13614 | req->txq.vf_sb = fp_idx; | |
13615 | req->txq.sb_index = HC_INDEX_ETH_TX_CQ_CONS_COS0; | |
13616 | req->txq.hc_rate = bp->tx_ticks ? 1000000/bp->tx_ticks : 0; | |
13617 | req->txq.flags = flags; | |
13618 | req->txq.traffic_type = LLFC_TRAFFIC_TYPE_NW; | |
13619 | ||
13620 | /* add list termination tlv */ | |
13621 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, | |
13622 | sizeof(struct channel_list_end_tlv)); | |
13623 | ||
13624 | /* output tlvs list */ | |
13625 | bnx2x_dp_tlv_list(bp, req); | |
13626 | ||
13627 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | |
13628 | if (rc) | |
13629 | BNX2X_ERR("Sending SETUP_Q message for queue[%d] failed!\n", | |
13630 | fp_idx); | |
13631 | ||
13632 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | |
13633 | BNX2X_ERR("Status of SETUP_Q for queue[%d] is %d\n", | |
13634 | fp_idx, resp->hdr.status); | |
13635 | return -EINVAL; | |
13636 | } | |
13637 | return rc; | |
13638 | } | |
13639 | ||
9b176b6b AE |
13640 | int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx) |
13641 | { | |
13642 | struct vfpf_q_op_tlv *req = &bp->vf2pf_mbox->req.q_op; | |
13643 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; | |
13644 | int rc; | |
13645 | ||
13646 | /* clear mailbox and prep first tlv */ | |
13647 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_TEARDOWN_Q, | |
13648 | sizeof(*req)); | |
13649 | ||
13650 | req->vf_qid = qidx; | |
13651 | ||
13652 | /* add list termination tlv */ | |
13653 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, | |
13654 | sizeof(struct channel_list_end_tlv)); | |
13655 | ||
13656 | /* output tlvs list */ | |
13657 | bnx2x_dp_tlv_list(bp, req); | |
13658 | ||
13659 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | |
13660 | ||
13661 | if (rc) { | |
13662 | BNX2X_ERR("Sending TEARDOWN for queue %d failed: %d\n", qidx, | |
13663 | rc); | |
13664 | return rc; | |
13665 | } | |
13666 | ||
13667 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | |
13668 | BNX2X_ERR("TEARDOWN for queue %d failed: %d\n", qidx, | |
13669 | resp->hdr.status); | |
13670 | return -EINVAL; | |
13671 | } | |
13672 | ||
13673 | return 0; | |
13674 | } | |
13675 | ||
8d9ac297 AE |
13676 | /* request pf to add a mac for the vf */ |
13677 | int bnx2x_vfpf_set_mac(struct bnx2x *bp) | |
13678 | { | |
13679 | struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters; | |
13680 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; | |
13681 | int rc; | |
13682 | ||
13683 | /* clear mailbox and prep first tlv */ | |
13684 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS, | |
13685 | sizeof(*req)); | |
13686 | ||
13687 | req->flags = VFPF_SET_Q_FILTERS_MAC_VLAN_CHANGED; | |
13688 | req->vf_qid = 0; | |
13689 | req->n_mac_vlan_filters = 1; | |
13690 | req->filters[0].flags = | |
13691 | VFPF_Q_FILTER_DEST_MAC_VALID | VFPF_Q_FILTER_SET_MAC; | |
13692 | ||
13693 | /* copy mac from device to request */ | |
13694 | memcpy(req->filters[0].mac, bp->dev->dev_addr, ETH_ALEN); | |
13695 | ||
13696 | /* add list termination tlv */ | |
13697 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, | |
13698 | sizeof(struct channel_list_end_tlv)); | |
13699 | ||
13700 | /* output tlvs list */ | |
13701 | bnx2x_dp_tlv_list(bp, req); | |
13702 | ||
13703 | /* send message to pf */ | |
13704 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | |
13705 | if (rc) { | |
13706 | BNX2X_ERR("failed to send message to pf. rc was %d\n", rc); | |
13707 | return rc; | |
13708 | } | |
13709 | ||
13710 | /* PF failed the transaction */ | |
13711 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | |
13712 | BNX2X_ERR("vfpf SET MAC failed: %d\n", resp->hdr.status); | |
13713 | return -EINVAL; | |
13714 | } | |
13715 | ||
13716 | return 0; | |
13717 | } | |
381ac16b AE |
13718 | |
13719 | int bnx2x_vfpf_set_mcast(struct net_device *dev) | |
13720 | { | |
13721 | struct bnx2x *bp = netdev_priv(dev); | |
13722 | struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters; | |
13723 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; | |
13724 | int rc, i = 0; | |
13725 | struct netdev_hw_addr *ha; | |
13726 | ||
13727 | if (bp->state != BNX2X_STATE_OPEN) { | |
13728 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
13729 | return -EINVAL; | |
13730 | } | |
13731 | ||
13732 | /* clear mailbox and prep first tlv */ | |
13733 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS, | |
13734 | sizeof(*req)); | |
13735 | ||
13736 | /* Get Rx mode requested */ | |
13737 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags); | |
13738 | ||
13739 | netdev_for_each_mc_addr(ha, dev) { | |
13740 | DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n", | |
13741 | bnx2x_mc_addr(ha)); | |
13742 | memcpy(req->multicast[i], bnx2x_mc_addr(ha), ETH_ALEN); | |
13743 | i++; | |
13744 | } | |
13745 | ||
13746 | /* We support four PFVF_MAX_MULTICAST_PER_VF mcast | |
13747 | * addresses tops | |
13748 | */ | |
13749 | if (i >= PFVF_MAX_MULTICAST_PER_VF) { | |
13750 | DP(NETIF_MSG_IFUP, | |
13751 | "VF supports not more than %d multicast MAC addresses\n", | |
13752 | PFVF_MAX_MULTICAST_PER_VF); | |
13753 | return -EINVAL; | |
13754 | } | |
13755 | ||
13756 | req->n_multicast = i; | |
13757 | req->flags |= VFPF_SET_Q_FILTERS_MULTICAST_CHANGED; | |
13758 | req->vf_qid = 0; | |
13759 | ||
13760 | /* add list termination tlv */ | |
13761 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, | |
13762 | sizeof(struct channel_list_end_tlv)); | |
13763 | ||
13764 | /* output tlvs list */ | |
13765 | bnx2x_dp_tlv_list(bp, req); | |
13766 | ||
13767 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | |
13768 | if (rc) { | |
13769 | BNX2X_ERR("Sending a message failed: %d\n", rc); | |
13770 | return rc; | |
13771 | } | |
13772 | ||
13773 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | |
13774 | BNX2X_ERR("Set Rx mode/multicast failed: %d\n", | |
13775 | resp->hdr.status); | |
13776 | return -EINVAL; | |
13777 | } | |
13778 | ||
13779 | return 0; | |
13780 | } | |
13781 | ||
13782 | int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp) | |
13783 | { | |
13784 | int mode = bp->rx_mode; | |
13785 | struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters; | |
13786 | struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp; | |
13787 | int rc; | |
13788 | ||
13789 | /* clear mailbox and prep first tlv */ | |
13790 | bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS, | |
13791 | sizeof(*req)); | |
13792 | ||
13793 | DP(NETIF_MSG_IFUP, "Rx mode is %d\n", mode); | |
13794 | ||
13795 | switch (mode) { | |
13796 | case BNX2X_RX_MODE_NONE: /* no Rx */ | |
13797 | req->rx_mask = VFPF_RX_MASK_ACCEPT_NONE; | |
13798 | break; | |
13799 | case BNX2X_RX_MODE_NORMAL: | |
13800 | req->rx_mask = VFPF_RX_MASK_ACCEPT_MATCHED_MULTICAST; | |
13801 | req->rx_mask |= VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST; | |
13802 | req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST; | |
13803 | break; | |
13804 | case BNX2X_RX_MODE_ALLMULTI: | |
13805 | req->rx_mask = VFPF_RX_MASK_ACCEPT_ALL_MULTICAST; | |
13806 | req->rx_mask |= VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST; | |
13807 | req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST; | |
13808 | break; | |
13809 | case BNX2X_RX_MODE_PROMISC: | |
13810 | req->rx_mask = VFPF_RX_MASK_ACCEPT_ALL_UNICAST; | |
13811 | req->rx_mask |= VFPF_RX_MASK_ACCEPT_ALL_MULTICAST; | |
13812 | req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST; | |
13813 | break; | |
13814 | default: | |
13815 | BNX2X_ERR("BAD rx mode (%d)\n", mode); | |
13816 | return -EINVAL; | |
13817 | } | |
13818 | ||
13819 | req->flags |= VFPF_SET_Q_FILTERS_RX_MASK_CHANGED; | |
13820 | req->vf_qid = 0; | |
13821 | ||
13822 | /* add list termination tlv */ | |
13823 | bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END, | |
13824 | sizeof(struct channel_list_end_tlv)); | |
13825 | ||
13826 | /* output tlvs list */ | |
13827 | bnx2x_dp_tlv_list(bp, req); | |
13828 | ||
13829 | rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping); | |
13830 | if (rc) | |
13831 | BNX2X_ERR("Sending a message failed: %d\n", rc); | |
13832 | ||
13833 | if (resp->hdr.status != PFVF_STATUS_SUCCESS) { | |
13834 | BNX2X_ERR("Set Rx mode failed: %d\n", resp->hdr.status); | |
13835 | return -EINVAL; | |
13836 | } | |
13837 | ||
13838 | return rc; | |
13839 | } |