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bnx2x: Removing indirect register access
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/dma-mapping.h>
35#include <linux/bitops.h>
36#include <linux/irq.h>
37#include <linux/delay.h>
38#include <asm/byteorder.h>
39#include <linux/time.h>
40#include <linux/ethtool.h>
41#include <linux/mii.h>
01789349 42#include <linux/if.h>
0c6671b0 43#include <linux/if_vlan.h>
a2fbb9ea 44#include <net/ip.h>
619c5cb6 45#include <net/ipv6.h>
a2fbb9ea
ET		 46#include <net/tcp.h>
47#include <net/checksum.h>
34f80b04 48#include <net/ip6_checksum.h>
a2fbb9ea
ET		 49#include <linux/workqueue.h>
50#include <linux/crc32.h>
34f80b04 51#include <linux/crc32c.h>
a2fbb9ea
ET		 52#include <linux/prefetch.h>
53#include <linux/zlib.h>
a2fbb9ea 54#include <linux/io.h>
45229b42 55#include <linux/stringify.h>
7ab24bfd 56#include <linux/vmalloc.h>
a2fbb9ea 57
a2fbb9ea
ET		 58#include "bnx2x.h"
59#include "bnx2x_init.h"
94a78b79 60#include "bnx2x_init_ops.h"
9f6c9258 61#include "bnx2x_cmn.h"
e4901dde 62#include "bnx2x_dcb.h"
042181f5 63#include "bnx2x_sp.h"
a2fbb9ea 64
94a78b79
VZ		 65#include <linux/firmware.h>
66#include "bnx2x_fw_file_hdr.h"
67/* FW files */
45229b42
BH		 68#define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 76
34f80b04
EG		 77/* Time in jiffies before concluding the transmitter is hung */
78#define TX_TIMEOUT (5*HZ)
a2fbb9ea 79
53a10565 80static char version[] __devinitdata =
619c5cb6 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
83
24e3fcef 84MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 85MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
a2fbb9ea
ET		 89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 91MODULE_FIRMWARE(FW_FILE_NAME_E1);
92MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 93MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 94
555f6c78
EG		 95static int multi_mode = 1;
96module_param(multi_mode, int, 0);
ca00392c
EG		 97MODULE_PARM_DESC(multi_mode, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))");
99
d6214d7a 100int num_queues;
54b9ddaa
VZ		 101module_param(num_queues, int, 0);
102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)");
555f6c78 104
19680c48 105static int disable_tpa;
19680c48 106module_param(disable_tpa, int, 0);
9898f86d 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 108
9ee3d37b
DK		 109#define INT_MODE_INTx 1
110#define INT_MODE_MSI 2
8badd27a
EG		 111static int int_mode;
112module_param(int_mode, int, 0);
619c5cb6 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 114 "(1 INT#x; 2 MSI)");
8badd27a 115
a18f5128
EG		 116static int dropless_fc;
117module_param(dropless_fc, int, 0);
118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
9898f86d 120static int poll;
a2fbb9ea 121module_param(poll, int, 0);
9898f86d 122MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 123
124static int mrrs = -1;
125module_param(mrrs, int, 0);
126MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
127
9898f86d 128static int debug;
a2fbb9ea 129module_param(debug, int, 0);
9898f86d
EG		 130MODULE_PARM_DESC(debug, " Default debug msglevel");
131
a2fbb9ea 132
619c5cb6
VZ		 133
134struct workqueue_struct *bnx2x_wq;
ec6ba945 135
a2fbb9ea
ET		 136enum bnx2x_board_type {
137 BCM57710 = 0,
619c5cb6
VZ		 138 BCM57711,
139 BCM57711E,
140 BCM57712,
141 BCM57712_MF,
142 BCM57800,
143 BCM57800_MF,
144 BCM57810,
145 BCM57810_MF,
146 BCM57840,
147 BCM57840_MF
a2fbb9ea
ET		 148};
149
34f80b04 150/* indexed by board_type, above */
53a10565 151static struct {
a2fbb9ea
ET		 152 char *name;
153} board_info[] __devinitdata = {
619c5cb6
VZ		 154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
165 "Ethernet Multi Function"}
a2fbb9ea
ET		 166};
167
619c5cb6
VZ		 168#ifndef PCI_DEVICE_ID_NX2_57710
169#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
170#endif
171#ifndef PCI_DEVICE_ID_NX2_57711
172#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
173#endif
174#ifndef PCI_DEVICE_ID_NX2_57711E
175#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
176#endif
177#ifndef PCI_DEVICE_ID_NX2_57712
178#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
179#endif
180#ifndef PCI_DEVICE_ID_NX2_57712_MF
181#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
182#endif
183#ifndef PCI_DEVICE_ID_NX2_57800
184#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
185#endif
186#ifndef PCI_DEVICE_ID_NX2_57800_MF
187#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
188#endif
189#ifndef PCI_DEVICE_ID_NX2_57810
190#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
191#endif
192#ifndef PCI_DEVICE_ID_NX2_57810_MF
193#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
194#endif
195#ifndef PCI_DEVICE_ID_NX2_57840
196#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
197#endif
198#ifndef PCI_DEVICE_ID_NX2_57840_MF
199#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
200#endif
a3aa1884 201static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
a2fbb9ea
ET		 213 { 0 }
214};
215
216MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
217
218/****************************************************************************
219* General service functions
220****************************************************************************/
221
619c5cb6
VZ		 222static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
223 u32 addr, dma_addr_t mapping)
224{
225 REG_WR(bp, addr, U64_LO(mapping));
226 REG_WR(bp, addr + 4, U64_HI(mapping));
227}
228
229static inline void storm_memset_spq_addr(struct bnx2x *bp,
230 dma_addr_t mapping, u16 abs_fid)
231{
232 u32 addr = XSEM_REG_FAST_MEMORY +
233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
234
235 __storm_memset_dma_mapping(bp, addr, mapping);
236}
237
238static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
239 u16 pf_id)
523224a3 240{
619c5cb6
VZ		 241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
242 pf_id);
243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
244 pf_id);
245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
246 pf_id);
247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
248 pf_id);
523224a3
DK		 249}
250
619c5cb6
VZ		 251static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
252 u8 enable)
253{
254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
255 enable);
256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
257 enable);
258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
259 enable);
260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
261 enable);
262}
523224a3
DK		 263
264static inline void storm_memset_eq_data(struct bnx2x *bp,
265 struct event_ring_data *eq_data,
266 u16 pfid)
267{
268 size_t size = sizeof(struct event_ring_data);
269
270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
271
272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
273}
274
275static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
276 u16 pfid)
277{
278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
279 REG_WR16(bp, addr, eq_prod);
280}
281
a2fbb9ea
ET		 282/* used only at init
283 * locking is done by mcp
284 */
8d96286a 285static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 286{
287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
290 PCICFG_VENDOR_ID_OFFSET);
291}
292
a2fbb9ea
ET		 293static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
294{
295 u32 val;
296
297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
300 PCICFG_VENDOR_ID_OFFSET);
301
302 return val;
303}
a2fbb9ea 304
f2e0899f
DK		 305#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
306#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
307#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
308#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
309#define DMAE_DP_DST_NONE "dst_addr [none]"
310
8d96286a 311static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
312 int msglvl)
f2e0899f
DK		 313{
314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
315
316 switch (dmae->opcode & DMAE_COMMAND_DST) {
317 case DMAE_CMD_DST_PCI:
318 if (src_type == DMAE_CMD_SRC_PCI)
319 DP(msglvl, "DMAE: opcode 0x%08x\n"
320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
321 "comp_addr [%x:%08x], comp_val 0x%08x\n",
322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
324 dmae->comp_addr_hi, dmae->comp_addr_lo,
325 dmae->comp_val);
326 else
327 DP(msglvl, "DMAE: opcode 0x%08x\n"
328 "src [%08x], len [%d*4], dst [%x:%08x]\n"
329 "comp_addr [%x:%08x], comp_val 0x%08x\n",
330 dmae->opcode, dmae->src_addr_lo >> 2,
331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
332 dmae->comp_addr_hi, dmae->comp_addr_lo,
333 dmae->comp_val);
334 break;
335 case DMAE_CMD_DST_GRC:
336 if (src_type == DMAE_CMD_SRC_PCI)
337 DP(msglvl, "DMAE: opcode 0x%08x\n"
338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
339 "comp_addr [%x:%08x], comp_val 0x%08x\n",
340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
341 dmae->len, dmae->dst_addr_lo >> 2,
342 dmae->comp_addr_hi, dmae->comp_addr_lo,
343 dmae->comp_val);
344 else
345 DP(msglvl, "DMAE: opcode 0x%08x\n"
346 "src [%08x], len [%d*4], dst [%08x]\n"
347 "comp_addr [%x:%08x], comp_val 0x%08x\n",
348 dmae->opcode, dmae->src_addr_lo >> 2,
349 dmae->len, dmae->dst_addr_lo >> 2,
350 dmae->comp_addr_hi, dmae->comp_addr_lo,
351 dmae->comp_val);
352 break;
353 default:
354 if (src_type == DMAE_CMD_SRC_PCI)
355 DP(msglvl, "DMAE: opcode 0x%08x\n"
f1deab50
JP		 356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
357 "comp_addr [%x:%08x] comp_val 0x%08x\n",
f2e0899f
DK		 358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
360 dmae->comp_val);
361 else
362 DP(msglvl, "DMAE: opcode 0x%08x\n"
f1deab50
JP		 363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
364 "comp_addr [%x:%08x] comp_val 0x%08x\n",
f2e0899f
DK		 365 dmae->opcode, dmae->src_addr_lo >> 2,
366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
367 dmae->comp_val);
368 break;
369 }
370
371}
372
a2fbb9ea 373/* copy command into DMAE command memory and set DMAE command go */
6c719d00 374void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 375{
376 u32 cmd_offset;
377 int i;
378
379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
382
ad8d3948
EG		 383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 385 }
386 REG_WR(bp, dmae_reg_go_c[idx], 1);
387}
388
f2e0899f 389u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 390{
f2e0899f
DK		 391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
392 DMAE_CMD_C_ENABLE);
393}
ad8d3948 394
f2e0899f
DK		 395u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
396{
397 return opcode & ~DMAE_CMD_SRC_RESET;
398}
ad8d3948 399
f2e0899f
DK		 400u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
401 bool with_comp, u8 comp_type)
402{
403 u32 opcode = 0;
404
405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
406 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 407
f2e0899f
DK		 408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
409
410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 414
a2fbb9ea 415#ifdef __BIG_ENDIAN
f2e0899f 416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 417#else
f2e0899f 418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 419#endif
f2e0899f
DK		 420 if (with_comp)
421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
422 return opcode;
423}
424
8d96286a 425static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
426 struct dmae_command *dmae,
427 u8 src_type, u8 dst_type)
f2e0899f
DK		 428{
429 memset(dmae, 0, sizeof(struct dmae_command));
430
431 /* set the opcode */
432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
433 true, DMAE_COMP_PCI);
434
435 /* fill in the completion parameters */
436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
438 dmae->comp_val = DMAE_COMP_VAL;
439}
440
441/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 442static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
443 struct dmae_command *dmae)
f2e0899f
DK		 444{
445 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 447 int rc = 0;
448
449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 452
619c5cb6
VZ		 453 /*
454 * Lock the dmae channel. Disable BHs to prevent a dead-lock
455 * as long as this code is called both from syscall context and
456 * from ndo_set_rx_mode() flow that may be called from BH.
457 */
6e30dd4e 458 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 459
f2e0899f 460 /* reset completion */
a2fbb9ea
ET		 461 *wb_comp = 0;
462
f2e0899f
DK		 463 /* post the command on the channel used for initializations */
464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 465
f2e0899f 466 /* wait for completion */
a2fbb9ea 467 udelay(5);
f2e0899f 468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
470
ad8d3948 471 if (!cnt) {
c3eefaf6 472 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 473 rc = DMAE_TIMEOUT;
474 goto unlock;
a2fbb9ea 475 }
ad8d3948 476 cnt--;
f2e0899f 477 udelay(50);
a2fbb9ea 478 }
f2e0899f
DK		 479 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
480 BNX2X_ERR("DMAE PCI error!\n");
481 rc = DMAE_PCI_ERROR;
482 }
483
484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 487
f2e0899f 488unlock:
6e30dd4e 489 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 490 return rc;
491}
492
493void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
494 u32 len32)
495{
496 struct dmae_command dmae;
497
498 if (!bp->dmae_ready) {
499 u32 *data = bnx2x_sp(bp, wb_data[0]);
500
127a425e
AE		 501 DP(BNX2X_MSG_OFF,
502 "DMAE is not ready (dst_addr %08x len32 %d) using indirect\n",
503 dst_addr, len32);
504 if (CHIP_IS_E1(bp))
505 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
506 else
507 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 508 return;
509 }
510
511 /* set opcode and fixed command fields */
512 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
513
514 /* fill in addresses and len */
515 dmae.src_addr_lo = U64_LO(dma_addr);
516 dmae.src_addr_hi = U64_HI(dma_addr);
517 dmae.dst_addr_lo = dst_addr >> 2;
518 dmae.dst_addr_hi = 0;
519 dmae.len = len32;
520
521 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
522
523 /* issue the command and wait for completion */
524 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 525}
526
c18487ee 527void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 528{
5ff7b6d4 529 struct dmae_command dmae;
ad8d3948
EG		 530
531 if (!bp->dmae_ready) {
532 u32 *data = bnx2x_sp(bp, wb_data[0]);
533 int i;
534
127a425e
AE		 535 if (CHIP_IS_E1(bp)) {
536 DP(BNX2X_MSG_OFF,
537 "DMAE is not ready (src_addr %08x len32 %d) using indirect\n",
538 src_addr, len32);
539 for (i = 0; i < len32; i++)
540 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
541 } else
542 for (i = 0; i < len32; i++)
543 data[i] = REG_RD(bp, src_addr + i*4);
544
ad8d3948
EG		 545 return;
546 }
547
f2e0899f
DK		 548 /* set opcode and fixed command fields */
549 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 550
f2e0899f 551 /* fill in addresses and len */
5ff7b6d4
EG		 552 dmae.src_addr_lo = src_addr >> 2;
553 dmae.src_addr_hi = 0;
554 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
555 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
556 dmae.len = len32;
ad8d3948 557
f2e0899f 558 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 559
f2e0899f
DK		 560 /* issue the command and wait for completion */
561 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 562}
563
8d96286a 564static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
565 u32 addr, u32 len)
573f2035 566{
02e3c6cb 567 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 568 int offset = 0;
569
02e3c6cb 570 while (len > dmae_wr_max) {
573f2035 571 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 572 addr + offset, dmae_wr_max);
573 offset += dmae_wr_max * 4;
574 len -= dmae_wr_max;
573f2035
EG		 575 }
576
577 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
578}
579
ad8d3948
EG		 580/* used only for slowpath so not inlined */
581static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
582{
583 u32 wb_write[2];
584
585 wb_write[0] = val_hi;
586 wb_write[1] = val_lo;
587 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 588}
a2fbb9ea 589
ad8d3948
EG		 590#ifdef USE_WB_RD
591static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
592{
593 u32 wb_data[2];
594
595 REG_RD_DMAE(bp, reg, wb_data, 2);
596
597 return HILO_U64(wb_data[0], wb_data[1]);
598}
599#endif
600
a2fbb9ea
ET		 601static int bnx2x_mc_assert(struct bnx2x *bp)
602{
a2fbb9ea 603 char last_idx;
34f80b04
EG		 604 int i, rc = 0;
605 u32 row0, row1, row2, row3;
606
607 /* XSTORM */
608 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
609 XSTORM_ASSERT_LIST_INDEX_OFFSET);
610 if (last_idx)
611 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
612
613 /* print the asserts */
614 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
615
616 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
617 XSTORM_ASSERT_LIST_OFFSET(i));
618 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
619 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
620 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
621 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
622 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
623 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
624
625 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
626 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
627 " 0x%08x 0x%08x 0x%08x\n",
628 i, row3, row2, row1, row0);
629 rc++;
630 } else {
631 break;
632 }
633 }
634
635 /* TSTORM */
636 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
637 TSTORM_ASSERT_LIST_INDEX_OFFSET);
638 if (last_idx)
639 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
640
641 /* print the asserts */
642 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
643
644 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
645 TSTORM_ASSERT_LIST_OFFSET(i));
646 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
647 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
648 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
649 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
650 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
651 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
652
653 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
654 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
655 " 0x%08x 0x%08x 0x%08x\n",
656 i, row3, row2, row1, row0);
657 rc++;
658 } else {
659 break;
660 }
661 }
662
663 /* CSTORM */
664 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
665 CSTORM_ASSERT_LIST_INDEX_OFFSET);
666 if (last_idx)
667 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
668
669 /* print the asserts */
670 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
671
672 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
673 CSTORM_ASSERT_LIST_OFFSET(i));
674 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
675 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
676 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
677 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
678 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
679 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
680
681 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
682 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
683 " 0x%08x 0x%08x 0x%08x\n",
684 i, row3, row2, row1, row0);
685 rc++;
686 } else {
687 break;
688 }
689 }
690
691 /* USTORM */
692 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_INDEX_OFFSET);
694 if (last_idx)
695 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
696
697 /* print the asserts */
698 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
699
700 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
701 USTORM_ASSERT_LIST_OFFSET(i));
702 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
703 USTORM_ASSERT_LIST_OFFSET(i) + 4);
704 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
705 USTORM_ASSERT_LIST_OFFSET(i) + 8);
706 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
707 USTORM_ASSERT_LIST_OFFSET(i) + 12);
708
709 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
710 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
711 " 0x%08x 0x%08x 0x%08x\n",
712 i, row3, row2, row1, row0);
713 rc++;
714 } else {
715 break;
a2fbb9ea
ET		 716 }
717 }
34f80b04 718
a2fbb9ea
ET		 719 return rc;
720}
c14423fe 721
7a25cc73 722void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 723{
7a25cc73 724 u32 addr, val;
a2fbb9ea 725 u32 mark, offset;
4781bfad 726 __be32 data[9];
a2fbb9ea 727 int word;
f2e0899f 728 u32 trace_shmem_base;
2145a920
VZ		 729 if (BP_NOMCP(bp)) {
730 BNX2X_ERR("NO MCP - can not dump\n");
731 return;
732 }
7a25cc73
DK		 733 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
734 (bp->common.bc_ver & 0xff0000) >> 16,
735 (bp->common.bc_ver & 0xff00) >> 8,
736 (bp->common.bc_ver & 0xff));
737
738 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
739 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
740 printk("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 741
f2e0899f
DK		 742 if (BP_PATH(bp) == 0)
743 trace_shmem_base = bp->common.shmem_base;
744 else
745 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
746 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 747 mark = REG_RD(bp, addr);
f2e0899f
DK		 748 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
749 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 750 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 751
7a25cc73 752 printk("%s", lvl);
f2e0899f 753 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 754 for (word = 0; word < 8; word++)
cdaa7cb8 755 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 756 data[8] = 0x0;
7995c64e 757 pr_cont("%s", (char *)data);
a2fbb9ea 758 }
cdaa7cb8 759 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 760 for (word = 0; word < 8; word++)
cdaa7cb8 761 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 762 data[8] = 0x0;
7995c64e 763 pr_cont("%s", (char *)data);
a2fbb9ea 764 }
7a25cc73
DK		 765 printk("%s" "end of fw dump\n", lvl);
766}
767
768static inline void bnx2x_fw_dump(struct bnx2x *bp)
769{
770 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 771}
772
6c719d00 773void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 774{
775 int i;
523224a3
DK		 776 u16 j;
777 struct hc_sp_status_block_data sp_sb_data;
778 int func = BP_FUNC(bp);
779#ifdef BNX2X_STOP_ON_ERROR
780 u16 start = 0, end = 0;
6383c0b3 781 u8 cos;
523224a3 782#endif
a2fbb9ea 783
66e855f3
YG		 784 bp->stats_state = STATS_STATE_DISABLED;
785 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
786
a2fbb9ea
ET		 787 BNX2X_ERR("begin crash dump -----------------\n");
788
8440d2b6
EG		 789 /* Indices */
790 /* Common */
523224a3 791 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
619c5cb6
VZ		 792 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
793 bp->def_idx, bp->def_att_idx, bp->attn_state,
794 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 795 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
796 bp->def_status_blk->atten_status_block.attn_bits,
797 bp->def_status_blk->atten_status_block.attn_bits_ack,
798 bp->def_status_blk->atten_status_block.status_block_id,
799 bp->def_status_blk->atten_status_block.attn_bits_index);
800 BNX2X_ERR(" def (");
801 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
802 pr_cont("0x%x%s",
f1deab50
JP		 803 bp->def_status_blk->sp_sb.index_values[i],
804 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
523224a3
DK		 805
806 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
807 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
808 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
809 i*sizeof(u32));
810
f1deab50 811 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
523224a3
DK		 812 sp_sb_data.igu_sb_id,
813 sp_sb_data.igu_seg_id,
814 sp_sb_data.p_func.pf_id,
815 sp_sb_data.p_func.vnic_id,
816 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 817 sp_sb_data.p_func.vf_valid,
818 sp_sb_data.state);
523224a3 819
8440d2b6 820
ec6ba945 821 for_each_eth_queue(bp, i) {
a2fbb9ea 822 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 823 int loop;
f2e0899f 824 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 825 struct hc_status_block_data_e1x sb_data_e1x;
826 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 827 CHIP_IS_E1x(bp) ?
828 sb_data_e1x.common.state_machine :
829 sb_data_e2.common.state_machine;
523224a3 830 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 831 CHIP_IS_E1x(bp) ?
832 sb_data_e1x.index_data :
833 sb_data_e2.index_data;
6383c0b3 834 u8 data_size, cos;
523224a3 835 u32 *sb_data_p;
6383c0b3 836 struct bnx2x_fp_txdata txdata;
523224a3
DK		 837
838 /* Rx */
cdaa7cb8 839 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 840 " rx_comp_prod(0x%x)"
cdaa7cb8 841 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 842 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 843 fp->rx_comp_prod,
66e855f3 844 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 845 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 846 " fp_hc_idx(0x%x)\n",
8440d2b6 847 fp->rx_sge_prod, fp->last_max_sge,
523224a3 848 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 849
523224a3 850 /* Tx */
6383c0b3
AE		 851 for_each_cos_in_tx_queue(fp, cos)
852 {
853 txdata = fp->txdata[cos];
854 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
855 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
856 " *tx_cons_sb(0x%x)\n",
857 i, txdata.tx_pkt_prod,
858 txdata.tx_pkt_cons, txdata.tx_bd_prod,
859 txdata.tx_bd_cons,
860 le16_to_cpu(*txdata.tx_cons_sb));
861 }
523224a3 862
619c5cb6
VZ		 863 loop = CHIP_IS_E1x(bp) ?
864 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 865
866 /* host sb data */
867
ec6ba945
VZ		 868#ifdef BCM_CNIC
869 if (IS_FCOE_FP(fp))
870 continue;
871#endif
523224a3
DK		 872 BNX2X_ERR(" run indexes (");
873 for (j = 0; j < HC_SB_MAX_SM; j++)
874 pr_cont("0x%x%s",
875 fp->sb_running_index[j],
876 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
877
878 BNX2X_ERR(" indexes (");
879 for (j = 0; j < loop; j++)
880 pr_cont("0x%x%s",
881 fp->sb_index_values[j],
882 (j == loop - 1) ? ")" : " ");
883 /* fw sb data */
619c5cb6
VZ		 884 data_size = CHIP_IS_E1x(bp) ?
885 sizeof(struct hc_status_block_data_e1x) :
886 sizeof(struct hc_status_block_data_e2);
523224a3 887 data_size /= sizeof(u32);
619c5cb6
VZ		 888 sb_data_p = CHIP_IS_E1x(bp) ?
889 (u32 *)&sb_data_e1x :
890 (u32 *)&sb_data_e2;
523224a3
DK		 891 /* copy sb data in here */
892 for (j = 0; j < data_size; j++)
893 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
894 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
895 j * sizeof(u32));
896
619c5cb6
VZ		 897 if (!CHIP_IS_E1x(bp)) {
898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
900 "state(0x%x)\n",
f2e0899f
DK		 901 sb_data_e2.common.p_func.pf_id,
902 sb_data_e2.common.p_func.vf_id,
903 sb_data_e2.common.p_func.vf_valid,
904 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 905 sb_data_e2.common.same_igu_sb_1b,
906 sb_data_e2.common.state);
f2e0899f 907 } else {
619c5cb6
VZ		 908 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
909 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
910 "state(0x%x)\n",
f2e0899f
DK		 911 sb_data_e1x.common.p_func.pf_id,
912 sb_data_e1x.common.p_func.vf_id,
913 sb_data_e1x.common.p_func.vf_valid,
914 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 915 sb_data_e1x.common.same_igu_sb_1b,
916 sb_data_e1x.common.state);
f2e0899f 917 }
523224a3
DK		 918
919 /* SB_SMs data */
920 for (j = 0; j < HC_SB_MAX_SM; j++) {
921 pr_cont("SM[%d] __flags (0x%x) "
922 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
923 "time_to_expire (0x%x) "
924 "timer_value(0x%x)\n", j,
925 hc_sm_p[j].__flags,
926 hc_sm_p[j].igu_sb_id,
927 hc_sm_p[j].igu_seg_id,
928 hc_sm_p[j].time_to_expire,
929 hc_sm_p[j].timer_value);
930 }
931
932 /* Indecies data */
933 for (j = 0; j < loop; j++) {
934 pr_cont("INDEX[%d] flags (0x%x) "
935 "timeout (0x%x)\n", j,
936 hc_index_p[j].flags,
937 hc_index_p[j].timeout);
938 }
8440d2b6 939 }
a2fbb9ea 940
523224a3 941#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 942 /* Rings */
943 /* Rx */
ec6ba945 944 for_each_rx_queue(bp, i) {
8440d2b6 945 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 946
947 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
948 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 949 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 950 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
951 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
952
c3eefaf6 953 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 954 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 955 }
956
3196a88a
EG		 957 start = RX_SGE(fp->rx_sge_prod);
958 end = RX_SGE(fp->last_max_sge);
8440d2b6 959 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 960 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
961 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
962
c3eefaf6
EG		 963 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
964 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 965 }
966
a2fbb9ea
ET		 967 start = RCQ_BD(fp->rx_comp_cons - 10);
968 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 969 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 970 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
971
c3eefaf6
EG		 972 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
973 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 974 }
975 }
976
8440d2b6 977 /* Tx */
ec6ba945 978 for_each_tx_queue(bp, i) {
8440d2b6 979 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3
AE		 980 for_each_cos_in_tx_queue(fp, cos) {
981 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
982
983 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
984 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
985 for (j = start; j != end; j = TX_BD(j + 1)) {
986 struct sw_tx_bd *sw_bd =
987 &txdata->tx_buf_ring[j];
988
989 BNX2X_ERR("fp%d: txdata %d, "
990 "packet[%x]=[%p,%x]\n",
991 i, cos, j, sw_bd->skb,
992 sw_bd->first_bd);
993 }
8440d2b6 994
6383c0b3
AE		 995 start = TX_BD(txdata->tx_bd_cons - 10);
996 end = TX_BD(txdata->tx_bd_cons + 254);
997 for (j = start; j != end; j = TX_BD(j + 1)) {
998 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 999
6383c0b3
AE		 1000 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
1001 "[%x:%x:%x:%x]\n",
1002 i, cos, j, tx_bd[0], tx_bd[1],
1003 tx_bd[2], tx_bd[3]);
1004 }
8440d2b6
EG		 1005 }
1006 }
523224a3 1007#endif
34f80b04 1008 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1009 bnx2x_mc_assert(bp);
1010 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1011}
1012
619c5cb6
VZ		 1013/*
1014 * FLR Support for E2
1015 *
1016 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1017 * initialization.
1018 */
1019#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1020#define FLR_WAIT_INTERAVAL 50 /* usec */
1021#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1022
1023struct pbf_pN_buf_regs {
1024 int pN;
1025 u32 init_crd;
1026 u32 crd;
1027 u32 crd_freed;
1028};
1029
1030struct pbf_pN_cmd_regs {
1031 int pN;
1032 u32 lines_occup;
1033 u32 lines_freed;
1034};
1035
1036static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1037 struct pbf_pN_buf_regs *regs,
1038 u32 poll_count)
1039{
1040 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1041 u32 cur_cnt = poll_count;
1042
1043 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1044 crd = crd_start = REG_RD(bp, regs->crd);
1045 init_crd = REG_RD(bp, regs->init_crd);
1046
1047 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1048 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1049 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1050
1051 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1052 (init_crd - crd_start))) {
1053 if (cur_cnt--) {
1054 udelay(FLR_WAIT_INTERAVAL);
1055 crd = REG_RD(bp, regs->crd);
1056 crd_freed = REG_RD(bp, regs->crd_freed);
1057 } else {
1058 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1059 regs->pN);
1060 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1061 regs->pN, crd);
1062 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1063 regs->pN, crd_freed);
1064 break;
1065 }
1066 }
1067 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1068 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1069}
1070
1071static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1072 struct pbf_pN_cmd_regs *regs,
1073 u32 poll_count)
1074{
1075 u32 occup, to_free, freed, freed_start;
1076 u32 cur_cnt = poll_count;
1077
1078 occup = to_free = REG_RD(bp, regs->lines_occup);
1079 freed = freed_start = REG_RD(bp, regs->lines_freed);
1080
1081 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1082 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1083
1084 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1085 if (cur_cnt--) {
1086 udelay(FLR_WAIT_INTERAVAL);
1087 occup = REG_RD(bp, regs->lines_occup);
1088 freed = REG_RD(bp, regs->lines_freed);
1089 } else {
1090 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1091 regs->pN);
1092 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1093 regs->pN, occup);
1094 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1095 regs->pN, freed);
1096 break;
1097 }
1098 }
1099 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1100 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1101}
1102
1103static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1104 u32 expected, u32 poll_count)
1105{
1106 u32 cur_cnt = poll_count;
1107 u32 val;
1108
1109 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1110 udelay(FLR_WAIT_INTERAVAL);
1111
1112 return val;
1113}
1114
1115static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1116 char *msg, u32 poll_cnt)
1117{
1118 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1119 if (val != 0) {
1120 BNX2X_ERR("%s usage count=%d\n", msg, val);
1121 return 1;
1122 }
1123 return 0;
1124}
1125
1126static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1127{
1128 /* adjust polling timeout */
1129 if (CHIP_REV_IS_EMUL(bp))
1130 return FLR_POLL_CNT * 2000;
1131
1132 if (CHIP_REV_IS_FPGA(bp))
1133 return FLR_POLL_CNT * 120;
1134
1135 return FLR_POLL_CNT;
1136}
1137
1138static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1139{
1140 struct pbf_pN_cmd_regs cmd_regs[] = {
1141 {0, (CHIP_IS_E3B0(bp)) ?
1142 PBF_REG_TQ_OCCUPANCY_Q0 :
1143 PBF_REG_P0_TQ_OCCUPANCY,
1144 (CHIP_IS_E3B0(bp)) ?
1145 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1146 PBF_REG_P0_TQ_LINES_FREED_CNT},
1147 {1, (CHIP_IS_E3B0(bp)) ?
1148 PBF_REG_TQ_OCCUPANCY_Q1 :
1149 PBF_REG_P1_TQ_OCCUPANCY,
1150 (CHIP_IS_E3B0(bp)) ?
1151 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1152 PBF_REG_P1_TQ_LINES_FREED_CNT},
1153 {4, (CHIP_IS_E3B0(bp)) ?
1154 PBF_REG_TQ_OCCUPANCY_LB_Q :
1155 PBF_REG_P4_TQ_OCCUPANCY,
1156 (CHIP_IS_E3B0(bp)) ?
1157 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1158 PBF_REG_P4_TQ_LINES_FREED_CNT}
1159 };
1160
1161 struct pbf_pN_buf_regs buf_regs[] = {
1162 {0, (CHIP_IS_E3B0(bp)) ?
1163 PBF_REG_INIT_CRD_Q0 :
1164 PBF_REG_P0_INIT_CRD ,
1165 (CHIP_IS_E3B0(bp)) ?
1166 PBF_REG_CREDIT_Q0 :
1167 PBF_REG_P0_CREDIT,
1168 (CHIP_IS_E3B0(bp)) ?
1169 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1170 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1171 {1, (CHIP_IS_E3B0(bp)) ?
1172 PBF_REG_INIT_CRD_Q1 :
1173 PBF_REG_P1_INIT_CRD,
1174 (CHIP_IS_E3B0(bp)) ?
1175 PBF_REG_CREDIT_Q1 :
1176 PBF_REG_P1_CREDIT,
1177 (CHIP_IS_E3B0(bp)) ?
1178 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1179 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1180 {4, (CHIP_IS_E3B0(bp)) ?
1181 PBF_REG_INIT_CRD_LB_Q :
1182 PBF_REG_P4_INIT_CRD,
1183 (CHIP_IS_E3B0(bp)) ?
1184 PBF_REG_CREDIT_LB_Q :
1185 PBF_REG_P4_CREDIT,
1186 (CHIP_IS_E3B0(bp)) ?
1187 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1188 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1189 };
1190
1191 int i;
1192
1193 /* Verify the command queues are flushed P0, P1, P4 */
1194 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1195 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1196
1197
1198 /* Verify the transmission buffers are flushed P0, P1, P4 */
1199 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1200 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1201}
1202
1203#define OP_GEN_PARAM(param) \
1204 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1205
1206#define OP_GEN_TYPE(type) \
1207 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1208
1209#define OP_GEN_AGG_VECT(index) \
1210 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1211
1212
1213static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1214 u32 poll_cnt)
1215{
1216 struct sdm_op_gen op_gen = {0};
1217
1218 u32 comp_addr = BAR_CSTRORM_INTMEM +
1219 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1220 int ret = 0;
1221
1222 if (REG_RD(bp, comp_addr)) {
1223 BNX2X_ERR("Cleanup complete is not 0\n");
1224 return 1;
1225 }
1226
1227 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1228 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1229 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1230 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1231
1232 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1233 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1234
1235 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1236 BNX2X_ERR("FW final cleanup did not succeed\n");
1237 ret = 1;
1238 }
1239 /* Zero completion for nxt FLR */
1240 REG_WR(bp, comp_addr, 0);
1241
1242 return ret;
1243}
1244
1245static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1246{
1247 int pos;
1248 u16 status;
1249
77c98e6a 1250 pos = pci_pcie_cap(dev);
619c5cb6
VZ		 1251 if (!pos)
1252 return false;
1253
1254 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1255 return status & PCI_EXP_DEVSTA_TRPND;
1256}
1257
1258/* PF FLR specific routines
1259*/
1260static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1261{
1262
1263 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1265 CFC_REG_NUM_LCIDS_INSIDE_PF,
1266 "CFC PF usage counter timed out",
1267 poll_cnt))
1268 return 1;
1269
1270
1271 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1272 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1273 DORQ_REG_PF_USAGE_CNT,
1274 "DQ PF usage counter timed out",
1275 poll_cnt))
1276 return 1;
1277
1278 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1279 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1280 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1281 "QM PF usage counter timed out",
1282 poll_cnt))
1283 return 1;
1284
1285 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1286 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1287 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1288 "Timers VNIC usage counter timed out",
1289 poll_cnt))
1290 return 1;
1291 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1292 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1293 "Timers NUM_SCANS usage counter timed out",
1294 poll_cnt))
1295 return 1;
1296
1297 /* Wait DMAE PF usage counter to zero */
1298 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1299 dmae_reg_go_c[INIT_DMAE_C(bp)],
1300 "DMAE dommand register timed out",
1301 poll_cnt))
1302 return 1;
1303
1304 return 0;
1305}
1306
1307static void bnx2x_hw_enable_status(struct bnx2x *bp)
1308{
1309 u32 val;
1310
1311 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1312 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1313
1314 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1315 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1316
1317 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1318 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1319
1320 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1321 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1322
1323 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1324 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1325
1326 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1327 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1328
1329 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1330 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1331
1332 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1333 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1334 val);
1335}
1336
1337static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1338{
1339 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1340
1341 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1342
1343 /* Re-enable PF target read access */
1344 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1345
1346 /* Poll HW usage counters */
1347 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1348 return -EBUSY;
1349
1350 /* Zero the igu 'trailing edge' and 'leading edge' */
1351
1352 /* Send the FW cleanup command */
1353 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1354 return -EBUSY;
1355
1356 /* ATC cleanup */
1357
1358 /* Verify TX hw is flushed */
1359 bnx2x_tx_hw_flushed(bp, poll_cnt);
1360
1361 /* Wait 100ms (not adjusted according to platform) */
1362 msleep(100);
1363
1364 /* Verify no pending pci transactions */
1365 if (bnx2x_is_pcie_pending(bp->pdev))
1366 BNX2X_ERR("PCIE Transactions still pending\n");
1367
1368 /* Debug */
1369 bnx2x_hw_enable_status(bp);
1370
1371 /*
1372 * Master enable - Due to WB DMAE writes performed before this
1373 * register is re-initialized as part of the regular function init
1374 */
1375 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1376
1377 return 0;
1378}
1379
f2e0899f 1380static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1381{
34f80b04 1382 int port = BP_PORT(bp);
a2fbb9ea
ET		 1383 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1384 u32 val = REG_RD(bp, addr);
1385 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1386 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1387
1388 if (msix) {
8badd27a
EG		 1389 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1390 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1391 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1393 } else if (msi) {
1394 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1395 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1396 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1397 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1398 } else {
1399 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1400 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1401 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1402 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1403
a0fd065c
DK		 1404 if (!CHIP_IS_E1(bp)) {
1405 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1406 val, port, addr);
615f8fd9 1407
a0fd065c 1408 REG_WR(bp, addr, val);
615f8fd9 1409
a0fd065c
DK		 1410 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1411 }
a2fbb9ea
ET		 1412 }
1413
a0fd065c
DK		 1414 if (CHIP_IS_E1(bp))
1415 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1416
8badd27a
EG		 1417 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1418 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1419
1420 REG_WR(bp, addr, val);
37dbbf32
EG		 1421 /*
1422 * Ensure that HC_CONFIG is written before leading/trailing edge config
1423 */
1424 mmiowb();
1425 barrier();
34f80b04 1426
f2e0899f 1427 if (!CHIP_IS_E1(bp)) {
34f80b04 1428 /* init leading/trailing edge */
fb3bff17 1429 if (IS_MF(bp)) {
3395a033 1430 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1431 if (bp->port.pmf)
4acac6a5
EG		 1432 /* enable nig and gpio3 attention */
1433 val |= 0x1100;
34f80b04
EG		 1434 } else
1435 val = 0xffff;
1436
1437 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1438 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1439 }
37dbbf32
EG		 1440
1441 /* Make sure that interrupts are indeed enabled from here on */
1442 mmiowb();
a2fbb9ea
ET		 1443}
1444
f2e0899f
DK		 1445static void bnx2x_igu_int_enable(struct bnx2x *bp)
1446{
1447 u32 val;
1448 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1449 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1450
1451 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1452
1453 if (msix) {
1454 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1455 IGU_PF_CONF_SINGLE_ISR_EN);
1456 val |= (IGU_PF_CONF_FUNC_EN |
1457 IGU_PF_CONF_MSI_MSIX_EN |
1458 IGU_PF_CONF_ATTN_BIT_EN);
1459 } else if (msi) {
1460 val &= ~IGU_PF_CONF_INT_LINE_EN;
1461 val |= (IGU_PF_CONF_FUNC_EN |
1462 IGU_PF_CONF_MSI_MSIX_EN |
1463 IGU_PF_CONF_ATTN_BIT_EN |
1464 IGU_PF_CONF_SINGLE_ISR_EN);
1465 } else {
1466 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1467 val |= (IGU_PF_CONF_FUNC_EN |
1468 IGU_PF_CONF_INT_LINE_EN |
1469 IGU_PF_CONF_ATTN_BIT_EN |
1470 IGU_PF_CONF_SINGLE_ISR_EN);
1471 }
1472
1473 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1474 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1475
1476 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1477
1478 barrier();
1479
1480 /* init leading/trailing edge */
1481 if (IS_MF(bp)) {
3395a033 1482 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1483 if (bp->port.pmf)
1484 /* enable nig and gpio3 attention */
1485 val |= 0x1100;
1486 } else
1487 val = 0xffff;
1488
1489 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1490 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1491
1492 /* Make sure that interrupts are indeed enabled from here on */
1493 mmiowb();
1494}
1495
1496void bnx2x_int_enable(struct bnx2x *bp)
1497{
1498 if (bp->common.int_block == INT_BLOCK_HC)
1499 bnx2x_hc_int_enable(bp);
1500 else
1501 bnx2x_igu_int_enable(bp);
1502}
1503
1504static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1505{
34f80b04 1506 int port = BP_PORT(bp);
a2fbb9ea
ET		 1507 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1508 u32 val = REG_RD(bp, addr);
1509
a0fd065c
DK		 1510 /*
1511 * in E1 we must use only PCI configuration space to disable
1512 * MSI/MSIX capablility
1513 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1514 */
1515 if (CHIP_IS_E1(bp)) {
1516 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1517 * Use mask register to prevent from HC sending interrupts
1518 * after we exit the function
1519 */
1520 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1521
1522 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1523 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1524 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1525 } else
1526 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1527 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1528 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1529 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1530
1531 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1532 val, port, addr);
1533
8badd27a
EG		 1534 /* flush all outstanding writes */
1535 mmiowb();
1536
a2fbb9ea
ET		 1537 REG_WR(bp, addr, val);
1538 if (REG_RD(bp, addr) != val)
1539 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1540}
1541
f2e0899f
DK		 1542static void bnx2x_igu_int_disable(struct bnx2x *bp)
1543{
1544 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1545
1546 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1547 IGU_PF_CONF_INT_LINE_EN |
1548 IGU_PF_CONF_ATTN_BIT_EN);
1549
1550 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1551
1552 /* flush all outstanding writes */
1553 mmiowb();
1554
1555 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1556 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1557 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1558}
1559
6383c0b3 1560void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1561{
1562 if (bp->common.int_block == INT_BLOCK_HC)
1563 bnx2x_hc_int_disable(bp);
1564 else
1565 bnx2x_igu_int_disable(bp);
1566}
1567
9f6c9258 1568void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1569{
a2fbb9ea 1570 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1571 int i, offset;
a2fbb9ea 1572
f8ef6e44
YG		 1573 if (disable_hw)
1574 /* prevent the HW from sending interrupts */
1575 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1576
1577 /* make sure all ISRs are done */
1578 if (msix) {
8badd27a
EG		 1579 synchronize_irq(bp->msix_table[0].vector);
1580 offset = 1;
37b091ba
MC		 1581#ifdef BCM_CNIC
1582 offset++;
1583#endif
ec6ba945 1584 for_each_eth_queue(bp, i)
754a2f52 1585 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1586 } else
1587 synchronize_irq(bp->pdev->irq);
1588
1589 /* make sure sp_task is not running */
1cf167f2 1590 cancel_delayed_work(&bp->sp_task);
3deb8167 1591 cancel_delayed_work(&bp->period_task);
1cf167f2 1592 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1593}
1594
34f80b04 1595/* fast path */
a2fbb9ea
ET		 1596
1597/*
34f80b04 1598 * General service functions
a2fbb9ea
ET		 1599 */
1600
72fd0718
VZ		 1601/* Return true if succeeded to acquire the lock */
1602static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1603{
1604 u32 lock_status;
1605 u32 resource_bit = (1 << resource);
1606 int func = BP_FUNC(bp);
1607 u32 hw_lock_control_reg;
1608
1609 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1610
1611 /* Validating that the resource is within range */
1612 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1613 DP(NETIF_MSG_HW,
1614 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1615 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1616 return false;
72fd0718
VZ		 1617 }
1618
1619 if (func <= 5)
1620 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1621 else
1622 hw_lock_control_reg =
1623 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1624
1625 /* Try to acquire the lock */
1626 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1627 lock_status = REG_RD(bp, hw_lock_control_reg);
1628 if (lock_status & resource_bit)
1629 return true;
1630
1631 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1632 return false;
1633}
1634
c9ee9206
VZ		 1635/**
1636 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1637 *
1638 * @bp: driver handle
1639 *
1640 * Returns the recovery leader resource id according to the engine this function
1641 * belongs to. Currently only only 2 engines is supported.
1642 */
1643static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1644{
1645 if (BP_PATH(bp))
1646 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1647 else
1648 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1649}
1650
1651/**
1652 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1653 *
1654 * @bp: driver handle
1655 *
1656 * Tries to aquire a leader lock for cuurent engine.
1657 */
1658static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1659{
1660 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1661}
1662
993ac7b5 1663#ifdef BCM_CNIC
619c5cb6 1664static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
993ac7b5 1665#endif
3196a88a 1666
619c5cb6 1667void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1668{
1669 struct bnx2x *bp = fp->bp;
1670 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1671 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6
VZ		 1672 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1673 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
a2fbb9ea 1674
34f80b04 1675 DP(BNX2X_MSG_SP,
a2fbb9ea 1676 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1677 fp->index, cid, command, bp->state,
34f80b04 1678 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1679
619c5cb6
VZ		 1680 switch (command) {
1681 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1682 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1683 drv_cmd = BNX2X_Q_CMD_UPDATE;
1684 break;
d6cae238 1685
619c5cb6 1686 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1687 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1688 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1689 break;
1690
6383c0b3
AE		 1691 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1692 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1693 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1694 break;
1695
619c5cb6 1696 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1697 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1698 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1699 break;
1700
619c5cb6 1701 case (RAMROD_CMD_ID_ETH_TERMINATE):
d6cae238 1702 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1703 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1704 break;
1705
619c5cb6 1706 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1707 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1708 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1709 break;
619c5cb6
VZ		 1710
1711 default:
1712 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1713 command, fp->index);
1714 return;
523224a3 1715 }
3196a88a 1716
619c5cb6
VZ		 1717 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1718 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1719 /* q_obj->complete_cmd() failure means that this was
1720 * an unexpected completion.
1721 *
1722 * In this case we don't want to increase the bp->spq_left
1723 * because apparently we haven't sent this command the first
1724 * place.
1725 */
1726#ifdef BNX2X_STOP_ON_ERROR
1727 bnx2x_panic();
1728#else
1729 return;
1730#endif
1731
8fe23fbd 1732 smp_mb__before_atomic_inc();
6e30dd4e 1733 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1734 /* push the change in bp->spq_left and towards the memory */
1735 smp_mb__after_atomic_inc();
49d66772 1736
d6cae238
VZ		 1737 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1738
523224a3 1739 return;
a2fbb9ea
ET		 1740}
1741
619c5cb6
VZ		 1742void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1743 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1744{
1745 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1746
1747 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1748 start);
1749}
1750
9f6c9258 1751irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1752{
555f6c78 1753 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1754 u16 status = bnx2x_ack_int(bp);
34f80b04 1755 u16 mask;
ca00392c 1756 int i;
6383c0b3 1757 u8 cos;
a2fbb9ea 1758
34f80b04 1759 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1760 if (unlikely(status == 0)) {
1761 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1762 return IRQ_NONE;
1763 }
f5372251 1764 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1765
3196a88a
EG		 1766#ifdef BNX2X_STOP_ON_ERROR
1767 if (unlikely(bp->panic))
1768 return IRQ_HANDLED;
1769#endif
1770
ec6ba945 1771 for_each_eth_queue(bp, i) {
ca00392c 1772 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1773
6383c0b3 1774 mask = 0x2 << (fp->index + CNIC_PRESENT);
ca00392c 1775 if (status & mask) {
619c5cb6 1776 /* Handle Rx or Tx according to SB id */
54b9ddaa 1777 prefetch(fp->rx_cons_sb);
6383c0b3
AE		 1778 for_each_cos_in_tx_queue(fp, cos)
1779 prefetch(fp->txdata[cos].tx_cons_sb);
523224a3 1780 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1781 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1782 status &= ~mask;
1783 }
a2fbb9ea
ET		 1784 }
1785
993ac7b5 1786#ifdef BCM_CNIC
523224a3 1787 mask = 0x2;
993ac7b5
MC		 1788 if (status & (mask | 0x1)) {
1789 struct cnic_ops *c_ops = NULL;
1790
619c5cb6
VZ		 1791 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1792 rcu_read_lock();
1793 c_ops = rcu_dereference(bp->cnic_ops);
1794 if (c_ops)
1795 c_ops->cnic_handler(bp->cnic_data, NULL);
1796 rcu_read_unlock();
1797 }
993ac7b5
MC		 1798
1799 status &= ~mask;
1800 }
1801#endif
a2fbb9ea 1802
34f80b04 1803 if (unlikely(status & 0x1)) {
1cf167f2 1804 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1805
1806 status &= ~0x1;
1807 if (!status)
1808 return IRQ_HANDLED;
1809 }
1810
cdaa7cb8
VZ		 1811 if (unlikely(status))
1812 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1813 status);
a2fbb9ea 1814
c18487ee 1815 return IRQ_HANDLED;
a2fbb9ea
ET		 1816}
1817
c18487ee
YR		 1818/* Link */
1819
1820/*
1821 * General service functions
1822 */
a2fbb9ea 1823
9f6c9258 1824int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1825{
1826 u32 lock_status;
1827 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1828 int func = BP_FUNC(bp);
1829 u32 hw_lock_control_reg;
c18487ee 1830 int cnt;
a2fbb9ea 1831
c18487ee
YR		 1832 /* Validating that the resource is within range */
1833 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1834 DP(NETIF_MSG_HW,
1835 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1836 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1837 return -EINVAL;
1838 }
a2fbb9ea 1839
4a37fb66
YG		 1840 if (func <= 5) {
1841 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1842 } else {
1843 hw_lock_control_reg =
1844 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1845 }
1846
c18487ee 1847 /* Validating that the resource is not already taken */
4a37fb66 1848 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1849 if (lock_status & resource_bit) {
1850 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1851 lock_status, resource_bit);
1852 return -EEXIST;
1853 }
a2fbb9ea 1854
46230476
EG		 1855 /* Try for 5 second every 5ms */
1856 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1857 /* Try to acquire the lock */
4a37fb66
YG		 1858 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1859 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1860 if (lock_status & resource_bit)
1861 return 0;
a2fbb9ea 1862
c18487ee 1863 msleep(5);
a2fbb9ea 1864 }
c18487ee
YR		 1865 DP(NETIF_MSG_HW, "Timeout\n");
1866 return -EAGAIN;
1867}
a2fbb9ea 1868
c9ee9206
VZ		 1869int bnx2x_release_leader_lock(struct bnx2x *bp)
1870{
1871 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1872}
1873
9f6c9258 1874int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1875{
1876 u32 lock_status;
1877 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1878 int func = BP_FUNC(bp);
1879 u32 hw_lock_control_reg;
a2fbb9ea 1880
72fd0718
VZ		 1881 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1882
c18487ee
YR		 1883 /* Validating that the resource is within range */
1884 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1885 DP(NETIF_MSG_HW,
1886 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1887 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1888 return -EINVAL;
1889 }
1890
4a37fb66
YG		 1891 if (func <= 5) {
1892 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1893 } else {
1894 hw_lock_control_reg =
1895 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1896 }
1897
c18487ee 1898 /* Validating that the resource is currently taken */
4a37fb66 1899 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1900 if (!(lock_status & resource_bit)) {
1901 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1902 lock_status, resource_bit);
1903 return -EFAULT;
a2fbb9ea
ET		 1904 }
1905
9f6c9258
DK		 1906 REG_WR(bp, hw_lock_control_reg, resource_bit);
1907 return 0;
c18487ee 1908}
a2fbb9ea 1909
9f6c9258 1910
4acac6a5
EG		 1911int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1912{
1913 /* The GPIO should be swapped if swap register is set and active */
1914 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1915 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1916 int gpio_shift = gpio_num +
1917 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1918 u32 gpio_mask = (1 << gpio_shift);
1919 u32 gpio_reg;
1920 int value;
1921
1922 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1923 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1924 return -EINVAL;
1925 }
1926
1927 /* read GPIO value */
1928 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1929
1930 /* get the requested pin value */
1931 if ((gpio_reg & gpio_mask) == gpio_mask)
1932 value = 1;
1933 else
1934 value = 0;
1935
1936 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1937
1938 return value;
1939}
1940
17de50b7 1941int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1942{
1943 /* The GPIO should be swapped if swap register is set and active */
1944 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1945 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1946 int gpio_shift = gpio_num +
1947 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1948 u32 gpio_mask = (1 << gpio_shift);
1949 u32 gpio_reg;
a2fbb9ea 1950
c18487ee
YR		 1951 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1952 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1953 return -EINVAL;
1954 }
a2fbb9ea 1955
4a37fb66 1956 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1957 /* read GPIO and mask except the float bits */
1958 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1959
c18487ee
YR		 1960 switch (mode) {
1961 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1962 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1963 gpio_num, gpio_shift);
1964 /* clear FLOAT and set CLR */
1965 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1966 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1967 break;
a2fbb9ea 1968
c18487ee
YR		 1969 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1970 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1971 gpio_num, gpio_shift);
1972 /* clear FLOAT and set SET */
1973 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1974 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1975 break;
a2fbb9ea 1976
17de50b7 1977 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1978 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1979 gpio_num, gpio_shift);
1980 /* set FLOAT */
1981 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1982 break;
a2fbb9ea 1983
c18487ee
YR		 1984 default:
1985 break;
a2fbb9ea
ET		 1986 }
1987
c18487ee 1988 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1989 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1990
c18487ee 1991 return 0;
a2fbb9ea
ET		 1992}
1993
0d40f0d4
YR		 1994int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1995{
1996 u32 gpio_reg = 0;
1997 int rc = 0;
1998
1999 /* Any port swapping should be handled by caller. */
2000
2001 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2002 /* read GPIO and mask except the float bits */
2003 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2004 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2005 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2006 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2007
2008 switch (mode) {
2009 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2010 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2011 /* set CLR */
2012 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2013 break;
2014
2015 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2016 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2017 /* set SET */
2018 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2019 break;
2020
2021 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2022 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2023 /* set FLOAT */
2024 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2025 break;
2026
2027 default:
2028 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2029 rc = -EINVAL;
2030 break;
2031 }
2032
2033 if (rc == 0)
2034 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2035
2036 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2037
2038 return rc;
2039}
2040
4acac6a5
EG		 2041int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2042{
2043 /* The GPIO should be swapped if swap register is set and active */
2044 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2045 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2046 int gpio_shift = gpio_num +
2047 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2048 u32 gpio_mask = (1 << gpio_shift);
2049 u32 gpio_reg;
2050
2051 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2052 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2053 return -EINVAL;
2054 }
2055
2056 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2057 /* read GPIO int */
2058 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2059
2060 switch (mode) {
2061 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2062 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2063 "output low\n", gpio_num, gpio_shift);
2064 /* clear SET and set CLR */
2065 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2066 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2067 break;
2068
2069 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2070 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2071 "output high\n", gpio_num, gpio_shift);
2072 /* clear CLR and set SET */
2073 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2074 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2075 break;
2076
2077 default:
2078 break;
2079 }
2080
2081 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2082 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2083
2084 return 0;
2085}
2086
c18487ee 2087static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 2088{
c18487ee
YR		 2089 u32 spio_mask = (1 << spio_num);
2090 u32 spio_reg;
a2fbb9ea 2091
c18487ee
YR		 2092 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2093 (spio_num > MISC_REGISTERS_SPIO_7)) {
2094 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2095 return -EINVAL;
a2fbb9ea
ET		 2096 }
2097
4a37fb66 2098 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 2099 /* read SPIO and mask except the float bits */
2100 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 2101
c18487ee 2102 switch (mode) {
6378c025 2103 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 2104 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2105 /* clear FLOAT and set CLR */
2106 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2107 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2108 break;
a2fbb9ea 2109
6378c025 2110 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 2111 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2112 /* clear FLOAT and set SET */
2113 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2114 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2115 break;
a2fbb9ea 2116
c18487ee
YR		 2117 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2118 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2119 /* set FLOAT */
2120 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2121 break;
a2fbb9ea 2122
c18487ee
YR		 2123 default:
2124 break;
a2fbb9ea
ET		 2125 }
2126
c18487ee 2127 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2128 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2129
a2fbb9ea
ET		 2130 return 0;
2131}
2132
9f6c9258 2133void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2134{
a22f0788 2135 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2136 switch (bp->link_vars.ieee_fc &
2137 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2139 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2140 ADVERTISED_Pause);
c18487ee 2141 break;
356e2385 2142
c18487ee 2143 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2144 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2145 ADVERTISED_Pause);
c18487ee 2146 break;
356e2385 2147
c18487ee 2148 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2149 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2150 break;
356e2385 2151
c18487ee 2152 default:
a22f0788 2153 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2154 ADVERTISED_Pause);
c18487ee
YR		 2155 break;
2156 }
2157}
f1410647 2158
9f6c9258 2159u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 2160{
19680c48
EG		 2161 if (!BP_NOMCP(bp)) {
2162 u8 rc;
a22f0788
YR		 2163 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2164 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1cb0c788
YR		 2165 /*
2166 * Initialize link parameters structure variables
2167 * It is recommended to turn off RX FC for jumbo frames
2168 * for better performance
2169 */
2170 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
c0700f90 2171 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 2172 else
c0700f90 2173 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 2174
4a37fb66 2175 bnx2x_acquire_phy_lock(bp);
b5bf9068 2176
a22f0788 2177 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2178 struct link_params *lp = &bp->link_params;
2179 lp->loopback_mode = LOOPBACK_XGXS;
2180 /* do PHY loopback at 10G speed, if possible */
2181 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2182 if (lp->speed_cap_mask[cfx_idx] &
2183 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2184 lp->req_line_speed[cfx_idx] =
2185 SPEED_10000;
2186 else
2187 lp->req_line_speed[cfx_idx] =
2188 SPEED_1000;
2189 }
a22f0788 2190 }
b5bf9068 2191
19680c48 2192 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2193
4a37fb66 2194 bnx2x_release_phy_lock(bp);
a2fbb9ea 2195
3c96c68b
EG		 2196 bnx2x_calc_fc_adv(bp);
2197
b5bf9068
EG		 2198 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2199 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2200 bnx2x_link_report(bp);
3deb8167
YR		 2201 } else
2202 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2203 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2204 return rc;
2205 }
f5372251 2206 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2207 return -EINVAL;
a2fbb9ea
ET		 2208}
2209
9f6c9258 2210void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2211{
19680c48 2212 if (!BP_NOMCP(bp)) {
4a37fb66 2213 bnx2x_acquire_phy_lock(bp);
54c2fb78 2214 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 2215 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2216 bnx2x_release_phy_lock(bp);
a2fbb9ea 2217
19680c48
EG		 2218 bnx2x_calc_fc_adv(bp);
2219 } else
f5372251 2220 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2221}
a2fbb9ea 2222
c18487ee
YR		 2223static void bnx2x__link_reset(struct bnx2x *bp)
2224{
19680c48 2225 if (!BP_NOMCP(bp)) {
4a37fb66 2226 bnx2x_acquire_phy_lock(bp);
589abe3a 2227 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 2228 bnx2x_release_phy_lock(bp);
19680c48 2229 } else
f5372251 2230 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2231}
a2fbb9ea 2232
a22f0788 2233u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2234{
2145a920 2235 u8 rc = 0;
a2fbb9ea 2236
2145a920
VZ		 2237 if (!BP_NOMCP(bp)) {
2238 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2239 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2240 is_serdes);
2145a920
VZ		 2241 bnx2x_release_phy_lock(bp);
2242 } else
2243 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2244
c18487ee
YR		 2245 return rc;
2246}
a2fbb9ea 2247
8a1c38d1 2248static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 2249{
8a1c38d1
EG		 2250 u32 r_param = bp->link_vars.line_speed / 8;
2251 u32 fair_periodic_timeout_usec;
2252 u32 t_fair;
34f80b04 2253
8a1c38d1
EG		 2254 memset(&(bp->cmng.rs_vars), 0,
2255 sizeof(struct rate_shaping_vars_per_port));
2256 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 2257
8a1c38d1
EG		 2258 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2259 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 2260
8a1c38d1
EG		 2261 /* this is the threshold below which no timer arming will occur
2262 1.25 coefficient is for the threshold to be a little bigger
2263 than the real time, to compensate for timer in-accuracy */
2264 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 2265 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2266
8a1c38d1
EG		 2267 /* resolution of fairness timer */
2268 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2269 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2270 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 2271
8a1c38d1
EG		 2272 /* this is the threshold below which we won't arm the timer anymore */
2273 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 2274
8a1c38d1
EG		 2275 /* we multiply by 1e3/8 to get bytes/msec.
2276 We don't want the credits to pass a credit
2277 of the t_fair*FAIR_MEM (algorithm resolution) */
2278 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2279 /* since each tick is 4 usec */
2280 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 2281}
2282
2691d51d
EG		 2283/* Calculates the sum of vn_min_rates.
2284 It's needed for further normalizing of the min_rates.
2285 Returns:
2286 sum of vn_min_rates.
2287 or
2288 0 - if all the min_rates are 0.
2289 In the later case fainess algorithm should be deactivated.
2290 If not all min_rates are zero then those that are zeroes will be set to 1.
2291 */
2292static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2293{
2294 int all_zero = 1;
2691d51d
EG		 2295 int vn;
2296
2297 bp->vn_weight_sum = 0;
3395a033 2298 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2299 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2300 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2301 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2302
2303 /* Skip hidden vns */
2304 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2305 continue;
2306
2307 /* If min rate is zero - set it to 1 */
2308 if (!vn_min_rate)
2309 vn_min_rate = DEF_MIN_RATE;
2310 else
2311 all_zero = 0;
2312
2313 bp->vn_weight_sum += vn_min_rate;
2314 }
2315
30ae438b
DK		 2316 /* if ETS or all min rates are zeros - disable fairness */
2317 if (BNX2X_IS_ETS_ENABLED(bp)) {
2318 bp->cmng.flags.cmng_enables &=
2319 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2320 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2321 } else if (all_zero) {
b015e3d1
EG		 2322 bp->cmng.flags.cmng_enables &=
2323 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2324 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2325 " fairness will be disabled\n");
2326 } else
2327 bp->cmng.flags.cmng_enables |=
2328 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2329}
2330
f2e0899f 2331static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 2332{
2333 struct rate_shaping_vars_per_vn m_rs_vn;
2334 struct fairness_vars_per_vn m_fair_vn;
f2e0899f 2335 u32 vn_cfg = bp->mf_config[vn];
3395a033 2336 int func = func_by_vn(bp, vn);
34f80b04
EG		 2337 u16 vn_min_rate, vn_max_rate;
2338 int i;
2339
2340 /* If function is hidden - set min and max to zeroes */
2341 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2342 vn_min_rate = 0;
2343 vn_max_rate = 0;
2344
2345 } else {
faa6fcbb
DK		 2346 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2347
34f80b04
EG		 2348 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2349 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 2350 /* If fairness is enabled (not all min rates are zeroes) and
2351 if current min rate is zero - set it to 1.
2352 This is a requirement of the algorithm. */
f2e0899f 2353 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 2354 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 2355
2356 if (IS_MF_SI(bp))
2357 /* maxCfg in percents of linkspeed */
2358 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2359 else
2360 /* maxCfg is absolute in 100Mb units */
2361 vn_max_rate = maxCfg * 100;
34f80b04 2362 }
f85582f8 2363
8a1c38d1 2364 DP(NETIF_MSG_IFUP,
b015e3d1 2365 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 2366 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 2367
2368 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2369 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2370
2371 /* global vn counter - maximal Mbps for this vn */
2372 m_rs_vn.vn_counter.rate = vn_max_rate;
2373
2374 /* quota - number of bytes transmitted in this period */
2375 m_rs_vn.vn_counter.quota =
2376 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2377
8a1c38d1 2378 if (bp->vn_weight_sum) {
34f80b04
EG		 2379 /* credit for each period of the fairness algorithm:
2380 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2381 vn_weight_sum should not be larger than 10000, thus
2382 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2383 than zero */
34f80b04 2384 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2385 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2386 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 2387 (bp->cmng.fair_vars.fair_threshold +
2388 MIN_ABOVE_THRESH));
cdaa7cb8 2389 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2390 m_fair_vn.vn_credit_delta);
2391 }
2392
34f80b04
EG		 2393 /* Store it to internal memory */
2394 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2395 REG_WR(bp, BAR_XSTRORM_INTMEM +
2396 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2397 ((u32 *)(&m_rs_vn))[i]);
2398
2399 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2400 REG_WR(bp, BAR_XSTRORM_INTMEM +
2401 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2402 ((u32 *)(&m_fair_vn))[i]);
2403}
f85582f8 2404
523224a3
DK		 2405static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2406{
2407 if (CHIP_REV_IS_SLOW(bp))
2408 return CMNG_FNS_NONE;
fb3bff17 2409 if (IS_MF(bp))
523224a3
DK		 2410 return CMNG_FNS_MINMAX;
2411
2412 return CMNG_FNS_NONE;
2413}
2414
2ae17f66 2415void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2416{
0793f83f 2417 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2418
2419 if (BP_NOMCP(bp))
2420 return; /* what should be the default bvalue in this case */
2421
0793f83f
DK		 2422 /* For 2 port configuration the absolute function number formula
2423 * is:
2424 * abs_func = 2 * vn + BP_PORT + BP_PATH
2425 *
2426 * and there are 4 functions per port
2427 *
2428 * For 4 port configuration it is
2429 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2430 *
2431 * and there are 2 functions per port
2432 */
3395a033 2433 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2434 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2435
2436 if (func >= E1H_FUNC_MAX)
2437 break;
2438
f2e0899f 2439 bp->mf_config[vn] =
523224a3
DK		 2440 MF_CFG_RD(bp, func_mf_config[func].config);
2441 }
2442}
2443
2444static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2445{
2446
2447 if (cmng_type == CMNG_FNS_MINMAX) {
2448 int vn;
2449
2450 /* clear cmng_enables */
2451 bp->cmng.flags.cmng_enables = 0;
2452
2453 /* read mf conf from shmem */
2454 if (read_cfg)
2455 bnx2x_read_mf_cfg(bp);
2456
2457 /* Init rate shaping and fairness contexts */
2458 bnx2x_init_port_minmax(bp);
2459
2460 /* vn_weight_sum and enable fairness if not 0 */
2461 bnx2x_calc_vn_weight_sum(bp);
2462
2463 /* calculate and set min-max rate for each vn */
c4154f25 2464 if (bp->port.pmf)
3395a033 2465 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
c4154f25 2466 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2467
2468 /* always enable rate shaping and fairness */
2469 bp->cmng.flags.cmng_enables |=
2470 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2471 if (!bp->vn_weight_sum)
2472 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2473 " fairness will be disabled\n");
2474 return;
2475 }
2476
2477 /* rate shaping and fairness are disabled */
2478 DP(NETIF_MSG_IFUP,
2479 "rate shaping and fairness are disabled\n");
2480}
34f80b04 2481
c18487ee
YR		 2482/* This function is called upon link interrupt */
2483static void bnx2x_link_attn(struct bnx2x *bp)
2484{
bb2a0f7a
YG		 2485 /* Make sure that we are synced with the current statistics */
2486 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2487
c18487ee 2488 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2489
bb2a0f7a
YG		 2490 if (bp->link_vars.link_up) {
2491
1c06328c 2492 /* dropless flow control */
f2e0899f 2493 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2494 int port = BP_PORT(bp);
2495 u32 pause_enabled = 0;
2496
2497 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2498 pause_enabled = 1;
2499
2500 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2501 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2502 pause_enabled);
2503 }
2504
619c5cb6 2505 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2506 struct host_port_stats *pstats;
2507
2508 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2509 /* reset old mac stats */
bb2a0f7a
YG		 2510 memset(&(pstats->mac_stx[0]), 0,
2511 sizeof(struct mac_stx));
2512 }
f34d28ea 2513 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2514 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2515 }
2516
f2e0899f
DK		 2517 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2518 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2519
f2e0899f
DK		 2520 if (cmng_fns != CMNG_FNS_NONE) {
2521 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2522 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2523 } else
2524 /* rate shaping and fairness are disabled */
2525 DP(NETIF_MSG_IFUP,
2526 "single function mode without fairness\n");
34f80b04 2527 }
9fdc3e95 2528
2ae17f66
VZ		 2529 __bnx2x_link_report(bp);
2530
9fdc3e95
DK		 2531 if (IS_MF(bp))
2532 bnx2x_link_sync_notify(bp);
c18487ee 2533}
a2fbb9ea 2534
9f6c9258 2535void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2536{
2ae17f66 2537 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2538 return;
a2fbb9ea 2539
00253a8c
DK		 2540 /* read updated dcb configuration */
2541 bnx2x_dcbx_pmf_update(bp);
2542
c18487ee 2543 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2544
bb2a0f7a
YG		 2545 if (bp->link_vars.link_up)
2546 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2547 else
2548 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2549
c18487ee
YR		 2550 /* indicate link status */
2551 bnx2x_link_report(bp);
a2fbb9ea 2552}
a2fbb9ea 2553
34f80b04
EG		 2554static void bnx2x_pmf_update(struct bnx2x *bp)
2555{
2556 int port = BP_PORT(bp);
2557 u32 val;
2558
2559 bp->port.pmf = 1;
2560 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2561
3deb8167
YR		 2562 /*
2563 * We need the mb() to ensure the ordering between the writing to
2564 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2565 */
2566 smp_mb();
2567
2568 /* queue a periodic task */
2569 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2570
ef01854e
DK		 2571 bnx2x_dcbx_pmf_update(bp);
2572
34f80b04 2573 /* enable nig attention */
3395a033 2574 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2575 if (bp->common.int_block == INT_BLOCK_HC) {
2576 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2577 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2578 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2579 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2580 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2581 }
bb2a0f7a
YG		 2582
2583 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2584}
2585
c18487ee 2586/* end of Link */
a2fbb9ea
ET		 2587
2588/* slow path */
2589
2590/*
2591 * General service functions
2592 */
2593
2691d51d 2594/* send the MCP a request, block until there is a reply */
a22f0788 2595u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2596{
f2e0899f 2597 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2598 u32 seq;
2691d51d
EG		 2599 u32 rc = 0;
2600 u32 cnt = 1;
2601 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2602
c4ff7cbf 2603 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2604 seq = ++bp->fw_seq;
f2e0899f
DK		 2605 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2606 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2607
754a2f52
DK		 2608 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2609 (command | seq), param);
2691d51d
EG		 2610
2611 do {
2612 /* let the FW do it's magic ... */
2613 msleep(delay);
2614
f2e0899f 2615 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2616
c4ff7cbf
EG		 2617 /* Give the FW up to 5 second (500*10ms) */
2618 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2619
2620 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2621 cnt*delay, rc, seq);
2622
2623 /* is this a reply to our command? */
2624 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2625 rc &= FW_MSG_CODE_MASK;
2626 else {
2627 /* FW BUG! */
2628 BNX2X_ERR("FW failed to respond!\n");
2629 bnx2x_fw_dump(bp);
2630 rc = 0;
2631 }
c4ff7cbf 2632 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2633
2634 return rc;
2635}
2636
ec6ba945 2637
619c5cb6
VZ		 2638void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2639{
2640 if (CHIP_IS_E1x(bp)) {
2641 struct tstorm_eth_function_common_config tcfg = {0};
2642
2643 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2644 }
2645
2646 /* Enable the function in the FW */
2647 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2648 storm_memset_func_en(bp, p->func_id, 1);
2649
2650 /* spq */
2651 if (p->func_flgs & FUNC_FLG_SPQ) {
2652 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2653 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2654 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2655 }
2656}
2657
6383c0b3
AE		 2658/**
2659 * bnx2x_get_tx_only_flags - Return common flags
2660 *
2661 * @bp device handle
2662 * @fp queue handle
2663 * @zero_stats TRUE if statistics zeroing is needed
2664 *
2665 * Return the flags that are common for the Tx-only and not normal connections.
2666 */
2667static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2668 struct bnx2x_fastpath *fp,
2669 bool zero_stats)
28912902 2670{
619c5cb6
VZ		 2671 unsigned long flags = 0;
2672
2673 /* PF driver will always initialize the Queue to an ACTIVE state */
2674 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2675
6383c0b3
AE		 2676 /* tx only connections collect statistics (on the same index as the
2677 * parent connection). The statistics are zeroed when the parent
2678 * connection is initialized.
2679 */
50f0a562
BW		 2680
2681 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2682 if (zero_stats)
2683 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2684
6383c0b3
AE		 2685
2686 return flags;
2687}
2688
2689static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2690 struct bnx2x_fastpath *fp,
2691 bool leading)
2692{
2693 unsigned long flags = 0;
2694
619c5cb6
VZ		 2695 /* calculate other queue flags */
2696 if (IS_MF_SD(bp))
2697 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2698
619c5cb6
VZ		 2699 if (IS_FCOE_FP(fp))
2700 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
523224a3 2701
f5219d8e 2702 if (!fp->disable_tpa) {
619c5cb6 2703 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e
VZ		 2704 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2705 }
619c5cb6 2706
619c5cb6
VZ		 2707 if (leading) {
2708 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2709 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2710 }
523224a3 2711
619c5cb6
VZ		 2712 /* Always set HW VLAN stripping */
2713 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 2714
6383c0b3
AE		 2715
2716 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 2717}
2718
619c5cb6 2719static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 2720 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2721 u8 cos)
619c5cb6
VZ		 2722{
2723 gen_init->stat_id = bnx2x_stats_id(fp);
2724 gen_init->spcl_id = fp->cl_id;
2725
2726 /* Always use mini-jumbo MTU for FCoE L2 ring */
2727 if (IS_FCOE_FP(fp))
2728 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2729 else
2730 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 2731
2732 gen_init->cos = cos;
619c5cb6
VZ		 2733}
2734
2735static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2736 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2737 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2738{
619c5cb6 2739 u8 max_sge = 0;
523224a3
DK		 2740 u16 sge_sz = 0;
2741 u16 tpa_agg_size = 0;
2742
523224a3 2743 if (!fp->disable_tpa) {
dfacf138
DK		 2744 pause->sge_th_lo = SGE_TH_LO(bp);
2745 pause->sge_th_hi = SGE_TH_HI(bp);
2746
2747 /* validate SGE ring has enough to cross high threshold */
2748 WARN_ON(bp->dropless_fc &&
2749 pause->sge_th_hi + FW_PREFETCH_CNT >
2750 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2751
523224a3
DK		 2752 tpa_agg_size = min_t(u32,
2753 (min_t(u32, 8, MAX_SKB_FRAGS) *
2754 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2755 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2756 SGE_PAGE_SHIFT;
2757 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2758 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2759 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2760 0xffff);
2761 }
2762
2763 /* pause - not for e1 */
2764 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 2765 pause->bd_th_lo = BD_TH_LO(bp);
2766 pause->bd_th_hi = BD_TH_HI(bp);
2767
2768 pause->rcq_th_lo = RCQ_TH_LO(bp);
2769 pause->rcq_th_hi = RCQ_TH_HI(bp);
2770 /*
2771 * validate that rings have enough entries to cross
2772 * high thresholds
2773 */
2774 WARN_ON(bp->dropless_fc &&
2775 pause->bd_th_hi + FW_PREFETCH_CNT >
2776 bp->rx_ring_size);
2777 WARN_ON(bp->dropless_fc &&
2778 pause->rcq_th_hi + FW_PREFETCH_CNT >
2779 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 2780
523224a3
DK		 2781 pause->pri_map = 1;
2782 }
2783
2784 /* rxq setup */
523224a3
DK		 2785 rxq_init->dscr_map = fp->rx_desc_mapping;
2786 rxq_init->sge_map = fp->rx_sge_mapping;
2787 rxq_init->rcq_map = fp->rx_comp_mapping;
2788 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 2789
619c5cb6
VZ		 2790 /* This should be a maximum number of data bytes that may be
2791 * placed on the BD (not including paddings).
2792 */
e52fcb24
ED		 2793 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2794 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 2795
523224a3 2796 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 2797 rxq_init->tpa_agg_sz = tpa_agg_size;
2798 rxq_init->sge_buf_sz = sge_sz;
2799 rxq_init->max_sges_pkt = max_sge;
619c5cb6
VZ		 2800 rxq_init->rss_engine_id = BP_FUNC(bp);
2801
2802 /* Maximum number or simultaneous TPA aggregation for this Queue.
2803 *
2804 * For PF Clients it should be the maximum avaliable number.
2805 * VF driver(s) may want to define it to a smaller value.
2806 */
dfacf138 2807 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 2808
523224a3
DK		 2809 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2810 rxq_init->fw_sb_id = fp->fw_sb_id;
2811
ec6ba945
VZ		 2812 if (IS_FCOE_FP(fp))
2813 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2814 else
6383c0b3 2815 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
523224a3
DK		 2816}
2817
619c5cb6 2818static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 2819 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2820 u8 cos)
523224a3 2821{
6383c0b3
AE		 2822 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2823 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 2824 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2825 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 2826
619c5cb6
VZ		 2827 /*
2828 * set the tss leading client id for TX classfication ==
2829 * leading RSS client id
2830 */
2831 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2832
ec6ba945
VZ		 2833 if (IS_FCOE_FP(fp)) {
2834 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2835 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2836 }
523224a3
DK		 2837}
2838
8d96286a 2839static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2840{
2841 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 2842 struct event_ring_data eq_data = { {0} };
2843 u16 flags;
2844
619c5cb6 2845 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2846 /* reset IGU PF statistics: MSIX + ATTN */
2847 /* PF */
2848 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2849 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2850 (CHIP_MODE_IS_4_PORT(bp) ?
2851 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2852 /* ATTN */
2853 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2854 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2855 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2856 (CHIP_MODE_IS_4_PORT(bp) ?
2857 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2858 }
2859
523224a3
DK		 2860 /* function setup flags */
2861 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2862
619c5cb6
VZ		 2863 /* This flag is relevant for E1x only.
2864 * E2 doesn't have a TPA configuration in a function level.
523224a3 2865 */
619c5cb6 2866 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 2867
2868 func_init.func_flgs = flags;
2869 func_init.pf_id = BP_FUNC(bp);
2870 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 2871 func_init.spq_map = bp->spq_mapping;
2872 func_init.spq_prod = bp->spq_prod_idx;
2873
2874 bnx2x_func_init(bp, &func_init);
2875
2876 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2877
2878 /*
619c5cb6
VZ		 2879 * Congestion management values depend on the link rate
2880 * There is no active link so initial link rate is set to 10 Gbps.
2881 * When the link comes up The congestion management values are
2882 * re-calculated according to the actual link rate.
2883 */
523224a3
DK		 2884 bp->link_vars.line_speed = SPEED_10000;
2885 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2886
2887 /* Only the PMF sets the HW */
2888 if (bp->port.pmf)
2889 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2890
523224a3
DK		 2891 /* init Event Queue */
2892 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2893 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2894 eq_data.producer = bp->eq_prod;
2895 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2896 eq_data.sb_id = DEF_SB_ID;
2897 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2898}
2899
2900
2901static void bnx2x_e1h_disable(struct bnx2x *bp)
2902{
2903 int port = BP_PORT(bp);
2904
619c5cb6 2905 bnx2x_tx_disable(bp);
523224a3
DK		 2906
2907 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 2908}
2909
2910static void bnx2x_e1h_enable(struct bnx2x *bp)
2911{
2912 int port = BP_PORT(bp);
2913
2914 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2915
2916 /* Tx queue should be only reenabled */
2917 netif_tx_wake_all_queues(bp->dev);
2918
2919 /*
2920 * Should not call netif_carrier_on since it will be called if the link
2921 * is up when checking for link state
2922 */
2923}
2924
1d187b34
BW		 2925#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
2926
2927static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
2928{
2929 struct eth_stats_info *ether_stat =
2930 &bp->slowpath->drv_info_to_mcp.ether_stat;
2931
2932 /* leave last char as NULL */
2933 memcpy(ether_stat->version, DRV_MODULE_VERSION,
2934 ETH_STAT_INFO_VERSION_LEN - 1);
2935
2936 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj,
2937 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
2938 ether_stat->mac_local);
2939
2940 ether_stat->mtu_size = bp->dev->mtu;
2941
2942 if (bp->dev->features & NETIF_F_RXCSUM)
2943 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
2944 if (bp->dev->features & NETIF_F_TSO)
2945 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
2946 ether_stat->feature_flags |= bp->common.boot_mode;
2947
2948 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
2949
2950 ether_stat->txq_size = bp->tx_ring_size;
2951 ether_stat->rxq_size = bp->rx_ring_size;
2952}
2953
2954static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
2955{
f2fd5c34 2956#ifdef BCM_CNIC
1d187b34
BW		 2957 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
2958 struct fcoe_stats_info *fcoe_stat =
2959 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
2960
2961 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN);
2962
2963 fcoe_stat->qos_priority =
2964 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
2965
2966 /* insert FCoE stats from ramrod response */
2967 if (!NO_FCOE(bp)) {
2968 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
2969 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2970 tstorm_queue_statistics;
2971
2972 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
2973 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2974 xstorm_queue_statistics;
2975
2976 struct fcoe_statistics_params *fw_fcoe_stat =
2977 &bp->fw_stats_data->fcoe;
2978
2979 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
2980 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
2981
2982 ADD_64(fcoe_stat->rx_bytes_hi,
2983 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
2984 fcoe_stat->rx_bytes_lo,
2985 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
2986
2987 ADD_64(fcoe_stat->rx_bytes_hi,
2988 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
2989 fcoe_stat->rx_bytes_lo,
2990 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
2991
2992 ADD_64(fcoe_stat->rx_bytes_hi,
2993 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
2994 fcoe_stat->rx_bytes_lo,
2995 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
2996
2997 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
2998 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
2999
3000 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3001 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3002
3003 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3004 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3005
3006 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
f33f1fcc 3007 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34
BW		 3008
3009 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3010 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3011
3012 ADD_64(fcoe_stat->tx_bytes_hi,
3013 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3014 fcoe_stat->tx_bytes_lo,
3015 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3016
3017 ADD_64(fcoe_stat->tx_bytes_hi,
3018 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3019 fcoe_stat->tx_bytes_lo,
3020 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3021
3022 ADD_64(fcoe_stat->tx_bytes_hi,
3023 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3024 fcoe_stat->tx_bytes_lo,
3025 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3026
3027 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3028 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3029
3030 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3031 fcoe_q_xstorm_stats->ucast_pkts_sent);
3032
3033 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3034 fcoe_q_xstorm_stats->bcast_pkts_sent);
3035
3036 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3037 fcoe_q_xstorm_stats->mcast_pkts_sent);
3038 }
3039
1d187b34
BW		 3040 /* ask L5 driver to add data to the struct */
3041 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3042#endif
3043}
3044
3045static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3046{
f2fd5c34 3047#ifdef BCM_CNIC
1d187b34
BW		 3048 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3049 struct iscsi_stats_info *iscsi_stat =
3050 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3051
3052 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3053
3054 iscsi_stat->qos_priority =
3055 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3056
1d187b34
BW		 3057 /* ask L5 driver to add data to the struct */
3058 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3059#endif
3060}
3061
0793f83f
DK		 3062/* called due to MCP event (on pmf):
3063 * reread new bandwidth configuration
3064 * configure FW
3065 * notify others function about the change
3066 */
3067static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
3068{
3069 if (bp->link_vars.link_up) {
3070 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3071 bnx2x_link_sync_notify(bp);
3072 }
3073 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3074}
3075
3076static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
3077{
3078 bnx2x_config_mf_bw(bp);
3079 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3080}
3081
1d187b34
BW		 3082static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3083{
3084 enum drv_info_opcode op_code;
3085 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3086
3087 /* if drv_info version supported by MFW doesn't match - send NACK */
3088 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3089 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3090 return;
3091 }
3092
3093 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3094 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3095
3096 memset(&bp->slowpath->drv_info_to_mcp, 0,
3097 sizeof(union drv_info_to_mcp));
3098
3099 switch (op_code) {
3100 case ETH_STATS_OPCODE:
3101 bnx2x_drv_info_ether_stat(bp);
3102 break;
3103 case FCOE_STATS_OPCODE:
3104 bnx2x_drv_info_fcoe_stat(bp);
3105 break;
3106 case ISCSI_STATS_OPCODE:
3107 bnx2x_drv_info_iscsi_stat(bp);
3108 break;
3109 default:
3110 /* if op code isn't supported - send NACK */
3111 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3112 return;
3113 }
3114
3115 /* if we got drv_info attn from MFW then these fields are defined in
3116 * shmem2 for sure
3117 */
3118 SHMEM2_WR(bp, drv_info_host_addr_lo,
3119 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3120 SHMEM2_WR(bp, drv_info_host_addr_hi,
3121 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3122
3123 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3124}
3125
523224a3
DK		 3126static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3127{
3128 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3129
3130 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3131
3132 /*
3133 * This is the only place besides the function initialization
3134 * where the bp->flags can change so it is done without any
3135 * locks
3136 */
f2e0899f 3137 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 3138 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
3139 bp->flags |= MF_FUNC_DIS;
3140
3141 bnx2x_e1h_disable(bp);
3142 } else {
3143 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
3144 bp->flags &= ~MF_FUNC_DIS;
3145
3146 bnx2x_e1h_enable(bp);
3147 }
3148 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3149 }
3150 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3151 bnx2x_config_mf_bw(bp);
523224a3
DK		 3152 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3153 }
3154
3155 /* Report results to MCP */
3156 if (dcc_event)
3157 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3158 else
3159 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3160}
3161
3162/* must be called under the spq lock */
3163static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3164{
3165 struct eth_spe *next_spe = bp->spq_prod_bd;
3166
3167 if (bp->spq_prod_bd == bp->spq_last_bd) {
3168 bp->spq_prod_bd = bp->spq;
3169 bp->spq_prod_idx = 0;
3170 DP(NETIF_MSG_TIMER, "end of spq\n");
3171 } else {
3172 bp->spq_prod_bd++;
3173 bp->spq_prod_idx++;
3174 }
3175 return next_spe;
3176}
3177
3178/* must be called under the spq lock */
28912902
MC		 3179static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3180{
3181 int func = BP_FUNC(bp);
3182
53e51e2f
VZ		 3183 /*
3184 * Make sure that BD data is updated before writing the producer:
3185 * BD data is written to the memory, the producer is read from the
3186 * memory, thus we need a full memory barrier to ensure the ordering.
3187 */
3188 mb();
28912902 3189
523224a3 3190 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3191 bp->spq_prod_idx);
28912902
MC		 3192 mmiowb();
3193}
3194
619c5cb6
VZ		 3195/**
3196 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3197 *
3198 * @cmd: command to check
3199 * @cmd_type: command type
3200 */
3201static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3202{
3203 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3204 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3205 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3206 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3207 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3208 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3209 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3210 return true;
3211 else
3212 return false;
3213
3214}
3215
3216
3217/**
3218 * bnx2x_sp_post - place a single command on an SP ring
3219 *
3220 * @bp: driver handle
3221 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3222 * @cid: SW CID the command is related to
3223 * @data_hi: command private data address (high 32 bits)
3224 * @data_lo: command private data address (low 32 bits)
3225 * @cmd_type: command type (e.g. NONE, ETH)
3226 *
3227 * SP data is handled as if it's always an address pair, thus data fields are
3228 * not swapped to little endian in upper functions. Instead this function swaps
3229 * data as if it's two u32 fields.
3230 */
9f6c9258 3231int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3232 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3233{
28912902 3234 struct eth_spe *spe;
523224a3 3235 u16 type;
619c5cb6 3236 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3237
a2fbb9ea
ET		 3238#ifdef BNX2X_STOP_ON_ERROR
3239 if (unlikely(bp->panic))
3240 return -EIO;
3241#endif
3242
34f80b04 3243 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3244
6e30dd4e
VZ		 3245 if (common) {
3246 if (!atomic_read(&bp->eq_spq_left)) {
3247 BNX2X_ERR("BUG! EQ ring full!\n");
3248 spin_unlock_bh(&bp->spq_lock);
3249 bnx2x_panic();
3250 return -EBUSY;
3251 }
3252 } else if (!atomic_read(&bp->cq_spq_left)) {
3253 BNX2X_ERR("BUG! SPQ ring full!\n");
3254 spin_unlock_bh(&bp->spq_lock);
3255 bnx2x_panic();
3256 return -EBUSY;
a2fbb9ea 3257 }
f1410647 3258
28912902
MC		 3259 spe = bnx2x_sp_get_next(bp);
3260
a2fbb9ea 3261 /* CID needs port number to be encoded int it */
28912902 3262 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3263 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3264 HW_CID(bp, cid));
523224a3 3265
619c5cb6 3266 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 3267
523224a3
DK		 3268 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3269 SPE_HDR_FUNCTION_ID);
a2fbb9ea 3270
523224a3
DK		 3271 spe->hdr.type = cpu_to_le16(type);
3272
3273 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3274 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3275
d6cae238
VZ		 3276 /*
3277 * It's ok if the actual decrement is issued towards the memory
3278 * somewhere between the spin_lock and spin_unlock. Thus no
3279 * more explict memory barrier is needed.
3280 */
3281 if (common)
3282 atomic_dec(&bp->eq_spq_left);
3283 else
3284 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3285
a2fbb9ea 3286
cdaa7cb8 3287 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
d6cae238
VZ		 3288 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3289 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3290 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3291 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3292 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3293 HW_CID(bp, cid), data_hi, data_lo, type,
3294 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3295
28912902 3296 bnx2x_sp_prod_update(bp);
34f80b04 3297 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3298 return 0;
3299}
3300
3301/* acquire split MCP access lock register */
4a37fb66 3302static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3303{
72fd0718 3304 u32 j, val;
34f80b04 3305 int rc = 0;
a2fbb9ea
ET		 3306
3307 might_sleep();
72fd0718 3308 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 3309 val = (1UL << 31);
3310 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3311 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3312 if (val & (1L << 31))
3313 break;
3314
3315 msleep(5);
3316 }
a2fbb9ea 3317 if (!(val & (1L << 31))) {
19680c48 3318 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3319 rc = -EBUSY;
3320 }
3321
3322 return rc;
3323}
3324
4a37fb66
YG		 3325/* release split MCP access lock register */
3326static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3327{
72fd0718 3328 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 3329}
3330
523224a3
DK		 3331#define BNX2X_DEF_SB_ATT_IDX 0x0001
3332#define BNX2X_DEF_SB_IDX 0x0002
3333
a2fbb9ea
ET		 3334static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3335{
523224a3 3336 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3337 u16 rc = 0;
3338
3339 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3340 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3341 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3342 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3343 }
523224a3
DK		 3344
3345 if (bp->def_idx != def_sb->sp_sb.running_index) {
3346 bp->def_idx = def_sb->sp_sb.running_index;
3347 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3348 }
523224a3
DK		 3349
3350 /* Do not reorder: indecies reading should complete before handling */
3351 barrier();
a2fbb9ea
ET		 3352 return rc;
3353}
3354
3355/*
3356 * slow path service functions
3357 */
3358
3359static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3360{
34f80b04 3361 int port = BP_PORT(bp);
a2fbb9ea
ET		 3362 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3363 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3364 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3365 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3366 u32 aeu_mask;
87942b46 3367 u32 nig_mask = 0;
f2e0899f 3368 u32 reg_addr;
a2fbb9ea 3369
a2fbb9ea
ET		 3370 if (bp->attn_state & asserted)
3371 BNX2X_ERR("IGU ERROR\n");
3372
3fcaf2e5
EG		 3373 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3374 aeu_mask = REG_RD(bp, aeu_addr);
3375
a2fbb9ea 3376 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3377 aeu_mask, asserted);
72fd0718 3378 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3379 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3380
3fcaf2e5
EG		 3381 REG_WR(bp, aeu_addr, aeu_mask);
3382 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3383
3fcaf2e5 3384 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3385 bp->attn_state |= asserted;
3fcaf2e5 3386 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3387
3388 if (asserted & ATTN_HARD_WIRED_MASK) {
3389 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3390
a5e9a7cf
EG		 3391 bnx2x_acquire_phy_lock(bp);
3392
877e9aa4 3393 /* save nig interrupt mask */
87942b46 3394 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3395
361c391e
YR		 3396 /* If nig_mask is not set, no need to call the update
3397 * function.
3398 */
3399 if (nig_mask) {
3400 REG_WR(bp, nig_int_mask_addr, 0);
3401
3402 bnx2x_link_attn(bp);
3403 }
a2fbb9ea
ET		 3404
3405 /* handle unicore attn? */
3406 }
3407 if (asserted & ATTN_SW_TIMER_4_FUNC)
3408 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3409
3410 if (asserted & GPIO_2_FUNC)
3411 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3412
3413 if (asserted & GPIO_3_FUNC)
3414 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3415
3416 if (asserted & GPIO_4_FUNC)
3417 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3418
3419 if (port == 0) {
3420 if (asserted & ATTN_GENERAL_ATTN_1) {
3421 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3422 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3423 }
3424 if (asserted & ATTN_GENERAL_ATTN_2) {
3425 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3426 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3427 }
3428 if (asserted & ATTN_GENERAL_ATTN_3) {
3429 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3430 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3431 }
3432 } else {
3433 if (asserted & ATTN_GENERAL_ATTN_4) {
3434 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3435 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3436 }
3437 if (asserted & ATTN_GENERAL_ATTN_5) {
3438 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3439 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3440 }
3441 if (asserted & ATTN_GENERAL_ATTN_6) {
3442 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3443 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3444 }
3445 }
3446
3447 } /* if hardwired */
3448
f2e0899f
DK		 3449 if (bp->common.int_block == INT_BLOCK_HC)
3450 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3451 COMMAND_REG_ATTN_BITS_SET);
3452 else
3453 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3454
3455 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3456 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3457 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3458
3459 /* now set back the mask */
a5e9a7cf 3460 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 3461 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3462 bnx2x_release_phy_lock(bp);
3463 }
a2fbb9ea
ET		 3464}
3465
fd4ef40d
EG		 3466static inline void bnx2x_fan_failure(struct bnx2x *bp)
3467{
3468 int port = BP_PORT(bp);
b7737c9b 3469 u32 ext_phy_config;
fd4ef40d 3470 /* mark the failure */
b7737c9b
YR		 3471 ext_phy_config =
3472 SHMEM_RD(bp,
3473 dev_info.port_hw_config[port].external_phy_config);
3474
3475 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3476 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3477 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3478 ext_phy_config);
fd4ef40d
EG		 3479
3480 /* log the failure */
cdaa7cb8
VZ		 3481 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3482 " the driver to shutdown the card to prevent permanent"
3483 " damage. Please contact OEM Support for assistance\n");
8304859a
AE		 3484
3485 /*
3486 * Scheudle device reset (unload)
3487 * This is due to some boards consuming sufficient power when driver is
3488 * up to overheat if fan fails.
3489 */
3490 smp_mb__before_clear_bit();
3491 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3492 smp_mb__after_clear_bit();
3493 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3494
fd4ef40d 3495}
ab6ad5a4 3496
877e9aa4 3497static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3498{
34f80b04 3499 int port = BP_PORT(bp);
877e9aa4 3500 int reg_offset;
d90d96ba 3501 u32 val;
877e9aa4 3502
34f80b04
EG		 3503 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3504 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3505
34f80b04 3506 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3507
3508 val = REG_RD(bp, reg_offset);
3509 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3510 REG_WR(bp, reg_offset, val);
3511
3512 BNX2X_ERR("SPIO5 hw attention\n");
3513
fd4ef40d 3514 /* Fan failure attention */
d90d96ba 3515 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3516 bnx2x_fan_failure(bp);
877e9aa4 3517 }
34f80b04 3518
3deb8167 3519 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3520 bnx2x_acquire_phy_lock(bp);
3521 bnx2x_handle_module_detect_int(&bp->link_params);
3522 bnx2x_release_phy_lock(bp);
3523 }
3524
34f80b04
EG		 3525 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3526
3527 val = REG_RD(bp, reg_offset);
3528 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3529 REG_WR(bp, reg_offset, val);
3530
3531 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3532 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3533 bnx2x_panic();
3534 }
877e9aa4
ET		 3535}
3536
3537static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3538{
3539 u32 val;
3540
0626b899 3541 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3542
3543 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3544 BNX2X_ERR("DB hw attention 0x%x\n", val);
3545 /* DORQ discard attention */
3546 if (val & 0x2)
3547 BNX2X_ERR("FATAL error from DORQ\n");
3548 }
34f80b04
EG		 3549
3550 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3551
3552 int port = BP_PORT(bp);
3553 int reg_offset;
3554
3555 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3556 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3557
3558 val = REG_RD(bp, reg_offset);
3559 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3560 REG_WR(bp, reg_offset, val);
3561
3562 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3563 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3564 bnx2x_panic();
3565 }
877e9aa4
ET		 3566}
3567
3568static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3569{
3570 u32 val;
3571
3572 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3573
3574 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3575 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3576 /* CFC error attention */
3577 if (val & 0x2)
3578 BNX2X_ERR("FATAL error from CFC\n");
3579 }
3580
3581 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3582 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3583 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3584 /* RQ_USDMDP_FIFO_OVERFLOW */
3585 if (val & 0x18000)
3586 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3587
3588 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3589 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3590 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3591 }
877e9aa4 3592 }
34f80b04
EG		 3593
3594 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3595
3596 int port = BP_PORT(bp);
3597 int reg_offset;
3598
3599 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3600 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3601
3602 val = REG_RD(bp, reg_offset);
3603 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3604 REG_WR(bp, reg_offset, val);
3605
3606 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3607 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3608 bnx2x_panic();
3609 }
877e9aa4
ET		 3610}
3611
3612static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3613{
34f80b04
EG		 3614 u32 val;
3615
877e9aa4
ET		 3616 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3617
34f80b04
EG		 3618 if (attn & BNX2X_PMF_LINK_ASSERT) {
3619 int func = BP_FUNC(bp);
3620
3621 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3622 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3623 func_mf_config[BP_ABS_FUNC(bp)].config);
3624 val = SHMEM_RD(bp,
3625 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3626 if (val & DRV_STATUS_DCC_EVENT_MASK)
3627 bnx2x_dcc_event(bp,
3628 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3629
3630 if (val & DRV_STATUS_SET_MF_BW)
3631 bnx2x_set_mf_bw(bp);
3632
1d187b34
BW		 3633 if (val & DRV_STATUS_DRV_INFO_REQ)
3634 bnx2x_handle_drv_info_req(bp);
2691d51d 3635 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3636 bnx2x_pmf_update(bp);
3637
e4901dde 3638 if (bp->port.pmf &&
785b9b1a
SR		 3639 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3640 bp->dcbx_enabled > 0)
e4901dde
VZ		 3641 /* start dcbx state machine */
3642 bnx2x_dcbx_set_params(bp,
3643 BNX2X_DCBX_STATE_NEG_RECEIVED);
3deb8167
YR		 3644 if (bp->link_vars.periodic_flags &
3645 PERIODIC_FLAGS_LINK_EVENT) {
3646 /* sync with link */
3647 bnx2x_acquire_phy_lock(bp);
3648 bp->link_vars.periodic_flags &=
3649 ~PERIODIC_FLAGS_LINK_EVENT;
3650 bnx2x_release_phy_lock(bp);
3651 if (IS_MF(bp))
3652 bnx2x_link_sync_notify(bp);
3653 bnx2x_link_report(bp);
3654 }
3655 /* Always call it here: bnx2x_link_report() will
3656 * prevent the link indication duplication.
3657 */
3658 bnx2x__link_status_update(bp);
34f80b04 3659 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3660
3661 BNX2X_ERR("MC assert!\n");
d6cae238 3662 bnx2x_mc_assert(bp);
877e9aa4
ET		 3663 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3664 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3665 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3666 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3667 bnx2x_panic();
3668
3669 } else if (attn & BNX2X_MCP_ASSERT) {
3670
3671 BNX2X_ERR("MCP assert!\n");
3672 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3673 bnx2x_fw_dump(bp);
877e9aa4
ET		 3674
3675 } else
3676 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3677 }
3678
3679 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3680 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3681 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3682 val = CHIP_IS_E1(bp) ? 0 :
3683 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3684 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3685 }
3686 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3687 val = CHIP_IS_E1(bp) ? 0 :
3688 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3689 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3690 }
877e9aa4 3691 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3692 }
3693}
3694
c9ee9206
VZ		 3695/*
3696 * Bits map:
3697 * 0-7 - Engine0 load counter.
3698 * 8-15 - Engine1 load counter.
3699 * 16 - Engine0 RESET_IN_PROGRESS bit.
3700 * 17 - Engine1 RESET_IN_PROGRESS bit.
3701 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3702 * on the engine
3703 * 19 - Engine1 ONE_IS_LOADED.
3704 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3705 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3706 * just the one belonging to its engine).
3707 *
3708 */
3709#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3710
3711#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3712#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3713#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3714#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3715#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3716#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3717#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3718
3719/*
3720 * Set the GLOBAL_RESET bit.
3721 *
3722 * Should be run under rtnl lock
3723 */
3724void bnx2x_set_reset_global(struct bnx2x *bp)
3725{
3726 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3727
3728 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3729 barrier();
3730 mmiowb();
3731}
3732
3733/*
3734 * Clear the GLOBAL_RESET bit.
3735 *
3736 * Should be run under rtnl lock
3737 */
3738static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3739{
3740 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3741
3742 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3743 barrier();
3744 mmiowb();
3745}
f85582f8 3746
72fd0718 3747/*
c9ee9206
VZ		 3748 * Checks the GLOBAL_RESET bit.
3749 *
72fd0718
VZ		 3750 * should be run under rtnl lock
3751 */
c9ee9206
VZ		 3752static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3753{
3754 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3755
3756 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3757 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3758}
3759
3760/*
3761 * Clear RESET_IN_PROGRESS bit for the current engine.
3762 *
3763 * Should be run under rtnl lock
3764 */
72fd0718
VZ		 3765static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3766{
c9ee9206
VZ		 3767 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3768 u32 bit = BP_PATH(bp) ?
3769 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3770
3771 /* Clear the bit */
3772 val &= ~bit;
3773 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3774 barrier();
3775 mmiowb();
3776}
3777
3778/*
c9ee9206
VZ		 3779 * Set RESET_IN_PROGRESS for the current engine.
3780 *
72fd0718
VZ		 3781 * should be run under rtnl lock
3782 */
c9ee9206 3783void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 3784{
c9ee9206
VZ		 3785 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3786 u32 bit = BP_PATH(bp) ?
3787 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3788
3789 /* Set the bit */
3790 val |= bit;
3791 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3792 barrier();
3793 mmiowb();
3794}
3795
3796/*
c9ee9206 3797 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 3798 * should be run under rtnl lock
3799 */
c9ee9206 3800bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 3801{
c9ee9206
VZ		 3802 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3803 u32 bit = engine ?
3804 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3805
3806 /* return false if bit is set */
3807 return (val & bit) ? false : true;
72fd0718
VZ		 3808}
3809
3810/*
c9ee9206
VZ		 3811 * Increment the load counter for the current engine.
3812 *
72fd0718
VZ		 3813 * should be run under rtnl lock
3814 */
c9ee9206 3815void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718 3816{
c9ee9206
VZ		 3817 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3818 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3819 BNX2X_PATH0_LOAD_CNT_MASK;
3820 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3821 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3822
3823 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3824
c9ee9206
VZ		 3825 /* get the current counter value */
3826 val1 = (val & mask) >> shift;
3827
3828 /* increment... */
3829 val1++;
3830
3831 /* clear the old value */
3832 val &= ~mask;
3833
3834 /* set the new one */
3835 val |= ((val1 << shift) & mask);
3836
3837 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3838 barrier();
3839 mmiowb();
3840}
3841
c9ee9206
VZ		 3842/**
3843 * bnx2x_dec_load_cnt - decrement the load counter
3844 *
3845 * @bp: driver handle
3846 *
3847 * Should be run under rtnl lock.
3848 * Decrements the load counter for the current engine. Returns
3849 * the new counter value.
72fd0718 3850 */
9f6c9258 3851u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718 3852{
c9ee9206
VZ		 3853 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3854 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3855 BNX2X_PATH0_LOAD_CNT_MASK;
3856 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3857 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3858
3859 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3860
c9ee9206
VZ		 3861 /* get the current counter value */
3862 val1 = (val & mask) >> shift;
3863
3864 /* decrement... */
3865 val1--;
3866
3867 /* clear the old value */
3868 val &= ~mask;
3869
3870 /* set the new one */
3871 val |= ((val1 << shift) & mask);
3872
3873 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3874 barrier();
3875 mmiowb();
3876
3877 return val1;
3878}
3879
3880/*
c9ee9206
VZ		 3881 * Read the load counter for the current engine.
3882 *
72fd0718
VZ		 3883 * should be run under rtnl lock
3884 */
c9ee9206 3885static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
72fd0718 3886{
c9ee9206
VZ		 3887 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3888 BNX2X_PATH0_LOAD_CNT_MASK);
3889 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3890 BNX2X_PATH0_LOAD_CNT_SHIFT);
3891 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3892
3893 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3894
3895 val = (val & mask) >> shift;
3896
3897 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3898
3899 return val;
72fd0718
VZ		 3900}
3901
c9ee9206
VZ		 3902/*
3903 * Reset the load counter for the current engine.
3904 *
3905 * should be run under rtnl lock
3906 */
72fd0718
VZ		 3907static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3908{
c9ee9206
VZ		 3909 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3910 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3911 BNX2X_PATH0_LOAD_CNT_MASK);
3912
3913 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
72fd0718
VZ		 3914}
3915
3916static inline void _print_next_block(int idx, const char *blk)
3917{
f1deab50 3918 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 3919}
3920
c9ee9206
VZ		 3921static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3922 bool print)
72fd0718
VZ		 3923{
3924 int i = 0;
3925 u32 cur_bit = 0;
3926 for (i = 0; sig; i++) {
3927 cur_bit = ((u32)0x1 << i);
3928 if (sig & cur_bit) {
3929 switch (cur_bit) {
3930 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
c9ee9206
VZ		 3931 if (print)
3932 _print_next_block(par_num++, "BRB");
72fd0718
VZ		 3933 break;
3934 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
c9ee9206
VZ		 3935 if (print)
3936 _print_next_block(par_num++, "PARSER");
72fd0718
VZ		 3937 break;
3938 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
c9ee9206
VZ		 3939 if (print)
3940 _print_next_block(par_num++, "TSDM");
72fd0718
VZ		 3941 break;
3942 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
c9ee9206
VZ		 3943 if (print)
3944 _print_next_block(par_num++,
3945 "SEARCHER");
3946 break;
3947 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3948 if (print)
3949 _print_next_block(par_num++, "TCM");
72fd0718
VZ		 3950 break;
3951 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
c9ee9206
VZ		 3952 if (print)
3953 _print_next_block(par_num++, "TSEMI");
3954 break;
3955 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3956 if (print)
3957 _print_next_block(par_num++, "XPB");
72fd0718
VZ		 3958 break;
3959 }
3960
3961 /* Clear the bit */
3962 sig &= ~cur_bit;
3963 }
3964 }
3965
3966 return par_num;
3967}
3968
c9ee9206
VZ		 3969static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3970 bool *global, bool print)
72fd0718
VZ		 3971{
3972 int i = 0;
3973 u32 cur_bit = 0;
3974 for (i = 0; sig; i++) {
3975 cur_bit = ((u32)0x1 << i);
3976 if (sig & cur_bit) {
3977 switch (cur_bit) {
c9ee9206
VZ		 3978 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3979 if (print)
3980 _print_next_block(par_num++, "PBF");
72fd0718
VZ		 3981 break;
3982 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
c9ee9206
VZ		 3983 if (print)
3984 _print_next_block(par_num++, "QM");
3985 break;
3986 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3987 if (print)
3988 _print_next_block(par_num++, "TM");
72fd0718
VZ		 3989 break;
3990 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
c9ee9206
VZ		 3991 if (print)
3992 _print_next_block(par_num++, "XSDM");
3993 break;
3994 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3995 if (print)
3996 _print_next_block(par_num++, "XCM");
72fd0718
VZ		 3997 break;
3998 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
c9ee9206
VZ		 3999 if (print)
4000 _print_next_block(par_num++, "XSEMI");
72fd0718
VZ		 4001 break;
4002 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
c9ee9206
VZ		 4003 if (print)
4004 _print_next_block(par_num++,
4005 "DOORBELLQ");
4006 break;
4007 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4008 if (print)
4009 _print_next_block(par_num++, "NIG");
72fd0718
VZ		 4010 break;
4011 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206
VZ		 4012 if (print)
4013 _print_next_block(par_num++,
4014 "VAUX PCI CORE");
4015 *global = true;
72fd0718
VZ		 4016 break;
4017 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
c9ee9206
VZ		 4018 if (print)
4019 _print_next_block(par_num++, "DEBUG");
72fd0718
VZ		 4020 break;
4021 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
c9ee9206
VZ		 4022 if (print)
4023 _print_next_block(par_num++, "USDM");
72fd0718 4024 break;
8736c826
VZ		 4025 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4026 if (print)
4027 _print_next_block(par_num++, "UCM");
4028 break;
72fd0718 4029 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
c9ee9206
VZ		 4030 if (print)
4031 _print_next_block(par_num++, "USEMI");
72fd0718
VZ		 4032 break;
4033 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
c9ee9206
VZ		 4034 if (print)
4035 _print_next_block(par_num++, "UPB");
72fd0718
VZ		 4036 break;
4037 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
c9ee9206
VZ		 4038 if (print)
4039 _print_next_block(par_num++, "CSDM");
72fd0718 4040 break;
8736c826
VZ		 4041 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4042 if (print)
4043 _print_next_block(par_num++, "CCM");
4044 break;
72fd0718
VZ		 4045 }
4046
4047 /* Clear the bit */
4048 sig &= ~cur_bit;
4049 }
4050 }
4051
4052 return par_num;
4053}
4054
c9ee9206
VZ		 4055static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4056 bool print)
72fd0718
VZ		 4057{
4058 int i = 0;
4059 u32 cur_bit = 0;
4060 for (i = 0; sig; i++) {
4061 cur_bit = ((u32)0x1 << i);
4062 if (sig & cur_bit) {
4063 switch (cur_bit) {
4064 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
c9ee9206
VZ		 4065 if (print)
4066 _print_next_block(par_num++, "CSEMI");
72fd0718
VZ		 4067 break;
4068 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
c9ee9206
VZ		 4069 if (print)
4070 _print_next_block(par_num++, "PXP");
72fd0718
VZ		 4071 break;
4072 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
c9ee9206
VZ		 4073 if (print)
4074 _print_next_block(par_num++,
72fd0718
VZ		 4075 "PXPPCICLOCKCLIENT");
4076 break;
4077 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
c9ee9206
VZ		 4078 if (print)
4079 _print_next_block(par_num++, "CFC");
72fd0718
VZ		 4080 break;
4081 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
c9ee9206
VZ		 4082 if (print)
4083 _print_next_block(par_num++, "CDU");
4084 break;
4085 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4086 if (print)
4087 _print_next_block(par_num++, "DMAE");
72fd0718
VZ		 4088 break;
4089 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
c9ee9206
VZ		 4090 if (print)
4091 _print_next_block(par_num++, "IGU");
72fd0718
VZ		 4092 break;
4093 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
c9ee9206
VZ		 4094 if (print)
4095 _print_next_block(par_num++, "MISC");
72fd0718
VZ		 4096 break;
4097 }
4098
4099 /* Clear the bit */
4100 sig &= ~cur_bit;
4101 }
4102 }
4103
4104 return par_num;
4105}
4106
c9ee9206
VZ		 4107static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4108 bool *global, bool print)
72fd0718
VZ		 4109{
4110 int i = 0;
4111 u32 cur_bit = 0;
4112 for (i = 0; sig; i++) {
4113 cur_bit = ((u32)0x1 << i);
4114 if (sig & cur_bit) {
4115 switch (cur_bit) {
4116 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206
VZ		 4117 if (print)
4118 _print_next_block(par_num++, "MCP ROM");
4119 *global = true;
72fd0718
VZ		 4120 break;
4121 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206
VZ		 4122 if (print)
4123 _print_next_block(par_num++,
4124 "MCP UMP RX");
4125 *global = true;
72fd0718
VZ		 4126 break;
4127 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206
VZ		 4128 if (print)
4129 _print_next_block(par_num++,
4130 "MCP UMP TX");
4131 *global = true;
72fd0718
VZ		 4132 break;
4133 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206
VZ		 4134 if (print)
4135 _print_next_block(par_num++,
4136 "MCP SCPAD");
4137 *global = true;
72fd0718
VZ		 4138 break;
4139 }
4140
4141 /* Clear the bit */
4142 sig &= ~cur_bit;
4143 }
4144 }
4145
4146 return par_num;
4147}
4148
8736c826
VZ		 4149static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4150 bool print)
4151{
4152 int i = 0;
4153 u32 cur_bit = 0;
4154 for (i = 0; sig; i++) {
4155 cur_bit = ((u32)0x1 << i);
4156 if (sig & cur_bit) {
4157 switch (cur_bit) {
4158 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4159 if (print)
4160 _print_next_block(par_num++, "PGLUE_B");
4161 break;
4162 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4163 if (print)
4164 _print_next_block(par_num++, "ATC");
4165 break;
4166 }
4167
4168 /* Clear the bit */
4169 sig &= ~cur_bit;
4170 }
4171 }
4172
4173 return par_num;
4174}
4175
c9ee9206 4176static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
8736c826 4177 u32 *sig)
72fd0718 4178{
8736c826
VZ		 4179 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4180 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4181 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4182 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4183 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718
VZ		 4184 int par_num = 0;
4185 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
8736c826
VZ		 4186 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4187 "[4]:0x%08x\n",
4188 sig[0] & HW_PRTY_ASSERT_SET_0,
4189 sig[1] & HW_PRTY_ASSERT_SET_1,
4190 sig[2] & HW_PRTY_ASSERT_SET_2,
4191 sig[3] & HW_PRTY_ASSERT_SET_3,
4192 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4193 if (print)
4194 netdev_err(bp->dev,
4195 "Parity errors detected in blocks: ");
4196 par_num = bnx2x_check_blocks_with_parity0(
8736c826 4197 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
c9ee9206 4198 par_num = bnx2x_check_blocks_with_parity1(
8736c826 4199 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
c9ee9206 4200 par_num = bnx2x_check_blocks_with_parity2(
8736c826 4201 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
c9ee9206 4202 par_num = bnx2x_check_blocks_with_parity3(
8736c826
VZ		 4203 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4204 par_num = bnx2x_check_blocks_with_parity4(
4205 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4206
c9ee9206
VZ		 4207 if (print)
4208 pr_cont("\n");
8736c826 4209
72fd0718
VZ		 4210 return true;
4211 } else
4212 return false;
4213}
4214
c9ee9206
VZ		 4215/**
4216 * bnx2x_chk_parity_attn - checks for parity attentions.
4217 *
4218 * @bp: driver handle
4219 * @global: true if there was a global attention
4220 * @print: show parity attention in syslog
4221 */
4222bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4223{
8736c826 4224 struct attn_route attn = { {0} };
72fd0718
VZ		 4225 int port = BP_PORT(bp);
4226
4227 attn.sig[0] = REG_RD(bp,
4228 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4229 port*4);
4230 attn.sig[1] = REG_RD(bp,
4231 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4232 port*4);
4233 attn.sig[2] = REG_RD(bp,
4234 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4235 port*4);
4236 attn.sig[3] = REG_RD(bp,
4237 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4238 port*4);
4239
8736c826
VZ		 4240 if (!CHIP_IS_E1x(bp))
4241 attn.sig[4] = REG_RD(bp,
4242 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4243 port*4);
4244
4245 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4246}
4247
f2e0899f
DK		 4248
4249static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4250{
4251 u32 val;
4252 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4253
4254 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4255 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4256 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4257 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4258 "ADDRESS_ERROR\n");
4259 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4260 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4261 "INCORRECT_RCV_BEHAVIOR\n");
4262 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4263 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4264 "WAS_ERROR_ATTN\n");
4265 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4266 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4267 "VF_LENGTH_VIOLATION_ATTN\n");
4268 if (val &
4269 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4270 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4271 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4272 if (val &
4273 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4274 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4275 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4276 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4277 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4278 "TCPL_ERROR_ATTN\n");
4279 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4280 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4281 "TCPL_IN_TWO_RCBS_ATTN\n");
4282 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4283 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4284 "CSSNOOP_FIFO_OVERFLOW\n");
4285 }
4286 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4287 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4288 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4289 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4290 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4291 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4292 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4293 "_ATC_TCPL_TO_NOT_PEND\n");
4294 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4295 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4296 "ATC_GPA_MULTIPLE_HITS\n");
4297 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4298 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4299 "ATC_RCPL_TO_EMPTY_CNT\n");
4300 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4301 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4302 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4303 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4304 "ATC_IREQ_LESS_THAN_STU\n");
4305 }
4306
4307 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4308 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4309 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4310 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4311 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4312 }
4313
4314}
4315
72fd0718
VZ		 4316static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4317{
4318 struct attn_route attn, *group_mask;
34f80b04 4319 int port = BP_PORT(bp);
877e9aa4 4320 int index;
a2fbb9ea
ET		 4321 u32 reg_addr;
4322 u32 val;
3fcaf2e5 4323 u32 aeu_mask;
c9ee9206 4324 bool global = false;
a2fbb9ea
ET		 4325
4326 /* need to take HW lock because MCP or other port might also
4327 try to handle this event */
4a37fb66 4328 bnx2x_acquire_alr(bp);
a2fbb9ea 4329
c9ee9206
VZ		 4330 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4331#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4332 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4333 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4334 /* Disable HW interrupts */
4335 bnx2x_int_disable(bp);
72fd0718
VZ		 4336 /* In case of parity errors don't handle attentions so that
4337 * other function would "see" parity errors.
4338 */
c9ee9206
VZ		 4339#else
4340 bnx2x_panic();
4341#endif
4342 bnx2x_release_alr(bp);
72fd0718
VZ		 4343 return;
4344 }
4345
a2fbb9ea
ET		 4346 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4347 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4348 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4349 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4350 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4351 attn.sig[4] =
4352 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4353 else
4354 attn.sig[4] = 0;
4355
4356 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4357 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4358
4359 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4360 if (deasserted & (1 << index)) {
72fd0718 4361 group_mask = &bp->attn_group[index];
a2fbb9ea 4362
f2e0899f
DK		 4363 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4364 "%08x %08x %08x\n",
4365 index,
4366 group_mask->sig[0], group_mask->sig[1],
4367 group_mask->sig[2], group_mask->sig[3],
4368 group_mask->sig[4]);
a2fbb9ea 4369
f2e0899f
DK		 4370 bnx2x_attn_int_deasserted4(bp,
4371 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4372 bnx2x_attn_int_deasserted3(bp,
72fd0718 4373 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4374 bnx2x_attn_int_deasserted1(bp,
72fd0718 4375 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4376 bnx2x_attn_int_deasserted2(bp,
72fd0718 4377 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4378 bnx2x_attn_int_deasserted0(bp,
72fd0718 4379 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4380 }
4381 }
4382
4a37fb66 4383 bnx2x_release_alr(bp);
a2fbb9ea 4384
f2e0899f
DK		 4385 if (bp->common.int_block == INT_BLOCK_HC)
4386 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4387 COMMAND_REG_ATTN_BITS_CLR);
4388 else
4389 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4390
4391 val = ~deasserted;
f2e0899f
DK		 4392 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4393 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4394 REG_WR(bp, reg_addr, val);
a2fbb9ea 4395
a2fbb9ea 4396 if (~bp->attn_state & deasserted)
3fcaf2e5 4397 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4398
4399 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4400 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4401
3fcaf2e5
EG		 4402 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4403 aeu_mask = REG_RD(bp, reg_addr);
4404
4405 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4406 aeu_mask, deasserted);
72fd0718 4407 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4408 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4409
3fcaf2e5
EG		 4410 REG_WR(bp, reg_addr, aeu_mask);
4411 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4412
4413 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4414 bp->attn_state &= ~deasserted;
4415 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4416}
4417
4418static void bnx2x_attn_int(struct bnx2x *bp)
4419{
4420 /* read local copy of bits */
68d59484
EG		 4421 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4422 attn_bits);
4423 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4424 attn_bits_ack);
a2fbb9ea
ET		 4425 u32 attn_state = bp->attn_state;
4426
4427 /* look for changed bits */
4428 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4429 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4430
4431 DP(NETIF_MSG_HW,
4432 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4433 attn_bits, attn_ack, asserted, deasserted);
4434
4435 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4436 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4437
4438 /* handle bits that were raised */
4439 if (asserted)
4440 bnx2x_attn_int_asserted(bp, asserted);
4441
4442 if (deasserted)
4443 bnx2x_attn_int_deasserted(bp, deasserted);
4444}
4445
619c5cb6
VZ		 4446void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4447 u16 index, u8 op, u8 update)
4448{
4449 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4450
4451 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4452 igu_addr);
4453}
4454
523224a3
DK		 4455static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4456{
4457 /* No memory barriers */
4458 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4459 mmiowb(); /* keep prod updates ordered */
4460}
4461
4462#ifdef BCM_CNIC
4463static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4464 union event_ring_elem *elem)
4465{
619c5cb6
VZ		 4466 u8 err = elem->message.error;
4467
523224a3 4468 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4469 (cid < bp->cnic_eth_dev.starting_cid &&
4470 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 4471 return 1;
4472
4473 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4474
619c5cb6
VZ		 4475 if (unlikely(err)) {
4476
523224a3
DK		 4477 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4478 cid);
4479 bnx2x_panic_dump(bp);
4480 }
619c5cb6 4481 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 4482 return 0;
4483}
4484#endif
4485
619c5cb6
VZ		 4486static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4487{
4488 struct bnx2x_mcast_ramrod_params rparam;
4489 int rc;
4490
4491 memset(&rparam, 0, sizeof(rparam));
4492
4493 rparam.mcast_obj = &bp->mcast_obj;
4494
4495 netif_addr_lock_bh(bp->dev);
4496
4497 /* Clear pending state for the last command */
4498 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4499
4500 /* If there are pending mcast commands - send them */
4501 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4502 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4503 if (rc < 0)
4504 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4505 rc);
4506 }
4507
4508 netif_addr_unlock_bh(bp->dev);
4509}
4510
4511static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4512 union event_ring_elem *elem)
4513{
4514 unsigned long ramrod_flags = 0;
4515 int rc = 0;
4516 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4517 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4518
4519 /* Always push next commands out, don't wait here */
4520 __set_bit(RAMROD_CONT, &ramrod_flags);
4521
4522 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4523 case BNX2X_FILTER_MAC_PENDING:
4524#ifdef BCM_CNIC
4525 if (cid == BNX2X_ISCSI_ETH_CID)
4526 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4527 else
4528#endif
4529 vlan_mac_obj = &bp->fp[cid].mac_obj;
4530
4531 break;
619c5cb6
VZ		 4532 case BNX2X_FILTER_MCAST_PENDING:
4533 /* This is only relevant for 57710 where multicast MACs are
4534 * configured as unicast MACs using the same ramrod.
4535 */
4536 bnx2x_handle_mcast_eqe(bp);
4537 return;
4538 default:
4539 BNX2X_ERR("Unsupported classification command: %d\n",
4540 elem->message.data.eth_event.echo);
4541 return;
4542 }
4543
4544 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4545
4546 if (rc < 0)
4547 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4548 else if (rc > 0)
4549 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4550
4551}
4552
4553#ifdef BCM_CNIC
4554static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4555#endif
4556
4557static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4558{
4559 netif_addr_lock_bh(bp->dev);
4560
4561 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4562
4563 /* Send rx_mode command again if was requested */
4564 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4565 bnx2x_set_storm_rx_mode(bp);
4566#ifdef BCM_CNIC
4567 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4568 &bp->sp_state))
4569 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4570 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4571 &bp->sp_state))
4572 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4573#endif
4574
4575 netif_addr_unlock_bh(bp->dev);
4576}
4577
4578static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4579 struct bnx2x *bp, u32 cid)
4580{
94f05b0f 4581 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
619c5cb6
VZ		 4582#ifdef BCM_CNIC
4583 if (cid == BNX2X_FCOE_ETH_CID)
4584 return &bnx2x_fcoe(bp, q_obj);
4585 else
4586#endif
6383c0b3 4587 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
619c5cb6
VZ		 4588}
4589
523224a3
DK		 4590static void bnx2x_eq_int(struct bnx2x *bp)
4591{
4592 u16 hw_cons, sw_cons, sw_prod;
4593 union event_ring_elem *elem;
4594 u32 cid;
4595 u8 opcode;
4596 int spqe_cnt = 0;
619c5cb6
VZ		 4597 struct bnx2x_queue_sp_obj *q_obj;
4598 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4599 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 4600
4601 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4602
4603 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4604 * when we get the the next-page we nned to adjust so the loop
4605 * condition below will be met. The next element is the size of a
4606 * regular element and hence incrementing by 1
4607 */
4608 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4609 hw_cons++;
4610
25985edc 4611 /* This function may never run in parallel with itself for a
523224a3
DK		 4612 * specific bp, thus there is no need in "paired" read memory
4613 * barrier here.
4614 */
4615 sw_cons = bp->eq_cons;
4616 sw_prod = bp->eq_prod;
4617
d6cae238 4618 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 4619 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 4620
4621 for (; sw_cons != hw_cons;
4622 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4623
4624
4625 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4626
4627 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4628 opcode = elem->message.opcode;
4629
4630
4631 /* handle eq element */
4632 switch (opcode) {
4633 case EVENT_RING_OPCODE_STAT_QUERY:
619c5cb6
VZ		 4634 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4635 bp->stats_comp++);
523224a3 4636 /* nothing to do with stats comp */
d6cae238 4637 goto next_spqe;
523224a3
DK		 4638
4639 case EVENT_RING_OPCODE_CFC_DEL:
4640 /* handle according to cid range */
4641 /*
4642 * we may want to verify here that the bp state is
4643 * HALTING
4644 */
d6cae238 4645 DP(BNX2X_MSG_SP,
523224a3
DK		 4646 "got delete ramrod for MULTI[%d]\n", cid);
4647#ifdef BCM_CNIC
4648 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4649 goto next_spqe;
4650#endif
619c5cb6
VZ		 4651 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4652
4653 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4654 break;
4655
4656
523224a3
DK		 4657
4658 goto next_spqe;
e4901dde
VZ		 4659
4660 case EVENT_RING_OPCODE_STOP_TRAFFIC:
d6cae238 4661 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
6debea87
DK		 4662 if (f_obj->complete_cmd(bp, f_obj,
4663 BNX2X_F_CMD_TX_STOP))
4664 break;
e4901dde
VZ		 4665 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4666 goto next_spqe;
619c5cb6 4667
e4901dde 4668 case EVENT_RING_OPCODE_START_TRAFFIC:
d6cae238 4669 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
6debea87
DK		 4670 if (f_obj->complete_cmd(bp, f_obj,
4671 BNX2X_F_CMD_TX_START))
4672 break;
e4901dde
VZ		 4673 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4674 goto next_spqe;
619c5cb6 4675 case EVENT_RING_OPCODE_FUNCTION_START:
d6cae238 4676 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
619c5cb6
VZ		 4677 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4678 break;
4679
4680 goto next_spqe;
4681
4682 case EVENT_RING_OPCODE_FUNCTION_STOP:
d6cae238 4683 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 4684 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4685 break;
4686
4687 goto next_spqe;
523224a3
DK		 4688 }
4689
4690 switch (opcode | bp->state) {
619c5cb6
VZ		 4691 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4692 BNX2X_STATE_OPEN):
4693 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 4694 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 4695 cid = elem->message.data.eth_event.echo &
4696 BNX2X_SWCID_MASK;
d6cae238 4697 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 4698 cid);
4699 rss_raw->clear_pending(rss_raw);
523224a3
DK		 4700 break;
4701
619c5cb6
VZ		 4702 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4703 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4704 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 4705 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4706 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4707 BNX2X_STATE_OPEN):
4708 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4709 BNX2X_STATE_DIAG):
4710 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4711 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4712 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 4713 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 4714 break;
4715
619c5cb6
VZ		 4716 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4717 BNX2X_STATE_OPEN):
4718 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4719 BNX2X_STATE_DIAG):
4720 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4721 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4722 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 4723 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 4724 break;
4725
619c5cb6
VZ		 4726 case (EVENT_RING_OPCODE_FILTERS_RULES |
4727 BNX2X_STATE_OPEN):
4728 case (EVENT_RING_OPCODE_FILTERS_RULES |
4729 BNX2X_STATE_DIAG):
4730 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 4731 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4732 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 4733 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 4734 break;
4735 default:
4736 /* unknown event log error and continue */
619c5cb6
VZ		 4737 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4738 elem->message.opcode, bp->state);
523224a3
DK		 4739 }
4740next_spqe:
4741 spqe_cnt++;
4742 } /* for */
4743
8fe23fbd 4744 smp_mb__before_atomic_inc();
6e30dd4e 4745 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 4746
4747 bp->eq_cons = sw_cons;
4748 bp->eq_prod = sw_prod;
4749 /* Make sure that above mem writes were issued towards the memory */
4750 smp_wmb();
4751
4752 /* update producer */
4753 bnx2x_update_eq_prod(bp, bp->eq_prod);
4754}
4755
a2fbb9ea
ET		 4756static void bnx2x_sp_task(struct work_struct *work)
4757{
1cf167f2 4758 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 4759 u16 status;
4760
a2fbb9ea 4761 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 4762/* if (status == 0) */
4763/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 4764
cdaa7cb8 4765 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 4766
877e9aa4 4767 /* HW attentions */
523224a3 4768 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 4769 bnx2x_attn_int(bp);
523224a3 4770 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 4771 }
4772
523224a3
DK		 4773 /* SP events: STAT_QUERY and others */
4774 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 4775#ifdef BCM_CNIC
4776 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 4777
ec6ba945 4778 if ((!NO_FCOE(bp)) &&
019dbb4c
VZ		 4779 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4780 /*
4781 * Prevent local bottom-halves from running as
4782 * we are going to change the local NAPI list.
4783 */
4784 local_bh_disable();
ec6ba945 4785 napi_schedule(&bnx2x_fcoe(bp, napi));
019dbb4c
VZ		 4786 local_bh_enable();
4787 }
ec6ba945 4788#endif
523224a3
DK		 4789 /* Handle EQ completions */
4790 bnx2x_eq_int(bp);
4791
4792 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4793 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4794
4795 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 4796 }
4797
4798 if (unlikely(status))
4799 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4800 status);
a2fbb9ea 4801
523224a3
DK		 4802 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4803 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 4804}
4805
9f6c9258 4806irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 4807{
4808 struct net_device *dev = dev_instance;
4809 struct bnx2x *bp = netdev_priv(dev);
4810
523224a3
DK		 4811 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4812 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 4813
4814#ifdef BNX2X_STOP_ON_ERROR
4815 if (unlikely(bp->panic))
4816 return IRQ_HANDLED;
4817#endif
4818
993ac7b5
MC		 4819#ifdef BCM_CNIC
4820 {
4821 struct cnic_ops *c_ops;
4822
4823 rcu_read_lock();
4824 c_ops = rcu_dereference(bp->cnic_ops);
4825 if (c_ops)
4826 c_ops->cnic_handler(bp->cnic_data, NULL);
4827 rcu_read_unlock();
4828 }
4829#endif
1cf167f2 4830 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 4831
4832 return IRQ_HANDLED;
4833}
4834
4835/* end of slow path */
4836
619c5cb6
VZ		 4837
4838void bnx2x_drv_pulse(struct bnx2x *bp)
4839{
4840 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4841 bp->fw_drv_pulse_wr_seq);
4842}
4843
4844
a2fbb9ea
ET		 4845static void bnx2x_timer(unsigned long data)
4846{
6383c0b3 4847 u8 cos;
a2fbb9ea
ET		 4848 struct bnx2x *bp = (struct bnx2x *) data;
4849
4850 if (!netif_running(bp->dev))
4851 return;
4852
a2fbb9ea
ET		 4853 if (poll) {
4854 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 4855
6383c0b3
AE		 4856 for_each_cos_in_tx_queue(fp, cos)
4857 bnx2x_tx_int(bp, &fp->txdata[cos]);
b8ee8328 4858 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 4859 }
4860
34f80b04 4861 if (!BP_NOMCP(bp)) {
f2e0899f 4862 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 4863 u32 drv_pulse;
4864 u32 mcp_pulse;
4865
4866 ++bp->fw_drv_pulse_wr_seq;
4867 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4868 /* TBD - add SYSTEM_TIME */
4869 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 4870 bnx2x_drv_pulse(bp);
a2fbb9ea 4871
f2e0899f 4872 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 4873 MCP_PULSE_SEQ_MASK);
4874 /* The delta between driver pulse and mcp response
4875 * should be 1 (before mcp response) or 0 (after mcp response)
4876 */
4877 if ((drv_pulse != mcp_pulse) &&
4878 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4879 /* someone lost a heartbeat... */
4880 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4881 drv_pulse, mcp_pulse);
4882 }
4883 }
4884
f34d28ea 4885 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 4886 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 4887
a2fbb9ea
ET		 4888 mod_timer(&bp->timer, jiffies + bp->current_interval);
4889}
4890
4891/* end of Statistics */
4892
4893/* nic init */
4894
4895/*
4896 * nic init service functions
4897 */
4898
523224a3 4899static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 4900{
523224a3
DK		 4901 u32 i;
4902 if (!(len%4) && !(addr%4))
4903 for (i = 0; i < len; i += 4)
4904 REG_WR(bp, addr + i, fill);
4905 else
4906 for (i = 0; i < len; i++)
4907 REG_WR8(bp, addr + i, fill);
34f80b04 4908
34f80b04
EG		 4909}
4910
523224a3
DK		 4911/* helper: writes FP SP data to FW - data_size in dwords */
4912static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4913 int fw_sb_id,
4914 u32 *sb_data_p,
4915 u32 data_size)
34f80b04 4916{
a2fbb9ea 4917 int index;
523224a3
DK		 4918 for (index = 0; index < data_size; index++)
4919 REG_WR(bp, BAR_CSTRORM_INTMEM +
4920 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4921 sizeof(u32)*index,
4922 *(sb_data_p + index));
4923}
a2fbb9ea 4924
523224a3
DK		 4925static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4926{
4927 u32 *sb_data_p;
4928 u32 data_size = 0;
f2e0899f 4929 struct hc_status_block_data_e2 sb_data_e2;
523224a3 4930 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 4931
523224a3 4932 /* disable the function first */
619c5cb6 4933 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4934 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4935 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 4936 sb_data_e2.common.p_func.vf_valid = false;
4937 sb_data_p = (u32 *)&sb_data_e2;
4938 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4939 } else {
4940 memset(&sb_data_e1x, 0,
4941 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4942 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 4943 sb_data_e1x.common.p_func.vf_valid = false;
4944 sb_data_p = (u32 *)&sb_data_e1x;
4945 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4946 }
523224a3 4947 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 4948
523224a3
DK		 4949 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4950 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4951 CSTORM_STATUS_BLOCK_SIZE);
4952 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4953 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4954 CSTORM_SYNC_BLOCK_SIZE);
4955}
34f80b04 4956
523224a3
DK		 4957/* helper: writes SP SB data to FW */
4958static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4959 struct hc_sp_status_block_data *sp_sb_data)
4960{
4961 int func = BP_FUNC(bp);
4962 int i;
4963 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4964 REG_WR(bp, BAR_CSTRORM_INTMEM +
4965 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4966 i*sizeof(u32),
4967 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4968}
4969
523224a3 4970static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4971{
4972 int func = BP_FUNC(bp);
523224a3
DK		 4973 struct hc_sp_status_block_data sp_sb_data;
4974 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4975
619c5cb6 4976 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 4977 sp_sb_data.p_func.vf_valid = false;
4978
4979 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4980
4981 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4982 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4983 CSTORM_SP_STATUS_BLOCK_SIZE);
4984 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4985 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4986 CSTORM_SP_SYNC_BLOCK_SIZE);
4987
4988}
4989
4990
4991static inline
4992void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4993 int igu_sb_id, int igu_seg_id)
4994{
4995 hc_sm->igu_sb_id = igu_sb_id;
4996 hc_sm->igu_seg_id = igu_seg_id;
4997 hc_sm->timer_value = 0xFF;
4998 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4999}
5000
150966ad
AE		 5001
5002/* allocates state machine ids. */
5003static inline
5004void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5005{
5006 /* zero out state machine indices */
5007 /* rx indices */
5008 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5009
5010 /* tx indices */
5011 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5012 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5013 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5014 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5015
5016 /* map indices */
5017 /* rx indices */
5018 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5019 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5020
5021 /* tx indices */
5022 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5023 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5024 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5025 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5026 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5027 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5028 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5029 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5030}
5031
8d96286a 5032static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5033 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5034{
523224a3
DK		 5035 int igu_seg_id;
5036
f2e0899f 5037 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5038 struct hc_status_block_data_e1x sb_data_e1x;
5039 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5040 int data_size;
5041 u32 *sb_data_p;
5042
f2e0899f
DK		 5043 if (CHIP_INT_MODE_IS_BC(bp))
5044 igu_seg_id = HC_SEG_ACCESS_NORM;
5045 else
5046 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5047
5048 bnx2x_zero_fp_sb(bp, fw_sb_id);
5049
619c5cb6 5050 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5051 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5052 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5053 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5054 sb_data_e2.common.p_func.vf_id = vfid;
5055 sb_data_e2.common.p_func.vf_valid = vf_valid;
5056 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5057 sb_data_e2.common.same_igu_sb_1b = true;
5058 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5059 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5060 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5061 sb_data_p = (u32 *)&sb_data_e2;
5062 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5063 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5064 } else {
5065 memset(&sb_data_e1x, 0,
5066 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5067 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5068 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5069 sb_data_e1x.common.p_func.vf_id = 0xff;
5070 sb_data_e1x.common.p_func.vf_valid = false;
5071 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5072 sb_data_e1x.common.same_igu_sb_1b = true;
5073 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5074 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5075 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5076 sb_data_p = (u32 *)&sb_data_e1x;
5077 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5078 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5079 }
523224a3
DK		 5080
5081 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5082 igu_sb_id, igu_seg_id);
5083 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5084 igu_sb_id, igu_seg_id);
5085
5086 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
5087
5088 /* write indecies to HW */
5089 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5090}
5091
619c5cb6 5092static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5093 u16 tx_usec, u16 rx_usec)
5094{
6383c0b3 5095 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5096 false, rx_usec);
6383c0b3
AE		 5097 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5098 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5099 tx_usec);
5100 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5101 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5102 tx_usec);
5103 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5104 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5105 tx_usec);
523224a3 5106}
f2e0899f 5107
523224a3
DK		 5108static void bnx2x_init_def_sb(struct bnx2x *bp)
5109{
5110 struct host_sp_status_block *def_sb = bp->def_status_blk;
5111 dma_addr_t mapping = bp->def_status_blk_mapping;
5112 int igu_sp_sb_index;
5113 int igu_seg_id;
34f80b04
EG		 5114 int port = BP_PORT(bp);
5115 int func = BP_FUNC(bp);
f2eaeb58 5116 int reg_offset, reg_offset_en5;
a2fbb9ea 5117 u64 section;
523224a3
DK		 5118 int index;
5119 struct hc_sp_status_block_data sp_sb_data;
5120 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5121
f2e0899f
DK		 5122 if (CHIP_INT_MODE_IS_BC(bp)) {
5123 igu_sp_sb_index = DEF_SB_IGU_ID;
5124 igu_seg_id = HC_SEG_ACCESS_DEF;
5125 } else {
5126 igu_sp_sb_index = bp->igu_dsb_id;
5127 igu_seg_id = IGU_SEG_ACCESS_DEF;
5128 }
a2fbb9ea
ET		 5129
5130 /* ATTN */
523224a3 5131 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5132 atten_status_block);
523224a3 5133 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5134
49d66772
ET		 5135 bp->attn_state = 0;
5136
a2fbb9ea
ET		 5137 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5138 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5139 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5140 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5141 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5142 int sindex;
5143 /* take care of sig[0]..sig[4] */
5144 for (sindex = 0; sindex < 4; sindex++)
5145 bp->attn_group[index].sig[sindex] =
5146 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5147
619c5cb6 5148 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5149 /*
5150 * enable5 is separate from the rest of the registers,
5151 * and therefore the address skip is 4
5152 * and not 16 between the different groups
5153 */
5154 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5155 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5156 else
5157 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5158 }
5159
f2e0899f
DK		 5160 if (bp->common.int_block == INT_BLOCK_HC) {
5161 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5162 HC_REG_ATTN_MSG0_ADDR_L);
5163
5164 REG_WR(bp, reg_offset, U64_LO(section));
5165 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5166 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5167 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5168 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5169 }
a2fbb9ea 5170
523224a3
DK		 5171 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5172 sp_sb);
a2fbb9ea 5173
523224a3 5174 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5175
619c5cb6 5176 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5177 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5178 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5179 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5180 sp_sb_data.igu_seg_id = igu_seg_id;
5181 sp_sb_data.p_func.pf_id = func;
f2e0899f 5182 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5183 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5184
523224a3 5185 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5186
523224a3 5187 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5188}
5189
9f6c9258 5190void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5191{
a2fbb9ea
ET		 5192 int i;
5193
ec6ba945 5194 for_each_eth_queue(bp, i)
523224a3 5195 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5196 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5197}
5198
a2fbb9ea
ET		 5199static void bnx2x_init_sp_ring(struct bnx2x *bp)
5200{
a2fbb9ea 5201 spin_lock_init(&bp->spq_lock);
6e30dd4e 5202 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5203
a2fbb9ea 5204 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5205 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5206 bp->spq_prod_bd = bp->spq;
5207 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5208}
5209
523224a3 5210static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5211{
5212 int i;
523224a3
DK		 5213 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5214 union event_ring_elem *elem =
5215 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5216
523224a3
DK		 5217 elem->next_page.addr.hi =
5218 cpu_to_le32(U64_HI(bp->eq_mapping +
5219 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5220 elem->next_page.addr.lo =
5221 cpu_to_le32(U64_LO(bp->eq_mapping +
5222 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5223 }
523224a3
DK		 5224 bp->eq_cons = 0;
5225 bp->eq_prod = NUM_EQ_DESC;
5226 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 5227 /* we want a warning message before it gets rought... */
5228 atomic_set(&bp->eq_spq_left,
5229 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5230}
5231
619c5cb6
VZ		 5232
5233/* called with netif_addr_lock_bh() */
5234void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5235 unsigned long rx_mode_flags,
5236 unsigned long rx_accept_flags,
5237 unsigned long tx_accept_flags,
5238 unsigned long ramrod_flags)
ab532cf3 5239{
619c5cb6
VZ		 5240 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5241 int rc;
5242
5243 memset(&ramrod_param, 0, sizeof(ramrod_param));
5244
5245 /* Prepare ramrod parameters */
5246 ramrod_param.cid = 0;
5247 ramrod_param.cl_id = cl_id;
5248 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5249 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5250
619c5cb6
VZ		 5251 ramrod_param.pstate = &bp->sp_state;
5252 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5253
619c5cb6
VZ		 5254 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5255 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5256
5257 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5258
5259 ramrod_param.ramrod_flags = ramrod_flags;
5260 ramrod_param.rx_mode_flags = rx_mode_flags;
5261
5262 ramrod_param.rx_accept_flags = rx_accept_flags;
5263 ramrod_param.tx_accept_flags = tx_accept_flags;
5264
5265 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5266 if (rc < 0) {
5267 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5268 return;
5269 }
a2fbb9ea
ET		 5270}
5271
619c5cb6
VZ		 5272/* called with netif_addr_lock_bh() */
5273void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 5274{
619c5cb6
VZ		 5275 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5276 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 5277
619c5cb6
VZ		 5278#ifdef BCM_CNIC
5279 if (!NO_FCOE(bp))
5280
5281 /* Configure rx_mode of FCoE Queue */
5282 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5283#endif
5284
5285 switch (bp->rx_mode) {
5286 case BNX2X_RX_MODE_NONE:
5287 /*
5288 * 'drop all' supersedes any accept flags that may have been
5289 * passed to the function.
5290 */
5291 break;
5292 case BNX2X_RX_MODE_NORMAL:
5293 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5294 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5295 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5296
5297 /* internal switching mode */
5298 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5299 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5300 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5301
5302 break;
5303 case BNX2X_RX_MODE_ALLMULTI:
5304 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5305 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5306 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5307
5308 /* internal switching mode */
5309 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5310 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5311 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5312
5313 break;
5314 case BNX2X_RX_MODE_PROMISC:
5315 /* According to deffinition of SI mode, iface in promisc mode
5316 * should receive matched and unmatched (in resolution of port)
5317 * unicast packets.
5318 */
5319 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5320 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5321 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5322 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5323
5324 /* internal switching mode */
5325 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5326 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5327
5328 if (IS_MF_SI(bp))
5329 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5330 else
5331 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5332
5333 break;
5334 default:
5335 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5336 return;
5337 }
de832a55 5338
619c5cb6
VZ		 5339 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5340 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5341 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 5342 }
5343
619c5cb6
VZ		 5344 __set_bit(RAMROD_RX, &ramrod_flags);
5345 __set_bit(RAMROD_TX, &ramrod_flags);
5346
5347 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5348 tx_accept_flags, ramrod_flags);
5349}
5350
5351static void bnx2x_init_internal_common(struct bnx2x *bp)
5352{
5353 int i;
5354
0793f83f
DK		 5355 if (IS_MF_SI(bp))
5356 /*
5357 * In switch independent mode, the TSTORM needs to accept
5358 * packets that failed classification, since approximate match
5359 * mac addresses aren't written to NIG LLH
5360 */
5361 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5362 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 5363 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5364 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5365 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 5366
523224a3
DK		 5367 /* Zero this manually as its initialization is
5368 currently missing in the initTool */
5369 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 5370 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 5371 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 5372 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5373 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5374 CHIP_INT_MODE_IS_BC(bp) ?
5375 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5376 }
523224a3 5377}
8a1c38d1 5378
471de716
EG		 5379static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5380{
5381 switch (load_code) {
5382 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5383 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 5384 bnx2x_init_internal_common(bp);
5385 /* no break */
5386
5387 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 5388 /* nothing to do */
471de716
EG		 5389 /* no break */
5390
5391 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 5392 /* internal memory per function is
5393 initialized inside bnx2x_pf_init */
471de716
EG		 5394 break;
5395
5396 default:
5397 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5398 break;
5399 }
5400}
5401
619c5cb6 5402static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 5403{
6383c0b3 5404 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
619c5cb6 5405}
523224a3 5406
619c5cb6
VZ		 5407static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5408{
6383c0b3 5409 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
619c5cb6
VZ		 5410}
5411
5412static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5413{
5414 if (CHIP_IS_E1x(fp->bp))
5415 return BP_L_ID(fp->bp) + fp->index;
5416 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5417 return bnx2x_fp_igu_sb_id(fp);
5418}
5419
6383c0b3 5420static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 5421{
5422 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 5423 u8 cos;
619c5cb6 5424 unsigned long q_type = 0;
6383c0b3 5425 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 5426 fp->rx_queue = fp_idx;
b3b83c3f 5427 fp->cid = fp_idx;
619c5cb6
VZ		 5428 fp->cl_id = bnx2x_fp_cl_id(fp);
5429 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5430 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 5431 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 5432 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5433
523224a3 5434 /* init shortcut */
619c5cb6 5435 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
523224a3
DK		 5436 /* Setup SB indicies */
5437 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 5438
619c5cb6
VZ		 5439 /* Configure Queue State object */
5440 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5441 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 5442
5443 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5444
5445 /* init tx data */
5446 for_each_cos_in_tx_queue(fp, cos) {
5447 bnx2x_init_txdata(bp, &fp->txdata[cos],
5448 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5449 FP_COS_TO_TXQ(fp, cos),
5450 BNX2X_TX_SB_INDEX_BASE + cos);
5451 cids[cos] = fp->txdata[cos].cid;
5452 }
5453
5454 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5455 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5456 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 5457
5458 /**
5459 * Configure classification DBs: Always enable Tx switching
5460 */
5461 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5462
523224a3
DK		 5463 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5464 "cl_id %d fw_sb %d igu_sb %d\n",
619c5cb6 5465 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
523224a3
DK		 5466 fp->igu_sb_id);
5467 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5468 fp->fw_sb_id, fp->igu_sb_id);
5469
5470 bnx2x_update_fpsb_idx(fp);
5471}
5472
9f6c9258 5473void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 5474{
5475 int i;
5476
ec6ba945 5477 for_each_eth_queue(bp, i)
6383c0b3 5478 bnx2x_init_eth_fp(bp, i);
37b091ba 5479#ifdef BCM_CNIC
ec6ba945
VZ		 5480 if (!NO_FCOE(bp))
5481 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 5482
5483 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5484 BNX2X_VF_ID_INVALID, false,
619c5cb6 5485 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 5486
37b091ba 5487#endif
a2fbb9ea 5488
020c7e3f
YR		 5489 /* Initialize MOD_ABS interrupts */
5490 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5491 bp->common.shmem_base, bp->common.shmem2_base,
5492 BP_PORT(bp));
16119785
EG		 5493 /* ensure status block indices were read */
5494 rmb();
5495
523224a3 5496 bnx2x_init_def_sb(bp);
5c862848 5497 bnx2x_update_dsb_idx(bp);
a2fbb9ea 5498 bnx2x_init_rx_rings(bp);
523224a3 5499 bnx2x_init_tx_rings(bp);
a2fbb9ea 5500 bnx2x_init_sp_ring(bp);
523224a3 5501 bnx2x_init_eq_ring(bp);
471de716 5502 bnx2x_init_internal(bp, load_code);
523224a3 5503 bnx2x_pf_init(bp);
0ef00459
EG		 5504 bnx2x_stats_init(bp);
5505
0ef00459
EG		 5506 /* flush all before enabling interrupts */
5507 mb();
5508 mmiowb();
5509
615f8fd9 5510 bnx2x_int_enable(bp);
eb8da205
EG		 5511
5512 /* Check for SPIO5 */
5513 bnx2x_attn_int_deasserted0(bp,
5514 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5515 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 5516}
5517
5518/* end of nic init */
5519
5520/*
5521 * gzip service functions
5522 */
5523
5524static int bnx2x_gunzip_init(struct bnx2x *bp)
5525{
1a983142
FT		 5526 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5527 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 5528 if (bp->gunzip_buf == NULL)
5529 goto gunzip_nomem1;
5530
5531 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5532 if (bp->strm == NULL)
5533 goto gunzip_nomem2;
5534
7ab24bfd 5535 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 5536 if (bp->strm->workspace == NULL)
5537 goto gunzip_nomem3;
5538
5539 return 0;
5540
5541gunzip_nomem3:
5542 kfree(bp->strm);
5543 bp->strm = NULL;
5544
5545gunzip_nomem2:
1a983142
FT		 5546 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5547 bp->gunzip_mapping);
a2fbb9ea
ET		 5548 bp->gunzip_buf = NULL;
5549
5550gunzip_nomem1:
cdaa7cb8
VZ		 5551 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5552 " un-compression\n");
a2fbb9ea
ET		 5553 return -ENOMEM;
5554}
5555
5556static void bnx2x_gunzip_end(struct bnx2x *bp)
5557{
b3b83c3f 5558 if (bp->strm) {
7ab24bfd 5559 vfree(bp->strm->workspace);
b3b83c3f
DK		 5560 kfree(bp->strm);
5561 bp->strm = NULL;
5562 }
a2fbb9ea
ET		 5563
5564 if (bp->gunzip_buf) {
1a983142
FT		 5565 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5566 bp->gunzip_mapping);
a2fbb9ea
ET		 5567 bp->gunzip_buf = NULL;
5568 }
5569}
5570
94a78b79 5571static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 5572{
5573 int n, rc;
5574
5575 /* check gzip header */
94a78b79
VZ		 5576 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5577 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 5578 return -EINVAL;
94a78b79 5579 }
a2fbb9ea
ET		 5580
5581 n = 10;
5582
34f80b04 5583#define FNAME 0x8
a2fbb9ea
ET		 5584
5585 if (zbuf[3] & FNAME)
5586 while ((zbuf[n++] != 0) && (n < len));
5587
94a78b79 5588 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 5589 bp->strm->avail_in = len - n;
5590 bp->strm->next_out = bp->gunzip_buf;
5591 bp->strm->avail_out = FW_BUF_SIZE;
5592
5593 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5594 if (rc != Z_OK)
5595 return rc;
5596
5597 rc = zlib_inflate(bp->strm, Z_FINISH);
5598 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 5599 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5600 bp->strm->msg);
a2fbb9ea
ET		 5601
5602 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5603 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 5604 netdev_err(bp->dev, "Firmware decompression error:"
5605 " gunzip_outlen (%d) not aligned\n",
5606 bp->gunzip_outlen);
a2fbb9ea
ET		 5607 bp->gunzip_outlen >>= 2;
5608
5609 zlib_inflateEnd(bp->strm);
5610
5611 if (rc == Z_STREAM_END)
5612 return 0;
5613
5614 return rc;
5615}
5616
5617/* nic load/unload */
5618
5619/*
34f80b04 5620 * General service functions
a2fbb9ea
ET		 5621 */
5622
5623/* send a NIG loopback debug packet */
5624static void bnx2x_lb_pckt(struct bnx2x *bp)
5625{
a2fbb9ea 5626 u32 wb_write[3];
a2fbb9ea
ET		 5627
5628 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 5629 wb_write[0] = 0x55555555;
5630 wb_write[1] = 0x55555555;
34f80b04 5631 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 5632 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5633
5634 /* NON-IP protocol */
a2fbb9ea
ET		 5635 wb_write[0] = 0x09000000;
5636 wb_write[1] = 0x55555555;
34f80b04 5637 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 5638 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5639}
5640
5641/* some of the internal memories
5642 * are not directly readable from the driver
5643 * to test them we send debug packets
5644 */
5645static int bnx2x_int_mem_test(struct bnx2x *bp)
5646{
5647 int factor;
5648 int count, i;
5649 u32 val = 0;
5650
ad8d3948 5651 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 5652 factor = 120;
ad8d3948
EG		 5653 else if (CHIP_REV_IS_EMUL(bp))
5654 factor = 200;
5655 else
a2fbb9ea 5656 factor = 1;
a2fbb9ea 5657
a2fbb9ea
ET		 5658 /* Disable inputs of parser neighbor blocks */
5659 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5660 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5661 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5662 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5663
5664 /* Write 0 to parser credits for CFC search request */
5665 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5666
5667 /* send Ethernet packet */
5668 bnx2x_lb_pckt(bp);
5669
5670 /* TODO do i reset NIG statistic? */
5671 /* Wait until NIG register shows 1 packet of size 0x10 */
5672 count = 1000 * factor;
5673 while (count) {
34f80b04 5674
a2fbb9ea
ET		 5675 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5676 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5677 if (val == 0x10)
5678 break;
5679
5680 msleep(10);
5681 count--;
5682 }
5683 if (val != 0x10) {
5684 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5685 return -1;
5686 }
5687
5688 /* Wait until PRS register shows 1 packet */
5689 count = 1000 * factor;
5690 while (count) {
5691 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 5692 if (val == 1)
5693 break;
5694
5695 msleep(10);
5696 count--;
5697 }
5698 if (val != 0x1) {
5699 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5700 return -2;
5701 }
5702
5703 /* Reset and init BRB, PRS */
34f80b04 5704 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 5705 msleep(50);
34f80b04 5706 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 5707 msleep(50);
619c5cb6
VZ		 5708 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5709 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 5710
5711 DP(NETIF_MSG_HW, "part2\n");
5712
5713 /* Disable inputs of parser neighbor blocks */
5714 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5715 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5716 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5717 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5718
5719 /* Write 0 to parser credits for CFC search request */
5720 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5721
5722 /* send 10 Ethernet packets */
5723 for (i = 0; i < 10; i++)
5724 bnx2x_lb_pckt(bp);
5725
5726 /* Wait until NIG register shows 10 + 1
5727 packets of size 11*0x10 = 0xb0 */
5728 count = 1000 * factor;
5729 while (count) {
34f80b04 5730
a2fbb9ea
ET		 5731 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5732 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5733 if (val == 0xb0)
5734 break;
5735
5736 msleep(10);
5737 count--;
5738 }
5739 if (val != 0xb0) {
5740 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5741 return -3;
5742 }
5743
5744 /* Wait until PRS register shows 2 packets */
5745 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5746 if (val != 2)
5747 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5748
5749 /* Write 1 to parser credits for CFC search request */
5750 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5751
5752 /* Wait until PRS register shows 3 packets */
5753 msleep(10 * factor);
5754 /* Wait until NIG register shows 1 packet of size 0x10 */
5755 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5756 if (val != 3)
5757 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5758
5759 /* clear NIG EOP FIFO */
5760 for (i = 0; i < 11; i++)
5761 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5762 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5763 if (val != 1) {
5764 BNX2X_ERR("clear of NIG failed\n");
5765 return -4;
5766 }
5767
5768 /* Reset and init BRB, PRS, NIG */
5769 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5770 msleep(50);
5771 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5772 msleep(50);
619c5cb6
VZ		 5773 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5774 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
37b091ba 5775#ifndef BCM_CNIC
a2fbb9ea
ET		 5776 /* set NIC mode */
5777 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5778#endif
5779
5780 /* Enable inputs of parser neighbor blocks */
5781 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5782 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5783 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 5784 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 5785
5786 DP(NETIF_MSG_HW, "done\n");
5787
5788 return 0; /* OK */
5789}
5790
4a33bc03 5791static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 5792{
5793 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 5794 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5795 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5796 else
5797 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 5798 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5799 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 5800 /*
5801 * mask read length error interrupts in brb for parser
5802 * (parsing unit and 'checksum and crc' unit)
5803 * these errors are legal (PU reads fixed length and CAC can cause
5804 * read length error on truncated packets)
5805 */
5806 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 5807 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5808 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5809 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5810 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5811 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 5812/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5813/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5814 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5815 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5816 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 5817/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5818/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5819 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5820 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5821 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5822 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 5823/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5824/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 5825
34f80b04
EG		 5826 if (CHIP_REV_IS_FPGA(bp))
5827 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
619c5cb6 5828 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5829 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5830 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5831 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5832 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5833 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5834 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 5835 else
5836 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 5837 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5838 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5839 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 5840/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 5841
5842 if (!CHIP_IS_E1x(bp))
5843 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5844 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5845
a2fbb9ea
ET		 5846 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5847 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 5848/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 5849 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 5850}
5851
81f75bbf
EG		 5852static void bnx2x_reset_common(struct bnx2x *bp)
5853{
619c5cb6
VZ		 5854 u32 val = 0x1400;
5855
81f75bbf
EG		 5856 /* reset_common */
5857 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5858 0xd3ffff7f);
619c5cb6
VZ		 5859
5860 if (CHIP_IS_E3(bp)) {
5861 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5862 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5863 }
5864
5865 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5866}
5867
5868static void bnx2x_setup_dmae(struct bnx2x *bp)
5869{
5870 bp->dmae_ready = 0;
5871 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 5872}
5873
573f2035
EG		 5874static void bnx2x_init_pxp(struct bnx2x *bp)
5875{
5876 u16 devctl;
5877 int r_order, w_order;
5878
5879 pci_read_config_word(bp->pdev,
b6c2f86e 5880 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 5881 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5882 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5883 if (bp->mrrs == -1)
5884 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5885 else {
5886 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5887 r_order = bp->mrrs;
5888 }
5889
5890 bnx2x_init_pxp_arb(bp, r_order, w_order);
5891}
fd4ef40d
EG		 5892
5893static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5894{
2145a920 5895 int is_required;
fd4ef40d 5896 u32 val;
2145a920 5897 int port;
fd4ef40d 5898
2145a920
VZ		 5899 if (BP_NOMCP(bp))
5900 return;
5901
5902 is_required = 0;
fd4ef40d
EG		 5903 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5904 SHARED_HW_CFG_FAN_FAILURE_MASK;
5905
5906 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5907 is_required = 1;
5908
5909 /*
5910 * The fan failure mechanism is usually related to the PHY type since
5911 * the power consumption of the board is affected by the PHY. Currently,
5912 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5913 */
5914 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5915 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 5916 is_required |=
d90d96ba
YR		 5917 bnx2x_fan_failure_det_req(
5918 bp,
5919 bp->common.shmem_base,
a22f0788 5920 bp->common.shmem2_base,
d90d96ba 5921 port);
fd4ef40d
EG		 5922 }
5923
5924 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5925
5926 if (is_required == 0)
5927 return;
5928
5929 /* Fan failure is indicated by SPIO 5 */
5930 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5931 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5932
5933 /* set to active low mode */
5934 val = REG_RD(bp, MISC_REG_SPIO_INT);
5935 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 5936 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 5937 REG_WR(bp, MISC_REG_SPIO_INT, val);
5938
5939 /* enable interrupt to signal the IGU */
5940 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5941 val |= (1 << MISC_REGISTERS_SPIO_5);
5942 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5943}
5944
f2e0899f
DK		 5945static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5946{
5947 u32 offset = 0;
5948
5949 if (CHIP_IS_E1(bp))
5950 return;
5951 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5952 return;
5953
5954 switch (BP_ABS_FUNC(bp)) {
5955 case 0:
5956 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5957 break;
5958 case 1:
5959 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5960 break;
5961 case 2:
5962 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5963 break;
5964 case 3:
5965 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5966 break;
5967 case 4:
5968 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5969 break;
5970 case 5:
5971 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5972 break;
5973 case 6:
5974 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5975 break;
5976 case 7:
5977 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5978 break;
5979 default:
5980 return;
5981 }
5982
5983 REG_WR(bp, offset, pretend_func_num);
5984 REG_RD(bp, offset);
5985 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5986}
5987
c9ee9206 5988void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 5989{
5990 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5991 val &= ~IGU_PF_CONF_FUNC_EN;
5992
5993 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5994 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5995 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5996}
5997
619c5cb6
VZ		 5998static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5999{
6000 u32 shmem_base[2], shmem2_base[2];
6001 shmem_base[0] = bp->common.shmem_base;
6002 shmem2_base[0] = bp->common.shmem2_base;
6003 if (!CHIP_IS_E1x(bp)) {
6004 shmem_base[1] =
6005 SHMEM2_RD(bp, other_shmem_base_addr);
6006 shmem2_base[1] =
6007 SHMEM2_RD(bp, other_shmem2_base_addr);
6008 }
6009 bnx2x_acquire_phy_lock(bp);
6010 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6011 bp->common.chip_id);
6012 bnx2x_release_phy_lock(bp);
6013}
6014
6015/**
6016 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6017 *
6018 * @bp: driver handle
6019 */
6020static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6021{
619c5cb6 6022 u32 val;
a2fbb9ea 6023
f2e0899f 6024 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6025
2031bd3a
DK		 6026 /*
6027 * take the UNDI lock to protect undi_unload flow from accessing
6028 * registers while we're resetting the chip
6029 */
7a06a122 6030 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6031
81f75bbf 6032 bnx2x_reset_common(bp);
34f80b04 6033 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6034
619c5cb6
VZ		 6035 val = 0xfffc;
6036 if (CHIP_IS_E3(bp)) {
6037 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6038 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6039 }
6040 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6041
7a06a122 6042 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6043
619c5cb6 6044 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6045
619c5cb6
VZ		 6046 if (!CHIP_IS_E1x(bp)) {
6047 u8 abs_func_id;
f2e0899f
DK		 6048
6049 /**
6050 * 4-port mode or 2-port mode we need to turn of master-enable
6051 * for everyone, after that, turn it back on for self.
6052 * so, we disregard multi-function or not, and always disable
6053 * for all functions on the given path, this means 0,2,4,6 for
6054 * path 0 and 1,3,5,7 for path 1
6055 */
619c5cb6
VZ		 6056 for (abs_func_id = BP_PATH(bp);
6057 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6058 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6059 REG_WR(bp,
6060 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6061 1);
6062 continue;
6063 }
6064
619c5cb6 6065 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6066 /* clear pf enable */
6067 bnx2x_pf_disable(bp);
6068 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6069 }
6070 }
a2fbb9ea 6071
619c5cb6 6072 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6073 if (CHIP_IS_E1(bp)) {
6074 /* enable HW interrupt from PXP on USDM overflow
6075 bit 16 on INT_MASK_0 */
6076 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6077 }
a2fbb9ea 6078
619c5cb6 6079 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6080 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 6081
6082#ifdef __BIG_ENDIAN
34f80b04
EG		 6083 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6084 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6085 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6086 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6087 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 6088 /* make sure this value is 0 */
6089 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 6090
6091/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6092 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6093 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6094 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6095 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 6096#endif
6097
523224a3
DK		 6098 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6099
34f80b04
EG		 6100 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6101 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6102
34f80b04
EG		 6103 /* let the HW do it's magic ... */
6104 msleep(100);
6105 /* finish PXP init */
6106 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6107 if (val != 1) {
6108 BNX2X_ERR("PXP2 CFG failed\n");
6109 return -EBUSY;
6110 }
6111 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6112 if (val != 1) {
6113 BNX2X_ERR("PXP2 RD_INIT failed\n");
6114 return -EBUSY;
6115 }
a2fbb9ea 6116
f2e0899f
DK		 6117 /* Timers bug workaround E2 only. We need to set the entire ILT to
6118 * have entries with value "0" and valid bit on.
6119 * This needs to be done by the first PF that is loaded in a path
6120 * (i.e. common phase)
6121 */
619c5cb6
VZ		 6122 if (!CHIP_IS_E1x(bp)) {
6123/* In E2 there is a bug in the timers block that can cause function 6 / 7
6124 * (i.e. vnic3) to start even if it is marked as "scan-off".
6125 * This occurs when a different function (func2,3) is being marked
6126 * as "scan-off". Real-life scenario for example: if a driver is being
6127 * load-unloaded while func6,7 are down. This will cause the timer to access
6128 * the ilt, translate to a logical address and send a request to read/write.
6129 * Since the ilt for the function that is down is not valid, this will cause
6130 * a translation error which is unrecoverable.
6131 * The Workaround is intended to make sure that when this happens nothing fatal
6132 * will occur. The workaround:
6133 * 1. First PF driver which loads on a path will:
6134 * a. After taking the chip out of reset, by using pretend,
6135 * it will write "0" to the following registers of
6136 * the other vnics.
6137 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6138 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6139 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6140 * And for itself it will write '1' to
6141 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6142 * dmae-operations (writing to pram for example.)
6143 * note: can be done for only function 6,7 but cleaner this
6144 * way.
6145 * b. Write zero+valid to the entire ILT.
6146 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6147 * VNIC3 (of that port). The range allocated will be the
6148 * entire ILT. This is needed to prevent ILT range error.
6149 * 2. Any PF driver load flow:
6150 * a. ILT update with the physical addresses of the allocated
6151 * logical pages.
6152 * b. Wait 20msec. - note that this timeout is needed to make
6153 * sure there are no requests in one of the PXP internal
6154 * queues with "old" ILT addresses.
6155 * c. PF enable in the PGLC.
6156 * d. Clear the was_error of the PF in the PGLC. (could have
6157 * occured while driver was down)
6158 * e. PF enable in the CFC (WEAK + STRONG)
6159 * f. Timers scan enable
6160 * 3. PF driver unload flow:
6161 * a. Clear the Timers scan_en.
6162 * b. Polling for scan_on=0 for that PF.
6163 * c. Clear the PF enable bit in the PXP.
6164 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6165 * e. Write zero+valid to all ILT entries (The valid bit must
6166 * stay set)
6167 * f. If this is VNIC 3 of a port then also init
6168 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6169 * to the last enrty in the ILT.
6170 *
6171 * Notes:
6172 * Currently the PF error in the PGLC is non recoverable.
6173 * In the future the there will be a recovery routine for this error.
6174 * Currently attention is masked.
6175 * Having an MCP lock on the load/unload process does not guarantee that
6176 * there is no Timer disable during Func6/7 enable. This is because the
6177 * Timers scan is currently being cleared by the MCP on FLR.
6178 * Step 2.d can be done only for PF6/7 and the driver can also check if
6179 * there is error before clearing it. But the flow above is simpler and
6180 * more general.
6181 * All ILT entries are written by zero+valid and not just PF6/7
6182 * ILT entries since in the future the ILT entries allocation for
6183 * PF-s might be dynamic.
6184 */
f2e0899f
DK		 6185 struct ilt_client_info ilt_cli;
6186 struct bnx2x_ilt ilt;
6187 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6188 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6189
b595076a 6190 /* initialize dummy TM client */
f2e0899f
DK		 6191 ilt_cli.start = 0;
6192 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6193 ilt_cli.client_num = ILT_CLIENT_TM;
6194
6195 /* Step 1: set zeroes to all ilt page entries with valid bit on
6196 * Step 2: set the timers first/last ilt entry to point
6197 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 6198 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 6199 *
6200 * both steps performed by call to bnx2x_ilt_client_init_op()
6201 * with dummy TM client
6202 *
6203 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6204 * and his brother are split registers
6205 */
6206 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6207 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6208 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6209
6210 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6211 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6212 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6213 }
6214
6215
34f80b04
EG		 6216 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6217 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 6218
619c5cb6 6219 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6220 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6221 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 6222 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 6223
619c5cb6 6224 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 6225
6226 /* let the HW do it's magic ... */
6227 do {
6228 msleep(200);
6229 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6230 } while (factor-- && (val != 1));
6231
6232 if (val != 1) {
6233 BNX2X_ERR("ATC_INIT failed\n");
6234 return -EBUSY;
6235 }
6236 }
6237
619c5cb6 6238 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 6239
34f80b04
EG		 6240 /* clean the DMAE memory */
6241 bp->dmae_ready = 1;
619c5cb6
VZ		 6242 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6243
6244 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6245
6246 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6247
6248 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6249
619c5cb6 6250 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6251
34f80b04
EG		 6252 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6253 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6254 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6255 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6256
619c5cb6 6257 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6258
f85582f8 6259
523224a3
DK		 6260 /* QM queues pointers table */
6261 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6262
34f80b04
EG		 6263 /* soft reset pulse */
6264 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6265 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 6266
37b091ba 6267#ifdef BCM_CNIC
619c5cb6 6268 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 6269#endif
a2fbb9ea 6270
619c5cb6 6271 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 6272 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 6273 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 6274 /* enable hw interrupt from doorbell Q */
6275 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 6276
619c5cb6 6277 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 6278
619c5cb6 6279 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 6280 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 6281
f2e0899f 6282 if (!CHIP_IS_E1(bp))
619c5cb6 6283 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 6284
619c5cb6
VZ		 6285 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6286 /* Bit-map indicating which L2 hdrs may appear
6287 * after the basic Ethernet header
6288 */
6289 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6290 bp->path_has_ovlan ? 7 : 6);
a2fbb9ea 6291
619c5cb6
VZ		 6292 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6293 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6294 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6295 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 6296
619c5cb6
VZ		 6297 if (!CHIP_IS_E1x(bp)) {
6298 /* reset VFC memories */
6299 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6300 VFC_MEMORIES_RST_REG_CAM_RST |
6301 VFC_MEMORIES_RST_REG_RAM_RST);
6302 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6303 VFC_MEMORIES_RST_REG_CAM_RST |
6304 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 6305
619c5cb6
VZ		 6306 msleep(20);
6307 }
a2fbb9ea 6308
619c5cb6
VZ		 6309 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6310 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6311 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6312 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 6313
34f80b04
EG		 6314 /* sync semi rtc */
6315 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6316 0x80000000);
6317 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6318 0x80000000);
a2fbb9ea 6319
619c5cb6
VZ		 6320 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6321 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6322 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 6323
619c5cb6
VZ		 6324 if (!CHIP_IS_E1x(bp))
6325 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6326 bp->path_has_ovlan ? 7 : 6);
f2e0899f 6327
34f80b04 6328 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 6329
619c5cb6
VZ		 6330 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6331
37b091ba
MC		 6332#ifdef BCM_CNIC
6333 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6334 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6335 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6336 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6337 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6338 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6339 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6340 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6341 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6342 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6343#endif
34f80b04 6344 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 6345
34f80b04
EG		 6346 if (sizeof(union cdu_context) != 1024)
6347 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 6348 dev_alert(&bp->pdev->dev, "please adjust the size "
6349 "of cdu_context(%ld)\n",
7995c64e 6350 (long)sizeof(union cdu_context));
a2fbb9ea 6351
619c5cb6 6352 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 6353 val = (4 << 24) + (0 << 12) + 1024;
6354 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 6355
619c5cb6 6356 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 6357 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 6358 /* enable context validation interrupt from CFC */
6359 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6360
6361 /* set the thresholds to prevent CFC/CDU race */
6362 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 6363
619c5cb6 6364 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 6365
619c5cb6 6366 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 6367 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6368
619c5cb6
VZ		 6369 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6370 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 6371
34f80b04
EG		 6372 /* Reset PCIE errors for debug */
6373 REG_WR(bp, 0x2814, 0xffffffff);
6374 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 6375
619c5cb6 6376 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6377 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6378 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6379 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6380 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6381 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6382 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6383 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6384 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6385 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6386 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6387 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6388 }
6389
619c5cb6 6390 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 6391 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 6392 /* in E3 this done in per-port section */
6393 if (!CHIP_IS_E3(bp))
6394 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 6395 }
619c5cb6
VZ		 6396 if (CHIP_IS_E1H(bp))
6397 /* not applicable for E2 (and above ...) */
6398 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 6399
6400 if (CHIP_REV_IS_SLOW(bp))
6401 msleep(200);
6402
6403 /* finish CFC init */
6404 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6405 if (val != 1) {
6406 BNX2X_ERR("CFC LL_INIT failed\n");
6407 return -EBUSY;
6408 }
6409 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6410 if (val != 1) {
6411 BNX2X_ERR("CFC AC_INIT failed\n");
6412 return -EBUSY;
6413 }
6414 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6415 if (val != 1) {
6416 BNX2X_ERR("CFC CAM_INIT failed\n");
6417 return -EBUSY;
6418 }
6419 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 6420
f2e0899f
DK		 6421 if (CHIP_IS_E1(bp)) {
6422 /* read NIG statistic
6423 to see if this is our first up since powerup */
6424 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6425 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 6426
f2e0899f
DK		 6427 /* do internal memory self test */
6428 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6429 BNX2X_ERR("internal mem self test failed\n");
6430 return -EBUSY;
6431 }
34f80b04
EG		 6432 }
6433
fd4ef40d
EG		 6434 bnx2x_setup_fan_failure_detection(bp);
6435
34f80b04
EG		 6436 /* clear PXP2 attentions */
6437 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 6438
4a33bc03 6439 bnx2x_enable_blocks_attention(bp);
c9ee9206 6440 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 6441
6bbca910 6442 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 6443 if (CHIP_IS_E1x(bp))
6444 bnx2x__common_init_phy(bp);
6bbca910
YR		 6445 } else
6446 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6447
34f80b04
EG		 6448 return 0;
6449}
a2fbb9ea 6450
619c5cb6
VZ		 6451/**
6452 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6453 *
6454 * @bp: driver handle
6455 */
6456static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6457{
6458 int rc = bnx2x_init_hw_common(bp);
6459
6460 if (rc)
6461 return rc;
6462
6463 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6464 if (!BP_NOMCP(bp))
6465 bnx2x__common_init_phy(bp);
6466
6467 return 0;
6468}
6469
523224a3 6470static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 6471{
6472 int port = BP_PORT(bp);
619c5cb6 6473 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 6474 u32 low, high;
34f80b04 6475 u32 val;
a2fbb9ea 6476
619c5cb6
VZ		 6477 bnx2x__link_reset(bp);
6478
cdaa7cb8 6479 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 6480
6481 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 6482
619c5cb6
VZ		 6483 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6484 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6485 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 6486
f2e0899f
DK		 6487 /* Timers bug workaround: disables the pf_master bit in pglue at
6488 * common phase, we need to enable it here before any dmae access are
6489 * attempted. Therefore we manually added the enable-master to the
6490 * port phase (it also happens in the function phase)
6491 */
619c5cb6 6492 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6493 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6494
619c5cb6
VZ		 6495 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6496 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6497 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6498 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6499
6500 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6501 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6502 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6503 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 6504
523224a3
DK		 6505 /* QM cid (connection) count */
6506 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 6507
523224a3 6508#ifdef BCM_CNIC
619c5cb6 6509 bnx2x_init_block(bp, BLOCK_TM, init_phase);
37b091ba
MC		 6510 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6511 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 6512#endif
cdaa7cb8 6513
619c5cb6 6514 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f
DK		 6515
6516 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 6517 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6518
6519 if (IS_MF(bp))
6520 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6521 else if (bp->dev->mtu > 4096) {
6522 if (bp->flags & ONE_PORT_FLAG)
6523 low = 160;
6524 else {
6525 val = bp->dev->mtu;
6526 /* (24*1024 + val*4)/256 */
6527 low = 96 + (val/64) +
6528 ((val % 64) ? 1 : 0);
6529 }
6530 } else
6531 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6532 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 6533 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6534 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 6535 }
1c06328c 6536
619c5cb6
VZ		 6537 if (CHIP_MODE_IS_4_PORT(bp))
6538 REG_WR(bp, (BP_PORT(bp) ?
6539 BRB1_REG_MAC_GUARANTIED_1 :
6540 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 6541
ca00392c 6542
619c5cb6
VZ		 6543 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6544 if (CHIP_IS_E3B0(bp))
6545 /* Ovlan exists only if we are in multi-function +
6546 * switch-dependent mode, in switch-independent there
6547 * is no ovlan headers
6548 */
6549 REG_WR(bp, BP_PORT(bp) ?
6550 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6551 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6552 (bp->path_has_ovlan ? 7 : 6));
356e2385 6553
619c5cb6
VZ		 6554 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6555 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6556 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6557 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 6558
619c5cb6
VZ		 6559 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6560 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6561 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6562 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 6563
619c5cb6
VZ		 6564 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6565 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 6566
619c5cb6
VZ		 6567 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6568
6569 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6570 /* configure PBF to work without PAUSE mtu 9000 */
6571 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 6572
f2e0899f
DK		 6573 /* update threshold */
6574 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6575 /* update init credit */
6576 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 6577
f2e0899f
DK		 6578 /* probe changes */
6579 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6580 udelay(50);
6581 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6582 }
a2fbb9ea 6583
37b091ba 6584#ifdef BCM_CNIC
619c5cb6 6585 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
a2fbb9ea 6586#endif
619c5cb6
VZ		 6587 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6588 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 6589
6590 if (CHIP_IS_E1(bp)) {
6591 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6592 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6593 }
619c5cb6 6594 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 6595
619c5cb6 6596 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6597
619c5cb6 6598 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 6599 /* init aeu_mask_attn_func_0/1:
6600 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6601 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6602 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 6603 val = IS_MF(bp) ? 0xF7 : 0x7;
6604 /* Enable DCBX attention for all but E1 */
6605 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6606 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 6607
619c5cb6
VZ		 6608 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6609
6610 if (!CHIP_IS_E1x(bp)) {
6611 /* Bit-map indicating which L2 hdrs may appear after the
6612 * basic Ethernet header
6613 */
6614 REG_WR(bp, BP_PORT(bp) ?
6615 NIG_REG_P1_HDRS_AFTER_BASIC :
6616 NIG_REG_P0_HDRS_AFTER_BASIC,
6617 IS_MF_SD(bp) ? 7 : 6);
6618
6619 if (CHIP_IS_E3(bp))
6620 REG_WR(bp, BP_PORT(bp) ?
6621 NIG_REG_LLH1_MF_MODE :
6622 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6623 }
6624 if (!CHIP_IS_E3(bp))
6625 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 6626
f2e0899f 6627 if (!CHIP_IS_E1(bp)) {
fb3bff17 6628 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 6629 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 6630 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 6631
619c5cb6 6632 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6633 val = 0;
6634 switch (bp->mf_mode) {
6635 case MULTI_FUNCTION_SD:
6636 val = 1;
6637 break;
6638 case MULTI_FUNCTION_SI:
6639 val = 2;
6640 break;
6641 }
6642
6643 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6644 NIG_REG_LLH0_CLS_TYPE), val);
6645 }
1c06328c
EG		 6646 {
6647 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6648 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6649 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6650 }
34f80b04
EG		 6651 }
6652
619c5cb6
VZ		 6653
6654 /* If SPIO5 is set to generate interrupts, enable it for this port */
6655 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6656 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
4d295db0
EG		 6657 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6658 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6659 val = REG_RD(bp, reg_addr);
f1410647 6660 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 6661 REG_WR(bp, reg_addr, val);
f1410647 6662 }
a2fbb9ea 6663
34f80b04
EG		 6664 return 0;
6665}
6666
34f80b04
EG		 6667static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6668{
6669 int reg;
6670
f2e0899f 6671 if (CHIP_IS_E1(bp))
34f80b04 6672 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 6673 else
6674 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 6675
6676 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6677}
6678
f2e0899f
DK		 6679static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6680{
619c5cb6 6681 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 6682}
6683
6684static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6685{
6686 u32 i, base = FUNC_ILT_BASE(func);
6687 for (i = base; i < base + ILT_PER_FUNC; i++)
6688 bnx2x_ilt_wr(bp, i, 0);
6689}
6690
523224a3 6691static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 6692{
6693 int port = BP_PORT(bp);
6694 int func = BP_FUNC(bp);
619c5cb6 6695 int init_phase = PHASE_PF0 + func;
523224a3
DK		 6696 struct bnx2x_ilt *ilt = BP_ILT(bp);
6697 u16 cdu_ilt_start;
8badd27a 6698 u32 addr, val;
f4a66897
VZ		 6699 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6700 int i, main_mem_width;
34f80b04 6701
cdaa7cb8 6702 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 6703
619c5cb6
VZ		 6704 /* FLR cleanup - hmmm */
6705 if (!CHIP_IS_E1x(bp))
6706 bnx2x_pf_flr_clnup(bp);
6707
8badd27a 6708 /* set MSI reconfigure capability */
f2e0899f
DK		 6709 if (bp->common.int_block == INT_BLOCK_HC) {
6710 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6711 val = REG_RD(bp, addr);
6712 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6713 REG_WR(bp, addr, val);
6714 }
8badd27a 6715
619c5cb6
VZ		 6716 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6717 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6718
523224a3
DK		 6719 ilt = BP_ILT(bp);
6720 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 6721
523224a3
DK		 6722 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6723 ilt->lines[cdu_ilt_start + i].page =
6724 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6725 ilt->lines[cdu_ilt_start + i].page_mapping =
6726 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6727 /* cdu ilt pages are allocated manually so there's no need to
6728 set the size */
37b091ba 6729 }
523224a3 6730 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 6731
523224a3
DK		 6732#ifdef BCM_CNIC
6733 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 6734
523224a3
DK		 6735 /* T1 hash bits value determines the T1 number of entries */
6736 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6737#endif
37b091ba 6738
523224a3
DK		 6739#ifndef BCM_CNIC
6740 /* set NIC mode */
6741 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6742#endif /* BCM_CNIC */
37b091ba 6743
619c5cb6 6744 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6745 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6746
6747 /* Turn on a single ISR mode in IGU if driver is going to use
6748 * INT#x or MSI
6749 */
6750 if (!(bp->flags & USING_MSIX_FLAG))
6751 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6752 /*
6753 * Timers workaround bug: function init part.
6754 * Need to wait 20msec after initializing ILT,
6755 * needed to make sure there are no requests in
6756 * one of the PXP internal queues with "old" ILT addresses
6757 */
6758 msleep(20);
6759 /*
6760 * Master enable - Due to WB DMAE writes performed before this
6761 * register is re-initialized as part of the regular function
6762 * init
6763 */
6764 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6765 /* Enable the function in IGU */
6766 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6767 }
6768
523224a3 6769 bp->dmae_ready = 1;
34f80b04 6770
619c5cb6 6771 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 6772
619c5cb6 6773 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6774 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6775
619c5cb6
VZ		 6776 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6777 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6778 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6779 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6780 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6781 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6782 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6783 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6784 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6785 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6786 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6787 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6788 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6789
6790 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6791 REG_WR(bp, QM_REG_PF_EN, 1);
6792
619c5cb6
VZ		 6793 if (!CHIP_IS_E1x(bp)) {
6794 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6795 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6796 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6797 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6798 }
6799 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6800
6801 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6802 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6803 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6804 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6805 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6806 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6807 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6808 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6809 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6810 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6811 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6812 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6813 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6814
619c5cb6 6815 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 6816
619c5cb6 6817 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 6818
619c5cb6 6819 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6820 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6821
fb3bff17 6822 if (IS_MF(bp)) {
34f80b04 6823 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 6824 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 6825 }
6826
619c5cb6 6827 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 6828
34f80b04 6829 /* HC init per function */
f2e0899f
DK		 6830 if (bp->common.int_block == INT_BLOCK_HC) {
6831 if (CHIP_IS_E1H(bp)) {
6832 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6833
6834 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6835 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6836 }
619c5cb6 6837 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 6838
6839 } else {
6840 int num_segs, sb_idx, prod_offset;
6841
34f80b04
EG		 6842 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6843
619c5cb6 6844 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6845 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6846 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6847 }
6848
619c5cb6 6849 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6850
619c5cb6 6851 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6852 int dsb_idx = 0;
6853 /**
6854 * Producer memory:
6855 * E2 mode: address 0-135 match to the mapping memory;
6856 * 136 - PF0 default prod; 137 - PF1 default prod;
6857 * 138 - PF2 default prod; 139 - PF3 default prod;
6858 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6859 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6860 * 144-147 reserved.
6861 *
6862 * E1.5 mode - In backward compatible mode;
6863 * for non default SB; each even line in the memory
6864 * holds the U producer and each odd line hold
6865 * the C producer. The first 128 producers are for
6866 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6867 * producers are for the DSB for each PF.
6868 * Each PF has five segments: (the order inside each
6869 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6870 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6871 * 144-147 attn prods;
6872 */
6873 /* non-default-status-blocks */
6874 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6875 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6876 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6877 prod_offset = (bp->igu_base_sb + sb_idx) *
6878 num_segs;
6879
6880 for (i = 0; i < num_segs; i++) {
6881 addr = IGU_REG_PROD_CONS_MEMORY +
6882 (prod_offset + i) * 4;
6883 REG_WR(bp, addr, 0);
6884 }
6885 /* send consumer update with value 0 */
6886 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6887 USTORM_ID, 0, IGU_INT_NOP, 1);
6888 bnx2x_igu_clear_sb(bp,
6889 bp->igu_base_sb + sb_idx);
6890 }
6891
6892 /* default-status-blocks */
6893 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6894 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6895
6896 if (CHIP_MODE_IS_4_PORT(bp))
6897 dsb_idx = BP_FUNC(bp);
6898 else
3395a033 6899 dsb_idx = BP_VN(bp);
f2e0899f
DK		 6900
6901 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6902 IGU_BC_BASE_DSB_PROD + dsb_idx :
6903 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6904
3395a033
DK		 6905 /*
6906 * igu prods come in chunks of E1HVN_MAX (4) -
6907 * does not matters what is the current chip mode
6908 */
f2e0899f
DK		 6909 for (i = 0; i < (num_segs * E1HVN_MAX);
6910 i += E1HVN_MAX) {
6911 addr = IGU_REG_PROD_CONS_MEMORY +
6912 (prod_offset + i)*4;
6913 REG_WR(bp, addr, 0);
6914 }
6915 /* send consumer update with 0 */
6916 if (CHIP_INT_MODE_IS_BC(bp)) {
6917 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6918 USTORM_ID, 0, IGU_INT_NOP, 1);
6919 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6920 CSTORM_ID, 0, IGU_INT_NOP, 1);
6921 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6922 XSTORM_ID, 0, IGU_INT_NOP, 1);
6923 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6924 TSTORM_ID, 0, IGU_INT_NOP, 1);
6925 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6926 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6927 } else {
6928 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6929 USTORM_ID, 0, IGU_INT_NOP, 1);
6930 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6931 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6932 }
6933 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6934
6935 /* !!! these should become driver const once
6936 rf-tool supports split-68 const */
6937 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6938 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6939 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6940 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6941 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6942 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6943 }
34f80b04 6944 }
34f80b04 6945
c14423fe 6946 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 6947 REG_WR(bp, 0x2114, 0xffffffff);
6948 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 6949
f4a66897
VZ		 6950 if (CHIP_IS_E1x(bp)) {
6951 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6952 main_mem_base = HC_REG_MAIN_MEMORY +
6953 BP_PORT(bp) * (main_mem_size * 4);
6954 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6955 main_mem_width = 8;
6956
6957 val = REG_RD(bp, main_mem_prty_clr);
6958 if (val)
6959 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6960 "block during "
6961 "function init (0x%x)!\n", val);
6962
6963 /* Clear "false" parity errors in MSI-X table */
6964 for (i = main_mem_base;
6965 i < main_mem_base + main_mem_size * 4;
6966 i += main_mem_width) {
6967 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6968 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6969 i, main_mem_width / 4);
6970 }
6971 /* Clear HC parity attention */
6972 REG_RD(bp, main_mem_prty_clr);
6973 }
6974
619c5cb6
VZ		 6975#ifdef BNX2X_STOP_ON_ERROR
6976 /* Enable STORMs SP logging */
6977 REG_WR8(bp, BAR_USTRORM_INTMEM +
6978 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6979 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6980 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6981 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6982 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6983 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6984 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6985#endif
6986
b7737c9b 6987 bnx2x_phy_probe(&bp->link_params);
f85582f8 6988
34f80b04
EG		 6989 return 0;
6990}
6991
a2fbb9ea 6992
9f6c9258 6993void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 6994{
a2fbb9ea 6995 /* fastpath */
b3b83c3f 6996 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 6997 /* end of fastpath */
6998
6999 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 7000 sizeof(struct host_sp_status_block));
a2fbb9ea 7001
619c5cb6
VZ		 7002 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7003 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7004
a2fbb9ea 7005 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 7006 sizeof(struct bnx2x_slowpath));
a2fbb9ea 7007
523224a3
DK		 7008 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
7009 bp->context.size);
7010
7011 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7012
7013 BNX2X_FREE(bp->ilt->lines);
f85582f8 7014
37b091ba 7015#ifdef BCM_CNIC
619c5cb6 7016 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7017 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7018 sizeof(struct host_hc_status_block_e2));
7019 else
7020 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7021 sizeof(struct host_hc_status_block_e1x));
f85582f8 7022
523224a3 7023 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 7024#endif
f85582f8 7025
7a9b2557 7026 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 7027
523224a3
DK		 7028 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7029 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 7030}
7031
7032static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7033{
7034 int num_groups;
50f0a562 7035 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
619c5cb6 7036
50f0a562
BW		 7037 /* number of queues for statistics is number of eth queues + FCoE */
7038 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
619c5cb6
VZ		 7039
7040 /* Total number of FW statistics requests =
50f0a562
BW		 7041 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7042 * num of queues
7043 */
7044 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
523224a3 7045
619c5cb6
VZ		 7046
7047 /* Request is built from stats_query_header and an array of
7048 * stats_query_cmd_group each of which contains
7049 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7050 * configured in the stats_query_header.
7051 */
50f0a562
BW		 7052 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7053 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
619c5cb6
VZ		 7054
7055 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7056 num_groups * sizeof(struct stats_query_cmd_group);
7057
7058 /* Data for statistics requests + stats_conter
7059 *
7060 * stats_counter holds per-STORM counters that are incremented
7061 * when STORM has finished with the current request.
50f0a562
BW		 7062 *
7063 * memory for FCoE offloaded statistics are counted anyway,
7064 * even if they will not be sent.
619c5cb6
VZ		 7065 */
7066 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7067 sizeof(struct per_pf_stats) +
50f0a562 7068 sizeof(struct fcoe_statistics_params) +
619c5cb6
VZ		 7069 sizeof(struct per_queue_stats) * num_queue_stats +
7070 sizeof(struct stats_counter);
7071
7072 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7073 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7074
7075 /* Set shortcuts */
7076 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7077 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7078
7079 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7080 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7081
7082 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7083 bp->fw_stats_req_sz;
7084 return 0;
7085
7086alloc_mem_err:
7087 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7088 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7089 return -ENOMEM;
a2fbb9ea
ET		 7090}
7091
f2e0899f 7092
9f6c9258 7093int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 7094{
523224a3 7095#ifdef BCM_CNIC
619c5cb6
VZ		 7096 if (!CHIP_IS_E1x(bp))
7097 /* size = the status block + ramrod buffers */
f2e0899f
DK		 7098 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7099 sizeof(struct host_hc_status_block_e2));
7100 else
7101 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
7102 sizeof(struct host_hc_status_block_e1x));
8badd27a 7103
523224a3
DK		 7104 /* allocate searcher T2 table */
7105 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7106#endif
a2fbb9ea 7107
8badd27a 7108
523224a3
DK		 7109 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7110 sizeof(struct host_sp_status_block));
a2fbb9ea 7111
523224a3
DK		 7112 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7113 sizeof(struct bnx2x_slowpath));
a2fbb9ea 7114
619c5cb6
VZ		 7115 /* Allocated memory for FW statistics */
7116 if (bnx2x_alloc_fw_stats_mem(bp))
7117 goto alloc_mem_err;
7118
6383c0b3 7119 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
f85582f8 7120
523224a3
DK		 7121 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
7122 bp->context.size);
65abd74d 7123
523224a3 7124 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 7125
523224a3
DK		 7126 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7127 goto alloc_mem_err;
65abd74d 7128
9f6c9258
DK		 7129 /* Slow path ring */
7130 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 7131
523224a3
DK		 7132 /* EQ */
7133 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7134 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 7135
b3b83c3f
DK		 7136
7137 /* fastpath */
7138 /* need to be done at the end, since it's self adjusting to amount
7139 * of memory available for RSS queues
7140 */
7141 if (bnx2x_alloc_fp_mem(bp))
7142 goto alloc_mem_err;
9f6c9258 7143 return 0;
e1510706 7144
9f6c9258
DK		 7145alloc_mem_err:
7146 bnx2x_free_mem(bp);
7147 return -ENOMEM;
65abd74d
YG		 7148}
7149
a2fbb9ea
ET		 7150/*
7151 * Init service functions
7152 */
a2fbb9ea 7153
619c5cb6
VZ		 7154int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7155 struct bnx2x_vlan_mac_obj *obj, bool set,
7156 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 7157{
619c5cb6
VZ		 7158 int rc;
7159 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 7160
619c5cb6 7161 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 7162
619c5cb6
VZ		 7163 /* Fill general parameters */
7164 ramrod_param.vlan_mac_obj = obj;
7165 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 7166
619c5cb6
VZ		 7167 /* Fill a user request section if needed */
7168 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7169 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 7170
619c5cb6 7171 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 7172
619c5cb6
VZ		 7173 /* Set the command: ADD or DEL */
7174 if (set)
7175 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7176 else
7177 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 7178 }
7179
619c5cb6
VZ		 7180 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7181 if (rc < 0)
7182 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7183 return rc;
a2fbb9ea
ET		 7184}
7185
619c5cb6
VZ		 7186int bnx2x_del_all_macs(struct bnx2x *bp,
7187 struct bnx2x_vlan_mac_obj *mac_obj,
7188 int mac_type, bool wait_for_comp)
e665bfda 7189{
619c5cb6
VZ		 7190 int rc;
7191 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 7192
619c5cb6
VZ		 7193 /* Wait for completion of requested */
7194 if (wait_for_comp)
7195 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 7196
619c5cb6
VZ		 7197 /* Set the mac type of addresses we want to clear */
7198 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 7199
619c5cb6
VZ		 7200 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7201 if (rc < 0)
7202 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 7203
619c5cb6 7204 return rc;
0793f83f
DK		 7205}
7206
619c5cb6 7207int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 7208{
619c5cb6 7209 unsigned long ramrod_flags = 0;
e665bfda 7210
614c76df
DK		 7211#ifdef BCM_CNIC
7212 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) {
7213 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n");
7214 return 0;
7215 }
7216#endif
7217
619c5cb6 7218 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 7219
619c5cb6
VZ		 7220 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7221 /* Eth MAC is set on RSS leading client (fp[0]) */
7222 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7223 BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 7224}
6e30dd4e 7225
619c5cb6 7226int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 7227{
619c5cb6 7228 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 7229}
a2fbb9ea 7230
d6214d7a 7231/**
e8920674 7232 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 7233 *
e8920674 7234 * @bp: driver handle
d6214d7a 7235 *
e8920674 7236 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 7237 */
9ee3d37b 7238static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 7239{
9ee3d37b 7240 switch (int_mode) {
d6214d7a
DK		 7241 case INT_MODE_MSI:
7242 bnx2x_enable_msi(bp);
7243 /* falling through... */
7244 case INT_MODE_INTx:
6383c0b3 7245 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7246 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 7247 break;
d6214d7a
DK		 7248 default:
7249 /* Set number of queues according to bp->multi_mode value */
7250 bnx2x_set_num_queues(bp);
ca00392c 7251
d6214d7a
DK		 7252 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7253 bp->num_queues);
ca00392c 7254
d6214d7a
DK		 7255 /* if we can't use MSI-X we only need one fp,
7256 * so try to enable MSI-X with the requested number of fp's
7257 * and fallback to MSI or legacy INTx with one fp
7258 */
9ee3d37b 7259 if (bnx2x_enable_msix(bp)) {
d6214d7a
DK		 7260 /* failed to enable MSI-X */
7261 if (bp->multi_mode)
7262 DP(NETIF_MSG_IFUP,
7263 "Multi requested but failed to "
7264 "enable MSI-X (%d), "
7265 "set number of queues to %d\n",
7266 bp->num_queues,
6383c0b3
AE		 7267 1 + NON_ETH_CONTEXT_USE);
7268 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7269
9ee3d37b 7270 /* Try to enable MSI */
d6214d7a
DK		 7271 if (!(bp->flags & DISABLE_MSI_FLAG))
7272 bnx2x_enable_msi(bp);
7273 }
9f6c9258
DK		 7274 break;
7275 }
a2fbb9ea
ET		 7276}
7277
c2bff63f
DK		 7278/* must be called prioir to any HW initializations */
7279static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7280{
7281 return L2_ILT_LINES(bp);
7282}
7283
523224a3
DK		 7284void bnx2x_ilt_set_info(struct bnx2x *bp)
7285{
7286 struct ilt_client_info *ilt_client;
7287 struct bnx2x_ilt *ilt = BP_ILT(bp);
7288 u16 line = 0;
7289
7290 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7291 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7292
7293 /* CDU */
7294 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7295 ilt_client->client_num = ILT_CLIENT_CDU;
7296 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7297 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7298 ilt_client->start = line;
619c5cb6 7299 line += bnx2x_cid_ilt_lines(bp);
523224a3
DK		 7300#ifdef BCM_CNIC
7301 line += CNIC_ILT_LINES;
7302#endif
7303 ilt_client->end = line - 1;
7304
7305 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7306 "flags 0x%x, hw psz %d\n",
7307 ilt_client->start,
7308 ilt_client->end,
7309 ilt_client->page_size,
7310 ilt_client->flags,
7311 ilog2(ilt_client->page_size >> 12));
7312
7313 /* QM */
7314 if (QM_INIT(bp->qm_cid_count)) {
7315 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7316 ilt_client->client_num = ILT_CLIENT_QM;
7317 ilt_client->page_size = QM_ILT_PAGE_SZ;
7318 ilt_client->flags = 0;
7319 ilt_client->start = line;
7320
7321 /* 4 bytes for each cid */
7322 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7323 QM_ILT_PAGE_SZ);
7324
7325 ilt_client->end = line - 1;
7326
7327 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7328 "flags 0x%x, hw psz %d\n",
7329 ilt_client->start,
7330 ilt_client->end,
7331 ilt_client->page_size,
7332 ilt_client->flags,
7333 ilog2(ilt_client->page_size >> 12));
7334
7335 }
7336 /* SRC */
7337 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7338#ifdef BCM_CNIC
7339 ilt_client->client_num = ILT_CLIENT_SRC;
7340 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7341 ilt_client->flags = 0;
7342 ilt_client->start = line;
7343 line += SRC_ILT_LINES;
7344 ilt_client->end = line - 1;
7345
7346 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7347 "flags 0x%x, hw psz %d\n",
7348 ilt_client->start,
7349 ilt_client->end,
7350 ilt_client->page_size,
7351 ilt_client->flags,
7352 ilog2(ilt_client->page_size >> 12));
7353
7354#else
7355 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7356#endif
9f6c9258 7357
523224a3
DK		 7358 /* TM */
7359 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7360#ifdef BCM_CNIC
7361 ilt_client->client_num = ILT_CLIENT_TM;
7362 ilt_client->page_size = TM_ILT_PAGE_SZ;
7363 ilt_client->flags = 0;
7364 ilt_client->start = line;
7365 line += TM_ILT_LINES;
7366 ilt_client->end = line - 1;
7367
7368 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7369 "flags 0x%x, hw psz %d\n",
7370 ilt_client->start,
7371 ilt_client->end,
7372 ilt_client->page_size,
7373 ilt_client->flags,
7374 ilog2(ilt_client->page_size >> 12));
9f6c9258 7375
523224a3
DK		 7376#else
7377 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7378#endif
619c5cb6 7379 BUG_ON(line > ILT_MAX_LINES);
523224a3 7380}
f85582f8 7381
619c5cb6
VZ		 7382/**
7383 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7384 *
7385 * @bp: driver handle
7386 * @fp: pointer to fastpath
7387 * @init_params: pointer to parameters structure
7388 *
7389 * parameters configured:
7390 * - HC configuration
7391 * - Queue's CDU context
7392 */
7393static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7394 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 7395{
6383c0b3
AE		 7396
7397 u8 cos;
619c5cb6
VZ		 7398 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7399 if (!IS_FCOE_FP(fp)) {
7400 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7401 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7402
7403 /* If HC is supporterd, enable host coalescing in the transition
7404 * to INIT state.
7405 */
7406 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7407 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7408
7409 /* HC rate */
7410 init_params->rx.hc_rate = bp->rx_ticks ?
7411 (1000000 / bp->rx_ticks) : 0;
7412 init_params->tx.hc_rate = bp->tx_ticks ?
7413 (1000000 / bp->tx_ticks) : 0;
7414
7415 /* FW SB ID */
7416 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7417 fp->fw_sb_id;
7418
7419 /*
7420 * CQ index among the SB indices: FCoE clients uses the default
7421 * SB, therefore it's different.
7422 */
6383c0b3
AE		 7423 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7424 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 7425 }
7426
6383c0b3
AE		 7427 /* set maximum number of COSs supported by this queue */
7428 init_params->max_cos = fp->max_cos;
7429
94f05b0f 7430 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 7431 fp->index, init_params->max_cos);
7432
7433 /* set the context pointers queue object */
7434 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7435 init_params->cxts[cos] =
7436 &bp->context.vcxt[fp->txdata[cos].cid].eth;
619c5cb6
VZ		 7437}
7438
6383c0b3
AE		 7439int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7440 struct bnx2x_queue_state_params *q_params,
7441 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7442 int tx_index, bool leading)
7443{
7444 memset(tx_only_params, 0, sizeof(*tx_only_params));
7445
7446 /* Set the command */
7447 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7448
7449 /* Set tx-only QUEUE flags: don't zero statistics */
7450 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7451
7452 /* choose the index of the cid to send the slow path on */
7453 tx_only_params->cid_index = tx_index;
7454
7455 /* Set general TX_ONLY_SETUP parameters */
7456 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7457
7458 /* Set Tx TX_ONLY_SETUP parameters */
7459 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7460
7461 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7462 "cos %d, primary cid %d, cid %d, "
94f05b0f 7463 "client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 7464 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7465 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7466 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7467
7468 /* send the ramrod */
7469 return bnx2x_queue_state_change(bp, q_params);
7470}
7471
7472
619c5cb6
VZ		 7473/**
7474 * bnx2x_setup_queue - setup queue
7475 *
7476 * @bp: driver handle
7477 * @fp: pointer to fastpath
7478 * @leading: is leading
7479 *
7480 * This function performs 2 steps in a Queue state machine
7481 * actually: 1) RESET->INIT 2) INIT->SETUP
7482 */
7483
7484int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7485 bool leading)
7486{
7487 struct bnx2x_queue_state_params q_params = {0};
7488 struct bnx2x_queue_setup_params *setup_params =
7489 &q_params.params.setup;
6383c0b3
AE		 7490 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7491 &q_params.params.tx_only;
a2fbb9ea 7492 int rc;
6383c0b3
AE		 7493 u8 tx_index;
7494
94f05b0f 7495 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index);
a2fbb9ea 7496
ec6ba945
VZ		 7497 /* reset IGU state skip FCoE L2 queue */
7498 if (!IS_FCOE_FP(fp))
7499 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 7500 IGU_INT_ENABLE, 0);
a2fbb9ea 7501
619c5cb6
VZ		 7502 q_params.q_obj = &fp->q_obj;
7503 /* We want to wait for completion in this context */
7504 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7505
619c5cb6
VZ		 7506 /* Prepare the INIT parameters */
7507 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 7508
619c5cb6
VZ		 7509 /* Set the command */
7510 q_params.cmd = BNX2X_Q_CMD_INIT;
7511
7512 /* Change the state to INIT */
7513 rc = bnx2x_queue_state_change(bp, &q_params);
7514 if (rc) {
6383c0b3 7515 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 7516 return rc;
7517 }
ec6ba945 7518
94f05b0f 7519 DP(BNX2X_MSG_SP, "init complete\n");
6383c0b3
AE		 7520
7521
619c5cb6
VZ		 7522 /* Now move the Queue to the SETUP state... */
7523 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 7524
619c5cb6
VZ		 7525 /* Set QUEUE flags */
7526 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 7527
619c5cb6 7528 /* Set general SETUP parameters */
6383c0b3
AE		 7529 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7530 FIRST_TX_COS_INDEX);
619c5cb6 7531
6383c0b3 7532 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 7533 &setup_params->rxq_params);
7534
6383c0b3
AE		 7535 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7536 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 7537
7538 /* Set the command */
7539 q_params.cmd = BNX2X_Q_CMD_SETUP;
7540
7541 /* Change the state to SETUP */
7542 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 7543 if (rc) {
7544 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7545 return rc;
7546 }
7547
7548 /* loop through the relevant tx-only indices */
7549 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7550 tx_index < fp->max_cos;
7551 tx_index++) {
7552
7553 /* prepare and send tx-only ramrod*/
7554 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7555 tx_only_params, tx_index, leading);
7556 if (rc) {
7557 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7558 fp->index, tx_index);
7559 return rc;
7560 }
7561 }
523224a3 7562
34f80b04 7563 return rc;
a2fbb9ea
ET		 7564}
7565
619c5cb6 7566static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 7567{
619c5cb6 7568 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 7569 struct bnx2x_fp_txdata *txdata;
619c5cb6 7570 struct bnx2x_queue_state_params q_params = {0};
6383c0b3
AE		 7571 int rc, tx_index;
7572
94f05b0f 7573 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 7574
619c5cb6
VZ		 7575 q_params.q_obj = &fp->q_obj;
7576 /* We want to wait for completion in this context */
7577 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7578
6383c0b3
AE		 7579
7580 /* close tx-only connections */
7581 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7582 tx_index < fp->max_cos;
7583 tx_index++){
7584
7585 /* ascertain this is a normal queue*/
7586 txdata = &fp->txdata[tx_index];
7587
94f05b0f 7588 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n",
6383c0b3
AE		 7589 txdata->txq_index);
7590
7591 /* send halt terminate on tx-only connection */
7592 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7593 memset(&q_params.params.terminate, 0,
7594 sizeof(q_params.params.terminate));
7595 q_params.params.terminate.cid_index = tx_index;
7596
7597 rc = bnx2x_queue_state_change(bp, &q_params);
7598 if (rc)
7599 return rc;
7600
7601 /* send halt terminate on tx-only connection */
7602 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7603 memset(&q_params.params.cfc_del, 0,
7604 sizeof(q_params.params.cfc_del));
7605 q_params.params.cfc_del.cid_index = tx_index;
7606 rc = bnx2x_queue_state_change(bp, &q_params);
7607 if (rc)
7608 return rc;
7609 }
7610 /* Stop the primary connection: */
7611 /* ...halt the connection */
619c5cb6
VZ		 7612 q_params.cmd = BNX2X_Q_CMD_HALT;
7613 rc = bnx2x_queue_state_change(bp, &q_params);
7614 if (rc)
da5a662a 7615 return rc;
a2fbb9ea 7616
6383c0b3 7617 /* ...terminate the connection */
619c5cb6 7618 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 7619 memset(&q_params.params.terminate, 0,
7620 sizeof(q_params.params.terminate));
7621 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 7622 rc = bnx2x_queue_state_change(bp, &q_params);
7623 if (rc)
523224a3 7624 return rc;
6383c0b3 7625 /* ...delete cfc entry */
619c5cb6 7626 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 7627 memset(&q_params.params.cfc_del, 0,
7628 sizeof(q_params.params.cfc_del));
7629 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 7630 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 7631}
7632
7633
34f80b04
EG		 7634static void bnx2x_reset_func(struct bnx2x *bp)
7635{
7636 int port = BP_PORT(bp);
7637 int func = BP_FUNC(bp);
f2e0899f 7638 int i;
523224a3
DK		 7639
7640 /* Disable the function in the FW */
7641 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7642 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7643 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7644 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7645
7646 /* FP SBs */
ec6ba945 7647 for_each_eth_queue(bp, i) {
523224a3 7648 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 7649 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7650 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7651 SB_DISABLED);
523224a3
DK		 7652 }
7653
619c5cb6
VZ		 7654#ifdef BCM_CNIC
7655 /* CNIC SB */
7656 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7657 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7658 SB_DISABLED);
7659#endif
523224a3 7660 /* SP SB */
619c5cb6 7661 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7662 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7663 SB_DISABLED);
523224a3
DK		 7664
7665 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7666 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7667 0);
34f80b04
EG		 7668
7669 /* Configure IGU */
f2e0899f
DK		 7670 if (bp->common.int_block == INT_BLOCK_HC) {
7671 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7672 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7673 } else {
7674 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7675 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7676 }
34f80b04 7677
37b091ba
MC		 7678#ifdef BCM_CNIC
7679 /* Disable Timer scan */
7680 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7681 /*
7682 * Wait for at least 10ms and up to 2 second for the timers scan to
7683 * complete
7684 */
7685 for (i = 0; i < 200; i++) {
7686 msleep(10);
7687 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7688 break;
7689 }
7690#endif
34f80b04 7691 /* Clear ILT */
f2e0899f
DK		 7692 bnx2x_clear_func_ilt(bp, func);
7693
7694 /* Timers workaround bug for E2: if this is vnic-3,
7695 * we need to set the entire ilt range for this timers.
7696 */
619c5cb6 7697 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 7698 struct ilt_client_info ilt_cli;
7699 /* use dummy TM client */
7700 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7701 ilt_cli.start = 0;
7702 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7703 ilt_cli.client_num = ILT_CLIENT_TM;
7704
7705 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7706 }
7707
7708 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 7709 if (!CHIP_IS_E1x(bp))
f2e0899f 7710 bnx2x_pf_disable(bp);
523224a3
DK		 7711
7712 bp->dmae_ready = 0;
34f80b04
EG		 7713}
7714
7715static void bnx2x_reset_port(struct bnx2x *bp)
7716{
7717 int port = BP_PORT(bp);
7718 u32 val;
7719
619c5cb6
VZ		 7720 /* Reset physical Link */
7721 bnx2x__link_reset(bp);
7722
34f80b04
EG		 7723 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7724
7725 /* Do not rcv packets to BRB */
7726 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7727 /* Do not direct rcv packets that are not for MCP to the BRB */
7728 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7729 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7730
7731 /* Configure AEU */
7732 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7733
7734 msleep(100);
7735 /* Check for BRB port occupancy */
7736 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7737 if (val)
7738 DP(NETIF_MSG_IFDOWN,
33471629 7739 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 7740
7741 /* TODO: Close Doorbell port? */
7742}
7743
619c5cb6 7744static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 7745{
619c5cb6 7746 struct bnx2x_func_state_params func_params = {0};
34f80b04 7747
619c5cb6
VZ		 7748 /* Prepare parameters for function state transitions */
7749 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 7750
619c5cb6
VZ		 7751 func_params.f_obj = &bp->func_obj;
7752 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 7753
619c5cb6 7754 func_params.params.hw_init.load_phase = load_code;
49d66772 7755
619c5cb6 7756 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 7757}
7758
619c5cb6 7759static inline int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 7760{
619c5cb6
VZ		 7761 struct bnx2x_func_state_params func_params = {0};
7762 int rc;
228241eb 7763
619c5cb6
VZ		 7764 /* Prepare parameters for function state transitions */
7765 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7766 func_params.f_obj = &bp->func_obj;
7767 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 7768
619c5cb6
VZ		 7769 /*
7770 * Try to stop the function the 'good way'. If fails (in case
7771 * of a parity error during bnx2x_chip_cleanup()) and we are
7772 * not in a debug mode, perform a state transaction in order to
7773 * enable further HW_RESET transaction.
7774 */
7775 rc = bnx2x_func_state_change(bp, &func_params);
7776 if (rc) {
34f80b04 7777#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 7778 return rc;
34f80b04 7779#else
619c5cb6
VZ		 7780 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7781 "transaction\n");
7782 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7783 return bnx2x_func_state_change(bp, &func_params);
34f80b04 7784#endif
228241eb 7785 }
a2fbb9ea 7786
619c5cb6
VZ		 7787 return 0;
7788}
523224a3 7789
619c5cb6
VZ		 7790/**
7791 * bnx2x_send_unload_req - request unload mode from the MCP.
7792 *
7793 * @bp: driver handle
7794 * @unload_mode: requested function's unload mode
7795 *
7796 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7797 */
7798u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7799{
7800 u32 reset_code = 0;
7801 int port = BP_PORT(bp);
3101c2bc 7802
619c5cb6 7803 /* Select the UNLOAD request mode */
65abd74d
YG		 7804 if (unload_mode == UNLOAD_NORMAL)
7805 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7806
7d0446c2 7807 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7808 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7809
7d0446c2 7810 else if (bp->wol) {
65abd74d
YG		 7811 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7812 u8 *mac_addr = bp->dev->dev_addr;
7813 u32 val;
f9977903
DK		 7814 u16 pmc;
7815
65abd74d 7816 /* The mac address is written to entries 1-4 to
f9977903
DK		 7817 * preserve entry 0 which is used by the PMF
7818 */
3395a033 7819 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 7820
7821 val = (mac_addr[0] << 8) | mac_addr[1];
7822 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7823
7824 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7825 (mac_addr[4] << 8) | mac_addr[5];
7826 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7827
f9977903
DK		 7828 /* Enable the PME and clear the status */
7829 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
7830 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
7831 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
7832
65abd74d
YG		 7833 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7834
7835 } else
7836 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7837
619c5cb6
VZ		 7838 /* Send the request to the MCP */
7839 if (!BP_NOMCP(bp))
7840 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7841 else {
7842 int path = BP_PATH(bp);
7843
7844 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7845 "%d, %d, %d\n",
7846 path, load_count[path][0], load_count[path][1],
7847 load_count[path][2]);
7848 load_count[path][0]--;
7849 load_count[path][1 + port]--;
7850 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7851 "%d, %d, %d\n",
7852 path, load_count[path][0], load_count[path][1],
7853 load_count[path][2]);
7854 if (load_count[path][0] == 0)
7855 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7856 else if (load_count[path][1 + port] == 0)
7857 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7858 else
7859 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7860 }
7861
7862 return reset_code;
7863}
7864
7865/**
7866 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7867 *
7868 * @bp: driver handle
7869 */
7870void bnx2x_send_unload_done(struct bnx2x *bp)
7871{
7872 /* Report UNLOAD_DONE to MCP */
7873 if (!BP_NOMCP(bp))
7874 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7875}
7876
6debea87
DK		 7877static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7878{
7879 int tout = 50;
7880 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7881
7882 if (!bp->port.pmf)
7883 return 0;
7884
7885 /*
7886 * (assumption: No Attention from MCP at this stage)
7887 * PMF probably in the middle of TXdisable/enable transaction
7888 * 1. Sync IRS for default SB
7889 * 2. Sync SP queue - this guarantes us that attention handling started
7890 * 3. Wait, that TXdisable/enable transaction completes
7891 *
7892 * 1+2 guranty that if DCBx attention was scheduled it already changed
7893 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7894 * received complettion for the transaction the state is TX_STOPPED.
7895 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7896 * transaction.
7897 */
7898
7899 /* make sure default SB ISR is done */
7900 if (msix)
7901 synchronize_irq(bp->msix_table[0].vector);
7902 else
7903 synchronize_irq(bp->pdev->irq);
7904
7905 flush_workqueue(bnx2x_wq);
7906
7907 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7908 BNX2X_F_STATE_STARTED && tout--)
7909 msleep(20);
7910
7911 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7912 BNX2X_F_STATE_STARTED) {
7913#ifdef BNX2X_STOP_ON_ERROR
7914 return -EBUSY;
7915#else
7916 /*
7917 * Failed to complete the transaction in a "good way"
7918 * Force both transactions with CLR bit
7919 */
7920 struct bnx2x_func_state_params func_params = {0};
7921
7922 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7923 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7924
7925 func_params.f_obj = &bp->func_obj;
7926 __set_bit(RAMROD_DRV_CLR_ONLY,
7927 &func_params.ramrod_flags);
7928
7929 /* STARTED-->TX_ST0PPED */
7930 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7931 bnx2x_func_state_change(bp, &func_params);
7932
7933 /* TX_ST0PPED-->STARTED */
7934 func_params.cmd = BNX2X_F_CMD_TX_START;
7935 return bnx2x_func_state_change(bp, &func_params);
7936#endif
7937 }
7938
7939 return 0;
7940}
7941
619c5cb6
VZ		 7942void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7943{
7944 int port = BP_PORT(bp);
6383c0b3
AE		 7945 int i, rc = 0;
7946 u8 cos;
619c5cb6
VZ		 7947 struct bnx2x_mcast_ramrod_params rparam = {0};
7948 u32 reset_code;
7949
7950 /* Wait until tx fastpath tasks complete */
7951 for_each_tx_queue(bp, i) {
7952 struct bnx2x_fastpath *fp = &bp->fp[i];
7953
6383c0b3
AE		 7954 for_each_cos_in_tx_queue(fp, cos)
7955 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
619c5cb6
VZ		 7956#ifdef BNX2X_STOP_ON_ERROR
7957 if (rc)
7958 return;
7959#endif
7960 }
7961
7962 /* Give HW time to discard old tx messages */
7963 usleep_range(1000, 1000);
7964
7965 /* Clean all ETH MACs */
7966 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7967 if (rc < 0)
7968 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7969
7970 /* Clean up UC list */
7971 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7972 true);
7973 if (rc < 0)
7974 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7975 "%d\n", rc);
7976
7977 /* Disable LLH */
7978 if (!CHIP_IS_E1(bp))
7979 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7980
7981 /* Set "drop all" (stop Rx).
7982 * We need to take a netif_addr_lock() here in order to prevent
7983 * a race between the completion code and this code.
7984 */
7985 netif_addr_lock_bh(bp->dev);
7986 /* Schedule the rx_mode command */
7987 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7988 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7989 else
7990 bnx2x_set_storm_rx_mode(bp);
7991
7992 /* Cleanup multicast configuration */
7993 rparam.mcast_obj = &bp->mcast_obj;
7994 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7995 if (rc < 0)
7996 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7997
7998 netif_addr_unlock_bh(bp->dev);
7999
8000
6debea87
DK		 8001
8002 /*
8003 * Send the UNLOAD_REQUEST to the MCP. This will return if
8004 * this function should perform FUNC, PORT or COMMON HW
8005 * reset.
8006 */
8007 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8008
8009 /*
8010 * (assumption: No Attention from MCP at this stage)
8011 * PMF probably in the middle of TXdisable/enable transaction
8012 */
8013 rc = bnx2x_func_wait_started(bp);
8014 if (rc) {
8015 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8016#ifdef BNX2X_STOP_ON_ERROR
8017 return;
8018#endif
8019 }
8020
34f80b04 8021 /* Close multi and leading connections
619c5cb6
VZ		 8022 * Completions for ramrods are collected in a synchronous way
8023 */
523224a3 8024 for_each_queue(bp, i)
619c5cb6 8025 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 8026#ifdef BNX2X_STOP_ON_ERROR
8027 return;
8028#else
228241eb 8029 goto unload_error;
523224a3 8030#endif
619c5cb6
VZ		 8031 /* If SP settings didn't get completed so far - something
8032 * very wrong has happen.
8033 */
8034 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8035 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 8036
619c5cb6
VZ		 8037#ifndef BNX2X_STOP_ON_ERROR
8038unload_error:
8039#endif
523224a3 8040 rc = bnx2x_func_stop(bp);
da5a662a 8041 if (rc) {
523224a3 8042 BNX2X_ERR("Function stop failed!\n");
da5a662a 8043#ifdef BNX2X_STOP_ON_ERROR
523224a3 8044 return;
523224a3 8045#endif
34f80b04 8046 }
a2fbb9ea 8047
523224a3
DK		 8048 /* Disable HW interrupts, NAPI */
8049 bnx2x_netif_stop(bp, 1);
8050
8051 /* Release IRQs */
d6214d7a 8052 bnx2x_free_irq(bp);
523224a3 8053
a2fbb9ea 8054 /* Reset the chip */
619c5cb6
VZ		 8055 rc = bnx2x_reset_hw(bp, reset_code);
8056 if (rc)
8057 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 8058
356e2385 8059
619c5cb6
VZ		 8060 /* Report UNLOAD_DONE to MCP */
8061 bnx2x_send_unload_done(bp);
72fd0718
VZ		 8062}
8063
9f6c9258 8064void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 8065{
8066 u32 val;
8067
8068 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
8069
8070 if (CHIP_IS_E1(bp)) {
8071 int port = BP_PORT(bp);
8072 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8073 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8074
8075 val = REG_RD(bp, addr);
8076 val &= ~(0x300);
8077 REG_WR(bp, addr, val);
619c5cb6 8078 } else {
72fd0718
VZ		 8079 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8080 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8081 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8082 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8083 }
8084}
8085
72fd0718
VZ		 8086/* Close gates #2, #3 and #4: */
8087static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8088{
c9ee9206 8089 u32 val;
72fd0718
VZ		 8090
8091 /* Gates #2 and #4a are closed/opened for "not E1" only */
8092 if (!CHIP_IS_E1(bp)) {
8093 /* #4 */
c9ee9206 8094 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 8095 /* #2 */
c9ee9206 8096 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 8097 }
8098
8099 /* #3 */
c9ee9206
VZ		 8100 if (CHIP_IS_E1x(bp)) {
8101 /* Prevent interrupts from HC on both ports */
8102 val = REG_RD(bp, HC_REG_CONFIG_1);
8103 REG_WR(bp, HC_REG_CONFIG_1,
8104 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8105 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8106
8107 val = REG_RD(bp, HC_REG_CONFIG_0);
8108 REG_WR(bp, HC_REG_CONFIG_0,
8109 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8110 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8111 } else {
8112 /* Prevent incomming interrupts in IGU */
8113 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8114
8115 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8116 (!close) ?
8117 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8118 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8119 }
72fd0718
VZ		 8120
8121 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
8122 close ? "closing" : "opening");
8123 mmiowb();
8124}
8125
8126#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8127
8128static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8129{
8130 /* Do some magic... */
8131 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8132 *magic_val = val & SHARED_MF_CLP_MAGIC;
8133 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8134}
8135
e8920674
DK		 8136/**
8137 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 8138 *
e8920674
DK		 8139 * @bp: driver handle
8140 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 8141 */
8142static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8143{
8144 /* Restore the `magic' bit value... */
72fd0718
VZ		 8145 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8146 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8147 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8148}
8149
f85582f8 8150/**
e8920674 8151 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 8152 *
e8920674
DK		 8153 * @bp: driver handle
8154 * @magic_val: old value of 'magic' bit.
8155 *
8156 * Takes care of CLP configurations.
72fd0718
VZ		 8157 */
8158static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8159{
8160 u32 shmem;
8161 u32 validity_offset;
8162
8163 DP(NETIF_MSG_HW, "Starting\n");
8164
8165 /* Set `magic' bit in order to save MF config */
8166 if (!CHIP_IS_E1(bp))
8167 bnx2x_clp_reset_prep(bp, magic_val);
8168
8169 /* Get shmem offset */
8170 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8171 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8172
8173 /* Clear validity map flags */
8174 if (shmem > 0)
8175 REG_WR(bp, shmem + validity_offset, 0);
8176}
8177
8178#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8179#define MCP_ONE_TIMEOUT 100 /* 100 ms */
8180
e8920674
DK		 8181/**
8182 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 8183 *
e8920674 8184 * @bp: driver handle
72fd0718
VZ		 8185 */
8186static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
8187{
8188 /* special handling for emulation and FPGA,
8189 wait 10 times longer */
8190 if (CHIP_REV_IS_SLOW(bp))
8191 msleep(MCP_ONE_TIMEOUT*10);
8192 else
8193 msleep(MCP_ONE_TIMEOUT);
8194}
8195
1b6e2ceb
DK		 8196/*
8197 * initializes bp->common.shmem_base and waits for validity signature to appear
8198 */
8199static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 8200{
1b6e2ceb
DK		 8201 int cnt = 0;
8202 u32 val = 0;
72fd0718 8203
1b6e2ceb
DK		 8204 do {
8205 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8206 if (bp->common.shmem_base) {
8207 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8208 if (val & SHR_MEM_VALIDITY_MB)
8209 return 0;
8210 }
72fd0718 8211
1b6e2ceb 8212 bnx2x_mcp_wait_one(bp);
72fd0718 8213
1b6e2ceb 8214 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 8215
1b6e2ceb 8216 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 8217
1b6e2ceb
DK		 8218 return -ENODEV;
8219}
72fd0718 8220
1b6e2ceb
DK		 8221static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8222{
8223 int rc = bnx2x_init_shmem(bp);
72fd0718 8224
72fd0718
VZ		 8225 /* Restore the `magic' bit value */
8226 if (!CHIP_IS_E1(bp))
8227 bnx2x_clp_reset_done(bp, magic_val);
8228
8229 return rc;
8230}
8231
8232static void bnx2x_pxp_prep(struct bnx2x *bp)
8233{
8234 if (!CHIP_IS_E1(bp)) {
8235 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8236 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 8237 mmiowb();
8238 }
8239}
8240
8241/*
8242 * Reset the whole chip except for:
8243 * - PCIE core
8244 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8245 * one reset bit)
8246 * - IGU
8247 * - MISC (including AEU)
8248 * - GRC
8249 * - RBCN, RBCP
8250 */
c9ee9206 8251static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 8252{
8253 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 8254 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 8255
8256 /*
8257 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8258 * (per chip) blocks.
8259 */
8260 global_bits2 =
8261 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8262 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 8263
8736c826 8264 /* Don't reset the following blocks */
72fd0718
VZ		 8265 not_reset_mask1 =
8266 MISC_REGISTERS_RESET_REG_1_RST_HC |
8267 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8268 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8269
8270 not_reset_mask2 =
c9ee9206 8271 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 8272 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8273 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8274 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8275 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8276 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8277 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 8278 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8279 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8280 MISC_REGISTERS_RESET_REG_2_PGLC;
72fd0718 8281
8736c826
VZ		 8282 /*
8283 * Keep the following blocks in reset:
8284 * - all xxMACs are handled by the bnx2x_link code.
8285 */
8286 stay_reset2 =
8287 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8288 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8289 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8290 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8291 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8292 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8293 MISC_REGISTERS_RESET_REG_2_XMAC |
8294 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8295
8296 /* Full reset masks according to the chip */
72fd0718
VZ		 8297 reset_mask1 = 0xffffffff;
8298
8299 if (CHIP_IS_E1(bp))
8300 reset_mask2 = 0xffff;
8736c826 8301 else if (CHIP_IS_E1H(bp))
72fd0718 8302 reset_mask2 = 0x1ffff;
8736c826
VZ		 8303 else if (CHIP_IS_E2(bp))
8304 reset_mask2 = 0xfffff;
8305 else /* CHIP_IS_E3 */
8306 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 8307
8308 /* Don't reset global blocks unless we need to */
8309 if (!global)
8310 reset_mask2 &= ~global_bits2;
8311
8312 /*
8313 * In case of attention in the QM, we need to reset PXP
8314 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8315 * because otherwise QM reset would release 'close the gates' shortly
8316 * before resetting the PXP, then the PSWRQ would send a write
8317 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8318 * read the payload data from PSWWR, but PSWWR would not
8319 * respond. The write queue in PGLUE would stuck, dmae commands
8320 * would not return. Therefore it's important to reset the second
8321 * reset register (containing the
8322 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8323 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8324 * bit).
8325 */
72fd0718
VZ		 8326 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8327 reset_mask2 & (~not_reset_mask2));
8328
c9ee9206
VZ		 8329 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8330 reset_mask1 & (~not_reset_mask1));
8331
72fd0718
VZ		 8332 barrier();
8333 mmiowb();
8334
8736c826
VZ		 8335 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8336 reset_mask2 & (~stay_reset2));
8337
8338 barrier();
8339 mmiowb();
8340
c9ee9206 8341 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 8342 mmiowb();
8343}
8344
c9ee9206
VZ		 8345/**
8346 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8347 * It should get cleared in no more than 1s.
8348 *
8349 * @bp: driver handle
8350 *
8351 * It should get cleared in no more than 1s. Returns 0 if
8352 * pending writes bit gets cleared.
8353 */
8354static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8355{
8356 u32 cnt = 1000;
8357 u32 pend_bits = 0;
8358
8359 do {
8360 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8361
8362 if (pend_bits == 0)
8363 break;
8364
8365 usleep_range(1000, 1000);
8366 } while (cnt-- > 0);
8367
8368 if (cnt <= 0) {
8369 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8370 pend_bits);
8371 return -EBUSY;
8372 }
8373
8374 return 0;
8375}
8376
8377static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 8378{
8379 int cnt = 1000;
8380 u32 val = 0;
8381 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8382
8383
8384 /* Empty the Tetris buffer, wait for 1s */
8385 do {
8386 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8387 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8388 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8389 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8390 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8391 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8392 ((port_is_idle_0 & 0x1) == 0x1) &&
8393 ((port_is_idle_1 & 0x1) == 0x1) &&
8394 (pgl_exp_rom2 == 0xffffffff))
8395 break;
c9ee9206 8396 usleep_range(1000, 1000);
72fd0718
VZ		 8397 } while (cnt-- > 0);
8398
8399 if (cnt <= 0) {
8400 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8401 " are still"
8402 " outstanding read requests after 1s!\n");
8403 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8404 " port_is_idle_0=0x%08x,"
8405 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8406 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8407 pgl_exp_rom2);
8408 return -EAGAIN;
8409 }
8410
8411 barrier();
8412
8413 /* Close gates #2, #3 and #4 */
8414 bnx2x_set_234_gates(bp, true);
8415
c9ee9206
VZ		 8416 /* Poll for IGU VQs for 57712 and newer chips */
8417 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8418 return -EAGAIN;
8419
8420
72fd0718
VZ		 8421 /* TBD: Indicate that "process kill" is in progress to MCP */
8422
8423 /* Clear "unprepared" bit */
8424 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8425 barrier();
8426
8427 /* Make sure all is written to the chip before the reset */
8428 mmiowb();
8429
8430 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8431 * PSWHST, GRC and PSWRD Tetris buffer.
8432 */
c9ee9206 8433 usleep_range(1000, 1000);
72fd0718
VZ		 8434
8435 /* Prepare to chip reset: */
8436 /* MCP */
c9ee9206
VZ		 8437 if (global)
8438 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 8439
8440 /* PXP */
8441 bnx2x_pxp_prep(bp);
8442 barrier();
8443
8444 /* reset the chip */
c9ee9206 8445 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 8446 barrier();
8447
8448 /* Recover after reset: */
8449 /* MCP */
c9ee9206 8450 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 8451 return -EAGAIN;
8452
c9ee9206
VZ		 8453 /* TBD: Add resetting the NO_MCP mode DB here */
8454
72fd0718
VZ		 8455 /* PXP */
8456 bnx2x_pxp_prep(bp);
8457
8458 /* Open the gates #2, #3 and #4 */
8459 bnx2x_set_234_gates(bp, false);
8460
8461 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8462 * reset state, re-enable attentions. */
8463
a2fbb9ea
ET		 8464 return 0;
8465}
8466
c9ee9206 8467int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 8468{
8469 int rc = 0;
c9ee9206
VZ		 8470 bool global = bnx2x_reset_is_global(bp);
8471
72fd0718 8472 /* Try to recover after the failure */
c9ee9206
VZ		 8473 if (bnx2x_process_kill(bp, global)) {
8474 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8475 "Aii!\n", BP_PATH(bp));
72fd0718
VZ		 8476 rc = -EAGAIN;
8477 goto exit_leader_reset;
8478 }
8479
c9ee9206
VZ		 8480 /*
8481 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8482 * state.
8483 */
72fd0718 8484 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 8485 if (global)
8486 bnx2x_clear_reset_global(bp);
72fd0718
VZ		 8487
8488exit_leader_reset:
8489 bp->is_leader = 0;
c9ee9206
VZ		 8490 bnx2x_release_leader_lock(bp);
8491 smp_mb();
72fd0718
VZ		 8492 return rc;
8493}
8494
c9ee9206
VZ		 8495static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8496{
8497 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8498
8499 /* Disconnect this device */
8500 netif_device_detach(bp->dev);
8501
8502 /*
8503 * Block ifup for all function on this engine until "process kill"
8504 * or power cycle.
8505 */
8506 bnx2x_set_reset_in_progress(bp);
8507
8508 /* Shut down the power */
8509 bnx2x_set_power_state(bp, PCI_D3hot);
8510
8511 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8512
8513 smp_mb();
8514}
8515
8516/*
8517 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 8518 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 8519 * will never be called when netif_running(bp->dev) is false.
8520 */
8521static void bnx2x_parity_recover(struct bnx2x *bp)
8522{
c9ee9206
VZ		 8523 bool global = false;
8524
72fd0718
VZ		 8525 DP(NETIF_MSG_HW, "Handling parity\n");
8526 while (1) {
8527 switch (bp->recovery_state) {
8528 case BNX2X_RECOVERY_INIT:
8529 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
c9ee9206
VZ		 8530 bnx2x_chk_parity_attn(bp, &global, false);
8531
72fd0718 8532 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 8533 if (bnx2x_trylock_leader_lock(bp)) {
8534 bnx2x_set_reset_in_progress(bp);
8535 /*
8536 * Check if there is a global attention and if
8537 * there was a global attention, set the global
8538 * reset bit.
8539 */
8540
8541 if (global)
8542 bnx2x_set_reset_global(bp);
8543
72fd0718 8544 bp->is_leader = 1;
c9ee9206 8545 }
72fd0718
VZ		 8546
8547 /* Stop the driver */
8548 /* If interface has been removed - break */
8549 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8550 return;
8551
8552 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206
VZ		 8553
8554 /*
8555 * Reset MCP command sequence number and MCP mail box
8556 * sequence as we are going to reset the MCP.
8557 */
8558 if (global) {
8559 bp->fw_seq = 0;
8560 bp->fw_drv_pulse_wr_seq = 0;
8561 }
8562
8563 /* Ensure "is_leader", MCP command sequence and
8564 * "recovery_state" update values are seen on other
8565 * CPUs.
72fd0718 8566 */
c9ee9206 8567 smp_mb();
72fd0718
VZ		 8568 break;
8569
8570 case BNX2X_RECOVERY_WAIT:
8571 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8572 if (bp->is_leader) {
c9ee9206
VZ		 8573 int other_engine = BP_PATH(bp) ? 0 : 1;
8574 u32 other_load_counter =
8575 bnx2x_get_load_cnt(bp, other_engine);
8576 u32 load_counter =
8577 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8578 global = bnx2x_reset_is_global(bp);
8579
8580 /*
8581 * In case of a parity in a global block, let
8582 * the first leader that performs a
8583 * leader_reset() reset the global blocks in
8584 * order to clear global attentions. Otherwise
8585 * the the gates will remain closed for that
8586 * engine.
8587 */
8588 if (load_counter ||
8589 (global && other_load_counter)) {
72fd0718
VZ		 8590 /* Wait until all other functions get
8591 * down.
8592 */
7be08a72 8593 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8594 HZ/10);
8595 return;
8596 } else {
8597 /* If all other functions got down -
8598 * try to bring the chip back to
8599 * normal. In any case it's an exit
8600 * point for a leader.
8601 */
c9ee9206
VZ		 8602 if (bnx2x_leader_reset(bp)) {
8603 bnx2x_recovery_failed(bp);
72fd0718
VZ		 8604 return;
8605 }
8606
c9ee9206
VZ		 8607 /* If we are here, means that the
8608 * leader has succeeded and doesn't
8609 * want to be a leader any more. Try
8610 * to continue as a none-leader.
8611 */
8612 break;
72fd0718
VZ		 8613 }
8614 } else { /* non-leader */
c9ee9206 8615 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 8616 /* Try to get a LEADER_LOCK HW lock as
8617 * long as a former leader may have
8618 * been unloaded by the user or
8619 * released a leadership by another
8620 * reason.
8621 */
c9ee9206 8622 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 8623 /* I'm a leader now! Restart a
8624 * switch case.
8625 */
8626 bp->is_leader = 1;
8627 break;
8628 }
8629
7be08a72 8630 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8631 HZ/10);
8632 return;
8633
c9ee9206
VZ		 8634 } else {
8635 /*
8636 * If there was a global attention, wait
8637 * for it to be cleared.
8638 */
8639 if (bnx2x_reset_is_global(bp)) {
8640 schedule_delayed_work(
7be08a72
AE		 8641 &bp->sp_rtnl_task,
8642 HZ/10);
c9ee9206
VZ		 8643 return;
8644 }
8645
8646 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8647 bnx2x_recovery_failed(bp);
8648 else {
8649 bp->recovery_state =
8650 BNX2X_RECOVERY_DONE;
8651 smp_mb();
8652 }
8653
72fd0718
VZ		 8654 return;
8655 }
8656 }
8657 default:
8658 return;
8659 }
8660 }
8661}
8662
8663/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8664 * scheduled on a general queue in order to prevent a dead lock.
8665 */
7be08a72 8666static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 8667{
7be08a72 8668 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 8669
8670 rtnl_lock();
8671
8672 if (!netif_running(bp->dev))
7be08a72
AE		 8673 goto sp_rtnl_exit;
8674
8675 /* if stop on error is defined no recovery flows should be executed */
8676#ifdef BNX2X_STOP_ON_ERROR
8677 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8678 "so reset not done to allow debug dump,\n"
8679 "you will need to reboot when done\n");
b1fb8740 8680 goto sp_rtnl_not_reset;
7be08a72 8681#endif
34f80b04 8682
7be08a72
AE		 8683 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8684 /*
b1fb8740
VZ		 8685 * Clear all pending SP commands as we are going to reset the
8686 * function anyway.
7be08a72 8687 */
b1fb8740
VZ		 8688 bp->sp_rtnl_state = 0;
8689 smp_mb();
8690
72fd0718 8691 bnx2x_parity_recover(bp);
b1fb8740
VZ		 8692
8693 goto sp_rtnl_exit;
8694 }
8695
8696 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8697 /*
8698 * Clear all pending SP commands as we are going to reset the
8699 * function anyway.
8700 */
8701 bp->sp_rtnl_state = 0;
8702 smp_mb();
8703
72fd0718
VZ		 8704 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8705 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740
VZ		 8706
8707 goto sp_rtnl_exit;
72fd0718 8708 }
b1fb8740
VZ		 8709#ifdef BNX2X_STOP_ON_ERROR
8710sp_rtnl_not_reset:
8711#endif
8712 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8713 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
34f80b04 8714
8304859a
AE		 8715 /*
8716 * in case of fan failure we need to reset id if the "stop on error"
8717 * debug flag is set, since we trying to prevent permanent overheating
8718 * damage
8719 */
8720 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
5219e4c9 8721 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n");
8304859a
AE		 8722 netif_device_detach(bp->dev);
8723 bnx2x_close(bp->dev);
8724 }
8725
7be08a72 8726sp_rtnl_exit:
34f80b04
EG		 8727 rtnl_unlock();
8728}
8729
a2fbb9ea
ET		 8730/* end of nic load/unload */
8731
3deb8167
YR		 8732static void bnx2x_period_task(struct work_struct *work)
8733{
8734 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8735
8736 if (!netif_running(bp->dev))
8737 goto period_task_exit;
8738
8739 if (CHIP_REV_IS_SLOW(bp)) {
8740 BNX2X_ERR("period task called on emulation, ignoring\n");
8741 goto period_task_exit;
8742 }
8743
8744 bnx2x_acquire_phy_lock(bp);
8745 /*
8746 * The barrier is needed to ensure the ordering between the writing to
8747 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8748 * the reading here.
8749 */
8750 smp_mb();
8751 if (bp->port.pmf) {
8752 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8753
8754 /* Re-queue task in 1 sec */
8755 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8756 }
8757
8758 bnx2x_release_phy_lock(bp);
8759period_task_exit:
8760 return;
8761}
8762
a2fbb9ea
ET		 8763/*
8764 * Init service functions
8765 */
8766
8d96286a 8767static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 8768{
8769 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8770 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8771 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 8772}
8773
f2e0899f 8774static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 8775{
f2e0899f 8776 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 8777
8778 /* Flush all outstanding writes */
8779 mmiowb();
8780
8781 /* Pretend to be function 0 */
8782 REG_WR(bp, reg, 0);
f2e0899f 8783 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 8784
8785 /* From now we are in the "like-E1" mode */
8786 bnx2x_int_disable(bp);
8787
8788 /* Flush all outstanding writes */
8789 mmiowb();
8790
f2e0899f
DK		 8791 /* Restore the original function */
8792 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8793 REG_RD(bp, reg);
f1ef27ef
EG		 8794}
8795
f2e0899f 8796static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 8797{
f2e0899f 8798 if (CHIP_IS_E1(bp))
f1ef27ef 8799 bnx2x_int_disable(bp);
f2e0899f
DK		 8800 else
8801 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 8802}
8803
34f80b04
EG		 8804static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8805{
8806 u32 val;
8807
8808 /* Check if there is any driver already loaded */
8809 val = REG_RD(bp, MISC_REG_UNPREPARED);
8810 if (val == 0x1) {
7a06a122
DK		 8811
8812 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8813 /*
8814 * Check if it is the UNDI driver
34f80b04
EG		 8815 * UNDI driver initializes CID offset for normal bell to 0x7
8816 */
8817 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8818 if (val == 0x7) {
8819 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 8820 /* save our pf_num */
8821 int orig_pf_num = bp->pf_num;
619c5cb6
VZ		 8822 int port;
8823 u32 swap_en, swap_val, value;
34f80b04 8824
b4661739
EG		 8825 /* clear the UNDI indication */
8826 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8827
34f80b04
EG		 8828 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8829
8830 /* try unload UNDI on port 0 */
f2e0899f 8831 bp->pf_num = 0;
da5a662a 8832 bp->fw_seq =
f2e0899f 8833 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8834 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 8835 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8836
8837 /* if UNDI is loaded on the other port */
8838 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8839
da5a662a 8840 /* send "DONE" for previous unload */
a22f0788
YR		 8841 bnx2x_fw_command(bp,
8842 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8843
8844 /* unload UNDI on port 1 */
f2e0899f 8845 bp->pf_num = 1;
da5a662a 8846 bp->fw_seq =
f2e0899f 8847 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 8848 DRV_MSG_SEQ_NUMBER_MASK);
8849 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8850
a22f0788 8851 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8852 }
8853
f2e0899f 8854 bnx2x_undi_int_disable(bp);
619c5cb6 8855 port = BP_PORT(bp);
da5a662a
VZ		 8856
8857 /* close input traffic and wait for it */
8858 /* Do not rcv packets to BRB */
619c5cb6
VZ		 8859 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8860 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
da5a662a
VZ		 8861 /* Do not direct rcv packets that are not for MCP to
8862 * the BRB */
619c5cb6
VZ		 8863 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8864 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
da5a662a 8865 /* clear AEU */
619c5cb6
VZ		 8866 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8867 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
da5a662a
VZ		 8868 msleep(10);
8869
8870 /* save NIG port swap info */
8871 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8872 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 8873 /* reset device */
8874 REG_WR(bp,
8875 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 8876 0xd3ffffff);
619c5cb6
VZ		 8877
8878 value = 0x1400;
8879 if (CHIP_IS_E3(bp)) {
8880 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8881 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8882 }
8883
34f80b04
EG		 8884 REG_WR(bp,
8885 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
619c5cb6
VZ		 8886 value);
8887
da5a662a
VZ		 8888 /* take the NIG out of reset and restore swap values */
8889 REG_WR(bp,
8890 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8891 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8892 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8893 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8894
8895 /* send unload done to the MCP */
a22f0788 8896 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8897
8898 /* restore our func and fw_seq */
f2e0899f 8899 bp->pf_num = orig_pf_num;
da5a662a 8900 bp->fw_seq =
f2e0899f 8901 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8902 DRV_MSG_SEQ_NUMBER_MASK);
7a06a122
DK		 8903 }
8904
8905 /* now it's safe to release the lock */
8906 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
34f80b04
EG		 8907 }
8908}
8909
8910static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8911{
1d187b34 8912 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 8913 u16 pmc;
34f80b04
EG		 8914
8915 /* Get the chip revision id and number. */
8916 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8917 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8918 id = ((val & 0xffff) << 16);
8919 val = REG_RD(bp, MISC_REG_CHIP_REV);
8920 id |= ((val & 0xf) << 12);
8921 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8922 id |= ((val & 0xff) << 4);
5a40e08e 8923 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 8924 id |= (val & 0xf);
8925 bp->common.chip_id = id;
523224a3
DK		 8926
8927 /* Set doorbell size */
8928 bp->db_size = (1 << BNX2X_DB_SHIFT);
8929
619c5cb6 8930 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8931 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8932 if ((val & 1) == 0)
8933 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8934 else
8935 val = (val >> 1) & 1;
8936 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8937 "2_PORT_MODE");
8938 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8939 CHIP_2_PORT_MODE;
8940
8941 if (CHIP_MODE_IS_4_PORT(bp))
8942 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8943 else
8944 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8945 } else {
8946 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8947 bp->pfid = bp->pf_num; /* 0..7 */
8948 }
8949
f2e0899f
DK		 8950 bp->link_params.chip_id = bp->common.chip_id;
8951 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 8952
1c06328c
EG		 8953 val = (REG_RD(bp, 0x2874) & 0x55);
8954 if ((bp->common.chip_id & 0x1) ||
8955 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8956 bp->flags |= ONE_PORT_FLAG;
8957 BNX2X_DEV_INFO("single port device\n");
8958 }
8959
34f80b04 8960 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 8961 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 8962 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8963 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8964 bp->common.flash_size, bp->common.flash_size);
8965
1b6e2ceb
DK		 8966 bnx2x_init_shmem(bp);
8967
619c5cb6
VZ		 8968
8969
f2e0899f
DK		 8970 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8971 MISC_REG_GENERIC_CR_1 :
8972 MISC_REG_GENERIC_CR_0));
1b6e2ceb 8973
34f80b04 8974 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 8975 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 8976 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8977 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 8978
f2e0899f 8979 if (!bp->common.shmem_base) {
34f80b04
EG		 8980 BNX2X_DEV_INFO("MCP not active\n");
8981 bp->flags |= NO_MCP_FLAG;
8982 return;
8983 }
8984
34f80b04 8985 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 8986 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 8987
8988 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8989 SHARED_HW_CFG_LED_MODE_MASK) >>
8990 SHARED_HW_CFG_LED_MODE_SHIFT);
8991
c2c8b03e
EG		 8992 bp->link_params.feature_config_flags = 0;
8993 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8994 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8995 bp->link_params.feature_config_flags |=
8996 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8997 else
8998 bp->link_params.feature_config_flags &=
8999 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9000
34f80b04
EG		 9001 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9002 bp->common.bc_ver = val;
9003 BNX2X_DEV_INFO("bc_ver %X\n", val);
9004 if (val < BNX2X_BC_VER) {
9005 /* for now only warn
9006 * later we might need to enforce this */
f2e0899f
DK		 9007 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
9008 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 9009 }
4d295db0 9010 bp->link_params.feature_config_flags |=
a22f0788 9011 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 9012 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9013
a22f0788
YR		 9014 bp->link_params.feature_config_flags |=
9015 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9016 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 9017
85242eea
YR		 9018 bp->link_params.feature_config_flags |=
9019 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9020 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
0e898dd7
BW		 9021 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9022 BC_SUPPORTS_PFC_STATS : 0;
85242eea 9023
1d187b34
BW		 9024 boot_mode = SHMEM_RD(bp,
9025 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9026 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9027 switch (boot_mode) {
9028 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9029 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9030 break;
9031 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9032 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9033 break;
9034 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9035 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9036 break;
9037 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9038 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9039 break;
9040 }
9041
f9a3ebbe
DK		 9042 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9043 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9044
72ce58c3 9045 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 9046 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 9047
9048 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9049 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9050 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9051 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9052
cdaa7cb8
VZ		 9053 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9054 val, val2, val3, val4);
34f80b04
EG		 9055}
9056
f2e0899f
DK		 9057#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9058#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9059
9060static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9061{
9062 int pfid = BP_FUNC(bp);
f2e0899f
DK		 9063 int igu_sb_id;
9064 u32 val;
6383c0b3 9065 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 9066
9067 bp->igu_base_sb = 0xff;
f2e0899f 9068 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 9069 int vn = BP_VN(bp);
6383c0b3 9070 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 9071 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9072 FP_SB_MAX_E1x;
9073
9074 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9075 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9076
9077 return;
9078 }
9079
9080 /* IGU in normal mode - read CAM */
9081 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9082 igu_sb_id++) {
9083 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9084 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9085 continue;
9086 fid = IGU_FID(val);
9087 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9088 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9089 continue;
9090 if (IGU_VEC(val) == 0)
9091 /* default status block */
9092 bp->igu_dsb_id = igu_sb_id;
9093 else {
9094 if (bp->igu_base_sb == 0xff)
9095 bp->igu_base_sb = igu_sb_id;
6383c0b3 9096 igu_sb_cnt++;
f2e0899f
DK		 9097 }
9098 }
9099 }
619c5cb6 9100
6383c0b3
AE		 9101#ifdef CONFIG_PCI_MSI
9102 /*
9103 * It's expected that number of CAM entries for this functions is equal
9104 * to the number evaluated based on the MSI-X table size. We want a
9105 * harsh warning if these values are different!
619c5cb6 9106 */
6383c0b3
AE		 9107 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
9108#endif
619c5cb6 9109
6383c0b3 9110 if (igu_sb_cnt == 0)
f2e0899f
DK		 9111 BNX2X_ERR("CAM configuration error\n");
9112}
9113
34f80b04
EG		 9114static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9115 u32 switch_cfg)
a2fbb9ea 9116{
a22f0788
YR		 9117 int cfg_size = 0, idx, port = BP_PORT(bp);
9118
9119 /* Aggregation of supported attributes of all external phys */
9120 bp->port.supported[0] = 0;
9121 bp->port.supported[1] = 0;
b7737c9b
YR		 9122 switch (bp->link_params.num_phys) {
9123 case 1:
a22f0788
YR		 9124 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9125 cfg_size = 1;
9126 break;
b7737c9b 9127 case 2:
a22f0788
YR		 9128 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9129 cfg_size = 1;
9130 break;
9131 case 3:
9132 if (bp->link_params.multi_phy_config &
9133 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
9134 bp->port.supported[1] =
9135 bp->link_params.phy[EXT_PHY1].supported;
9136 bp->port.supported[0] =
9137 bp->link_params.phy[EXT_PHY2].supported;
9138 } else {
9139 bp->port.supported[0] =
9140 bp->link_params.phy[EXT_PHY1].supported;
9141 bp->port.supported[1] =
9142 bp->link_params.phy[EXT_PHY2].supported;
9143 }
9144 cfg_size = 2;
9145 break;
b7737c9b 9146 }
a2fbb9ea 9147
a22f0788 9148 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 9149 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 9150 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 9151 SHMEM_RD(bp,
a22f0788
YR		 9152 dev_info.port_hw_config[port].external_phy_config),
9153 SHMEM_RD(bp,
9154 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 9155 return;
f85582f8 9156 }
a2fbb9ea 9157
619c5cb6
VZ		 9158 if (CHIP_IS_E3(bp))
9159 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9160 else {
9161 switch (switch_cfg) {
9162 case SWITCH_CFG_1G:
9163 bp->port.phy_addr = REG_RD(
9164 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9165 break;
9166 case SWITCH_CFG_10G:
9167 bp->port.phy_addr = REG_RD(
9168 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9169 break;
9170 default:
9171 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9172 bp->port.link_config[0]);
9173 return;
9174 }
a2fbb9ea 9175 }
619c5cb6 9176 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 9177 /* mask what we support according to speed_cap_mask per configuration */
9178 for (idx = 0; idx < cfg_size; idx++) {
9179 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9180 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 9181 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 9182
a22f0788 9183 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9184 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 9185 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 9186
a22f0788 9187 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9188 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 9189 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 9190
a22f0788 9191 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9192 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 9193 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 9194
a22f0788 9195 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9196 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 9197 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 9198 SUPPORTED_1000baseT_Full);
a2fbb9ea 9199
a22f0788 9200 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9201 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 9202 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 9203
a22f0788 9204 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9205 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 9206 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9207
9208 }
a2fbb9ea 9209
a22f0788
YR		 9210 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9211 bp->port.supported[1]);
a2fbb9ea
ET		 9212}
9213
34f80b04 9214static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 9215{
a22f0788
YR		 9216 u32 link_config, idx, cfg_size = 0;
9217 bp->port.advertising[0] = 0;
9218 bp->port.advertising[1] = 0;
9219 switch (bp->link_params.num_phys) {
9220 case 1:
9221 case 2:
9222 cfg_size = 1;
9223 break;
9224 case 3:
9225 cfg_size = 2;
9226 break;
9227 }
9228 for (idx = 0; idx < cfg_size; idx++) {
9229 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9230 link_config = bp->port.link_config[idx];
9231 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 9232 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 9233 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9234 bp->link_params.req_line_speed[idx] =
9235 SPEED_AUTO_NEG;
9236 bp->port.advertising[idx] |=
9237 bp->port.supported[idx];
f85582f8
DK		 9238 } else {
9239 /* force 10G, no AN */
a22f0788
YR		 9240 bp->link_params.req_line_speed[idx] =
9241 SPEED_10000;
9242 bp->port.advertising[idx] |=
9243 (ADVERTISED_10000baseT_Full |
f85582f8 9244 ADVERTISED_FIBRE);
a22f0788 9245 continue;
f85582f8
DK		 9246 }
9247 break;
a2fbb9ea 9248
f85582f8 9249 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 9250 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9251 bp->link_params.req_line_speed[idx] =
9252 SPEED_10;
9253 bp->port.advertising[idx] |=
9254 (ADVERTISED_10baseT_Full |
f85582f8
DK		 9255 ADVERTISED_TP);
9256 } else {
754a2f52 9257 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9258 "Invalid link_config 0x%x"
9259 " speed_cap_mask 0x%x\n",
9260 link_config,
a22f0788 9261 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9262 return;
9263 }
9264 break;
a2fbb9ea 9265
f85582f8 9266 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 9267 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9268 bp->link_params.req_line_speed[idx] =
9269 SPEED_10;
9270 bp->link_params.req_duplex[idx] =
9271 DUPLEX_HALF;
9272 bp->port.advertising[idx] |=
9273 (ADVERTISED_10baseT_Half |
f85582f8
DK		 9274 ADVERTISED_TP);
9275 } else {
754a2f52 9276 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9277 "Invalid link_config 0x%x"
9278 " speed_cap_mask 0x%x\n",
9279 link_config,
9280 bp->link_params.speed_cap_mask[idx]);
9281 return;
9282 }
9283 break;
a2fbb9ea 9284
f85582f8
DK		 9285 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9286 if (bp->port.supported[idx] &
9287 SUPPORTED_100baseT_Full) {
a22f0788
YR		 9288 bp->link_params.req_line_speed[idx] =
9289 SPEED_100;
9290 bp->port.advertising[idx] |=
9291 (ADVERTISED_100baseT_Full |
f85582f8
DK		 9292 ADVERTISED_TP);
9293 } else {
754a2f52 9294 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9295 "Invalid link_config 0x%x"
9296 " speed_cap_mask 0x%x\n",
9297 link_config,
9298 bp->link_params.speed_cap_mask[idx]);
9299 return;
9300 }
9301 break;
a2fbb9ea 9302
f85582f8
DK		 9303 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9304 if (bp->port.supported[idx] &
9305 SUPPORTED_100baseT_Half) {
9306 bp->link_params.req_line_speed[idx] =
9307 SPEED_100;
9308 bp->link_params.req_duplex[idx] =
9309 DUPLEX_HALF;
a22f0788
YR		 9310 bp->port.advertising[idx] |=
9311 (ADVERTISED_100baseT_Half |
f85582f8
DK		 9312 ADVERTISED_TP);
9313 } else {
754a2f52 9314 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9315 "Invalid link_config 0x%x"
9316 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9317 link_config,
9318 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9319 return;
9320 }
9321 break;
a2fbb9ea 9322
f85582f8 9323 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 9324 if (bp->port.supported[idx] &
9325 SUPPORTED_1000baseT_Full) {
9326 bp->link_params.req_line_speed[idx] =
9327 SPEED_1000;
9328 bp->port.advertising[idx] |=
9329 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 9330 ADVERTISED_TP);
9331 } else {
754a2f52 9332 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9333 "Invalid link_config 0x%x"
9334 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9335 link_config,
9336 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9337 return;
9338 }
9339 break;
a2fbb9ea 9340
f85582f8 9341 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 9342 if (bp->port.supported[idx] &
9343 SUPPORTED_2500baseX_Full) {
9344 bp->link_params.req_line_speed[idx] =
9345 SPEED_2500;
9346 bp->port.advertising[idx] |=
9347 (ADVERTISED_2500baseX_Full |
34f80b04 9348 ADVERTISED_TP);
f85582f8 9349 } else {
754a2f52 9350 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9351 "Invalid link_config 0x%x"
9352 " speed_cap_mask 0x%x\n",
a22f0788 9353 link_config,
f85582f8
DK		 9354 bp->link_params.speed_cap_mask[idx]);
9355 return;
9356 }
9357 break;
a2fbb9ea 9358
f85582f8 9359 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 9360 if (bp->port.supported[idx] &
9361 SUPPORTED_10000baseT_Full) {
9362 bp->link_params.req_line_speed[idx] =
9363 SPEED_10000;
9364 bp->port.advertising[idx] |=
9365 (ADVERTISED_10000baseT_Full |
34f80b04 9366 ADVERTISED_FIBRE);
f85582f8 9367 } else {
754a2f52 9368 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9369 "Invalid link_config 0x%x"
9370 " speed_cap_mask 0x%x\n",
a22f0788 9371 link_config,
f85582f8
DK		 9372 bp->link_params.speed_cap_mask[idx]);
9373 return;
9374 }
9375 break;
3c9ada22
YR		 9376 case PORT_FEATURE_LINK_SPEED_20G:
9377 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 9378
3c9ada22 9379 break;
f85582f8 9380 default:
754a2f52
DK		 9381 BNX2X_ERR("NVRAM config error. "
9382 "BAD link speed link_config 0x%x\n",
9383 link_config);
f85582f8
DK		 9384 bp->link_params.req_line_speed[idx] =
9385 SPEED_AUTO_NEG;
9386 bp->port.advertising[idx] =
9387 bp->port.supported[idx];
9388 break;
9389 }
a2fbb9ea 9390
a22f0788 9391 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 9392 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 9393 if ((bp->link_params.req_flow_ctrl[idx] ==
9394 BNX2X_FLOW_CTRL_AUTO) &&
9395 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9396 bp->link_params.req_flow_ctrl[idx] =
9397 BNX2X_FLOW_CTRL_NONE;
9398 }
a2fbb9ea 9399
a22f0788
YR		 9400 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9401 " 0x%x advertising 0x%x\n",
9402 bp->link_params.req_line_speed[idx],
9403 bp->link_params.req_duplex[idx],
9404 bp->link_params.req_flow_ctrl[idx],
9405 bp->port.advertising[idx]);
9406 }
a2fbb9ea
ET		 9407}
9408
e665bfda
MC		 9409static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9410{
9411 mac_hi = cpu_to_be16(mac_hi);
9412 mac_lo = cpu_to_be32(mac_lo);
9413 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9414 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9415}
9416
34f80b04 9417static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 9418{
34f80b04 9419 int port = BP_PORT(bp);
589abe3a 9420 u32 config;
6f38ad93 9421 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 9422
c18487ee 9423 bp->link_params.bp = bp;
34f80b04 9424 bp->link_params.port = port;
c18487ee 9425
c18487ee 9426 bp->link_params.lane_config =
a2fbb9ea 9427 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 9428
a22f0788 9429 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 9430 SHMEM_RD(bp,
9431 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 9432 bp->link_params.speed_cap_mask[1] =
9433 SHMEM_RD(bp,
9434 dev_info.port_hw_config[port].speed_capability_mask2);
9435 bp->port.link_config[0] =
a2fbb9ea
ET		 9436 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9437
a22f0788
YR		 9438 bp->port.link_config[1] =
9439 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 9440
a22f0788
YR		 9441 bp->link_params.multi_phy_config =
9442 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 9443 /* If the device is capable of WoL, set the default state according
9444 * to the HW
9445 */
4d295db0 9446 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 9447 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9448 (config & PORT_FEATURE_WOL_ENABLED));
9449
f85582f8 9450 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 9451 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 9452 bp->link_params.lane_config,
a22f0788
YR		 9453 bp->link_params.speed_cap_mask[0],
9454 bp->port.link_config[0]);
a2fbb9ea 9455
a22f0788 9456 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 9457 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 9458 bnx2x_phy_probe(&bp->link_params);
c18487ee 9459 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 9460
9461 bnx2x_link_settings_requested(bp);
9462
01cd4528
EG		 9463 /*
9464 * If connected directly, work with the internal PHY, otherwise, work
9465 * with the external PHY
9466 */
b7737c9b
YR		 9467 ext_phy_config =
9468 SHMEM_RD(bp,
9469 dev_info.port_hw_config[port].external_phy_config);
9470 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 9471 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 9472 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 9473
9474 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9475 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9476 bp->mdio.prtad =
b7737c9b 9477 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 9478
9479 /*
9480 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9481 * In MF mode, it is set to cover self test cases
9482 */
9483 if (IS_MF(bp))
9484 bp->port.need_hw_lock = 1;
9485 else
9486 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9487 bp->common.shmem_base,
9488 bp->common.shmem2_base);
0793f83f 9489}
01cd4528 9490
b306f5ed 9491void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 9492{
7185bb33 9493#ifdef BCM_CNIC
bf61ee14 9494 int port = BP_PORT(bp);
bf61ee14 9495
2ba45142 9496 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 9497 drv_lic_key[port].max_iscsi_conn);
2ba45142 9498
b306f5ed 9499 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 9500 bp->cnic_eth_dev.max_iscsi_conn =
9501 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9502 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9503
b306f5ed
DK		 9504 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
9505 bp->cnic_eth_dev.max_iscsi_conn);
9506
9507 /*
9508 * If maximum allowed number of connections is zero -
9509 * disable the feature.
9510 */
9511 if (!bp->cnic_eth_dev.max_iscsi_conn)
9512 bp->flags |= NO_ISCSI_FLAG;
7185bb33
DK		 9513#else
9514 bp->flags |= NO_ISCSI_FLAG;
9515#endif
b306f5ed
DK		 9516}
9517
9518static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
9519{
7185bb33 9520#ifdef BCM_CNIC
b306f5ed
DK		 9521 int port = BP_PORT(bp);
9522 int func = BP_ABS_FUNC(bp);
9523
9524 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9525 drv_lic_key[port].max_fcoe_conn);
9526
9527 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 9528 bp->cnic_eth_dev.max_fcoe_conn =
9529 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9530 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9531
bf61ee14
VZ		 9532 /* Read the WWN: */
9533 if (!IS_MF(bp)) {
9534 /* Port info */
9535 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9536 SHMEM_RD(bp,
9537 dev_info.port_hw_config[port].
9538 fcoe_wwn_port_name_upper);
9539 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9540 SHMEM_RD(bp,
9541 dev_info.port_hw_config[port].
9542 fcoe_wwn_port_name_lower);
9543
9544 /* Node info */
9545 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9546 SHMEM_RD(bp,
9547 dev_info.port_hw_config[port].
9548 fcoe_wwn_node_name_upper);
9549 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9550 SHMEM_RD(bp,
9551 dev_info.port_hw_config[port].
9552 fcoe_wwn_node_name_lower);
9553 } else if (!IS_MF_SD(bp)) {
9554 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9555
9556 /*
9557 * Read the WWN info only if the FCoE feature is enabled for
9558 * this function.
9559 */
9560 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9561 /* Port info */
9562 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9563 MF_CFG_RD(bp, func_ext_config[func].
9564 fcoe_wwn_port_name_upper);
9565 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9566 MF_CFG_RD(bp, func_ext_config[func].
9567 fcoe_wwn_port_name_lower);
9568
9569 /* Node info */
9570 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9571 MF_CFG_RD(bp, func_ext_config[func].
9572 fcoe_wwn_node_name_upper);
9573 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9574 MF_CFG_RD(bp, func_ext_config[func].
9575 fcoe_wwn_node_name_lower);
9576 }
9577 }
9578
b306f5ed 9579 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 9580
bf61ee14
VZ		 9581 /*
9582 * If maximum allowed number of connections is zero -
2ba45142
VZ		 9583 * disable the feature.
9584 */
2ba45142
VZ		 9585 if (!bp->cnic_eth_dev.max_fcoe_conn)
9586 bp->flags |= NO_FCOE_FLAG;
7185bb33
DK		 9587#else
9588 bp->flags |= NO_FCOE_FLAG;
9589#endif
2ba45142 9590}
b306f5ed
DK		 9591
9592static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9593{
9594 /*
9595 * iSCSI may be dynamically disabled but reading
9596 * info here we will decrease memory usage by driver
9597 * if the feature is disabled for good
9598 */
9599 bnx2x_get_iscsi_info(bp);
9600 bnx2x_get_fcoe_info(bp);
9601}
2ba45142 9602
0793f83f
DK		 9603static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9604{
9605 u32 val, val2;
9606 int func = BP_ABS_FUNC(bp);
9607 int port = BP_PORT(bp);
2ba45142
VZ		 9608#ifdef BCM_CNIC
9609 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9610 u8 *fip_mac = bp->fip_mac;
9611#endif
0793f83f 9612
619c5cb6
VZ		 9613 /* Zero primary MAC configuration */
9614 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9615
0793f83f
DK		 9616 if (BP_NOMCP(bp)) {
9617 BNX2X_ERROR("warning: random MAC workaround active\n");
9618 random_ether_addr(bp->dev->dev_addr);
9619 } else if (IS_MF(bp)) {
9620 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9621 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9622 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9623 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9624 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 9625
9626#ifdef BCM_CNIC
614c76df
DK		 9627 /*
9628 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142
VZ		 9629 * FCoE MAC then the appropriate feature should be disabled.
9630 */
0793f83f
DK		 9631 if (IS_MF_SI(bp)) {
9632 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9633 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9634 val2 = MF_CFG_RD(bp, func_ext_config[func].
9635 iscsi_mac_addr_upper);
9636 val = MF_CFG_RD(bp, func_ext_config[func].
9637 iscsi_mac_addr_lower);
2ba45142 9638 bnx2x_set_mac_buf(iscsi_mac, val, val2);
0f9dad10
JP		 9639 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9640 iscsi_mac);
2ba45142
VZ		 9641 } else
9642 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9643
9644 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9645 val2 = MF_CFG_RD(bp, func_ext_config[func].
9646 fcoe_mac_addr_upper);
9647 val = MF_CFG_RD(bp, func_ext_config[func].
9648 fcoe_mac_addr_lower);
2ba45142 9649 bnx2x_set_mac_buf(fip_mac, val, val2);
614c76df 9650 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
0f9dad10 9651 fip_mac);
2ba45142 9652
2ba45142
VZ		 9653 } else
9654 bp->flags |= NO_FCOE_FLAG;
614c76df
DK		 9655 } else { /* SD mode */
9656 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) {
9657 /* use primary mac as iscsi mac */
9658 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
9659 /* Zero primary MAC configuration */
9660 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9661
9662 BNX2X_DEV_INFO("SD ISCSI MODE\n");
9663 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9664 iscsi_mac);
9665 }
0793f83f 9666 }
37b091ba 9667#endif
0793f83f
DK		 9668 } else {
9669 /* in SF read MACs from port configuration */
9670 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9671 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9672 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9673
9674#ifdef BCM_CNIC
9675 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9676 iscsi_mac_upper);
9677 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9678 iscsi_mac_lower);
2ba45142 9679 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 9680
9681 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9682 fcoe_fip_mac_upper);
9683 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9684 fcoe_fip_mac_lower);
9685 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 9686#endif
9687 }
9688
9689 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9690 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9691
ec6ba945 9692#ifdef BCM_CNIC
c03bd39c
VZ		 9693 /* Set the FCoE MAC in MF_SD mode */
9694 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9695 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
426b9241
DK		 9696
9697 /* Disable iSCSI if MAC configuration is
9698 * invalid.
9699 */
9700 if (!is_valid_ether_addr(iscsi_mac)) {
9701 bp->flags |= NO_ISCSI_FLAG;
9702 memset(iscsi_mac, 0, ETH_ALEN);
9703 }
9704
9705 /* Disable FCoE if MAC configuration is
9706 * invalid.
9707 */
9708 if (!is_valid_ether_addr(fip_mac)) {
9709 bp->flags |= NO_FCOE_FLAG;
9710 memset(bp->fip_mac, 0, ETH_ALEN);
9711 }
ec6ba945 9712#endif
619c5cb6 9713
614c76df 9714 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6
VZ		 9715 dev_err(&bp->pdev->dev,
9716 "bad Ethernet MAC address configuration: "
0f9dad10 9717 "%pM, change it manually before bringing up "
619c5cb6 9718 "the appropriate network interface\n",
0f9dad10 9719 bp->dev->dev_addr);
34f80b04
EG		 9720}
9721
9722static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9723{
0793f83f 9724 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 9725 int vn;
0793f83f 9726 u32 val = 0;
34f80b04 9727 int rc = 0;
a2fbb9ea 9728
34f80b04 9729 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 9730
6383c0b3
AE		 9731 /*
9732 * initialize IGU parameters
9733 */
f2e0899f
DK		 9734 if (CHIP_IS_E1x(bp)) {
9735 bp->common.int_block = INT_BLOCK_HC;
9736
9737 bp->igu_dsb_id = DEF_SB_IGU_ID;
9738 bp->igu_base_sb = 0;
f2e0899f
DK		 9739 } else {
9740 bp->common.int_block = INT_BLOCK_IGU;
7a06a122
DK		 9741
9742 /* do not allow device reset during IGU info preocessing */
9743 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9744
f2e0899f 9745 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 9746
9747 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9748 int tout = 5000;
9749
9750 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9751
9752 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9753 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9754 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9755
9756 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9757 tout--;
9758 usleep_range(1000, 1000);
9759 }
9760
9761 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9762 dev_err(&bp->pdev->dev,
9763 "FORCING Normal Mode failed!!!\n");
9764 return -EPERM;
9765 }
9766 }
9767
f2e0899f 9768 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 9769 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 9770 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9771 } else
619c5cb6 9772 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 9773
f2e0899f
DK		 9774 bnx2x_get_igu_cam_info(bp);
9775
7a06a122 9776 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
f2e0899f 9777 }
619c5cb6
VZ		 9778
9779 /*
9780 * set base FW non-default (fast path) status block id, this value is
9781 * used to initialize the fw_sb_id saved on the fp/queue structure to
9782 * determine the id used by the FW.
9783 */
9784 if (CHIP_IS_E1x(bp))
9785 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9786 else /*
9787 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9788 * the same queue are indicated on the same IGU SB). So we prefer
9789 * FW and IGU SBs to be the same value.
9790 */
9791 bp->base_fw_ndsb = bp->igu_base_sb;
9792
9793 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9794 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9795 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 9796
9797 /*
9798 * Initialize MF configuration
9799 */
523224a3 9800
fb3bff17
DK		 9801 bp->mf_ov = 0;
9802 bp->mf_mode = 0;
3395a033 9803 vn = BP_VN(bp);
0793f83f 9804
f2e0899f 9805 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 9806 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9807 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9808 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9809
f2e0899f
DK		 9810 if (SHMEM2_HAS(bp, mf_cfg_addr))
9811 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9812 else
9813 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 9814 offsetof(struct shmem_region, func_mb) +
9815 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 9816 /*
9817 * get mf configuration:
25985edc 9818 * 1. existence of MF configuration
0793f83f
DK		 9819 * 2. MAC address must be legal (check only upper bytes)
9820 * for Switch-Independent mode;
9821 * OVLAN must be legal for Switch-Dependent mode
9822 * 3. SF_MODE configures specific MF mode
9823 */
9824 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9825 /* get mf configuration */
9826 val = SHMEM_RD(bp,
9827 dev_info.shared_feature_config.config);
9828 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9829
9830 switch (val) {
9831 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9832 val = MF_CFG_RD(bp, func_mf_config[func].
9833 mac_upper);
9834 /* check for legal mac (upper bytes)*/
9835 if (val != 0xffff) {
9836 bp->mf_mode = MULTI_FUNCTION_SI;
9837 bp->mf_config[vn] = MF_CFG_RD(bp,
9838 func_mf_config[func].config);
9839 } else
619c5cb6
VZ		 9840 BNX2X_DEV_INFO("illegal MAC address "
9841 "for SI\n");
0793f83f
DK		 9842 break;
9843 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9844 /* get OV configuration */
9845 val = MF_CFG_RD(bp,
9846 func_mf_config[FUNC_0].e1hov_tag);
9847 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9848
9849 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9850 bp->mf_mode = MULTI_FUNCTION_SD;
9851 bp->mf_config[vn] = MF_CFG_RD(bp,
9852 func_mf_config[func].config);
9853 } else
754a2f52 9854 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f
DK		 9855 break;
9856 default:
9857 /* Unknown configuration: reset mf_config */
9858 bp->mf_config[vn] = 0;
754a2f52 9859 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
0793f83f
DK		 9860 }
9861 }
a2fbb9ea 9862
2691d51d 9863 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 9864 IS_MF(bp) ? "multi" : "single");
2691d51d 9865
0793f83f
DK		 9866 switch (bp->mf_mode) {
9867 case MULTI_FUNCTION_SD:
9868 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9869 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 9870 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 9871 bp->mf_ov = val;
619c5cb6
VZ		 9872 bp->path_has_ovlan = true;
9873
9874 BNX2X_DEV_INFO("MF OV for func %d is %d "
9875 "(0x%04x)\n", func, bp->mf_ov,
9876 bp->mf_ov);
2691d51d 9877 } else {
619c5cb6
VZ		 9878 dev_err(&bp->pdev->dev,
9879 "No valid MF OV for func %d, "
9880 "aborting\n", func);
9881 return -EPERM;
34f80b04 9882 }
0793f83f
DK		 9883 break;
9884 case MULTI_FUNCTION_SI:
9885 BNX2X_DEV_INFO("func %d is in MF "
9886 "switch-independent mode\n", func);
9887 break;
9888 default:
9889 if (vn) {
619c5cb6
VZ		 9890 dev_err(&bp->pdev->dev,
9891 "VN %d is in a single function mode, "
9892 "aborting\n", vn);
9893 return -EPERM;
2691d51d 9894 }
0793f83f 9895 break;
34f80b04 9896 }
0793f83f 9897
619c5cb6
VZ		 9898 /* check if other port on the path needs ovlan:
9899 * Since MF configuration is shared between ports
9900 * Possible mixed modes are only
9901 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9902 */
9903 if (CHIP_MODE_IS_4_PORT(bp) &&
9904 !bp->path_has_ovlan &&
9905 !IS_MF(bp) &&
9906 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9907 u8 other_port = !BP_PORT(bp);
9908 u8 other_func = BP_PATH(bp) + 2*other_port;
9909 val = MF_CFG_RD(bp,
9910 func_mf_config[other_func].e1hov_tag);
9911 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9912 bp->path_has_ovlan = true;
9913 }
34f80b04 9914 }
a2fbb9ea 9915
f2e0899f
DK		 9916 /* adjust igu_sb_cnt to MF for E1x */
9917 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 9918 bp->igu_sb_cnt /= E1HVN_MAX;
9919
619c5cb6
VZ		 9920 /* port info */
9921 bnx2x_get_port_hwinfo(bp);
f2e0899f 9922
0793f83f
DK		 9923 /* Get MAC addresses */
9924 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 9925
2ba45142 9926 bnx2x_get_cnic_info(bp);
2ba45142 9927
619c5cb6
VZ		 9928 /* Get current FW pulse sequence */
9929 if (!BP_NOMCP(bp)) {
9930 int mb_idx = BP_FW_MB_IDX(bp);
9931
9932 bp->fw_drv_pulse_wr_seq =
9933 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9934 DRV_PULSE_SEQ_MASK);
9935 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9936 }
9937
34f80b04
EG		 9938 return rc;
9939}
9940
34f24c7f
VZ		 9941static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9942{
9943 int cnt, i, block_end, rodi;
fcdf95cb 9944 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 9945 char str_id_reg[VENDOR_ID_LEN+1];
9946 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 9947 char *vpd_data;
9948 char *vpd_extended_data = NULL;
34f24c7f
VZ		 9949 u8 len;
9950
fcdf95cb 9951 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 9952 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9953
9954 if (cnt < BNX2X_VPD_LEN)
9955 goto out_not_found;
9956
fcdf95cb
BW		 9957 /* VPD RO tag should be first tag after identifier string, hence
9958 * we should be able to find it in first BNX2X_VPD_LEN chars
9959 */
9960 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 9961 PCI_VPD_LRDT_RO_DATA);
9962 if (i < 0)
9963 goto out_not_found;
9964
34f24c7f 9965 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 9966 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 9967
9968 i += PCI_VPD_LRDT_TAG_SIZE;
9969
fcdf95cb
BW		 9970 if (block_end > BNX2X_VPD_LEN) {
9971 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
9972 if (vpd_extended_data == NULL)
9973 goto out_not_found;
9974
9975 /* read rest of vpd image into vpd_extended_data */
9976 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
9977 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
9978 block_end - BNX2X_VPD_LEN,
9979 vpd_extended_data + BNX2X_VPD_LEN);
9980 if (cnt < (block_end - BNX2X_VPD_LEN))
9981 goto out_not_found;
9982 vpd_data = vpd_extended_data;
9983 } else
9984 vpd_data = vpd_start;
9985
9986 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 9987
9988 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9989 PCI_VPD_RO_KEYWORD_MFR_ID);
9990 if (rodi < 0)
9991 goto out_not_found;
9992
9993 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9994
9995 if (len != VENDOR_ID_LEN)
9996 goto out_not_found;
9997
9998 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9999
10000 /* vendor specific info */
10001 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10002 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10003 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10004 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
10005
10006 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10007 PCI_VPD_RO_KEYWORD_VENDOR0);
10008 if (rodi >= 0) {
10009 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10010
10011 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10012
10013 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
10014 memcpy(bp->fw_ver, &vpd_data[rodi], len);
10015 bp->fw_ver[len] = ' ';
10016 }
10017 }
fcdf95cb 10018 kfree(vpd_extended_data);
34f24c7f
VZ		 10019 return;
10020 }
10021out_not_found:
fcdf95cb 10022 kfree(vpd_extended_data);
34f24c7f
VZ		 10023 return;
10024}
10025
619c5cb6
VZ		 10026static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10027{
10028 u32 flags = 0;
10029
10030 if (CHIP_REV_IS_FPGA(bp))
10031 SET_FLAGS(flags, MODE_FPGA);
10032 else if (CHIP_REV_IS_EMUL(bp))
10033 SET_FLAGS(flags, MODE_EMUL);
10034 else
10035 SET_FLAGS(flags, MODE_ASIC);
10036
10037 if (CHIP_MODE_IS_4_PORT(bp))
10038 SET_FLAGS(flags, MODE_PORT4);
10039 else
10040 SET_FLAGS(flags, MODE_PORT2);
10041
10042 if (CHIP_IS_E2(bp))
10043 SET_FLAGS(flags, MODE_E2);
10044 else if (CHIP_IS_E3(bp)) {
10045 SET_FLAGS(flags, MODE_E3);
10046 if (CHIP_REV(bp) == CHIP_REV_Ax)
10047 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 10048 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10049 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 10050 }
10051
10052 if (IS_MF(bp)) {
10053 SET_FLAGS(flags, MODE_MF);
10054 switch (bp->mf_mode) {
10055 case MULTI_FUNCTION_SD:
10056 SET_FLAGS(flags, MODE_MF_SD);
10057 break;
10058 case MULTI_FUNCTION_SI:
10059 SET_FLAGS(flags, MODE_MF_SI);
10060 break;
10061 }
10062 } else
10063 SET_FLAGS(flags, MODE_SF);
10064
10065#if defined(__LITTLE_ENDIAN)
10066 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10067#else /*(__BIG_ENDIAN)*/
10068 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10069#endif
10070 INIT_MODE_FLAGS(bp) = flags;
10071}
10072
34f80b04
EG		 10073static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10074{
f2e0899f 10075 int func;
87942b46 10076 int timer_interval;
34f80b04
EG		 10077 int rc;
10078
34f80b04 10079 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 10080 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 10081 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 10082#ifdef BCM_CNIC
10083 mutex_init(&bp->cnic_mutex);
10084#endif
a2fbb9ea 10085
1cf167f2 10086 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 10087 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 10088 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
34f80b04 10089 rc = bnx2x_get_hwinfo(bp);
619c5cb6
VZ		 10090 if (rc)
10091 return rc;
34f80b04 10092
619c5cb6
VZ		 10093 bnx2x_set_modes_bitmap(bp);
10094
10095 rc = bnx2x_alloc_mem_bp(bp);
10096 if (rc)
10097 return rc;
523224a3 10098
34f24c7f 10099 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 10100
10101 func = BP_FUNC(bp);
10102
34f80b04
EG		 10103 /* need to reset chip if undi was active */
10104 if (!BP_NOMCP(bp))
10105 bnx2x_undi_unload(bp);
10106
0735f2fc
DK		 10107 /* init fw_seq after undi_unload! */
10108 if (!BP_NOMCP(bp)) {
10109 bp->fw_seq =
10110 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10111 DRV_MSG_SEQ_NUMBER_MASK);
10112 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10113 }
10114
34f80b04 10115 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 10116 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 10117
10118 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 10119 dev_err(&bp->pdev->dev, "MCP disabled, "
10120 "must load devices in order!\n");
34f80b04 10121
555f6c78 10122 bp->multi_mode = multi_mode;
555f6c78 10123
614c76df
DK		 10124 bp->disable_tpa = disable_tpa;
10125
10126#ifdef BCM_CNIC
10127 bp->disable_tpa |= IS_MF_ISCSI_SD(bp);
10128#endif
10129
7a9b2557 10130 /* Set TPA flags */
614c76df 10131 if (bp->disable_tpa) {
7a9b2557
VZ		 10132 bp->flags &= ~TPA_ENABLE_FLAG;
10133 bp->dev->features &= ~NETIF_F_LRO;
10134 } else {
10135 bp->flags |= TPA_ENABLE_FLAG;
10136 bp->dev->features |= NETIF_F_LRO;
10137 }
10138
a18f5128
EG		 10139 if (CHIP_IS_E1(bp))
10140 bp->dropless_fc = 0;
10141 else
10142 bp->dropless_fc = dropless_fc;
10143
8d5726c4 10144 bp->mrrs = mrrs;
7a9b2557 10145
34f80b04 10146 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 10147
7d323bfd 10148 /* make sure that the numbers are in the right granularity */
523224a3
DK		 10149 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10150 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 10151
87942b46
EG		 10152 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
10153 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 10154
10155 init_timer(&bp->timer);
10156 bp->timer.expires = jiffies + bp->current_interval;
10157 bp->timer.data = (unsigned long) bp;
10158 bp->timer.function = bnx2x_timer;
10159
785b9b1a 10160 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 10161 bnx2x_dcbx_init_params(bp);
10162
619c5cb6
VZ		 10163#ifdef BCM_CNIC
10164 if (CHIP_IS_E1x(bp))
10165 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10166 else
10167 bp->cnic_base_cl_id = FP_SB_MAX_E2;
10168#endif
10169
6383c0b3
AE		 10170 /* multiple tx priority */
10171 if (CHIP_IS_E1x(bp))
10172 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
10173 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10174 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
10175 if (CHIP_IS_E3B0(bp))
10176 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
10177
34f80b04 10178 return rc;
a2fbb9ea
ET		 10179}
10180
a2fbb9ea 10181
de0c62db
DK		 10182/****************************************************************************
10183* General service functions
10184****************************************************************************/
a2fbb9ea 10185
619c5cb6
VZ		 10186/*
10187 * net_device service functions
10188 */
10189
bb2a0f7a 10190/* called with rtnl_lock */
a2fbb9ea
ET		 10191static int bnx2x_open(struct net_device *dev)
10192{
10193 struct bnx2x *bp = netdev_priv(dev);
c9ee9206
VZ		 10194 bool global = false;
10195 int other_engine = BP_PATH(bp) ? 0 : 1;
10196 u32 other_load_counter, load_counter;
a2fbb9ea 10197
6eccabb3
EG		 10198 netif_carrier_off(dev);
10199
a2fbb9ea
ET		 10200 bnx2x_set_power_state(bp, PCI_D0);
10201
c9ee9206
VZ		 10202 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
10203 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
10204
10205 /*
10206 * If parity had happen during the unload, then attentions
10207 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10208 * want the first function loaded on the current engine to
10209 * complete the recovery.
10210 */
10211 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10212 bnx2x_chk_parity_attn(bp, &global, true))
72fd0718 10213 do {
c9ee9206
VZ		 10214 /*
10215 * If there are attentions and they are in a global
10216 * blocks, set the GLOBAL_RESET bit regardless whether
10217 * it will be this function that will complete the
10218 * recovery or not.
72fd0718 10219 */
c9ee9206
VZ		 10220 if (global)
10221 bnx2x_set_reset_global(bp);
72fd0718 10222
c9ee9206
VZ		 10223 /*
10224 * Only the first function on the current engine should
10225 * try to recover in open. In case of attentions in
10226 * global blocks only the first in the chip should try
10227 * to recover.
72fd0718 10228 */
c9ee9206
VZ		 10229 if ((!load_counter &&
10230 (!global || !other_load_counter)) &&
10231 bnx2x_trylock_leader_lock(bp) &&
10232 !bnx2x_leader_reset(bp)) {
10233 netdev_info(bp->dev, "Recovered in open\n");
72fd0718
VZ		 10234 break;
10235 }
10236
c9ee9206 10237 /* recovery has failed... */
72fd0718 10238 bnx2x_set_power_state(bp, PCI_D3hot);
c9ee9206 10239 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 10240
c9ee9206 10241 netdev_err(bp->dev, "Recovery flow hasn't been properly"
72fd0718
VZ		 10242 " completed yet. Try again later. If u still see this"
10243 " message after a few retries then power cycle is"
c9ee9206 10244 " required.\n");
72fd0718
VZ		 10245
10246 return -EAGAIN;
10247 } while (0);
72fd0718
VZ		 10248
10249 bp->recovery_state = BNX2X_RECOVERY_DONE;
bb2a0f7a 10250 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 10251}
10252
bb2a0f7a 10253/* called with rtnl_lock */
8304859a 10254int bnx2x_close(struct net_device *dev)
a2fbb9ea 10255{
a2fbb9ea
ET		 10256 struct bnx2x *bp = netdev_priv(dev);
10257
10258 /* Unload the driver, release IRQs */
bb2a0f7a 10259 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
c9ee9206
VZ		 10260
10261 /* Power off */
d3dbfee0 10262 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 10263
10264 return 0;
10265}
10266
619c5cb6
VZ		 10267static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
10268 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 10269{
619c5cb6
VZ		 10270 int mc_count = netdev_mc_count(bp->dev);
10271 struct bnx2x_mcast_list_elem *mc_mac =
10272 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
10273 struct netdev_hw_addr *ha;
6e30dd4e 10274
619c5cb6
VZ		 10275 if (!mc_mac)
10276 return -ENOMEM;
6e30dd4e 10277
619c5cb6 10278 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 10279
619c5cb6
VZ		 10280 netdev_for_each_mc_addr(ha, bp->dev) {
10281 mc_mac->mac = bnx2x_mc_addr(ha);
10282 list_add_tail(&mc_mac->link, &p->mcast_list);
10283 mc_mac++;
6e30dd4e 10284 }
619c5cb6
VZ		 10285
10286 p->mcast_list_len = mc_count;
10287
10288 return 0;
6e30dd4e
VZ		 10289}
10290
619c5cb6
VZ		 10291static inline void bnx2x_free_mcast_macs_list(
10292 struct bnx2x_mcast_ramrod_params *p)
10293{
10294 struct bnx2x_mcast_list_elem *mc_mac =
10295 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
10296 link);
10297
10298 WARN_ON(!mc_mac);
10299 kfree(mc_mac);
10300}
10301
10302/**
10303 * bnx2x_set_uc_list - configure a new unicast MACs list.
10304 *
10305 * @bp: driver handle
6e30dd4e 10306 *
619c5cb6 10307 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 10308 */
619c5cb6 10309static inline int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 10310{
619c5cb6 10311 int rc;
6e30dd4e 10312 struct net_device *dev = bp->dev;
6e30dd4e 10313 struct netdev_hw_addr *ha;
619c5cb6
VZ		 10314 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
10315 unsigned long ramrod_flags = 0;
6e30dd4e 10316
619c5cb6
VZ		 10317 /* First schedule a cleanup up of old configuration */
10318 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
10319 if (rc < 0) {
10320 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10321 return rc;
10322 }
6e30dd4e
VZ		 10323
10324 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 10325 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10326 BNX2X_UC_LIST_MAC, &ramrod_flags);
10327 if (rc < 0) {
10328 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10329 rc);
10330 return rc;
6e30dd4e
VZ		 10331 }
10332 }
10333
619c5cb6
VZ		 10334 /* Execute the pending commands */
10335 __set_bit(RAMROD_CONT, &ramrod_flags);
10336 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10337 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 10338}
10339
619c5cb6 10340static inline int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 10341{
619c5cb6
VZ		 10342 struct net_device *dev = bp->dev;
10343 struct bnx2x_mcast_ramrod_params rparam = {0};
10344 int rc = 0;
6e30dd4e 10345
619c5cb6 10346 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 10347
619c5cb6
VZ		 10348 /* first, clear all configured multicast MACs */
10349 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10350 if (rc < 0) {
10351 BNX2X_ERR("Failed to clear multicast "
10352 "configuration: %d\n", rc);
10353 return rc;
10354 }
6e30dd4e 10355
619c5cb6
VZ		 10356 /* then, configure a new MACs list */
10357 if (netdev_mc_count(dev)) {
10358 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10359 if (rc) {
10360 BNX2X_ERR("Failed to create multicast MACs "
10361 "list: %d\n", rc);
10362 return rc;
10363 }
6e30dd4e 10364
619c5cb6
VZ		 10365 /* Now add the new MACs */
10366 rc = bnx2x_config_mcast(bp, &rparam,
10367 BNX2X_MCAST_CMD_ADD);
10368 if (rc < 0)
10369 BNX2X_ERR("Failed to set a new multicast "
10370 "configuration: %d\n", rc);
6e30dd4e 10371
619c5cb6
VZ		 10372 bnx2x_free_mcast_macs_list(&rparam);
10373 }
6e30dd4e 10374
619c5cb6 10375 return rc;
6e30dd4e
VZ		 10376}
10377
6e30dd4e 10378
619c5cb6 10379/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 10380void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 10381{
10382 struct bnx2x *bp = netdev_priv(dev);
10383 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 10384
10385 if (bp->state != BNX2X_STATE_OPEN) {
10386 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10387 return;
10388 }
10389
619c5cb6 10390 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 10391
10392 if (dev->flags & IFF_PROMISC)
10393 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 10394 else if ((dev->flags & IFF_ALLMULTI) ||
10395 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10396 CHIP_IS_E1(bp)))
34f80b04 10397 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 10398 else {
10399 /* some multicasts */
619c5cb6 10400 if (bnx2x_set_mc_list(bp) < 0)
6e30dd4e 10401 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 10402
619c5cb6 10403 if (bnx2x_set_uc_list(bp) < 0)
6e30dd4e 10404 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 10405 }
10406
10407 bp->rx_mode = rx_mode;
614c76df
DK		 10408#ifdef BCM_CNIC
10409 /* handle ISCSI SD mode */
10410 if (IS_MF_ISCSI_SD(bp))
10411 bp->rx_mode = BNX2X_RX_MODE_NONE;
10412#endif
619c5cb6
VZ		 10413
10414 /* Schedule the rx_mode command */
10415 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10416 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10417 return;
10418 }
10419
34f80b04
EG		 10420 bnx2x_set_storm_rx_mode(bp);
10421}
10422
c18487ee 10423/* called with rtnl_lock */
01cd4528
EG		 10424static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10425 int devad, u16 addr)
a2fbb9ea 10426{
01cd4528
EG		 10427 struct bnx2x *bp = netdev_priv(netdev);
10428 u16 value;
10429 int rc;
a2fbb9ea 10430
01cd4528
EG		 10431 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10432 prtad, devad, addr);
a2fbb9ea 10433
01cd4528
EG		 10434 /* The HW expects different devad if CL22 is used */
10435 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 10436
01cd4528 10437 bnx2x_acquire_phy_lock(bp);
e10bc84d 10438 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 10439 bnx2x_release_phy_lock(bp);
10440 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 10441
01cd4528
EG		 10442 if (!rc)
10443 rc = value;
10444 return rc;
10445}
a2fbb9ea 10446
01cd4528
EG		 10447/* called with rtnl_lock */
10448static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10449 u16 addr, u16 value)
10450{
10451 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 10452 int rc;
10453
10454 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10455 " value 0x%x\n", prtad, devad, addr, value);
10456
01cd4528
EG		 10457 /* The HW expects different devad if CL22 is used */
10458 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 10459
01cd4528 10460 bnx2x_acquire_phy_lock(bp);
e10bc84d 10461 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 10462 bnx2x_release_phy_lock(bp);
10463 return rc;
10464}
c18487ee 10465
01cd4528
EG		 10466/* called with rtnl_lock */
10467static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10468{
10469 struct bnx2x *bp = netdev_priv(dev);
10470 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 10471
01cd4528
EG		 10472 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10473 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 10474
01cd4528
EG		 10475 if (!netif_running(dev))
10476 return -EAGAIN;
10477
10478 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 10479}
10480
257ddbda 10481#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 10482static void poll_bnx2x(struct net_device *dev)
10483{
10484 struct bnx2x *bp = netdev_priv(dev);
10485
10486 disable_irq(bp->pdev->irq);
10487 bnx2x_interrupt(bp->pdev->irq, dev);
10488 enable_irq(bp->pdev->irq);
10489}
10490#endif
10491
614c76df
DK		 10492static int bnx2x_validate_addr(struct net_device *dev)
10493{
10494 struct bnx2x *bp = netdev_priv(dev);
10495
10496 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr))
10497 return -EADDRNOTAVAIL;
10498 return 0;
10499}
10500
c64213cd
SH		 10501static const struct net_device_ops bnx2x_netdev_ops = {
10502 .ndo_open = bnx2x_open,
10503 .ndo_stop = bnx2x_close,
10504 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 10505 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 10506 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 10507 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 10508 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 10509 .ndo_do_ioctl = bnx2x_ioctl,
10510 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 10511 .ndo_fix_features = bnx2x_fix_features,
10512 .ndo_set_features = bnx2x_set_features,
c64213cd 10513 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 10514#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 10515 .ndo_poll_controller = poll_bnx2x,
10516#endif
6383c0b3
AE		 10517 .ndo_setup_tc = bnx2x_setup_tc,
10518
bf61ee14
VZ		 10519#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10520 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10521#endif
c64213cd
SH		 10522};
10523
619c5cb6
VZ		 10524static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10525{
10526 struct device *dev = &bp->pdev->dev;
10527
10528 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10529 bp->flags |= USING_DAC_FLAG;
10530 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10531 dev_err(dev, "dma_set_coherent_mask failed, "
10532 "aborting\n");
10533 return -EIO;
10534 }
10535 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10536 dev_err(dev, "System does not support DMA, aborting\n");
10537 return -EIO;
10538 }
10539
10540 return 0;
10541}
10542
34f80b04 10543static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
619c5cb6
VZ		 10544 struct net_device *dev,
10545 unsigned long board_type)
a2fbb9ea
ET		 10546{
10547 struct bnx2x *bp;
10548 int rc;
65087cfe
AE		 10549 bool chip_is_e1x = (board_type == BCM57710 ||
10550 board_type == BCM57711 ||
10551 board_type == BCM57711E);
a2fbb9ea
ET		 10552
10553 SET_NETDEV_DEV(dev, &pdev->dev);
10554 bp = netdev_priv(dev);
10555
34f80b04
EG		 10556 bp->dev = dev;
10557 bp->pdev = pdev;
a2fbb9ea 10558 bp->flags = 0;
f2e0899f 10559 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 10560
10561 rc = pci_enable_device(pdev);
10562 if (rc) {
cdaa7cb8
VZ		 10563 dev_err(&bp->pdev->dev,
10564 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 10565 goto err_out;
10566 }
10567
10568 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10569 dev_err(&bp->pdev->dev,
10570 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 10571 rc = -ENODEV;
10572 goto err_out_disable;
10573 }
10574
10575 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10576 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10577 " base address, aborting\n");
a2fbb9ea
ET		 10578 rc = -ENODEV;
10579 goto err_out_disable;
10580 }
10581
34f80b04
EG		 10582 if (atomic_read(&pdev->enable_cnt) == 1) {
10583 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10584 if (rc) {
cdaa7cb8
VZ		 10585 dev_err(&bp->pdev->dev,
10586 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 10587 goto err_out_disable;
10588 }
a2fbb9ea 10589
34f80b04
EG		 10590 pci_set_master(pdev);
10591 pci_save_state(pdev);
10592 }
a2fbb9ea
ET		 10593
10594 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10595 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 10596 dev_err(&bp->pdev->dev,
10597 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 10598 rc = -EIO;
10599 goto err_out_release;
10600 }
10601
77c98e6a
JM		 10602 if (!pci_is_pcie(pdev)) {
10603 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 10604 rc = -EIO;
10605 goto err_out_release;
10606 }
10607
619c5cb6
VZ		 10608 rc = bnx2x_set_coherency_mask(bp);
10609 if (rc)
a2fbb9ea 10610 goto err_out_release;
a2fbb9ea 10611
34f80b04
EG		 10612 dev->mem_start = pci_resource_start(pdev, 0);
10613 dev->base_addr = dev->mem_start;
10614 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 10615
10616 dev->irq = pdev->irq;
10617
275f165f 10618 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 10619 if (!bp->regview) {
cdaa7cb8
VZ		 10620 dev_err(&bp->pdev->dev,
10621 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 10622 rc = -ENOMEM;
10623 goto err_out_release;
10624 }
10625
a2fbb9ea
ET		 10626 bnx2x_set_power_state(bp, PCI_D0);
10627
34f80b04
EG		 10628 /* clean indirect addresses */
10629 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10630 PCICFG_VENDOR_ID_OFFSET);
a5c53dbc
DK		 10631 /*
10632 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 10633 * is not used by the driver.
10634 */
10635 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10636 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10637 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10638 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
a5c53dbc 10639
65087cfe 10640 if (chip_is_e1x) {
a5c53dbc
DK		 10641 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10642 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10643 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10644 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10645 }
a2fbb9ea 10646
2189400b 10647 /*
619c5cb6 10648 * Enable internal target-read (in case we are probed after PF FLR).
2189400b 10649 * Must be done prior to any BAR read access. Only for 57712 and up
619c5cb6 10650 */
65087cfe 10651 if (!chip_is_e1x)
2189400b 10652 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
619c5cb6 10653
72fd0718
VZ		 10654 /* Reset the load counter */
10655 bnx2x_clear_load_cnt(bp);
10656
34f80b04 10657 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 10658
c64213cd 10659 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 10660 bnx2x_set_ethtool_ops(dev);
5316bc0b 10661
01789349
JP		 10662 dev->priv_flags |= IFF_UNICAST_FLT;
10663
66371c44 10664 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6e68c912
MS		 10665 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO |
10666 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
66371c44
MM		 10667
10668 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10669 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10670
10671 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 10672 if (bp->flags & USING_DAC_FLAG)
66371c44 10673 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 10674
538dd2e3
MB		 10675 /* Add Loopback capability to the device */
10676 dev->hw_features |= NETIF_F_LOOPBACK;
10677
98507672 10678#ifdef BCM_DCBNL
785b9b1a
SR		 10679 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10680#endif
10681
01cd4528
EG		 10682 /* get_port_hwinfo() will set prtad and mmds properly */
10683 bp->mdio.prtad = MDIO_PRTAD_NONE;
10684 bp->mdio.mmds = 0;
10685 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10686 bp->mdio.dev = dev;
10687 bp->mdio.mdio_read = bnx2x_mdio_read;
10688 bp->mdio.mdio_write = bnx2x_mdio_write;
10689
a2fbb9ea
ET		 10690 return 0;
10691
a2fbb9ea 10692err_out_release:
34f80b04
EG		 10693 if (atomic_read(&pdev->enable_cnt) == 1)
10694 pci_release_regions(pdev);
a2fbb9ea
ET		 10695
10696err_out_disable:
10697 pci_disable_device(pdev);
10698 pci_set_drvdata(pdev, NULL);
10699
10700err_out:
10701 return rc;
10702}
10703
37f9ce62
EG		 10704static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10705 int *width, int *speed)
25047950
ET		 10706{
10707 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10708
37f9ce62 10709 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 10710
37f9ce62
EG		 10711 /* return value of 1=2.5GHz 2=5GHz */
10712 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 10713}
37f9ce62 10714
6891dd25 10715static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 10716{
37f9ce62 10717 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 10718 struct bnx2x_fw_file_hdr *fw_hdr;
10719 struct bnx2x_fw_file_section *sections;
94a78b79 10720 u32 offset, len, num_ops;
37f9ce62 10721 u16 *ops_offsets;
94a78b79 10722 int i;
37f9ce62 10723 const u8 *fw_ver;
94a78b79
VZ		 10724
10725 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10726 return -EINVAL;
10727
10728 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10729 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10730
10731 /* Make sure none of the offsets and sizes make us read beyond
10732 * the end of the firmware data */
10733 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10734 offset = be32_to_cpu(sections[i].offset);
10735 len = be32_to_cpu(sections[i].len);
10736 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 10737 dev_err(&bp->pdev->dev,
10738 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 10739 return -EINVAL;
10740 }
10741 }
10742
10743 /* Likewise for the init_ops offsets */
10744 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10745 ops_offsets = (u16 *)(firmware->data + offset);
10746 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10747
10748 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10749 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 10750 dev_err(&bp->pdev->dev,
10751 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 10752 return -EINVAL;
10753 }
10754 }
10755
10756 /* Check FW version */
10757 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10758 fw_ver = firmware->data + offset;
10759 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10760 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10761 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10762 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 10763 dev_err(&bp->pdev->dev,
10764 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 10765 fw_ver[0], fw_ver[1], fw_ver[2],
10766 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10767 BCM_5710_FW_MINOR_VERSION,
10768 BCM_5710_FW_REVISION_VERSION,
10769 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 10770 return -EINVAL;
94a78b79
VZ		 10771 }
10772
10773 return 0;
10774}
10775
ab6ad5a4 10776static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10777{
ab6ad5a4
EG		 10778 const __be32 *source = (const __be32 *)_source;
10779 u32 *target = (u32 *)_target;
94a78b79 10780 u32 i;
94a78b79
VZ		 10781
10782 for (i = 0; i < n/4; i++)
10783 target[i] = be32_to_cpu(source[i]);
10784}
10785
10786/*
10787 Ops array is stored in the following format:
10788 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10789 */
ab6ad5a4 10790static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 10791{
ab6ad5a4
EG		 10792 const __be32 *source = (const __be32 *)_source;
10793 struct raw_op *target = (struct raw_op *)_target;
94a78b79 10794 u32 i, j, tmp;
94a78b79 10795
ab6ad5a4 10796 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 10797 tmp = be32_to_cpu(source[j]);
10798 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 10799 target[i].offset = tmp & 0xffffff;
10800 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 10801 }
10802}
ab6ad5a4 10803
523224a3
DK		 10804/**
10805 * IRO array is stored in the following format:
10806 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10807 */
10808static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10809{
10810 const __be32 *source = (const __be32 *)_source;
10811 struct iro *target = (struct iro *)_target;
10812 u32 i, j, tmp;
10813
10814 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10815 target[i].base = be32_to_cpu(source[j]);
10816 j++;
10817 tmp = be32_to_cpu(source[j]);
10818 target[i].m1 = (tmp >> 16) & 0xffff;
10819 target[i].m2 = tmp & 0xffff;
10820 j++;
10821 tmp = be32_to_cpu(source[j]);
10822 target[i].m3 = (tmp >> 16) & 0xffff;
10823 target[i].size = tmp & 0xffff;
10824 j++;
10825 }
10826}
10827
ab6ad5a4 10828static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10829{
ab6ad5a4
EG		 10830 const __be16 *source = (const __be16 *)_source;
10831 u16 *target = (u16 *)_target;
94a78b79 10832 u32 i;
94a78b79
VZ		 10833
10834 for (i = 0; i < n/2; i++)
10835 target[i] = be16_to_cpu(source[i]);
10836}
10837
7995c64e
JP		 10838#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10839do { \
10840 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10841 bp->arr = kmalloc(len, GFP_KERNEL); \
10842 if (!bp->arr) { \
10843 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10844 goto lbl; \
10845 } \
10846 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10847 (u8 *)bp->arr, len); \
10848} while (0)
94a78b79 10849
6891dd25 10850int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 10851{
94a78b79 10852 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 10853 int rc;
94a78b79 10854
94a78b79 10855
eb2afd4a
DK		 10856 if (!bp->firmware) {
10857 const char *fw_file_name;
94a78b79 10858
eb2afd4a
DK		 10859 if (CHIP_IS_E1(bp))
10860 fw_file_name = FW_FILE_NAME_E1;
10861 else if (CHIP_IS_E1H(bp))
10862 fw_file_name = FW_FILE_NAME_E1H;
10863 else if (!CHIP_IS_E1x(bp))
10864 fw_file_name = FW_FILE_NAME_E2;
10865 else {
10866 BNX2X_ERR("Unsupported chip revision\n");
10867 return -EINVAL;
10868 }
10869 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 10870
eb2afd4a
DK		 10871 rc = request_firmware(&bp->firmware, fw_file_name,
10872 &bp->pdev->dev);
10873 if (rc) {
10874 BNX2X_ERR("Can't load firmware file %s\n",
10875 fw_file_name);
10876 goto request_firmware_exit;
10877 }
10878
10879 rc = bnx2x_check_firmware(bp);
10880 if (rc) {
10881 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10882 goto request_firmware_exit;
10883 }
94a78b79
VZ		 10884 }
10885
10886 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10887
10888 /* Initialize the pointers to the init arrays */
10889 /* Blob */
10890 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10891
10892 /* Opcodes */
10893 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10894
10895 /* Offsets */
ab6ad5a4
EG		 10896 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10897 be16_to_cpu_n);
94a78b79
VZ		 10898
10899 /* STORMs firmware */
573f2035
EG		 10900 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10901 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10902 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10903 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10904 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10905 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10906 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10907 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10908 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10909 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10910 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10911 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10912 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10913 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10914 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10915 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 10916 /* IRO */
10917 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 10918
10919 return 0;
ab6ad5a4 10920
523224a3
DK		 10921iro_alloc_err:
10922 kfree(bp->init_ops_offsets);
94a78b79
VZ		 10923init_offsets_alloc_err:
10924 kfree(bp->init_ops);
10925init_ops_alloc_err:
10926 kfree(bp->init_data);
10927request_firmware_exit:
10928 release_firmware(bp->firmware);
10929
10930 return rc;
10931}
10932
619c5cb6
VZ		 10933static void bnx2x_release_firmware(struct bnx2x *bp)
10934{
10935 kfree(bp->init_ops_offsets);
10936 kfree(bp->init_ops);
10937 kfree(bp->init_data);
10938 release_firmware(bp->firmware);
eb2afd4a 10939 bp->firmware = NULL;
619c5cb6
VZ		 10940}
10941
10942
10943static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10944 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10945 .init_hw_cmn = bnx2x_init_hw_common,
10946 .init_hw_port = bnx2x_init_hw_port,
10947 .init_hw_func = bnx2x_init_hw_func,
10948
10949 .reset_hw_cmn = bnx2x_reset_common,
10950 .reset_hw_port = bnx2x_reset_port,
10951 .reset_hw_func = bnx2x_reset_func,
10952
10953 .gunzip_init = bnx2x_gunzip_init,
10954 .gunzip_end = bnx2x_gunzip_end,
10955
10956 .init_fw = bnx2x_init_firmware,
10957 .release_fw = bnx2x_release_firmware,
10958};
10959
10960void bnx2x__init_func_obj(struct bnx2x *bp)
10961{
10962 /* Prepare DMAE related driver resources */
10963 bnx2x_setup_dmae(bp);
10964
10965 bnx2x_init_func_obj(bp, &bp->func_obj,
10966 bnx2x_sp(bp, func_rdata),
10967 bnx2x_sp_mapping(bp, func_rdata),
10968 &bnx2x_func_sp_drv);
10969}
10970
10971/* must be called after sriov-enable */
6383c0b3 10972static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 10973{
6383c0b3 10974 int cid_count = BNX2X_L2_CID_COUNT(bp);
94a78b79 10975
523224a3
DK		 10976#ifdef BCM_CNIC
10977 cid_count += CNIC_CID_MAX;
10978#endif
10979 return roundup(cid_count, QM_CID_ROUND);
10980}
f85582f8 10981
619c5cb6 10982/**
6383c0b3 10983 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 10984 *
10985 * @dev: pci device
10986 *
10987 */
6383c0b3 10988static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
619c5cb6
VZ		 10989{
10990 int pos;
10991 u16 control;
10992
10993 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
6383c0b3
AE		 10994
10995 /*
10996 * If MSI-X is not supported - return number of SBs needed to support
10997 * one fast path queue: one FP queue + SB for CNIC
10998 */
619c5cb6 10999 if (!pos)
6383c0b3 11000 return 1 + CNIC_PRESENT;
619c5cb6 11001
6383c0b3
AE		 11002 /*
11003 * The value in the PCI configuration space is the index of the last
11004 * entry, namely one less than the actual size of the table, which is
11005 * exactly what we want to return from this function: number of all SBs
11006 * without the default SB.
11007 */
619c5cb6 11008 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
6383c0b3 11009 return control & PCI_MSIX_FLAGS_QSIZE;
619c5cb6
VZ		 11010}
11011
a2fbb9ea
ET		 11012static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11013 const struct pci_device_id *ent)
11014{
a2fbb9ea
ET		 11015 struct net_device *dev = NULL;
11016 struct bnx2x *bp;
37f9ce62 11017 int pcie_width, pcie_speed;
6383c0b3
AE		 11018 int rc, max_non_def_sbs;
11019 int rx_count, tx_count, rss_count;
11020 /*
11021 * An estimated maximum supported CoS number according to the chip
11022 * version.
11023 * We will try to roughly estimate the maximum number of CoSes this chip
11024 * may support in order to minimize the memory allocated for Tx
11025 * netdev_queue's. This number will be accurately calculated during the
11026 * initialization of bp->max_cos based on the chip versions AND chip
11027 * revision in the bnx2x_init_bp().
11028 */
11029 u8 max_cos_est = 0;
523224a3 11030
f2e0899f
DK		 11031 switch (ent->driver_data) {
11032 case BCM57710:
11033 case BCM57711:
11034 case BCM57711E:
6383c0b3
AE		 11035 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11036 break;
11037
f2e0899f 11038 case BCM57712:
619c5cb6 11039 case BCM57712_MF:
6383c0b3
AE		 11040 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11041 break;
11042
619c5cb6
VZ		 11043 case BCM57800:
11044 case BCM57800_MF:
11045 case BCM57810:
11046 case BCM57810_MF:
11047 case BCM57840:
11048 case BCM57840_MF:
6383c0b3 11049 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
f2e0899f 11050 break;
a2fbb9ea 11051
f2e0899f
DK		 11052 default:
11053 pr_err("Unknown board_type (%ld), aborting\n",
11054 ent->driver_data);
870634b0 11055 return -ENODEV;
f2e0899f
DK		 11056 }
11057
6383c0b3
AE		 11058 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11059
11060 /* !!! FIXME !!!
11061 * Do not allow the maximum SB count to grow above 16
11062 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
11063 * We will use the FP_SB_MAX_E1x macro for this matter.
11064 */
11065 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
11066
11067 WARN_ON(!max_non_def_sbs);
11068
11069 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11070 rss_count = max_non_def_sbs - CNIC_PRESENT;
11071
11072 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11073 rx_count = rss_count + FCOE_PRESENT;
11074
11075 /*
11076 * Maximum number of netdev Tx queues:
11077 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11078 */
11079 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
f85582f8 11080
a2fbb9ea 11081 /* dev zeroed in init_etherdev */
6383c0b3 11082 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
34f80b04 11083 if (!dev) {
cdaa7cb8 11084 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 11085 return -ENOMEM;
34f80b04 11086 }
a2fbb9ea 11087
a2fbb9ea 11088 bp = netdev_priv(dev);
a2fbb9ea 11089
6383c0b3
AE		 11090 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
11091 tx_count, rx_count);
df4770de 11092
6383c0b3
AE		 11093 bp->igu_sb_cnt = max_non_def_sbs;
11094 bp->msg_enable = debug;
11095 pci_set_drvdata(pdev, dev);
523224a3 11096
619c5cb6 11097 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
a2fbb9ea
ET		 11098 if (rc < 0) {
11099 free_netdev(dev);
11100 return rc;
11101 }
11102
94f05b0f 11103 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs);
619c5cb6 11104
34f80b04 11105 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 11106 if (rc)
11107 goto init_one_exit;
11108
6383c0b3
AE		 11109 /*
11110 * Map doorbels here as we need the real value of bp->max_cos which
11111 * is initialized in bnx2x_init_bp().
11112 */
11113 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11114 min_t(u64, BNX2X_DB_SIZE(bp),
11115 pci_resource_len(pdev, 2)));
11116 if (!bp->doorbells) {
11117 dev_err(&bp->pdev->dev,
11118 "Cannot map doorbell space, aborting\n");
11119 rc = -ENOMEM;
11120 goto init_one_exit;
11121 }
11122
523224a3 11123 /* calc qm_cid_count */
6383c0b3 11124 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
523224a3 11125
ec6ba945 11126#ifdef BCM_CNIC
62ac0dc9
DK		 11127 /* disable FCOE L2 queue for E1x */
11128 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 11129 bp->flags |= NO_FCOE_FLAG;
11130
11131#endif
11132
25985edc 11133 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 11134 * needed, set bp->num_queues appropriately.
11135 */
11136 bnx2x_set_int_mode(bp);
11137
11138 /* Add all NAPI objects */
11139 bnx2x_add_all_napi(bp);
11140
b340007f
VZ		 11141 rc = register_netdev(dev);
11142 if (rc) {
11143 dev_err(&pdev->dev, "Cannot register net device\n");
11144 goto init_one_exit;
11145 }
11146
ec6ba945
VZ		 11147#ifdef BCM_CNIC
11148 if (!NO_FCOE(bp)) {
11149 /* Add storage MAC address */
11150 rtnl_lock();
11151 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11152 rtnl_unlock();
11153 }
11154#endif
11155
37f9ce62 11156 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 11157
94f05b0f
JP		 11158 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11159 board_info[ent->driver_data].name,
11160 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11161 pcie_width,
11162 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11163 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11164 "5GHz (Gen2)" : "2.5GHz",
11165 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 11166
a2fbb9ea 11167 return 0;
34f80b04
EG		 11168
11169init_one_exit:
11170 if (bp->regview)
11171 iounmap(bp->regview);
11172
11173 if (bp->doorbells)
11174 iounmap(bp->doorbells);
11175
11176 free_netdev(dev);
11177
11178 if (atomic_read(&pdev->enable_cnt) == 1)
11179 pci_release_regions(pdev);
11180
11181 pci_disable_device(pdev);
11182 pci_set_drvdata(pdev, NULL);
11183
11184 return rc;
a2fbb9ea
ET		 11185}
11186
11187static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11188{
11189 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 11190 struct bnx2x *bp;
11191
11192 if (!dev) {
cdaa7cb8 11193 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 11194 return;
11195 }
228241eb 11196 bp = netdev_priv(dev);
a2fbb9ea 11197
ec6ba945
VZ		 11198#ifdef BCM_CNIC
11199 /* Delete storage MAC address */
11200 if (!NO_FCOE(bp)) {
11201 rtnl_lock();
11202 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11203 rtnl_unlock();
11204 }
11205#endif
11206
98507672
SR		 11207#ifdef BCM_DCBNL
11208 /* Delete app tlvs from dcbnl */
11209 bnx2x_dcbnl_update_applist(bp, true);
11210#endif
11211
a2fbb9ea
ET		 11212 unregister_netdev(dev);
11213
d6214d7a
DK		 11214 /* Delete all NAPI objects */
11215 bnx2x_del_all_napi(bp);
11216
084d6cbb
VZ		 11217 /* Power on: we can't let PCI layer write to us while we are in D3 */
11218 bnx2x_set_power_state(bp, PCI_D0);
11219
d6214d7a
DK		 11220 /* Disable MSI/MSI-X */
11221 bnx2x_disable_msi(bp);
f85582f8 11222
084d6cbb
VZ		 11223 /* Power off */
11224 bnx2x_set_power_state(bp, PCI_D3hot);
11225
72fd0718 11226 /* Make sure RESET task is not scheduled before continuing */
7be08a72 11227 cancel_delayed_work_sync(&bp->sp_rtnl_task);
72fd0718 11228
a2fbb9ea
ET		 11229 if (bp->regview)
11230 iounmap(bp->regview);
11231
11232 if (bp->doorbells)
11233 iounmap(bp->doorbells);
11234
eb2afd4a
DK		 11235 bnx2x_release_firmware(bp);
11236
523224a3
DK		 11237 bnx2x_free_mem_bp(bp);
11238
a2fbb9ea 11239 free_netdev(dev);
34f80b04
EG		 11240
11241 if (atomic_read(&pdev->enable_cnt) == 1)
11242 pci_release_regions(pdev);
11243
a2fbb9ea
ET		 11244 pci_disable_device(pdev);
11245 pci_set_drvdata(pdev, NULL);
11246}
11247
f8ef6e44
YG		 11248static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
11249{
11250 int i;
11251
11252 bp->state = BNX2X_STATE_ERROR;
11253
11254 bp->rx_mode = BNX2X_RX_MODE_NONE;
11255
619c5cb6
VZ		 11256#ifdef BCM_CNIC
11257 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
11258#endif
11259 /* Stop Tx */
11260 bnx2x_tx_disable(bp);
11261
f8ef6e44
YG		 11262 bnx2x_netif_stop(bp, 0);
11263
11264 del_timer_sync(&bp->timer);
619c5cb6
VZ		 11265
11266 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 11267
11268 /* Release IRQs */
d6214d7a 11269 bnx2x_free_irq(bp);
f8ef6e44 11270
f8ef6e44
YG		 11271 /* Free SKBs, SGEs, TPA pool and driver internals */
11272 bnx2x_free_skbs(bp);
523224a3 11273
ec6ba945 11274 for_each_rx_queue(bp, i)
f8ef6e44 11275 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 11276
f8ef6e44
YG		 11277 bnx2x_free_mem(bp);
11278
11279 bp->state = BNX2X_STATE_CLOSED;
11280
619c5cb6
VZ		 11281 netif_carrier_off(bp->dev);
11282
f8ef6e44
YG		 11283 return 0;
11284}
11285
11286static void bnx2x_eeh_recover(struct bnx2x *bp)
11287{
11288 u32 val;
11289
11290 mutex_init(&bp->port.phy_mutex);
11291
11292 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
11293 bp->link_params.shmem_base = bp->common.shmem_base;
11294 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
11295
11296 if (!bp->common.shmem_base ||
11297 (bp->common.shmem_base < 0xA0000) ||
11298 (bp->common.shmem_base >= 0xC0000)) {
11299 BNX2X_DEV_INFO("MCP not active\n");
11300 bp->flags |= NO_MCP_FLAG;
11301 return;
11302 }
11303
11304 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
11305 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11306 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11307 BNX2X_ERR("BAD MCP validity signature\n");
11308
11309 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 11310 bp->fw_seq =
11311 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11312 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 11313 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11314 }
11315}
11316
493adb1f
WX		 11317/**
11318 * bnx2x_io_error_detected - called when PCI error is detected
11319 * @pdev: Pointer to PCI device
11320 * @state: The current pci connection state
11321 *
11322 * This function is called after a PCI bus error affecting
11323 * this device has been detected.
11324 */
11325static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11326 pci_channel_state_t state)
11327{
11328 struct net_device *dev = pci_get_drvdata(pdev);
11329 struct bnx2x *bp = netdev_priv(dev);
11330
11331 rtnl_lock();
11332
11333 netif_device_detach(dev);
11334
07ce50e4
DN		 11335 if (state == pci_channel_io_perm_failure) {
11336 rtnl_unlock();
11337 return PCI_ERS_RESULT_DISCONNECT;
11338 }
11339
493adb1f 11340 if (netif_running(dev))
f8ef6e44 11341 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 11342
11343 pci_disable_device(pdev);
11344
11345 rtnl_unlock();
11346
11347 /* Request a slot reset */
11348 return PCI_ERS_RESULT_NEED_RESET;
11349}
11350
11351/**
11352 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11353 * @pdev: Pointer to PCI device
11354 *
11355 * Restart the card from scratch, as if from a cold-boot.
11356 */
11357static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11358{
11359 struct net_device *dev = pci_get_drvdata(pdev);
11360 struct bnx2x *bp = netdev_priv(dev);
11361
11362 rtnl_lock();
11363
11364 if (pci_enable_device(pdev)) {
11365 dev_err(&pdev->dev,
11366 "Cannot re-enable PCI device after reset\n");
11367 rtnl_unlock();
11368 return PCI_ERS_RESULT_DISCONNECT;
11369 }
11370
11371 pci_set_master(pdev);
11372 pci_restore_state(pdev);
11373
11374 if (netif_running(dev))
11375 bnx2x_set_power_state(bp, PCI_D0);
11376
11377 rtnl_unlock();
11378
11379 return PCI_ERS_RESULT_RECOVERED;
11380}
11381
11382/**
11383 * bnx2x_io_resume - called when traffic can start flowing again
11384 * @pdev: Pointer to PCI device
11385 *
11386 * This callback is called when the error recovery driver tells us that
11387 * its OK to resume normal operation.
11388 */
11389static void bnx2x_io_resume(struct pci_dev *pdev)
11390{
11391 struct net_device *dev = pci_get_drvdata(pdev);
11392 struct bnx2x *bp = netdev_priv(dev);
11393
72fd0718 11394 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
754a2f52
DK		 11395 netdev_err(bp->dev, "Handling parity error recovery. "
11396 "Try again later\n");
72fd0718
VZ		 11397 return;
11398 }
11399
493adb1f
WX		 11400 rtnl_lock();
11401
f8ef6e44
YG		 11402 bnx2x_eeh_recover(bp);
11403
493adb1f 11404 if (netif_running(dev))
f8ef6e44 11405 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 11406
11407 netif_device_attach(dev);
11408
11409 rtnl_unlock();
11410}
11411
11412static struct pci_error_handlers bnx2x_err_handler = {
11413 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 11414 .slot_reset = bnx2x_io_slot_reset,
11415 .resume = bnx2x_io_resume,
493adb1f
WX		 11416};
11417
a2fbb9ea 11418static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 11419 .name = DRV_MODULE_NAME,
11420 .id_table = bnx2x_pci_tbl,
11421 .probe = bnx2x_init_one,
11422 .remove = __devexit_p(bnx2x_remove_one),
11423 .suspend = bnx2x_suspend,
11424 .resume = bnx2x_resume,
11425 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 11426};
11427
11428static int __init bnx2x_init(void)
11429{
dd21ca6d
SG		 11430 int ret;
11431
7995c64e 11432 pr_info("%s", version);
938cf541 11433
1cf167f2
EG		 11434 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11435 if (bnx2x_wq == NULL) {
7995c64e 11436 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 11437 return -ENOMEM;
11438 }
11439
dd21ca6d
SG		 11440 ret = pci_register_driver(&bnx2x_pci_driver);
11441 if (ret) {
7995c64e 11442 pr_err("Cannot register driver\n");
dd21ca6d
SG		 11443 destroy_workqueue(bnx2x_wq);
11444 }
11445 return ret;
a2fbb9ea
ET		 11446}
11447
11448static void __exit bnx2x_cleanup(void)
11449{
11450 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 11451
11452 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 11453}
11454
3deb8167
YR		 11455void bnx2x_notify_link_changed(struct bnx2x *bp)
11456{
11457 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11458}
11459
a2fbb9ea
ET		 11460module_init(bnx2x_init);
11461module_exit(bnx2x_cleanup);
11462
993ac7b5 11463#ifdef BCM_CNIC
619c5cb6
VZ		 11464/**
11465 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11466 *
11467 * @bp: driver handle
11468 * @set: set or clear the CAM entry
11469 *
11470 * This function will wait until the ramdord completion returns.
11471 * Return 0 if success, -ENODEV if ramrod doesn't return.
11472 */
11473static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11474{
11475 unsigned long ramrod_flags = 0;
11476
11477 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11478 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11479 &bp->iscsi_l2_mac_obj, true,
11480 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11481}
993ac7b5
MC		 11482
11483/* count denotes the number of new completions we have seen */
11484static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11485{
11486 struct eth_spe *spe;
11487
11488#ifdef BNX2X_STOP_ON_ERROR
11489 if (unlikely(bp->panic))
11490 return;
11491#endif
11492
11493 spin_lock_bh(&bp->spq_lock);
c2bff63f 11494 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 11495 bp->cnic_spq_pending -= count;
11496
993ac7b5 11497
c2bff63f
DK		 11498 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11499 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11500 & SPE_HDR_CONN_TYPE) >>
11501 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 11502 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11503 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 11504
11505 /* Set validation for iSCSI L2 client before sending SETUP
11506 * ramrod
11507 */
11508 if (type == ETH_CONNECTION_TYPE) {
c2bff63f 11509 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
619c5cb6
VZ		 11510 bnx2x_set_ctx_validation(bp, &bp->context.
11511 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11512 BNX2X_ISCSI_ETH_CID);
c2bff63f
DK		 11513 }
11514
619c5cb6
VZ		 11515 /*
11516 * There may be not more than 8 L2, not more than 8 L5 SPEs
11517 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 11518 * COMMON ramrods is not more than the EQ and SPQ can
11519 * accommodate.
c2bff63f 11520 */
6e30dd4e
VZ		 11521 if (type == ETH_CONNECTION_TYPE) {
11522 if (!atomic_read(&bp->cq_spq_left))
11523 break;
11524 else
11525 atomic_dec(&bp->cq_spq_left);
11526 } else if (type == NONE_CONNECTION_TYPE) {
11527 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 11528 break;
11529 else
6e30dd4e 11530 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 11531 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11532 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 11533 if (bp->cnic_spq_pending >=
11534 bp->cnic_eth_dev.max_kwqe_pending)
11535 break;
11536 else
11537 bp->cnic_spq_pending++;
11538 } else {
11539 BNX2X_ERR("Unknown SPE type: %d\n", type);
11540 bnx2x_panic();
993ac7b5 11541 break;
c2bff63f 11542 }
993ac7b5
MC		 11543
11544 spe = bnx2x_sp_get_next(bp);
11545 *spe = *bp->cnic_kwq_cons;
11546
993ac7b5
MC		 11547 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11548 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11549
11550 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11551 bp->cnic_kwq_cons = bp->cnic_kwq;
11552 else
11553 bp->cnic_kwq_cons++;
11554 }
11555 bnx2x_sp_prod_update(bp);
11556 spin_unlock_bh(&bp->spq_lock);
11557}
11558
11559static int bnx2x_cnic_sp_queue(struct net_device *dev,
11560 struct kwqe_16 *kwqes[], u32 count)
11561{
11562 struct bnx2x *bp = netdev_priv(dev);
11563 int i;
11564
11565#ifdef BNX2X_STOP_ON_ERROR
11566 if (unlikely(bp->panic))
11567 return -EIO;
11568#endif
11569
11570 spin_lock_bh(&bp->spq_lock);
11571
11572 for (i = 0; i < count; i++) {
11573 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11574
11575 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11576 break;
11577
11578 *bp->cnic_kwq_prod = *spe;
11579
11580 bp->cnic_kwq_pending++;
11581
11582 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11583 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 11584 spe->data.update_data_addr.hi,
11585 spe->data.update_data_addr.lo,
993ac7b5
MC		 11586 bp->cnic_kwq_pending);
11587
11588 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11589 bp->cnic_kwq_prod = bp->cnic_kwq;
11590 else
11591 bp->cnic_kwq_prod++;
11592 }
11593
11594 spin_unlock_bh(&bp->spq_lock);
11595
11596 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11597 bnx2x_cnic_sp_post(bp, 0);
11598
11599 return i;
11600}
11601
11602static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11603{
11604 struct cnic_ops *c_ops;
11605 int rc = 0;
11606
11607 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 11608 c_ops = rcu_dereference_protected(bp->cnic_ops,
11609 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 11610 if (c_ops)
11611 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11612 mutex_unlock(&bp->cnic_mutex);
11613
11614 return rc;
11615}
11616
11617static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11618{
11619 struct cnic_ops *c_ops;
11620 int rc = 0;
11621
11622 rcu_read_lock();
11623 c_ops = rcu_dereference(bp->cnic_ops);
11624 if (c_ops)
11625 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11626 rcu_read_unlock();
11627
11628 return rc;
11629}
11630
11631/*
11632 * for commands that have no data
11633 */
9f6c9258 11634int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 11635{
11636 struct cnic_ctl_info ctl = {0};
11637
11638 ctl.cmd = cmd;
11639
11640 return bnx2x_cnic_ctl_send(bp, &ctl);
11641}
11642
619c5cb6 11643static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 11644{
619c5cb6 11645 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 11646
11647 /* first we tell CNIC and only then we count this as a completion */
11648 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11649 ctl.data.comp.cid = cid;
619c5cb6 11650 ctl.data.comp.error = err;
993ac7b5
MC		 11651
11652 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 11653 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 11654}
11655
619c5cb6
VZ		 11656
11657/* Called with netif_addr_lock_bh() taken.
11658 * Sets an rx_mode config for an iSCSI ETH client.
11659 * Doesn't block.
11660 * Completion should be checked outside.
11661 */
11662static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11663{
11664 unsigned long accept_flags = 0, ramrod_flags = 0;
11665 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11666 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11667
11668 if (start) {
11669 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11670 * because it's the only way for UIO Queue to accept
11671 * multicasts (in non-promiscuous mode only one Queue per
11672 * function will receive multicast packets (leading in our
11673 * case).
11674 */
11675 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11676 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11677 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11678 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11679
11680 /* Clear STOP_PENDING bit if START is requested */
11681 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11682
11683 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11684 } else
11685 /* Clear START_PENDING bit if STOP is requested */
11686 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11687
11688 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11689 set_bit(sched_state, &bp->sp_state);
11690 else {
11691 __set_bit(RAMROD_RX, &ramrod_flags);
11692 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11693 ramrod_flags);
11694 }
11695}
11696
11697
993ac7b5
MC		 11698static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11699{
11700 struct bnx2x *bp = netdev_priv(dev);
11701 int rc = 0;
11702
11703 switch (ctl->cmd) {
11704 case DRV_CTL_CTXTBL_WR_CMD: {
11705 u32 index = ctl->data.io.offset;
11706 dma_addr_t addr = ctl->data.io.dma_addr;
11707
11708 bnx2x_ilt_wr(bp, index, addr);
11709 break;
11710 }
11711
c2bff63f
DK		 11712 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11713 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 11714
11715 bnx2x_cnic_sp_post(bp, count);
11716 break;
11717 }
11718
11719 /* rtnl_lock is held. */
11720 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 11721 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11722 unsigned long sp_bits = 0;
11723
11724 /* Configure the iSCSI classification object */
11725 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11726 cp->iscsi_l2_client_id,
11727 cp->iscsi_l2_cid, BP_FUNC(bp),
11728 bnx2x_sp(bp, mac_rdata),
11729 bnx2x_sp_mapping(bp, mac_rdata),
11730 BNX2X_FILTER_MAC_PENDING,
11731 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11732 &bp->macs_pool);
ec6ba945 11733
523224a3 11734 /* Set iSCSI MAC address */
619c5cb6
VZ		 11735 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11736 if (rc)
11737 break;
523224a3
DK		 11738
11739 mmiowb();
11740 barrier();
11741
619c5cb6
VZ		 11742 /* Start accepting on iSCSI L2 ring */
11743
11744 netif_addr_lock_bh(dev);
11745 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11746 netif_addr_unlock_bh(dev);
11747
11748 /* bits to wait on */
11749 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11750 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11751
11752 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11753 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 11754
993ac7b5
MC		 11755 break;
11756 }
11757
11758 /* rtnl_lock is held. */
11759 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 11760 unsigned long sp_bits = 0;
993ac7b5 11761
523224a3 11762 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 11763 netif_addr_lock_bh(dev);
11764 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11765 netif_addr_unlock_bh(dev);
11766
11767 /* bits to wait on */
11768 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11769 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11770
11771 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11772 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 11773
11774 mmiowb();
11775 barrier();
11776
11777 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 11778 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11779 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 11780 break;
11781 }
c2bff63f
DK		 11782 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11783 int count = ctl->data.credit.credit_count;
11784
11785 smp_mb__before_atomic_inc();
6e30dd4e 11786 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 11787 smp_mb__after_atomic_inc();
11788 break;
11789 }
1d187b34
BW		 11790 case DRV_CTL_ULP_REGISTER_CMD: {
11791 int ulp_type = ctl->data.ulp_type;
11792
11793 if (CHIP_IS_E3(bp)) {
11794 int idx = BP_FW_MB_IDX(bp);
11795 u32 cap;
11796
11797 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
11798 if (ulp_type == CNIC_ULP_ISCSI)
11799 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
11800 else if (ulp_type == CNIC_ULP_FCOE)
11801 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
11802 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
11803 }
11804 break;
11805 }
11806 case DRV_CTL_ULP_UNREGISTER_CMD: {
11807 int ulp_type = ctl->data.ulp_type;
11808
11809 if (CHIP_IS_E3(bp)) {
11810 int idx = BP_FW_MB_IDX(bp);
11811 u32 cap;
11812
11813 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
11814 if (ulp_type == CNIC_ULP_ISCSI)
11815 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
11816 else if (ulp_type == CNIC_ULP_FCOE)
11817 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
11818 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
11819 }
11820 break;
11821 }
993ac7b5
MC		 11822
11823 default:
11824 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11825 rc = -EINVAL;
11826 }
11827
11828 return rc;
11829}
11830
9f6c9258 11831void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 11832{
11833 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11834
11835 if (bp->flags & USING_MSIX_FLAG) {
11836 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11837 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11838 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11839 } else {
11840 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11841 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11842 }
619c5cb6 11843 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 11844 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11845 else
11846 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11847
619c5cb6
VZ		 11848 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11849 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 11850 cp->irq_arr[1].status_blk = bp->def_status_blk;
11851 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 11852 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 11853
11854 cp->num_irq = 2;
11855}
11856
11857static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11858 void *data)
11859{
11860 struct bnx2x *bp = netdev_priv(dev);
11861 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11862
11863 if (ops == NULL)
11864 return -EINVAL;
11865
993ac7b5
MC		 11866 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11867 if (!bp->cnic_kwq)
11868 return -ENOMEM;
11869
11870 bp->cnic_kwq_cons = bp->cnic_kwq;
11871 bp->cnic_kwq_prod = bp->cnic_kwq;
11872 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11873
11874 bp->cnic_spq_pending = 0;
11875 bp->cnic_kwq_pending = 0;
11876
11877 bp->cnic_data = data;
11878
11879 cp->num_irq = 0;
619c5cb6 11880 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 11881 cp->iro_arr = bp->iro_arr;
993ac7b5 11882
993ac7b5 11883 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 11884
993ac7b5
MC		 11885 rcu_assign_pointer(bp->cnic_ops, ops);
11886
11887 return 0;
11888}
11889
11890static int bnx2x_unregister_cnic(struct net_device *dev)
11891{
11892 struct bnx2x *bp = netdev_priv(dev);
11893 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11894
11895 mutex_lock(&bp->cnic_mutex);
993ac7b5 11896 cp->drv_state = 0;
2cfa5a04 11897 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 11898 mutex_unlock(&bp->cnic_mutex);
11899 synchronize_rcu();
11900 kfree(bp->cnic_kwq);
11901 bp->cnic_kwq = NULL;
11902
11903 return 0;
11904}
11905
11906struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11907{
11908 struct bnx2x *bp = netdev_priv(dev);
11909 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11910
2ba45142
VZ		 11911 /* If both iSCSI and FCoE are disabled - return NULL in
11912 * order to indicate CNIC that it should not try to work
11913 * with this device.
11914 */
11915 if (NO_ISCSI(bp) && NO_FCOE(bp))
11916 return NULL;
11917
993ac7b5
MC		 11918 cp->drv_owner = THIS_MODULE;
11919 cp->chip_id = CHIP_ID(bp);
11920 cp->pdev = bp->pdev;
11921 cp->io_base = bp->regview;
11922 cp->io_base2 = bp->doorbells;
11923 cp->max_kwqe_pending = 8;
523224a3 11924 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 11925 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11926 bnx2x_cid_ilt_lines(bp);
993ac7b5 11927 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 11928 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 11929 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11930 cp->drv_ctl = bnx2x_drv_ctl;
11931 cp->drv_register_cnic = bnx2x_register_cnic;
11932 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945 11933 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
619c5cb6
VZ		 11934 cp->iscsi_l2_client_id =
11935 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
c2bff63f
DK		 11936 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11937
2ba45142
VZ		 11938 if (NO_ISCSI_OOO(bp))
11939 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11940
11941 if (NO_ISCSI(bp))
11942 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11943
11944 if (NO_FCOE(bp))
11945 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11946
c2bff63f
DK		 11947 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11948 "starting cid %d\n",
11949 cp->ctx_blk_size,
11950 cp->ctx_tbl_offset,
11951 cp->ctx_tbl_len,
11952 cp->starting_cid);
993ac7b5
MC		 11953 return cp;
11954}
11955EXPORT_SYMBOL(bnx2x_cnic_probe);
11956
11957#endif /* BCM_CNIC */
94a78b79 11958
Linux 6.x block layer and io_uring tree(s)