Commit | Line | Data |
---|---|---|
34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
f1deab50 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
a2fbb9ea ET |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> /* for dev_info() */ | |
24 | #include <linux/timer.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
a2fbb9ea ET |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/bitops.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/byteorder.h> | |
39 | #include <linux/time.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
0c6671b0 | 42 | #include <linux/if_vlan.h> |
a2fbb9ea | 43 | #include <net/ip.h> |
619c5cb6 | 44 | #include <net/ipv6.h> |
a2fbb9ea ET |
45 | #include <net/tcp.h> |
46 | #include <net/checksum.h> | |
34f80b04 | 47 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
48 | #include <linux/workqueue.h> |
49 | #include <linux/crc32.h> | |
34f80b04 | 50 | #include <linux/crc32c.h> |
a2fbb9ea ET |
51 | #include <linux/prefetch.h> |
52 | #include <linux/zlib.h> | |
a2fbb9ea | 53 | #include <linux/io.h> |
452427b0 | 54 | #include <linux/semaphore.h> |
45229b42 | 55 | #include <linux/stringify.h> |
7ab24bfd | 56 | #include <linux/vmalloc.h> |
a2fbb9ea | 57 | |
a2fbb9ea ET |
58 | #include "bnx2x.h" |
59 | #include "bnx2x_init.h" | |
94a78b79 | 60 | #include "bnx2x_init_ops.h" |
9f6c9258 | 61 | #include "bnx2x_cmn.h" |
1ab4434c | 62 | #include "bnx2x_vfpf.h" |
e4901dde | 63 | #include "bnx2x_dcb.h" |
042181f5 | 64 | #include "bnx2x_sp.h" |
a2fbb9ea | 65 | |
94a78b79 VZ |
66 | #include <linux/firmware.h> |
67 | #include "bnx2x_fw_file_hdr.h" | |
68 | /* FW files */ | |
45229b42 BH |
69 | #define FW_FILE_VERSION \ |
70 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
71 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
72 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
73 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
74 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
75 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 76 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 77 | |
2e499d3c BW |
78 | #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN) |
79 | ||
34f80b04 EG |
80 | /* Time in jiffies before concluding the transmitter is hung */ |
81 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 82 | |
0329aba1 | 83 | static char version[] = |
619c5cb6 | 84 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
85 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
86 | ||
24e3fcef | 87 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 88 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
89 | "BCM57710/57711/57711E/" |
90 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
91 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
92 | MODULE_LICENSE("GPL"); |
93 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
94 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
95 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 96 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 97 | |
ca00392c | 98 | |
d6214d7a | 99 | int num_queues; |
54b9ddaa | 100 | module_param(num_queues, int, 0); |
96305234 DK |
101 | MODULE_PARM_DESC(num_queues, |
102 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 103 | |
19680c48 | 104 | static int disable_tpa; |
19680c48 | 105 | module_param(disable_tpa, int, 0); |
9898f86d | 106 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 107 | |
9ee3d37b DK |
108 | #define INT_MODE_INTx 1 |
109 | #define INT_MODE_MSI 2 | |
0e8d2ec5 | 110 | int int_mode; |
8badd27a | 111 | module_param(int_mode, int, 0); |
619c5cb6 | 112 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 113 | "(1 INT#x; 2 MSI)"); |
8badd27a | 114 | |
a18f5128 EG |
115 | static int dropless_fc; |
116 | module_param(dropless_fc, int, 0); | |
117 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
118 | ||
8d5726c4 EG |
119 | static int mrrs = -1; |
120 | module_param(mrrs, int, 0); | |
121 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
122 | ||
9898f86d | 123 | static int debug; |
a2fbb9ea | 124 | module_param(debug, int, 0); |
9898f86d EG |
125 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
126 | ||
a2fbb9ea | 127 | |
619c5cb6 VZ |
128 | |
129 | struct workqueue_struct *bnx2x_wq; | |
ec6ba945 | 130 | |
1ef1d45a BW |
131 | struct bnx2x_mac_vals { |
132 | u32 xmac_addr; | |
133 | u32 xmac_val; | |
134 | u32 emac_addr; | |
135 | u32 emac_val; | |
136 | u32 umac_addr; | |
137 | u32 umac_val; | |
138 | u32 bmac_addr; | |
139 | u32 bmac_val[2]; | |
140 | }; | |
141 | ||
a2fbb9ea ET |
142 | enum bnx2x_board_type { |
143 | BCM57710 = 0, | |
619c5cb6 VZ |
144 | BCM57711, |
145 | BCM57711E, | |
146 | BCM57712, | |
147 | BCM57712_MF, | |
1ab4434c | 148 | BCM57712_VF, |
619c5cb6 VZ |
149 | BCM57800, |
150 | BCM57800_MF, | |
1ab4434c | 151 | BCM57800_VF, |
619c5cb6 VZ |
152 | BCM57810, |
153 | BCM57810_MF, | |
1ab4434c | 154 | BCM57810_VF, |
c3def943 YM |
155 | BCM57840_4_10, |
156 | BCM57840_2_20, | |
7e8e02df | 157 | BCM57840_MF, |
1ab4434c | 158 | BCM57840_VF, |
7e8e02df | 159 | BCM57811, |
1ab4434c AE |
160 | BCM57811_MF, |
161 | BCM57840_O, | |
162 | BCM57840_MFO, | |
163 | BCM57811_VF | |
a2fbb9ea ET |
164 | }; |
165 | ||
34f80b04 | 166 | /* indexed by board_type, above */ |
53a10565 | 167 | static struct { |
a2fbb9ea | 168 | char *name; |
0329aba1 | 169 | } board_info[] = { |
1ab4434c AE |
170 | [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
171 | [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
172 | [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
173 | [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
174 | [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
175 | [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" }, | |
176 | [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
177 | [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
178 | [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" }, | |
179 | [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
180 | [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
181 | [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" }, | |
182 | [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" }, | |
183 | [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" }, | |
184 | [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
185 | [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }, | |
186 | [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" }, | |
187 | [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" }, | |
188 | [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
189 | [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
190 | [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" } | |
a2fbb9ea ET |
191 | }; |
192 | ||
619c5cb6 VZ |
193 | #ifndef PCI_DEVICE_ID_NX2_57710 |
194 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
195 | #endif | |
196 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
197 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
198 | #endif | |
199 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
200 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
201 | #endif | |
202 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
203 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
204 | #endif | |
205 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
206 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
207 | #endif | |
8395be5e AE |
208 | #ifndef PCI_DEVICE_ID_NX2_57712_VF |
209 | #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF | |
210 | #endif | |
619c5cb6 VZ |
211 | #ifndef PCI_DEVICE_ID_NX2_57800 |
212 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
213 | #endif | |
214 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
215 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
216 | #endif | |
8395be5e AE |
217 | #ifndef PCI_DEVICE_ID_NX2_57800_VF |
218 | #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF | |
219 | #endif | |
619c5cb6 VZ |
220 | #ifndef PCI_DEVICE_ID_NX2_57810 |
221 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
222 | #endif | |
223 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
224 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
225 | #endif | |
c3def943 YM |
226 | #ifndef PCI_DEVICE_ID_NX2_57840_O |
227 | #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE | |
228 | #endif | |
8395be5e AE |
229 | #ifndef PCI_DEVICE_ID_NX2_57810_VF |
230 | #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF | |
231 | #endif | |
c3def943 YM |
232 | #ifndef PCI_DEVICE_ID_NX2_57840_4_10 |
233 | #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 | |
234 | #endif | |
235 | #ifndef PCI_DEVICE_ID_NX2_57840_2_20 | |
236 | #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 | |
237 | #endif | |
238 | #ifndef PCI_DEVICE_ID_NX2_57840_MFO | |
239 | #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE | |
619c5cb6 VZ |
240 | #endif |
241 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
242 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
243 | #endif | |
8395be5e AE |
244 | #ifndef PCI_DEVICE_ID_NX2_57840_VF |
245 | #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF | |
246 | #endif | |
7e8e02df BW |
247 | #ifndef PCI_DEVICE_ID_NX2_57811 |
248 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
249 | #endif | |
250 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
251 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
252 | #endif | |
8395be5e AE |
253 | #ifndef PCI_DEVICE_ID_NX2_57811_VF |
254 | #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF | |
255 | #endif | |
256 | ||
a3aa1884 | 257 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
258 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
259 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
260 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 261 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 | 262 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
8395be5e | 263 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, |
619c5cb6 VZ |
264 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, |
265 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
8395be5e | 266 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, |
619c5cb6 VZ |
267 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, |
268 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
c3def943 YM |
269 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, |
270 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, | |
271 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, | |
8395be5e | 272 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, |
c3def943 | 273 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, |
619c5cb6 | 274 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
8395be5e | 275 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
7e8e02df BW |
276 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
277 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
8395be5e | 278 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, |
a2fbb9ea ET |
279 | { 0 } |
280 | }; | |
281 | ||
282 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
283 | ||
452427b0 YM |
284 | /* Global resources for unloading a previously loaded device */ |
285 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
286 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
287 | static LIST_HEAD(bnx2x_prev_list); | |
a2fbb9ea ET |
288 | /**************************************************************************** |
289 | * General service functions | |
290 | ****************************************************************************/ | |
291 | ||
1191cb83 | 292 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
619c5cb6 VZ |
293 | u32 addr, dma_addr_t mapping) |
294 | { | |
295 | REG_WR(bp, addr, U64_LO(mapping)); | |
296 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
297 | } | |
298 | ||
1191cb83 ED |
299 | static void storm_memset_spq_addr(struct bnx2x *bp, |
300 | dma_addr_t mapping, u16 abs_fid) | |
619c5cb6 VZ |
301 | { |
302 | u32 addr = XSEM_REG_FAST_MEMORY + | |
303 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
304 | ||
305 | __storm_memset_dma_mapping(bp, addr, mapping); | |
306 | } | |
307 | ||
1191cb83 ED |
308 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
309 | u16 pf_id) | |
523224a3 | 310 | { |
619c5cb6 VZ |
311 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
312 | pf_id); | |
313 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
314 | pf_id); | |
315 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
316 | pf_id); | |
317 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
318 | pf_id); | |
523224a3 DK |
319 | } |
320 | ||
1191cb83 ED |
321 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
322 | u8 enable) | |
619c5cb6 VZ |
323 | { |
324 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
325 | enable); | |
326 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
327 | enable); | |
328 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
329 | enable); | |
330 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
331 | enable); | |
332 | } | |
523224a3 | 333 | |
1191cb83 ED |
334 | static void storm_memset_eq_data(struct bnx2x *bp, |
335 | struct event_ring_data *eq_data, | |
523224a3 DK |
336 | u16 pfid) |
337 | { | |
338 | size_t size = sizeof(struct event_ring_data); | |
339 | ||
340 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
341 | ||
342 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
343 | } | |
344 | ||
1191cb83 ED |
345 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
346 | u16 pfid) | |
523224a3 DK |
347 | { |
348 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
349 | REG_WR16(bp, addr, eq_prod); | |
350 | } | |
351 | ||
a2fbb9ea ET |
352 | /* used only at init |
353 | * locking is done by mcp | |
354 | */ | |
8d96286a | 355 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
356 | { |
357 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
358 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
359 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
360 | PCICFG_VENDOR_ID_OFFSET); | |
361 | } | |
362 | ||
a2fbb9ea ET |
363 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
364 | { | |
365 | u32 val; | |
366 | ||
367 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
368 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
369 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
370 | PCICFG_VENDOR_ID_OFFSET); | |
371 | ||
372 | return val; | |
373 | } | |
a2fbb9ea | 374 | |
f2e0899f DK |
375 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
376 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
377 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
378 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
379 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
380 | ||
fd1fc79d AE |
381 | void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl) |
382 | { | |
383 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; | |
384 | ||
385 | switch (dmae->opcode & DMAE_COMMAND_DST) { | |
386 | case DMAE_CMD_DST_PCI: | |
387 | if (src_type == DMAE_CMD_SRC_PCI) | |
388 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
389 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" | |
390 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
391 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
392 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
393 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
394 | dmae->comp_val); | |
395 | else | |
396 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
397 | "src [%08x], len [%d*4], dst [%x:%08x]\n" | |
398 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
399 | dmae->opcode, dmae->src_addr_lo >> 2, | |
400 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
401 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
402 | dmae->comp_val); | |
403 | break; | |
404 | case DMAE_CMD_DST_GRC: | |
405 | if (src_type == DMAE_CMD_SRC_PCI) | |
406 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
407 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" | |
408 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
409 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
410 | dmae->len, dmae->dst_addr_lo >> 2, | |
411 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
412 | dmae->comp_val); | |
413 | else | |
414 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
415 | "src [%08x], len [%d*4], dst [%08x]\n" | |
416 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
417 | dmae->opcode, dmae->src_addr_lo >> 2, | |
418 | dmae->len, dmae->dst_addr_lo >> 2, | |
419 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
420 | dmae->comp_val); | |
421 | break; | |
422 | default: | |
423 | if (src_type == DMAE_CMD_SRC_PCI) | |
424 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
425 | "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" | |
426 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
427 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
428 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
429 | dmae->comp_val); | |
430 | else | |
431 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
432 | "src_addr [%08x] len [%d * 4] dst_addr [none]\n" | |
433 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
434 | dmae->opcode, dmae->src_addr_lo >> 2, | |
435 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
436 | dmae->comp_val); | |
437 | break; | |
438 | } | |
439 | } | |
f2e0899f | 440 | |
a2fbb9ea | 441 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 442 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
443 | { |
444 | u32 cmd_offset; | |
445 | int i; | |
446 | ||
447 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
448 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
449 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
450 | } |
451 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
452 | } | |
453 | ||
f2e0899f | 454 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 455 | { |
f2e0899f DK |
456 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
457 | DMAE_CMD_C_ENABLE); | |
458 | } | |
ad8d3948 | 459 | |
f2e0899f DK |
460 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
461 | { | |
462 | return opcode & ~DMAE_CMD_SRC_RESET; | |
463 | } | |
ad8d3948 | 464 | |
f2e0899f DK |
465 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
466 | bool with_comp, u8 comp_type) | |
467 | { | |
468 | u32 opcode = 0; | |
469 | ||
470 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
471 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 472 | |
f2e0899f DK |
473 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
474 | ||
475 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
476 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
477 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 478 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 479 | |
a2fbb9ea | 480 | #ifdef __BIG_ENDIAN |
f2e0899f | 481 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 482 | #else |
f2e0899f | 483 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 484 | #endif |
f2e0899f DK |
485 | if (with_comp) |
486 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
487 | return opcode; | |
488 | } | |
489 | ||
fd1fc79d | 490 | void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
8d96286a | 491 | struct dmae_command *dmae, |
492 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
493 | { |
494 | memset(dmae, 0, sizeof(struct dmae_command)); | |
495 | ||
496 | /* set the opcode */ | |
497 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
498 | true, DMAE_COMP_PCI); | |
499 | ||
500 | /* fill in the completion parameters */ | |
501 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
502 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
503 | dmae->comp_val = DMAE_COMP_VAL; | |
504 | } | |
505 | ||
fd1fc79d AE |
506 | /* issue a dmae command over the init-channel and wait for completion */ |
507 | int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae) | |
f2e0899f DK |
508 | { |
509 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 510 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
511 | int rc = 0; |
512 | ||
619c5cb6 VZ |
513 | /* |
514 | * Lock the dmae channel. Disable BHs to prevent a dead-lock | |
515 | * as long as this code is called both from syscall context and | |
516 | * from ndo_set_rx_mode() flow that may be called from BH. | |
517 | */ | |
6e30dd4e | 518 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 519 | |
f2e0899f | 520 | /* reset completion */ |
a2fbb9ea ET |
521 | *wb_comp = 0; |
522 | ||
f2e0899f DK |
523 | /* post the command on the channel used for initializations */ |
524 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 525 | |
f2e0899f | 526 | /* wait for completion */ |
a2fbb9ea | 527 | udelay(5); |
f2e0899f | 528 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 529 | |
95c6c616 AE |
530 | if (!cnt || |
531 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
532 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 533 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
534 | rc = DMAE_TIMEOUT; |
535 | goto unlock; | |
a2fbb9ea | 536 | } |
ad8d3948 | 537 | cnt--; |
f2e0899f | 538 | udelay(50); |
a2fbb9ea | 539 | } |
f2e0899f DK |
540 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
541 | BNX2X_ERR("DMAE PCI error!\n"); | |
542 | rc = DMAE_PCI_ERROR; | |
543 | } | |
544 | ||
f2e0899f | 545 | unlock: |
6e30dd4e | 546 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
547 | return rc; |
548 | } | |
549 | ||
550 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
551 | u32 len32) | |
552 | { | |
553 | struct dmae_command dmae; | |
554 | ||
555 | if (!bp->dmae_ready) { | |
556 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
557 | ||
127a425e AE |
558 | if (CHIP_IS_E1(bp)) |
559 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
560 | else | |
561 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
562 | return; |
563 | } | |
564 | ||
565 | /* set opcode and fixed command fields */ | |
566 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
567 | ||
568 | /* fill in addresses and len */ | |
569 | dmae.src_addr_lo = U64_LO(dma_addr); | |
570 | dmae.src_addr_hi = U64_HI(dma_addr); | |
571 | dmae.dst_addr_lo = dst_addr >> 2; | |
572 | dmae.dst_addr_hi = 0; | |
573 | dmae.len = len32; | |
574 | ||
f2e0899f DK |
575 | /* issue the command and wait for completion */ |
576 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
a2fbb9ea ET |
577 | } |
578 | ||
c18487ee | 579 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 580 | { |
5ff7b6d4 | 581 | struct dmae_command dmae; |
ad8d3948 EG |
582 | |
583 | if (!bp->dmae_ready) { | |
584 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
585 | int i; | |
586 | ||
51c1a580 | 587 | if (CHIP_IS_E1(bp)) |
127a425e AE |
588 | for (i = 0; i < len32; i++) |
589 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 590 | else |
127a425e AE |
591 | for (i = 0; i < len32; i++) |
592 | data[i] = REG_RD(bp, src_addr + i*4); | |
593 | ||
ad8d3948 EG |
594 | return; |
595 | } | |
596 | ||
f2e0899f DK |
597 | /* set opcode and fixed command fields */ |
598 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 599 | |
f2e0899f | 600 | /* fill in addresses and len */ |
5ff7b6d4 EG |
601 | dmae.src_addr_lo = src_addr >> 2; |
602 | dmae.src_addr_hi = 0; | |
603 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
604 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
605 | dmae.len = len32; | |
ad8d3948 | 606 | |
f2e0899f DK |
607 | /* issue the command and wait for completion */ |
608 | bnx2x_issue_dmae_with_comp(bp, &dmae); | |
ad8d3948 EG |
609 | } |
610 | ||
8d96286a | 611 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
612 | u32 addr, u32 len) | |
573f2035 | 613 | { |
02e3c6cb | 614 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
615 | int offset = 0; |
616 | ||
02e3c6cb | 617 | while (len > dmae_wr_max) { |
573f2035 | 618 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
619 | addr + offset, dmae_wr_max); |
620 | offset += dmae_wr_max * 4; | |
621 | len -= dmae_wr_max; | |
573f2035 EG |
622 | } |
623 | ||
624 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
625 | } | |
626 | ||
a2fbb9ea ET |
627 | static int bnx2x_mc_assert(struct bnx2x *bp) |
628 | { | |
a2fbb9ea | 629 | char last_idx; |
34f80b04 EG |
630 | int i, rc = 0; |
631 | u32 row0, row1, row2, row3; | |
632 | ||
633 | /* XSTORM */ | |
634 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
635 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
636 | if (last_idx) | |
637 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
638 | ||
639 | /* print the asserts */ | |
640 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
641 | ||
642 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
643 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
644 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
645 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
646 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
647 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
648 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
649 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
650 | ||
651 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 652 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
653 | i, row3, row2, row1, row0); |
654 | rc++; | |
655 | } else { | |
656 | break; | |
657 | } | |
658 | } | |
659 | ||
660 | /* TSTORM */ | |
661 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
662 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
663 | if (last_idx) | |
664 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
665 | ||
666 | /* print the asserts */ | |
667 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
668 | ||
669 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
670 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
671 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
672 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
673 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
674 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
675 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
676 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
677 | ||
678 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 679 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
680 | i, row3, row2, row1, row0); |
681 | rc++; | |
682 | } else { | |
683 | break; | |
684 | } | |
685 | } | |
686 | ||
687 | /* CSTORM */ | |
688 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
689 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
690 | if (last_idx) | |
691 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
692 | ||
693 | /* print the asserts */ | |
694 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
695 | ||
696 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
697 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
698 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
699 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
700 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
701 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
702 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
703 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
704 | ||
705 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 706 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
707 | i, row3, row2, row1, row0); |
708 | rc++; | |
709 | } else { | |
710 | break; | |
711 | } | |
712 | } | |
713 | ||
714 | /* USTORM */ | |
715 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
716 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
717 | if (last_idx) | |
718 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
719 | ||
720 | /* print the asserts */ | |
721 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
722 | ||
723 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
724 | USTORM_ASSERT_LIST_OFFSET(i)); | |
725 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
726 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
727 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
728 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
729 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
730 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
731 | ||
732 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 733 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
734 | i, row3, row2, row1, row0); |
735 | rc++; | |
736 | } else { | |
737 | break; | |
a2fbb9ea ET |
738 | } |
739 | } | |
34f80b04 | 740 | |
a2fbb9ea ET |
741 | return rc; |
742 | } | |
c14423fe | 743 | |
7a25cc73 | 744 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 745 | { |
7a25cc73 | 746 | u32 addr, val; |
a2fbb9ea | 747 | u32 mark, offset; |
4781bfad | 748 | __be32 data[9]; |
a2fbb9ea | 749 | int word; |
f2e0899f | 750 | u32 trace_shmem_base; |
2145a920 VZ |
751 | if (BP_NOMCP(bp)) { |
752 | BNX2X_ERR("NO MCP - can not dump\n"); | |
753 | return; | |
754 | } | |
7a25cc73 DK |
755 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
756 | (bp->common.bc_ver & 0xff0000) >> 16, | |
757 | (bp->common.bc_ver & 0xff00) >> 8, | |
758 | (bp->common.bc_ver & 0xff)); | |
759 | ||
760 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
761 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 762 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 763 | |
f2e0899f DK |
764 | if (BP_PATH(bp) == 0) |
765 | trace_shmem_base = bp->common.shmem_base; | |
766 | else | |
767 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
de128804 DK |
768 | addr = trace_shmem_base - 0x800; |
769 | ||
770 | /* validate TRCB signature */ | |
771 | mark = REG_RD(bp, addr); | |
772 | if (mark != MFW_TRACE_SIGNATURE) { | |
773 | BNX2X_ERR("Trace buffer signature is missing."); | |
774 | return ; | |
775 | } | |
776 | ||
777 | /* read cyclic buffer pointer */ | |
778 | addr += 4; | |
cdaa7cb8 | 779 | mark = REG_RD(bp, addr); |
f2e0899f DK |
780 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
781 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 782 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 783 | |
7a25cc73 | 784 | printk("%s", lvl); |
f2e0899f | 785 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 786 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 787 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 788 | data[8] = 0x0; |
7995c64e | 789 | pr_cont("%s", (char *)data); |
a2fbb9ea | 790 | } |
cdaa7cb8 | 791 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 792 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 793 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 794 | data[8] = 0x0; |
7995c64e | 795 | pr_cont("%s", (char *)data); |
a2fbb9ea | 796 | } |
7a25cc73 DK |
797 | printk("%s" "end of fw dump\n", lvl); |
798 | } | |
799 | ||
1191cb83 | 800 | static void bnx2x_fw_dump(struct bnx2x *bp) |
7a25cc73 DK |
801 | { |
802 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
803 | } |
804 | ||
6c719d00 | 805 | void bnx2x_panic_dump(struct bnx2x *bp) |
a2fbb9ea ET |
806 | { |
807 | int i; | |
523224a3 DK |
808 | u16 j; |
809 | struct hc_sp_status_block_data sp_sb_data; | |
810 | int func = BP_FUNC(bp); | |
811 | #ifdef BNX2X_STOP_ON_ERROR | |
812 | u16 start = 0, end = 0; | |
6383c0b3 | 813 | u8 cos; |
523224a3 | 814 | #endif |
a2fbb9ea | 815 | |
66e855f3 | 816 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 817 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
818 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
819 | ||
a2fbb9ea ET |
820 | BNX2X_ERR("begin crash dump -----------------\n"); |
821 | ||
8440d2b6 EG |
822 | /* Indices */ |
823 | /* Common */ | |
51c1a580 | 824 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
619c5cb6 VZ |
825 | bp->def_idx, bp->def_att_idx, bp->attn_state, |
826 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
827 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
828 | bp->def_status_blk->atten_status_block.attn_bits, | |
829 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
830 | bp->def_status_blk->atten_status_block.status_block_id, | |
831 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
832 | BNX2X_ERR(" def ("); | |
833 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
834 | pr_cont("0x%x%s", | |
f1deab50 JP |
835 | bp->def_status_blk->sp_sb.index_values[i], |
836 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
523224a3 DK |
837 | |
838 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
839 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
840 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
841 | i*sizeof(u32)); | |
842 | ||
f1deab50 | 843 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", |
523224a3 DK |
844 | sp_sb_data.igu_sb_id, |
845 | sp_sb_data.igu_seg_id, | |
846 | sp_sb_data.p_func.pf_id, | |
847 | sp_sb_data.p_func.vnic_id, | |
848 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
849 | sp_sb_data.p_func.vf_valid, |
850 | sp_sb_data.state); | |
523224a3 | 851 | |
8440d2b6 | 852 | |
ec6ba945 | 853 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 854 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 855 | int loop; |
f2e0899f | 856 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
857 | struct hc_status_block_data_e1x sb_data_e1x; |
858 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
859 | CHIP_IS_E1x(bp) ? |
860 | sb_data_e1x.common.state_machine : | |
861 | sb_data_e2.common.state_machine; | |
523224a3 | 862 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
863 | CHIP_IS_E1x(bp) ? |
864 | sb_data_e1x.index_data : | |
865 | sb_data_e2.index_data; | |
6383c0b3 | 866 | u8 data_size, cos; |
523224a3 | 867 | u32 *sb_data_p; |
6383c0b3 | 868 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
869 | |
870 | /* Rx */ | |
51c1a580 | 871 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 872 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 873 | fp->rx_comp_prod, |
66e855f3 | 874 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 875 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 876 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 877 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 878 | |
523224a3 | 879 | /* Tx */ |
6383c0b3 AE |
880 | for_each_cos_in_tx_queue(fp, cos) |
881 | { | |
65565884 | 882 | txdata = *fp->txdata_ptr[cos]; |
51c1a580 | 883 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
884 | i, txdata.tx_pkt_prod, |
885 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
886 | txdata.tx_bd_cons, | |
887 | le16_to_cpu(*txdata.tx_cons_sb)); | |
888 | } | |
523224a3 | 889 | |
619c5cb6 VZ |
890 | loop = CHIP_IS_E1x(bp) ? |
891 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
892 | |
893 | /* host sb data */ | |
894 | ||
ec6ba945 VZ |
895 | if (IS_FCOE_FP(fp)) |
896 | continue; | |
55c11941 | 897 | |
523224a3 DK |
898 | BNX2X_ERR(" run indexes ("); |
899 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
900 | pr_cont("0x%x%s", | |
901 | fp->sb_running_index[j], | |
902 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
903 | ||
904 | BNX2X_ERR(" indexes ("); | |
905 | for (j = 0; j < loop; j++) | |
906 | pr_cont("0x%x%s", | |
907 | fp->sb_index_values[j], | |
908 | (j == loop - 1) ? ")" : " "); | |
909 | /* fw sb data */ | |
619c5cb6 VZ |
910 | data_size = CHIP_IS_E1x(bp) ? |
911 | sizeof(struct hc_status_block_data_e1x) : | |
912 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 913 | data_size /= sizeof(u32); |
619c5cb6 VZ |
914 | sb_data_p = CHIP_IS_E1x(bp) ? |
915 | (u32 *)&sb_data_e1x : | |
916 | (u32 *)&sb_data_e2; | |
523224a3 DK |
917 | /* copy sb data in here */ |
918 | for (j = 0; j < data_size; j++) | |
919 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
920 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
921 | j * sizeof(u32)); | |
922 | ||
619c5cb6 | 923 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 924 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
925 | sb_data_e2.common.p_func.pf_id, |
926 | sb_data_e2.common.p_func.vf_id, | |
927 | sb_data_e2.common.p_func.vf_valid, | |
928 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
929 | sb_data_e2.common.same_igu_sb_1b, |
930 | sb_data_e2.common.state); | |
f2e0899f | 931 | } else { |
51c1a580 | 932 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
933 | sb_data_e1x.common.p_func.pf_id, |
934 | sb_data_e1x.common.p_func.vf_id, | |
935 | sb_data_e1x.common.p_func.vf_valid, | |
936 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
937 | sb_data_e1x.common.same_igu_sb_1b, |
938 | sb_data_e1x.common.state); | |
f2e0899f | 939 | } |
523224a3 DK |
940 | |
941 | /* SB_SMs data */ | |
942 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
943 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
944 | j, hc_sm_p[j].__flags, | |
945 | hc_sm_p[j].igu_sb_id, | |
946 | hc_sm_p[j].igu_seg_id, | |
947 | hc_sm_p[j].time_to_expire, | |
948 | hc_sm_p[j].timer_value); | |
523224a3 DK |
949 | } |
950 | ||
951 | /* Indecies data */ | |
952 | for (j = 0; j < loop; j++) { | |
51c1a580 | 953 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
954 | hc_index_p[j].flags, |
955 | hc_index_p[j].timeout); | |
956 | } | |
8440d2b6 | 957 | } |
a2fbb9ea | 958 | |
523224a3 | 959 | #ifdef BNX2X_STOP_ON_ERROR |
8440d2b6 EG |
960 | /* Rings */ |
961 | /* Rx */ | |
55c11941 | 962 | for_each_valid_rx_queue(bp, i) { |
8440d2b6 | 963 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
964 | |
965 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
966 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 967 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
968 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
969 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
970 | ||
c3eefaf6 | 971 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 972 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
973 | } |
974 | ||
3196a88a EG |
975 | start = RX_SGE(fp->rx_sge_prod); |
976 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 977 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
978 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
979 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
980 | ||
c3eefaf6 EG |
981 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
982 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
983 | } |
984 | ||
a2fbb9ea ET |
985 | start = RCQ_BD(fp->rx_comp_cons - 10); |
986 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 987 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
988 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
989 | ||
c3eefaf6 EG |
990 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
991 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
992 | } |
993 | } | |
994 | ||
8440d2b6 | 995 | /* Tx */ |
55c11941 | 996 | for_each_valid_tx_queue(bp, i) { |
8440d2b6 | 997 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 | 998 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 999 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 AE |
1000 | |
1001 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
1002 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
1003 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1004 | struct sw_tx_bd *sw_bd = | |
1005 | &txdata->tx_buf_ring[j]; | |
1006 | ||
51c1a580 | 1007 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
1008 | i, cos, j, sw_bd->skb, |
1009 | sw_bd->first_bd); | |
1010 | } | |
8440d2b6 | 1011 | |
6383c0b3 AE |
1012 | start = TX_BD(txdata->tx_bd_cons - 10); |
1013 | end = TX_BD(txdata->tx_bd_cons + 254); | |
1014 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1015 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 1016 | |
51c1a580 | 1017 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
1018 | i, cos, j, tx_bd[0], tx_bd[1], |
1019 | tx_bd[2], tx_bd[3]); | |
1020 | } | |
8440d2b6 EG |
1021 | } |
1022 | } | |
523224a3 | 1023 | #endif |
34f80b04 | 1024 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
1025 | bnx2x_mc_assert(bp); |
1026 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
1027 | } |
1028 | ||
619c5cb6 VZ |
1029 | /* |
1030 | * FLR Support for E2 | |
1031 | * | |
1032 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
1033 | * initialization. | |
1034 | */ | |
1035 | #define FLR_WAIT_USEC 10000 /* 10 miliseconds */ | |
89db4ad8 AE |
1036 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
1037 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
1038 | |
1039 | struct pbf_pN_buf_regs { | |
1040 | int pN; | |
1041 | u32 init_crd; | |
1042 | u32 crd; | |
1043 | u32 crd_freed; | |
1044 | }; | |
1045 | ||
1046 | struct pbf_pN_cmd_regs { | |
1047 | int pN; | |
1048 | u32 lines_occup; | |
1049 | u32 lines_freed; | |
1050 | }; | |
1051 | ||
1052 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
1053 | struct pbf_pN_buf_regs *regs, | |
1054 | u32 poll_count) | |
1055 | { | |
1056 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
1057 | u32 cur_cnt = poll_count; | |
1058 | ||
1059 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
1060 | crd = crd_start = REG_RD(bp, regs->crd); | |
1061 | init_crd = REG_RD(bp, regs->init_crd); | |
1062 | ||
1063 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
1064 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
1065 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
1066 | ||
1067 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
1068 | (init_crd - crd_start))) { | |
1069 | if (cur_cnt--) { | |
89db4ad8 | 1070 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1071 | crd = REG_RD(bp, regs->crd); |
1072 | crd_freed = REG_RD(bp, regs->crd_freed); | |
1073 | } else { | |
1074 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
1075 | regs->pN); | |
1076 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
1077 | regs->pN, crd); | |
1078 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
1079 | regs->pN, crd_freed); | |
1080 | break; | |
1081 | } | |
1082 | } | |
1083 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 1084 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1085 | } |
1086 | ||
1087 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
1088 | struct pbf_pN_cmd_regs *regs, | |
1089 | u32 poll_count) | |
1090 | { | |
1091 | u32 occup, to_free, freed, freed_start; | |
1092 | u32 cur_cnt = poll_count; | |
1093 | ||
1094 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1095 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1096 | ||
1097 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1098 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1099 | ||
1100 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1101 | if (cur_cnt--) { | |
89db4ad8 | 1102 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1103 | occup = REG_RD(bp, regs->lines_occup); |
1104 | freed = REG_RD(bp, regs->lines_freed); | |
1105 | } else { | |
1106 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1107 | regs->pN); | |
1108 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1109 | regs->pN, occup); | |
1110 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1111 | regs->pN, freed); | |
1112 | break; | |
1113 | } | |
1114 | } | |
1115 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 1116 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1117 | } |
1118 | ||
1191cb83 ED |
1119 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
1120 | u32 expected, u32 poll_count) | |
619c5cb6 VZ |
1121 | { |
1122 | u32 cur_cnt = poll_count; | |
1123 | u32 val; | |
1124 | ||
1125 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1126 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1127 | |
1128 | return val; | |
1129 | } | |
1130 | ||
d16132ce AE |
1131 | int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1132 | char *msg, u32 poll_cnt) | |
619c5cb6 VZ |
1133 | { |
1134 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1135 | if (val != 0) { | |
1136 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1137 | return 1; | |
1138 | } | |
1139 | return 0; | |
1140 | } | |
1141 | ||
d16132ce AE |
1142 | /* Common routines with VF FLR cleanup */ |
1143 | u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
619c5cb6 VZ |
1144 | { |
1145 | /* adjust polling timeout */ | |
1146 | if (CHIP_REV_IS_EMUL(bp)) | |
1147 | return FLR_POLL_CNT * 2000; | |
1148 | ||
1149 | if (CHIP_REV_IS_FPGA(bp)) | |
1150 | return FLR_POLL_CNT * 120; | |
1151 | ||
1152 | return FLR_POLL_CNT; | |
1153 | } | |
1154 | ||
d16132ce | 1155 | void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) |
619c5cb6 VZ |
1156 | { |
1157 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1158 | {0, (CHIP_IS_E3B0(bp)) ? | |
1159 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1160 | PBF_REG_P0_TQ_OCCUPANCY, | |
1161 | (CHIP_IS_E3B0(bp)) ? | |
1162 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1163 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1164 | {1, (CHIP_IS_E3B0(bp)) ? | |
1165 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1166 | PBF_REG_P1_TQ_OCCUPANCY, | |
1167 | (CHIP_IS_E3B0(bp)) ? | |
1168 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1169 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1170 | {4, (CHIP_IS_E3B0(bp)) ? | |
1171 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1172 | PBF_REG_P4_TQ_OCCUPANCY, | |
1173 | (CHIP_IS_E3B0(bp)) ? | |
1174 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1175 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1176 | }; | |
1177 | ||
1178 | struct pbf_pN_buf_regs buf_regs[] = { | |
1179 | {0, (CHIP_IS_E3B0(bp)) ? | |
1180 | PBF_REG_INIT_CRD_Q0 : | |
1181 | PBF_REG_P0_INIT_CRD , | |
1182 | (CHIP_IS_E3B0(bp)) ? | |
1183 | PBF_REG_CREDIT_Q0 : | |
1184 | PBF_REG_P0_CREDIT, | |
1185 | (CHIP_IS_E3B0(bp)) ? | |
1186 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1187 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1188 | {1, (CHIP_IS_E3B0(bp)) ? | |
1189 | PBF_REG_INIT_CRD_Q1 : | |
1190 | PBF_REG_P1_INIT_CRD, | |
1191 | (CHIP_IS_E3B0(bp)) ? | |
1192 | PBF_REG_CREDIT_Q1 : | |
1193 | PBF_REG_P1_CREDIT, | |
1194 | (CHIP_IS_E3B0(bp)) ? | |
1195 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1196 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1197 | {4, (CHIP_IS_E3B0(bp)) ? | |
1198 | PBF_REG_INIT_CRD_LB_Q : | |
1199 | PBF_REG_P4_INIT_CRD, | |
1200 | (CHIP_IS_E3B0(bp)) ? | |
1201 | PBF_REG_CREDIT_LB_Q : | |
1202 | PBF_REG_P4_CREDIT, | |
1203 | (CHIP_IS_E3B0(bp)) ? | |
1204 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1205 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1206 | }; | |
1207 | ||
1208 | int i; | |
1209 | ||
1210 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1211 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1212 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1213 | ||
1214 | ||
1215 | /* Verify the transmission buffers are flushed P0, P1, P4 */ | |
1216 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1217 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1218 | } | |
1219 | ||
1220 | #define OP_GEN_PARAM(param) \ | |
1221 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1222 | ||
1223 | #define OP_GEN_TYPE(type) \ | |
1224 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1225 | ||
1226 | #define OP_GEN_AGG_VECT(index) \ | |
1227 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1228 | ||
1229 | ||
d16132ce | 1230 | int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) |
619c5cb6 VZ |
1231 | { |
1232 | struct sdm_op_gen op_gen = {0}; | |
1233 | ||
1234 | u32 comp_addr = BAR_CSTRORM_INTMEM + | |
1235 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1236 | int ret = 0; | |
1237 | ||
1238 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1239 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1240 | return 1; |
1241 | } | |
1242 | ||
1243 | op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); | |
1244 | op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1245 | op_gen.command |= OP_GEN_AGG_VECT(clnup_func); | |
1246 | op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
1247 | ||
89db4ad8 | 1248 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
619c5cb6 VZ |
1249 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command); |
1250 | ||
1251 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1252 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1253 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1254 | (REG_RD(bp, comp_addr))); | |
d16132ce AE |
1255 | bnx2x_panic(); |
1256 | return 1; | |
619c5cb6 VZ |
1257 | } |
1258 | /* Zero completion for nxt FLR */ | |
1259 | REG_WR(bp, comp_addr, 0); | |
1260 | ||
1261 | return ret; | |
1262 | } | |
1263 | ||
b56e9670 | 1264 | u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
619c5cb6 | 1265 | { |
619c5cb6 VZ |
1266 | u16 status; |
1267 | ||
2a80eebc | 1268 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
619c5cb6 VZ |
1269 | return status & PCI_EXP_DEVSTA_TRPND; |
1270 | } | |
1271 | ||
1272 | /* PF FLR specific routines | |
1273 | */ | |
1274 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1275 | { | |
1276 | ||
1277 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ | |
1278 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1279 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1280 | "CFC PF usage counter timed out", | |
1281 | poll_cnt)) | |
1282 | return 1; | |
1283 | ||
1284 | ||
1285 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ | |
1286 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1287 | DORQ_REG_PF_USAGE_CNT, | |
1288 | "DQ PF usage counter timed out", | |
1289 | poll_cnt)) | |
1290 | return 1; | |
1291 | ||
1292 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1293 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1294 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1295 | "QM PF usage counter timed out", | |
1296 | poll_cnt)) | |
1297 | return 1; | |
1298 | ||
1299 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1300 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1301 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1302 | "Timers VNIC usage counter timed out", | |
1303 | poll_cnt)) | |
1304 | return 1; | |
1305 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1306 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1307 | "Timers NUM_SCANS usage counter timed out", | |
1308 | poll_cnt)) | |
1309 | return 1; | |
1310 | ||
1311 | /* Wait DMAE PF usage counter to zero */ | |
1312 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1313 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
1314 | "DMAE dommand register timed out", | |
1315 | poll_cnt)) | |
1316 | return 1; | |
1317 | ||
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1322 | { | |
1323 | u32 val; | |
1324 | ||
1325 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1326 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1327 | ||
1328 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1329 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1330 | ||
1331 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1332 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1333 | ||
1334 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1335 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1336 | ||
1337 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1338 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1339 | ||
1340 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1341 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1342 | ||
1343 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1344 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1345 | ||
1346 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1347 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1348 | val); | |
1349 | } | |
1350 | ||
1351 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1352 | { | |
1353 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1354 | ||
1355 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1356 | ||
1357 | /* Re-enable PF target read access */ | |
1358 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1359 | ||
1360 | /* Poll HW usage counters */ | |
89db4ad8 | 1361 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1362 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1363 | return -EBUSY; | |
1364 | ||
1365 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1366 | ||
1367 | /* Send the FW cleanup command */ | |
1368 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1369 | return -EBUSY; | |
1370 | ||
1371 | /* ATC cleanup */ | |
1372 | ||
1373 | /* Verify TX hw is flushed */ | |
1374 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1375 | ||
1376 | /* Wait 100ms (not adjusted according to platform) */ | |
1377 | msleep(100); | |
1378 | ||
1379 | /* Verify no pending pci transactions */ | |
1380 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1381 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1382 | ||
1383 | /* Debug */ | |
1384 | bnx2x_hw_enable_status(bp); | |
1385 | ||
1386 | /* | |
1387 | * Master enable - Due to WB DMAE writes performed before this | |
1388 | * register is re-initialized as part of the regular function init | |
1389 | */ | |
1390 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1391 | ||
1392 | return 0; | |
1393 | } | |
1394 | ||
f2e0899f | 1395 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1396 | { |
34f80b04 | 1397 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1398 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1399 | u32 val = REG_RD(bp, addr); | |
69c326b3 DK |
1400 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1401 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1402 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
a2fbb9ea ET |
1403 | |
1404 | if (msix) { | |
8badd27a EG |
1405 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1406 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1407 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1408 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
69c326b3 DK |
1409 | if (single_msix) |
1410 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; | |
8badd27a EG |
1411 | } else if (msi) { |
1412 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1413 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1414 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1415 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1416 | } else { |
1417 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1418 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1419 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1420 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1421 | |
a0fd065c | 1422 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1423 | DP(NETIF_MSG_IFUP, |
1424 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1425 | |
a0fd065c | 1426 | REG_WR(bp, addr, val); |
615f8fd9 | 1427 | |
a0fd065c DK |
1428 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1429 | } | |
a2fbb9ea ET |
1430 | } |
1431 | ||
a0fd065c DK |
1432 | if (CHIP_IS_E1(bp)) |
1433 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1434 | ||
51c1a580 MS |
1435 | DP(NETIF_MSG_IFUP, |
1436 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1437 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1438 | |
1439 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1440 | /* |
1441 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1442 | */ | |
1443 | mmiowb(); | |
1444 | barrier(); | |
34f80b04 | 1445 | |
f2e0899f | 1446 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1447 | /* init leading/trailing edge */ |
fb3bff17 | 1448 | if (IS_MF(bp)) { |
3395a033 | 1449 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1450 | if (bp->port.pmf) |
4acac6a5 EG |
1451 | /* enable nig and gpio3 attention */ |
1452 | val |= 0x1100; | |
34f80b04 EG |
1453 | } else |
1454 | val = 0xffff; | |
1455 | ||
1456 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1457 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1458 | } | |
37dbbf32 EG |
1459 | |
1460 | /* Make sure that interrupts are indeed enabled from here on */ | |
1461 | mmiowb(); | |
a2fbb9ea ET |
1462 | } |
1463 | ||
f2e0899f DK |
1464 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1465 | { | |
1466 | u32 val; | |
30a5de77 DK |
1467 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1468 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1469 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1470 | |
1471 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1472 | ||
1473 | if (msix) { | |
1474 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1475 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1476 | val |= (IGU_PF_CONF_FUNC_EN | | |
1477 | IGU_PF_CONF_MSI_MSIX_EN | | |
1478 | IGU_PF_CONF_ATTN_BIT_EN); | |
30a5de77 DK |
1479 | |
1480 | if (single_msix) | |
1481 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1482 | } else if (msi) { |
1483 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
1484 | val |= (IGU_PF_CONF_FUNC_EN | | |
1485 | IGU_PF_CONF_MSI_MSIX_EN | | |
1486 | IGU_PF_CONF_ATTN_BIT_EN | | |
1487 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1488 | } else { | |
1489 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
1490 | val |= (IGU_PF_CONF_FUNC_EN | | |
1491 | IGU_PF_CONF_INT_LINE_EN | | |
1492 | IGU_PF_CONF_ATTN_BIT_EN | | |
1493 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1494 | } | |
1495 | ||
51c1a580 | 1496 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1497 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1498 | ||
1499 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1500 | ||
79a8557a YM |
1501 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1502 | pci_intx(bp->pdev, true); | |
1503 | ||
f2e0899f DK |
1504 | barrier(); |
1505 | ||
1506 | /* init leading/trailing edge */ | |
1507 | if (IS_MF(bp)) { | |
3395a033 | 1508 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1509 | if (bp->port.pmf) |
1510 | /* enable nig and gpio3 attention */ | |
1511 | val |= 0x1100; | |
1512 | } else | |
1513 | val = 0xffff; | |
1514 | ||
1515 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1516 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1517 | ||
1518 | /* Make sure that interrupts are indeed enabled from here on */ | |
1519 | mmiowb(); | |
1520 | } | |
1521 | ||
1522 | void bnx2x_int_enable(struct bnx2x *bp) | |
1523 | { | |
1524 | if (bp->common.int_block == INT_BLOCK_HC) | |
1525 | bnx2x_hc_int_enable(bp); | |
1526 | else | |
1527 | bnx2x_igu_int_enable(bp); | |
1528 | } | |
1529 | ||
1530 | static void bnx2x_hc_int_disable(struct bnx2x *bp) | |
a2fbb9ea | 1531 | { |
34f80b04 | 1532 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1533 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1534 | u32 val = REG_RD(bp, addr); | |
1535 | ||
a0fd065c DK |
1536 | /* |
1537 | * in E1 we must use only PCI configuration space to disable | |
1538 | * MSI/MSIX capablility | |
1539 | * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
1540 | */ | |
1541 | if (CHIP_IS_E1(bp)) { | |
1542 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
1543 | * Use mask register to prevent from HC sending interrupts | |
1544 | * after we exit the function | |
1545 | */ | |
1546 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
1547 | ||
1548 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1549 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1550 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
1551 | } else | |
1552 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1553 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1554 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
1555 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea | 1556 | |
51c1a580 MS |
1557 | DP(NETIF_MSG_IFDOWN, |
1558 | "write %x to HC %d (addr 0x%x)\n", | |
a2fbb9ea ET |
1559 | val, port, addr); |
1560 | ||
8badd27a EG |
1561 | /* flush all outstanding writes */ |
1562 | mmiowb(); | |
1563 | ||
a2fbb9ea ET |
1564 | REG_WR(bp, addr, val); |
1565 | if (REG_RD(bp, addr) != val) | |
1566 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1567 | } | |
1568 | ||
f2e0899f DK |
1569 | static void bnx2x_igu_int_disable(struct bnx2x *bp) |
1570 | { | |
1571 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1572 | ||
1573 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
1574 | IGU_PF_CONF_INT_LINE_EN | | |
1575 | IGU_PF_CONF_ATTN_BIT_EN); | |
1576 | ||
51c1a580 | 1577 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); |
f2e0899f DK |
1578 | |
1579 | /* flush all outstanding writes */ | |
1580 | mmiowb(); | |
1581 | ||
1582 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1583 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
1584 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | |
1585 | } | |
1586 | ||
910cc727 | 1587 | static void bnx2x_int_disable(struct bnx2x *bp) |
f2e0899f DK |
1588 | { |
1589 | if (bp->common.int_block == INT_BLOCK_HC) | |
1590 | bnx2x_hc_int_disable(bp); | |
1591 | else | |
1592 | bnx2x_igu_int_disable(bp); | |
1593 | } | |
1594 | ||
9f6c9258 | 1595 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1596 | { |
a2fbb9ea | 1597 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1598 | int i, offset; |
a2fbb9ea | 1599 | |
f8ef6e44 YG |
1600 | if (disable_hw) |
1601 | /* prevent the HW from sending interrupts */ | |
1602 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1603 | |
1604 | /* make sure all ISRs are done */ | |
1605 | if (msix) { | |
8badd27a EG |
1606 | synchronize_irq(bp->msix_table[0].vector); |
1607 | offset = 1; | |
55c11941 MS |
1608 | if (CNIC_SUPPORT(bp)) |
1609 | offset++; | |
ec6ba945 | 1610 | for_each_eth_queue(bp, i) |
754a2f52 | 1611 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1612 | } else |
1613 | synchronize_irq(bp->pdev->irq); | |
1614 | ||
1615 | /* make sure sp_task is not running */ | |
1cf167f2 | 1616 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1617 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1618 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1619 | } |
1620 | ||
34f80b04 | 1621 | /* fast path */ |
a2fbb9ea ET |
1622 | |
1623 | /* | |
34f80b04 | 1624 | * General service functions |
a2fbb9ea ET |
1625 | */ |
1626 | ||
72fd0718 VZ |
1627 | /* Return true if succeeded to acquire the lock */ |
1628 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1629 | { | |
1630 | u32 lock_status; | |
1631 | u32 resource_bit = (1 << resource); | |
1632 | int func = BP_FUNC(bp); | |
1633 | u32 hw_lock_control_reg; | |
1634 | ||
51c1a580 MS |
1635 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1636 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1637 | |
1638 | /* Validating that the resource is within range */ | |
1639 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1640 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1641 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1642 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1643 | return false; |
72fd0718 VZ |
1644 | } |
1645 | ||
1646 | if (func <= 5) | |
1647 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1648 | else | |
1649 | hw_lock_control_reg = | |
1650 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1651 | ||
1652 | /* Try to acquire the lock */ | |
1653 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1654 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1655 | if (lock_status & resource_bit) | |
1656 | return true; | |
1657 | ||
51c1a580 MS |
1658 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1659 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1660 | return false; |
1661 | } | |
1662 | ||
c9ee9206 VZ |
1663 | /** |
1664 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1665 | * | |
1666 | * @bp: driver handle | |
1667 | * | |
1668 | * Returns the recovery leader resource id according to the engine this function | |
1669 | * belongs to. Currently only only 2 engines is supported. | |
1670 | */ | |
1191cb83 | 1671 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
c9ee9206 VZ |
1672 | { |
1673 | if (BP_PATH(bp)) | |
1674 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1675 | else | |
1676 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1677 | } | |
1678 | ||
1679 | /** | |
1680 | * bnx2x_trylock_leader_lock- try to aquire a leader lock. | |
1681 | * | |
1682 | * @bp: driver handle | |
1683 | * | |
1191cb83 | 1684 | * Tries to aquire a leader lock for current engine. |
c9ee9206 | 1685 | */ |
1191cb83 | 1686 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
c9ee9206 VZ |
1687 | { |
1688 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1689 | } | |
1690 | ||
619c5cb6 | 1691 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
55c11941 | 1692 | |
fd1fc79d AE |
1693 | /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ |
1694 | static int bnx2x_schedule_sp_task(struct bnx2x *bp) | |
1695 | { | |
1696 | /* Set the interrupt occurred bit for the sp-task to recognize it | |
1697 | * must ack the interrupt and transition according to the IGU | |
1698 | * state machine. | |
1699 | */ | |
1700 | atomic_set(&bp->interrupt_occurred, 1); | |
1701 | ||
1702 | /* The sp_task must execute only after this bit | |
1703 | * is set, otherwise we will get out of sync and miss all | |
1704 | * further interrupts. Hence, the barrier. | |
1705 | */ | |
1706 | smp_wmb(); | |
1707 | ||
1708 | /* schedule sp_task to workqueue */ | |
1709 | return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1710 | } | |
3196a88a | 1711 | |
619c5cb6 | 1712 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1713 | { |
1714 | struct bnx2x *bp = fp->bp; | |
1715 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1716 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 | 1717 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
15192a8c | 1718 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a2fbb9ea | 1719 | |
34f80b04 | 1720 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1721 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1722 | fp->index, cid, command, bp->state, |
34f80b04 | 1723 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1724 | |
fd1fc79d AE |
1725 | /* If cid is within VF range, replace the slowpath object with the |
1726 | * one corresponding to this VF | |
1727 | */ | |
1728 | if (cid >= BNX2X_FIRST_VF_CID && | |
1729 | cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) | |
1730 | bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); | |
1731 | ||
619c5cb6 VZ |
1732 | switch (command) { |
1733 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1734 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1735 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1736 | break; | |
d6cae238 | 1737 | |
619c5cb6 | 1738 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1739 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1740 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1741 | break; |
1742 | ||
6383c0b3 | 1743 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1744 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1745 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1746 | break; | |
1747 | ||
619c5cb6 | 1748 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1749 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1750 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1751 | break; |
1752 | ||
619c5cb6 | 1753 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
d6cae238 | 1754 | DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid); |
619c5cb6 | 1755 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1756 | break; |
1757 | ||
619c5cb6 | 1758 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1759 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1760 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1761 | break; |
619c5cb6 VZ |
1762 | |
1763 | default: | |
1764 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1765 | command, fp->index); | |
1766 | return; | |
523224a3 | 1767 | } |
3196a88a | 1768 | |
619c5cb6 VZ |
1769 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1770 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1771 | /* q_obj->complete_cmd() failure means that this was | |
1772 | * an unexpected completion. | |
1773 | * | |
1774 | * In this case we don't want to increase the bp->spq_left | |
1775 | * because apparently we haven't sent this command the first | |
1776 | * place. | |
1777 | */ | |
1778 | #ifdef BNX2X_STOP_ON_ERROR | |
1779 | bnx2x_panic(); | |
1780 | #else | |
1781 | return; | |
1782 | #endif | |
fd1fc79d AE |
1783 | /* SRIOV: reschedule any 'in_progress' operations */ |
1784 | bnx2x_iov_sp_event(bp, cid, true); | |
619c5cb6 | 1785 | |
8fe23fbd | 1786 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1787 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1788 | /* push the change in bp->spq_left and towards the memory */ |
1789 | smp_mb__after_atomic_inc(); | |
49d66772 | 1790 | |
d6cae238 VZ |
1791 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1792 | ||
a3348722 BW |
1793 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1794 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1795 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1796 | * flow, then ACK MCP at the end | |
1797 | * | |
1798 | * mark pending ACK to MCP bit. | |
1799 | * prevent case that both bits are cleared. | |
1800 | * At the end of load/unload driver checks that | |
1801 | * sp_state is cleaerd, and this order prevents | |
1802 | * races | |
1803 | */ | |
1804 | smp_mb__before_clear_bit(); | |
1805 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); | |
1806 | wmb(); | |
1807 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
1808 | smp_mb__after_clear_bit(); | |
1809 | ||
fd1fc79d AE |
1810 | /* schedule the sp task as mcp ack is required */ |
1811 | bnx2x_schedule_sp_task(bp); | |
a3348722 BW |
1812 | } |
1813 | ||
523224a3 | 1814 | return; |
a2fbb9ea ET |
1815 | } |
1816 | ||
9f6c9258 | 1817 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1818 | { |
555f6c78 | 1819 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1820 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1821 | u16 mask; |
ca00392c | 1822 | int i; |
6383c0b3 | 1823 | u8 cos; |
a2fbb9ea | 1824 | |
34f80b04 | 1825 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1826 | if (unlikely(status == 0)) { |
1827 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1828 | return IRQ_NONE; | |
1829 | } | |
f5372251 | 1830 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1831 | |
3196a88a EG |
1832 | #ifdef BNX2X_STOP_ON_ERROR |
1833 | if (unlikely(bp->panic)) | |
1834 | return IRQ_HANDLED; | |
1835 | #endif | |
1836 | ||
ec6ba945 | 1837 | for_each_eth_queue(bp, i) { |
ca00392c | 1838 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1839 | |
55c11941 | 1840 | mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); |
ca00392c | 1841 | if (status & mask) { |
619c5cb6 | 1842 | /* Handle Rx or Tx according to SB id */ |
54b9ddaa | 1843 | prefetch(fp->rx_cons_sb); |
6383c0b3 | 1844 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1845 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
523224a3 | 1846 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1847 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1848 | status &= ~mask; |
1849 | } | |
a2fbb9ea ET |
1850 | } |
1851 | ||
55c11941 MS |
1852 | if (CNIC_SUPPORT(bp)) { |
1853 | mask = 0x2; | |
1854 | if (status & (mask | 0x1)) { | |
1855 | struct cnic_ops *c_ops = NULL; | |
993ac7b5 | 1856 | |
55c11941 MS |
1857 | if (likely(bp->state == BNX2X_STATE_OPEN)) { |
1858 | rcu_read_lock(); | |
1859 | c_ops = rcu_dereference(bp->cnic_ops); | |
1860 | if (c_ops) | |
1861 | c_ops->cnic_handler(bp->cnic_data, | |
1862 | NULL); | |
1863 | rcu_read_unlock(); | |
1864 | } | |
993ac7b5 | 1865 | |
55c11941 MS |
1866 | status &= ~mask; |
1867 | } | |
993ac7b5 | 1868 | } |
a2fbb9ea | 1869 | |
34f80b04 | 1870 | if (unlikely(status & 0x1)) { |
fd1fc79d AE |
1871 | |
1872 | /* schedule sp task to perform default status block work, ack | |
1873 | * attentions and enable interrupts. | |
1874 | */ | |
1875 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
1876 | |
1877 | status &= ~0x1; | |
1878 | if (!status) | |
1879 | return IRQ_HANDLED; | |
1880 | } | |
1881 | ||
cdaa7cb8 VZ |
1882 | if (unlikely(status)) |
1883 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1884 | status); |
a2fbb9ea | 1885 | |
c18487ee | 1886 | return IRQ_HANDLED; |
a2fbb9ea ET |
1887 | } |
1888 | ||
c18487ee YR |
1889 | /* Link */ |
1890 | ||
1891 | /* | |
1892 | * General service functions | |
1893 | */ | |
a2fbb9ea | 1894 | |
9f6c9258 | 1895 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1896 | { |
1897 | u32 lock_status; | |
1898 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1899 | int func = BP_FUNC(bp); |
1900 | u32 hw_lock_control_reg; | |
c18487ee | 1901 | int cnt; |
a2fbb9ea | 1902 | |
c18487ee YR |
1903 | /* Validating that the resource is within range */ |
1904 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1905 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1906 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1907 | return -EINVAL; | |
1908 | } | |
a2fbb9ea | 1909 | |
4a37fb66 YG |
1910 | if (func <= 5) { |
1911 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1912 | } else { | |
1913 | hw_lock_control_reg = | |
1914 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1915 | } | |
1916 | ||
c18487ee | 1917 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1918 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1919 | if (lock_status & resource_bit) { |
51c1a580 | 1920 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
1921 | lock_status, resource_bit); |
1922 | return -EEXIST; | |
1923 | } | |
a2fbb9ea | 1924 | |
46230476 EG |
1925 | /* Try for 5 second every 5ms */ |
1926 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1927 | /* Try to acquire the lock */ |
4a37fb66 YG |
1928 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1929 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1930 | if (lock_status & resource_bit) |
1931 | return 0; | |
a2fbb9ea | 1932 | |
c18487ee | 1933 | msleep(5); |
a2fbb9ea | 1934 | } |
51c1a580 | 1935 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
1936 | return -EAGAIN; |
1937 | } | |
a2fbb9ea | 1938 | |
c9ee9206 VZ |
1939 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1940 | { | |
1941 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1942 | } | |
1943 | ||
9f6c9258 | 1944 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1945 | { |
1946 | u32 lock_status; | |
1947 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1948 | int func = BP_FUNC(bp); |
1949 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1950 | |
c18487ee YR |
1951 | /* Validating that the resource is within range */ |
1952 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1953 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1954 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1955 | return -EINVAL; | |
1956 | } | |
1957 | ||
4a37fb66 YG |
1958 | if (func <= 5) { |
1959 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1960 | } else { | |
1961 | hw_lock_control_reg = | |
1962 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1963 | } | |
1964 | ||
c18487ee | 1965 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1966 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1967 | if (!(lock_status & resource_bit)) { |
51c1a580 | 1968 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n", |
c18487ee YR |
1969 | lock_status, resource_bit); |
1970 | return -EFAULT; | |
a2fbb9ea ET |
1971 | } |
1972 | ||
9f6c9258 DK |
1973 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1974 | return 0; | |
c18487ee | 1975 | } |
a2fbb9ea | 1976 | |
9f6c9258 | 1977 | |
4acac6a5 EG |
1978 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
1979 | { | |
1980 | /* The GPIO should be swapped if swap register is set and active */ | |
1981 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
1982 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
1983 | int gpio_shift = gpio_num + | |
1984 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
1985 | u32 gpio_mask = (1 << gpio_shift); | |
1986 | u32 gpio_reg; | |
1987 | int value; | |
1988 | ||
1989 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
1990 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
1991 | return -EINVAL; | |
1992 | } | |
1993 | ||
1994 | /* read GPIO value */ | |
1995 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
1996 | ||
1997 | /* get the requested pin value */ | |
1998 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
1999 | value = 1; | |
2000 | else | |
2001 | value = 0; | |
2002 | ||
2003 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
2004 | ||
2005 | return value; | |
2006 | } | |
2007 | ||
17de50b7 | 2008 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
2009 | { |
2010 | /* The GPIO should be swapped if swap register is set and active */ | |
2011 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 2012 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
2013 | int gpio_shift = gpio_num + |
2014 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2015 | u32 gpio_mask = (1 << gpio_shift); | |
2016 | u32 gpio_reg; | |
a2fbb9ea | 2017 | |
c18487ee YR |
2018 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
2019 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2020 | return -EINVAL; | |
2021 | } | |
a2fbb9ea | 2022 | |
4a37fb66 | 2023 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
2024 | /* read GPIO and mask except the float bits */ |
2025 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 2026 | |
c18487ee YR |
2027 | switch (mode) { |
2028 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
2029 | DP(NETIF_MSG_LINK, |
2030 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
2031 | gpio_num, gpio_shift); |
2032 | /* clear FLOAT and set CLR */ | |
2033 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2034 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
2035 | break; | |
a2fbb9ea | 2036 | |
c18487ee | 2037 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
2038 | DP(NETIF_MSG_LINK, |
2039 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
2040 | gpio_num, gpio_shift); |
2041 | /* clear FLOAT and set SET */ | |
2042 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2043 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
2044 | break; | |
a2fbb9ea | 2045 | |
17de50b7 | 2046 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
2047 | DP(NETIF_MSG_LINK, |
2048 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
2049 | gpio_num, gpio_shift); |
2050 | /* set FLOAT */ | |
2051 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2052 | break; | |
a2fbb9ea | 2053 | |
c18487ee YR |
2054 | default: |
2055 | break; | |
a2fbb9ea ET |
2056 | } |
2057 | ||
c18487ee | 2058 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 2059 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 2060 | |
c18487ee | 2061 | return 0; |
a2fbb9ea ET |
2062 | } |
2063 | ||
0d40f0d4 YR |
2064 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
2065 | { | |
2066 | u32 gpio_reg = 0; | |
2067 | int rc = 0; | |
2068 | ||
2069 | /* Any port swapping should be handled by caller. */ | |
2070 | ||
2071 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2072 | /* read GPIO and mask except the float bits */ | |
2073 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2074 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2075 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2076 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
2077 | ||
2078 | switch (mode) { | |
2079 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
2080 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
2081 | /* set CLR */ | |
2082 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2083 | break; | |
2084 | ||
2085 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
2086 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
2087 | /* set SET */ | |
2088 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
2089 | break; | |
2090 | ||
2091 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
2092 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
2093 | /* set FLOAT */ | |
2094 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2095 | break; | |
2096 | ||
2097 | default: | |
2098 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
2099 | rc = -EINVAL; | |
2100 | break; | |
2101 | } | |
2102 | ||
2103 | if (rc == 0) | |
2104 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
2105 | ||
2106 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2107 | ||
2108 | return rc; | |
2109 | } | |
2110 | ||
4acac6a5 EG |
2111 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2112 | { | |
2113 | /* The GPIO should be swapped if swap register is set and active */ | |
2114 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2115 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2116 | int gpio_shift = gpio_num + | |
2117 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2118 | u32 gpio_mask = (1 << gpio_shift); | |
2119 | u32 gpio_reg; | |
2120 | ||
2121 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2122 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2123 | return -EINVAL; | |
2124 | } | |
2125 | ||
2126 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2127 | /* read GPIO int */ | |
2128 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2129 | ||
2130 | switch (mode) { | |
2131 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
2132 | DP(NETIF_MSG_LINK, |
2133 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
2134 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2135 | /* clear SET and set CLR */ |
2136 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2137 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2138 | break; | |
2139 | ||
2140 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2141 | DP(NETIF_MSG_LINK, |
2142 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2143 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2144 | /* clear CLR and set SET */ |
2145 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2146 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2147 | break; | |
2148 | ||
2149 | default: | |
2150 | break; | |
2151 | } | |
2152 | ||
2153 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2154 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2155 | ||
2156 | return 0; | |
2157 | } | |
2158 | ||
d6d99a3f | 2159 | static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) |
a2fbb9ea | 2160 | { |
c18487ee | 2161 | u32 spio_reg; |
a2fbb9ea | 2162 | |
d6d99a3f YM |
2163 | /* Only 2 SPIOs are configurable */ |
2164 | if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { | |
2165 | BNX2X_ERR("Invalid SPIO 0x%x\n", spio); | |
c18487ee | 2166 | return -EINVAL; |
a2fbb9ea ET |
2167 | } |
2168 | ||
4a37fb66 | 2169 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2170 | /* read SPIO and mask except the float bits */ |
d6d99a3f | 2171 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); |
a2fbb9ea | 2172 | |
c18487ee | 2173 | switch (mode) { |
d6d99a3f YM |
2174 | case MISC_SPIO_OUTPUT_LOW: |
2175 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); | |
c18487ee | 2176 | /* clear FLOAT and set CLR */ |
d6d99a3f YM |
2177 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2178 | spio_reg |= (spio << MISC_SPIO_CLR_POS); | |
c18487ee | 2179 | break; |
a2fbb9ea | 2180 | |
d6d99a3f YM |
2181 | case MISC_SPIO_OUTPUT_HIGH: |
2182 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); | |
c18487ee | 2183 | /* clear FLOAT and set SET */ |
d6d99a3f YM |
2184 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2185 | spio_reg |= (spio << MISC_SPIO_SET_POS); | |
c18487ee | 2186 | break; |
a2fbb9ea | 2187 | |
d6d99a3f YM |
2188 | case MISC_SPIO_INPUT_HI_Z: |
2189 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); | |
c18487ee | 2190 | /* set FLOAT */ |
d6d99a3f | 2191 | spio_reg |= (spio << MISC_SPIO_FLOAT_POS); |
c18487ee | 2192 | break; |
a2fbb9ea | 2193 | |
c18487ee YR |
2194 | default: |
2195 | break; | |
a2fbb9ea ET |
2196 | } |
2197 | ||
c18487ee | 2198 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2199 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2200 | |
a2fbb9ea ET |
2201 | return 0; |
2202 | } | |
2203 | ||
9f6c9258 | 2204 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2205 | { |
a22f0788 | 2206 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2207 | switch (bp->link_vars.ieee_fc & |
2208 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2209 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2210 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2211 | ADVERTISED_Pause); |
c18487ee | 2212 | break; |
356e2385 | 2213 | |
c18487ee | 2214 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2215 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2216 | ADVERTISED_Pause); |
c18487ee | 2217 | break; |
356e2385 | 2218 | |
c18487ee | 2219 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2220 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2221 | break; |
356e2385 | 2222 | |
c18487ee | 2223 | default: |
a22f0788 | 2224 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2225 | ADVERTISED_Pause); |
c18487ee YR |
2226 | break; |
2227 | } | |
2228 | } | |
f1410647 | 2229 | |
cd1dfce2 | 2230 | static void bnx2x_set_requested_fc(struct bnx2x *bp) |
c18487ee | 2231 | { |
cd1dfce2 YM |
2232 | /* Initialize link parameters structure variables |
2233 | * It is recommended to turn off RX FC for jumbo frames | |
2234 | * for better performance | |
2235 | */ | |
2236 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
2237 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; | |
2238 | else | |
2239 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; | |
2240 | } | |
a2fbb9ea | 2241 | |
cd1dfce2 YM |
2242 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
2243 | { | |
2244 | int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); | |
2245 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
2246 | ||
2247 | if (!BP_NOMCP(bp)) { | |
2248 | bnx2x_set_requested_fc(bp); | |
4a37fb66 | 2249 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2250 | |
a22f0788 | 2251 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2252 | struct link_params *lp = &bp->link_params; |
2253 | lp->loopback_mode = LOOPBACK_XGXS; | |
2254 | /* do PHY loopback at 10G speed, if possible */ | |
2255 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2256 | if (lp->speed_cap_mask[cfx_idx] & | |
2257 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2258 | lp->req_line_speed[cfx_idx] = | |
2259 | SPEED_10000; | |
2260 | else | |
2261 | lp->req_line_speed[cfx_idx] = | |
2262 | SPEED_1000; | |
2263 | } | |
a22f0788 | 2264 | } |
b5bf9068 | 2265 | |
8970b2e4 MS |
2266 | if (load_mode == LOAD_LOOPBACK_EXT) { |
2267 | struct link_params *lp = &bp->link_params; | |
2268 | lp->loopback_mode = LOOPBACK_EXT; | |
2269 | } | |
2270 | ||
19680c48 | 2271 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2272 | |
4a37fb66 | 2273 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2274 | |
3c96c68b EG |
2275 | bnx2x_calc_fc_adv(bp); |
2276 | ||
cd1dfce2 | 2277 | if (bp->link_vars.link_up) { |
b5bf9068 | 2278 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
19680c48 | 2279 | bnx2x_link_report(bp); |
cd1dfce2 YM |
2280 | } |
2281 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2282 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2283 | return rc; |
2284 | } | |
f5372251 | 2285 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2286 | return -EINVAL; |
a2fbb9ea ET |
2287 | } |
2288 | ||
9f6c9258 | 2289 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2290 | { |
19680c48 | 2291 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2292 | bnx2x_acquire_phy_lock(bp); |
19680c48 | 2293 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2294 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2295 | |
19680c48 EG |
2296 | bnx2x_calc_fc_adv(bp); |
2297 | } else | |
f5372251 | 2298 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2299 | } |
a2fbb9ea | 2300 | |
c18487ee YR |
2301 | static void bnx2x__link_reset(struct bnx2x *bp) |
2302 | { | |
19680c48 | 2303 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2304 | bnx2x_acquire_phy_lock(bp); |
5d07d868 | 2305 | bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2306 | bnx2x_release_phy_lock(bp); |
19680c48 | 2307 | } else |
f5372251 | 2308 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2309 | } |
a2fbb9ea | 2310 | |
5d07d868 YM |
2311 | void bnx2x_force_link_reset(struct bnx2x *bp) |
2312 | { | |
2313 | bnx2x_acquire_phy_lock(bp); | |
2314 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); | |
2315 | bnx2x_release_phy_lock(bp); | |
2316 | } | |
2317 | ||
a22f0788 | 2318 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2319 | { |
2145a920 | 2320 | u8 rc = 0; |
a2fbb9ea | 2321 | |
2145a920 VZ |
2322 | if (!BP_NOMCP(bp)) { |
2323 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2324 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2325 | is_serdes); | |
2145a920 VZ |
2326 | bnx2x_release_phy_lock(bp); |
2327 | } else | |
2328 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2329 | |
c18487ee YR |
2330 | return rc; |
2331 | } | |
a2fbb9ea | 2332 | |
34f80b04 | 2333 | |
2691d51d EG |
2334 | /* Calculates the sum of vn_min_rates. |
2335 | It's needed for further normalizing of the min_rates. | |
2336 | Returns: | |
2337 | sum of vn_min_rates. | |
2338 | or | |
2339 | 0 - if all the min_rates are 0. | |
2340 | In the later case fainess algorithm should be deactivated. | |
2341 | If not all min_rates are zero then those that are zeroes will be set to 1. | |
2342 | */ | |
b475d78f YM |
2343 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2344 | struct cmng_init_input *input) | |
2691d51d EG |
2345 | { |
2346 | int all_zero = 1; | |
2691d51d EG |
2347 | int vn; |
2348 | ||
3395a033 | 2349 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2350 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2351 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2352 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2353 | ||
2354 | /* Skip hidden vns */ | |
2355 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2356 | vn_min_rate = 0; |
2691d51d | 2357 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2358 | else if (!vn_min_rate) |
2691d51d EG |
2359 | vn_min_rate = DEF_MIN_RATE; |
2360 | else | |
2361 | all_zero = 0; | |
2362 | ||
b475d78f | 2363 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2364 | } |
2365 | ||
30ae438b DK |
2366 | /* if ETS or all min rates are zeros - disable fairness */ |
2367 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2368 | input->flags.cmng_enables &= |
30ae438b DK |
2369 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2370 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2371 | } else if (all_zero) { | |
b475d78f | 2372 | input->flags.cmng_enables &= |
b015e3d1 | 2373 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2374 | DP(NETIF_MSG_IFUP, |
2375 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2376 | } else |
b475d78f | 2377 | input->flags.cmng_enables |= |
b015e3d1 | 2378 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2379 | } |
2380 | ||
b475d78f YM |
2381 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2382 | struct cmng_init_input *input) | |
34f80b04 | 2383 | { |
b475d78f | 2384 | u16 vn_max_rate; |
f2e0899f | 2385 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2386 | |
b475d78f | 2387 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2388 | vn_max_rate = 0; |
b475d78f | 2389 | else { |
faa6fcbb DK |
2390 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2391 | ||
b475d78f | 2392 | if (IS_MF_SI(bp)) { |
faa6fcbb DK |
2393 | /* maxCfg in percents of linkspeed */ |
2394 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2395 | } else /* SD modes */ |
faa6fcbb DK |
2396 | /* maxCfg is absolute in 100Mb units */ |
2397 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2398 | } |
f85582f8 | 2399 | |
b475d78f | 2400 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2401 | |
b475d78f | 2402 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2403 | } |
f85582f8 | 2404 | |
b475d78f | 2405 | |
523224a3 DK |
2406 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2407 | { | |
2408 | if (CHIP_REV_IS_SLOW(bp)) | |
2409 | return CMNG_FNS_NONE; | |
fb3bff17 | 2410 | if (IS_MF(bp)) |
523224a3 DK |
2411 | return CMNG_FNS_MINMAX; |
2412 | ||
2413 | return CMNG_FNS_NONE; | |
2414 | } | |
2415 | ||
2ae17f66 | 2416 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2417 | { |
0793f83f | 2418 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2419 | |
2420 | if (BP_NOMCP(bp)) | |
2421 | return; /* what should be the default bvalue in this case */ | |
2422 | ||
0793f83f DK |
2423 | /* For 2 port configuration the absolute function number formula |
2424 | * is: | |
2425 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2426 | * | |
2427 | * and there are 4 functions per port | |
2428 | * | |
2429 | * For 4 port configuration it is | |
2430 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2431 | * | |
2432 | * and there are 2 functions per port | |
2433 | */ | |
3395a033 | 2434 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2435 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2436 | ||
2437 | if (func >= E1H_FUNC_MAX) | |
2438 | break; | |
2439 | ||
f2e0899f | 2440 | bp->mf_config[vn] = |
523224a3 DK |
2441 | MF_CFG_RD(bp, func_mf_config[func].config); |
2442 | } | |
a3348722 BW |
2443 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2444 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2445 | bp->flags |= MF_FUNC_DIS; | |
2446 | } else { | |
2447 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2448 | bp->flags &= ~MF_FUNC_DIS; | |
2449 | } | |
523224a3 DK |
2450 | } |
2451 | ||
2452 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2453 | { | |
b475d78f YM |
2454 | struct cmng_init_input input; |
2455 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2456 | ||
2457 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 DK |
2458 | |
2459 | if (cmng_type == CMNG_FNS_MINMAX) { | |
2460 | int vn; | |
2461 | ||
523224a3 DK |
2462 | /* read mf conf from shmem */ |
2463 | if (read_cfg) | |
2464 | bnx2x_read_mf_cfg(bp); | |
2465 | ||
523224a3 | 2466 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2467 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2468 | |
2469 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2470 | if (bp->port.pmf) |
3395a033 | 2471 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2472 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2473 | |
2474 | /* always enable rate shaping and fairness */ | |
b475d78f | 2475 | input.flags.cmng_enables |= |
523224a3 | 2476 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2477 | |
2478 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2479 | return; |
2480 | } | |
2481 | ||
2482 | /* rate shaping and fairness are disabled */ | |
2483 | DP(NETIF_MSG_IFUP, | |
2484 | "rate shaping and fairness are disabled\n"); | |
2485 | } | |
34f80b04 | 2486 | |
1191cb83 ED |
2487 | static void storm_memset_cmng(struct bnx2x *bp, |
2488 | struct cmng_init *cmng, | |
2489 | u8 port) | |
2490 | { | |
2491 | int vn; | |
2492 | size_t size = sizeof(struct cmng_struct_per_port); | |
2493 | ||
2494 | u32 addr = BAR_XSTRORM_INTMEM + | |
2495 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
2496 | ||
2497 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); | |
2498 | ||
2499 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
2500 | int func = func_by_vn(bp, vn); | |
2501 | ||
2502 | addr = BAR_XSTRORM_INTMEM + | |
2503 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); | |
2504 | size = sizeof(struct rate_shaping_vars_per_vn); | |
2505 | __storm_memset_struct(bp, addr, size, | |
2506 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); | |
2507 | ||
2508 | addr = BAR_XSTRORM_INTMEM + | |
2509 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); | |
2510 | size = sizeof(struct fairness_vars_per_vn); | |
2511 | __storm_memset_struct(bp, addr, size, | |
2512 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); | |
2513 | } | |
2514 | } | |
2515 | ||
c18487ee YR |
2516 | /* This function is called upon link interrupt */ |
2517 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2518 | { | |
bb2a0f7a YG |
2519 | /* Make sure that we are synced with the current statistics */ |
2520 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2521 | ||
c18487ee | 2522 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2523 | |
bb2a0f7a YG |
2524 | if (bp->link_vars.link_up) { |
2525 | ||
1c06328c | 2526 | /* dropless flow control */ |
f2e0899f | 2527 | if (!CHIP_IS_E1(bp) && bp->dropless_fc) { |
1c06328c EG |
2528 | int port = BP_PORT(bp); |
2529 | u32 pause_enabled = 0; | |
2530 | ||
2531 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2532 | pause_enabled = 1; | |
2533 | ||
2534 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
ca00392c | 2535 | USTORM_ETH_PAUSE_ENABLED_OFFSET(port), |
1c06328c EG |
2536 | pause_enabled); |
2537 | } | |
2538 | ||
619c5cb6 | 2539 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2540 | struct host_port_stats *pstats; |
2541 | ||
2542 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2543 | /* reset old mac stats */ |
bb2a0f7a YG |
2544 | memset(&(pstats->mac_stx[0]), 0, |
2545 | sizeof(struct mac_stx)); | |
2546 | } | |
f34d28ea | 2547 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2548 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2549 | } | |
2550 | ||
f2e0899f DK |
2551 | if (bp->link_vars.link_up && bp->link_vars.line_speed) { |
2552 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
8a1c38d1 | 2553 | |
f2e0899f DK |
2554 | if (cmng_fns != CMNG_FNS_NONE) { |
2555 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2556 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2557 | } else | |
2558 | /* rate shaping and fairness are disabled */ | |
2559 | DP(NETIF_MSG_IFUP, | |
2560 | "single function mode without fairness\n"); | |
34f80b04 | 2561 | } |
9fdc3e95 | 2562 | |
2ae17f66 VZ |
2563 | __bnx2x_link_report(bp); |
2564 | ||
9fdc3e95 DK |
2565 | if (IS_MF(bp)) |
2566 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2567 | } |
a2fbb9ea | 2568 | |
9f6c9258 | 2569 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2570 | { |
2ae17f66 | 2571 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2572 | return; |
a2fbb9ea | 2573 | |
00253a8c | 2574 | /* read updated dcb configuration */ |
ad5afc89 AE |
2575 | if (IS_PF(bp)) { |
2576 | bnx2x_dcbx_pmf_update(bp); | |
2577 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); | |
2578 | if (bp->link_vars.link_up) | |
2579 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2580 | else | |
2581 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2582 | /* indicate link status */ | |
2583 | bnx2x_link_report(bp); | |
a2fbb9ea | 2584 | |
ad5afc89 AE |
2585 | } else { /* VF */ |
2586 | bp->port.supported[0] |= (SUPPORTED_10baseT_Half | | |
2587 | SUPPORTED_10baseT_Full | | |
2588 | SUPPORTED_100baseT_Half | | |
2589 | SUPPORTED_100baseT_Full | | |
2590 | SUPPORTED_1000baseT_Full | | |
2591 | SUPPORTED_2500baseX_Full | | |
2592 | SUPPORTED_10000baseT_Full | | |
2593 | SUPPORTED_TP | | |
2594 | SUPPORTED_FIBRE | | |
2595 | SUPPORTED_Autoneg | | |
2596 | SUPPORTED_Pause | | |
2597 | SUPPORTED_Asym_Pause); | |
2598 | bp->port.advertising[0] = bp->port.supported[0]; | |
2599 | ||
2600 | bp->link_params.bp = bp; | |
2601 | bp->link_params.port = BP_PORT(bp); | |
2602 | bp->link_params.req_duplex[0] = DUPLEX_FULL; | |
2603 | bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; | |
2604 | bp->link_params.req_line_speed[0] = SPEED_10000; | |
2605 | bp->link_params.speed_cap_mask[0] = 0x7f0000; | |
2606 | bp->link_params.switch_cfg = SWITCH_CFG_10G; | |
2607 | bp->link_vars.mac_type = MAC_TYPE_BMAC; | |
2608 | bp->link_vars.line_speed = SPEED_10000; | |
2609 | bp->link_vars.link_status = | |
2610 | (LINK_STATUS_LINK_UP | | |
2611 | LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); | |
2612 | bp->link_vars.link_up = 1; | |
2613 | bp->link_vars.duplex = DUPLEX_FULL; | |
2614 | bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
2615 | __bnx2x_link_report(bp); | |
bb2a0f7a | 2616 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
ad5afc89 | 2617 | } |
a2fbb9ea | 2618 | } |
a2fbb9ea | 2619 | |
a3348722 BW |
2620 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2621 | u16 vlan_val, u8 allowed_prio) | |
2622 | { | |
2623 | struct bnx2x_func_state_params func_params = {0}; | |
2624 | struct bnx2x_func_afex_update_params *f_update_params = | |
2625 | &func_params.params.afex_update; | |
2626 | ||
2627 | func_params.f_obj = &bp->func_obj; | |
2628 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2629 | ||
2630 | /* no need to wait for RAMROD completion, so don't | |
2631 | * set RAMROD_COMP_WAIT flag | |
2632 | */ | |
2633 | ||
2634 | f_update_params->vif_id = vifid; | |
2635 | f_update_params->afex_default_vlan = vlan_val; | |
2636 | f_update_params->allowed_priorities = allowed_prio; | |
2637 | ||
2638 | /* if ramrod can not be sent, response to MCP immediately */ | |
2639 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2640 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2641 | ||
2642 | return 0; | |
2643 | } | |
2644 | ||
2645 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2646 | u16 vif_index, u8 func_bit_map) | |
2647 | { | |
2648 | struct bnx2x_func_state_params func_params = {0}; | |
2649 | struct bnx2x_func_afex_viflists_params *update_params = | |
2650 | &func_params.params.afex_viflists; | |
2651 | int rc; | |
2652 | u32 drv_msg_code; | |
2653 | ||
2654 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2655 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2656 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2657 | cmd_type); | |
2658 | ||
2659 | func_params.f_obj = &bp->func_obj; | |
2660 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2661 | ||
2662 | /* set parameters according to cmd_type */ | |
2663 | update_params->afex_vif_list_command = cmd_type; | |
2664 | update_params->vif_list_index = cpu_to_le16(vif_index); | |
2665 | update_params->func_bit_map = | |
2666 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2667 | update_params->func_to_clear = 0; | |
2668 | drv_msg_code = | |
2669 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2670 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2671 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2672 | ||
2673 | /* if ramrod can not be sent, respond to MCP immediately for | |
2674 | * SET and GET requests (other are not triggered from MCP) | |
2675 | */ | |
2676 | rc = bnx2x_func_state_change(bp, &func_params); | |
2677 | if (rc < 0) | |
2678 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2679 | ||
2680 | return 0; | |
2681 | } | |
2682 | ||
2683 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2684 | { | |
2685 | struct afex_stats afex_stats; | |
2686 | u32 func = BP_ABS_FUNC(bp); | |
2687 | u32 mf_config; | |
2688 | u16 vlan_val; | |
2689 | u32 vlan_prio; | |
2690 | u16 vif_id; | |
2691 | u8 allowed_prio; | |
2692 | u8 vlan_mode; | |
2693 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2694 | ||
2695 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2696 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2697 | DP(BNX2X_MSG_MCP, | |
2698 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2699 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2700 | } | |
2701 | ||
2702 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2703 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2704 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2705 | DP(BNX2X_MSG_MCP, | |
2706 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2707 | vifid, addrs); | |
2708 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2709 | addrs); | |
2710 | } | |
2711 | ||
2712 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2713 | addr_to_write = SHMEM2_RD(bp, | |
2714 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2715 | stats_type = SHMEM2_RD(bp, | |
2716 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2717 | ||
2718 | DP(BNX2X_MSG_MCP, | |
2719 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2720 | addr_to_write); | |
2721 | ||
2722 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2723 | ||
2724 | /* write response to scratchpad, for MCP */ | |
2725 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2726 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2727 | *(((u32 *)(&afex_stats))+i)); | |
2728 | ||
2729 | /* send ack message to MCP */ | |
2730 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2731 | } | |
2732 | ||
2733 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2734 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2735 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2736 | DP(BNX2X_MSG_MCP, | |
2737 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2738 | mf_config); | |
2739 | ||
2740 | /* if VIF_SET is "enabled" */ | |
2741 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2742 | /* set rate limit directly to internal RAM */ | |
2743 | struct cmng_init_input cmng_input; | |
2744 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2745 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2746 | u32 addr = BAR_XSTRORM_INTMEM + | |
2747 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2748 | ||
2749 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2750 | ||
2751 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2752 | m_rs_vn.vn_counter.rate = | |
2753 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2754 | m_rs_vn.vn_counter.quota = | |
2755 | (m_rs_vn.vn_counter.rate * | |
2756 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2757 | ||
2758 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2759 | ||
2760 | /* read relevant values from mf_cfg struct in shmem */ | |
2761 | vif_id = | |
2762 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2763 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2764 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2765 | vlan_val = | |
2766 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2767 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2768 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2769 | vlan_prio = (mf_config & | |
2770 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2771 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2772 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2773 | vlan_mode = | |
2774 | (MF_CFG_RD(bp, | |
2775 | func_mf_config[func].afex_config) & | |
2776 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2777 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2778 | allowed_prio = | |
2779 | (MF_CFG_RD(bp, | |
2780 | func_mf_config[func].afex_config) & | |
2781 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2782 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2783 | ||
2784 | /* send ramrod to FW, return in case of failure */ | |
2785 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2786 | allowed_prio)) | |
2787 | return; | |
2788 | ||
2789 | bp->afex_def_vlan_tag = vlan_val; | |
2790 | bp->afex_vlan_mode = vlan_mode; | |
2791 | } else { | |
2792 | /* notify link down because BP->flags is disabled */ | |
2793 | bnx2x_link_report(bp); | |
2794 | ||
2795 | /* send INVALID VIF ramrod to FW */ | |
2796 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2797 | ||
2798 | /* Reset the default afex VLAN */ | |
2799 | bp->afex_def_vlan_tag = -1; | |
2800 | } | |
2801 | } | |
2802 | } | |
2803 | ||
34f80b04 EG |
2804 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2805 | { | |
2806 | int port = BP_PORT(bp); | |
2807 | u32 val; | |
2808 | ||
2809 | bp->port.pmf = 1; | |
51c1a580 | 2810 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2811 | |
3deb8167 YR |
2812 | /* |
2813 | * We need the mb() to ensure the ordering between the writing to | |
2814 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2815 | */ | |
2816 | smp_mb(); | |
2817 | ||
2818 | /* queue a periodic task */ | |
2819 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2820 | ||
ef01854e DK |
2821 | bnx2x_dcbx_pmf_update(bp); |
2822 | ||
34f80b04 | 2823 | /* enable nig attention */ |
3395a033 | 2824 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2825 | if (bp->common.int_block == INT_BLOCK_HC) { |
2826 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2827 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2828 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2829 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2830 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2831 | } | |
bb2a0f7a YG |
2832 | |
2833 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2834 | } |
2835 | ||
c18487ee | 2836 | /* end of Link */ |
a2fbb9ea ET |
2837 | |
2838 | /* slow path */ | |
2839 | ||
2840 | /* | |
2841 | * General service functions | |
2842 | */ | |
2843 | ||
2691d51d | 2844 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2845 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2846 | { |
f2e0899f | 2847 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2848 | u32 seq; |
2691d51d EG |
2849 | u32 rc = 0; |
2850 | u32 cnt = 1; | |
2851 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2852 | ||
c4ff7cbf | 2853 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2854 | seq = ++bp->fw_seq; |
f2e0899f DK |
2855 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2856 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2857 | ||
754a2f52 DK |
2858 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2859 | (command | seq), param); | |
2691d51d EG |
2860 | |
2861 | do { | |
2862 | /* let the FW do it's magic ... */ | |
2863 | msleep(delay); | |
2864 | ||
f2e0899f | 2865 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2866 | |
c4ff7cbf EG |
2867 | /* Give the FW up to 5 second (500*10ms) */ |
2868 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2869 | |
2870 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2871 | cnt*delay, rc, seq); | |
2872 | ||
2873 | /* is this a reply to our command? */ | |
2874 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2875 | rc &= FW_MSG_CODE_MASK; | |
2876 | else { | |
2877 | /* FW BUG! */ | |
2878 | BNX2X_ERR("FW failed to respond!\n"); | |
2879 | bnx2x_fw_dump(bp); | |
2880 | rc = 0; | |
2881 | } | |
c4ff7cbf | 2882 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2883 | |
2884 | return rc; | |
2885 | } | |
2886 | ||
ec6ba945 | 2887 | |
1191cb83 ED |
2888 | static void storm_memset_func_cfg(struct bnx2x *bp, |
2889 | struct tstorm_eth_function_common_config *tcfg, | |
2890 | u16 abs_fid) | |
2891 | { | |
2892 | size_t size = sizeof(struct tstorm_eth_function_common_config); | |
2893 | ||
2894 | u32 addr = BAR_TSTRORM_INTMEM + | |
2895 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); | |
2896 | ||
2897 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); | |
2898 | } | |
2899 | ||
619c5cb6 VZ |
2900 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2901 | { | |
2902 | if (CHIP_IS_E1x(bp)) { | |
2903 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2904 | ||
2905 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2906 | } | |
2907 | ||
2908 | /* Enable the function in the FW */ | |
2909 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2910 | storm_memset_func_en(bp, p->func_id, 1); | |
2911 | ||
2912 | /* spq */ | |
2913 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2914 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2915 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2916 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2917 | } | |
2918 | } | |
2919 | ||
6383c0b3 AE |
2920 | /** |
2921 | * bnx2x_get_tx_only_flags - Return common flags | |
2922 | * | |
2923 | * @bp device handle | |
2924 | * @fp queue handle | |
2925 | * @zero_stats TRUE if statistics zeroing is needed | |
2926 | * | |
2927 | * Return the flags that are common for the Tx-only and not normal connections. | |
2928 | */ | |
1191cb83 ED |
2929 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
2930 | struct bnx2x_fastpath *fp, | |
2931 | bool zero_stats) | |
28912902 | 2932 | { |
619c5cb6 VZ |
2933 | unsigned long flags = 0; |
2934 | ||
2935 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2936 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2937 | |
6383c0b3 AE |
2938 | /* tx only connections collect statistics (on the same index as the |
2939 | * parent connection). The statistics are zeroed when the parent | |
2940 | * connection is initialized. | |
2941 | */ | |
50f0a562 BW |
2942 | |
2943 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2944 | if (zero_stats) | |
2945 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2946 | ||
6383c0b3 AE |
2947 | |
2948 | return flags; | |
2949 | } | |
2950 | ||
1191cb83 ED |
2951 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
2952 | struct bnx2x_fastpath *fp, | |
2953 | bool leading) | |
6383c0b3 AE |
2954 | { |
2955 | unsigned long flags = 0; | |
2956 | ||
619c5cb6 VZ |
2957 | /* calculate other queue flags */ |
2958 | if (IS_MF_SD(bp)) | |
2959 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 2960 | |
a3348722 | 2961 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 2962 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
2963 | /* For FCoE - force usage of default priority (for afex) */ |
2964 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
2965 | } | |
523224a3 | 2966 | |
f5219d8e | 2967 | if (!fp->disable_tpa) { |
619c5cb6 | 2968 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 2969 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
2970 | if (fp->mode == TPA_MODE_GRO) |
2971 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 2972 | } |
619c5cb6 | 2973 | |
619c5cb6 VZ |
2974 | if (leading) { |
2975 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
2976 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
2977 | } | |
523224a3 | 2978 | |
619c5cb6 VZ |
2979 | /* Always set HW VLAN stripping */ |
2980 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 2981 | |
a3348722 BW |
2982 | /* configure silent vlan removal */ |
2983 | if (IS_MF_AFEX(bp)) | |
2984 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
2985 | ||
6383c0b3 AE |
2986 | |
2987 | return flags | bnx2x_get_common_flags(bp, fp, true); | |
523224a3 DK |
2988 | } |
2989 | ||
619c5cb6 | 2990 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
2991 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
2992 | u8 cos) | |
619c5cb6 VZ |
2993 | { |
2994 | gen_init->stat_id = bnx2x_stats_id(fp); | |
2995 | gen_init->spcl_id = fp->cl_id; | |
2996 | ||
2997 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
2998 | if (IS_FCOE_FP(fp)) | |
2999 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
3000 | else | |
3001 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
3002 | |
3003 | gen_init->cos = cos; | |
619c5cb6 VZ |
3004 | } |
3005 | ||
3006 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 3007 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 3008 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 3009 | { |
619c5cb6 | 3010 | u8 max_sge = 0; |
523224a3 DK |
3011 | u16 sge_sz = 0; |
3012 | u16 tpa_agg_size = 0; | |
3013 | ||
523224a3 | 3014 | if (!fp->disable_tpa) { |
dfacf138 DK |
3015 | pause->sge_th_lo = SGE_TH_LO(bp); |
3016 | pause->sge_th_hi = SGE_TH_HI(bp); | |
3017 | ||
3018 | /* validate SGE ring has enough to cross high threshold */ | |
3019 | WARN_ON(bp->dropless_fc && | |
3020 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
3021 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
3022 | ||
523224a3 DK |
3023 | tpa_agg_size = min_t(u32, |
3024 | (min_t(u32, 8, MAX_SKB_FRAGS) * | |
3025 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); | |
3026 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> | |
3027 | SGE_PAGE_SHIFT; | |
3028 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
3029 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
3030 | sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE, | |
3031 | 0xffff); | |
3032 | } | |
3033 | ||
3034 | /* pause - not for e1 */ | |
3035 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
3036 | pause->bd_th_lo = BD_TH_LO(bp); |
3037 | pause->bd_th_hi = BD_TH_HI(bp); | |
3038 | ||
3039 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
3040 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
3041 | /* | |
3042 | * validate that rings have enough entries to cross | |
3043 | * high thresholds | |
3044 | */ | |
3045 | WARN_ON(bp->dropless_fc && | |
3046 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
3047 | bp->rx_ring_size); | |
3048 | WARN_ON(bp->dropless_fc && | |
3049 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
3050 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 3051 | |
523224a3 DK |
3052 | pause->pri_map = 1; |
3053 | } | |
3054 | ||
3055 | /* rxq setup */ | |
523224a3 DK |
3056 | rxq_init->dscr_map = fp->rx_desc_mapping; |
3057 | rxq_init->sge_map = fp->rx_sge_mapping; | |
3058 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
3059 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 3060 | |
619c5cb6 VZ |
3061 | /* This should be a maximum number of data bytes that may be |
3062 | * placed on the BD (not including paddings). | |
3063 | */ | |
e52fcb24 ED |
3064 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
3065 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; | |
a8c94b91 | 3066 | |
523224a3 | 3067 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
3068 | rxq_init->tpa_agg_sz = tpa_agg_size; |
3069 | rxq_init->sge_buf_sz = sge_sz; | |
3070 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 3071 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 3072 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
3073 | |
3074 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
3075 | * | |
3076 | * For PF Clients it should be the maximum avaliable number. | |
3077 | * VF driver(s) may want to define it to a smaller value. | |
3078 | */ | |
dfacf138 | 3079 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 3080 | |
523224a3 DK |
3081 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
3082 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
3083 | ||
ec6ba945 VZ |
3084 | if (IS_FCOE_FP(fp)) |
3085 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
3086 | else | |
6383c0b3 | 3087 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
3088 | /* configure silent vlan removal |
3089 | * if multi function mode is afex, then mask default vlan | |
3090 | */ | |
3091 | if (IS_MF_AFEX(bp)) { | |
3092 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
3093 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
3094 | } | |
523224a3 DK |
3095 | } |
3096 | ||
619c5cb6 | 3097 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
3098 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
3099 | u8 cos) | |
523224a3 | 3100 | { |
65565884 | 3101 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
6383c0b3 | 3102 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
523224a3 DK |
3103 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
3104 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 3105 | |
619c5cb6 VZ |
3106 | /* |
3107 | * set the tss leading client id for TX classfication == | |
3108 | * leading RSS client id | |
3109 | */ | |
3110 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
3111 | ||
ec6ba945 VZ |
3112 | if (IS_FCOE_FP(fp)) { |
3113 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
3114 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
3115 | } | |
523224a3 DK |
3116 | } |
3117 | ||
8d96286a | 3118 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
3119 | { |
3120 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
3121 | struct event_ring_data eq_data = { {0} }; |
3122 | u16 flags; | |
3123 | ||
619c5cb6 | 3124 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
3125 | /* reset IGU PF statistics: MSIX + ATTN */ |
3126 | /* PF */ | |
3127 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3128 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3129 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3130 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3131 | /* ATTN */ | |
3132 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3133 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3134 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
3135 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3136 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3137 | } | |
3138 | ||
523224a3 DK |
3139 | /* function setup flags */ |
3140 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
3141 | ||
619c5cb6 VZ |
3142 | /* This flag is relevant for E1x only. |
3143 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 3144 | */ |
619c5cb6 | 3145 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
3146 | |
3147 | func_init.func_flgs = flags; | |
3148 | func_init.pf_id = BP_FUNC(bp); | |
3149 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
3150 | func_init.spq_map = bp->spq_mapping; |
3151 | func_init.spq_prod = bp->spq_prod_idx; | |
3152 | ||
3153 | bnx2x_func_init(bp, &func_init); | |
3154 | ||
3155 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
3156 | ||
3157 | /* | |
619c5cb6 VZ |
3158 | * Congestion management values depend on the link rate |
3159 | * There is no active link so initial link rate is set to 10 Gbps. | |
3160 | * When the link comes up The congestion management values are | |
3161 | * re-calculated according to the actual link rate. | |
3162 | */ | |
523224a3 DK |
3163 | bp->link_vars.line_speed = SPEED_10000; |
3164 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
3165 | ||
3166 | /* Only the PMF sets the HW */ | |
3167 | if (bp->port.pmf) | |
3168 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3169 | ||
523224a3 DK |
3170 | /* init Event Queue */ |
3171 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); | |
3172 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
3173 | eq_data.producer = bp->eq_prod; | |
3174 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
3175 | eq_data.sb_id = DEF_SB_ID; | |
3176 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
3177 | } | |
3178 | ||
3179 | ||
3180 | static void bnx2x_e1h_disable(struct bnx2x *bp) | |
3181 | { | |
3182 | int port = BP_PORT(bp); | |
3183 | ||
619c5cb6 | 3184 | bnx2x_tx_disable(bp); |
523224a3 DK |
3185 | |
3186 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
3187 | } |
3188 | ||
3189 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
3190 | { | |
3191 | int port = BP_PORT(bp); | |
3192 | ||
3193 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
3194 | ||
3195 | /* Tx queue should be only reenabled */ | |
3196 | netif_tx_wake_all_queues(bp->dev); | |
3197 | ||
3198 | /* | |
3199 | * Should not call netif_carrier_on since it will be called if the link | |
3200 | * is up when checking for link state | |
3201 | */ | |
3202 | } | |
3203 | ||
1d187b34 BW |
3204 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
3205 | ||
3206 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
3207 | { | |
3208 | struct eth_stats_info *ether_stat = | |
3209 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
3210 | ||
786fdf0b DC |
3211 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, |
3212 | ETH_STAT_INFO_VERSION_LEN); | |
1d187b34 | 3213 | |
15192a8c BW |
3214 | bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj, |
3215 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
3216 | ether_stat->mac_local); | |
1d187b34 BW |
3217 | |
3218 | ether_stat->mtu_size = bp->dev->mtu; | |
3219 | ||
3220 | if (bp->dev->features & NETIF_F_RXCSUM) | |
3221 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
3222 | if (bp->dev->features & NETIF_F_TSO) | |
3223 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
3224 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3225 | ||
3226 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3227 | ||
3228 | ether_stat->txq_size = bp->tx_ring_size; | |
3229 | ether_stat->rxq_size = bp->rx_ring_size; | |
3230 | } | |
3231 | ||
3232 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3233 | { | |
3234 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3235 | struct fcoe_stats_info *fcoe_stat = | |
3236 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3237 | ||
55c11941 MS |
3238 | if (!CNIC_LOADED(bp)) |
3239 | return; | |
3240 | ||
2e499d3c BW |
3241 | memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT, |
3242 | bp->fip_mac, ETH_ALEN); | |
1d187b34 BW |
3243 | |
3244 | fcoe_stat->qos_priority = | |
3245 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3246 | ||
3247 | /* insert FCoE stats from ramrod response */ | |
3248 | if (!NO_FCOE(bp)) { | |
3249 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
65565884 | 3250 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3251 | tstorm_queue_statistics; |
3252 | ||
3253 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
65565884 | 3254 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3255 | xstorm_queue_statistics; |
3256 | ||
3257 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3258 | &bp->fw_stats_data->fcoe; | |
3259 | ||
3260 | ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo, | |
3261 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
3262 | ||
3263 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3264 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3265 | fcoe_stat->rx_bytes_lo, | |
3266 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
3267 | ||
3268 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3269 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3270 | fcoe_stat->rx_bytes_lo, | |
3271 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
3272 | ||
3273 | ADD_64(fcoe_stat->rx_bytes_hi, | |
3274 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3275 | fcoe_stat->rx_bytes_lo, | |
3276 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
3277 | ||
3278 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3279 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
3280 | ||
3281 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3282 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
3283 | ||
3284 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
3285 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
3286 | ||
3287 | ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo, | |
f33f1fcc | 3288 | fcoe_q_tstorm_stats->rcv_mcast_pkts); |
1d187b34 BW |
3289 | |
3290 | ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo, | |
3291 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
3292 | ||
3293 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3294 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3295 | fcoe_stat->tx_bytes_lo, | |
3296 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
3297 | ||
3298 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3299 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3300 | fcoe_stat->tx_bytes_lo, | |
3301 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
3302 | ||
3303 | ADD_64(fcoe_stat->tx_bytes_hi, | |
3304 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3305 | fcoe_stat->tx_bytes_lo, | |
3306 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
3307 | ||
3308 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3309 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
3310 | ||
3311 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3312 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
3313 | ||
3314 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3315 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
3316 | ||
3317 | ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo, | |
3318 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
3319 | } | |
3320 | ||
1d187b34 BW |
3321 | /* ask L5 driver to add data to the struct */ |
3322 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
1d187b34 BW |
3323 | } |
3324 | ||
3325 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3326 | { | |
3327 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3328 | struct iscsi_stats_info *iscsi_stat = | |
3329 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3330 | ||
55c11941 MS |
3331 | if (!CNIC_LOADED(bp)) |
3332 | return; | |
3333 | ||
2e499d3c BW |
3334 | memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT, |
3335 | bp->cnic_eth_dev.iscsi_mac, ETH_ALEN); | |
1d187b34 BW |
3336 | |
3337 | iscsi_stat->qos_priority = | |
3338 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3339 | ||
1d187b34 BW |
3340 | /* ask L5 driver to add data to the struct */ |
3341 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
1d187b34 BW |
3342 | } |
3343 | ||
0793f83f DK |
3344 | /* called due to MCP event (on pmf): |
3345 | * reread new bandwidth configuration | |
3346 | * configure FW | |
3347 | * notify others function about the change | |
3348 | */ | |
1191cb83 | 3349 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3350 | { |
3351 | if (bp->link_vars.link_up) { | |
3352 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3353 | bnx2x_link_sync_notify(bp); | |
3354 | } | |
3355 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3356 | } | |
3357 | ||
1191cb83 | 3358 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3359 | { |
3360 | bnx2x_config_mf_bw(bp); | |
3361 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3362 | } | |
3363 | ||
c8c60d88 YM |
3364 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
3365 | { | |
3366 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); | |
3367 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); | |
3368 | } | |
3369 | ||
1d187b34 BW |
3370 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3371 | { | |
3372 | enum drv_info_opcode op_code; | |
3373 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
3374 | ||
3375 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3376 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3377 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3378 | return; | |
3379 | } | |
3380 | ||
3381 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3382 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3383 | ||
3384 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3385 | sizeof(union drv_info_to_mcp)); | |
3386 | ||
3387 | switch (op_code) { | |
3388 | case ETH_STATS_OPCODE: | |
3389 | bnx2x_drv_info_ether_stat(bp); | |
3390 | break; | |
3391 | case FCOE_STATS_OPCODE: | |
3392 | bnx2x_drv_info_fcoe_stat(bp); | |
3393 | break; | |
3394 | case ISCSI_STATS_OPCODE: | |
3395 | bnx2x_drv_info_iscsi_stat(bp); | |
3396 | break; | |
3397 | default: | |
3398 | /* if op code isn't supported - send NACK */ | |
3399 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3400 | return; | |
3401 | } | |
3402 | ||
3403 | /* if we got drv_info attn from MFW then these fields are defined in | |
3404 | * shmem2 for sure | |
3405 | */ | |
3406 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3407 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3408 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3409 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3410 | ||
3411 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
3412 | } | |
3413 | ||
523224a3 DK |
3414 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
3415 | { | |
3416 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
3417 | ||
3418 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
3419 | ||
3420 | /* | |
3421 | * This is the only place besides the function initialization | |
3422 | * where the bp->flags can change so it is done without any | |
3423 | * locks | |
3424 | */ | |
f2e0899f | 3425 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3426 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3427 | bp->flags |= MF_FUNC_DIS; |
3428 | ||
3429 | bnx2x_e1h_disable(bp); | |
3430 | } else { | |
51c1a580 | 3431 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3432 | bp->flags &= ~MF_FUNC_DIS; |
3433 | ||
3434 | bnx2x_e1h_enable(bp); | |
3435 | } | |
3436 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
3437 | } | |
3438 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 3439 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
3440 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
3441 | } | |
3442 | ||
3443 | /* Report results to MCP */ | |
3444 | if (dcc_event) | |
3445 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
3446 | else | |
3447 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
3448 | } | |
3449 | ||
3450 | /* must be called under the spq lock */ | |
1191cb83 | 3451 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
523224a3 DK |
3452 | { |
3453 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3454 | ||
3455 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3456 | bp->spq_prod_bd = bp->spq; | |
3457 | bp->spq_prod_idx = 0; | |
51c1a580 | 3458 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3459 | } else { |
3460 | bp->spq_prod_bd++; | |
3461 | bp->spq_prod_idx++; | |
3462 | } | |
3463 | return next_spe; | |
3464 | } | |
3465 | ||
3466 | /* must be called under the spq lock */ | |
1191cb83 | 3467 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
28912902 MC |
3468 | { |
3469 | int func = BP_FUNC(bp); | |
3470 | ||
53e51e2f VZ |
3471 | /* |
3472 | * Make sure that BD data is updated before writing the producer: | |
3473 | * BD data is written to the memory, the producer is read from the | |
3474 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3475 | */ | |
3476 | mb(); | |
28912902 | 3477 | |
523224a3 | 3478 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3479 | bp->spq_prod_idx); |
28912902 MC |
3480 | mmiowb(); |
3481 | } | |
3482 | ||
619c5cb6 VZ |
3483 | /** |
3484 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3485 | * | |
3486 | * @cmd: command to check | |
3487 | * @cmd_type: command type | |
3488 | */ | |
1191cb83 | 3489 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
619c5cb6 VZ |
3490 | { |
3491 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3492 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3493 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3494 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3495 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3496 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3497 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3498 | return true; | |
3499 | else | |
3500 | return false; | |
3501 | ||
3502 | } | |
3503 | ||
3504 | ||
3505 | /** | |
3506 | * bnx2x_sp_post - place a single command on an SP ring | |
3507 | * | |
3508 | * @bp: driver handle | |
3509 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3510 | * @cid: SW CID the command is related to | |
3511 | * @data_hi: command private data address (high 32 bits) | |
3512 | * @data_lo: command private data address (low 32 bits) | |
3513 | * @cmd_type: command type (e.g. NONE, ETH) | |
3514 | * | |
3515 | * SP data is handled as if it's always an address pair, thus data fields are | |
3516 | * not swapped to little endian in upper functions. Instead this function swaps | |
3517 | * data as if it's two u32 fields. | |
3518 | */ | |
9f6c9258 | 3519 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3520 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3521 | { |
28912902 | 3522 | struct eth_spe *spe; |
523224a3 | 3523 | u16 type; |
619c5cb6 | 3524 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3525 | |
a2fbb9ea | 3526 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3527 | if (unlikely(bp->panic)) { |
3528 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3529 | return -EIO; |
51c1a580 | 3530 | } |
a2fbb9ea ET |
3531 | #endif |
3532 | ||
34f80b04 | 3533 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3534 | |
6e30dd4e VZ |
3535 | if (common) { |
3536 | if (!atomic_read(&bp->eq_spq_left)) { | |
3537 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3538 | spin_unlock_bh(&bp->spq_lock); | |
3539 | bnx2x_panic(); | |
3540 | return -EBUSY; | |
3541 | } | |
3542 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3543 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3544 | spin_unlock_bh(&bp->spq_lock); | |
3545 | bnx2x_panic(); | |
3546 | return -EBUSY; | |
a2fbb9ea | 3547 | } |
f1410647 | 3548 | |
28912902 MC |
3549 | spe = bnx2x_sp_get_next(bp); |
3550 | ||
a2fbb9ea | 3551 | /* CID needs port number to be encoded int it */ |
28912902 | 3552 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3553 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3554 | HW_CID(bp, cid)); | |
523224a3 | 3555 | |
619c5cb6 | 3556 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3557 | |
523224a3 DK |
3558 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3559 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3560 | |
523224a3 DK |
3561 | spe->hdr.type = cpu_to_le16(type); |
3562 | ||
3563 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3564 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3565 | ||
d6cae238 VZ |
3566 | /* |
3567 | * It's ok if the actual decrement is issued towards the memory | |
3568 | * somewhere between the spin_lock and spin_unlock. Thus no | |
3569 | * more explict memory barrier is needed. | |
3570 | */ | |
3571 | if (common) | |
3572 | atomic_dec(&bp->eq_spq_left); | |
3573 | else | |
3574 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3575 | |
a2fbb9ea | 3576 | |
51c1a580 MS |
3577 | DP(BNX2X_MSG_SP, |
3578 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3579 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3580 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3581 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3582 | HW_CID(bp, cid), data_hi, data_lo, type, |
3583 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3584 | |
28912902 | 3585 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3586 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3587 | return 0; |
3588 | } | |
3589 | ||
3590 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3591 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3592 | { |
72fd0718 | 3593 | u32 j, val; |
34f80b04 | 3594 | int rc = 0; |
a2fbb9ea ET |
3595 | |
3596 | might_sleep(); | |
72fd0718 | 3597 | for (j = 0; j < 1000; j++) { |
a2fbb9ea ET |
3598 | val = (1UL << 31); |
3599 | REG_WR(bp, GRCBASE_MCP + 0x9c, val); | |
3600 | val = REG_RD(bp, GRCBASE_MCP + 0x9c); | |
3601 | if (val & (1L << 31)) | |
3602 | break; | |
3603 | ||
3604 | msleep(5); | |
3605 | } | |
a2fbb9ea | 3606 | if (!(val & (1L << 31))) { |
19680c48 | 3607 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3608 | rc = -EBUSY; |
3609 | } | |
3610 | ||
3611 | return rc; | |
3612 | } | |
3613 | ||
4a37fb66 YG |
3614 | /* release split MCP access lock register */ |
3615 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3616 | { |
72fd0718 | 3617 | REG_WR(bp, GRCBASE_MCP + 0x9c, 0); |
a2fbb9ea ET |
3618 | } |
3619 | ||
523224a3 DK |
3620 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3621 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3622 | ||
1191cb83 | 3623 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
a2fbb9ea | 3624 | { |
523224a3 | 3625 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3626 | u16 rc = 0; |
3627 | ||
3628 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3629 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3630 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3631 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3632 | } |
523224a3 DK |
3633 | |
3634 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3635 | bp->def_idx = def_sb->sp_sb.running_index; | |
3636 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3637 | } |
523224a3 DK |
3638 | |
3639 | /* Do not reorder: indecies reading should complete before handling */ | |
3640 | barrier(); | |
a2fbb9ea ET |
3641 | return rc; |
3642 | } | |
3643 | ||
3644 | /* | |
3645 | * slow path service functions | |
3646 | */ | |
3647 | ||
3648 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3649 | { | |
34f80b04 | 3650 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3651 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3652 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3653 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3654 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3655 | u32 aeu_mask; |
87942b46 | 3656 | u32 nig_mask = 0; |
f2e0899f | 3657 | u32 reg_addr; |
a2fbb9ea | 3658 | |
a2fbb9ea ET |
3659 | if (bp->attn_state & asserted) |
3660 | BNX2X_ERR("IGU ERROR\n"); | |
3661 | ||
3fcaf2e5 EG |
3662 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3663 | aeu_mask = REG_RD(bp, aeu_addr); | |
3664 | ||
a2fbb9ea | 3665 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3666 | aeu_mask, asserted); |
72fd0718 | 3667 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3668 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3669 | |
3fcaf2e5 EG |
3670 | REG_WR(bp, aeu_addr, aeu_mask); |
3671 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3672 | |
3fcaf2e5 | 3673 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3674 | bp->attn_state |= asserted; |
3fcaf2e5 | 3675 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3676 | |
3677 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3678 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3679 | |
a5e9a7cf EG |
3680 | bnx2x_acquire_phy_lock(bp); |
3681 | ||
877e9aa4 | 3682 | /* save nig interrupt mask */ |
87942b46 | 3683 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3684 | |
361c391e YR |
3685 | /* If nig_mask is not set, no need to call the update |
3686 | * function. | |
3687 | */ | |
3688 | if (nig_mask) { | |
3689 | REG_WR(bp, nig_int_mask_addr, 0); | |
3690 | ||
3691 | bnx2x_link_attn(bp); | |
3692 | } | |
a2fbb9ea ET |
3693 | |
3694 | /* handle unicore attn? */ | |
3695 | } | |
3696 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3697 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3698 | ||
3699 | if (asserted & GPIO_2_FUNC) | |
3700 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3701 | ||
3702 | if (asserted & GPIO_3_FUNC) | |
3703 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3704 | ||
3705 | if (asserted & GPIO_4_FUNC) | |
3706 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3707 | ||
3708 | if (port == 0) { | |
3709 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3710 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3711 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3712 | } | |
3713 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3714 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3715 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3716 | } | |
3717 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3718 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3719 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3720 | } | |
3721 | } else { | |
3722 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3723 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3724 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3725 | } | |
3726 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3727 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3728 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3729 | } | |
3730 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3731 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3732 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3733 | } | |
3734 | } | |
3735 | ||
3736 | } /* if hardwired */ | |
3737 | ||
f2e0899f DK |
3738 | if (bp->common.int_block == INT_BLOCK_HC) |
3739 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3740 | COMMAND_REG_ATTN_BITS_SET); | |
3741 | else | |
3742 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3743 | ||
3744 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3745 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3746 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3747 | |
3748 | /* now set back the mask */ | |
a5e9a7cf | 3749 | if (asserted & ATTN_NIG_FOR_FUNC) { |
27c1151c YR |
3750 | /* Verify that IGU ack through BAR was written before restoring |
3751 | * NIG mask. This loop should exit after 2-3 iterations max. | |
3752 | */ | |
3753 | if (bp->common.int_block != INT_BLOCK_HC) { | |
3754 | u32 cnt = 0, igu_acked; | |
3755 | do { | |
3756 | igu_acked = REG_RD(bp, | |
3757 | IGU_REG_ATTENTION_ACK_BITS); | |
3758 | } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && | |
3759 | (++cnt < MAX_IGU_ATTN_ACK_TO)); | |
3760 | if (!igu_acked) | |
3761 | DP(NETIF_MSG_HW, | |
3762 | "Failed to verify IGU ack on time\n"); | |
3763 | barrier(); | |
3764 | } | |
87942b46 | 3765 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3766 | bnx2x_release_phy_lock(bp); |
3767 | } | |
a2fbb9ea ET |
3768 | } |
3769 | ||
1191cb83 | 3770 | static void bnx2x_fan_failure(struct bnx2x *bp) |
fd4ef40d EG |
3771 | { |
3772 | int port = BP_PORT(bp); | |
b7737c9b | 3773 | u32 ext_phy_config; |
fd4ef40d | 3774 | /* mark the failure */ |
b7737c9b YR |
3775 | ext_phy_config = |
3776 | SHMEM_RD(bp, | |
3777 | dev_info.port_hw_config[port].external_phy_config); | |
3778 | ||
3779 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3780 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3781 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3782 | ext_phy_config); |
fd4ef40d EG |
3783 | |
3784 | /* log the failure */ | |
51c1a580 MS |
3785 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
3786 | "Please contact OEM Support for assistance\n"); | |
8304859a AE |
3787 | |
3788 | /* | |
3789 | * Scheudle device reset (unload) | |
3790 | * This is due to some boards consuming sufficient power when driver is | |
3791 | * up to overheat if fan fails. | |
3792 | */ | |
3793 | smp_mb__before_clear_bit(); | |
3794 | set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); | |
3795 | smp_mb__after_clear_bit(); | |
3796 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
3797 | ||
fd4ef40d | 3798 | } |
ab6ad5a4 | 3799 | |
1191cb83 | 3800 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3801 | { |
34f80b04 | 3802 | int port = BP_PORT(bp); |
877e9aa4 | 3803 | int reg_offset; |
d90d96ba | 3804 | u32 val; |
877e9aa4 | 3805 | |
34f80b04 EG |
3806 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3807 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3808 | |
34f80b04 | 3809 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3810 | |
3811 | val = REG_RD(bp, reg_offset); | |
3812 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3813 | REG_WR(bp, reg_offset, val); | |
3814 | ||
3815 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3816 | ||
fd4ef40d | 3817 | /* Fan failure attention */ |
d90d96ba | 3818 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3819 | bnx2x_fan_failure(bp); |
877e9aa4 | 3820 | } |
34f80b04 | 3821 | |
3deb8167 | 3822 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3823 | bnx2x_acquire_phy_lock(bp); |
3824 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3825 | bnx2x_release_phy_lock(bp); | |
3826 | } | |
3827 | ||
34f80b04 EG |
3828 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3829 | ||
3830 | val = REG_RD(bp, reg_offset); | |
3831 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3832 | REG_WR(bp, reg_offset, val); | |
3833 | ||
3834 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3835 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3836 | bnx2x_panic(); |
3837 | } | |
877e9aa4 ET |
3838 | } |
3839 | ||
1191cb83 | 3840 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3841 | { |
3842 | u32 val; | |
3843 | ||
0626b899 | 3844 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3845 | |
3846 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3847 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3848 | /* DORQ discard attention */ | |
3849 | if (val & 0x2) | |
3850 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3851 | } | |
34f80b04 EG |
3852 | |
3853 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3854 | ||
3855 | int port = BP_PORT(bp); | |
3856 | int reg_offset; | |
3857 | ||
3858 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3859 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3860 | ||
3861 | val = REG_RD(bp, reg_offset); | |
3862 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3863 | REG_WR(bp, reg_offset, val); | |
3864 | ||
3865 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3866 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3867 | bnx2x_panic(); |
3868 | } | |
877e9aa4 ET |
3869 | } |
3870 | ||
1191cb83 | 3871 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3872 | { |
3873 | u32 val; | |
3874 | ||
3875 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3876 | ||
3877 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3878 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3879 | /* CFC error attention */ | |
3880 | if (val & 0x2) | |
3881 | BNX2X_ERR("FATAL error from CFC\n"); | |
3882 | } | |
3883 | ||
3884 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3885 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3886 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3887 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3888 | if (val & 0x18000) | |
3889 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3890 | |
3891 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3892 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3893 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3894 | } | |
877e9aa4 | 3895 | } |
34f80b04 EG |
3896 | |
3897 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3898 | ||
3899 | int port = BP_PORT(bp); | |
3900 | int reg_offset; | |
3901 | ||
3902 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3903 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3904 | ||
3905 | val = REG_RD(bp, reg_offset); | |
3906 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3907 | REG_WR(bp, reg_offset, val); | |
3908 | ||
3909 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3910 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3911 | bnx2x_panic(); |
3912 | } | |
877e9aa4 ET |
3913 | } |
3914 | ||
1191cb83 | 3915 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
877e9aa4 | 3916 | { |
34f80b04 EG |
3917 | u32 val; |
3918 | ||
877e9aa4 ET |
3919 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3920 | ||
34f80b04 EG |
3921 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3922 | int func = BP_FUNC(bp); | |
3923 | ||
3924 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 3925 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
3926 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3927 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3928 | val = SHMEM_RD(bp, | |
3929 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3930 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3931 | bnx2x_dcc_event(bp, | |
3932 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3933 | |
3934 | if (val & DRV_STATUS_SET_MF_BW) | |
3935 | bnx2x_set_mf_bw(bp); | |
3936 | ||
1d187b34 BW |
3937 | if (val & DRV_STATUS_DRV_INFO_REQ) |
3938 | bnx2x_handle_drv_info_req(bp); | |
d16132ce AE |
3939 | |
3940 | if (val & DRV_STATUS_VF_DISABLED) | |
3941 | bnx2x_vf_handle_flr_event(bp); | |
3942 | ||
2691d51d | 3943 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3944 | bnx2x_pmf_update(bp); |
3945 | ||
e4901dde | 3946 | if (bp->port.pmf && |
785b9b1a SR |
3947 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
3948 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
3949 | /* start dcbx state machine */ |
3950 | bnx2x_dcbx_set_params(bp, | |
3951 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
3952 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
3953 | bnx2x_handle_afex_cmd(bp, | |
3954 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
c8c60d88 YM |
3955 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
3956 | bnx2x_handle_eee_event(bp); | |
3deb8167 YR |
3957 | if (bp->link_vars.periodic_flags & |
3958 | PERIODIC_FLAGS_LINK_EVENT) { | |
3959 | /* sync with link */ | |
3960 | bnx2x_acquire_phy_lock(bp); | |
3961 | bp->link_vars.periodic_flags &= | |
3962 | ~PERIODIC_FLAGS_LINK_EVENT; | |
3963 | bnx2x_release_phy_lock(bp); | |
3964 | if (IS_MF(bp)) | |
3965 | bnx2x_link_sync_notify(bp); | |
3966 | bnx2x_link_report(bp); | |
3967 | } | |
3968 | /* Always call it here: bnx2x_link_report() will | |
3969 | * prevent the link indication duplication. | |
3970 | */ | |
3971 | bnx2x__link_status_update(bp); | |
34f80b04 | 3972 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
3973 | |
3974 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 3975 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
3976 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
3977 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
3978 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
3979 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
3980 | bnx2x_panic(); | |
3981 | ||
3982 | } else if (attn & BNX2X_MCP_ASSERT) { | |
3983 | ||
3984 | BNX2X_ERR("MCP assert!\n"); | |
3985 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 3986 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
3987 | |
3988 | } else | |
3989 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
3990 | } | |
3991 | ||
3992 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
3993 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
3994 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
3995 | val = CHIP_IS_E1(bp) ? 0 : |
3996 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
3997 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
3998 | } | |
3999 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
4000 | val = CHIP_IS_E1(bp) ? 0 : |
4001 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
4002 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
4003 | } | |
877e9aa4 | 4004 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
4005 | } |
4006 | } | |
4007 | ||
c9ee9206 VZ |
4008 | /* |
4009 | * Bits map: | |
4010 | * 0-7 - Engine0 load counter. | |
4011 | * 8-15 - Engine1 load counter. | |
4012 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
4013 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
4014 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
4015 | * on the engine | |
4016 | * 19 - Engine1 ONE_IS_LOADED. | |
4017 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
4018 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
4019 | * just the one belonging to its engine). | |
4020 | * | |
4021 | */ | |
4022 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
4023 | ||
4024 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
4025 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
4026 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
4027 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
4028 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
4029 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
4030 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
4031 | ||
4032 | /* | |
4033 | * Set the GLOBAL_RESET bit. | |
4034 | * | |
4035 | * Should be run under rtnl lock | |
4036 | */ | |
4037 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
4038 | { | |
f16da43b AE |
4039 | u32 val; |
4040 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4041 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4042 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 4043 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
4044 | } |
4045 | ||
4046 | /* | |
4047 | * Clear the GLOBAL_RESET bit. | |
4048 | * | |
4049 | * Should be run under rtnl lock | |
4050 | */ | |
1191cb83 | 4051 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
c9ee9206 | 4052 | { |
f16da43b AE |
4053 | u32 val; |
4054 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4055 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4056 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 4057 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 4058 | } |
f85582f8 | 4059 | |
72fd0718 | 4060 | /* |
c9ee9206 VZ |
4061 | * Checks the GLOBAL_RESET bit. |
4062 | * | |
72fd0718 VZ |
4063 | * should be run under rtnl lock |
4064 | */ | |
1191cb83 | 4065 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
c9ee9206 VZ |
4066 | { |
4067 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4068 | ||
4069 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
4070 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
4071 | } | |
4072 | ||
4073 | /* | |
4074 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
4075 | * | |
4076 | * Should be run under rtnl lock | |
4077 | */ | |
1191cb83 | 4078 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
72fd0718 | 4079 | { |
f16da43b | 4080 | u32 val; |
c9ee9206 VZ |
4081 | u32 bit = BP_PATH(bp) ? |
4082 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4083 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4084 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4085 | |
4086 | /* Clear the bit */ | |
4087 | val &= ~bit; | |
4088 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4089 | |
4090 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
4091 | } |
4092 | ||
4093 | /* | |
c9ee9206 VZ |
4094 | * Set RESET_IN_PROGRESS for the current engine. |
4095 | * | |
72fd0718 VZ |
4096 | * should be run under rtnl lock |
4097 | */ | |
c9ee9206 | 4098 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 4099 | { |
f16da43b | 4100 | u32 val; |
c9ee9206 VZ |
4101 | u32 bit = BP_PATH(bp) ? |
4102 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4103 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4104 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4105 | |
4106 | /* Set the bit */ | |
4107 | val |= bit; | |
4108 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4109 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4110 | } |
4111 | ||
4112 | /* | |
c9ee9206 | 4113 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
4114 | * should be run under rtnl lock |
4115 | */ | |
c9ee9206 | 4116 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 4117 | { |
c9ee9206 VZ |
4118 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
4119 | u32 bit = engine ? | |
4120 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
4121 | ||
4122 | /* return false if bit is set */ | |
4123 | return (val & bit) ? false : true; | |
72fd0718 VZ |
4124 | } |
4125 | ||
4126 | /* | |
889b9af3 | 4127 | * set pf load for the current pf. |
c9ee9206 | 4128 | * |
72fd0718 VZ |
4129 | * should be run under rtnl lock |
4130 | */ | |
889b9af3 | 4131 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 4132 | { |
f16da43b | 4133 | u32 val1, val; |
c9ee9206 VZ |
4134 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4135 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4136 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4137 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4138 | |
f16da43b AE |
4139 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4140 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4141 | ||
51c1a580 | 4142 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4143 | |
c9ee9206 VZ |
4144 | /* get the current counter value */ |
4145 | val1 = (val & mask) >> shift; | |
4146 | ||
889b9af3 AE |
4147 | /* set bit of that PF */ |
4148 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
4149 | |
4150 | /* clear the old value */ | |
4151 | val &= ~mask; | |
4152 | ||
4153 | /* set the new one */ | |
4154 | val |= ((val1 << shift) & mask); | |
4155 | ||
4156 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4157 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4158 | } |
4159 | ||
c9ee9206 | 4160 | /** |
889b9af3 | 4161 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
4162 | * |
4163 | * @bp: driver handle | |
4164 | * | |
4165 | * Should be run under rtnl lock. | |
4166 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 4167 | * whether other functions are still loaded |
72fd0718 | 4168 | */ |
889b9af3 | 4169 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 4170 | { |
f16da43b | 4171 | u32 val1, val; |
c9ee9206 VZ |
4172 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4173 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4174 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4175 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4176 | |
f16da43b AE |
4177 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4178 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 4179 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4180 | |
c9ee9206 VZ |
4181 | /* get the current counter value */ |
4182 | val1 = (val & mask) >> shift; | |
4183 | ||
889b9af3 AE |
4184 | /* clear bit of that PF */ |
4185 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
4186 | |
4187 | /* clear the old value */ | |
4188 | val &= ~mask; | |
4189 | ||
4190 | /* set the new one */ | |
4191 | val |= ((val1 << shift) & mask); | |
4192 | ||
4193 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4194 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4195 | return val1 != 0; | |
72fd0718 VZ |
4196 | } |
4197 | ||
4198 | /* | |
889b9af3 | 4199 | * Read the load status for the current engine. |
c9ee9206 | 4200 | * |
72fd0718 VZ |
4201 | * should be run under rtnl lock |
4202 | */ | |
1191cb83 | 4203 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 4204 | { |
c9ee9206 VZ |
4205 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
4206 | BNX2X_PATH0_LOAD_CNT_MASK); | |
4207 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4208 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
4209 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4210 | ||
51c1a580 | 4211 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
4212 | |
4213 | val = (val & mask) >> shift; | |
4214 | ||
51c1a580 MS |
4215 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
4216 | engine, val); | |
c9ee9206 | 4217 | |
889b9af3 | 4218 | return val != 0; |
72fd0718 VZ |
4219 | } |
4220 | ||
1191cb83 | 4221 | static void _print_next_block(int idx, const char *blk) |
72fd0718 | 4222 | { |
f1deab50 | 4223 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
4224 | } |
4225 | ||
1191cb83 ED |
4226 | static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num, |
4227 | bool print) | |
72fd0718 VZ |
4228 | { |
4229 | int i = 0; | |
4230 | u32 cur_bit = 0; | |
4231 | for (i = 0; sig; i++) { | |
4232 | cur_bit = ((u32)0x1 << i); | |
4233 | if (sig & cur_bit) { | |
4234 | switch (cur_bit) { | |
4235 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
c9ee9206 VZ |
4236 | if (print) |
4237 | _print_next_block(par_num++, "BRB"); | |
72fd0718 VZ |
4238 | break; |
4239 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
c9ee9206 VZ |
4240 | if (print) |
4241 | _print_next_block(par_num++, "PARSER"); | |
72fd0718 VZ |
4242 | break; |
4243 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4244 | if (print) |
4245 | _print_next_block(par_num++, "TSDM"); | |
72fd0718 VZ |
4246 | break; |
4247 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
c9ee9206 VZ |
4248 | if (print) |
4249 | _print_next_block(par_num++, | |
4250 | "SEARCHER"); | |
4251 | break; | |
4252 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
4253 | if (print) | |
4254 | _print_next_block(par_num++, "TCM"); | |
72fd0718 VZ |
4255 | break; |
4256 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4257 | if (print) |
4258 | _print_next_block(par_num++, "TSEMI"); | |
4259 | break; | |
4260 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
4261 | if (print) | |
4262 | _print_next_block(par_num++, "XPB"); | |
72fd0718 VZ |
4263 | break; |
4264 | } | |
4265 | ||
4266 | /* Clear the bit */ | |
4267 | sig &= ~cur_bit; | |
4268 | } | |
4269 | } | |
4270 | ||
4271 | return par_num; | |
4272 | } | |
4273 | ||
1191cb83 ED |
4274 | static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num, |
4275 | bool *global, bool print) | |
72fd0718 VZ |
4276 | { |
4277 | int i = 0; | |
4278 | u32 cur_bit = 0; | |
4279 | for (i = 0; sig; i++) { | |
4280 | cur_bit = ((u32)0x1 << i); | |
4281 | if (sig & cur_bit) { | |
4282 | switch (cur_bit) { | |
c9ee9206 VZ |
4283 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
4284 | if (print) | |
4285 | _print_next_block(par_num++, "PBF"); | |
72fd0718 VZ |
4286 | break; |
4287 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
c9ee9206 VZ |
4288 | if (print) |
4289 | _print_next_block(par_num++, "QM"); | |
4290 | break; | |
4291 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
4292 | if (print) | |
4293 | _print_next_block(par_num++, "TM"); | |
72fd0718 VZ |
4294 | break; |
4295 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4296 | if (print) |
4297 | _print_next_block(par_num++, "XSDM"); | |
4298 | break; | |
4299 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
4300 | if (print) | |
4301 | _print_next_block(par_num++, "XCM"); | |
72fd0718 VZ |
4302 | break; |
4303 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4304 | if (print) |
4305 | _print_next_block(par_num++, "XSEMI"); | |
72fd0718 VZ |
4306 | break; |
4307 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
c9ee9206 VZ |
4308 | if (print) |
4309 | _print_next_block(par_num++, | |
4310 | "DOORBELLQ"); | |
4311 | break; | |
4312 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
4313 | if (print) | |
4314 | _print_next_block(par_num++, "NIG"); | |
72fd0718 VZ |
4315 | break; |
4316 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
4317 | if (print) |
4318 | _print_next_block(par_num++, | |
4319 | "VAUX PCI CORE"); | |
4320 | *global = true; | |
72fd0718 VZ |
4321 | break; |
4322 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
c9ee9206 VZ |
4323 | if (print) |
4324 | _print_next_block(par_num++, "DEBUG"); | |
72fd0718 VZ |
4325 | break; |
4326 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
c9ee9206 VZ |
4327 | if (print) |
4328 | _print_next_block(par_num++, "USDM"); | |
72fd0718 | 4329 | break; |
8736c826 VZ |
4330 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
4331 | if (print) | |
4332 | _print_next_block(par_num++, "UCM"); | |
4333 | break; | |
72fd0718 | 4334 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
c9ee9206 VZ |
4335 | if (print) |
4336 | _print_next_block(par_num++, "USEMI"); | |
72fd0718 VZ |
4337 | break; |
4338 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
c9ee9206 VZ |
4339 | if (print) |
4340 | _print_next_block(par_num++, "UPB"); | |
72fd0718 VZ |
4341 | break; |
4342 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
c9ee9206 VZ |
4343 | if (print) |
4344 | _print_next_block(par_num++, "CSDM"); | |
72fd0718 | 4345 | break; |
8736c826 VZ |
4346 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
4347 | if (print) | |
4348 | _print_next_block(par_num++, "CCM"); | |
4349 | break; | |
72fd0718 VZ |
4350 | } |
4351 | ||
4352 | /* Clear the bit */ | |
4353 | sig &= ~cur_bit; | |
4354 | } | |
4355 | } | |
4356 | ||
4357 | return par_num; | |
4358 | } | |
4359 | ||
1191cb83 ED |
4360 | static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num, |
4361 | bool print) | |
72fd0718 VZ |
4362 | { |
4363 | int i = 0; | |
4364 | u32 cur_bit = 0; | |
4365 | for (i = 0; sig; i++) { | |
4366 | cur_bit = ((u32)0x1 << i); | |
4367 | if (sig & cur_bit) { | |
4368 | switch (cur_bit) { | |
4369 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
c9ee9206 VZ |
4370 | if (print) |
4371 | _print_next_block(par_num++, "CSEMI"); | |
72fd0718 VZ |
4372 | break; |
4373 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
c9ee9206 VZ |
4374 | if (print) |
4375 | _print_next_block(par_num++, "PXP"); | |
72fd0718 VZ |
4376 | break; |
4377 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
4378 | if (print) |
4379 | _print_next_block(par_num++, | |
72fd0718 VZ |
4380 | "PXPPCICLOCKCLIENT"); |
4381 | break; | |
4382 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
c9ee9206 VZ |
4383 | if (print) |
4384 | _print_next_block(par_num++, "CFC"); | |
72fd0718 VZ |
4385 | break; |
4386 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
c9ee9206 VZ |
4387 | if (print) |
4388 | _print_next_block(par_num++, "CDU"); | |
4389 | break; | |
4390 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
4391 | if (print) | |
4392 | _print_next_block(par_num++, "DMAE"); | |
72fd0718 VZ |
4393 | break; |
4394 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
c9ee9206 VZ |
4395 | if (print) |
4396 | _print_next_block(par_num++, "IGU"); | |
72fd0718 VZ |
4397 | break; |
4398 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
c9ee9206 VZ |
4399 | if (print) |
4400 | _print_next_block(par_num++, "MISC"); | |
72fd0718 VZ |
4401 | break; |
4402 | } | |
4403 | ||
4404 | /* Clear the bit */ | |
4405 | sig &= ~cur_bit; | |
4406 | } | |
4407 | } | |
4408 | ||
4409 | return par_num; | |
4410 | } | |
4411 | ||
1191cb83 ED |
4412 | static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
4413 | bool *global, bool print) | |
72fd0718 VZ |
4414 | { |
4415 | int i = 0; | |
4416 | u32 cur_bit = 0; | |
4417 | for (i = 0; sig; i++) { | |
4418 | cur_bit = ((u32)0x1 << i); | |
4419 | if (sig & cur_bit) { | |
4420 | switch (cur_bit) { | |
4421 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
4422 | if (print) |
4423 | _print_next_block(par_num++, "MCP ROM"); | |
4424 | *global = true; | |
72fd0718 VZ |
4425 | break; |
4426 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
4427 | if (print) |
4428 | _print_next_block(par_num++, | |
4429 | "MCP UMP RX"); | |
4430 | *global = true; | |
72fd0718 VZ |
4431 | break; |
4432 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
4433 | if (print) |
4434 | _print_next_block(par_num++, | |
4435 | "MCP UMP TX"); | |
4436 | *global = true; | |
72fd0718 VZ |
4437 | break; |
4438 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
4439 | if (print) |
4440 | _print_next_block(par_num++, | |
4441 | "MCP SCPAD"); | |
4442 | *global = true; | |
72fd0718 VZ |
4443 | break; |
4444 | } | |
4445 | ||
4446 | /* Clear the bit */ | |
4447 | sig &= ~cur_bit; | |
4448 | } | |
4449 | } | |
4450 | ||
4451 | return par_num; | |
4452 | } | |
4453 | ||
1191cb83 ED |
4454 | static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num, |
4455 | bool print) | |
8736c826 VZ |
4456 | { |
4457 | int i = 0; | |
4458 | u32 cur_bit = 0; | |
4459 | for (i = 0; sig; i++) { | |
4460 | cur_bit = ((u32)0x1 << i); | |
4461 | if (sig & cur_bit) { | |
4462 | switch (cur_bit) { | |
4463 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
4464 | if (print) | |
4465 | _print_next_block(par_num++, "PGLUE_B"); | |
4466 | break; | |
4467 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
4468 | if (print) | |
4469 | _print_next_block(par_num++, "ATC"); | |
4470 | break; | |
4471 | } | |
4472 | ||
4473 | /* Clear the bit */ | |
4474 | sig &= ~cur_bit; | |
4475 | } | |
4476 | } | |
4477 | ||
4478 | return par_num; | |
4479 | } | |
4480 | ||
1191cb83 ED |
4481 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
4482 | u32 *sig) | |
72fd0718 | 4483 | { |
8736c826 VZ |
4484 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4485 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4486 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4487 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4488 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4489 | int par_num = 0; |
51c1a580 MS |
4490 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4491 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4492 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4493 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4494 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4495 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4496 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4497 | if (print) |
4498 | netdev_err(bp->dev, | |
4499 | "Parity errors detected in blocks: "); | |
4500 | par_num = bnx2x_check_blocks_with_parity0( | |
8736c826 | 4501 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
c9ee9206 | 4502 | par_num = bnx2x_check_blocks_with_parity1( |
8736c826 | 4503 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
c9ee9206 | 4504 | par_num = bnx2x_check_blocks_with_parity2( |
8736c826 | 4505 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
c9ee9206 | 4506 | par_num = bnx2x_check_blocks_with_parity3( |
8736c826 VZ |
4507 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
4508 | par_num = bnx2x_check_blocks_with_parity4( | |
4509 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); | |
4510 | ||
c9ee9206 VZ |
4511 | if (print) |
4512 | pr_cont("\n"); | |
8736c826 | 4513 | |
72fd0718 VZ |
4514 | return true; |
4515 | } else | |
4516 | return false; | |
4517 | } | |
4518 | ||
c9ee9206 VZ |
4519 | /** |
4520 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4521 | * | |
4522 | * @bp: driver handle | |
4523 | * @global: true if there was a global attention | |
4524 | * @print: show parity attention in syslog | |
4525 | */ | |
4526 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4527 | { |
8736c826 | 4528 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4529 | int port = BP_PORT(bp); |
4530 | ||
4531 | attn.sig[0] = REG_RD(bp, | |
4532 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4533 | port*4); | |
4534 | attn.sig[1] = REG_RD(bp, | |
4535 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4536 | port*4); | |
4537 | attn.sig[2] = REG_RD(bp, | |
4538 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4539 | port*4); | |
4540 | attn.sig[3] = REG_RD(bp, | |
4541 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4542 | port*4); | |
4543 | ||
8736c826 VZ |
4544 | if (!CHIP_IS_E1x(bp)) |
4545 | attn.sig[4] = REG_RD(bp, | |
4546 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4547 | port*4); | |
4548 | ||
4549 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4550 | } |
4551 | ||
f2e0899f | 4552 | |
1191cb83 | 4553 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
f2e0899f DK |
4554 | { |
4555 | u32 val; | |
4556 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
4557 | ||
4558 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
4559 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
4560 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 4561 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 4562 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 4563 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 4564 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 4565 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 4566 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 4567 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
4568 | if (val & |
4569 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 4570 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
4571 | if (val & |
4572 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 4573 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 4574 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 4575 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 4576 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 4577 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 4578 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 4579 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
4580 | } |
4581 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4582 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4583 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4584 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4585 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4586 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 4587 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 4588 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 4589 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 4590 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 4591 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
4592 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
4593 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4594 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 4595 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
4596 | } |
4597 | ||
4598 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4599 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4600 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4601 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4602 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4603 | } | |
4604 | ||
4605 | } | |
4606 | ||
72fd0718 VZ |
4607 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4608 | { | |
4609 | struct attn_route attn, *group_mask; | |
34f80b04 | 4610 | int port = BP_PORT(bp); |
877e9aa4 | 4611 | int index; |
a2fbb9ea ET |
4612 | u32 reg_addr; |
4613 | u32 val; | |
3fcaf2e5 | 4614 | u32 aeu_mask; |
c9ee9206 | 4615 | bool global = false; |
a2fbb9ea ET |
4616 | |
4617 | /* need to take HW lock because MCP or other port might also | |
4618 | try to handle this event */ | |
4a37fb66 | 4619 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4620 | |
c9ee9206 VZ |
4621 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4622 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4623 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4624 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4625 | /* Disable HW interrupts */ |
4626 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4627 | /* In case of parity errors don't handle attentions so that |
4628 | * other function would "see" parity errors. | |
4629 | */ | |
c9ee9206 VZ |
4630 | #else |
4631 | bnx2x_panic(); | |
4632 | #endif | |
4633 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4634 | return; |
4635 | } | |
4636 | ||
a2fbb9ea ET |
4637 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4638 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4639 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4640 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4641 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4642 | attn.sig[4] = |
4643 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4644 | else | |
4645 | attn.sig[4] = 0; | |
4646 | ||
4647 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4648 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4649 | |
4650 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4651 | if (deasserted & (1 << index)) { | |
72fd0718 | 4652 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4653 | |
51c1a580 | 4654 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
4655 | index, |
4656 | group_mask->sig[0], group_mask->sig[1], | |
4657 | group_mask->sig[2], group_mask->sig[3], | |
4658 | group_mask->sig[4]); | |
a2fbb9ea | 4659 | |
f2e0899f DK |
4660 | bnx2x_attn_int_deasserted4(bp, |
4661 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4662 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4663 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4664 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4665 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4666 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4667 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4668 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4669 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4670 | } |
4671 | } | |
4672 | ||
4a37fb66 | 4673 | bnx2x_release_alr(bp); |
a2fbb9ea | 4674 | |
f2e0899f DK |
4675 | if (bp->common.int_block == INT_BLOCK_HC) |
4676 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4677 | COMMAND_REG_ATTN_BITS_CLR); | |
4678 | else | |
4679 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4680 | |
4681 | val = ~deasserted; | |
f2e0899f DK |
4682 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4683 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4684 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4685 | |
a2fbb9ea | 4686 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4687 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4688 | |
4689 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4690 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4691 | ||
3fcaf2e5 EG |
4692 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4693 | aeu_mask = REG_RD(bp, reg_addr); | |
4694 | ||
4695 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4696 | aeu_mask, deasserted); | |
72fd0718 | 4697 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4698 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4699 | |
3fcaf2e5 EG |
4700 | REG_WR(bp, reg_addr, aeu_mask); |
4701 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4702 | |
4703 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4704 | bp->attn_state &= ~deasserted; | |
4705 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4706 | } | |
4707 | ||
4708 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4709 | { | |
4710 | /* read local copy of bits */ | |
68d59484 EG |
4711 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4712 | attn_bits); | |
4713 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4714 | attn_bits_ack); | |
a2fbb9ea ET |
4715 | u32 attn_state = bp->attn_state; |
4716 | ||
4717 | /* look for changed bits */ | |
4718 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4719 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4720 | ||
4721 | DP(NETIF_MSG_HW, | |
4722 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4723 | attn_bits, attn_ack, asserted, deasserted); | |
4724 | ||
4725 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4726 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4727 | |
4728 | /* handle bits that were raised */ | |
4729 | if (asserted) | |
4730 | bnx2x_attn_int_asserted(bp, asserted); | |
4731 | ||
4732 | if (deasserted) | |
4733 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4734 | } | |
4735 | ||
619c5cb6 VZ |
4736 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4737 | u16 index, u8 op, u8 update) | |
4738 | { | |
dc1ba591 AE |
4739 | u32 igu_addr = bp->igu_base_addr; |
4740 | igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
619c5cb6 VZ |
4741 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, |
4742 | igu_addr); | |
4743 | } | |
4744 | ||
1191cb83 | 4745 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
523224a3 DK |
4746 | { |
4747 | /* No memory barriers */ | |
4748 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4749 | mmiowb(); /* keep prod updates ordered */ | |
4750 | } | |
4751 | ||
523224a3 DK |
4752 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, |
4753 | union event_ring_elem *elem) | |
4754 | { | |
619c5cb6 VZ |
4755 | u8 err = elem->message.error; |
4756 | ||
523224a3 | 4757 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4758 | (cid < bp->cnic_eth_dev.starting_cid && |
4759 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4760 | return 1; |
4761 | ||
4762 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4763 | ||
619c5cb6 VZ |
4764 | if (unlikely(err)) { |
4765 | ||
523224a3 DK |
4766 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4767 | cid); | |
4768 | bnx2x_panic_dump(bp); | |
4769 | } | |
619c5cb6 | 4770 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4771 | return 0; |
4772 | } | |
523224a3 | 4773 | |
1191cb83 | 4774 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
4775 | { |
4776 | struct bnx2x_mcast_ramrod_params rparam; | |
4777 | int rc; | |
4778 | ||
4779 | memset(&rparam, 0, sizeof(rparam)); | |
4780 | ||
4781 | rparam.mcast_obj = &bp->mcast_obj; | |
4782 | ||
4783 | netif_addr_lock_bh(bp->dev); | |
4784 | ||
4785 | /* Clear pending state for the last command */ | |
4786 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4787 | ||
4788 | /* If there are pending mcast commands - send them */ | |
4789 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4790 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4791 | if (rc < 0) | |
4792 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4793 | rc); | |
4794 | } | |
4795 | ||
4796 | netif_addr_unlock_bh(bp->dev); | |
4797 | } | |
4798 | ||
1191cb83 ED |
4799 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
4800 | union event_ring_elem *elem) | |
619c5cb6 VZ |
4801 | { |
4802 | unsigned long ramrod_flags = 0; | |
4803 | int rc = 0; | |
4804 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4805 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4806 | ||
4807 | /* Always push next commands out, don't wait here */ | |
4808 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4809 | ||
4810 | switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { | |
4811 | case BNX2X_FILTER_MAC_PENDING: | |
51c1a580 | 4812 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
55c11941 | 4813 | if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) |
619c5cb6 VZ |
4814 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
4815 | else | |
15192a8c | 4816 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
619c5cb6 VZ |
4817 | |
4818 | break; | |
619c5cb6 | 4819 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 4820 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
4821 | /* This is only relevant for 57710 where multicast MACs are |
4822 | * configured as unicast MACs using the same ramrod. | |
4823 | */ | |
4824 | bnx2x_handle_mcast_eqe(bp); | |
4825 | return; | |
4826 | default: | |
4827 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4828 | elem->message.data.eth_event.echo); | |
4829 | return; | |
4830 | } | |
4831 | ||
4832 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4833 | ||
4834 | if (rc < 0) | |
4835 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4836 | else if (rc > 0) | |
4837 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
4838 | ||
4839 | } | |
4840 | ||
619c5cb6 | 4841 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); |
619c5cb6 | 4842 | |
1191cb83 | 4843 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
4844 | { |
4845 | netif_addr_lock_bh(bp->dev); | |
4846 | ||
4847 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
4848 | ||
4849 | /* Send rx_mode command again if was requested */ | |
4850 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
4851 | bnx2x_set_storm_rx_mode(bp); | |
619c5cb6 VZ |
4852 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, |
4853 | &bp->sp_state)) | |
4854 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
4855 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
4856 | &bp->sp_state)) | |
4857 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
619c5cb6 VZ |
4858 | |
4859 | netif_addr_unlock_bh(bp->dev); | |
4860 | } | |
4861 | ||
1191cb83 | 4862 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
a3348722 BW |
4863 | union event_ring_elem *elem) |
4864 | { | |
4865 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
4866 | DP(BNX2X_MSG_SP, | |
4867 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
4868 | elem->message.data.vif_list_event.func_bit_map); | |
4869 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
4870 | elem->message.data.vif_list_event.func_bit_map); | |
4871 | } else if (elem->message.data.vif_list_event.echo == | |
4872 | VIF_LIST_RULE_SET) { | |
4873 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
4874 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
4875 | } | |
4876 | } | |
4877 | ||
4878 | /* called with rtnl_lock */ | |
1191cb83 | 4879 | static void bnx2x_after_function_update(struct bnx2x *bp) |
a3348722 BW |
4880 | { |
4881 | int q, rc; | |
4882 | struct bnx2x_fastpath *fp; | |
4883 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
4884 | struct bnx2x_queue_update_params *q_update_params = | |
4885 | &queue_params.params.update; | |
4886 | ||
4887 | /* Send Q update command with afex vlan removal values for all Qs */ | |
4888 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; | |
4889 | ||
4890 | /* set silent vlan removal values according to vlan mode */ | |
4891 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
4892 | &q_update_params->update_flags); | |
4893 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
4894 | &q_update_params->update_flags); | |
4895 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
4896 | ||
4897 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
4898 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
4899 | q_update_params->silent_removal_value = 0; | |
4900 | q_update_params->silent_removal_mask = 0; | |
4901 | } else { | |
4902 | q_update_params->silent_removal_value = | |
4903 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
4904 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
4905 | } | |
4906 | ||
4907 | for_each_eth_queue(bp, q) { | |
4908 | /* Set the appropriate Queue object */ | |
4909 | fp = &bp->fp[q]; | |
15192a8c | 4910 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
4911 | |
4912 | /* send the ramrod */ | |
4913 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
4914 | if (rc < 0) | |
4915 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
4916 | q); | |
4917 | } | |
4918 | ||
a3348722 | 4919 | if (!NO_FCOE(bp)) { |
65565884 | 4920 | fp = &bp->fp[FCOE_IDX(bp)]; |
15192a8c | 4921 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
4922 | |
4923 | /* clear pending completion bit */ | |
4924 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
4925 | ||
4926 | /* mark latest Q bit */ | |
4927 | smp_mb__before_clear_bit(); | |
4928 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
4929 | smp_mb__after_clear_bit(); | |
4930 | ||
4931 | /* send Q update ramrod for FCoE Q */ | |
4932 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
4933 | if (rc < 0) | |
4934 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
4935 | q); | |
4936 | } else { | |
4937 | /* If no FCoE ring - ACK MCP now */ | |
4938 | bnx2x_link_report(bp); | |
4939 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
4940 | } | |
a3348722 BW |
4941 | } |
4942 | ||
1191cb83 | 4943 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
619c5cb6 VZ |
4944 | struct bnx2x *bp, u32 cid) |
4945 | { | |
94f05b0f | 4946 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
55c11941 MS |
4947 | |
4948 | if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) | |
15192a8c | 4949 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
619c5cb6 | 4950 | else |
15192a8c | 4951 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
619c5cb6 VZ |
4952 | } |
4953 | ||
523224a3 DK |
4954 | static void bnx2x_eq_int(struct bnx2x *bp) |
4955 | { | |
4956 | u16 hw_cons, sw_cons, sw_prod; | |
4957 | union event_ring_elem *elem; | |
55c11941 | 4958 | u8 echo; |
523224a3 DK |
4959 | u32 cid; |
4960 | u8 opcode; | |
fd1fc79d | 4961 | int rc, spqe_cnt = 0; |
619c5cb6 VZ |
4962 | struct bnx2x_queue_sp_obj *q_obj; |
4963 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
4964 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
4965 | |
4966 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
4967 | ||
4968 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
4969 | * when we get the the next-page we nned to adjust so the loop | |
4970 | * condition below will be met. The next element is the size of a | |
4971 | * regular element and hence incrementing by 1 | |
4972 | */ | |
4973 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
4974 | hw_cons++; | |
4975 | ||
25985edc | 4976 | /* This function may never run in parallel with itself for a |
523224a3 DK |
4977 | * specific bp, thus there is no need in "paired" read memory |
4978 | * barrier here. | |
4979 | */ | |
4980 | sw_cons = bp->eq_cons; | |
4981 | sw_prod = bp->eq_prod; | |
4982 | ||
d6cae238 | 4983 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 4984 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
4985 | |
4986 | for (; sw_cons != hw_cons; | |
4987 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
4988 | ||
4989 | ||
4990 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; | |
4991 | ||
fd1fc79d AE |
4992 | rc = bnx2x_iov_eq_sp_event(bp, elem); |
4993 | if (!rc) { | |
4994 | DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", | |
4995 | rc); | |
4996 | goto next_spqe; | |
4997 | } | |
523224a3 DK |
4998 | cid = SW_CID(elem->message.data.cfc_del_event.cid); |
4999 | opcode = elem->message.opcode; | |
5000 | ||
5001 | ||
5002 | /* handle eq element */ | |
5003 | switch (opcode) { | |
fd1fc79d AE |
5004 | case EVENT_RING_OPCODE_VF_PF_CHANNEL: |
5005 | DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n"); | |
5006 | bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event); | |
5007 | continue; | |
5008 | ||
523224a3 | 5009 | case EVENT_RING_OPCODE_STAT_QUERY: |
51c1a580 MS |
5010 | DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, |
5011 | "got statistics comp event %d\n", | |
619c5cb6 | 5012 | bp->stats_comp++); |
523224a3 | 5013 | /* nothing to do with stats comp */ |
d6cae238 | 5014 | goto next_spqe; |
523224a3 DK |
5015 | |
5016 | case EVENT_RING_OPCODE_CFC_DEL: | |
5017 | /* handle according to cid range */ | |
5018 | /* | |
5019 | * we may want to verify here that the bp state is | |
5020 | * HALTING | |
5021 | */ | |
d6cae238 | 5022 | DP(BNX2X_MSG_SP, |
523224a3 | 5023 | "got delete ramrod for MULTI[%d]\n", cid); |
55c11941 MS |
5024 | |
5025 | if (CNIC_LOADED(bp) && | |
5026 | !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
523224a3 | 5027 | goto next_spqe; |
55c11941 | 5028 | |
619c5cb6 VZ |
5029 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
5030 | ||
5031 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
5032 | break; | |
5033 | ||
5034 | ||
523224a3 DK |
5035 | |
5036 | goto next_spqe; | |
e4901dde VZ |
5037 | |
5038 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 5039 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6debea87 DK |
5040 | if (f_obj->complete_cmd(bp, f_obj, |
5041 | BNX2X_F_CMD_TX_STOP)) | |
5042 | break; | |
e4901dde VZ |
5043 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
5044 | goto next_spqe; | |
619c5cb6 | 5045 | |
e4901dde | 5046 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 5047 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6debea87 DK |
5048 | if (f_obj->complete_cmd(bp, f_obj, |
5049 | BNX2X_F_CMD_TX_START)) | |
5050 | break; | |
e4901dde VZ |
5051 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
5052 | goto next_spqe; | |
55c11941 | 5053 | |
a3348722 | 5054 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
55c11941 MS |
5055 | echo = elem->message.data.function_update_event.echo; |
5056 | if (echo == SWITCH_UPDATE) { | |
5057 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, | |
5058 | "got FUNC_SWITCH_UPDATE ramrod\n"); | |
5059 | if (f_obj->complete_cmd( | |
5060 | bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) | |
5061 | break; | |
a3348722 | 5062 | |
55c11941 MS |
5063 | } else { |
5064 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, | |
5065 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
5066 | f_obj->complete_cmd(bp, f_obj, | |
5067 | BNX2X_F_CMD_AFEX_UPDATE); | |
5068 | ||
5069 | /* We will perform the Queues update from | |
5070 | * sp_rtnl task as all Queue SP operations | |
5071 | * should run under rtnl_lock. | |
5072 | */ | |
5073 | smp_mb__before_clear_bit(); | |
5074 | set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, | |
5075 | &bp->sp_rtnl_state); | |
5076 | smp_mb__after_clear_bit(); | |
5077 | ||
5078 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
5079 | } | |
a3348722 | 5080 | |
a3348722 BW |
5081 | goto next_spqe; |
5082 | ||
5083 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
5084 | f_obj->complete_cmd(bp, f_obj, | |
5085 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
5086 | bnx2x_after_afex_vif_lists(bp, elem); | |
5087 | goto next_spqe; | |
619c5cb6 | 5088 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
5089 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5090 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
5091 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
5092 | break; | |
5093 | ||
5094 | goto next_spqe; | |
5095 | ||
5096 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
5097 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5098 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
5099 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
5100 | break; | |
5101 | ||
5102 | goto next_spqe; | |
523224a3 DK |
5103 | } |
5104 | ||
5105 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
5106 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
5107 | BNX2X_STATE_OPEN): | |
5108 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 5109 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
5110 | cid = elem->message.data.eth_event.echo & |
5111 | BNX2X_SWCID_MASK; | |
d6cae238 | 5112 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
5113 | cid); |
5114 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
5115 | break; |
5116 | ||
619c5cb6 VZ |
5117 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
5118 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
5119 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 5120 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
5121 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
5122 | BNX2X_STATE_OPEN): | |
5123 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5124 | BNX2X_STATE_DIAG): | |
5125 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5126 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5127 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 5128 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
5129 | break; |
5130 | ||
619c5cb6 VZ |
5131 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
5132 | BNX2X_STATE_OPEN): | |
5133 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5134 | BNX2X_STATE_DIAG): | |
5135 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5136 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5137 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 5138 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
5139 | break; |
5140 | ||
619c5cb6 VZ |
5141 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
5142 | BNX2X_STATE_OPEN): | |
5143 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
5144 | BNX2X_STATE_DIAG): | |
5145 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 5146 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 5147 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 5148 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
5149 | break; |
5150 | default: | |
5151 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
5152 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
5153 | elem->message.opcode, bp->state); | |
523224a3 DK |
5154 | } |
5155 | next_spqe: | |
5156 | spqe_cnt++; | |
5157 | } /* for */ | |
5158 | ||
8fe23fbd | 5159 | smp_mb__before_atomic_inc(); |
6e30dd4e | 5160 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
5161 | |
5162 | bp->eq_cons = sw_cons; | |
5163 | bp->eq_prod = sw_prod; | |
5164 | /* Make sure that above mem writes were issued towards the memory */ | |
5165 | smp_wmb(); | |
5166 | ||
5167 | /* update producer */ | |
5168 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
5169 | } | |
5170 | ||
a2fbb9ea ET |
5171 | static void bnx2x_sp_task(struct work_struct *work) |
5172 | { | |
1cf167f2 | 5173 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea | 5174 | |
fd1fc79d | 5175 | DP(BNX2X_MSG_SP, "sp task invoked\n"); |
a2fbb9ea | 5176 | |
fd1fc79d AE |
5177 | /* make sure the atomic interupt_occurred has been written */ |
5178 | smp_rmb(); | |
5179 | if (atomic_read(&bp->interrupt_occurred)) { | |
a2fbb9ea | 5180 | |
fd1fc79d AE |
5181 | /* what work needs to be performed? */ |
5182 | u16 status = bnx2x_update_dsb_idx(bp); | |
cdaa7cb8 | 5183 | |
fd1fc79d AE |
5184 | DP(BNX2X_MSG_SP, "status %x\n", status); |
5185 | DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); | |
5186 | atomic_set(&bp->interrupt_occurred, 0); | |
5187 | ||
5188 | /* HW attentions */ | |
5189 | if (status & BNX2X_DEF_SB_ATT_IDX) { | |
5190 | bnx2x_attn_int(bp); | |
5191 | status &= ~BNX2X_DEF_SB_ATT_IDX; | |
5192 | } | |
5193 | ||
5194 | /* SP events: STAT_QUERY and others */ | |
5195 | if (status & BNX2X_DEF_SB_IDX) { | |
5196 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 5197 | |
55c11941 | 5198 | if (FCOE_INIT(bp) && |
fd1fc79d AE |
5199 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
5200 | /* Prevent local bottom-halves from running as | |
5201 | * we are going to change the local NAPI list. | |
5202 | */ | |
5203 | local_bh_disable(); | |
5204 | napi_schedule(&bnx2x_fcoe(bp, napi)); | |
5205 | local_bh_enable(); | |
5206 | } | |
5207 | ||
5208 | /* Handle EQ completions */ | |
5209 | bnx2x_eq_int(bp); | |
5210 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
5211 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
5212 | ||
5213 | status &= ~BNX2X_DEF_SB_IDX; | |
019dbb4c | 5214 | } |
55c11941 | 5215 | |
fd1fc79d AE |
5216 | /* if status is non zero then perhaps something went wrong */ |
5217 | if (unlikely(status)) | |
5218 | DP(BNX2X_MSG_SP, | |
5219 | "got an unknown interrupt! (status 0x%x)\n", status); | |
523224a3 | 5220 | |
fd1fc79d AE |
5221 | /* ack status block only if something was actually handled */ |
5222 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, | |
5223 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
523224a3 | 5224 | |
cdaa7cb8 VZ |
5225 | } |
5226 | ||
fd1fc79d AE |
5227 | /* must be called after the EQ processing (since eq leads to sriov |
5228 | * ramrod completion flows). | |
5229 | * This flow may have been scheduled by the arrival of a ramrod | |
5230 | * completion, or by the sriov code rescheduling itself. | |
5231 | */ | |
5232 | bnx2x_iov_sp_task(bp); | |
a3348722 BW |
5233 | |
5234 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ | |
5235 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
5236 | &bp->sp_state)) { | |
5237 | bnx2x_link_report(bp); | |
5238 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5239 | } | |
a2fbb9ea ET |
5240 | } |
5241 | ||
9f6c9258 | 5242 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
5243 | { |
5244 | struct net_device *dev = dev_instance; | |
5245 | struct bnx2x *bp = netdev_priv(dev); | |
5246 | ||
523224a3 DK |
5247 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
5248 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
5249 | |
5250 | #ifdef BNX2X_STOP_ON_ERROR | |
5251 | if (unlikely(bp->panic)) | |
5252 | return IRQ_HANDLED; | |
5253 | #endif | |
5254 | ||
55c11941 | 5255 | if (CNIC_LOADED(bp)) { |
993ac7b5 MC |
5256 | struct cnic_ops *c_ops; |
5257 | ||
5258 | rcu_read_lock(); | |
5259 | c_ops = rcu_dereference(bp->cnic_ops); | |
5260 | if (c_ops) | |
5261 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
5262 | rcu_read_unlock(); | |
5263 | } | |
55c11941 | 5264 | |
fd1fc79d AE |
5265 | /* schedule sp task to perform default status block work, ack |
5266 | * attentions and enable interrupts. | |
5267 | */ | |
5268 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
5269 | |
5270 | return IRQ_HANDLED; | |
5271 | } | |
5272 | ||
5273 | /* end of slow path */ | |
5274 | ||
619c5cb6 VZ |
5275 | |
5276 | void bnx2x_drv_pulse(struct bnx2x *bp) | |
5277 | { | |
5278 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5279 | bp->fw_drv_pulse_wr_seq); | |
5280 | } | |
5281 | ||
a2fbb9ea ET |
5282 | static void bnx2x_timer(unsigned long data) |
5283 | { | |
5284 | struct bnx2x *bp = (struct bnx2x *) data; | |
5285 | ||
5286 | if (!netif_running(bp->dev)) | |
5287 | return; | |
5288 | ||
67c431a5 AE |
5289 | if (IS_PF(bp) && |
5290 | !BP_NOMCP(bp)) { | |
f2e0899f | 5291 | int mb_idx = BP_FW_MB_IDX(bp); |
a2fbb9ea ET |
5292 | u32 drv_pulse; |
5293 | u32 mcp_pulse; | |
5294 | ||
5295 | ++bp->fw_drv_pulse_wr_seq; | |
5296 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
5297 | /* TBD - add SYSTEM_TIME */ | |
5298 | drv_pulse = bp->fw_drv_pulse_wr_seq; | |
619c5cb6 | 5299 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5300 | |
f2e0899f | 5301 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5302 | MCP_PULSE_SEQ_MASK); |
5303 | /* The delta between driver pulse and mcp response | |
5304 | * should be 1 (before mcp response) or 0 (after mcp response) | |
5305 | */ | |
5306 | if ((drv_pulse != mcp_pulse) && | |
5307 | (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { | |
5308 | /* someone lost a heartbeat... */ | |
5309 | BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
5310 | drv_pulse, mcp_pulse); | |
5311 | } | |
5312 | } | |
5313 | ||
f34d28ea | 5314 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5315 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5316 | |
abc5a021 AE |
5317 | /* sample pf vf bulletin board for new posts from pf */ |
5318 | if (IS_VF(bp)) | |
5319 | bnx2x_sample_bulletin(bp); | |
5320 | ||
a2fbb9ea ET |
5321 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5322 | } | |
5323 | ||
5324 | /* end of Statistics */ | |
5325 | ||
5326 | /* nic init */ | |
5327 | ||
5328 | /* | |
5329 | * nic init service functions | |
5330 | */ | |
5331 | ||
1191cb83 | 5332 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5333 | { |
523224a3 DK |
5334 | u32 i; |
5335 | if (!(len%4) && !(addr%4)) | |
5336 | for (i = 0; i < len; i += 4) | |
5337 | REG_WR(bp, addr + i, fill); | |
5338 | else | |
5339 | for (i = 0; i < len; i++) | |
5340 | REG_WR8(bp, addr + i, fill); | |
34f80b04 | 5341 | |
34f80b04 EG |
5342 | } |
5343 | ||
523224a3 | 5344 | /* helper: writes FP SP data to FW - data_size in dwords */ |
1191cb83 ED |
5345 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
5346 | int fw_sb_id, | |
5347 | u32 *sb_data_p, | |
5348 | u32 data_size) | |
34f80b04 | 5349 | { |
a2fbb9ea | 5350 | int index; |
523224a3 DK |
5351 | for (index = 0; index < data_size; index++) |
5352 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5353 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5354 | sizeof(u32)*index, | |
5355 | *(sb_data_p + index)); | |
5356 | } | |
a2fbb9ea | 5357 | |
1191cb83 | 5358 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
523224a3 DK |
5359 | { |
5360 | u32 *sb_data_p; | |
5361 | u32 data_size = 0; | |
f2e0899f | 5362 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5363 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5364 | |
523224a3 | 5365 | /* disable the function first */ |
619c5cb6 | 5366 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5367 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5368 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5369 | sb_data_e2.common.p_func.vf_valid = false; |
5370 | sb_data_p = (u32 *)&sb_data_e2; | |
5371 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5372 | } else { | |
5373 | memset(&sb_data_e1x, 0, | |
5374 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5375 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5376 | sb_data_e1x.common.p_func.vf_valid = false; |
5377 | sb_data_p = (u32 *)&sb_data_e1x; | |
5378 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5379 | } | |
523224a3 | 5380 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5381 | |
523224a3 DK |
5382 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5383 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5384 | CSTORM_STATUS_BLOCK_SIZE); | |
5385 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5386 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5387 | CSTORM_SYNC_BLOCK_SIZE); | |
5388 | } | |
34f80b04 | 5389 | |
523224a3 | 5390 | /* helper: writes SP SB data to FW */ |
1191cb83 | 5391 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
523224a3 DK |
5392 | struct hc_sp_status_block_data *sp_sb_data) |
5393 | { | |
5394 | int func = BP_FUNC(bp); | |
5395 | int i; | |
5396 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5397 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5398 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5399 | i*sizeof(u32), | |
5400 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5401 | } |
5402 | ||
1191cb83 | 5403 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5404 | { |
5405 | int func = BP_FUNC(bp); | |
523224a3 DK |
5406 | struct hc_sp_status_block_data sp_sb_data; |
5407 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5408 | |
619c5cb6 | 5409 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5410 | sp_sb_data.p_func.vf_valid = false; |
5411 | ||
5412 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5413 | ||
5414 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5415 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5416 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5417 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5418 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5419 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
5420 | ||
5421 | } | |
5422 | ||
5423 | ||
1191cb83 | 5424 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
523224a3 DK |
5425 | int igu_sb_id, int igu_seg_id) |
5426 | { | |
5427 | hc_sm->igu_sb_id = igu_sb_id; | |
5428 | hc_sm->igu_seg_id = igu_seg_id; | |
5429 | hc_sm->timer_value = 0xFF; | |
5430 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5431 | } |
5432 | ||
150966ad AE |
5433 | |
5434 | /* allocates state machine ids. */ | |
1191cb83 | 5435 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
150966ad AE |
5436 | { |
5437 | /* zero out state machine indices */ | |
5438 | /* rx indices */ | |
5439 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5440 | ||
5441 | /* tx indices */ | |
5442 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5443 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5444 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5445 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5446 | ||
5447 | /* map indices */ | |
5448 | /* rx indices */ | |
5449 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5450 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5451 | ||
5452 | /* tx indices */ | |
5453 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5454 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5455 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5456 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5457 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5458 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5459 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5460 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5461 | } | |
5462 | ||
b93288d5 | 5463 | void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5464 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5465 | { |
523224a3 DK |
5466 | int igu_seg_id; |
5467 | ||
f2e0899f | 5468 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5469 | struct hc_status_block_data_e1x sb_data_e1x; |
5470 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5471 | int data_size; |
5472 | u32 *sb_data_p; | |
5473 | ||
f2e0899f DK |
5474 | if (CHIP_INT_MODE_IS_BC(bp)) |
5475 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5476 | else | |
5477 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5478 | |
5479 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5480 | ||
619c5cb6 | 5481 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5482 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5483 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5484 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5485 | sb_data_e2.common.p_func.vf_id = vfid; | |
5486 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5487 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5488 | sb_data_e2.common.same_igu_sb_1b = true; | |
5489 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5490 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5491 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5492 | sb_data_p = (u32 *)&sb_data_e2; |
5493 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5494 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5495 | } else { |
5496 | memset(&sb_data_e1x, 0, | |
5497 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5498 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5499 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5500 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5501 | sb_data_e1x.common.p_func.vf_valid = false; | |
5502 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
5503 | sb_data_e1x.common.same_igu_sb_1b = true; | |
5504 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
5505 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
5506 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
5507 | sb_data_p = (u32 *)&sb_data_e1x; |
5508 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 5509 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 5510 | } |
523224a3 DK |
5511 | |
5512 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
5513 | igu_sb_id, igu_seg_id); | |
5514 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
5515 | igu_sb_id, igu_seg_id); | |
5516 | ||
51c1a580 | 5517 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 DK |
5518 | |
5519 | /* write indecies to HW */ | |
5520 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); | |
5521 | } | |
5522 | ||
619c5cb6 | 5523 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
5524 | u16 tx_usec, u16 rx_usec) |
5525 | { | |
6383c0b3 | 5526 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 5527 | false, rx_usec); |
6383c0b3 AE |
5528 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
5529 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
5530 | tx_usec); | |
5531 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5532 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
5533 | tx_usec); | |
5534 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5535 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
5536 | tx_usec); | |
523224a3 | 5537 | } |
f2e0899f | 5538 | |
523224a3 DK |
5539 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
5540 | { | |
5541 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
5542 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
5543 | int igu_sp_sb_index; | |
5544 | int igu_seg_id; | |
34f80b04 EG |
5545 | int port = BP_PORT(bp); |
5546 | int func = BP_FUNC(bp); | |
f2eaeb58 | 5547 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 5548 | u64 section; |
523224a3 DK |
5549 | int index; |
5550 | struct hc_sp_status_block_data sp_sb_data; | |
5551 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
5552 | ||
f2e0899f DK |
5553 | if (CHIP_INT_MODE_IS_BC(bp)) { |
5554 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
5555 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
5556 | } else { | |
5557 | igu_sp_sb_index = bp->igu_dsb_id; | |
5558 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
5559 | } | |
a2fbb9ea ET |
5560 | |
5561 | /* ATTN */ | |
523224a3 | 5562 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 5563 | atten_status_block); |
523224a3 | 5564 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 5565 | |
49d66772 ET |
5566 | bp->attn_state = 0; |
5567 | ||
a2fbb9ea ET |
5568 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
5569 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
5570 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
5571 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 5572 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
5573 | int sindex; |
5574 | /* take care of sig[0]..sig[4] */ | |
5575 | for (sindex = 0; sindex < 4; sindex++) | |
5576 | bp->attn_group[index].sig[sindex] = | |
5577 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 5578 | |
619c5cb6 | 5579 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5580 | /* |
5581 | * enable5 is separate from the rest of the registers, | |
5582 | * and therefore the address skip is 4 | |
5583 | * and not 16 between the different groups | |
5584 | */ | |
5585 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 5586 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
5587 | else |
5588 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
5589 | } |
5590 | ||
f2e0899f DK |
5591 | if (bp->common.int_block == INT_BLOCK_HC) { |
5592 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
5593 | HC_REG_ATTN_MSG0_ADDR_L); | |
5594 | ||
5595 | REG_WR(bp, reg_offset, U64_LO(section)); | |
5596 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 5597 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5598 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
5599 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
5600 | } | |
a2fbb9ea | 5601 | |
523224a3 DK |
5602 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
5603 | sp_sb); | |
a2fbb9ea | 5604 | |
523224a3 | 5605 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 5606 | |
619c5cb6 | 5607 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
5608 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
5609 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
5610 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
5611 | sp_sb_data.igu_seg_id = igu_seg_id; | |
5612 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 5613 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 5614 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 5615 | |
523224a3 | 5616 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 5617 | |
523224a3 | 5618 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
5619 | } |
5620 | ||
9f6c9258 | 5621 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 5622 | { |
a2fbb9ea ET |
5623 | int i; |
5624 | ||
ec6ba945 | 5625 | for_each_eth_queue(bp, i) |
523224a3 | 5626 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 5627 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
5628 | } |
5629 | ||
a2fbb9ea ET |
5630 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
5631 | { | |
a2fbb9ea | 5632 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 5633 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 5634 | |
a2fbb9ea | 5635 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
5636 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
5637 | bp->spq_prod_bd = bp->spq; | |
5638 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
5639 | } |
5640 | ||
523224a3 | 5641 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
5642 | { |
5643 | int i; | |
523224a3 DK |
5644 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
5645 | union event_ring_elem *elem = | |
5646 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 5647 | |
523224a3 DK |
5648 | elem->next_page.addr.hi = |
5649 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
5650 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
5651 | elem->next_page.addr.lo = | |
5652 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
5653 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 5654 | } |
523224a3 DK |
5655 | bp->eq_cons = 0; |
5656 | bp->eq_prod = NUM_EQ_DESC; | |
5657 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
6e30dd4e VZ |
5658 | /* we want a warning message before it gets rought... */ |
5659 | atomic_set(&bp->eq_spq_left, | |
5660 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
5661 | } |
5662 | ||
619c5cb6 VZ |
5663 | |
5664 | /* called with netif_addr_lock_bh() */ | |
5665 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, | |
5666 | unsigned long rx_mode_flags, | |
5667 | unsigned long rx_accept_flags, | |
5668 | unsigned long tx_accept_flags, | |
5669 | unsigned long ramrod_flags) | |
ab532cf3 | 5670 | { |
619c5cb6 VZ |
5671 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
5672 | int rc; | |
5673 | ||
5674 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
5675 | ||
5676 | /* Prepare ramrod parameters */ | |
5677 | ramrod_param.cid = 0; | |
5678 | ramrod_param.cl_id = cl_id; | |
5679 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
5680 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 5681 | |
619c5cb6 VZ |
5682 | ramrod_param.pstate = &bp->sp_state; |
5683 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 5684 | |
619c5cb6 VZ |
5685 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
5686 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
5687 | ||
5688 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5689 | ||
5690 | ramrod_param.ramrod_flags = ramrod_flags; | |
5691 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
5692 | ||
5693 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
5694 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
5695 | ||
5696 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
5697 | if (rc < 0) { | |
5698 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
5699 | return; | |
5700 | } | |
a2fbb9ea ET |
5701 | } |
5702 | ||
619c5cb6 VZ |
5703 | /* called with netif_addr_lock_bh() */ |
5704 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
471de716 | 5705 | { |
619c5cb6 VZ |
5706 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; |
5707 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
471de716 | 5708 | |
619c5cb6 VZ |
5709 | if (!NO_FCOE(bp)) |
5710 | ||
5711 | /* Configure rx_mode of FCoE Queue */ | |
5712 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
619c5cb6 VZ |
5713 | |
5714 | switch (bp->rx_mode) { | |
5715 | case BNX2X_RX_MODE_NONE: | |
5716 | /* | |
5717 | * 'drop all' supersedes any accept flags that may have been | |
5718 | * passed to the function. | |
5719 | */ | |
5720 | break; | |
5721 | case BNX2X_RX_MODE_NORMAL: | |
5722 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5723 | __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags); | |
5724 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5725 | ||
5726 | /* internal switching mode */ | |
5727 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5728 | __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags); | |
5729 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5730 | ||
5731 | break; | |
5732 | case BNX2X_RX_MODE_ALLMULTI: | |
5733 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5734 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5735 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5736 | ||
5737 | /* internal switching mode */ | |
5738 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5739 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5740 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5741 | ||
5742 | break; | |
5743 | case BNX2X_RX_MODE_PROMISC: | |
5744 | /* According to deffinition of SI mode, iface in promisc mode | |
5745 | * should receive matched and unmatched (in resolution of port) | |
5746 | * unicast packets. | |
5747 | */ | |
5748 | __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags); | |
5749 | __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags); | |
5750 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags); | |
5751 | __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags); | |
5752 | ||
5753 | /* internal switching mode */ | |
5754 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags); | |
5755 | __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags); | |
5756 | ||
5757 | if (IS_MF_SI(bp)) | |
5758 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags); | |
5759 | else | |
5760 | __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags); | |
5761 | ||
5762 | break; | |
5763 | default: | |
5764 | BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode); | |
5765 | return; | |
5766 | } | |
de832a55 | 5767 | |
619c5cb6 VZ |
5768 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
5769 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags); | |
5770 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags); | |
34f80b04 EG |
5771 | } |
5772 | ||
619c5cb6 VZ |
5773 | __set_bit(RAMROD_RX, &ramrod_flags); |
5774 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5775 | ||
5776 | bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags, | |
5777 | tx_accept_flags, ramrod_flags); | |
5778 | } | |
5779 | ||
5780 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5781 | { | |
5782 | int i; | |
5783 | ||
0793f83f DK |
5784 | if (IS_MF_SI(bp)) |
5785 | /* | |
5786 | * In switch independent mode, the TSTORM needs to accept | |
5787 | * packets that failed classification, since approximate match | |
5788 | * mac addresses aren't written to NIG LLH | |
5789 | */ | |
5790 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5791 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5792 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5793 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5794 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5795 | |
523224a3 DK |
5796 | /* Zero this manually as its initialization is |
5797 | currently missing in the initTool */ | |
5798 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5799 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5800 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5801 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5802 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5803 | CHIP_INT_MODE_IS_BC(bp) ? | |
5804 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5805 | } | |
523224a3 | 5806 | } |
8a1c38d1 | 5807 | |
471de716 EG |
5808 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5809 | { | |
5810 | switch (load_code) { | |
5811 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5812 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5813 | bnx2x_init_internal_common(bp); |
5814 | /* no break */ | |
5815 | ||
5816 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5817 | /* nothing to do */ |
471de716 EG |
5818 | /* no break */ |
5819 | ||
5820 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5821 | /* internal memory per function is |
5822 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5823 | break; |
5824 | ||
5825 | default: | |
5826 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
5827 | break; | |
5828 | } | |
5829 | } | |
5830 | ||
619c5cb6 | 5831 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 5832 | { |
55c11941 | 5833 | return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 | 5834 | } |
523224a3 | 5835 | |
619c5cb6 VZ |
5836 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
5837 | { | |
55c11941 | 5838 | return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 VZ |
5839 | } |
5840 | ||
1191cb83 | 5841 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
619c5cb6 VZ |
5842 | { |
5843 | if (CHIP_IS_E1x(fp->bp)) | |
5844 | return BP_L_ID(fp->bp) + fp->index; | |
5845 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
5846 | return bnx2x_fp_igu_sb_id(fp); | |
5847 | } | |
5848 | ||
6383c0b3 | 5849 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
5850 | { |
5851 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 5852 | u8 cos; |
619c5cb6 | 5853 | unsigned long q_type = 0; |
6383c0b3 | 5854 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 5855 | fp->rx_queue = fp_idx; |
b3b83c3f | 5856 | fp->cid = fp_idx; |
619c5cb6 VZ |
5857 | fp->cl_id = bnx2x_fp_cl_id(fp); |
5858 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
5859 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 5860 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
5861 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
5862 | ||
523224a3 | 5863 | /* init shortcut */ |
619c5cb6 | 5864 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 5865 | |
523224a3 DK |
5866 | /* Setup SB indicies */ |
5867 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; | |
523224a3 | 5868 | |
619c5cb6 VZ |
5869 | /* Configure Queue State object */ |
5870 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
5871 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
5872 | |
5873 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
5874 | ||
5875 | /* init tx data */ | |
5876 | for_each_cos_in_tx_queue(fp, cos) { | |
65565884 MS |
5877 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
5878 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), | |
5879 | FP_COS_TO_TXQ(fp, cos, bp), | |
5880 | BNX2X_TX_SB_INDEX_BASE + cos, fp); | |
5881 | cids[cos] = fp->txdata_ptr[cos]->cid; | |
6383c0b3 AE |
5882 | } |
5883 | ||
ad5afc89 AE |
5884 | /* nothing more for vf to do here */ |
5885 | if (IS_VF(bp)) | |
5886 | return; | |
5887 | ||
5888 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
5889 | fp->fw_sb_id, fp->igu_sb_id); | |
5890 | bnx2x_update_fpsb_idx(fp); | |
15192a8c BW |
5891 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
5892 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 5893 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 VZ |
5894 | |
5895 | /** | |
5896 | * Configure classification DBs: Always enable Tx switching | |
5897 | */ | |
5898 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
5899 | ||
ad5afc89 AE |
5900 | DP(NETIF_MSG_IFUP, |
5901 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
5902 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
5903 | fp->igu_sb_id); | |
523224a3 DK |
5904 | } |
5905 | ||
1191cb83 ED |
5906 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
5907 | { | |
5908 | int i; | |
5909 | ||
5910 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
5911 | struct eth_tx_next_bd *tx_next_bd = | |
5912 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
5913 | ||
5914 | tx_next_bd->addr_hi = | |
5915 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + | |
5916 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
5917 | tx_next_bd->addr_lo = | |
5918 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + | |
5919 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
5920 | } | |
5921 | ||
5922 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); | |
5923 | txdata->tx_db.data.zero_fill1 = 0; | |
5924 | txdata->tx_db.data.prod = 0; | |
5925 | ||
5926 | txdata->tx_pkt_prod = 0; | |
5927 | txdata->tx_pkt_cons = 0; | |
5928 | txdata->tx_bd_prod = 0; | |
5929 | txdata->tx_bd_cons = 0; | |
5930 | txdata->tx_pkt = 0; | |
5931 | } | |
5932 | ||
55c11941 MS |
5933 | static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) |
5934 | { | |
5935 | int i; | |
5936 | ||
5937 | for_each_tx_queue_cnic(bp, i) | |
5938 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); | |
5939 | } | |
1191cb83 ED |
5940 | static void bnx2x_init_tx_rings(struct bnx2x *bp) |
5941 | { | |
5942 | int i; | |
5943 | u8 cos; | |
5944 | ||
55c11941 | 5945 | for_each_eth_queue(bp, i) |
1191cb83 | 5946 | for_each_cos_in_tx_queue(&bp->fp[i], cos) |
65565884 | 5947 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
1191cb83 ED |
5948 | } |
5949 | ||
55c11941 | 5950 | void bnx2x_nic_init_cnic(struct bnx2x *bp) |
a2fbb9ea | 5951 | { |
ec6ba945 VZ |
5952 | if (!NO_FCOE(bp)) |
5953 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
5954 | |
5955 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
5956 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 5957 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 5958 | |
55c11941 MS |
5959 | /* ensure status block indices were read */ |
5960 | rmb(); | |
5961 | bnx2x_init_rx_rings_cnic(bp); | |
5962 | bnx2x_init_tx_rings_cnic(bp); | |
5963 | ||
5964 | /* flush all */ | |
5965 | mb(); | |
5966 | mmiowb(); | |
5967 | } | |
a2fbb9ea | 5968 | |
55c11941 MS |
5969 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) |
5970 | { | |
5971 | int i; | |
5972 | ||
5973 | for_each_eth_queue(bp, i) | |
5974 | bnx2x_init_eth_fp(bp, i); | |
ad5afc89 AE |
5975 | |
5976 | /* ensure status block indices were read */ | |
5977 | rmb(); | |
5978 | bnx2x_init_rx_rings(bp); | |
5979 | bnx2x_init_tx_rings(bp); | |
5980 | ||
5981 | if (IS_VF(bp)) | |
5982 | return; | |
5983 | ||
020c7e3f YR |
5984 | /* Initialize MOD_ABS interrupts */ |
5985 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
5986 | bp->common.shmem_base, bp->common.shmem2_base, | |
5987 | BP_PORT(bp)); | |
16119785 | 5988 | |
523224a3 | 5989 | bnx2x_init_def_sb(bp); |
5c862848 | 5990 | bnx2x_update_dsb_idx(bp); |
a2fbb9ea | 5991 | bnx2x_init_sp_ring(bp); |
523224a3 | 5992 | bnx2x_init_eq_ring(bp); |
471de716 | 5993 | bnx2x_init_internal(bp, load_code); |
523224a3 | 5994 | bnx2x_pf_init(bp); |
0ef00459 EG |
5995 | bnx2x_stats_init(bp); |
5996 | ||
0ef00459 EG |
5997 | /* flush all before enabling interrupts */ |
5998 | mb(); | |
5999 | mmiowb(); | |
6000 | ||
615f8fd9 | 6001 | bnx2x_int_enable(bp); |
eb8da205 EG |
6002 | |
6003 | /* Check for SPIO5 */ | |
6004 | bnx2x_attn_int_deasserted0(bp, | |
6005 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
6006 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
6007 | } |
6008 | ||
6009 | /* end of nic init */ | |
6010 | ||
6011 | /* | |
6012 | * gzip service functions | |
6013 | */ | |
6014 | ||
6015 | static int bnx2x_gunzip_init(struct bnx2x *bp) | |
6016 | { | |
1a983142 FT |
6017 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
6018 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
6019 | if (bp->gunzip_buf == NULL) |
6020 | goto gunzip_nomem1; | |
6021 | ||
6022 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
6023 | if (bp->strm == NULL) | |
6024 | goto gunzip_nomem2; | |
6025 | ||
7ab24bfd | 6026 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
6027 | if (bp->strm->workspace == NULL) |
6028 | goto gunzip_nomem3; | |
6029 | ||
6030 | return 0; | |
6031 | ||
6032 | gunzip_nomem3: | |
6033 | kfree(bp->strm); | |
6034 | bp->strm = NULL; | |
6035 | ||
6036 | gunzip_nomem2: | |
1a983142 FT |
6037 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6038 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6039 | bp->gunzip_buf = NULL; |
6040 | ||
6041 | gunzip_nomem1: | |
51c1a580 | 6042 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
6043 | return -ENOMEM; |
6044 | } | |
6045 | ||
6046 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
6047 | { | |
b3b83c3f | 6048 | if (bp->strm) { |
7ab24bfd | 6049 | vfree(bp->strm->workspace); |
b3b83c3f DK |
6050 | kfree(bp->strm); |
6051 | bp->strm = NULL; | |
6052 | } | |
a2fbb9ea ET |
6053 | |
6054 | if (bp->gunzip_buf) { | |
1a983142 FT |
6055 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6056 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6057 | bp->gunzip_buf = NULL; |
6058 | } | |
6059 | } | |
6060 | ||
94a78b79 | 6061 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
6062 | { |
6063 | int n, rc; | |
6064 | ||
6065 | /* check gzip header */ | |
94a78b79 VZ |
6066 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
6067 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 6068 | return -EINVAL; |
94a78b79 | 6069 | } |
a2fbb9ea ET |
6070 | |
6071 | n = 10; | |
6072 | ||
34f80b04 | 6073 | #define FNAME 0x8 |
a2fbb9ea ET |
6074 | |
6075 | if (zbuf[3] & FNAME) | |
6076 | while ((zbuf[n++] != 0) && (n < len)); | |
6077 | ||
94a78b79 | 6078 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
6079 | bp->strm->avail_in = len - n; |
6080 | bp->strm->next_out = bp->gunzip_buf; | |
6081 | bp->strm->avail_out = FW_BUF_SIZE; | |
6082 | ||
6083 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
6084 | if (rc != Z_OK) | |
6085 | return rc; | |
6086 | ||
6087 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
6088 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
6089 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
6090 | bp->strm->msg); | |
a2fbb9ea ET |
6091 | |
6092 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
6093 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
6094 | netdev_err(bp->dev, |
6095 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 6096 | bp->gunzip_outlen); |
a2fbb9ea ET |
6097 | bp->gunzip_outlen >>= 2; |
6098 | ||
6099 | zlib_inflateEnd(bp->strm); | |
6100 | ||
6101 | if (rc == Z_STREAM_END) | |
6102 | return 0; | |
6103 | ||
6104 | return rc; | |
6105 | } | |
6106 | ||
6107 | /* nic load/unload */ | |
6108 | ||
6109 | /* | |
34f80b04 | 6110 | * General service functions |
a2fbb9ea ET |
6111 | */ |
6112 | ||
6113 | /* send a NIG loopback debug packet */ | |
6114 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
6115 | { | |
a2fbb9ea | 6116 | u32 wb_write[3]; |
a2fbb9ea ET |
6117 | |
6118 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
6119 | wb_write[0] = 0x55555555; |
6120 | wb_write[1] = 0x55555555; | |
34f80b04 | 6121 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 6122 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6123 | |
6124 | /* NON-IP protocol */ | |
a2fbb9ea ET |
6125 | wb_write[0] = 0x09000000; |
6126 | wb_write[1] = 0x55555555; | |
34f80b04 | 6127 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 6128 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6129 | } |
6130 | ||
6131 | /* some of the internal memories | |
6132 | * are not directly readable from the driver | |
6133 | * to test them we send debug packets | |
6134 | */ | |
6135 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
6136 | { | |
6137 | int factor; | |
6138 | int count, i; | |
6139 | u32 val = 0; | |
6140 | ||
ad8d3948 | 6141 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 6142 | factor = 120; |
ad8d3948 EG |
6143 | else if (CHIP_REV_IS_EMUL(bp)) |
6144 | factor = 200; | |
6145 | else | |
a2fbb9ea | 6146 | factor = 1; |
a2fbb9ea | 6147 | |
a2fbb9ea ET |
6148 | /* Disable inputs of parser neighbor blocks */ |
6149 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6150 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6151 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6152 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6153 | |
6154 | /* Write 0 to parser credits for CFC search request */ | |
6155 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6156 | ||
6157 | /* send Ethernet packet */ | |
6158 | bnx2x_lb_pckt(bp); | |
6159 | ||
6160 | /* TODO do i reset NIG statistic? */ | |
6161 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6162 | count = 1000 * factor; | |
6163 | while (count) { | |
34f80b04 | 6164 | |
a2fbb9ea ET |
6165 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6166 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6167 | if (val == 0x10) |
6168 | break; | |
6169 | ||
6170 | msleep(10); | |
6171 | count--; | |
6172 | } | |
6173 | if (val != 0x10) { | |
6174 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6175 | return -1; | |
6176 | } | |
6177 | ||
6178 | /* Wait until PRS register shows 1 packet */ | |
6179 | count = 1000 * factor; | |
6180 | while (count) { | |
6181 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
6182 | if (val == 1) |
6183 | break; | |
6184 | ||
6185 | msleep(10); | |
6186 | count--; | |
6187 | } | |
6188 | if (val != 0x1) { | |
6189 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6190 | return -2; | |
6191 | } | |
6192 | ||
6193 | /* Reset and init BRB, PRS */ | |
34f80b04 | 6194 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 6195 | msleep(50); |
34f80b04 | 6196 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 6197 | msleep(50); |
619c5cb6 VZ |
6198 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6199 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
6200 | |
6201 | DP(NETIF_MSG_HW, "part2\n"); | |
6202 | ||
6203 | /* Disable inputs of parser neighbor blocks */ | |
6204 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6205 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6206 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6207 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6208 | |
6209 | /* Write 0 to parser credits for CFC search request */ | |
6210 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6211 | ||
6212 | /* send 10 Ethernet packets */ | |
6213 | for (i = 0; i < 10; i++) | |
6214 | bnx2x_lb_pckt(bp); | |
6215 | ||
6216 | /* Wait until NIG register shows 10 + 1 | |
6217 | packets of size 11*0x10 = 0xb0 */ | |
6218 | count = 1000 * factor; | |
6219 | while (count) { | |
34f80b04 | 6220 | |
a2fbb9ea ET |
6221 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6222 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6223 | if (val == 0xb0) |
6224 | break; | |
6225 | ||
6226 | msleep(10); | |
6227 | count--; | |
6228 | } | |
6229 | if (val != 0xb0) { | |
6230 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6231 | return -3; | |
6232 | } | |
6233 | ||
6234 | /* Wait until PRS register shows 2 packets */ | |
6235 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6236 | if (val != 2) | |
6237 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6238 | ||
6239 | /* Write 1 to parser credits for CFC search request */ | |
6240 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
6241 | ||
6242 | /* Wait until PRS register shows 3 packets */ | |
6243 | msleep(10 * factor); | |
6244 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6245 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6246 | if (val != 3) | |
6247 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6248 | ||
6249 | /* clear NIG EOP FIFO */ | |
6250 | for (i = 0; i < 11; i++) | |
6251 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
6252 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
6253 | if (val != 1) { | |
6254 | BNX2X_ERR("clear of NIG failed\n"); | |
6255 | return -4; | |
6256 | } | |
6257 | ||
6258 | /* Reset and init BRB, PRS, NIG */ | |
6259 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
6260 | msleep(50); | |
6261 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
6262 | msleep(50); | |
619c5cb6 VZ |
6263 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6264 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
55c11941 MS |
6265 | if (!CNIC_SUPPORT(bp)) |
6266 | /* set NIC mode */ | |
6267 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
a2fbb9ea ET |
6268 | |
6269 | /* Enable inputs of parser neighbor blocks */ | |
6270 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
6271 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
6272 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 6273 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
6274 | |
6275 | DP(NETIF_MSG_HW, "done\n"); | |
6276 | ||
6277 | return 0; /* OK */ | |
6278 | } | |
6279 | ||
4a33bc03 | 6280 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea | 6281 | { |
b343d002 YM |
6282 | u32 val; |
6283 | ||
a2fbb9ea | 6284 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); |
619c5cb6 | 6285 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6286 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
6287 | else | |
6288 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
6289 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
6290 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
6291 | /* |
6292 | * mask read length error interrupts in brb for parser | |
6293 | * (parsing unit and 'checksum and crc' unit) | |
6294 | * these errors are legal (PU reads fixed length and CAC can cause | |
6295 | * read length error on truncated packets) | |
6296 | */ | |
6297 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
6298 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
6299 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
6300 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
6301 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
6302 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
6303 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
6304 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6305 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
6306 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
6307 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
6308 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
6309 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6310 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
6311 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
6312 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
6313 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
6314 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
6315 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 6316 | |
b343d002 YM |
6317 | val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
6318 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | | |
6319 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; | |
6320 | if (!CHIP_IS_E1x(bp)) | |
6321 | val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | | |
6322 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; | |
6323 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); | |
6324 | ||
a2fbb9ea ET |
6325 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
6326 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
6327 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 6328 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6329 | |
6330 | if (!CHIP_IS_E1x(bp)) | |
6331 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6332 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6333 | ||
a2fbb9ea ET |
6334 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6335 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6336 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6337 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6338 | } |
6339 | ||
81f75bbf EG |
6340 | static void bnx2x_reset_common(struct bnx2x *bp) |
6341 | { | |
619c5cb6 VZ |
6342 | u32 val = 0x1400; |
6343 | ||
81f75bbf EG |
6344 | /* reset_common */ |
6345 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6346 | 0xd3ffff7f); | |
619c5cb6 VZ |
6347 | |
6348 | if (CHIP_IS_E3(bp)) { | |
6349 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6350 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6351 | } | |
6352 | ||
6353 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6354 | } | |
6355 | ||
6356 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6357 | { | |
6358 | bp->dmae_ready = 0; | |
6359 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6360 | } |
6361 | ||
573f2035 EG |
6362 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6363 | { | |
6364 | u16 devctl; | |
6365 | int r_order, w_order; | |
6366 | ||
2a80eebc | 6367 | pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6368 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6369 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6370 | if (bp->mrrs == -1) | |
6371 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6372 | else { | |
6373 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6374 | r_order = bp->mrrs; | |
6375 | } | |
6376 | ||
6377 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6378 | } | |
fd4ef40d EG |
6379 | |
6380 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6381 | { | |
2145a920 | 6382 | int is_required; |
fd4ef40d | 6383 | u32 val; |
2145a920 | 6384 | int port; |
fd4ef40d | 6385 | |
2145a920 VZ |
6386 | if (BP_NOMCP(bp)) |
6387 | return; | |
6388 | ||
6389 | is_required = 0; | |
fd4ef40d EG |
6390 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6391 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6392 | ||
6393 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6394 | is_required = 1; | |
6395 | ||
6396 | /* | |
6397 | * The fan failure mechanism is usually related to the PHY type since | |
6398 | * the power consumption of the board is affected by the PHY. Currently, | |
6399 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6400 | */ | |
6401 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6402 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6403 | is_required |= |
d90d96ba YR |
6404 | bnx2x_fan_failure_det_req( |
6405 | bp, | |
6406 | bp->common.shmem_base, | |
a22f0788 | 6407 | bp->common.shmem2_base, |
d90d96ba | 6408 | port); |
fd4ef40d EG |
6409 | } |
6410 | ||
6411 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6412 | ||
6413 | if (is_required == 0) | |
6414 | return; | |
6415 | ||
6416 | /* Fan failure is indicated by SPIO 5 */ | |
d6d99a3f | 6417 | bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); |
fd4ef40d EG |
6418 | |
6419 | /* set to active low mode */ | |
6420 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
d6d99a3f | 6421 | val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6422 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6423 | ||
6424 | /* enable interrupt to signal the IGU */ | |
6425 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 6426 | val |= MISC_SPIO_SPIO5; |
fd4ef40d EG |
6427 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); |
6428 | } | |
6429 | ||
c9ee9206 | 6430 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6431 | { |
6432 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6433 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6434 | ||
6435 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6436 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6437 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6438 | } | |
6439 | ||
1191cb83 | 6440 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
619c5cb6 VZ |
6441 | { |
6442 | u32 shmem_base[2], shmem2_base[2]; | |
b884d95b YR |
6443 | /* Avoid common init in case MFW supports LFA */ |
6444 | if (SHMEM2_RD(bp, size) > | |
6445 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
6446 | return; | |
619c5cb6 VZ |
6447 | shmem_base[0] = bp->common.shmem_base; |
6448 | shmem2_base[0] = bp->common.shmem2_base; | |
6449 | if (!CHIP_IS_E1x(bp)) { | |
6450 | shmem_base[1] = | |
6451 | SHMEM2_RD(bp, other_shmem_base_addr); | |
6452 | shmem2_base[1] = | |
6453 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
6454 | } | |
6455 | bnx2x_acquire_phy_lock(bp); | |
6456 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
6457 | bp->common.chip_id); | |
6458 | bnx2x_release_phy_lock(bp); | |
6459 | } | |
6460 | ||
6461 | /** | |
6462 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
6463 | * | |
6464 | * @bp: driver handle | |
6465 | */ | |
6466 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 6467 | { |
619c5cb6 | 6468 | u32 val; |
a2fbb9ea | 6469 | |
51c1a580 | 6470 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 6471 | |
2031bd3a DK |
6472 | /* |
6473 | * take the UNDI lock to protect undi_unload flow from accessing | |
6474 | * registers while we're resetting the chip | |
6475 | */ | |
7a06a122 | 6476 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6477 | |
81f75bbf | 6478 | bnx2x_reset_common(bp); |
34f80b04 | 6479 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 6480 | |
619c5cb6 VZ |
6481 | val = 0xfffc; |
6482 | if (CHIP_IS_E3(bp)) { | |
6483 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6484 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6485 | } | |
6486 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
6487 | ||
7a06a122 | 6488 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6489 | |
619c5cb6 | 6490 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 6491 | |
619c5cb6 VZ |
6492 | if (!CHIP_IS_E1x(bp)) { |
6493 | u8 abs_func_id; | |
f2e0899f DK |
6494 | |
6495 | /** | |
6496 | * 4-port mode or 2-port mode we need to turn of master-enable | |
6497 | * for everyone, after that, turn it back on for self. | |
6498 | * so, we disregard multi-function or not, and always disable | |
6499 | * for all functions on the given path, this means 0,2,4,6 for | |
6500 | * path 0 and 1,3,5,7 for path 1 | |
6501 | */ | |
619c5cb6 VZ |
6502 | for (abs_func_id = BP_PATH(bp); |
6503 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
6504 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
6505 | REG_WR(bp, |
6506 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
6507 | 1); | |
6508 | continue; | |
6509 | } | |
6510 | ||
619c5cb6 | 6511 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
6512 | /* clear pf enable */ |
6513 | bnx2x_pf_disable(bp); | |
6514 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6515 | } | |
6516 | } | |
a2fbb9ea | 6517 | |
619c5cb6 | 6518 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
6519 | if (CHIP_IS_E1(bp)) { |
6520 | /* enable HW interrupt from PXP on USDM overflow | |
6521 | bit 16 on INT_MASK_0 */ | |
6522 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
6523 | } | |
a2fbb9ea | 6524 | |
619c5cb6 | 6525 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 6526 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
6527 | |
6528 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
6529 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
6530 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
6531 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
6532 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
6533 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
6534 | /* make sure this value is 0 */ |
6535 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
6536 | |
6537 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
6538 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
6539 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
6540 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
6541 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
6542 | #endif |
6543 | ||
523224a3 DK |
6544 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
6545 | ||
34f80b04 EG |
6546 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
6547 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 6548 | |
34f80b04 EG |
6549 | /* let the HW do it's magic ... */ |
6550 | msleep(100); | |
6551 | /* finish PXP init */ | |
6552 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
6553 | if (val != 1) { | |
6554 | BNX2X_ERR("PXP2 CFG failed\n"); | |
6555 | return -EBUSY; | |
6556 | } | |
6557 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
6558 | if (val != 1) { | |
6559 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
6560 | return -EBUSY; | |
6561 | } | |
a2fbb9ea | 6562 | |
f2e0899f DK |
6563 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
6564 | * have entries with value "0" and valid bit on. | |
6565 | * This needs to be done by the first PF that is loaded in a path | |
6566 | * (i.e. common phase) | |
6567 | */ | |
619c5cb6 VZ |
6568 | if (!CHIP_IS_E1x(bp)) { |
6569 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
6570 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
6571 | * This occurs when a different function (func2,3) is being marked | |
6572 | * as "scan-off". Real-life scenario for example: if a driver is being | |
6573 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
6574 | * the ilt, translate to a logical address and send a request to read/write. | |
6575 | * Since the ilt for the function that is down is not valid, this will cause | |
6576 | * a translation error which is unrecoverable. | |
6577 | * The Workaround is intended to make sure that when this happens nothing fatal | |
6578 | * will occur. The workaround: | |
6579 | * 1. First PF driver which loads on a path will: | |
6580 | * a. After taking the chip out of reset, by using pretend, | |
6581 | * it will write "0" to the following registers of | |
6582 | * the other vnics. | |
6583 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6584 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
6585 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
6586 | * And for itself it will write '1' to | |
6587 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
6588 | * dmae-operations (writing to pram for example.) | |
6589 | * note: can be done for only function 6,7 but cleaner this | |
6590 | * way. | |
6591 | * b. Write zero+valid to the entire ILT. | |
6592 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
6593 | * VNIC3 (of that port). The range allocated will be the | |
6594 | * entire ILT. This is needed to prevent ILT range error. | |
6595 | * 2. Any PF driver load flow: | |
6596 | * a. ILT update with the physical addresses of the allocated | |
6597 | * logical pages. | |
6598 | * b. Wait 20msec. - note that this timeout is needed to make | |
6599 | * sure there are no requests in one of the PXP internal | |
6600 | * queues with "old" ILT addresses. | |
6601 | * c. PF enable in the PGLC. | |
6602 | * d. Clear the was_error of the PF in the PGLC. (could have | |
6603 | * occured while driver was down) | |
6604 | * e. PF enable in the CFC (WEAK + STRONG) | |
6605 | * f. Timers scan enable | |
6606 | * 3. PF driver unload flow: | |
6607 | * a. Clear the Timers scan_en. | |
6608 | * b. Polling for scan_on=0 for that PF. | |
6609 | * c. Clear the PF enable bit in the PXP. | |
6610 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
6611 | * e. Write zero+valid to all ILT entries (The valid bit must | |
6612 | * stay set) | |
6613 | * f. If this is VNIC 3 of a port then also init | |
6614 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
6615 | * to the last enrty in the ILT. | |
6616 | * | |
6617 | * Notes: | |
6618 | * Currently the PF error in the PGLC is non recoverable. | |
6619 | * In the future the there will be a recovery routine for this error. | |
6620 | * Currently attention is masked. | |
6621 | * Having an MCP lock on the load/unload process does not guarantee that | |
6622 | * there is no Timer disable during Func6/7 enable. This is because the | |
6623 | * Timers scan is currently being cleared by the MCP on FLR. | |
6624 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
6625 | * there is error before clearing it. But the flow above is simpler and | |
6626 | * more general. | |
6627 | * All ILT entries are written by zero+valid and not just PF6/7 | |
6628 | * ILT entries since in the future the ILT entries allocation for | |
6629 | * PF-s might be dynamic. | |
6630 | */ | |
f2e0899f DK |
6631 | struct ilt_client_info ilt_cli; |
6632 | struct bnx2x_ilt ilt; | |
6633 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
6634 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
6635 | ||
b595076a | 6636 | /* initialize dummy TM client */ |
f2e0899f DK |
6637 | ilt_cli.start = 0; |
6638 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
6639 | ilt_cli.client_num = ILT_CLIENT_TM; | |
6640 | ||
6641 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
6642 | * Step 2: set the timers first/last ilt entry to point | |
6643 | * to the entire range to prevent ILT range error for 3rd/4th | |
619c5cb6 | 6644 | * vnic (this code assumes existance of the vnic) |
f2e0899f DK |
6645 | * |
6646 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
6647 | * with dummy TM client | |
6648 | * | |
6649 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
6650 | * and his brother are split registers | |
6651 | */ | |
6652 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
6653 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
6654 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6655 | ||
6656 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
6657 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
6658 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
6659 | } | |
6660 | ||
6661 | ||
34f80b04 EG |
6662 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
6663 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 6664 | |
619c5cb6 | 6665 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6666 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
6667 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 6668 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 6669 | |
619c5cb6 | 6670 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
6671 | |
6672 | /* let the HW do it's magic ... */ | |
6673 | do { | |
6674 | msleep(200); | |
6675 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
6676 | } while (factor-- && (val != 1)); | |
6677 | ||
6678 | if (val != 1) { | |
6679 | BNX2X_ERR("ATC_INIT failed\n"); | |
6680 | return -EBUSY; | |
6681 | } | |
6682 | } | |
6683 | ||
619c5cb6 | 6684 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 6685 | |
b56e9670 AE |
6686 | bnx2x_iov_init_dmae(bp); |
6687 | ||
34f80b04 EG |
6688 | /* clean the DMAE memory */ |
6689 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
6690 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
6691 | ||
6692 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
6693 | ||
6694 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
6695 | ||
6696 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 6697 | |
619c5cb6 | 6698 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 6699 | |
34f80b04 EG |
6700 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
6701 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
6702 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
6703 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
6704 | ||
619c5cb6 | 6705 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 6706 | |
f85582f8 | 6707 | |
523224a3 DK |
6708 | /* QM queues pointers table */ |
6709 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
6710 | ||
34f80b04 EG |
6711 | /* soft reset pulse */ |
6712 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
6713 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 6714 | |
55c11941 MS |
6715 | if (CNIC_SUPPORT(bp)) |
6716 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); | |
a2fbb9ea | 6717 | |
619c5cb6 | 6718 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
523224a3 | 6719 | REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT); |
619c5cb6 | 6720 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
6721 | /* enable hw interrupt from doorbell Q */ |
6722 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 6723 | |
619c5cb6 | 6724 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 6725 | |
619c5cb6 | 6726 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 6727 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 6728 | |
f2e0899f | 6729 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 6730 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 6731 | |
a3348722 BW |
6732 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
6733 | if (IS_MF_AFEX(bp)) { | |
6734 | /* configure that VNTag and VLAN headers must be | |
6735 | * received in afex mode | |
6736 | */ | |
6737 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
6738 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
6739 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
6740 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
6741 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
6742 | } else { | |
6743 | /* Bit-map indicating which L2 hdrs may appear | |
6744 | * after the basic Ethernet header | |
6745 | */ | |
6746 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
6747 | bp->path_has_ovlan ? 7 : 6); | |
6748 | } | |
6749 | } | |
a2fbb9ea | 6750 | |
619c5cb6 VZ |
6751 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
6752 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
6753 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
6754 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 6755 | |
619c5cb6 VZ |
6756 | if (!CHIP_IS_E1x(bp)) { |
6757 | /* reset VFC memories */ | |
6758 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6759 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6760 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6761 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6762 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6763 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6764 | |
619c5cb6 VZ |
6765 | msleep(20); |
6766 | } | |
a2fbb9ea | 6767 | |
619c5cb6 VZ |
6768 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6769 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6770 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6771 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6772 | |
34f80b04 EG |
6773 | /* sync semi rtc */ |
6774 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6775 | 0x80000000); | |
6776 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6777 | 0x80000000); | |
a2fbb9ea | 6778 | |
619c5cb6 VZ |
6779 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6780 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6781 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6782 | |
a3348722 BW |
6783 | if (!CHIP_IS_E1x(bp)) { |
6784 | if (IS_MF_AFEX(bp)) { | |
6785 | /* configure that VNTag and VLAN headers must be | |
6786 | * sent in afex mode | |
6787 | */ | |
6788 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
6789 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
6790 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
6791 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
6792 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
6793 | } else { | |
6794 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6795 | bp->path_has_ovlan ? 7 : 6); | |
6796 | } | |
6797 | } | |
f2e0899f | 6798 | |
34f80b04 | 6799 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6800 | |
619c5cb6 VZ |
6801 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6802 | ||
55c11941 MS |
6803 | if (CNIC_SUPPORT(bp)) { |
6804 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6805 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6806 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6807 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6808 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6809 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6810 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6811 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6812 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6813 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6814 | } | |
34f80b04 | 6815 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6816 | |
34f80b04 EG |
6817 | if (sizeof(union cdu_context) != 1024) |
6818 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
6819 | dev_alert(&bp->pdev->dev, |
6820 | "please adjust the size of cdu_context(%ld)\n", | |
6821 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 6822 | |
619c5cb6 | 6823 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
6824 | val = (4 << 24) + (0 << 12) + 1024; |
6825 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 6826 | |
619c5cb6 | 6827 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 6828 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
6829 | /* enable context validation interrupt from CFC */ |
6830 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
6831 | ||
6832 | /* set the thresholds to prevent CFC/CDU race */ | |
6833 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 6834 | |
619c5cb6 | 6835 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 6836 | |
619c5cb6 | 6837 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
6838 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
6839 | ||
619c5cb6 VZ |
6840 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
6841 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 6842 | |
34f80b04 EG |
6843 | /* Reset PCIE errors for debug */ |
6844 | REG_WR(bp, 0x2814, 0xffffffff); | |
6845 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 6846 | |
619c5cb6 | 6847 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6848 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
6849 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
6850 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
6851 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
6852 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
6853 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
6854 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
6855 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
6856 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
6857 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
6858 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
6859 | } | |
6860 | ||
619c5cb6 | 6861 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 6862 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
6863 | /* in E3 this done in per-port section */ |
6864 | if (!CHIP_IS_E3(bp)) | |
6865 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 6866 | } |
619c5cb6 VZ |
6867 | if (CHIP_IS_E1H(bp)) |
6868 | /* not applicable for E2 (and above ...) */ | |
6869 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
6870 | |
6871 | if (CHIP_REV_IS_SLOW(bp)) | |
6872 | msleep(200); | |
6873 | ||
6874 | /* finish CFC init */ | |
6875 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
6876 | if (val != 1) { | |
6877 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
6878 | return -EBUSY; | |
6879 | } | |
6880 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
6881 | if (val != 1) { | |
6882 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
6883 | return -EBUSY; | |
6884 | } | |
6885 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
6886 | if (val != 1) { | |
6887 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
6888 | return -EBUSY; | |
6889 | } | |
6890 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 6891 | |
f2e0899f DK |
6892 | if (CHIP_IS_E1(bp)) { |
6893 | /* read NIG statistic | |
6894 | to see if this is our first up since powerup */ | |
6895 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
6896 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 6897 | |
f2e0899f DK |
6898 | /* do internal memory self test */ |
6899 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
6900 | BNX2X_ERR("internal mem self test failed\n"); | |
6901 | return -EBUSY; | |
6902 | } | |
34f80b04 EG |
6903 | } |
6904 | ||
fd4ef40d EG |
6905 | bnx2x_setup_fan_failure_detection(bp); |
6906 | ||
34f80b04 EG |
6907 | /* clear PXP2 attentions */ |
6908 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 6909 | |
4a33bc03 | 6910 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 6911 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 6912 | |
6bbca910 | 6913 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
6914 | if (CHIP_IS_E1x(bp)) |
6915 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
6916 | } else |
6917 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
6918 | ||
34f80b04 EG |
6919 | return 0; |
6920 | } | |
a2fbb9ea | 6921 | |
619c5cb6 VZ |
6922 | /** |
6923 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
6924 | * | |
6925 | * @bp: driver handle | |
6926 | */ | |
6927 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
6928 | { | |
6929 | int rc = bnx2x_init_hw_common(bp); | |
6930 | ||
6931 | if (rc) | |
6932 | return rc; | |
6933 | ||
6934 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
6935 | if (!BP_NOMCP(bp)) | |
6936 | bnx2x__common_init_phy(bp); | |
6937 | ||
6938 | return 0; | |
6939 | } | |
6940 | ||
523224a3 | 6941 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
6942 | { |
6943 | int port = BP_PORT(bp); | |
619c5cb6 | 6944 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 6945 | u32 low, high; |
34f80b04 | 6946 | u32 val; |
a2fbb9ea | 6947 | |
619c5cb6 | 6948 | |
51c1a580 | 6949 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
6950 | |
6951 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 6952 | |
619c5cb6 VZ |
6953 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
6954 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
6955 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 6956 | |
f2e0899f DK |
6957 | /* Timers bug workaround: disables the pf_master bit in pglue at |
6958 | * common phase, we need to enable it here before any dmae access are | |
6959 | * attempted. Therefore we manually added the enable-master to the | |
6960 | * port phase (it also happens in the function phase) | |
6961 | */ | |
619c5cb6 | 6962 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6963 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
6964 | ||
619c5cb6 VZ |
6965 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
6966 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
6967 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
6968 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
6969 | ||
6970 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
6971 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
6972 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
6973 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 6974 | |
523224a3 DK |
6975 | /* QM cid (connection) count */ |
6976 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 6977 | |
55c11941 MS |
6978 | if (CNIC_SUPPORT(bp)) { |
6979 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
6980 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); | |
6981 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
6982 | } | |
cdaa7cb8 | 6983 | |
619c5cb6 | 6984 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f | 6985 | |
2b674047 DK |
6986 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
6987 | ||
f2e0899f | 6988 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { |
619c5cb6 VZ |
6989 | |
6990 | if (IS_MF(bp)) | |
6991 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
6992 | else if (bp->dev->mtu > 4096) { | |
6993 | if (bp->flags & ONE_PORT_FLAG) | |
6994 | low = 160; | |
6995 | else { | |
6996 | val = bp->dev->mtu; | |
6997 | /* (24*1024 + val*4)/256 */ | |
6998 | low = 96 + (val/64) + | |
6999 | ((val % 64) ? 1 : 0); | |
7000 | } | |
7001 | } else | |
7002 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
7003 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
7004 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
7005 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 7006 | } |
1c06328c | 7007 | |
619c5cb6 VZ |
7008 | if (CHIP_MODE_IS_4_PORT(bp)) |
7009 | REG_WR(bp, (BP_PORT(bp) ? | |
7010 | BRB1_REG_MAC_GUARANTIED_1 : | |
7011 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 7012 | |
ca00392c | 7013 | |
619c5cb6 | 7014 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
7015 | if (CHIP_IS_E3B0(bp)) { |
7016 | if (IS_MF_AFEX(bp)) { | |
7017 | /* configure headers for AFEX mode */ | |
7018 | REG_WR(bp, BP_PORT(bp) ? | |
7019 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7020 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
7021 | REG_WR(bp, BP_PORT(bp) ? | |
7022 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
7023 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
7024 | REG_WR(bp, BP_PORT(bp) ? | |
7025 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
7026 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
7027 | } else { | |
7028 | /* Ovlan exists only if we are in multi-function + | |
7029 | * switch-dependent mode, in switch-independent there | |
7030 | * is no ovlan headers | |
7031 | */ | |
7032 | REG_WR(bp, BP_PORT(bp) ? | |
7033 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7034 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
7035 | (bp->path_has_ovlan ? 7 : 6)); | |
7036 | } | |
7037 | } | |
356e2385 | 7038 | |
619c5cb6 VZ |
7039 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
7040 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7041 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7042 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 7043 | |
619c5cb6 VZ |
7044 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
7045 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7046 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7047 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 7048 | |
619c5cb6 VZ |
7049 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
7050 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 7051 | |
619c5cb6 VZ |
7052 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
7053 | ||
7054 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
7055 | /* configure PBF to work without PAUSE mtu 9000 */ |
7056 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 7057 | |
f2e0899f DK |
7058 | /* update threshold */ |
7059 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
7060 | /* update init credit */ | |
7061 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 7062 | |
f2e0899f DK |
7063 | /* probe changes */ |
7064 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
7065 | udelay(50); | |
7066 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
7067 | } | |
a2fbb9ea | 7068 | |
55c11941 MS |
7069 | if (CNIC_SUPPORT(bp)) |
7070 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7071 | ||
619c5cb6 VZ |
7072 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
7073 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
7074 | |
7075 | if (CHIP_IS_E1(bp)) { | |
7076 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7077 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7078 | } | |
619c5cb6 | 7079 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 7080 | |
619c5cb6 | 7081 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7082 | |
619c5cb6 | 7083 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 EG |
7084 | /* init aeu_mask_attn_func_0/1: |
7085 | * - SF mode: bits 3-7 are masked. only bits 0-2 are in use | |
7086 | * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF | |
7087 | * bits 4-7 are used for "per vn group attention" */ | |
e4901dde VZ |
7088 | val = IS_MF(bp) ? 0xF7 : 0x7; |
7089 | /* Enable DCBX attention for all but E1 */ | |
7090 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
7091 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 7092 | |
619c5cb6 VZ |
7093 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
7094 | ||
7095 | if (!CHIP_IS_E1x(bp)) { | |
7096 | /* Bit-map indicating which L2 hdrs may appear after the | |
7097 | * basic Ethernet header | |
7098 | */ | |
a3348722 BW |
7099 | if (IS_MF_AFEX(bp)) |
7100 | REG_WR(bp, BP_PORT(bp) ? | |
7101 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7102 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
7103 | else | |
7104 | REG_WR(bp, BP_PORT(bp) ? | |
7105 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7106 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
7107 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
7108 | |
7109 | if (CHIP_IS_E3(bp)) | |
7110 | REG_WR(bp, BP_PORT(bp) ? | |
7111 | NIG_REG_LLH1_MF_MODE : | |
7112 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
7113 | } | |
7114 | if (!CHIP_IS_E3(bp)) | |
7115 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 7116 | |
f2e0899f | 7117 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 7118 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 7119 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 7120 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 7121 | |
619c5cb6 | 7122 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7123 | val = 0; |
7124 | switch (bp->mf_mode) { | |
7125 | case MULTI_FUNCTION_SD: | |
7126 | val = 1; | |
7127 | break; | |
7128 | case MULTI_FUNCTION_SI: | |
a3348722 | 7129 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
7130 | val = 2; |
7131 | break; | |
7132 | } | |
7133 | ||
7134 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
7135 | NIG_REG_LLH0_CLS_TYPE), val); | |
7136 | } | |
1c06328c EG |
7137 | { |
7138 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
7139 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
7140 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
7141 | } | |
34f80b04 EG |
7142 | } |
7143 | ||
619c5cb6 VZ |
7144 | |
7145 | /* If SPIO5 is set to generate interrupts, enable it for this port */ | |
7146 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 7147 | if (val & MISC_SPIO_SPIO5) { |
4d295db0 EG |
7148 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
7149 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
7150 | val = REG_RD(bp, reg_addr); | |
f1410647 | 7151 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 7152 | REG_WR(bp, reg_addr, val); |
f1410647 | 7153 | } |
a2fbb9ea | 7154 | |
34f80b04 EG |
7155 | return 0; |
7156 | } | |
7157 | ||
34f80b04 EG |
7158 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
7159 | { | |
7160 | int reg; | |
32d68de1 | 7161 | u32 wb_write[2]; |
34f80b04 | 7162 | |
f2e0899f | 7163 | if (CHIP_IS_E1(bp)) |
34f80b04 | 7164 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
7165 | else |
7166 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 7167 | |
32d68de1 YM |
7168 | wb_write[0] = ONCHIP_ADDR1(addr); |
7169 | wb_write[1] = ONCHIP_ADDR2(addr); | |
7170 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
7171 | } |
7172 | ||
b56e9670 | 7173 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) |
1191cb83 ED |
7174 | { |
7175 | u32 data, ctl, cnt = 100; | |
7176 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
7177 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
7178 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
7179 | u32 sb_bit = 1 << (idu_sb_id%32); | |
b56e9670 | 7180 | u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; |
1191cb83 ED |
7181 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; |
7182 | ||
7183 | /* Not supported in BC mode */ | |
7184 | if (CHIP_INT_MODE_IS_BC(bp)) | |
7185 | return; | |
7186 | ||
7187 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
7188 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
7189 | IGU_REGULAR_CLEANUP_SET | | |
7190 | IGU_REGULAR_BCLEANUP; | |
7191 | ||
7192 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
7193 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
7194 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
7195 | ||
7196 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7197 | data, igu_addr_data); | |
7198 | REG_WR(bp, igu_addr_data, data); | |
7199 | mmiowb(); | |
7200 | barrier(); | |
7201 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7202 | ctl, igu_addr_ctl); | |
7203 | REG_WR(bp, igu_addr_ctl, ctl); | |
7204 | mmiowb(); | |
7205 | barrier(); | |
7206 | ||
7207 | /* wait for clean up to finish */ | |
7208 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
7209 | msleep(20); | |
7210 | ||
7211 | ||
7212 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { | |
7213 | DP(NETIF_MSG_HW, | |
7214 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
7215 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
7216 | } | |
7217 | } | |
7218 | ||
7219 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) | |
f2e0899f | 7220 | { |
619c5cb6 | 7221 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
7222 | } |
7223 | ||
1191cb83 | 7224 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
f2e0899f DK |
7225 | { |
7226 | u32 i, base = FUNC_ILT_BASE(func); | |
7227 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
7228 | bnx2x_ilt_wr(bp, i, 0); | |
7229 | } | |
7230 | ||
55c11941 | 7231 | |
910cc727 | 7232 | static void bnx2x_init_searcher(struct bnx2x *bp) |
55c11941 MS |
7233 | { |
7234 | int port = BP_PORT(bp); | |
7235 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
7236 | /* T1 hash bits value determines the T1 number of entries */ | |
7237 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
7238 | } | |
7239 | ||
7240 | static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) | |
7241 | { | |
7242 | int rc; | |
7243 | struct bnx2x_func_state_params func_params = {NULL}; | |
7244 | struct bnx2x_func_switch_update_params *switch_update_params = | |
7245 | &func_params.params.switch_update; | |
7246 | ||
7247 | /* Prepare parameters for function state transitions */ | |
7248 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7249 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
7250 | ||
7251 | func_params.f_obj = &bp->func_obj; | |
7252 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
7253 | ||
7254 | /* Function parameters */ | |
7255 | switch_update_params->suspend = suspend; | |
7256 | ||
7257 | rc = bnx2x_func_state_change(bp, &func_params); | |
7258 | ||
7259 | return rc; | |
7260 | } | |
7261 | ||
910cc727 | 7262 | static int bnx2x_reset_nic_mode(struct bnx2x *bp) |
55c11941 MS |
7263 | { |
7264 | int rc, i, port = BP_PORT(bp); | |
7265 | int vlan_en = 0, mac_en[NUM_MACS]; | |
7266 | ||
7267 | ||
7268 | /* Close input from network */ | |
7269 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7270 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
7271 | } else { | |
7272 | vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7273 | NIG_REG_LLH0_FUNC_EN); | |
7274 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7275 | NIG_REG_LLH0_FUNC_EN, 0); | |
7276 | for (i = 0; i < NUM_MACS; i++) { | |
7277 | mac_en[i] = REG_RD(bp, port ? | |
7278 | (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7279 | 4 * i) : | |
7280 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + | |
7281 | 4 * i)); | |
7282 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7283 | 4 * i) : | |
7284 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); | |
7285 | } | |
7286 | } | |
7287 | ||
7288 | /* Close BMC to host */ | |
7289 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7290 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); | |
7291 | ||
7292 | /* Suspend Tx switching to the PF. Completion of this ramrod | |
7293 | * further guarantees that all the packets of that PF / child | |
7294 | * VFs in BRB were processed by the Parser, so it is safe to | |
7295 | * change the NIC_MODE register. | |
7296 | */ | |
7297 | rc = bnx2x_func_switch_update(bp, 1); | |
7298 | if (rc) { | |
7299 | BNX2X_ERR("Can't suspend tx-switching!\n"); | |
7300 | return rc; | |
7301 | } | |
7302 | ||
7303 | /* Change NIC_MODE register */ | |
7304 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7305 | ||
7306 | /* Open input from network */ | |
7307 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7308 | bnx2x_set_rx_filter(&bp->link_params, 1); | |
7309 | } else { | |
7310 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7311 | NIG_REG_LLH0_FUNC_EN, vlan_en); | |
7312 | for (i = 0; i < NUM_MACS; i++) { | |
7313 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7314 | 4 * i) : | |
7315 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), | |
7316 | mac_en[i]); | |
7317 | } | |
7318 | } | |
7319 | ||
7320 | /* Enable BMC to host */ | |
7321 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7322 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); | |
7323 | ||
7324 | /* Resume Tx switching to the PF */ | |
7325 | rc = bnx2x_func_switch_update(bp, 0); | |
7326 | if (rc) { | |
7327 | BNX2X_ERR("Can't resume tx-switching!\n"); | |
7328 | return rc; | |
7329 | } | |
7330 | ||
7331 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7332 | return 0; | |
7333 | } | |
7334 | ||
7335 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp) | |
7336 | { | |
7337 | int rc; | |
7338 | ||
7339 | bnx2x_ilt_init_op_cnic(bp, INITOP_SET); | |
7340 | ||
7341 | if (CONFIGURE_NIC_MODE(bp)) { | |
7342 | /* Configrue searcher as part of function hw init */ | |
7343 | bnx2x_init_searcher(bp); | |
7344 | ||
7345 | /* Reset NIC mode */ | |
7346 | rc = bnx2x_reset_nic_mode(bp); | |
7347 | if (rc) | |
7348 | BNX2X_ERR("Can't change NIC mode!\n"); | |
7349 | return rc; | |
7350 | } | |
7351 | ||
7352 | return 0; | |
7353 | } | |
7354 | ||
523224a3 | 7355 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
7356 | { |
7357 | int port = BP_PORT(bp); | |
7358 | int func = BP_FUNC(bp); | |
619c5cb6 | 7359 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
7360 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
7361 | u16 cdu_ilt_start; | |
8badd27a | 7362 | u32 addr, val; |
f4a66897 | 7363 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 7364 | int i, main_mem_width, rc; |
34f80b04 | 7365 | |
51c1a580 | 7366 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 7367 | |
619c5cb6 | 7368 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
7369 | if (!CHIP_IS_E1x(bp)) { |
7370 | rc = bnx2x_pf_flr_clnup(bp); | |
7371 | if (rc) | |
7372 | return rc; | |
7373 | } | |
619c5cb6 | 7374 | |
8badd27a | 7375 | /* set MSI reconfigure capability */ |
f2e0899f DK |
7376 | if (bp->common.int_block == INT_BLOCK_HC) { |
7377 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
7378 | val = REG_RD(bp, addr); | |
7379 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
7380 | REG_WR(bp, addr, val); | |
7381 | } | |
8badd27a | 7382 | |
619c5cb6 VZ |
7383 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
7384 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
7385 | ||
523224a3 DK |
7386 | ilt = BP_ILT(bp); |
7387 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 7388 | |
290ca2bb AE |
7389 | if (IS_SRIOV(bp)) |
7390 | cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; | |
7391 | cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); | |
7392 | ||
7393 | /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes | |
7394 | * those of the VFs, so start line should be reset | |
7395 | */ | |
7396 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
523224a3 | 7397 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
a052997e | 7398 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
523224a3 | 7399 | ilt->lines[cdu_ilt_start + i].page_mapping = |
a052997e MS |
7400 | bp->context[i].cxt_mapping; |
7401 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; | |
37b091ba | 7402 | } |
290ca2bb | 7403 | |
523224a3 | 7404 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 7405 | |
55c11941 MS |
7406 | if (!CONFIGURE_NIC_MODE(bp)) { |
7407 | bnx2x_init_searcher(bp); | |
7408 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7409 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7410 | } else { | |
7411 | /* Set NIC mode */ | |
7412 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
7413 | DP(NETIF_MSG_IFUP, "NIC MODE configrued\n"); | |
37b091ba | 7414 | |
55c11941 | 7415 | } |
37b091ba | 7416 | |
619c5cb6 | 7417 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7418 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
7419 | ||
7420 | /* Turn on a single ISR mode in IGU if driver is going to use | |
7421 | * INT#x or MSI | |
7422 | */ | |
7423 | if (!(bp->flags & USING_MSIX_FLAG)) | |
7424 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
7425 | /* | |
7426 | * Timers workaround bug: function init part. | |
7427 | * Need to wait 20msec after initializing ILT, | |
7428 | * needed to make sure there are no requests in | |
7429 | * one of the PXP internal queues with "old" ILT addresses | |
7430 | */ | |
7431 | msleep(20); | |
7432 | /* | |
7433 | * Master enable - Due to WB DMAE writes performed before this | |
7434 | * register is re-initialized as part of the regular function | |
7435 | * init | |
7436 | */ | |
7437 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
7438 | /* Enable the function in IGU */ | |
7439 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
7440 | } | |
7441 | ||
523224a3 | 7442 | bp->dmae_ready = 1; |
34f80b04 | 7443 | |
619c5cb6 | 7444 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 7445 | |
619c5cb6 | 7446 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7447 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
7448 | ||
619c5cb6 VZ |
7449 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7450 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7451 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
7452 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7453 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
7454 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7455 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7456 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7457 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
7458 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
7459 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7460 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7461 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
7462 | ||
7463 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7464 | REG_WR(bp, QM_REG_PF_EN, 1); |
7465 | ||
619c5cb6 VZ |
7466 | if (!CHIP_IS_E1x(bp)) { |
7467 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7468 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7469 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7470 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7471 | } | |
7472 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7473 | ||
7474 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7475 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
b56e9670 AE |
7476 | |
7477 | bnx2x_iov_init_dq(bp); | |
7478 | ||
619c5cb6 VZ |
7479 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
7480 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
7481 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
7482 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7483 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7484 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
7485 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
7486 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
7487 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
7488 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7489 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
7490 | ||
619c5cb6 | 7491 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 7492 | |
619c5cb6 | 7493 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 7494 | |
619c5cb6 | 7495 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7496 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
7497 | ||
fb3bff17 | 7498 | if (IS_MF(bp)) { |
34f80b04 | 7499 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 7500 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
7501 | } |
7502 | ||
619c5cb6 | 7503 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 7504 | |
34f80b04 | 7505 | /* HC init per function */ |
f2e0899f DK |
7506 | if (bp->common.int_block == INT_BLOCK_HC) { |
7507 | if (CHIP_IS_E1H(bp)) { | |
7508 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
7509 | ||
7510 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7511 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7512 | } | |
619c5cb6 | 7513 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
7514 | |
7515 | } else { | |
7516 | int num_segs, sb_idx, prod_offset; | |
7517 | ||
34f80b04 EG |
7518 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
7519 | ||
619c5cb6 | 7520 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7521 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
7522 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7523 | } | |
7524 | ||
619c5cb6 | 7525 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7526 | |
619c5cb6 | 7527 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7528 | int dsb_idx = 0; |
7529 | /** | |
7530 | * Producer memory: | |
7531 | * E2 mode: address 0-135 match to the mapping memory; | |
7532 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
7533 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
7534 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
7535 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
7536 | * 144-147 reserved. | |
7537 | * | |
7538 | * E1.5 mode - In backward compatible mode; | |
7539 | * for non default SB; each even line in the memory | |
7540 | * holds the U producer and each odd line hold | |
7541 | * the C producer. The first 128 producers are for | |
7542 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
7543 | * producers are for the DSB for each PF. | |
7544 | * Each PF has five segments: (the order inside each | |
7545 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
7546 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
7547 | * 144-147 attn prods; | |
7548 | */ | |
7549 | /* non-default-status-blocks */ | |
7550 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7551 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
7552 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
7553 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
7554 | num_segs; | |
7555 | ||
7556 | for (i = 0; i < num_segs; i++) { | |
7557 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7558 | (prod_offset + i) * 4; | |
7559 | REG_WR(bp, addr, 0); | |
7560 | } | |
7561 | /* send consumer update with value 0 */ | |
7562 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
7563 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7564 | bnx2x_igu_clear_sb(bp, | |
7565 | bp->igu_base_sb + sb_idx); | |
7566 | } | |
7567 | ||
7568 | /* default-status-blocks */ | |
7569 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7570 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
7571 | ||
7572 | if (CHIP_MODE_IS_4_PORT(bp)) | |
7573 | dsb_idx = BP_FUNC(bp); | |
7574 | else | |
3395a033 | 7575 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
7576 | |
7577 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
7578 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
7579 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
7580 | ||
3395a033 DK |
7581 | /* |
7582 | * igu prods come in chunks of E1HVN_MAX (4) - | |
7583 | * does not matters what is the current chip mode | |
7584 | */ | |
f2e0899f DK |
7585 | for (i = 0; i < (num_segs * E1HVN_MAX); |
7586 | i += E1HVN_MAX) { | |
7587 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7588 | (prod_offset + i)*4; | |
7589 | REG_WR(bp, addr, 0); | |
7590 | } | |
7591 | /* send consumer update with 0 */ | |
7592 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
7593 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7594 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7595 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7596 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
7597 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7598 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
7599 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7600 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
7601 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7602 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7603 | } else { | |
7604 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7605 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7606 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7607 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7608 | } | |
7609 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
7610 | ||
7611 | /* !!! these should become driver const once | |
7612 | rf-tool supports split-68 const */ | |
7613 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
7614 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
7615 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
7616 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
7617 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
7618 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
7619 | } | |
34f80b04 | 7620 | } |
34f80b04 | 7621 | |
c14423fe | 7622 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
7623 | REG_WR(bp, 0x2114, 0xffffffff); |
7624 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 7625 | |
f4a66897 VZ |
7626 | if (CHIP_IS_E1x(bp)) { |
7627 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
7628 | main_mem_base = HC_REG_MAIN_MEMORY + | |
7629 | BP_PORT(bp) * (main_mem_size * 4); | |
7630 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
7631 | main_mem_width = 8; | |
7632 | ||
7633 | val = REG_RD(bp, main_mem_prty_clr); | |
7634 | if (val) | |
51c1a580 MS |
7635 | DP(NETIF_MSG_HW, |
7636 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
7637 | val); | |
f4a66897 VZ |
7638 | |
7639 | /* Clear "false" parity errors in MSI-X table */ | |
7640 | for (i = main_mem_base; | |
7641 | i < main_mem_base + main_mem_size * 4; | |
7642 | i += main_mem_width) { | |
7643 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
7644 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
7645 | i, main_mem_width / 4); | |
7646 | } | |
7647 | /* Clear HC parity attention */ | |
7648 | REG_RD(bp, main_mem_prty_clr); | |
7649 | } | |
7650 | ||
619c5cb6 VZ |
7651 | #ifdef BNX2X_STOP_ON_ERROR |
7652 | /* Enable STORMs SP logging */ | |
7653 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
7654 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7655 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
7656 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7657 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7658 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7659 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
7660 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7661 | #endif | |
7662 | ||
b7737c9b | 7663 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 7664 | |
34f80b04 EG |
7665 | return 0; |
7666 | } | |
7667 | ||
a2fbb9ea | 7668 | |
55c11941 MS |
7669 | void bnx2x_free_mem_cnic(struct bnx2x *bp) |
7670 | { | |
7671 | bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); | |
7672 | ||
7673 | if (!CHIP_IS_E1x(bp)) | |
7674 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, | |
7675 | sizeof(struct host_hc_status_block_e2)); | |
7676 | else | |
7677 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
7678 | sizeof(struct host_hc_status_block_e1x)); | |
7679 | ||
7680 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); | |
7681 | } | |
7682 | ||
9f6c9258 | 7683 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 7684 | { |
a052997e MS |
7685 | int i; |
7686 | ||
a2fbb9ea | 7687 | /* fastpath */ |
b3b83c3f | 7688 | bnx2x_free_fp_mem(bp); |
a2fbb9ea ET |
7689 | /* end of fastpath */ |
7690 | ||
7691 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
523224a3 | 7692 | sizeof(struct host_sp_status_block)); |
a2fbb9ea | 7693 | |
619c5cb6 VZ |
7694 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
7695 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7696 | ||
a2fbb9ea | 7697 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 7698 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 7699 | |
a052997e MS |
7700 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
7701 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, | |
7702 | bp->context[i].size); | |
523224a3 DK |
7703 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
7704 | ||
7705 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 7706 | |
7a9b2557 | 7707 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 7708 | |
523224a3 DK |
7709 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
7710 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
619c5cb6 VZ |
7711 | } |
7712 | ||
a2fbb9ea | 7713 | |
55c11941 | 7714 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp) |
a2fbb9ea | 7715 | { |
619c5cb6 VZ |
7716 | if (!CHIP_IS_E1x(bp)) |
7717 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
7718 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
7719 | sizeof(struct host_hc_status_block_e2)); | |
7720 | else | |
55c11941 MS |
7721 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, |
7722 | &bp->cnic_sb_mapping, | |
7723 | sizeof(struct | |
7724 | host_hc_status_block_e1x)); | |
8badd27a | 7725 | |
55c11941 MS |
7726 | if (CONFIGURE_NIC_MODE(bp)) |
7727 | /* allocate searcher T2 table, as it wan't allocated before */ | |
7728 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
7729 | ||
7730 | /* write address to which L5 should insert its values */ | |
7731 | bp->cnic_eth_dev.addr_drv_info_to_mcp = | |
7732 | &bp->slowpath->drv_info_to_mcp; | |
7733 | ||
7734 | if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) | |
7735 | goto alloc_mem_err; | |
7736 | ||
7737 | return 0; | |
7738 | ||
7739 | alloc_mem_err: | |
7740 | bnx2x_free_mem_cnic(bp); | |
7741 | BNX2X_ERR("Can't allocate memory\n"); | |
7742 | return -ENOMEM; | |
7743 | } | |
7744 | ||
7745 | int bnx2x_alloc_mem(struct bnx2x *bp) | |
7746 | { | |
7747 | int i, allocated, context_size; | |
a2fbb9ea | 7748 | |
55c11941 MS |
7749 | if (!CONFIGURE_NIC_MODE(bp)) |
7750 | /* allocate searcher T2 table */ | |
7751 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
8badd27a | 7752 | |
523224a3 DK |
7753 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
7754 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 7755 | |
523224a3 DK |
7756 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
7757 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 7758 | |
a052997e MS |
7759 | /* Allocate memory for CDU context: |
7760 | * This memory is allocated separately and not in the generic ILT | |
7761 | * functions because CDU differs in few aspects: | |
7762 | * 1. There are multiple entities allocating memory for context - | |
7763 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls | |
7764 | * its own ILT lines. | |
7765 | * 2. Since CDU page-size is not a single 4KB page (which is the case | |
7766 | * for the other ILT clients), to be efficient we want to support | |
7767 | * allocation of sub-page-size in the last entry. | |
7768 | * 3. Context pointers are used by the driver to pass to FW / update | |
7769 | * the context (for the other ILT clients the pointers are used just to | |
7770 | * free the memory during unload). | |
7771 | */ | |
7772 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); | |
65abd74d | 7773 | |
a052997e MS |
7774 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
7775 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, | |
7776 | (context_size - allocated)); | |
7777 | BNX2X_PCI_ALLOC(bp->context[i].vcxt, | |
7778 | &bp->context[i].cxt_mapping, | |
7779 | bp->context[i].size); | |
7780 | allocated += bp->context[i].size; | |
7781 | } | |
523224a3 | 7782 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 7783 | |
523224a3 DK |
7784 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
7785 | goto alloc_mem_err; | |
65abd74d | 7786 | |
67c431a5 AE |
7787 | if (bnx2x_iov_alloc_mem(bp)) |
7788 | goto alloc_mem_err; | |
7789 | ||
9f6c9258 DK |
7790 | /* Slow path ring */ |
7791 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 7792 | |
523224a3 DK |
7793 | /* EQ */ |
7794 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
7795 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 7796 | |
9f6c9258 | 7797 | return 0; |
e1510706 | 7798 | |
9f6c9258 DK |
7799 | alloc_mem_err: |
7800 | bnx2x_free_mem(bp); | |
51c1a580 | 7801 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 7802 | return -ENOMEM; |
65abd74d YG |
7803 | } |
7804 | ||
a2fbb9ea ET |
7805 | /* |
7806 | * Init service functions | |
7807 | */ | |
a2fbb9ea | 7808 | |
619c5cb6 VZ |
7809 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
7810 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
7811 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 7812 | { |
619c5cb6 VZ |
7813 | int rc; |
7814 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 7815 | |
619c5cb6 | 7816 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 7817 | |
619c5cb6 VZ |
7818 | /* Fill general parameters */ |
7819 | ramrod_param.vlan_mac_obj = obj; | |
7820 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 7821 | |
619c5cb6 VZ |
7822 | /* Fill a user request section if needed */ |
7823 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
7824 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 7825 | |
619c5cb6 | 7826 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 7827 | |
619c5cb6 VZ |
7828 | /* Set the command: ADD or DEL */ |
7829 | if (set) | |
7830 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
7831 | else | |
7832 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
7833 | } |
7834 | ||
619c5cb6 | 7835 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7b5342d9 YM |
7836 | |
7837 | if (rc == -EEXIST) { | |
7838 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
7839 | /* do not treat adding same MAC as error */ | |
7840 | rc = 0; | |
7841 | } else if (rc < 0) | |
619c5cb6 | 7842 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); |
7b5342d9 | 7843 | |
619c5cb6 | 7844 | return rc; |
a2fbb9ea ET |
7845 | } |
7846 | ||
619c5cb6 VZ |
7847 | int bnx2x_del_all_macs(struct bnx2x *bp, |
7848 | struct bnx2x_vlan_mac_obj *mac_obj, | |
7849 | int mac_type, bool wait_for_comp) | |
e665bfda | 7850 | { |
619c5cb6 VZ |
7851 | int rc; |
7852 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 7853 | |
619c5cb6 VZ |
7854 | /* Wait for completion of requested */ |
7855 | if (wait_for_comp) | |
7856 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 7857 | |
619c5cb6 VZ |
7858 | /* Set the mac type of addresses we want to clear */ |
7859 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 7860 | |
619c5cb6 VZ |
7861 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
7862 | if (rc < 0) | |
7863 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 7864 | |
619c5cb6 | 7865 | return rc; |
0793f83f DK |
7866 | } |
7867 | ||
619c5cb6 | 7868 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 7869 | { |
619c5cb6 | 7870 | unsigned long ramrod_flags = 0; |
e665bfda | 7871 | |
a3348722 BW |
7872 | if (is_zero_ether_addr(bp->dev->dev_addr) && |
7873 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { | |
51c1a580 MS |
7874 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, |
7875 | "Ignoring Zero MAC for STORAGE SD mode\n"); | |
614c76df DK |
7876 | return 0; |
7877 | } | |
614c76df | 7878 | |
619c5cb6 | 7879 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
0793f83f | 7880 | |
619c5cb6 VZ |
7881 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); |
7882 | /* Eth MAC is set on RSS leading client (fp[0]) */ | |
15192a8c BW |
7883 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj, |
7884 | set, BNX2X_ETH_MAC, &ramrod_flags); | |
e665bfda | 7885 | } |
6e30dd4e | 7886 | |
619c5cb6 | 7887 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 7888 | { |
619c5cb6 | 7889 | return bnx2x_setup_queue(bp, &bp->fp[0], 1); |
993ac7b5 | 7890 | } |
a2fbb9ea | 7891 | |
d6214d7a | 7892 | /** |
e8920674 | 7893 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 7894 | * |
e8920674 | 7895 | * @bp: driver handle |
d6214d7a | 7896 | * |
e8920674 | 7897 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 7898 | */ |
1ab4434c | 7899 | int bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 7900 | { |
1ab4434c AE |
7901 | int rc = 0; |
7902 | ||
7903 | if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) | |
7904 | return -EINVAL; | |
7905 | ||
9ee3d37b | 7906 | switch (int_mode) { |
1ab4434c AE |
7907 | case BNX2X_INT_MODE_MSIX: |
7908 | /* attempt to enable msix */ | |
7909 | rc = bnx2x_enable_msix(bp); | |
7910 | ||
7911 | /* msix attained */ | |
7912 | if (!rc) | |
7913 | return 0; | |
7914 | ||
7915 | /* vfs use only msix */ | |
7916 | if (rc && IS_VF(bp)) | |
7917 | return rc; | |
7918 | ||
7919 | /* failed to enable multiple MSI-X */ | |
7920 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
7921 | bp->num_queues, | |
7922 | 1 + bp->num_cnic_queues); | |
7923 | ||
7924 | /* falling through... */ | |
7925 | case BNX2X_INT_MODE_MSI: | |
d6214d7a | 7926 | bnx2x_enable_msi(bp); |
1ab4434c | 7927 | |
d6214d7a | 7928 | /* falling through... */ |
1ab4434c | 7929 | case BNX2X_INT_MODE_INTX: |
55c11941 MS |
7930 | bp->num_ethernet_queues = 1; |
7931 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
51c1a580 | 7932 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 7933 | break; |
d6214d7a | 7934 | default: |
1ab4434c AE |
7935 | BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); |
7936 | return -EINVAL; | |
9f6c9258 | 7937 | } |
1ab4434c | 7938 | return 0; |
a2fbb9ea ET |
7939 | } |
7940 | ||
1ab4434c | 7941 | /* must be called prior to any HW initializations */ |
c2bff63f DK |
7942 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) |
7943 | { | |
290ca2bb AE |
7944 | if (IS_SRIOV(bp)) |
7945 | return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; | |
c2bff63f DK |
7946 | return L2_ILT_LINES(bp); |
7947 | } | |
7948 | ||
523224a3 DK |
7949 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
7950 | { | |
7951 | struct ilt_client_info *ilt_client; | |
7952 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
7953 | u16 line = 0; | |
7954 | ||
7955 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
7956 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
7957 | ||
7958 | /* CDU */ | |
7959 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
7960 | ilt_client->client_num = ILT_CLIENT_CDU; | |
7961 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
7962 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
7963 | ilt_client->start = line; | |
619c5cb6 | 7964 | line += bnx2x_cid_ilt_lines(bp); |
55c11941 MS |
7965 | |
7966 | if (CNIC_SUPPORT(bp)) | |
7967 | line += CNIC_ILT_LINES; | |
523224a3 DK |
7968 | ilt_client->end = line - 1; |
7969 | ||
51c1a580 | 7970 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
7971 | ilt_client->start, |
7972 | ilt_client->end, | |
7973 | ilt_client->page_size, | |
7974 | ilt_client->flags, | |
7975 | ilog2(ilt_client->page_size >> 12)); | |
7976 | ||
7977 | /* QM */ | |
7978 | if (QM_INIT(bp->qm_cid_count)) { | |
7979 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
7980 | ilt_client->client_num = ILT_CLIENT_QM; | |
7981 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
7982 | ilt_client->flags = 0; | |
7983 | ilt_client->start = line; | |
7984 | ||
7985 | /* 4 bytes for each cid */ | |
7986 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
7987 | QM_ILT_PAGE_SZ); | |
7988 | ||
7989 | ilt_client->end = line - 1; | |
7990 | ||
51c1a580 MS |
7991 | DP(NETIF_MSG_IFUP, |
7992 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
7993 | ilt_client->start, |
7994 | ilt_client->end, | |
7995 | ilt_client->page_size, | |
7996 | ilt_client->flags, | |
7997 | ilog2(ilt_client->page_size >> 12)); | |
7998 | ||
7999 | } | |
523224a3 | 8000 | |
55c11941 MS |
8001 | if (CNIC_SUPPORT(bp)) { |
8002 | /* SRC */ | |
8003 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
8004 | ilt_client->client_num = ILT_CLIENT_SRC; | |
8005 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
8006 | ilt_client->flags = 0; | |
8007 | ilt_client->start = line; | |
8008 | line += SRC_ILT_LINES; | |
8009 | ilt_client->end = line - 1; | |
523224a3 | 8010 | |
55c11941 MS |
8011 | DP(NETIF_MSG_IFUP, |
8012 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8013 | ilt_client->start, | |
8014 | ilt_client->end, | |
8015 | ilt_client->page_size, | |
8016 | ilt_client->flags, | |
8017 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 8018 | |
55c11941 MS |
8019 | /* TM */ |
8020 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
8021 | ilt_client->client_num = ILT_CLIENT_TM; | |
8022 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
8023 | ilt_client->flags = 0; | |
8024 | ilt_client->start = line; | |
8025 | line += TM_ILT_LINES; | |
8026 | ilt_client->end = line - 1; | |
523224a3 | 8027 | |
55c11941 MS |
8028 | DP(NETIF_MSG_IFUP, |
8029 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8030 | ilt_client->start, | |
8031 | ilt_client->end, | |
8032 | ilt_client->page_size, | |
8033 | ilt_client->flags, | |
8034 | ilog2(ilt_client->page_size >> 12)); | |
8035 | } | |
9f6c9258 | 8036 | |
619c5cb6 | 8037 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 8038 | } |
f85582f8 | 8039 | |
619c5cb6 VZ |
8040 | /** |
8041 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
8042 | * | |
8043 | * @bp: driver handle | |
8044 | * @fp: pointer to fastpath | |
8045 | * @init_params: pointer to parameters structure | |
8046 | * | |
8047 | * parameters configured: | |
8048 | * - HC configuration | |
8049 | * - Queue's CDU context | |
8050 | */ | |
1191cb83 | 8051 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
619c5cb6 | 8052 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
a2fbb9ea | 8053 | { |
6383c0b3 AE |
8054 | |
8055 | u8 cos; | |
a052997e MS |
8056 | int cxt_index, cxt_offset; |
8057 | ||
619c5cb6 VZ |
8058 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
8059 | if (!IS_FCOE_FP(fp)) { | |
8060 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
8061 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
8062 | ||
8063 | /* If HC is supporterd, enable host coalescing in the transition | |
8064 | * to INIT state. | |
8065 | */ | |
8066 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
8067 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
8068 | ||
8069 | /* HC rate */ | |
8070 | init_params->rx.hc_rate = bp->rx_ticks ? | |
8071 | (1000000 / bp->rx_ticks) : 0; | |
8072 | init_params->tx.hc_rate = bp->tx_ticks ? | |
8073 | (1000000 / bp->tx_ticks) : 0; | |
8074 | ||
8075 | /* FW SB ID */ | |
8076 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
8077 | fp->fw_sb_id; | |
8078 | ||
8079 | /* | |
8080 | * CQ index among the SB indices: FCoE clients uses the default | |
8081 | * SB, therefore it's different. | |
8082 | */ | |
6383c0b3 AE |
8083 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
8084 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
8085 | } |
8086 | ||
6383c0b3 AE |
8087 | /* set maximum number of COSs supported by this queue */ |
8088 | init_params->max_cos = fp->max_cos; | |
8089 | ||
51c1a580 | 8090 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
8091 | fp->index, init_params->max_cos); |
8092 | ||
8093 | /* set the context pointers queue object */ | |
a052997e | 8094 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
65565884 MS |
8095 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
8096 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * | |
a052997e | 8097 | ILT_PAGE_CIDS); |
6383c0b3 | 8098 | init_params->cxts[cos] = |
a052997e MS |
8099 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
8100 | } | |
619c5cb6 VZ |
8101 | } |
8102 | ||
910cc727 | 8103 | static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
6383c0b3 AE |
8104 | struct bnx2x_queue_state_params *q_params, |
8105 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
8106 | int tx_index, bool leading) | |
8107 | { | |
8108 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
8109 | ||
8110 | /* Set the command */ | |
8111 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
8112 | ||
8113 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
8114 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
8115 | ||
8116 | /* choose the index of the cid to send the slow path on */ | |
8117 | tx_only_params->cid_index = tx_index; | |
8118 | ||
8119 | /* Set general TX_ONLY_SETUP parameters */ | |
8120 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
8121 | ||
8122 | /* Set Tx TX_ONLY_SETUP parameters */ | |
8123 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
8124 | ||
51c1a580 MS |
8125 | DP(NETIF_MSG_IFUP, |
8126 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
8127 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
8128 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
8129 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
8130 | ||
8131 | /* send the ramrod */ | |
8132 | return bnx2x_queue_state_change(bp, q_params); | |
8133 | } | |
8134 | ||
8135 | ||
619c5cb6 VZ |
8136 | /** |
8137 | * bnx2x_setup_queue - setup queue | |
8138 | * | |
8139 | * @bp: driver handle | |
8140 | * @fp: pointer to fastpath | |
8141 | * @leading: is leading | |
8142 | * | |
8143 | * This function performs 2 steps in a Queue state machine | |
8144 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
8145 | */ | |
8146 | ||
8147 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
8148 | bool leading) | |
8149 | { | |
3b603066 | 8150 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
8151 | struct bnx2x_queue_setup_params *setup_params = |
8152 | &q_params.params.setup; | |
6383c0b3 AE |
8153 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
8154 | &q_params.params.tx_only; | |
a2fbb9ea | 8155 | int rc; |
6383c0b3 AE |
8156 | u8 tx_index; |
8157 | ||
51c1a580 | 8158 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 8159 | |
ec6ba945 VZ |
8160 | /* reset IGU state skip FCoE L2 queue */ |
8161 | if (!IS_FCOE_FP(fp)) | |
8162 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 8163 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 8164 | |
15192a8c | 8165 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8166 | /* We want to wait for completion in this context */ |
8167 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8168 | |
619c5cb6 VZ |
8169 | /* Prepare the INIT parameters */ |
8170 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 8171 | |
619c5cb6 VZ |
8172 | /* Set the command */ |
8173 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
8174 | ||
8175 | /* Change the state to INIT */ | |
8176 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8177 | if (rc) { | |
6383c0b3 | 8178 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
8179 | return rc; |
8180 | } | |
ec6ba945 | 8181 | |
51c1a580 | 8182 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 AE |
8183 | |
8184 | ||
619c5cb6 VZ |
8185 | /* Now move the Queue to the SETUP state... */ |
8186 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 8187 | |
619c5cb6 VZ |
8188 | /* Set QUEUE flags */ |
8189 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 8190 | |
619c5cb6 | 8191 | /* Set general SETUP parameters */ |
6383c0b3 AE |
8192 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
8193 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 8194 | |
6383c0b3 | 8195 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
8196 | &setup_params->rxq_params); |
8197 | ||
6383c0b3 AE |
8198 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
8199 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
8200 | |
8201 | /* Set the command */ | |
8202 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
8203 | ||
55c11941 MS |
8204 | if (IS_FCOE_FP(fp)) |
8205 | bp->fcoe_init = true; | |
8206 | ||
619c5cb6 VZ |
8207 | /* Change the state to SETUP */ |
8208 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
8209 | if (rc) { |
8210 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
8211 | return rc; | |
8212 | } | |
8213 | ||
8214 | /* loop through the relevant tx-only indices */ | |
8215 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8216 | tx_index < fp->max_cos; | |
8217 | tx_index++) { | |
8218 | ||
8219 | /* prepare and send tx-only ramrod*/ | |
8220 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
8221 | tx_only_params, tx_index, leading); | |
8222 | if (rc) { | |
8223 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
8224 | fp->index, tx_index); | |
8225 | return rc; | |
8226 | } | |
8227 | } | |
523224a3 | 8228 | |
34f80b04 | 8229 | return rc; |
a2fbb9ea ET |
8230 | } |
8231 | ||
619c5cb6 | 8232 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 8233 | { |
619c5cb6 | 8234 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 8235 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 8236 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
8237 | int rc, tx_index; |
8238 | ||
51c1a580 | 8239 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 8240 | |
15192a8c | 8241 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8242 | /* We want to wait for completion in this context */ |
8243 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8244 | |
6383c0b3 AE |
8245 | |
8246 | /* close tx-only connections */ | |
8247 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8248 | tx_index < fp->max_cos; | |
8249 | tx_index++){ | |
8250 | ||
8251 | /* ascertain this is a normal queue*/ | |
65565884 | 8252 | txdata = fp->txdata_ptr[tx_index]; |
6383c0b3 | 8253 | |
51c1a580 | 8254 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
8255 | txdata->txq_index); |
8256 | ||
8257 | /* send halt terminate on tx-only connection */ | |
8258 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
8259 | memset(&q_params.params.terminate, 0, | |
8260 | sizeof(q_params.params.terminate)); | |
8261 | q_params.params.terminate.cid_index = tx_index; | |
8262 | ||
8263 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8264 | if (rc) | |
8265 | return rc; | |
8266 | ||
8267 | /* send halt terminate on tx-only connection */ | |
8268 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
8269 | memset(&q_params.params.cfc_del, 0, | |
8270 | sizeof(q_params.params.cfc_del)); | |
8271 | q_params.params.cfc_del.cid_index = tx_index; | |
8272 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8273 | if (rc) | |
8274 | return rc; | |
8275 | } | |
8276 | /* Stop the primary connection: */ | |
8277 | /* ...halt the connection */ | |
619c5cb6 VZ |
8278 | q_params.cmd = BNX2X_Q_CMD_HALT; |
8279 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8280 | if (rc) | |
da5a662a | 8281 | return rc; |
a2fbb9ea | 8282 | |
6383c0b3 | 8283 | /* ...terminate the connection */ |
619c5cb6 | 8284 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
8285 | memset(&q_params.params.terminate, 0, |
8286 | sizeof(q_params.params.terminate)); | |
8287 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
8288 | rc = bnx2x_queue_state_change(bp, &q_params); |
8289 | if (rc) | |
523224a3 | 8290 | return rc; |
6383c0b3 | 8291 | /* ...delete cfc entry */ |
619c5cb6 | 8292 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
8293 | memset(&q_params.params.cfc_del, 0, |
8294 | sizeof(q_params.params.cfc_del)); | |
8295 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 8296 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
8297 | } |
8298 | ||
8299 | ||
34f80b04 EG |
8300 | static void bnx2x_reset_func(struct bnx2x *bp) |
8301 | { | |
8302 | int port = BP_PORT(bp); | |
8303 | int func = BP_FUNC(bp); | |
f2e0899f | 8304 | int i; |
523224a3 DK |
8305 | |
8306 | /* Disable the function in the FW */ | |
8307 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
8308 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
8309 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
8310 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
8311 | ||
8312 | /* FP SBs */ | |
ec6ba945 | 8313 | for_each_eth_queue(bp, i) { |
523224a3 | 8314 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 8315 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8316 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
8317 | SB_DISABLED); | |
523224a3 DK |
8318 | } |
8319 | ||
55c11941 MS |
8320 | if (CNIC_LOADED(bp)) |
8321 | /* CNIC SB */ | |
8322 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8323 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET | |
8324 | (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); | |
8325 | ||
523224a3 | 8326 | /* SP SB */ |
619c5cb6 | 8327 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8328 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
8329 | SB_DISABLED); | |
523224a3 DK |
8330 | |
8331 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
8332 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
8333 | 0); | |
34f80b04 EG |
8334 | |
8335 | /* Configure IGU */ | |
f2e0899f DK |
8336 | if (bp->common.int_block == INT_BLOCK_HC) { |
8337 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8338 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8339 | } else { | |
8340 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
8341 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8342 | } | |
34f80b04 | 8343 | |
55c11941 MS |
8344 | if (CNIC_LOADED(bp)) { |
8345 | /* Disable Timer scan */ | |
8346 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
8347 | /* | |
8348 | * Wait for at least 10ms and up to 2 second for the timers | |
8349 | * scan to complete | |
8350 | */ | |
8351 | for (i = 0; i < 200; i++) { | |
8352 | msleep(10); | |
8353 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) | |
8354 | break; | |
8355 | } | |
37b091ba | 8356 | } |
34f80b04 | 8357 | /* Clear ILT */ |
f2e0899f DK |
8358 | bnx2x_clear_func_ilt(bp, func); |
8359 | ||
8360 | /* Timers workaround bug for E2: if this is vnic-3, | |
8361 | * we need to set the entire ilt range for this timers. | |
8362 | */ | |
619c5cb6 | 8363 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
8364 | struct ilt_client_info ilt_cli; |
8365 | /* use dummy TM client */ | |
8366 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
8367 | ilt_cli.start = 0; | |
8368 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
8369 | ilt_cli.client_num = ILT_CLIENT_TM; | |
8370 | ||
8371 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
8372 | } | |
8373 | ||
8374 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 8375 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 8376 | bnx2x_pf_disable(bp); |
523224a3 DK |
8377 | |
8378 | bp->dmae_ready = 0; | |
34f80b04 EG |
8379 | } |
8380 | ||
8381 | static void bnx2x_reset_port(struct bnx2x *bp) | |
8382 | { | |
8383 | int port = BP_PORT(bp); | |
8384 | u32 val; | |
8385 | ||
619c5cb6 VZ |
8386 | /* Reset physical Link */ |
8387 | bnx2x__link_reset(bp); | |
8388 | ||
34f80b04 EG |
8389 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
8390 | ||
8391 | /* Do not rcv packets to BRB */ | |
8392 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
8393 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
8394 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
8395 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
8396 | ||
8397 | /* Configure AEU */ | |
8398 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
8399 | ||
8400 | msleep(100); | |
8401 | /* Check for BRB port occupancy */ | |
8402 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
8403 | if (val) | |
8404 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 8405 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
8406 | |
8407 | /* TODO: Close Doorbell port? */ | |
8408 | } | |
8409 | ||
1191cb83 | 8410 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 8411 | { |
3b603066 | 8412 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 8413 | |
619c5cb6 VZ |
8414 | /* Prepare parameters for function state transitions */ |
8415 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 8416 | |
619c5cb6 VZ |
8417 | func_params.f_obj = &bp->func_obj; |
8418 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 8419 | |
619c5cb6 | 8420 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 8421 | |
619c5cb6 | 8422 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
8423 | } |
8424 | ||
1191cb83 | 8425 | static int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 8426 | { |
3b603066 | 8427 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 8428 | int rc; |
228241eb | 8429 | |
619c5cb6 VZ |
8430 | /* Prepare parameters for function state transitions */ |
8431 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
8432 | func_params.f_obj = &bp->func_obj; | |
8433 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 8434 | |
619c5cb6 VZ |
8435 | /* |
8436 | * Try to stop the function the 'good way'. If fails (in case | |
8437 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
8438 | * not in a debug mode, perform a state transaction in order to | |
8439 | * enable further HW_RESET transaction. | |
8440 | */ | |
8441 | rc = bnx2x_func_state_change(bp, &func_params); | |
8442 | if (rc) { | |
34f80b04 | 8443 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 8444 | return rc; |
34f80b04 | 8445 | #else |
51c1a580 | 8446 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
8447 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
8448 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 8449 | #endif |
228241eb | 8450 | } |
a2fbb9ea | 8451 | |
619c5cb6 VZ |
8452 | return 0; |
8453 | } | |
523224a3 | 8454 | |
619c5cb6 VZ |
8455 | /** |
8456 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
8457 | * | |
8458 | * @bp: driver handle | |
8459 | * @unload_mode: requested function's unload mode | |
8460 | * | |
8461 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
8462 | */ | |
8463 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
8464 | { | |
8465 | u32 reset_code = 0; | |
8466 | int port = BP_PORT(bp); | |
3101c2bc | 8467 | |
619c5cb6 | 8468 | /* Select the UNLOAD request mode */ |
65abd74d YG |
8469 | if (unload_mode == UNLOAD_NORMAL) |
8470 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
8471 | ||
7d0446c2 | 8472 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 8473 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 8474 | |
7d0446c2 | 8475 | else if (bp->wol) { |
65abd74d YG |
8476 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
8477 | u8 *mac_addr = bp->dev->dev_addr; | |
8478 | u32 val; | |
f9977903 DK |
8479 | u16 pmc; |
8480 | ||
65abd74d | 8481 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
8482 | * preserve entry 0 which is used by the PMF |
8483 | */ | |
3395a033 | 8484 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
8485 | |
8486 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
8487 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
8488 | ||
8489 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
8490 | (mac_addr[4] << 8) | mac_addr[5]; | |
8491 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
8492 | ||
f9977903 DK |
8493 | /* Enable the PME and clear the status */ |
8494 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc); | |
8495 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; | |
8496 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc); | |
8497 | ||
65abd74d YG |
8498 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
8499 | ||
8500 | } else | |
8501 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 8502 | |
619c5cb6 VZ |
8503 | /* Send the request to the MCP */ |
8504 | if (!BP_NOMCP(bp)) | |
8505 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
8506 | else { | |
8507 | int path = BP_PATH(bp); | |
8508 | ||
51c1a580 | 8509 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8510 | path, load_count[path][0], load_count[path][1], |
8511 | load_count[path][2]); | |
8512 | load_count[path][0]--; | |
8513 | load_count[path][1 + port]--; | |
51c1a580 | 8514 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8515 | path, load_count[path][0], load_count[path][1], |
8516 | load_count[path][2]); | |
8517 | if (load_count[path][0] == 0) | |
8518 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
8519 | else if (load_count[path][1 + port] == 0) | |
8520 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
8521 | else | |
8522 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
8523 | } | |
8524 | ||
8525 | return reset_code; | |
8526 | } | |
8527 | ||
8528 | /** | |
8529 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
8530 | * | |
8531 | * @bp: driver handle | |
5d07d868 | 8532 | * @keep_link: true iff link should be kept up |
619c5cb6 | 8533 | */ |
5d07d868 | 8534 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) |
619c5cb6 | 8535 | { |
5d07d868 YM |
8536 | u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; |
8537 | ||
619c5cb6 VZ |
8538 | /* Report UNLOAD_DONE to MCP */ |
8539 | if (!BP_NOMCP(bp)) | |
5d07d868 | 8540 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); |
619c5cb6 VZ |
8541 | } |
8542 | ||
1191cb83 | 8543 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
6debea87 DK |
8544 | { |
8545 | int tout = 50; | |
8546 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8547 | ||
8548 | if (!bp->port.pmf) | |
8549 | return 0; | |
8550 | ||
8551 | /* | |
8552 | * (assumption: No Attention from MCP at this stage) | |
8553 | * PMF probably in the middle of TXdisable/enable transaction | |
8554 | * 1. Sync IRS for default SB | |
8555 | * 2. Sync SP queue - this guarantes us that attention handling started | |
8556 | * 3. Wait, that TXdisable/enable transaction completes | |
8557 | * | |
8558 | * 1+2 guranty that if DCBx attention was scheduled it already changed | |
8559 | * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy | |
8560 | * received complettion for the transaction the state is TX_STOPPED. | |
8561 | * State will return to STARTED after completion of TX_STOPPED-->STARTED | |
8562 | * transaction. | |
8563 | */ | |
8564 | ||
8565 | /* make sure default SB ISR is done */ | |
8566 | if (msix) | |
8567 | synchronize_irq(bp->msix_table[0].vector); | |
8568 | else | |
8569 | synchronize_irq(bp->pdev->irq); | |
8570 | ||
8571 | flush_workqueue(bnx2x_wq); | |
8572 | ||
8573 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8574 | BNX2X_F_STATE_STARTED && tout--) | |
8575 | msleep(20); | |
8576 | ||
8577 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8578 | BNX2X_F_STATE_STARTED) { | |
8579 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 8580 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
8581 | return -EBUSY; |
8582 | #else | |
8583 | /* | |
8584 | * Failed to complete the transaction in a "good way" | |
8585 | * Force both transactions with CLR bit | |
8586 | */ | |
3b603066 | 8587 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 8588 | |
51c1a580 MS |
8589 | DP(NETIF_MSG_IFDOWN, |
8590 | "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); | |
6debea87 DK |
8591 | |
8592 | func_params.f_obj = &bp->func_obj; | |
8593 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
8594 | &func_params.ramrod_flags); | |
8595 | ||
8596 | /* STARTED-->TX_ST0PPED */ | |
8597 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
8598 | bnx2x_func_state_change(bp, &func_params); | |
8599 | ||
8600 | /* TX_ST0PPED-->STARTED */ | |
8601 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
8602 | return bnx2x_func_state_change(bp, &func_params); | |
8603 | #endif | |
8604 | } | |
8605 | ||
8606 | return 0; | |
8607 | } | |
8608 | ||
5d07d868 | 8609 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) |
619c5cb6 VZ |
8610 | { |
8611 | int port = BP_PORT(bp); | |
6383c0b3 AE |
8612 | int i, rc = 0; |
8613 | u8 cos; | |
3b603066 | 8614 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
8615 | u32 reset_code; |
8616 | ||
8617 | /* Wait until tx fastpath tasks complete */ | |
8618 | for_each_tx_queue(bp, i) { | |
8619 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
8620 | ||
6383c0b3 | 8621 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 8622 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
619c5cb6 VZ |
8623 | #ifdef BNX2X_STOP_ON_ERROR |
8624 | if (rc) | |
8625 | return; | |
8626 | #endif | |
8627 | } | |
8628 | ||
8629 | /* Give HW time to discard old tx messages */ | |
8630 | usleep_range(1000, 1000); | |
8631 | ||
8632 | /* Clean all ETH MACs */ | |
15192a8c BW |
8633 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
8634 | false); | |
619c5cb6 VZ |
8635 | if (rc < 0) |
8636 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
8637 | ||
8638 | /* Clean up UC list */ | |
15192a8c | 8639 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
619c5cb6 VZ |
8640 | true); |
8641 | if (rc < 0) | |
51c1a580 MS |
8642 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
8643 | rc); | |
619c5cb6 VZ |
8644 | |
8645 | /* Disable LLH */ | |
8646 | if (!CHIP_IS_E1(bp)) | |
8647 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
8648 | ||
8649 | /* Set "drop all" (stop Rx). | |
8650 | * We need to take a netif_addr_lock() here in order to prevent | |
8651 | * a race between the completion code and this code. | |
8652 | */ | |
8653 | netif_addr_lock_bh(bp->dev); | |
8654 | /* Schedule the rx_mode command */ | |
8655 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
8656 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8657 | else | |
8658 | bnx2x_set_storm_rx_mode(bp); | |
8659 | ||
8660 | /* Cleanup multicast configuration */ | |
8661 | rparam.mcast_obj = &bp->mcast_obj; | |
8662 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
8663 | if (rc < 0) | |
8664 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
8665 | ||
8666 | netif_addr_unlock_bh(bp->dev); | |
8667 | ||
f1929b01 | 8668 | bnx2x_iov_chip_cleanup(bp); |
619c5cb6 | 8669 | |
6debea87 DK |
8670 | |
8671 | /* | |
8672 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
8673 | * this function should perform FUNC, PORT or COMMON HW | |
8674 | * reset. | |
8675 | */ | |
8676 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
8677 | ||
8678 | /* | |
8679 | * (assumption: No Attention from MCP at this stage) | |
8680 | * PMF probably in the middle of TXdisable/enable transaction | |
8681 | */ | |
8682 | rc = bnx2x_func_wait_started(bp); | |
8683 | if (rc) { | |
8684 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
8685 | #ifdef BNX2X_STOP_ON_ERROR | |
8686 | return; | |
8687 | #endif | |
8688 | } | |
8689 | ||
34f80b04 | 8690 | /* Close multi and leading connections |
619c5cb6 VZ |
8691 | * Completions for ramrods are collected in a synchronous way |
8692 | */ | |
55c11941 | 8693 | for_each_eth_queue(bp, i) |
619c5cb6 | 8694 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
8695 | #ifdef BNX2X_STOP_ON_ERROR |
8696 | return; | |
8697 | #else | |
228241eb | 8698 | goto unload_error; |
523224a3 | 8699 | #endif |
55c11941 MS |
8700 | |
8701 | if (CNIC_LOADED(bp)) { | |
8702 | for_each_cnic_queue(bp, i) | |
8703 | if (bnx2x_stop_queue(bp, i)) | |
8704 | #ifdef BNX2X_STOP_ON_ERROR | |
8705 | return; | |
8706 | #else | |
8707 | goto unload_error; | |
8708 | #endif | |
8709 | } | |
8710 | ||
619c5cb6 VZ |
8711 | /* If SP settings didn't get completed so far - something |
8712 | * very wrong has happen. | |
8713 | */ | |
8714 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
8715 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 8716 | |
619c5cb6 VZ |
8717 | #ifndef BNX2X_STOP_ON_ERROR |
8718 | unload_error: | |
8719 | #endif | |
523224a3 | 8720 | rc = bnx2x_func_stop(bp); |
da5a662a | 8721 | if (rc) { |
523224a3 | 8722 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 8723 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 8724 | return; |
523224a3 | 8725 | #endif |
34f80b04 | 8726 | } |
a2fbb9ea | 8727 | |
523224a3 DK |
8728 | /* Disable HW interrupts, NAPI */ |
8729 | bnx2x_netif_stop(bp, 1); | |
26614ba5 MS |
8730 | /* Delete all NAPI objects */ |
8731 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
8732 | if (CNIC_LOADED(bp)) |
8733 | bnx2x_del_all_napi_cnic(bp); | |
523224a3 DK |
8734 | |
8735 | /* Release IRQs */ | |
d6214d7a | 8736 | bnx2x_free_irq(bp); |
523224a3 | 8737 | |
a2fbb9ea | 8738 | /* Reset the chip */ |
619c5cb6 VZ |
8739 | rc = bnx2x_reset_hw(bp, reset_code); |
8740 | if (rc) | |
8741 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 8742 | |
356e2385 | 8743 | |
619c5cb6 | 8744 | /* Report UNLOAD_DONE to MCP */ |
5d07d868 | 8745 | bnx2x_send_unload_done(bp, keep_link); |
72fd0718 VZ |
8746 | } |
8747 | ||
9f6c9258 | 8748 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
8749 | { |
8750 | u32 val; | |
8751 | ||
51c1a580 | 8752 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
8753 | |
8754 | if (CHIP_IS_E1(bp)) { | |
8755 | int port = BP_PORT(bp); | |
8756 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
8757 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
8758 | ||
8759 | val = REG_RD(bp, addr); | |
8760 | val &= ~(0x300); | |
8761 | REG_WR(bp, addr, val); | |
619c5cb6 | 8762 | } else { |
72fd0718 VZ |
8763 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
8764 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
8765 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
8766 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
8767 | } | |
8768 | } | |
8769 | ||
72fd0718 VZ |
8770 | /* Close gates #2, #3 and #4: */ |
8771 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
8772 | { | |
c9ee9206 | 8773 | u32 val; |
72fd0718 VZ |
8774 | |
8775 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
8776 | if (!CHIP_IS_E1(bp)) { | |
8777 | /* #4 */ | |
c9ee9206 | 8778 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 8779 | /* #2 */ |
c9ee9206 | 8780 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
8781 | } |
8782 | ||
8783 | /* #3 */ | |
c9ee9206 VZ |
8784 | if (CHIP_IS_E1x(bp)) { |
8785 | /* Prevent interrupts from HC on both ports */ | |
8786 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
8787 | REG_WR(bp, HC_REG_CONFIG_1, | |
8788 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
8789 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
8790 | ||
8791 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
8792 | REG_WR(bp, HC_REG_CONFIG_0, | |
8793 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
8794 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
8795 | } else { | |
8796 | /* Prevent incomming interrupts in IGU */ | |
8797 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | |
8798 | ||
8799 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
8800 | (!close) ? | |
8801 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
8802 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
8803 | } | |
72fd0718 | 8804 | |
51c1a580 | 8805 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
8806 | close ? "closing" : "opening"); |
8807 | mmiowb(); | |
8808 | } | |
8809 | ||
8810 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
8811 | ||
8812 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
8813 | { | |
8814 | /* Do some magic... */ | |
8815 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
8816 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
8817 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
8818 | } | |
8819 | ||
e8920674 DK |
8820 | /** |
8821 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 8822 | * |
e8920674 DK |
8823 | * @bp: driver handle |
8824 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
8825 | */ |
8826 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
8827 | { | |
8828 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
8829 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
8830 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
8831 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
8832 | } | |
8833 | ||
f85582f8 | 8834 | /** |
e8920674 | 8835 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 8836 | * |
e8920674 DK |
8837 | * @bp: driver handle |
8838 | * @magic_val: old value of 'magic' bit. | |
8839 | * | |
8840 | * Takes care of CLP configurations. | |
72fd0718 VZ |
8841 | */ |
8842 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
8843 | { | |
8844 | u32 shmem; | |
8845 | u32 validity_offset; | |
8846 | ||
51c1a580 | 8847 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
8848 | |
8849 | /* Set `magic' bit in order to save MF config */ | |
8850 | if (!CHIP_IS_E1(bp)) | |
8851 | bnx2x_clp_reset_prep(bp, magic_val); | |
8852 | ||
8853 | /* Get shmem offset */ | |
8854 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
c55e771b BW |
8855 | validity_offset = |
8856 | offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); | |
72fd0718 VZ |
8857 | |
8858 | /* Clear validity map flags */ | |
8859 | if (shmem > 0) | |
8860 | REG_WR(bp, shmem + validity_offset, 0); | |
8861 | } | |
8862 | ||
8863 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
8864 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
8865 | ||
e8920674 DK |
8866 | /** |
8867 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 8868 | * |
e8920674 | 8869 | * @bp: driver handle |
72fd0718 | 8870 | */ |
1191cb83 | 8871 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
72fd0718 VZ |
8872 | { |
8873 | /* special handling for emulation and FPGA, | |
8874 | wait 10 times longer */ | |
8875 | if (CHIP_REV_IS_SLOW(bp)) | |
8876 | msleep(MCP_ONE_TIMEOUT*10); | |
8877 | else | |
8878 | msleep(MCP_ONE_TIMEOUT); | |
8879 | } | |
8880 | ||
1b6e2ceb DK |
8881 | /* |
8882 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
8883 | */ | |
8884 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 8885 | { |
1b6e2ceb DK |
8886 | int cnt = 0; |
8887 | u32 val = 0; | |
72fd0718 | 8888 | |
1b6e2ceb DK |
8889 | do { |
8890 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
8891 | if (bp->common.shmem_base) { | |
8892 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
8893 | if (val & SHR_MEM_VALIDITY_MB) | |
8894 | return 0; | |
8895 | } | |
72fd0718 | 8896 | |
1b6e2ceb | 8897 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 8898 | |
1b6e2ceb | 8899 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 8900 | |
1b6e2ceb | 8901 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 8902 | |
1b6e2ceb DK |
8903 | return -ENODEV; |
8904 | } | |
72fd0718 | 8905 | |
1b6e2ceb DK |
8906 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
8907 | { | |
8908 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 8909 | |
72fd0718 VZ |
8910 | /* Restore the `magic' bit value */ |
8911 | if (!CHIP_IS_E1(bp)) | |
8912 | bnx2x_clp_reset_done(bp, magic_val); | |
8913 | ||
8914 | return rc; | |
8915 | } | |
8916 | ||
8917 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
8918 | { | |
8919 | if (!CHIP_IS_E1(bp)) { | |
8920 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
8921 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
8922 | mmiowb(); |
8923 | } | |
8924 | } | |
8925 | ||
8926 | /* | |
8927 | * Reset the whole chip except for: | |
8928 | * - PCIE core | |
8929 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
8930 | * one reset bit) | |
8931 | * - IGU | |
8932 | * - MISC (including AEU) | |
8933 | * - GRC | |
8934 | * - RBCN, RBCP | |
8935 | */ | |
c9ee9206 | 8936 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
8937 | { |
8938 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 8939 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
8940 | |
8941 | /* | |
8942 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
8943 | * (per chip) blocks. | |
8944 | */ | |
8945 | global_bits2 = | |
8946 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
8947 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 8948 | |
c55e771b BW |
8949 | /* Don't reset the following blocks. |
8950 | * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be | |
8951 | * reset, as in 4 port device they might still be owned | |
8952 | * by the MCP (there is only one leader per path). | |
8953 | */ | |
72fd0718 VZ |
8954 | not_reset_mask1 = |
8955 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
8956 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
8957 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
8958 | ||
8959 | not_reset_mask2 = | |
c9ee9206 | 8960 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
8961 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
8962 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
8963 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
8964 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
8965 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
8966 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
8967 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
8968 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
c55e771b BW |
8969 | MISC_REGISTERS_RESET_REG_2_PGLC | |
8970 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
8971 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
8972 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
8973 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
8974 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
8975 | MISC_REGISTERS_RESET_REG_2_UMAC1; | |
72fd0718 | 8976 | |
8736c826 VZ |
8977 | /* |
8978 | * Keep the following blocks in reset: | |
8979 | * - all xxMACs are handled by the bnx2x_link code. | |
8980 | */ | |
8981 | stay_reset2 = | |
8736c826 VZ |
8982 | MISC_REGISTERS_RESET_REG_2_XMAC | |
8983 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
8984 | ||
8985 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
8986 | reset_mask1 = 0xffffffff; |
8987 | ||
8988 | if (CHIP_IS_E1(bp)) | |
8989 | reset_mask2 = 0xffff; | |
8736c826 | 8990 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 8991 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
8992 | else if (CHIP_IS_E2(bp)) |
8993 | reset_mask2 = 0xfffff; | |
8994 | else /* CHIP_IS_E3 */ | |
8995 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
8996 | |
8997 | /* Don't reset global blocks unless we need to */ | |
8998 | if (!global) | |
8999 | reset_mask2 &= ~global_bits2; | |
9000 | ||
9001 | /* | |
9002 | * In case of attention in the QM, we need to reset PXP | |
9003 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
9004 | * because otherwise QM reset would release 'close the gates' shortly | |
9005 | * before resetting the PXP, then the PSWRQ would send a write | |
9006 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
9007 | * read the payload data from PSWWR, but PSWWR would not | |
9008 | * respond. The write queue in PGLUE would stuck, dmae commands | |
9009 | * would not return. Therefore it's important to reset the second | |
9010 | * reset register (containing the | |
9011 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
9012 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
9013 | * bit). | |
9014 | */ | |
72fd0718 VZ |
9015 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
9016 | reset_mask2 & (~not_reset_mask2)); | |
9017 | ||
c9ee9206 VZ |
9018 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
9019 | reset_mask1 & (~not_reset_mask1)); | |
9020 | ||
72fd0718 VZ |
9021 | barrier(); |
9022 | mmiowb(); | |
9023 | ||
8736c826 VZ |
9024 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
9025 | reset_mask2 & (~stay_reset2)); | |
9026 | ||
9027 | barrier(); | |
9028 | mmiowb(); | |
9029 | ||
c9ee9206 | 9030 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
9031 | mmiowb(); |
9032 | } | |
9033 | ||
c9ee9206 VZ |
9034 | /** |
9035 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
9036 | * It should get cleared in no more than 1s. | |
9037 | * | |
9038 | * @bp: driver handle | |
9039 | * | |
9040 | * It should get cleared in no more than 1s. Returns 0 if | |
9041 | * pending writes bit gets cleared. | |
9042 | */ | |
9043 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
9044 | { | |
9045 | u32 cnt = 1000; | |
9046 | u32 pend_bits = 0; | |
9047 | ||
9048 | do { | |
9049 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
9050 | ||
9051 | if (pend_bits == 0) | |
9052 | break; | |
9053 | ||
9054 | usleep_range(1000, 1000); | |
9055 | } while (cnt-- > 0); | |
9056 | ||
9057 | if (cnt <= 0) { | |
9058 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
9059 | pend_bits); | |
9060 | return -EBUSY; | |
9061 | } | |
9062 | ||
9063 | return 0; | |
9064 | } | |
9065 | ||
9066 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
9067 | { |
9068 | int cnt = 1000; | |
9069 | u32 val = 0; | |
9070 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
c55e771b | 9071 | u32 tags_63_32 = 0; |
72fd0718 VZ |
9072 | |
9073 | ||
9074 | /* Empty the Tetris buffer, wait for 1s */ | |
9075 | do { | |
9076 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
9077 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
9078 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
9079 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
9080 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
c55e771b BW |
9081 | if (CHIP_IS_E3(bp)) |
9082 | tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); | |
9083 | ||
72fd0718 VZ |
9084 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && |
9085 | ((port_is_idle_0 & 0x1) == 0x1) && | |
9086 | ((port_is_idle_1 & 0x1) == 0x1) && | |
c55e771b BW |
9087 | (pgl_exp_rom2 == 0xffffffff) && |
9088 | (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) | |
72fd0718 | 9089 | break; |
c9ee9206 | 9090 | usleep_range(1000, 1000); |
72fd0718 VZ |
9091 | } while (cnt-- > 0); |
9092 | ||
9093 | if (cnt <= 0) { | |
51c1a580 MS |
9094 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
9095 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
9096 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
9097 | pgl_exp_rom2); | |
9098 | return -EAGAIN; | |
9099 | } | |
9100 | ||
9101 | barrier(); | |
9102 | ||
9103 | /* Close gates #2, #3 and #4 */ | |
9104 | bnx2x_set_234_gates(bp, true); | |
9105 | ||
c9ee9206 VZ |
9106 | /* Poll for IGU VQs for 57712 and newer chips */ |
9107 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
9108 | return -EAGAIN; | |
9109 | ||
9110 | ||
72fd0718 VZ |
9111 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
9112 | ||
9113 | /* Clear "unprepared" bit */ | |
9114 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
9115 | barrier(); | |
9116 | ||
9117 | /* Make sure all is written to the chip before the reset */ | |
9118 | mmiowb(); | |
9119 | ||
9120 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
9121 | * PSWHST, GRC and PSWRD Tetris buffer. | |
9122 | */ | |
c9ee9206 | 9123 | usleep_range(1000, 1000); |
72fd0718 VZ |
9124 | |
9125 | /* Prepare to chip reset: */ | |
9126 | /* MCP */ | |
c9ee9206 VZ |
9127 | if (global) |
9128 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
9129 | |
9130 | /* PXP */ | |
9131 | bnx2x_pxp_prep(bp); | |
9132 | barrier(); | |
9133 | ||
9134 | /* reset the chip */ | |
c9ee9206 | 9135 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
9136 | barrier(); |
9137 | ||
9138 | /* Recover after reset: */ | |
9139 | /* MCP */ | |
c9ee9206 | 9140 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
9141 | return -EAGAIN; |
9142 | ||
c9ee9206 VZ |
9143 | /* TBD: Add resetting the NO_MCP mode DB here */ |
9144 | ||
72fd0718 VZ |
9145 | /* Open the gates #2, #3 and #4 */ |
9146 | bnx2x_set_234_gates(bp, false); | |
9147 | ||
9148 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
9149 | * reset state, re-enable attentions. */ | |
9150 | ||
a2fbb9ea ET |
9151 | return 0; |
9152 | } | |
9153 | ||
910cc727 | 9154 | static int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
9155 | { |
9156 | int rc = 0; | |
c9ee9206 | 9157 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
9158 | u32 load_code; |
9159 | ||
9160 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
9161 | * driver is owner of the HW | |
9162 | */ | |
9163 | if (!global && !BP_NOMCP(bp)) { | |
5d07d868 YM |
9164 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, |
9165 | DRV_MSG_CODE_LOAD_REQ_WITH_LFA); | |
95c6c616 AE |
9166 | if (!load_code) { |
9167 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9168 | rc = -EAGAIN; | |
9169 | goto exit_leader_reset; | |
9170 | } | |
9171 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
9172 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
9173 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
9174 | rc = -EAGAIN; | |
9175 | goto exit_leader_reset2; | |
9176 | } | |
9177 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
9178 | if (!load_code) { | |
9179 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9180 | rc = -EAGAIN; | |
9181 | goto exit_leader_reset2; | |
9182 | } | |
9183 | } | |
c9ee9206 | 9184 | |
72fd0718 | 9185 | /* Try to recover after the failure */ |
c9ee9206 | 9186 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
9187 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
9188 | BP_PATH(bp)); | |
72fd0718 | 9189 | rc = -EAGAIN; |
95c6c616 | 9190 | goto exit_leader_reset2; |
72fd0718 VZ |
9191 | } |
9192 | ||
c9ee9206 VZ |
9193 | /* |
9194 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
9195 | * state. | |
9196 | */ | |
72fd0718 | 9197 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
9198 | if (global) |
9199 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 9200 | |
95c6c616 AE |
9201 | exit_leader_reset2: |
9202 | /* unload "fake driver" if it was loaded */ | |
9203 | if (!global && !BP_NOMCP(bp)) { | |
9204 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
9205 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9206 | } | |
72fd0718 VZ |
9207 | exit_leader_reset: |
9208 | bp->is_leader = 0; | |
c9ee9206 VZ |
9209 | bnx2x_release_leader_lock(bp); |
9210 | smp_mb(); | |
72fd0718 VZ |
9211 | return rc; |
9212 | } | |
9213 | ||
1191cb83 | 9214 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
c9ee9206 VZ |
9215 | { |
9216 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
9217 | ||
9218 | /* Disconnect this device */ | |
9219 | netif_device_detach(bp->dev); | |
9220 | ||
9221 | /* | |
9222 | * Block ifup for all function on this engine until "process kill" | |
9223 | * or power cycle. | |
9224 | */ | |
9225 | bnx2x_set_reset_in_progress(bp); | |
9226 | ||
9227 | /* Shut down the power */ | |
9228 | bnx2x_set_power_state(bp, PCI_D3hot); | |
9229 | ||
9230 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
9231 | ||
9232 | smp_mb(); | |
9233 | } | |
9234 | ||
9235 | /* | |
9236 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 9237 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
9238 | * will never be called when netif_running(bp->dev) is false. |
9239 | */ | |
9240 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
9241 | { | |
c9ee9206 | 9242 | bool global = false; |
7a752993 | 9243 | u32 error_recovered, error_unrecovered; |
95c6c616 | 9244 | bool is_parity; |
c9ee9206 | 9245 | |
72fd0718 VZ |
9246 | DP(NETIF_MSG_HW, "Handling parity\n"); |
9247 | while (1) { | |
9248 | switch (bp->recovery_state) { | |
9249 | case BNX2X_RECOVERY_INIT: | |
9250 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
9251 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
9252 | WARN_ON(!is_parity); | |
c9ee9206 | 9253 | |
72fd0718 | 9254 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
9255 | if (bnx2x_trylock_leader_lock(bp)) { |
9256 | bnx2x_set_reset_in_progress(bp); | |
9257 | /* | |
9258 | * Check if there is a global attention and if | |
9259 | * there was a global attention, set the global | |
9260 | * reset bit. | |
9261 | */ | |
9262 | ||
9263 | if (global) | |
9264 | bnx2x_set_reset_global(bp); | |
9265 | ||
72fd0718 | 9266 | bp->is_leader = 1; |
c9ee9206 | 9267 | } |
72fd0718 VZ |
9268 | |
9269 | /* Stop the driver */ | |
9270 | /* If interface has been removed - break */ | |
5d07d868 | 9271 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) |
72fd0718 VZ |
9272 | return; |
9273 | ||
9274 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 9275 | |
c9ee9206 VZ |
9276 | /* Ensure "is_leader", MCP command sequence and |
9277 | * "recovery_state" update values are seen on other | |
9278 | * CPUs. | |
72fd0718 | 9279 | */ |
c9ee9206 | 9280 | smp_mb(); |
72fd0718 VZ |
9281 | break; |
9282 | ||
9283 | case BNX2X_RECOVERY_WAIT: | |
9284 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
9285 | if (bp->is_leader) { | |
c9ee9206 | 9286 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
9287 | bool other_load_status = |
9288 | bnx2x_get_load_status(bp, other_engine); | |
9289 | bool load_status = | |
9290 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
9291 | global = bnx2x_reset_is_global(bp); |
9292 | ||
9293 | /* | |
9294 | * In case of a parity in a global block, let | |
9295 | * the first leader that performs a | |
9296 | * leader_reset() reset the global blocks in | |
9297 | * order to clear global attentions. Otherwise | |
9298 | * the the gates will remain closed for that | |
9299 | * engine. | |
9300 | */ | |
889b9af3 AE |
9301 | if (load_status || |
9302 | (global && other_load_status)) { | |
72fd0718 VZ |
9303 | /* Wait until all other functions get |
9304 | * down. | |
9305 | */ | |
7be08a72 | 9306 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9307 | HZ/10); |
9308 | return; | |
9309 | } else { | |
9310 | /* If all other functions got down - | |
9311 | * try to bring the chip back to | |
9312 | * normal. In any case it's an exit | |
9313 | * point for a leader. | |
9314 | */ | |
c9ee9206 VZ |
9315 | if (bnx2x_leader_reset(bp)) { |
9316 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
9317 | return; |
9318 | } | |
9319 | ||
c9ee9206 VZ |
9320 | /* If we are here, means that the |
9321 | * leader has succeeded and doesn't | |
9322 | * want to be a leader any more. Try | |
9323 | * to continue as a none-leader. | |
9324 | */ | |
9325 | break; | |
72fd0718 VZ |
9326 | } |
9327 | } else { /* non-leader */ | |
c9ee9206 | 9328 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
9329 | /* Try to get a LEADER_LOCK HW lock as |
9330 | * long as a former leader may have | |
9331 | * been unloaded by the user or | |
9332 | * released a leadership by another | |
9333 | * reason. | |
9334 | */ | |
c9ee9206 | 9335 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
9336 | /* I'm a leader now! Restart a |
9337 | * switch case. | |
9338 | */ | |
9339 | bp->is_leader = 1; | |
9340 | break; | |
9341 | } | |
9342 | ||
7be08a72 | 9343 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9344 | HZ/10); |
9345 | return; | |
9346 | ||
c9ee9206 VZ |
9347 | } else { |
9348 | /* | |
9349 | * If there was a global attention, wait | |
9350 | * for it to be cleared. | |
9351 | */ | |
9352 | if (bnx2x_reset_is_global(bp)) { | |
9353 | schedule_delayed_work( | |
7be08a72 AE |
9354 | &bp->sp_rtnl_task, |
9355 | HZ/10); | |
c9ee9206 VZ |
9356 | return; |
9357 | } | |
9358 | ||
7a752993 AE |
9359 | error_recovered = |
9360 | bp->eth_stats.recoverable_error; | |
9361 | error_unrecovered = | |
9362 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
9363 | bp->recovery_state = |
9364 | BNX2X_RECOVERY_NIC_LOADING; | |
9365 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 9366 | error_unrecovered++; |
95c6c616 | 9367 | netdev_err(bp->dev, |
51c1a580 | 9368 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
9369 | /* Disconnect this device */ |
9370 | netif_device_detach(bp->dev); | |
9371 | /* Shut down the power */ | |
9372 | bnx2x_set_power_state( | |
9373 | bp, PCI_D3hot); | |
9374 | smp_mb(); | |
9375 | } else { | |
c9ee9206 VZ |
9376 | bp->recovery_state = |
9377 | BNX2X_RECOVERY_DONE; | |
7a752993 | 9378 | error_recovered++; |
c9ee9206 VZ |
9379 | smp_mb(); |
9380 | } | |
7a752993 AE |
9381 | bp->eth_stats.recoverable_error = |
9382 | error_recovered; | |
9383 | bp->eth_stats.unrecoverable_error = | |
9384 | error_unrecovered; | |
c9ee9206 | 9385 | |
72fd0718 VZ |
9386 | return; |
9387 | } | |
9388 | } | |
9389 | default: | |
9390 | return; | |
9391 | } | |
9392 | } | |
9393 | } | |
9394 | ||
56ad3152 MS |
9395 | static int bnx2x_close(struct net_device *dev); |
9396 | ||
72fd0718 VZ |
9397 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
9398 | * scheduled on a general queue in order to prevent a dead lock. | |
9399 | */ | |
7be08a72 | 9400 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 9401 | { |
7be08a72 | 9402 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
9403 | |
9404 | rtnl_lock(); | |
9405 | ||
8395be5e AE |
9406 | if (!netif_running(bp->dev)) { |
9407 | rtnl_unlock(); | |
9408 | return; | |
9409 | } | |
7be08a72 AE |
9410 | |
9411 | /* if stop on error is defined no recovery flows should be executed */ | |
9412 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 9413 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
7be08a72 | 9414 | "you will need to reboot when done\n"); |
b1fb8740 | 9415 | goto sp_rtnl_not_reset; |
7be08a72 | 9416 | #endif |
34f80b04 | 9417 | |
7be08a72 AE |
9418 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
9419 | /* | |
b1fb8740 VZ |
9420 | * Clear all pending SP commands as we are going to reset the |
9421 | * function anyway. | |
7be08a72 | 9422 | */ |
b1fb8740 VZ |
9423 | bp->sp_rtnl_state = 0; |
9424 | smp_mb(); | |
9425 | ||
72fd0718 | 9426 | bnx2x_parity_recover(bp); |
b1fb8740 | 9427 | |
8395be5e AE |
9428 | rtnl_unlock(); |
9429 | return; | |
b1fb8740 VZ |
9430 | } |
9431 | ||
9432 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
9433 | /* | |
9434 | * Clear all pending SP commands as we are going to reset the | |
9435 | * function anyway. | |
9436 | */ | |
9437 | bp->sp_rtnl_state = 0; | |
9438 | smp_mb(); | |
9439 | ||
5d07d868 | 9440 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
72fd0718 | 9441 | bnx2x_nic_load(bp, LOAD_NORMAL); |
b1fb8740 | 9442 | |
8395be5e AE |
9443 | rtnl_unlock(); |
9444 | return; | |
72fd0718 | 9445 | } |
b1fb8740 VZ |
9446 | #ifdef BNX2X_STOP_ON_ERROR |
9447 | sp_rtnl_not_reset: | |
9448 | #endif | |
9449 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
9450 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
9451 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
9452 | bnx2x_after_function_update(bp); | |
8304859a AE |
9453 | /* |
9454 | * in case of fan failure we need to reset id if the "stop on error" | |
9455 | * debug flag is set, since we trying to prevent permanent overheating | |
9456 | * damage | |
9457 | */ | |
9458 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 9459 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
9460 | netif_device_detach(bp->dev); |
9461 | bnx2x_close(bp->dev); | |
8395be5e AE |
9462 | rtnl_unlock(); |
9463 | return; | |
8304859a AE |
9464 | } |
9465 | ||
381ac16b AE |
9466 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { |
9467 | DP(BNX2X_MSG_SP, | |
9468 | "sending set mcast vf pf channel message from rtnl sp-task\n"); | |
9469 | bnx2x_vfpf_set_mcast(bp->dev); | |
9470 | } | |
9471 | ||
9472 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, | |
9473 | &bp->sp_rtnl_state)) { | |
9474 | DP(BNX2X_MSG_SP, | |
9475 | "sending set storm rx mode vf pf channel message from rtnl sp-task\n"); | |
9476 | bnx2x_vfpf_storm_rx_mode(bp); | |
9477 | } | |
9478 | ||
8395be5e AE |
9479 | /* work which needs rtnl lock not-taken (as it takes the lock itself and |
9480 | * can be called from other contexts as well) | |
9481 | */ | |
34f80b04 | 9482 | rtnl_unlock(); |
8395be5e | 9483 | |
6411280a | 9484 | /* enable SR-IOV if applicable */ |
8395be5e | 9485 | if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, |
6411280a AE |
9486 | &bp->sp_rtnl_state)) |
9487 | bnx2x_enable_sriov(bp); | |
34f80b04 EG |
9488 | } |
9489 | ||
3deb8167 YR |
9490 | static void bnx2x_period_task(struct work_struct *work) |
9491 | { | |
9492 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
9493 | ||
9494 | if (!netif_running(bp->dev)) | |
9495 | goto period_task_exit; | |
9496 | ||
9497 | if (CHIP_REV_IS_SLOW(bp)) { | |
9498 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
9499 | goto period_task_exit; | |
9500 | } | |
9501 | ||
9502 | bnx2x_acquire_phy_lock(bp); | |
9503 | /* | |
9504 | * The barrier is needed to ensure the ordering between the writing to | |
9505 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
9506 | * the reading here. | |
9507 | */ | |
9508 | smp_mb(); | |
9509 | if (bp->port.pmf) { | |
9510 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
9511 | ||
9512 | /* Re-queue task in 1 sec */ | |
9513 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
9514 | } | |
9515 | ||
9516 | bnx2x_release_phy_lock(bp); | |
9517 | period_task_exit: | |
9518 | return; | |
9519 | } | |
9520 | ||
a2fbb9ea ET |
9521 | /* |
9522 | * Init service functions | |
9523 | */ | |
9524 | ||
b56e9670 | 9525 | u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
9526 | { |
9527 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
9528 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
9529 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
9530 | } |
9531 | ||
f2e0899f | 9532 | static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp) |
f1ef27ef | 9533 | { |
f2e0899f | 9534 | u32 reg = bnx2x_get_pretend_reg(bp); |
f1ef27ef EG |
9535 | |
9536 | /* Flush all outstanding writes */ | |
9537 | mmiowb(); | |
9538 | ||
9539 | /* Pretend to be function 0 */ | |
9540 | REG_WR(bp, reg, 0); | |
f2e0899f | 9541 | REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */ |
f1ef27ef EG |
9542 | |
9543 | /* From now we are in the "like-E1" mode */ | |
9544 | bnx2x_int_disable(bp); | |
9545 | ||
9546 | /* Flush all outstanding writes */ | |
9547 | mmiowb(); | |
9548 | ||
f2e0899f DK |
9549 | /* Restore the original function */ |
9550 | REG_WR(bp, reg, BP_ABS_FUNC(bp)); | |
9551 | REG_RD(bp, reg); | |
f1ef27ef EG |
9552 | } |
9553 | ||
f2e0899f | 9554 | static inline void bnx2x_undi_int_disable(struct bnx2x *bp) |
f1ef27ef | 9555 | { |
f2e0899f | 9556 | if (CHIP_IS_E1(bp)) |
f1ef27ef | 9557 | bnx2x_int_disable(bp); |
f2e0899f DK |
9558 | else |
9559 | bnx2x_undi_int_disable_e1h(bp); | |
f1ef27ef EG |
9560 | } |
9561 | ||
1ef1d45a BW |
9562 | static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, |
9563 | struct bnx2x_mac_vals *vals) | |
34f80b04 | 9564 | { |
452427b0 YM |
9565 | u32 val, base_addr, offset, mask, reset_reg; |
9566 | bool mac_stopped = false; | |
9567 | u8 port = BP_PORT(bp); | |
34f80b04 | 9568 | |
1ef1d45a BW |
9569 | /* reset addresses as they also mark which values were changed */ |
9570 | vals->bmac_addr = 0; | |
9571 | vals->umac_addr = 0; | |
9572 | vals->xmac_addr = 0; | |
9573 | vals->emac_addr = 0; | |
9574 | ||
452427b0 | 9575 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 9576 | |
452427b0 YM |
9577 | if (!CHIP_IS_E3(bp)) { |
9578 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
9579 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
9580 | if ((mask & reset_reg) && val) { | |
9581 | u32 wb_data[2]; | |
9582 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
9583 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
9584 | : NIG_REG_INGRESS_BMAC0_MEM; | |
9585 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
9586 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 9587 | |
452427b0 YM |
9588 | /* |
9589 | * use rd/wr since we cannot use dmae. This is safe | |
9590 | * since MCP won't access the bus due to the request | |
9591 | * to unload, and no function on the path can be | |
9592 | * loaded at this time. | |
9593 | */ | |
9594 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
9595 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
1ef1d45a BW |
9596 | vals->bmac_addr = base_addr + offset; |
9597 | vals->bmac_val[0] = wb_data[0]; | |
9598 | vals->bmac_val[1] = wb_data[1]; | |
452427b0 | 9599 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
1ef1d45a BW |
9600 | REG_WR(bp, vals->bmac_addr, wb_data[0]); |
9601 | REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); | |
452427b0 YM |
9602 | |
9603 | } | |
9604 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
1ef1d45a BW |
9605 | vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; |
9606 | vals->emac_val = REG_RD(bp, vals->emac_addr); | |
9607 | REG_WR(bp, vals->emac_addr, 0); | |
452427b0 YM |
9608 | mac_stopped = true; |
9609 | } else { | |
9610 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
9611 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
9612 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
9613 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
9614 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9615 | val & ~(1 << 1)); | |
9616 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9617 | val | (1 << 1)); | |
1ef1d45a BW |
9618 | vals->xmac_addr = base_addr + XMAC_REG_CTRL; |
9619 | vals->xmac_val = REG_RD(bp, vals->xmac_addr); | |
9620 | REG_WR(bp, vals->xmac_addr, 0); | |
452427b0 YM |
9621 | mac_stopped = true; |
9622 | } | |
9623 | mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
9624 | if (mask & reset_reg) { | |
9625 | BNX2X_DEV_INFO("Disable umac Rx\n"); | |
9626 | base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1ef1d45a BW |
9627 | vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG; |
9628 | vals->umac_val = REG_RD(bp, vals->umac_addr); | |
9629 | REG_WR(bp, vals->umac_addr, 0); | |
452427b0 YM |
9630 | mac_stopped = true; |
9631 | } | |
9632 | } | |
9633 | ||
9634 | if (mac_stopped) | |
9635 | msleep(20); | |
9636 | ||
9637 | } | |
9638 | ||
9639 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
9640 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) | |
9641 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
9642 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
9643 | ||
1dd06ae8 | 9644 | static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc) |
452427b0 YM |
9645 | { |
9646 | u16 rcq, bd; | |
9647 | u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); | |
9648 | ||
9649 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; | |
9650 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
9651 | ||
9652 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
9653 | REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); | |
9654 | ||
9655 | BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", | |
9656 | port, bd, rcq); | |
9657 | } | |
9658 | ||
0329aba1 | 9659 | static int bnx2x_prev_mcp_done(struct bnx2x *bp) |
452427b0 | 9660 | { |
5d07d868 YM |
9661 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, |
9662 | DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); | |
452427b0 YM |
9663 | if (!rc) { |
9664 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9665 | return -EBUSY; | |
9666 | } | |
9667 | ||
9668 | return 0; | |
9669 | } | |
9670 | ||
c63da990 BW |
9671 | static struct bnx2x_prev_path_list * |
9672 | bnx2x_prev_path_get_entry(struct bnx2x *bp) | |
9673 | { | |
9674 | struct bnx2x_prev_path_list *tmp_list; | |
9675 | ||
9676 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) | |
9677 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
9678 | bp->pdev->bus->number == tmp_list->bus && | |
9679 | BP_PATH(bp) == tmp_list->path) | |
9680 | return tmp_list; | |
9681 | ||
9682 | return NULL; | |
9683 | } | |
9684 | ||
0329aba1 | 9685 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) |
452427b0 YM |
9686 | { |
9687 | struct bnx2x_prev_path_list *tmp_list; | |
9688 | int rc = false; | |
9689 | ||
9690 | if (down_trylock(&bnx2x_prev_sem)) | |
9691 | return false; | |
9692 | ||
9693 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) { | |
9694 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
9695 | bp->pdev->bus->number == tmp_list->bus && | |
9696 | BP_PATH(bp) == tmp_list->path) { | |
9697 | rc = true; | |
9698 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
9699 | BP_PATH(bp)); | |
9700 | break; | |
9701 | } | |
9702 | } | |
9703 | ||
9704 | up(&bnx2x_prev_sem); | |
9705 | ||
9706 | return rc; | |
9707 | } | |
9708 | ||
c63da990 | 9709 | static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) |
452427b0 YM |
9710 | { |
9711 | struct bnx2x_prev_path_list *tmp_list; | |
9712 | int rc; | |
9713 | ||
ea4b3857 | 9714 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); |
452427b0 YM |
9715 | if (!tmp_list) { |
9716 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
9717 | return -ENOMEM; | |
9718 | } | |
9719 | ||
9720 | tmp_list->bus = bp->pdev->bus->number; | |
9721 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
9722 | tmp_list->path = BP_PATH(bp); | |
c63da990 | 9723 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; |
452427b0 YM |
9724 | |
9725 | rc = down_interruptible(&bnx2x_prev_sem); | |
9726 | if (rc) { | |
9727 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9728 | kfree(tmp_list); | |
9729 | } else { | |
9730 | BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n", | |
9731 | BP_PATH(bp)); | |
9732 | list_add(&tmp_list->list, &bnx2x_prev_list); | |
9733 | up(&bnx2x_prev_sem); | |
9734 | } | |
9735 | ||
9736 | return rc; | |
9737 | } | |
9738 | ||
0329aba1 | 9739 | static int bnx2x_do_flr(struct bnx2x *bp) |
452427b0 | 9740 | { |
2a80eebc | 9741 | int i; |
452427b0 YM |
9742 | u16 status; |
9743 | struct pci_dev *dev = bp->pdev; | |
9744 | ||
8eee694c YM |
9745 | |
9746 | if (CHIP_IS_E1x(bp)) { | |
9747 | BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); | |
9748 | return -EINVAL; | |
9749 | } | |
9750 | ||
9751 | /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ | |
9752 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
9753 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
9754 | bp->common.bc_ver); | |
9755 | return -EINVAL; | |
9756 | } | |
452427b0 | 9757 | |
452427b0 YM |
9758 | /* Wait for Transaction Pending bit clean */ |
9759 | for (i = 0; i < 4; i++) { | |
9760 | if (i) | |
9761 | msleep((1 << (i - 1)) * 100); | |
9762 | ||
2a80eebc | 9763 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
452427b0 YM |
9764 | if (!(status & PCI_EXP_DEVSTA_TRPND)) |
9765 | goto clear; | |
9766 | } | |
9767 | ||
9768 | dev_err(&dev->dev, | |
9769 | "transaction is not cleared; proceeding with reset anyway\n"); | |
9770 | ||
9771 | clear: | |
452427b0 | 9772 | |
8eee694c | 9773 | BNX2X_DEV_INFO("Initiating FLR\n"); |
452427b0 YM |
9774 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); |
9775 | ||
9776 | return 0; | |
9777 | } | |
9778 | ||
0329aba1 | 9779 | static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) |
452427b0 YM |
9780 | { |
9781 | int rc; | |
9782 | ||
9783 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
9784 | ||
9785 | /* Test if previous unload process was already finished for this path */ | |
9786 | if (bnx2x_prev_is_path_marked(bp)) | |
9787 | return bnx2x_prev_mcp_done(bp); | |
9788 | ||
9789 | /* If function has FLR capabilities, and existing FW version matches | |
9790 | * the one required, then FLR will be sufficient to clean any residue | |
9791 | * left by previous driver | |
9792 | */ | |
ad5afc89 | 9793 | rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION); |
8eee694c YM |
9794 | |
9795 | if (!rc) { | |
9796 | /* fw version is good */ | |
9797 | BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); | |
9798 | rc = bnx2x_do_flr(bp); | |
9799 | } | |
9800 | ||
9801 | if (!rc) { | |
9802 | /* FLR was performed */ | |
9803 | BNX2X_DEV_INFO("FLR successful\n"); | |
9804 | return 0; | |
9805 | } | |
9806 | ||
9807 | BNX2X_DEV_INFO("Could not FLR\n"); | |
452427b0 YM |
9808 | |
9809 | /* Close the MCP request, return failure*/ | |
9810 | rc = bnx2x_prev_mcp_done(bp); | |
9811 | if (!rc) | |
9812 | rc = BNX2X_PREV_WAIT_NEEDED; | |
9813 | ||
9814 | return rc; | |
9815 | } | |
9816 | ||
0329aba1 | 9817 | static int bnx2x_prev_unload_common(struct bnx2x *bp) |
452427b0 YM |
9818 | { |
9819 | u32 reset_reg, tmp_reg = 0, rc; | |
c63da990 | 9820 | bool prev_undi = false; |
1ef1d45a BW |
9821 | struct bnx2x_mac_vals mac_vals; |
9822 | ||
452427b0 YM |
9823 | /* It is possible a previous function received 'common' answer, |
9824 | * but hasn't loaded yet, therefore creating a scenario of | |
9825 | * multiple functions receiving 'common' on the same path. | |
9826 | */ | |
9827 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
9828 | ||
1ef1d45a BW |
9829 | memset(&mac_vals, 0, sizeof(mac_vals)); |
9830 | ||
452427b0 YM |
9831 | if (bnx2x_prev_is_path_marked(bp)) |
9832 | return bnx2x_prev_mcp_done(bp); | |
9833 | ||
9834 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
9835 | ||
9836 | /* Reset should be performed after BRB is emptied */ | |
9837 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
9838 | u32 timer_count = 1000; | |
452427b0 YM |
9839 | |
9840 | /* Close the MAC Rx to prevent BRB from filling up */ | |
1ef1d45a BW |
9841 | bnx2x_prev_unload_close_mac(bp, &mac_vals); |
9842 | ||
9843 | /* close LLH filters towards the BRB */ | |
9844 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
452427b0 YM |
9845 | |
9846 | /* Check if the UNDI driver was previously loaded | |
34f80b04 EG |
9847 | * UNDI driver initializes CID offset for normal bell to 0x7 |
9848 | */ | |
452427b0 YM |
9849 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); |
9850 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { | |
9851 | tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); | |
9852 | if (tmp_reg == 0x7) { | |
9853 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
9854 | prev_undi = true; | |
9855 | /* clear the UNDI indication */ | |
9856 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
a74801c5 YM |
9857 | /* clear possible idle check errors */ |
9858 | REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); | |
34f80b04 | 9859 | } |
452427b0 YM |
9860 | } |
9861 | /* wait until BRB is empty */ | |
9862 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
9863 | while (timer_count) { | |
9864 | u32 prev_brb = tmp_reg; | |
34f80b04 | 9865 | |
452427b0 YM |
9866 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
9867 | if (!tmp_reg) | |
9868 | break; | |
619c5cb6 | 9869 | |
452427b0 | 9870 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 9871 | |
452427b0 YM |
9872 | /* reset timer as long as BRB actually gets emptied */ |
9873 | if (prev_brb > tmp_reg) | |
9874 | timer_count = 1000; | |
9875 | else | |
9876 | timer_count--; | |
da5a662a | 9877 | |
452427b0 YM |
9878 | /* If UNDI resides in memory, manually increment it */ |
9879 | if (prev_undi) | |
9880 | bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); | |
da5a662a | 9881 | |
452427b0 | 9882 | udelay(10); |
7a06a122 | 9883 | } |
452427b0 YM |
9884 | |
9885 | if (!timer_count) | |
9886 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
9887 | ||
34f80b04 | 9888 | } |
f16da43b | 9889 | |
452427b0 YM |
9890 | /* No packets are in the pipeline, path is ready for reset */ |
9891 | bnx2x_reset_common(bp); | |
9892 | ||
1ef1d45a BW |
9893 | if (mac_vals.xmac_addr) |
9894 | REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); | |
9895 | if (mac_vals.umac_addr) | |
9896 | REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val); | |
9897 | if (mac_vals.emac_addr) | |
9898 | REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); | |
9899 | if (mac_vals.bmac_addr) { | |
9900 | REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); | |
9901 | REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); | |
9902 | } | |
9903 | ||
c63da990 | 9904 | rc = bnx2x_prev_mark_path(bp, prev_undi); |
452427b0 YM |
9905 | if (rc) { |
9906 | bnx2x_prev_mcp_done(bp); | |
9907 | return rc; | |
9908 | } | |
9909 | ||
9910 | return bnx2x_prev_mcp_done(bp); | |
9911 | } | |
9912 | ||
24f06716 AE |
9913 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
9914 | * and boot began, or when kdump kernel was loaded. Either case would invalidate | |
9915 | * the addresses of the transaction, resulting in was-error bit set in the pci | |
9916 | * causing all hw-to-host pcie transactions to timeout. If this happened we want | |
9917 | * to clear the interrupt which detected this from the pglueb and the was done | |
9918 | * bit | |
9919 | */ | |
0329aba1 | 9920 | static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp) |
24f06716 | 9921 | { |
4a25417c AE |
9922 | if (!CHIP_IS_E1x(bp)) { |
9923 | u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS); | |
9924 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { | |
9925 | BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing"); | |
9926 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, | |
9927 | 1 << BP_FUNC(bp)); | |
9928 | } | |
24f06716 AE |
9929 | } |
9930 | } | |
9931 | ||
0329aba1 | 9932 | static int bnx2x_prev_unload(struct bnx2x *bp) |
452427b0 YM |
9933 | { |
9934 | int time_counter = 10; | |
9935 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
c63da990 | 9936 | struct bnx2x_prev_path_list *prev_list; |
452427b0 YM |
9937 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); |
9938 | ||
24f06716 AE |
9939 | /* clear hw from errors which may have resulted from an interrupted |
9940 | * dmae transaction. | |
9941 | */ | |
9942 | bnx2x_prev_interrupted_dmae(bp); | |
9943 | ||
9944 | /* Release previously held locks */ | |
452427b0 YM |
9945 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
9946 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
9947 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
9948 | ||
9949 | hw_lock_val = (REG_RD(bp, hw_lock_reg)); | |
9950 | if (hw_lock_val) { | |
9951 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
9952 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
9953 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
9954 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
9955 | } | |
9956 | ||
9957 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
9958 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
9959 | } else | |
9960 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
9961 | ||
9962 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
9963 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
9964 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); | |
9965 | } | |
9966 | ||
9967 | ||
9968 | do { | |
9969 | /* Lock MCP using an unload request */ | |
9970 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
9971 | if (!fw) { | |
9972 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9973 | rc = -EBUSY; | |
9974 | break; | |
9975 | } | |
9976 | ||
9977 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { | |
9978 | rc = bnx2x_prev_unload_common(bp); | |
9979 | break; | |
9980 | } | |
9981 | ||
9982 | /* non-common reply from MCP night require looping */ | |
9983 | rc = bnx2x_prev_unload_uncommon(bp); | |
9984 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
9985 | break; | |
9986 | ||
9987 | msleep(20); | |
9988 | } while (--time_counter); | |
9989 | ||
9990 | if (!time_counter || rc) { | |
9991 | BNX2X_ERR("Failed unloading previous driver, aborting\n"); | |
9992 | rc = -EBUSY; | |
9993 | } | |
9994 | ||
c63da990 BW |
9995 | /* Mark function if its port was used to boot from SAN */ |
9996 | prev_list = bnx2x_prev_path_get_entry(bp); | |
9997 | if (prev_list && (prev_list->undi & (1 << BP_PORT(bp)))) | |
9998 | bp->link_params.feature_config_flags |= | |
9999 | FEATURE_CONFIG_BOOT_FROM_SAN; | |
10000 | ||
452427b0 YM |
10001 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); |
10002 | ||
10003 | return rc; | |
34f80b04 EG |
10004 | } |
10005 | ||
0329aba1 | 10006 | static void bnx2x_get_common_hwinfo(struct bnx2x *bp) |
34f80b04 | 10007 | { |
1d187b34 | 10008 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 10009 | u16 pmc; |
34f80b04 EG |
10010 | |
10011 | /* Get the chip revision id and number. */ | |
10012 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
10013 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
10014 | id = ((val & 0xffff) << 16); | |
10015 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
10016 | id |= ((val & 0xf) << 12); | |
10017 | val = REG_RD(bp, MISC_REG_CHIP_METAL); | |
10018 | id |= ((val & 0xff) << 4); | |
5a40e08e | 10019 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
10020 | id |= (val & 0xf); |
10021 | bp->common.chip_id = id; | |
523224a3 | 10022 | |
7e8e02df BW |
10023 | /* force 57811 according to MISC register */ |
10024 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
10025 | if (CHIP_IS_57810(bp)) | |
10026 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
10027 | (bp->common.chip_id & 0x0000FFFF); | |
10028 | else if (CHIP_IS_57810_MF(bp)) | |
10029 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
10030 | (bp->common.chip_id & 0x0000FFFF); | |
10031 | bp->common.chip_id |= 0x1; | |
10032 | } | |
10033 | ||
523224a3 DK |
10034 | /* Set doorbell size */ |
10035 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
10036 | ||
619c5cb6 | 10037 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
10038 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
10039 | if ((val & 1) == 0) | |
10040 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
10041 | else | |
10042 | val = (val >> 1) & 1; | |
10043 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
10044 | "2_PORT_MODE"); | |
10045 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
10046 | CHIP_2_PORT_MODE; | |
10047 | ||
10048 | if (CHIP_MODE_IS_4_PORT(bp)) | |
10049 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
10050 | else | |
10051 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
10052 | } else { | |
10053 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
10054 | bp->pfid = bp->pf_num; /* 0..7 */ | |
10055 | } | |
10056 | ||
51c1a580 MS |
10057 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
10058 | ||
f2e0899f DK |
10059 | bp->link_params.chip_id = bp->common.chip_id; |
10060 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 10061 | |
1c06328c EG |
10062 | val = (REG_RD(bp, 0x2874) & 0x55); |
10063 | if ((bp->common.chip_id & 0x1) || | |
10064 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
10065 | bp->flags |= ONE_PORT_FLAG; | |
10066 | BNX2X_DEV_INFO("single port device\n"); | |
10067 | } | |
10068 | ||
34f80b04 | 10069 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 10070 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
10071 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
10072 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
10073 | bp->common.flash_size, bp->common.flash_size); | |
10074 | ||
1b6e2ceb DK |
10075 | bnx2x_init_shmem(bp); |
10076 | ||
619c5cb6 VZ |
10077 | |
10078 | ||
f2e0899f DK |
10079 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
10080 | MISC_REG_GENERIC_CR_1 : | |
10081 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 10082 | |
34f80b04 | 10083 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 10084 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
b884d95b YR |
10085 | if (SHMEM2_RD(bp, size) > |
10086 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
10087 | bp->link_params.lfa_base = | |
10088 | REG_RD(bp, bp->common.shmem2_base + | |
10089 | (u32)offsetof(struct shmem2_region, | |
10090 | lfa_host_addr[BP_PORT(bp)])); | |
10091 | else | |
10092 | bp->link_params.lfa_base = 0; | |
2691d51d EG |
10093 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
10094 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 10095 | |
f2e0899f | 10096 | if (!bp->common.shmem_base) { |
34f80b04 EG |
10097 | BNX2X_DEV_INFO("MCP not active\n"); |
10098 | bp->flags |= NO_MCP_FLAG; | |
10099 | return; | |
10100 | } | |
10101 | ||
34f80b04 | 10102 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 10103 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
10104 | |
10105 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
10106 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
10107 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
10108 | ||
c2c8b03e EG |
10109 | bp->link_params.feature_config_flags = 0; |
10110 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
10111 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
10112 | bp->link_params.feature_config_flags |= | |
10113 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
10114 | else | |
10115 | bp->link_params.feature_config_flags &= | |
10116 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
10117 | ||
34f80b04 EG |
10118 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
10119 | bp->common.bc_ver = val; | |
10120 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
10121 | if (val < BNX2X_BC_VER) { | |
10122 | /* for now only warn | |
10123 | * later we might need to enforce this */ | |
51c1a580 MS |
10124 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
10125 | BNX2X_BC_VER, val); | |
34f80b04 | 10126 | } |
4d295db0 | 10127 | bp->link_params.feature_config_flags |= |
a22f0788 | 10128 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
10129 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
10130 | ||
a22f0788 YR |
10131 | bp->link_params.feature_config_flags |= |
10132 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
10133 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
10134 | bp->link_params.feature_config_flags |= |
10135 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
10136 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
10137 | bp->link_params.feature_config_flags |= |
10138 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
10139 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
55386fe8 YR |
10140 | |
10141 | bp->link_params.feature_config_flags |= | |
10142 | (val >= REQ_BC_VER_4_MT_SUPPORTED) ? | |
10143 | FEATURE_CONFIG_MT_SUPPORT : 0; | |
10144 | ||
0e898dd7 BW |
10145 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
10146 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 10147 | |
2e499d3c BW |
10148 | bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? |
10149 | BC_SUPPORTS_FCOE_FEATURES : 0; | |
10150 | ||
9876879f BW |
10151 | bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? |
10152 | BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; | |
1d187b34 BW |
10153 | boot_mode = SHMEM_RD(bp, |
10154 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
10155 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
10156 | switch (boot_mode) { | |
10157 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
10158 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
10159 | break; | |
10160 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
10161 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
10162 | break; | |
10163 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
10164 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
10165 | break; | |
10166 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
10167 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
10168 | break; | |
10169 | } | |
10170 | ||
f9a3ebbe DK |
10171 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); |
10172 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; | |
10173 | ||
72ce58c3 | 10174 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 10175 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
10176 | |
10177 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
10178 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
10179 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
10180 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
10181 | ||
cdaa7cb8 VZ |
10182 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
10183 | val, val2, val3, val4); | |
34f80b04 EG |
10184 | } |
10185 | ||
f2e0899f DK |
10186 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
10187 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
10188 | ||
0329aba1 | 10189 | static int bnx2x_get_igu_cam_info(struct bnx2x *bp) |
f2e0899f DK |
10190 | { |
10191 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
10192 | int igu_sb_id; |
10193 | u32 val; | |
6383c0b3 | 10194 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
10195 | |
10196 | bp->igu_base_sb = 0xff; | |
f2e0899f | 10197 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 10198 | int vn = BP_VN(bp); |
6383c0b3 | 10199 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
10200 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
10201 | FP_SB_MAX_E1x; | |
10202 | ||
10203 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
10204 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
10205 | ||
9b341bb1 | 10206 | return 0; |
f2e0899f DK |
10207 | } |
10208 | ||
10209 | /* IGU in normal mode - read CAM */ | |
10210 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
10211 | igu_sb_id++) { | |
10212 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
10213 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
10214 | continue; | |
10215 | fid = IGU_FID(val); | |
10216 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
10217 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
10218 | continue; | |
10219 | if (IGU_VEC(val) == 0) | |
10220 | /* default status block */ | |
10221 | bp->igu_dsb_id = igu_sb_id; | |
10222 | else { | |
10223 | if (bp->igu_base_sb == 0xff) | |
10224 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 10225 | igu_sb_cnt++; |
f2e0899f DK |
10226 | } |
10227 | } | |
10228 | } | |
619c5cb6 | 10229 | |
6383c0b3 | 10230 | #ifdef CONFIG_PCI_MSI |
185d4c8b AE |
10231 | /* Due to new PF resource allocation by MFW T7.4 and above, it's |
10232 | * optional that number of CAM entries will not be equal to the value | |
10233 | * advertised in PCI. | |
10234 | * Driver should use the minimal value of both as the actual status | |
10235 | * block count | |
619c5cb6 | 10236 | */ |
185d4c8b | 10237 | bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); |
6383c0b3 | 10238 | #endif |
619c5cb6 | 10239 | |
9b341bb1 | 10240 | if (igu_sb_cnt == 0) { |
f2e0899f | 10241 | BNX2X_ERR("CAM configuration error\n"); |
9b341bb1 BW |
10242 | return -EINVAL; |
10243 | } | |
10244 | ||
10245 | return 0; | |
f2e0899f DK |
10246 | } |
10247 | ||
1dd06ae8 | 10248 | static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) |
a2fbb9ea | 10249 | { |
a22f0788 YR |
10250 | int cfg_size = 0, idx, port = BP_PORT(bp); |
10251 | ||
10252 | /* Aggregation of supported attributes of all external phys */ | |
10253 | bp->port.supported[0] = 0; | |
10254 | bp->port.supported[1] = 0; | |
b7737c9b YR |
10255 | switch (bp->link_params.num_phys) { |
10256 | case 1: | |
a22f0788 YR |
10257 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
10258 | cfg_size = 1; | |
10259 | break; | |
b7737c9b | 10260 | case 2: |
a22f0788 YR |
10261 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
10262 | cfg_size = 1; | |
10263 | break; | |
10264 | case 3: | |
10265 | if (bp->link_params.multi_phy_config & | |
10266 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
10267 | bp->port.supported[1] = | |
10268 | bp->link_params.phy[EXT_PHY1].supported; | |
10269 | bp->port.supported[0] = | |
10270 | bp->link_params.phy[EXT_PHY2].supported; | |
10271 | } else { | |
10272 | bp->port.supported[0] = | |
10273 | bp->link_params.phy[EXT_PHY1].supported; | |
10274 | bp->port.supported[1] = | |
10275 | bp->link_params.phy[EXT_PHY2].supported; | |
10276 | } | |
10277 | cfg_size = 2; | |
10278 | break; | |
b7737c9b | 10279 | } |
a2fbb9ea | 10280 | |
a22f0788 | 10281 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 10282 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 10283 | SHMEM_RD(bp, |
a22f0788 YR |
10284 | dev_info.port_hw_config[port].external_phy_config), |
10285 | SHMEM_RD(bp, | |
10286 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 10287 | return; |
f85582f8 | 10288 | } |
a2fbb9ea | 10289 | |
619c5cb6 VZ |
10290 | if (CHIP_IS_E3(bp)) |
10291 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
10292 | else { | |
10293 | switch (switch_cfg) { | |
10294 | case SWITCH_CFG_1G: | |
10295 | bp->port.phy_addr = REG_RD( | |
10296 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
10297 | break; | |
10298 | case SWITCH_CFG_10G: | |
10299 | bp->port.phy_addr = REG_RD( | |
10300 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
10301 | break; | |
10302 | default: | |
10303 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
10304 | bp->port.link_config[0]); | |
10305 | return; | |
10306 | } | |
a2fbb9ea | 10307 | } |
619c5cb6 | 10308 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
10309 | /* mask what we support according to speed_cap_mask per configuration */ |
10310 | for (idx = 0; idx < cfg_size; idx++) { | |
10311 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 10312 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 10313 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 10314 | |
a22f0788 | 10315 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10316 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 10317 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 10318 | |
a22f0788 | 10319 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10320 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 10321 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 10322 | |
a22f0788 | 10323 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10324 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 10325 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 10326 | |
a22f0788 | 10327 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10328 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 10329 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 10330 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 10331 | |
a22f0788 | 10332 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10333 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 10334 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 10335 | |
a22f0788 | 10336 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10337 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 YR |
10338 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
10339 | ||
10340 | } | |
a2fbb9ea | 10341 | |
a22f0788 YR |
10342 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
10343 | bp->port.supported[1]); | |
a2fbb9ea ET |
10344 | } |
10345 | ||
0329aba1 | 10346 | static void bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 10347 | { |
a22f0788 YR |
10348 | u32 link_config, idx, cfg_size = 0; |
10349 | bp->port.advertising[0] = 0; | |
10350 | bp->port.advertising[1] = 0; | |
10351 | switch (bp->link_params.num_phys) { | |
10352 | case 1: | |
10353 | case 2: | |
10354 | cfg_size = 1; | |
10355 | break; | |
10356 | case 3: | |
10357 | cfg_size = 2; | |
10358 | break; | |
10359 | } | |
10360 | for (idx = 0; idx < cfg_size; idx++) { | |
10361 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
10362 | link_config = bp->port.link_config[idx]; | |
10363 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 10364 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
10365 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
10366 | bp->link_params.req_line_speed[idx] = | |
10367 | SPEED_AUTO_NEG; | |
10368 | bp->port.advertising[idx] |= | |
10369 | bp->port.supported[idx]; | |
10bd1f24 MY |
10370 | if (bp->link_params.phy[EXT_PHY1].type == |
10371 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
10372 | bp->port.advertising[idx] |= | |
10373 | (SUPPORTED_100baseT_Half | | |
10374 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
10375 | } else { |
10376 | /* force 10G, no AN */ | |
a22f0788 YR |
10377 | bp->link_params.req_line_speed[idx] = |
10378 | SPEED_10000; | |
10379 | bp->port.advertising[idx] |= | |
10380 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 10381 | ADVERTISED_FIBRE); |
a22f0788 | 10382 | continue; |
f85582f8 DK |
10383 | } |
10384 | break; | |
a2fbb9ea | 10385 | |
f85582f8 | 10386 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
10387 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
10388 | bp->link_params.req_line_speed[idx] = | |
10389 | SPEED_10; | |
10390 | bp->port.advertising[idx] |= | |
10391 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
10392 | ADVERTISED_TP); |
10393 | } else { | |
51c1a580 | 10394 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 10395 | link_config, |
a22f0788 | 10396 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
10397 | return; |
10398 | } | |
10399 | break; | |
a2fbb9ea | 10400 | |
f85582f8 | 10401 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
10402 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
10403 | bp->link_params.req_line_speed[idx] = | |
10404 | SPEED_10; | |
10405 | bp->link_params.req_duplex[idx] = | |
10406 | DUPLEX_HALF; | |
10407 | bp->port.advertising[idx] |= | |
10408 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
10409 | ADVERTISED_TP); |
10410 | } else { | |
51c1a580 | 10411 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
10412 | link_config, |
10413 | bp->link_params.speed_cap_mask[idx]); | |
10414 | return; | |
10415 | } | |
10416 | break; | |
a2fbb9ea | 10417 | |
f85582f8 DK |
10418 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
10419 | if (bp->port.supported[idx] & | |
10420 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
10421 | bp->link_params.req_line_speed[idx] = |
10422 | SPEED_100; | |
10423 | bp->port.advertising[idx] |= | |
10424 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
10425 | ADVERTISED_TP); |
10426 | } else { | |
51c1a580 | 10427 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
10428 | link_config, |
10429 | bp->link_params.speed_cap_mask[idx]); | |
10430 | return; | |
10431 | } | |
10432 | break; | |
a2fbb9ea | 10433 | |
f85582f8 DK |
10434 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
10435 | if (bp->port.supported[idx] & | |
10436 | SUPPORTED_100baseT_Half) { | |
10437 | bp->link_params.req_line_speed[idx] = | |
10438 | SPEED_100; | |
10439 | bp->link_params.req_duplex[idx] = | |
10440 | DUPLEX_HALF; | |
a22f0788 YR |
10441 | bp->port.advertising[idx] |= |
10442 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
10443 | ADVERTISED_TP); |
10444 | } else { | |
51c1a580 | 10445 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10446 | link_config, |
10447 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10448 | return; |
10449 | } | |
10450 | break; | |
a2fbb9ea | 10451 | |
f85582f8 | 10452 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
10453 | if (bp->port.supported[idx] & |
10454 | SUPPORTED_1000baseT_Full) { | |
10455 | bp->link_params.req_line_speed[idx] = | |
10456 | SPEED_1000; | |
10457 | bp->port.advertising[idx] |= | |
10458 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
10459 | ADVERTISED_TP); |
10460 | } else { | |
51c1a580 | 10461 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10462 | link_config, |
10463 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10464 | return; |
10465 | } | |
10466 | break; | |
a2fbb9ea | 10467 | |
f85582f8 | 10468 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
10469 | if (bp->port.supported[idx] & |
10470 | SUPPORTED_2500baseX_Full) { | |
10471 | bp->link_params.req_line_speed[idx] = | |
10472 | SPEED_2500; | |
10473 | bp->port.advertising[idx] |= | |
10474 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 10475 | ADVERTISED_TP); |
f85582f8 | 10476 | } else { |
51c1a580 | 10477 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10478 | link_config, |
f85582f8 DK |
10479 | bp->link_params.speed_cap_mask[idx]); |
10480 | return; | |
10481 | } | |
10482 | break; | |
a2fbb9ea | 10483 | |
f85582f8 | 10484 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
10485 | if (bp->port.supported[idx] & |
10486 | SUPPORTED_10000baseT_Full) { | |
10487 | bp->link_params.req_line_speed[idx] = | |
10488 | SPEED_10000; | |
10489 | bp->port.advertising[idx] |= | |
10490 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 10491 | ADVERTISED_FIBRE); |
f85582f8 | 10492 | } else { |
51c1a580 | 10493 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10494 | link_config, |
f85582f8 DK |
10495 | bp->link_params.speed_cap_mask[idx]); |
10496 | return; | |
10497 | } | |
10498 | break; | |
3c9ada22 YR |
10499 | case PORT_FEATURE_LINK_SPEED_20G: |
10500 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 10501 | |
3c9ada22 | 10502 | break; |
f85582f8 | 10503 | default: |
51c1a580 | 10504 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 10505 | link_config); |
f85582f8 DK |
10506 | bp->link_params.req_line_speed[idx] = |
10507 | SPEED_AUTO_NEG; | |
10508 | bp->port.advertising[idx] = | |
10509 | bp->port.supported[idx]; | |
10510 | break; | |
10511 | } | |
a2fbb9ea | 10512 | |
a22f0788 | 10513 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 10514 | PORT_FEATURE_FLOW_CONTROL_MASK); |
cd1dfce2 YM |
10515 | if (bp->link_params.req_flow_ctrl[idx] == |
10516 | BNX2X_FLOW_CTRL_AUTO) { | |
10517 | if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) | |
10518 | bp->link_params.req_flow_ctrl[idx] = | |
10519 | BNX2X_FLOW_CTRL_NONE; | |
10520 | else | |
10521 | bnx2x_set_requested_fc(bp); | |
a22f0788 | 10522 | } |
a2fbb9ea | 10523 | |
51c1a580 | 10524 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
10525 | bp->link_params.req_line_speed[idx], |
10526 | bp->link_params.req_duplex[idx], | |
10527 | bp->link_params.req_flow_ctrl[idx], | |
10528 | bp->port.advertising[idx]); | |
10529 | } | |
a2fbb9ea ET |
10530 | } |
10531 | ||
0329aba1 | 10532 | static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
e665bfda MC |
10533 | { |
10534 | mac_hi = cpu_to_be16(mac_hi); | |
10535 | mac_lo = cpu_to_be32(mac_lo); | |
10536 | memcpy(mac_buf, &mac_hi, sizeof(mac_hi)); | |
10537 | memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo)); | |
10538 | } | |
10539 | ||
0329aba1 | 10540 | static void bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 10541 | { |
34f80b04 | 10542 | int port = BP_PORT(bp); |
589abe3a | 10543 | u32 config; |
c8c60d88 | 10544 | u32 ext_phy_type, ext_phy_config, eee_mode; |
a2fbb9ea | 10545 | |
c18487ee | 10546 | bp->link_params.bp = bp; |
34f80b04 | 10547 | bp->link_params.port = port; |
c18487ee | 10548 | |
c18487ee | 10549 | bp->link_params.lane_config = |
a2fbb9ea | 10550 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 10551 | |
a22f0788 | 10552 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea ET |
10553 | SHMEM_RD(bp, |
10554 | dev_info.port_hw_config[port].speed_capability_mask); | |
a22f0788 YR |
10555 | bp->link_params.speed_cap_mask[1] = |
10556 | SHMEM_RD(bp, | |
10557 | dev_info.port_hw_config[port].speed_capability_mask2); | |
10558 | bp->port.link_config[0] = | |
a2fbb9ea ET |
10559 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
10560 | ||
a22f0788 YR |
10561 | bp->port.link_config[1] = |
10562 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 10563 | |
a22f0788 YR |
10564 | bp->link_params.multi_phy_config = |
10565 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
10566 | /* If the device is capable of WoL, set the default state according |
10567 | * to the HW | |
10568 | */ | |
4d295db0 | 10569 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
10570 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
10571 | (config & PORT_FEATURE_WOL_ENABLED)); | |
10572 | ||
4ba7699b YM |
10573 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == |
10574 | PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) | |
10575 | bp->flags |= NO_ISCSI_FLAG; | |
10576 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == | |
10577 | PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) | |
10578 | bp->flags |= NO_FCOE_FLAG; | |
10579 | ||
51c1a580 | 10580 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 10581 | bp->link_params.lane_config, |
a22f0788 YR |
10582 | bp->link_params.speed_cap_mask[0], |
10583 | bp->port.link_config[0]); | |
a2fbb9ea | 10584 | |
a22f0788 | 10585 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 10586 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 10587 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 10588 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
10589 | |
10590 | bnx2x_link_settings_requested(bp); | |
10591 | ||
01cd4528 EG |
10592 | /* |
10593 | * If connected directly, work with the internal PHY, otherwise, work | |
10594 | * with the external PHY | |
10595 | */ | |
b7737c9b YR |
10596 | ext_phy_config = |
10597 | SHMEM_RD(bp, | |
10598 | dev_info.port_hw_config[port].external_phy_config); | |
10599 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 10600 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 10601 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
10602 | |
10603 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
10604 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
10605 | bp->mdio.prtad = | |
b7737c9b | 10606 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d | 10607 | |
c8c60d88 YM |
10608 | /* Configure link feature according to nvram value */ |
10609 | eee_mode = (((SHMEM_RD(bp, dev_info. | |
10610 | port_feature_config[port].eee_power_mode)) & | |
10611 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
10612 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
10613 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { | |
10614 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | | |
10615 | EEE_MODE_ENABLE_LPI | | |
10616 | EEE_MODE_OUTPUT_TIME; | |
10617 | } else { | |
10618 | bp->link_params.eee_mode = 0; | |
10619 | } | |
0793f83f | 10620 | } |
01cd4528 | 10621 | |
b306f5ed | 10622 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 10623 | { |
9e62e912 | 10624 | u32 no_flags = NO_ISCSI_FLAG; |
bf61ee14 | 10625 | int port = BP_PORT(bp); |
2ba45142 | 10626 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 10627 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 10628 | |
55c11941 MS |
10629 | if (!CNIC_SUPPORT(bp)) { |
10630 | bp->flags |= no_flags; | |
10631 | return; | |
10632 | } | |
10633 | ||
b306f5ed | 10634 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
10635 | bp->cnic_eth_dev.max_iscsi_conn = |
10636 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
10637 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
10638 | ||
b306f5ed DK |
10639 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
10640 | bp->cnic_eth_dev.max_iscsi_conn); | |
10641 | ||
10642 | /* | |
10643 | * If maximum allowed number of connections is zero - | |
10644 | * disable the feature. | |
10645 | */ | |
10646 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 10647 | bp->flags |= no_flags; |
55c11941 | 10648 | |
b306f5ed DK |
10649 | } |
10650 | ||
0329aba1 | 10651 | static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) |
9e62e912 DK |
10652 | { |
10653 | /* Port info */ | |
10654 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10655 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
10656 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10657 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
10658 | ||
10659 | /* Node info */ | |
10660 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10661 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
10662 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10663 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
10664 | } | |
0329aba1 | 10665 | static void bnx2x_get_fcoe_info(struct bnx2x *bp) |
b306f5ed DK |
10666 | { |
10667 | int port = BP_PORT(bp); | |
10668 | int func = BP_ABS_FUNC(bp); | |
b306f5ed DK |
10669 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
10670 | drv_lic_key[port].max_fcoe_conn); | |
10671 | ||
55c11941 MS |
10672 | if (!CNIC_SUPPORT(bp)) { |
10673 | bp->flags |= NO_FCOE_FLAG; | |
10674 | return; | |
10675 | } | |
10676 | ||
b306f5ed | 10677 | /* Get the number of maximum allowed FCoE connections */ |
2ba45142 VZ |
10678 | bp->cnic_eth_dev.max_fcoe_conn = |
10679 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
10680 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
10681 | ||
bf61ee14 VZ |
10682 | /* Read the WWN: */ |
10683 | if (!IS_MF(bp)) { | |
10684 | /* Port info */ | |
10685 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10686 | SHMEM_RD(bp, | |
10687 | dev_info.port_hw_config[port]. | |
10688 | fcoe_wwn_port_name_upper); | |
10689 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10690 | SHMEM_RD(bp, | |
10691 | dev_info.port_hw_config[port]. | |
10692 | fcoe_wwn_port_name_lower); | |
10693 | ||
10694 | /* Node info */ | |
10695 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10696 | SHMEM_RD(bp, | |
10697 | dev_info.port_hw_config[port]. | |
10698 | fcoe_wwn_node_name_upper); | |
10699 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10700 | SHMEM_RD(bp, | |
10701 | dev_info.port_hw_config[port]. | |
10702 | fcoe_wwn_node_name_lower); | |
10703 | } else if (!IS_MF_SD(bp)) { | |
bf61ee14 VZ |
10704 | /* |
10705 | * Read the WWN info only if the FCoE feature is enabled for | |
10706 | * this function. | |
10707 | */ | |
7b5342d9 | 10708 | if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) |
9e62e912 DK |
10709 | bnx2x_get_ext_wwn_info(bp, func); |
10710 | ||
382e513a | 10711 | } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) { |
9e62e912 | 10712 | bnx2x_get_ext_wwn_info(bp, func); |
382e513a | 10713 | } |
bf61ee14 | 10714 | |
b306f5ed | 10715 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 10716 | |
bf61ee14 VZ |
10717 | /* |
10718 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
10719 | * disable the feature. |
10720 | */ | |
2ba45142 VZ |
10721 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
10722 | bp->flags |= NO_FCOE_FLAG; | |
10723 | } | |
b306f5ed | 10724 | |
0329aba1 | 10725 | static void bnx2x_get_cnic_info(struct bnx2x *bp) |
b306f5ed DK |
10726 | { |
10727 | /* | |
10728 | * iSCSI may be dynamically disabled but reading | |
10729 | * info here we will decrease memory usage by driver | |
10730 | * if the feature is disabled for good | |
10731 | */ | |
10732 | bnx2x_get_iscsi_info(bp); | |
10733 | bnx2x_get_fcoe_info(bp); | |
10734 | } | |
2ba45142 | 10735 | |
0329aba1 | 10736 | static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) |
0793f83f DK |
10737 | { |
10738 | u32 val, val2; | |
10739 | int func = BP_ABS_FUNC(bp); | |
10740 | int port = BP_PORT(bp); | |
2ba45142 VZ |
10741 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; |
10742 | u8 *fip_mac = bp->fip_mac; | |
0793f83f | 10743 | |
55c11941 MS |
10744 | if (IS_MF(bp)) { |
10745 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 10746 | * FCoE MAC then the appropriate feature should be disabled. |
55c11941 MS |
10747 | * In non SD mode features configuration comes from struct |
10748 | * func_ext_config. | |
2ba45142 | 10749 | */ |
55c11941 | 10750 | if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) { |
0793f83f DK |
10751 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
10752 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
10753 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 10754 | iscsi_mac_addr_upper); |
0793f83f | 10755 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 10756 | iscsi_mac_addr_lower); |
2ba45142 | 10757 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
55c11941 MS |
10758 | BNX2X_DEV_INFO |
10759 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
10760 | } else { | |
2ba45142 | 10761 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
55c11941 | 10762 | } |
2ba45142 VZ |
10763 | |
10764 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
10765 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 10766 | fcoe_mac_addr_upper); |
2ba45142 | 10767 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 10768 | fcoe_mac_addr_lower); |
2ba45142 | 10769 | bnx2x_set_mac_buf(fip_mac, val, val2); |
55c11941 MS |
10770 | BNX2X_DEV_INFO |
10771 | ("Read FCoE L2 MAC: %pM\n", fip_mac); | |
10772 | } else { | |
2ba45142 | 10773 | bp->flags |= NO_FCOE_FLAG; |
55c11941 | 10774 | } |
a3348722 BW |
10775 | |
10776 | bp->mf_ext_config = cfg; | |
10777 | ||
9e62e912 | 10778 | } else { /* SD MODE */ |
55c11941 MS |
10779 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { |
10780 | /* use primary mac as iscsi mac */ | |
10781 | memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); | |
10782 | ||
10783 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
10784 | BNX2X_DEV_INFO | |
10785 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
10786 | } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { | |
10787 | /* use primary mac as fip mac */ | |
10788 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); | |
10789 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
10790 | BNX2X_DEV_INFO | |
10791 | ("Read FIP MAC: %pM\n", fip_mac); | |
614c76df | 10792 | } |
0793f83f | 10793 | } |
a3348722 | 10794 | |
55c11941 MS |
10795 | if (IS_MF_STORAGE_SD(bp)) |
10796 | /* Zero primary MAC configuration */ | |
10797 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
10798 | ||
f72839d0 | 10799 | if (IS_MF_FCOE_AFEX(bp) || IS_MF_FCOE_SD(bp)) |
a3348722 BW |
10800 | /* use FIP MAC as primary MAC */ |
10801 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); | |
10802 | ||
0793f83f | 10803 | } else { |
0793f83f | 10804 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 10805 | iscsi_mac_upper); |
0793f83f | 10806 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 10807 | iscsi_mac_lower); |
2ba45142 | 10808 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
10809 | |
10810 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
55c11941 | 10811 | fcoe_fip_mac_upper); |
c03bd39c | 10812 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 10813 | fcoe_fip_mac_lower); |
c03bd39c | 10814 | bnx2x_set_mac_buf(fip_mac, val, val2); |
0793f83f DK |
10815 | } |
10816 | ||
55c11941 | 10817 | /* Disable iSCSI OOO if MAC configuration is invalid. */ |
426b9241 | 10818 | if (!is_valid_ether_addr(iscsi_mac)) { |
55c11941 | 10819 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
426b9241 DK |
10820 | memset(iscsi_mac, 0, ETH_ALEN); |
10821 | } | |
10822 | ||
55c11941 | 10823 | /* Disable FCoE if MAC configuration is invalid. */ |
426b9241 DK |
10824 | if (!is_valid_ether_addr(fip_mac)) { |
10825 | bp->flags |= NO_FCOE_FLAG; | |
10826 | memset(bp->fip_mac, 0, ETH_ALEN); | |
10827 | } | |
55c11941 MS |
10828 | } |
10829 | ||
0329aba1 | 10830 | static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
55c11941 MS |
10831 | { |
10832 | u32 val, val2; | |
10833 | int func = BP_ABS_FUNC(bp); | |
10834 | int port = BP_PORT(bp); | |
10835 | ||
10836 | /* Zero primary MAC configuration */ | |
10837 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
10838 | ||
10839 | if (BP_NOMCP(bp)) { | |
10840 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
10841 | eth_hw_addr_random(bp->dev); | |
10842 | } else if (IS_MF(bp)) { | |
10843 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
10844 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
10845 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
10846 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
10847 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
10848 | ||
10849 | if (CNIC_SUPPORT(bp)) | |
10850 | bnx2x_get_cnic_mac_hwinfo(bp); | |
10851 | } else { | |
10852 | /* in SF read MACs from port configuration */ | |
10853 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
10854 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
10855 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
10856 | ||
10857 | if (CNIC_SUPPORT(bp)) | |
10858 | bnx2x_get_cnic_mac_hwinfo(bp); | |
10859 | } | |
10860 | ||
10861 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
619c5cb6 | 10862 | |
614c76df | 10863 | if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) |
619c5cb6 | 10864 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
10865 | "bad Ethernet MAC address configuration: %pM\n" |
10866 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 10867 | bp->dev->dev_addr); |
7964211d | 10868 | } |
51c1a580 | 10869 | |
0329aba1 | 10870 | static bool bnx2x_get_dropless_info(struct bnx2x *bp) |
7964211d YM |
10871 | { |
10872 | int tmp; | |
10873 | u32 cfg; | |
51c1a580 | 10874 | |
7964211d YM |
10875 | if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { |
10876 | /* Take function: tmp = func */ | |
10877 | tmp = BP_ABS_FUNC(bp); | |
10878 | cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); | |
10879 | cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); | |
10880 | } else { | |
10881 | /* Take port: tmp = port */ | |
10882 | tmp = BP_PORT(bp); | |
10883 | cfg = SHMEM_RD(bp, | |
10884 | dev_info.port_hw_config[tmp].generic_features); | |
10885 | cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); | |
10886 | } | |
10887 | return cfg; | |
34f80b04 EG |
10888 | } |
10889 | ||
0329aba1 | 10890 | static int bnx2x_get_hwinfo(struct bnx2x *bp) |
34f80b04 | 10891 | { |
0793f83f | 10892 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 10893 | int vn; |
0793f83f | 10894 | u32 val = 0; |
34f80b04 | 10895 | int rc = 0; |
a2fbb9ea | 10896 | |
34f80b04 | 10897 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 10898 | |
6383c0b3 AE |
10899 | /* |
10900 | * initialize IGU parameters | |
10901 | */ | |
f2e0899f DK |
10902 | if (CHIP_IS_E1x(bp)) { |
10903 | bp->common.int_block = INT_BLOCK_HC; | |
10904 | ||
10905 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
10906 | bp->igu_base_sb = 0; | |
f2e0899f DK |
10907 | } else { |
10908 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 DK |
10909 | |
10910 | /* do not allow device reset during IGU info preocessing */ | |
10911 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | |
10912 | ||
f2e0899f | 10913 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
10914 | |
10915 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
10916 | int tout = 5000; | |
10917 | ||
10918 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
10919 | ||
10920 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
10921 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
10922 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
10923 | ||
10924 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
10925 | tout--; | |
10926 | usleep_range(1000, 1000); | |
10927 | } | |
10928 | ||
10929 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
10930 | dev_err(&bp->pdev->dev, | |
10931 | "FORCING Normal Mode failed!!!\n"); | |
9b341bb1 BW |
10932 | bnx2x_release_hw_lock(bp, |
10933 | HW_LOCK_RESOURCE_RESET); | |
619c5cb6 VZ |
10934 | return -EPERM; |
10935 | } | |
10936 | } | |
10937 | ||
f2e0899f | 10938 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 10939 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
10940 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
10941 | } else | |
619c5cb6 | 10942 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 10943 | |
9b341bb1 | 10944 | rc = bnx2x_get_igu_cam_info(bp); |
7a06a122 | 10945 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
9b341bb1 BW |
10946 | if (rc) |
10947 | return rc; | |
f2e0899f | 10948 | } |
619c5cb6 VZ |
10949 | |
10950 | /* | |
10951 | * set base FW non-default (fast path) status block id, this value is | |
10952 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
10953 | * determine the id used by the FW. | |
10954 | */ | |
10955 | if (CHIP_IS_E1x(bp)) | |
10956 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
10957 | else /* | |
10958 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
10959 | * the same queue are indicated on the same IGU SB). So we prefer | |
10960 | * FW and IGU SBs to be the same value. | |
10961 | */ | |
10962 | bp->base_fw_ndsb = bp->igu_base_sb; | |
10963 | ||
10964 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
10965 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
10966 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
10967 | |
10968 | /* | |
10969 | * Initialize MF configuration | |
10970 | */ | |
523224a3 | 10971 | |
fb3bff17 DK |
10972 | bp->mf_ov = 0; |
10973 | bp->mf_mode = 0; | |
3395a033 | 10974 | vn = BP_VN(bp); |
0793f83f | 10975 | |
f2e0899f | 10976 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
10977 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
10978 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
10979 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
10980 | ||
f2e0899f DK |
10981 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
10982 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
10983 | else | |
10984 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
10985 | offsetof(struct shmem_region, func_mb) + |
10986 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
10987 | /* |
10988 | * get mf configuration: | |
25985edc | 10989 | * 1. existence of MF configuration |
0793f83f DK |
10990 | * 2. MAC address must be legal (check only upper bytes) |
10991 | * for Switch-Independent mode; | |
10992 | * OVLAN must be legal for Switch-Dependent mode | |
10993 | * 3. SF_MODE configures specific MF mode | |
10994 | */ | |
10995 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
10996 | /* get mf configuration */ | |
10997 | val = SHMEM_RD(bp, | |
10998 | dev_info.shared_feature_config.config); | |
10999 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
11000 | ||
11001 | switch (val) { | |
11002 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
11003 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
11004 | mac_upper); | |
11005 | /* check for legal mac (upper bytes)*/ | |
11006 | if (val != 0xffff) { | |
11007 | bp->mf_mode = MULTI_FUNCTION_SI; | |
11008 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11009 | func_mf_config[func].config); | |
11010 | } else | |
51c1a580 | 11011 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); |
0793f83f | 11012 | break; |
a3348722 BW |
11013 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
11014 | if ((!CHIP_IS_E1x(bp)) && | |
11015 | (MF_CFG_RD(bp, func_mf_config[func]. | |
11016 | mac_upper) != 0xffff) && | |
11017 | (SHMEM2_HAS(bp, | |
11018 | afex_driver_support))) { | |
11019 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
11020 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11021 | func_mf_config[func].config); | |
11022 | } else { | |
11023 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
11024 | } | |
11025 | break; | |
0793f83f DK |
11026 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
11027 | /* get OV configuration */ | |
11028 | val = MF_CFG_RD(bp, | |
11029 | func_mf_config[FUNC_0].e1hov_tag); | |
11030 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
11031 | ||
11032 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
11033 | bp->mf_mode = MULTI_FUNCTION_SD; | |
11034 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11035 | func_mf_config[func].config); | |
11036 | } else | |
754a2f52 | 11037 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f DK |
11038 | break; |
11039 | default: | |
11040 | /* Unknown configuration: reset mf_config */ | |
11041 | bp->mf_config[vn] = 0; | |
51c1a580 | 11042 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
11043 | } |
11044 | } | |
a2fbb9ea | 11045 | |
2691d51d | 11046 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 11047 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 11048 | |
0793f83f DK |
11049 | switch (bp->mf_mode) { |
11050 | case MULTI_FUNCTION_SD: | |
11051 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
11052 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 11053 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 11054 | bp->mf_ov = val; |
619c5cb6 VZ |
11055 | bp->path_has_ovlan = true; |
11056 | ||
51c1a580 MS |
11057 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
11058 | func, bp->mf_ov, bp->mf_ov); | |
2691d51d | 11059 | } else { |
619c5cb6 | 11060 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11061 | "No valid MF OV for func %d, aborting\n", |
11062 | func); | |
619c5cb6 | 11063 | return -EPERM; |
34f80b04 | 11064 | } |
0793f83f | 11065 | break; |
a3348722 BW |
11066 | case MULTI_FUNCTION_AFEX: |
11067 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
11068 | break; | |
0793f83f | 11069 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
11070 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
11071 | func); | |
0793f83f DK |
11072 | break; |
11073 | default: | |
11074 | if (vn) { | |
619c5cb6 | 11075 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11076 | "VN %d is in a single function mode, aborting\n", |
11077 | vn); | |
619c5cb6 | 11078 | return -EPERM; |
2691d51d | 11079 | } |
0793f83f | 11080 | break; |
34f80b04 | 11081 | } |
0793f83f | 11082 | |
619c5cb6 VZ |
11083 | /* check if other port on the path needs ovlan: |
11084 | * Since MF configuration is shared between ports | |
11085 | * Possible mixed modes are only | |
11086 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
11087 | */ | |
11088 | if (CHIP_MODE_IS_4_PORT(bp) && | |
11089 | !bp->path_has_ovlan && | |
11090 | !IS_MF(bp) && | |
11091 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
11092 | u8 other_port = !BP_PORT(bp); | |
11093 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
11094 | val = MF_CFG_RD(bp, | |
11095 | func_mf_config[other_func].e1hov_tag); | |
11096 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
11097 | bp->path_has_ovlan = true; | |
11098 | } | |
34f80b04 | 11099 | } |
a2fbb9ea | 11100 | |
f2e0899f DK |
11101 | /* adjust igu_sb_cnt to MF for E1x */ |
11102 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
11103 | bp->igu_sb_cnt /= E1HVN_MAX; |
11104 | ||
619c5cb6 VZ |
11105 | /* port info */ |
11106 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 11107 | |
0793f83f DK |
11108 | /* Get MAC addresses */ |
11109 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 11110 | |
2ba45142 | 11111 | bnx2x_get_cnic_info(bp); |
2ba45142 | 11112 | |
34f80b04 EG |
11113 | return rc; |
11114 | } | |
11115 | ||
0329aba1 | 11116 | static void bnx2x_read_fwinfo(struct bnx2x *bp) |
34f24c7f VZ |
11117 | { |
11118 | int cnt, i, block_end, rodi; | |
fcdf95cb | 11119 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
11120 | char str_id_reg[VENDOR_ID_LEN+1]; |
11121 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
11122 | char *vpd_data; |
11123 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
11124 | u8 len; |
11125 | ||
fcdf95cb | 11126 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
11127 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
11128 | ||
11129 | if (cnt < BNX2X_VPD_LEN) | |
11130 | goto out_not_found; | |
11131 | ||
fcdf95cb BW |
11132 | /* VPD RO tag should be first tag after identifier string, hence |
11133 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
11134 | */ | |
11135 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
11136 | PCI_VPD_LRDT_RO_DATA); |
11137 | if (i < 0) | |
11138 | goto out_not_found; | |
11139 | ||
34f24c7f | 11140 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 11141 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
11142 | |
11143 | i += PCI_VPD_LRDT_TAG_SIZE; | |
11144 | ||
fcdf95cb BW |
11145 | if (block_end > BNX2X_VPD_LEN) { |
11146 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
11147 | if (vpd_extended_data == NULL) | |
11148 | goto out_not_found; | |
11149 | ||
11150 | /* read rest of vpd image into vpd_extended_data */ | |
11151 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
11152 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
11153 | block_end - BNX2X_VPD_LEN, | |
11154 | vpd_extended_data + BNX2X_VPD_LEN); | |
11155 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
11156 | goto out_not_found; | |
11157 | vpd_data = vpd_extended_data; | |
11158 | } else | |
11159 | vpd_data = vpd_start; | |
11160 | ||
11161 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
11162 | |
11163 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
11164 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
11165 | if (rodi < 0) | |
11166 | goto out_not_found; | |
11167 | ||
11168 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
11169 | ||
11170 | if (len != VENDOR_ID_LEN) | |
11171 | goto out_not_found; | |
11172 | ||
11173 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11174 | ||
11175 | /* vendor specific info */ | |
11176 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
11177 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
11178 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
11179 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
11180 | ||
11181 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
11182 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
11183 | if (rodi >= 0) { | |
11184 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
11185 | ||
11186 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11187 | ||
11188 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
11189 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
11190 | bp->fw_ver[len] = ' '; | |
11191 | } | |
11192 | } | |
fcdf95cb | 11193 | kfree(vpd_extended_data); |
34f24c7f VZ |
11194 | return; |
11195 | } | |
11196 | out_not_found: | |
fcdf95cb | 11197 | kfree(vpd_extended_data); |
34f24c7f VZ |
11198 | return; |
11199 | } | |
11200 | ||
0329aba1 | 11201 | static void bnx2x_set_modes_bitmap(struct bnx2x *bp) |
619c5cb6 VZ |
11202 | { |
11203 | u32 flags = 0; | |
11204 | ||
11205 | if (CHIP_REV_IS_FPGA(bp)) | |
11206 | SET_FLAGS(flags, MODE_FPGA); | |
11207 | else if (CHIP_REV_IS_EMUL(bp)) | |
11208 | SET_FLAGS(flags, MODE_EMUL); | |
11209 | else | |
11210 | SET_FLAGS(flags, MODE_ASIC); | |
11211 | ||
11212 | if (CHIP_MODE_IS_4_PORT(bp)) | |
11213 | SET_FLAGS(flags, MODE_PORT4); | |
11214 | else | |
11215 | SET_FLAGS(flags, MODE_PORT2); | |
11216 | ||
11217 | if (CHIP_IS_E2(bp)) | |
11218 | SET_FLAGS(flags, MODE_E2); | |
11219 | else if (CHIP_IS_E3(bp)) { | |
11220 | SET_FLAGS(flags, MODE_E3); | |
11221 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
11222 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
11223 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
11224 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
11225 | } |
11226 | ||
11227 | if (IS_MF(bp)) { | |
11228 | SET_FLAGS(flags, MODE_MF); | |
11229 | switch (bp->mf_mode) { | |
11230 | case MULTI_FUNCTION_SD: | |
11231 | SET_FLAGS(flags, MODE_MF_SD); | |
11232 | break; | |
11233 | case MULTI_FUNCTION_SI: | |
11234 | SET_FLAGS(flags, MODE_MF_SI); | |
11235 | break; | |
a3348722 BW |
11236 | case MULTI_FUNCTION_AFEX: |
11237 | SET_FLAGS(flags, MODE_MF_AFEX); | |
11238 | break; | |
619c5cb6 VZ |
11239 | } |
11240 | } else | |
11241 | SET_FLAGS(flags, MODE_SF); | |
11242 | ||
11243 | #if defined(__LITTLE_ENDIAN) | |
11244 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
11245 | #else /*(__BIG_ENDIAN)*/ | |
11246 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
11247 | #endif | |
11248 | INIT_MODE_FLAGS(bp) = flags; | |
11249 | } | |
11250 | ||
0329aba1 | 11251 | static int bnx2x_init_bp(struct bnx2x *bp) |
34f80b04 | 11252 | { |
f2e0899f | 11253 | int func; |
34f80b04 EG |
11254 | int rc; |
11255 | ||
34f80b04 | 11256 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 11257 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 11258 | spin_lock_init(&bp->stats_lock); |
55c11941 | 11259 | |
a2fbb9ea | 11260 | |
1cf167f2 | 11261 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 11262 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 11263 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
1ab4434c AE |
11264 | if (IS_PF(bp)) { |
11265 | rc = bnx2x_get_hwinfo(bp); | |
11266 | if (rc) | |
11267 | return rc; | |
11268 | } else { | |
11269 | random_ether_addr(bp->dev->dev_addr); | |
11270 | } | |
34f80b04 | 11271 | |
619c5cb6 VZ |
11272 | bnx2x_set_modes_bitmap(bp); |
11273 | ||
11274 | rc = bnx2x_alloc_mem_bp(bp); | |
11275 | if (rc) | |
11276 | return rc; | |
523224a3 | 11277 | |
34f24c7f | 11278 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
11279 | |
11280 | func = BP_FUNC(bp); | |
11281 | ||
34f80b04 | 11282 | /* need to reset chip if undi was active */ |
1ab4434c | 11283 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
452427b0 YM |
11284 | /* init fw_seq */ |
11285 | bp->fw_seq = | |
11286 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
11287 | DRV_MSG_SEQ_NUMBER_MASK; | |
11288 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
11289 | ||
11290 | bnx2x_prev_unload(bp); | |
11291 | } | |
11292 | ||
34f80b04 EG |
11293 | |
11294 | if (CHIP_REV_IS_FPGA(bp)) | |
cdaa7cb8 | 11295 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
11296 | |
11297 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 11298 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 11299 | |
614c76df | 11300 | bp->disable_tpa = disable_tpa; |
a3348722 | 11301 | bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp); |
614c76df | 11302 | |
7a9b2557 | 11303 | /* Set TPA flags */ |
614c76df | 11304 | if (bp->disable_tpa) { |
621b4d66 | 11305 | bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
11306 | bp->dev->features &= ~NETIF_F_LRO; |
11307 | } else { | |
621b4d66 | 11308 | bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
11309 | bp->dev->features |= NETIF_F_LRO; |
11310 | } | |
11311 | ||
a18f5128 EG |
11312 | if (CHIP_IS_E1(bp)) |
11313 | bp->dropless_fc = 0; | |
11314 | else | |
7964211d | 11315 | bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); |
a18f5128 | 11316 | |
8d5726c4 | 11317 | bp->mrrs = mrrs; |
7a9b2557 | 11318 | |
a3348722 | 11319 | bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; |
1ab4434c AE |
11320 | if (IS_VF(bp)) |
11321 | bp->rx_ring_size = MAX_RX_AVAIL; | |
34f80b04 | 11322 | |
7d323bfd | 11323 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
11324 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
11325 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 11326 | |
fc543637 | 11327 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 EG |
11328 | |
11329 | init_timer(&bp->timer); | |
11330 | bp->timer.expires = jiffies + bp->current_interval; | |
11331 | bp->timer.data = (unsigned long) bp; | |
11332 | bp->timer.function = bnx2x_timer; | |
11333 | ||
0370cf90 BW |
11334 | if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && |
11335 | SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && | |
11336 | SHMEM2_RD(bp, dcbx_lldp_params_offset) && | |
11337 | SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) { | |
11338 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); | |
11339 | bnx2x_dcbx_init_params(bp); | |
11340 | } else { | |
11341 | bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); | |
11342 | } | |
e4901dde | 11343 | |
619c5cb6 VZ |
11344 | if (CHIP_IS_E1x(bp)) |
11345 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
11346 | else | |
11347 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
619c5cb6 | 11348 | |
6383c0b3 | 11349 | /* multiple tx priority */ |
1ab4434c AE |
11350 | if (IS_VF(bp)) |
11351 | bp->max_cos = 1; | |
11352 | else if (CHIP_IS_E1x(bp)) | |
6383c0b3 | 11353 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; |
1ab4434c | 11354 | else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) |
6383c0b3 | 11355 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; |
1ab4434c | 11356 | else if (CHIP_IS_E3B0(bp)) |
6383c0b3 | 11357 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; |
1ab4434c AE |
11358 | else |
11359 | BNX2X_ERR("unknown chip %x revision %x\n", | |
11360 | CHIP_NUM(bp), CHIP_REV(bp)); | |
11361 | BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); | |
6383c0b3 | 11362 | |
55c11941 MS |
11363 | /* We need at least one default status block for slow-path events, |
11364 | * second status block for the L2 queue, and a third status block for | |
11365 | * CNIC if supproted. | |
11366 | */ | |
11367 | if (CNIC_SUPPORT(bp)) | |
11368 | bp->min_msix_vec_cnt = 3; | |
11369 | else | |
11370 | bp->min_msix_vec_cnt = 2; | |
11371 | BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); | |
11372 | ||
34f80b04 | 11373 | return rc; |
a2fbb9ea ET |
11374 | } |
11375 | ||
a2fbb9ea | 11376 | |
de0c62db DK |
11377 | /**************************************************************************** |
11378 | * General service functions | |
11379 | ****************************************************************************/ | |
a2fbb9ea | 11380 | |
619c5cb6 VZ |
11381 | /* |
11382 | * net_device service functions | |
11383 | */ | |
11384 | ||
8395be5e AE |
11385 | static int bnx2x_open_epilog(struct bnx2x *bp) |
11386 | { | |
11387 | /* Enable sriov via delayed work. This must be done via delayed work | |
11388 | * because it causes the probe of the vf devices to be run, which invoke | |
11389 | * register_netdevice which must have rtnl lock taken. As we are holding | |
11390 | * the lock right now, that could only work if the probe would not take | |
11391 | * the lock. However, as the probe of the vf may be called from other | |
11392 | * contexts as well (such as passthrough to vm failes) it can't assume | |
11393 | * the lock is being held for it. Using delayed work here allows the | |
11394 | * probe code to simply take the lock (i.e. wait for it to be released | |
11395 | * if it is being held). | |
11396 | */ | |
11397 | smp_mb__before_clear_bit(); | |
11398 | set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, &bp->sp_rtnl_state); | |
11399 | smp_mb__after_clear_bit(); | |
11400 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
11401 | ||
11402 | return 0; | |
11403 | } | |
11404 | ||
bb2a0f7a | 11405 | /* called with rtnl_lock */ |
a2fbb9ea ET |
11406 | static int bnx2x_open(struct net_device *dev) |
11407 | { | |
11408 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
11409 | bool global = false; |
11410 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
889b9af3 | 11411 | bool other_load_status, load_status; |
8395be5e | 11412 | int rc; |
a2fbb9ea | 11413 | |
1355b704 MY |
11414 | bp->stats_init = true; |
11415 | ||
6eccabb3 EG |
11416 | netif_carrier_off(dev); |
11417 | ||
a2fbb9ea ET |
11418 | bnx2x_set_power_state(bp, PCI_D0); |
11419 | ||
ad5afc89 | 11420 | /* If parity had happen during the unload, then attentions |
c9ee9206 VZ |
11421 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we |
11422 | * want the first function loaded on the current engine to | |
11423 | * complete the recovery. | |
ad5afc89 | 11424 | * Parity recovery is only relevant for PF driver. |
c9ee9206 | 11425 | */ |
ad5afc89 AE |
11426 | if (IS_PF(bp)) { |
11427 | other_load_status = bnx2x_get_load_status(bp, other_engine); | |
11428 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
11429 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
11430 | bnx2x_chk_parity_attn(bp, &global, true)) { | |
11431 | do { | |
11432 | /* If there are attentions and they are in a | |
11433 | * global blocks, set the GLOBAL_RESET bit | |
11434 | * regardless whether it will be this function | |
11435 | * that will complete the recovery or not. | |
11436 | */ | |
11437 | if (global) | |
11438 | bnx2x_set_reset_global(bp); | |
72fd0718 | 11439 | |
ad5afc89 AE |
11440 | /* Only the first function on the current |
11441 | * engine should try to recover in open. In case | |
11442 | * of attentions in global blocks only the first | |
11443 | * in the chip should try to recover. | |
11444 | */ | |
11445 | if ((!load_status && | |
11446 | (!global || !other_load_status)) && | |
11447 | bnx2x_trylock_leader_lock(bp) && | |
11448 | !bnx2x_leader_reset(bp)) { | |
11449 | netdev_info(bp->dev, | |
11450 | "Recovered in open\n"); | |
11451 | break; | |
11452 | } | |
72fd0718 | 11453 | |
ad5afc89 AE |
11454 | /* recovery has failed... */ |
11455 | bnx2x_set_power_state(bp, PCI_D3hot); | |
11456 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
72fd0718 | 11457 | |
ad5afc89 AE |
11458 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
11459 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 | 11460 | |
ad5afc89 AE |
11461 | return -EAGAIN; |
11462 | } while (0); | |
11463 | } | |
11464 | } | |
72fd0718 VZ |
11465 | |
11466 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
8395be5e AE |
11467 | rc = bnx2x_nic_load(bp, LOAD_OPEN); |
11468 | if (rc) | |
11469 | return rc; | |
11470 | return bnx2x_open_epilog(bp); | |
a2fbb9ea ET |
11471 | } |
11472 | ||
bb2a0f7a | 11473 | /* called with rtnl_lock */ |
56ad3152 | 11474 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 11475 | { |
a2fbb9ea ET |
11476 | struct bnx2x *bp = netdev_priv(dev); |
11477 | ||
11478 | /* Unload the driver, release IRQs */ | |
5d07d868 | 11479 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
c9ee9206 VZ |
11480 | |
11481 | /* Power off */ | |
d3dbfee0 | 11482 | bnx2x_set_power_state(bp, PCI_D3hot); |
a2fbb9ea ET |
11483 | |
11484 | return 0; | |
11485 | } | |
11486 | ||
1191cb83 ED |
11487 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
11488 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 11489 | { |
619c5cb6 VZ |
11490 | int mc_count = netdev_mc_count(bp->dev); |
11491 | struct bnx2x_mcast_list_elem *mc_mac = | |
11492 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
11493 | struct netdev_hw_addr *ha; | |
6e30dd4e | 11494 | |
619c5cb6 VZ |
11495 | if (!mc_mac) |
11496 | return -ENOMEM; | |
6e30dd4e | 11497 | |
619c5cb6 | 11498 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 11499 | |
619c5cb6 VZ |
11500 | netdev_for_each_mc_addr(ha, bp->dev) { |
11501 | mc_mac->mac = bnx2x_mc_addr(ha); | |
11502 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
11503 | mc_mac++; | |
6e30dd4e | 11504 | } |
619c5cb6 VZ |
11505 | |
11506 | p->mcast_list_len = mc_count; | |
11507 | ||
11508 | return 0; | |
6e30dd4e VZ |
11509 | } |
11510 | ||
1191cb83 | 11511 | static void bnx2x_free_mcast_macs_list( |
619c5cb6 VZ |
11512 | struct bnx2x_mcast_ramrod_params *p) |
11513 | { | |
11514 | struct bnx2x_mcast_list_elem *mc_mac = | |
11515 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
11516 | link); | |
11517 | ||
11518 | WARN_ON(!mc_mac); | |
11519 | kfree(mc_mac); | |
11520 | } | |
11521 | ||
11522 | /** | |
11523 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
11524 | * | |
11525 | * @bp: driver handle | |
6e30dd4e | 11526 | * |
619c5cb6 | 11527 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 11528 | */ |
1191cb83 | 11529 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 11530 | { |
619c5cb6 | 11531 | int rc; |
6e30dd4e | 11532 | struct net_device *dev = bp->dev; |
6e30dd4e | 11533 | struct netdev_hw_addr *ha; |
15192a8c | 11534 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 | 11535 | unsigned long ramrod_flags = 0; |
6e30dd4e | 11536 | |
619c5cb6 VZ |
11537 | /* First schedule a cleanup up of old configuration */ |
11538 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
11539 | if (rc < 0) { | |
11540 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
11541 | return rc; | |
11542 | } | |
6e30dd4e VZ |
11543 | |
11544 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
11545 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
11546 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
7b5342d9 YM |
11547 | if (rc == -EEXIST) { |
11548 | DP(BNX2X_MSG_SP, | |
11549 | "Failed to schedule ADD operations: %d\n", rc); | |
11550 | /* do not treat adding same MAC as error */ | |
11551 | rc = 0; | |
11552 | ||
11553 | } else if (rc < 0) { | |
11554 | ||
619c5cb6 VZ |
11555 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", |
11556 | rc); | |
11557 | return rc; | |
6e30dd4e VZ |
11558 | } |
11559 | } | |
11560 | ||
619c5cb6 VZ |
11561 | /* Execute the pending commands */ |
11562 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
11563 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
11564 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
11565 | } |
11566 | ||
1191cb83 | 11567 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 11568 | { |
619c5cb6 | 11569 | struct net_device *dev = bp->dev; |
3b603066 | 11570 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 11571 | int rc = 0; |
6e30dd4e | 11572 | |
619c5cb6 | 11573 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 11574 | |
619c5cb6 VZ |
11575 | /* first, clear all configured multicast MACs */ |
11576 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
11577 | if (rc < 0) { | |
51c1a580 | 11578 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
11579 | return rc; |
11580 | } | |
6e30dd4e | 11581 | |
619c5cb6 VZ |
11582 | /* then, configure a new MACs list */ |
11583 | if (netdev_mc_count(dev)) { | |
11584 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
11585 | if (rc) { | |
51c1a580 MS |
11586 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
11587 | rc); | |
619c5cb6 VZ |
11588 | return rc; |
11589 | } | |
6e30dd4e | 11590 | |
619c5cb6 VZ |
11591 | /* Now add the new MACs */ |
11592 | rc = bnx2x_config_mcast(bp, &rparam, | |
11593 | BNX2X_MCAST_CMD_ADD); | |
11594 | if (rc < 0) | |
51c1a580 MS |
11595 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
11596 | rc); | |
6e30dd4e | 11597 | |
619c5cb6 VZ |
11598 | bnx2x_free_mcast_macs_list(&rparam); |
11599 | } | |
6e30dd4e | 11600 | |
619c5cb6 | 11601 | return rc; |
6e30dd4e VZ |
11602 | } |
11603 | ||
6e30dd4e | 11604 | |
619c5cb6 | 11605 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 11606 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
11607 | { |
11608 | struct bnx2x *bp = netdev_priv(dev); | |
11609 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 EG |
11610 | |
11611 | if (bp->state != BNX2X_STATE_OPEN) { | |
11612 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
11613 | return; | |
11614 | } | |
11615 | ||
619c5cb6 | 11616 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 EG |
11617 | |
11618 | if (dev->flags & IFF_PROMISC) | |
11619 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
619c5cb6 VZ |
11620 | else if ((dev->flags & IFF_ALLMULTI) || |
11621 | ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) && | |
11622 | CHIP_IS_E1(bp))) | |
34f80b04 | 11623 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
6e30dd4e | 11624 | else { |
381ac16b AE |
11625 | if (IS_PF(bp)) { |
11626 | /* some multicasts */ | |
11627 | if (bnx2x_set_mc_list(bp) < 0) | |
11628 | rx_mode = BNX2X_RX_MODE_ALLMULTI; | |
34f80b04 | 11629 | |
381ac16b AE |
11630 | if (bnx2x_set_uc_list(bp) < 0) |
11631 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
11632 | } else { | |
11633 | /* configuring mcast to a vf involves sleeping (when we | |
11634 | * wait for the pf's response). Since this function is | |
11635 | * called from non sleepable context we must schedule | |
11636 | * a work item for this purpose | |
11637 | */ | |
11638 | smp_mb__before_clear_bit(); | |
11639 | set_bit(BNX2X_SP_RTNL_VFPF_MCAST, | |
11640 | &bp->sp_rtnl_state); | |
11641 | smp_mb__after_clear_bit(); | |
11642 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
11643 | } | |
34f80b04 EG |
11644 | } |
11645 | ||
11646 | bp->rx_mode = rx_mode; | |
614c76df DK |
11647 | /* handle ISCSI SD mode */ |
11648 | if (IS_MF_ISCSI_SD(bp)) | |
11649 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
619c5cb6 VZ |
11650 | |
11651 | /* Schedule the rx_mode command */ | |
11652 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
11653 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
11654 | return; | |
11655 | } | |
11656 | ||
381ac16b AE |
11657 | if (IS_PF(bp)) { |
11658 | bnx2x_set_storm_rx_mode(bp); | |
11659 | } else { | |
11660 | /* configuring rx mode to storms in a vf involves sleeping (when | |
11661 | * we wait for the pf's response). Since this function is | |
11662 | * called from non sleepable context we must schedule | |
11663 | * a work item for this purpose | |
11664 | */ | |
11665 | smp_mb__before_clear_bit(); | |
11666 | set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, | |
11667 | &bp->sp_rtnl_state); | |
11668 | smp_mb__after_clear_bit(); | |
11669 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
11670 | } | |
34f80b04 EG |
11671 | } |
11672 | ||
c18487ee | 11673 | /* called with rtnl_lock */ |
01cd4528 EG |
11674 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
11675 | int devad, u16 addr) | |
a2fbb9ea | 11676 | { |
01cd4528 EG |
11677 | struct bnx2x *bp = netdev_priv(netdev); |
11678 | u16 value; | |
11679 | int rc; | |
a2fbb9ea | 11680 | |
01cd4528 EG |
11681 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
11682 | prtad, devad, addr); | |
a2fbb9ea | 11683 | |
01cd4528 EG |
11684 | /* The HW expects different devad if CL22 is used */ |
11685 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 11686 | |
01cd4528 | 11687 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11688 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
11689 | bnx2x_release_phy_lock(bp); |
11690 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 11691 | |
01cd4528 EG |
11692 | if (!rc) |
11693 | rc = value; | |
11694 | return rc; | |
11695 | } | |
a2fbb9ea | 11696 | |
01cd4528 EG |
11697 | /* called with rtnl_lock */ |
11698 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
11699 | u16 addr, u16 value) | |
11700 | { | |
11701 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
11702 | int rc; |
11703 | ||
51c1a580 MS |
11704 | DP(NETIF_MSG_LINK, |
11705 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
11706 | prtad, devad, addr, value); | |
01cd4528 | 11707 | |
01cd4528 EG |
11708 | /* The HW expects different devad if CL22 is used */ |
11709 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 11710 | |
01cd4528 | 11711 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11712 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
11713 | bnx2x_release_phy_lock(bp); |
11714 | return rc; | |
11715 | } | |
c18487ee | 11716 | |
01cd4528 EG |
11717 | /* called with rtnl_lock */ |
11718 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
11719 | { | |
11720 | struct bnx2x *bp = netdev_priv(dev); | |
11721 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 11722 | |
01cd4528 EG |
11723 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
11724 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 11725 | |
01cd4528 EG |
11726 | if (!netif_running(dev)) |
11727 | return -EAGAIN; | |
11728 | ||
11729 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
11730 | } |
11731 | ||
257ddbda | 11732 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
11733 | static void poll_bnx2x(struct net_device *dev) |
11734 | { | |
11735 | struct bnx2x *bp = netdev_priv(dev); | |
14a15d61 | 11736 | int i; |
a2fbb9ea | 11737 | |
14a15d61 MS |
11738 | for_each_eth_queue(bp, i) { |
11739 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
11740 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); | |
11741 | } | |
a2fbb9ea ET |
11742 | } |
11743 | #endif | |
11744 | ||
614c76df DK |
11745 | static int bnx2x_validate_addr(struct net_device *dev) |
11746 | { | |
11747 | struct bnx2x *bp = netdev_priv(dev); | |
11748 | ||
51c1a580 MS |
11749 | if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { |
11750 | BNX2X_ERR("Non-valid Ethernet address\n"); | |
614c76df | 11751 | return -EADDRNOTAVAIL; |
51c1a580 | 11752 | } |
614c76df DK |
11753 | return 0; |
11754 | } | |
11755 | ||
c64213cd SH |
11756 | static const struct net_device_ops bnx2x_netdev_ops = { |
11757 | .ndo_open = bnx2x_open, | |
11758 | .ndo_stop = bnx2x_close, | |
11759 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 11760 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 11761 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 11762 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 11763 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
11764 | .ndo_do_ioctl = bnx2x_ioctl, |
11765 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
11766 | .ndo_fix_features = bnx2x_fix_features, |
11767 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 11768 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 11769 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
11770 | .ndo_poll_controller = poll_bnx2x, |
11771 | #endif | |
6383c0b3 | 11772 | .ndo_setup_tc = bnx2x_setup_tc, |
6411280a | 11773 | #ifdef CONFIG_BNX2X_SRIOV |
abc5a021 | 11774 | .ndo_set_vf_mac = bnx2x_set_vf_mac, |
6411280a | 11775 | #endif |
55c11941 | 11776 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
11777 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
11778 | #endif | |
c64213cd SH |
11779 | }; |
11780 | ||
1191cb83 | 11781 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
619c5cb6 VZ |
11782 | { |
11783 | struct device *dev = &bp->pdev->dev; | |
11784 | ||
11785 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
11786 | bp->flags |= USING_DAC_FLAG; | |
11787 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
51c1a580 | 11788 | dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); |
619c5cb6 VZ |
11789 | return -EIO; |
11790 | } | |
11791 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
11792 | dev_err(dev, "System does not support DMA, aborting\n"); | |
11793 | return -EIO; | |
11794 | } | |
11795 | ||
11796 | return 0; | |
11797 | } | |
11798 | ||
1ab4434c AE |
11799 | static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, |
11800 | struct net_device *dev, unsigned long board_type) | |
a2fbb9ea | 11801 | { |
a2fbb9ea | 11802 | int rc; |
c22610d0 | 11803 | u32 pci_cfg_dword; |
65087cfe AE |
11804 | bool chip_is_e1x = (board_type == BCM57710 || |
11805 | board_type == BCM57711 || | |
11806 | board_type == BCM57711E); | |
a2fbb9ea ET |
11807 | |
11808 | SET_NETDEV_DEV(dev, &pdev->dev); | |
a2fbb9ea | 11809 | |
34f80b04 EG |
11810 | bp->dev = dev; |
11811 | bp->pdev = pdev; | |
a2fbb9ea ET |
11812 | |
11813 | rc = pci_enable_device(pdev); | |
11814 | if (rc) { | |
cdaa7cb8 VZ |
11815 | dev_err(&bp->pdev->dev, |
11816 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
11817 | goto err_out; |
11818 | } | |
11819 | ||
11820 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
11821 | dev_err(&bp->pdev->dev, |
11822 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
11823 | rc = -ENODEV; |
11824 | goto err_out_disable; | |
11825 | } | |
11826 | ||
1ab4434c AE |
11827 | if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
11828 | dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); | |
a2fbb9ea ET |
11829 | rc = -ENODEV; |
11830 | goto err_out_disable; | |
11831 | } | |
11832 | ||
092a5fc9 YR |
11833 | pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); |
11834 | if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == | |
11835 | PCICFG_REVESION_ID_ERROR_VAL) { | |
11836 | pr_err("PCI device error, probably due to fan failure, aborting\n"); | |
11837 | rc = -ENODEV; | |
11838 | goto err_out_disable; | |
11839 | } | |
11840 | ||
34f80b04 EG |
11841 | if (atomic_read(&pdev->enable_cnt) == 1) { |
11842 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
11843 | if (rc) { | |
cdaa7cb8 VZ |
11844 | dev_err(&bp->pdev->dev, |
11845 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
11846 | goto err_out_disable; |
11847 | } | |
a2fbb9ea | 11848 | |
34f80b04 EG |
11849 | pci_set_master(pdev); |
11850 | pci_save_state(pdev); | |
11851 | } | |
a2fbb9ea | 11852 | |
1ab4434c AE |
11853 | if (IS_PF(bp)) { |
11854 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
11855 | if (bp->pm_cap == 0) { | |
11856 | dev_err(&bp->pdev->dev, | |
11857 | "Cannot find power management capability, aborting\n"); | |
11858 | rc = -EIO; | |
11859 | goto err_out_release; | |
11860 | } | |
a2fbb9ea ET |
11861 | } |
11862 | ||
77c98e6a | 11863 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 11864 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
11865 | rc = -EIO; |
11866 | goto err_out_release; | |
11867 | } | |
11868 | ||
619c5cb6 VZ |
11869 | rc = bnx2x_set_coherency_mask(bp); |
11870 | if (rc) | |
a2fbb9ea | 11871 | goto err_out_release; |
a2fbb9ea | 11872 | |
34f80b04 EG |
11873 | dev->mem_start = pci_resource_start(pdev, 0); |
11874 | dev->base_addr = dev->mem_start; | |
11875 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
11876 | |
11877 | dev->irq = pdev->irq; | |
11878 | ||
275f165f | 11879 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 11880 | if (!bp->regview) { |
cdaa7cb8 VZ |
11881 | dev_err(&bp->pdev->dev, |
11882 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
11883 | rc = -ENOMEM; |
11884 | goto err_out_release; | |
11885 | } | |
11886 | ||
c22610d0 AE |
11887 | /* In E1/E1H use pci device function given by kernel. |
11888 | * In E2/E3 read physical function from ME register since these chips | |
11889 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
11890 | * (depending on hypervisor). | |
11891 | */ | |
11892 | if (chip_is_e1x) | |
11893 | bp->pf_num = PCI_FUNC(pdev->devfn); | |
11894 | else {/* chip is E2/3*/ | |
11895 | pci_read_config_dword(bp->pdev, | |
11896 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
11897 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
11898 | ME_REG_ABS_PF_NUM_SHIFT); | |
11899 | } | |
51c1a580 | 11900 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 11901 | |
a2fbb9ea ET |
11902 | bnx2x_set_power_state(bp, PCI_D0); |
11903 | ||
34f80b04 EG |
11904 | /* clean indirect addresses */ |
11905 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
11906 | PCICFG_VENDOR_ID_OFFSET); | |
a5c53dbc DK |
11907 | /* |
11908 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
11909 | * is not used by the driver. |
11910 | */ | |
1ab4434c AE |
11911 | if (IS_PF(bp)) { |
11912 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
11913 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
11914 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
11915 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
11916 | ||
11917 | if (chip_is_e1x) { | |
11918 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); | |
11919 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
11920 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
11921 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
11922 | } | |
a5c53dbc | 11923 | |
1ab4434c AE |
11924 | /* Enable internal target-read (in case we are probed after PF |
11925 | * FLR). Must be done prior to any BAR read access. Only for | |
11926 | * 57712 and up | |
11927 | */ | |
11928 | if (!chip_is_e1x) | |
11929 | REG_WR(bp, | |
11930 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
a5c53dbc | 11931 | } |
a2fbb9ea | 11932 | |
34f80b04 | 11933 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 11934 | |
c64213cd | 11935 | dev->netdev_ops = &bnx2x_netdev_ops; |
de0c62db | 11936 | bnx2x_set_ethtool_ops(dev); |
5316bc0b | 11937 | |
01789349 JP |
11938 | dev->priv_flags |= IFF_UNICAST_FLT; |
11939 | ||
66371c44 | 11940 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
11941 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
11942 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
11943 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX; | |
66371c44 MM |
11944 | |
11945 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
11946 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
11947 | ||
11948 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX; | |
5316bc0b | 11949 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 11950 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 11951 | |
538dd2e3 MB |
11952 | /* Add Loopback capability to the device */ |
11953 | dev->hw_features |= NETIF_F_LOOPBACK; | |
11954 | ||
98507672 | 11955 | #ifdef BCM_DCBNL |
785b9b1a SR |
11956 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
11957 | #endif | |
11958 | ||
01cd4528 EG |
11959 | /* get_port_hwinfo() will set prtad and mmds properly */ |
11960 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
11961 | bp->mdio.mmds = 0; | |
11962 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
11963 | bp->mdio.dev = dev; | |
11964 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
11965 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
11966 | ||
a2fbb9ea ET |
11967 | return 0; |
11968 | ||
a2fbb9ea | 11969 | err_out_release: |
34f80b04 EG |
11970 | if (atomic_read(&pdev->enable_cnt) == 1) |
11971 | pci_release_regions(pdev); | |
a2fbb9ea ET |
11972 | |
11973 | err_out_disable: | |
11974 | pci_disable_device(pdev); | |
11975 | pci_set_drvdata(pdev, NULL); | |
11976 | ||
11977 | err_out: | |
11978 | return rc; | |
11979 | } | |
11980 | ||
1dd06ae8 | 11981 | static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed) |
25047950 | 11982 | { |
1ab4434c | 11983 | u32 val = 0; |
25047950 | 11984 | |
1ab4434c | 11985 | pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val); |
37f9ce62 | 11986 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 11987 | |
37f9ce62 EG |
11988 | /* return value of 1=2.5GHz 2=5GHz */ |
11989 | *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; | |
25047950 | 11990 | } |
37f9ce62 | 11991 | |
6891dd25 | 11992 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 11993 | { |
37f9ce62 | 11994 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
11995 | struct bnx2x_fw_file_hdr *fw_hdr; |
11996 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 11997 | u32 offset, len, num_ops; |
37f9ce62 | 11998 | u16 *ops_offsets; |
94a78b79 | 11999 | int i; |
37f9ce62 | 12000 | const u8 *fw_ver; |
94a78b79 | 12001 | |
51c1a580 MS |
12002 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
12003 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 12004 | return -EINVAL; |
51c1a580 | 12005 | } |
94a78b79 VZ |
12006 | |
12007 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
12008 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
12009 | ||
12010 | /* Make sure none of the offsets and sizes make us read beyond | |
12011 | * the end of the firmware data */ | |
12012 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
12013 | offset = be32_to_cpu(sections[i].offset); | |
12014 | len = be32_to_cpu(sections[i].len); | |
12015 | if (offset + len > firmware->size) { | |
51c1a580 | 12016 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
12017 | return -EINVAL; |
12018 | } | |
12019 | } | |
12020 | ||
12021 | /* Likewise for the init_ops offsets */ | |
12022 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
12023 | ops_offsets = (u16 *)(firmware->data + offset); | |
12024 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); | |
12025 | ||
12026 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
12027 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 12028 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
12029 | return -EINVAL; |
12030 | } | |
12031 | } | |
12032 | ||
12033 | /* Check FW version */ | |
12034 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
12035 | fw_ver = firmware->data + offset; | |
12036 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
12037 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
12038 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
12039 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
12040 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
12041 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
12042 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
12043 | BCM_5710_FW_MINOR_VERSION, |
12044 | BCM_5710_FW_REVISION_VERSION, | |
12045 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 12046 | return -EINVAL; |
94a78b79 VZ |
12047 | } |
12048 | ||
12049 | return 0; | |
12050 | } | |
12051 | ||
1191cb83 | 12052 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12053 | { |
ab6ad5a4 EG |
12054 | const __be32 *source = (const __be32 *)_source; |
12055 | u32 *target = (u32 *)_target; | |
94a78b79 | 12056 | u32 i; |
94a78b79 VZ |
12057 | |
12058 | for (i = 0; i < n/4; i++) | |
12059 | target[i] = be32_to_cpu(source[i]); | |
12060 | } | |
12061 | ||
12062 | /* | |
12063 | Ops array is stored in the following format: | |
12064 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
12065 | */ | |
1191cb83 | 12066 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12067 | { |
ab6ad5a4 EG |
12068 | const __be32 *source = (const __be32 *)_source; |
12069 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 12070 | u32 i, j, tmp; |
94a78b79 | 12071 | |
ab6ad5a4 | 12072 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
12073 | tmp = be32_to_cpu(source[j]); |
12074 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
12075 | target[i].offset = tmp & 0xffffff; |
12076 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
12077 | } |
12078 | } | |
ab6ad5a4 | 12079 | |
1aa8b471 | 12080 | /* IRO array is stored in the following format: |
523224a3 DK |
12081 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } |
12082 | */ | |
1191cb83 | 12083 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
523224a3 DK |
12084 | { |
12085 | const __be32 *source = (const __be32 *)_source; | |
12086 | struct iro *target = (struct iro *)_target; | |
12087 | u32 i, j, tmp; | |
12088 | ||
12089 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
12090 | target[i].base = be32_to_cpu(source[j]); | |
12091 | j++; | |
12092 | tmp = be32_to_cpu(source[j]); | |
12093 | target[i].m1 = (tmp >> 16) & 0xffff; | |
12094 | target[i].m2 = tmp & 0xffff; | |
12095 | j++; | |
12096 | tmp = be32_to_cpu(source[j]); | |
12097 | target[i].m3 = (tmp >> 16) & 0xffff; | |
12098 | target[i].size = tmp & 0xffff; | |
12099 | j++; | |
12100 | } | |
12101 | } | |
12102 | ||
1191cb83 | 12103 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12104 | { |
ab6ad5a4 EG |
12105 | const __be16 *source = (const __be16 *)_source; |
12106 | u16 *target = (u16 *)_target; | |
94a78b79 | 12107 | u32 i; |
94a78b79 VZ |
12108 | |
12109 | for (i = 0; i < n/2; i++) | |
12110 | target[i] = be16_to_cpu(source[i]); | |
12111 | } | |
12112 | ||
7995c64e JP |
12113 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
12114 | do { \ | |
12115 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
12116 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 12117 | if (!bp->arr) \ |
7995c64e | 12118 | goto lbl; \ |
7995c64e JP |
12119 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
12120 | (u8 *)bp->arr, len); \ | |
12121 | } while (0) | |
94a78b79 | 12122 | |
3b603066 | 12123 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 12124 | { |
c0ea452e | 12125 | const char *fw_file_name; |
94a78b79 | 12126 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 12127 | int rc; |
94a78b79 | 12128 | |
c0ea452e MS |
12129 | if (bp->firmware) |
12130 | return 0; | |
94a78b79 | 12131 | |
c0ea452e MS |
12132 | if (CHIP_IS_E1(bp)) |
12133 | fw_file_name = FW_FILE_NAME_E1; | |
12134 | else if (CHIP_IS_E1H(bp)) | |
12135 | fw_file_name = FW_FILE_NAME_E1H; | |
12136 | else if (!CHIP_IS_E1x(bp)) | |
12137 | fw_file_name = FW_FILE_NAME_E2; | |
12138 | else { | |
12139 | BNX2X_ERR("Unsupported chip revision\n"); | |
12140 | return -EINVAL; | |
12141 | } | |
12142 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 12143 | |
c0ea452e MS |
12144 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
12145 | if (rc) { | |
12146 | BNX2X_ERR("Can't load firmware file %s\n", | |
12147 | fw_file_name); | |
12148 | goto request_firmware_exit; | |
12149 | } | |
eb2afd4a | 12150 | |
c0ea452e MS |
12151 | rc = bnx2x_check_firmware(bp); |
12152 | if (rc) { | |
12153 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
12154 | goto request_firmware_exit; | |
94a78b79 VZ |
12155 | } |
12156 | ||
12157 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
12158 | ||
12159 | /* Initialize the pointers to the init arrays */ | |
12160 | /* Blob */ | |
12161 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
12162 | ||
12163 | /* Opcodes */ | |
12164 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
12165 | ||
12166 | /* Offsets */ | |
ab6ad5a4 EG |
12167 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
12168 | be16_to_cpu_n); | |
94a78b79 VZ |
12169 | |
12170 | /* STORMs firmware */ | |
573f2035 EG |
12171 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
12172 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
12173 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12174 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
12175 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12176 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
12177 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
12178 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
12179 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12180 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
12181 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12182 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
12183 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12184 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
12185 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12186 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
12187 | /* IRO */ |
12188 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
12189 | |
12190 | return 0; | |
ab6ad5a4 | 12191 | |
523224a3 DK |
12192 | iro_alloc_err: |
12193 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
12194 | init_offsets_alloc_err: |
12195 | kfree(bp->init_ops); | |
12196 | init_ops_alloc_err: | |
12197 | kfree(bp->init_data); | |
12198 | request_firmware_exit: | |
12199 | release_firmware(bp->firmware); | |
127d0a19 | 12200 | bp->firmware = NULL; |
94a78b79 VZ |
12201 | |
12202 | return rc; | |
12203 | } | |
12204 | ||
619c5cb6 VZ |
12205 | static void bnx2x_release_firmware(struct bnx2x *bp) |
12206 | { | |
12207 | kfree(bp->init_ops_offsets); | |
12208 | kfree(bp->init_ops); | |
12209 | kfree(bp->init_data); | |
12210 | release_firmware(bp->firmware); | |
eb2afd4a | 12211 | bp->firmware = NULL; |
619c5cb6 VZ |
12212 | } |
12213 | ||
12214 | ||
12215 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { | |
12216 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
12217 | .init_hw_cmn = bnx2x_init_hw_common, | |
12218 | .init_hw_port = bnx2x_init_hw_port, | |
12219 | .init_hw_func = bnx2x_init_hw_func, | |
12220 | ||
12221 | .reset_hw_cmn = bnx2x_reset_common, | |
12222 | .reset_hw_port = bnx2x_reset_port, | |
12223 | .reset_hw_func = bnx2x_reset_func, | |
12224 | ||
12225 | .gunzip_init = bnx2x_gunzip_init, | |
12226 | .gunzip_end = bnx2x_gunzip_end, | |
12227 | ||
12228 | .init_fw = bnx2x_init_firmware, | |
12229 | .release_fw = bnx2x_release_firmware, | |
12230 | }; | |
12231 | ||
12232 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
12233 | { | |
12234 | /* Prepare DMAE related driver resources */ | |
12235 | bnx2x_setup_dmae(bp); | |
12236 | ||
12237 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
12238 | bnx2x_sp(bp, func_rdata), | |
12239 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
12240 | bnx2x_sp(bp, func_afex_rdata), |
12241 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
12242 | &bnx2x_func_sp_drv); |
12243 | } | |
12244 | ||
12245 | /* must be called after sriov-enable */ | |
1191cb83 | 12246 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 12247 | { |
37ae41a9 | 12248 | int cid_count = BNX2X_L2_MAX_CID(bp); |
94a78b79 | 12249 | |
290ca2bb AE |
12250 | if (IS_SRIOV(bp)) |
12251 | cid_count += BNX2X_VF_CIDS; | |
12252 | ||
55c11941 MS |
12253 | if (CNIC_SUPPORT(bp)) |
12254 | cid_count += CNIC_CID_MAX; | |
290ca2bb | 12255 | |
523224a3 DK |
12256 | return roundup(cid_count, QM_CID_ROUND); |
12257 | } | |
f85582f8 | 12258 | |
619c5cb6 | 12259 | /** |
6383c0b3 | 12260 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
12261 | * |
12262 | * @dev: pci device | |
12263 | * | |
12264 | */ | |
55c11941 | 12265 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, |
1ab4434c | 12266 | int cnic_cnt, bool is_vf) |
619c5cb6 | 12267 | { |
1ab4434c AE |
12268 | int pos, index; |
12269 | u16 control = 0; | |
619c5cb6 VZ |
12270 | |
12271 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); | |
6383c0b3 AE |
12272 | |
12273 | /* | |
12274 | * If MSI-X is not supported - return number of SBs needed to support | |
12275 | * one fast path queue: one FP queue + SB for CNIC | |
12276 | */ | |
1ab4434c AE |
12277 | if (!pos) { |
12278 | dev_info(&pdev->dev, "no msix capability found\n"); | |
55c11941 | 12279 | return 1 + cnic_cnt; |
1ab4434c AE |
12280 | } |
12281 | dev_info(&pdev->dev, "msix capability found\n"); | |
619c5cb6 | 12282 | |
6383c0b3 AE |
12283 | /* |
12284 | * The value in the PCI configuration space is the index of the last | |
12285 | * entry, namely one less than the actual size of the table, which is | |
12286 | * exactly what we want to return from this function: number of all SBs | |
12287 | * without the default SB. | |
1ab4434c | 12288 | * For VFs there is no default SB, then we return (index+1). |
6383c0b3 | 12289 | */ |
619c5cb6 | 12290 | pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); |
619c5cb6 | 12291 | |
1ab4434c | 12292 | index = control & PCI_MSIX_FLAGS_QSIZE; |
4bd9b0ff | 12293 | |
1ab4434c AE |
12294 | return is_vf ? index + 1 : index; |
12295 | } | |
523224a3 | 12296 | |
1ab4434c AE |
12297 | static int set_max_cos_est(int chip_id) |
12298 | { | |
12299 | switch (chip_id) { | |
f2e0899f DK |
12300 | case BCM57710: |
12301 | case BCM57711: | |
12302 | case BCM57711E: | |
1ab4434c | 12303 | return BNX2X_MULTI_TX_COS_E1X; |
f2e0899f | 12304 | case BCM57712: |
619c5cb6 | 12305 | case BCM57712_MF: |
1ab4434c AE |
12306 | case BCM57712_VF: |
12307 | return BNX2X_MULTI_TX_COS_E2_E3A0; | |
619c5cb6 VZ |
12308 | case BCM57800: |
12309 | case BCM57800_MF: | |
1ab4434c | 12310 | case BCM57800_VF: |
619c5cb6 VZ |
12311 | case BCM57810: |
12312 | case BCM57810_MF: | |
c3def943 YM |
12313 | case BCM57840_4_10: |
12314 | case BCM57840_2_20: | |
1ab4434c | 12315 | case BCM57840_O: |
c3def943 | 12316 | case BCM57840_MFO: |
1ab4434c | 12317 | case BCM57810_VF: |
619c5cb6 | 12318 | case BCM57840_MF: |
1ab4434c | 12319 | case BCM57840_VF: |
7e8e02df BW |
12320 | case BCM57811: |
12321 | case BCM57811_MF: | |
1ab4434c AE |
12322 | case BCM57811_VF: |
12323 | return BNX2X_MULTI_TX_COS_E3B0; | |
12324 | return 1; | |
f2e0899f | 12325 | default: |
1ab4434c | 12326 | pr_err("Unknown board_type (%d), aborting\n", chip_id); |
870634b0 | 12327 | return -ENODEV; |
f2e0899f | 12328 | } |
1ab4434c | 12329 | } |
f2e0899f | 12330 | |
1ab4434c AE |
12331 | static int set_is_vf(int chip_id) |
12332 | { | |
12333 | switch (chip_id) { | |
12334 | case BCM57712_VF: | |
12335 | case BCM57800_VF: | |
12336 | case BCM57810_VF: | |
12337 | case BCM57840_VF: | |
12338 | case BCM57811_VF: | |
12339 | return true; | |
12340 | default: | |
12341 | return false; | |
12342 | } | |
12343 | } | |
6383c0b3 | 12344 | |
1ab4434c AE |
12345 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); |
12346 | ||
12347 | static int bnx2x_init_one(struct pci_dev *pdev, | |
12348 | const struct pci_device_id *ent) | |
12349 | { | |
12350 | struct net_device *dev = NULL; | |
12351 | struct bnx2x *bp; | |
12352 | int pcie_width, pcie_speed; | |
12353 | int rc, max_non_def_sbs; | |
12354 | int rx_count, tx_count, rss_count, doorbell_size; | |
12355 | int max_cos_est; | |
12356 | bool is_vf; | |
12357 | int cnic_cnt; | |
12358 | ||
12359 | /* An estimated maximum supported CoS number according to the chip | |
12360 | * version. | |
12361 | * We will try to roughly estimate the maximum number of CoSes this chip | |
12362 | * may support in order to minimize the memory allocated for Tx | |
12363 | * netdev_queue's. This number will be accurately calculated during the | |
12364 | * initialization of bp->max_cos based on the chip versions AND chip | |
12365 | * revision in the bnx2x_init_bp(). | |
12366 | */ | |
12367 | max_cos_est = set_max_cos_est(ent->driver_data); | |
12368 | if (max_cos_est < 0) | |
12369 | return max_cos_est; | |
12370 | is_vf = set_is_vf(ent->driver_data); | |
12371 | cnic_cnt = is_vf ? 0 : 1; | |
12372 | ||
12373 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf); | |
6383c0b3 AE |
12374 | |
12375 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
1ab4434c AE |
12376 | rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt; |
12377 | ||
12378 | if (rss_count < 1) | |
12379 | return -EINVAL; | |
6383c0b3 AE |
12380 | |
12381 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
55c11941 | 12382 | rx_count = rss_count + cnic_cnt; |
6383c0b3 | 12383 | |
1ab4434c | 12384 | /* Maximum number of netdev Tx queues: |
37ae41a9 | 12385 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
6383c0b3 | 12386 | */ |
55c11941 | 12387 | tx_count = rss_count * max_cos_est + cnic_cnt; |
f85582f8 | 12388 | |
a2fbb9ea | 12389 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 12390 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 12391 | if (!dev) |
a2fbb9ea ET |
12392 | return -ENOMEM; |
12393 | ||
a2fbb9ea | 12394 | bp = netdev_priv(dev); |
a2fbb9ea | 12395 | |
1ab4434c AE |
12396 | bp->flags = 0; |
12397 | if (is_vf) | |
12398 | bp->flags |= IS_VF_FLAG; | |
12399 | ||
6383c0b3 | 12400 | bp->igu_sb_cnt = max_non_def_sbs; |
1ab4434c | 12401 | bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; |
6383c0b3 | 12402 | bp->msg_enable = debug; |
55c11941 | 12403 | bp->cnic_support = cnic_cnt; |
4bd9b0ff | 12404 | bp->cnic_probe = bnx2x_cnic_probe; |
55c11941 | 12405 | |
6383c0b3 | 12406 | pci_set_drvdata(pdev, dev); |
523224a3 | 12407 | |
1ab4434c | 12408 | rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); |
a2fbb9ea ET |
12409 | if (rc < 0) { |
12410 | free_netdev(dev); | |
12411 | return rc; | |
12412 | } | |
12413 | ||
1ab4434c AE |
12414 | BNX2X_DEV_INFO("This is a %s function\n", |
12415 | IS_PF(bp) ? "physical" : "virtual"); | |
55c11941 | 12416 | BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); |
1ab4434c | 12417 | BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); |
60aa0509 MS |
12418 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
12419 | tx_count, rx_count); | |
12420 | ||
34f80b04 | 12421 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
12422 | if (rc) |
12423 | goto init_one_exit; | |
12424 | ||
1ab4434c AE |
12425 | /* Map doorbells here as we need the real value of bp->max_cos which |
12426 | * is initialized in bnx2x_init_bp() to determine the number of | |
12427 | * l2 connections. | |
6383c0b3 | 12428 | */ |
1ab4434c | 12429 | if (IS_VF(bp)) { |
6411280a AE |
12430 | bnx2x_vf_map_doorbells(bp); |
12431 | rc = bnx2x_vf_pci_alloc(bp); | |
12432 | if (rc) | |
12433 | goto init_one_exit; | |
1ab4434c AE |
12434 | } else { |
12435 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); | |
12436 | if (doorbell_size > pci_resource_len(pdev, 2)) { | |
12437 | dev_err(&bp->pdev->dev, | |
12438 | "Cannot map doorbells, bar size too small, aborting\n"); | |
12439 | rc = -ENOMEM; | |
12440 | goto init_one_exit; | |
12441 | } | |
12442 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
12443 | doorbell_size); | |
37ae41a9 | 12444 | } |
6383c0b3 AE |
12445 | if (!bp->doorbells) { |
12446 | dev_err(&bp->pdev->dev, | |
12447 | "Cannot map doorbell space, aborting\n"); | |
12448 | rc = -ENOMEM; | |
12449 | goto init_one_exit; | |
12450 | } | |
12451 | ||
be1f1ffa AE |
12452 | if (IS_VF(bp)) { |
12453 | rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); | |
12454 | if (rc) | |
12455 | goto init_one_exit; | |
12456 | } | |
12457 | ||
290ca2bb AE |
12458 | /* Enable SRIOV if capability found in configuration space. |
12459 | * Once the generic SR-IOV framework makes it in from the | |
12460 | * pci tree this will be revised, to allow dynamic control | |
12461 | * over the number of VFs. Right now, change the num of vfs | |
12462 | * param below to enable SR-IOV. | |
12463 | */ | |
12464 | rc = bnx2x_iov_init_one(bp, int_mode, 0/*num vfs*/); | |
12465 | if (rc) | |
12466 | goto init_one_exit; | |
12467 | ||
523224a3 | 12468 | /* calc qm_cid_count */ |
6383c0b3 | 12469 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
1ab4434c | 12470 | BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); |
523224a3 | 12471 | |
55c11941 | 12472 | /* disable FCOE L2 queue for E1x*/ |
62ac0dc9 | 12473 | if (CHIP_IS_E1x(bp)) |
ec6ba945 VZ |
12474 | bp->flags |= NO_FCOE_FLAG; |
12475 | ||
477864dd DK |
12476 | /* disable FCOE for 57840 device, until FW supports it */ |
12477 | switch (ent->driver_data) { | |
12478 | case BCM57840_O: | |
12479 | case BCM57840_4_10: | |
12480 | case BCM57840_2_20: | |
12481 | case BCM57840_MFO: | |
12482 | case BCM57840_MF: | |
12483 | bp->flags |= NO_FCOE_FLAG; | |
12484 | } | |
0e8d2ec5 MS |
12485 | |
12486 | /* Set bp->num_queues for MSI-X mode*/ | |
12487 | bnx2x_set_num_queues(bp); | |
12488 | ||
25985edc | 12489 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
0e8d2ec5 | 12490 | * needed. |
d6214d7a | 12491 | */ |
1ab4434c AE |
12492 | rc = bnx2x_set_int_mode(bp); |
12493 | if (rc) { | |
12494 | dev_err(&pdev->dev, "Cannot set interrupts\n"); | |
12495 | goto init_one_exit; | |
12496 | } | |
d6214d7a | 12497 | |
1ab4434c | 12498 | /* register the net device */ |
b340007f VZ |
12499 | rc = register_netdev(dev); |
12500 | if (rc) { | |
12501 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
12502 | goto init_one_exit; | |
12503 | } | |
1ab4434c | 12504 | BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); |
b340007f | 12505 | |
55c11941 | 12506 | |
ec6ba945 VZ |
12507 | if (!NO_FCOE(bp)) { |
12508 | /* Add storage MAC address */ | |
12509 | rtnl_lock(); | |
12510 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
12511 | rtnl_unlock(); | |
12512 | } | |
ec6ba945 | 12513 | |
37f9ce62 | 12514 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
1ab4434c AE |
12515 | BNX2X_DEV_INFO("got pcie width %d and speed %d\n", |
12516 | pcie_width, pcie_speed); | |
d6214d7a | 12517 | |
51c1a580 MS |
12518 | BNX2X_DEV_INFO( |
12519 | "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", | |
94f05b0f JP |
12520 | board_info[ent->driver_data].name, |
12521 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
12522 | pcie_width, | |
12523 | ((!CHIP_IS_E2(bp) && pcie_speed == 2) || | |
12524 | (CHIP_IS_E2(bp) && pcie_speed == 1)) ? | |
12525 | "5GHz (Gen2)" : "2.5GHz", | |
12526 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 12527 | |
a2fbb9ea | 12528 | return 0; |
34f80b04 EG |
12529 | |
12530 | init_one_exit: | |
12531 | if (bp->regview) | |
12532 | iounmap(bp->regview); | |
12533 | ||
1ab4434c | 12534 | if (IS_PF(bp) && bp->doorbells) |
34f80b04 EG |
12535 | iounmap(bp->doorbells); |
12536 | ||
12537 | free_netdev(dev); | |
12538 | ||
12539 | if (atomic_read(&pdev->enable_cnt) == 1) | |
12540 | pci_release_regions(pdev); | |
12541 | ||
12542 | pci_disable_device(pdev); | |
12543 | pci_set_drvdata(pdev, NULL); | |
12544 | ||
12545 | return rc; | |
a2fbb9ea ET |
12546 | } |
12547 | ||
0329aba1 | 12548 | static void bnx2x_remove_one(struct pci_dev *pdev) |
a2fbb9ea ET |
12549 | { |
12550 | struct net_device *dev = pci_get_drvdata(pdev); | |
228241eb ET |
12551 | struct bnx2x *bp; |
12552 | ||
12553 | if (!dev) { | |
cdaa7cb8 | 12554 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); |
228241eb ET |
12555 | return; |
12556 | } | |
228241eb | 12557 | bp = netdev_priv(dev); |
a2fbb9ea | 12558 | |
ec6ba945 VZ |
12559 | /* Delete storage MAC address */ |
12560 | if (!NO_FCOE(bp)) { | |
12561 | rtnl_lock(); | |
12562 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
12563 | rtnl_unlock(); | |
12564 | } | |
ec6ba945 | 12565 | |
98507672 SR |
12566 | #ifdef BCM_DCBNL |
12567 | /* Delete app tlvs from dcbnl */ | |
12568 | bnx2x_dcbnl_update_applist(bp, true); | |
12569 | #endif | |
12570 | ||
a2fbb9ea ET |
12571 | unregister_netdev(dev); |
12572 | ||
084d6cbb | 12573 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
1ab4434c AE |
12574 | if (IS_PF(bp)) |
12575 | bnx2x_set_power_state(bp, PCI_D0); | |
084d6cbb | 12576 | |
d6214d7a DK |
12577 | /* Disable MSI/MSI-X */ |
12578 | bnx2x_disable_msi(bp); | |
f85582f8 | 12579 | |
084d6cbb | 12580 | /* Power off */ |
1ab4434c AE |
12581 | if (IS_PF(bp)) |
12582 | bnx2x_set_power_state(bp, PCI_D3hot); | |
084d6cbb | 12583 | |
72fd0718 | 12584 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 12585 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
290ca2bb AE |
12586 | |
12587 | bnx2x_iov_remove_one(bp); | |
12588 | ||
4513f925 AE |
12589 | /* send message via vfpf channel to release the resources of this vf */ |
12590 | if (IS_VF(bp)) | |
12591 | bnx2x_vfpf_release(bp); | |
72fd0718 | 12592 | |
a2fbb9ea ET |
12593 | if (bp->regview) |
12594 | iounmap(bp->regview); | |
12595 | ||
1ab4434c AE |
12596 | /* for vf doorbells are part of the regview and were unmapped along with |
12597 | * it. FW is only loaded by PF. | |
12598 | */ | |
12599 | if (IS_PF(bp)) { | |
12600 | if (bp->doorbells) | |
12601 | iounmap(bp->doorbells); | |
eb2afd4a | 12602 | |
1ab4434c AE |
12603 | bnx2x_release_firmware(bp); |
12604 | } | |
523224a3 DK |
12605 | bnx2x_free_mem_bp(bp); |
12606 | ||
a2fbb9ea | 12607 | free_netdev(dev); |
34f80b04 EG |
12608 | |
12609 | if (atomic_read(&pdev->enable_cnt) == 1) | |
12610 | pci_release_regions(pdev); | |
12611 | ||
a2fbb9ea ET |
12612 | pci_disable_device(pdev); |
12613 | pci_set_drvdata(pdev, NULL); | |
12614 | } | |
12615 | ||
f8ef6e44 YG |
12616 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
12617 | { | |
12618 | int i; | |
12619 | ||
12620 | bp->state = BNX2X_STATE_ERROR; | |
12621 | ||
12622 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
12623 | ||
55c11941 MS |
12624 | if (CNIC_LOADED(bp)) |
12625 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
12626 | ||
619c5cb6 VZ |
12627 | /* Stop Tx */ |
12628 | bnx2x_tx_disable(bp); | |
12629 | ||
f8ef6e44 | 12630 | bnx2x_netif_stop(bp, 0); |
26614ba5 MS |
12631 | /* Delete all NAPI objects */ |
12632 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
12633 | if (CNIC_LOADED(bp)) |
12634 | bnx2x_del_all_napi_cnic(bp); | |
f8ef6e44 YG |
12635 | |
12636 | del_timer_sync(&bp->timer); | |
619c5cb6 VZ |
12637 | |
12638 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
f8ef6e44 YG |
12639 | |
12640 | /* Release IRQs */ | |
d6214d7a | 12641 | bnx2x_free_irq(bp); |
f8ef6e44 | 12642 | |
f8ef6e44 YG |
12643 | /* Free SKBs, SGEs, TPA pool and driver internals */ |
12644 | bnx2x_free_skbs(bp); | |
523224a3 | 12645 | |
ec6ba945 | 12646 | for_each_rx_queue(bp, i) |
f8ef6e44 | 12647 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); |
d6214d7a | 12648 | |
f8ef6e44 YG |
12649 | bnx2x_free_mem(bp); |
12650 | ||
12651 | bp->state = BNX2X_STATE_CLOSED; | |
12652 | ||
619c5cb6 VZ |
12653 | netif_carrier_off(bp->dev); |
12654 | ||
f8ef6e44 YG |
12655 | return 0; |
12656 | } | |
12657 | ||
12658 | static void bnx2x_eeh_recover(struct bnx2x *bp) | |
12659 | { | |
12660 | u32 val; | |
12661 | ||
12662 | mutex_init(&bp->port.phy_mutex); | |
12663 | ||
f8ef6e44 YG |
12664 | |
12665 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
12666 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
12667 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | |
12668 | BNX2X_ERR("BAD MCP validity signature\n"); | |
f8ef6e44 YG |
12669 | } |
12670 | ||
493adb1f WX |
12671 | /** |
12672 | * bnx2x_io_error_detected - called when PCI error is detected | |
12673 | * @pdev: Pointer to PCI device | |
12674 | * @state: The current pci connection state | |
12675 | * | |
12676 | * This function is called after a PCI bus error affecting | |
12677 | * this device has been detected. | |
12678 | */ | |
12679 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
12680 | pci_channel_state_t state) | |
12681 | { | |
12682 | struct net_device *dev = pci_get_drvdata(pdev); | |
12683 | struct bnx2x *bp = netdev_priv(dev); | |
12684 | ||
12685 | rtnl_lock(); | |
12686 | ||
12687 | netif_device_detach(dev); | |
12688 | ||
07ce50e4 DN |
12689 | if (state == pci_channel_io_perm_failure) { |
12690 | rtnl_unlock(); | |
12691 | return PCI_ERS_RESULT_DISCONNECT; | |
12692 | } | |
12693 | ||
493adb1f | 12694 | if (netif_running(dev)) |
f8ef6e44 | 12695 | bnx2x_eeh_nic_unload(bp); |
493adb1f WX |
12696 | |
12697 | pci_disable_device(pdev); | |
12698 | ||
12699 | rtnl_unlock(); | |
12700 | ||
12701 | /* Request a slot reset */ | |
12702 | return PCI_ERS_RESULT_NEED_RESET; | |
12703 | } | |
12704 | ||
12705 | /** | |
12706 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
12707 | * @pdev: Pointer to PCI device | |
12708 | * | |
12709 | * Restart the card from scratch, as if from a cold-boot. | |
12710 | */ | |
12711 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
12712 | { | |
12713 | struct net_device *dev = pci_get_drvdata(pdev); | |
12714 | struct bnx2x *bp = netdev_priv(dev); | |
12715 | ||
12716 | rtnl_lock(); | |
12717 | ||
12718 | if (pci_enable_device(pdev)) { | |
12719 | dev_err(&pdev->dev, | |
12720 | "Cannot re-enable PCI device after reset\n"); | |
12721 | rtnl_unlock(); | |
12722 | return PCI_ERS_RESULT_DISCONNECT; | |
12723 | } | |
12724 | ||
12725 | pci_set_master(pdev); | |
12726 | pci_restore_state(pdev); | |
12727 | ||
12728 | if (netif_running(dev)) | |
12729 | bnx2x_set_power_state(bp, PCI_D0); | |
12730 | ||
12731 | rtnl_unlock(); | |
12732 | ||
12733 | return PCI_ERS_RESULT_RECOVERED; | |
12734 | } | |
12735 | ||
12736 | /** | |
12737 | * bnx2x_io_resume - called when traffic can start flowing again | |
12738 | * @pdev: Pointer to PCI device | |
12739 | * | |
12740 | * This callback is called when the error recovery driver tells us that | |
12741 | * its OK to resume normal operation. | |
12742 | */ | |
12743 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
12744 | { | |
12745 | struct net_device *dev = pci_get_drvdata(pdev); | |
12746 | struct bnx2x *bp = netdev_priv(dev); | |
12747 | ||
72fd0718 | 12748 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 12749 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
12750 | return; |
12751 | } | |
12752 | ||
493adb1f WX |
12753 | rtnl_lock(); |
12754 | ||
f8ef6e44 YG |
12755 | bnx2x_eeh_recover(bp); |
12756 | ||
493adb1f | 12757 | if (netif_running(dev)) |
f8ef6e44 | 12758 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
12759 | |
12760 | netif_device_attach(dev); | |
12761 | ||
12762 | rtnl_unlock(); | |
12763 | } | |
12764 | ||
3646f0e5 | 12765 | static const struct pci_error_handlers bnx2x_err_handler = { |
493adb1f | 12766 | .error_detected = bnx2x_io_error_detected, |
356e2385 EG |
12767 | .slot_reset = bnx2x_io_slot_reset, |
12768 | .resume = bnx2x_io_resume, | |
493adb1f WX |
12769 | }; |
12770 | ||
a2fbb9ea | 12771 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
12772 | .name = DRV_MODULE_NAME, |
12773 | .id_table = bnx2x_pci_tbl, | |
12774 | .probe = bnx2x_init_one, | |
0329aba1 | 12775 | .remove = bnx2x_remove_one, |
493adb1f WX |
12776 | .suspend = bnx2x_suspend, |
12777 | .resume = bnx2x_resume, | |
12778 | .err_handler = &bnx2x_err_handler, | |
a2fbb9ea ET |
12779 | }; |
12780 | ||
12781 | static int __init bnx2x_init(void) | |
12782 | { | |
dd21ca6d SG |
12783 | int ret; |
12784 | ||
7995c64e | 12785 | pr_info("%s", version); |
938cf541 | 12786 | |
1cf167f2 EG |
12787 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
12788 | if (bnx2x_wq == NULL) { | |
7995c64e | 12789 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
12790 | return -ENOMEM; |
12791 | } | |
12792 | ||
dd21ca6d SG |
12793 | ret = pci_register_driver(&bnx2x_pci_driver); |
12794 | if (ret) { | |
7995c64e | 12795 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
12796 | destroy_workqueue(bnx2x_wq); |
12797 | } | |
12798 | return ret; | |
a2fbb9ea ET |
12799 | } |
12800 | ||
12801 | static void __exit bnx2x_cleanup(void) | |
12802 | { | |
452427b0 | 12803 | struct list_head *pos, *q; |
a2fbb9ea | 12804 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
12805 | |
12806 | destroy_workqueue(bnx2x_wq); | |
452427b0 YM |
12807 | |
12808 | /* Free globablly allocated resources */ | |
12809 | list_for_each_safe(pos, q, &bnx2x_prev_list) { | |
12810 | struct bnx2x_prev_path_list *tmp = | |
12811 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
12812 | list_del(pos); | |
12813 | kfree(tmp); | |
12814 | } | |
a2fbb9ea ET |
12815 | } |
12816 | ||
3deb8167 YR |
12817 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
12818 | { | |
12819 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
12820 | } | |
12821 | ||
a2fbb9ea ET |
12822 | module_init(bnx2x_init); |
12823 | module_exit(bnx2x_cleanup); | |
12824 | ||
619c5cb6 VZ |
12825 | /** |
12826 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
12827 | * | |
12828 | * @bp: driver handle | |
12829 | * @set: set or clear the CAM entry | |
12830 | * | |
12831 | * This function will wait until the ramdord completion returns. | |
12832 | * Return 0 if success, -ENODEV if ramrod doesn't return. | |
12833 | */ | |
1191cb83 | 12834 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
619c5cb6 VZ |
12835 | { |
12836 | unsigned long ramrod_flags = 0; | |
12837 | ||
12838 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
12839 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
12840 | &bp->iscsi_l2_mac_obj, true, | |
12841 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
12842 | } | |
993ac7b5 MC |
12843 | |
12844 | /* count denotes the number of new completions we have seen */ | |
12845 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
12846 | { | |
12847 | struct eth_spe *spe; | |
a052997e | 12848 | int cxt_index, cxt_offset; |
993ac7b5 MC |
12849 | |
12850 | #ifdef BNX2X_STOP_ON_ERROR | |
12851 | if (unlikely(bp->panic)) | |
12852 | return; | |
12853 | #endif | |
12854 | ||
12855 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 12856 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
12857 | bp->cnic_spq_pending -= count; |
12858 | ||
993ac7b5 | 12859 | |
c2bff63f DK |
12860 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
12861 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
12862 | & SPE_HDR_CONN_TYPE) >> | |
12863 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
12864 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
12865 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
12866 | |
12867 | /* Set validation for iSCSI L2 client before sending SETUP | |
12868 | * ramrod | |
12869 | */ | |
12870 | if (type == ETH_CONNECTION_TYPE) { | |
a052997e | 12871 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
37ae41a9 | 12872 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
a052997e | 12873 | ILT_PAGE_CIDS; |
37ae41a9 | 12874 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
a052997e MS |
12875 | (cxt_index * ILT_PAGE_CIDS); |
12876 | bnx2x_set_ctx_validation(bp, | |
12877 | &bp->context[cxt_index]. | |
12878 | vcxt[cxt_offset].eth, | |
37ae41a9 | 12879 | BNX2X_ISCSI_ETH_CID(bp)); |
a052997e | 12880 | } |
c2bff63f DK |
12881 | } |
12882 | ||
619c5cb6 VZ |
12883 | /* |
12884 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
12885 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
12886 | * COMMON ramrods is not more than the EQ and SPQ can |
12887 | * accommodate. | |
c2bff63f | 12888 | */ |
6e30dd4e VZ |
12889 | if (type == ETH_CONNECTION_TYPE) { |
12890 | if (!atomic_read(&bp->cq_spq_left)) | |
12891 | break; | |
12892 | else | |
12893 | atomic_dec(&bp->cq_spq_left); | |
12894 | } else if (type == NONE_CONNECTION_TYPE) { | |
12895 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
12896 | break; |
12897 | else | |
6e30dd4e | 12898 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
12899 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
12900 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
12901 | if (bp->cnic_spq_pending >= |
12902 | bp->cnic_eth_dev.max_kwqe_pending) | |
12903 | break; | |
12904 | else | |
12905 | bp->cnic_spq_pending++; | |
12906 | } else { | |
12907 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
12908 | bnx2x_panic(); | |
993ac7b5 | 12909 | break; |
c2bff63f | 12910 | } |
993ac7b5 MC |
12911 | |
12912 | spe = bnx2x_sp_get_next(bp); | |
12913 | *spe = *bp->cnic_kwq_cons; | |
12914 | ||
51c1a580 | 12915 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
12916 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
12917 | ||
12918 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
12919 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
12920 | else | |
12921 | bp->cnic_kwq_cons++; | |
12922 | } | |
12923 | bnx2x_sp_prod_update(bp); | |
12924 | spin_unlock_bh(&bp->spq_lock); | |
12925 | } | |
12926 | ||
12927 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
12928 | struct kwqe_16 *kwqes[], u32 count) | |
12929 | { | |
12930 | struct bnx2x *bp = netdev_priv(dev); | |
12931 | int i; | |
12932 | ||
12933 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
12934 | if (unlikely(bp->panic)) { |
12935 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 12936 | return -EIO; |
51c1a580 | 12937 | } |
993ac7b5 MC |
12938 | #endif |
12939 | ||
95c6c616 AE |
12940 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
12941 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 12942 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
12943 | return -EAGAIN; |
12944 | } | |
12945 | ||
993ac7b5 MC |
12946 | spin_lock_bh(&bp->spq_lock); |
12947 | ||
12948 | for (i = 0; i < count; i++) { | |
12949 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
12950 | ||
12951 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
12952 | break; | |
12953 | ||
12954 | *bp->cnic_kwq_prod = *spe; | |
12955 | ||
12956 | bp->cnic_kwq_pending++; | |
12957 | ||
51c1a580 | 12958 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 12959 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
12960 | spe->data.update_data_addr.hi, |
12961 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
12962 | bp->cnic_kwq_pending); |
12963 | ||
12964 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
12965 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
12966 | else | |
12967 | bp->cnic_kwq_prod++; | |
12968 | } | |
12969 | ||
12970 | spin_unlock_bh(&bp->spq_lock); | |
12971 | ||
12972 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
12973 | bnx2x_cnic_sp_post(bp, 0); | |
12974 | ||
12975 | return i; | |
12976 | } | |
12977 | ||
12978 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
12979 | { | |
12980 | struct cnic_ops *c_ops; | |
12981 | int rc = 0; | |
12982 | ||
12983 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
12984 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
12985 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
12986 | if (c_ops) |
12987 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
12988 | mutex_unlock(&bp->cnic_mutex); | |
12989 | ||
12990 | return rc; | |
12991 | } | |
12992 | ||
12993 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
12994 | { | |
12995 | struct cnic_ops *c_ops; | |
12996 | int rc = 0; | |
12997 | ||
12998 | rcu_read_lock(); | |
12999 | c_ops = rcu_dereference(bp->cnic_ops); | |
13000 | if (c_ops) | |
13001 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
13002 | rcu_read_unlock(); | |
13003 | ||
13004 | return rc; | |
13005 | } | |
13006 | ||
13007 | /* | |
13008 | * for commands that have no data | |
13009 | */ | |
9f6c9258 | 13010 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
13011 | { |
13012 | struct cnic_ctl_info ctl = {0}; | |
13013 | ||
13014 | ctl.cmd = cmd; | |
13015 | ||
13016 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
13017 | } | |
13018 | ||
619c5cb6 | 13019 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 13020 | { |
619c5cb6 | 13021 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
13022 | |
13023 | /* first we tell CNIC and only then we count this as a completion */ | |
13024 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
13025 | ctl.data.comp.cid = cid; | |
619c5cb6 | 13026 | ctl.data.comp.error = err; |
993ac7b5 MC |
13027 | |
13028 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 13029 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
13030 | } |
13031 | ||
619c5cb6 VZ |
13032 | |
13033 | /* Called with netif_addr_lock_bh() taken. | |
13034 | * Sets an rx_mode config for an iSCSI ETH client. | |
13035 | * Doesn't block. | |
13036 | * Completion should be checked outside. | |
13037 | */ | |
13038 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
13039 | { | |
13040 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
13041 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
13042 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
13043 | ||
13044 | if (start) { | |
13045 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
13046 | * because it's the only way for UIO Queue to accept | |
13047 | * multicasts (in non-promiscuous mode only one Queue per | |
13048 | * function will receive multicast packets (leading in our | |
13049 | * case). | |
13050 | */ | |
13051 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
13052 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
13053 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
13054 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
13055 | ||
13056 | /* Clear STOP_PENDING bit if START is requested */ | |
13057 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
13058 | ||
13059 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
13060 | } else | |
13061 | /* Clear START_PENDING bit if STOP is requested */ | |
13062 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
13063 | ||
13064 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
13065 | set_bit(sched_state, &bp->sp_state); | |
13066 | else { | |
13067 | __set_bit(RAMROD_RX, &ramrod_flags); | |
13068 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
13069 | ramrod_flags); | |
13070 | } | |
13071 | } | |
13072 | ||
13073 | ||
993ac7b5 MC |
13074 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
13075 | { | |
13076 | struct bnx2x *bp = netdev_priv(dev); | |
13077 | int rc = 0; | |
13078 | ||
13079 | switch (ctl->cmd) { | |
13080 | case DRV_CTL_CTXTBL_WR_CMD: { | |
13081 | u32 index = ctl->data.io.offset; | |
13082 | dma_addr_t addr = ctl->data.io.dma_addr; | |
13083 | ||
13084 | bnx2x_ilt_wr(bp, index, addr); | |
13085 | break; | |
13086 | } | |
13087 | ||
c2bff63f DK |
13088 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
13089 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
13090 | |
13091 | bnx2x_cnic_sp_post(bp, count); | |
13092 | break; | |
13093 | } | |
13094 | ||
13095 | /* rtnl_lock is held. */ | |
13096 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
13097 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
13098 | unsigned long sp_bits = 0; | |
13099 | ||
13100 | /* Configure the iSCSI classification object */ | |
13101 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
13102 | cp->iscsi_l2_client_id, | |
13103 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
13104 | bnx2x_sp(bp, mac_rdata), | |
13105 | bnx2x_sp_mapping(bp, mac_rdata), | |
13106 | BNX2X_FILTER_MAC_PENDING, | |
13107 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
13108 | &bp->macs_pool); | |
ec6ba945 | 13109 | |
523224a3 | 13110 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
13111 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
13112 | if (rc) | |
13113 | break; | |
523224a3 DK |
13114 | |
13115 | mmiowb(); | |
13116 | barrier(); | |
13117 | ||
619c5cb6 VZ |
13118 | /* Start accepting on iSCSI L2 ring */ |
13119 | ||
13120 | netif_addr_lock_bh(dev); | |
13121 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
13122 | netif_addr_unlock_bh(dev); | |
13123 | ||
13124 | /* bits to wait on */ | |
13125 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
13126 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
13127 | ||
13128 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
13129 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 13130 | |
993ac7b5 MC |
13131 | break; |
13132 | } | |
13133 | ||
13134 | /* rtnl_lock is held. */ | |
13135 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 13136 | unsigned long sp_bits = 0; |
993ac7b5 | 13137 | |
523224a3 | 13138 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
13139 | netif_addr_lock_bh(dev); |
13140 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
13141 | netif_addr_unlock_bh(dev); | |
13142 | ||
13143 | /* bits to wait on */ | |
13144 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
13145 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
13146 | ||
13147 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
13148 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
13149 | |
13150 | mmiowb(); | |
13151 | barrier(); | |
13152 | ||
13153 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
13154 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
13155 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
13156 | break; |
13157 | } | |
c2bff63f DK |
13158 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
13159 | int count = ctl->data.credit.credit_count; | |
13160 | ||
13161 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 13162 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
13163 | smp_mb__after_atomic_inc(); |
13164 | break; | |
13165 | } | |
1d187b34 | 13166 | case DRV_CTL_ULP_REGISTER_CMD: { |
2e499d3c | 13167 | int ulp_type = ctl->data.register_data.ulp_type; |
1d187b34 BW |
13168 | |
13169 | if (CHIP_IS_E3(bp)) { | |
13170 | int idx = BP_FW_MB_IDX(bp); | |
2e499d3c BW |
13171 | u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
13172 | int path = BP_PATH(bp); | |
13173 | int port = BP_PORT(bp); | |
13174 | int i; | |
13175 | u32 scratch_offset; | |
13176 | u32 *host_addr; | |
1d187b34 | 13177 | |
2e499d3c | 13178 | /* first write capability to shmem2 */ |
1d187b34 BW |
13179 | if (ulp_type == CNIC_ULP_ISCSI) |
13180 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
13181 | else if (ulp_type == CNIC_ULP_FCOE) | |
13182 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
13183 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
2e499d3c BW |
13184 | |
13185 | if ((ulp_type != CNIC_ULP_FCOE) || | |
13186 | (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || | |
13187 | (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) | |
13188 | break; | |
13189 | ||
13190 | /* if reached here - should write fcoe capabilities */ | |
13191 | scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); | |
13192 | if (!scratch_offset) | |
13193 | break; | |
13194 | scratch_offset += offsetof(struct glob_ncsi_oem_data, | |
13195 | fcoe_features[path][port]); | |
13196 | host_addr = (u32 *) &(ctl->data.register_data. | |
13197 | fcoe_features); | |
13198 | for (i = 0; i < sizeof(struct fcoe_capabilities); | |
13199 | i += 4) | |
13200 | REG_WR(bp, scratch_offset + i, | |
13201 | *(host_addr + i/4)); | |
1d187b34 BW |
13202 | } |
13203 | break; | |
13204 | } | |
2e499d3c | 13205 | |
1d187b34 BW |
13206 | case DRV_CTL_ULP_UNREGISTER_CMD: { |
13207 | int ulp_type = ctl->data.ulp_type; | |
13208 | ||
13209 | if (CHIP_IS_E3(bp)) { | |
13210 | int idx = BP_FW_MB_IDX(bp); | |
13211 | u32 cap; | |
13212 | ||
13213 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
13214 | if (ulp_type == CNIC_ULP_ISCSI) | |
13215 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
13216 | else if (ulp_type == CNIC_ULP_FCOE) | |
13217 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
13218 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
13219 | } | |
13220 | break; | |
13221 | } | |
993ac7b5 MC |
13222 | |
13223 | default: | |
13224 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
13225 | rc = -EINVAL; | |
13226 | } | |
13227 | ||
13228 | return rc; | |
13229 | } | |
13230 | ||
9f6c9258 | 13231 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
13232 | { |
13233 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13234 | ||
13235 | if (bp->flags & USING_MSIX_FLAG) { | |
13236 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
13237 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
13238 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
13239 | } else { | |
13240 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
13241 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
13242 | } | |
619c5cb6 | 13243 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
13244 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
13245 | else | |
13246 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
13247 | ||
619c5cb6 VZ |
13248 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
13249 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
13250 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
13251 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 13252 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
13253 | |
13254 | cp->num_irq = 2; | |
13255 | } | |
13256 | ||
37ae41a9 MS |
13257 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
13258 | { | |
13259 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13260 | ||
13261 | ||
13262 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + | |
13263 | bnx2x_cid_ilt_lines(bp); | |
13264 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; | |
13265 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); | |
13266 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); | |
13267 | ||
13268 | if (NO_ISCSI_OOO(bp)) | |
13269 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
13270 | } | |
13271 | ||
993ac7b5 MC |
13272 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
13273 | void *data) | |
13274 | { | |
13275 | struct bnx2x *bp = netdev_priv(dev); | |
13276 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
55c11941 MS |
13277 | int rc; |
13278 | ||
13279 | DP(NETIF_MSG_IFUP, "Register_cnic called\n"); | |
993ac7b5 | 13280 | |
51c1a580 MS |
13281 | if (ops == NULL) { |
13282 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 13283 | return -EINVAL; |
51c1a580 | 13284 | } |
993ac7b5 | 13285 | |
55c11941 MS |
13286 | if (!CNIC_SUPPORT(bp)) { |
13287 | BNX2X_ERR("Can't register CNIC when not supported\n"); | |
13288 | return -EOPNOTSUPP; | |
13289 | } | |
13290 | ||
13291 | if (!CNIC_LOADED(bp)) { | |
13292 | rc = bnx2x_load_cnic(bp); | |
13293 | if (rc) { | |
13294 | BNX2X_ERR("CNIC-related load failed\n"); | |
13295 | return rc; | |
13296 | } | |
13297 | ||
13298 | } | |
13299 | ||
13300 | bp->cnic_enabled = true; | |
13301 | ||
993ac7b5 MC |
13302 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
13303 | if (!bp->cnic_kwq) | |
13304 | return -ENOMEM; | |
13305 | ||
13306 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
13307 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
13308 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
13309 | ||
13310 | bp->cnic_spq_pending = 0; | |
13311 | bp->cnic_kwq_pending = 0; | |
13312 | ||
13313 | bp->cnic_data = data; | |
13314 | ||
13315 | cp->num_irq = 0; | |
619c5cb6 | 13316 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 13317 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 13318 | |
993ac7b5 | 13319 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 13320 | |
993ac7b5 MC |
13321 | rcu_assign_pointer(bp->cnic_ops, ops); |
13322 | ||
13323 | return 0; | |
13324 | } | |
13325 | ||
13326 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
13327 | { | |
13328 | struct bnx2x *bp = netdev_priv(dev); | |
13329 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13330 | ||
13331 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 13332 | cp->drv_state = 0; |
2cfa5a04 | 13333 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
13334 | mutex_unlock(&bp->cnic_mutex); |
13335 | synchronize_rcu(); | |
13336 | kfree(bp->cnic_kwq); | |
13337 | bp->cnic_kwq = NULL; | |
13338 | ||
13339 | return 0; | |
13340 | } | |
13341 | ||
13342 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
13343 | { | |
13344 | struct bnx2x *bp = netdev_priv(dev); | |
13345 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13346 | ||
2ba45142 VZ |
13347 | /* If both iSCSI and FCoE are disabled - return NULL in |
13348 | * order to indicate CNIC that it should not try to work | |
13349 | * with this device. | |
13350 | */ | |
13351 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
13352 | return NULL; | |
13353 | ||
993ac7b5 MC |
13354 | cp->drv_owner = THIS_MODULE; |
13355 | cp->chip_id = CHIP_ID(bp); | |
13356 | cp->pdev = bp->pdev; | |
13357 | cp->io_base = bp->regview; | |
13358 | cp->io_base2 = bp->doorbells; | |
13359 | cp->max_kwqe_pending = 8; | |
523224a3 | 13360 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
13361 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
13362 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 13363 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 13364 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
13365 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
13366 | cp->drv_ctl = bnx2x_drv_ctl; | |
13367 | cp->drv_register_cnic = bnx2x_register_cnic; | |
13368 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
37ae41a9 | 13369 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
619c5cb6 VZ |
13370 | cp->iscsi_l2_client_id = |
13371 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
37ae41a9 | 13372 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
c2bff63f | 13373 | |
2ba45142 VZ |
13374 | if (NO_ISCSI_OOO(bp)) |
13375 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
13376 | ||
13377 | if (NO_ISCSI(bp)) | |
13378 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
13379 | ||
13380 | if (NO_FCOE(bp)) | |
13381 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
13382 | ||
51c1a580 MS |
13383 | BNX2X_DEV_INFO( |
13384 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
13385 | cp->ctx_blk_size, |
13386 | cp->ctx_tbl_offset, | |
13387 | cp->ctx_tbl_len, | |
13388 | cp->starting_cid); | |
993ac7b5 MC |
13389 | return cp; |
13390 | } | |
993ac7b5 | 13391 | |
6411280a | 13392 | u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) |
9b176b6b | 13393 | { |
6411280a AE |
13394 | struct bnx2x *bp = fp->bp; |
13395 | u32 offset = BAR_USTRORM_INTMEM; | |
abc5a021 | 13396 | |
6411280a AE |
13397 | if (IS_VF(bp)) |
13398 | return bnx2x_vf_ustorm_prods_offset(bp, fp); | |
13399 | else if (!CHIP_IS_E1x(bp)) | |
13400 | offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
13401 | else | |
13402 | offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
8d9ac297 | 13403 | |
6411280a | 13404 | return offset; |
8d9ac297 | 13405 | } |
381ac16b | 13406 | |
6411280a AE |
13407 | /* called only on E1H or E2. |
13408 | * When pretending to be PF, the pretend value is the function number 0...7 | |
13409 | * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID | |
13410 | * combination | |
13411 | */ | |
13412 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) | |
381ac16b | 13413 | { |
6411280a | 13414 | u32 pretend_reg; |
381ac16b | 13415 | |
23826850 | 13416 | if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) |
6411280a | 13417 | return -1; |
381ac16b | 13418 | |
6411280a AE |
13419 | /* get my own pretend register */ |
13420 | pretend_reg = bnx2x_get_pretend_reg(bp); | |
13421 | REG_WR(bp, pretend_reg, pretend_func_val); | |
13422 | REG_RD(bp, pretend_reg); | |
381ac16b AE |
13423 | return 0; |
13424 | } |