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bnx2x: 1G sfp+ module handling
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
f1deab50
JP		 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
de0c62db
DK		 20#include <linux/ethtool.h>
21#include <linux/netdevice.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/crc32.h>
de0c62db
DK		 25#include "bnx2x.h"
26#include "bnx2x_cmn.h"
27#include "bnx2x_dump.h"
4a33bc03 28#include "bnx2x_init.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
ec6ba945
VZ		 66};
67
68#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
69
70static const struct {
71 long offset;
72 int size;
73 u32 flags;
74#define STATS_FLAGS_PORT 1
75#define STATS_FLAGS_FUNC 2
76#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
77 char string[ETH_GSTRING_LEN];
78} bnx2x_stats_arr[] = {
79/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_bytes" },
81 { STATS_OFFSET32(error_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
83 { STATS_OFFSET32(total_unicast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
85 { STATS_OFFSET32(total_multicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
87 { STATS_OFFSET32(total_broadcast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
90 8, STATS_FLAGS_PORT, "rx_crc_errors" },
91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
92 8, STATS_FLAGS_PORT, "rx_align_errors" },
93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
94 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
97/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
98 8, STATS_FLAGS_PORT, "rx_fragments" },
99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
100 8, STATS_FLAGS_PORT, "rx_jabbers" },
101 { STATS_OFFSET32(no_buff_discard_hi),
102 8, STATS_FLAGS_BOTH, "rx_discards" },
103 { STATS_OFFSET32(mac_filter_discard),
104 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 105 { STATS_OFFSET32(mf_tag_discard),
106 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
0e898dd7
BW		 107 { STATS_OFFSET32(pfc_frames_received_hi),
108 8, STATS_FLAGS_PORT, "pfc_frames_received" },
109 { STATS_OFFSET32(pfc_frames_sent_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
ec6ba945
VZ		 111 { STATS_OFFSET32(brb_drop_hi),
112 8, STATS_FLAGS_PORT, "rx_brb_discard" },
113 { STATS_OFFSET32(brb_truncate_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
115 { STATS_OFFSET32(pause_frames_received_hi),
116 8, STATS_FLAGS_PORT, "rx_pause_frames" },
117 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
118 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
119 { STATS_OFFSET32(nig_timer_max),
120 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
121/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
122 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
123 { STATS_OFFSET32(rx_skb_alloc_failed),
124 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
125 { STATS_OFFSET32(hw_csum_err),
126 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
127
128 { STATS_OFFSET32(total_bytes_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bytes" },
130 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
131 8, STATS_FLAGS_PORT, "tx_error_bytes" },
132 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
133 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
134 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
136 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
138 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
139 8, STATS_FLAGS_PORT, "tx_mac_errors" },
140 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
141 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
142/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
143 8, STATS_FLAGS_PORT, "tx_single_collisions" },
144 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
147 8, STATS_FLAGS_PORT, "tx_deferred" },
148 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
149 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
150 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_late_collisions" },
152 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_total_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
155 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
157 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
159 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
161 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
162/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
163 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
164 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
165 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
166 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
168 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 169 8, STATS_FLAGS_PORT, "tx_pause_frames" },
170 { STATS_OFFSET32(total_tpa_aggregations_hi),
171 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
172 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
174 { STATS_OFFSET32(total_tpa_bytes_hi),
7a752993
AE		 175 8, STATS_FLAGS_FUNC, "tpa_bytes"},
176 { STATS_OFFSET32(recoverable_error),
177 4, STATS_FLAGS_FUNC, "recoverable_errors" },
178 { STATS_OFFSET32(unrecoverable_error),
179 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
e9939c80
YM		 180 { STATS_OFFSET32(eee_tx_lpi),
181 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
ec6ba945
VZ		 182};
183
184#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 185static int bnx2x_get_port_type(struct bnx2x *bp)
186{
187 int port_type;
188 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
189 switch (bp->link_params.phy[phy_idx].media_type) {
dbef807e
YM		 190 case ETH_PHY_SFPP_10G_FIBER:
191 case ETH_PHY_SFP_1G_FIBER:
1ac9e428
YR		 192 case ETH_PHY_XFP_FIBER:
193 case ETH_PHY_KR:
194 case ETH_PHY_CX4:
195 port_type = PORT_FIBRE;
196 break;
197 case ETH_PHY_DA_TWINAX:
198 port_type = PORT_DA;
199 break;
200 case ETH_PHY_BASE_T:
201 port_type = PORT_TP;
202 break;
203 case ETH_PHY_NOT_PRESENT:
204 port_type = PORT_NONE;
205 break;
206 case ETH_PHY_UNSPECIFIED:
207 default:
208 port_type = PORT_OTHER;
209 break;
210 }
211 return port_type;
212}
ec6ba945 213
de0c62db
DK		 214static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
215{
216 struct bnx2x *bp = netdev_priv(dev);
a22f0788 217 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 218
a22f0788
YR		 219 /* Dual Media boards present all available port types */
220 cmd->supported = bp->port.supported[cfg_idx] |
221 (bp->port.supported[cfg_idx ^ 1] &
222 (SUPPORTED_TP | SUPPORTED_FIBRE));
223 cmd->advertising = bp->port.advertising[cfg_idx];
dbef807e
YM		 224 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
225 ETH_PHY_SFP_1G_FIBER) {
226 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
227 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
228 }
de0c62db 229
38298461
YM		 230 if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) {
231 if (!(bp->flags & MF_FUNC_DIS)) {
232 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
233 cmd->duplex = bp->link_vars.duplex;
234 } else {
235 ethtool_cmd_speed_set(
236 cmd, bp->link_params.req_line_speed[cfg_idx]);
237 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
238 }
239
240 if (IS_MF(bp) && !BP_NOMCP(bp))
241 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
de0c62db 242 } else {
38298461
YM		 243 cmd->duplex = DUPLEX_UNKNOWN;
244 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
de0c62db 245 }
f2e0899f 246
1ac9e428 247 cmd->port = bnx2x_get_port_type(bp);
a22f0788 248
de0c62db
DK		 249 cmd->phy_address = bp->mdio.prtad;
250 cmd->transceiver = XCVR_INTERNAL;
251
a22f0788 252 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 253 cmd->autoneg = AUTONEG_ENABLE;
254 else
255 cmd->autoneg = AUTONEG_DISABLE;
256
9e7e8399
MY		 257 /* Publish LP advertised speeds and FC */
258 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
259 u32 status = bp->link_vars.link_status;
260
261 cmd->lp_advertising |= ADVERTISED_Autoneg;
262 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
263 cmd->lp_advertising |= ADVERTISED_Pause;
264 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
265 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
266
267 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
268 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
269 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
270 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
271 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
272 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
273 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
274 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
275 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
276 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
277 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
278 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
279 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
280 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
281 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
282 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
283 }
284
de0c62db
DK		 285 cmd->maxtxpkt = 0;
286 cmd->maxrxpkt = 0;
287
51c1a580 288 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
f1deab50
JP		 289 " supported 0x%x advertising 0x%x speed %u\n"
290 " duplex %d port %d phy_address %d transceiver %d\n"
291 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 292 cmd->cmd, cmd->supported, cmd->advertising,
293 ethtool_cmd_speed(cmd),
de0c62db
DK		 294 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
295 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
296
297 return 0;
298}
299
300static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
301{
302 struct bnx2x *bp = netdev_priv(dev);
a22f0788 303 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
dbef807e 304 u32 speed, phy_idx;
de0c62db 305
0793f83f 306 if (IS_MF_SD(bp))
de0c62db
DK		 307 return 0;
308
51c1a580 309 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
b3337e4c 310 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 311 " duplex %d port %d phy_address %d transceiver %d\n"
312 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 313 cmd->cmd, cmd->supported, cmd->advertising,
314 ethtool_cmd_speed(cmd),
de0c62db
DK		 315 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
316 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
317
b3337e4c 318 speed = ethtool_cmd_speed(cmd);
0793f83f 319
38298461
YM		 320 /* If recieved a request for an unknown duplex, assume full*/
321 if (cmd->duplex == DUPLEX_UNKNOWN)
322 cmd->duplex = DUPLEX_FULL;
323
0793f83f 324 if (IS_MF_SI(bp)) {
e3835b99 325 u32 part;
0793f83f
DK		 326 u32 line_speed = bp->link_vars.line_speed;
327
328 /* use 10G if no link detected */
329 if (!line_speed)
330 line_speed = 10000;
331
332 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
51c1a580
MS		 333 DP(BNX2X_MSG_ETHTOOL,
334 "To set speed BC %X or higher is required, please upgrade BC\n",
335 REQ_BC_VER_4_SET_MF_BW);
0793f83f
DK		 336 return -EINVAL;
337 }
e3835b99 338
faa6fcbb 339 part = (speed * 100) / line_speed;
e3835b99 340
faa6fcbb 341 if (line_speed < speed || !part) {
51c1a580
MS		 342 DP(BNX2X_MSG_ETHTOOL,
343 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
0793f83f
DK		 344 return -EINVAL;
345 }
0793f83f 346
e3835b99
DK		 347 if (bp->state != BNX2X_STATE_OPEN)
348 /* store value for following "load" */
349 bp->pending_max = part;
350 else
351 bnx2x_update_max_mf_config(bp, part);
0793f83f 352
0793f83f
DK		 353 return 0;
354 }
355
a22f0788
YR		 356 cfg_idx = bnx2x_get_link_cfg_idx(bp);
357 old_multi_phy_config = bp->link_params.multi_phy_config;
358 switch (cmd->port) {
359 case PORT_TP:
360 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
361 break; /* no port change */
362
363 if (!(bp->port.supported[0] & SUPPORTED_TP ||
364 bp->port.supported[1] & SUPPORTED_TP)) {
51c1a580 365 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 366 return -EINVAL;
367 }
368 bp->link_params.multi_phy_config &=
369 ~PORT_HW_CFG_PHY_SELECTION_MASK;
370 if (bp->link_params.multi_phy_config &
371 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
372 bp->link_params.multi_phy_config |=
373 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
374 else
375 bp->link_params.multi_phy_config |=
376 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
377 break;
378 case PORT_FIBRE:
bfdb5823 379 case PORT_DA:
a22f0788
YR		 380 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
381 break; /* no port change */
382
383 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
384 bp->port.supported[1] & SUPPORTED_FIBRE)) {
51c1a580 385 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 386 return -EINVAL;
387 }
388 bp->link_params.multi_phy_config &=
389 ~PORT_HW_CFG_PHY_SELECTION_MASK;
390 if (bp->link_params.multi_phy_config &
391 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
392 bp->link_params.multi_phy_config |=
393 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
394 else
395 bp->link_params.multi_phy_config |=
396 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
397 break;
398 default:
51c1a580 399 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
a22f0788
YR		 400 return -EINVAL;
401 }
2f751a80 402 /* Save new config in case command complete successully */
a22f0788
YR		 403 new_multi_phy_config = bp->link_params.multi_phy_config;
404 /* Get the new cfg_idx */
405 cfg_idx = bnx2x_get_link_cfg_idx(bp);
406 /* Restore old config in case command failed */
407 bp->link_params.multi_phy_config = old_multi_phy_config;
51c1a580 408 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
a22f0788 409
de0c62db 410 if (cmd->autoneg == AUTONEG_ENABLE) {
75318327
YR		 411 u32 an_supported_speed = bp->port.supported[cfg_idx];
412 if (bp->link_params.phy[EXT_PHY1].type ==
413 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
414 an_supported_speed |= (SUPPORTED_100baseT_Half |
415 SUPPORTED_100baseT_Full);
a22f0788 416 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 417 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
de0c62db
DK		 418 return -EINVAL;
419 }
420
421 /* advertise the requested speed and duplex if supported */
75318327 422 if (cmd->advertising & ~an_supported_speed) {
51c1a580
MS		 423 DP(BNX2X_MSG_ETHTOOL,
424 "Advertisement parameters are not supported\n");
8d661637
YR		 425 return -EINVAL;
426 }
de0c62db 427
a22f0788 428 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
8d661637
YR		 429 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
430 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
de0c62db 431 cmd->advertising);
8d661637
YR		 432 if (cmd->advertising) {
433
434 bp->link_params.speed_cap_mask[cfg_idx] = 0;
435 if (cmd->advertising & ADVERTISED_10baseT_Half) {
436 bp->link_params.speed_cap_mask[cfg_idx] |=
437 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
438 }
439 if (cmd->advertising & ADVERTISED_10baseT_Full)
440 bp->link_params.speed_cap_mask[cfg_idx] |=
441 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
de0c62db 442
8d661637
YR		 443 if (cmd->advertising & ADVERTISED_100baseT_Full)
444 bp->link_params.speed_cap_mask[cfg_idx] |=
445 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
446
447 if (cmd->advertising & ADVERTISED_100baseT_Half) {
448 bp->link_params.speed_cap_mask[cfg_idx] |=
449 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
450 }
451 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
452 bp->link_params.speed_cap_mask[cfg_idx] |=
453 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
454 }
455 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
456 ADVERTISED_1000baseKX_Full))
457 bp->link_params.speed_cap_mask[cfg_idx] |=
458 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
459
460 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
461 ADVERTISED_10000baseKX4_Full |
462 ADVERTISED_10000baseKR_Full))
463 bp->link_params.speed_cap_mask[cfg_idx] |=
464 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
465 }
de0c62db
DK		 466 } else { /* forced speed */
467 /* advertise the requested speed and duplex if supported */
a22f0788 468 switch (speed) {
de0c62db
DK		 469 case SPEED_10:
470 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 471 if (!(bp->port.supported[cfg_idx] &
de0c62db 472 SUPPORTED_10baseT_Full)) {
51c1a580 473 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 474 "10M full not supported\n");
475 return -EINVAL;
476 }
477
478 advertising = (ADVERTISED_10baseT_Full |
479 ADVERTISED_TP);
480 } else {
a22f0788 481 if (!(bp->port.supported[cfg_idx] &
de0c62db 482 SUPPORTED_10baseT_Half)) {
51c1a580 483 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 484 "10M half not supported\n");
485 return -EINVAL;
486 }
487
488 advertising = (ADVERTISED_10baseT_Half |
489 ADVERTISED_TP);
490 }
491 break;
492
493 case SPEED_100:
494 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 495 if (!(bp->port.supported[cfg_idx] &
de0c62db 496 SUPPORTED_100baseT_Full)) {
51c1a580 497 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 498 "100M full not supported\n");
499 return -EINVAL;
500 }
501
502 advertising = (ADVERTISED_100baseT_Full |
503 ADVERTISED_TP);
504 } else {
a22f0788 505 if (!(bp->port.supported[cfg_idx] &
de0c62db 506 SUPPORTED_100baseT_Half)) {
51c1a580 507 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 508 "100M half not supported\n");
509 return -EINVAL;
510 }
511
512 advertising = (ADVERTISED_100baseT_Half |
513 ADVERTISED_TP);
514 }
515 break;
516
517 case SPEED_1000:
518 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 519 DP(BNX2X_MSG_ETHTOOL,
520 "1G half not supported\n");
de0c62db
DK		 521 return -EINVAL;
522 }
523
a22f0788
YR		 524 if (!(bp->port.supported[cfg_idx] &
525 SUPPORTED_1000baseT_Full)) {
51c1a580
MS		 526 DP(BNX2X_MSG_ETHTOOL,
527 "1G full not supported\n");
de0c62db
DK		 528 return -EINVAL;
529 }
530
531 advertising = (ADVERTISED_1000baseT_Full |
532 ADVERTISED_TP);
533 break;
534
535 case SPEED_2500:
536 if (cmd->duplex != DUPLEX_FULL) {
51c1a580 537 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 538 "2.5G half not supported\n");
539 return -EINVAL;
540 }
541
a22f0788
YR		 542 if (!(bp->port.supported[cfg_idx]
543 & SUPPORTED_2500baseX_Full)) {
51c1a580 544 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 545 "2.5G full not supported\n");
546 return -EINVAL;
547 }
548
549 advertising = (ADVERTISED_2500baseX_Full |
550 ADVERTISED_TP);
551 break;
552
553 case SPEED_10000:
554 if (cmd->duplex != DUPLEX_FULL) {
51c1a580
MS		 555 DP(BNX2X_MSG_ETHTOOL,
556 "10G half not supported\n");
de0c62db
DK		 557 return -EINVAL;
558 }
dbef807e 559 phy_idx = bnx2x_get_cur_phy_idx(bp);
a22f0788 560 if (!(bp->port.supported[cfg_idx]
dbef807e
YM		 561 & SUPPORTED_10000baseT_Full) ||
562 (bp->link_params.phy[phy_idx].media_type ==
563 ETH_PHY_SFP_1G_FIBER)) {
51c1a580
MS		 564 DP(BNX2X_MSG_ETHTOOL,
565 "10G full not supported\n");
de0c62db
DK		 566 return -EINVAL;
567 }
568
569 advertising = (ADVERTISED_10000baseT_Full |
570 ADVERTISED_FIBRE);
571 break;
572
573 default:
51c1a580 574 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
de0c62db
DK		 575 return -EINVAL;
576 }
577
a22f0788
YR		 578 bp->link_params.req_line_speed[cfg_idx] = speed;
579 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
580 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 581 }
582
51c1a580 583 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
f1deab50 584 " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 585 bp->link_params.req_line_speed[cfg_idx],
586 bp->link_params.req_duplex[cfg_idx],
587 bp->port.advertising[cfg_idx]);
de0c62db 588
a22f0788
YR		 589 /* Set new config */
590 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 591 if (netif_running(dev)) {
592 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
593 bnx2x_link_set(bp);
594 }
595
596 return 0;
597}
598
599#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
600#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 601#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
0fea29c1
VZ		 602#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
603#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
604
1191cb83
ED		 605static bool bnx2x_is_reg_online(struct bnx2x *bp,
606 const struct reg_addr *reg_info)
0fea29c1
VZ		 607{
608 if (CHIP_IS_E1(bp))
609 return IS_E1_ONLINE(reg_info->info);
610 else if (CHIP_IS_E1H(bp))
611 return IS_E1H_ONLINE(reg_info->info);
612 else if (CHIP_IS_E2(bp))
613 return IS_E2_ONLINE(reg_info->info);
614 else if (CHIP_IS_E3A0(bp))
615 return IS_E3_ONLINE(reg_info->info);
616 else if (CHIP_IS_E3B0(bp))
617 return IS_E3B0_ONLINE(reg_info->info);
618 else
619 return false;
620}
621
622/******* Paged registers info selectors ********/
1191cb83 623static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
0fea29c1
VZ		 624{
625 if (CHIP_IS_E2(bp))
626 return page_vals_e2;
627 else if (CHIP_IS_E3(bp))
628 return page_vals_e3;
629 else
630 return NULL;
631}
632
1191cb83 633static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
0fea29c1
VZ		 634{
635 if (CHIP_IS_E2(bp))
636 return PAGE_MODE_VALUES_E2;
637 else if (CHIP_IS_E3(bp))
638 return PAGE_MODE_VALUES_E3;
639 else
640 return 0;
641}
642
1191cb83 643static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
0fea29c1
VZ		 644{
645 if (CHIP_IS_E2(bp))
646 return page_write_regs_e2;
647 else if (CHIP_IS_E3(bp))
648 return page_write_regs_e3;
649 else
650 return NULL;
651}
652
1191cb83 653static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
0fea29c1
VZ		 654{
655 if (CHIP_IS_E2(bp))
656 return PAGE_WRITE_REGS_E2;
657 else if (CHIP_IS_E3(bp))
658 return PAGE_WRITE_REGS_E3;
659 else
660 return 0;
661}
662
1191cb83 663static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
0fea29c1
VZ		 664{
665 if (CHIP_IS_E2(bp))
666 return page_read_regs_e2;
667 else if (CHIP_IS_E3(bp))
668 return page_read_regs_e3;
669 else
670 return NULL;
671}
672
1191cb83 673static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
0fea29c1
VZ		 674{
675 if (CHIP_IS_E2(bp))
676 return PAGE_READ_REGS_E2;
677 else if (CHIP_IS_E3(bp))
678 return PAGE_READ_REGS_E3;
679 else
680 return 0;
681}
682
1191cb83 683static int __bnx2x_get_regs_len(struct bnx2x *bp)
0fea29c1
VZ		 684{
685 int num_pages = __bnx2x_get_page_reg_num(bp);
686 int page_write_num = __bnx2x_get_page_write_num(bp);
687 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
688 int page_read_num = __bnx2x_get_page_read_num(bp);
689 int regdump_len = 0;
690 int i, j, k;
691
692 for (i = 0; i < REGS_COUNT; i++)
693 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
694 regdump_len += reg_addrs[i].size;
695
696 for (i = 0; i < num_pages; i++)
697 for (j = 0; j < page_write_num; j++)
698 for (k = 0; k < page_read_num; k++)
699 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
700 regdump_len += page_read_addr[k].size;
701
702 return regdump_len;
703}
de0c62db
DK		 704
705static int bnx2x_get_regs_len(struct net_device *dev)
706{
707 struct bnx2x *bp = netdev_priv(dev);
708 int regdump_len = 0;
de0c62db 709
0fea29c1 710 regdump_len = __bnx2x_get_regs_len(bp);
de0c62db
DK		 711 regdump_len *= 4;
712 regdump_len += sizeof(struct dump_hdr);
713
714 return regdump_len;
715}
716
0fea29c1
VZ		 717/**
718 * bnx2x_read_pages_regs - read "paged" registers
719 *
720 * @bp device handle
721 * @p output buffer
722 *
723 * Reads "paged" memories: memories that may only be read by first writing to a
724 * specific address ("write address") and then reading from a specific address
725 * ("read address"). There may be more than one write address per "page" and
726 * more than one read address per write address.
727 */
1191cb83 728static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
f2e0899f
DK		 729{
730 u32 i, j, k, n;
0fea29c1
VZ		 731 /* addresses of the paged registers */
732 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
733 /* number of paged registers */
734 int num_pages = __bnx2x_get_page_reg_num(bp);
735 /* write addresses */
736 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
737 /* number of write addresses */
738 int write_num = __bnx2x_get_page_write_num(bp);
739 /* read addresses info */
740 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
741 /* number of read addresses */
742 int read_num = __bnx2x_get_page_read_num(bp);
743
744 for (i = 0; i < num_pages; i++) {
745 for (j = 0; j < write_num; j++) {
746 REG_WR(bp, write_addr[j], page_addr[i]);
747 for (k = 0; k < read_num; k++)
748 if (bnx2x_is_reg_online(bp, &read_addr[k]))
f2e0899f 749 for (n = 0; n <
0fea29c1 750 read_addr[k].size; n++)
f2e0899f 751 *p++ = REG_RD(bp,
0fea29c1 752 read_addr[k].addr + n*4);
f2e0899f
DK		 753 }
754 }
755}
756
1191cb83 757static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
0fea29c1
VZ		 758{
759 u32 i, j;
760
761 /* Read the regular registers */
762 for (i = 0; i < REGS_COUNT; i++)
763 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
764 for (j = 0; j < reg_addrs[i].size; j++)
765 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
766
767 /* Read "paged" registes */
768 bnx2x_read_pages_regs(bp, p);
769}
770
de0c62db
DK		 771static void bnx2x_get_regs(struct net_device *dev,
772 struct ethtool_regs *regs, void *_p)
773{
0fea29c1 774 u32 *p = _p;
de0c62db
DK		 775 struct bnx2x *bp = netdev_priv(dev);
776 struct dump_hdr dump_hdr = {0};
777
778 regs->version = 0;
779 memset(p, 0, regs->len);
780
781 if (!netif_running(bp->dev))
782 return;
783
4a33bc03
VZ		 784 /* Disable parity attentions as long as following dump may
785 * cause false alarms by reading never written registers. We
786 * will re-enable parity attentions right after the dump.
787 */
788 bnx2x_disable_blocks_parity(bp);
789
de0c62db
DK		 790 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
791 dump_hdr.dump_sign = dump_sign_all;
792 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
793 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
794 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
795 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 796
797 if (CHIP_IS_E1(bp))
798 dump_hdr.info = RI_E1_ONLINE;
799 else if (CHIP_IS_E1H(bp))
800 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 801 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 802 dump_hdr.info = RI_E2_ONLINE |
803 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 804
805 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
806 p += dump_hdr.hdr_size + 1;
807
0fea29c1
VZ		 808 /* Actually read the registers */
809 __bnx2x_get_regs(bp, p);
810
4a33bc03
VZ		 811 /* Re-enable parity attentions */
812 bnx2x_clear_blocks_parity(bp);
c9ee9206 813 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 814}
815
de0c62db
DK		 816static void bnx2x_get_drvinfo(struct net_device *dev,
817 struct ethtool_drvinfo *info)
818{
819 struct bnx2x *bp = netdev_priv(dev);
820 u8 phy_fw_ver[PHY_FW_VER_LEN];
821
68aad78c
RJ		 822 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
823 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
de0c62db
DK		 824
825 phy_fw_ver[0] = '\0';
a1e785e0
MY		 826 bnx2x_get_ext_phy_fw_version(&bp->link_params,
827 phy_fw_ver, PHY_FW_VER_LEN);
68aad78c 828 strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
de0c62db
DK		 829 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
830 "bc %d.%d.%d%s%s",
831 (bp->common.bc_ver & 0xff0000) >> 16,
832 (bp->common.bc_ver & 0xff00) >> 8,
833 (bp->common.bc_ver & 0xff),
834 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
68aad78c 835 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
de0c62db 836 info->n_stats = BNX2X_NUM_STATS;
cf2c1df6 837 info->testinfo_len = BNX2X_NUM_TESTS(bp);
de0c62db
DK		 838 info->eedump_len = bp->common.flash_size;
839 info->regdump_len = bnx2x_get_regs_len(dev);
840}
841
842static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
843{
844 struct bnx2x *bp = netdev_priv(dev);
845
846 if (bp->flags & NO_WOL_FLAG) {
847 wol->supported = 0;
848 wol->wolopts = 0;
849 } else {
850 wol->supported = WAKE_MAGIC;
851 if (bp->wol)
852 wol->wolopts = WAKE_MAGIC;
853 else
854 wol->wolopts = 0;
855 }
856 memset(&wol->sopass, 0, sizeof(wol->sopass));
857}
858
859static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
860{
861 struct bnx2x *bp = netdev_priv(dev);
862
51c1a580
MS		 863 if (wol->wolopts & ~WAKE_MAGIC) {
864 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 865 return -EINVAL;
51c1a580 866 }
de0c62db
DK		 867
868 if (wol->wolopts & WAKE_MAGIC) {
51c1a580
MS		 869 if (bp->flags & NO_WOL_FLAG) {
870 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
de0c62db 871 return -EINVAL;
51c1a580 872 }
de0c62db
DK		 873 bp->wol = 1;
874 } else
875 bp->wol = 0;
876
877 return 0;
878}
879
880static u32 bnx2x_get_msglevel(struct net_device *dev)
881{
882 struct bnx2x *bp = netdev_priv(dev);
883
884 return bp->msg_enable;
885}
886
887static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
888{
889 struct bnx2x *bp = netdev_priv(dev);
890
7a25cc73
DK		 891 if (capable(CAP_NET_ADMIN)) {
892 /* dump MCP trace */
893 if (level & BNX2X_MSG_MCP)
894 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 895 bp->msg_enable = level;
7a25cc73 896 }
de0c62db
DK		 897}
898
899static int bnx2x_nway_reset(struct net_device *dev)
900{
901 struct bnx2x *bp = netdev_priv(dev);
902
903 if (!bp->port.pmf)
904 return 0;
905
906 if (netif_running(dev)) {
907 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
908 bnx2x_link_set(bp);
909 }
910
911 return 0;
912}
913
914static u32 bnx2x_get_link(struct net_device *dev)
915{
916 struct bnx2x *bp = netdev_priv(dev);
917
f2e0899f 918 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 919 return 0;
920
921 return bp->link_vars.link_up;
922}
923
924static int bnx2x_get_eeprom_len(struct net_device *dev)
925{
926 struct bnx2x *bp = netdev_priv(dev);
927
928 return bp->common.flash_size;
929}
930
f16da43b
AE		 931/* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
932 * we done things the other way around, if two pfs from the same port would
933 * attempt to access nvram at the same time, we could run into a scenario such
934 * as:
935 * pf A takes the port lock.
936 * pf B succeeds in taking the same lock since they are from the same port.
937 * pf A takes the per pf misc lock. Performs eeprom access.
938 * pf A finishes. Unlocks the per pf misc lock.
939 * Pf B takes the lock and proceeds to perform it's own access.
940 * pf A unlocks the per port lock, while pf B is still working (!).
941 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
942 * acess corrupted by pf B).*
943 */
de0c62db
DK		 944static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
945{
946 int port = BP_PORT(bp);
947 int count, i;
f16da43b
AE		 948 u32 val;
949
950 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
951 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 952
953 /* adjust timeout for emulation/FPGA */
754a2f52 954 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 955 if (CHIP_REV_IS_SLOW(bp))
956 count *= 100;
957
958 /* request access to nvram interface */
959 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
960 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
961
962 for (i = 0; i < count*10; i++) {
963 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
964 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
965 break;
966
967 udelay(5);
968 }
969
970 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
51c1a580
MS		 971 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
972 "cannot get access to nvram interface\n");
de0c62db
DK		 973 return -EBUSY;
974 }
975
976 return 0;
977}
978
979static int bnx2x_release_nvram_lock(struct bnx2x *bp)
980{
981 int port = BP_PORT(bp);
982 int count, i;
f16da43b 983 u32 val;
de0c62db
DK		 984
985 /* adjust timeout for emulation/FPGA */
754a2f52 986 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 987 if (CHIP_REV_IS_SLOW(bp))
988 count *= 100;
989
990 /* relinquish nvram interface */
991 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
992 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
993
994 for (i = 0; i < count*10; i++) {
995 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
996 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
997 break;
998
999 udelay(5);
1000 }
1001
1002 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
51c1a580
MS		 1003 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1004 "cannot free access to nvram interface\n");
de0c62db
DK		 1005 return -EBUSY;
1006 }
1007
f16da43b
AE		 1008 /* release HW lock: protect against other PFs in PF Direct Assignment */
1009 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
de0c62db
DK		 1010 return 0;
1011}
1012
1013static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1014{
1015 u32 val;
1016
1017 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1018
1019 /* enable both bits, even on read */
1020 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1021 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1022 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1023}
1024
1025static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1026{
1027 u32 val;
1028
1029 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1030
1031 /* disable both bits, even after read */
1032 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1033 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1034 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1035}
1036
1037static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1038 u32 cmd_flags)
1039{
1040 int count, i, rc;
1041 u32 val;
1042
1043 /* build the command word */
1044 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1045
1046 /* need to clear DONE bit separately */
1047 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1048
1049 /* address of the NVRAM to read from */
1050 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1051 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1052
1053 /* issue a read command */
1054 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1055
1056 /* adjust timeout for emulation/FPGA */
754a2f52 1057 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1058 if (CHIP_REV_IS_SLOW(bp))
1059 count *= 100;
1060
1061 /* wait for completion */
1062 *ret_val = 0;
1063 rc = -EBUSY;
1064 for (i = 0; i < count; i++) {
1065 udelay(5);
1066 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1067
1068 if (val & MCPR_NVM_COMMAND_DONE) {
1069 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1070 /* we read nvram data in cpu order
1071 * but ethtool sees it as an array of bytes
1072 * converting to big-endian will do the work */
1073 *ret_val = cpu_to_be32(val);
1074 rc = 0;
1075 break;
1076 }
1077 }
51c1a580
MS		 1078 if (rc == -EBUSY)
1079 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1080 "nvram read timeout expired\n");
de0c62db
DK		 1081 return rc;
1082}
1083
1084static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1085 int buf_size)
1086{
1087 int rc;
1088 u32 cmd_flags;
1089 __be32 val;
1090
1091 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1092 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1093 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1094 offset, buf_size);
1095 return -EINVAL;
1096 }
1097
1098 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1099 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1100 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1101 offset, buf_size, bp->common.flash_size);
1102 return -EINVAL;
1103 }
1104
1105 /* request access to nvram interface */
1106 rc = bnx2x_acquire_nvram_lock(bp);
1107 if (rc)
1108 return rc;
1109
1110 /* enable access to nvram interface */
1111 bnx2x_enable_nvram_access(bp);
1112
1113 /* read the first word(s) */
1114 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1115 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1116 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1117 memcpy(ret_buf, &val, 4);
1118
1119 /* advance to the next dword */
1120 offset += sizeof(u32);
1121 ret_buf += sizeof(u32);
1122 buf_size -= sizeof(u32);
1123 cmd_flags = 0;
1124 }
1125
1126 if (rc == 0) {
1127 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1128 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1129 memcpy(ret_buf, &val, 4);
1130 }
1131
1132 /* disable access to nvram interface */
1133 bnx2x_disable_nvram_access(bp);
1134 bnx2x_release_nvram_lock(bp);
1135
1136 return rc;
1137}
1138
1139static int bnx2x_get_eeprom(struct net_device *dev,
1140 struct ethtool_eeprom *eeprom, u8 *eebuf)
1141{
1142 struct bnx2x *bp = netdev_priv(dev);
1143 int rc;
1144
51c1a580
MS		 1145 if (!netif_running(dev)) {
1146 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1147 "cannot access eeprom when the interface is down\n");
de0c62db 1148 return -EAGAIN;
51c1a580 1149 }
de0c62db 1150
51c1a580 1151 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1152 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1153 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1154 eeprom->len, eeprom->len);
1155
1156 /* parameters already validated in ethtool_get_eeprom */
1157
1158 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1159
1160 return rc;
1161}
1162
1163static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1164 u32 cmd_flags)
1165{
1166 int count, i, rc;
1167
1168 /* build the command word */
1169 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1170
1171 /* need to clear DONE bit separately */
1172 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1173
1174 /* write the data */
1175 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1176
1177 /* address of the NVRAM to write to */
1178 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1179 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1180
1181 /* issue the write command */
1182 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1183
1184 /* adjust timeout for emulation/FPGA */
754a2f52 1185 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1186 if (CHIP_REV_IS_SLOW(bp))
1187 count *= 100;
1188
1189 /* wait for completion */
1190 rc = -EBUSY;
1191 for (i = 0; i < count; i++) {
1192 udelay(5);
1193 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1194 if (val & MCPR_NVM_COMMAND_DONE) {
1195 rc = 0;
1196 break;
1197 }
1198 }
1199
51c1a580
MS		 1200 if (rc == -EBUSY)
1201 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1202 "nvram write timeout expired\n");
de0c62db
DK		 1203 return rc;
1204}
1205
1206#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1207
1208static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1209 int buf_size)
1210{
1211 int rc;
1212 u32 cmd_flags;
1213 u32 align_offset;
1214 __be32 val;
1215
1216 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1217 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1218 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1219 offset, buf_size, bp->common.flash_size);
1220 return -EINVAL;
1221 }
1222
1223 /* request access to nvram interface */
1224 rc = bnx2x_acquire_nvram_lock(bp);
1225 if (rc)
1226 return rc;
1227
1228 /* enable access to nvram interface */
1229 bnx2x_enable_nvram_access(bp);
1230
1231 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1232 align_offset = (offset & ~0x03);
1233 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1234
1235 if (rc == 0) {
1236 val &= ~(0xff << BYTE_OFFSET(offset));
1237 val |= (*data_buf << BYTE_OFFSET(offset));
1238
1239 /* nvram data is returned as an array of bytes
1240 * convert it back to cpu order */
1241 val = be32_to_cpu(val);
1242
1243 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1244 cmd_flags);
1245 }
1246
1247 /* disable access to nvram interface */
1248 bnx2x_disable_nvram_access(bp);
1249 bnx2x_release_nvram_lock(bp);
1250
1251 return rc;
1252}
1253
1254static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1255 int buf_size)
1256{
1257 int rc;
1258 u32 cmd_flags;
1259 u32 val;
1260 u32 written_so_far;
1261
1262 if (buf_size == 1) /* ethtool */
1263 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1264
1265 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
51c1a580 1266 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 1267 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1268 offset, buf_size);
1269 return -EINVAL;
1270 }
1271
1272 if (offset + buf_size > bp->common.flash_size) {
51c1a580
MS		 1273 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1274 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
de0c62db
DK		 1275 offset, buf_size, bp->common.flash_size);
1276 return -EINVAL;
1277 }
1278
1279 /* request access to nvram interface */
1280 rc = bnx2x_acquire_nvram_lock(bp);
1281 if (rc)
1282 return rc;
1283
1284 /* enable access to nvram interface */
1285 bnx2x_enable_nvram_access(bp);
1286
1287 written_so_far = 0;
1288 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1289 while ((written_so_far < buf_size) && (rc == 0)) {
1290 if (written_so_far == (buf_size - sizeof(u32)))
1291 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1292 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1293 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1294 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1295 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1296
1297 memcpy(&val, data_buf, 4);
1298
1299 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1300
1301 /* advance to the next dword */
1302 offset += sizeof(u32);
1303 data_buf += sizeof(u32);
1304 written_so_far += sizeof(u32);
1305 cmd_flags = 0;
1306 }
1307
1308 /* disable access to nvram interface */
1309 bnx2x_disable_nvram_access(bp);
1310 bnx2x_release_nvram_lock(bp);
1311
1312 return rc;
1313}
1314
1315static int bnx2x_set_eeprom(struct net_device *dev,
1316 struct ethtool_eeprom *eeprom, u8 *eebuf)
1317{
1318 struct bnx2x *bp = netdev_priv(dev);
1319 int port = BP_PORT(bp);
1320 int rc = 0;
e10bc84d 1321 u32 ext_phy_config;
51c1a580
MS		 1322 if (!netif_running(dev)) {
1323 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1324 "cannot access eeprom when the interface is down\n");
de0c62db 1325 return -EAGAIN;
51c1a580 1326 }
de0c62db 1327
51c1a580 1328 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
f1deab50 1329 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
de0c62db
DK		 1330 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1331 eeprom->len, eeprom->len);
1332
1333 /* parameters already validated in ethtool_set_eeprom */
1334
1335 /* PHY eeprom can be accessed only by the PMF */
1336 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
51c1a580
MS		 1337 !bp->port.pmf) {
1338 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1339 "wrong magic or interface is not pmf\n");
de0c62db 1340 return -EINVAL;
51c1a580 1341 }
de0c62db 1342
e10bc84d
YR		 1343 ext_phy_config =
1344 SHMEM_RD(bp,
1345 dev_info.port_hw_config[port].external_phy_config);
1346
de0c62db
DK		 1347 if (eeprom->magic == 0x50485950) {
1348 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1349 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1350
1351 bnx2x_acquire_phy_lock(bp);
1352 rc |= bnx2x_link_reset(&bp->link_params,
1353 &bp->link_vars, 0);
e10bc84d 1354 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1355 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1356 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1357 MISC_REGISTERS_GPIO_HIGH, port);
1358 bnx2x_release_phy_lock(bp);
1359 bnx2x_link_report(bp);
1360
1361 } else if (eeprom->magic == 0x50485952) {
1362 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1363 if (bp->state == BNX2X_STATE_OPEN) {
1364 bnx2x_acquire_phy_lock(bp);
1365 rc |= bnx2x_link_reset(&bp->link_params,
1366 &bp->link_vars, 1);
1367
1368 rc |= bnx2x_phy_init(&bp->link_params,
1369 &bp->link_vars);
1370 bnx2x_release_phy_lock(bp);
1371 bnx2x_calc_fc_adv(bp);
1372 }
1373 } else if (eeprom->magic == 0x53985943) {
1374 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1375 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1376 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1377
1378 /* DSP Remove Download Mode */
1379 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1380 MISC_REGISTERS_GPIO_LOW, port);
1381
1382 bnx2x_acquire_phy_lock(bp);
1383
e10bc84d
YR		 1384 bnx2x_sfx7101_sp_sw_reset(bp,
1385 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1386
1387 /* wait 0.5 sec to allow it to run */
1388 msleep(500);
1389 bnx2x_ext_phy_hw_reset(bp, port);
1390 msleep(500);
1391 bnx2x_release_phy_lock(bp);
1392 }
1393 } else
1394 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1395
1396 return rc;
1397}
f85582f8 1398
de0c62db
DK		 1399static int bnx2x_get_coalesce(struct net_device *dev,
1400 struct ethtool_coalesce *coal)
1401{
1402 struct bnx2x *bp = netdev_priv(dev);
1403
1404 memset(coal, 0, sizeof(struct ethtool_coalesce));
1405
1406 coal->rx_coalesce_usecs = bp->rx_ticks;
1407 coal->tx_coalesce_usecs = bp->tx_ticks;
1408
1409 return 0;
1410}
1411
1412static int bnx2x_set_coalesce(struct net_device *dev,
1413 struct ethtool_coalesce *coal)
1414{
1415 struct bnx2x *bp = netdev_priv(dev);
1416
1417 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1418 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1419 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1420
1421 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1422 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1423 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1424
1425 if (netif_running(dev))
1426 bnx2x_update_coalesce(bp);
1427
1428 return 0;
1429}
1430
1431static void bnx2x_get_ringparam(struct net_device *dev,
1432 struct ethtool_ringparam *ering)
1433{
1434 struct bnx2x *bp = netdev_priv(dev);
1435
1436 ering->rx_max_pending = MAX_RX_AVAIL;
de0c62db 1437
25141580
DK		 1438 if (bp->rx_ring_size)
1439 ering->rx_pending = bp->rx_ring_size;
1440 else
c2188952 1441 ering->rx_pending = MAX_RX_AVAIL;
25141580 1442
a3348722 1443 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
de0c62db
DK		 1444 ering->tx_pending = bp->tx_ring_size;
1445}
1446
1447static int bnx2x_set_ringparam(struct net_device *dev,
1448 struct ethtool_ringparam *ering)
1449{
1450 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1451
1452 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 1453 DP(BNX2X_MSG_ETHTOOL,
1454 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 1455 return -EAGAIN;
1456 }
1457
1458 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1459 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1460 MIN_RX_SIZE_TPA)) ||
a3348722 1461 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
51c1a580
MS		 1462 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1463 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db 1464 return -EINVAL;
51c1a580 1465 }
de0c62db
DK		 1466
1467 bp->rx_ring_size = ering->rx_pending;
1468 bp->tx_ring_size = ering->tx_pending;
1469
a9fccec7 1470 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1471}
1472
1473static void bnx2x_get_pauseparam(struct net_device *dev,
1474 struct ethtool_pauseparam *epause)
1475{
1476 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1477 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
9e7e8399
MY		 1478 int cfg_reg;
1479
a22f0788
YR		 1480 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1481 BNX2X_FLOW_CTRL_AUTO);
de0c62db 1482
9e7e8399 1483 if (!epause->autoneg)
241fb5d2 1484 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
9e7e8399
MY		 1485 else
1486 cfg_reg = bp->link_params.req_fc_auto_adv;
1487
1488 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
de0c62db 1489 BNX2X_FLOW_CTRL_RX);
9e7e8399 1490 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
de0c62db
DK		 1491 BNX2X_FLOW_CTRL_TX);
1492
51c1a580 1493 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1494 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1495 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1496}
1497
1498static int bnx2x_set_pauseparam(struct net_device *dev,
1499 struct ethtool_pauseparam *epause)
1500{
1501 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1502 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1503 if (IS_MF(bp))
de0c62db
DK		 1504 return 0;
1505
51c1a580 1506 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
f1deab50 1507 " autoneg %d rx_pause %d tx_pause %d\n",
de0c62db
DK		 1508 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1509
a22f0788 1510 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1511
1512 if (epause->rx_pause)
a22f0788 1513 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1514
1515 if (epause->tx_pause)
a22f0788 1516 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1517
a22f0788
YR		 1518 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1519 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1520
1521 if (epause->autoneg) {
a22f0788 1522 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
51c1a580 1523 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
de0c62db
DK		 1524 return -EINVAL;
1525 }
1526
a22f0788
YR		 1527 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1528 bp->link_params.req_flow_ctrl[cfg_idx] =
1529 BNX2X_FLOW_CTRL_AUTO;
1530 }
de0c62db
DK		 1531 }
1532
51c1a580 1533 DP(BNX2X_MSG_ETHTOOL,
a22f0788 1534 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1535
1536 if (netif_running(dev)) {
1537 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1538 bnx2x_link_set(bp);
1539 }
1540
1541 return 0;
1542}
1543
cf2c1df6
MS		 1544char *bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF] = {
1545 "register_test (offline) ",
1546 "memory_test (offline) ",
1547 "int_loopback_test (offline)",
1548 "ext_loopback_test (offline)",
1549 "nvram_test (online) ",
1550 "interrupt_test (online) ",
1551 "link_test (online) "
de0c62db
DK		 1552};
1553
e9939c80
YM		 1554static u32 bnx2x_eee_to_adv(u32 eee_adv)
1555{
1556 u32 modes = 0;
1557
1558 if (eee_adv & SHMEM_EEE_100M_ADV)
1559 modes |= ADVERTISED_100baseT_Full;
1560 if (eee_adv & SHMEM_EEE_1G_ADV)
1561 modes |= ADVERTISED_1000baseT_Full;
1562 if (eee_adv & SHMEM_EEE_10G_ADV)
1563 modes |= ADVERTISED_10000baseT_Full;
1564
1565 return modes;
1566}
1567
1568static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1569{
1570 u32 eee_adv = 0;
1571 if (modes & ADVERTISED_100baseT_Full)
1572 eee_adv |= SHMEM_EEE_100M_ADV;
1573 if (modes & ADVERTISED_1000baseT_Full)
1574 eee_adv |= SHMEM_EEE_1G_ADV;
1575 if (modes & ADVERTISED_10000baseT_Full)
1576 eee_adv |= SHMEM_EEE_10G_ADV;
1577
1578 return eee_adv << shift;
1579}
1580
1581static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1582{
1583 struct bnx2x *bp = netdev_priv(dev);
1584 u32 eee_cfg;
1585
1586 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1587 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1588 return -EOPNOTSUPP;
1589 }
1590
1591 eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1592
1593 edata->supported =
1594 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1595 SHMEM_EEE_SUPPORTED_SHIFT);
1596
1597 edata->advertised =
1598 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1599 SHMEM_EEE_ADV_STATUS_SHIFT);
1600 edata->lp_advertised =
1601 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1602 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1603
1604 /* SHMEM value is in 16u units --> Convert to 1u units. */
1605 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1606
1607 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
1608 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
1609 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1610
1611 return 0;
1612}
1613
1614static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1615{
1616 struct bnx2x *bp = netdev_priv(dev);
1617 u32 eee_cfg;
1618 u32 advertised;
1619
1620 if (IS_MF(bp))
1621 return 0;
1622
1623 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1624 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1625 return -EOPNOTSUPP;
1626 }
1627
1628 eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1629
1630 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1631 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1632 return -EOPNOTSUPP;
1633 }
1634
1635 advertised = bnx2x_adv_to_eee(edata->advertised,
1636 SHMEM_EEE_ADV_STATUS_SHIFT);
1637 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1638 DP(BNX2X_MSG_ETHTOOL,
1639 "Direct manipulation of EEE advertisment is not supported\n");
1640 return -EINVAL;
1641 }
1642
1643 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1644 DP(BNX2X_MSG_ETHTOOL,
1645 "Maximal Tx Lpi timer supported is %x(u)\n",
1646 EEE_MODE_TIMER_MASK);
1647 return -EINVAL;
1648 }
1649 if (edata->tx_lpi_enabled &&
1650 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1651 DP(BNX2X_MSG_ETHTOOL,
1652 "Minimal Tx Lpi timer supported is %d(u)\n",
1653 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1654 return -EINVAL;
1655 }
1656
1657 /* All is well; Apply changes*/
1658 if (edata->eee_enabled)
1659 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1660 else
1661 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1662
1663 if (edata->tx_lpi_enabled)
1664 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1665 else
1666 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1667
1668 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1669 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1670 EEE_MODE_TIMER_MASK) |
1671 EEE_MODE_OVERRIDE_NVRAM |
1672 EEE_MODE_OUTPUT_TIME;
1673
1674 /* Restart link to propogate changes */
1675 if (netif_running(dev)) {
1676 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1677 bnx2x_link_set(bp);
1678 }
1679
1680 return 0;
1681}
1682
1683
619c5cb6
VZ		 1684enum {
1685 BNX2X_CHIP_E1_OFST = 0,
1686 BNX2X_CHIP_E1H_OFST,
1687 BNX2X_CHIP_E2_OFST,
1688 BNX2X_CHIP_E3_OFST,
1689 BNX2X_CHIP_E3B0_OFST,
1690 BNX2X_CHIP_MAX_OFST
1691};
1692
1693#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1694#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1695#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1696#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1697#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1698
1699#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1700#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1701
de0c62db
DK		 1702static int bnx2x_test_registers(struct bnx2x *bp)
1703{
1704 int idx, i, rc = -ENODEV;
619c5cb6 1705 u32 wr_val = 0, hw;
de0c62db
DK		 1706 int port = BP_PORT(bp);
1707 static const struct {
619c5cb6 1708 u32 hw;
de0c62db
DK		 1709 u32 offset0;
1710 u32 offset1;
1711 u32 mask;
1712 } reg_tbl[] = {
619c5cb6
VZ		 1713/* 0 */ { BNX2X_CHIP_MASK_ALL,
1714 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1715 { BNX2X_CHIP_MASK_ALL,
1716 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1717 { BNX2X_CHIP_MASK_E1X,
1718 HC_REG_AGG_INT_0, 4, 0x000003ff },
1719 { BNX2X_CHIP_MASK_ALL,
1720 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1721 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1722 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1723 { BNX2X_CHIP_MASK_E3B0,
1724 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1725 { BNX2X_CHIP_MASK_ALL,
1726 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1727 { BNX2X_CHIP_MASK_ALL,
1728 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1729 { BNX2X_CHIP_MASK_ALL,
1730 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1731 { BNX2X_CHIP_MASK_ALL,
1732 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1733/* 10 */ { BNX2X_CHIP_MASK_ALL,
1734 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1735 { BNX2X_CHIP_MASK_ALL,
1736 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1737 { BNX2X_CHIP_MASK_ALL,
1738 QM_REG_CONNNUM_0, 4, 0x000fffff },
1739 { BNX2X_CHIP_MASK_ALL,
1740 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1741 { BNX2X_CHIP_MASK_ALL,
1742 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1743 { BNX2X_CHIP_MASK_ALL,
1744 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1745 { BNX2X_CHIP_MASK_ALL,
1746 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1747 { BNX2X_CHIP_MASK_ALL,
1748 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1749 { BNX2X_CHIP_MASK_ALL,
1750 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1751 { BNX2X_CHIP_MASK_ALL,
1752 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1753/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1754 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1755 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1756 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1757 { BNX2X_CHIP_MASK_ALL,
1758 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1759 { BNX2X_CHIP_MASK_ALL,
1760 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1761 { BNX2X_CHIP_MASK_ALL,
1762 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1763 { BNX2X_CHIP_MASK_ALL,
1764 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1765 { BNX2X_CHIP_MASK_ALL,
1766 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1767 { BNX2X_CHIP_MASK_ALL,
1768 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1769 { BNX2X_CHIP_MASK_ALL,
1770 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1771 { BNX2X_CHIP_MASK_ALL,
1772 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1773/* 30 */ { BNX2X_CHIP_MASK_ALL,
1774 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1775 { BNX2X_CHIP_MASK_ALL,
1776 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1777 { BNX2X_CHIP_MASK_ALL,
1778 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1779 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1780 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1781 { BNX2X_CHIP_MASK_ALL,
1782 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1783 { BNX2X_CHIP_MASK_ALL,
1784 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1785 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1786 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1787 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1788 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1789
1790 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1791 };
1792
51c1a580
MS		 1793 if (!netif_running(bp->dev)) {
1794 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1795 "cannot access eeprom when the interface is down\n");
de0c62db 1796 return rc;
51c1a580 1797 }
de0c62db 1798
619c5cb6
VZ		 1799 if (CHIP_IS_E1(bp))
1800 hw = BNX2X_CHIP_MASK_E1;
1801 else if (CHIP_IS_E1H(bp))
1802 hw = BNX2X_CHIP_MASK_E1H;
1803 else if (CHIP_IS_E2(bp))
1804 hw = BNX2X_CHIP_MASK_E2;
1805 else if (CHIP_IS_E3B0(bp))
1806 hw = BNX2X_CHIP_MASK_E3B0;
1807 else /* e3 A0 */
1808 hw = BNX2X_CHIP_MASK_E3;
1809
de0c62db
DK		 1810 /* Repeat the test twice:
1811 First by writing 0x00000000, second by writing 0xffffffff */
1812 for (idx = 0; idx < 2; idx++) {
1813
1814 switch (idx) {
1815 case 0:
1816 wr_val = 0;
1817 break;
1818 case 1:
1819 wr_val = 0xffffffff;
1820 break;
1821 }
1822
1823 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1824 u32 offset, mask, save_val, val;
619c5cb6 1825 if (!(hw & reg_tbl[i].hw))
f2e0899f 1826 continue;
de0c62db
DK		 1827
1828 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1829 mask = reg_tbl[i].mask;
1830
1831 save_val = REG_RD(bp, offset);
1832
ec6ba945 1833 REG_WR(bp, offset, wr_val & mask);
f85582f8 1834
de0c62db
DK		 1835 val = REG_RD(bp, offset);
1836
1837 /* Restore the original register's value */
1838 REG_WR(bp, offset, save_val);
1839
1840 /* verify value is as expected */
1841 if ((val & mask) != (wr_val & mask)) {
51c1a580 1842 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1843 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1844 offset, val, wr_val, mask);
1845 goto test_reg_exit;
1846 }
1847 }
1848 }
1849
1850 rc = 0;
1851
1852test_reg_exit:
1853 return rc;
1854}
1855
1856static int bnx2x_test_memory(struct bnx2x *bp)
1857{
1858 int i, j, rc = -ENODEV;
619c5cb6 1859 u32 val, index;
de0c62db
DK		 1860 static const struct {
1861 u32 offset;
1862 int size;
1863 } mem_tbl[] = {
1864 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1865 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1866 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1867 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1868 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1869 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1870 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1871
1872 { 0xffffffff, 0 }
1873 };
619c5cb6 1874
de0c62db
DK		 1875 static const struct {
1876 char *name;
1877 u32 offset;
619c5cb6 1878 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1879 } prty_tbl[] = {
619c5cb6
VZ		 1880 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1881 {0x3ffc0, 0, 0, 0} },
1882 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1883 {0x2, 0x2, 0, 0} },
1884 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1885 {0, 0, 0, 0} },
1886 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1887 {0x3ffc0, 0, 0, 0} },
1888 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1889 {0x3ffc0, 0, 0, 0} },
1890 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1891 {0x3ffc1, 0, 0, 0} },
1892
1893 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1894 };
1895
51c1a580
MS		 1896 if (!netif_running(bp->dev)) {
1897 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1898 "cannot access eeprom when the interface is down\n");
de0c62db 1899 return rc;
51c1a580 1900 }
de0c62db 1901
619c5cb6
VZ		 1902 if (CHIP_IS_E1(bp))
1903 index = BNX2X_CHIP_E1_OFST;
1904 else if (CHIP_IS_E1H(bp))
1905 index = BNX2X_CHIP_E1H_OFST;
1906 else if (CHIP_IS_E2(bp))
1907 index = BNX2X_CHIP_E2_OFST;
1908 else /* e3 */
1909 index = BNX2X_CHIP_E3_OFST;
1910
f2e0899f
DK		 1911 /* pre-Check the parity status */
1912 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1913 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1914 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1915 DP(BNX2X_MSG_ETHTOOL,
f2e0899f
DK		 1916 "%s is 0x%x\n", prty_tbl[i].name, val);
1917 goto test_mem_exit;
1918 }
1919 }
1920
de0c62db
DK		 1921 /* Go through all the memories */
1922 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1923 for (j = 0; j < mem_tbl[i].size; j++)
1924 REG_RD(bp, mem_tbl[i].offset + j*4);
1925
1926 /* Check the parity status */
1927 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1928 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1929 if (val & ~(prty_tbl[i].hw_mask[index])) {
51c1a580 1930 DP(BNX2X_MSG_ETHTOOL,
de0c62db
DK		 1931 "%s is 0x%x\n", prty_tbl[i].name, val);
1932 goto test_mem_exit;
1933 }
1934 }
1935
1936 rc = 0;
1937
1938test_mem_exit:
1939 return rc;
1940}
1941
a22f0788 1942static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1943{
f2e0899f 1944 int cnt = 1400;
de0c62db 1945
619c5cb6 1946 if (link_up) {
a22f0788 1947 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 1948 msleep(20);
1949
1950 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
51c1a580 1951 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
8970b2e4
MS		 1952
1953 cnt = 1400;
1954 while (!bp->link_vars.link_up && cnt--)
1955 msleep(20);
1956
1957 if (cnt <= 0 && !bp->link_vars.link_up)
1958 DP(BNX2X_MSG_ETHTOOL,
1959 "Timeout waiting for link init\n");
619c5cb6 1960 }
de0c62db
DK		 1961}
1962
619c5cb6 1963static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 1964{
1965 unsigned int pkt_size, num_pkts, i;
1966 struct sk_buff *skb;
1967 unsigned char *packet;
1968 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1969 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
65565884 1970 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
de0c62db
DK		 1971 u16 tx_start_idx, tx_idx;
1972 u16 rx_start_idx, rx_idx;
b0700b1e 1973 u16 pkt_prod, bd_prod;
de0c62db
DK		 1974 struct sw_tx_bd *tx_buf;
1975 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1976 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1977 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1978 dma_addr_t mapping;
1979 union eth_rx_cqe *cqe;
619c5cb6 1980 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 1981 struct sw_rx_bd *rx_buf;
1982 u16 len;
1983 int rc = -ENODEV;
e52fcb24 1984 u8 *data;
8970b2e4
MS		 1985 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
1986 txdata->txq_index);
de0c62db
DK		 1987
1988 /* check the loopback mode */
1989 switch (loopback_mode) {
1990 case BNX2X_PHY_LOOPBACK:
8970b2e4
MS		 1991 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
1992 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
de0c62db 1993 return -EINVAL;
8970b2e4 1994 }
de0c62db
DK		 1995 break;
1996 case BNX2X_MAC_LOOPBACK:
32911333
YR		 1997 if (CHIP_IS_E3(bp)) {
1998 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1999 if (bp->port.supported[cfg_idx] &
2000 (SUPPORTED_10000baseT_Full |
2001 SUPPORTED_20000baseMLD2_Full |
2002 SUPPORTED_20000baseKR2_Full))
2003 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2004 else
2005 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2006 } else
2007 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2008
de0c62db
DK		 2009 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2010 break;
8970b2e4
MS		 2011 case BNX2X_EXT_LOOPBACK:
2012 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2013 DP(BNX2X_MSG_ETHTOOL,
2014 "Can't configure external loopback\n");
2015 return -EINVAL;
2016 }
2017 break;
de0c62db 2018 default:
51c1a580 2019 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
de0c62db
DK		 2020 return -EINVAL;
2021 }
2022
2023 /* prepare the loopback packet */
2024 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2025 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 2026 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db 2027 if (!skb) {
51c1a580 2028 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
de0c62db
DK		 2029 rc = -ENOMEM;
2030 goto test_loopback_exit;
2031 }
2032 packet = skb_put(skb, pkt_size);
2033 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2034 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2035 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2036 for (i = ETH_HLEN; i < pkt_size; i++)
2037 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 2038 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2039 skb_headlen(skb), DMA_TO_DEVICE);
2040 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2041 rc = -ENOMEM;
2042 dev_kfree_skb(skb);
51c1a580 2043 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
619c5cb6
VZ		 2044 goto test_loopback_exit;
2045 }
de0c62db
DK		 2046
2047 /* send the loopback packet */
2048 num_pkts = 0;
6383c0b3 2049 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2050 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2051
73dbb5e1
DK		 2052 netdev_tx_sent_queue(txq, skb->len);
2053
6383c0b3
AE		 2054 pkt_prod = txdata->tx_pkt_prod++;
2055 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2056 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 2057 tx_buf->skb = skb;
2058 tx_buf->flags = 0;
2059
6383c0b3
AE		 2060 bd_prod = TX_BD(txdata->tx_bd_prod);
2061 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 2062 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2063 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2064 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2065 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 2066 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 2067 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 2068 SET_FLAG(tx_start_bd->general_data,
2069 ETH_TX_START_BD_ETH_ADDR_TYPE,
2070 UNICAST_ADDRESS);
2071 SET_FLAG(tx_start_bd->general_data,
2072 ETH_TX_START_BD_HDR_NBDS,
2073 1);
de0c62db
DK		 2074
2075 /* turn on parsing and get a BD */
2076 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 2077
6383c0b3
AE		 2078 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2079 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 2080
f2e0899f 2081 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 2082 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 2083
2084 wmb();
2085
6383c0b3 2086 txdata->tx_db.data.prod += 2;
de0c62db 2087 barrier();
6383c0b3 2088 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 2089
2090 mmiowb();
619c5cb6 2091 barrier();
de0c62db
DK		 2092
2093 num_pkts++;
6383c0b3 2094 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 2095
2096 udelay(100);
2097
6383c0b3 2098 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 2099 if (tx_idx != tx_start_idx + num_pkts)
2100 goto test_loopback_exit;
2101
f2e0899f
DK		 2102 /* Unlike HC IGU won't generate an interrupt for status block
2103 * updates that have been performed while interrupts were
2104 * disabled.
2105 */
e1210d12
ED		 2106 if (bp->common.int_block == INT_BLOCK_IGU) {
2107 /* Disable local BHes to prevent a dead-lock situation between
2108 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2109 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2110 */
2111 local_bh_disable();
6383c0b3 2112 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 2113 local_bh_enable();
2114 }
f2e0899f 2115
de0c62db
DK		 2116 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2117 if (rx_idx != rx_start_idx + num_pkts)
2118 goto test_loopback_exit;
2119
b0700b1e 2120 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
de0c62db 2121 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 2122 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2123 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 2124 goto test_loopback_rx_exit;
2125
621b4d66 2126 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
de0c62db
DK		 2127 if (len != pkt_size)
2128 goto test_loopback_rx_exit;
2129
2130 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 2131 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 2132 dma_unmap_addr(rx_buf, mapping),
2133 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
e52fcb24 2134 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
de0c62db 2135 for (i = ETH_HLEN; i < pkt_size; i++)
e52fcb24 2136 if (*(data + i) != (unsigned char) (i & 0xff))
de0c62db
DK		 2137 goto test_loopback_rx_exit;
2138
2139 rc = 0;
2140
2141test_loopback_rx_exit:
2142
2143 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2144 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2145 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2146 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2147
2148 /* Update producers */
2149 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2150 fp_rx->rx_sge_prod);
2151
2152test_loopback_exit:
2153 bp->link_params.loopback_mode = LOOPBACK_NONE;
2154
2155 return rc;
2156}
2157
619c5cb6 2158static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 2159{
2160 int rc = 0, res;
2161
2162 if (BP_NOMCP(bp))
2163 return rc;
2164
2165 if (!netif_running(bp->dev))
2166 return BNX2X_LOOPBACK_FAILED;
2167
2168 bnx2x_netif_stop(bp, 1);
2169 bnx2x_acquire_phy_lock(bp);
2170
619c5cb6 2171 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db 2172 if (res) {
51c1a580 2173 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
de0c62db
DK		 2174 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2175 }
2176
619c5cb6 2177 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db 2178 if (res) {
51c1a580 2179 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
de0c62db
DK		 2180 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2181 }
2182
2183 bnx2x_release_phy_lock(bp);
2184 bnx2x_netif_start(bp);
2185
2186 return rc;
2187}
2188
8970b2e4
MS		 2189static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2190{
2191 int rc;
2192 u8 is_serdes =
2193 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2194
2195 if (BP_NOMCP(bp))
2196 return -ENODEV;
2197
2198 if (!netif_running(bp->dev))
2199 return BNX2X_EXT_LOOPBACK_FAILED;
2200
2201 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2202 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2203 if (rc) {
2204 DP(BNX2X_MSG_ETHTOOL,
2205 "Can't perform self-test, nic_load (for external lb) failed\n");
2206 return -ENODEV;
2207 }
2208 bnx2x_wait_for_link(bp, 1, is_serdes);
2209
2210 bnx2x_netif_stop(bp, 1);
2211
2212 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2213 if (rc)
2214 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2215
2216 bnx2x_netif_start(bp);
2217
2218 return rc;
2219}
2220
de0c62db
DK		 2221#define CRC32_RESIDUAL 0xdebb20e3
2222
2223static int bnx2x_test_nvram(struct bnx2x *bp)
2224{
2225 static const struct {
2226 int offset;
2227 int size;
2228 } nvram_tbl[] = {
2229 { 0, 0x14 }, /* bootstrap */
2230 { 0x14, 0xec }, /* dir */
2231 { 0x100, 0x350 }, /* manuf_info */
2232 { 0x450, 0xf0 }, /* feature_info */
2233 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 2234 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 2235 { 0, 0 }
2236 };
afa13b4b
MY		 2237 __be32 *buf;
2238 u8 *data;
de0c62db
DK		 2239 int i, rc;
2240 u32 magic, crc;
2241
2242 if (BP_NOMCP(bp))
2243 return 0;
2244
afa13b4b
MY		 2245 buf = kmalloc(0x350, GFP_KERNEL);
2246 if (!buf) {
51c1a580 2247 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
afa13b4b
MY		 2248 rc = -ENOMEM;
2249 goto test_nvram_exit;
2250 }
2251 data = (u8 *)buf;
2252
de0c62db
DK		 2253 rc = bnx2x_nvram_read(bp, 0, data, 4);
2254 if (rc) {
51c1a580
MS		 2255 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2256 "magic value read (rc %d)\n", rc);
de0c62db
DK		 2257 goto test_nvram_exit;
2258 }
2259
2260 magic = be32_to_cpu(buf[0]);
2261 if (magic != 0x669955aa) {
51c1a580
MS		 2262 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2263 "wrong magic value (0x%08x)\n", magic);
de0c62db
DK		 2264 rc = -ENODEV;
2265 goto test_nvram_exit;
2266 }
2267
2268 for (i = 0; nvram_tbl[i].size; i++) {
2269
2270 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2271 nvram_tbl[i].size);
2272 if (rc) {
51c1a580 2273 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
de0c62db
DK		 2274 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2275 goto test_nvram_exit;
2276 }
2277
2278 crc = ether_crc_le(nvram_tbl[i].size, data);
2279 if (crc != CRC32_RESIDUAL) {
51c1a580
MS		 2280 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2281 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
de0c62db
DK		 2282 rc = -ENODEV;
2283 goto test_nvram_exit;
2284 }
2285 }
2286
2287test_nvram_exit:
afa13b4b 2288 kfree(buf);
de0c62db
DK		 2289 return rc;
2290}
2291
619c5cb6 2292/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 2293static int bnx2x_test_intr(struct bnx2x *bp)
2294{
3b603066 2295 struct bnx2x_queue_state_params params = {NULL};
de0c62db 2296
51c1a580
MS		 2297 if (!netif_running(bp->dev)) {
2298 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2299 "cannot access eeprom when the interface is down\n");
de0c62db 2300 return -ENODEV;
51c1a580 2301 }
de0c62db 2302
15192a8c 2303 params.q_obj = &bp->sp_objs->q_obj;
619c5cb6 2304 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 2305
619c5cb6
VZ		 2306 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2307
2308 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 2309}
2310
2311static void bnx2x_self_test(struct net_device *dev,
2312 struct ethtool_test *etest, u64 *buf)
2313{
2314 struct bnx2x *bp = netdev_priv(dev);
a22f0788 2315 u8 is_serdes;
cf2c1df6
MS		 2316 int rc;
2317
de0c62db 2318 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580
MS		 2319 netdev_err(bp->dev,
2320 "Handling parity error recovery. Try again later\n");
de0c62db
DK		 2321 etest->flags |= ETH_TEST_FL_FAILED;
2322 return;
2323 }
8970b2e4
MS		 2324 DP(BNX2X_MSG_ETHTOOL,
2325 "Self-test command parameters: offline = %d, external_lb = %d\n",
2326 (etest->flags & ETH_TEST_FL_OFFLINE),
2327 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
de0c62db 2328
cf2c1df6 2329 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
de0c62db 2330
cf2c1df6
MS		 2331 if (!netif_running(dev)) {
2332 DP(BNX2X_MSG_ETHTOOL,
2333 "Can't perform self-test when interface is down\n");
de0c62db 2334 return;
cf2c1df6 2335 }
de0c62db 2336
a22f0788 2337 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db 2338
cf2c1df6
MS		 2339 /* offline tests are not supported in MF mode */
2340 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
de0c62db
DK		 2341 int port = BP_PORT(bp);
2342 u32 val;
2343 u8 link_up;
2344
2345 /* save current value of input enable for TX port IF */
2346 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2347 /* disable input for TX port IF */
2348 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2349
a22f0788
YR		 2350 link_up = bp->link_vars.link_up;
2351
de0c62db 2352 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
cf2c1df6
MS		 2353 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2354 if (rc) {
2355 etest->flags |= ETH_TEST_FL_FAILED;
2356 DP(BNX2X_MSG_ETHTOOL,
2357 "Can't perform self-test, nic_load (for offline) failed\n");
2358 return;
2359 }
2360
de0c62db 2361 /* wait until link state is restored */
619c5cb6 2362 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2363
2364 if (bnx2x_test_registers(bp) != 0) {
2365 buf[0] = 1;
2366 etest->flags |= ETH_TEST_FL_FAILED;
2367 }
2368 if (bnx2x_test_memory(bp) != 0) {
2369 buf[1] = 1;
2370 etest->flags |= ETH_TEST_FL_FAILED;
2371 }
f85582f8 2372
8970b2e4 2373 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
de0c62db
DK		 2374 if (buf[2] != 0)
2375 etest->flags |= ETH_TEST_FL_FAILED;
2376
8970b2e4
MS		 2377 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2378 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2379 if (buf[3] != 0)
2380 etest->flags |= ETH_TEST_FL_FAILED;
2381 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2382 }
2383
de0c62db
DK		 2384 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2385
2386 /* restore input for TX port IF */
2387 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
cf2c1df6
MS		 2388 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2389 if (rc) {
2390 etest->flags |= ETH_TEST_FL_FAILED;
2391 DP(BNX2X_MSG_ETHTOOL,
2392 "Can't perform self-test, nic_load (for online) failed\n");
2393 return;
2394 }
de0c62db 2395 /* wait until link state is restored */
a22f0788 2396 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2397 }
2398 if (bnx2x_test_nvram(bp) != 0) {
cf2c1df6
MS		 2399 if (!IS_MF(bp))
2400 buf[4] = 1;
2401 else
2402 buf[0] = 1;
de0c62db
DK		 2403 etest->flags |= ETH_TEST_FL_FAILED;
2404 }
2405 if (bnx2x_test_intr(bp) != 0) {
cf2c1df6
MS		 2406 if (!IS_MF(bp))
2407 buf[5] = 1;
2408 else
2409 buf[1] = 1;
de0c62db
DK		 2410 etest->flags |= ETH_TEST_FL_FAILED;
2411 }
633ac363
DK		 2412
2413 if (bnx2x_link_test(bp, is_serdes) != 0) {
cf2c1df6
MS		 2414 if (!IS_MF(bp))
2415 buf[6] = 1;
2416 else
2417 buf[2] = 1;
633ac363
DK		 2418 etest->flags |= ETH_TEST_FL_FAILED;
2419 }
de0c62db
DK		 2420
2421#ifdef BNX2X_EXTRA_DEBUG
2422 bnx2x_panic_dump(bp);
2423#endif
2424}
2425
de0c62db
DK		 2426#define IS_PORT_STAT(i) \
2427 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2428#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2429#define IS_MF_MODE_STAT(bp) \
2430 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2431
619c5cb6
VZ		 2432/* ethtool statistics are displayed for all regular ethernet queues and the
2433 * fcoe L2 queue if not disabled
2434 */
1191cb83 2435static int bnx2x_num_stat_queues(struct bnx2x *bp)
619c5cb6
VZ		 2436{
2437 return BNX2X_NUM_ETH_QUEUES(bp);
2438}
2439
de0c62db
DK		 2440static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2441{
2442 struct bnx2x *bp = netdev_priv(dev);
2443 int i, num_stats;
2444
2445 switch (stringset) {
2446 case ETH_SS_STATS:
2447 if (is_multi(bp)) {
619c5cb6 2448 num_stats = bnx2x_num_stat_queues(bp) *
d5e83632
YM		 2449 BNX2X_NUM_Q_STATS;
2450 } else
2451 num_stats = 0;
2452 if (IS_MF_MODE_STAT(bp)) {
2453 for (i = 0; i < BNX2X_NUM_STATS; i++)
2454 if (IS_FUNC_STAT(i))
2455 num_stats++;
2456 } else
2457 num_stats += BNX2X_NUM_STATS;
2458
de0c62db
DK		 2459 return num_stats;
2460
2461 case ETH_SS_TEST:
cf2c1df6 2462 return BNX2X_NUM_TESTS(bp);
de0c62db
DK		 2463
2464 default:
2465 return -EINVAL;
2466 }
2467}
2468
2469static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2470{
2471 struct bnx2x *bp = netdev_priv(dev);
cf2c1df6 2472 int i, j, k, offset, start;
ec6ba945 2473 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2474
2475 switch (stringset) {
2476 case ETH_SS_STATS:
d5e83632 2477 k = 0;
de0c62db 2478 if (is_multi(bp)) {
619c5cb6 2479 for_each_eth_queue(bp, i) {
ec6ba945 2480 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2481 sprintf(queue_name, "%d", i);
de0c62db 2482 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2483 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2484 ETH_GSTRING_LEN,
2485 bnx2x_q_stats_arr[j].string,
2486 queue_name);
de0c62db
DK		 2487 k += BNX2X_NUM_Q_STATS;
2488 }
de0c62db 2489 }
d5e83632
YM		 2490
2491
2492 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2493 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2494 continue;
2495 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2496 bnx2x_stats_arr[i].string);
2497 j++;
2498 }
2499
de0c62db
DK		 2500 break;
2501
2502 case ETH_SS_TEST:
cf2c1df6
MS		 2503 /* First 4 tests cannot be done in MF mode */
2504 if (!IS_MF(bp))
2505 start = 0;
2506 else
2507 start = 4;
2508 for (i = 0, j = start; j < (start + BNX2X_NUM_TESTS(bp));
2509 i++, j++) {
2510 offset = sprintf(buf+32*i, "%s",
2511 bnx2x_tests_str_arr[j]);
2512 *(buf+offset) = '\0';
2513 }
de0c62db
DK		 2514 break;
2515 }
2516}
2517
2518static void bnx2x_get_ethtool_stats(struct net_device *dev,
2519 struct ethtool_stats *stats, u64 *buf)
2520{
2521 struct bnx2x *bp = netdev_priv(dev);
2522 u32 *hw_stats, *offset;
d5e83632 2523 int i, j, k = 0;
de0c62db
DK		 2524
2525 if (is_multi(bp)) {
619c5cb6 2526 for_each_eth_queue(bp, i) {
15192a8c 2527 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
de0c62db
DK		 2528 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2529 if (bnx2x_q_stats_arr[j].size == 0) {
2530 /* skip this counter */
2531 buf[k + j] = 0;
2532 continue;
2533 }
2534 offset = (hw_stats +
2535 bnx2x_q_stats_arr[j].offset);
2536 if (bnx2x_q_stats_arr[j].size == 4) {
2537 /* 4-byte counter */
2538 buf[k + j] = (u64) *offset;
2539 continue;
2540 }
2541 /* 8-byte counter */
2542 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2543 }
2544 k += BNX2X_NUM_Q_STATS;
2545 }
d5e83632
YM		 2546 }
2547
2548 hw_stats = (u32 *)&bp->eth_stats;
2549 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2550 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2551 continue;
2552 if (bnx2x_stats_arr[i].size == 0) {
2553 /* skip this counter */
2554 buf[k + j] = 0;
2555 j++;
2556 continue;
de0c62db 2557 }
d5e83632
YM		 2558 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2559 if (bnx2x_stats_arr[i].size == 4) {
2560 /* 4-byte counter */
2561 buf[k + j] = (u64) *offset;
de0c62db 2562 j++;
d5e83632 2563 continue;
de0c62db 2564 }
d5e83632
YM		 2565 /* 8-byte counter */
2566 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2567 j++;
de0c62db
DK		 2568 }
2569}
2570
32d36134 2571static int bnx2x_set_phys_id(struct net_device *dev,
2572 enum ethtool_phys_id_state state)
de0c62db
DK		 2573{
2574 struct bnx2x *bp = netdev_priv(dev);
de0c62db 2575
51c1a580
MS		 2576 if (!netif_running(dev)) {
2577 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2578 "cannot access eeprom when the interface is down\n");
32d36134 2579 return -EAGAIN;
51c1a580 2580 }
de0c62db 2581
51c1a580
MS		 2582 if (!bp->port.pmf) {
2583 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
32d36134 2584 return -EOPNOTSUPP;
51c1a580 2585 }
de0c62db 2586
32d36134 2587 switch (state) {
2588 case ETHTOOL_ID_ACTIVE:
fce55922 2589 return 1; /* cycle on/off once per second */
de0c62db 2590
32d36134 2591 case ETHTOOL_ID_ON:
2592 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2593 LED_MODE_ON, SPEED_1000);
32d36134 2594 break;
de0c62db 2595
32d36134 2596 case ETHTOOL_ID_OFF:
2597 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2598 LED_MODE_FRONT_PANEL_OFF, 0);
de0c62db 2599
32d36134 2600 break;
2601
2602 case ETHTOOL_ID_INACTIVE:
e1943424
DM		 2603 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2604 LED_MODE_OPER,
2605 bp->link_vars.line_speed);
32d36134 2606 }
de0c62db
DK		 2607
2608 return 0;
2609}
2610
5d317c6a
MS		 2611static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2612{
2613
2614 switch (info->flow_type) {
2615 case TCP_V4_FLOW:
2616 case TCP_V6_FLOW:
2617 info->data = RXH_IP_SRC | RXH_IP_DST |
2618 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2619 break;
2620 case UDP_V4_FLOW:
2621 if (bp->rss_conf_obj.udp_rss_v4)
2622 info->data = RXH_IP_SRC | RXH_IP_DST |
2623 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2624 else
2625 info->data = RXH_IP_SRC | RXH_IP_DST;
2626 break;
2627 case UDP_V6_FLOW:
2628 if (bp->rss_conf_obj.udp_rss_v6)
2629 info->data = RXH_IP_SRC | RXH_IP_DST |
2630 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2631 else
2632 info->data = RXH_IP_SRC | RXH_IP_DST;
2633 break;
2634 case IPV4_FLOW:
2635 case IPV6_FLOW:
2636 info->data = RXH_IP_SRC | RXH_IP_DST;
2637 break;
2638 default:
2639 info->data = 0;
2640 break;
2641 }
2642
2643 return 0;
2644}
2645
ab532cf3 2646static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
815c7db5 2647 u32 *rules __always_unused)
ab532cf3
TH		 2648{
2649 struct bnx2x *bp = netdev_priv(dev);
2650
2651 switch (info->cmd) {
2652 case ETHTOOL_GRXRINGS:
2653 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2654 return 0;
5d317c6a
MS		 2655 case ETHTOOL_GRXFH:
2656 return bnx2x_get_rss_flags(bp, info);
2657 default:
2658 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2659 return -EOPNOTSUPP;
2660 }
2661}
2662
2663static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2664{
2665 int udp_rss_requested;
2666
2667 DP(BNX2X_MSG_ETHTOOL,
2668 "Set rss flags command parameters: flow type = %d, data = %llu\n",
2669 info->flow_type, info->data);
2670
2671 switch (info->flow_type) {
2672 case TCP_V4_FLOW:
2673 case TCP_V6_FLOW:
2674 /* For TCP only 4-tupple hash is supported */
2675 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2676 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2677 DP(BNX2X_MSG_ETHTOOL,
2678 "Command parameters not supported\n");
2679 return -EINVAL;
2680 } else {
2681 return 0;
2682 }
2683
2684 case UDP_V4_FLOW:
2685 case UDP_V6_FLOW:
2686 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2687 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2688 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2689 udp_rss_requested = 1;
2690 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2691 udp_rss_requested = 0;
2692 else
2693 return -EINVAL;
2694 if ((info->flow_type == UDP_V4_FLOW) &&
2695 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
2696 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
2697 DP(BNX2X_MSG_ETHTOOL,
2698 "rss re-configured, UDP 4-tupple %s\n",
2699 udp_rss_requested ? "enabled" : "disabled");
2700 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2701 } else if ((info->flow_type == UDP_V6_FLOW) &&
2702 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
2703 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
2704 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
2705 DP(BNX2X_MSG_ETHTOOL,
2706 "rss re-configured, UDP 4-tupple %s\n",
2707 udp_rss_requested ? "enabled" : "disabled");
2708 } else {
2709 return 0;
2710 }
2711 case IPV4_FLOW:
2712 case IPV6_FLOW:
2713 /* For IP only 2-tupple hash is supported */
2714 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
2715 DP(BNX2X_MSG_ETHTOOL,
2716 "Command parameters not supported\n");
2717 return -EINVAL;
2718 } else {
2719 return 0;
2720 }
2721 case SCTP_V4_FLOW:
2722 case AH_ESP_V4_FLOW:
2723 case AH_V4_FLOW:
2724 case ESP_V4_FLOW:
2725 case SCTP_V6_FLOW:
2726 case AH_ESP_V6_FLOW:
2727 case AH_V6_FLOW:
2728 case ESP_V6_FLOW:
2729 case IP_USER_FLOW:
2730 case ETHER_FLOW:
2731 /* RSS is not supported for these protocols */
2732 if (info->data) {
2733 DP(BNX2X_MSG_ETHTOOL,
2734 "Command parameters not supported\n");
2735 return -EINVAL;
2736 } else {
2737 return 0;
2738 }
2739 default:
2740 return -EINVAL;
2741 }
2742}
2743
2744static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
2745{
2746 struct bnx2x *bp = netdev_priv(dev);
ab532cf3 2747
5d317c6a
MS		 2748 switch (info->cmd) {
2749 case ETHTOOL_SRXFH:
2750 return bnx2x_set_rss_flags(bp, info);
ab532cf3 2751 default:
51c1a580 2752 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
ab532cf3
TH		 2753 return -EOPNOTSUPP;
2754 }
2755}
2756
7850f63f
BH		 2757static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2758{
96305234 2759 return T_ETH_INDIRECTION_TABLE_SIZE;
7850f63f
BH		 2760}
2761
2762static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
ab532cf3
TH		 2763{
2764 struct bnx2x *bp = netdev_priv(dev);
619c5cb6
VZ		 2765 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2766 size_t i;
ab532cf3 2767
619c5cb6
VZ		 2768 /* Get the current configuration of the RSS indirection table */
2769 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2770
2771 /*
2772 * We can't use a memcpy() as an internal storage of an
2773 * indirection table is a u8 array while indir->ring_index
2774 * points to an array of u32.
2775 *
2776 * Indirection table contains the FW Client IDs, so we need to
2777 * align the returned table to the Client ID of the leading RSS
2778 * queue.
2779 */
7850f63f
BH		 2780 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2781 indir[i] = ind_table[i] - bp->fp->cl_id;
619c5cb6 2782
ab532cf3
TH		 2783 return 0;
2784}
2785
7850f63f 2786static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ab532cf3
TH		 2787{
2788 struct bnx2x *bp = netdev_priv(dev);
2789 size_t i;
619c5cb6
VZ		 2790
2791 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
619c5cb6
VZ		 2792 /*
2793 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2794 * as an internal storage of an indirection table is a u8 array
2795 * while indir->ring_index points to an array of u32.
2796 *
2797 * Indirection table contains the FW Client IDs, so we need to
2798 * align the received table to the Client ID of the leading RSS
2799 * queue
2800 */
5d317c6a 2801 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
619c5cb6 2802 }
ab532cf3 2803
5d317c6a 2804 return bnx2x_config_rss_eth(bp, false);
ab532cf3
TH		 2805}
2806
0e8d2ec5
MS		 2807/**
2808 * bnx2x_get_channels - gets the number of RSS queues.
2809 *
2810 * @dev: net device
2811 * @channels: returns the number of max / current queues
2812 */
2813static void bnx2x_get_channels(struct net_device *dev,
2814 struct ethtool_channels *channels)
2815{
2816 struct bnx2x *bp = netdev_priv(dev);
2817
2818 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
2819 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
2820}
2821
2822/**
2823 * bnx2x_change_num_queues - change the number of RSS queues.
2824 *
2825 * @bp: bnx2x private structure
2826 *
2827 * Re-configure interrupt mode to get the new number of MSI-X
2828 * vectors and re-add NAPI objects.
2829 */
2830static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
2831{
2832 bnx2x_del_all_napi(bp);
2833 bnx2x_disable_msi(bp);
2834 BNX2X_NUM_QUEUES(bp) = num_rss + NON_ETH_CONTEXT_USE;
2835 bnx2x_set_int_mode(bp);
2836 bnx2x_add_all_napi(bp);
2837}
2838
2839/**
2840 * bnx2x_set_channels - sets the number of RSS queues.
2841 *
2842 * @dev: net device
2843 * @channels: includes the number of queues requested
2844 */
2845static int bnx2x_set_channels(struct net_device *dev,
2846 struct ethtool_channels *channels)
2847{
2848 struct bnx2x *bp = netdev_priv(dev);
2849
2850
2851 DP(BNX2X_MSG_ETHTOOL,
2852 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
2853 channels->rx_count, channels->tx_count, channels->other_count,
2854 channels->combined_count);
2855
2856 /* We don't support separate rx / tx channels.
2857 * We don't allow setting 'other' channels.
2858 */
2859 if (channels->rx_count || channels->tx_count || channels->other_count
2860 || (channels->combined_count == 0) ||
2861 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
2862 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
2863 return -EINVAL;
2864 }
2865
2866 /* Check if there was a change in the active parameters */
2867 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
2868 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
2869 return 0;
2870 }
2871
2872 /* Set the requested number of queues in bp context.
2873 * Note that the actual number of queues created during load may be
2874 * less than requested if memory is low.
2875 */
2876 if (unlikely(!netif_running(dev))) {
2877 bnx2x_change_num_queues(bp, channels->combined_count);
2878 return 0;
2879 }
2880 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2881 bnx2x_change_num_queues(bp, channels->combined_count);
2882 return bnx2x_nic_load(bp, LOAD_NORMAL);
2883}
2884
de0c62db
DK		 2885static const struct ethtool_ops bnx2x_ethtool_ops = {
2886 .get_settings = bnx2x_get_settings,
2887 .set_settings = bnx2x_set_settings,
2888 .get_drvinfo = bnx2x_get_drvinfo,
2889 .get_regs_len = bnx2x_get_regs_len,
2890 .get_regs = bnx2x_get_regs,
2891 .get_wol = bnx2x_get_wol,
2892 .set_wol = bnx2x_set_wol,
2893 .get_msglevel = bnx2x_get_msglevel,
2894 .set_msglevel = bnx2x_set_msglevel,
2895 .nway_reset = bnx2x_nway_reset,
2896 .get_link = bnx2x_get_link,
2897 .get_eeprom_len = bnx2x_get_eeprom_len,
2898 .get_eeprom = bnx2x_get_eeprom,
2899 .set_eeprom = bnx2x_set_eeprom,
2900 .get_coalesce = bnx2x_get_coalesce,
2901 .set_coalesce = bnx2x_set_coalesce,
2902 .get_ringparam = bnx2x_get_ringparam,
2903 .set_ringparam = bnx2x_set_ringparam,
2904 .get_pauseparam = bnx2x_get_pauseparam,
2905 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2906 .self_test = bnx2x_self_test,
2907 .get_sset_count = bnx2x_get_sset_count,
2908 .get_strings = bnx2x_get_strings,
32d36134 2909 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2910 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3 2911 .get_rxnfc = bnx2x_get_rxnfc,
5d317c6a 2912 .set_rxnfc = bnx2x_set_rxnfc,
7850f63f 2913 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
ab532cf3
TH		 2914 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2915 .set_rxfh_indir = bnx2x_set_rxfh_indir,
0e8d2ec5
MS		 2916 .get_channels = bnx2x_get_channels,
2917 .set_channels = bnx2x_set_channels,
e9939c80
YM		 2918 .get_eee = bnx2x_get_eee,
2919 .set_eee = bnx2x_set_eee,
de0c62db
DK		 2920};
2921
2922void bnx2x_set_ethtool_ops(struct net_device *netdev)
2923{
2924 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2925}
Linux 6.x block layer and io_uring tree(s)