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de0c62db DK |
1 | /* bnx2x_ethtool.c: Broadcom Everest network driver. |
2 | * | |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
de0c62db DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
f1deab50 JP |
17 | |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
19 | ||
de0c62db DK |
20 | #include <linux/ethtool.h> |
21 | #include <linux/netdevice.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/crc32.h> | |
25 | ||
26 | ||
27 | #include "bnx2x.h" | |
28 | #include "bnx2x_cmn.h" | |
29 | #include "bnx2x_dump.h" | |
4a33bc03 | 30 | #include "bnx2x_init.h" |
042181f5 | 31 | #include "bnx2x_sp.h" |
de0c62db | 32 | |
ec6ba945 VZ |
33 | /* Note: in the format strings below %s is replaced by the queue-name which is |
34 | * either its index or 'fcoe' for the fcoe queue. Make sure the format string | |
35 | * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2 | |
36 | */ | |
37 | #define MAX_QUEUE_NAME_LEN 4 | |
38 | static const struct { | |
39 | long offset; | |
40 | int size; | |
41 | char string[ETH_GSTRING_LEN]; | |
42 | } bnx2x_q_stats_arr[] = { | |
43 | /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" }, | |
ec6ba945 VZ |
44 | { Q_STATS_OFFSET32(total_unicast_packets_received_hi), |
45 | 8, "[%s]: rx_ucast_packets" }, | |
46 | { Q_STATS_OFFSET32(total_multicast_packets_received_hi), | |
47 | 8, "[%s]: rx_mcast_packets" }, | |
48 | { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), | |
49 | 8, "[%s]: rx_bcast_packets" }, | |
50 | { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" }, | |
51 | { Q_STATS_OFFSET32(rx_err_discard_pkt), | |
52 | 4, "[%s]: rx_phy_ip_err_discards"}, | |
53 | { Q_STATS_OFFSET32(rx_skb_alloc_failed), | |
54 | 4, "[%s]: rx_skb_alloc_discard" }, | |
55 | { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" }, | |
56 | ||
619c5cb6 VZ |
57 | { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" }, |
58 | /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), | |
ec6ba945 VZ |
59 | 8, "[%s]: tx_ucast_packets" }, |
60 | { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), | |
61 | 8, "[%s]: tx_mcast_packets" }, | |
62 | { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), | |
619c5cb6 VZ |
63 | 8, "[%s]: tx_bcast_packets" }, |
64 | { Q_STATS_OFFSET32(total_tpa_aggregations_hi), | |
65 | 8, "[%s]: tpa_aggregations" }, | |
66 | { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), | |
67 | 8, "[%s]: tpa_aggregated_frames"}, | |
68 | { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"} | |
ec6ba945 VZ |
69 | }; |
70 | ||
71 | #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr) | |
72 | ||
73 | static const struct { | |
74 | long offset; | |
75 | int size; | |
76 | u32 flags; | |
77 | #define STATS_FLAGS_PORT 1 | |
78 | #define STATS_FLAGS_FUNC 2 | |
79 | #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) | |
80 | char string[ETH_GSTRING_LEN]; | |
81 | } bnx2x_stats_arr[] = { | |
82 | /* 1 */ { STATS_OFFSET32(total_bytes_received_hi), | |
83 | 8, STATS_FLAGS_BOTH, "rx_bytes" }, | |
84 | { STATS_OFFSET32(error_bytes_received_hi), | |
85 | 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, | |
86 | { STATS_OFFSET32(total_unicast_packets_received_hi), | |
87 | 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, | |
88 | { STATS_OFFSET32(total_multicast_packets_received_hi), | |
89 | 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, | |
90 | { STATS_OFFSET32(total_broadcast_packets_received_hi), | |
91 | 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, | |
92 | { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), | |
93 | 8, STATS_FLAGS_PORT, "rx_crc_errors" }, | |
94 | { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), | |
95 | 8, STATS_FLAGS_PORT, "rx_align_errors" }, | |
96 | { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), | |
97 | 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, | |
98 | { STATS_OFFSET32(etherstatsoverrsizepkts_hi), | |
99 | 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, | |
100 | /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi), | |
101 | 8, STATS_FLAGS_PORT, "rx_fragments" }, | |
102 | { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), | |
103 | 8, STATS_FLAGS_PORT, "rx_jabbers" }, | |
104 | { STATS_OFFSET32(no_buff_discard_hi), | |
105 | 8, STATS_FLAGS_BOTH, "rx_discards" }, | |
106 | { STATS_OFFSET32(mac_filter_discard), | |
107 | 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, | |
619c5cb6 VZ |
108 | { STATS_OFFSET32(mf_tag_discard), |
109 | 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, | |
0e898dd7 BW |
110 | { STATS_OFFSET32(pfc_frames_received_hi), |
111 | 8, STATS_FLAGS_PORT, "pfc_frames_received" }, | |
112 | { STATS_OFFSET32(pfc_frames_sent_hi), | |
113 | 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, | |
ec6ba945 VZ |
114 | { STATS_OFFSET32(brb_drop_hi), |
115 | 8, STATS_FLAGS_PORT, "rx_brb_discard" }, | |
116 | { STATS_OFFSET32(brb_truncate_hi), | |
117 | 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, | |
118 | { STATS_OFFSET32(pause_frames_received_hi), | |
119 | 8, STATS_FLAGS_PORT, "rx_pause_frames" }, | |
120 | { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), | |
121 | 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, | |
122 | { STATS_OFFSET32(nig_timer_max), | |
123 | 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, | |
124 | /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt), | |
125 | 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"}, | |
126 | { STATS_OFFSET32(rx_skb_alloc_failed), | |
127 | 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" }, | |
128 | { STATS_OFFSET32(hw_csum_err), | |
129 | 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" }, | |
130 | ||
131 | { STATS_OFFSET32(total_bytes_transmitted_hi), | |
132 | 8, STATS_FLAGS_BOTH, "tx_bytes" }, | |
133 | { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), | |
134 | 8, STATS_FLAGS_PORT, "tx_error_bytes" }, | |
135 | { STATS_OFFSET32(total_unicast_packets_transmitted_hi), | |
136 | 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, | |
137 | { STATS_OFFSET32(total_multicast_packets_transmitted_hi), | |
138 | 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, | |
139 | { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), | |
140 | 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, | |
141 | { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), | |
142 | 8, STATS_FLAGS_PORT, "tx_mac_errors" }, | |
143 | { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), | |
144 | 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, | |
145 | /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), | |
146 | 8, STATS_FLAGS_PORT, "tx_single_collisions" }, | |
147 | { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), | |
148 | 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, | |
149 | { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), | |
150 | 8, STATS_FLAGS_PORT, "tx_deferred" }, | |
151 | { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), | |
152 | 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, | |
153 | { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), | |
154 | 8, STATS_FLAGS_PORT, "tx_late_collisions" }, | |
155 | { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), | |
156 | 8, STATS_FLAGS_PORT, "tx_total_collisions" }, | |
157 | { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), | |
158 | 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, | |
159 | { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), | |
160 | 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, | |
161 | { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), | |
162 | 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, | |
163 | { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), | |
164 | 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, | |
165 | /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), | |
166 | 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, | |
167 | { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), | |
168 | 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, | |
169 | { STATS_OFFSET32(etherstatspktsover1522octets_hi), | |
170 | 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, | |
171 | { STATS_OFFSET32(pause_frames_sent_hi), | |
619c5cb6 VZ |
172 | 8, STATS_FLAGS_PORT, "tx_pause_frames" }, |
173 | { STATS_OFFSET32(total_tpa_aggregations_hi), | |
174 | 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, | |
175 | { STATS_OFFSET32(total_tpa_aggregated_frames_hi), | |
176 | 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, | |
177 | { STATS_OFFSET32(total_tpa_bytes_hi), | |
7a752993 AE |
178 | 8, STATS_FLAGS_FUNC, "tpa_bytes"}, |
179 | { STATS_OFFSET32(recoverable_error), | |
180 | 4, STATS_FLAGS_FUNC, "recoverable_errors" }, | |
181 | { STATS_OFFSET32(unrecoverable_error), | |
182 | 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, | |
ec6ba945 VZ |
183 | }; |
184 | ||
185 | #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr) | |
1ac9e428 YR |
186 | static int bnx2x_get_port_type(struct bnx2x *bp) |
187 | { | |
188 | int port_type; | |
189 | u32 phy_idx = bnx2x_get_cur_phy_idx(bp); | |
190 | switch (bp->link_params.phy[phy_idx].media_type) { | |
191 | case ETH_PHY_SFP_FIBER: | |
192 | case ETH_PHY_XFP_FIBER: | |
193 | case ETH_PHY_KR: | |
194 | case ETH_PHY_CX4: | |
195 | port_type = PORT_FIBRE; | |
196 | break; | |
197 | case ETH_PHY_DA_TWINAX: | |
198 | port_type = PORT_DA; | |
199 | break; | |
200 | case ETH_PHY_BASE_T: | |
201 | port_type = PORT_TP; | |
202 | break; | |
203 | case ETH_PHY_NOT_PRESENT: | |
204 | port_type = PORT_NONE; | |
205 | break; | |
206 | case ETH_PHY_UNSPECIFIED: | |
207 | default: | |
208 | port_type = PORT_OTHER; | |
209 | break; | |
210 | } | |
211 | return port_type; | |
212 | } | |
ec6ba945 | 213 | |
de0c62db DK |
214 | static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
215 | { | |
216 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 217 | int cfg_idx = bnx2x_get_link_cfg_idx(bp); |
b3337e4c | 218 | |
a22f0788 YR |
219 | /* Dual Media boards present all available port types */ |
220 | cmd->supported = bp->port.supported[cfg_idx] | | |
221 | (bp->port.supported[cfg_idx ^ 1] & | |
222 | (SUPPORTED_TP | SUPPORTED_FIBRE)); | |
223 | cmd->advertising = bp->port.advertising[cfg_idx]; | |
de0c62db | 224 | |
38298461 YM |
225 | if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) { |
226 | if (!(bp->flags & MF_FUNC_DIS)) { | |
227 | ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed); | |
228 | cmd->duplex = bp->link_vars.duplex; | |
229 | } else { | |
230 | ethtool_cmd_speed_set( | |
231 | cmd, bp->link_params.req_line_speed[cfg_idx]); | |
232 | cmd->duplex = bp->link_params.req_duplex[cfg_idx]; | |
233 | } | |
234 | ||
235 | if (IS_MF(bp) && !BP_NOMCP(bp)) | |
236 | ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp)); | |
de0c62db | 237 | } else { |
38298461 YM |
238 | cmd->duplex = DUPLEX_UNKNOWN; |
239 | ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); | |
de0c62db | 240 | } |
f2e0899f | 241 | |
1ac9e428 | 242 | cmd->port = bnx2x_get_port_type(bp); |
a22f0788 | 243 | |
de0c62db DK |
244 | cmd->phy_address = bp->mdio.prtad; |
245 | cmd->transceiver = XCVR_INTERNAL; | |
246 | ||
a22f0788 | 247 | if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) |
de0c62db DK |
248 | cmd->autoneg = AUTONEG_ENABLE; |
249 | else | |
250 | cmd->autoneg = AUTONEG_DISABLE; | |
251 | ||
9e7e8399 MY |
252 | /* Publish LP advertised speeds and FC */ |
253 | if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
254 | u32 status = bp->link_vars.link_status; | |
255 | ||
256 | cmd->lp_advertising |= ADVERTISED_Autoneg; | |
257 | if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE) | |
258 | cmd->lp_advertising |= ADVERTISED_Pause; | |
259 | if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) | |
260 | cmd->lp_advertising |= ADVERTISED_Asym_Pause; | |
261 | ||
262 | if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE) | |
263 | cmd->lp_advertising |= ADVERTISED_10baseT_Half; | |
264 | if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE) | |
265 | cmd->lp_advertising |= ADVERTISED_10baseT_Full; | |
266 | if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE) | |
267 | cmd->lp_advertising |= ADVERTISED_100baseT_Half; | |
268 | if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE) | |
269 | cmd->lp_advertising |= ADVERTISED_100baseT_Full; | |
270 | if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) | |
271 | cmd->lp_advertising |= ADVERTISED_1000baseT_Half; | |
272 | if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) | |
273 | cmd->lp_advertising |= ADVERTISED_1000baseT_Full; | |
274 | if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE) | |
275 | cmd->lp_advertising |= ADVERTISED_2500baseX_Full; | |
276 | if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) | |
277 | cmd->lp_advertising |= ADVERTISED_10000baseT_Full; | |
278 | } | |
279 | ||
de0c62db DK |
280 | cmd->maxtxpkt = 0; |
281 | cmd->maxrxpkt = 0; | |
282 | ||
51c1a580 | 283 | DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" |
f1deab50 JP |
284 | " supported 0x%x advertising 0x%x speed %u\n" |
285 | " duplex %d port %d phy_address %d transceiver %d\n" | |
286 | " autoneg %d maxtxpkt %d maxrxpkt %d\n", | |
b3337e4c DD |
287 | cmd->cmd, cmd->supported, cmd->advertising, |
288 | ethtool_cmd_speed(cmd), | |
de0c62db DK |
289 | cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, |
290 | cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
296 | { | |
297 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 298 | u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config; |
0793f83f | 299 | u32 speed; |
de0c62db | 300 | |
0793f83f | 301 | if (IS_MF_SD(bp)) |
de0c62db DK |
302 | return 0; |
303 | ||
51c1a580 | 304 | DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n" |
b3337e4c | 305 | " supported 0x%x advertising 0x%x speed %u\n" |
0793f83f DK |
306 | " duplex %d port %d phy_address %d transceiver %d\n" |
307 | " autoneg %d maxtxpkt %d maxrxpkt %d\n", | |
b3337e4c DD |
308 | cmd->cmd, cmd->supported, cmd->advertising, |
309 | ethtool_cmd_speed(cmd), | |
de0c62db DK |
310 | cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver, |
311 | cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt); | |
312 | ||
b3337e4c | 313 | speed = ethtool_cmd_speed(cmd); |
0793f83f | 314 | |
38298461 YM |
315 | /* If recieved a request for an unknown duplex, assume full*/ |
316 | if (cmd->duplex == DUPLEX_UNKNOWN) | |
317 | cmd->duplex = DUPLEX_FULL; | |
318 | ||
0793f83f | 319 | if (IS_MF_SI(bp)) { |
e3835b99 | 320 | u32 part; |
0793f83f DK |
321 | u32 line_speed = bp->link_vars.line_speed; |
322 | ||
323 | /* use 10G if no link detected */ | |
324 | if (!line_speed) | |
325 | line_speed = 10000; | |
326 | ||
327 | if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { | |
51c1a580 MS |
328 | DP(BNX2X_MSG_ETHTOOL, |
329 | "To set speed BC %X or higher is required, please upgrade BC\n", | |
330 | REQ_BC_VER_4_SET_MF_BW); | |
0793f83f DK |
331 | return -EINVAL; |
332 | } | |
e3835b99 | 333 | |
faa6fcbb | 334 | part = (speed * 100) / line_speed; |
e3835b99 | 335 | |
faa6fcbb | 336 | if (line_speed < speed || !part) { |
51c1a580 MS |
337 | DP(BNX2X_MSG_ETHTOOL, |
338 | "Speed setting should be in a range from 1%% to 100%% of actual line speed\n"); | |
0793f83f DK |
339 | return -EINVAL; |
340 | } | |
0793f83f | 341 | |
e3835b99 DK |
342 | if (bp->state != BNX2X_STATE_OPEN) |
343 | /* store value for following "load" */ | |
344 | bp->pending_max = part; | |
345 | else | |
346 | bnx2x_update_max_mf_config(bp, part); | |
0793f83f | 347 | |
0793f83f DK |
348 | return 0; |
349 | } | |
350 | ||
a22f0788 YR |
351 | cfg_idx = bnx2x_get_link_cfg_idx(bp); |
352 | old_multi_phy_config = bp->link_params.multi_phy_config; | |
353 | switch (cmd->port) { | |
354 | case PORT_TP: | |
355 | if (bp->port.supported[cfg_idx] & SUPPORTED_TP) | |
356 | break; /* no port change */ | |
357 | ||
358 | if (!(bp->port.supported[0] & SUPPORTED_TP || | |
359 | bp->port.supported[1] & SUPPORTED_TP)) { | |
51c1a580 | 360 | DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); |
a22f0788 YR |
361 | return -EINVAL; |
362 | } | |
363 | bp->link_params.multi_phy_config &= | |
364 | ~PORT_HW_CFG_PHY_SELECTION_MASK; | |
365 | if (bp->link_params.multi_phy_config & | |
366 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) | |
367 | bp->link_params.multi_phy_config |= | |
368 | PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
369 | else | |
370 | bp->link_params.multi_phy_config |= | |
371 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
372 | break; | |
373 | case PORT_FIBRE: | |
bfdb5823 | 374 | case PORT_DA: |
a22f0788 YR |
375 | if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) |
376 | break; /* no port change */ | |
377 | ||
378 | if (!(bp->port.supported[0] & SUPPORTED_FIBRE || | |
379 | bp->port.supported[1] & SUPPORTED_FIBRE)) { | |
51c1a580 | 380 | DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); |
a22f0788 YR |
381 | return -EINVAL; |
382 | } | |
383 | bp->link_params.multi_phy_config &= | |
384 | ~PORT_HW_CFG_PHY_SELECTION_MASK; | |
385 | if (bp->link_params.multi_phy_config & | |
386 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) | |
387 | bp->link_params.multi_phy_config |= | |
388 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
389 | else | |
390 | bp->link_params.multi_phy_config |= | |
391 | PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
392 | break; | |
393 | default: | |
51c1a580 | 394 | DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n"); |
a22f0788 YR |
395 | return -EINVAL; |
396 | } | |
2f751a80 | 397 | /* Save new config in case command complete successully */ |
a22f0788 YR |
398 | new_multi_phy_config = bp->link_params.multi_phy_config; |
399 | /* Get the new cfg_idx */ | |
400 | cfg_idx = bnx2x_get_link_cfg_idx(bp); | |
401 | /* Restore old config in case command failed */ | |
402 | bp->link_params.multi_phy_config = old_multi_phy_config; | |
51c1a580 | 403 | DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx); |
a22f0788 | 404 | |
de0c62db | 405 | if (cmd->autoneg == AUTONEG_ENABLE) { |
75318327 YR |
406 | u32 an_supported_speed = bp->port.supported[cfg_idx]; |
407 | if (bp->link_params.phy[EXT_PHY1].type == | |
408 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
409 | an_supported_speed |= (SUPPORTED_100baseT_Half | | |
410 | SUPPORTED_100baseT_Full); | |
a22f0788 | 411 | if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { |
51c1a580 | 412 | DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n"); |
de0c62db DK |
413 | return -EINVAL; |
414 | } | |
415 | ||
416 | /* advertise the requested speed and duplex if supported */ | |
75318327 | 417 | if (cmd->advertising & ~an_supported_speed) { |
51c1a580 MS |
418 | DP(BNX2X_MSG_ETHTOOL, |
419 | "Advertisement parameters are not supported\n"); | |
8d661637 YR |
420 | return -EINVAL; |
421 | } | |
de0c62db | 422 | |
a22f0788 | 423 | bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; |
8d661637 YR |
424 | bp->link_params.req_duplex[cfg_idx] = cmd->duplex; |
425 | bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | | |
de0c62db | 426 | cmd->advertising); |
8d661637 YR |
427 | if (cmd->advertising) { |
428 | ||
429 | bp->link_params.speed_cap_mask[cfg_idx] = 0; | |
430 | if (cmd->advertising & ADVERTISED_10baseT_Half) { | |
431 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
432 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; | |
433 | } | |
434 | if (cmd->advertising & ADVERTISED_10baseT_Full) | |
435 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
436 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; | |
de0c62db | 437 | |
8d661637 YR |
438 | if (cmd->advertising & ADVERTISED_100baseT_Full) |
439 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
440 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; | |
441 | ||
442 | if (cmd->advertising & ADVERTISED_100baseT_Half) { | |
443 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
444 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; | |
445 | } | |
446 | if (cmd->advertising & ADVERTISED_1000baseT_Half) { | |
447 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
448 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; | |
449 | } | |
450 | if (cmd->advertising & (ADVERTISED_1000baseT_Full | | |
451 | ADVERTISED_1000baseKX_Full)) | |
452 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
453 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; | |
454 | ||
455 | if (cmd->advertising & (ADVERTISED_10000baseT_Full | | |
456 | ADVERTISED_10000baseKX4_Full | | |
457 | ADVERTISED_10000baseKR_Full)) | |
458 | bp->link_params.speed_cap_mask[cfg_idx] |= | |
459 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; | |
460 | } | |
de0c62db DK |
461 | } else { /* forced speed */ |
462 | /* advertise the requested speed and duplex if supported */ | |
a22f0788 | 463 | switch (speed) { |
de0c62db DK |
464 | case SPEED_10: |
465 | if (cmd->duplex == DUPLEX_FULL) { | |
a22f0788 | 466 | if (!(bp->port.supported[cfg_idx] & |
de0c62db | 467 | SUPPORTED_10baseT_Full)) { |
51c1a580 | 468 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
469 | "10M full not supported\n"); |
470 | return -EINVAL; | |
471 | } | |
472 | ||
473 | advertising = (ADVERTISED_10baseT_Full | | |
474 | ADVERTISED_TP); | |
475 | } else { | |
a22f0788 | 476 | if (!(bp->port.supported[cfg_idx] & |
de0c62db | 477 | SUPPORTED_10baseT_Half)) { |
51c1a580 | 478 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
479 | "10M half not supported\n"); |
480 | return -EINVAL; | |
481 | } | |
482 | ||
483 | advertising = (ADVERTISED_10baseT_Half | | |
484 | ADVERTISED_TP); | |
485 | } | |
486 | break; | |
487 | ||
488 | case SPEED_100: | |
489 | if (cmd->duplex == DUPLEX_FULL) { | |
a22f0788 | 490 | if (!(bp->port.supported[cfg_idx] & |
de0c62db | 491 | SUPPORTED_100baseT_Full)) { |
51c1a580 | 492 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
493 | "100M full not supported\n"); |
494 | return -EINVAL; | |
495 | } | |
496 | ||
497 | advertising = (ADVERTISED_100baseT_Full | | |
498 | ADVERTISED_TP); | |
499 | } else { | |
a22f0788 | 500 | if (!(bp->port.supported[cfg_idx] & |
de0c62db | 501 | SUPPORTED_100baseT_Half)) { |
51c1a580 | 502 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
503 | "100M half not supported\n"); |
504 | return -EINVAL; | |
505 | } | |
506 | ||
507 | advertising = (ADVERTISED_100baseT_Half | | |
508 | ADVERTISED_TP); | |
509 | } | |
510 | break; | |
511 | ||
512 | case SPEED_1000: | |
513 | if (cmd->duplex != DUPLEX_FULL) { | |
51c1a580 MS |
514 | DP(BNX2X_MSG_ETHTOOL, |
515 | "1G half not supported\n"); | |
de0c62db DK |
516 | return -EINVAL; |
517 | } | |
518 | ||
a22f0788 YR |
519 | if (!(bp->port.supported[cfg_idx] & |
520 | SUPPORTED_1000baseT_Full)) { | |
51c1a580 MS |
521 | DP(BNX2X_MSG_ETHTOOL, |
522 | "1G full not supported\n"); | |
de0c62db DK |
523 | return -EINVAL; |
524 | } | |
525 | ||
526 | advertising = (ADVERTISED_1000baseT_Full | | |
527 | ADVERTISED_TP); | |
528 | break; | |
529 | ||
530 | case SPEED_2500: | |
531 | if (cmd->duplex != DUPLEX_FULL) { | |
51c1a580 | 532 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
533 | "2.5G half not supported\n"); |
534 | return -EINVAL; | |
535 | } | |
536 | ||
a22f0788 YR |
537 | if (!(bp->port.supported[cfg_idx] |
538 | & SUPPORTED_2500baseX_Full)) { | |
51c1a580 | 539 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
540 | "2.5G full not supported\n"); |
541 | return -EINVAL; | |
542 | } | |
543 | ||
544 | advertising = (ADVERTISED_2500baseX_Full | | |
545 | ADVERTISED_TP); | |
546 | break; | |
547 | ||
548 | case SPEED_10000: | |
549 | if (cmd->duplex != DUPLEX_FULL) { | |
51c1a580 MS |
550 | DP(BNX2X_MSG_ETHTOOL, |
551 | "10G half not supported\n"); | |
de0c62db DK |
552 | return -EINVAL; |
553 | } | |
554 | ||
a22f0788 YR |
555 | if (!(bp->port.supported[cfg_idx] |
556 | & SUPPORTED_10000baseT_Full)) { | |
51c1a580 MS |
557 | DP(BNX2X_MSG_ETHTOOL, |
558 | "10G full not supported\n"); | |
de0c62db DK |
559 | return -EINVAL; |
560 | } | |
561 | ||
562 | advertising = (ADVERTISED_10000baseT_Full | | |
563 | ADVERTISED_FIBRE); | |
564 | break; | |
565 | ||
566 | default: | |
51c1a580 | 567 | DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed); |
de0c62db DK |
568 | return -EINVAL; |
569 | } | |
570 | ||
a22f0788 YR |
571 | bp->link_params.req_line_speed[cfg_idx] = speed; |
572 | bp->link_params.req_duplex[cfg_idx] = cmd->duplex; | |
573 | bp->port.advertising[cfg_idx] = advertising; | |
de0c62db DK |
574 | } |
575 | ||
51c1a580 | 576 | DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n" |
f1deab50 | 577 | " req_duplex %d advertising 0x%x\n", |
a22f0788 YR |
578 | bp->link_params.req_line_speed[cfg_idx], |
579 | bp->link_params.req_duplex[cfg_idx], | |
580 | bp->port.advertising[cfg_idx]); | |
de0c62db | 581 | |
a22f0788 YR |
582 | /* Set new config */ |
583 | bp->link_params.multi_phy_config = new_multi_phy_config; | |
de0c62db DK |
584 | if (netif_running(dev)) { |
585 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
586 | bnx2x_link_set(bp); | |
587 | } | |
588 | ||
589 | return 0; | |
590 | } | |
591 | ||
592 | #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE) | |
593 | #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE) | |
f2e0899f | 594 | #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE) |
0fea29c1 VZ |
595 | #define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE) |
596 | #define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE) | |
597 | ||
598 | static inline bool bnx2x_is_reg_online(struct bnx2x *bp, | |
599 | const struct reg_addr *reg_info) | |
600 | { | |
601 | if (CHIP_IS_E1(bp)) | |
602 | return IS_E1_ONLINE(reg_info->info); | |
603 | else if (CHIP_IS_E1H(bp)) | |
604 | return IS_E1H_ONLINE(reg_info->info); | |
605 | else if (CHIP_IS_E2(bp)) | |
606 | return IS_E2_ONLINE(reg_info->info); | |
607 | else if (CHIP_IS_E3A0(bp)) | |
608 | return IS_E3_ONLINE(reg_info->info); | |
609 | else if (CHIP_IS_E3B0(bp)) | |
610 | return IS_E3B0_ONLINE(reg_info->info); | |
611 | else | |
612 | return false; | |
613 | } | |
614 | ||
615 | /******* Paged registers info selectors ********/ | |
616 | static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp) | |
617 | { | |
618 | if (CHIP_IS_E2(bp)) | |
619 | return page_vals_e2; | |
620 | else if (CHIP_IS_E3(bp)) | |
621 | return page_vals_e3; | |
622 | else | |
623 | return NULL; | |
624 | } | |
625 | ||
626 | static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp) | |
627 | { | |
628 | if (CHIP_IS_E2(bp)) | |
629 | return PAGE_MODE_VALUES_E2; | |
630 | else if (CHIP_IS_E3(bp)) | |
631 | return PAGE_MODE_VALUES_E3; | |
632 | else | |
633 | return 0; | |
634 | } | |
635 | ||
636 | static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp) | |
637 | { | |
638 | if (CHIP_IS_E2(bp)) | |
639 | return page_write_regs_e2; | |
640 | else if (CHIP_IS_E3(bp)) | |
641 | return page_write_regs_e3; | |
642 | else | |
643 | return NULL; | |
644 | } | |
645 | ||
646 | static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp) | |
647 | { | |
648 | if (CHIP_IS_E2(bp)) | |
649 | return PAGE_WRITE_REGS_E2; | |
650 | else if (CHIP_IS_E3(bp)) | |
651 | return PAGE_WRITE_REGS_E3; | |
652 | else | |
653 | return 0; | |
654 | } | |
655 | ||
656 | static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp) | |
657 | { | |
658 | if (CHIP_IS_E2(bp)) | |
659 | return page_read_regs_e2; | |
660 | else if (CHIP_IS_E3(bp)) | |
661 | return page_read_regs_e3; | |
662 | else | |
663 | return NULL; | |
664 | } | |
665 | ||
666 | static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp) | |
667 | { | |
668 | if (CHIP_IS_E2(bp)) | |
669 | return PAGE_READ_REGS_E2; | |
670 | else if (CHIP_IS_E3(bp)) | |
671 | return PAGE_READ_REGS_E3; | |
672 | else | |
673 | return 0; | |
674 | } | |
675 | ||
676 | static inline int __bnx2x_get_regs_len(struct bnx2x *bp) | |
677 | { | |
678 | int num_pages = __bnx2x_get_page_reg_num(bp); | |
679 | int page_write_num = __bnx2x_get_page_write_num(bp); | |
680 | const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp); | |
681 | int page_read_num = __bnx2x_get_page_read_num(bp); | |
682 | int regdump_len = 0; | |
683 | int i, j, k; | |
684 | ||
685 | for (i = 0; i < REGS_COUNT; i++) | |
686 | if (bnx2x_is_reg_online(bp, ®_addrs[i])) | |
687 | regdump_len += reg_addrs[i].size; | |
688 | ||
689 | for (i = 0; i < num_pages; i++) | |
690 | for (j = 0; j < page_write_num; j++) | |
691 | for (k = 0; k < page_read_num; k++) | |
692 | if (bnx2x_is_reg_online(bp, &page_read_addr[k])) | |
693 | regdump_len += page_read_addr[k].size; | |
694 | ||
695 | return regdump_len; | |
696 | } | |
de0c62db DK |
697 | |
698 | static int bnx2x_get_regs_len(struct net_device *dev) | |
699 | { | |
700 | struct bnx2x *bp = netdev_priv(dev); | |
701 | int regdump_len = 0; | |
de0c62db | 702 | |
0fea29c1 | 703 | regdump_len = __bnx2x_get_regs_len(bp); |
de0c62db DK |
704 | regdump_len *= 4; |
705 | regdump_len += sizeof(struct dump_hdr); | |
706 | ||
707 | return regdump_len; | |
708 | } | |
709 | ||
0fea29c1 VZ |
710 | /** |
711 | * bnx2x_read_pages_regs - read "paged" registers | |
712 | * | |
713 | * @bp device handle | |
714 | * @p output buffer | |
715 | * | |
716 | * Reads "paged" memories: memories that may only be read by first writing to a | |
717 | * specific address ("write address") and then reading from a specific address | |
718 | * ("read address"). There may be more than one write address per "page" and | |
719 | * more than one read address per write address. | |
720 | */ | |
721 | static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p) | |
f2e0899f DK |
722 | { |
723 | u32 i, j, k, n; | |
0fea29c1 VZ |
724 | /* addresses of the paged registers */ |
725 | const u32 *page_addr = __bnx2x_get_page_addr_ar(bp); | |
726 | /* number of paged registers */ | |
727 | int num_pages = __bnx2x_get_page_reg_num(bp); | |
728 | /* write addresses */ | |
729 | const u32 *write_addr = __bnx2x_get_page_write_ar(bp); | |
730 | /* number of write addresses */ | |
731 | int write_num = __bnx2x_get_page_write_num(bp); | |
732 | /* read addresses info */ | |
733 | const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp); | |
734 | /* number of read addresses */ | |
735 | int read_num = __bnx2x_get_page_read_num(bp); | |
736 | ||
737 | for (i = 0; i < num_pages; i++) { | |
738 | for (j = 0; j < write_num; j++) { | |
739 | REG_WR(bp, write_addr[j], page_addr[i]); | |
740 | for (k = 0; k < read_num; k++) | |
741 | if (bnx2x_is_reg_online(bp, &read_addr[k])) | |
f2e0899f | 742 | for (n = 0; n < |
0fea29c1 | 743 | read_addr[k].size; n++) |
f2e0899f | 744 | *p++ = REG_RD(bp, |
0fea29c1 | 745 | read_addr[k].addr + n*4); |
f2e0899f DK |
746 | } |
747 | } | |
748 | } | |
749 | ||
0fea29c1 VZ |
750 | static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p) |
751 | { | |
752 | u32 i, j; | |
753 | ||
754 | /* Read the regular registers */ | |
755 | for (i = 0; i < REGS_COUNT; i++) | |
756 | if (bnx2x_is_reg_online(bp, ®_addrs[i])) | |
757 | for (j = 0; j < reg_addrs[i].size; j++) | |
758 | *p++ = REG_RD(bp, reg_addrs[i].addr + j*4); | |
759 | ||
760 | /* Read "paged" registes */ | |
761 | bnx2x_read_pages_regs(bp, p); | |
762 | } | |
763 | ||
de0c62db DK |
764 | static void bnx2x_get_regs(struct net_device *dev, |
765 | struct ethtool_regs *regs, void *_p) | |
766 | { | |
0fea29c1 | 767 | u32 *p = _p; |
de0c62db DK |
768 | struct bnx2x *bp = netdev_priv(dev); |
769 | struct dump_hdr dump_hdr = {0}; | |
770 | ||
771 | regs->version = 0; | |
772 | memset(p, 0, regs->len); | |
773 | ||
774 | if (!netif_running(bp->dev)) | |
775 | return; | |
776 | ||
4a33bc03 VZ |
777 | /* Disable parity attentions as long as following dump may |
778 | * cause false alarms by reading never written registers. We | |
779 | * will re-enable parity attentions right after the dump. | |
780 | */ | |
781 | bnx2x_disable_blocks_parity(bp); | |
782 | ||
de0c62db DK |
783 | dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1; |
784 | dump_hdr.dump_sign = dump_sign_all; | |
785 | dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR); | |
786 | dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR); | |
787 | dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR); | |
788 | dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR); | |
f2e0899f DK |
789 | |
790 | if (CHIP_IS_E1(bp)) | |
791 | dump_hdr.info = RI_E1_ONLINE; | |
792 | else if (CHIP_IS_E1H(bp)) | |
793 | dump_hdr.info = RI_E1H_ONLINE; | |
619c5cb6 | 794 | else if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
795 | dump_hdr.info = RI_E2_ONLINE | |
796 | (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP); | |
de0c62db DK |
797 | |
798 | memcpy(p, &dump_hdr, sizeof(struct dump_hdr)); | |
799 | p += dump_hdr.hdr_size + 1; | |
800 | ||
0fea29c1 VZ |
801 | /* Actually read the registers */ |
802 | __bnx2x_get_regs(bp, p); | |
803 | ||
4a33bc03 VZ |
804 | /* Re-enable parity attentions */ |
805 | bnx2x_clear_blocks_parity(bp); | |
c9ee9206 | 806 | bnx2x_enable_blocks_parity(bp); |
de0c62db DK |
807 | } |
808 | ||
de0c62db DK |
809 | static void bnx2x_get_drvinfo(struct net_device *dev, |
810 | struct ethtool_drvinfo *info) | |
811 | { | |
812 | struct bnx2x *bp = netdev_priv(dev); | |
813 | u8 phy_fw_ver[PHY_FW_VER_LEN]; | |
814 | ||
68aad78c RJ |
815 | strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); |
816 | strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); | |
de0c62db DK |
817 | |
818 | phy_fw_ver[0] = '\0'; | |
a1e785e0 MY |
819 | bnx2x_get_ext_phy_fw_version(&bp->link_params, |
820 | phy_fw_ver, PHY_FW_VER_LEN); | |
68aad78c | 821 | strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version)); |
de0c62db DK |
822 | snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver), |
823 | "bc %d.%d.%d%s%s", | |
824 | (bp->common.bc_ver & 0xff0000) >> 16, | |
825 | (bp->common.bc_ver & 0xff00) >> 8, | |
826 | (bp->common.bc_ver & 0xff), | |
827 | ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver); | |
68aad78c | 828 | strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info)); |
de0c62db DK |
829 | info->n_stats = BNX2X_NUM_STATS; |
830 | info->testinfo_len = BNX2X_NUM_TESTS; | |
831 | info->eedump_len = bp->common.flash_size; | |
832 | info->regdump_len = bnx2x_get_regs_len(dev); | |
833 | } | |
834 | ||
835 | static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
836 | { | |
837 | struct bnx2x *bp = netdev_priv(dev); | |
838 | ||
839 | if (bp->flags & NO_WOL_FLAG) { | |
840 | wol->supported = 0; | |
841 | wol->wolopts = 0; | |
842 | } else { | |
843 | wol->supported = WAKE_MAGIC; | |
844 | if (bp->wol) | |
845 | wol->wolopts = WAKE_MAGIC; | |
846 | else | |
847 | wol->wolopts = 0; | |
848 | } | |
849 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
850 | } | |
851 | ||
852 | static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
853 | { | |
854 | struct bnx2x *bp = netdev_priv(dev); | |
855 | ||
51c1a580 MS |
856 | if (wol->wolopts & ~WAKE_MAGIC) { |
857 | DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n"); | |
de0c62db | 858 | return -EINVAL; |
51c1a580 | 859 | } |
de0c62db DK |
860 | |
861 | if (wol->wolopts & WAKE_MAGIC) { | |
51c1a580 MS |
862 | if (bp->flags & NO_WOL_FLAG) { |
863 | DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n"); | |
de0c62db | 864 | return -EINVAL; |
51c1a580 | 865 | } |
de0c62db DK |
866 | bp->wol = 1; |
867 | } else | |
868 | bp->wol = 0; | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | static u32 bnx2x_get_msglevel(struct net_device *dev) | |
874 | { | |
875 | struct bnx2x *bp = netdev_priv(dev); | |
876 | ||
877 | return bp->msg_enable; | |
878 | } | |
879 | ||
880 | static void bnx2x_set_msglevel(struct net_device *dev, u32 level) | |
881 | { | |
882 | struct bnx2x *bp = netdev_priv(dev); | |
883 | ||
7a25cc73 DK |
884 | if (capable(CAP_NET_ADMIN)) { |
885 | /* dump MCP trace */ | |
886 | if (level & BNX2X_MSG_MCP) | |
887 | bnx2x_fw_dump_lvl(bp, KERN_INFO); | |
de0c62db | 888 | bp->msg_enable = level; |
7a25cc73 | 889 | } |
de0c62db DK |
890 | } |
891 | ||
892 | static int bnx2x_nway_reset(struct net_device *dev) | |
893 | { | |
894 | struct bnx2x *bp = netdev_priv(dev); | |
895 | ||
896 | if (!bp->port.pmf) | |
897 | return 0; | |
898 | ||
899 | if (netif_running(dev)) { | |
900 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
901 | bnx2x_link_set(bp); | |
902 | } | |
903 | ||
904 | return 0; | |
905 | } | |
906 | ||
907 | static u32 bnx2x_get_link(struct net_device *dev) | |
908 | { | |
909 | struct bnx2x *bp = netdev_priv(dev); | |
910 | ||
f2e0899f | 911 | if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN)) |
de0c62db DK |
912 | return 0; |
913 | ||
914 | return bp->link_vars.link_up; | |
915 | } | |
916 | ||
917 | static int bnx2x_get_eeprom_len(struct net_device *dev) | |
918 | { | |
919 | struct bnx2x *bp = netdev_priv(dev); | |
920 | ||
921 | return bp->common.flash_size; | |
922 | } | |
923 | ||
f16da43b AE |
924 | /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had |
925 | * we done things the other way around, if two pfs from the same port would | |
926 | * attempt to access nvram at the same time, we could run into a scenario such | |
927 | * as: | |
928 | * pf A takes the port lock. | |
929 | * pf B succeeds in taking the same lock since they are from the same port. | |
930 | * pf A takes the per pf misc lock. Performs eeprom access. | |
931 | * pf A finishes. Unlocks the per pf misc lock. | |
932 | * Pf B takes the lock and proceeds to perform it's own access. | |
933 | * pf A unlocks the per port lock, while pf B is still working (!). | |
934 | * mcp takes the per port lock and corrupts pf B's access (and/or has it's own | |
935 | * acess corrupted by pf B).* | |
936 | */ | |
de0c62db DK |
937 | static int bnx2x_acquire_nvram_lock(struct bnx2x *bp) |
938 | { | |
939 | int port = BP_PORT(bp); | |
940 | int count, i; | |
f16da43b AE |
941 | u32 val; |
942 | ||
943 | /* acquire HW lock: protect against other PFs in PF Direct Assignment */ | |
944 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); | |
de0c62db DK |
945 | |
946 | /* adjust timeout for emulation/FPGA */ | |
754a2f52 | 947 | count = BNX2X_NVRAM_TIMEOUT_COUNT; |
de0c62db DK |
948 | if (CHIP_REV_IS_SLOW(bp)) |
949 | count *= 100; | |
950 | ||
951 | /* request access to nvram interface */ | |
952 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
953 | (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); | |
954 | ||
955 | for (i = 0; i < count*10; i++) { | |
956 | val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); | |
957 | if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) | |
958 | break; | |
959 | ||
960 | udelay(5); | |
961 | } | |
962 | ||
963 | if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { | |
51c1a580 MS |
964 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
965 | "cannot get access to nvram interface\n"); | |
de0c62db DK |
966 | return -EBUSY; |
967 | } | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
972 | static int bnx2x_release_nvram_lock(struct bnx2x *bp) | |
973 | { | |
974 | int port = BP_PORT(bp); | |
975 | int count, i; | |
f16da43b | 976 | u32 val; |
de0c62db DK |
977 | |
978 | /* adjust timeout for emulation/FPGA */ | |
754a2f52 | 979 | count = BNX2X_NVRAM_TIMEOUT_COUNT; |
de0c62db DK |
980 | if (CHIP_REV_IS_SLOW(bp)) |
981 | count *= 100; | |
982 | ||
983 | /* relinquish nvram interface */ | |
984 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
985 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); | |
986 | ||
987 | for (i = 0; i < count*10; i++) { | |
988 | val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB); | |
989 | if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) | |
990 | break; | |
991 | ||
992 | udelay(5); | |
993 | } | |
994 | ||
995 | if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { | |
51c1a580 MS |
996 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
997 | "cannot free access to nvram interface\n"); | |
de0c62db DK |
998 | return -EBUSY; |
999 | } | |
1000 | ||
f16da43b AE |
1001 | /* release HW lock: protect against other PFs in PF Direct Assignment */ |
1002 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM); | |
de0c62db DK |
1003 | return 0; |
1004 | } | |
1005 | ||
1006 | static void bnx2x_enable_nvram_access(struct bnx2x *bp) | |
1007 | { | |
1008 | u32 val; | |
1009 | ||
1010 | val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); | |
1011 | ||
1012 | /* enable both bits, even on read */ | |
1013 | REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, | |
1014 | (val | MCPR_NVM_ACCESS_ENABLE_EN | | |
1015 | MCPR_NVM_ACCESS_ENABLE_WR_EN)); | |
1016 | } | |
1017 | ||
1018 | static void bnx2x_disable_nvram_access(struct bnx2x *bp) | |
1019 | { | |
1020 | u32 val; | |
1021 | ||
1022 | val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE); | |
1023 | ||
1024 | /* disable both bits, even after read */ | |
1025 | REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, | |
1026 | (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | | |
1027 | MCPR_NVM_ACCESS_ENABLE_WR_EN))); | |
1028 | } | |
1029 | ||
1030 | static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val, | |
1031 | u32 cmd_flags) | |
1032 | { | |
1033 | int count, i, rc; | |
1034 | u32 val; | |
1035 | ||
1036 | /* build the command word */ | |
1037 | cmd_flags |= MCPR_NVM_COMMAND_DOIT; | |
1038 | ||
1039 | /* need to clear DONE bit separately */ | |
1040 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); | |
1041 | ||
1042 | /* address of the NVRAM to read from */ | |
1043 | REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, | |
1044 | (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); | |
1045 | ||
1046 | /* issue a read command */ | |
1047 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); | |
1048 | ||
1049 | /* adjust timeout for emulation/FPGA */ | |
754a2f52 | 1050 | count = BNX2X_NVRAM_TIMEOUT_COUNT; |
de0c62db DK |
1051 | if (CHIP_REV_IS_SLOW(bp)) |
1052 | count *= 100; | |
1053 | ||
1054 | /* wait for completion */ | |
1055 | *ret_val = 0; | |
1056 | rc = -EBUSY; | |
1057 | for (i = 0; i < count; i++) { | |
1058 | udelay(5); | |
1059 | val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); | |
1060 | ||
1061 | if (val & MCPR_NVM_COMMAND_DONE) { | |
1062 | val = REG_RD(bp, MCP_REG_MCPR_NVM_READ); | |
1063 | /* we read nvram data in cpu order | |
1064 | * but ethtool sees it as an array of bytes | |
1065 | * converting to big-endian will do the work */ | |
1066 | *ret_val = cpu_to_be32(val); | |
1067 | rc = 0; | |
1068 | break; | |
1069 | } | |
1070 | } | |
51c1a580 MS |
1071 | if (rc == -EBUSY) |
1072 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
1073 | "nvram read timeout expired\n"); | |
de0c62db DK |
1074 | return rc; |
1075 | } | |
1076 | ||
1077 | static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, | |
1078 | int buf_size) | |
1079 | { | |
1080 | int rc; | |
1081 | u32 cmd_flags; | |
1082 | __be32 val; | |
1083 | ||
1084 | if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { | |
51c1a580 | 1085 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
de0c62db DK |
1086 | "Invalid parameter: offset 0x%x buf_size 0x%x\n", |
1087 | offset, buf_size); | |
1088 | return -EINVAL; | |
1089 | } | |
1090 | ||
1091 | if (offset + buf_size > bp->common.flash_size) { | |
51c1a580 MS |
1092 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1093 | "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", | |
de0c62db DK |
1094 | offset, buf_size, bp->common.flash_size); |
1095 | return -EINVAL; | |
1096 | } | |
1097 | ||
1098 | /* request access to nvram interface */ | |
1099 | rc = bnx2x_acquire_nvram_lock(bp); | |
1100 | if (rc) | |
1101 | return rc; | |
1102 | ||
1103 | /* enable access to nvram interface */ | |
1104 | bnx2x_enable_nvram_access(bp); | |
1105 | ||
1106 | /* read the first word(s) */ | |
1107 | cmd_flags = MCPR_NVM_COMMAND_FIRST; | |
1108 | while ((buf_size > sizeof(u32)) && (rc == 0)) { | |
1109 | rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); | |
1110 | memcpy(ret_buf, &val, 4); | |
1111 | ||
1112 | /* advance to the next dword */ | |
1113 | offset += sizeof(u32); | |
1114 | ret_buf += sizeof(u32); | |
1115 | buf_size -= sizeof(u32); | |
1116 | cmd_flags = 0; | |
1117 | } | |
1118 | ||
1119 | if (rc == 0) { | |
1120 | cmd_flags |= MCPR_NVM_COMMAND_LAST; | |
1121 | rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags); | |
1122 | memcpy(ret_buf, &val, 4); | |
1123 | } | |
1124 | ||
1125 | /* disable access to nvram interface */ | |
1126 | bnx2x_disable_nvram_access(bp); | |
1127 | bnx2x_release_nvram_lock(bp); | |
1128 | ||
1129 | return rc; | |
1130 | } | |
1131 | ||
1132 | static int bnx2x_get_eeprom(struct net_device *dev, | |
1133 | struct ethtool_eeprom *eeprom, u8 *eebuf) | |
1134 | { | |
1135 | struct bnx2x *bp = netdev_priv(dev); | |
1136 | int rc; | |
1137 | ||
51c1a580 MS |
1138 | if (!netif_running(dev)) { |
1139 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
1140 | "cannot access eeprom when the interface is down\n"); | |
de0c62db | 1141 | return -EAGAIN; |
51c1a580 | 1142 | } |
de0c62db | 1143 | |
51c1a580 | 1144 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" |
f1deab50 | 1145 | " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", |
de0c62db DK |
1146 | eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, |
1147 | eeprom->len, eeprom->len); | |
1148 | ||
1149 | /* parameters already validated in ethtool_get_eeprom */ | |
1150 | ||
1151 | rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); | |
1152 | ||
1153 | return rc; | |
1154 | } | |
1155 | ||
1156 | static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, | |
1157 | u32 cmd_flags) | |
1158 | { | |
1159 | int count, i, rc; | |
1160 | ||
1161 | /* build the command word */ | |
1162 | cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; | |
1163 | ||
1164 | /* need to clear DONE bit separately */ | |
1165 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); | |
1166 | ||
1167 | /* write the data */ | |
1168 | REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); | |
1169 | ||
1170 | /* address of the NVRAM to write to */ | |
1171 | REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, | |
1172 | (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); | |
1173 | ||
1174 | /* issue the write command */ | |
1175 | REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); | |
1176 | ||
1177 | /* adjust timeout for emulation/FPGA */ | |
754a2f52 | 1178 | count = BNX2X_NVRAM_TIMEOUT_COUNT; |
de0c62db DK |
1179 | if (CHIP_REV_IS_SLOW(bp)) |
1180 | count *= 100; | |
1181 | ||
1182 | /* wait for completion */ | |
1183 | rc = -EBUSY; | |
1184 | for (i = 0; i < count; i++) { | |
1185 | udelay(5); | |
1186 | val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND); | |
1187 | if (val & MCPR_NVM_COMMAND_DONE) { | |
1188 | rc = 0; | |
1189 | break; | |
1190 | } | |
1191 | } | |
1192 | ||
51c1a580 MS |
1193 | if (rc == -EBUSY) |
1194 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
1195 | "nvram write timeout expired\n"); | |
de0c62db DK |
1196 | return rc; |
1197 | } | |
1198 | ||
1199 | #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) | |
1200 | ||
1201 | static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, | |
1202 | int buf_size) | |
1203 | { | |
1204 | int rc; | |
1205 | u32 cmd_flags; | |
1206 | u32 align_offset; | |
1207 | __be32 val; | |
1208 | ||
1209 | if (offset + buf_size > bp->common.flash_size) { | |
51c1a580 MS |
1210 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1211 | "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", | |
de0c62db DK |
1212 | offset, buf_size, bp->common.flash_size); |
1213 | return -EINVAL; | |
1214 | } | |
1215 | ||
1216 | /* request access to nvram interface */ | |
1217 | rc = bnx2x_acquire_nvram_lock(bp); | |
1218 | if (rc) | |
1219 | return rc; | |
1220 | ||
1221 | /* enable access to nvram interface */ | |
1222 | bnx2x_enable_nvram_access(bp); | |
1223 | ||
1224 | cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); | |
1225 | align_offset = (offset & ~0x03); | |
1226 | rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags); | |
1227 | ||
1228 | if (rc == 0) { | |
1229 | val &= ~(0xff << BYTE_OFFSET(offset)); | |
1230 | val |= (*data_buf << BYTE_OFFSET(offset)); | |
1231 | ||
1232 | /* nvram data is returned as an array of bytes | |
1233 | * convert it back to cpu order */ | |
1234 | val = be32_to_cpu(val); | |
1235 | ||
1236 | rc = bnx2x_nvram_write_dword(bp, align_offset, val, | |
1237 | cmd_flags); | |
1238 | } | |
1239 | ||
1240 | /* disable access to nvram interface */ | |
1241 | bnx2x_disable_nvram_access(bp); | |
1242 | bnx2x_release_nvram_lock(bp); | |
1243 | ||
1244 | return rc; | |
1245 | } | |
1246 | ||
1247 | static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, | |
1248 | int buf_size) | |
1249 | { | |
1250 | int rc; | |
1251 | u32 cmd_flags; | |
1252 | u32 val; | |
1253 | u32 written_so_far; | |
1254 | ||
1255 | if (buf_size == 1) /* ethtool */ | |
1256 | return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); | |
1257 | ||
1258 | if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { | |
51c1a580 | 1259 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
de0c62db DK |
1260 | "Invalid parameter: offset 0x%x buf_size 0x%x\n", |
1261 | offset, buf_size); | |
1262 | return -EINVAL; | |
1263 | } | |
1264 | ||
1265 | if (offset + buf_size > bp->common.flash_size) { | |
51c1a580 MS |
1266 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
1267 | "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n", | |
de0c62db DK |
1268 | offset, buf_size, bp->common.flash_size); |
1269 | return -EINVAL; | |
1270 | } | |
1271 | ||
1272 | /* request access to nvram interface */ | |
1273 | rc = bnx2x_acquire_nvram_lock(bp); | |
1274 | if (rc) | |
1275 | return rc; | |
1276 | ||
1277 | /* enable access to nvram interface */ | |
1278 | bnx2x_enable_nvram_access(bp); | |
1279 | ||
1280 | written_so_far = 0; | |
1281 | cmd_flags = MCPR_NVM_COMMAND_FIRST; | |
1282 | while ((written_so_far < buf_size) && (rc == 0)) { | |
1283 | if (written_so_far == (buf_size - sizeof(u32))) | |
1284 | cmd_flags |= MCPR_NVM_COMMAND_LAST; | |
754a2f52 | 1285 | else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0) |
de0c62db | 1286 | cmd_flags |= MCPR_NVM_COMMAND_LAST; |
754a2f52 | 1287 | else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0) |
de0c62db DK |
1288 | cmd_flags |= MCPR_NVM_COMMAND_FIRST; |
1289 | ||
1290 | memcpy(&val, data_buf, 4); | |
1291 | ||
1292 | rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags); | |
1293 | ||
1294 | /* advance to the next dword */ | |
1295 | offset += sizeof(u32); | |
1296 | data_buf += sizeof(u32); | |
1297 | written_so_far += sizeof(u32); | |
1298 | cmd_flags = 0; | |
1299 | } | |
1300 | ||
1301 | /* disable access to nvram interface */ | |
1302 | bnx2x_disable_nvram_access(bp); | |
1303 | bnx2x_release_nvram_lock(bp); | |
1304 | ||
1305 | return rc; | |
1306 | } | |
1307 | ||
1308 | static int bnx2x_set_eeprom(struct net_device *dev, | |
1309 | struct ethtool_eeprom *eeprom, u8 *eebuf) | |
1310 | { | |
1311 | struct bnx2x *bp = netdev_priv(dev); | |
1312 | int port = BP_PORT(bp); | |
1313 | int rc = 0; | |
e10bc84d | 1314 | u32 ext_phy_config; |
51c1a580 MS |
1315 | if (!netif_running(dev)) { |
1316 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
1317 | "cannot access eeprom when the interface is down\n"); | |
de0c62db | 1318 | return -EAGAIN; |
51c1a580 | 1319 | } |
de0c62db | 1320 | |
51c1a580 | 1321 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" |
f1deab50 | 1322 | " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", |
de0c62db DK |
1323 | eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, |
1324 | eeprom->len, eeprom->len); | |
1325 | ||
1326 | /* parameters already validated in ethtool_set_eeprom */ | |
1327 | ||
1328 | /* PHY eeprom can be accessed only by the PMF */ | |
1329 | if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && | |
51c1a580 MS |
1330 | !bp->port.pmf) { |
1331 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
1332 | "wrong magic or interface is not pmf\n"); | |
de0c62db | 1333 | return -EINVAL; |
51c1a580 | 1334 | } |
de0c62db | 1335 | |
e10bc84d YR |
1336 | ext_phy_config = |
1337 | SHMEM_RD(bp, | |
1338 | dev_info.port_hw_config[port].external_phy_config); | |
1339 | ||
de0c62db DK |
1340 | if (eeprom->magic == 0x50485950) { |
1341 | /* 'PHYP' (0x50485950): prepare phy for FW upgrade */ | |
1342 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
1343 | ||
1344 | bnx2x_acquire_phy_lock(bp); | |
1345 | rc |= bnx2x_link_reset(&bp->link_params, | |
1346 | &bp->link_vars, 0); | |
e10bc84d | 1347 | if (XGXS_EXT_PHY_TYPE(ext_phy_config) == |
de0c62db DK |
1348 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) |
1349 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
1350 | MISC_REGISTERS_GPIO_HIGH, port); | |
1351 | bnx2x_release_phy_lock(bp); | |
1352 | bnx2x_link_report(bp); | |
1353 | ||
1354 | } else if (eeprom->magic == 0x50485952) { | |
1355 | /* 'PHYR' (0x50485952): re-init link after FW upgrade */ | |
1356 | if (bp->state == BNX2X_STATE_OPEN) { | |
1357 | bnx2x_acquire_phy_lock(bp); | |
1358 | rc |= bnx2x_link_reset(&bp->link_params, | |
1359 | &bp->link_vars, 1); | |
1360 | ||
1361 | rc |= bnx2x_phy_init(&bp->link_params, | |
1362 | &bp->link_vars); | |
1363 | bnx2x_release_phy_lock(bp); | |
1364 | bnx2x_calc_fc_adv(bp); | |
1365 | } | |
1366 | } else if (eeprom->magic == 0x53985943) { | |
1367 | /* 'PHYC' (0x53985943): PHY FW upgrade completed */ | |
e10bc84d | 1368 | if (XGXS_EXT_PHY_TYPE(ext_phy_config) == |
de0c62db | 1369 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) { |
de0c62db DK |
1370 | |
1371 | /* DSP Remove Download Mode */ | |
1372 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
1373 | MISC_REGISTERS_GPIO_LOW, port); | |
1374 | ||
1375 | bnx2x_acquire_phy_lock(bp); | |
1376 | ||
e10bc84d YR |
1377 | bnx2x_sfx7101_sp_sw_reset(bp, |
1378 | &bp->link_params.phy[EXT_PHY1]); | |
de0c62db DK |
1379 | |
1380 | /* wait 0.5 sec to allow it to run */ | |
1381 | msleep(500); | |
1382 | bnx2x_ext_phy_hw_reset(bp, port); | |
1383 | msleep(500); | |
1384 | bnx2x_release_phy_lock(bp); | |
1385 | } | |
1386 | } else | |
1387 | rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); | |
1388 | ||
1389 | return rc; | |
1390 | } | |
f85582f8 | 1391 | |
de0c62db DK |
1392 | static int bnx2x_get_coalesce(struct net_device *dev, |
1393 | struct ethtool_coalesce *coal) | |
1394 | { | |
1395 | struct bnx2x *bp = netdev_priv(dev); | |
1396 | ||
1397 | memset(coal, 0, sizeof(struct ethtool_coalesce)); | |
1398 | ||
1399 | coal->rx_coalesce_usecs = bp->rx_ticks; | |
1400 | coal->tx_coalesce_usecs = bp->tx_ticks; | |
1401 | ||
1402 | return 0; | |
1403 | } | |
1404 | ||
1405 | static int bnx2x_set_coalesce(struct net_device *dev, | |
1406 | struct ethtool_coalesce *coal) | |
1407 | { | |
1408 | struct bnx2x *bp = netdev_priv(dev); | |
1409 | ||
1410 | bp->rx_ticks = (u16)coal->rx_coalesce_usecs; | |
1411 | if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT) | |
1412 | bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT; | |
1413 | ||
1414 | bp->tx_ticks = (u16)coal->tx_coalesce_usecs; | |
1415 | if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT) | |
1416 | bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT; | |
1417 | ||
1418 | if (netif_running(dev)) | |
1419 | bnx2x_update_coalesce(bp); | |
1420 | ||
1421 | return 0; | |
1422 | } | |
1423 | ||
1424 | static void bnx2x_get_ringparam(struct net_device *dev, | |
1425 | struct ethtool_ringparam *ering) | |
1426 | { | |
1427 | struct bnx2x *bp = netdev_priv(dev); | |
1428 | ||
1429 | ering->rx_max_pending = MAX_RX_AVAIL; | |
de0c62db | 1430 | |
25141580 DK |
1431 | if (bp->rx_ring_size) |
1432 | ering->rx_pending = bp->rx_ring_size; | |
1433 | else | |
c2188952 | 1434 | ering->rx_pending = MAX_RX_AVAIL; |
25141580 | 1435 | |
de0c62db DK |
1436 | ering->tx_max_pending = MAX_TX_AVAIL; |
1437 | ering->tx_pending = bp->tx_ring_size; | |
1438 | } | |
1439 | ||
1440 | static int bnx2x_set_ringparam(struct net_device *dev, | |
1441 | struct ethtool_ringparam *ering) | |
1442 | { | |
1443 | struct bnx2x *bp = netdev_priv(dev); | |
de0c62db DK |
1444 | |
1445 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { | |
51c1a580 MS |
1446 | DP(BNX2X_MSG_ETHTOOL, |
1447 | "Handling parity error recovery. Try again later\n"); | |
de0c62db DK |
1448 | return -EAGAIN; |
1449 | } | |
1450 | ||
1451 | if ((ering->rx_pending > MAX_RX_AVAIL) || | |
b3b83c3f DK |
1452 | (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : |
1453 | MIN_RX_SIZE_TPA)) || | |
de0c62db | 1454 | (ering->tx_pending > MAX_TX_AVAIL) || |
51c1a580 MS |
1455 | (ering->tx_pending <= MAX_SKB_FRAGS + 4)) { |
1456 | DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); | |
de0c62db | 1457 | return -EINVAL; |
51c1a580 | 1458 | } |
de0c62db DK |
1459 | |
1460 | bp->rx_ring_size = ering->rx_pending; | |
1461 | bp->tx_ring_size = ering->tx_pending; | |
1462 | ||
a9fccec7 | 1463 | return bnx2x_reload_if_running(dev); |
de0c62db DK |
1464 | } |
1465 | ||
1466 | static void bnx2x_get_pauseparam(struct net_device *dev, | |
1467 | struct ethtool_pauseparam *epause) | |
1468 | { | |
1469 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 1470 | int cfg_idx = bnx2x_get_link_cfg_idx(bp); |
9e7e8399 MY |
1471 | int cfg_reg; |
1472 | ||
a22f0788 YR |
1473 | epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] == |
1474 | BNX2X_FLOW_CTRL_AUTO); | |
de0c62db | 1475 | |
9e7e8399 | 1476 | if (!epause->autoneg) |
241fb5d2 | 1477 | cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; |
9e7e8399 MY |
1478 | else |
1479 | cfg_reg = bp->link_params.req_fc_auto_adv; | |
1480 | ||
1481 | epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == | |
de0c62db | 1482 | BNX2X_FLOW_CTRL_RX); |
9e7e8399 | 1483 | epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == |
de0c62db DK |
1484 | BNX2X_FLOW_CTRL_TX); |
1485 | ||
51c1a580 | 1486 | DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" |
f1deab50 | 1487 | " autoneg %d rx_pause %d tx_pause %d\n", |
de0c62db DK |
1488 | epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); |
1489 | } | |
1490 | ||
1491 | static int bnx2x_set_pauseparam(struct net_device *dev, | |
1492 | struct ethtool_pauseparam *epause) | |
1493 | { | |
1494 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 1495 | u32 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
fb3bff17 | 1496 | if (IS_MF(bp)) |
de0c62db DK |
1497 | return 0; |
1498 | ||
51c1a580 | 1499 | DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n" |
f1deab50 | 1500 | " autoneg %d rx_pause %d tx_pause %d\n", |
de0c62db DK |
1501 | epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); |
1502 | ||
a22f0788 | 1503 | bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO; |
de0c62db DK |
1504 | |
1505 | if (epause->rx_pause) | |
a22f0788 | 1506 | bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX; |
de0c62db DK |
1507 | |
1508 | if (epause->tx_pause) | |
a22f0788 | 1509 | bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX; |
de0c62db | 1510 | |
a22f0788 YR |
1511 | if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO) |
1512 | bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE; | |
de0c62db DK |
1513 | |
1514 | if (epause->autoneg) { | |
a22f0788 | 1515 | if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { |
51c1a580 | 1516 | DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n"); |
de0c62db DK |
1517 | return -EINVAL; |
1518 | } | |
1519 | ||
a22f0788 YR |
1520 | if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) { |
1521 | bp->link_params.req_flow_ctrl[cfg_idx] = | |
1522 | BNX2X_FLOW_CTRL_AUTO; | |
1523 | } | |
de0c62db DK |
1524 | } |
1525 | ||
51c1a580 | 1526 | DP(BNX2X_MSG_ETHTOOL, |
a22f0788 | 1527 | "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); |
de0c62db DK |
1528 | |
1529 | if (netif_running(dev)) { | |
1530 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
1531 | bnx2x_link_set(bp); | |
1532 | } | |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | ||
de0c62db DK |
1537 | static const struct { |
1538 | char string[ETH_GSTRING_LEN]; | |
1539 | } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = { | |
1540 | { "register_test (offline)" }, | |
1541 | { "memory_test (offline)" }, | |
1542 | { "loopback_test (offline)" }, | |
1543 | { "nvram_test (online)" }, | |
1544 | { "interrupt_test (online)" }, | |
1545 | { "link_test (online)" }, | |
1546 | { "idle check (online)" } | |
1547 | }; | |
1548 | ||
619c5cb6 VZ |
1549 | enum { |
1550 | BNX2X_CHIP_E1_OFST = 0, | |
1551 | BNX2X_CHIP_E1H_OFST, | |
1552 | BNX2X_CHIP_E2_OFST, | |
1553 | BNX2X_CHIP_E3_OFST, | |
1554 | BNX2X_CHIP_E3B0_OFST, | |
1555 | BNX2X_CHIP_MAX_OFST | |
1556 | }; | |
1557 | ||
1558 | #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST) | |
1559 | #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST) | |
1560 | #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST) | |
1561 | #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST) | |
1562 | #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST) | |
1563 | ||
1564 | #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1) | |
1565 | #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H) | |
1566 | ||
de0c62db DK |
1567 | static int bnx2x_test_registers(struct bnx2x *bp) |
1568 | { | |
1569 | int idx, i, rc = -ENODEV; | |
619c5cb6 | 1570 | u32 wr_val = 0, hw; |
de0c62db DK |
1571 | int port = BP_PORT(bp); |
1572 | static const struct { | |
619c5cb6 | 1573 | u32 hw; |
de0c62db DK |
1574 | u32 offset0; |
1575 | u32 offset1; | |
1576 | u32 mask; | |
1577 | } reg_tbl[] = { | |
619c5cb6 VZ |
1578 | /* 0 */ { BNX2X_CHIP_MASK_ALL, |
1579 | BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff }, | |
1580 | { BNX2X_CHIP_MASK_ALL, | |
1581 | DORQ_REG_DB_ADDR0, 4, 0xffffffff }, | |
1582 | { BNX2X_CHIP_MASK_E1X, | |
1583 | HC_REG_AGG_INT_0, 4, 0x000003ff }, | |
1584 | { BNX2X_CHIP_MASK_ALL, | |
1585 | PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 }, | |
1586 | { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3, | |
1587 | PBF_REG_P0_INIT_CRD, 4, 0x000007ff }, | |
1588 | { BNX2X_CHIP_MASK_E3B0, | |
1589 | PBF_REG_INIT_CRD_Q0, 4, 0x000007ff }, | |
1590 | { BNX2X_CHIP_MASK_ALL, | |
1591 | PRS_REG_CID_PORT_0, 4, 0x00ffffff }, | |
1592 | { BNX2X_CHIP_MASK_ALL, | |
1593 | PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff }, | |
1594 | { BNX2X_CHIP_MASK_ALL, | |
1595 | PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, | |
1596 | { BNX2X_CHIP_MASK_ALL, | |
1597 | PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff }, | |
1598 | /* 10 */ { BNX2X_CHIP_MASK_ALL, | |
1599 | PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff }, | |
1600 | { BNX2X_CHIP_MASK_ALL, | |
1601 | PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff }, | |
1602 | { BNX2X_CHIP_MASK_ALL, | |
1603 | QM_REG_CONNNUM_0, 4, 0x000fffff }, | |
1604 | { BNX2X_CHIP_MASK_ALL, | |
1605 | TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff }, | |
1606 | { BNX2X_CHIP_MASK_ALL, | |
1607 | SRC_REG_KEYRSS0_0, 40, 0xffffffff }, | |
1608 | { BNX2X_CHIP_MASK_ALL, | |
1609 | SRC_REG_KEYRSS0_7, 40, 0xffffffff }, | |
1610 | { BNX2X_CHIP_MASK_ALL, | |
1611 | XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 }, | |
1612 | { BNX2X_CHIP_MASK_ALL, | |
1613 | XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 }, | |
1614 | { BNX2X_CHIP_MASK_ALL, | |
1615 | XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff }, | |
1616 | { BNX2X_CHIP_MASK_ALL, | |
1617 | NIG_REG_LLH0_T_BIT, 4, 0x00000001 }, | |
1618 | /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, | |
1619 | NIG_REG_EMAC0_IN_EN, 4, 0x00000001 }, | |
1620 | { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, | |
1621 | NIG_REG_BMAC0_IN_EN, 4, 0x00000001 }, | |
1622 | { BNX2X_CHIP_MASK_ALL, | |
1623 | NIG_REG_XCM0_OUT_EN, 4, 0x00000001 }, | |
1624 | { BNX2X_CHIP_MASK_ALL, | |
1625 | NIG_REG_BRB0_OUT_EN, 4, 0x00000001 }, | |
1626 | { BNX2X_CHIP_MASK_ALL, | |
1627 | NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 }, | |
1628 | { BNX2X_CHIP_MASK_ALL, | |
1629 | NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff }, | |
1630 | { BNX2X_CHIP_MASK_ALL, | |
1631 | NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff }, | |
1632 | { BNX2X_CHIP_MASK_ALL, | |
1633 | NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff }, | |
1634 | { BNX2X_CHIP_MASK_ALL, | |
1635 | NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff }, | |
1636 | { BNX2X_CHIP_MASK_ALL, | |
1637 | NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 }, | |
1638 | /* 30 */ { BNX2X_CHIP_MASK_ALL, | |
1639 | NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff }, | |
1640 | { BNX2X_CHIP_MASK_ALL, | |
1641 | NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff }, | |
1642 | { BNX2X_CHIP_MASK_ALL, | |
1643 | NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff }, | |
1644 | { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, | |
1645 | NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 }, | |
1646 | { BNX2X_CHIP_MASK_ALL, | |
1647 | NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001}, | |
1648 | { BNX2X_CHIP_MASK_ALL, | |
1649 | NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff }, | |
1650 | { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, | |
1651 | NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 }, | |
1652 | { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2, | |
1653 | NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f }, | |
1654 | ||
1655 | { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } | |
de0c62db DK |
1656 | }; |
1657 | ||
51c1a580 MS |
1658 | if (!netif_running(bp->dev)) { |
1659 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
1660 | "cannot access eeprom when the interface is down\n"); | |
de0c62db | 1661 | return rc; |
51c1a580 | 1662 | } |
de0c62db | 1663 | |
619c5cb6 VZ |
1664 | if (CHIP_IS_E1(bp)) |
1665 | hw = BNX2X_CHIP_MASK_E1; | |
1666 | else if (CHIP_IS_E1H(bp)) | |
1667 | hw = BNX2X_CHIP_MASK_E1H; | |
1668 | else if (CHIP_IS_E2(bp)) | |
1669 | hw = BNX2X_CHIP_MASK_E2; | |
1670 | else if (CHIP_IS_E3B0(bp)) | |
1671 | hw = BNX2X_CHIP_MASK_E3B0; | |
1672 | else /* e3 A0 */ | |
1673 | hw = BNX2X_CHIP_MASK_E3; | |
1674 | ||
de0c62db DK |
1675 | /* Repeat the test twice: |
1676 | First by writing 0x00000000, second by writing 0xffffffff */ | |
1677 | for (idx = 0; idx < 2; idx++) { | |
1678 | ||
1679 | switch (idx) { | |
1680 | case 0: | |
1681 | wr_val = 0; | |
1682 | break; | |
1683 | case 1: | |
1684 | wr_val = 0xffffffff; | |
1685 | break; | |
1686 | } | |
1687 | ||
1688 | for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { | |
1689 | u32 offset, mask, save_val, val; | |
619c5cb6 | 1690 | if (!(hw & reg_tbl[i].hw)) |
f2e0899f | 1691 | continue; |
de0c62db DK |
1692 | |
1693 | offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; | |
1694 | mask = reg_tbl[i].mask; | |
1695 | ||
1696 | save_val = REG_RD(bp, offset); | |
1697 | ||
ec6ba945 | 1698 | REG_WR(bp, offset, wr_val & mask); |
f85582f8 | 1699 | |
de0c62db DK |
1700 | val = REG_RD(bp, offset); |
1701 | ||
1702 | /* Restore the original register's value */ | |
1703 | REG_WR(bp, offset, save_val); | |
1704 | ||
1705 | /* verify value is as expected */ | |
1706 | if ((val & mask) != (wr_val & mask)) { | |
51c1a580 | 1707 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
1708 | "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", |
1709 | offset, val, wr_val, mask); | |
1710 | goto test_reg_exit; | |
1711 | } | |
1712 | } | |
1713 | } | |
1714 | ||
1715 | rc = 0; | |
1716 | ||
1717 | test_reg_exit: | |
1718 | return rc; | |
1719 | } | |
1720 | ||
1721 | static int bnx2x_test_memory(struct bnx2x *bp) | |
1722 | { | |
1723 | int i, j, rc = -ENODEV; | |
619c5cb6 | 1724 | u32 val, index; |
de0c62db DK |
1725 | static const struct { |
1726 | u32 offset; | |
1727 | int size; | |
1728 | } mem_tbl[] = { | |
1729 | { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE }, | |
1730 | { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE }, | |
1731 | { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE }, | |
1732 | { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE }, | |
1733 | { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE }, | |
1734 | { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE }, | |
1735 | { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE }, | |
1736 | ||
1737 | { 0xffffffff, 0 } | |
1738 | }; | |
619c5cb6 | 1739 | |
de0c62db DK |
1740 | static const struct { |
1741 | char *name; | |
1742 | u32 offset; | |
619c5cb6 | 1743 | u32 hw_mask[BNX2X_CHIP_MAX_OFST]; |
de0c62db | 1744 | } prty_tbl[] = { |
619c5cb6 VZ |
1745 | { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, |
1746 | {0x3ffc0, 0, 0, 0} }, | |
1747 | { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, | |
1748 | {0x2, 0x2, 0, 0} }, | |
1749 | { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, | |
1750 | {0, 0, 0, 0} }, | |
1751 | { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, | |
1752 | {0x3ffc0, 0, 0, 0} }, | |
1753 | { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, | |
1754 | {0x3ffc0, 0, 0, 0} }, | |
1755 | { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, | |
1756 | {0x3ffc1, 0, 0, 0} }, | |
1757 | ||
1758 | { NULL, 0xffffffff, {0, 0, 0, 0} } | |
de0c62db DK |
1759 | }; |
1760 | ||
51c1a580 MS |
1761 | if (!netif_running(bp->dev)) { |
1762 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
1763 | "cannot access eeprom when the interface is down\n"); | |
de0c62db | 1764 | return rc; |
51c1a580 | 1765 | } |
de0c62db | 1766 | |
619c5cb6 VZ |
1767 | if (CHIP_IS_E1(bp)) |
1768 | index = BNX2X_CHIP_E1_OFST; | |
1769 | else if (CHIP_IS_E1H(bp)) | |
1770 | index = BNX2X_CHIP_E1H_OFST; | |
1771 | else if (CHIP_IS_E2(bp)) | |
1772 | index = BNX2X_CHIP_E2_OFST; | |
1773 | else /* e3 */ | |
1774 | index = BNX2X_CHIP_E3_OFST; | |
1775 | ||
f2e0899f DK |
1776 | /* pre-Check the parity status */ |
1777 | for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { | |
1778 | val = REG_RD(bp, prty_tbl[i].offset); | |
619c5cb6 | 1779 | if (val & ~(prty_tbl[i].hw_mask[index])) { |
51c1a580 | 1780 | DP(BNX2X_MSG_ETHTOOL, |
f2e0899f DK |
1781 | "%s is 0x%x\n", prty_tbl[i].name, val); |
1782 | goto test_mem_exit; | |
1783 | } | |
1784 | } | |
1785 | ||
de0c62db DK |
1786 | /* Go through all the memories */ |
1787 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) | |
1788 | for (j = 0; j < mem_tbl[i].size; j++) | |
1789 | REG_RD(bp, mem_tbl[i].offset + j*4); | |
1790 | ||
1791 | /* Check the parity status */ | |
1792 | for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { | |
1793 | val = REG_RD(bp, prty_tbl[i].offset); | |
619c5cb6 | 1794 | if (val & ~(prty_tbl[i].hw_mask[index])) { |
51c1a580 | 1795 | DP(BNX2X_MSG_ETHTOOL, |
de0c62db DK |
1796 | "%s is 0x%x\n", prty_tbl[i].name, val); |
1797 | goto test_mem_exit; | |
1798 | } | |
1799 | } | |
1800 | ||
1801 | rc = 0; | |
1802 | ||
1803 | test_mem_exit: | |
1804 | return rc; | |
1805 | } | |
1806 | ||
a22f0788 | 1807 | static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes) |
de0c62db | 1808 | { |
f2e0899f | 1809 | int cnt = 1400; |
de0c62db | 1810 | |
619c5cb6 | 1811 | if (link_up) { |
a22f0788 | 1812 | while (bnx2x_link_test(bp, is_serdes) && cnt--) |
619c5cb6 VZ |
1813 | msleep(20); |
1814 | ||
1815 | if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) | |
51c1a580 | 1816 | DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n"); |
619c5cb6 | 1817 | } |
de0c62db DK |
1818 | } |
1819 | ||
619c5cb6 | 1820 | static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode) |
de0c62db DK |
1821 | { |
1822 | unsigned int pkt_size, num_pkts, i; | |
1823 | struct sk_buff *skb; | |
1824 | unsigned char *packet; | |
1825 | struct bnx2x_fastpath *fp_rx = &bp->fp[0]; | |
1826 | struct bnx2x_fastpath *fp_tx = &bp->fp[0]; | |
6383c0b3 | 1827 | struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0]; |
de0c62db DK |
1828 | u16 tx_start_idx, tx_idx; |
1829 | u16 rx_start_idx, rx_idx; | |
b0700b1e | 1830 | u16 pkt_prod, bd_prod; |
de0c62db DK |
1831 | struct sw_tx_bd *tx_buf; |
1832 | struct eth_tx_start_bd *tx_start_bd; | |
f2e0899f DK |
1833 | struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; |
1834 | struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; | |
de0c62db DK |
1835 | dma_addr_t mapping; |
1836 | union eth_rx_cqe *cqe; | |
619c5cb6 | 1837 | u8 cqe_fp_flags, cqe_fp_type; |
de0c62db DK |
1838 | struct sw_rx_bd *rx_buf; |
1839 | u16 len; | |
1840 | int rc = -ENODEV; | |
e52fcb24 | 1841 | u8 *data; |
73dbb5e1 | 1842 | struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txdata->txq_index); |
de0c62db DK |
1843 | |
1844 | /* check the loopback mode */ | |
1845 | switch (loopback_mode) { | |
1846 | case BNX2X_PHY_LOOPBACK: | |
de6eae1f | 1847 | if (bp->link_params.loopback_mode != LOOPBACK_XGXS) |
de0c62db DK |
1848 | return -EINVAL; |
1849 | break; | |
1850 | case BNX2X_MAC_LOOPBACK: | |
32911333 YR |
1851 | if (CHIP_IS_E3(bp)) { |
1852 | int cfg_idx = bnx2x_get_link_cfg_idx(bp); | |
1853 | if (bp->port.supported[cfg_idx] & | |
1854 | (SUPPORTED_10000baseT_Full | | |
1855 | SUPPORTED_20000baseMLD2_Full | | |
1856 | SUPPORTED_20000baseKR2_Full)) | |
1857 | bp->link_params.loopback_mode = LOOPBACK_XMAC; | |
1858 | else | |
1859 | bp->link_params.loopback_mode = LOOPBACK_UMAC; | |
1860 | } else | |
1861 | bp->link_params.loopback_mode = LOOPBACK_BMAC; | |
1862 | ||
de0c62db DK |
1863 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
1864 | break; | |
1865 | default: | |
51c1a580 | 1866 | DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); |
de0c62db DK |
1867 | return -EINVAL; |
1868 | } | |
1869 | ||
1870 | /* prepare the loopback packet */ | |
1871 | pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ? | |
1872 | bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); | |
a8c94b91 | 1873 | skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); |
de0c62db | 1874 | if (!skb) { |
51c1a580 | 1875 | DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n"); |
de0c62db DK |
1876 | rc = -ENOMEM; |
1877 | goto test_loopback_exit; | |
1878 | } | |
1879 | packet = skb_put(skb, pkt_size); | |
1880 | memcpy(packet, bp->dev->dev_addr, ETH_ALEN); | |
1881 | memset(packet + ETH_ALEN, 0, ETH_ALEN); | |
1882 | memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN)); | |
1883 | for (i = ETH_HLEN; i < pkt_size; i++) | |
1884 | packet[i] = (unsigned char) (i & 0xff); | |
619c5cb6 VZ |
1885 | mapping = dma_map_single(&bp->pdev->dev, skb->data, |
1886 | skb_headlen(skb), DMA_TO_DEVICE); | |
1887 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
1888 | rc = -ENOMEM; | |
1889 | dev_kfree_skb(skb); | |
51c1a580 | 1890 | DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n"); |
619c5cb6 VZ |
1891 | goto test_loopback_exit; |
1892 | } | |
de0c62db DK |
1893 | |
1894 | /* send the loopback packet */ | |
1895 | num_pkts = 0; | |
6383c0b3 | 1896 | tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb); |
de0c62db DK |
1897 | rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb); |
1898 | ||
73dbb5e1 DK |
1899 | netdev_tx_sent_queue(txq, skb->len); |
1900 | ||
6383c0b3 AE |
1901 | pkt_prod = txdata->tx_pkt_prod++; |
1902 | tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)]; | |
1903 | tx_buf->first_bd = txdata->tx_bd_prod; | |
de0c62db DK |
1904 | tx_buf->skb = skb; |
1905 | tx_buf->flags = 0; | |
1906 | ||
6383c0b3 AE |
1907 | bd_prod = TX_BD(txdata->tx_bd_prod); |
1908 | tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd; | |
de0c62db DK |
1909 | tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); |
1910 | tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
1911 | tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */ | |
1912 | tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); | |
523224a3 | 1913 | tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod); |
de0c62db | 1914 | tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; |
523224a3 DK |
1915 | SET_FLAG(tx_start_bd->general_data, |
1916 | ETH_TX_START_BD_ETH_ADDR_TYPE, | |
1917 | UNICAST_ADDRESS); | |
1918 | SET_FLAG(tx_start_bd->general_data, | |
1919 | ETH_TX_START_BD_HDR_NBDS, | |
1920 | 1); | |
de0c62db DK |
1921 | |
1922 | /* turn on parsing and get a BD */ | |
1923 | bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); | |
f85582f8 | 1924 | |
6383c0b3 AE |
1925 | pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x; |
1926 | pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2; | |
de0c62db | 1927 | |
f2e0899f | 1928 | memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); |
523224a3 | 1929 | memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); |
de0c62db DK |
1930 | |
1931 | wmb(); | |
1932 | ||
6383c0b3 | 1933 | txdata->tx_db.data.prod += 2; |
de0c62db | 1934 | barrier(); |
6383c0b3 | 1935 | DOORBELL(bp, txdata->cid, txdata->tx_db.raw); |
de0c62db DK |
1936 | |
1937 | mmiowb(); | |
619c5cb6 | 1938 | barrier(); |
de0c62db DK |
1939 | |
1940 | num_pkts++; | |
6383c0b3 | 1941 | txdata->tx_bd_prod += 2; /* start + pbd */ |
de0c62db DK |
1942 | |
1943 | udelay(100); | |
1944 | ||
6383c0b3 | 1945 | tx_idx = le16_to_cpu(*txdata->tx_cons_sb); |
de0c62db DK |
1946 | if (tx_idx != tx_start_idx + num_pkts) |
1947 | goto test_loopback_exit; | |
1948 | ||
f2e0899f DK |
1949 | /* Unlike HC IGU won't generate an interrupt for status block |
1950 | * updates that have been performed while interrupts were | |
1951 | * disabled. | |
1952 | */ | |
e1210d12 ED |
1953 | if (bp->common.int_block == INT_BLOCK_IGU) { |
1954 | /* Disable local BHes to prevent a dead-lock situation between | |
1955 | * sch_direct_xmit() and bnx2x_run_loopback() (calling | |
1956 | * bnx2x_tx_int()), as both are taking netif_tx_lock(). | |
1957 | */ | |
1958 | local_bh_disable(); | |
6383c0b3 | 1959 | bnx2x_tx_int(bp, txdata); |
e1210d12 ED |
1960 | local_bh_enable(); |
1961 | } | |
f2e0899f | 1962 | |
de0c62db DK |
1963 | rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb); |
1964 | if (rx_idx != rx_start_idx + num_pkts) | |
1965 | goto test_loopback_exit; | |
1966 | ||
b0700b1e | 1967 | cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)]; |
de0c62db | 1968 | cqe_fp_flags = cqe->fast_path_cqe.type_error_flags; |
619c5cb6 VZ |
1969 | cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; |
1970 | if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS)) | |
de0c62db DK |
1971 | goto test_loopback_rx_exit; |
1972 | ||
621b4d66 | 1973 | len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len); |
de0c62db DK |
1974 | if (len != pkt_size) |
1975 | goto test_loopback_rx_exit; | |
1976 | ||
1977 | rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)]; | |
9924cafc | 1978 | dma_sync_single_for_cpu(&bp->pdev->dev, |
619c5cb6 VZ |
1979 | dma_unmap_addr(rx_buf, mapping), |
1980 | fp_rx->rx_buf_size, DMA_FROM_DEVICE); | |
e52fcb24 | 1981 | data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset; |
de0c62db | 1982 | for (i = ETH_HLEN; i < pkt_size; i++) |
e52fcb24 | 1983 | if (*(data + i) != (unsigned char) (i & 0xff)) |
de0c62db DK |
1984 | goto test_loopback_rx_exit; |
1985 | ||
1986 | rc = 0; | |
1987 | ||
1988 | test_loopback_rx_exit: | |
1989 | ||
1990 | fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons); | |
1991 | fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod); | |
1992 | fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons); | |
1993 | fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod); | |
1994 | ||
1995 | /* Update producers */ | |
1996 | bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod, | |
1997 | fp_rx->rx_sge_prod); | |
1998 | ||
1999 | test_loopback_exit: | |
2000 | bp->link_params.loopback_mode = LOOPBACK_NONE; | |
2001 | ||
2002 | return rc; | |
2003 | } | |
2004 | ||
619c5cb6 | 2005 | static int bnx2x_test_loopback(struct bnx2x *bp) |
de0c62db DK |
2006 | { |
2007 | int rc = 0, res; | |
2008 | ||
2009 | if (BP_NOMCP(bp)) | |
2010 | return rc; | |
2011 | ||
2012 | if (!netif_running(bp->dev)) | |
2013 | return BNX2X_LOOPBACK_FAILED; | |
2014 | ||
2015 | bnx2x_netif_stop(bp, 1); | |
2016 | bnx2x_acquire_phy_lock(bp); | |
2017 | ||
619c5cb6 | 2018 | res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); |
de0c62db | 2019 | if (res) { |
51c1a580 | 2020 | DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res); |
de0c62db DK |
2021 | rc |= BNX2X_PHY_LOOPBACK_FAILED; |
2022 | } | |
2023 | ||
619c5cb6 | 2024 | res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); |
de0c62db | 2025 | if (res) { |
51c1a580 | 2026 | DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res); |
de0c62db DK |
2027 | rc |= BNX2X_MAC_LOOPBACK_FAILED; |
2028 | } | |
2029 | ||
2030 | bnx2x_release_phy_lock(bp); | |
2031 | bnx2x_netif_start(bp); | |
2032 | ||
2033 | return rc; | |
2034 | } | |
2035 | ||
2036 | #define CRC32_RESIDUAL 0xdebb20e3 | |
2037 | ||
2038 | static int bnx2x_test_nvram(struct bnx2x *bp) | |
2039 | { | |
2040 | static const struct { | |
2041 | int offset; | |
2042 | int size; | |
2043 | } nvram_tbl[] = { | |
2044 | { 0, 0x14 }, /* bootstrap */ | |
2045 | { 0x14, 0xec }, /* dir */ | |
2046 | { 0x100, 0x350 }, /* manuf_info */ | |
2047 | { 0x450, 0xf0 }, /* feature_info */ | |
2048 | { 0x640, 0x64 }, /* upgrade_key_info */ | |
de0c62db | 2049 | { 0x708, 0x70 }, /* manuf_key_info */ |
de0c62db DK |
2050 | { 0, 0 } |
2051 | }; | |
afa13b4b MY |
2052 | __be32 *buf; |
2053 | u8 *data; | |
de0c62db DK |
2054 | int i, rc; |
2055 | u32 magic, crc; | |
2056 | ||
2057 | if (BP_NOMCP(bp)) | |
2058 | return 0; | |
2059 | ||
afa13b4b MY |
2060 | buf = kmalloc(0x350, GFP_KERNEL); |
2061 | if (!buf) { | |
51c1a580 | 2062 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n"); |
afa13b4b MY |
2063 | rc = -ENOMEM; |
2064 | goto test_nvram_exit; | |
2065 | } | |
2066 | data = (u8 *)buf; | |
2067 | ||
de0c62db DK |
2068 | rc = bnx2x_nvram_read(bp, 0, data, 4); |
2069 | if (rc) { | |
51c1a580 MS |
2070 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
2071 | "magic value read (rc %d)\n", rc); | |
de0c62db DK |
2072 | goto test_nvram_exit; |
2073 | } | |
2074 | ||
2075 | magic = be32_to_cpu(buf[0]); | |
2076 | if (magic != 0x669955aa) { | |
51c1a580 MS |
2077 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
2078 | "wrong magic value (0x%08x)\n", magic); | |
de0c62db DK |
2079 | rc = -ENODEV; |
2080 | goto test_nvram_exit; | |
2081 | } | |
2082 | ||
2083 | for (i = 0; nvram_tbl[i].size; i++) { | |
2084 | ||
2085 | rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, | |
2086 | nvram_tbl[i].size); | |
2087 | if (rc) { | |
51c1a580 | 2088 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
de0c62db DK |
2089 | "nvram_tbl[%d] read data (rc %d)\n", i, rc); |
2090 | goto test_nvram_exit; | |
2091 | } | |
2092 | ||
2093 | crc = ether_crc_le(nvram_tbl[i].size, data); | |
2094 | if (crc != CRC32_RESIDUAL) { | |
51c1a580 MS |
2095 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, |
2096 | "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc); | |
de0c62db DK |
2097 | rc = -ENODEV; |
2098 | goto test_nvram_exit; | |
2099 | } | |
2100 | } | |
2101 | ||
2102 | test_nvram_exit: | |
afa13b4b | 2103 | kfree(buf); |
de0c62db DK |
2104 | return rc; |
2105 | } | |
2106 | ||
619c5cb6 | 2107 | /* Send an EMPTY ramrod on the first queue */ |
de0c62db DK |
2108 | static int bnx2x_test_intr(struct bnx2x *bp) |
2109 | { | |
619c5cb6 | 2110 | struct bnx2x_queue_state_params params = {0}; |
de0c62db | 2111 | |
51c1a580 MS |
2112 | if (!netif_running(bp->dev)) { |
2113 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
2114 | "cannot access eeprom when the interface is down\n"); | |
de0c62db | 2115 | return -ENODEV; |
51c1a580 | 2116 | } |
de0c62db | 2117 | |
619c5cb6 VZ |
2118 | params.q_obj = &bp->fp->q_obj; |
2119 | params.cmd = BNX2X_Q_CMD_EMPTY; | |
de0c62db | 2120 | |
619c5cb6 VZ |
2121 | __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); |
2122 | ||
2123 | return bnx2x_queue_state_change(bp, ¶ms); | |
de0c62db DK |
2124 | } |
2125 | ||
2126 | static void bnx2x_self_test(struct net_device *dev, | |
2127 | struct ethtool_test *etest, u64 *buf) | |
2128 | { | |
2129 | struct bnx2x *bp = netdev_priv(dev); | |
a22f0788 | 2130 | u8 is_serdes; |
de0c62db | 2131 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 MS |
2132 | netdev_err(bp->dev, |
2133 | "Handling parity error recovery. Try again later\n"); | |
de0c62db DK |
2134 | etest->flags |= ETH_TEST_FL_FAILED; |
2135 | return; | |
2136 | } | |
2137 | ||
2138 | memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS); | |
2139 | ||
2140 | if (!netif_running(dev)) | |
2141 | return; | |
2142 | ||
2143 | /* offline tests are not supported in MF mode */ | |
fb3bff17 | 2144 | if (IS_MF(bp)) |
de0c62db | 2145 | etest->flags &= ~ETH_TEST_FL_OFFLINE; |
a22f0788 | 2146 | is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0; |
de0c62db DK |
2147 | |
2148 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | |
2149 | int port = BP_PORT(bp); | |
2150 | u32 val; | |
2151 | u8 link_up; | |
2152 | ||
2153 | /* save current value of input enable for TX port IF */ | |
2154 | val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4); | |
2155 | /* disable input for TX port IF */ | |
2156 | REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); | |
2157 | ||
a22f0788 YR |
2158 | link_up = bp->link_vars.link_up; |
2159 | ||
de0c62db DK |
2160 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); |
2161 | bnx2x_nic_load(bp, LOAD_DIAG); | |
2162 | /* wait until link state is restored */ | |
619c5cb6 | 2163 | bnx2x_wait_for_link(bp, 1, is_serdes); |
de0c62db DK |
2164 | |
2165 | if (bnx2x_test_registers(bp) != 0) { | |
2166 | buf[0] = 1; | |
2167 | etest->flags |= ETH_TEST_FL_FAILED; | |
2168 | } | |
2169 | if (bnx2x_test_memory(bp) != 0) { | |
2170 | buf[1] = 1; | |
2171 | etest->flags |= ETH_TEST_FL_FAILED; | |
2172 | } | |
f85582f8 | 2173 | |
619c5cb6 | 2174 | buf[2] = bnx2x_test_loopback(bp); |
de0c62db DK |
2175 | if (buf[2] != 0) |
2176 | etest->flags |= ETH_TEST_FL_FAILED; | |
2177 | ||
2178 | bnx2x_nic_unload(bp, UNLOAD_NORMAL); | |
2179 | ||
2180 | /* restore input for TX port IF */ | |
2181 | REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); | |
2182 | ||
2183 | bnx2x_nic_load(bp, LOAD_NORMAL); | |
2184 | /* wait until link state is restored */ | |
a22f0788 | 2185 | bnx2x_wait_for_link(bp, link_up, is_serdes); |
de0c62db DK |
2186 | } |
2187 | if (bnx2x_test_nvram(bp) != 0) { | |
2188 | buf[3] = 1; | |
2189 | etest->flags |= ETH_TEST_FL_FAILED; | |
2190 | } | |
2191 | if (bnx2x_test_intr(bp) != 0) { | |
2192 | buf[4] = 1; | |
2193 | etest->flags |= ETH_TEST_FL_FAILED; | |
2194 | } | |
633ac363 DK |
2195 | |
2196 | if (bnx2x_link_test(bp, is_serdes) != 0) { | |
2197 | buf[5] = 1; | |
2198 | etest->flags |= ETH_TEST_FL_FAILED; | |
2199 | } | |
de0c62db DK |
2200 | |
2201 | #ifdef BNX2X_EXTRA_DEBUG | |
2202 | bnx2x_panic_dump(bp); | |
2203 | #endif | |
2204 | } | |
2205 | ||
de0c62db DK |
2206 | #define IS_PORT_STAT(i) \ |
2207 | ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT) | |
2208 | #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC) | |
fb3bff17 DK |
2209 | #define IS_MF_MODE_STAT(bp) \ |
2210 | (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) | |
de0c62db | 2211 | |
619c5cb6 VZ |
2212 | /* ethtool statistics are displayed for all regular ethernet queues and the |
2213 | * fcoe L2 queue if not disabled | |
2214 | */ | |
2215 | static inline int bnx2x_num_stat_queues(struct bnx2x *bp) | |
2216 | { | |
2217 | return BNX2X_NUM_ETH_QUEUES(bp); | |
2218 | } | |
2219 | ||
de0c62db DK |
2220 | static int bnx2x_get_sset_count(struct net_device *dev, int stringset) |
2221 | { | |
2222 | struct bnx2x *bp = netdev_priv(dev); | |
2223 | int i, num_stats; | |
2224 | ||
2225 | switch (stringset) { | |
2226 | case ETH_SS_STATS: | |
2227 | if (is_multi(bp)) { | |
619c5cb6 | 2228 | num_stats = bnx2x_num_stat_queues(bp) * |
d5e83632 YM |
2229 | BNX2X_NUM_Q_STATS; |
2230 | } else | |
2231 | num_stats = 0; | |
2232 | if (IS_MF_MODE_STAT(bp)) { | |
2233 | for (i = 0; i < BNX2X_NUM_STATS; i++) | |
2234 | if (IS_FUNC_STAT(i)) | |
2235 | num_stats++; | |
2236 | } else | |
2237 | num_stats += BNX2X_NUM_STATS; | |
2238 | ||
de0c62db DK |
2239 | return num_stats; |
2240 | ||
2241 | case ETH_SS_TEST: | |
2242 | return BNX2X_NUM_TESTS; | |
2243 | ||
2244 | default: | |
2245 | return -EINVAL; | |
2246 | } | |
2247 | } | |
2248 | ||
2249 | static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | |
2250 | { | |
2251 | struct bnx2x *bp = netdev_priv(dev); | |
2252 | int i, j, k; | |
ec6ba945 | 2253 | char queue_name[MAX_QUEUE_NAME_LEN+1]; |
de0c62db DK |
2254 | |
2255 | switch (stringset) { | |
2256 | case ETH_SS_STATS: | |
d5e83632 | 2257 | k = 0; |
de0c62db | 2258 | if (is_multi(bp)) { |
619c5cb6 | 2259 | for_each_eth_queue(bp, i) { |
ec6ba945 | 2260 | memset(queue_name, 0, sizeof(queue_name)); |
619c5cb6 | 2261 | sprintf(queue_name, "%d", i); |
de0c62db | 2262 | for (j = 0; j < BNX2X_NUM_Q_STATS; j++) |
ec6ba945 VZ |
2263 | snprintf(buf + (k + j)*ETH_GSTRING_LEN, |
2264 | ETH_GSTRING_LEN, | |
2265 | bnx2x_q_stats_arr[j].string, | |
2266 | queue_name); | |
de0c62db DK |
2267 | k += BNX2X_NUM_Q_STATS; |
2268 | } | |
de0c62db | 2269 | } |
d5e83632 YM |
2270 | |
2271 | ||
2272 | for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { | |
2273 | if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) | |
2274 | continue; | |
2275 | strcpy(buf + (k + j)*ETH_GSTRING_LEN, | |
2276 | bnx2x_stats_arr[i].string); | |
2277 | j++; | |
2278 | } | |
2279 | ||
de0c62db DK |
2280 | break; |
2281 | ||
2282 | case ETH_SS_TEST: | |
2283 | memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr)); | |
2284 | break; | |
2285 | } | |
2286 | } | |
2287 | ||
2288 | static void bnx2x_get_ethtool_stats(struct net_device *dev, | |
2289 | struct ethtool_stats *stats, u64 *buf) | |
2290 | { | |
2291 | struct bnx2x *bp = netdev_priv(dev); | |
2292 | u32 *hw_stats, *offset; | |
d5e83632 | 2293 | int i, j, k = 0; |
de0c62db DK |
2294 | |
2295 | if (is_multi(bp)) { | |
619c5cb6 | 2296 | for_each_eth_queue(bp, i) { |
de0c62db DK |
2297 | hw_stats = (u32 *)&bp->fp[i].eth_q_stats; |
2298 | for (j = 0; j < BNX2X_NUM_Q_STATS; j++) { | |
2299 | if (bnx2x_q_stats_arr[j].size == 0) { | |
2300 | /* skip this counter */ | |
2301 | buf[k + j] = 0; | |
2302 | continue; | |
2303 | } | |
2304 | offset = (hw_stats + | |
2305 | bnx2x_q_stats_arr[j].offset); | |
2306 | if (bnx2x_q_stats_arr[j].size == 4) { | |
2307 | /* 4-byte counter */ | |
2308 | buf[k + j] = (u64) *offset; | |
2309 | continue; | |
2310 | } | |
2311 | /* 8-byte counter */ | |
2312 | buf[k + j] = HILO_U64(*offset, *(offset + 1)); | |
2313 | } | |
2314 | k += BNX2X_NUM_Q_STATS; | |
2315 | } | |
d5e83632 YM |
2316 | } |
2317 | ||
2318 | hw_stats = (u32 *)&bp->eth_stats; | |
2319 | for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { | |
2320 | if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i)) | |
2321 | continue; | |
2322 | if (bnx2x_stats_arr[i].size == 0) { | |
2323 | /* skip this counter */ | |
2324 | buf[k + j] = 0; | |
2325 | j++; | |
2326 | continue; | |
de0c62db | 2327 | } |
d5e83632 YM |
2328 | offset = (hw_stats + bnx2x_stats_arr[i].offset); |
2329 | if (bnx2x_stats_arr[i].size == 4) { | |
2330 | /* 4-byte counter */ | |
2331 | buf[k + j] = (u64) *offset; | |
de0c62db | 2332 | j++; |
d5e83632 | 2333 | continue; |
de0c62db | 2334 | } |
d5e83632 YM |
2335 | /* 8-byte counter */ |
2336 | buf[k + j] = HILO_U64(*offset, *(offset + 1)); | |
2337 | j++; | |
de0c62db DK |
2338 | } |
2339 | } | |
2340 | ||
32d36134 | 2341 | static int bnx2x_set_phys_id(struct net_device *dev, |
2342 | enum ethtool_phys_id_state state) | |
de0c62db DK |
2343 | { |
2344 | struct bnx2x *bp = netdev_priv(dev); | |
de0c62db | 2345 | |
51c1a580 MS |
2346 | if (!netif_running(dev)) { |
2347 | DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, | |
2348 | "cannot access eeprom when the interface is down\n"); | |
32d36134 | 2349 | return -EAGAIN; |
51c1a580 | 2350 | } |
de0c62db | 2351 | |
51c1a580 MS |
2352 | if (!bp->port.pmf) { |
2353 | DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n"); | |
32d36134 | 2354 | return -EOPNOTSUPP; |
51c1a580 | 2355 | } |
de0c62db | 2356 | |
32d36134 | 2357 | switch (state) { |
2358 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 2359 | return 1; /* cycle on/off once per second */ |
de0c62db | 2360 | |
32d36134 | 2361 | case ETHTOOL_ID_ON: |
2362 | bnx2x_set_led(&bp->link_params, &bp->link_vars, | |
e1943424 | 2363 | LED_MODE_ON, SPEED_1000); |
32d36134 | 2364 | break; |
de0c62db | 2365 | |
32d36134 | 2366 | case ETHTOOL_ID_OFF: |
2367 | bnx2x_set_led(&bp->link_params, &bp->link_vars, | |
e1943424 | 2368 | LED_MODE_FRONT_PANEL_OFF, 0); |
de0c62db | 2369 | |
32d36134 | 2370 | break; |
2371 | ||
2372 | case ETHTOOL_ID_INACTIVE: | |
e1943424 DM |
2373 | bnx2x_set_led(&bp->link_params, &bp->link_vars, |
2374 | LED_MODE_OPER, | |
2375 | bp->link_vars.line_speed); | |
32d36134 | 2376 | } |
de0c62db DK |
2377 | |
2378 | return 0; | |
2379 | } | |
2380 | ||
ab532cf3 | 2381 | static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, |
815c7db5 | 2382 | u32 *rules __always_unused) |
ab532cf3 TH |
2383 | { |
2384 | struct bnx2x *bp = netdev_priv(dev); | |
2385 | ||
2386 | switch (info->cmd) { | |
2387 | case ETHTOOL_GRXRINGS: | |
2388 | info->data = BNX2X_NUM_ETH_QUEUES(bp); | |
2389 | return 0; | |
2390 | ||
2391 | default: | |
51c1a580 | 2392 | DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n"); |
ab532cf3 TH |
2393 | return -EOPNOTSUPP; |
2394 | } | |
2395 | } | |
2396 | ||
7850f63f BH |
2397 | static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev) |
2398 | { | |
2399 | struct bnx2x *bp = netdev_priv(dev); | |
2400 | ||
2401 | return (bp->multi_mode == ETH_RSS_MODE_DISABLED ? | |
2402 | 0 : T_ETH_INDIRECTION_TABLE_SIZE); | |
2403 | } | |
2404 | ||
2405 | static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir) | |
ab532cf3 TH |
2406 | { |
2407 | struct bnx2x *bp = netdev_priv(dev); | |
619c5cb6 VZ |
2408 | u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; |
2409 | size_t i; | |
ab532cf3 | 2410 | |
619c5cb6 VZ |
2411 | /* Get the current configuration of the RSS indirection table */ |
2412 | bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table); | |
2413 | ||
2414 | /* | |
2415 | * We can't use a memcpy() as an internal storage of an | |
2416 | * indirection table is a u8 array while indir->ring_index | |
2417 | * points to an array of u32. | |
2418 | * | |
2419 | * Indirection table contains the FW Client IDs, so we need to | |
2420 | * align the returned table to the Client ID of the leading RSS | |
2421 | * queue. | |
2422 | */ | |
7850f63f BH |
2423 | for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) |
2424 | indir[i] = ind_table[i] - bp->fp->cl_id; | |
619c5cb6 | 2425 | |
ab532cf3 TH |
2426 | return 0; |
2427 | } | |
2428 | ||
7850f63f | 2429 | static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir) |
ab532cf3 TH |
2430 | { |
2431 | struct bnx2x *bp = netdev_priv(dev); | |
2432 | size_t i; | |
619c5cb6 | 2433 | u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0}; |
619c5cb6 VZ |
2434 | |
2435 | for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { | |
619c5cb6 VZ |
2436 | /* |
2437 | * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy() | |
2438 | * as an internal storage of an indirection table is a u8 array | |
2439 | * while indir->ring_index points to an array of u32. | |
2440 | * | |
2441 | * Indirection table contains the FW Client IDs, so we need to | |
2442 | * align the received table to the Client ID of the leading RSS | |
2443 | * queue | |
2444 | */ | |
7850f63f | 2445 | ind_table[i] = indir[i] + bp->fp->cl_id; |
619c5cb6 | 2446 | } |
ab532cf3 | 2447 | |
619c5cb6 | 2448 | return bnx2x_config_rss_pf(bp, ind_table, false); |
ab532cf3 TH |
2449 | } |
2450 | ||
de0c62db DK |
2451 | static const struct ethtool_ops bnx2x_ethtool_ops = { |
2452 | .get_settings = bnx2x_get_settings, | |
2453 | .set_settings = bnx2x_set_settings, | |
2454 | .get_drvinfo = bnx2x_get_drvinfo, | |
2455 | .get_regs_len = bnx2x_get_regs_len, | |
2456 | .get_regs = bnx2x_get_regs, | |
2457 | .get_wol = bnx2x_get_wol, | |
2458 | .set_wol = bnx2x_set_wol, | |
2459 | .get_msglevel = bnx2x_get_msglevel, | |
2460 | .set_msglevel = bnx2x_set_msglevel, | |
2461 | .nway_reset = bnx2x_nway_reset, | |
2462 | .get_link = bnx2x_get_link, | |
2463 | .get_eeprom_len = bnx2x_get_eeprom_len, | |
2464 | .get_eeprom = bnx2x_get_eeprom, | |
2465 | .set_eeprom = bnx2x_set_eeprom, | |
2466 | .get_coalesce = bnx2x_get_coalesce, | |
2467 | .set_coalesce = bnx2x_set_coalesce, | |
2468 | .get_ringparam = bnx2x_get_ringparam, | |
2469 | .set_ringparam = bnx2x_set_ringparam, | |
2470 | .get_pauseparam = bnx2x_get_pauseparam, | |
2471 | .set_pauseparam = bnx2x_set_pauseparam, | |
de0c62db DK |
2472 | .self_test = bnx2x_self_test, |
2473 | .get_sset_count = bnx2x_get_sset_count, | |
2474 | .get_strings = bnx2x_get_strings, | |
32d36134 | 2475 | .set_phys_id = bnx2x_set_phys_id, |
de0c62db | 2476 | .get_ethtool_stats = bnx2x_get_ethtool_stats, |
ab532cf3 | 2477 | .get_rxnfc = bnx2x_get_rxnfc, |
7850f63f | 2478 | .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size, |
ab532cf3 TH |
2479 | .get_rxfh_indir = bnx2x_get_rxfh_indir, |
2480 | .set_rxfh_indir = bnx2x_set_rxfh_indir, | |
de0c62db DK |
2481 | }; |
2482 | ||
2483 | void bnx2x_set_ethtool_ops(struct net_device *netdev) | |
2484 | { | |
2485 | SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops); | |
2486 | } |