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9f6c9258 DK |
1 | /* bnx2x_cmn.h: Broadcom Everest network driver. |
2 | * | |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
9f6c9258 DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #ifndef BNX2X_CMN_H | |
18 | #define BNX2X_CMN_H | |
19 | ||
20 | #include <linux/types.h> | |
619c5cb6 | 21 | #include <linux/pci.h> |
9f6c9258 | 22 | #include <linux/netdevice.h> |
614c76df | 23 | #include <linux/etherdevice.h> |
9f6c9258 | 24 | |
9f6c9258 | 25 | #include "bnx2x.h" |
6411280a | 26 | #include "bnx2x_sriov.h" |
9f6c9258 | 27 | |
619c5cb6 VZ |
28 | /* This is used as a replacement for an MCP if it's not present */ |
29 | extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ | |
30 | ||
d6214d7a | 31 | extern int num_queues; |
0e8d2ec5 | 32 | extern int int_mode; |
9f6c9258 | 33 | |
b3b83c3f DK |
34 | /************************ Macros ********************************/ |
35 | #define BNX2X_PCI_FREE(x, y, size) \ | |
36 | do { \ | |
37 | if (x) { \ | |
38 | dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ | |
39 | x = NULL; \ | |
40 | y = 0; \ | |
41 | } \ | |
42 | } while (0) | |
43 | ||
44 | #define BNX2X_FREE(x) \ | |
45 | do { \ | |
46 | if (x) { \ | |
47 | kfree((void *)x); \ | |
48 | x = NULL; \ | |
49 | } \ | |
50 | } while (0) | |
51 | ||
6bf07b8e YM |
52 | #define BNX2X_PCI_ALLOC(x, y, size) \ |
53 | do { \ | |
54 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, \ | |
55 | GFP_KERNEL | __GFP_ZERO); \ | |
56 | if (x == NULL) \ | |
57 | goto alloc_mem_err; \ | |
58 | DP(NETIF_MSG_HW, "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \ | |
59 | (unsigned long long)(*y), x); \ | |
60 | } while (0) | |
b3b83c3f DK |
61 | |
62 | #define BNX2X_ALLOC(x, size) \ | |
63 | do { \ | |
64 | x = kzalloc(size, GFP_KERNEL); \ | |
65 | if (x == NULL) \ | |
66 | goto alloc_mem_err; \ | |
67 | } while (0) | |
68 | ||
9f6c9258 DK |
69 | /*********************** Interfaces **************************** |
70 | * Functions that need to be implemented by each driver version | |
71 | */ | |
619c5cb6 VZ |
72 | /* Init */ |
73 | ||
74 | /** | |
75 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
76 | * | |
77 | * @bp: driver handle | |
78 | * @unload_mode: requested function's unload mode | |
79 | * | |
80 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
81 | */ | |
82 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); | |
83 | ||
84 | /** | |
85 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
86 | * | |
87 | * @bp: driver handle | |
5d07d868 | 88 | * @keep_link: true iff link should be kept up |
619c5cb6 | 89 | */ |
5d07d868 | 90 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); |
619c5cb6 VZ |
91 | |
92 | /** | |
96305234 | 93 | * bnx2x_config_rss_pf - configure RSS parameters in a PF. |
619c5cb6 VZ |
94 | * |
95 | * @bp: driver handle | |
49ce9c2c | 96 | * @rss_obj: RSS object to use |
619c5cb6 VZ |
97 | * @ind_table: indirection table to configure |
98 | * @config_hash: re-configure RSS hash keys configuration | |
99 | */ | |
96305234 | 100 | int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, |
5d317c6a | 101 | bool config_hash); |
619c5cb6 VZ |
102 | |
103 | /** | |
104 | * bnx2x__init_func_obj - init function object | |
105 | * | |
106 | * @bp: driver handle | |
107 | * | |
108 | * Initializes the Function Object with the appropriate | |
109 | * parameters which include a function slow path driver | |
110 | * interface. | |
111 | */ | |
112 | void bnx2x__init_func_obj(struct bnx2x *bp); | |
113 | ||
114 | /** | |
115 | * bnx2x_setup_queue - setup eth queue. | |
116 | * | |
117 | * @bp: driver handle | |
118 | * @fp: pointer to the fastpath structure | |
119 | * @leading: boolean | |
120 | * | |
121 | */ | |
122 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
123 | bool leading); | |
124 | ||
125 | /** | |
126 | * bnx2x_setup_leading - bring up a leading eth queue. | |
127 | * | |
128 | * @bp: driver handle | |
129 | */ | |
130 | int bnx2x_setup_leading(struct bnx2x *bp); | |
131 | ||
132 | /** | |
133 | * bnx2x_fw_command - send the MCP a request | |
134 | * | |
135 | * @bp: driver handle | |
136 | * @command: request | |
137 | * @param: request's parameter | |
138 | * | |
139 | * block until there is a reply | |
140 | */ | |
141 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); | |
9f6c9258 DK |
142 | |
143 | /** | |
e8920674 | 144 | * bnx2x_initial_phy_init - initialize link parameters structure variables. |
9f6c9258 | 145 | * |
e8920674 DK |
146 | * @bp: driver handle |
147 | * @load_mode: current mode | |
9f6c9258 | 148 | */ |
cd1dfce2 | 149 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); |
9f6c9258 DK |
150 | |
151 | /** | |
e8920674 | 152 | * bnx2x_link_set - configure hw according to link parameters structure. |
9f6c9258 | 153 | * |
e8920674 | 154 | * @bp: driver handle |
9f6c9258 DK |
155 | */ |
156 | void bnx2x_link_set(struct bnx2x *bp); | |
157 | ||
5d07d868 YM |
158 | /** |
159 | * bnx2x_force_link_reset - Forces link reset, and put the PHY | |
160 | * in reset as well. | |
161 | * | |
162 | * @bp: driver handle | |
163 | */ | |
164 | void bnx2x_force_link_reset(struct bnx2x *bp); | |
165 | ||
9f6c9258 | 166 | /** |
e8920674 | 167 | * bnx2x_link_test - query link status. |
9f6c9258 | 168 | * |
e8920674 DK |
169 | * @bp: driver handle |
170 | * @is_serdes: bool | |
9f6c9258 | 171 | * |
e8920674 | 172 | * Returns 0 if link is UP. |
9f6c9258 | 173 | */ |
a22f0788 | 174 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 | 175 | |
619c5cb6 VZ |
176 | /** |
177 | * bnx2x_drv_pulse - write driver pulse to shmem | |
178 | * | |
179 | * @bp: driver handle | |
180 | * | |
181 | * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox | |
182 | * in the shmem. | |
183 | */ | |
184 | void bnx2x_drv_pulse(struct bnx2x *bp); | |
185 | ||
186 | /** | |
187 | * bnx2x_igu_ack_sb - update IGU with current SB value | |
188 | * | |
189 | * @bp: driver handle | |
190 | * @igu_sb_id: SB id | |
191 | * @segment: SB segment | |
192 | * @index: SB index | |
193 | * @op: SB operation | |
194 | * @update: is HW update required | |
195 | */ | |
196 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
197 | u16 index, u8 op, u8 update); | |
198 | ||
c9ee9206 VZ |
199 | /* Disable transactions from chip to host */ |
200 | void bnx2x_pf_disable(struct bnx2x *bp); | |
07ba6af4 | 201 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); |
c9ee9206 | 202 | |
9f6c9258 | 203 | /** |
e8920674 | 204 | * bnx2x__link_status_update - handles link status change. |
9f6c9258 | 205 | * |
e8920674 | 206 | * @bp: driver handle |
9f6c9258 DK |
207 | */ |
208 | void bnx2x__link_status_update(struct bnx2x *bp); | |
209 | ||
f85582f8 | 210 | /** |
e8920674 | 211 | * bnx2x_link_report - report link status to upper layer. |
f85582f8 | 212 | * |
e8920674 | 213 | * @bp: driver handle |
f85582f8 DK |
214 | */ |
215 | void bnx2x_link_report(struct bnx2x *bp); | |
216 | ||
2ae17f66 VZ |
217 | /* None-atomic version of bnx2x_link_report() */ |
218 | void __bnx2x_link_report(struct bnx2x *bp); | |
219 | ||
0793f83f | 220 | /** |
e8920674 | 221 | * bnx2x_get_mf_speed - calculate MF speed. |
0793f83f | 222 | * |
e8920674 | 223 | * @bp: driver handle |
0793f83f | 224 | * |
e8920674 | 225 | * Takes into account current linespeed and MF configuration. |
0793f83f DK |
226 | */ |
227 | u16 bnx2x_get_mf_speed(struct bnx2x *bp); | |
228 | ||
9f6c9258 | 229 | /** |
e8920674 | 230 | * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler |
9f6c9258 | 231 | * |
e8920674 DK |
232 | * @irq: irq number |
233 | * @dev_instance: private instance | |
9f6c9258 DK |
234 | */ |
235 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
236 | ||
237 | /** | |
e8920674 | 238 | * bnx2x_interrupt - non MSI-X interrupt handler |
9f6c9258 | 239 | * |
e8920674 DK |
240 | * @irq: irq number |
241 | * @dev_instance: private instance | |
9f6c9258 DK |
242 | */ |
243 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
9f6c9258 DK |
244 | |
245 | /** | |
e8920674 | 246 | * bnx2x_cnic_notify - send command to cnic driver |
9f6c9258 | 247 | * |
e8920674 DK |
248 | * @bp: driver handle |
249 | * @cmd: command | |
9f6c9258 DK |
250 | */ |
251 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
252 | ||
253 | /** | |
e8920674 | 254 | * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information |
9f6c9258 | 255 | * |
e8920674 | 256 | * @bp: driver handle |
9f6c9258 DK |
257 | */ |
258 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
37ae41a9 MS |
259 | |
260 | /** | |
261 | * bnx2x_setup_cnic_info - provides cnic with updated info | |
262 | * | |
263 | * @bp: driver handle | |
264 | */ | |
265 | void bnx2x_setup_cnic_info(struct bnx2x *bp); | |
266 | ||
9f6c9258 | 267 | /** |
e8920674 | 268 | * bnx2x_int_enable - enable HW interrupts. |
9f6c9258 | 269 | * |
e8920674 | 270 | * @bp: driver handle |
9f6c9258 DK |
271 | */ |
272 | void bnx2x_int_enable(struct bnx2x *bp); | |
273 | ||
274 | /** | |
e8920674 DK |
275 | * bnx2x_int_disable_sync - disable interrupts. |
276 | * | |
277 | * @bp: driver handle | |
278 | * @disable_hw: true, disable HW interrupts. | |
9f6c9258 | 279 | * |
e8920674 DK |
280 | * This function ensures that there are no |
281 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
9f6c9258 DK |
282 | */ |
283 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
284 | ||
9f6c9258 | 285 | /** |
55c11941 | 286 | * bnx2x_nic_init_cnic - init driver internals for cnic. |
e8920674 DK |
287 | * |
288 | * @bp: driver handle | |
289 | * @load_code: COMMON, PORT or FUNCTION | |
290 | * | |
291 | * Initializes: | |
9f6c9258 DK |
292 | * - rings |
293 | * - status blocks | |
294 | * - etc. | |
9f6c9258 | 295 | */ |
55c11941 | 296 | void bnx2x_nic_init_cnic(struct bnx2x *bp); |
9f6c9258 | 297 | |
55c11941 | 298 | /** |
ecf01c22 | 299 | * bnx2x_preirq_nic_init - init driver internals. |
55c11941 MS |
300 | * |
301 | * @bp: driver handle | |
302 | * | |
303 | * Initializes: | |
ecf01c22 YM |
304 | * - fastpath object |
305 | * - fastpath rings | |
306 | * etc. | |
307 | */ | |
308 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp); | |
309 | ||
310 | /** | |
311 | * bnx2x_postirq_nic_init - init driver internals. | |
312 | * | |
313 | * @bp: driver handle | |
314 | * @load_code: COMMON, PORT or FUNCTION | |
315 | * | |
316 | * Initializes: | |
55c11941 | 317 | * - status blocks |
ecf01c22 | 318 | * - slowpath rings |
55c11941 MS |
319 | * - etc. |
320 | */ | |
ecf01c22 | 321 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code); |
55c11941 MS |
322 | /** |
323 | * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. | |
324 | * | |
325 | * @bp: driver handle | |
326 | */ | |
327 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp); | |
9f6c9258 | 328 | /** |
e8920674 | 329 | * bnx2x_alloc_mem - allocate driver's memory. |
9f6c9258 | 330 | * |
e8920674 | 331 | * @bp: driver handle |
9f6c9258 DK |
332 | */ |
333 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
334 | ||
55c11941 MS |
335 | /** |
336 | * bnx2x_free_mem_cnic - release driver's memory for cnic. | |
337 | * | |
338 | * @bp: driver handle | |
339 | */ | |
340 | void bnx2x_free_mem_cnic(struct bnx2x *bp); | |
9f6c9258 | 341 | /** |
e8920674 | 342 | * bnx2x_free_mem - release driver's memory. |
9f6c9258 | 343 | * |
e8920674 | 344 | * @bp: driver handle |
9f6c9258 DK |
345 | */ |
346 | void bnx2x_free_mem(struct bnx2x *bp); | |
347 | ||
9f6c9258 | 348 | /** |
e8920674 | 349 | * bnx2x_set_num_queues - set number of queues according to mode. |
9f6c9258 | 350 | * |
e8920674 | 351 | * @bp: driver handle |
9f6c9258 | 352 | */ |
d6214d7a | 353 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
354 | |
355 | /** | |
e8920674 DK |
356 | * bnx2x_chip_cleanup - cleanup chip internals. |
357 | * | |
358 | * @bp: driver handle | |
359 | * @unload_mode: COMMON, PORT, FUNCTION | |
5d07d868 | 360 | * @keep_link: true iff link should be kept up. |
e8920674 | 361 | * |
9f6c9258 | 362 | * - Cleanup MAC configuration. |
e8920674 | 363 | * - Closes clients. |
9f6c9258 | 364 | * - etc. |
9f6c9258 | 365 | */ |
5d07d868 | 366 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); |
9f6c9258 DK |
367 | |
368 | /** | |
e8920674 | 369 | * bnx2x_acquire_hw_lock - acquire HW lock. |
9f6c9258 | 370 | * |
e8920674 DK |
371 | * @bp: driver handle |
372 | * @resource: resource bit which was locked | |
9f6c9258 DK |
373 | */ |
374 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
375 | ||
376 | /** | |
e8920674 | 377 | * bnx2x_release_hw_lock - release HW lock. |
9f6c9258 | 378 | * |
e8920674 DK |
379 | * @bp: driver handle |
380 | * @resource: resource bit which was locked | |
9f6c9258 DK |
381 | */ |
382 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
383 | ||
c9ee9206 VZ |
384 | /** |
385 | * bnx2x_release_leader_lock - release recovery leader lock | |
386 | * | |
387 | * @bp: driver handle | |
388 | */ | |
389 | int bnx2x_release_leader_lock(struct bnx2x *bp); | |
390 | ||
9f6c9258 | 391 | /** |
e8920674 DK |
392 | * bnx2x_set_eth_mac - configure eth MAC address in the HW |
393 | * | |
394 | * @bp: driver handle | |
395 | * @set: set or clear | |
9f6c9258 | 396 | * |
e8920674 | 397 | * Configures according to the value in netdev->dev_addr. |
9f6c9258 | 398 | */ |
619c5cb6 | 399 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); |
9f6c9258 | 400 | |
ec6ba945 | 401 | /** |
619c5cb6 | 402 | * bnx2x_set_rx_mode - set MAC filtering configurations. |
ec6ba945 | 403 | * |
619c5cb6 | 404 | * @dev: netdevice |
ec6ba945 | 405 | * |
619c5cb6 VZ |
406 | * called with netif_tx_lock from dev_mcast.c |
407 | * If bp->state is OPEN, should be called with | |
408 | * netif_addr_lock_bh() | |
ec6ba945 | 409 | */ |
619c5cb6 | 410 | void bnx2x_set_rx_mode(struct net_device *dev); |
ec6ba945 VZ |
411 | |
412 | /** | |
619c5cb6 | 413 | * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. |
ec6ba945 | 414 | * |
e8920674 | 415 | * @bp: driver handle |
619c5cb6 VZ |
416 | * |
417 | * If bp->state is OPEN, should be called with | |
418 | * netif_addr_lock_bh(). | |
ec6ba945 | 419 | */ |
924d75ab | 420 | int bnx2x_set_storm_rx_mode(struct bnx2x *bp); |
ec6ba945 | 421 | |
9f6c9258 | 422 | /** |
619c5cb6 | 423 | * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. |
9f6c9258 | 424 | * |
619c5cb6 VZ |
425 | * @bp: driver handle |
426 | * @cl_id: client id | |
427 | * @rx_mode_flags: rx mode configuration | |
428 | * @rx_accept_flags: rx accept configuration | |
429 | * @tx_accept_flags: tx accept configuration (tx switch) | |
430 | * @ramrod_flags: ramrod configuration | |
9f6c9258 | 431 | */ |
924d75ab YM |
432 | int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
433 | unsigned long rx_mode_flags, | |
434 | unsigned long rx_accept_flags, | |
435 | unsigned long tx_accept_flags, | |
436 | unsigned long ramrod_flags); | |
9f6c9258 | 437 | |
9f6c9258 | 438 | /* Parity errors related */ |
889b9af3 AE |
439 | void bnx2x_set_pf_load(struct bnx2x *bp); |
440 | bool bnx2x_clear_pf_load(struct bnx2x *bp); | |
c9ee9206 VZ |
441 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); |
442 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); | |
443 | void bnx2x_set_reset_in_progress(struct bnx2x *bp); | |
444 | void bnx2x_set_reset_global(struct bnx2x *bp); | |
9f6c9258 | 445 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); |
55c11941 | 446 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp); |
9f6c9258 | 447 | |
9f6c9258 | 448 | /** |
e8920674 | 449 | * bnx2x_sp_event - handle ramrods completion. |
9f6c9258 | 450 | * |
e8920674 DK |
451 | * @fp: fastpath handle for the event |
452 | * @rr_cqe: eth_rx_cqe | |
9f6c9258 | 453 | */ |
f85582f8 | 454 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 455 | |
523224a3 | 456 | /** |
e8920674 | 457 | * bnx2x_ilt_set_info - prepare ILT configurations. |
523224a3 | 458 | * |
e8920674 | 459 | * @bp: driver handle |
523224a3 DK |
460 | */ |
461 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 462 | |
55c11941 MS |
463 | /** |
464 | * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC | |
465 | * and TM. | |
466 | * | |
467 | * @bp: driver handle | |
468 | */ | |
469 | void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); | |
470 | ||
e4901dde | 471 | /** |
e8920674 | 472 | * bnx2x_dcbx_init - initialize dcbx protocol. |
e4901dde | 473 | * |
e8920674 | 474 | * @bp: driver handle |
e4901dde | 475 | */ |
9876879f | 476 | void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); |
e4901dde | 477 | |
f85582f8 | 478 | /** |
e8920674 | 479 | * bnx2x_set_power_state - set power state to the requested value. |
f85582f8 | 480 | * |
e8920674 DK |
481 | * @bp: driver handle |
482 | * @state: required state D0 or D3hot | |
f85582f8 | 483 | * |
e8920674 | 484 | * Currently only D0 and D3hot are supported. |
f85582f8 DK |
485 | */ |
486 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
487 | ||
e3835b99 | 488 | /** |
e8920674 | 489 | * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. |
e3835b99 | 490 | * |
e8920674 DK |
491 | * @bp: driver handle |
492 | * @value: new value | |
e3835b99 DK |
493 | */ |
494 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); | |
619c5cb6 | 495 | /* Error handling */ |
7a25cc73 DK |
496 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); |
497 | ||
f85582f8 | 498 | /* dev_close main block */ |
5d07d868 | 499 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); |
f85582f8 DK |
500 | |
501 | /* dev_open main block */ | |
502 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
503 | ||
504 | /* hard_xmit callback */ | |
505 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
506 | ||
6383c0b3 AE |
507 | /* setup_tc callback */ |
508 | int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); | |
509 | ||
3ec9f9ca AE |
510 | int bnx2x_get_vf_config(struct net_device *dev, int vf, |
511 | struct ifla_vf_info *ivi); | |
abc5a021 | 512 | int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); |
3ec9f9ca | 513 | int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos); |
abc5a021 | 514 | |
8307fa3e VZ |
515 | /* select_queue callback */ |
516 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); | |
517 | ||
dc1ba591 AE |
518 | static inline void bnx2x_update_rx_prod(struct bnx2x *bp, |
519 | struct bnx2x_fastpath *fp, | |
520 | u16 bd_prod, u16 rx_comp_prod, | |
521 | u16 rx_sge_prod) | |
522 | { | |
523 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
524 | u32 i; | |
525 | ||
526 | /* Update producers */ | |
527 | rx_prods.bd_prod = bd_prod; | |
528 | rx_prods.cqe_prod = rx_comp_prod; | |
529 | rx_prods.sge_prod = rx_sge_prod; | |
530 | ||
531 | /* Make sure that the BD and SGE data is updated before updating the | |
532 | * producers since FW might read the BD/SGE right after the producer | |
533 | * is updated. | |
534 | * This is only applicable for weak-ordered memory model archs such | |
535 | * as IA-64. The following barrier is also mandatory since FW will | |
536 | * assumes BDs must have buffers. | |
537 | */ | |
538 | wmb(); | |
539 | ||
540 | for (i = 0; i < sizeof(rx_prods)/4; i++) | |
541 | REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, | |
542 | ((u32 *)&rx_prods)[i]); | |
543 | ||
544 | mmiowb(); /* keep prod updates ordered */ | |
545 | ||
546 | DP(NETIF_MSG_RX_STATUS, | |
547 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
548 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
549 | } | |
550 | ||
a9fccec7 DK |
551 | /* reload helper */ |
552 | int bnx2x_reload_if_running(struct net_device *dev); | |
553 | ||
f85582f8 DK |
554 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); |
555 | ||
556 | /* NAPI poll Rx part */ | |
557 | int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); | |
558 | ||
559 | /* NAPI poll Tx part */ | |
6383c0b3 | 560 | int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); |
f85582f8 DK |
561 | |
562 | /* suspend/resume callbacks */ | |
563 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
564 | int bnx2x_resume(struct pci_dev *pdev); | |
565 | ||
566 | /* Release IRQ vectors */ | |
567 | void bnx2x_free_irq(struct bnx2x *bp); | |
568 | ||
55c11941 | 569 | void bnx2x_free_fp_mem_cnic(struct bnx2x *bp); |
b3b83c3f | 570 | void bnx2x_free_fp_mem(struct bnx2x *bp); |
55c11941 | 571 | int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp); |
b3b83c3f | 572 | int bnx2x_alloc_fp_mem(struct bnx2x *bp); |
f85582f8 | 573 | void bnx2x_init_rx_rings(struct bnx2x *bp); |
55c11941 MS |
574 | void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); |
575 | void bnx2x_free_skbs_cnic(struct bnx2x *bp); | |
f85582f8 DK |
576 | void bnx2x_free_skbs(struct bnx2x *bp); |
577 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
578 | void bnx2x_netif_start(struct bnx2x *bp); | |
55c11941 | 579 | int bnx2x_load_cnic(struct bnx2x *bp); |
f85582f8 | 580 | |
d6214d7a | 581 | /** |
e8920674 | 582 | * bnx2x_enable_msix - set msix configuration. |
d6214d7a | 583 | * |
e8920674 | 584 | * @bp: driver handle |
d6214d7a | 585 | * |
e8920674 DK |
586 | * fills msix_table, requests vectors, updates num_queues |
587 | * according to number of available vectors. | |
d6214d7a | 588 | */ |
0e8d2ec5 | 589 | int bnx2x_enable_msix(struct bnx2x *bp); |
d6214d7a DK |
590 | |
591 | /** | |
e8920674 | 592 | * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly |
d6214d7a | 593 | * |
e8920674 | 594 | * @bp: driver handle |
d6214d7a DK |
595 | */ |
596 | int bnx2x_enable_msi(struct bnx2x *bp); | |
597 | ||
d6214d7a | 598 | /** |
e8920674 | 599 | * bnx2x_poll - NAPI callback |
d6214d7a | 600 | * |
e8920674 DK |
601 | * @napi: napi structure |
602 | * @budget: | |
d6214d7a | 603 | * |
d6214d7a DK |
604 | */ |
605 | int bnx2x_poll(struct napi_struct *napi, int budget); | |
f85582f8 | 606 | |
8f20aa57 DK |
607 | /** |
608 | * bnx2x_low_latency_recv - LL callback | |
609 | * | |
610 | * @napi: napi structure | |
611 | */ | |
612 | int bnx2x_low_latency_recv(struct napi_struct *napi); | |
613 | ||
f85582f8 | 614 | /** |
e8920674 | 615 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
f85582f8 | 616 | * |
e8920674 | 617 | * @bp: driver handle |
f85582f8 | 618 | */ |
0329aba1 | 619 | int bnx2x_alloc_mem_bp(struct bnx2x *bp); |
e8920674 DK |
620 | |
621 | /** | |
622 | * bnx2x_free_mem_bp - release memories outsize main driver structure | |
623 | * | |
624 | * @bp: driver handle | |
625 | */ | |
f85582f8 DK |
626 | void bnx2x_free_mem_bp(struct bnx2x *bp); |
627 | ||
628 | /** | |
e8920674 | 629 | * bnx2x_change_mtu - change mtu netdev callback |
f85582f8 | 630 | * |
e8920674 DK |
631 | * @dev: net device |
632 | * @new_mtu: requested mtu | |
f85582f8 | 633 | * |
f85582f8 DK |
634 | */ |
635 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
636 | ||
55c11941 | 637 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
638 | /** |
639 | * bnx2x_fcoe_get_wwn - return the requested WWN value for this port | |
640 | * | |
641 | * @dev: net_device | |
642 | * @wwn: output buffer | |
643 | * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) | |
644 | * | |
645 | */ | |
646 | int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); | |
647 | #endif | |
621b4d66 | 648 | |
c8f44aff | 649 | netdev_features_t bnx2x_fix_features(struct net_device *dev, |
621b4d66 | 650 | netdev_features_t features); |
c8f44aff | 651 | int bnx2x_set_features(struct net_device *dev, netdev_features_t features); |
66371c44 | 652 | |
f85582f8 | 653 | /** |
e8920674 | 654 | * bnx2x_tx_timeout - tx timeout netdev callback |
f85582f8 | 655 | * |
e8920674 | 656 | * @dev: net device |
f85582f8 DK |
657 | */ |
658 | void bnx2x_tx_timeout(struct net_device *dev); | |
659 | ||
619c5cb6 VZ |
660 | /*********************** Inlines **********************************/ |
661 | /*********************** Fast path ********************************/ | |
9f6c9258 DK |
662 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
663 | { | |
9f6c9258 | 664 | barrier(); /* status block is written to by the chip */ |
523224a3 | 665 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
666 | } |
667 | ||
f2e0899f DK |
668 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
669 | u8 segment, u16 index, u8 op, | |
670 | u8 update, u32 igu_addr) | |
671 | { | |
672 | struct igu_regular cmd_data = {0}; | |
673 | ||
674 | cmd_data.sb_id_and_flags = | |
675 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
676 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
677 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
678 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
679 | ||
51c1a580 | 680 | DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", |
f2e0899f DK |
681 | cmd_data.sb_id_and_flags, igu_addr); |
682 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
683 | ||
684 | /* Make sure that ACK is written */ | |
685 | mmiowb(); | |
686 | barrier(); | |
687 | } | |
688 | ||
f2e0899f DK |
689 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, |
690 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
691 | { |
692 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
693 | COMMAND_REG_INT_ACK); | |
694 | struct igu_ack_register igu_ack; | |
695 | ||
696 | igu_ack.status_block_index = index; | |
697 | igu_ack.sb_id_and_flags = | |
698 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
699 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
700 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
701 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
702 | ||
9f6c9258 DK |
703 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); |
704 | ||
705 | /* Make sure that ACK is written */ | |
706 | mmiowb(); | |
707 | barrier(); | |
708 | } | |
f2e0899f | 709 | |
f2e0899f DK |
710 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, |
711 | u16 index, u8 op, u8 update) | |
712 | { | |
713 | if (bp->common.int_block == INT_BLOCK_HC) | |
714 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
715 | else { | |
716 | u8 segment; | |
717 | ||
718 | if (CHIP_INT_MODE_IS_BC(bp)) | |
719 | segment = storm; | |
720 | else if (igu_sb_id != bp->igu_dsb_id) | |
721 | segment = IGU_SEG_ACCESS_DEF; | |
722 | else if (storm == ATTENTION_ID) | |
723 | segment = IGU_SEG_ACCESS_ATTN; | |
724 | else | |
725 | segment = IGU_SEG_ACCESS_DEF; | |
726 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
727 | } | |
728 | } | |
729 | ||
730 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
731 | { |
732 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
733 | COMMAND_REG_SIMD_MASK); | |
734 | u32 result = REG_RD(bp, hc_addr); | |
735 | ||
f2e0899f | 736 | barrier(); |
9f6c9258 DK |
737 | return result; |
738 | } | |
739 | ||
f2e0899f DK |
740 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
741 | { | |
742 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
743 | u32 result = REG_RD(bp, igu_addr); | |
744 | ||
51c1a580 | 745 | DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", |
f2e0899f DK |
746 | result, igu_addr); |
747 | ||
748 | barrier(); | |
749 | return result; | |
750 | } | |
751 | ||
752 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
753 | { | |
754 | barrier(); | |
755 | if (bp->common.int_block == INT_BLOCK_HC) | |
756 | return bnx2x_hc_ack_int(bp); | |
757 | else | |
758 | return bnx2x_igu_ack_int(bp); | |
759 | } | |
760 | ||
6383c0b3 | 761 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
762 | { |
763 | /* Tell compiler that consumer and producer can change */ | |
764 | barrier(); | |
6383c0b3 | 765 | return txdata->tx_pkt_prod != txdata->tx_pkt_cons; |
9f6c9258 DK |
766 | } |
767 | ||
6383c0b3 AE |
768 | static inline u16 bnx2x_tx_avail(struct bnx2x *bp, |
769 | struct bnx2x_fp_txdata *txdata) | |
9f6c9258 DK |
770 | { |
771 | s16 used; | |
772 | u16 prod; | |
773 | u16 cons; | |
774 | ||
6383c0b3 AE |
775 | prod = txdata->tx_bd_prod; |
776 | cons = txdata->tx_bd_cons; | |
9f6c9258 | 777 | |
7b5342d9 | 778 | used = SUB_S16(prod, cons); |
9f6c9258 DK |
779 | |
780 | #ifdef BNX2X_STOP_ON_ERROR | |
781 | WARN_ON(used < 0); | |
7b5342d9 YM |
782 | WARN_ON(used > txdata->tx_ring_size); |
783 | WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); | |
9f6c9258 DK |
784 | #endif |
785 | ||
7b5342d9 | 786 | return (s16)(txdata->tx_ring_size) - used; |
9f6c9258 DK |
787 | } |
788 | ||
6383c0b3 | 789 | static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) |
9f6c9258 DK |
790 | { |
791 | u16 hw_cons; | |
792 | ||
793 | /* Tell compiler that status block fields can change */ | |
794 | barrier(); | |
6383c0b3 AE |
795 | hw_cons = le16_to_cpu(*txdata->tx_cons_sb); |
796 | return hw_cons != txdata->tx_pkt_cons; | |
797 | } | |
798 | ||
799 | static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
800 | { | |
801 | u8 cos; | |
802 | for_each_cos_in_tx_queue(fp, cos) | |
65565884 | 803 | if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) |
6383c0b3 AE |
804 | return true; |
805 | return false; | |
9f6c9258 DK |
806 | } |
807 | ||
523224a3 DK |
808 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
809 | { | |
810 | u16 rx_cons_sb; | |
811 | ||
812 | /* Tell compiler that status block fields can change */ | |
813 | barrier(); | |
814 | rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); | |
815 | if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) | |
816 | rx_cons_sb++; | |
817 | return (fp->rx_comp_cons != rx_cons_sb); | |
818 | } | |
f85582f8 | 819 | |
f2e0899f | 820 | /** |
619c5cb6 | 821 | * bnx2x_tx_disable - disables tx from stack point of view |
f2e0899f | 822 | * |
e8920674 | 823 | * @bp: driver handle |
f2e0899f DK |
824 | */ |
825 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
826 | { | |
827 | netif_tx_disable(bp->dev); | |
828 | netif_carrier_off(bp->dev); | |
829 | } | |
830 | ||
9f6c9258 DK |
831 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
832 | struct bnx2x_fastpath *fp, u16 index) | |
833 | { | |
834 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
835 | struct page *page = sw_buf->page; | |
836 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
837 | ||
838 | /* Skip "next page" elements */ | |
839 | if (!page) | |
840 | return; | |
841 | ||
842 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), | |
924d75ab | 843 | SGE_PAGES, DMA_FROM_DEVICE); |
9f6c9258 DK |
844 | __free_pages(page, PAGES_PER_SGE_SHIFT); |
845 | ||
846 | sw_buf->page = NULL; | |
847 | sge->addr_hi = 0; | |
848 | sge->addr_lo = 0; | |
849 | } | |
850 | ||
55c11941 | 851 | static inline void bnx2x_add_all_napi_cnic(struct bnx2x *bp) |
d6214d7a DK |
852 | { |
853 | int i; | |
523224a3 | 854 | |
55c11941 | 855 | /* Add NAPI objects */ |
8f20aa57 | 856 | for_each_rx_queue_cnic(bp, i) { |
55c11941 | 857 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
6fac4115 | 858 | bnx2x_poll, NAPI_POLL_WEIGHT); |
8f20aa57 DK |
859 | napi_hash_add(&bnx2x_fp(bp, i, napi)); |
860 | } | |
55c11941 MS |
861 | } |
862 | ||
863 | static inline void bnx2x_add_all_napi(struct bnx2x *bp) | |
864 | { | |
865 | int i; | |
0e8d2ec5 | 866 | |
d6214d7a | 867 | /* Add NAPI objects */ |
8f20aa57 | 868 | for_each_eth_queue(bp, i) { |
d6214d7a | 869 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
6fac4115 | 870 | bnx2x_poll, NAPI_POLL_WEIGHT); |
8f20aa57 DK |
871 | napi_hash_add(&bnx2x_fp(bp, i, napi)); |
872 | } | |
d6214d7a | 873 | } |
523224a3 | 874 | |
55c11941 MS |
875 | static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) |
876 | { | |
877 | int i; | |
878 | ||
8f20aa57 DK |
879 | for_each_rx_queue_cnic(bp, i) { |
880 | napi_hash_del(&bnx2x_fp(bp, i, napi)); | |
55c11941 | 881 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 882 | } |
55c11941 MS |
883 | } |
884 | ||
d6214d7a DK |
885 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
886 | { | |
887 | int i; | |
888 | ||
8f20aa57 DK |
889 | for_each_eth_queue(bp, i) { |
890 | napi_hash_del(&bnx2x_fp(bp, i, napi)); | |
d6214d7a | 891 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
8f20aa57 | 892 | } |
d6214d7a | 893 | } |
523224a3 | 894 | |
1ab4434c | 895 | int bnx2x_set_int_mode(struct bnx2x *bp); |
0e8d2ec5 | 896 | |
d6214d7a DK |
897 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
898 | { | |
899 | if (bp->flags & USING_MSIX_FLAG) { | |
900 | pci_disable_msix(bp->pdev); | |
30a5de77 | 901 | bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); |
d6214d7a DK |
902 | } else if (bp->flags & USING_MSI_FLAG) { |
903 | pci_disable_msi(bp->pdev); | |
904 | bp->flags &= ~USING_MSI_FLAG; | |
905 | } | |
906 | } | |
907 | ||
908 | static inline int bnx2x_calc_num_queues(struct bnx2x *bp) | |
909 | { | |
910 | return num_queues ? | |
911 | min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : | |
7d515413 YM |
912 | min_t(int, netif_get_num_default_rss_queues(), |
913 | BNX2X_MAX_QUEUES(bp)); | |
d6214d7a | 914 | } |
523224a3 DK |
915 | |
916 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) | |
9f6c9258 | 917 | { |
523224a3 | 918 | int i, j; |
9f6c9258 | 919 | |
523224a3 DK |
920 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
921 | int idx = RX_SGE_CNT * i - 1; | |
922 | ||
923 | for (j = 0; j < 2; j++) { | |
619c5cb6 | 924 | BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); |
523224a3 DK |
925 | idx--; |
926 | } | |
927 | } | |
928 | } | |
929 | ||
930 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
931 | { | |
932 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
b3637827 | 933 | memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); |
523224a3 DK |
934 | |
935 | /* Clear the two last indices in the page to 1: | |
936 | these are the indices that correspond to the "next" element, | |
937 | hence will never be indicated and should be removed from | |
938 | the calculations. */ | |
939 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
940 | } |
941 | ||
e52fcb24 | 942 | /* note that we are not allocating a new buffer, |
9f6c9258 DK |
943 | * we are just moving one from cons to prod |
944 | * we are not creating a new mapping, | |
945 | * so there is no need to check for dma_mapping_error(). | |
946 | */ | |
e52fcb24 | 947 | static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, |
749a8503 | 948 | u16 cons, u16 prod) |
9f6c9258 | 949 | { |
9f6c9258 DK |
950 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; |
951 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
952 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
953 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
954 | ||
9f6c9258 DK |
955 | dma_unmap_addr_set(prod_rx_buf, mapping, |
956 | dma_unmap_addr(cons_rx_buf, mapping)); | |
e52fcb24 | 957 | prod_rx_buf->data = cons_rx_buf->data; |
9f6c9258 DK |
958 | *prod_bd = *cons_bd; |
959 | } | |
f85582f8 | 960 | |
619c5cb6 VZ |
961 | /************************* Init ******************************************/ |
962 | ||
b475d78f YM |
963 | /* returns func by VN for current port */ |
964 | static inline int func_by_vn(struct bnx2x *bp, int vn) | |
965 | { | |
966 | return 2 * vn + BP_PORT(bp); | |
967 | } | |
968 | ||
5d317c6a | 969 | static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) |
96305234 | 970 | { |
5d317c6a | 971 | return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); |
96305234 DK |
972 | } |
973 | ||
619c5cb6 VZ |
974 | /** |
975 | * bnx2x_func_start - init function | |
976 | * | |
977 | * @bp: driver handle | |
978 | * | |
979 | * Must be called before sending CLIENT_SETUP for the first client. | |
980 | */ | |
981 | static inline int bnx2x_func_start(struct bnx2x *bp) | |
982 | { | |
3b603066 | 983 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 VZ |
984 | struct bnx2x_func_start_params *start_params = |
985 | &func_params.params.start; | |
986 | ||
987 | /* Prepare parameters for function state transitions */ | |
988 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
989 | ||
990 | func_params.f_obj = &bp->func_obj; | |
991 | func_params.cmd = BNX2X_F_CMD_START; | |
992 | ||
993 | /* Function parameters */ | |
994 | start_params->mf_mode = bp->mf_mode; | |
995 | start_params->sd_vlan_tag = bp->mf_ov; | |
8d7b0278 AE |
996 | |
997 | if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) | |
6383c0b3 | 998 | start_params->network_cos_mode = STATIC_COS; |
8d7b0278 AE |
999 | else /* CHIP_IS_E1X */ |
1000 | start_params->network_cos_mode = FW_WRR; | |
619c5cb6 | 1001 | |
1bc277f7 DK |
1002 | start_params->gre_tunnel_mode = IPGRE_TUNNEL; |
1003 | start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS; | |
1004 | ||
619c5cb6 VZ |
1005 | return bnx2x_func_state_change(bp, &func_params); |
1006 | } | |
1007 | ||
619c5cb6 VZ |
1008 | /** |
1009 | * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format | |
1010 | * | |
1011 | * @fw_hi: pointer to upper part | |
1012 | * @fw_mid: pointer to middle part | |
1013 | * @fw_lo: pointer to lower part | |
1014 | * @mac: pointer to MAC address | |
1015 | */ | |
86564c3f YM |
1016 | static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, |
1017 | __le16 *fw_lo, u8 *mac) | |
619c5cb6 VZ |
1018 | { |
1019 | ((u8 *)fw_hi)[0] = mac[1]; | |
1020 | ((u8 *)fw_hi)[1] = mac[0]; | |
1021 | ((u8 *)fw_mid)[0] = mac[3]; | |
1022 | ((u8 *)fw_mid)[1] = mac[2]; | |
1023 | ((u8 *)fw_lo)[0] = mac[5]; | |
1024 | ((u8 *)fw_lo)[1] = mac[4]; | |
1025 | } | |
1026 | ||
523224a3 DK |
1027 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
1028 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 1029 | { |
523224a3 | 1030 | int i; |
9f6c9258 | 1031 | |
b3b83c3f DK |
1032 | if (fp->disable_tpa) |
1033 | return; | |
1034 | ||
523224a3 DK |
1035 | for (i = 0; i < last; i++) |
1036 | bnx2x_free_rx_sge(bp, fp, i); | |
9f6c9258 DK |
1037 | } |
1038 | ||
523224a3 | 1039 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 1040 | { |
523224a3 | 1041 | int i; |
9f6c9258 | 1042 | |
523224a3 DK |
1043 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
1044 | struct eth_rx_bd *rx_bd; | |
1045 | ||
1046 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
1047 | rx_bd->addr_hi = | |
1048 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
1049 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
1050 | rx_bd->addr_lo = | |
1051 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
1052 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
1053 | } | |
9f6c9258 DK |
1054 | } |
1055 | ||
619c5cb6 VZ |
1056 | /* Statistics ID are global per chip/path, while Client IDs for E1x are per |
1057 | * port. | |
1058 | */ | |
1059 | static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) | |
1060 | { | |
de5c3741 YM |
1061 | struct bnx2x *bp = fp->bp; |
1062 | if (!CHIP_IS_E1x(bp)) { | |
de5c3741 YM |
1063 | /* there are special statistics counters for FCoE 136..140 */ |
1064 | if (IS_FCOE_FP(fp)) | |
1065 | return bp->cnic_base_cl_id + (bp->pf_num >> 1); | |
619c5cb6 | 1066 | return fp->cl_id; |
de5c3741 YM |
1067 | } |
1068 | return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; | |
619c5cb6 VZ |
1069 | } |
1070 | ||
1071 | static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, | |
1072 | bnx2x_obj_type obj_type) | |
1073 | { | |
1074 | struct bnx2x *bp = fp->bp; | |
1075 | ||
1076 | /* Configure classification DBs */ | |
15192a8c BW |
1077 | bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, |
1078 | fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), | |
619c5cb6 VZ |
1079 | bnx2x_sp_mapping(bp, mac_rdata), |
1080 | BNX2X_FILTER_MAC_PENDING, | |
1081 | &bp->sp_state, obj_type, | |
1082 | &bp->macs_pool); | |
1083 | } | |
1084 | ||
1085 | /** | |
1086 | * bnx2x_get_path_func_num - get number of active functions | |
1087 | * | |
1088 | * @bp: driver handle | |
1089 | * | |
1090 | * Calculates the number of active (not hidden) functions on the | |
1091 | * current path. | |
1092 | */ | |
1093 | static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) | |
1094 | { | |
1095 | u8 func_num = 0, i; | |
1096 | ||
1097 | /* 57710 has only one function per-port */ | |
1098 | if (CHIP_IS_E1(bp)) | |
1099 | return 1; | |
1100 | ||
1101 | /* Calculate a number of functions enabled on the current | |
1102 | * PATH/PORT. | |
1103 | */ | |
1104 | if (CHIP_REV_IS_SLOW(bp)) { | |
1105 | if (IS_MF(bp)) | |
1106 | func_num = 4; | |
1107 | else | |
1108 | func_num = 2; | |
1109 | } else { | |
1110 | for (i = 0; i < E1H_FUNC_MAX / 2; i++) { | |
1111 | u32 func_config = | |
1112 | MF_CFG_RD(bp, | |
1113 | func_mf_config[BP_PORT(bp) + 2 * i]. | |
1114 | config); | |
1115 | func_num += | |
1116 | ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); | |
1117 | } | |
1118 | } | |
1119 | ||
1120 | WARN_ON(!func_num); | |
1121 | ||
1122 | return func_num; | |
1123 | } | |
1124 | ||
1125 | static inline void bnx2x_init_bp_objs(struct bnx2x *bp) | |
1126 | { | |
1127 | /* RX_MODE controlling object */ | |
1128 | bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); | |
1129 | ||
1130 | /* multicast configuration controlling object */ | |
1131 | bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, | |
1132 | BP_FUNC(bp), BP_FUNC(bp), | |
1133 | bnx2x_sp(bp, mcast_rdata), | |
1134 | bnx2x_sp_mapping(bp, mcast_rdata), | |
1135 | BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, | |
1136 | BNX2X_OBJ_TYPE_RX); | |
1137 | ||
1138 | /* Setup CAM credit pools */ | |
1139 | bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), | |
1140 | bnx2x_get_path_func_num(bp)); | |
1141 | ||
b56e9670 AE |
1142 | bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1, |
1143 | bnx2x_get_path_func_num(bp)); | |
1144 | ||
619c5cb6 VZ |
1145 | /* RSS configuration object */ |
1146 | bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, | |
1147 | bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), | |
1148 | bnx2x_sp(bp, rss_rdata), | |
1149 | bnx2x_sp_mapping(bp, rss_rdata), | |
1150 | BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, | |
1151 | BNX2X_OBJ_TYPE_RX); | |
1152 | } | |
1153 | ||
1154 | static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) | |
1155 | { | |
1156 | if (CHIP_IS_E1x(fp->bp)) | |
1157 | return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; | |
1158 | else | |
1159 | return fp->cl_id; | |
1160 | } | |
1161 | ||
6411280a | 1162 | u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); |
619c5cb6 | 1163 | |
6383c0b3 | 1164 | static inline void bnx2x_init_txdata(struct bnx2x *bp, |
65565884 MS |
1165 | struct bnx2x_fp_txdata *txdata, u32 cid, |
1166 | int txq_index, __le16 *tx_cons_sb, | |
1167 | struct bnx2x_fastpath *fp) | |
6383c0b3 AE |
1168 | { |
1169 | txdata->cid = cid; | |
1170 | txdata->txq_index = txq_index; | |
1171 | txdata->tx_cons_sb = tx_cons_sb; | |
65565884 | 1172 | txdata->parent_fp = fp; |
7b5342d9 | 1173 | txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; |
6383c0b3 | 1174 | |
51c1a580 | 1175 | DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", |
6383c0b3 AE |
1176 | txdata->cid, txdata->txq_index); |
1177 | } | |
619c5cb6 | 1178 | |
619c5cb6 VZ |
1179 | static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) |
1180 | { | |
1181 | return bp->cnic_base_cl_id + cl_idx + | |
134d0f97 | 1182 | (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; |
619c5cb6 VZ |
1183 | } |
1184 | ||
1185 | static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) | |
1186 | { | |
619c5cb6 VZ |
1187 | /* the 'first' id is allocated for the cnic */ |
1188 | return bp->base_fw_ndsb; | |
1189 | } | |
1190 | ||
1191 | static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) | |
1192 | { | |
1193 | return bp->igu_base_sb; | |
1194 | } | |
1195 | ||
ec6ba945 VZ |
1196 | static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) |
1197 | { | |
619c5cb6 VZ |
1198 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); |
1199 | unsigned long q_type = 0; | |
1200 | ||
f233cafe | 1201 | bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); |
619c5cb6 VZ |
1202 | bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, |
1203 | BNX2X_FCOE_ETH_CL_ID_IDX); | |
37ae41a9 | 1204 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); |
ec6ba945 VZ |
1205 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; |
1206 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
ec6ba945 | 1207 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; |
65565884 MS |
1208 | bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), |
1209 | fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, | |
1210 | fp); | |
6383c0b3 | 1211 | |
51c1a580 | 1212 | DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); |
6383c0b3 | 1213 | |
ec6ba945 | 1214 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 | 1215 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); |
ec6ba945 | 1216 | /* init shortcut */ |
619c5cb6 VZ |
1217 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = |
1218 | bnx2x_rx_ustorm_prods_offset(fp); | |
1219 | ||
1220 | /* Configure Queue State object */ | |
1221 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
1222 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
1223 | |
1224 | /* No multi-CoS for FCoE L2 client */ | |
1225 | BUG_ON(fp->max_cos != 1); | |
1226 | ||
15192a8c BW |
1227 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, |
1228 | &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 1229 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 | 1230 | |
51c1a580 MS |
1231 | DP(NETIF_MSG_IFUP, |
1232 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
619c5cb6 VZ |
1233 | fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, |
1234 | fp->igu_sb_id); | |
ec6ba945 | 1235 | } |
523224a3 | 1236 | |
619c5cb6 | 1237 | static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, |
6383c0b3 | 1238 | struct bnx2x_fp_txdata *txdata) |
619c5cb6 VZ |
1239 | { |
1240 | int cnt = 1000; | |
1241 | ||
6383c0b3 | 1242 | while (bnx2x_has_tx_work_unload(txdata)) { |
619c5cb6 | 1243 | if (!cnt) { |
51c1a580 | 1244 | BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", |
6383c0b3 AE |
1245 | txdata->txq_index, txdata->tx_pkt_prod, |
1246 | txdata->tx_pkt_cons); | |
619c5cb6 VZ |
1247 | #ifdef BNX2X_STOP_ON_ERROR |
1248 | bnx2x_panic(); | |
1249 | return -EBUSY; | |
1250 | #else | |
1251 | break; | |
1252 | #endif | |
1253 | } | |
1254 | cnt--; | |
0926d499 | 1255 | usleep_range(1000, 2000); |
619c5cb6 VZ |
1256 | } |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
1ac9e428 YR |
1261 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
1262 | ||
523224a3 DK |
1263 | static inline void __storm_memset_struct(struct bnx2x *bp, |
1264 | u32 addr, size_t size, u32 *data) | |
1265 | { | |
1266 | int i; | |
1267 | for (i = 0; i < size/4; i++) | |
1268 | REG_WR(bp, addr + (i * 4), data[i]); | |
1269 | } | |
1270 | ||
619c5cb6 VZ |
1271 | /** |
1272 | * bnx2x_wait_sp_comp - wait for the outstanding SP commands. | |
1273 | * | |
1274 | * @bp: driver handle | |
1275 | * @mask: bits that need to be cleared | |
1276 | */ | |
1277 | static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) | |
1278 | { | |
1279 | int tout = 5000; /* Wait for 5 secs tops */ | |
1280 | ||
1281 | while (tout--) { | |
1282 | smp_mb(); | |
1283 | netif_addr_lock_bh(bp->dev); | |
1284 | if (!(bp->sp_state & mask)) { | |
1285 | netif_addr_unlock_bh(bp->dev); | |
1286 | return true; | |
1287 | } | |
1288 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1289 | |
0926d499 | 1290 | usleep_range(1000, 2000); |
619c5cb6 VZ |
1291 | } |
1292 | ||
1293 | smp_mb(); | |
1294 | ||
1295 | netif_addr_lock_bh(bp->dev); | |
1296 | if (bp->sp_state & mask) { | |
51c1a580 MS |
1297 | BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", |
1298 | bp->sp_state, mask); | |
619c5cb6 VZ |
1299 | netif_addr_unlock_bh(bp->dev); |
1300 | return false; | |
1301 | } | |
1302 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1303 | |
619c5cb6 | 1304 | return true; |
523224a3 | 1305 | } |
f85582f8 | 1306 | |
619c5cb6 VZ |
1307 | /** |
1308 | * bnx2x_set_ctx_validation - set CDU context validation values | |
1309 | * | |
1310 | * @bp: driver handle | |
1311 | * @cxt: context of the connection on the host memory | |
1312 | * @cid: SW CID of the connection to be configured | |
1313 | */ | |
1314 | void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, | |
1315 | u32 cid); | |
1316 | ||
1317 | void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, | |
1318 | u8 sb_index, u8 disable, u16 usec); | |
9f6c9258 DK |
1319 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); |
1320 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
1321 | ||
faa6fcbb | 1322 | /** |
e8920674 | 1323 | * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. |
faa6fcbb | 1324 | * |
e8920674 DK |
1325 | * @bp: driver handle |
1326 | * @mf_cfg: MF configuration | |
faa6fcbb | 1327 | * |
faa6fcbb DK |
1328 | */ |
1329 | static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) | |
1330 | { | |
1331 | u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> | |
1332 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1333 | if (!max_cfg) { | |
51c1a580 | 1334 | DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, |
96b0accb | 1335 | "Max BW configured to 0 - using 100 instead\n"); |
faa6fcbb DK |
1336 | max_cfg = 100; |
1337 | } | |
1338 | return max_cfg; | |
1339 | } | |
1340 | ||
621b4d66 DK |
1341 | /* checks if HW supports GRO for given MTU */ |
1342 | static inline bool bnx2x_mtu_allows_gro(int mtu) | |
1343 | { | |
1344 | /* gro frags per page */ | |
1345 | int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); | |
1346 | ||
1347 | /* | |
16a5fd92 YM |
1348 | * 1. Number of frags should not grow above MAX_SKB_FRAGS |
1349 | * 2. Frag must fit the page | |
621b4d66 DK |
1350 | */ |
1351 | return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; | |
1352 | } | |
55c11941 | 1353 | |
b306f5ed DK |
1354 | /** |
1355 | * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. | |
1356 | * | |
1357 | * @bp: driver handle | |
1358 | * | |
1359 | */ | |
1360 | void bnx2x_get_iscsi_info(struct bnx2x *bp); | |
00253a8c DK |
1361 | |
1362 | /** | |
1363 | * bnx2x_link_sync_notify - send notification to other functions. | |
1364 | * | |
1365 | * @bp: driver handle | |
1366 | * | |
1367 | */ | |
1368 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) | |
1369 | { | |
1370 | int func; | |
1371 | int vn; | |
1372 | ||
1373 | /* Set the attention towards other drivers on the same port */ | |
1374 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
1375 | if (vn == BP_VN(bp)) | |
1376 | continue; | |
1377 | ||
1378 | func = func_by_vn(bp, vn); | |
1379 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | |
1380 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | |
1381 | } | |
1382 | } | |
1383 | ||
1384 | /** | |
1385 | * bnx2x_update_drv_flags - update flags in shmem | |
1386 | * | |
1387 | * @bp: driver handle | |
1388 | * @flags: flags to update | |
1389 | * @set: set or clear | |
1390 | * | |
1391 | */ | |
1392 | static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) | |
1393 | { | |
1394 | if (SHMEM2_HAS(bp, drv_flags)) { | |
1395 | u32 drv_flags; | |
f16da43b | 1396 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1397 | drv_flags = SHMEM2_RD(bp, drv_flags); |
1398 | ||
1399 | if (set) | |
1400 | SET_FLAGS(drv_flags, flags); | |
1401 | else | |
1402 | RESET_FLAGS(drv_flags, flags); | |
1403 | ||
1404 | SHMEM2_WR(bp, drv_flags, drv_flags); | |
51c1a580 | 1405 | DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); |
f16da43b | 1406 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); |
00253a8c DK |
1407 | } |
1408 | } | |
1409 | ||
614c76df DK |
1410 | static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) |
1411 | { | |
55c11941 MS |
1412 | if (is_valid_ether_addr(addr) || |
1413 | (is_zero_ether_addr(addr) && | |
1414 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))) | |
614c76df | 1415 | return true; |
55c11941 | 1416 | |
614c76df DK |
1417 | return false; |
1418 | } | |
1419 | ||
8ca5e17e | 1420 | /** |
2de67439 | 1421 | * bnx2x_fill_fw_str - Fill buffer with FW version string |
8ca5e17e AE |
1422 | * |
1423 | * @bp: driver handle | |
1424 | * @buf: character buffer to fill with the fw name | |
1425 | * @buf_len: length of the above buffer | |
1426 | * | |
1427 | */ | |
1428 | void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); | |
7fa6f340 YM |
1429 | |
1430 | int bnx2x_drain_tx_queues(struct bnx2x *bp); | |
1431 | void bnx2x_squeeze_objects(struct bnx2x *bp); | |
1432 | ||
9f6c9258 | 1433 | #endif /* BNX2X_CMN_H */ |