Commit | Line | Data |
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a2fbb9ea ET |
1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | |
85b26ea1 | 3 | * Copyright (c) 2007-2012 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
ec6ba945 | 16 | #include <linux/netdevice.h> |
b7f080cf | 17 | #include <linux/dma-mapping.h> |
ec6ba945 | 18 | #include <linux/types.h> |
a2fbb9ea | 19 | |
34f80b04 EG |
20 | /* compilation time flags */ |
21 | ||
22 | /* define this to make the driver freeze on error to allow getting debug info | |
23 | * (you will need to reboot afterwards) */ | |
24 | /* #define BNX2X_STOP_ON_ERROR */ | |
25 | ||
0b0a635f DK |
26 | #define DRV_MODULE_VERSION "1.72.10-0" |
27 | #define DRV_MODULE_RELDATE "2012/02/20" | |
de0c62db DK |
28 | #define BNX2X_BC_VER 0x040200 |
29 | ||
785b9b1a | 30 | #if defined(CONFIG_DCB) |
98507672 | 31 | #define BCM_DCBNL |
785b9b1a | 32 | #endif |
993ac7b5 MC |
33 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
34 | #define BCM_CNIC 1 | |
5d1e859c | 35 | #include "../cnic_if.h" |
993ac7b5 | 36 | #endif |
0c6671b0 | 37 | |
1ac218c8 VZ |
38 | #ifdef BCM_CNIC |
39 | #define BNX2X_MIN_MSIX_VEC_CNT 3 | |
40 | #define BNX2X_MSIX_VEC_FP_START 2 | |
41 | #else | |
42 | #define BNX2X_MIN_MSIX_VEC_CNT 2 | |
43 | #define BNX2X_MSIX_VEC_FP_START 1 | |
44 | #endif | |
01cd4528 EG |
45 | |
46 | #include <linux/mdio.h> | |
619c5cb6 | 47 | |
359d8b15 EG |
48 | #include "bnx2x_reg.h" |
49 | #include "bnx2x_fw_defs.h" | |
50 | #include "bnx2x_hsi.h" | |
51 | #include "bnx2x_link.h" | |
619c5cb6 | 52 | #include "bnx2x_sp.h" |
e4901dde | 53 | #include "bnx2x_dcb.h" |
6c719d00 | 54 | #include "bnx2x_stats.h" |
359d8b15 | 55 | |
a2fbb9ea ET |
56 | /* error/debug prints */ |
57 | ||
34f80b04 | 58 | #define DRV_MODULE_NAME "bnx2x" |
a2fbb9ea ET |
59 | |
60 | /* for messages that are currently off */ | |
51c1a580 MS |
61 | #define BNX2X_MSG_OFF 0x0 |
62 | #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ | |
63 | #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ | |
64 | #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ | |
65 | #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ | |
66 | #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ | |
67 | #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ | |
68 | #define BNX2X_MSG_IOV 0x0800000 | |
69 | #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ | |
70 | #define BNX2X_MSG_ETHTOOL 0x4000000 | |
71 | #define BNX2X_MSG_DCB 0x8000000 | |
a2fbb9ea | 72 | |
a2fbb9ea | 73 | /* regular debug print */ |
f1deab50 | 74 | #define DP(__mask, fmt, ...) \ |
7995c64e | 75 | do { \ |
51c1a580 | 76 | if (unlikely(bp->msg_enable & (__mask))) \ |
f1deab50 JP |
77 | pr_notice("[%s:%d(%s)]" fmt, \ |
78 | __func__, __LINE__, \ | |
79 | bp->dev ? (bp->dev->name) : "?", \ | |
80 | ##__VA_ARGS__); \ | |
7995c64e | 81 | } while (0) |
a2fbb9ea | 82 | |
f1deab50 | 83 | #define DP_CONT(__mask, fmt, ...) \ |
619c5cb6 | 84 | do { \ |
51c1a580 | 85 | if (unlikely(bp->msg_enable & (__mask))) \ |
f1deab50 | 86 | pr_cont(fmt, ##__VA_ARGS__); \ |
619c5cb6 VZ |
87 | } while (0) |
88 | ||
34f80b04 | 89 | /* errors debug print */ |
f1deab50 | 90 | #define BNX2X_DBG_ERR(fmt, ...) \ |
7995c64e | 91 | do { \ |
51c1a580 | 92 | if (unlikely(netif_msg_probe(bp))) \ |
f1deab50 | 93 | pr_err("[%s:%d(%s)]" fmt, \ |
7995c64e JP |
94 | __func__, __LINE__, \ |
95 | bp->dev ? (bp->dev->name) : "?", \ | |
f1deab50 | 96 | ##__VA_ARGS__); \ |
7995c64e | 97 | } while (0) |
a2fbb9ea | 98 | |
34f80b04 | 99 | /* for errors (never masked) */ |
f1deab50 | 100 | #define BNX2X_ERR(fmt, ...) \ |
7995c64e | 101 | do { \ |
f1deab50 | 102 | pr_err("[%s:%d(%s)]" fmt, \ |
7995c64e JP |
103 | __func__, __LINE__, \ |
104 | bp->dev ? (bp->dev->name) : "?", \ | |
f1deab50 JP |
105 | ##__VA_ARGS__); \ |
106 | } while (0) | |
cdaa7cb8 | 107 | |
f1deab50 JP |
108 | #define BNX2X_ERROR(fmt, ...) \ |
109 | pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) | |
cdaa7cb8 | 110 | |
f1410647 | 111 | |
a2fbb9ea | 112 | /* before we have a dev->name use dev_info() */ |
f1deab50 | 113 | #define BNX2X_DEV_INFO(fmt, ...) \ |
7995c64e | 114 | do { \ |
51c1a580 | 115 | if (unlikely(netif_msg_probe(bp))) \ |
f1deab50 | 116 | dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ |
7995c64e | 117 | } while (0) |
a2fbb9ea | 118 | |
a2fbb9ea | 119 | #ifdef BNX2X_STOP_ON_ERROR |
6383c0b3 | 120 | void bnx2x_int_disable(struct bnx2x *bp); |
f1deab50 JP |
121 | #define bnx2x_panic() \ |
122 | do { \ | |
123 | bp->panic = 1; \ | |
124 | BNX2X_ERR("driver assert\n"); \ | |
125 | bnx2x_int_disable(bp); \ | |
126 | bnx2x_panic_dump(bp); \ | |
127 | } while (0) | |
a2fbb9ea | 128 | #else |
f1deab50 JP |
129 | #define bnx2x_panic() \ |
130 | do { \ | |
131 | bp->panic = 1; \ | |
132 | BNX2X_ERR("driver assert\n"); \ | |
133 | bnx2x_panic_dump(bp); \ | |
134 | } while (0) | |
a2fbb9ea ET |
135 | #endif |
136 | ||
523224a3 | 137 | #define bnx2x_mc_addr(ha) ((ha)->addr) |
6e30dd4e | 138 | #define bnx2x_uc_addr(ha) ((ha)->addr) |
a2fbb9ea | 139 | |
34f80b04 EG |
140 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
141 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | |
142 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
a2fbb9ea | 143 | |
a2fbb9ea | 144 | |
523224a3 | 145 | #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) |
a2fbb9ea | 146 | |
34f80b04 EG |
147 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
148 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
523224a3 | 149 | #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) |
34f80b04 EG |
150 | |
151 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
a2fbb9ea | 152 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
34f80b04 | 153 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
a2fbb9ea | 154 | |
34f80b04 EG |
155 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
156 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
a2fbb9ea | 157 | |
c18487ee YR |
158 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
159 | do { \ | |
160 | bnx2x_read_dmae(bp, offset, len32);\ | |
573f2035 | 161 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ |
c18487ee YR |
162 | } while (0) |
163 | ||
34f80b04 | 164 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
a2fbb9ea | 165 | do { \ |
573f2035 | 166 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ |
a2fbb9ea ET |
167 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
168 | offset, len32); \ | |
169 | } while (0) | |
170 | ||
523224a3 DK |
171 | #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ |
172 | REG_WR_DMAE(bp, offset, valp, len32) | |
173 | ||
3359fced | 174 | #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ |
573f2035 EG |
175 | do { \ |
176 | memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ | |
177 | bnx2x_write_big_buf_wb(bp, addr, len32); \ | |
178 | } while (0) | |
179 | ||
34f80b04 EG |
180 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
181 | offsetof(struct shmem_region, field)) | |
182 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
183 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
a2fbb9ea | 184 | |
2691d51d EG |
185 | #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ |
186 | offsetof(struct shmem2_region, field)) | |
187 | #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) | |
188 | #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) | |
523224a3 DK |
189 | #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ |
190 | offsetof(struct mf_cfg, field)) | |
f85582f8 | 191 | #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ |
f2e0899f | 192 | offsetof(struct mf2_cfg, field)) |
2691d51d | 193 | |
523224a3 DK |
194 | #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) |
195 | #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ | |
196 | MF_CFG_ADDR(bp, field), (val)) | |
f2e0899f | 197 | #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) |
f85582f8 | 198 | |
f2e0899f DK |
199 | #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ |
200 | (SHMEM2_RD((bp), size) > \ | |
201 | offsetof(struct shmem2_region, field))) | |
72fd0718 | 202 | |
345b5d52 | 203 | #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
3196a88a | 204 | #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
a2fbb9ea | 205 | |
523224a3 DK |
206 | /* SP SB indices */ |
207 | ||
208 | /* General SP events - stats query, cfc delete, etc */ | |
209 | #define HC_SP_INDEX_ETH_DEF_CONS 3 | |
210 | ||
211 | /* EQ completions */ | |
212 | #define HC_SP_INDEX_EQ_CONS 7 | |
213 | ||
ec6ba945 VZ |
214 | /* FCoE L2 connection completions */ |
215 | #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 | |
216 | #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 | |
523224a3 DK |
217 | /* iSCSI L2 */ |
218 | #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 | |
219 | #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 | |
220 | ||
ec6ba945 VZ |
221 | /* Special clients parameters */ |
222 | ||
223 | /* SB indices */ | |
224 | /* FCoE L2 */ | |
225 | #define BNX2X_FCOE_L2_RX_INDEX \ | |
226 | (&bp->def_status_blk->sp_sb.\ | |
227 | index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) | |
228 | ||
229 | #define BNX2X_FCOE_L2_TX_INDEX \ | |
230 | (&bp->def_status_blk->sp_sb.\ | |
231 | index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) | |
232 | ||
523224a3 DK |
233 | /** |
234 | * CIDs and CLIDs: | |
235 | * CLIDs below is a CLID for func 0, then the CLID for other | |
236 | * functions will be calculated by the formula: | |
237 | * | |
238 | * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X | |
239 | * | |
240 | */ | |
134d0f97 DK |
241 | enum { |
242 | BNX2X_ISCSI_ETH_CL_ID_IDX, | |
243 | BNX2X_FCOE_ETH_CL_ID_IDX, | |
244 | BNX2X_MAX_CNIC_ETH_CL_ID_IDX, | |
245 | }; | |
246 | ||
247 | #define BNX2X_CNIC_START_ETH_CID 48 | |
248 | enum { | |
249 | /* iSCSI L2 */ | |
250 | BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID, | |
251 | /* FCoE L2 */ | |
252 | BNX2X_FCOE_ETH_CID, | |
253 | }; | |
ec6ba945 | 254 | |
523224a3 DK |
255 | /** Additional rings budgeting */ |
256 | #ifdef BCM_CNIC | |
6383c0b3 AE |
257 | #define CNIC_PRESENT 1 |
258 | #define FCOE_PRESENT 1 | |
523224a3 | 259 | #else |
6383c0b3 AE |
260 | #define CNIC_PRESENT 0 |
261 | #define FCOE_PRESENT 0 | |
523224a3 | 262 | #endif /* BCM_CNIC */ |
6383c0b3 | 263 | #define NON_ETH_CONTEXT_USE (FCOE_PRESENT) |
523224a3 | 264 | |
72fd0718 VZ |
265 | #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ |
266 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR | |
267 | ||
523224a3 DK |
268 | #define SM_RX_ID 0 |
269 | #define SM_TX_ID 1 | |
a2fbb9ea | 270 | |
6383c0b3 AE |
271 | /* defines for multiple tx priority indices */ |
272 | #define FIRST_TX_ONLY_COS_INDEX 1 | |
273 | #define FIRST_TX_COS_INDEX 0 | |
274 | ||
275 | /* defines for decodeing the fastpath index and the cos index out of the | |
276 | * transmission queue index | |
277 | */ | |
278 | #define MAX_TXQS_PER_COS FP_SB_MAX_E1x | |
279 | ||
280 | #define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS) | |
281 | #define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS) | |
282 | ||
283 | /* rules for calculating the cids of tx-only connections */ | |
284 | #define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS) | |
285 | #define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS) | |
286 | ||
287 | /* fp index inside class of service range */ | |
288 | #define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS) | |
289 | ||
290 | /* | |
291 | * 0..15 eth cos0 | |
292 | * 16..31 eth cos1 if applicable | |
293 | * 32..47 eth cos2 If applicable | |
294 | * fcoe queue follows eth queues (16, 32, 48 depending on cos) | |
295 | */ | |
296 | #define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos) | |
297 | #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp)) | |
a2fbb9ea | 298 | |
6383c0b3 | 299 | /* fast path */ |
e52fcb24 ED |
300 | /* |
301 | * This driver uses new build_skb() API : | |
302 | * RX ring buffer contains pointer to kmalloc() data only, | |
303 | * skb are built only after Hardware filled the frame. | |
304 | */ | |
a2fbb9ea | 305 | struct sw_rx_bd { |
e52fcb24 | 306 | u8 *data; |
1a983142 | 307 | DEFINE_DMA_UNMAP_ADDR(mapping); |
a2fbb9ea ET |
308 | }; |
309 | ||
310 | struct sw_tx_bd { | |
34f80b04 EG |
311 | struct sk_buff *skb; |
312 | u16 first_bd; | |
ca00392c EG |
313 | u8 flags; |
314 | /* Set on the first BD descriptor when there is a split BD */ | |
315 | #define BNX2X_TSO_SPLIT_BD (1<<0) | |
a2fbb9ea ET |
316 | }; |
317 | ||
7a9b2557 VZ |
318 | struct sw_rx_page { |
319 | struct page *page; | |
1a983142 | 320 | DEFINE_DMA_UNMAP_ADDR(mapping); |
7a9b2557 VZ |
321 | }; |
322 | ||
ca00392c EG |
323 | union db_prod { |
324 | struct doorbell_set_prod data; | |
325 | u32 raw; | |
326 | }; | |
327 | ||
dfacf138 DK |
328 | /* dropless fc FW/HW related params */ |
329 | #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) | |
330 | #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ | |
331 | ETH_MAX_AGGREGATION_QUEUES_E1 :\ | |
332 | ETH_MAX_AGGREGATION_QUEUES_E1H_E2) | |
333 | #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) | |
334 | #define FW_PREFETCH_CNT 16 | |
335 | #define DROPLESS_FC_HEADROOM 100 | |
7a9b2557 VZ |
336 | |
337 | /* MC hsi */ | |
619c5cb6 VZ |
338 | #define BCM_PAGE_SHIFT 12 |
339 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
340 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
7a9b2557 VZ |
341 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) |
342 | ||
619c5cb6 VZ |
343 | #define PAGES_PER_SGE_SHIFT 0 |
344 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | |
345 | #define SGE_PAGE_SIZE PAGE_SIZE | |
346 | #define SGE_PAGE_SHIFT PAGE_SHIFT | |
347 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) | |
fe603b4d | 348 | #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) |
7a9b2557 VZ |
349 | |
350 | /* SGE ring related macros */ | |
619c5cb6 | 351 | #define NUM_RX_SGE_PAGES 2 |
7a9b2557 | 352 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) |
dfacf138 DK |
353 | #define NEXT_PAGE_SGE_DESC_CNT 2 |
354 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) | |
33471629 | 355 | /* RX_SGE_CNT is promised to be a power of 2 */ |
619c5cb6 VZ |
356 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
357 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | |
358 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | |
7a9b2557 | 359 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ |
dfacf138 DK |
360 | (MAX_RX_SGE_CNT - 1)) ? \ |
361 | (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ | |
362 | (x) + 1) | |
619c5cb6 VZ |
363 | #define RX_SGE(x) ((x) & MAX_RX_SGE) |
364 | ||
dfacf138 DK |
365 | /* |
366 | * Number of required SGEs is the sum of two: | |
367 | * 1. Number of possible opened aggregations (next packet for | |
368 | * these aggregations will probably consume SGE immidiatelly) | |
369 | * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only | |
370 | * after placement on BD for new TPA aggregation) | |
371 | * | |
372 | * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page | |
373 | */ | |
374 | #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ | |
375 | (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) | |
376 | #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ | |
377 | MAX_RX_SGE_CNT) | |
378 | #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ | |
379 | NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) | |
380 | #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) | |
381 | ||
619c5cb6 | 382 | /* Manipulate a bit vector defined as an array of u64 */ |
7a9b2557 | 383 | |
7a9b2557 | 384 | /* Number of bits in one sge_mask array element */ |
619c5cb6 VZ |
385 | #define BIT_VEC64_ELEM_SZ 64 |
386 | #define BIT_VEC64_ELEM_SHIFT 6 | |
387 | #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) | |
388 | ||
389 | ||
390 | #define __BIT_VEC64_SET_BIT(el, bit) \ | |
391 | do { \ | |
392 | el = ((el) | ((u64)0x1 << (bit))); \ | |
393 | } while (0) | |
394 | ||
395 | #define __BIT_VEC64_CLEAR_BIT(el, bit) \ | |
396 | do { \ | |
397 | el = ((el) & (~((u64)0x1 << (bit)))); \ | |
398 | } while (0) | |
399 | ||
400 | ||
401 | #define BIT_VEC64_SET_BIT(vec64, idx) \ | |
402 | __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ | |
403 | (idx) & BIT_VEC64_ELEM_MASK) | |
404 | ||
405 | #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ | |
406 | __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ | |
407 | (idx) & BIT_VEC64_ELEM_MASK) | |
408 | ||
409 | #define BIT_VEC64_TEST_BIT(vec64, idx) \ | |
410 | (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ | |
411 | ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) | |
7a9b2557 VZ |
412 | |
413 | /* Creates a bitmask of all ones in less significant bits. | |
414 | idx - index of the most significant bit in the created mask */ | |
619c5cb6 VZ |
415 | #define BIT_VEC64_ONES_MASK(idx) \ |
416 | (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) | |
417 | #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) | |
418 | ||
419 | /*******************************************************/ | |
420 | ||
421 | ||
7a9b2557 VZ |
422 | |
423 | /* Number of u64 elements in SGE mask array */ | |
b3637827 | 424 | #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) |
7a9b2557 VZ |
425 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) |
426 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) | |
427 | ||
523224a3 DK |
428 | union host_hc_status_block { |
429 | /* pointer to fp status block e1x */ | |
430 | struct host_hc_status_block_e1x *e1x_sb; | |
f2e0899f DK |
431 | /* pointer to fp status block e2 */ |
432 | struct host_hc_status_block_e2 *e2_sb; | |
523224a3 | 433 | }; |
7a9b2557 | 434 | |
619c5cb6 VZ |
435 | struct bnx2x_agg_info { |
436 | /* | |
e52fcb24 ED |
437 | * First aggregation buffer is a data buffer, the following - are pages. |
438 | * We will preallocate the data buffer for each aggregation when | |
619c5cb6 VZ |
439 | * we open the interface and will replace the BD at the consumer |
440 | * with this one when we receive the TPA_START CQE in order to | |
441 | * keep the Rx BD ring consistent. | |
442 | */ | |
443 | struct sw_rx_bd first_buf; | |
444 | u8 tpa_state; | |
445 | #define BNX2X_TPA_START 1 | |
446 | #define BNX2X_TPA_STOP 2 | |
447 | #define BNX2X_TPA_ERROR 3 | |
448 | u8 placement_offset; | |
449 | u16 parsing_flags; | |
450 | u16 vlan_tag; | |
451 | u16 len_on_bd; | |
e52fcb24 | 452 | u32 rxhash; |
621b4d66 DK |
453 | u16 gro_size; |
454 | u16 full_page; | |
619c5cb6 VZ |
455 | }; |
456 | ||
457 | #define Q_STATS_OFFSET32(stat_name) \ | |
458 | (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) | |
459 | ||
6383c0b3 AE |
460 | struct bnx2x_fp_txdata { |
461 | ||
462 | struct sw_tx_bd *tx_buf_ring; | |
463 | ||
464 | union eth_tx_bd_types *tx_desc_ring; | |
465 | dma_addr_t tx_desc_mapping; | |
466 | ||
467 | u32 cid; | |
468 | ||
469 | union db_prod tx_db; | |
470 | ||
471 | u16 tx_pkt_prod; | |
472 | u16 tx_pkt_cons; | |
473 | u16 tx_bd_prod; | |
474 | u16 tx_bd_cons; | |
475 | ||
476 | unsigned long tx_pkt; | |
477 | ||
478 | __le16 *tx_cons_sb; | |
479 | ||
480 | int txq_index; | |
481 | }; | |
482 | ||
621b4d66 DK |
483 | enum bnx2x_tpa_mode_t { |
484 | TPA_MODE_LRO, | |
485 | TPA_MODE_GRO | |
486 | }; | |
487 | ||
a2fbb9ea | 488 | struct bnx2x_fastpath { |
619c5cb6 | 489 | struct bnx2x *bp; /* parent */ |
a2fbb9ea | 490 | |
d6214d7a | 491 | #define BNX2X_NAPI_WEIGHT 128 |
34f80b04 | 492 | struct napi_struct napi; |
f85582f8 | 493 | union host_hc_status_block status_blk; |
523224a3 DK |
494 | /* chip independed shortcuts into sb structure */ |
495 | __le16 *sb_index_values; | |
496 | __le16 *sb_running_index; | |
497 | /* chip independed shortcut into rx_prods_offset memory */ | |
498 | u32 ustorm_rx_prods_offset; | |
499 | ||
a8c94b91 VZ |
500 | u32 rx_buf_size; |
501 | ||
34f80b04 | 502 | dma_addr_t status_blk_mapping; |
a2fbb9ea | 503 | |
621b4d66 DK |
504 | enum bnx2x_tpa_mode_t mode; |
505 | ||
6383c0b3 AE |
506 | u8 max_cos; /* actual number of active tx coses */ |
507 | struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS]; | |
a2fbb9ea | 508 | |
7a9b2557 VZ |
509 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
510 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ | |
a2fbb9ea ET |
511 | |
512 | struct eth_rx_bd *rx_desc_ring; | |
34f80b04 | 513 | dma_addr_t rx_desc_mapping; |
a2fbb9ea ET |
514 | |
515 | union eth_rx_cqe *rx_comp_ring; | |
34f80b04 EG |
516 | dma_addr_t rx_comp_mapping; |
517 | ||
7a9b2557 VZ |
518 | /* SGE ring */ |
519 | struct eth_rx_sge *rx_sge_ring; | |
520 | dma_addr_t rx_sge_mapping; | |
521 | ||
522 | u64 sge_mask[RX_SGE_MASK_LEN]; | |
523 | ||
619c5cb6 | 524 | u32 cid; |
34f80b04 | 525 | |
6383c0b3 AE |
526 | __le16 fp_hc_idx; |
527 | ||
f85582f8 | 528 | u8 index; /* number in fp array */ |
f233cafe | 529 | u8 rx_queue; /* index for skb_record */ |
f85582f8 | 530 | u8 cl_id; /* eth client id */ |
523224a3 DK |
531 | u8 cl_qzone_id; |
532 | u8 fw_sb_id; /* status block number in FW */ | |
533 | u8 igu_sb_id; /* status block number in HW */ | |
34f80b04 EG |
534 | |
535 | u16 rx_bd_prod; | |
536 | u16 rx_bd_cons; | |
537 | u16 rx_comp_prod; | |
538 | u16 rx_comp_cons; | |
7a9b2557 VZ |
539 | u16 rx_sge_prod; |
540 | /* The last maximal completed SGE */ | |
541 | u16 last_max_sge; | |
4781bfad | 542 | __le16 *rx_cons_sb; |
6383c0b3 | 543 | unsigned long rx_pkt, |
66e855f3 | 544 | rx_calls; |
ab6ad5a4 | 545 | |
7a9b2557 | 546 | /* TPA related */ |
619c5cb6 | 547 | struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; |
7a9b2557 VZ |
548 | u8 disable_tpa; |
549 | #ifdef BNX2X_STOP_ON_ERROR | |
550 | u64 tpa_queue_used; | |
551 | #endif | |
a2fbb9ea | 552 | |
619c5cb6 VZ |
553 | struct tstorm_per_queue_stats old_tclient; |
554 | struct ustorm_per_queue_stats old_uclient; | |
555 | struct xstorm_per_queue_stats old_xclient; | |
de832a55 | 556 | struct bnx2x_eth_q_stats eth_q_stats; |
1355b704 | 557 | struct bnx2x_eth_q_stats_old eth_q_stats_old; |
de832a55 | 558 | |
ca00392c EG |
559 | /* The size is calculated using the following: |
560 | sizeof name field from netdev structure + | |
561 | 4 ('-Xx-' string) + | |
562 | 4 (for the digits and to make it DWORD aligned) */ | |
563 | #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) | |
564 | char name[FP_NAME_SIZE]; | |
619c5cb6 VZ |
565 | |
566 | /* MACs object */ | |
567 | struct bnx2x_vlan_mac_obj mac_obj; | |
568 | ||
569 | /* Queue State object */ | |
570 | struct bnx2x_queue_sp_obj q_obj; | |
571 | ||
a2fbb9ea ET |
572 | }; |
573 | ||
34f80b04 | 574 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
a8c94b91 VZ |
575 | |
576 | /* Use 2500 as a mini-jumbo MTU for FCoE */ | |
577 | #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 | |
578 | ||
619c5cb6 | 579 | /* FCoE L2 `fastpath' entry is right after the eth entries */ |
ec6ba945 VZ |
580 | #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) |
581 | #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) | |
582 | #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) | |
6383c0b3 AE |
583 | #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ |
584 | txdata[FIRST_TX_COS_INDEX].var) | |
619c5cb6 VZ |
585 | |
586 | ||
6383c0b3 AE |
587 | #define IS_ETH_FP(fp) (fp->index < \ |
588 | BNX2X_NUM_ETH_QUEUES(fp->bp)) | |
619c5cb6 | 589 | #ifdef BCM_CNIC |
ec6ba945 VZ |
590 | #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) |
591 | #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) | |
592 | #else | |
593 | #define IS_FCOE_FP(fp) false | |
594 | #define IS_FCOE_IDX(idx) false | |
595 | #endif | |
7a9b2557 VZ |
596 | |
597 | ||
598 | /* MC hsi */ | |
619c5cb6 VZ |
599 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ |
600 | #define RX_COPY_THRESH 92 | |
7a9b2557 | 601 | |
619c5cb6 | 602 | #define NUM_TX_RINGS 16 |
ca00392c | 603 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
dfacf138 DK |
604 | #define NEXT_PAGE_TX_DESC_CNT 1 |
605 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) | |
619c5cb6 VZ |
606 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) |
607 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
608 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
7a9b2557 | 609 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
dfacf138 DK |
610 | (MAX_TX_DESC_CNT - 1)) ? \ |
611 | (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ | |
612 | (x) + 1) | |
619c5cb6 VZ |
613 | #define TX_BD(x) ((x) & MAX_TX_BD) |
614 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
7a9b2557 VZ |
615 | |
616 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | |
619c5cb6 | 617 | #define NUM_RX_RINGS 8 |
7a9b2557 | 618 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
dfacf138 DK |
619 | #define NEXT_PAGE_RX_DESC_CNT 2 |
620 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) | |
619c5cb6 VZ |
621 | #define RX_DESC_MASK (RX_DESC_CNT - 1) |
622 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
623 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
624 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
dfacf138 DK |
625 | |
626 | /* dropless fc calculations for BDs | |
627 | * | |
628 | * Number of BDs should as number of buffers in BRB: | |
629 | * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT | |
630 | * "next" elements on each page | |
631 | */ | |
632 | #define NUM_BD_REQ BRB_SIZE(bp) | |
633 | #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ | |
634 | MAX_RX_DESC_CNT) | |
635 | #define BD_TH_LO(bp) (NUM_BD_REQ + \ | |
636 | NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ | |
637 | FW_DROP_LEVEL(bp)) | |
638 | #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) | |
639 | ||
640 | #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) | |
619c5cb6 VZ |
641 | |
642 | #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ | |
643 | ETH_MIN_RX_CQES_WITH_TPA_E1 : \ | |
644 | ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) | |
645 | #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA | |
646 | #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) | |
647 | #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ | |
648 | MIN_RX_AVAIL)) | |
649 | ||
7a9b2557 | 650 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
dfacf138 DK |
651 | (MAX_RX_DESC_CNT - 1)) ? \ |
652 | (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ | |
653 | (x) + 1) | |
619c5cb6 | 654 | #define RX_BD(x) ((x) & MAX_RX_BD) |
7a9b2557 | 655 | |
619c5cb6 VZ |
656 | /* |
657 | * As long as CQE is X times bigger than BD entry we have to allocate X times | |
658 | * more pages for CQ ring in order to keep it balanced with BD ring | |
659 | */ | |
660 | #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) | |
661 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) | |
7a9b2557 | 662 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
dfacf138 DK |
663 | #define NEXT_PAGE_RCQ_DESC_CNT 1 |
664 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) | |
619c5cb6 VZ |
665 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) |
666 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
667 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
7a9b2557 | 668 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ |
dfacf138 DK |
669 | (MAX_RCQ_DESC_CNT - 1)) ? \ |
670 | (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ | |
671 | (x) + 1) | |
619c5cb6 | 672 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) |
7a9b2557 | 673 | |
dfacf138 DK |
674 | /* dropless fc calculations for RCQs |
675 | * | |
676 | * Number of RCQs should be as number of buffers in BRB: | |
677 | * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT | |
678 | * "next" elements on each page | |
679 | */ | |
680 | #define NUM_RCQ_REQ BRB_SIZE(bp) | |
681 | #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ | |
682 | MAX_RCQ_DESC_CNT) | |
683 | #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ | |
684 | NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ | |
685 | FW_DROP_LEVEL(bp)) | |
686 | #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) | |
687 | ||
7a9b2557 | 688 | |
33471629 | 689 | /* This is needed for determining of last_max */ |
619c5cb6 VZ |
690 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
691 | #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) | |
7a9b2557 | 692 | |
7a9b2557 | 693 | |
619c5cb6 VZ |
694 | #define BNX2X_SWCID_SHIFT 17 |
695 | #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) | |
7a9b2557 VZ |
696 | |
697 | /* used on a CID received from the HW */ | |
619c5cb6 | 698 | #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) |
7a9b2557 VZ |
699 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ |
700 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
701 | ||
bb2a0f7a YG |
702 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
703 | le32_to_cpu((bd)->addr_lo)) | |
704 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
705 | ||
523224a3 DK |
706 | #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ |
707 | #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ | |
619c5cb6 VZ |
708 | #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) |
709 | #error "Min DB doorbell stride is 8" | |
710 | #endif | |
7a9b2557 VZ |
711 | #define DPM_TRIGER_TYPE 0x40 |
712 | #define DOORBELL(bp, cid, val) \ | |
713 | do { \ | |
523224a3 | 714 | writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ |
7a9b2557 VZ |
715 | DPM_TRIGER_TYPE); \ |
716 | } while (0) | |
717 | ||
718 | ||
719 | /* TX CSUM helpers */ | |
720 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ | |
721 | skb->csum_offset) | |
722 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | |
723 | skb->csum_offset)) | |
724 | ||
725 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | |
726 | ||
727 | #define XMIT_PLAIN 0 | |
728 | #define XMIT_CSUM_V4 0x1 | |
729 | #define XMIT_CSUM_V6 0x2 | |
730 | #define XMIT_CSUM_TCP 0x4 | |
731 | #define XMIT_GSO_V4 0x8 | |
732 | #define XMIT_GSO_V6 0x10 | |
733 | ||
734 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) | |
735 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) | |
736 | ||
737 | ||
34f80b04 | 738 | /* stuff added to make the code fit 80Col */ |
619c5cb6 VZ |
739 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
740 | #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) | |
741 | #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) | |
742 | #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) | |
743 | #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) | |
7a9b2557 | 744 | |
1adcd8be EG |
745 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
746 | ||
747 | #define BNX2X_IP_CSUM_ERR(cqe) \ | |
748 | (!((cqe)->fast_path_cqe.status_flags & \ | |
749 | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ | |
750 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
751 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) | |
752 | ||
753 | #define BNX2X_L4_CSUM_ERR(cqe) \ | |
754 | (!((cqe)->fast_path_cqe.status_flags & \ | |
755 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ | |
756 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
757 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) | |
758 | ||
759 | #define BNX2X_RX_CSUM_OK(cqe) \ | |
760 | (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) | |
7a9b2557 | 761 | |
052a38e0 EG |
762 | #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ |
763 | (((le16_to_cpu(flags) & \ | |
764 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ | |
765 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ | |
766 | == PRS_FLAG_OVERETH_IPV4) | |
7a9b2557 | 767 | #define BNX2X_RX_SUM_FIX(cqe) \ |
052a38e0 | 768 | BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) |
7a9b2557 | 769 | |
619c5cb6 VZ |
770 | |
771 | #define FP_USB_FUNC_OFF \ | |
772 | offsetof(struct cstorm_status_block_u, func) | |
773 | #define FP_CSB_FUNC_OFF \ | |
774 | offsetof(struct cstorm_status_block_c, func) | |
775 | ||
150966ad | 776 | #define HC_INDEX_ETH_RX_CQ_CONS 1 |
619c5cb6 | 777 | |
150966ad | 778 | #define HC_INDEX_OOO_TX_CQ_CONS 4 |
6383c0b3 | 779 | |
150966ad AE |
780 | #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 |
781 | ||
782 | #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 | |
6383c0b3 | 783 | |
150966ad AE |
784 | #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 |
785 | ||
786 | #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 | |
a2fbb9ea | 787 | |
34f80b04 | 788 | #define BNX2X_RX_SB_INDEX \ |
619c5cb6 | 789 | (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) |
a2fbb9ea | 790 | |
6383c0b3 AE |
791 | #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 |
792 | ||
793 | #define BNX2X_TX_SB_INDEX_COS0 \ | |
794 | (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) | |
7a9b2557 VZ |
795 | |
796 | /* end of fast path */ | |
797 | ||
34f80b04 | 798 | /* common */ |
a2fbb9ea | 799 | |
34f80b04 | 800 | struct bnx2x_common { |
a2fbb9ea | 801 | |
ad8d3948 | 802 | u32 chip_id; |
a2fbb9ea | 803 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
34f80b04 | 804 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
ad8d3948 | 805 | |
34f80b04 | 806 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
ad8d3948 EG |
807 | #define CHIP_NUM_57710 0x164e |
808 | #define CHIP_NUM_57711 0x164f | |
809 | #define CHIP_NUM_57711E 0x1650 | |
f2e0899f | 810 | #define CHIP_NUM_57712 0x1662 |
619c5cb6 VZ |
811 | #define CHIP_NUM_57712_MF 0x1663 |
812 | #define CHIP_NUM_57713 0x1651 | |
813 | #define CHIP_NUM_57713E 0x1652 | |
814 | #define CHIP_NUM_57800 0x168a | |
815 | #define CHIP_NUM_57800_MF 0x16a5 | |
816 | #define CHIP_NUM_57810 0x168e | |
817 | #define CHIP_NUM_57810_MF 0x16ae | |
818 | #define CHIP_NUM_57840 0x168d | |
819 | #define CHIP_NUM_57840_MF 0x16ab | |
ad8d3948 EG |
820 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) |
821 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
822 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
f2e0899f | 823 | #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) |
619c5cb6 VZ |
824 | #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) |
825 | #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) | |
826 | #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) | |
827 | #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) | |
828 | #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) | |
829 | #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840) | |
830 | #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF) | |
ad8d3948 EG |
831 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ |
832 | CHIP_IS_57711E(bp)) | |
f2e0899f | 833 | #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ |
619c5cb6 VZ |
834 | CHIP_IS_57712_MF(bp)) |
835 | #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ | |
836 | CHIP_IS_57800_MF(bp) || \ | |
837 | CHIP_IS_57810(bp) || \ | |
838 | CHIP_IS_57810_MF(bp) || \ | |
839 | CHIP_IS_57840(bp) || \ | |
840 | CHIP_IS_57840_MF(bp)) | |
f2e0899f | 841 | #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) |
619c5cb6 VZ |
842 | #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) |
843 | #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) | |
844 | ||
845 | #define CHIP_REV_SHIFT 12 | |
846 | #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) | |
847 | #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) | |
848 | #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) | |
849 | #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) | |
ad8d3948 | 850 | /* assume maximum 5 revisions */ |
619c5cb6 | 851 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) |
ad8d3948 EG |
852 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ |
853 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
619c5cb6 | 854 | !(CHIP_REV_VAL(bp) & 0x00001000)) |
ad8d3948 EG |
855 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ |
856 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
619c5cb6 | 857 | (CHIP_REV_VAL(bp) & 0x00001000)) |
ad8d3948 EG |
858 | |
859 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
860 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
861 | ||
34f80b04 EG |
862 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
863 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
619c5cb6 VZ |
864 | #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ |
865 | (CHIP_REV_SHIFT + 1)) \ | |
866 | << CHIP_REV_SHIFT) | |
867 | #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ | |
868 | CHIP_REV_SIM(bp) :\ | |
869 | CHIP_REV_VAL(bp)) | |
870 | #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ | |
871 | (CHIP_REV(bp) == CHIP_REV_Bx)) | |
872 | #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ | |
873 | (CHIP_REV(bp) == CHIP_REV_Ax)) | |
a2fbb9ea | 874 | |
34f80b04 | 875 | int flash_size; |
754a2f52 DK |
876 | #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ |
877 | #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 | |
878 | #define BNX2X_NVRAM_PAGE_SIZE 256 | |
a2fbb9ea | 879 | |
34f80b04 | 880 | u32 shmem_base; |
2691d51d | 881 | u32 shmem2_base; |
523224a3 | 882 | u32 mf_cfg_base; |
f2e0899f | 883 | u32 mf2_cfg_base; |
34f80b04 EG |
884 | |
885 | u32 hw_config; | |
c18487ee | 886 | |
34f80b04 | 887 | u32 bc_ver; |
523224a3 DK |
888 | |
889 | u8 int_block; | |
890 | #define INT_BLOCK_HC 0 | |
f2e0899f DK |
891 | #define INT_BLOCK_IGU 1 |
892 | #define INT_BLOCK_MODE_NORMAL 0 | |
893 | #define INT_BLOCK_MODE_BW_COMP 2 | |
894 | #define CHIP_INT_MODE_IS_NBC(bp) \ | |
619c5cb6 | 895 | (!CHIP_IS_E1x(bp) && \ |
f2e0899f DK |
896 | !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) |
897 | #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) | |
898 | ||
523224a3 | 899 | u8 chip_port_mode; |
f2e0899f DK |
900 | #define CHIP_4_PORT_MODE 0x0 |
901 | #define CHIP_2_PORT_MODE 0x1 | |
523224a3 | 902 | #define CHIP_PORT_MODE_NONE 0x2 |
f2e0899f DK |
903 | #define CHIP_MODE(bp) (bp->common.chip_port_mode) |
904 | #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) | |
1d187b34 BW |
905 | |
906 | u32 boot_mode; | |
34f80b04 | 907 | }; |
c18487ee | 908 | |
f2e0899f DK |
909 | /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ |
910 | #define BNX2X_IGU_STAS_MSG_VF_CNT 64 | |
911 | #define BNX2X_IGU_STAS_MSG_PF_CNT 4 | |
34f80b04 EG |
912 | |
913 | /* end of common */ | |
914 | ||
915 | /* port */ | |
916 | ||
917 | struct bnx2x_port { | |
918 | u32 pmf; | |
c18487ee | 919 | |
a22f0788 | 920 | u32 link_config[LINK_CONFIG_SIZE]; |
a2fbb9ea | 921 | |
a22f0788 | 922 | u32 supported[LINK_CONFIG_SIZE]; |
34f80b04 EG |
923 | /* link settings - missing defines */ |
924 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
925 | ||
a22f0788 | 926 | u32 advertising[LINK_CONFIG_SIZE]; |
a2fbb9ea | 927 | /* link settings - missing defines */ |
34f80b04 | 928 | #define ADVERTISED_2500baseX_Full (1 << 15) |
a2fbb9ea | 929 | |
34f80b04 | 930 | u32 phy_addr; |
c18487ee YR |
931 | |
932 | /* used to synchronize phy accesses */ | |
933 | struct mutex phy_mutex; | |
46c6a674 | 934 | int need_hw_lock; |
c18487ee | 935 | |
34f80b04 | 936 | u32 port_stx; |
a2fbb9ea | 937 | |
34f80b04 EG |
938 | struct nig_stats old_nig_stats; |
939 | }; | |
a2fbb9ea | 940 | |
34f80b04 EG |
941 | /* end of port */ |
942 | ||
619c5cb6 VZ |
943 | #define STATS_OFFSET32(stat_name) \ |
944 | (offsetof(struct bnx2x_eth_stats, stat_name) / 4) | |
bb2a0f7a | 945 | |
619c5cb6 VZ |
946 | /* slow path */ |
947 | ||
948 | /* slow path work-queue */ | |
949 | extern struct workqueue_struct *bnx2x_wq; | |
950 | ||
951 | #define BNX2X_MAX_NUM_OF_VFS 64 | |
523224a3 | 952 | #define BNX2X_VF_ID_INVALID 0xFF |
34f80b04 | 953 | |
523224a3 DK |
954 | /* |
955 | * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is | |
956 | * control by the number of fast-path status blocks supported by the | |
957 | * device (HW/FW). Each fast-path status block (FP-SB) aka non-default | |
958 | * status block represents an independent interrupts context that can | |
959 | * serve a regular L2 networking queue. However special L2 queues such | |
960 | * as the FCoE queue do not require a FP-SB and other components like | |
961 | * the CNIC may consume FP-SB reducing the number of possible L2 queues | |
962 | * | |
963 | * If the maximum number of FP-SB available is X then: | |
964 | * a. If CNIC is supported it consumes 1 FP-SB thus the max number of | |
965 | * regular L2 queues is Y=X-1 | |
966 | * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) | |
967 | * c. If the FCoE L2 queue is supported the actual number of L2 queues | |
968 | * is Y+1 | |
969 | * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for | |
970 | * slow-path interrupts) or Y+2 if CNIC is supported (one additional | |
971 | * FP interrupt context for the CNIC). | |
972 | * e. The number of HW context (CID count) is always X or X+1 if FCoE | |
973 | * L2 queue is supported. the cid for the FCoE L2 queue is always X. | |
974 | */ | |
975 | ||
619c5cb6 VZ |
976 | /* fast-path interrupt contexts E1x */ |
977 | #define FP_SB_MAX_E1x 16 | |
978 | /* fast-path interrupt contexts E2 */ | |
979 | #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 | |
523224a3 | 980 | |
34f80b04 EG |
981 | union cdu_context { |
982 | struct eth_context eth; | |
983 | char pad[1024]; | |
984 | }; | |
985 | ||
523224a3 DK |
986 | /* CDU host DB constants */ |
987 | #define CDU_ILT_PAGE_SZ_HW 3 | |
6383c0b3 | 988 | #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */ |
523224a3 DK |
989 | #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) |
990 | ||
991 | #ifdef BCM_CNIC | |
992 | #define CNIC_ISCSI_CID_MAX 256 | |
ec6ba945 VZ |
993 | #define CNIC_FCOE_CID_MAX 2048 |
994 | #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) | |
523224a3 DK |
995 | #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) |
996 | #endif | |
997 | ||
619c5cb6 VZ |
998 | #define QM_ILT_PAGE_SZ_HW 0 |
999 | #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
1000 | #define QM_CID_ROUND 1024 |
1001 | ||
1002 | #ifdef BCM_CNIC | |
1003 | /* TM (timers) host DB constants */ | |
619c5cb6 VZ |
1004 | #define TM_ILT_PAGE_SZ_HW 0 |
1005 | #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
1006 | /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ |
1007 | #define TM_CONN_NUM 1024 | |
1008 | #define TM_ILT_SZ (8 * TM_CONN_NUM) | |
1009 | #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) | |
1010 | ||
1011 | /* SRC (Searcher) host DB constants */ | |
619c5cb6 VZ |
1012 | #define SRC_ILT_PAGE_SZ_HW 0 |
1013 | #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
1014 | #define SRC_HASH_BITS 10 |
1015 | #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ | |
1016 | #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) | |
1017 | #define SRC_T2_SZ SRC_ILT_SZ | |
1018 | #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) | |
619c5cb6 | 1019 | |
523224a3 DK |
1020 | #endif |
1021 | ||
619c5cb6 | 1022 | #define MAX_DMAE_C 8 |
34f80b04 EG |
1023 | |
1024 | /* DMA memory not used in fastpath */ | |
1025 | struct bnx2x_slowpath { | |
619c5cb6 VZ |
1026 | union { |
1027 | struct mac_configuration_cmd e1x; | |
1028 | struct eth_classify_rules_ramrod_data e2; | |
1029 | } mac_rdata; | |
1030 | ||
1031 | ||
1032 | union { | |
1033 | struct tstorm_eth_mac_filter_config e1x; | |
1034 | struct eth_filter_rules_ramrod_data e2; | |
1035 | } rx_mode_rdata; | |
1036 | ||
1037 | union { | |
1038 | struct mac_configuration_cmd e1; | |
1039 | struct eth_multicast_rules_ramrod_data e2; | |
1040 | } mcast_rdata; | |
1041 | ||
1042 | struct eth_rss_update_ramrod_data rss_rdata; | |
1043 | ||
1044 | /* Queue State related ramrods are always sent under rtnl_lock */ | |
1045 | union { | |
1046 | struct client_init_ramrod_data init_data; | |
1047 | struct client_update_ramrod_data update_data; | |
1048 | } q_rdata; | |
1049 | ||
1050 | union { | |
1051 | struct function_start_data func_start; | |
6debea87 DK |
1052 | /* pfc configuration for DCBX ramrod */ |
1053 | struct flow_control_configuration pfc_config; | |
619c5cb6 | 1054 | } func_rdata; |
34f80b04 EG |
1055 | |
1056 | /* used by dmae command executer */ | |
1057 | struct dmae_command dmae[MAX_DMAE_C]; | |
1058 | ||
bb2a0f7a YG |
1059 | u32 stats_comp; |
1060 | union mac_stats mac_stats; | |
1061 | struct nig_stats nig_stats; | |
1062 | struct host_port_stats port_stats; | |
1063 | struct host_func_stats func_stats; | |
34f80b04 EG |
1064 | |
1065 | u32 wb_comp; | |
34f80b04 | 1066 | u32 wb_data[4]; |
1d187b34 BW |
1067 | |
1068 | union drv_info_to_mcp drv_info_to_mcp; | |
34f80b04 EG |
1069 | }; |
1070 | ||
1071 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
1072 | #define bnx2x_sp_mapping(bp, var) \ | |
1073 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
1074 | ||
1075 | ||
1076 | /* attn group wiring */ | |
1077 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
1078 | ||
1079 | struct attn_route { | |
619c5cb6 | 1080 | u32 sig[5]; |
34f80b04 EG |
1081 | }; |
1082 | ||
523224a3 DK |
1083 | struct iro { |
1084 | u32 base; | |
1085 | u16 m1; | |
1086 | u16 m2; | |
1087 | u16 m3; | |
1088 | u16 size; | |
1089 | }; | |
1090 | ||
1091 | struct hw_context { | |
1092 | union cdu_context *vcxt; | |
1093 | dma_addr_t cxt_mapping; | |
1094 | size_t size; | |
1095 | }; | |
1096 | ||
1097 | /* forward */ | |
1098 | struct bnx2x_ilt; | |
1099 | ||
c9ee9206 VZ |
1100 | |
1101 | enum bnx2x_recovery_state { | |
72fd0718 VZ |
1102 | BNX2X_RECOVERY_DONE, |
1103 | BNX2X_RECOVERY_INIT, | |
1104 | BNX2X_RECOVERY_WAIT, | |
95c6c616 AE |
1105 | BNX2X_RECOVERY_FAILED, |
1106 | BNX2X_RECOVERY_NIC_LOADING | |
c9ee9206 | 1107 | }; |
72fd0718 | 1108 | |
619c5cb6 | 1109 | /* |
523224a3 DK |
1110 | * Event queue (EQ or event ring) MC hsi |
1111 | * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 | |
1112 | */ | |
1113 | #define NUM_EQ_PAGES 1 | |
1114 | #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) | |
1115 | #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) | |
1116 | #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) | |
1117 | #define EQ_DESC_MASK (NUM_EQ_DESC - 1) | |
1118 | #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) | |
1119 | ||
1120 | /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ | |
1121 | #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ | |
1122 | (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) | |
1123 | ||
1124 | /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ | |
1125 | #define EQ_DESC(x) ((x) & EQ_DESC_MASK) | |
1126 | ||
1127 | #define BNX2X_EQ_INDEX \ | |
1128 | (&bp->def_status_blk->sp_sb.\ | |
1129 | index_values[HC_SP_INDEX_EQ_CONS]) | |
1130 | ||
2ae17f66 VZ |
1131 | /* This is a data that will be used to create a link report message. |
1132 | * We will keep the data used for the last link report in order | |
1133 | * to prevent reporting the same link parameters twice. | |
1134 | */ | |
1135 | struct bnx2x_link_report_data { | |
1136 | u16 line_speed; /* Effective line speed */ | |
1137 | unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ | |
1138 | }; | |
1139 | ||
1140 | enum { | |
1141 | BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ | |
1142 | BNX2X_LINK_REPORT_LINK_DOWN, | |
1143 | BNX2X_LINK_REPORT_RX_FC_ON, | |
1144 | BNX2X_LINK_REPORT_TX_FC_ON, | |
1145 | }; | |
1146 | ||
619c5cb6 VZ |
1147 | enum { |
1148 | BNX2X_PORT_QUERY_IDX, | |
1149 | BNX2X_PF_QUERY_IDX, | |
50f0a562 | 1150 | BNX2X_FCOE_QUERY_IDX, |
619c5cb6 VZ |
1151 | BNX2X_FIRST_QUEUE_QUERY_IDX, |
1152 | }; | |
1153 | ||
1154 | struct bnx2x_fw_stats_req { | |
1155 | struct stats_query_header hdr; | |
50f0a562 BW |
1156 | struct stats_query_entry query[FP_SB_MAX_E1x+ |
1157 | BNX2X_FIRST_QUEUE_QUERY_IDX]; | |
619c5cb6 VZ |
1158 | }; |
1159 | ||
1160 | struct bnx2x_fw_stats_data { | |
1161 | struct stats_counter storm_counters; | |
1162 | struct per_port_stats port; | |
1163 | struct per_pf_stats pf; | |
50f0a562 | 1164 | struct fcoe_statistics_params fcoe; |
619c5cb6 VZ |
1165 | struct per_queue_stats queue_stats[1]; |
1166 | }; | |
1167 | ||
7be08a72 AE |
1168 | /* Public slow path states */ |
1169 | enum { | |
6383c0b3 | 1170 | BNX2X_SP_RTNL_SETUP_TC, |
7be08a72 | 1171 | BNX2X_SP_RTNL_TX_TIMEOUT, |
8304859a | 1172 | BNX2X_SP_RTNL_FAN_FAILURE, |
7be08a72 AE |
1173 | }; |
1174 | ||
1175 | ||
34f80b04 EG |
1176 | struct bnx2x { |
1177 | /* Fields used in the tx and intr/napi performance paths | |
1178 | * are grouped together in the beginning of the structure | |
1179 | */ | |
523224a3 | 1180 | struct bnx2x_fastpath *fp; |
34f80b04 EG |
1181 | void __iomem *regview; |
1182 | void __iomem *doorbells; | |
523224a3 | 1183 | u16 db_size; |
34f80b04 | 1184 | |
619c5cb6 VZ |
1185 | u8 pf_num; /* absolute PF number */ |
1186 | u8 pfid; /* per-path PF number */ | |
1187 | int base_fw_ndsb; /**/ | |
1188 | #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) | |
1189 | #define BP_PORT(bp) (bp->pfid & 1) | |
1190 | #define BP_FUNC(bp) (bp->pfid) | |
1191 | #define BP_ABS_FUNC(bp) (bp->pf_num) | |
3395a033 DK |
1192 | #define BP_VN(bp) ((bp)->pfid >> 1) |
1193 | #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) | |
1194 | #define BP_L_ID(bp) (BP_VN(bp) << 2) | |
1195 | #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ | |
1196 | (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) | |
1197 | #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) | |
619c5cb6 | 1198 | |
34f80b04 EG |
1199 | struct net_device *dev; |
1200 | struct pci_dev *pdev; | |
1201 | ||
619c5cb6 | 1202 | const struct iro *iro_arr; |
523224a3 DK |
1203 | #define IRO (bp->iro_arr) |
1204 | ||
c9ee9206 | 1205 | enum bnx2x_recovery_state recovery_state; |
72fd0718 | 1206 | int is_leader; |
523224a3 | 1207 | struct msix_entry *msix_table; |
34f80b04 EG |
1208 | |
1209 | int tx_ring_size; | |
1210 | ||
523224a3 DK |
1211 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
1212 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
34f80b04 EG |
1213 | #define ETH_MIN_PACKET_SIZE 60 |
1214 | #define ETH_MAX_PACKET_SIZE 1500 | |
1215 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
621b4d66 DK |
1216 | /* TCP with Timestamp Option (32) + IPv6 (40) */ |
1217 | #define ETH_MAX_TPA_HEADER_SIZE 72 | |
fe603b4d | 1218 | #define ETH_MIN_TPA_HEADER_SIZE 40 |
a2fbb9ea | 1219 | |
0f00846d | 1220 | /* Max supported alignment is 256 (8 shift) */ |
e52fcb24 ED |
1221 | #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) |
1222 | ||
1223 | /* FW uses 2 Cache lines Alignment for start packet and size | |
1224 | * | |
1225 | * We assume skb_build() uses sizeof(struct skb_shared_info) bytes | |
1226 | * at the end of skb->data, to avoid wasting a full cache line. | |
1227 | * This reduces memory use (skb->truesize). | |
1228 | */ | |
1229 | #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) | |
1230 | ||
1231 | #define BNX2X_FW_RX_ALIGN_END \ | |
1232 | max(1UL << BNX2X_RX_ALIGN_SHIFT, \ | |
1233 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1234 | ||
523224a3 | 1235 | #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) |
0f00846d | 1236 | |
523224a3 DK |
1237 | struct host_sp_status_block *def_status_blk; |
1238 | #define DEF_SB_IGU_ID 16 | |
1239 | #define DEF_SB_ID HC_SP_SB_ID | |
1240 | __le16 def_idx; | |
4781bfad | 1241 | __le16 def_att_idx; |
34f80b04 EG |
1242 | u32 attn_state; |
1243 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
34f80b04 EG |
1244 | |
1245 | /* slow path ring */ | |
1246 | struct eth_spe *spq; | |
1247 | dma_addr_t spq_mapping; | |
1248 | u16 spq_prod_idx; | |
1249 | struct eth_spe *spq_prod_bd; | |
1250 | struct eth_spe *spq_last_bd; | |
4781bfad | 1251 | __le16 *dsb_sp_prod; |
6e30dd4e | 1252 | atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ |
34f80b04 EG |
1253 | /* used to synchronize spq accesses */ |
1254 | spinlock_t spq_lock; | |
1255 | ||
523224a3 DK |
1256 | /* event queue */ |
1257 | union event_ring_elem *eq_ring; | |
1258 | dma_addr_t eq_mapping; | |
1259 | u16 eq_prod; | |
1260 | u16 eq_cons; | |
1261 | __le16 *eq_cons_sb; | |
6e30dd4e | 1262 | atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ |
523224a3 | 1263 | |
619c5cb6 VZ |
1264 | |
1265 | ||
1266 | /* Counter for marking that there is a STAT_QUERY ramrod pending */ | |
1267 | u16 stats_pending; | |
1268 | /* Counter for completed statistics ramrods */ | |
1269 | u16 stats_comp; | |
34f80b04 | 1270 | |
33471629 | 1271 | /* End of fields used in the performance code paths */ |
34f80b04 EG |
1272 | |
1273 | int panic; | |
7995c64e | 1274 | int msg_enable; |
34f80b04 EG |
1275 | |
1276 | u32 flags; | |
619c5cb6 VZ |
1277 | #define PCIX_FLAG (1 << 0) |
1278 | #define PCI_32BIT_FLAG (1 << 1) | |
1279 | #define ONE_PORT_FLAG (1 << 2) | |
1280 | #define NO_WOL_FLAG (1 << 3) | |
1281 | #define USING_DAC_FLAG (1 << 4) | |
1282 | #define USING_MSIX_FLAG (1 << 5) | |
1283 | #define USING_MSI_FLAG (1 << 6) | |
1284 | #define DISABLE_MSI_FLAG (1 << 7) | |
1285 | #define TPA_ENABLE_FLAG (1 << 8) | |
1286 | #define NO_MCP_FLAG (1 << 9) | |
1287 | ||
34f80b04 | 1288 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) |
621b4d66 | 1289 | #define GRO_ENABLE_FLAG (1 << 10) |
619c5cb6 VZ |
1290 | #define MF_FUNC_DIS (1 << 11) |
1291 | #define OWN_CNIC_IRQ (1 << 12) | |
1292 | #define NO_ISCSI_OOO_FLAG (1 << 13) | |
1293 | #define NO_ISCSI_FLAG (1 << 14) | |
1294 | #define NO_FCOE_FLAG (1 << 15) | |
0e898dd7 | 1295 | #define BC_SUPPORTS_PFC_STATS (1 << 17) |
ec6ba945 | 1296 | |
2ba45142 VZ |
1297 | #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) |
1298 | #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) | |
619c5cb6 | 1299 | #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) |
37b091ba | 1300 | |
34f80b04 | 1301 | int pm_cap; |
8d5726c4 | 1302 | int mrrs; |
34f80b04 | 1303 | |
1cf167f2 | 1304 | struct delayed_work sp_task; |
7be08a72 | 1305 | struct delayed_work sp_rtnl_task; |
3deb8167 YR |
1306 | |
1307 | struct delayed_work period_task; | |
34f80b04 | 1308 | struct timer_list timer; |
34f80b04 EG |
1309 | int current_interval; |
1310 | ||
1311 | u16 fw_seq; | |
1312 | u16 fw_drv_pulse_wr_seq; | |
1313 | u32 func_stx; | |
1314 | ||
1315 | struct link_params link_params; | |
1316 | struct link_vars link_vars; | |
2ae17f66 VZ |
1317 | u32 link_cnt; |
1318 | struct bnx2x_link_report_data last_reported_link; | |
1319 | ||
01cd4528 | 1320 | struct mdio_if_info mdio; |
a2fbb9ea | 1321 | |
34f80b04 EG |
1322 | struct bnx2x_common common; |
1323 | struct bnx2x_port port; | |
1324 | ||
8a1c38d1 EG |
1325 | struct cmng_struct_per_port cmng; |
1326 | u32 vn_weight_sum; | |
f2e0899f DK |
1327 | u32 mf_config[E1HVN_MAX]; |
1328 | u32 mf2_config[E2_FUNC_MAX]; | |
619c5cb6 | 1329 | u32 path_has_ovlan; /* E3 */ |
fb3bff17 DK |
1330 | u16 mf_ov; |
1331 | u8 mf_mode; | |
f85582f8 | 1332 | #define IS_MF(bp) (bp->mf_mode != 0) |
0793f83f DK |
1333 | #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) |
1334 | #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) | |
a2fbb9ea | 1335 | |
f1410647 ET |
1336 | u8 wol; |
1337 | ||
fe603b4d DK |
1338 | bool gro_check; |
1339 | ||
34f80b04 | 1340 | int rx_ring_size; |
a2fbb9ea | 1341 | |
34f80b04 EG |
1342 | u16 tx_quick_cons_trip_int; |
1343 | u16 tx_quick_cons_trip; | |
1344 | u16 tx_ticks_int; | |
1345 | u16 tx_ticks; | |
a2fbb9ea | 1346 | |
34f80b04 EG |
1347 | u16 rx_quick_cons_trip_int; |
1348 | u16 rx_quick_cons_trip; | |
1349 | u16 rx_ticks_int; | |
1350 | u16 rx_ticks; | |
cdaa7cb8 VZ |
1351 | /* Maximal coalescing timeout in us */ |
1352 | #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) | |
a2fbb9ea | 1353 | |
34f80b04 | 1354 | u32 lin_cnt; |
a2fbb9ea | 1355 | |
619c5cb6 | 1356 | u16 state; |
356e2385 | 1357 | #define BNX2X_STATE_CLOSED 0 |
34f80b04 EG |
1358 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
1359 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
a2fbb9ea | 1360 | #define BNX2X_STATE_OPEN 0x3000 |
34f80b04 | 1361 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
a2fbb9ea | 1362 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
619c5cb6 | 1363 | |
34f80b04 EG |
1364 | #define BNX2X_STATE_DIAG 0xe000 |
1365 | #define BNX2X_STATE_ERROR 0xf000 | |
a2fbb9ea | 1366 | |
555f6c78 | 1367 | int multi_mode; |
6383c0b3 AE |
1368 | #define BNX2X_MAX_PRIORITY 8 |
1369 | #define BNX2X_MAX_ENTRIES_PER_PRI 16 | |
1370 | #define BNX2X_MAX_COS 3 | |
1371 | #define BNX2X_MAX_TX_COS 2 | |
54b9ddaa | 1372 | int num_queues; |
5d7cd496 | 1373 | int disable_tpa; |
523224a3 | 1374 | |
34f80b04 EG |
1375 | u32 rx_mode; |
1376 | #define BNX2X_RX_MODE_NONE 0 | |
1377 | #define BNX2X_RX_MODE_NORMAL 1 | |
1378 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
1379 | #define BNX2X_RX_MODE_PROMISC 3 | |
1380 | #define BNX2X_MAX_MULTICAST 64 | |
a2fbb9ea | 1381 | |
523224a3 DK |
1382 | u8 igu_dsb_id; |
1383 | u8 igu_base_sb; | |
1384 | u8 igu_sb_cnt; | |
34f80b04 | 1385 | dma_addr_t def_status_blk_mapping; |
a2fbb9ea | 1386 | |
34f80b04 EG |
1387 | struct bnx2x_slowpath *slowpath; |
1388 | dma_addr_t slowpath_mapping; | |
619c5cb6 VZ |
1389 | |
1390 | /* Total number of FW statistics requests */ | |
1391 | u8 fw_stats_num; | |
1392 | ||
1393 | /* | |
1394 | * This is a memory buffer that will contain both statistics | |
1395 | * ramrod request and data. | |
1396 | */ | |
1397 | void *fw_stats; | |
1398 | dma_addr_t fw_stats_mapping; | |
1399 | ||
1400 | /* | |
1401 | * FW statistics request shortcut (points at the | |
1402 | * beginning of fw_stats buffer). | |
1403 | */ | |
1404 | struct bnx2x_fw_stats_req *fw_stats_req; | |
1405 | dma_addr_t fw_stats_req_mapping; | |
1406 | int fw_stats_req_sz; | |
1407 | ||
1408 | /* | |
1409 | * FW statistics data shortcut (points at the begining of | |
1410 | * fw_stats buffer + fw_stats_req_sz). | |
1411 | */ | |
1412 | struct bnx2x_fw_stats_data *fw_stats_data; | |
1413 | dma_addr_t fw_stats_data_mapping; | |
1414 | int fw_stats_data_sz; | |
1415 | ||
523224a3 DK |
1416 | struct hw_context context; |
1417 | ||
1418 | struct bnx2x_ilt *ilt; | |
1419 | #define BP_ILT(bp) ((bp)->ilt) | |
619c5cb6 | 1420 | #define ILT_MAX_LINES 256 |
6383c0b3 AE |
1421 | /* |
1422 | * Maximum supported number of RSS queues: number of IGU SBs minus one that goes | |
1423 | * to CNIC. | |
1424 | */ | |
1425 | #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT) | |
523224a3 | 1426 | |
6383c0b3 AE |
1427 | /* |
1428 | * Maximum CID count that might be required by the bnx2x: | |
1429 | * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related) | |
1430 | */ | |
1431 | #define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\ | |
1432 | NON_ETH_CONTEXT_USE + CNIC_PRESENT) | |
1433 | #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ | |
1434 | ILT_PAGE_CIDS)) | |
1435 | #define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT)) | |
523224a3 DK |
1436 | |
1437 | int qm_cid_count; | |
a2fbb9ea | 1438 | |
a18f5128 EG |
1439 | int dropless_fc; |
1440 | ||
37b091ba MC |
1441 | #ifdef BCM_CNIC |
1442 | u32 cnic_flags; | |
1443 | #define BNX2X_CNIC_FLAG_MAC_SET 1 | |
37b091ba MC |
1444 | void *t2; |
1445 | dma_addr_t t2_mapping; | |
13707f9e | 1446 | struct cnic_ops __rcu *cnic_ops; |
37b091ba MC |
1447 | void *cnic_data; |
1448 | u32 cnic_tag; | |
1449 | struct cnic_eth_dev cnic_eth_dev; | |
523224a3 | 1450 | union host_hc_status_block cnic_sb; |
37b091ba | 1451 | dma_addr_t cnic_sb_mapping; |
37b091ba MC |
1452 | struct eth_spe *cnic_kwq; |
1453 | struct eth_spe *cnic_kwq_prod; | |
1454 | struct eth_spe *cnic_kwq_cons; | |
1455 | struct eth_spe *cnic_kwq_last; | |
1456 | u16 cnic_kwq_pending; | |
1457 | u16 cnic_spq_pending; | |
ec6ba945 | 1458 | u8 fip_mac[ETH_ALEN]; |
619c5cb6 VZ |
1459 | struct mutex cnic_mutex; |
1460 | struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; | |
1461 | ||
1462 | /* Start index of the "special" (CNIC related) L2 cleints */ | |
1463 | u8 cnic_base_cl_id; | |
37b091ba MC |
1464 | #endif |
1465 | ||
ad8d3948 EG |
1466 | int dmae_ready; |
1467 | /* used to synchronize dmae accesses */ | |
6e30dd4e | 1468 | spinlock_t dmae_lock; |
ad8d3948 | 1469 | |
c4ff7cbf EG |
1470 | /* used to protect the FW mail box */ |
1471 | struct mutex fw_mb_mutex; | |
1472 | ||
bb2a0f7a YG |
1473 | /* used to synchronize stats collecting */ |
1474 | int stats_state; | |
a13773a5 VZ |
1475 | |
1476 | /* used for synchronization of concurrent threads statistics handling */ | |
1477 | spinlock_t stats_lock; | |
1478 | ||
bb2a0f7a YG |
1479 | /* used by dmae command loader */ |
1480 | struct dmae_command stats_dmae; | |
1481 | int executer_idx; | |
ad8d3948 | 1482 | |
bb2a0f7a | 1483 | u16 stats_counter; |
bb2a0f7a | 1484 | struct bnx2x_eth_stats eth_stats; |
1355b704 MY |
1485 | struct bnx2x_eth_stats_old eth_stats_old; |
1486 | struct bnx2x_net_stats_old net_stats_old; | |
1487 | struct bnx2x_fw_port_stats_old fw_stats_old; | |
1488 | bool stats_init; | |
bb2a0f7a YG |
1489 | |
1490 | struct z_stream_s *strm; | |
1491 | void *gunzip_buf; | |
1492 | dma_addr_t gunzip_mapping; | |
1493 | int gunzip_outlen; | |
ad8d3948 | 1494 | #define FW_BUF_SIZE 0x8000 |
573f2035 EG |
1495 | #define GUNZIP_BUF(bp) (bp->gunzip_buf) |
1496 | #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) | |
1497 | #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) | |
a2fbb9ea | 1498 | |
ab6ad5a4 | 1499 | struct raw_op *init_ops; |
94a78b79 | 1500 | /* Init blocks offsets inside init_ops */ |
ab6ad5a4 | 1501 | u16 *init_ops_offsets; |
94a78b79 | 1502 | /* Data blob - has 32 bit granularity */ |
ab6ad5a4 | 1503 | u32 *init_data; |
619c5cb6 VZ |
1504 | u32 init_mode_flags; |
1505 | #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) | |
94a78b79 | 1506 | /* Zipped PRAM blobs - raw data */ |
ab6ad5a4 EG |
1507 | const u8 *tsem_int_table_data; |
1508 | const u8 *tsem_pram_data; | |
1509 | const u8 *usem_int_table_data; | |
1510 | const u8 *usem_pram_data; | |
1511 | const u8 *xsem_int_table_data; | |
1512 | const u8 *xsem_pram_data; | |
1513 | const u8 *csem_int_table_data; | |
1514 | const u8 *csem_pram_data; | |
573f2035 EG |
1515 | #define INIT_OPS(bp) (bp->init_ops) |
1516 | #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) | |
1517 | #define INIT_DATA(bp) (bp->init_data) | |
1518 | #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) | |
1519 | #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) | |
1520 | #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) | |
1521 | #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) | |
1522 | #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) | |
1523 | #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) | |
1524 | #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) | |
1525 | #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) | |
1526 | ||
619c5cb6 | 1527 | #define PHY_FW_VER_LEN 20 |
34f24c7f | 1528 | char fw_ver[32]; |
ab6ad5a4 | 1529 | const struct firmware *firmware; |
619c5cb6 | 1530 | |
785b9b1a SR |
1531 | /* DCB support on/off */ |
1532 | u16 dcb_state; | |
1533 | #define BNX2X_DCB_STATE_OFF 0 | |
1534 | #define BNX2X_DCB_STATE_ON 1 | |
1535 | ||
1536 | /* DCBX engine mode */ | |
1537 | int dcbx_enabled; | |
1538 | #define BNX2X_DCBX_ENABLED_OFF 0 | |
1539 | #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 | |
1540 | #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 | |
1541 | #define BNX2X_DCBX_ENABLED_INVALID (-1) | |
1542 | ||
1543 | bool dcbx_mode_uset; | |
1544 | ||
e4901dde | 1545 | struct bnx2x_config_dcbx_params dcbx_config_params; |
e4901dde VZ |
1546 | struct bnx2x_dcbx_port_params dcbx_port_params; |
1547 | int dcb_version; | |
1548 | ||
619c5cb6 VZ |
1549 | /* CAM credit pools */ |
1550 | struct bnx2x_credit_pool_obj macs_pool; | |
1551 | ||
1552 | /* RX_MODE object */ | |
1553 | struct bnx2x_rx_mode_obj rx_mode_obj; | |
1554 | ||
1555 | /* MCAST object */ | |
1556 | struct bnx2x_mcast_obj mcast_obj; | |
1557 | ||
1558 | /* RSS configuration object */ | |
1559 | struct bnx2x_rss_config_obj rss_conf_obj; | |
1560 | ||
1561 | /* Function State controlling object */ | |
1562 | struct bnx2x_func_sp_obj func_obj; | |
1563 | ||
1564 | unsigned long sp_state; | |
1565 | ||
7be08a72 AE |
1566 | /* operation indication for the sp_rtnl task */ |
1567 | unsigned long sp_rtnl_state; | |
1568 | ||
619c5cb6 | 1569 | /* DCBX Negotation results */ |
e4901dde VZ |
1570 | struct dcbx_features dcbx_local_feat; |
1571 | u32 dcbx_error; | |
619c5cb6 | 1572 | |
0be6bc62 SR |
1573 | #ifdef BCM_DCBNL |
1574 | struct dcbx_features dcbx_remote_feat; | |
1575 | u32 dcbx_remote_flags; | |
1576 | #endif | |
e3835b99 | 1577 | u32 pending_max; |
6383c0b3 AE |
1578 | |
1579 | /* multiple tx classes of service */ | |
1580 | u8 max_cos; | |
1581 | ||
1582 | /* priority to cos mapping */ | |
1583 | u8 prio_to_cos[8]; | |
a2fbb9ea ET |
1584 | }; |
1585 | ||
619c5cb6 VZ |
1586 | /* Tx queues may be less or equal to Rx queues */ |
1587 | extern int num_queues; | |
54b9ddaa | 1588 | #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) |
6383c0b3 AE |
1589 | #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE) |
1590 | #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) | |
ec6ba945 | 1591 | |
54b9ddaa | 1592 | #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) |
3196a88a | 1593 | |
6383c0b3 AE |
1594 | #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) |
1595 | /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ | |
523224a3 DK |
1596 | |
1597 | #define RSS_IPV4_CAP_MASK \ | |
1598 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | |
1599 | ||
1600 | #define RSS_IPV4_TCP_CAP_MASK \ | |
1601 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | |
1602 | ||
1603 | #define RSS_IPV6_CAP_MASK \ | |
1604 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | |
1605 | ||
1606 | #define RSS_IPV6_TCP_CAP_MASK \ | |
1607 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | |
1608 | ||
1609 | /* func init flags */ | |
619c5cb6 VZ |
1610 | #define FUNC_FLG_RSS 0x0001 |
1611 | #define FUNC_FLG_STATS 0x0002 | |
1612 | /* removed FUNC_FLG_UNMATCHED 0x0004 */ | |
1613 | #define FUNC_FLG_TPA 0x0008 | |
1614 | #define FUNC_FLG_SPQ 0x0010 | |
1615 | #define FUNC_FLG_LEADING 0x0020 /* PF only */ | |
523224a3 | 1616 | |
523224a3 DK |
1617 | |
1618 | struct bnx2x_func_init_params { | |
523224a3 DK |
1619 | /* dma */ |
1620 | dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ | |
1621 | dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ | |
1622 | ||
1623 | u16 func_flgs; | |
1624 | u16 func_id; /* abs fid */ | |
1625 | u16 pf_id; | |
1626 | u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ | |
1627 | }; | |
1628 | ||
ec6ba945 | 1629 | #define for_each_eth_queue(bp, var) \ |
6383c0b3 | 1630 | for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) |
ec6ba945 VZ |
1631 | |
1632 | #define for_each_nondefault_eth_queue(bp, var) \ | |
6383c0b3 | 1633 | for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) |
ec6ba945 | 1634 | |
555f6c78 | 1635 | #define for_each_queue(bp, var) \ |
6383c0b3 | 1636 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1637 | if (skip_queue(bp, var)) \ |
1638 | continue; \ | |
1639 | else | |
1640 | ||
6383c0b3 | 1641 | /* Skip forwarding FP */ |
ec6ba945 | 1642 | #define for_each_rx_queue(bp, var) \ |
6383c0b3 | 1643 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1644 | if (skip_rx_queue(bp, var)) \ |
1645 | continue; \ | |
1646 | else | |
1647 | ||
6383c0b3 | 1648 | /* Skip OOO FP */ |
ec6ba945 | 1649 | #define for_each_tx_queue(bp, var) \ |
6383c0b3 | 1650 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1651 | if (skip_tx_queue(bp, var)) \ |
1652 | continue; \ | |
1653 | else | |
1654 | ||
3196a88a | 1655 | #define for_each_nondefault_queue(bp, var) \ |
6383c0b3 | 1656 | for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1657 | if (skip_queue(bp, var)) \ |
1658 | continue; \ | |
1659 | else | |
3196a88a | 1660 | |
6383c0b3 AE |
1661 | #define for_each_cos_in_tx_queue(fp, var) \ |
1662 | for ((var) = 0; (var) < (fp)->max_cos; (var)++) | |
1663 | ||
ec6ba945 | 1664 | /* skip rx queue |
008d23e4 | 1665 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
ec6ba945 VZ |
1666 | */ |
1667 | #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1668 | ||
1669 | /* skip tx queue | |
008d23e4 | 1670 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
ec6ba945 VZ |
1671 | */ |
1672 | #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1673 | ||
1674 | #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
3196a88a | 1675 | |
f85582f8 | 1676 | |
619c5cb6 VZ |
1677 | |
1678 | ||
1679 | /** | |
1680 | * bnx2x_set_mac_one - configure a single MAC address | |
1681 | * | |
1682 | * @bp: driver handle | |
1683 | * @mac: MAC to configure | |
1684 | * @obj: MAC object handle | |
1685 | * @set: if 'true' add a new MAC, otherwise - delete | |
1686 | * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) | |
1687 | * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) | |
1688 | * | |
1689 | * Configures one MAC according to provided parameters or continues the | |
1690 | * execution of previously scheduled commands if RAMROD_CONT is set in | |
1691 | * ramrod_flags. | |
1692 | * | |
1693 | * Returns zero if operation has successfully completed, a positive value if the | |
1694 | * operation has been successfully scheduled and a negative - if a requested | |
1695 | * operations has failed. | |
1696 | */ | |
1697 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, | |
1698 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
1699 | int mac_type, unsigned long *ramrod_flags); | |
1700 | /** | |
1701 | * Deletes all MACs configured for the specific MAC object. | |
1702 | * | |
1703 | * @param bp Function driver instance | |
1704 | * @param mac_obj MAC object to cleanup | |
1705 | * | |
1706 | * @return zero if all MACs were cleaned | |
1707 | */ | |
1708 | ||
1709 | /** | |
1710 | * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object | |
1711 | * | |
1712 | * @bp: driver handle | |
1713 | * @mac_obj: MAC object handle | |
1714 | * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) | |
1715 | * @wait_for_comp: if 'true' block until completion | |
1716 | * | |
1717 | * Deletes all MACs of the specific type (e.g. ETH, UC list). | |
1718 | * | |
1719 | * Returns zero if operation has successfully completed, a positive value if the | |
1720 | * operation has been successfully scheduled and a negative - if a requested | |
1721 | * operations has failed. | |
1722 | */ | |
1723 | int bnx2x_del_all_macs(struct bnx2x *bp, | |
1724 | struct bnx2x_vlan_mac_obj *mac_obj, | |
1725 | int mac_type, bool wait_for_comp); | |
1726 | ||
1727 | /* Init Function API */ | |
1728 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); | |
1729 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); | |
1730 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); | |
1731 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); | |
1732 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); | |
2ae17f66 VZ |
1733 | void bnx2x_read_mf_cfg(struct bnx2x *bp); |
1734 | ||
619c5cb6 | 1735 | |
f85582f8 | 1736 | /* dmae */ |
c18487ee YR |
1737 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
1738 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
1739 | u32 len32); | |
f85582f8 DK |
1740 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); |
1741 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); | |
1742 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); | |
1743 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, | |
1744 | bool with_comp, u8 comp_type); | |
1745 | ||
f85582f8 | 1746 | |
de0c62db DK |
1747 | void bnx2x_calc_fc_adv(struct bnx2x *bp); |
1748 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, | |
619c5cb6 | 1749 | u32 data_hi, u32 data_lo, int cmd_type); |
de0c62db | 1750 | void bnx2x_update_coalesce(struct bnx2x *bp); |
1ac9e428 | 1751 | int bnx2x_get_cur_phy_idx(struct bnx2x *bp); |
f85582f8 | 1752 | |
34f80b04 EG |
1753 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
1754 | int wait) | |
1755 | { | |
1756 | u32 val; | |
1757 | ||
1758 | do { | |
1759 | val = REG_RD(bp, reg); | |
1760 | if (val == expected) | |
1761 | break; | |
1762 | ms -= wait; | |
1763 | msleep(wait); | |
1764 | ||
1765 | } while (ms > 0); | |
1766 | ||
1767 | return val; | |
1768 | } | |
f85582f8 | 1769 | |
523224a3 DK |
1770 | #define BNX2X_ILT_ZALLOC(x, y, size) \ |
1771 | do { \ | |
d245a111 | 1772 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ |
523224a3 DK |
1773 | if (x) \ |
1774 | memset(x, 0, size); \ | |
1775 | } while (0) | |
1776 | ||
1777 | #define BNX2X_ILT_FREE(x, y, size) \ | |
1778 | do { \ | |
1779 | if (x) { \ | |
d245a111 | 1780 | dma_free_coherent(&bp->pdev->dev, size, x, y); \ |
523224a3 DK |
1781 | x = NULL; \ |
1782 | y = 0; \ | |
1783 | } \ | |
1784 | } while (0) | |
1785 | ||
1786 | #define ILOG2(x) (ilog2((x))) | |
1787 | ||
1788 | #define ILT_NUM_PAGE_ENTRIES (3072) | |
1789 | /* In 57710/11 we use whole table since we have 8 func | |
f85582f8 DK |
1790 | * In 57712 we have only 4 func, but use same size per func, then only half of |
1791 | * the table in use | |
523224a3 DK |
1792 | */ |
1793 | #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) | |
1794 | ||
1795 | #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) | |
1796 | /* | |
1797 | * the phys address is shifted right 12 bits and has an added | |
1798 | * 1=valid bit added to the 53rd bit | |
1799 | * then since this is a wide register(TM) | |
1800 | * we split it into two 32 bit writes | |
1801 | */ | |
1802 | #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) | |
1803 | #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) | |
34f80b04 | 1804 | |
34f80b04 EG |
1805 | /* load/unload mode */ |
1806 | #define LOAD_NORMAL 0 | |
1807 | #define LOAD_OPEN 1 | |
1808 | #define LOAD_DIAG 2 | |
1809 | #define UNLOAD_NORMAL 0 | |
1810 | #define UNLOAD_CLOSE 1 | |
f85582f8 | 1811 | #define UNLOAD_RECOVERY 2 |
34f80b04 | 1812 | |
bb2a0f7a | 1813 | |
ad8d3948 | 1814 | /* DMAE command defines */ |
f2e0899f DK |
1815 | #define DMAE_TIMEOUT -1 |
1816 | #define DMAE_PCI_ERROR -2 /* E2 and onward */ | |
1817 | #define DMAE_NOT_RDY -3 | |
1818 | #define DMAE_PCI_ERR_FLAG 0x80000000 | |
1819 | ||
1820 | #define DMAE_SRC_PCI 0 | |
1821 | #define DMAE_SRC_GRC 1 | |
1822 | ||
1823 | #define DMAE_DST_NONE 0 | |
1824 | #define DMAE_DST_PCI 1 | |
1825 | #define DMAE_DST_GRC 2 | |
1826 | ||
1827 | #define DMAE_COMP_PCI 0 | |
1828 | #define DMAE_COMP_GRC 1 | |
1829 | ||
1830 | /* E2 and onward - PCI error handling in the completion */ | |
1831 | ||
1832 | #define DMAE_COMP_REGULAR 0 | |
1833 | #define DMAE_COM_SET_ERR 1 | |
ad8d3948 | 1834 | |
f2e0899f DK |
1835 | #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ |
1836 | DMAE_COMMAND_SRC_SHIFT) | |
1837 | #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ | |
1838 | DMAE_COMMAND_SRC_SHIFT) | |
ad8d3948 | 1839 | |
f2e0899f DK |
1840 | #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ |
1841 | DMAE_COMMAND_DST_SHIFT) | |
1842 | #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ | |
1843 | DMAE_COMMAND_DST_SHIFT) | |
1844 | ||
1845 | #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ | |
1846 | DMAE_COMMAND_C_DST_SHIFT) | |
1847 | #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ | |
1848 | DMAE_COMMAND_C_DST_SHIFT) | |
ad8d3948 EG |
1849 | |
1850 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
1851 | ||
1852 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1853 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1854 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1855 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1856 | ||
1857 | #define DMAE_CMD_PORT_0 0 | |
1858 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
1859 | ||
1860 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
1861 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
1862 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
1863 | ||
f2e0899f DK |
1864 | #define DMAE_SRC_PF 0 |
1865 | #define DMAE_SRC_VF 1 | |
1866 | ||
1867 | #define DMAE_DST_PF 0 | |
1868 | #define DMAE_DST_VF 1 | |
1869 | ||
1870 | #define DMAE_C_SRC 0 | |
1871 | #define DMAE_C_DST 1 | |
1872 | ||
ad8d3948 | 1873 | #define DMAE_LEN32_RD_MAX 0x80 |
02e3c6cb | 1874 | #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
ad8d3948 | 1875 | |
f2e0899f DK |
1876 | #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit |
1877 | indicates eror */ | |
ad8d3948 EG |
1878 | |
1879 | #define MAX_DMAE_C_PER_PORT 8 | |
ab6ad5a4 | 1880 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
3395a033 | 1881 | BP_VN(bp)) |
ab6ad5a4 | 1882 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 EG |
1883 | E1HVN_MAX) |
1884 | ||
25047950 ET |
1885 | /* PCIE link and speed */ |
1886 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
1887 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
1888 | #define PCICFG_LINK_SPEED 0xf0000 | |
1889 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
a2fbb9ea | 1890 | |
bb2a0f7a | 1891 | |
d3d4f495 | 1892 | #define BNX2X_NUM_TESTS 7 |
bb2a0f7a | 1893 | |
b5bf9068 EG |
1894 | #define BNX2X_PHY_LOOPBACK 0 |
1895 | #define BNX2X_MAC_LOOPBACK 1 | |
1896 | #define BNX2X_PHY_LOOPBACK_FAILED 1 | |
1897 | #define BNX2X_MAC_LOOPBACK_FAILED 2 | |
bb2a0f7a YG |
1898 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ |
1899 | BNX2X_PHY_LOOPBACK_FAILED) | |
96fc1784 | 1900 | |
7a9b2557 VZ |
1901 | |
1902 | #define STROM_ASSERT_ARRAY_SIZE 50 | |
1903 | ||
96fc1784 | 1904 | |
34f80b04 | 1905 | /* must be used on a CID before placing it on a HW ring */ |
ab6ad5a4 | 1906 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
3395a033 | 1907 | (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ |
619c5cb6 | 1908 | (x)) |
7a9b2557 VZ |
1909 | |
1910 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
1911 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
1912 | ||
1913 | ||
523224a3 | 1914 | #define BNX2X_BTR 4 |
7a9b2557 | 1915 | #define MAX_SPQ_PENDING 8 |
a2fbb9ea | 1916 | |
ff80ee02 DK |
1917 | /* CMNG constants, as derived from system spec calculations */ |
1918 | /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ | |
1919 | #define DEF_MIN_RATE 100 | |
9b3de1ef DK |
1920 | /* resolution of the rate shaping timer - 400 usec */ |
1921 | #define RS_PERIODIC_TIMEOUT_USEC 400 | |
34f80b04 | 1922 | /* number of bytes in single QM arbitration cycle - |
ff80ee02 DK |
1923 | * coefficient for calculating the fairness timer */ |
1924 | #define QM_ARB_BYTES 160000 | |
1925 | /* resolution of Min algorithm 1:100 */ | |
1926 | #define MIN_RES 100 | |
1927 | /* how many bytes above threshold for the minimal credit of Min algorithm*/ | |
1928 | #define MIN_ABOVE_THRESH 32768 | |
1929 | /* Fairness algorithm integration time coefficient - | |
1930 | * for calculating the actual Tfair */ | |
1931 | #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) | |
1932 | /* Memory of fairness algorithm . 2 cycles */ | |
1933 | #define FAIR_MEM 2 | |
34f80b04 EG |
1934 | |
1935 | ||
1936 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1937 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1938 | #define GPIO_2_FUNC (1L << 10) | |
1939 | #define GPIO_3_FUNC (1L << 11) | |
1940 | #define GPIO_4_FUNC (1L << 12) | |
1941 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1942 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1943 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1944 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1945 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1946 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1947 | ||
1948 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1949 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
1950 | |
1951 | ||
34f80b04 EG |
1952 | /* stuff added to make the code fit 80Col */ |
1953 | ||
1954 | #define BNX2X_PMF_LINK_ASSERT \ | |
1955 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
1956 | ||
a2fbb9ea ET |
1957 | #define BNX2X_MC_ASSERT_BITS \ |
1958 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1959 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1960 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1961 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1962 | ||
1963 | #define BNX2X_MCP_ASSERT \ | |
1964 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1965 | ||
34f80b04 EG |
1966 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
1967 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1968 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1969 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1970 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1971 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1972 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1973 | ||
a2fbb9ea ET |
1974 | #define HW_INTERRUT_ASSERT_SET_0 \ |
1975 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1976 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1977 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
c9ee9206 | 1978 | AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) |
34f80b04 | 1979 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
a2fbb9ea ET |
1980 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
1981 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1982 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
c9ee9206 VZ |
1983 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ |
1984 | AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ | |
1985 | AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) | |
a2fbb9ea ET |
1986 | #define HW_INTERRUT_ASSERT_SET_1 \ |
1987 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1988 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1989 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1990 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1991 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1992 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1993 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1994 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1995 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1996 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1997 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
c9ee9206 | 1998 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ |
a2fbb9ea | 1999 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
c9ee9206 | 2000 | AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ |
a2fbb9ea | 2001 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ |
c9ee9206 | 2002 | AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ |
a2fbb9ea | 2003 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ |
ab6ad5a4 | 2004 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
c9ee9206 | 2005 | AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ |
ab6ad5a4 | 2006 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ |
a2fbb9ea ET |
2007 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
2008 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
c9ee9206 | 2009 | AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ |
a2fbb9ea ET |
2010 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ |
2011 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
c9ee9206 VZ |
2012 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ |
2013 | AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) | |
a2fbb9ea ET |
2014 | #define HW_INTERRUT_ASSERT_SET_2 \ |
2015 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
2016 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
2017 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
2018 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
2019 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
34f80b04 | 2020 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
a2fbb9ea ET |
2021 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
2022 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
2023 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
2024 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
c9ee9206 | 2025 | AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ |
a2fbb9ea ET |
2026 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ |
2027 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
2028 | ||
72fd0718 VZ |
2029 | #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ |
2030 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ | |
2031 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ | |
2032 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) | |
a2fbb9ea | 2033 | |
8736c826 VZ |
2034 | #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ |
2035 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) | |
2036 | ||
34f80b04 | 2037 | #define MULTI_MASK 0x7f |
a2fbb9ea | 2038 | |
619c5cb6 VZ |
2039 | |
2040 | #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) | |
2041 | #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) | |
2042 | #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) | |
2043 | #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) | |
2044 | ||
2045 | #define DEF_USB_IGU_INDEX_OFF \ | |
2046 | offsetof(struct cstorm_def_status_block_u, igu_index) | |
2047 | #define DEF_CSB_IGU_INDEX_OFF \ | |
2048 | offsetof(struct cstorm_def_status_block_c, igu_index) | |
2049 | #define DEF_XSB_IGU_INDEX_OFF \ | |
2050 | offsetof(struct xstorm_def_status_block, igu_index) | |
2051 | #define DEF_TSB_IGU_INDEX_OFF \ | |
2052 | offsetof(struct tstorm_def_status_block, igu_index) | |
2053 | ||
2054 | #define DEF_USB_SEGMENT_OFF \ | |
2055 | offsetof(struct cstorm_def_status_block_u, segment) | |
2056 | #define DEF_CSB_SEGMENT_OFF \ | |
2057 | offsetof(struct cstorm_def_status_block_c, segment) | |
2058 | #define DEF_XSB_SEGMENT_OFF \ | |
2059 | offsetof(struct xstorm_def_status_block, segment) | |
2060 | #define DEF_TSB_SEGMENT_OFF \ | |
2061 | offsetof(struct tstorm_def_status_block, segment) | |
2062 | ||
a2fbb9ea | 2063 | #define BNX2X_SP_DSB_INDEX \ |
523224a3 DK |
2064 | (&bp->def_status_blk->sp_sb.\ |
2065 | index_values[HC_SP_INDEX_ETH_DEF_CONS]) | |
f85582f8 | 2066 | |
523224a3 DK |
2067 | #define SET_FLAG(value, mask, flag) \ |
2068 | do {\ | |
2069 | (value) &= ~(mask);\ | |
2070 | (value) |= ((flag) << (mask##_SHIFT));\ | |
2071 | } while (0) | |
a2fbb9ea | 2072 | |
523224a3 | 2073 | #define GET_FLAG(value, mask) \ |
619c5cb6 | 2074 | (((value) & (mask)) >> (mask##_SHIFT)) |
a2fbb9ea | 2075 | |
f2e0899f DK |
2076 | #define GET_FIELD(value, fname) \ |
2077 | (((value) & (fname##_MASK)) >> (fname##_SHIFT)) | |
2078 | ||
a2fbb9ea | 2079 | #define CAM_IS_INVALID(x) \ |
523224a3 DK |
2080 | (GET_FLAG(x.flags, \ |
2081 | MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ | |
2082 | (T_ETH_MAC_COMMAND_INVALIDATE)) | |
a2fbb9ea | 2083 | |
34f80b04 EG |
2084 | /* Number of u32 elements in MC hash array */ |
2085 | #define MC_HASH_SIZE 8 | |
2086 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
2087 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
a2fbb9ea ET |
2088 | |
2089 | ||
34f80b04 EG |
2090 | #ifndef PXP2_REG_PXP2_INT_STS |
2091 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
2092 | #endif | |
2093 | ||
f2e0899f DK |
2094 | #ifndef ETH_MAX_RX_CLIENTS_E2 |
2095 | #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H | |
2096 | #endif | |
f85582f8 | 2097 | |
34f24c7f VZ |
2098 | #define BNX2X_VPD_LEN 128 |
2099 | #define VENDOR_ID_LEN 4 | |
2100 | ||
523224a3 DK |
2101 | /* Congestion management fairness mode */ |
2102 | #define CMNG_FNS_NONE 0 | |
2103 | #define CMNG_FNS_MINMAX 1 | |
2104 | ||
2105 | #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ | |
2106 | #define HC_SEG_ACCESS_ATTN 4 | |
2107 | #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ | |
2108 | ||
619c5cb6 VZ |
2109 | static const u32 dmae_reg_go_c[] = { |
2110 | DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, | |
2111 | DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, | |
2112 | DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, | |
2113 | DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 | |
2114 | }; | |
de0c62db | 2115 | |
619c5cb6 | 2116 | void bnx2x_set_ethtool_ops(struct net_device *netdev); |
3deb8167 | 2117 | void bnx2x_notify_link_changed(struct bnx2x *bp); |
614c76df DK |
2118 | |
2119 | ||
2120 | #define BNX2X_MF_PROTOCOL(bp) \ | |
2121 | ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) | |
2122 | ||
2123 | #ifdef BCM_CNIC | |
2124 | #define BNX2X_IS_MF_PROTOCOL_ISCSI(bp) \ | |
2125 | (BNX2X_MF_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) | |
2126 | ||
2127 | #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) | |
2128 | #endif | |
2129 | ||
a2fbb9ea | 2130 | #endif /* bnx2x.h */ |