Commit | Line | Data |
---|---|---|
a2fbb9ea ET |
1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | |
5de92408 | 3 | * Copyright (c) 2007-2011 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
ec6ba945 | 16 | #include <linux/netdevice.h> |
b7f080cf | 17 | #include <linux/dma-mapping.h> |
ec6ba945 | 18 | #include <linux/types.h> |
a2fbb9ea | 19 | |
34f80b04 EG |
20 | /* compilation time flags */ |
21 | ||
22 | /* define this to make the driver freeze on error to allow getting debug info | |
23 | * (you will need to reboot afterwards) */ | |
24 | /* #define BNX2X_STOP_ON_ERROR */ | |
25 | ||
5d70b88c DK |
26 | #define DRV_MODULE_VERSION "1.70.35-0" |
27 | #define DRV_MODULE_RELDATE "2011/11/10" | |
de0c62db DK |
28 | #define BNX2X_BC_VER 0x040200 |
29 | ||
785b9b1a | 30 | #if defined(CONFIG_DCB) |
98507672 | 31 | #define BCM_DCBNL |
785b9b1a | 32 | #endif |
993ac7b5 MC |
33 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
34 | #define BCM_CNIC 1 | |
5d1e859c | 35 | #include "../cnic_if.h" |
993ac7b5 | 36 | #endif |
0c6671b0 | 37 | |
1ac218c8 VZ |
38 | #ifdef BCM_CNIC |
39 | #define BNX2X_MIN_MSIX_VEC_CNT 3 | |
40 | #define BNX2X_MSIX_VEC_FP_START 2 | |
41 | #else | |
42 | #define BNX2X_MIN_MSIX_VEC_CNT 2 | |
43 | #define BNX2X_MSIX_VEC_FP_START 1 | |
44 | #endif | |
01cd4528 EG |
45 | |
46 | #include <linux/mdio.h> | |
619c5cb6 | 47 | |
359d8b15 EG |
48 | #include "bnx2x_reg.h" |
49 | #include "bnx2x_fw_defs.h" | |
50 | #include "bnx2x_hsi.h" | |
51 | #include "bnx2x_link.h" | |
619c5cb6 | 52 | #include "bnx2x_sp.h" |
e4901dde | 53 | #include "bnx2x_dcb.h" |
6c719d00 | 54 | #include "bnx2x_stats.h" |
359d8b15 | 55 | |
a2fbb9ea ET |
56 | /* error/debug prints */ |
57 | ||
34f80b04 | 58 | #define DRV_MODULE_NAME "bnx2x" |
a2fbb9ea ET |
59 | |
60 | /* for messages that are currently off */ | |
34f80b04 EG |
61 | #define BNX2X_MSG_OFF 0 |
62 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ | |
63 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ | |
64 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ | |
65 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ | |
f1410647 ET |
66 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
67 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | |
a2fbb9ea | 68 | |
a2fbb9ea | 69 | /* regular debug print */ |
f1deab50 | 70 | #define DP(__mask, fmt, ...) \ |
7995c64e JP |
71 | do { \ |
72 | if (bp->msg_enable & (__mask)) \ | |
f1deab50 JP |
73 | pr_notice("[%s:%d(%s)]" fmt, \ |
74 | __func__, __LINE__, \ | |
75 | bp->dev ? (bp->dev->name) : "?", \ | |
76 | ##__VA_ARGS__); \ | |
7995c64e | 77 | } while (0) |
a2fbb9ea | 78 | |
f1deab50 | 79 | #define DP_CONT(__mask, fmt, ...) \ |
619c5cb6 VZ |
80 | do { \ |
81 | if (bp->msg_enable & (__mask)) \ | |
f1deab50 | 82 | pr_cont(fmt, ##__VA_ARGS__); \ |
619c5cb6 VZ |
83 | } while (0) |
84 | ||
34f80b04 | 85 | /* errors debug print */ |
f1deab50 | 86 | #define BNX2X_DBG_ERR(fmt, ...) \ |
7995c64e JP |
87 | do { \ |
88 | if (netif_msg_probe(bp)) \ | |
f1deab50 | 89 | pr_err("[%s:%d(%s)]" fmt, \ |
7995c64e JP |
90 | __func__, __LINE__, \ |
91 | bp->dev ? (bp->dev->name) : "?", \ | |
f1deab50 | 92 | ##__VA_ARGS__); \ |
7995c64e | 93 | } while (0) |
a2fbb9ea | 94 | |
34f80b04 | 95 | /* for errors (never masked) */ |
f1deab50 | 96 | #define BNX2X_ERR(fmt, ...) \ |
7995c64e | 97 | do { \ |
f1deab50 | 98 | pr_err("[%s:%d(%s)]" fmt, \ |
7995c64e JP |
99 | __func__, __LINE__, \ |
100 | bp->dev ? (bp->dev->name) : "?", \ | |
f1deab50 JP |
101 | ##__VA_ARGS__); \ |
102 | } while (0) | |
cdaa7cb8 | 103 | |
f1deab50 JP |
104 | #define BNX2X_ERROR(fmt, ...) \ |
105 | pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) | |
cdaa7cb8 | 106 | |
f1410647 | 107 | |
a2fbb9ea | 108 | /* before we have a dev->name use dev_info() */ |
f1deab50 | 109 | #define BNX2X_DEV_INFO(fmt, ...) \ |
7995c64e JP |
110 | do { \ |
111 | if (netif_msg_probe(bp)) \ | |
f1deab50 | 112 | dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ |
7995c64e | 113 | } while (0) |
a2fbb9ea | 114 | |
a2fbb9ea | 115 | #ifdef BNX2X_STOP_ON_ERROR |
6383c0b3 | 116 | void bnx2x_int_disable(struct bnx2x *bp); |
f1deab50 JP |
117 | #define bnx2x_panic() \ |
118 | do { \ | |
119 | bp->panic = 1; \ | |
120 | BNX2X_ERR("driver assert\n"); \ | |
121 | bnx2x_int_disable(bp); \ | |
122 | bnx2x_panic_dump(bp); \ | |
123 | } while (0) | |
a2fbb9ea | 124 | #else |
f1deab50 JP |
125 | #define bnx2x_panic() \ |
126 | do { \ | |
127 | bp->panic = 1; \ | |
128 | BNX2X_ERR("driver assert\n"); \ | |
129 | bnx2x_panic_dump(bp); \ | |
130 | } while (0) | |
a2fbb9ea ET |
131 | #endif |
132 | ||
523224a3 | 133 | #define bnx2x_mc_addr(ha) ((ha)->addr) |
6e30dd4e | 134 | #define bnx2x_uc_addr(ha) ((ha)->addr) |
a2fbb9ea | 135 | |
34f80b04 EG |
136 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
137 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | |
138 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
a2fbb9ea | 139 | |
a2fbb9ea | 140 | |
523224a3 | 141 | #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) |
a2fbb9ea | 142 | |
34f80b04 EG |
143 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
144 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
523224a3 | 145 | #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) |
34f80b04 EG |
146 | |
147 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
a2fbb9ea | 148 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
34f80b04 | 149 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
a2fbb9ea | 150 | |
34f80b04 EG |
151 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
152 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
a2fbb9ea | 153 | |
c18487ee YR |
154 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
155 | do { \ | |
156 | bnx2x_read_dmae(bp, offset, len32);\ | |
573f2035 | 157 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ |
c18487ee YR |
158 | } while (0) |
159 | ||
34f80b04 | 160 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
a2fbb9ea | 161 | do { \ |
573f2035 | 162 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ |
a2fbb9ea ET |
163 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
164 | offset, len32); \ | |
165 | } while (0) | |
166 | ||
523224a3 DK |
167 | #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ |
168 | REG_WR_DMAE(bp, offset, valp, len32) | |
169 | ||
3359fced | 170 | #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ |
573f2035 EG |
171 | do { \ |
172 | memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ | |
173 | bnx2x_write_big_buf_wb(bp, addr, len32); \ | |
174 | } while (0) | |
175 | ||
34f80b04 EG |
176 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
177 | offsetof(struct shmem_region, field)) | |
178 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
179 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
a2fbb9ea | 180 | |
2691d51d EG |
181 | #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ |
182 | offsetof(struct shmem2_region, field)) | |
183 | #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) | |
184 | #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) | |
523224a3 DK |
185 | #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ |
186 | offsetof(struct mf_cfg, field)) | |
f85582f8 | 187 | #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ |
f2e0899f | 188 | offsetof(struct mf2_cfg, field)) |
2691d51d | 189 | |
523224a3 DK |
190 | #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) |
191 | #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ | |
192 | MF_CFG_ADDR(bp, field), (val)) | |
f2e0899f | 193 | #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) |
f85582f8 | 194 | |
f2e0899f DK |
195 | #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ |
196 | (SHMEM2_RD((bp), size) > \ | |
197 | offsetof(struct shmem2_region, field))) | |
72fd0718 | 198 | |
345b5d52 | 199 | #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
3196a88a | 200 | #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
a2fbb9ea | 201 | |
523224a3 DK |
202 | /* SP SB indices */ |
203 | ||
204 | /* General SP events - stats query, cfc delete, etc */ | |
205 | #define HC_SP_INDEX_ETH_DEF_CONS 3 | |
206 | ||
207 | /* EQ completions */ | |
208 | #define HC_SP_INDEX_EQ_CONS 7 | |
209 | ||
ec6ba945 VZ |
210 | /* FCoE L2 connection completions */ |
211 | #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 | |
212 | #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 | |
523224a3 DK |
213 | /* iSCSI L2 */ |
214 | #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 | |
215 | #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 | |
216 | ||
ec6ba945 VZ |
217 | /* Special clients parameters */ |
218 | ||
219 | /* SB indices */ | |
220 | /* FCoE L2 */ | |
221 | #define BNX2X_FCOE_L2_RX_INDEX \ | |
222 | (&bp->def_status_blk->sp_sb.\ | |
223 | index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) | |
224 | ||
225 | #define BNX2X_FCOE_L2_TX_INDEX \ | |
226 | (&bp->def_status_blk->sp_sb.\ | |
227 | index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) | |
228 | ||
523224a3 DK |
229 | /** |
230 | * CIDs and CLIDs: | |
231 | * CLIDs below is a CLID for func 0, then the CLID for other | |
232 | * functions will be calculated by the formula: | |
233 | * | |
234 | * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X | |
235 | * | |
236 | */ | |
134d0f97 DK |
237 | enum { |
238 | BNX2X_ISCSI_ETH_CL_ID_IDX, | |
239 | BNX2X_FCOE_ETH_CL_ID_IDX, | |
240 | BNX2X_MAX_CNIC_ETH_CL_ID_IDX, | |
241 | }; | |
242 | ||
243 | #define BNX2X_CNIC_START_ETH_CID 48 | |
244 | enum { | |
245 | /* iSCSI L2 */ | |
246 | BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID, | |
247 | /* FCoE L2 */ | |
248 | BNX2X_FCOE_ETH_CID, | |
249 | }; | |
ec6ba945 | 250 | |
523224a3 DK |
251 | /** Additional rings budgeting */ |
252 | #ifdef BCM_CNIC | |
6383c0b3 AE |
253 | #define CNIC_PRESENT 1 |
254 | #define FCOE_PRESENT 1 | |
523224a3 | 255 | #else |
6383c0b3 AE |
256 | #define CNIC_PRESENT 0 |
257 | #define FCOE_PRESENT 0 | |
523224a3 | 258 | #endif /* BCM_CNIC */ |
6383c0b3 | 259 | #define NON_ETH_CONTEXT_USE (FCOE_PRESENT) |
523224a3 | 260 | |
72fd0718 VZ |
261 | #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ |
262 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR | |
263 | ||
523224a3 DK |
264 | #define SM_RX_ID 0 |
265 | #define SM_TX_ID 1 | |
a2fbb9ea | 266 | |
6383c0b3 AE |
267 | /* defines for multiple tx priority indices */ |
268 | #define FIRST_TX_ONLY_COS_INDEX 1 | |
269 | #define FIRST_TX_COS_INDEX 0 | |
270 | ||
271 | /* defines for decodeing the fastpath index and the cos index out of the | |
272 | * transmission queue index | |
273 | */ | |
274 | #define MAX_TXQS_PER_COS FP_SB_MAX_E1x | |
275 | ||
276 | #define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS) | |
277 | #define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS) | |
278 | ||
279 | /* rules for calculating the cids of tx-only connections */ | |
280 | #define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS) | |
281 | #define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS) | |
282 | ||
283 | /* fp index inside class of service range */ | |
284 | #define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS) | |
285 | ||
286 | /* | |
287 | * 0..15 eth cos0 | |
288 | * 16..31 eth cos1 if applicable | |
289 | * 32..47 eth cos2 If applicable | |
290 | * fcoe queue follows eth queues (16, 32, 48 depending on cos) | |
291 | */ | |
292 | #define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos) | |
293 | #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp)) | |
a2fbb9ea | 294 | |
6383c0b3 | 295 | /* fast path */ |
e52fcb24 ED |
296 | /* |
297 | * This driver uses new build_skb() API : | |
298 | * RX ring buffer contains pointer to kmalloc() data only, | |
299 | * skb are built only after Hardware filled the frame. | |
300 | */ | |
a2fbb9ea | 301 | struct sw_rx_bd { |
e52fcb24 | 302 | u8 *data; |
1a983142 | 303 | DEFINE_DMA_UNMAP_ADDR(mapping); |
a2fbb9ea ET |
304 | }; |
305 | ||
306 | struct sw_tx_bd { | |
34f80b04 EG |
307 | struct sk_buff *skb; |
308 | u16 first_bd; | |
ca00392c EG |
309 | u8 flags; |
310 | /* Set on the first BD descriptor when there is a split BD */ | |
311 | #define BNX2X_TSO_SPLIT_BD (1<<0) | |
a2fbb9ea ET |
312 | }; |
313 | ||
7a9b2557 VZ |
314 | struct sw_rx_page { |
315 | struct page *page; | |
1a983142 | 316 | DEFINE_DMA_UNMAP_ADDR(mapping); |
7a9b2557 VZ |
317 | }; |
318 | ||
ca00392c EG |
319 | union db_prod { |
320 | struct doorbell_set_prod data; | |
321 | u32 raw; | |
322 | }; | |
323 | ||
dfacf138 DK |
324 | /* dropless fc FW/HW related params */ |
325 | #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) | |
326 | #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ | |
327 | ETH_MAX_AGGREGATION_QUEUES_E1 :\ | |
328 | ETH_MAX_AGGREGATION_QUEUES_E1H_E2) | |
329 | #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) | |
330 | #define FW_PREFETCH_CNT 16 | |
331 | #define DROPLESS_FC_HEADROOM 100 | |
7a9b2557 VZ |
332 | |
333 | /* MC hsi */ | |
619c5cb6 VZ |
334 | #define BCM_PAGE_SHIFT 12 |
335 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
336 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
7a9b2557 VZ |
337 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) |
338 | ||
619c5cb6 VZ |
339 | #define PAGES_PER_SGE_SHIFT 0 |
340 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | |
341 | #define SGE_PAGE_SIZE PAGE_SIZE | |
342 | #define SGE_PAGE_SHIFT PAGE_SHIFT | |
343 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) | |
7a9b2557 VZ |
344 | |
345 | /* SGE ring related macros */ | |
619c5cb6 | 346 | #define NUM_RX_SGE_PAGES 2 |
7a9b2557 | 347 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) |
dfacf138 DK |
348 | #define NEXT_PAGE_SGE_DESC_CNT 2 |
349 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) | |
33471629 | 350 | /* RX_SGE_CNT is promised to be a power of 2 */ |
619c5cb6 VZ |
351 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
352 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | |
353 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | |
7a9b2557 | 354 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ |
dfacf138 DK |
355 | (MAX_RX_SGE_CNT - 1)) ? \ |
356 | (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ | |
357 | (x) + 1) | |
619c5cb6 VZ |
358 | #define RX_SGE(x) ((x) & MAX_RX_SGE) |
359 | ||
dfacf138 DK |
360 | /* |
361 | * Number of required SGEs is the sum of two: | |
362 | * 1. Number of possible opened aggregations (next packet for | |
363 | * these aggregations will probably consume SGE immidiatelly) | |
364 | * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only | |
365 | * after placement on BD for new TPA aggregation) | |
366 | * | |
367 | * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page | |
368 | */ | |
369 | #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ | |
370 | (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) | |
371 | #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ | |
372 | MAX_RX_SGE_CNT) | |
373 | #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ | |
374 | NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) | |
375 | #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) | |
376 | ||
619c5cb6 | 377 | /* Manipulate a bit vector defined as an array of u64 */ |
7a9b2557 | 378 | |
7a9b2557 | 379 | /* Number of bits in one sge_mask array element */ |
619c5cb6 VZ |
380 | #define BIT_VEC64_ELEM_SZ 64 |
381 | #define BIT_VEC64_ELEM_SHIFT 6 | |
382 | #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) | |
383 | ||
384 | ||
385 | #define __BIT_VEC64_SET_BIT(el, bit) \ | |
386 | do { \ | |
387 | el = ((el) | ((u64)0x1 << (bit))); \ | |
388 | } while (0) | |
389 | ||
390 | #define __BIT_VEC64_CLEAR_BIT(el, bit) \ | |
391 | do { \ | |
392 | el = ((el) & (~((u64)0x1 << (bit)))); \ | |
393 | } while (0) | |
394 | ||
395 | ||
396 | #define BIT_VEC64_SET_BIT(vec64, idx) \ | |
397 | __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ | |
398 | (idx) & BIT_VEC64_ELEM_MASK) | |
399 | ||
400 | #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ | |
401 | __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ | |
402 | (idx) & BIT_VEC64_ELEM_MASK) | |
403 | ||
404 | #define BIT_VEC64_TEST_BIT(vec64, idx) \ | |
405 | (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ | |
406 | ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) | |
7a9b2557 VZ |
407 | |
408 | /* Creates a bitmask of all ones in less significant bits. | |
409 | idx - index of the most significant bit in the created mask */ | |
619c5cb6 VZ |
410 | #define BIT_VEC64_ONES_MASK(idx) \ |
411 | (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) | |
412 | #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) | |
413 | ||
414 | /*******************************************************/ | |
415 | ||
416 | ||
7a9b2557 VZ |
417 | |
418 | /* Number of u64 elements in SGE mask array */ | |
b3637827 | 419 | #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) |
7a9b2557 VZ |
420 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) |
421 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) | |
422 | ||
523224a3 DK |
423 | union host_hc_status_block { |
424 | /* pointer to fp status block e1x */ | |
425 | struct host_hc_status_block_e1x *e1x_sb; | |
f2e0899f DK |
426 | /* pointer to fp status block e2 */ |
427 | struct host_hc_status_block_e2 *e2_sb; | |
523224a3 | 428 | }; |
7a9b2557 | 429 | |
619c5cb6 VZ |
430 | struct bnx2x_agg_info { |
431 | /* | |
e52fcb24 ED |
432 | * First aggregation buffer is a data buffer, the following - are pages. |
433 | * We will preallocate the data buffer for each aggregation when | |
619c5cb6 VZ |
434 | * we open the interface and will replace the BD at the consumer |
435 | * with this one when we receive the TPA_START CQE in order to | |
436 | * keep the Rx BD ring consistent. | |
437 | */ | |
438 | struct sw_rx_bd first_buf; | |
439 | u8 tpa_state; | |
440 | #define BNX2X_TPA_START 1 | |
441 | #define BNX2X_TPA_STOP 2 | |
442 | #define BNX2X_TPA_ERROR 3 | |
443 | u8 placement_offset; | |
444 | u16 parsing_flags; | |
445 | u16 vlan_tag; | |
446 | u16 len_on_bd; | |
e52fcb24 | 447 | u32 rxhash; |
619c5cb6 VZ |
448 | }; |
449 | ||
450 | #define Q_STATS_OFFSET32(stat_name) \ | |
451 | (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) | |
452 | ||
6383c0b3 AE |
453 | struct bnx2x_fp_txdata { |
454 | ||
455 | struct sw_tx_bd *tx_buf_ring; | |
456 | ||
457 | union eth_tx_bd_types *tx_desc_ring; | |
458 | dma_addr_t tx_desc_mapping; | |
459 | ||
460 | u32 cid; | |
461 | ||
462 | union db_prod tx_db; | |
463 | ||
464 | u16 tx_pkt_prod; | |
465 | u16 tx_pkt_cons; | |
466 | u16 tx_bd_prod; | |
467 | u16 tx_bd_cons; | |
468 | ||
469 | unsigned long tx_pkt; | |
470 | ||
471 | __le16 *tx_cons_sb; | |
472 | ||
473 | int txq_index; | |
474 | }; | |
475 | ||
a2fbb9ea | 476 | struct bnx2x_fastpath { |
619c5cb6 | 477 | struct bnx2x *bp; /* parent */ |
a2fbb9ea | 478 | |
d6214d7a | 479 | #define BNX2X_NAPI_WEIGHT 128 |
34f80b04 | 480 | struct napi_struct napi; |
f85582f8 | 481 | union host_hc_status_block status_blk; |
523224a3 DK |
482 | /* chip independed shortcuts into sb structure */ |
483 | __le16 *sb_index_values; | |
484 | __le16 *sb_running_index; | |
485 | /* chip independed shortcut into rx_prods_offset memory */ | |
486 | u32 ustorm_rx_prods_offset; | |
487 | ||
a8c94b91 VZ |
488 | u32 rx_buf_size; |
489 | ||
34f80b04 | 490 | dma_addr_t status_blk_mapping; |
a2fbb9ea | 491 | |
6383c0b3 AE |
492 | u8 max_cos; /* actual number of active tx coses */ |
493 | struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS]; | |
a2fbb9ea | 494 | |
7a9b2557 VZ |
495 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
496 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ | |
a2fbb9ea ET |
497 | |
498 | struct eth_rx_bd *rx_desc_ring; | |
34f80b04 | 499 | dma_addr_t rx_desc_mapping; |
a2fbb9ea ET |
500 | |
501 | union eth_rx_cqe *rx_comp_ring; | |
34f80b04 EG |
502 | dma_addr_t rx_comp_mapping; |
503 | ||
7a9b2557 VZ |
504 | /* SGE ring */ |
505 | struct eth_rx_sge *rx_sge_ring; | |
506 | dma_addr_t rx_sge_mapping; | |
507 | ||
508 | u64 sge_mask[RX_SGE_MASK_LEN]; | |
509 | ||
619c5cb6 | 510 | u32 cid; |
34f80b04 | 511 | |
6383c0b3 AE |
512 | __le16 fp_hc_idx; |
513 | ||
f85582f8 | 514 | u8 index; /* number in fp array */ |
f233cafe | 515 | u8 rx_queue; /* index for skb_record */ |
f85582f8 | 516 | u8 cl_id; /* eth client id */ |
523224a3 DK |
517 | u8 cl_qzone_id; |
518 | u8 fw_sb_id; /* status block number in FW */ | |
519 | u8 igu_sb_id; /* status block number in HW */ | |
34f80b04 EG |
520 | |
521 | u16 rx_bd_prod; | |
522 | u16 rx_bd_cons; | |
523 | u16 rx_comp_prod; | |
524 | u16 rx_comp_cons; | |
7a9b2557 VZ |
525 | u16 rx_sge_prod; |
526 | /* The last maximal completed SGE */ | |
527 | u16 last_max_sge; | |
4781bfad | 528 | __le16 *rx_cons_sb; |
6383c0b3 | 529 | unsigned long rx_pkt, |
66e855f3 | 530 | rx_calls; |
ab6ad5a4 | 531 | |
7a9b2557 | 532 | /* TPA related */ |
619c5cb6 | 533 | struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; |
7a9b2557 VZ |
534 | u8 disable_tpa; |
535 | #ifdef BNX2X_STOP_ON_ERROR | |
536 | u64 tpa_queue_used; | |
537 | #endif | |
a2fbb9ea | 538 | |
619c5cb6 VZ |
539 | struct tstorm_per_queue_stats old_tclient; |
540 | struct ustorm_per_queue_stats old_uclient; | |
541 | struct xstorm_per_queue_stats old_xclient; | |
de832a55 EG |
542 | struct bnx2x_eth_q_stats eth_q_stats; |
543 | ||
ca00392c EG |
544 | /* The size is calculated using the following: |
545 | sizeof name field from netdev structure + | |
546 | 4 ('-Xx-' string) + | |
547 | 4 (for the digits and to make it DWORD aligned) */ | |
548 | #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) | |
549 | char name[FP_NAME_SIZE]; | |
619c5cb6 VZ |
550 | |
551 | /* MACs object */ | |
552 | struct bnx2x_vlan_mac_obj mac_obj; | |
553 | ||
554 | /* Queue State object */ | |
555 | struct bnx2x_queue_sp_obj q_obj; | |
556 | ||
a2fbb9ea ET |
557 | }; |
558 | ||
34f80b04 | 559 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
a8c94b91 VZ |
560 | |
561 | /* Use 2500 as a mini-jumbo MTU for FCoE */ | |
562 | #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 | |
563 | ||
619c5cb6 | 564 | /* FCoE L2 `fastpath' entry is right after the eth entries */ |
ec6ba945 VZ |
565 | #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) |
566 | #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) | |
567 | #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) | |
6383c0b3 AE |
568 | #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ |
569 | txdata[FIRST_TX_COS_INDEX].var) | |
619c5cb6 VZ |
570 | |
571 | ||
6383c0b3 AE |
572 | #define IS_ETH_FP(fp) (fp->index < \ |
573 | BNX2X_NUM_ETH_QUEUES(fp->bp)) | |
619c5cb6 | 574 | #ifdef BCM_CNIC |
ec6ba945 VZ |
575 | #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) |
576 | #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) | |
577 | #else | |
578 | #define IS_FCOE_FP(fp) false | |
579 | #define IS_FCOE_IDX(idx) false | |
580 | #endif | |
7a9b2557 VZ |
581 | |
582 | ||
583 | /* MC hsi */ | |
619c5cb6 VZ |
584 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ |
585 | #define RX_COPY_THRESH 92 | |
7a9b2557 | 586 | |
619c5cb6 | 587 | #define NUM_TX_RINGS 16 |
ca00392c | 588 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
dfacf138 DK |
589 | #define NEXT_PAGE_TX_DESC_CNT 1 |
590 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) | |
619c5cb6 VZ |
591 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) |
592 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
593 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
7a9b2557 | 594 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
dfacf138 DK |
595 | (MAX_TX_DESC_CNT - 1)) ? \ |
596 | (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ | |
597 | (x) + 1) | |
619c5cb6 VZ |
598 | #define TX_BD(x) ((x) & MAX_TX_BD) |
599 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
7a9b2557 VZ |
600 | |
601 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | |
619c5cb6 | 602 | #define NUM_RX_RINGS 8 |
7a9b2557 | 603 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
dfacf138 DK |
604 | #define NEXT_PAGE_RX_DESC_CNT 2 |
605 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) | |
619c5cb6 VZ |
606 | #define RX_DESC_MASK (RX_DESC_CNT - 1) |
607 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
608 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
609 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
dfacf138 DK |
610 | |
611 | /* dropless fc calculations for BDs | |
612 | * | |
613 | * Number of BDs should as number of buffers in BRB: | |
614 | * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT | |
615 | * "next" elements on each page | |
616 | */ | |
617 | #define NUM_BD_REQ BRB_SIZE(bp) | |
618 | #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ | |
619 | MAX_RX_DESC_CNT) | |
620 | #define BD_TH_LO(bp) (NUM_BD_REQ + \ | |
621 | NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ | |
622 | FW_DROP_LEVEL(bp)) | |
623 | #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) | |
624 | ||
625 | #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) | |
619c5cb6 VZ |
626 | |
627 | #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ | |
628 | ETH_MIN_RX_CQES_WITH_TPA_E1 : \ | |
629 | ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) | |
630 | #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA | |
631 | #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) | |
632 | #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ | |
633 | MIN_RX_AVAIL)) | |
634 | ||
7a9b2557 | 635 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
dfacf138 DK |
636 | (MAX_RX_DESC_CNT - 1)) ? \ |
637 | (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ | |
638 | (x) + 1) | |
619c5cb6 | 639 | #define RX_BD(x) ((x) & MAX_RX_BD) |
7a9b2557 | 640 | |
619c5cb6 VZ |
641 | /* |
642 | * As long as CQE is X times bigger than BD entry we have to allocate X times | |
643 | * more pages for CQ ring in order to keep it balanced with BD ring | |
644 | */ | |
645 | #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) | |
646 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) | |
7a9b2557 | 647 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
dfacf138 DK |
648 | #define NEXT_PAGE_RCQ_DESC_CNT 1 |
649 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) | |
619c5cb6 VZ |
650 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) |
651 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
652 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
7a9b2557 | 653 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ |
dfacf138 DK |
654 | (MAX_RCQ_DESC_CNT - 1)) ? \ |
655 | (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ | |
656 | (x) + 1) | |
619c5cb6 | 657 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) |
7a9b2557 | 658 | |
dfacf138 DK |
659 | /* dropless fc calculations for RCQs |
660 | * | |
661 | * Number of RCQs should be as number of buffers in BRB: | |
662 | * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT | |
663 | * "next" elements on each page | |
664 | */ | |
665 | #define NUM_RCQ_REQ BRB_SIZE(bp) | |
666 | #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ | |
667 | MAX_RCQ_DESC_CNT) | |
668 | #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ | |
669 | NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ | |
670 | FW_DROP_LEVEL(bp)) | |
671 | #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) | |
672 | ||
7a9b2557 | 673 | |
33471629 | 674 | /* This is needed for determining of last_max */ |
619c5cb6 VZ |
675 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
676 | #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) | |
7a9b2557 | 677 | |
7a9b2557 | 678 | |
619c5cb6 VZ |
679 | #define BNX2X_SWCID_SHIFT 17 |
680 | #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) | |
7a9b2557 VZ |
681 | |
682 | /* used on a CID received from the HW */ | |
619c5cb6 | 683 | #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) |
7a9b2557 VZ |
684 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ |
685 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
686 | ||
bb2a0f7a YG |
687 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
688 | le32_to_cpu((bd)->addr_lo)) | |
689 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
690 | ||
523224a3 DK |
691 | #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ |
692 | #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ | |
619c5cb6 VZ |
693 | #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) |
694 | #error "Min DB doorbell stride is 8" | |
695 | #endif | |
7a9b2557 VZ |
696 | #define DPM_TRIGER_TYPE 0x40 |
697 | #define DOORBELL(bp, cid, val) \ | |
698 | do { \ | |
523224a3 | 699 | writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ |
7a9b2557 VZ |
700 | DPM_TRIGER_TYPE); \ |
701 | } while (0) | |
702 | ||
703 | ||
704 | /* TX CSUM helpers */ | |
705 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ | |
706 | skb->csum_offset) | |
707 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | |
708 | skb->csum_offset)) | |
709 | ||
710 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | |
711 | ||
712 | #define XMIT_PLAIN 0 | |
713 | #define XMIT_CSUM_V4 0x1 | |
714 | #define XMIT_CSUM_V6 0x2 | |
715 | #define XMIT_CSUM_TCP 0x4 | |
716 | #define XMIT_GSO_V4 0x8 | |
717 | #define XMIT_GSO_V6 0x10 | |
718 | ||
719 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) | |
720 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) | |
721 | ||
722 | ||
34f80b04 | 723 | /* stuff added to make the code fit 80Col */ |
619c5cb6 VZ |
724 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
725 | #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) | |
726 | #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) | |
727 | #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) | |
728 | #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) | |
7a9b2557 | 729 | |
1adcd8be EG |
730 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
731 | ||
732 | #define BNX2X_IP_CSUM_ERR(cqe) \ | |
733 | (!((cqe)->fast_path_cqe.status_flags & \ | |
734 | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ | |
735 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
736 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) | |
737 | ||
738 | #define BNX2X_L4_CSUM_ERR(cqe) \ | |
739 | (!((cqe)->fast_path_cqe.status_flags & \ | |
740 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ | |
741 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
742 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) | |
743 | ||
744 | #define BNX2X_RX_CSUM_OK(cqe) \ | |
745 | (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) | |
7a9b2557 | 746 | |
052a38e0 EG |
747 | #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ |
748 | (((le16_to_cpu(flags) & \ | |
749 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ | |
750 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ | |
751 | == PRS_FLAG_OVERETH_IPV4) | |
7a9b2557 | 752 | #define BNX2X_RX_SUM_FIX(cqe) \ |
052a38e0 | 753 | BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) |
7a9b2557 | 754 | |
619c5cb6 VZ |
755 | |
756 | #define FP_USB_FUNC_OFF \ | |
757 | offsetof(struct cstorm_status_block_u, func) | |
758 | #define FP_CSB_FUNC_OFF \ | |
759 | offsetof(struct cstorm_status_block_c, func) | |
760 | ||
150966ad | 761 | #define HC_INDEX_ETH_RX_CQ_CONS 1 |
619c5cb6 | 762 | |
150966ad | 763 | #define HC_INDEX_OOO_TX_CQ_CONS 4 |
6383c0b3 | 764 | |
150966ad AE |
765 | #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 |
766 | ||
767 | #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 | |
6383c0b3 | 768 | |
150966ad AE |
769 | #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 |
770 | ||
771 | #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 | |
a2fbb9ea | 772 | |
34f80b04 | 773 | #define BNX2X_RX_SB_INDEX \ |
619c5cb6 | 774 | (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) |
a2fbb9ea | 775 | |
6383c0b3 AE |
776 | #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 |
777 | ||
778 | #define BNX2X_TX_SB_INDEX_COS0 \ | |
779 | (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) | |
7a9b2557 VZ |
780 | |
781 | /* end of fast path */ | |
782 | ||
34f80b04 | 783 | /* common */ |
a2fbb9ea | 784 | |
34f80b04 | 785 | struct bnx2x_common { |
a2fbb9ea | 786 | |
ad8d3948 | 787 | u32 chip_id; |
a2fbb9ea | 788 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
34f80b04 | 789 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
ad8d3948 | 790 | |
34f80b04 | 791 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
ad8d3948 EG |
792 | #define CHIP_NUM_57710 0x164e |
793 | #define CHIP_NUM_57711 0x164f | |
794 | #define CHIP_NUM_57711E 0x1650 | |
f2e0899f | 795 | #define CHIP_NUM_57712 0x1662 |
619c5cb6 VZ |
796 | #define CHIP_NUM_57712_MF 0x1663 |
797 | #define CHIP_NUM_57713 0x1651 | |
798 | #define CHIP_NUM_57713E 0x1652 | |
799 | #define CHIP_NUM_57800 0x168a | |
800 | #define CHIP_NUM_57800_MF 0x16a5 | |
801 | #define CHIP_NUM_57810 0x168e | |
802 | #define CHIP_NUM_57810_MF 0x16ae | |
803 | #define CHIP_NUM_57840 0x168d | |
804 | #define CHIP_NUM_57840_MF 0x16ab | |
ad8d3948 EG |
805 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) |
806 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
807 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
f2e0899f | 808 | #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) |
619c5cb6 VZ |
809 | #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) |
810 | #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) | |
811 | #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) | |
812 | #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) | |
813 | #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) | |
814 | #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840) | |
815 | #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF) | |
ad8d3948 EG |
816 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ |
817 | CHIP_IS_57711E(bp)) | |
f2e0899f | 818 | #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ |
619c5cb6 VZ |
819 | CHIP_IS_57712_MF(bp)) |
820 | #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ | |
821 | CHIP_IS_57800_MF(bp) || \ | |
822 | CHIP_IS_57810(bp) || \ | |
823 | CHIP_IS_57810_MF(bp) || \ | |
824 | CHIP_IS_57840(bp) || \ | |
825 | CHIP_IS_57840_MF(bp)) | |
f2e0899f | 826 | #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) |
619c5cb6 VZ |
827 | #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) |
828 | #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) | |
829 | ||
830 | #define CHIP_REV_SHIFT 12 | |
831 | #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) | |
832 | #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) | |
833 | #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) | |
834 | #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) | |
ad8d3948 | 835 | /* assume maximum 5 revisions */ |
619c5cb6 | 836 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) |
ad8d3948 EG |
837 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ |
838 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
619c5cb6 | 839 | !(CHIP_REV_VAL(bp) & 0x00001000)) |
ad8d3948 EG |
840 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ |
841 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
619c5cb6 | 842 | (CHIP_REV_VAL(bp) & 0x00001000)) |
ad8d3948 EG |
843 | |
844 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
845 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
846 | ||
34f80b04 EG |
847 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
848 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
619c5cb6 VZ |
849 | #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ |
850 | (CHIP_REV_SHIFT + 1)) \ | |
851 | << CHIP_REV_SHIFT) | |
852 | #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ | |
853 | CHIP_REV_SIM(bp) :\ | |
854 | CHIP_REV_VAL(bp)) | |
855 | #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ | |
856 | (CHIP_REV(bp) == CHIP_REV_Bx)) | |
857 | #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ | |
858 | (CHIP_REV(bp) == CHIP_REV_Ax)) | |
a2fbb9ea | 859 | |
34f80b04 | 860 | int flash_size; |
754a2f52 DK |
861 | #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ |
862 | #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 | |
863 | #define BNX2X_NVRAM_PAGE_SIZE 256 | |
a2fbb9ea | 864 | |
34f80b04 | 865 | u32 shmem_base; |
2691d51d | 866 | u32 shmem2_base; |
523224a3 | 867 | u32 mf_cfg_base; |
f2e0899f | 868 | u32 mf2_cfg_base; |
34f80b04 EG |
869 | |
870 | u32 hw_config; | |
c18487ee | 871 | |
34f80b04 | 872 | u32 bc_ver; |
523224a3 DK |
873 | |
874 | u8 int_block; | |
875 | #define INT_BLOCK_HC 0 | |
f2e0899f DK |
876 | #define INT_BLOCK_IGU 1 |
877 | #define INT_BLOCK_MODE_NORMAL 0 | |
878 | #define INT_BLOCK_MODE_BW_COMP 2 | |
879 | #define CHIP_INT_MODE_IS_NBC(bp) \ | |
619c5cb6 | 880 | (!CHIP_IS_E1x(bp) && \ |
f2e0899f DK |
881 | !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) |
882 | #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) | |
883 | ||
523224a3 | 884 | u8 chip_port_mode; |
f2e0899f DK |
885 | #define CHIP_4_PORT_MODE 0x0 |
886 | #define CHIP_2_PORT_MODE 0x1 | |
523224a3 | 887 | #define CHIP_PORT_MODE_NONE 0x2 |
f2e0899f DK |
888 | #define CHIP_MODE(bp) (bp->common.chip_port_mode) |
889 | #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) | |
34f80b04 | 890 | }; |
c18487ee | 891 | |
f2e0899f DK |
892 | /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ |
893 | #define BNX2X_IGU_STAS_MSG_VF_CNT 64 | |
894 | #define BNX2X_IGU_STAS_MSG_PF_CNT 4 | |
34f80b04 EG |
895 | |
896 | /* end of common */ | |
897 | ||
898 | /* port */ | |
899 | ||
900 | struct bnx2x_port { | |
901 | u32 pmf; | |
c18487ee | 902 | |
a22f0788 | 903 | u32 link_config[LINK_CONFIG_SIZE]; |
a2fbb9ea | 904 | |
a22f0788 | 905 | u32 supported[LINK_CONFIG_SIZE]; |
34f80b04 EG |
906 | /* link settings - missing defines */ |
907 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
908 | ||
a22f0788 | 909 | u32 advertising[LINK_CONFIG_SIZE]; |
a2fbb9ea | 910 | /* link settings - missing defines */ |
34f80b04 | 911 | #define ADVERTISED_2500baseX_Full (1 << 15) |
a2fbb9ea | 912 | |
34f80b04 | 913 | u32 phy_addr; |
c18487ee YR |
914 | |
915 | /* used to synchronize phy accesses */ | |
916 | struct mutex phy_mutex; | |
46c6a674 | 917 | int need_hw_lock; |
c18487ee | 918 | |
34f80b04 | 919 | u32 port_stx; |
a2fbb9ea | 920 | |
34f80b04 EG |
921 | struct nig_stats old_nig_stats; |
922 | }; | |
a2fbb9ea | 923 | |
34f80b04 EG |
924 | /* end of port */ |
925 | ||
619c5cb6 VZ |
926 | #define STATS_OFFSET32(stat_name) \ |
927 | (offsetof(struct bnx2x_eth_stats, stat_name) / 4) | |
bb2a0f7a | 928 | |
619c5cb6 VZ |
929 | /* slow path */ |
930 | ||
931 | /* slow path work-queue */ | |
932 | extern struct workqueue_struct *bnx2x_wq; | |
933 | ||
934 | #define BNX2X_MAX_NUM_OF_VFS 64 | |
523224a3 | 935 | #define BNX2X_VF_ID_INVALID 0xFF |
34f80b04 | 936 | |
523224a3 DK |
937 | /* |
938 | * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is | |
939 | * control by the number of fast-path status blocks supported by the | |
940 | * device (HW/FW). Each fast-path status block (FP-SB) aka non-default | |
941 | * status block represents an independent interrupts context that can | |
942 | * serve a regular L2 networking queue. However special L2 queues such | |
943 | * as the FCoE queue do not require a FP-SB and other components like | |
944 | * the CNIC may consume FP-SB reducing the number of possible L2 queues | |
945 | * | |
946 | * If the maximum number of FP-SB available is X then: | |
947 | * a. If CNIC is supported it consumes 1 FP-SB thus the max number of | |
948 | * regular L2 queues is Y=X-1 | |
949 | * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) | |
950 | * c. If the FCoE L2 queue is supported the actual number of L2 queues | |
951 | * is Y+1 | |
952 | * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for | |
953 | * slow-path interrupts) or Y+2 if CNIC is supported (one additional | |
954 | * FP interrupt context for the CNIC). | |
955 | * e. The number of HW context (CID count) is always X or X+1 if FCoE | |
956 | * L2 queue is supported. the cid for the FCoE L2 queue is always X. | |
957 | */ | |
958 | ||
619c5cb6 VZ |
959 | /* fast-path interrupt contexts E1x */ |
960 | #define FP_SB_MAX_E1x 16 | |
961 | /* fast-path interrupt contexts E2 */ | |
962 | #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 | |
523224a3 | 963 | |
34f80b04 EG |
964 | union cdu_context { |
965 | struct eth_context eth; | |
966 | char pad[1024]; | |
967 | }; | |
968 | ||
523224a3 DK |
969 | /* CDU host DB constants */ |
970 | #define CDU_ILT_PAGE_SZ_HW 3 | |
6383c0b3 | 971 | #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */ |
523224a3 DK |
972 | #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) |
973 | ||
974 | #ifdef BCM_CNIC | |
975 | #define CNIC_ISCSI_CID_MAX 256 | |
ec6ba945 VZ |
976 | #define CNIC_FCOE_CID_MAX 2048 |
977 | #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) | |
523224a3 DK |
978 | #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) |
979 | #endif | |
980 | ||
619c5cb6 VZ |
981 | #define QM_ILT_PAGE_SZ_HW 0 |
982 | #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
983 | #define QM_CID_ROUND 1024 |
984 | ||
985 | #ifdef BCM_CNIC | |
986 | /* TM (timers) host DB constants */ | |
619c5cb6 VZ |
987 | #define TM_ILT_PAGE_SZ_HW 0 |
988 | #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
989 | /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ |
990 | #define TM_CONN_NUM 1024 | |
991 | #define TM_ILT_SZ (8 * TM_CONN_NUM) | |
992 | #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) | |
993 | ||
994 | /* SRC (Searcher) host DB constants */ | |
619c5cb6 VZ |
995 | #define SRC_ILT_PAGE_SZ_HW 0 |
996 | #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
997 | #define SRC_HASH_BITS 10 |
998 | #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ | |
999 | #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) | |
1000 | #define SRC_T2_SZ SRC_ILT_SZ | |
1001 | #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) | |
619c5cb6 | 1002 | |
523224a3 DK |
1003 | #endif |
1004 | ||
619c5cb6 | 1005 | #define MAX_DMAE_C 8 |
34f80b04 EG |
1006 | |
1007 | /* DMA memory not used in fastpath */ | |
1008 | struct bnx2x_slowpath { | |
619c5cb6 VZ |
1009 | union { |
1010 | struct mac_configuration_cmd e1x; | |
1011 | struct eth_classify_rules_ramrod_data e2; | |
1012 | } mac_rdata; | |
1013 | ||
1014 | ||
1015 | union { | |
1016 | struct tstorm_eth_mac_filter_config e1x; | |
1017 | struct eth_filter_rules_ramrod_data e2; | |
1018 | } rx_mode_rdata; | |
1019 | ||
1020 | union { | |
1021 | struct mac_configuration_cmd e1; | |
1022 | struct eth_multicast_rules_ramrod_data e2; | |
1023 | } mcast_rdata; | |
1024 | ||
1025 | struct eth_rss_update_ramrod_data rss_rdata; | |
1026 | ||
1027 | /* Queue State related ramrods are always sent under rtnl_lock */ | |
1028 | union { | |
1029 | struct client_init_ramrod_data init_data; | |
1030 | struct client_update_ramrod_data update_data; | |
1031 | } q_rdata; | |
1032 | ||
1033 | union { | |
1034 | struct function_start_data func_start; | |
6debea87 DK |
1035 | /* pfc configuration for DCBX ramrod */ |
1036 | struct flow_control_configuration pfc_config; | |
619c5cb6 | 1037 | } func_rdata; |
34f80b04 EG |
1038 | |
1039 | /* used by dmae command executer */ | |
1040 | struct dmae_command dmae[MAX_DMAE_C]; | |
1041 | ||
bb2a0f7a YG |
1042 | u32 stats_comp; |
1043 | union mac_stats mac_stats; | |
1044 | struct nig_stats nig_stats; | |
1045 | struct host_port_stats port_stats; | |
1046 | struct host_func_stats func_stats; | |
6fe49bb9 | 1047 | struct host_func_stats func_stats_base; |
34f80b04 EG |
1048 | |
1049 | u32 wb_comp; | |
34f80b04 EG |
1050 | u32 wb_data[4]; |
1051 | }; | |
1052 | ||
1053 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
1054 | #define bnx2x_sp_mapping(bp, var) \ | |
1055 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
1056 | ||
1057 | ||
1058 | /* attn group wiring */ | |
1059 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
1060 | ||
1061 | struct attn_route { | |
619c5cb6 | 1062 | u32 sig[5]; |
34f80b04 EG |
1063 | }; |
1064 | ||
523224a3 DK |
1065 | struct iro { |
1066 | u32 base; | |
1067 | u16 m1; | |
1068 | u16 m2; | |
1069 | u16 m3; | |
1070 | u16 size; | |
1071 | }; | |
1072 | ||
1073 | struct hw_context { | |
1074 | union cdu_context *vcxt; | |
1075 | dma_addr_t cxt_mapping; | |
1076 | size_t size; | |
1077 | }; | |
1078 | ||
1079 | /* forward */ | |
1080 | struct bnx2x_ilt; | |
1081 | ||
c9ee9206 VZ |
1082 | |
1083 | enum bnx2x_recovery_state { | |
72fd0718 VZ |
1084 | BNX2X_RECOVERY_DONE, |
1085 | BNX2X_RECOVERY_INIT, | |
1086 | BNX2X_RECOVERY_WAIT, | |
c9ee9206 VZ |
1087 | BNX2X_RECOVERY_FAILED |
1088 | }; | |
72fd0718 | 1089 | |
619c5cb6 | 1090 | /* |
523224a3 DK |
1091 | * Event queue (EQ or event ring) MC hsi |
1092 | * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 | |
1093 | */ | |
1094 | #define NUM_EQ_PAGES 1 | |
1095 | #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) | |
1096 | #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) | |
1097 | #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) | |
1098 | #define EQ_DESC_MASK (NUM_EQ_DESC - 1) | |
1099 | #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) | |
1100 | ||
1101 | /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ | |
1102 | #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ | |
1103 | (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) | |
1104 | ||
1105 | /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ | |
1106 | #define EQ_DESC(x) ((x) & EQ_DESC_MASK) | |
1107 | ||
1108 | #define BNX2X_EQ_INDEX \ | |
1109 | (&bp->def_status_blk->sp_sb.\ | |
1110 | index_values[HC_SP_INDEX_EQ_CONS]) | |
1111 | ||
2ae17f66 VZ |
1112 | /* This is a data that will be used to create a link report message. |
1113 | * We will keep the data used for the last link report in order | |
1114 | * to prevent reporting the same link parameters twice. | |
1115 | */ | |
1116 | struct bnx2x_link_report_data { | |
1117 | u16 line_speed; /* Effective line speed */ | |
1118 | unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ | |
1119 | }; | |
1120 | ||
1121 | enum { | |
1122 | BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ | |
1123 | BNX2X_LINK_REPORT_LINK_DOWN, | |
1124 | BNX2X_LINK_REPORT_RX_FC_ON, | |
1125 | BNX2X_LINK_REPORT_TX_FC_ON, | |
1126 | }; | |
1127 | ||
619c5cb6 VZ |
1128 | enum { |
1129 | BNX2X_PORT_QUERY_IDX, | |
1130 | BNX2X_PF_QUERY_IDX, | |
1131 | BNX2X_FIRST_QUEUE_QUERY_IDX, | |
1132 | }; | |
1133 | ||
1134 | struct bnx2x_fw_stats_req { | |
1135 | struct stats_query_header hdr; | |
1136 | struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; | |
1137 | }; | |
1138 | ||
1139 | struct bnx2x_fw_stats_data { | |
1140 | struct stats_counter storm_counters; | |
1141 | struct per_port_stats port; | |
1142 | struct per_pf_stats pf; | |
1143 | struct per_queue_stats queue_stats[1]; | |
1144 | }; | |
1145 | ||
7be08a72 AE |
1146 | /* Public slow path states */ |
1147 | enum { | |
6383c0b3 | 1148 | BNX2X_SP_RTNL_SETUP_TC, |
7be08a72 | 1149 | BNX2X_SP_RTNL_TX_TIMEOUT, |
8304859a | 1150 | BNX2X_SP_RTNL_FAN_FAILURE, |
7be08a72 AE |
1151 | }; |
1152 | ||
1153 | ||
34f80b04 EG |
1154 | struct bnx2x { |
1155 | /* Fields used in the tx and intr/napi performance paths | |
1156 | * are grouped together in the beginning of the structure | |
1157 | */ | |
523224a3 | 1158 | struct bnx2x_fastpath *fp; |
34f80b04 EG |
1159 | void __iomem *regview; |
1160 | void __iomem *doorbells; | |
523224a3 | 1161 | u16 db_size; |
34f80b04 | 1162 | |
619c5cb6 VZ |
1163 | u8 pf_num; /* absolute PF number */ |
1164 | u8 pfid; /* per-path PF number */ | |
1165 | int base_fw_ndsb; /**/ | |
1166 | #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) | |
1167 | #define BP_PORT(bp) (bp->pfid & 1) | |
1168 | #define BP_FUNC(bp) (bp->pfid) | |
1169 | #define BP_ABS_FUNC(bp) (bp->pf_num) | |
3395a033 DK |
1170 | #define BP_VN(bp) ((bp)->pfid >> 1) |
1171 | #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) | |
1172 | #define BP_L_ID(bp) (BP_VN(bp) << 2) | |
1173 | #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ | |
1174 | (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) | |
1175 | #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) | |
619c5cb6 | 1176 | |
34f80b04 EG |
1177 | struct net_device *dev; |
1178 | struct pci_dev *pdev; | |
1179 | ||
619c5cb6 | 1180 | const struct iro *iro_arr; |
523224a3 DK |
1181 | #define IRO (bp->iro_arr) |
1182 | ||
c9ee9206 | 1183 | enum bnx2x_recovery_state recovery_state; |
72fd0718 | 1184 | int is_leader; |
523224a3 | 1185 | struct msix_entry *msix_table; |
34f80b04 EG |
1186 | |
1187 | int tx_ring_size; | |
1188 | ||
523224a3 DK |
1189 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
1190 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
34f80b04 EG |
1191 | #define ETH_MIN_PACKET_SIZE 60 |
1192 | #define ETH_MAX_PACKET_SIZE 1500 | |
1193 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
a2fbb9ea | 1194 | |
0f00846d | 1195 | /* Max supported alignment is 256 (8 shift) */ |
e52fcb24 ED |
1196 | #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) |
1197 | ||
1198 | /* FW uses 2 Cache lines Alignment for start packet and size | |
1199 | * | |
1200 | * We assume skb_build() uses sizeof(struct skb_shared_info) bytes | |
1201 | * at the end of skb->data, to avoid wasting a full cache line. | |
1202 | * This reduces memory use (skb->truesize). | |
1203 | */ | |
1204 | #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) | |
1205 | ||
1206 | #define BNX2X_FW_RX_ALIGN_END \ | |
1207 | max(1UL << BNX2X_RX_ALIGN_SHIFT, \ | |
1208 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1209 | ||
523224a3 | 1210 | #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) |
0f00846d | 1211 | |
523224a3 DK |
1212 | struct host_sp_status_block *def_status_blk; |
1213 | #define DEF_SB_IGU_ID 16 | |
1214 | #define DEF_SB_ID HC_SP_SB_ID | |
1215 | __le16 def_idx; | |
4781bfad | 1216 | __le16 def_att_idx; |
34f80b04 EG |
1217 | u32 attn_state; |
1218 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
34f80b04 EG |
1219 | |
1220 | /* slow path ring */ | |
1221 | struct eth_spe *spq; | |
1222 | dma_addr_t spq_mapping; | |
1223 | u16 spq_prod_idx; | |
1224 | struct eth_spe *spq_prod_bd; | |
1225 | struct eth_spe *spq_last_bd; | |
4781bfad | 1226 | __le16 *dsb_sp_prod; |
6e30dd4e | 1227 | atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ |
34f80b04 EG |
1228 | /* used to synchronize spq accesses */ |
1229 | spinlock_t spq_lock; | |
1230 | ||
523224a3 DK |
1231 | /* event queue */ |
1232 | union event_ring_elem *eq_ring; | |
1233 | dma_addr_t eq_mapping; | |
1234 | u16 eq_prod; | |
1235 | u16 eq_cons; | |
1236 | __le16 *eq_cons_sb; | |
6e30dd4e | 1237 | atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ |
523224a3 | 1238 | |
619c5cb6 VZ |
1239 | |
1240 | ||
1241 | /* Counter for marking that there is a STAT_QUERY ramrod pending */ | |
1242 | u16 stats_pending; | |
1243 | /* Counter for completed statistics ramrods */ | |
1244 | u16 stats_comp; | |
34f80b04 | 1245 | |
33471629 | 1246 | /* End of fields used in the performance code paths */ |
34f80b04 EG |
1247 | |
1248 | int panic; | |
7995c64e | 1249 | int msg_enable; |
34f80b04 EG |
1250 | |
1251 | u32 flags; | |
619c5cb6 VZ |
1252 | #define PCIX_FLAG (1 << 0) |
1253 | #define PCI_32BIT_FLAG (1 << 1) | |
1254 | #define ONE_PORT_FLAG (1 << 2) | |
1255 | #define NO_WOL_FLAG (1 << 3) | |
1256 | #define USING_DAC_FLAG (1 << 4) | |
1257 | #define USING_MSIX_FLAG (1 << 5) | |
1258 | #define USING_MSI_FLAG (1 << 6) | |
1259 | #define DISABLE_MSI_FLAG (1 << 7) | |
1260 | #define TPA_ENABLE_FLAG (1 << 8) | |
1261 | #define NO_MCP_FLAG (1 << 9) | |
1262 | ||
34f80b04 | 1263 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) |
619c5cb6 VZ |
1264 | #define MF_FUNC_DIS (1 << 11) |
1265 | #define OWN_CNIC_IRQ (1 << 12) | |
1266 | #define NO_ISCSI_OOO_FLAG (1 << 13) | |
1267 | #define NO_ISCSI_FLAG (1 << 14) | |
1268 | #define NO_FCOE_FLAG (1 << 15) | |
ec6ba945 | 1269 | |
2ba45142 VZ |
1270 | #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) |
1271 | #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) | |
619c5cb6 | 1272 | #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) |
37b091ba | 1273 | |
34f80b04 | 1274 | int pm_cap; |
8d5726c4 | 1275 | int mrrs; |
34f80b04 | 1276 | |
1cf167f2 | 1277 | struct delayed_work sp_task; |
7be08a72 | 1278 | struct delayed_work sp_rtnl_task; |
3deb8167 YR |
1279 | |
1280 | struct delayed_work period_task; | |
34f80b04 | 1281 | struct timer_list timer; |
34f80b04 EG |
1282 | int current_interval; |
1283 | ||
1284 | u16 fw_seq; | |
1285 | u16 fw_drv_pulse_wr_seq; | |
1286 | u32 func_stx; | |
1287 | ||
1288 | struct link_params link_params; | |
1289 | struct link_vars link_vars; | |
2ae17f66 VZ |
1290 | u32 link_cnt; |
1291 | struct bnx2x_link_report_data last_reported_link; | |
1292 | ||
01cd4528 | 1293 | struct mdio_if_info mdio; |
a2fbb9ea | 1294 | |
34f80b04 EG |
1295 | struct bnx2x_common common; |
1296 | struct bnx2x_port port; | |
1297 | ||
8a1c38d1 EG |
1298 | struct cmng_struct_per_port cmng; |
1299 | u32 vn_weight_sum; | |
f2e0899f DK |
1300 | u32 mf_config[E1HVN_MAX]; |
1301 | u32 mf2_config[E2_FUNC_MAX]; | |
619c5cb6 | 1302 | u32 path_has_ovlan; /* E3 */ |
fb3bff17 DK |
1303 | u16 mf_ov; |
1304 | u8 mf_mode; | |
f85582f8 | 1305 | #define IS_MF(bp) (bp->mf_mode != 0) |
0793f83f DK |
1306 | #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) |
1307 | #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) | |
a2fbb9ea | 1308 | |
f1410647 ET |
1309 | u8 wol; |
1310 | ||
34f80b04 | 1311 | int rx_ring_size; |
a2fbb9ea | 1312 | |
34f80b04 EG |
1313 | u16 tx_quick_cons_trip_int; |
1314 | u16 tx_quick_cons_trip; | |
1315 | u16 tx_ticks_int; | |
1316 | u16 tx_ticks; | |
a2fbb9ea | 1317 | |
34f80b04 EG |
1318 | u16 rx_quick_cons_trip_int; |
1319 | u16 rx_quick_cons_trip; | |
1320 | u16 rx_ticks_int; | |
1321 | u16 rx_ticks; | |
cdaa7cb8 VZ |
1322 | /* Maximal coalescing timeout in us */ |
1323 | #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) | |
a2fbb9ea | 1324 | |
34f80b04 | 1325 | u32 lin_cnt; |
a2fbb9ea | 1326 | |
619c5cb6 | 1327 | u16 state; |
356e2385 | 1328 | #define BNX2X_STATE_CLOSED 0 |
34f80b04 EG |
1329 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
1330 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
a2fbb9ea | 1331 | #define BNX2X_STATE_OPEN 0x3000 |
34f80b04 | 1332 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
a2fbb9ea | 1333 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
619c5cb6 | 1334 | |
34f80b04 EG |
1335 | #define BNX2X_STATE_DIAG 0xe000 |
1336 | #define BNX2X_STATE_ERROR 0xf000 | |
a2fbb9ea | 1337 | |
555f6c78 | 1338 | int multi_mode; |
6383c0b3 AE |
1339 | #define BNX2X_MAX_PRIORITY 8 |
1340 | #define BNX2X_MAX_ENTRIES_PER_PRI 16 | |
1341 | #define BNX2X_MAX_COS 3 | |
1342 | #define BNX2X_MAX_TX_COS 2 | |
54b9ddaa | 1343 | int num_queues; |
5d7cd496 | 1344 | int disable_tpa; |
523224a3 | 1345 | |
34f80b04 EG |
1346 | u32 rx_mode; |
1347 | #define BNX2X_RX_MODE_NONE 0 | |
1348 | #define BNX2X_RX_MODE_NORMAL 1 | |
1349 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
1350 | #define BNX2X_RX_MODE_PROMISC 3 | |
1351 | #define BNX2X_MAX_MULTICAST 64 | |
a2fbb9ea | 1352 | |
523224a3 DK |
1353 | u8 igu_dsb_id; |
1354 | u8 igu_base_sb; | |
1355 | u8 igu_sb_cnt; | |
34f80b04 | 1356 | dma_addr_t def_status_blk_mapping; |
a2fbb9ea | 1357 | |
34f80b04 EG |
1358 | struct bnx2x_slowpath *slowpath; |
1359 | dma_addr_t slowpath_mapping; | |
619c5cb6 VZ |
1360 | |
1361 | /* Total number of FW statistics requests */ | |
1362 | u8 fw_stats_num; | |
1363 | ||
1364 | /* | |
1365 | * This is a memory buffer that will contain both statistics | |
1366 | * ramrod request and data. | |
1367 | */ | |
1368 | void *fw_stats; | |
1369 | dma_addr_t fw_stats_mapping; | |
1370 | ||
1371 | /* | |
1372 | * FW statistics request shortcut (points at the | |
1373 | * beginning of fw_stats buffer). | |
1374 | */ | |
1375 | struct bnx2x_fw_stats_req *fw_stats_req; | |
1376 | dma_addr_t fw_stats_req_mapping; | |
1377 | int fw_stats_req_sz; | |
1378 | ||
1379 | /* | |
1380 | * FW statistics data shortcut (points at the begining of | |
1381 | * fw_stats buffer + fw_stats_req_sz). | |
1382 | */ | |
1383 | struct bnx2x_fw_stats_data *fw_stats_data; | |
1384 | dma_addr_t fw_stats_data_mapping; | |
1385 | int fw_stats_data_sz; | |
1386 | ||
523224a3 DK |
1387 | struct hw_context context; |
1388 | ||
1389 | struct bnx2x_ilt *ilt; | |
1390 | #define BP_ILT(bp) ((bp)->ilt) | |
619c5cb6 | 1391 | #define ILT_MAX_LINES 256 |
6383c0b3 AE |
1392 | /* |
1393 | * Maximum supported number of RSS queues: number of IGU SBs minus one that goes | |
1394 | * to CNIC. | |
1395 | */ | |
1396 | #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT) | |
523224a3 | 1397 | |
6383c0b3 AE |
1398 | /* |
1399 | * Maximum CID count that might be required by the bnx2x: | |
1400 | * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related) | |
1401 | */ | |
1402 | #define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\ | |
1403 | NON_ETH_CONTEXT_USE + CNIC_PRESENT) | |
1404 | #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ | |
1405 | ILT_PAGE_CIDS)) | |
1406 | #define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT)) | |
523224a3 DK |
1407 | |
1408 | int qm_cid_count; | |
a2fbb9ea | 1409 | |
a18f5128 EG |
1410 | int dropless_fc; |
1411 | ||
37b091ba MC |
1412 | #ifdef BCM_CNIC |
1413 | u32 cnic_flags; | |
1414 | #define BNX2X_CNIC_FLAG_MAC_SET 1 | |
37b091ba MC |
1415 | void *t2; |
1416 | dma_addr_t t2_mapping; | |
13707f9e | 1417 | struct cnic_ops __rcu *cnic_ops; |
37b091ba MC |
1418 | void *cnic_data; |
1419 | u32 cnic_tag; | |
1420 | struct cnic_eth_dev cnic_eth_dev; | |
523224a3 | 1421 | union host_hc_status_block cnic_sb; |
37b091ba | 1422 | dma_addr_t cnic_sb_mapping; |
37b091ba MC |
1423 | struct eth_spe *cnic_kwq; |
1424 | struct eth_spe *cnic_kwq_prod; | |
1425 | struct eth_spe *cnic_kwq_cons; | |
1426 | struct eth_spe *cnic_kwq_last; | |
1427 | u16 cnic_kwq_pending; | |
1428 | u16 cnic_spq_pending; | |
ec6ba945 | 1429 | u8 fip_mac[ETH_ALEN]; |
619c5cb6 VZ |
1430 | struct mutex cnic_mutex; |
1431 | struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; | |
1432 | ||
1433 | /* Start index of the "special" (CNIC related) L2 cleints */ | |
1434 | u8 cnic_base_cl_id; | |
37b091ba MC |
1435 | #endif |
1436 | ||
ad8d3948 EG |
1437 | int dmae_ready; |
1438 | /* used to synchronize dmae accesses */ | |
6e30dd4e | 1439 | spinlock_t dmae_lock; |
ad8d3948 | 1440 | |
c4ff7cbf EG |
1441 | /* used to protect the FW mail box */ |
1442 | struct mutex fw_mb_mutex; | |
1443 | ||
bb2a0f7a YG |
1444 | /* used to synchronize stats collecting */ |
1445 | int stats_state; | |
a13773a5 VZ |
1446 | |
1447 | /* used for synchronization of concurrent threads statistics handling */ | |
1448 | spinlock_t stats_lock; | |
1449 | ||
bb2a0f7a YG |
1450 | /* used by dmae command loader */ |
1451 | struct dmae_command stats_dmae; | |
1452 | int executer_idx; | |
ad8d3948 | 1453 | |
bb2a0f7a | 1454 | u16 stats_counter; |
bb2a0f7a YG |
1455 | struct bnx2x_eth_stats eth_stats; |
1456 | ||
1457 | struct z_stream_s *strm; | |
1458 | void *gunzip_buf; | |
1459 | dma_addr_t gunzip_mapping; | |
1460 | int gunzip_outlen; | |
ad8d3948 | 1461 | #define FW_BUF_SIZE 0x8000 |
573f2035 EG |
1462 | #define GUNZIP_BUF(bp) (bp->gunzip_buf) |
1463 | #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) | |
1464 | #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) | |
a2fbb9ea | 1465 | |
ab6ad5a4 | 1466 | struct raw_op *init_ops; |
94a78b79 | 1467 | /* Init blocks offsets inside init_ops */ |
ab6ad5a4 | 1468 | u16 *init_ops_offsets; |
94a78b79 | 1469 | /* Data blob - has 32 bit granularity */ |
ab6ad5a4 | 1470 | u32 *init_data; |
619c5cb6 VZ |
1471 | u32 init_mode_flags; |
1472 | #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) | |
94a78b79 | 1473 | /* Zipped PRAM blobs - raw data */ |
ab6ad5a4 EG |
1474 | const u8 *tsem_int_table_data; |
1475 | const u8 *tsem_pram_data; | |
1476 | const u8 *usem_int_table_data; | |
1477 | const u8 *usem_pram_data; | |
1478 | const u8 *xsem_int_table_data; | |
1479 | const u8 *xsem_pram_data; | |
1480 | const u8 *csem_int_table_data; | |
1481 | const u8 *csem_pram_data; | |
573f2035 EG |
1482 | #define INIT_OPS(bp) (bp->init_ops) |
1483 | #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) | |
1484 | #define INIT_DATA(bp) (bp->init_data) | |
1485 | #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) | |
1486 | #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) | |
1487 | #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) | |
1488 | #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) | |
1489 | #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) | |
1490 | #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) | |
1491 | #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) | |
1492 | #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) | |
1493 | ||
619c5cb6 | 1494 | #define PHY_FW_VER_LEN 20 |
34f24c7f | 1495 | char fw_ver[32]; |
ab6ad5a4 | 1496 | const struct firmware *firmware; |
619c5cb6 | 1497 | |
785b9b1a SR |
1498 | /* DCB support on/off */ |
1499 | u16 dcb_state; | |
1500 | #define BNX2X_DCB_STATE_OFF 0 | |
1501 | #define BNX2X_DCB_STATE_ON 1 | |
1502 | ||
1503 | /* DCBX engine mode */ | |
1504 | int dcbx_enabled; | |
1505 | #define BNX2X_DCBX_ENABLED_OFF 0 | |
1506 | #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 | |
1507 | #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 | |
1508 | #define BNX2X_DCBX_ENABLED_INVALID (-1) | |
1509 | ||
1510 | bool dcbx_mode_uset; | |
1511 | ||
e4901dde | 1512 | struct bnx2x_config_dcbx_params dcbx_config_params; |
e4901dde VZ |
1513 | struct bnx2x_dcbx_port_params dcbx_port_params; |
1514 | int dcb_version; | |
1515 | ||
619c5cb6 VZ |
1516 | /* CAM credit pools */ |
1517 | struct bnx2x_credit_pool_obj macs_pool; | |
1518 | ||
1519 | /* RX_MODE object */ | |
1520 | struct bnx2x_rx_mode_obj rx_mode_obj; | |
1521 | ||
1522 | /* MCAST object */ | |
1523 | struct bnx2x_mcast_obj mcast_obj; | |
1524 | ||
1525 | /* RSS configuration object */ | |
1526 | struct bnx2x_rss_config_obj rss_conf_obj; | |
1527 | ||
1528 | /* Function State controlling object */ | |
1529 | struct bnx2x_func_sp_obj func_obj; | |
1530 | ||
1531 | unsigned long sp_state; | |
1532 | ||
7be08a72 AE |
1533 | /* operation indication for the sp_rtnl task */ |
1534 | unsigned long sp_rtnl_state; | |
1535 | ||
619c5cb6 | 1536 | /* DCBX Negotation results */ |
e4901dde VZ |
1537 | struct dcbx_features dcbx_local_feat; |
1538 | u32 dcbx_error; | |
619c5cb6 | 1539 | |
0be6bc62 SR |
1540 | #ifdef BCM_DCBNL |
1541 | struct dcbx_features dcbx_remote_feat; | |
1542 | u32 dcbx_remote_flags; | |
1543 | #endif | |
e3835b99 | 1544 | u32 pending_max; |
6383c0b3 AE |
1545 | |
1546 | /* multiple tx classes of service */ | |
1547 | u8 max_cos; | |
1548 | ||
1549 | /* priority to cos mapping */ | |
1550 | u8 prio_to_cos[8]; | |
a2fbb9ea ET |
1551 | }; |
1552 | ||
619c5cb6 VZ |
1553 | /* Tx queues may be less or equal to Rx queues */ |
1554 | extern int num_queues; | |
54b9ddaa | 1555 | #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) |
6383c0b3 AE |
1556 | #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE) |
1557 | #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) | |
ec6ba945 | 1558 | |
54b9ddaa | 1559 | #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) |
3196a88a | 1560 | |
6383c0b3 AE |
1561 | #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) |
1562 | /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ | |
523224a3 DK |
1563 | |
1564 | #define RSS_IPV4_CAP_MASK \ | |
1565 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | |
1566 | ||
1567 | #define RSS_IPV4_TCP_CAP_MASK \ | |
1568 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | |
1569 | ||
1570 | #define RSS_IPV6_CAP_MASK \ | |
1571 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | |
1572 | ||
1573 | #define RSS_IPV6_TCP_CAP_MASK \ | |
1574 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | |
1575 | ||
1576 | /* func init flags */ | |
619c5cb6 VZ |
1577 | #define FUNC_FLG_RSS 0x0001 |
1578 | #define FUNC_FLG_STATS 0x0002 | |
1579 | /* removed FUNC_FLG_UNMATCHED 0x0004 */ | |
1580 | #define FUNC_FLG_TPA 0x0008 | |
1581 | #define FUNC_FLG_SPQ 0x0010 | |
1582 | #define FUNC_FLG_LEADING 0x0020 /* PF only */ | |
523224a3 | 1583 | |
523224a3 DK |
1584 | |
1585 | struct bnx2x_func_init_params { | |
523224a3 DK |
1586 | /* dma */ |
1587 | dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ | |
1588 | dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ | |
1589 | ||
1590 | u16 func_flgs; | |
1591 | u16 func_id; /* abs fid */ | |
1592 | u16 pf_id; | |
1593 | u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ | |
1594 | }; | |
1595 | ||
ec6ba945 | 1596 | #define for_each_eth_queue(bp, var) \ |
6383c0b3 | 1597 | for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) |
ec6ba945 VZ |
1598 | |
1599 | #define for_each_nondefault_eth_queue(bp, var) \ | |
6383c0b3 | 1600 | for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) |
ec6ba945 | 1601 | |
555f6c78 | 1602 | #define for_each_queue(bp, var) \ |
6383c0b3 | 1603 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1604 | if (skip_queue(bp, var)) \ |
1605 | continue; \ | |
1606 | else | |
1607 | ||
6383c0b3 | 1608 | /* Skip forwarding FP */ |
ec6ba945 | 1609 | #define for_each_rx_queue(bp, var) \ |
6383c0b3 | 1610 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1611 | if (skip_rx_queue(bp, var)) \ |
1612 | continue; \ | |
1613 | else | |
1614 | ||
6383c0b3 | 1615 | /* Skip OOO FP */ |
ec6ba945 | 1616 | #define for_each_tx_queue(bp, var) \ |
6383c0b3 | 1617 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1618 | if (skip_tx_queue(bp, var)) \ |
1619 | continue; \ | |
1620 | else | |
1621 | ||
3196a88a | 1622 | #define for_each_nondefault_queue(bp, var) \ |
6383c0b3 | 1623 | for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1624 | if (skip_queue(bp, var)) \ |
1625 | continue; \ | |
1626 | else | |
3196a88a | 1627 | |
6383c0b3 AE |
1628 | #define for_each_cos_in_tx_queue(fp, var) \ |
1629 | for ((var) = 0; (var) < (fp)->max_cos; (var)++) | |
1630 | ||
ec6ba945 | 1631 | /* skip rx queue |
008d23e4 | 1632 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
ec6ba945 VZ |
1633 | */ |
1634 | #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1635 | ||
1636 | /* skip tx queue | |
008d23e4 | 1637 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
ec6ba945 VZ |
1638 | */ |
1639 | #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1640 | ||
1641 | #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
3196a88a | 1642 | |
f85582f8 | 1643 | |
619c5cb6 VZ |
1644 | |
1645 | ||
1646 | /** | |
1647 | * bnx2x_set_mac_one - configure a single MAC address | |
1648 | * | |
1649 | * @bp: driver handle | |
1650 | * @mac: MAC to configure | |
1651 | * @obj: MAC object handle | |
1652 | * @set: if 'true' add a new MAC, otherwise - delete | |
1653 | * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) | |
1654 | * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) | |
1655 | * | |
1656 | * Configures one MAC according to provided parameters or continues the | |
1657 | * execution of previously scheduled commands if RAMROD_CONT is set in | |
1658 | * ramrod_flags. | |
1659 | * | |
1660 | * Returns zero if operation has successfully completed, a positive value if the | |
1661 | * operation has been successfully scheduled and a negative - if a requested | |
1662 | * operations has failed. | |
1663 | */ | |
1664 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, | |
1665 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
1666 | int mac_type, unsigned long *ramrod_flags); | |
1667 | /** | |
1668 | * Deletes all MACs configured for the specific MAC object. | |
1669 | * | |
1670 | * @param bp Function driver instance | |
1671 | * @param mac_obj MAC object to cleanup | |
1672 | * | |
1673 | * @return zero if all MACs were cleaned | |
1674 | */ | |
1675 | ||
1676 | /** | |
1677 | * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object | |
1678 | * | |
1679 | * @bp: driver handle | |
1680 | * @mac_obj: MAC object handle | |
1681 | * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) | |
1682 | * @wait_for_comp: if 'true' block until completion | |
1683 | * | |
1684 | * Deletes all MACs of the specific type (e.g. ETH, UC list). | |
1685 | * | |
1686 | * Returns zero if operation has successfully completed, a positive value if the | |
1687 | * operation has been successfully scheduled and a negative - if a requested | |
1688 | * operations has failed. | |
1689 | */ | |
1690 | int bnx2x_del_all_macs(struct bnx2x *bp, | |
1691 | struct bnx2x_vlan_mac_obj *mac_obj, | |
1692 | int mac_type, bool wait_for_comp); | |
1693 | ||
1694 | /* Init Function API */ | |
1695 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); | |
1696 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); | |
1697 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); | |
1698 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); | |
1699 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); | |
2ae17f66 VZ |
1700 | void bnx2x_read_mf_cfg(struct bnx2x *bp); |
1701 | ||
619c5cb6 | 1702 | |
f85582f8 | 1703 | /* dmae */ |
c18487ee YR |
1704 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
1705 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
1706 | u32 len32); | |
f85582f8 DK |
1707 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); |
1708 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); | |
1709 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); | |
1710 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, | |
1711 | bool with_comp, u8 comp_type); | |
1712 | ||
f85582f8 | 1713 | |
de0c62db DK |
1714 | void bnx2x_calc_fc_adv(struct bnx2x *bp); |
1715 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, | |
619c5cb6 | 1716 | u32 data_hi, u32 data_lo, int cmd_type); |
de0c62db | 1717 | void bnx2x_update_coalesce(struct bnx2x *bp); |
1ac9e428 | 1718 | int bnx2x_get_cur_phy_idx(struct bnx2x *bp); |
f85582f8 | 1719 | |
34f80b04 EG |
1720 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
1721 | int wait) | |
1722 | { | |
1723 | u32 val; | |
1724 | ||
1725 | do { | |
1726 | val = REG_RD(bp, reg); | |
1727 | if (val == expected) | |
1728 | break; | |
1729 | ms -= wait; | |
1730 | msleep(wait); | |
1731 | ||
1732 | } while (ms > 0); | |
1733 | ||
1734 | return val; | |
1735 | } | |
f85582f8 | 1736 | |
523224a3 DK |
1737 | #define BNX2X_ILT_ZALLOC(x, y, size) \ |
1738 | do { \ | |
d245a111 | 1739 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ |
523224a3 DK |
1740 | if (x) \ |
1741 | memset(x, 0, size); \ | |
1742 | } while (0) | |
1743 | ||
1744 | #define BNX2X_ILT_FREE(x, y, size) \ | |
1745 | do { \ | |
1746 | if (x) { \ | |
d245a111 | 1747 | dma_free_coherent(&bp->pdev->dev, size, x, y); \ |
523224a3 DK |
1748 | x = NULL; \ |
1749 | y = 0; \ | |
1750 | } \ | |
1751 | } while (0) | |
1752 | ||
1753 | #define ILOG2(x) (ilog2((x))) | |
1754 | ||
1755 | #define ILT_NUM_PAGE_ENTRIES (3072) | |
1756 | /* In 57710/11 we use whole table since we have 8 func | |
f85582f8 DK |
1757 | * In 57712 we have only 4 func, but use same size per func, then only half of |
1758 | * the table in use | |
523224a3 DK |
1759 | */ |
1760 | #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) | |
1761 | ||
1762 | #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) | |
1763 | /* | |
1764 | * the phys address is shifted right 12 bits and has an added | |
1765 | * 1=valid bit added to the 53rd bit | |
1766 | * then since this is a wide register(TM) | |
1767 | * we split it into two 32 bit writes | |
1768 | */ | |
1769 | #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) | |
1770 | #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) | |
34f80b04 | 1771 | |
34f80b04 EG |
1772 | /* load/unload mode */ |
1773 | #define LOAD_NORMAL 0 | |
1774 | #define LOAD_OPEN 1 | |
1775 | #define LOAD_DIAG 2 | |
1776 | #define UNLOAD_NORMAL 0 | |
1777 | #define UNLOAD_CLOSE 1 | |
f85582f8 | 1778 | #define UNLOAD_RECOVERY 2 |
34f80b04 | 1779 | |
bb2a0f7a | 1780 | |
ad8d3948 | 1781 | /* DMAE command defines */ |
f2e0899f DK |
1782 | #define DMAE_TIMEOUT -1 |
1783 | #define DMAE_PCI_ERROR -2 /* E2 and onward */ | |
1784 | #define DMAE_NOT_RDY -3 | |
1785 | #define DMAE_PCI_ERR_FLAG 0x80000000 | |
1786 | ||
1787 | #define DMAE_SRC_PCI 0 | |
1788 | #define DMAE_SRC_GRC 1 | |
1789 | ||
1790 | #define DMAE_DST_NONE 0 | |
1791 | #define DMAE_DST_PCI 1 | |
1792 | #define DMAE_DST_GRC 2 | |
1793 | ||
1794 | #define DMAE_COMP_PCI 0 | |
1795 | #define DMAE_COMP_GRC 1 | |
1796 | ||
1797 | /* E2 and onward - PCI error handling in the completion */ | |
1798 | ||
1799 | #define DMAE_COMP_REGULAR 0 | |
1800 | #define DMAE_COM_SET_ERR 1 | |
ad8d3948 | 1801 | |
f2e0899f DK |
1802 | #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ |
1803 | DMAE_COMMAND_SRC_SHIFT) | |
1804 | #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ | |
1805 | DMAE_COMMAND_SRC_SHIFT) | |
ad8d3948 | 1806 | |
f2e0899f DK |
1807 | #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ |
1808 | DMAE_COMMAND_DST_SHIFT) | |
1809 | #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ | |
1810 | DMAE_COMMAND_DST_SHIFT) | |
1811 | ||
1812 | #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ | |
1813 | DMAE_COMMAND_C_DST_SHIFT) | |
1814 | #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ | |
1815 | DMAE_COMMAND_C_DST_SHIFT) | |
ad8d3948 EG |
1816 | |
1817 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
1818 | ||
1819 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1820 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1821 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1822 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1823 | ||
1824 | #define DMAE_CMD_PORT_0 0 | |
1825 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
1826 | ||
1827 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
1828 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
1829 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
1830 | ||
f2e0899f DK |
1831 | #define DMAE_SRC_PF 0 |
1832 | #define DMAE_SRC_VF 1 | |
1833 | ||
1834 | #define DMAE_DST_PF 0 | |
1835 | #define DMAE_DST_VF 1 | |
1836 | ||
1837 | #define DMAE_C_SRC 0 | |
1838 | #define DMAE_C_DST 1 | |
1839 | ||
ad8d3948 | 1840 | #define DMAE_LEN32_RD_MAX 0x80 |
02e3c6cb | 1841 | #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
ad8d3948 | 1842 | |
f2e0899f DK |
1843 | #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit |
1844 | indicates eror */ | |
ad8d3948 EG |
1845 | |
1846 | #define MAX_DMAE_C_PER_PORT 8 | |
ab6ad5a4 | 1847 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
3395a033 | 1848 | BP_VN(bp)) |
ab6ad5a4 | 1849 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 EG |
1850 | E1HVN_MAX) |
1851 | ||
25047950 ET |
1852 | /* PCIE link and speed */ |
1853 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
1854 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
1855 | #define PCICFG_LINK_SPEED 0xf0000 | |
1856 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
a2fbb9ea | 1857 | |
bb2a0f7a | 1858 | |
d3d4f495 | 1859 | #define BNX2X_NUM_TESTS 7 |
bb2a0f7a | 1860 | |
b5bf9068 EG |
1861 | #define BNX2X_PHY_LOOPBACK 0 |
1862 | #define BNX2X_MAC_LOOPBACK 1 | |
1863 | #define BNX2X_PHY_LOOPBACK_FAILED 1 | |
1864 | #define BNX2X_MAC_LOOPBACK_FAILED 2 | |
bb2a0f7a YG |
1865 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ |
1866 | BNX2X_PHY_LOOPBACK_FAILED) | |
96fc1784 | 1867 | |
7a9b2557 VZ |
1868 | |
1869 | #define STROM_ASSERT_ARRAY_SIZE 50 | |
1870 | ||
96fc1784 | 1871 | |
34f80b04 | 1872 | /* must be used on a CID before placing it on a HW ring */ |
ab6ad5a4 | 1873 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
3395a033 | 1874 | (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ |
619c5cb6 | 1875 | (x)) |
7a9b2557 VZ |
1876 | |
1877 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
1878 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
1879 | ||
1880 | ||
523224a3 | 1881 | #define BNX2X_BTR 4 |
7a9b2557 | 1882 | #define MAX_SPQ_PENDING 8 |
a2fbb9ea | 1883 | |
ff80ee02 DK |
1884 | /* CMNG constants, as derived from system spec calculations */ |
1885 | /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ | |
1886 | #define DEF_MIN_RATE 100 | |
9b3de1ef DK |
1887 | /* resolution of the rate shaping timer - 400 usec */ |
1888 | #define RS_PERIODIC_TIMEOUT_USEC 400 | |
34f80b04 | 1889 | /* number of bytes in single QM arbitration cycle - |
ff80ee02 DK |
1890 | * coefficient for calculating the fairness timer */ |
1891 | #define QM_ARB_BYTES 160000 | |
1892 | /* resolution of Min algorithm 1:100 */ | |
1893 | #define MIN_RES 100 | |
1894 | /* how many bytes above threshold for the minimal credit of Min algorithm*/ | |
1895 | #define MIN_ABOVE_THRESH 32768 | |
1896 | /* Fairness algorithm integration time coefficient - | |
1897 | * for calculating the actual Tfair */ | |
1898 | #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) | |
1899 | /* Memory of fairness algorithm . 2 cycles */ | |
1900 | #define FAIR_MEM 2 | |
34f80b04 EG |
1901 | |
1902 | ||
1903 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1904 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1905 | #define GPIO_2_FUNC (1L << 10) | |
1906 | #define GPIO_3_FUNC (1L << 11) | |
1907 | #define GPIO_4_FUNC (1L << 12) | |
1908 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1909 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1910 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1911 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1912 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1913 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1914 | ||
1915 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1916 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
1917 | |
1918 | ||
34f80b04 EG |
1919 | /* stuff added to make the code fit 80Col */ |
1920 | ||
1921 | #define BNX2X_PMF_LINK_ASSERT \ | |
1922 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
1923 | ||
a2fbb9ea ET |
1924 | #define BNX2X_MC_ASSERT_BITS \ |
1925 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1926 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1927 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1928 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1929 | ||
1930 | #define BNX2X_MCP_ASSERT \ | |
1931 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1932 | ||
34f80b04 EG |
1933 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
1934 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1935 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1936 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1937 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1938 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1939 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1940 | ||
a2fbb9ea ET |
1941 | #define HW_INTERRUT_ASSERT_SET_0 \ |
1942 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1943 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1944 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
c9ee9206 | 1945 | AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) |
34f80b04 | 1946 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
a2fbb9ea ET |
1947 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
1948 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1949 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
c9ee9206 VZ |
1950 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ |
1951 | AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ | |
1952 | AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) | |
a2fbb9ea ET |
1953 | #define HW_INTERRUT_ASSERT_SET_1 \ |
1954 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1955 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1956 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1957 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1958 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1959 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1960 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1961 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1962 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1963 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1964 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
c9ee9206 | 1965 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ |
a2fbb9ea | 1966 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
c9ee9206 | 1967 | AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ |
a2fbb9ea | 1968 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ |
c9ee9206 | 1969 | AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ |
a2fbb9ea | 1970 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ |
ab6ad5a4 | 1971 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
c9ee9206 | 1972 | AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ |
ab6ad5a4 | 1973 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ |
a2fbb9ea ET |
1974 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
1975 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
c9ee9206 | 1976 | AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ |
a2fbb9ea ET |
1977 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ |
1978 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
c9ee9206 VZ |
1979 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ |
1980 | AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) | |
a2fbb9ea ET |
1981 | #define HW_INTERRUT_ASSERT_SET_2 \ |
1982 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
1983 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
1984 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
1985 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
1986 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
34f80b04 | 1987 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
a2fbb9ea ET |
1988 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
1989 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
1990 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
1991 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
c9ee9206 | 1992 | AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ |
a2fbb9ea ET |
1993 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ |
1994 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
1995 | ||
72fd0718 VZ |
1996 | #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ |
1997 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ | |
1998 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ | |
1999 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) | |
a2fbb9ea | 2000 | |
8736c826 VZ |
2001 | #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ |
2002 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) | |
2003 | ||
34f80b04 | 2004 | #define MULTI_MASK 0x7f |
a2fbb9ea | 2005 | |
619c5cb6 VZ |
2006 | |
2007 | #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) | |
2008 | #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) | |
2009 | #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) | |
2010 | #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) | |
2011 | ||
2012 | #define DEF_USB_IGU_INDEX_OFF \ | |
2013 | offsetof(struct cstorm_def_status_block_u, igu_index) | |
2014 | #define DEF_CSB_IGU_INDEX_OFF \ | |
2015 | offsetof(struct cstorm_def_status_block_c, igu_index) | |
2016 | #define DEF_XSB_IGU_INDEX_OFF \ | |
2017 | offsetof(struct xstorm_def_status_block, igu_index) | |
2018 | #define DEF_TSB_IGU_INDEX_OFF \ | |
2019 | offsetof(struct tstorm_def_status_block, igu_index) | |
2020 | ||
2021 | #define DEF_USB_SEGMENT_OFF \ | |
2022 | offsetof(struct cstorm_def_status_block_u, segment) | |
2023 | #define DEF_CSB_SEGMENT_OFF \ | |
2024 | offsetof(struct cstorm_def_status_block_c, segment) | |
2025 | #define DEF_XSB_SEGMENT_OFF \ | |
2026 | offsetof(struct xstorm_def_status_block, segment) | |
2027 | #define DEF_TSB_SEGMENT_OFF \ | |
2028 | offsetof(struct tstorm_def_status_block, segment) | |
2029 | ||
a2fbb9ea | 2030 | #define BNX2X_SP_DSB_INDEX \ |
523224a3 DK |
2031 | (&bp->def_status_blk->sp_sb.\ |
2032 | index_values[HC_SP_INDEX_ETH_DEF_CONS]) | |
f85582f8 | 2033 | |
523224a3 DK |
2034 | #define SET_FLAG(value, mask, flag) \ |
2035 | do {\ | |
2036 | (value) &= ~(mask);\ | |
2037 | (value) |= ((flag) << (mask##_SHIFT));\ | |
2038 | } while (0) | |
a2fbb9ea | 2039 | |
523224a3 | 2040 | #define GET_FLAG(value, mask) \ |
619c5cb6 | 2041 | (((value) & (mask)) >> (mask##_SHIFT)) |
a2fbb9ea | 2042 | |
f2e0899f DK |
2043 | #define GET_FIELD(value, fname) \ |
2044 | (((value) & (fname##_MASK)) >> (fname##_SHIFT)) | |
2045 | ||
a2fbb9ea | 2046 | #define CAM_IS_INVALID(x) \ |
523224a3 DK |
2047 | (GET_FLAG(x.flags, \ |
2048 | MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ | |
2049 | (T_ETH_MAC_COMMAND_INVALIDATE)) | |
a2fbb9ea | 2050 | |
34f80b04 EG |
2051 | /* Number of u32 elements in MC hash array */ |
2052 | #define MC_HASH_SIZE 8 | |
2053 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
2054 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
a2fbb9ea ET |
2055 | |
2056 | ||
34f80b04 EG |
2057 | #ifndef PXP2_REG_PXP2_INT_STS |
2058 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
2059 | #endif | |
2060 | ||
f2e0899f DK |
2061 | #ifndef ETH_MAX_RX_CLIENTS_E2 |
2062 | #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H | |
2063 | #endif | |
f85582f8 | 2064 | |
34f24c7f VZ |
2065 | #define BNX2X_VPD_LEN 128 |
2066 | #define VENDOR_ID_LEN 4 | |
2067 | ||
8304859a AE |
2068 | int bnx2x_close(struct net_device *dev); |
2069 | ||
523224a3 DK |
2070 | /* Congestion management fairness mode */ |
2071 | #define CMNG_FNS_NONE 0 | |
2072 | #define CMNG_FNS_MINMAX 1 | |
2073 | ||
2074 | #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ | |
2075 | #define HC_SEG_ACCESS_ATTN 4 | |
2076 | #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ | |
2077 | ||
619c5cb6 VZ |
2078 | static const u32 dmae_reg_go_c[] = { |
2079 | DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, | |
2080 | DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, | |
2081 | DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, | |
2082 | DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 | |
2083 | }; | |
de0c62db | 2084 | |
619c5cb6 | 2085 | void bnx2x_set_ethtool_ops(struct net_device *netdev); |
3deb8167 | 2086 | void bnx2x_notify_link_changed(struct bnx2x *bp); |
a2fbb9ea | 2087 | #endif /* bnx2x.h */ |