bnx2x: Clean before update RSS arrives
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x.h
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1/* bnx2x.h: Broadcom Everest network driver.
2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
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4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
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9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
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11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
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16
17#include <linux/pci.h>
ec6ba945 18#include <linux/netdevice.h>
b7f080cf 19#include <linux/dma-mapping.h>
ec6ba945 20#include <linux/types.h>
290ca2bb 21#include <linux/pci_regs.h>
a2fbb9ea 22
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23/* compilation time flags */
24
25/* define this to make the driver freeze on error to allow getting debug info
26 * (you will need to reboot afterwards) */
27/* #define BNX2X_STOP_ON_ERROR */
28
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29#define DRV_MODULE_VERSION "1.78.17-0"
30#define DRV_MODULE_RELDATE "2013/04/11"
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31#define BNX2X_BC_VER 0x040200
32
785b9b1a 33#if defined(CONFIG_DCB)
98507672 34#define BCM_DCBNL
785b9b1a 35#endif
b475d78f 36
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37#include "bnx2x_hsi.h"
38
5d1e859c 39#include "../cnic_if.h"
0c6671b0 40
55c11941 41#define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
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42
43#include <linux/mdio.h>
619c5cb6 44
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45#include "bnx2x_reg.h"
46#include "bnx2x_fw_defs.h"
2e499d3c 47#include "bnx2x_mfw_req.h"
359d8b15 48#include "bnx2x_link.h"
619c5cb6 49#include "bnx2x_sp.h"
e4901dde 50#include "bnx2x_dcb.h"
6c719d00 51#include "bnx2x_stats.h"
be1f1ffa 52#include "bnx2x_vfpf.h"
359d8b15 53
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54enum bnx2x_int_mode {
55 BNX2X_INT_MODE_MSIX,
56 BNX2X_INT_MODE_INTX,
57 BNX2X_INT_MODE_MSI
58};
59
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60/* error/debug prints */
61
34f80b04 62#define DRV_MODULE_NAME "bnx2x"
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63
64/* for messages that are currently off */
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65#define BNX2X_MSG_OFF 0x0
66#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
67#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
68#define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
69#define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
70#define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
71#define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
72#define BNX2X_MSG_IOV 0x0800000
73#define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
74#define BNX2X_MSG_ETHTOOL 0x4000000
75#define BNX2X_MSG_DCB 0x8000000
a2fbb9ea 76
a2fbb9ea 77/* regular debug print */
f1deab50 78#define DP(__mask, fmt, ...) \
7995c64e 79do { \
51c1a580 80 if (unlikely(bp->msg_enable & (__mask))) \
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81 pr_notice("[%s:%d(%s)]" fmt, \
82 __func__, __LINE__, \
83 bp->dev ? (bp->dev->name) : "?", \
84 ##__VA_ARGS__); \
7995c64e 85} while (0)
a2fbb9ea 86
f1deab50 87#define DP_CONT(__mask, fmt, ...) \
619c5cb6 88do { \
51c1a580 89 if (unlikely(bp->msg_enable & (__mask))) \
f1deab50 90 pr_cont(fmt, ##__VA_ARGS__); \
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91} while (0)
92
34f80b04 93/* errors debug print */
f1deab50 94#define BNX2X_DBG_ERR(fmt, ...) \
7995c64e 95do { \
51c1a580 96 if (unlikely(netif_msg_probe(bp))) \
f1deab50 97 pr_err("[%s:%d(%s)]" fmt, \
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98 __func__, __LINE__, \
99 bp->dev ? (bp->dev->name) : "?", \
f1deab50 100 ##__VA_ARGS__); \
7995c64e 101} while (0)
a2fbb9ea 102
34f80b04 103/* for errors (never masked) */
f1deab50 104#define BNX2X_ERR(fmt, ...) \
7995c64e 105do { \
f1deab50 106 pr_err("[%s:%d(%s)]" fmt, \
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107 __func__, __LINE__, \
108 bp->dev ? (bp->dev->name) : "?", \
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109 ##__VA_ARGS__); \
110} while (0)
cdaa7cb8 111
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112#define BNX2X_ERROR(fmt, ...) \
113 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
cdaa7cb8 114
a2fbb9ea 115/* before we have a dev->name use dev_info() */
f1deab50 116#define BNX2X_DEV_INFO(fmt, ...) \
7995c64e 117do { \
51c1a580 118 if (unlikely(netif_msg_probe(bp))) \
f1deab50 119 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
7995c64e 120} while (0)
a2fbb9ea 121
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122/* Error handling */
123void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
a2fbb9ea 124#ifdef BNX2X_STOP_ON_ERROR
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125#define bnx2x_panic() \
126do { \
127 bp->panic = 1; \
128 BNX2X_ERR("driver assert\n"); \
823e1d90 129 bnx2x_panic_dump(bp, true); \
f1deab50 130} while (0)
a2fbb9ea 131#else
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132#define bnx2x_panic() \
133do { \
134 bp->panic = 1; \
135 BNX2X_ERR("driver assert\n"); \
823e1d90 136 bnx2x_panic_dump(bp, false); \
f1deab50 137} while (0)
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138#endif
139
523224a3 140#define bnx2x_mc_addr(ha) ((ha)->addr)
6e30dd4e 141#define bnx2x_uc_addr(ha) ((ha)->addr)
a2fbb9ea 142
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143#define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
144#define U64_HI(x) ((u32)(((u64)(x)) >> 32))
34f80b04 145#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
a2fbb9ea 146
523224a3 147#define REG_ADDR(bp, offset) ((bp->regview) + (offset))
a2fbb9ea 148
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149#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
150#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
523224a3 151#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
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152
153#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
a2fbb9ea 154#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
34f80b04 155#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
a2fbb9ea 156
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157#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
158#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
a2fbb9ea 159
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160#define REG_RD_DMAE(bp, offset, valp, len32) \
161 do { \
162 bnx2x_read_dmae(bp, offset, len32);\
573f2035 163 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
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164 } while (0)
165
34f80b04 166#define REG_WR_DMAE(bp, offset, valp, len32) \
a2fbb9ea 167 do { \
573f2035 168 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
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169 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
170 offset, len32); \
171 } while (0)
172
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173#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
174 REG_WR_DMAE(bp, offset, valp, len32)
175
3359fced 176#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
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177 do { \
178 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
179 bnx2x_write_big_buf_wb(bp, addr, len32); \
180 } while (0)
181
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182#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
183 offsetof(struct shmem_region, field))
184#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
185#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
a2fbb9ea 186
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187#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
188 offsetof(struct shmem2_region, field))
189#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
190#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
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191#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
192 offsetof(struct mf_cfg, field))
f85582f8 193#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
f2e0899f 194 offsetof(struct mf2_cfg, field))
2691d51d 195
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196#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
197#define MF_CFG_WR(bp, field, val) REG_WR(bp,\
198 MF_CFG_ADDR(bp, field), (val))
f2e0899f 199#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
f85582f8 200
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201#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
202 (SHMEM2_RD((bp), size) > \
203 offsetof(struct shmem2_region, field)))
72fd0718 204
345b5d52 205#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
3196a88a 206#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
a2fbb9ea 207
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208/* SP SB indices */
209
210/* General SP events - stats query, cfc delete, etc */
211#define HC_SP_INDEX_ETH_DEF_CONS 3
212
213/* EQ completions */
214#define HC_SP_INDEX_EQ_CONS 7
215
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216/* FCoE L2 connection completions */
217#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
218#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
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219/* iSCSI L2 */
220#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
221#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
222
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223/* Special clients parameters */
224
225/* SB indices */
226/* FCoE L2 */
227#define BNX2X_FCOE_L2_RX_INDEX \
228 (&bp->def_status_blk->sp_sb.\
229 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
230
231#define BNX2X_FCOE_L2_TX_INDEX \
232 (&bp->def_status_blk->sp_sb.\
233 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
234
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235/**
236 * CIDs and CLIDs:
237 * CLIDs below is a CLID for func 0, then the CLID for other
238 * functions will be calculated by the formula:
239 *
240 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
241 *
242 */
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243enum {
244 BNX2X_ISCSI_ETH_CL_ID_IDX,
245 BNX2X_FCOE_ETH_CL_ID_IDX,
246 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
247};
248
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249/* use a value high enough to be above all the PFs, which has least significant
250 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to
251 * calculate doorbell address according to old doorbell configuration scheme
252 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
253 * We must avoid coming up with cid 8 for iscsi since according to this method
254 * the designated UIO cid will come out 0 and it has a special handling for that
255 * case which doesn't suit us. Therefore will will cieling to closes cid which
256 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
257 */
258
259#define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
37ae41a9 260 (bp)->max_cos)
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261/* amount of cids traversed by UIO's DPM addition to doorbell */
262#define UIO_DPM 8
263/* roundup to DPM offset */
264#define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \
265 UIO_DPM))
266/* offset to nearest value which has lsb nibble matching DPM */
267#define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \
268 (UIO_DPM * 2))
269/* add offset to rounded-up cid to get a value which could be used with UIO */
270#define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
271/* but wait - avoid UIO special case for cid 0 */
272#define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \
273 (UIO_DPM_ALIGN(bp) == UIO_DPM))
274/* Properly DPM aligned CID dajusted to cid 0 secal case */
275#define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \
276 (UIO_DPM_CID0_OFFSET(bp)))
277/* how many cids were wasted - need this value for cid allocation */
278#define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \
279 BNX2X_1st_NON_L2_ETH_CID(bp))
134d0f97 280 /* iSCSI L2 */
37ae41a9 281#define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
134d0f97 282 /* FCoE L2 */
37ae41a9 283#define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
ec6ba945 284
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285#define CNIC_SUPPORT(bp) ((bp)->cnic_support)
286#define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
287#define CNIC_LOADED(bp) ((bp)->cnic_loaded)
288#define FCOE_INIT(bp) ((bp)->fcoe_init)
523224a3 289
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290#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
291 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
292
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293#define SM_RX_ID 0
294#define SM_TX_ID 1
a2fbb9ea 295
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296/* defines for multiple tx priority indices */
297#define FIRST_TX_ONLY_COS_INDEX 1
298#define FIRST_TX_COS_INDEX 0
299
6383c0b3 300/* rules for calculating the cids of tx-only connections */
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301#define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
302#define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
303 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
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304
305/* fp index inside class of service range */
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306#define FP_COS_TO_TXQ(fp, cos, bp) \
307 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
308
309/* Indexes for transmission queues array:
310 * txdata for RSS i CoS j is at location i + (j * num of RSS)
311 * txdata for FCoE (if exist) is at location max cos * num of RSS
312 * txdata for FWD (if exist) is one location after FCoE
313 * txdata for OOO (if exist) is one location after FWD
6383c0b3 314 */
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315enum {
316 FCOE_TXQ_IDX_OFFSET,
317 FWD_TXQ_IDX_OFFSET,
318 OOO_TXQ_IDX_OFFSET,
319};
320#define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
65565884 321#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
a2fbb9ea 322
6383c0b3 323/* fast path */
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324/*
325 * This driver uses new build_skb() API :
326 * RX ring buffer contains pointer to kmalloc() data only,
327 * skb are built only after Hardware filled the frame.
328 */
a2fbb9ea 329struct sw_rx_bd {
e52fcb24 330 u8 *data;
1a983142 331 DEFINE_DMA_UNMAP_ADDR(mapping);
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332};
333
334struct sw_tx_bd {
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335 struct sk_buff *skb;
336 u16 first_bd;
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337 u8 flags;
338/* Set on the first BD descriptor when there is a split BD */
339#define BNX2X_TSO_SPLIT_BD (1<<0)
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340};
341
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342struct sw_rx_page {
343 struct page *page;
1a983142 344 DEFINE_DMA_UNMAP_ADDR(mapping);
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345};
346
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347union db_prod {
348 struct doorbell_set_prod data;
349 u32 raw;
350};
351
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352/* dropless fc FW/HW related params */
353#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
354#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
355 ETH_MAX_AGGREGATION_QUEUES_E1 :\
356 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
357#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
358#define FW_PREFETCH_CNT 16
359#define DROPLESS_FC_HEADROOM 100
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360
361/* MC hsi */
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362#define BCM_PAGE_SHIFT 12
363#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
364#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
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365#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
366
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367#define PAGES_PER_SGE_SHIFT 0
368#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
369#define SGE_PAGE_SIZE PAGE_SIZE
370#define SGE_PAGE_SHIFT PAGE_SHIFT
371#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
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372#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
373#define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
374 SGE_PAGES), 0xffff)
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375
376/* SGE ring related macros */
619c5cb6 377#define NUM_RX_SGE_PAGES 2
7a9b2557 378#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
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379#define NEXT_PAGE_SGE_DESC_CNT 2
380#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
33471629 381/* RX_SGE_CNT is promised to be a power of 2 */
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382#define RX_SGE_MASK (RX_SGE_CNT - 1)
383#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
384#define MAX_RX_SGE (NUM_RX_SGE - 1)
7a9b2557 385#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
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386 (MAX_RX_SGE_CNT - 1)) ? \
387 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
388 (x) + 1)
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389#define RX_SGE(x) ((x) & MAX_RX_SGE)
390
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391/*
392 * Number of required SGEs is the sum of two:
393 * 1. Number of possible opened aggregations (next packet for
16a5fd92 394 * these aggregations will probably consume SGE immediately)
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395 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
396 * after placement on BD for new TPA aggregation)
397 *
398 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
399 */
400#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
401 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
402#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
403 MAX_RX_SGE_CNT)
404#define SGE_TH_LO(bp) (NUM_SGE_REQ + \
405 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
406#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
407
619c5cb6 408/* Manipulate a bit vector defined as an array of u64 */
7a9b2557 409
7a9b2557 410/* Number of bits in one sge_mask array element */
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411#define BIT_VEC64_ELEM_SZ 64
412#define BIT_VEC64_ELEM_SHIFT 6
413#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
414
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415#define __BIT_VEC64_SET_BIT(el, bit) \
416 do { \
417 el = ((el) | ((u64)0x1 << (bit))); \
418 } while (0)
419
420#define __BIT_VEC64_CLEAR_BIT(el, bit) \
421 do { \
422 el = ((el) & (~((u64)0x1 << (bit)))); \
423 } while (0)
424
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425#define BIT_VEC64_SET_BIT(vec64, idx) \
426 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
427 (idx) & BIT_VEC64_ELEM_MASK)
428
429#define BIT_VEC64_CLEAR_BIT(vec64, idx) \
430 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
431 (idx) & BIT_VEC64_ELEM_MASK)
432
433#define BIT_VEC64_TEST_BIT(vec64, idx) \
434 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
435 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
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436
437/* Creates a bitmask of all ones in less significant bits.
438 idx - index of the most significant bit in the created mask */
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439#define BIT_VEC64_ONES_MASK(idx) \
440 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
441#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
442
443/*******************************************************/
444
7a9b2557 445/* Number of u64 elements in SGE mask array */
b3637827 446#define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
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447#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
448#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
449
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450union host_hc_status_block {
451 /* pointer to fp status block e1x */
452 struct host_hc_status_block_e1x *e1x_sb;
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453 /* pointer to fp status block e2 */
454 struct host_hc_status_block_e2 *e2_sb;
523224a3 455};
7a9b2557 456
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457struct bnx2x_agg_info {
458 /*
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459 * First aggregation buffer is a data buffer, the following - are pages.
460 * We will preallocate the data buffer for each aggregation when
619c5cb6
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461 * we open the interface and will replace the BD at the consumer
462 * with this one when we receive the TPA_START CQE in order to
463 * keep the Rx BD ring consistent.
464 */
465 struct sw_rx_bd first_buf;
466 u8 tpa_state;
467#define BNX2X_TPA_START 1
468#define BNX2X_TPA_STOP 2
469#define BNX2X_TPA_ERROR 3
470 u8 placement_offset;
471 u16 parsing_flags;
472 u16 vlan_tag;
473 u16 len_on_bd;
e52fcb24 474 u32 rxhash;
a334b5fb 475 bool l4_rxhash;
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476 u16 gro_size;
477 u16 full_page;
619c5cb6
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478};
479
480#define Q_STATS_OFFSET32(stat_name) \
481 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
482
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483struct bnx2x_fp_txdata {
484
485 struct sw_tx_bd *tx_buf_ring;
486
487 union eth_tx_bd_types *tx_desc_ring;
488 dma_addr_t tx_desc_mapping;
489
490 u32 cid;
491
492 union db_prod tx_db;
493
494 u16 tx_pkt_prod;
495 u16 tx_pkt_cons;
496 u16 tx_bd_prod;
497 u16 tx_bd_cons;
498
499 unsigned long tx_pkt;
500
501 __le16 *tx_cons_sb;
502
503 int txq_index;
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504 struct bnx2x_fastpath *parent_fp;
505 int tx_ring_size;
6383c0b3
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506};
507
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508enum bnx2x_tpa_mode_t {
509 TPA_MODE_LRO,
510 TPA_MODE_GRO
511};
512
a2fbb9ea 513struct bnx2x_fastpath {
619c5cb6 514 struct bnx2x *bp; /* parent */
a2fbb9ea 515
34f80b04 516 struct napi_struct napi;
8f20aa57 517
e0d1095a 518#ifdef CONFIG_NET_RX_BUSY_POLL
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519 unsigned int state;
520#define BNX2X_FP_STATE_IDLE 0
521#define BNX2X_FP_STATE_NAPI (1 << 0) /* NAPI owns this FP */
522#define BNX2X_FP_STATE_POLL (1 << 1) /* poll owns this FP */
523#define BNX2X_FP_STATE_NAPI_YIELD (1 << 2) /* NAPI yielded this FP */
524#define BNX2X_FP_STATE_POLL_YIELD (1 << 3) /* poll yielded this FP */
525#define BNX2X_FP_YIELD (BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD)
526#define BNX2X_FP_LOCKED (BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL)
527#define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD)
528 /* protect state */
529 spinlock_t lock;
e0d1095a 530#endif /* CONFIG_NET_RX_BUSY_POLL */
8f20aa57 531
f85582f8 532 union host_hc_status_block status_blk;
16a5fd92 533 /* chip independent shortcuts into sb structure */
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534 __le16 *sb_index_values;
535 __le16 *sb_running_index;
16a5fd92 536 /* chip independent shortcut into rx_prods_offset memory */
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537 u32 ustorm_rx_prods_offset;
538
a8c94b91 539 u32 rx_buf_size;
d46d132c 540 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
34f80b04 541 dma_addr_t status_blk_mapping;
a2fbb9ea 542
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543 enum bnx2x_tpa_mode_t mode;
544
6383c0b3 545 u8 max_cos; /* actual number of active tx coses */
65565884 546 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
a2fbb9ea 547
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548 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
549 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
a2fbb9ea
ET
550
551 struct eth_rx_bd *rx_desc_ring;
34f80b04 552 dma_addr_t rx_desc_mapping;
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ET
553
554 union eth_rx_cqe *rx_comp_ring;
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555 dma_addr_t rx_comp_mapping;
556
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557 /* SGE ring */
558 struct eth_rx_sge *rx_sge_ring;
559 dma_addr_t rx_sge_mapping;
560
561 u64 sge_mask[RX_SGE_MASK_LEN];
562
619c5cb6 563 u32 cid;
34f80b04 564
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565 __le16 fp_hc_idx;
566
f85582f8 567 u8 index; /* number in fp array */
f233cafe 568 u8 rx_queue; /* index for skb_record */
f85582f8 569 u8 cl_id; /* eth client id */
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570 u8 cl_qzone_id;
571 u8 fw_sb_id; /* status block number in FW */
572 u8 igu_sb_id; /* status block number in HW */
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573
574 u16 rx_bd_prod;
575 u16 rx_bd_cons;
576 u16 rx_comp_prod;
577 u16 rx_comp_cons;
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578 u16 rx_sge_prod;
579 /* The last maximal completed SGE */
580 u16 last_max_sge;
4781bfad 581 __le16 *rx_cons_sb;
6383c0b3 582 unsigned long rx_pkt,
66e855f3 583 rx_calls;
ab6ad5a4 584
7a9b2557 585 /* TPA related */
15192a8c 586 struct bnx2x_agg_info *tpa_info;
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587 u8 disable_tpa;
588#ifdef BNX2X_STOP_ON_ERROR
589 u64 tpa_queue_used;
590#endif
ca00392c
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591 /* The size is calculated using the following:
592 sizeof name field from netdev structure +
593 4 ('-Xx-' string) +
594 4 (for the digits and to make it DWORD aligned) */
595#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
596 char name[FP_NAME_SIZE];
a2fbb9ea
ET
597};
598
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599#define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
600#define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
601#define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
602#define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
a8c94b91 603
e0d1095a 604#ifdef CONFIG_NET_RX_BUSY_POLL
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605static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp)
606{
607 spin_lock_init(&fp->lock);
608 fp->state = BNX2X_FP_STATE_IDLE;
609}
610
611/* called from the device poll routine to get ownership of a FP */
612static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
613{
614 bool rc = true;
615
616 spin_lock(&fp->lock);
617 if (fp->state & BNX2X_FP_LOCKED) {
618 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI);
619 fp->state |= BNX2X_FP_STATE_NAPI_YIELD;
620 rc = false;
621 } else {
622 /* we don't care if someone yielded */
623 fp->state = BNX2X_FP_STATE_NAPI;
624 }
625 spin_unlock(&fp->lock);
626 return rc;
627}
628
629/* returns true is someone tried to get the FP while napi had it */
630static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
631{
632 bool rc = false;
633
634 spin_lock(&fp->lock);
635 WARN_ON(fp->state &
636 (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD));
637
638 if (fp->state & BNX2X_FP_STATE_POLL_YIELD)
639 rc = true;
640 fp->state = BNX2X_FP_STATE_IDLE;
641 spin_unlock(&fp->lock);
642 return rc;
643}
644
645/* called from bnx2x_low_latency_poll() */
646static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
647{
648 bool rc = true;
649
650 spin_lock_bh(&fp->lock);
651 if ((fp->state & BNX2X_FP_LOCKED)) {
652 fp->state |= BNX2X_FP_STATE_POLL_YIELD;
653 rc = false;
654 } else {
655 /* preserve yield marks */
656 fp->state |= BNX2X_FP_STATE_POLL;
657 }
658 spin_unlock_bh(&fp->lock);
659 return rc;
660}
661
662/* returns true if someone tried to get the FP while it was locked */
663static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
664{
665 bool rc = false;
666
667 spin_lock_bh(&fp->lock);
668 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI);
669
670 if (fp->state & BNX2X_FP_STATE_POLL_YIELD)
671 rc = true;
672 fp->state = BNX2X_FP_STATE_IDLE;
673 spin_unlock_bh(&fp->lock);
674 return rc;
675}
676
677/* true if a socket is polling, even if it did not get the lock */
678static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
679{
680 WARN_ON(!(fp->state & BNX2X_FP_LOCKED));
681 return fp->state & BNX2X_FP_USER_PEND;
682}
683#else
684static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp)
685{
686}
687
688static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
689{
690 return true;
691}
692
693static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
694{
695 return false;
696}
697
698static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
699{
700 return false;
701}
702
703static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
704{
705 return false;
706}
707
708static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
709{
710 return false;
711}
e0d1095a 712#endif /* CONFIG_NET_RX_BUSY_POLL */
8f20aa57 713
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714/* Use 2500 as a mini-jumbo MTU for FCoE */
715#define BNX2X_FCOE_MINI_JUMBO_MTU 2500
716
65565884
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717#define FCOE_IDX_OFFSET 0
718
719#define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
720 FCOE_IDX_OFFSET)
721#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
722#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
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723#define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
724#define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
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725#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
726 txdata_ptr[FIRST_TX_COS_INDEX] \
727 ->var)
619c5cb6 728
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MS
729#define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
730#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
731#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
7a9b2557 732
7a9b2557 733/* MC hsi */
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734#define MAX_FETCH_BD 13 /* HW max BDs per packet */
735#define RX_COPY_THRESH 92
7a9b2557 736
619c5cb6 737#define NUM_TX_RINGS 16
ca00392c 738#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
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739#define NEXT_PAGE_TX_DESC_CNT 1
740#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
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741#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
742#define MAX_TX_BD (NUM_TX_BD - 1)
743#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
7a9b2557 744#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
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745 (MAX_TX_DESC_CNT - 1)) ? \
746 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
747 (x) + 1)
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748#define TX_BD(x) ((x) & MAX_TX_BD)
749#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
7a9b2557 750
7df2dc6b
DK
751/* number of NEXT_PAGE descriptors may be required during placement */
752#define NEXT_CNT_PER_TX_PKT(bds) \
753 (((bds) + MAX_TX_DESC_CNT - 1) / \
754 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
755/* max BDs per tx packet w/o next_pages:
756 * START_BD - describes packed
757 * START_BD(splitted) - includes unpaged data segment for GSO
758 * PARSING_BD - for TSO and CSUM data
a848ade4 759 * PARSING_BD2 - for encapsulation data
16a5fd92 760 * Frag BDs - describes pages for frags
7df2dc6b 761 */
a848ade4 762#define BDS_PER_TX_PKT 4
7df2dc6b
DK
763#define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
764/* max BDs per tx packet including next pages */
765#define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
766 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
767
7a9b2557 768/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
619c5cb6 769#define NUM_RX_RINGS 8
7a9b2557 770#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
dfacf138
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771#define NEXT_PAGE_RX_DESC_CNT 2
772#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
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773#define RX_DESC_MASK (RX_DESC_CNT - 1)
774#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
775#define MAX_RX_BD (NUM_RX_BD - 1)
776#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
dfacf138
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777
778/* dropless fc calculations for BDs
779 *
780 * Number of BDs should as number of buffers in BRB:
781 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
782 * "next" elements on each page
783 */
784#define NUM_BD_REQ BRB_SIZE(bp)
785#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
786 MAX_RX_DESC_CNT)
787#define BD_TH_LO(bp) (NUM_BD_REQ + \
788 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
789 FW_DROP_LEVEL(bp))
790#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
791
792#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
619c5cb6
VZ
793
794#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
795 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
796 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
797#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
798#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
799#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
800 MIN_RX_AVAIL))
801
7a9b2557 802#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
dfacf138
DK
803 (MAX_RX_DESC_CNT - 1)) ? \
804 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
805 (x) + 1)
619c5cb6 806#define RX_BD(x) ((x) & MAX_RX_BD)
7a9b2557 807
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VZ
808/*
809 * As long as CQE is X times bigger than BD entry we have to allocate X times
810 * more pages for CQ ring in order to keep it balanced with BD ring
811 */
812#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
813#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
7a9b2557 814#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
dfacf138
DK
815#define NEXT_PAGE_RCQ_DESC_CNT 1
816#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
619c5cb6
VZ
817#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
818#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
819#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
7a9b2557 820#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
dfacf138
DK
821 (MAX_RCQ_DESC_CNT - 1)) ? \
822 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
823 (x) + 1)
619c5cb6 824#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
7a9b2557 825
dfacf138
DK
826/* dropless fc calculations for RCQs
827 *
828 * Number of RCQs should be as number of buffers in BRB:
829 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
830 * "next" elements on each page
831 */
832#define NUM_RCQ_REQ BRB_SIZE(bp)
833#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
834 MAX_RCQ_DESC_CNT)
835#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
836 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
837 FW_DROP_LEVEL(bp))
838#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
839
33471629 840/* This is needed for determining of last_max */
619c5cb6
VZ
841#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
842#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
7a9b2557 843
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VZ
844#define BNX2X_SWCID_SHIFT 17
845#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
7a9b2557
VZ
846
847/* used on a CID received from the HW */
619c5cb6 848#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
7a9b2557
VZ
849#define CQE_CMD(x) (le32_to_cpu(x) >> \
850 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
851
bb2a0f7a
YG
852#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
853 le32_to_cpu((bd)->addr_lo))
854#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
855
523224a3 856#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
b9871bcf 857#define BNX2X_DB_SHIFT 3 /* 8 bytes*/
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VZ
858#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
859#error "Min DB doorbell stride is 8"
860#endif
7a9b2557
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861#define DOORBELL(bp, cid, val) \
862 do { \
b9871bcf 863 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \
7a9b2557
VZ
864 } while (0)
865
7a9b2557
VZ
866/* TX CSUM helpers */
867#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
868 skb->csum_offset)
869#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
870 skb->csum_offset))
871
91226790 872#define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
7a9b2557 873
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874#define XMIT_PLAIN 0
875#define XMIT_CSUM_V4 (1 << 0)
876#define XMIT_CSUM_V6 (1 << 1)
877#define XMIT_CSUM_TCP (1 << 2)
878#define XMIT_GSO_V4 (1 << 3)
879#define XMIT_GSO_V6 (1 << 4)
880#define XMIT_CSUM_ENC_V4 (1 << 5)
881#define XMIT_CSUM_ENC_V6 (1 << 6)
882#define XMIT_GSO_ENC_V4 (1 << 7)
883#define XMIT_GSO_ENC_V6 (1 << 8)
884
885#define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
886#define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
887
888#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
889#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
7a9b2557 890
34f80b04 891/* stuff added to make the code fit 80Col */
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VZ
892#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
893#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
894#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
895#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
896#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
7a9b2557 897
1adcd8be
EG
898#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
899
052a38e0
EG
900#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
901 (((le16_to_cpu(flags) & \
902 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
903 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
904 == PRS_FLAG_OVERETH_IPV4)
7a9b2557 905#define BNX2X_RX_SUM_FIX(cqe) \
052a38e0 906 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
7a9b2557 907
619c5cb6
VZ
908#define FP_USB_FUNC_OFF \
909 offsetof(struct cstorm_status_block_u, func)
910#define FP_CSB_FUNC_OFF \
911 offsetof(struct cstorm_status_block_c, func)
912
150966ad 913#define HC_INDEX_ETH_RX_CQ_CONS 1
619c5cb6 914
150966ad 915#define HC_INDEX_OOO_TX_CQ_CONS 4
6383c0b3 916
150966ad
AE
917#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
918
919#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
6383c0b3 920
150966ad
AE
921#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
922
923#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
a2fbb9ea 924
34f80b04 925#define BNX2X_RX_SB_INDEX \
619c5cb6 926 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
a2fbb9ea 927
6383c0b3
AE
928#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
929
930#define BNX2X_TX_SB_INDEX_COS0 \
931 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
7a9b2557
VZ
932
933/* end of fast path */
934
34f80b04 935/* common */
a2fbb9ea 936
34f80b04 937struct bnx2x_common {
a2fbb9ea 938
ad8d3948 939 u32 chip_id;
a2fbb9ea 940/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
34f80b04 941#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
ad8d3948 942
34f80b04 943#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
ad8d3948
EG
944#define CHIP_NUM_57710 0x164e
945#define CHIP_NUM_57711 0x164f
946#define CHIP_NUM_57711E 0x1650
f2e0899f 947#define CHIP_NUM_57712 0x1662
619c5cb6 948#define CHIP_NUM_57712_MF 0x1663
8395be5e 949#define CHIP_NUM_57712_VF 0x166f
619c5cb6
VZ
950#define CHIP_NUM_57713 0x1651
951#define CHIP_NUM_57713E 0x1652
952#define CHIP_NUM_57800 0x168a
953#define CHIP_NUM_57800_MF 0x16a5
8395be5e 954#define CHIP_NUM_57800_VF 0x16a9
619c5cb6
VZ
955#define CHIP_NUM_57810 0x168e
956#define CHIP_NUM_57810_MF 0x16ae
8395be5e 957#define CHIP_NUM_57810_VF 0x16af
7e8e02df
BW
958#define CHIP_NUM_57811 0x163d
959#define CHIP_NUM_57811_MF 0x163e
8395be5e 960#define CHIP_NUM_57811_VF 0x163f
2de67439 961#define CHIP_NUM_57840_OBSOLETE 0x168d
c3def943
YM
962#define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
963#define CHIP_NUM_57840_4_10 0x16a1
964#define CHIP_NUM_57840_2_20 0x16a2
965#define CHIP_NUM_57840_MF 0x16a4
8395be5e 966#define CHIP_NUM_57840_VF 0x16ad
ad8d3948
EG
967#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
968#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
969#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
f2e0899f 970#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
8395be5e 971#define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
619c5cb6
VZ
972#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
973#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
974#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
8395be5e 975#define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
619c5cb6
VZ
976#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
977#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
8395be5e 978#define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
7e8e02df
BW
979#define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
980#define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
8395be5e 981#define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
c3def943
YM
982#define CHIP_IS_57840(bp) \
983 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
984 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
985 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
986#define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
987 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
8395be5e 988#define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
ad8d3948
EG
989#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
990 CHIP_IS_57711E(bp))
edb944d2
DK
991#define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
992 CHIP_IS_57811_MF(bp) || \
993 CHIP_IS_57811_VF(bp))
f2e0899f 994#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
6ab20355
YM
995 CHIP_IS_57712_MF(bp) || \
996 CHIP_IS_57712_VF(bp))
619c5cb6
VZ
997#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
998 CHIP_IS_57800_MF(bp) || \
6ab20355 999 CHIP_IS_57800_VF(bp) || \
619c5cb6
VZ
1000 CHIP_IS_57810(bp) || \
1001 CHIP_IS_57810_MF(bp) || \
8395be5e 1002 CHIP_IS_57810_VF(bp) || \
edb944d2 1003 CHIP_IS_57811xx(bp) || \
619c5cb6 1004 CHIP_IS_57840(bp) || \
8395be5e
AE
1005 CHIP_IS_57840_MF(bp) || \
1006 CHIP_IS_57840_VF(bp))
f2e0899f 1007#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
619c5cb6
VZ
1008#define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
1009#define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
1010
1011#define CHIP_REV_SHIFT 12
1012#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
1013#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
1014#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
1015#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
ad8d3948 1016/* assume maximum 5 revisions */
619c5cb6 1017#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
ad8d3948
EG
1018/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
1019#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
619c5cb6 1020 !(CHIP_REV_VAL(bp) & 0x00001000))
ad8d3948
EG
1021/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
1022#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
619c5cb6 1023 (CHIP_REV_VAL(bp) & 0x00001000))
ad8d3948
EG
1024
1025#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
1026 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
1027
34f80b04
EG
1028#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
1029#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
619c5cb6
VZ
1030#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
1031 (CHIP_REV_SHIFT + 1)) \
1032 << CHIP_REV_SHIFT)
1033#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
1034 CHIP_REV_SIM(bp) :\
1035 CHIP_REV_VAL(bp))
1036#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
1037 (CHIP_REV(bp) == CHIP_REV_Bx))
1038#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
1039 (CHIP_REV(bp) == CHIP_REV_Ax))
55c11941 1040/* This define is used in two main places:
16a5fd92 1041 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
55c11941
MS
1042 * to nic-only mode or to offload mode. Offload mode is configured if either the
1043 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
1044 * registered for this port (which means that the user wants storage services).
1045 * 2. During cnic-related load, to know if offload mode is already configured in
16a5fd92 1046 * the HW or needs to be configured.
55c11941 1047 * Since the transition from nic-mode to offload-mode in HW causes traffic
16a5fd92 1048 * corruption, nic-mode is configured only in ports on which storage services
55c11941
MS
1049 * where never requested.
1050 */
1051#define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
a2fbb9ea 1052
34f80b04 1053 int flash_size;
754a2f52
DK
1054#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
1055#define BNX2X_NVRAM_TIMEOUT_COUNT 30000
1056#define BNX2X_NVRAM_PAGE_SIZE 256
a2fbb9ea 1057
34f80b04 1058 u32 shmem_base;
2691d51d 1059 u32 shmem2_base;
523224a3 1060 u32 mf_cfg_base;
f2e0899f 1061 u32 mf2_cfg_base;
34f80b04
EG
1062
1063 u32 hw_config;
c18487ee 1064
34f80b04 1065 u32 bc_ver;
523224a3
DK
1066
1067 u8 int_block;
1068#define INT_BLOCK_HC 0
f2e0899f
DK
1069#define INT_BLOCK_IGU 1
1070#define INT_BLOCK_MODE_NORMAL 0
1071#define INT_BLOCK_MODE_BW_COMP 2
1072#define CHIP_INT_MODE_IS_NBC(bp) \
619c5cb6 1073 (!CHIP_IS_E1x(bp) && \
f2e0899f
DK
1074 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
1075#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
1076
523224a3 1077 u8 chip_port_mode;
f2e0899f
DK
1078#define CHIP_4_PORT_MODE 0x0
1079#define CHIP_2_PORT_MODE 0x1
523224a3 1080#define CHIP_PORT_MODE_NONE 0x2
f2e0899f
DK
1081#define CHIP_MODE(bp) (bp->common.chip_port_mode)
1082#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
1d187b34
BW
1083
1084 u32 boot_mode;
34f80b04 1085};
c18487ee 1086
f2e0899f
DK
1087/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
1088#define BNX2X_IGU_STAS_MSG_VF_CNT 64
1089#define BNX2X_IGU_STAS_MSG_PF_CNT 4
34f80b04 1090
27c1151c 1091#define MAX_IGU_ATTN_ACK_TO 100
34f80b04
EG
1092/* end of common */
1093
1094/* port */
1095
1096struct bnx2x_port {
1097 u32 pmf;
c18487ee 1098
a22f0788 1099 u32 link_config[LINK_CONFIG_SIZE];
a2fbb9ea 1100
a22f0788 1101 u32 supported[LINK_CONFIG_SIZE];
34f80b04
EG
1102/* link settings - missing defines */
1103#define SUPPORTED_2500baseX_Full (1 << 15)
1104
a22f0788 1105 u32 advertising[LINK_CONFIG_SIZE];
a2fbb9ea 1106/* link settings - missing defines */
34f80b04 1107#define ADVERTISED_2500baseX_Full (1 << 15)
a2fbb9ea 1108
34f80b04 1109 u32 phy_addr;
c18487ee
YR
1110
1111 /* used to synchronize phy accesses */
1112 struct mutex phy_mutex;
1113
34f80b04 1114 u32 port_stx;
a2fbb9ea 1115
34f80b04
EG
1116 struct nig_stats old_nig_stats;
1117};
a2fbb9ea 1118
34f80b04
EG
1119/* end of port */
1120
619c5cb6
VZ
1121#define STATS_OFFSET32(stat_name) \
1122 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
bb2a0f7a 1123
619c5cb6
VZ
1124/* slow path */
1125
1126/* slow path work-queue */
1127extern struct workqueue_struct *bnx2x_wq;
1128
1129#define BNX2X_MAX_NUM_OF_VFS 64
b9871bcf 1130#define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */
1ab4434c 1131#define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
b9871bcf
AE
1132
1133/* We need to reserve doorbell addresses for all VF and queue combinations */
1ab4434c 1134#define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
b9871bcf
AE
1135
1136/* The doorbell is configured to have the same number of CIDs for PFs and for
1137 * VFs. For this reason the PF CID zone is as large as the VF zone.
1138 */
1139#define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS
1140#define BNX2X_MAX_NUM_VF_QUEUES 64
523224a3 1141#define BNX2X_VF_ID_INVALID 0xFF
34f80b04 1142
b9871bcf
AE
1143/* the number of VF CIDS multiplied by the amount of bytes reserved for each
1144 * cid must not exceed the size of the VF doorbell
1145 */
1146#define BNX2X_VF_BAR_SIZE 512
1147#if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1148#error "VF doorbell bar size is 512"
1149#endif
1150
523224a3
DK
1151/*
1152 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1153 * control by the number of fast-path status blocks supported by the
1154 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1155 * status block represents an independent interrupts context that can
1156 * serve a regular L2 networking queue. However special L2 queues such
1157 * as the FCoE queue do not require a FP-SB and other components like
1158 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1159 *
1160 * If the maximum number of FP-SB available is X then:
1161 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1162 * regular L2 queues is Y=X-1
16a5fd92 1163 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
523224a3
DK
1164 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1165 * is Y+1
1166 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1167 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1168 * FP interrupt context for the CNIC).
1169 * e. The number of HW context (CID count) is always X or X+1 if FCoE
16a5fd92 1170 * L2 queue is supported. The cid for the FCoE L2 queue is always X.
523224a3
DK
1171 */
1172
619c5cb6
VZ
1173/* fast-path interrupt contexts E1x */
1174#define FP_SB_MAX_E1x 16
1175/* fast-path interrupt contexts E2 */
1176#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
523224a3 1177
34f80b04
EG
1178union cdu_context {
1179 struct eth_context eth;
1180 char pad[1024];
1181};
1182
523224a3 1183/* CDU host DB constants */
a052997e
MS
1184#define CDU_ILT_PAGE_SZ_HW 2
1185#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
523224a3
DK
1186#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1187
523224a3 1188#define CNIC_ISCSI_CID_MAX 256
ec6ba945
VZ
1189#define CNIC_FCOE_CID_MAX 2048
1190#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
523224a3 1191#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
523224a3 1192
619c5cb6
VZ
1193#define QM_ILT_PAGE_SZ_HW 0
1194#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
523224a3
DK
1195#define QM_CID_ROUND 1024
1196
523224a3 1197/* TM (timers) host DB constants */
619c5cb6
VZ
1198#define TM_ILT_PAGE_SZ_HW 0
1199#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
0907f34c
AE
1200#define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \
1201 BNX2X_VF_CIDS + \
1202 CNIC_ISCSI_CID_MAX)
523224a3
DK
1203#define TM_ILT_SZ (8 * TM_CONN_NUM)
1204#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1205
1206/* SRC (Searcher) host DB constants */
619c5cb6
VZ
1207#define SRC_ILT_PAGE_SZ_HW 0
1208#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
523224a3
DK
1209#define SRC_HASH_BITS 10
1210#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1211#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1212#define SRC_T2_SZ SRC_ILT_SZ
1213#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
619c5cb6 1214
619c5cb6 1215#define MAX_DMAE_C 8
34f80b04
EG
1216
1217/* DMA memory not used in fastpath */
1218struct bnx2x_slowpath {
619c5cb6
VZ
1219 union {
1220 struct mac_configuration_cmd e1x;
1221 struct eth_classify_rules_ramrod_data e2;
1222 } mac_rdata;
1223
619c5cb6
VZ
1224 union {
1225 struct tstorm_eth_mac_filter_config e1x;
1226 struct eth_filter_rules_ramrod_data e2;
1227 } rx_mode_rdata;
1228
1229 union {
1230 struct mac_configuration_cmd e1;
1231 struct eth_multicast_rules_ramrod_data e2;
1232 } mcast_rdata;
1233
1234 struct eth_rss_update_ramrod_data rss_rdata;
1235
1236 /* Queue State related ramrods are always sent under rtnl_lock */
1237 union {
1238 struct client_init_ramrod_data init_data;
1239 struct client_update_ramrod_data update_data;
1240 } q_rdata;
1241
1242 union {
1243 struct function_start_data func_start;
6debea87
DK
1244 /* pfc configuration for DCBX ramrod */
1245 struct flow_control_configuration pfc_config;
619c5cb6 1246 } func_rdata;
34f80b04 1247
a3348722
BW
1248 /* afex ramrod can not be a part of func_rdata union because these
1249 * events might arrive in parallel to other events from func_rdata.
1250 * Therefore, if they would have been defined in the same union,
1251 * data can get corrupted.
1252 */
1253 struct afex_vif_list_ramrod_data func_afex_rdata;
1254
34f80b04
EG
1255 /* used by dmae command executer */
1256 struct dmae_command dmae[MAX_DMAE_C];
1257
bb2a0f7a
YG
1258 u32 stats_comp;
1259 union mac_stats mac_stats;
1260 struct nig_stats nig_stats;
1261 struct host_port_stats port_stats;
1262 struct host_func_stats func_stats;
34f80b04
EG
1263
1264 u32 wb_comp;
34f80b04 1265 u32 wb_data[4];
1d187b34
BW
1266
1267 union drv_info_to_mcp drv_info_to_mcp;
34f80b04
EG
1268};
1269
1270#define bnx2x_sp(bp, var) (&bp->slowpath->var)
1271#define bnx2x_sp_mapping(bp, var) \
1272 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1273
34f80b04
EG
1274/* attn group wiring */
1275#define MAX_DYNAMIC_ATTN_GRPS 8
1276
1277struct attn_route {
619c5cb6 1278 u32 sig[5];
34f80b04
EG
1279};
1280
523224a3
DK
1281struct iro {
1282 u32 base;
1283 u16 m1;
1284 u16 m2;
1285 u16 m3;
1286 u16 size;
1287};
1288
1289struct hw_context {
1290 union cdu_context *vcxt;
1291 dma_addr_t cxt_mapping;
1292 size_t size;
1293};
1294
1295/* forward */
1296struct bnx2x_ilt;
1297
290ca2bb 1298struct bnx2x_vfdb;
c9ee9206
VZ
1299
1300enum bnx2x_recovery_state {
72fd0718
VZ
1301 BNX2X_RECOVERY_DONE,
1302 BNX2X_RECOVERY_INIT,
1303 BNX2X_RECOVERY_WAIT,
95c6c616
AE
1304 BNX2X_RECOVERY_FAILED,
1305 BNX2X_RECOVERY_NIC_LOADING
c9ee9206 1306};
72fd0718 1307
619c5cb6 1308/*
523224a3
DK
1309 * Event queue (EQ or event ring) MC hsi
1310 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1311 */
1312#define NUM_EQ_PAGES 1
1313#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1314#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1315#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1316#define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1317#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1318
1319/* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1320#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1321 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1322
1323/* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1324#define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1325
1326#define BNX2X_EQ_INDEX \
1327 (&bp->def_status_blk->sp_sb.\
1328 index_values[HC_SP_INDEX_EQ_CONS])
1329
2ae17f66
VZ
1330/* This is a data that will be used to create a link report message.
1331 * We will keep the data used for the last link report in order
1332 * to prevent reporting the same link parameters twice.
1333 */
1334struct bnx2x_link_report_data {
1335 u16 line_speed; /* Effective line speed */
1336 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1337};
1338
1339enum {
1340 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1341 BNX2X_LINK_REPORT_LINK_DOWN,
1342 BNX2X_LINK_REPORT_RX_FC_ON,
1343 BNX2X_LINK_REPORT_TX_FC_ON,
1344};
1345
619c5cb6
VZ
1346enum {
1347 BNX2X_PORT_QUERY_IDX,
1348 BNX2X_PF_QUERY_IDX,
50f0a562 1349 BNX2X_FCOE_QUERY_IDX,
619c5cb6
VZ
1350 BNX2X_FIRST_QUEUE_QUERY_IDX,
1351};
1352
1353struct bnx2x_fw_stats_req {
1354 struct stats_query_header hdr;
50f0a562
BW
1355 struct stats_query_entry query[FP_SB_MAX_E1x+
1356 BNX2X_FIRST_QUEUE_QUERY_IDX];
619c5cb6
VZ
1357};
1358
1359struct bnx2x_fw_stats_data {
2de67439
YM
1360 struct stats_counter storm_counters;
1361 struct per_port_stats port;
1362 struct per_pf_stats pf;
50f0a562 1363 struct fcoe_statistics_params fcoe;
2de67439 1364 struct per_queue_stats queue_stats[1];
619c5cb6
VZ
1365};
1366
7be08a72
AE
1367/* Public slow path states */
1368enum {
6383c0b3 1369 BNX2X_SP_RTNL_SETUP_TC,
7be08a72 1370 BNX2X_SP_RTNL_TX_TIMEOUT,
8304859a 1371 BNX2X_SP_RTNL_FAN_FAILURE,
8395be5e
AE
1372 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1373 BNX2X_SP_RTNL_ENABLE_SRIOV,
381ac16b 1374 BNX2X_SP_RTNL_VFPF_MCAST,
78c3bcc5 1375 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
8b09be5f 1376 BNX2X_SP_RTNL_RX_MODE,
3ec9f9ca 1377 BNX2X_SP_RTNL_HYPERVISOR_VLAN,
07b4eb3b 1378 BNX2X_SP_RTNL_TX_STOP,
7be08a72
AE
1379};
1380
452427b0 1381struct bnx2x_prev_path_list {
7fa6f340 1382 struct list_head list;
452427b0
YM
1383 u8 bus;
1384 u8 slot;
1385 u8 path;
7fa6f340 1386 u8 aer;
c63da990 1387 u8 undi;
452427b0
YM
1388};
1389
15192a8c
BW
1390struct bnx2x_sp_objs {
1391 /* MACs object */
1392 struct bnx2x_vlan_mac_obj mac_obj;
1393
1394 /* Queue State object */
1395 struct bnx2x_queue_sp_obj q_obj;
1396};
1397
1398struct bnx2x_fp_stats {
1399 struct tstorm_per_queue_stats old_tclient;
1400 struct ustorm_per_queue_stats old_uclient;
1401 struct xstorm_per_queue_stats old_xclient;
1402 struct bnx2x_eth_q_stats eth_q_stats;
1403 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1404};
1405
34f80b04
EG
1406struct bnx2x {
1407 /* Fields used in the tx and intr/napi performance paths
1408 * are grouped together in the beginning of the structure
1409 */
523224a3 1410 struct bnx2x_fastpath *fp;
15192a8c
BW
1411 struct bnx2x_sp_objs *sp_objs;
1412 struct bnx2x_fp_stats *fp_stats;
65565884 1413 struct bnx2x_fp_txdata *bnx2x_txq;
34f80b04
EG
1414 void __iomem *regview;
1415 void __iomem *doorbells;
523224a3 1416 u16 db_size;
34f80b04 1417
619c5cb6
VZ
1418 u8 pf_num; /* absolute PF number */
1419 u8 pfid; /* per-path PF number */
1420 int base_fw_ndsb; /**/
1421#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1422#define BP_PORT(bp) (bp->pfid & 1)
1423#define BP_FUNC(bp) (bp->pfid)
1424#define BP_ABS_FUNC(bp) (bp->pf_num)
3395a033
DK
1425#define BP_VN(bp) ((bp)->pfid >> 1)
1426#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1427#define BP_L_ID(bp) (BP_VN(bp) << 2)
1428#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1429 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1430#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
619c5cb6 1431
6411280a 1432#ifdef CONFIG_BNX2X_SRIOV
1d6f3cd8
DK
1433 /* protects vf2pf mailbox from simultaneous access */
1434 struct mutex vf2pf_mutex;
1ab4434c
AE
1435 /* vf pf channel mailbox contains request and response buffers */
1436 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1437 dma_addr_t vf2pf_mbox_mapping;
1438
be1f1ffa
AE
1439 /* we set aside a copy of the acquire response */
1440 struct pfvf_acquire_resp_tlv acquire_resp;
1441
abc5a021
AE
1442 /* bulletin board for messages from pf to vf */
1443 union pf_vf_bulletin *pf2vf_bulletin;
1444 dma_addr_t pf2vf_bulletin_mapping;
1445
1446 struct pf_vf_bulletin_content old_bulletin;
3c76feff
AE
1447
1448 u16 requested_nr_virtfn;
6411280a 1449#endif /* CONFIG_BNX2X_SRIOV */
abc5a021 1450
34f80b04
EG
1451 struct net_device *dev;
1452 struct pci_dev *pdev;
1453
619c5cb6 1454 const struct iro *iro_arr;
523224a3
DK
1455#define IRO (bp->iro_arr)
1456
c9ee9206 1457 enum bnx2x_recovery_state recovery_state;
72fd0718 1458 int is_leader;
523224a3 1459 struct msix_entry *msix_table;
34f80b04
EG
1460
1461 int tx_ring_size;
1462
523224a3
DK
1463/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1464#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
34f80b04
EG
1465#define ETH_MIN_PACKET_SIZE 60
1466#define ETH_MAX_PACKET_SIZE 1500
1467#define ETH_MAX_JUMBO_PACKET_SIZE 9600
621b4d66
DK
1468/* TCP with Timestamp Option (32) + IPv6 (40) */
1469#define ETH_MAX_TPA_HEADER_SIZE 72
a2fbb9ea 1470
0f00846d 1471 /* Max supported alignment is 256 (8 shift) */
e52fcb24
ED
1472#define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1473
1474 /* FW uses 2 Cache lines Alignment for start packet and size
1475 *
1476 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1477 * at the end of skb->data, to avoid wasting a full cache line.
1478 * This reduces memory use (skb->truesize).
1479 */
1480#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1481
1482#define BNX2X_FW_RX_ALIGN_END \
f57b07c0 1483 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
e52fcb24
ED
1484 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1485
523224a3 1486#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
0f00846d 1487
523224a3
DK
1488 struct host_sp_status_block *def_status_blk;
1489#define DEF_SB_IGU_ID 16
1490#define DEF_SB_ID HC_SP_SB_ID
1491 __le16 def_idx;
4781bfad 1492 __le16 def_att_idx;
34f80b04
EG
1493 u32 attn_state;
1494 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
34f80b04
EG
1495
1496 /* slow path ring */
1497 struct eth_spe *spq;
1498 dma_addr_t spq_mapping;
1499 u16 spq_prod_idx;
1500 struct eth_spe *spq_prod_bd;
1501 struct eth_spe *spq_last_bd;
4781bfad 1502 __le16 *dsb_sp_prod;
6e30dd4e 1503 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
34f80b04
EG
1504 /* used to synchronize spq accesses */
1505 spinlock_t spq_lock;
1506
523224a3
DK
1507 /* event queue */
1508 union event_ring_elem *eq_ring;
1509 dma_addr_t eq_mapping;
1510 u16 eq_prod;
1511 u16 eq_cons;
1512 __le16 *eq_cons_sb;
6e30dd4e 1513 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
523224a3 1514
619c5cb6
VZ
1515 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1516 u16 stats_pending;
1517 /* Counter for completed statistics ramrods */
1518 u16 stats_comp;
34f80b04 1519
33471629 1520 /* End of fields used in the performance code paths */
34f80b04
EG
1521
1522 int panic;
7995c64e 1523 int msg_enable;
34f80b04
EG
1524
1525 u32 flags;
619c5cb6
VZ
1526#define PCIX_FLAG (1 << 0)
1527#define PCI_32BIT_FLAG (1 << 1)
1528#define ONE_PORT_FLAG (1 << 2)
1529#define NO_WOL_FLAG (1 << 3)
619c5cb6
VZ
1530#define USING_MSIX_FLAG (1 << 5)
1531#define USING_MSI_FLAG (1 << 6)
1532#define DISABLE_MSI_FLAG (1 << 7)
1533#define TPA_ENABLE_FLAG (1 << 8)
1534#define NO_MCP_FLAG (1 << 9)
621b4d66 1535#define GRO_ENABLE_FLAG (1 << 10)
619c5cb6
VZ
1536#define MF_FUNC_DIS (1 << 11)
1537#define OWN_CNIC_IRQ (1 << 12)
1538#define NO_ISCSI_OOO_FLAG (1 << 13)
1539#define NO_ISCSI_FLAG (1 << 14)
1540#define NO_FCOE_FLAG (1 << 15)
0e898dd7 1541#define BC_SUPPORTS_PFC_STATS (1 << 17)
2e499d3c 1542#define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
30a5de77 1543#define USING_SINGLE_MSIX_FLAG (1 << 20)
9876879f 1544#define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1ab4434c 1545#define IS_VF_FLAG (1 << 22)
78c3bcc5 1546#define INTERRUPTS_ENABLED_FLAG (1 << 23)
a6d3a5ba 1547#define BC_SUPPORTS_RMMOD_CMD (1 << 24)
3d7d562c 1548#define HAS_PHYS_PORT_ID (1 << 25)
1ab4434c
AE
1549
1550#define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
6411280a
AE
1551
1552#ifdef CONFIG_BNX2X_SRIOV
1ab4434c
AE
1553#define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1554#define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
6411280a
AE
1555#else
1556#define IS_VF(bp) false
1557#define IS_PF(bp) true
1558#endif
ec6ba945 1559
2ba45142
VZ
1560#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1561#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
619c5cb6 1562#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
37b091ba 1563
55c11941
MS
1564 u8 cnic_support;
1565 bool cnic_enabled;
1566 bool cnic_loaded;
4bd9b0ff 1567 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
55c11941
MS
1568
1569 /* Flag that indicates that we can start looking for FCoE L2 queue
1570 * completions in the default status block.
1571 */
1572 bool fcoe_init;
1573
8d5726c4 1574 int mrrs;
34f80b04 1575
1cf167f2 1576 struct delayed_work sp_task;
fd1fc79d 1577 atomic_t interrupt_occurred;
7be08a72 1578 struct delayed_work sp_rtnl_task;
3deb8167
YR
1579
1580 struct delayed_work period_task;
34f80b04 1581 struct timer_list timer;
34f80b04
EG
1582 int current_interval;
1583
1584 u16 fw_seq;
1585 u16 fw_drv_pulse_wr_seq;
1586 u32 func_stx;
1587
1588 struct link_params link_params;
1589 struct link_vars link_vars;
2ae17f66
VZ
1590 u32 link_cnt;
1591 struct bnx2x_link_report_data last_reported_link;
1592
01cd4528 1593 struct mdio_if_info mdio;
a2fbb9ea 1594
34f80b04
EG
1595 struct bnx2x_common common;
1596 struct bnx2x_port port;
1597
b475d78f
YM
1598 struct cmng_init cmng;
1599
f2e0899f 1600 u32 mf_config[E1HVN_MAX];
a3348722 1601 u32 mf_ext_config;
619c5cb6 1602 u32 path_has_ovlan; /* E3 */
fb3bff17
DK
1603 u16 mf_ov;
1604 u8 mf_mode;
f85582f8 1605#define IS_MF(bp) (bp->mf_mode != 0)
0793f83f
DK
1606#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1607#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
a3348722 1608#define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
a2fbb9ea 1609
f1410647
ET
1610 u8 wol;
1611
34f80b04 1612 int rx_ring_size;
a2fbb9ea 1613
34f80b04
EG
1614 u16 tx_quick_cons_trip_int;
1615 u16 tx_quick_cons_trip;
1616 u16 tx_ticks_int;
1617 u16 tx_ticks;
a2fbb9ea 1618
34f80b04
EG
1619 u16 rx_quick_cons_trip_int;
1620 u16 rx_quick_cons_trip;
1621 u16 rx_ticks_int;
1622 u16 rx_ticks;
cdaa7cb8 1623/* Maximal coalescing timeout in us */
6802516e 1624#define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR)
a2fbb9ea 1625
34f80b04 1626 u32 lin_cnt;
a2fbb9ea 1627
619c5cb6 1628 u16 state;
356e2385 1629#define BNX2X_STATE_CLOSED 0
34f80b04
EG
1630#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1631#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
a2fbb9ea 1632#define BNX2X_STATE_OPEN 0x3000
34f80b04 1633#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
a2fbb9ea 1634#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
619c5cb6 1635
34f80b04
EG
1636#define BNX2X_STATE_DIAG 0xe000
1637#define BNX2X_STATE_ERROR 0xf000
a2fbb9ea 1638
6383c0b3
AE
1639#define BNX2X_MAX_PRIORITY 8
1640#define BNX2X_MAX_ENTRIES_PER_PRI 16
1641#define BNX2X_MAX_COS 3
1642#define BNX2X_MAX_TX_COS 2
54b9ddaa 1643 int num_queues;
55c11941
MS
1644 uint num_ethernet_queues;
1645 uint num_cnic_queues;
0e8d2ec5 1646 int num_napi_queues;
5d7cd496 1647 int disable_tpa;
523224a3 1648
34f80b04
EG
1649 u32 rx_mode;
1650#define BNX2X_RX_MODE_NONE 0
1651#define BNX2X_RX_MODE_NORMAL 1
1652#define BNX2X_RX_MODE_ALLMULTI 2
1653#define BNX2X_RX_MODE_PROMISC 3
1654#define BNX2X_MAX_MULTICAST 64
a2fbb9ea 1655
523224a3
DK
1656 u8 igu_dsb_id;
1657 u8 igu_base_sb;
1658 u8 igu_sb_cnt;
55c11941 1659 u8 min_msix_vec_cnt;
65565884 1660
1ab4434c 1661 u32 igu_base_addr;
34f80b04 1662 dma_addr_t def_status_blk_mapping;
a2fbb9ea 1663
34f80b04
EG
1664 struct bnx2x_slowpath *slowpath;
1665 dma_addr_t slowpath_mapping;
619c5cb6
VZ
1666
1667 /* Total number of FW statistics requests */
1668 u8 fw_stats_num;
1669
1670 /*
1671 * This is a memory buffer that will contain both statistics
1672 * ramrod request and data.
1673 */
1674 void *fw_stats;
1675 dma_addr_t fw_stats_mapping;
1676
1677 /*
1678 * FW statistics request shortcut (points at the
1679 * beginning of fw_stats buffer).
1680 */
1681 struct bnx2x_fw_stats_req *fw_stats_req;
1682 dma_addr_t fw_stats_req_mapping;
1683 int fw_stats_req_sz;
1684
1685 /*
4907cb7b 1686 * FW statistics data shortcut (points at the beginning of
619c5cb6
VZ
1687 * fw_stats buffer + fw_stats_req_sz).
1688 */
1689 struct bnx2x_fw_stats_data *fw_stats_data;
1690 dma_addr_t fw_stats_data_mapping;
1691 int fw_stats_data_sz;
1692
b9871bcf 1693 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB
a052997e
MS
1694 * context size we need 8 ILT entries.
1695 */
b9871bcf 1696#define ILT_MAX_L2_LINES 32
a052997e 1697 struct hw_context context[ILT_MAX_L2_LINES];
523224a3
DK
1698
1699 struct bnx2x_ilt *ilt;
1700#define BP_ILT(bp) ((bp)->ilt)
619c5cb6 1701#define ILT_MAX_LINES 256
6383c0b3
AE
1702/*
1703 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1704 * to CNIC.
1705 */
55c11941 1706#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
523224a3 1707
6383c0b3
AE
1708/*
1709 * Maximum CID count that might be required by the bnx2x:
37ae41a9 1710 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
6383c0b3 1711 */
f78afb35 1712
37ae41a9 1713#define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
f78afb35 1714 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
37ae41a9 1715#define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
f78afb35 1716 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
6383c0b3
AE
1717#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1718 ILT_PAGE_CIDS))
523224a3
DK
1719
1720 int qm_cid_count;
a2fbb9ea 1721
7964211d 1722 bool dropless_fc;
a18f5128 1723
37b091ba
MC
1724 void *t2;
1725 dma_addr_t t2_mapping;
13707f9e 1726 struct cnic_ops __rcu *cnic_ops;
37b091ba
MC
1727 void *cnic_data;
1728 u32 cnic_tag;
1729 struct cnic_eth_dev cnic_eth_dev;
523224a3 1730 union host_hc_status_block cnic_sb;
37b091ba 1731 dma_addr_t cnic_sb_mapping;
37b091ba
MC
1732 struct eth_spe *cnic_kwq;
1733 struct eth_spe *cnic_kwq_prod;
1734 struct eth_spe *cnic_kwq_cons;
1735 struct eth_spe *cnic_kwq_last;
1736 u16 cnic_kwq_pending;
1737 u16 cnic_spq_pending;
ec6ba945 1738 u8 fip_mac[ETH_ALEN];
619c5cb6
VZ
1739 struct mutex cnic_mutex;
1740 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1741
16a5fd92 1742 /* Start index of the "special" (CNIC related) L2 clients */
619c5cb6 1743 u8 cnic_base_cl_id;
37b091ba 1744
ad8d3948
EG
1745 int dmae_ready;
1746 /* used to synchronize dmae accesses */
6e30dd4e 1747 spinlock_t dmae_lock;
ad8d3948 1748
c4ff7cbf
EG
1749 /* used to protect the FW mail box */
1750 struct mutex fw_mb_mutex;
1751
bb2a0f7a
YG
1752 /* used to synchronize stats collecting */
1753 int stats_state;
a13773a5
VZ
1754
1755 /* used for synchronization of concurrent threads statistics handling */
1756 spinlock_t stats_lock;
1757
bb2a0f7a
YG
1758 /* used by dmae command loader */
1759 struct dmae_command stats_dmae;
1760 int executer_idx;
ad8d3948 1761
bb2a0f7a 1762 u16 stats_counter;
bb2a0f7a 1763 struct bnx2x_eth_stats eth_stats;
cb4dca27 1764 struct host_func_stats func_stats;
1355b704
MY
1765 struct bnx2x_eth_stats_old eth_stats_old;
1766 struct bnx2x_net_stats_old net_stats_old;
1767 struct bnx2x_fw_port_stats_old fw_stats_old;
1768 bool stats_init;
bb2a0f7a
YG
1769
1770 struct z_stream_s *strm;
1771 void *gunzip_buf;
1772 dma_addr_t gunzip_mapping;
1773 int gunzip_outlen;
ad8d3948 1774#define FW_BUF_SIZE 0x8000
573f2035
EG
1775#define GUNZIP_BUF(bp) (bp->gunzip_buf)
1776#define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1777#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
a2fbb9ea 1778
ab6ad5a4 1779 struct raw_op *init_ops;
94a78b79 1780 /* Init blocks offsets inside init_ops */
ab6ad5a4 1781 u16 *init_ops_offsets;
94a78b79 1782 /* Data blob - has 32 bit granularity */
ab6ad5a4 1783 u32 *init_data;
619c5cb6
VZ
1784 u32 init_mode_flags;
1785#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
94a78b79 1786 /* Zipped PRAM blobs - raw data */
ab6ad5a4
EG
1787 const u8 *tsem_int_table_data;
1788 const u8 *tsem_pram_data;
1789 const u8 *usem_int_table_data;
1790 const u8 *usem_pram_data;
1791 const u8 *xsem_int_table_data;
1792 const u8 *xsem_pram_data;
1793 const u8 *csem_int_table_data;
1794 const u8 *csem_pram_data;
573f2035
EG
1795#define INIT_OPS(bp) (bp->init_ops)
1796#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1797#define INIT_DATA(bp) (bp->init_data)
1798#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1799#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1800#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1801#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1802#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1803#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1804#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1805#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1806
619c5cb6 1807#define PHY_FW_VER_LEN 20
34f24c7f 1808 char fw_ver[32];
ab6ad5a4 1809 const struct firmware *firmware;
619c5cb6 1810
290ca2bb
AE
1811 struct bnx2x_vfdb *vfdb;
1812#define IS_SRIOV(bp) ((bp)->vfdb)
1813
785b9b1a
SR
1814 /* DCB support on/off */
1815 u16 dcb_state;
1816#define BNX2X_DCB_STATE_OFF 0
1817#define BNX2X_DCB_STATE_ON 1
1818
1819 /* DCBX engine mode */
1820 int dcbx_enabled;
1821#define BNX2X_DCBX_ENABLED_OFF 0
1822#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1823#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1824#define BNX2X_DCBX_ENABLED_INVALID (-1)
1825
1826 bool dcbx_mode_uset;
1827
e4901dde 1828 struct bnx2x_config_dcbx_params dcbx_config_params;
e4901dde
VZ
1829 struct bnx2x_dcbx_port_params dcbx_port_params;
1830 int dcb_version;
1831
619c5cb6 1832 /* CAM credit pools */
b56e9670
AE
1833
1834 /* used only in sriov */
1835 struct bnx2x_credit_pool_obj vlans_pool;
1836
619c5cb6
VZ
1837 struct bnx2x_credit_pool_obj macs_pool;
1838
1839 /* RX_MODE object */
1840 struct bnx2x_rx_mode_obj rx_mode_obj;
1841
1842 /* MCAST object */
1843 struct bnx2x_mcast_obj mcast_obj;
1844
1845 /* RSS configuration object */
1846 struct bnx2x_rss_config_obj rss_conf_obj;
1847
1848 /* Function State controlling object */
1849 struct bnx2x_func_sp_obj func_obj;
1850
1851 unsigned long sp_state;
1852
7be08a72
AE
1853 /* operation indication for the sp_rtnl task */
1854 unsigned long sp_rtnl_state;
1855
16a5fd92 1856 /* DCBX Negotiation results */
e4901dde
VZ
1857 struct dcbx_features dcbx_local_feat;
1858 u32 dcbx_error;
619c5cb6 1859
0be6bc62
SR
1860#ifdef BCM_DCBNL
1861 struct dcbx_features dcbx_remote_feat;
1862 u32 dcbx_remote_flags;
1863#endif
a3348722
BW
1864 /* AFEX: store default vlan used */
1865 int afex_def_vlan_tag;
1866 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
e3835b99 1867 u32 pending_max;
6383c0b3
AE
1868
1869 /* multiple tx classes of service */
1870 u8 max_cos;
1871
1872 /* priority to cos mapping */
1873 u8 prio_to_cos[8];
c3146eb6
DK
1874
1875 int fp_array_size;
07ba6af4 1876 u32 dump_preset_idx;
507393eb
DK
1877 bool stats_started;
1878 struct semaphore stats_sema;
3d7d562c
YM
1879
1880 u8 phys_port_id[ETH_ALEN];
a2fbb9ea
ET
1881};
1882
619c5cb6
VZ
1883/* Tx queues may be less or equal to Rx queues */
1884extern int num_queues;
54b9ddaa 1885#define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
55c11941 1886#define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
65565884 1887#define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
55c11941 1888 (bp)->num_cnic_queues)
6383c0b3 1889#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
ec6ba945 1890
54b9ddaa 1891#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
3196a88a 1892
6383c0b3
AE
1893#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1894/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
523224a3
DK
1895
1896#define RSS_IPV4_CAP_MASK \
1897 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1898
1899#define RSS_IPV4_TCP_CAP_MASK \
1900 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1901
1902#define RSS_IPV6_CAP_MASK \
1903 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1904
1905#define RSS_IPV6_TCP_CAP_MASK \
1906 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1907
1908/* func init flags */
619c5cb6
VZ
1909#define FUNC_FLG_RSS 0x0001
1910#define FUNC_FLG_STATS 0x0002
1911/* removed FUNC_FLG_UNMATCHED 0x0004 */
1912#define FUNC_FLG_TPA 0x0008
1913#define FUNC_FLG_SPQ 0x0010
1914#define FUNC_FLG_LEADING 0x0020 /* PF only */
b9871bcf 1915#define FUNC_FLG_LEADING_STATS 0x0040
523224a3 1916struct bnx2x_func_init_params {
523224a3
DK
1917 /* dma */
1918 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1919 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1920
1921 u16 func_flgs;
1922 u16 func_id; /* abs fid */
1923 u16 pf_id;
1924 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1925};
1926
55c11941
MS
1927#define for_each_cnic_queue(bp, var) \
1928 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1929 (var)++) \
1930 if (skip_queue(bp, var)) \
1931 continue; \
1932 else
1933
ec6ba945 1934#define for_each_eth_queue(bp, var) \
6383c0b3 1935 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
ec6ba945
VZ
1936
1937#define for_each_nondefault_eth_queue(bp, var) \
6383c0b3 1938 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
ec6ba945 1939
555f6c78 1940#define for_each_queue(bp, var) \
6383c0b3 1941 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
ec6ba945
VZ
1942 if (skip_queue(bp, var)) \
1943 continue; \
1944 else
1945
6383c0b3 1946/* Skip forwarding FP */
55c11941
MS
1947#define for_each_valid_rx_queue(bp, var) \
1948 for ((var) = 0; \
1949 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1950 BNX2X_NUM_ETH_QUEUES(bp)); \
1951 (var)++) \
1952 if (skip_rx_queue(bp, var)) \
1953 continue; \
1954 else
1955
1956#define for_each_rx_queue_cnic(bp, var) \
1957 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1958 (var)++) \
1959 if (skip_rx_queue(bp, var)) \
1960 continue; \
1961 else
1962
ec6ba945 1963#define for_each_rx_queue(bp, var) \
6383c0b3 1964 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
ec6ba945
VZ
1965 if (skip_rx_queue(bp, var)) \
1966 continue; \
1967 else
1968
6383c0b3 1969/* Skip OOO FP */
55c11941
MS
1970#define for_each_valid_tx_queue(bp, var) \
1971 for ((var) = 0; \
1972 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1973 BNX2X_NUM_ETH_QUEUES(bp)); \
1974 (var)++) \
1975 if (skip_tx_queue(bp, var)) \
1976 continue; \
1977 else
1978
1979#define for_each_tx_queue_cnic(bp, var) \
1980 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1981 (var)++) \
1982 if (skip_tx_queue(bp, var)) \
1983 continue; \
1984 else
1985
ec6ba945 1986#define for_each_tx_queue(bp, var) \
6383c0b3 1987 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
ec6ba945
VZ
1988 if (skip_tx_queue(bp, var)) \
1989 continue; \
1990 else
1991
3196a88a 1992#define for_each_nondefault_queue(bp, var) \
6383c0b3 1993 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
ec6ba945
VZ
1994 if (skip_queue(bp, var)) \
1995 continue; \
1996 else
3196a88a 1997
6383c0b3
AE
1998#define for_each_cos_in_tx_queue(fp, var) \
1999 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
2000
ec6ba945 2001/* skip rx queue
008d23e4 2002 * if FCOE l2 support is disabled and this is the fcoe L2 queue
ec6ba945
VZ
2003 */
2004#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2005
2006/* skip tx queue
008d23e4 2007 * if FCOE l2 support is disabled and this is the fcoe L2 queue
ec6ba945
VZ
2008 */
2009#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2010
2011#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
3196a88a 2012
619c5cb6
VZ
2013/**
2014 * bnx2x_set_mac_one - configure a single MAC address
2015 *
2016 * @bp: driver handle
2017 * @mac: MAC to configure
2018 * @obj: MAC object handle
2019 * @set: if 'true' add a new MAC, otherwise - delete
2020 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
2021 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
2022 *
2023 * Configures one MAC according to provided parameters or continues the
2024 * execution of previously scheduled commands if RAMROD_CONT is set in
2025 * ramrod_flags.
2026 *
2027 * Returns zero if operation has successfully completed, a positive value if the
2028 * operation has been successfully scheduled and a negative - if a requested
2029 * operations has failed.
2030 */
2031int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
2032 struct bnx2x_vlan_mac_obj *obj, bool set,
2033 int mac_type, unsigned long *ramrod_flags);
619c5cb6
VZ
2034/**
2035 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2036 *
2037 * @bp: driver handle
2038 * @mac_obj: MAC object handle
2039 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
2040 * @wait_for_comp: if 'true' block until completion
2041 *
2042 * Deletes all MACs of the specific type (e.g. ETH, UC list).
2043 *
2044 * Returns zero if operation has successfully completed, a positive value if the
2045 * operation has been successfully scheduled and a negative - if a requested
2046 * operations has failed.
2047 */
2048int bnx2x_del_all_macs(struct bnx2x *bp,
2049 struct bnx2x_vlan_mac_obj *mac_obj,
2050 int mac_type, bool wait_for_comp);
2051
2052/* Init Function API */
2053void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
b93288d5
AE
2054void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2055 u8 vf_valid, int fw_sb_id, int igu_sb_id);
b56e9670 2056u32 bnx2x_get_pretend_reg(struct bnx2x *bp);
619c5cb6
VZ
2057int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2058int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2059int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2060int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2ae17f66
VZ
2061void bnx2x_read_mf_cfg(struct bnx2x *bp);
2062
b56e9670 2063int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
619c5cb6 2064
f85582f8 2065/* dmae */
c18487ee
YR
2066void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2067void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2068 u32 len32);
f85582f8
DK
2069void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2070u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
2071u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
2072u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2073 bool with_comp, u8 comp_type);
2074
fd1fc79d
AE
2075void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2076 u8 src_type, u8 dst_type);
32316a46
AE
2077int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2078 u32 *comp);
fd1fc79d 2079
d16132ce
AE
2080/* FLR related routines */
2081u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2082void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2083int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
b56e9670 2084u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
d16132ce
AE
2085int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2086 char *msg, u32 poll_cnt);
f85582f8 2087
de0c62db
DK
2088void bnx2x_calc_fc_adv(struct bnx2x *bp);
2089int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 2090 u32 data_hi, u32 data_lo, int cmd_type);
de0c62db 2091void bnx2x_update_coalesce(struct bnx2x *bp);
1ac9e428 2092int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
f85582f8 2093
178135c1
DK
2094bool bnx2x_port_after_undi(struct bnx2x *bp);
2095
34f80b04
EG
2096static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
2097 int wait)
2098{
2099 u32 val;
2100
2101 do {
2102 val = REG_RD(bp, reg);
2103 if (val == expected)
2104 break;
2105 ms -= wait;
2106 msleep(wait);
2107
2108 } while (ms > 0);
2109
2110 return val;
2111}
f85582f8 2112
b56e9670
AE
2113void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2114 bool is_pf);
2115
ede23fa8
JP
2116#define BNX2X_ILT_ZALLOC(x, y, size) \
2117 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
523224a3
DK
2118
2119#define BNX2X_ILT_FREE(x, y, size) \
2120 do { \
2121 if (x) { \
d245a111 2122 dma_free_coherent(&bp->pdev->dev, size, x, y); \
523224a3
DK
2123 x = NULL; \
2124 y = 0; \
2125 } \
2126 } while (0)
2127
2128#define ILOG2(x) (ilog2((x)))
2129
2130#define ILT_NUM_PAGE_ENTRIES (3072)
2131/* In 57710/11 we use whole table since we have 8 func
f85582f8
DK
2132 * In 57712 we have only 4 func, but use same size per func, then only half of
2133 * the table in use
523224a3
DK
2134 */
2135#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
2136
2137#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
2138/*
2139 * the phys address is shifted right 12 bits and has an added
2140 * 1=valid bit added to the 53rd bit
2141 * then since this is a wide register(TM)
2142 * we split it into two 32 bit writes
2143 */
2144#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2145#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
34f80b04 2146
34f80b04
EG
2147/* load/unload mode */
2148#define LOAD_NORMAL 0
2149#define LOAD_OPEN 1
2150#define LOAD_DIAG 2
8970b2e4 2151#define LOAD_LOOPBACK_EXT 3
34f80b04
EG
2152#define UNLOAD_NORMAL 0
2153#define UNLOAD_CLOSE 1
f85582f8 2154#define UNLOAD_RECOVERY 2
34f80b04 2155
ad8d3948 2156/* DMAE command defines */
f2e0899f
DK
2157#define DMAE_TIMEOUT -1
2158#define DMAE_PCI_ERROR -2 /* E2 and onward */
2159#define DMAE_NOT_RDY -3
2160#define DMAE_PCI_ERR_FLAG 0x80000000
2161
2162#define DMAE_SRC_PCI 0
2163#define DMAE_SRC_GRC 1
2164
2165#define DMAE_DST_NONE 0
2166#define DMAE_DST_PCI 1
2167#define DMAE_DST_GRC 2
2168
2169#define DMAE_COMP_PCI 0
2170#define DMAE_COMP_GRC 1
2171
2172/* E2 and onward - PCI error handling in the completion */
2173
2174#define DMAE_COMP_REGULAR 0
2175#define DMAE_COM_SET_ERR 1
ad8d3948 2176
f2e0899f
DK
2177#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2178 DMAE_COMMAND_SRC_SHIFT)
2179#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2180 DMAE_COMMAND_SRC_SHIFT)
ad8d3948 2181
f2e0899f
DK
2182#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2183 DMAE_COMMAND_DST_SHIFT)
2184#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2185 DMAE_COMMAND_DST_SHIFT)
2186
2187#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2188 DMAE_COMMAND_C_DST_SHIFT)
2189#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2190 DMAE_COMMAND_C_DST_SHIFT)
ad8d3948
EG
2191
2192#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2193
2194#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2195#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2196#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2197#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2198
2199#define DMAE_CMD_PORT_0 0
2200#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2201
2202#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2203#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2204#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2205
f2e0899f
DK
2206#define DMAE_SRC_PF 0
2207#define DMAE_SRC_VF 1
2208
2209#define DMAE_DST_PF 0
2210#define DMAE_DST_VF 1
2211
2212#define DMAE_C_SRC 0
2213#define DMAE_C_DST 1
2214
ad8d3948 2215#define DMAE_LEN32_RD_MAX 0x80
02e3c6cb 2216#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
ad8d3948 2217
f2e0899f 2218#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
16a5fd92
YM
2219 * indicates error
2220 */
ad8d3948
EG
2221
2222#define MAX_DMAE_C_PER_PORT 8
ab6ad5a4 2223#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
3395a033 2224 BP_VN(bp))
ab6ad5a4 2225#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
ad8d3948
EG
2226 E1HVN_MAX)
2227
25047950
ET
2228/* PCIE link and speed */
2229#define PCICFG_LINK_WIDTH 0x1f00000
2230#define PCICFG_LINK_WIDTH_SHIFT 20
2231#define PCICFG_LINK_SPEED 0xf0000
2232#define PCICFG_LINK_SPEED_SHIFT 16
a2fbb9ea 2233
cf2c1df6
MS
2234#define BNX2X_NUM_TESTS_SF 7
2235#define BNX2X_NUM_TESTS_MF 3
2236#define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
75543741 2237 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
bb2a0f7a 2238
b5bf9068
EG
2239#define BNX2X_PHY_LOOPBACK 0
2240#define BNX2X_MAC_LOOPBACK 1
8970b2e4 2241#define BNX2X_EXT_LOOPBACK 2
b5bf9068
EG
2242#define BNX2X_PHY_LOOPBACK_FAILED 1
2243#define BNX2X_MAC_LOOPBACK_FAILED 2
8970b2e4 2244#define BNX2X_EXT_LOOPBACK_FAILED 3
bb2a0f7a
YG
2245#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2246 BNX2X_PHY_LOOPBACK_FAILED)
96fc1784 2247
7a9b2557
VZ
2248#define STROM_ASSERT_ARRAY_SIZE 50
2249
34f80b04 2250/* must be used on a CID before placing it on a HW ring */
ab6ad5a4 2251#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
3395a033 2252 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
619c5cb6 2253 (x))
7a9b2557
VZ
2254
2255#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2256#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2257
523224a3 2258#define BNX2X_BTR 4
7a9b2557 2259#define MAX_SPQ_PENDING 8
a2fbb9ea 2260
ff80ee02
DK
2261/* CMNG constants, as derived from system spec calculations */
2262/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2263#define DEF_MIN_RATE 100
9b3de1ef
DK
2264/* resolution of the rate shaping timer - 400 usec */
2265#define RS_PERIODIC_TIMEOUT_USEC 400
34f80b04 2266/* number of bytes in single QM arbitration cycle -
ff80ee02
DK
2267 * coefficient for calculating the fairness timer */
2268#define QM_ARB_BYTES 160000
2269/* resolution of Min algorithm 1:100 */
2270#define MIN_RES 100
2271/* how many bytes above threshold for the minimal credit of Min algorithm*/
2272#define MIN_ABOVE_THRESH 32768
2273/* Fairness algorithm integration time coefficient -
2274 * for calculating the actual Tfair */
2275#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2276/* Memory of fairness algorithm . 2 cycles */
2277#define FAIR_MEM 2
34f80b04 2278
34f80b04
EG
2279#define ATTN_NIG_FOR_FUNC (1L << 8)
2280#define ATTN_SW_TIMER_4_FUNC (1L << 9)
2281#define GPIO_2_FUNC (1L << 10)
2282#define GPIO_3_FUNC (1L << 11)
2283#define GPIO_4_FUNC (1L << 12)
2284#define ATTN_GENERAL_ATTN_1 (1L << 13)
2285#define ATTN_GENERAL_ATTN_2 (1L << 14)
2286#define ATTN_GENERAL_ATTN_3 (1L << 15)
2287#define ATTN_GENERAL_ATTN_4 (1L << 13)
2288#define ATTN_GENERAL_ATTN_5 (1L << 14)
2289#define ATTN_GENERAL_ATTN_6 (1L << 15)
2290
2291#define ATTN_HARD_WIRED_MASK 0xff00
2292#define ATTENTION_ID 4
a2fbb9ea 2293
3521b419
YM
2294#define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \
2295 IS_MF_FCOE_AFEX(bp))
a2fbb9ea 2296
34f80b04
EG
2297/* stuff added to make the code fit 80Col */
2298
2299#define BNX2X_PMF_LINK_ASSERT \
2300 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2301
a2fbb9ea
ET
2302#define BNX2X_MC_ASSERT_BITS \
2303 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2304 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2305 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2306 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2307
2308#define BNX2X_MCP_ASSERT \
2309 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2310
34f80b04
EG
2311#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2312#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2313 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2314 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2315 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2316 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2317 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2318
a2fbb9ea
ET
2319#define HW_INTERRUT_ASSERT_SET_0 \
2320 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2321 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2322 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
c14a09b7 2323 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
c9ee9206 2324 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
34f80b04 2325#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
a2fbb9ea
ET
2326 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2327 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2328 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
c9ee9206
VZ
2329 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2330 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2331 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
a2fbb9ea
ET
2332#define HW_INTERRUT_ASSERT_SET_1 \
2333 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2334 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2335 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2336 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2337 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2338 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2339 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2340 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2341 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2342 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2343 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
c9ee9206 2344#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
a2fbb9ea 2345 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
c9ee9206 2346 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
a2fbb9ea 2347 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
c9ee9206 2348 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
a2fbb9ea 2349 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
ab6ad5a4 2350 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
c9ee9206 2351 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
ab6ad5a4 2352 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
a2fbb9ea
ET
2353 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2354 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
c9ee9206 2355 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
a2fbb9ea
ET
2356 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2357 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
c9ee9206
VZ
2358 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2359 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
a2fbb9ea
ET
2360#define HW_INTERRUT_ASSERT_SET_2 \
2361 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2362 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2363 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2364 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2365 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
34f80b04 2366#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
a2fbb9ea
ET
2367 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2368 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2369 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2370 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
c9ee9206 2371 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
a2fbb9ea
ET
2372 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2373 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2374
72fd0718
VZ
2375#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2376 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2377 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2378 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
a2fbb9ea 2379
8736c826
VZ
2380#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2381 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2382
34f80b04 2383#define MULTI_MASK 0x7f
a2fbb9ea 2384
619c5cb6
VZ
2385#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2386#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2387#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2388#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2389
2390#define DEF_USB_IGU_INDEX_OFF \
2391 offsetof(struct cstorm_def_status_block_u, igu_index)
2392#define DEF_CSB_IGU_INDEX_OFF \
2393 offsetof(struct cstorm_def_status_block_c, igu_index)
2394#define DEF_XSB_IGU_INDEX_OFF \
2395 offsetof(struct xstorm_def_status_block, igu_index)
2396#define DEF_TSB_IGU_INDEX_OFF \
2397 offsetof(struct tstorm_def_status_block, igu_index)
2398
2399#define DEF_USB_SEGMENT_OFF \
2400 offsetof(struct cstorm_def_status_block_u, segment)
2401#define DEF_CSB_SEGMENT_OFF \
2402 offsetof(struct cstorm_def_status_block_c, segment)
2403#define DEF_XSB_SEGMENT_OFF \
2404 offsetof(struct xstorm_def_status_block, segment)
2405#define DEF_TSB_SEGMENT_OFF \
2406 offsetof(struct tstorm_def_status_block, segment)
2407
a2fbb9ea 2408#define BNX2X_SP_DSB_INDEX \
523224a3
DK
2409 (&bp->def_status_blk->sp_sb.\
2410 index_values[HC_SP_INDEX_ETH_DEF_CONS])
f85582f8 2411
a2fbb9ea 2412#define CAM_IS_INVALID(x) \
523224a3
DK
2413 (GET_FLAG(x.flags, \
2414 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2415 (T_ETH_MAC_COMMAND_INVALIDATE))
a2fbb9ea 2416
34f80b04
EG
2417/* Number of u32 elements in MC hash array */
2418#define MC_HASH_SIZE 8
2419#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2420 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
a2fbb9ea 2421
34f80b04
EG
2422#ifndef PXP2_REG_PXP2_INT_STS
2423#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2424#endif
2425
f2e0899f
DK
2426#ifndef ETH_MAX_RX_CLIENTS_E2
2427#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2428#endif
f85582f8 2429
34f24c7f
VZ
2430#define BNX2X_VPD_LEN 128
2431#define VENDOR_ID_LEN 4
2432
be1f1ffa
AE
2433#define VF_ACQUIRE_THRESH 3
2434#define VF_ACQUIRE_MAC_FILTERS 1
2435#define VF_ACQUIRE_MC_FILTERS 10
2436
2437#define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2438 (!((me_reg) & ME_REG_VF_ERR)))
ad5afc89 2439int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code);
523224a3 2440/* Congestion management fairness mode */
2de67439
YM
2441#define CMNG_FNS_NONE 0
2442#define CMNG_FNS_MINMAX 1
523224a3
DK
2443
2444#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2445#define HC_SEG_ACCESS_ATTN 4
2446#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2447
619c5cb6
VZ
2448static const u32 dmae_reg_go_c[] = {
2449 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2450 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2451 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2452 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2453};
de0c62db 2454
005a07ba 2455void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
3deb8167 2456void bnx2x_notify_link_changed(struct bnx2x *bp);
614c76df 2457
9e62e912 2458#define BNX2X_MF_SD_PROTOCOL(bp) \
614c76df
DK
2459 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2460
9e62e912
DK
2461#define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2462 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
614c76df 2463
9e62e912
DK
2464#define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2465 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2466
2467#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2468#define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2469
a3348722
BW
2470#define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2471 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2472
2473#define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
9e62e912
DK
2474#define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2475 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2476 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
614c76df 2477
2de67439
YM
2478#define SET_FLAG(value, mask, flag) \
2479 do {\
2480 (value) &= ~(mask);\
2481 (value) |= ((flag) << (mask##_SHIFT));\
2482 } while (0)
2483
2484#define GET_FLAG(value, mask) \
2485 (((value) & (mask)) >> (mask##_SHIFT))
2486
2487#define GET_FIELD(value, fname) \
2488 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2489
55c11941
MS
2490enum {
2491 SWITCH_UPDATE,
2492 AFEX_UPDATE,
2493};
2494
2495#define NUM_MACS 8
a3348722 2496
568e2426 2497void bnx2x_set_local_cmng(struct bnx2x *bp);
1a6974b2
YM
2498
2499#define MCPR_SCRATCH_BASE(bp) \
2500 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2501
e848582c
DK
2502#define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
2503
a2fbb9ea 2504#endif /* bnx2x.h */