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[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bgmac.c
CommitLineData
dd4544f0
RM		 1/*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
9#include "bgmac.h"
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
11e5e76e 16#include <linux/phy.h>
c25b23b8 17#include <linux/phy_fixed.h>
dd4544f0
RM		 18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
edb15d83 20#include <bcm47xx_nvram.h>
dd4544f0
RM		 21
22static const struct bcma_device_id bgmac_bcma_tbl[] = {
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
f7219b52 25 {},
dd4544f0
RM		 26};
27MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
28
29static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
30 u32 value, int timeout)
31{
32 u32 val;
33 int i;
34
35 for (i = 0; i < timeout / 10; i++) {
36 val = bcma_read32(core, reg);
37 if ((val & mask) == value)
38 return true;
39 udelay(10);
40 }
41 pr_err("Timeout waiting for reg 0x%X\n", reg);
42 return false;
43}
44
45/**************************************************
46 * DMA
47 **************************************************/
48
49static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
50{
51 u32 val;
52 int i;
53
54 if (!ring->mmio_base)
55 return;
56
57 /* Suspend DMA TX ring first.
58 * bgmac_wait_value doesn't support waiting for any of few values, so
59 * implement whole loop here.
60 */
61 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
62 BGMAC_DMA_TX_SUSPEND);
63 for (i = 0; i < 10000 / 10; i++) {
64 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
65 val &= BGMAC_DMA_TX_STAT;
66 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
67 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
68 val == BGMAC_DMA_TX_STAT_STOPPED) {
69 i = 0;
70 break;
71 }
72 udelay(10);
73 }
74 if (i)
75 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
76 ring->mmio_base, val);
77
78 /* Remove SUSPEND bit */
79 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
80 if (!bgmac_wait_value(bgmac->core,
81 ring->mmio_base + BGMAC_DMA_TX_STATUS,
82 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
83 10000)) {
84 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
85 ring->mmio_base);
86 udelay(300);
87 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
88 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
89 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
90 ring->mmio_base);
91 }
92}
93
94static void bgmac_dma_tx_enable(struct bgmac *bgmac,
95 struct bgmac_dma_ring *ring)
96{
97 u32 ctl;
98
99 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
56ceecde
HM		 100 if (bgmac->core->id.rev >= 4) {
101 ctl &= ~BGMAC_DMA_TX_BL_MASK;
102 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
103
104 ctl &= ~BGMAC_DMA_TX_MR_MASK;
105 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
106
107 ctl &= ~BGMAC_DMA_TX_PC_MASK;
108 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
109
110 ctl &= ~BGMAC_DMA_TX_PT_MASK;
111 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
112 }
dd4544f0
RM		 113 ctl |= BGMAC_DMA_TX_ENABLE;
114 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
115 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
116}
117
9cde9450
FF		 118static void
119bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
120 int i, int len, u32 ctl0)
121{
122 struct bgmac_slot_info *slot;
123 struct bgmac_dma_desc *dma_desc;
124 u32 ctl1;
125
126 if (i == ring->num_slots - 1)
127 ctl0 |= BGMAC_DESC_CTL0_EOT;
128
129 ctl1 = len & BGMAC_DESC_CTL1_LEN;
130
131 slot = &ring->slots[i];
132 dma_desc = &ring->cpu_base[i];
133 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
134 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
135 dma_desc->ctl0 = cpu_to_le32(ctl0);
136 dma_desc->ctl1 = cpu_to_le32(ctl1);
137}
138
dd4544f0
RM		 139static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
140 struct bgmac_dma_ring *ring,
141 struct sk_buff *skb)
142{
143 struct device *dma_dev = bgmac->core->dma_dev;
144 struct net_device *net_dev = bgmac->net_dev;
9cde9450 145 struct bgmac_slot_info *slot = &ring->slots[ring->end];
dd4544f0 146 int free_slots;
9cde9450
FF		 147 int nr_frags;
148 u32 flags;
149 int index = ring->end;
150 int i;
dd4544f0
RM		 151
152 if (skb->len > BGMAC_DESC_CTL1_LEN) {
153 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
9cde9450 154 goto err_drop;
dd4544f0
RM		 155 }
156
9cde9450
FF		 157 if (skb->ip_summed == CHECKSUM_PARTIAL)
158 skb_checksum_help(skb);
159
160 nr_frags = skb_shinfo(skb)->nr_frags;
161
dd4544f0
RM		 162 if (ring->start <= ring->end)
163 free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS;
164 else
165 free_slots = ring->start - ring->end;
9cde9450
FF		 166
167 if (free_slots <= nr_frags + 1) {
dd4544f0
RM		 168 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
169 netif_stop_queue(net_dev);
170 return NETDEV_TX_BUSY;
171 }
172
9cde9450 173 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
dd4544f0 174 DMA_TO_DEVICE);
9cde9450
FF		 175 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
176 goto err_dma_head;
dd4544f0 177
9cde9450
FF		 178 flags = BGMAC_DESC_CTL0_SOF;
179 if (!nr_frags)
180 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
dd4544f0 181
9cde9450
FF		 182 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
183 flags = 0;
184
185 for (i = 0; i < nr_frags; i++) {
186 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
187 int len = skb_frag_size(frag);
188
189 index = (index + 1) % BGMAC_TX_RING_SLOTS;
190 slot = &ring->slots[index];
191 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
192 len, DMA_TO_DEVICE);
193 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
194 goto err_dma;
195
196 if (i == nr_frags - 1)
197 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
198
199 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
200 }
201
202 slot->skb = skb;
dd4544f0 203
49a467b4
HM		 204 netdev_sent_queue(net_dev, skb->len);
205
dd4544f0
RM		 206 wmb();
207
208 /* Increase ring->end to point empty slot. We tell hardware the first
209 * slot it should *not* read.
210 */
9cde9450 211 ring->end = (index + 1) % BGMAC_TX_RING_SLOTS;
dd4544f0 212 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
9900303e 213 ring->index_base +
dd4544f0
RM		 214 ring->end * sizeof(struct bgmac_dma_desc));
215
9cde9450
FF		 216 free_slots -= nr_frags + 1;
217 if (free_slots < 8)
dd4544f0
RM		 218 netif_stop_queue(net_dev);
219
220 return NETDEV_TX_OK;
221
9cde9450
FF		 222err_dma:
223 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
224 DMA_TO_DEVICE);
225
226 while (i > 0) {
227 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
228 struct bgmac_slot_info *slot = &ring->slots[index];
229 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
230 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
231
232 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
233 }
234
235err_dma_head:
236 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
237 ring->mmio_base);
238
239err_drop:
dd4544f0
RM		 240 dev_kfree_skb(skb);
241 return NETDEV_TX_OK;
242}
243
244/* Free transmitted packets */
245static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
246{
247 struct device *dma_dev = bgmac->core->dma_dev;
248 int empty_slot;
249 bool freed = false;
49a467b4 250 unsigned bytes_compl = 0, pkts_compl = 0;
dd4544f0
RM		 251
252 /* The last slot that hardware didn't consume yet */
253 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
254 empty_slot &= BGMAC_DMA_TX_STATDPTR;
9900303e
RM		 255 empty_slot -= ring->index_base;
256 empty_slot &= BGMAC_DMA_TX_STATDPTR;
dd4544f0
RM		 257 empty_slot /= sizeof(struct bgmac_dma_desc);
258
259 while (ring->start != empty_slot) {
260 struct bgmac_slot_info *slot = &ring->slots[ring->start];
9cde9450
FF		 261 u32 ctl1 = le32_to_cpu(ring->cpu_base[ring->start].ctl1);
262 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
dd4544f0 263
9cde9450
FF		 264 if (!slot->dma_addr) {
265 bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n",
266 ring->start, ring->end);
267 goto next;
268 }
269
270 if (ctl1 & BGMAC_DESC_CTL0_SOF)
dd4544f0 271 /* Unmap no longer used buffer */
9cde9450
FF		 272 dma_unmap_single(dma_dev, slot->dma_addr, len,
273 DMA_TO_DEVICE);
274 else
275 dma_unmap_page(dma_dev, slot->dma_addr, len,
276 DMA_TO_DEVICE);
dd4544f0 277
9cde9450 278 if (slot->skb) {
49a467b4
HM		 279 bytes_compl += slot->skb->len;
280 pkts_compl++;
281
dd4544f0
RM		 282 /* Free memory! :) */
283 dev_kfree_skb(slot->skb);
284 slot->skb = NULL;
dd4544f0
RM		 285 }
286
9cde9450
FF		 287next:
288 slot->dma_addr = 0;
dd4544f0
RM		 289 if (++ring->start >= BGMAC_TX_RING_SLOTS)
290 ring->start = 0;
291 freed = true;
292 }
293
9cde9450
FF		 294 if (!pkts_compl)
295 return;
296
49a467b4
HM		 297 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
298
9cde9450 299 if (netif_queue_stopped(bgmac->net_dev))
dd4544f0
RM		 300 netif_wake_queue(bgmac->net_dev);
301}
302
303static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
304{
305 if (!ring->mmio_base)
306 return;
307
308 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
309 if (!bgmac_wait_value(bgmac->core,
310 ring->mmio_base + BGMAC_DMA_RX_STATUS,
311 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
312 10000))
313 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
314 ring->mmio_base);
315}
316
317static void bgmac_dma_rx_enable(struct bgmac *bgmac,
318 struct bgmac_dma_ring *ring)
319{
320 u32 ctl;
321
322 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
56ceecde
HM		 323 if (bgmac->core->id.rev >= 4) {
324 ctl &= ~BGMAC_DMA_RX_BL_MASK;
325 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
326
327 ctl &= ~BGMAC_DMA_RX_PC_MASK;
328 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
329
330 ctl &= ~BGMAC_DMA_RX_PT_MASK;
331 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
332 }
dd4544f0
RM		 333 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
334 ctl |= BGMAC_DMA_RX_ENABLE;
335 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
336 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
337 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
338 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
339}
340
341static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
342 struct bgmac_slot_info *slot)
343{
344 struct device *dma_dev = bgmac->core->dma_dev;
b757a62e 345 dma_addr_t dma_addr;
dd4544f0 346 struct bgmac_rx_header *rx;
45c9b3c0 347 void *buf;
dd4544f0
RM		 348
349 /* Alloc skb */
45c9b3c0
FF		 350 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
351 if (!buf)
dd4544f0 352 return -ENOMEM;
dd4544f0
RM		 353
354 /* Poison - if everything goes fine, hardware will overwrite it */
45c9b3c0 355 rx = buf;
dd4544f0
RM		 356 rx->len = cpu_to_le16(0xdead);
357 rx->flags = cpu_to_le16(0xbeef);
358
359 /* Map skb for the DMA */
45c9b3c0
FF		 360 dma_addr = dma_map_single(dma_dev, buf, BGMAC_RX_BUF_SIZE,
361 DMA_FROM_DEVICE);
b757a62e 362 if (dma_mapping_error(dma_dev, dma_addr)) {
dd4544f0 363 bgmac_err(bgmac, "DMA mapping error\n");
45c9b3c0 364 put_page(virt_to_head_page(buf));
dd4544f0
RM		 365 return -ENOMEM;
366 }
b757a62e
NH		 367
368 /* Update the slot */
45c9b3c0 369 slot->buf = buf;
b757a62e
NH		 370 slot->dma_addr = dma_addr;
371
dd4544f0
RM		 372 return 0;
373}
374
d549c76b
RM		 375static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
376 struct bgmac_dma_ring *ring, int desc_idx)
377{
378 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
379 u32 ctl0 = 0, ctl1 = 0;
380
381 if (desc_idx == ring->num_slots - 1)
382 ctl0 |= BGMAC_DESC_CTL0_EOT;
383 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
384 /* Is there any BGMAC device that requires extension? */
385 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
386 * B43_DMA64_DCTL1_ADDREXT_MASK;
387 */
388
389 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
390 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
391 dma_desc->ctl0 = cpu_to_le32(ctl0);
392 dma_desc->ctl1 = cpu_to_le32(ctl1);
393}
394
dd4544f0
RM		 395static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
396 int weight)
397{
398 u32 end_slot;
399 int handled = 0;
400
401 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
402 end_slot &= BGMAC_DMA_RX_STATDPTR;
9900303e
RM		 403 end_slot -= ring->index_base;
404 end_slot &= BGMAC_DMA_RX_STATDPTR;
dd4544f0
RM		 405 end_slot /= sizeof(struct bgmac_dma_desc);
406
407 ring->end = end_slot;
408
409 while (ring->start != ring->end) {
410 struct device *dma_dev = bgmac->core->dma_dev;
411 struct bgmac_slot_info *slot = &ring->slots[ring->start];
45c9b3c0
FF		 412 struct bgmac_rx_header *rx = slot->buf;
413 struct sk_buff *skb;
414 void *buf = slot->buf;
dd4544f0
RM		 415 u16 len, flags;
416
417 /* Unmap buffer to make it accessible to the CPU */
418 dma_sync_single_for_cpu(dma_dev, slot->dma_addr,
419 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
420
421 /* Get info from the header */
dd4544f0
RM		 422 len = le16_to_cpu(rx->len);
423 flags = le16_to_cpu(rx->flags);
424
92b9ccd3
RM		 425 do {
426 dma_addr_t old_dma_addr = slot->dma_addr;
427 int err;
428
429 /* Check for poison and drop or pass the packet */
430 if (len == 0xdead && flags == 0xbeef) {
431 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
432 ring->start);
433 dma_sync_single_for_device(dma_dev,
434 slot->dma_addr,
435 BGMAC_RX_BUF_SIZE,
436 DMA_FROM_DEVICE);
437 break;
438 }
439
02e71127
HM		 440 /* Omit CRC. */
441 len -= ETH_FCS_LEN;
442
92b9ccd3
RM		 443 /* Prepare new skb as replacement */
444 err = bgmac_dma_rx_skb_for_slot(bgmac, slot);
445 if (err) {
446 /* Poison the old skb */
447 rx->len = cpu_to_le16(0xdead);
448 rx->flags = cpu_to_le16(0xbeef);
449
450 dma_sync_single_for_device(dma_dev,
451 slot->dma_addr,
452 BGMAC_RX_BUF_SIZE,
453 DMA_FROM_DEVICE);
454 break;
dd4544f0 455 }
92b9ccd3 456 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
dd4544f0 457
92b9ccd3
RM		 458 /* Unmap old skb, we'll pass it to the netfif */
459 dma_unmap_single(dma_dev, old_dma_addr,
460 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
461
45c9b3c0 462 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
92b9ccd3
RM		 463 skb_put(skb, BGMAC_RX_FRAME_OFFSET + len);
464 skb_pull(skb, BGMAC_RX_FRAME_OFFSET);
dd4544f0 465
92b9ccd3
RM		 466 skb_checksum_none_assert(skb);
467 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
45c9b3c0 468 napi_gro_receive(&bgmac->napi, skb);
92b9ccd3
RM		 469 handled++;
470 } while (0);
dd4544f0
RM		 471
472 if (++ring->start >= BGMAC_RX_RING_SLOTS)
473 ring->start = 0;
474
475 if (handled >= weight) /* Should never be greater */
476 break;
477 }
478
479 return handled;
480}
481
482/* Does ring support unaligned addressing? */
483static bool bgmac_dma_unaligned(struct bgmac *bgmac,
484 struct bgmac_dma_ring *ring,
485 enum bgmac_dma_ring_type ring_type)
486{
487 switch (ring_type) {
488 case BGMAC_DMA_RING_TX:
489 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
490 0xff0);
491 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
492 return true;
493 break;
494 case BGMAC_DMA_RING_RX:
495 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
496 0xff0);
497 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
498 return true;
499 break;
500 }
501 return false;
502}
503
45c9b3c0
FF		 504static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
505 struct bgmac_dma_ring *ring)
dd4544f0
RM		 506{
507 struct device *dma_dev = bgmac->core->dma_dev;
9cde9450 508 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
dd4544f0 509 struct bgmac_slot_info *slot;
dd4544f0
RM		 510 int i;
511
512 for (i = 0; i < ring->num_slots; i++) {
9cde9450
FF		 513 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
514
dd4544f0 515 slot = &ring->slots[i];
9cde9450
FF		 516 dev_kfree_skb(slot->skb);
517
518 if (!slot->dma_addr)
519 continue;
520
521 if (slot->skb)
522 dma_unmap_single(dma_dev, slot->dma_addr,
523 len, DMA_TO_DEVICE);
524 else
525 dma_unmap_page(dma_dev, slot->dma_addr,
526 len, DMA_TO_DEVICE);
dd4544f0 527 }
45c9b3c0
FF		 528}
529
530static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
531 struct bgmac_dma_ring *ring)
532{
533 struct device *dma_dev = bgmac->core->dma_dev;
534 struct bgmac_slot_info *slot;
535 int i;
536
537 for (i = 0; i < ring->num_slots; i++) {
538 slot = &ring->slots[i];
539 if (!slot->buf)
540 continue;
dd4544f0 541
45c9b3c0
FF		 542 if (slot->dma_addr)
543 dma_unmap_single(dma_dev, slot->dma_addr,
544 BGMAC_RX_BUF_SIZE,
545 DMA_FROM_DEVICE);
546 put_page(virt_to_head_page(slot->buf));
dd4544f0
RM		 547 }
548}
549
45c9b3c0
FF		 550static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
551 struct bgmac_dma_ring *ring)
552{
553 struct device *dma_dev = bgmac->core->dma_dev;
554 int size;
555
556 if (!ring->cpu_base)
557 return;
558
559 /* Free ring of descriptors */
560 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
561 dma_free_coherent(dma_dev, size, ring->cpu_base,
562 ring->dma_base);
563}
564
dd4544f0
RM		 565static void bgmac_dma_free(struct bgmac *bgmac)
566{
567 int i;
568
45c9b3c0
FF		 569 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
570 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
571 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]);
572 }
573 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
574 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
575 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]);
576 }
dd4544f0
RM		 577}
578
579static int bgmac_dma_alloc(struct bgmac *bgmac)
580{
581 struct device *dma_dev = bgmac->core->dma_dev;
582 struct bgmac_dma_ring *ring;
583 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
584 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
585 int size; /* ring size: different for Tx and Rx */
586 int err;
587 int i;
588
589 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
590 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
591
592 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
593 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
594 return -ENOTSUPP;
595 }
596
597 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
598 ring = &bgmac->tx_ring[i];
599 ring->num_slots = BGMAC_TX_RING_SLOTS;
600 ring->mmio_base = ring_base[i];
dd4544f0
RM		 601
602 /* Alloc ring of descriptors */
603 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
604 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
605 &ring->dma_base,
606 GFP_KERNEL);
607 if (!ring->cpu_base) {
608 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
609 ring->mmio_base);
610 goto err_dma_free;
611 }
dd4544f0 612
9900303e
RM		 613 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
614 BGMAC_DMA_RING_TX);
615 if (ring->unaligned)
616 ring->index_base = lower_32_bits(ring->dma_base);
617 else
618 ring->index_base = 0;
619
dd4544f0
RM		 620 /* No need to alloc TX slots yet */
621 }
622
623 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
70a737b7
RM		 624 int j;
625
dd4544f0
RM		 626 ring = &bgmac->rx_ring[i];
627 ring->num_slots = BGMAC_RX_RING_SLOTS;
628 ring->mmio_base = ring_base[i];
dd4544f0
RM		 629
630 /* Alloc ring of descriptors */
631 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
632 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
633 &ring->dma_base,
634 GFP_KERNEL);
635 if (!ring->cpu_base) {
636 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
637 ring->mmio_base);
638 err = -ENOMEM;
639 goto err_dma_free;
640 }
dd4544f0 641
9900303e
RM		 642 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
643 BGMAC_DMA_RING_RX);
644 if (ring->unaligned)
645 ring->index_base = lower_32_bits(ring->dma_base);
646 else
647 ring->index_base = 0;
648
dd4544f0 649 /* Alloc RX slots */
70a737b7
RM		 650 for (j = 0; j < ring->num_slots; j++) {
651 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
dd4544f0
RM		 652 if (err) {
653 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n");
654 goto err_dma_free;
655 }
656 }
657 }
658
659 return 0;
660
661err_dma_free:
662 bgmac_dma_free(bgmac);
663 return -ENOMEM;
664}
665
666static void bgmac_dma_init(struct bgmac *bgmac)
667{
668 struct bgmac_dma_ring *ring;
dd4544f0
RM		 669 int i;
670
671 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
672 ring = &bgmac->tx_ring[i];
673
9900303e
RM		 674 if (!ring->unaligned)
675 bgmac_dma_tx_enable(bgmac, ring);
dd4544f0
RM		 676 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
677 lower_32_bits(ring->dma_base));
678 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
679 upper_32_bits(ring->dma_base));
9900303e
RM		 680 if (ring->unaligned)
681 bgmac_dma_tx_enable(bgmac, ring);
dd4544f0
RM		 682
683 ring->start = 0;
684 ring->end = 0; /* Points the slot that should *not* be read */
685 }
686
687 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
70a737b7
RM		 688 int j;
689
dd4544f0
RM		 690 ring = &bgmac->rx_ring[i];
691
9900303e
RM		 692 if (!ring->unaligned)
693 bgmac_dma_rx_enable(bgmac, ring);
dd4544f0
RM		 694 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
695 lower_32_bits(ring->dma_base));
696 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
697 upper_32_bits(ring->dma_base));
9900303e
RM		 698 if (ring->unaligned)
699 bgmac_dma_rx_enable(bgmac, ring);
dd4544f0 700
d549c76b
RM		 701 for (j = 0; j < ring->num_slots; j++)
702 bgmac_dma_rx_setup_desc(bgmac, ring, j);
dd4544f0
RM		 703
704 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
9900303e 705 ring->index_base +
dd4544f0
RM		 706 ring->num_slots * sizeof(struct bgmac_dma_desc));
707
708 ring->start = 0;
709 ring->end = 0;
710 }
711}
712
713/**************************************************
714 * PHY ops
715 **************************************************/
716
217a55a3 717static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
dd4544f0
RM		 718{
719 struct bcma_device *core;
720 u16 phy_access_addr;
721 u16 phy_ctl_addr;
722 u32 tmp;
723
724 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
725 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
726 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
727 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
728 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
729 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
730 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
731 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
732 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
733 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
734 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
735
736 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
737 core = bgmac->core->bus->drv_gmac_cmn.core;
738 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
739 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
740 } else {
741 core = bgmac->core;
742 phy_access_addr = BGMAC_PHY_ACCESS;
743 phy_ctl_addr = BGMAC_PHY_CNTL;
744 }
745
746 tmp = bcma_read32(core, phy_ctl_addr);
747 tmp &= ~BGMAC_PC_EPA_MASK;
748 tmp |= phyaddr;
749 bcma_write32(core, phy_ctl_addr, tmp);
750
751 tmp = BGMAC_PA_START;
752 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
753 tmp |= reg << BGMAC_PA_REG_SHIFT;
754 bcma_write32(core, phy_access_addr, tmp);
755
756 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
757 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
758 phyaddr, reg);
759 return 0xffff;
760 }
761
762 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
763}
764
765/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
217a55a3 766static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
dd4544f0
RM		 767{
768 struct bcma_device *core;
769 u16 phy_access_addr;
770 u16 phy_ctl_addr;
771 u32 tmp;
772
773 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
774 core = bgmac->core->bus->drv_gmac_cmn.core;
775 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
776 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
777 } else {
778 core = bgmac->core;
779 phy_access_addr = BGMAC_PHY_ACCESS;
780 phy_ctl_addr = BGMAC_PHY_CNTL;
781 }
782
783 tmp = bcma_read32(core, phy_ctl_addr);
784 tmp &= ~BGMAC_PC_EPA_MASK;
785 tmp |= phyaddr;
786 bcma_write32(core, phy_ctl_addr, tmp);
787
788 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
789 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
790 bgmac_warn(bgmac, "Error setting MDIO int\n");
791
792 tmp = BGMAC_PA_START;
793 tmp |= BGMAC_PA_WRITE;
794 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
795 tmp |= reg << BGMAC_PA_REG_SHIFT;
796 tmp |= value;
797 bcma_write32(core, phy_access_addr, tmp);
798
217a55a3 799 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
dd4544f0
RM		 800 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
801 phyaddr, reg);
217a55a3
RM		 802 return -ETIMEDOUT;
803 }
804
805 return 0;
dd4544f0
RM		 806}
807
dd4544f0
RM		 808/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
809static void bgmac_phy_init(struct bgmac *bgmac)
810{
811 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
812 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
813 u8 i;
814
815 if (ci->id == BCMA_CHIP_ID_BCM5356) {
816 for (i = 0; i < 5; i++) {
817 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
818 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
819 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
820 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
821 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
822 }
823 }
824 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
825 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
826 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
827 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
828 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
829 for (i = 0; i < 5; i++) {
830 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
831 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
832 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
833 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
834 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
835 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
836 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
837 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
838 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
839 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
840 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
841 }
842 }
843}
844
845/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
846static void bgmac_phy_reset(struct bgmac *bgmac)
847{
848 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
849 return;
850
5322dbf0 851 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
dd4544f0 852 udelay(100);
5322dbf0 853 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
dd4544f0
RM		 854 bgmac_err(bgmac, "PHY reset failed\n");
855 bgmac_phy_init(bgmac);
856}
857
858/**************************************************
859 * Chip ops
860 **************************************************/
861
862/* TODO: can we just drop @force? Can we don't reset MAC at all if there is
863 * nothing to change? Try if after stabilizng driver.
864 */
865static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
866 bool force)
867{
868 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
869 u32 new_val = (cmdcfg & mask) | set;
870
48e07fbe 871 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
dd4544f0
RM		 872 udelay(2);
873
874 if (new_val != cmdcfg || force)
875 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
876
48e07fbe 877 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
dd4544f0
RM		 878 udelay(2);
879}
880
4e209001
HM		 881static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
882{
883 u32 tmp;
884
885 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
886 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
887 tmp = (addr[4] << 8) | addr[5];
888 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
889}
890
c6edfe10
HM		 891static void bgmac_set_rx_mode(struct net_device *net_dev)
892{
893 struct bgmac *bgmac = netdev_priv(net_dev);
894
895 if (net_dev->flags & IFF_PROMISC)
e9ba1039 896 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
c6edfe10 897 else
e9ba1039 898 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
c6edfe10
HM		 899}
900
dd4544f0
RM		 901#if 0 /* We don't use that regs yet */
902static void bgmac_chip_stats_update(struct bgmac *bgmac)
903{
904 int i;
905
906 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
907 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
908 bgmac->mib_tx_regs[i] =
909 bgmac_read(bgmac,
910 BGMAC_TX_GOOD_OCTETS + (i * 4));
911 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
912 bgmac->mib_rx_regs[i] =
913 bgmac_read(bgmac,
914 BGMAC_RX_GOOD_OCTETS + (i * 4));
915 }
916
917 /* TODO: what else? how to handle BCM4706? Specs are needed */
918}
919#endif
920
921static void bgmac_clear_mib(struct bgmac *bgmac)
922{
923 int i;
924
925 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
926 return;
927
928 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
929 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
930 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
931 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
932 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
933}
934
935/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
5824d2d1 936static void bgmac_mac_speed(struct bgmac *bgmac)
dd4544f0
RM		 937{
938 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
939 u32 set = 0;
940
5824d2d1
RM		 941 switch (bgmac->mac_speed) {
942 case SPEED_10:
dd4544f0 943 set |= BGMAC_CMDCFG_ES_10;
5824d2d1
RM		 944 break;
945 case SPEED_100:
dd4544f0 946 set |= BGMAC_CMDCFG_ES_100;
5824d2d1
RM		 947 break;
948 case SPEED_1000:
dd4544f0 949 set |= BGMAC_CMDCFG_ES_1000;
5824d2d1 950 break;
6df4aff9
HM		 951 case SPEED_2500:
952 set |= BGMAC_CMDCFG_ES_2500;
953 break;
5824d2d1
RM		 954 default:
955 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
956 }
957
958 if (bgmac->mac_duplex == DUPLEX_HALF)
dd4544f0 959 set |= BGMAC_CMDCFG_HD;
5824d2d1 960
dd4544f0
RM		 961 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
962}
963
964static void bgmac_miiconfig(struct bgmac *bgmac)
965{
6df4aff9
HM		 966 struct bcma_device *core = bgmac->core;
967 struct bcma_chipinfo *ci = &core->bus->chipinfo;
968 u8 imode;
969
970 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
971 ci->id == BCMA_CHIP_ID_BCM53018) {
972 bcma_awrite32(core, BCMA_IOCTL,
973 bcma_aread32(core, BCMA_IOCTL) | 0x40 |
974 BGMAC_BCMA_IOCTL_SW_CLKEN);
975 bgmac->mac_speed = SPEED_2500;
5824d2d1
RM		 976 bgmac->mac_duplex = DUPLEX_FULL;
977 bgmac_mac_speed(bgmac);
6df4aff9
HM		 978 } else {
979 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
980 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
981 if (imode == 0 || imode == 1) {
982 bgmac->mac_speed = SPEED_100;
983 bgmac->mac_duplex = DUPLEX_FULL;
984 bgmac_mac_speed(bgmac);
985 }
dd4544f0
RM		 986 }
987}
988
989/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
990static void bgmac_chip_reset(struct bgmac *bgmac)
991{
992 struct bcma_device *core = bgmac->core;
993 struct bcma_bus *bus = core->bus;
994 struct bcma_chipinfo *ci = &bus->chipinfo;
6df4aff9 995 u32 flags;
dd4544f0
RM		 996 u32 iost;
997 int i;
998
999 if (bcma_core_is_enabled(core)) {
1000 if (!bgmac->stats_grabbed) {
1001 /* bgmac_chip_stats_update(bgmac); */
1002 bgmac->stats_grabbed = true;
1003 }
1004
1005 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
1006 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
1007
1008 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1009 udelay(1);
1010
1011 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
1012 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
1013
1014 /* TODO: Clear software multicast filter list */
1015 }
1016
1017 iost = bcma_aread32(core, BCMA_IOST);
1a0ab767 1018 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
dd4544f0 1019 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1a0ab767 1020 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
dd4544f0
RM		 1021 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
1022
6df4aff9
HM		 1023 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
1024 if (ci->id != BCMA_CHIP_ID_BCM4707) {
1025 flags = 0;
1026 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
1027 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
1028 if (!bgmac->has_robosw)
1029 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
1030 }
1031 bcma_core_enable(core, flags);
dd4544f0
RM		 1032 }
1033
6df4aff9
HM		 1034 /* Request Misc PLL for corerev > 2 */
1035 if (core->id.rev > 2 &&
1036 ci->id != BCMA_CHIP_ID_BCM4707 &&
1037 ci->id != BCMA_CHIP_ID_BCM53018) {
1a0ab767
RM		 1038 bgmac_set(bgmac, BCMA_CLKCTLST,
1039 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
1040 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
1041 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1042 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
dd4544f0
RM		 1043 1000);
1044 }
1045
1a0ab767
RM		 1046 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1047 ci->id == BCMA_CHIP_ID_BCM4749 ||
dd4544f0
RM		 1048 ci->id == BCMA_CHIP_ID_BCM53572) {
1049 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
1050 u8 et_swtype = 0;
1051 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
6a391e7b 1052 BGMAC_CHIPCTL_1_IF_TYPE_MII;
3647268d 1053 char buf[4];
dd4544f0 1054
3647268d 1055 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
dd4544f0
RM		 1056 if (kstrtou8(buf, 0, &et_swtype))
1057 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
1058 buf);
1059 et_swtype &= 0x0f;
1060 et_swtype <<= 4;
1061 sw_type = et_swtype;
1a0ab767 1062 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
dd4544f0 1063 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
1a0ab767
RM		 1064 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1065 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1066 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
b5a4c2f3
HM		 1067 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
1068 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
dd4544f0
RM		 1069 }
1070 bcma_chipco_chipctl_maskset(cc, 1,
1071 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
1072 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
1073 sw_type);
1074 }
1075
1076 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
1077 bcma_awrite32(core, BCMA_IOCTL,
1078 bcma_aread32(core, BCMA_IOCTL) &
1079 ~BGMAC_BCMA_IOCTL_SW_RESET);
1080
1081 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
1082 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
1083 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
1084 * be keps until taking MAC out of the reset.
1085 */
1086 bgmac_cmdcfg_maskset(bgmac,
1087 ~(BGMAC_CMDCFG_TE |
1088 BGMAC_CMDCFG_RE |
1089 BGMAC_CMDCFG_RPI |
1090 BGMAC_CMDCFG_TAI |
1091 BGMAC_CMDCFG_HD |
1092 BGMAC_CMDCFG_ML |
1093 BGMAC_CMDCFG_CFE |
1094 BGMAC_CMDCFG_RL |
1095 BGMAC_CMDCFG_RED |
1096 BGMAC_CMDCFG_PE |
1097 BGMAC_CMDCFG_TPI |
1098 BGMAC_CMDCFG_PAD_EN |
1099 BGMAC_CMDCFG_PF),
1100 BGMAC_CMDCFG_PROM |
1101 BGMAC_CMDCFG_NLC |
1102 BGMAC_CMDCFG_CFE |
48e07fbe 1103 BGMAC_CMDCFG_SR(core->id.rev),
dd4544f0 1104 false);
d469962f
RM		 1105 bgmac->mac_speed = SPEED_UNKNOWN;
1106 bgmac->mac_duplex = DUPLEX_UNKNOWN;
dd4544f0
RM		 1107
1108 bgmac_clear_mib(bgmac);
1109 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
1110 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
1111 BCMA_GMAC_CMN_PC_MTE);
1112 else
1113 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1114 bgmac_miiconfig(bgmac);
1115 bgmac_phy_init(bgmac);
1116
49a467b4
HM		 1117 netdev_reset_queue(bgmac->net_dev);
1118
dd4544f0
RM		 1119 bgmac->int_status = 0;
1120}
1121
1122static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1123{
1124 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1125}
1126
1127static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1128{
1129 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
4160815f 1130 bgmac_read(bgmac, BGMAC_INT_MASK);
dd4544f0
RM		 1131}
1132
1133/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1134static void bgmac_enable(struct bgmac *bgmac)
1135{
1136 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1137 u32 cmdcfg;
1138 u32 mode;
1139 u32 rxq_ctl;
1140 u32 fl_ctl;
1141 u16 bp_clk;
1142 u8 mdp;
1143
1144 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1145 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
48e07fbe 1146 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
dd4544f0
RM		 1147 udelay(2);
1148 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1149 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1150
1151 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1152 BGMAC_DS_MM_SHIFT;
1153 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1154 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1155 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1156 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1157 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1158
1159 switch (ci->id) {
1160 case BCMA_CHIP_ID_BCM5357:
1161 case BCMA_CHIP_ID_BCM4749:
1162 case BCMA_CHIP_ID_BCM53572:
1163 case BCMA_CHIP_ID_BCM4716:
1164 case BCMA_CHIP_ID_BCM47162:
1165 fl_ctl = 0x03cb04cb;
1166 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1167 ci->id == BCMA_CHIP_ID_BCM4749 ||
1168 ci->id == BCMA_CHIP_ID_BCM53572)
1169 fl_ctl = 0x2300e1;
1170 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1171 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1172 break;
1173 }
1174
6df4aff9
HM		 1175 if (ci->id != BCMA_CHIP_ID_BCM4707 &&
1176 ci->id != BCMA_CHIP_ID_BCM53018) {
1177 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1178 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1179 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
1180 1000000;
1181 mdp = (bp_clk * 128 / 1000) - 3;
1182 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1183 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1184 }
dd4544f0
RM		 1185}
1186
1187/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1188static void bgmac_chip_init(struct bgmac *bgmac, bool full_init)
1189{
1190 struct bgmac_dma_ring *ring;
dd4544f0
RM		 1191 int i;
1192
1193 /* 1 interrupt per received frame */
1194 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1195
1196 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1197 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1198
c6edfe10 1199 bgmac_set_rx_mode(bgmac->net_dev);
dd4544f0 1200
4e209001 1201 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
dd4544f0
RM		 1202
1203 if (bgmac->loopback)
e9ba1039 1204 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
dd4544f0 1205 else
e9ba1039 1206 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
dd4544f0
RM		 1207
1208 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1209
dd4544f0
RM		 1210 if (full_init) {
1211 bgmac_dma_init(bgmac);
1212 if (1) /* FIXME: is there any case we don't want IRQs? */
1213 bgmac_chip_intrs_on(bgmac);
1214 } else {
1215 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
1216 ring = &bgmac->rx_ring[i];
1217 bgmac_dma_rx_enable(bgmac, ring);
1218 }
1219 }
1220
1221 bgmac_enable(bgmac);
1222}
1223
1224static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1225{
1226 struct bgmac *bgmac = netdev_priv(dev_id);
1227
1228 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1229 int_status &= bgmac->int_mask;
1230
1231 if (!int_status)
1232 return IRQ_NONE;
1233
1234 /* Ack */
1235 bgmac_write(bgmac, BGMAC_INT_STATUS, int_status);
1236
1237 /* Disable new interrupts until handling existing ones */
1238 bgmac_chip_intrs_off(bgmac);
1239
1240 bgmac->int_status = int_status;
1241
1242 napi_schedule(&bgmac->napi);
1243
1244 return IRQ_HANDLED;
1245}
1246
1247static int bgmac_poll(struct napi_struct *napi, int weight)
1248{
1249 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1250 struct bgmac_dma_ring *ring;
1251 int handled = 0;
1252
1253 if (bgmac->int_status & BGMAC_IS_TX0) {
1254 ring = &bgmac->tx_ring[0];
1255 bgmac_dma_tx_free(bgmac, ring);
1256 bgmac->int_status &= ~BGMAC_IS_TX0;
1257 }
1258
1259 if (bgmac->int_status & BGMAC_IS_RX) {
1260 ring = &bgmac->rx_ring[0];
1261 handled += bgmac_dma_rx_read(bgmac, ring, weight);
1262 bgmac->int_status &= ~BGMAC_IS_RX;
1263 }
1264
1265 if (bgmac->int_status) {
1266 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status);
1267 bgmac->int_status = 0;
1268 }
1269
43f159c6 1270 if (handled < weight) {
dd4544f0 1271 napi_complete(napi);
43f159c6
HM		 1272 bgmac_chip_intrs_on(bgmac);
1273 }
dd4544f0
RM		 1274
1275 return handled;
1276}
1277
1278/**************************************************
1279 * net_device_ops
1280 **************************************************/
1281
1282static int bgmac_open(struct net_device *net_dev)
1283{
1284 struct bgmac *bgmac = netdev_priv(net_dev);
1285 int err = 0;
1286
1287 bgmac_chip_reset(bgmac);
1288 /* Specs say about reclaiming rings here, but we do that in DMA init */
1289 bgmac_chip_init(bgmac, true);
1290
1291 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1292 KBUILD_MODNAME, net_dev);
1293 if (err < 0) {
1294 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
1295 goto err_out;
1296 }
1297 napi_enable(&bgmac->napi);
1298
4e34da4d
RM		 1299 phy_start(bgmac->phy_dev);
1300
dd4544f0
RM		 1301 netif_carrier_on(net_dev);
1302
1303err_out:
1304 return err;
1305}
1306
1307static int bgmac_stop(struct net_device *net_dev)
1308{
1309 struct bgmac *bgmac = netdev_priv(net_dev);
1310
1311 netif_carrier_off(net_dev);
1312
4e34da4d
RM		 1313 phy_stop(bgmac->phy_dev);
1314
dd4544f0
RM		 1315 napi_disable(&bgmac->napi);
1316 bgmac_chip_intrs_off(bgmac);
1317 free_irq(bgmac->core->irq, net_dev);
1318
1319 bgmac_chip_reset(bgmac);
1320
1321 return 0;
1322}
1323
1324static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1325 struct net_device *net_dev)
1326{
1327 struct bgmac *bgmac = netdev_priv(net_dev);
1328 struct bgmac_dma_ring *ring;
1329
1330 /* No QOS support yet */
1331 ring = &bgmac->tx_ring[0];
1332 return bgmac_dma_tx_add(bgmac, ring, skb);
1333}
1334
4e209001
HM		 1335static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1336{
1337 struct bgmac *bgmac = netdev_priv(net_dev);
1338 int ret;
1339
1340 ret = eth_prepare_mac_addr_change(net_dev, addr);
1341 if (ret < 0)
1342 return ret;
1343 bgmac_write_mac_address(bgmac, (u8 *)addr);
1344 eth_commit_mac_addr_change(net_dev, addr);
1345 return 0;
1346}
1347
dd4544f0
RM		 1348static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1349{
1350 struct bgmac *bgmac = netdev_priv(net_dev);
69c58852
HM		 1351
1352 if (!netif_running(net_dev))
1353 return -EINVAL;
1354
1355 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
dd4544f0
RM		 1356}
1357
1358static const struct net_device_ops bgmac_netdev_ops = {
1359 .ndo_open = bgmac_open,
1360 .ndo_stop = bgmac_stop,
1361 .ndo_start_xmit = bgmac_start_xmit,
c6edfe10 1362 .ndo_set_rx_mode = bgmac_set_rx_mode,
4e209001 1363 .ndo_set_mac_address = bgmac_set_mac_address,
522c5907 1364 .ndo_validate_addr = eth_validate_addr,
dd4544f0
RM		 1365 .ndo_do_ioctl = bgmac_ioctl,
1366};
1367
1368/**************************************************
1369 * ethtool_ops
1370 **************************************************/
1371
1372static int bgmac_get_settings(struct net_device *net_dev,
1373 struct ethtool_cmd *cmd)
1374{
1375 struct bgmac *bgmac = netdev_priv(net_dev);
1376
5824d2d1 1377 return phy_ethtool_gset(bgmac->phy_dev, cmd);
dd4544f0
RM		 1378}
1379
dd4544f0
RM		 1380static int bgmac_set_settings(struct net_device *net_dev,
1381 struct ethtool_cmd *cmd)
1382{
1383 struct bgmac *bgmac = netdev_priv(net_dev);
1384
5824d2d1 1385 return phy_ethtool_sset(bgmac->phy_dev, cmd);
dd4544f0 1386}
dd4544f0
RM		 1387
1388static void bgmac_get_drvinfo(struct net_device *net_dev,
1389 struct ethtool_drvinfo *info)
1390{
1391 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1392 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1393}
1394
1395static const struct ethtool_ops bgmac_ethtool_ops = {
1396 .get_settings = bgmac_get_settings,
5824d2d1 1397 .set_settings = bgmac_set_settings,
dd4544f0
RM		 1398 .get_drvinfo = bgmac_get_drvinfo,
1399};
1400
11e5e76e
RM		 1401/**************************************************
1402 * MII
1403 **************************************************/
1404
1405static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1406{
1407 return bgmac_phy_read(bus->priv, mii_id, regnum);
1408}
1409
1410static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1411 u16 value)
1412{
1413 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1414}
1415
5824d2d1
RM		 1416static void bgmac_adjust_link(struct net_device *net_dev)
1417{
1418 struct bgmac *bgmac = netdev_priv(net_dev);
1419 struct phy_device *phy_dev = bgmac->phy_dev;
1420 bool update = false;
1421
1422 if (phy_dev->link) {
1423 if (phy_dev->speed != bgmac->mac_speed) {
1424 bgmac->mac_speed = phy_dev->speed;
1425 update = true;
1426 }
1427
1428 if (phy_dev->duplex != bgmac->mac_duplex) {
1429 bgmac->mac_duplex = phy_dev->duplex;
1430 update = true;
1431 }
1432 }
1433
1434 if (update) {
1435 bgmac_mac_speed(bgmac);
1436 phy_print_status(phy_dev);
1437 }
1438}
1439
c25b23b8
RM		 1440static int bgmac_fixed_phy_register(struct bgmac *bgmac)
1441{
1442 struct fixed_phy_status fphy_status = {
1443 .link = 1,
1444 .speed = SPEED_1000,
1445 .duplex = DUPLEX_FULL,
1446 };
1447 struct phy_device *phy_dev;
1448 int err;
1449
1450 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
1451 if (!phy_dev || IS_ERR(phy_dev)) {
1452 bgmac_err(bgmac, "Failed to register fixed PHY device\n");
1453 return -ENODEV;
1454 }
1455
1456 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1457 PHY_INTERFACE_MODE_MII);
1458 if (err) {
1459 bgmac_err(bgmac, "Connecting PHY failed\n");
1460 return err;
1461 }
1462
1463 bgmac->phy_dev = phy_dev;
1464
1465 return err;
1466}
1467
11e5e76e
RM		 1468static int bgmac_mii_register(struct bgmac *bgmac)
1469{
c25b23b8 1470 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
11e5e76e 1471 struct mii_bus *mii_bus;
5824d2d1
RM		 1472 struct phy_device *phy_dev;
1473 char bus_id[MII_BUS_ID_SIZE + 3];
11e5e76e
RM		 1474 int i, err = 0;
1475
c25b23b8
RM		 1476 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
1477 ci->id == BCMA_CHIP_ID_BCM53018)
1478 return bgmac_fixed_phy_register(bgmac);
1479
11e5e76e
RM		 1480 mii_bus = mdiobus_alloc();
1481 if (!mii_bus)
1482 return -ENOMEM;
1483
1484 mii_bus->name = "bgmac mii bus";
1485 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1486 bgmac->core->core_unit);
1487 mii_bus->priv = bgmac;
1488 mii_bus->read = bgmac_mii_read;
1489 mii_bus->write = bgmac_mii_write;
1490 mii_bus->parent = &bgmac->core->dev;
1491 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1492
1493 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1494 if (!mii_bus->irq) {
1495 err = -ENOMEM;
1496 goto err_free_bus;
1497 }
1498 for (i = 0; i < PHY_MAX_ADDR; i++)
1499 mii_bus->irq[i] = PHY_POLL;
1500
1501 err = mdiobus_register(mii_bus);
1502 if (err) {
1503 bgmac_err(bgmac, "Registration of mii bus failed\n");
1504 goto err_free_irq;
1505 }
1506
1507 bgmac->mii_bus = mii_bus;
1508
5824d2d1
RM		 1509 /* Connect to the PHY */
1510 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
1511 bgmac->phyaddr);
1512 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
1513 PHY_INTERFACE_MODE_MII);
1514 if (IS_ERR(phy_dev)) {
1515 bgmac_err(bgmac, "PHY connecton failed\n");
1516 err = PTR_ERR(phy_dev);
1517 goto err_unregister_bus;
1518 }
1519 bgmac->phy_dev = phy_dev;
1520
11e5e76e
RM		 1521 return err;
1522
5824d2d1
RM		 1523err_unregister_bus:
1524 mdiobus_unregister(mii_bus);
11e5e76e
RM		 1525err_free_irq:
1526 kfree(mii_bus->irq);
1527err_free_bus:
1528 mdiobus_free(mii_bus);
1529 return err;
1530}
1531
1532static void bgmac_mii_unregister(struct bgmac *bgmac)
1533{
1534 struct mii_bus *mii_bus = bgmac->mii_bus;
1535
1536 mdiobus_unregister(mii_bus);
1537 kfree(mii_bus->irq);
1538 mdiobus_free(mii_bus);
1539}
1540
dd4544f0
RM		 1541/**************************************************
1542 * BCMA bus ops
1543 **************************************************/
1544
1545/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1546static int bgmac_probe(struct bcma_device *core)
1547{
21697336 1548 struct bcma_chipinfo *ci = &core->bus->chipinfo;
dd4544f0
RM		 1549 struct net_device *net_dev;
1550 struct bgmac *bgmac;
1551 struct ssb_sprom *sprom = &core->bus->sprom;
1552 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
1553 int err;
1554
1555 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
1556 if (core->core_unit > 1) {
1557 pr_err("Unsupported core_unit %d\n", core->core_unit);
1558 return -ENOTSUPP;
1559 }
1560
d166f218
RM		 1561 if (!is_valid_ether_addr(mac)) {
1562 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1563 eth_random_addr(mac);
1564 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1565 }
1566
dd4544f0
RM		 1567 /* Allocation and references */
1568 net_dev = alloc_etherdev(sizeof(*bgmac));
1569 if (!net_dev)
1570 return -ENOMEM;
1571 net_dev->netdev_ops = &bgmac_netdev_ops;
1572 net_dev->irq = core->irq;
7ad24ea4 1573 net_dev->ethtool_ops = &bgmac_ethtool_ops;
dd4544f0
RM		 1574 bgmac = netdev_priv(net_dev);
1575 bgmac->net_dev = net_dev;
1576 bgmac->core = core;
1577 bcma_set_drvdata(core, bgmac);
1578
1579 /* Defaults */
dd4544f0
RM		 1580 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1581
1582 /* On BCM4706 we need common core to access PHY */
1583 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1584 !core->bus->drv_gmac_cmn.core) {
1585 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1586 err = -ENODEV;
1587 goto err_netdev_free;
1588 }
1589 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1590
1591 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
1592 sprom->et0phyaddr;
1593 bgmac->phyaddr &= BGMAC_PHY_MASK;
1594 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1595 bgmac_err(bgmac, "No PHY found\n");
1596 err = -ENODEV;
1597 goto err_netdev_free;
1598 }
1599 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1600 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1601
1602 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1603 bgmac_err(bgmac, "PCI setup not implemented\n");
1604 err = -ENOTSUPP;
1605 goto err_netdev_free;
1606 }
1607
1608 bgmac_chip_reset(bgmac);
1609
622a521f 1610 /* For Northstar, we have to take all GMAC core out of reset */
21697336
RM		 1611 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
1612 ci->id == BCMA_CHIP_ID_BCM53018) {
622a521f
HM		 1613 struct bcma_device *ns_core;
1614 int ns_gmac;
1615
1616 /* Northstar has 4 GMAC cores */
1617 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
0e595934 1618 /* As Northstar requirement, we have to reset all GMACs
622a521f
HM		 1619 * before accessing one. bgmac_chip_reset() call
1620 * bcma_core_enable() for this core. Then the other
0e595934 1621 * three GMACs didn't reset. We do it here.
622a521f
HM		 1622 */
1623 ns_core = bcma_find_core_unit(core->bus,
1624 BCMA_CORE_MAC_GBIT,
1625 ns_gmac);
1626 if (ns_core && !bcma_core_is_enabled(ns_core))
1627 bcma_core_enable(ns_core, 0);
1628 }
1629 }
1630
dd4544f0
RM		 1631 err = bgmac_dma_alloc(bgmac);
1632 if (err) {
1633 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1634 goto err_netdev_free;
1635 }
1636
1637 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
edb15d83 1638 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
dd4544f0
RM		 1639 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1640
1641 /* TODO: reset the external phy. Specs are needed */
1642 bgmac_phy_reset(bgmac);
1643
1644 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1645 BGMAC_BFL_ENETROBO);
1646 if (bgmac->has_robosw)
1647 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1648
1649 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1650 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1651
6216642f
HM		 1652 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1653
11e5e76e
RM		 1654 err = bgmac_mii_register(bgmac);
1655 if (err) {
1656 bgmac_err(bgmac, "Cannot register MDIO\n");
11e5e76e
RM		 1657 goto err_dma_free;
1658 }
1659
9cde9450
FF		 1660 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1661 net_dev->hw_features = net_dev->features;
1662 net_dev->vlan_features = net_dev->features;
1663
dd4544f0
RM		 1664 err = register_netdev(bgmac->net_dev);
1665 if (err) {
1666 bgmac_err(bgmac, "Cannot register net device\n");
11e5e76e 1667 goto err_mii_unregister;
dd4544f0
RM		 1668 }
1669
1670 netif_carrier_off(net_dev);
1671
dd4544f0
RM		 1672 return 0;
1673
11e5e76e
RM		 1674err_mii_unregister:
1675 bgmac_mii_unregister(bgmac);
dd4544f0
RM		 1676err_dma_free:
1677 bgmac_dma_free(bgmac);
1678
1679err_netdev_free:
1680 bcma_set_drvdata(core, NULL);
1681 free_netdev(net_dev);
1682
1683 return err;
1684}
1685
1686static void bgmac_remove(struct bcma_device *core)
1687{
1688 struct bgmac *bgmac = bcma_get_drvdata(core);
1689
dd4544f0 1690 unregister_netdev(bgmac->net_dev);
11e5e76e 1691 bgmac_mii_unregister(bgmac);
6216642f 1692 netif_napi_del(&bgmac->napi);
dd4544f0
RM		 1693 bgmac_dma_free(bgmac);
1694 bcma_set_drvdata(core, NULL);
1695 free_netdev(bgmac->net_dev);
1696}
1697
1698static struct bcma_driver bgmac_bcma_driver = {
1699 .name = KBUILD_MODNAME,
1700 .id_table = bgmac_bcma_tbl,
1701 .probe = bgmac_probe,
1702 .remove = bgmac_remove,
1703};
1704
1705static int __init bgmac_init(void)
1706{
1707 int err;
1708
1709 err = bcma_driver_register(&bgmac_bcma_driver);
1710 if (err)
1711 return err;
1712 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1713
1714 return 0;
1715}
1716
1717static void __exit bgmac_exit(void)
1718{
1719 bcma_driver_unregister(&bgmac_bcma_driver);
1720}
1721
1722module_init(bgmac_init)
1723module_exit(bgmac_exit)
1724
1725MODULE_AUTHOR("Rafał Miłecki");
1726MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)