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bgmac: reset cached MAC state during chip reset
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bgmac.c
CommitLineData
dd4544f0
RM		 1/*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
9#include "bgmac.h"
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
11e5e76e 16#include <linux/phy.h>
dd4544f0
RM		 17#include <linux/interrupt.h>
18#include <linux/dma-mapping.h>
edb15d83 19#include <bcm47xx_nvram.h>
dd4544f0
RM		 20
21static const struct bcma_device_id bgmac_bcma_tbl[] = {
22 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
24 BCMA_CORETABLE_END
25};
26MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
27
28static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
29 u32 value, int timeout)
30{
31 u32 val;
32 int i;
33
34 for (i = 0; i < timeout / 10; i++) {
35 val = bcma_read32(core, reg);
36 if ((val & mask) == value)
37 return true;
38 udelay(10);
39 }
40 pr_err("Timeout waiting for reg 0x%X\n", reg);
41 return false;
42}
43
44/**************************************************
45 * DMA
46 **************************************************/
47
48static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
49{
50 u32 val;
51 int i;
52
53 if (!ring->mmio_base)
54 return;
55
56 /* Suspend DMA TX ring first.
57 * bgmac_wait_value doesn't support waiting for any of few values, so
58 * implement whole loop here.
59 */
60 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
61 BGMAC_DMA_TX_SUSPEND);
62 for (i = 0; i < 10000 / 10; i++) {
63 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
64 val &= BGMAC_DMA_TX_STAT;
65 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
66 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
67 val == BGMAC_DMA_TX_STAT_STOPPED) {
68 i = 0;
69 break;
70 }
71 udelay(10);
72 }
73 if (i)
74 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
75 ring->mmio_base, val);
76
77 /* Remove SUSPEND bit */
78 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
79 if (!bgmac_wait_value(bgmac->core,
80 ring->mmio_base + BGMAC_DMA_TX_STATUS,
81 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
82 10000)) {
83 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
84 ring->mmio_base);
85 udelay(300);
86 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
87 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
88 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
89 ring->mmio_base);
90 }
91}
92
93static void bgmac_dma_tx_enable(struct bgmac *bgmac,
94 struct bgmac_dma_ring *ring)
95{
96 u32 ctl;
97
98 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
99 ctl |= BGMAC_DMA_TX_ENABLE;
100 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
101 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
102}
103
104static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
105 struct bgmac_dma_ring *ring,
106 struct sk_buff *skb)
107{
108 struct device *dma_dev = bgmac->core->dma_dev;
109 struct net_device *net_dev = bgmac->net_dev;
110 struct bgmac_dma_desc *dma_desc;
111 struct bgmac_slot_info *slot;
112 u32 ctl0, ctl1;
113 int free_slots;
114
115 if (skb->len > BGMAC_DESC_CTL1_LEN) {
116 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
117 goto err_stop_drop;
118 }
119
120 if (ring->start <= ring->end)
121 free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS;
122 else
123 free_slots = ring->start - ring->end;
124 if (free_slots == 1) {
125 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
126 netif_stop_queue(net_dev);
127 return NETDEV_TX_BUSY;
128 }
129
130 slot = &ring->slots[ring->end];
131 slot->skb = skb;
132 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len,
133 DMA_TO_DEVICE);
134 if (dma_mapping_error(dma_dev, slot->dma_addr)) {
135 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
136 ring->mmio_base);
137 goto err_stop_drop;
138 }
139
140 ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF;
141 if (ring->end == ring->num_slots - 1)
142 ctl0 |= BGMAC_DESC_CTL0_EOT;
143 ctl1 = skb->len & BGMAC_DESC_CTL1_LEN;
144
145 dma_desc = ring->cpu_base;
146 dma_desc += ring->end;
147 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
148 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
149 dma_desc->ctl0 = cpu_to_le32(ctl0);
150 dma_desc->ctl1 = cpu_to_le32(ctl1);
151
49a467b4
HM		 152 netdev_sent_queue(net_dev, skb->len);
153
dd4544f0
RM		 154 wmb();
155
156 /* Increase ring->end to point empty slot. We tell hardware the first
157 * slot it should *not* read.
158 */
159 if (++ring->end >= BGMAC_TX_RING_SLOTS)
160 ring->end = 0;
161 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
9900303e 162 ring->index_base +
dd4544f0
RM		 163 ring->end * sizeof(struct bgmac_dma_desc));
164
165 /* Always keep one slot free to allow detecting bugged calls. */
166 if (--free_slots == 1)
167 netif_stop_queue(net_dev);
168
169 return NETDEV_TX_OK;
170
171err_stop_drop:
172 netif_stop_queue(net_dev);
173 dev_kfree_skb(skb);
174 return NETDEV_TX_OK;
175}
176
177/* Free transmitted packets */
178static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
179{
180 struct device *dma_dev = bgmac->core->dma_dev;
181 int empty_slot;
182 bool freed = false;
49a467b4 183 unsigned bytes_compl = 0, pkts_compl = 0;
dd4544f0
RM		 184
185 /* The last slot that hardware didn't consume yet */
186 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
187 empty_slot &= BGMAC_DMA_TX_STATDPTR;
9900303e
RM		 188 empty_slot -= ring->index_base;
189 empty_slot &= BGMAC_DMA_TX_STATDPTR;
dd4544f0
RM		 190 empty_slot /= sizeof(struct bgmac_dma_desc);
191
192 while (ring->start != empty_slot) {
193 struct bgmac_slot_info *slot = &ring->slots[ring->start];
194
195 if (slot->skb) {
196 /* Unmap no longer used buffer */
197 dma_unmap_single(dma_dev, slot->dma_addr,
198 slot->skb->len, DMA_TO_DEVICE);
199 slot->dma_addr = 0;
200
49a467b4
HM		 201 bytes_compl += slot->skb->len;
202 pkts_compl++;
203
dd4544f0
RM		 204 /* Free memory! :) */
205 dev_kfree_skb(slot->skb);
206 slot->skb = NULL;
207 } else {
208 bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n",
209 ring->start, ring->end);
210 }
211
212 if (++ring->start >= BGMAC_TX_RING_SLOTS)
213 ring->start = 0;
214 freed = true;
215 }
216
49a467b4
HM		 217 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
218
dd4544f0
RM		 219 if (freed && netif_queue_stopped(bgmac->net_dev))
220 netif_wake_queue(bgmac->net_dev);
221}
222
223static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
224{
225 if (!ring->mmio_base)
226 return;
227
228 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
229 if (!bgmac_wait_value(bgmac->core,
230 ring->mmio_base + BGMAC_DMA_RX_STATUS,
231 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
232 10000))
233 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
234 ring->mmio_base);
235}
236
237static void bgmac_dma_rx_enable(struct bgmac *bgmac,
238 struct bgmac_dma_ring *ring)
239{
240 u32 ctl;
241
242 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
243 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
244 ctl |= BGMAC_DMA_RX_ENABLE;
245 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
246 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
247 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
248 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
249}
250
251static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
252 struct bgmac_slot_info *slot)
253{
254 struct device *dma_dev = bgmac->core->dma_dev;
b757a62e
NH		 255 struct sk_buff *skb;
256 dma_addr_t dma_addr;
dd4544f0
RM		 257 struct bgmac_rx_header *rx;
258
259 /* Alloc skb */
b757a62e
NH		 260 skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE);
261 if (!skb)
dd4544f0 262 return -ENOMEM;
dd4544f0
RM		 263
264 /* Poison - if everything goes fine, hardware will overwrite it */
b757a62e 265 rx = (struct bgmac_rx_header *)skb->data;
dd4544f0
RM		 266 rx->len = cpu_to_le16(0xdead);
267 rx->flags = cpu_to_le16(0xbeef);
268
269 /* Map skb for the DMA */
b757a62e
NH		 270 dma_addr = dma_map_single(dma_dev, skb->data,
271 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
272 if (dma_mapping_error(dma_dev, dma_addr)) {
dd4544f0 273 bgmac_err(bgmac, "DMA mapping error\n");
b757a62e 274 dev_kfree_skb(skb);
dd4544f0
RM		 275 return -ENOMEM;
276 }
b757a62e
NH		 277
278 /* Update the slot */
279 slot->skb = skb;
280 slot->dma_addr = dma_addr;
281
dd4544f0
RM		 282 if (slot->dma_addr & 0xC0000000)
283 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
284
285 return 0;
286}
287
d549c76b
RM		 288static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
289 struct bgmac_dma_ring *ring, int desc_idx)
290{
291 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
292 u32 ctl0 = 0, ctl1 = 0;
293
294 if (desc_idx == ring->num_slots - 1)
295 ctl0 |= BGMAC_DESC_CTL0_EOT;
296 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
297 /* Is there any BGMAC device that requires extension? */
298 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
299 * B43_DMA64_DCTL1_ADDREXT_MASK;
300 */
301
302 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
303 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
304 dma_desc->ctl0 = cpu_to_le32(ctl0);
305 dma_desc->ctl1 = cpu_to_le32(ctl1);
306}
307
dd4544f0
RM		 308static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
309 int weight)
310{
311 u32 end_slot;
312 int handled = 0;
313
314 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
315 end_slot &= BGMAC_DMA_RX_STATDPTR;
9900303e
RM		 316 end_slot -= ring->index_base;
317 end_slot &= BGMAC_DMA_RX_STATDPTR;
dd4544f0
RM		 318 end_slot /= sizeof(struct bgmac_dma_desc);
319
320 ring->end = end_slot;
321
322 while (ring->start != ring->end) {
323 struct device *dma_dev = bgmac->core->dma_dev;
324 struct bgmac_slot_info *slot = &ring->slots[ring->start];
325 struct sk_buff *skb = slot->skb;
dd4544f0
RM		 326 struct bgmac_rx_header *rx;
327 u16 len, flags;
328
329 /* Unmap buffer to make it accessible to the CPU */
330 dma_sync_single_for_cpu(dma_dev, slot->dma_addr,
331 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
332
333 /* Get info from the header */
334 rx = (struct bgmac_rx_header *)skb->data;
335 len = le16_to_cpu(rx->len);
336 flags = le16_to_cpu(rx->flags);
337
92b9ccd3
RM		 338 do {
339 dma_addr_t old_dma_addr = slot->dma_addr;
340 int err;
341
342 /* Check for poison and drop or pass the packet */
343 if (len == 0xdead && flags == 0xbeef) {
344 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
345 ring->start);
346 dma_sync_single_for_device(dma_dev,
347 slot->dma_addr,
348 BGMAC_RX_BUF_SIZE,
349 DMA_FROM_DEVICE);
350 break;
351 }
352
02e71127
HM		 353 /* Omit CRC. */
354 len -= ETH_FCS_LEN;
355
92b9ccd3
RM		 356 /* Prepare new skb as replacement */
357 err = bgmac_dma_rx_skb_for_slot(bgmac, slot);
358 if (err) {
359 /* Poison the old skb */
360 rx->len = cpu_to_le16(0xdead);
361 rx->flags = cpu_to_le16(0xbeef);
362
363 dma_sync_single_for_device(dma_dev,
364 slot->dma_addr,
365 BGMAC_RX_BUF_SIZE,
366 DMA_FROM_DEVICE);
367 break;
dd4544f0 368 }
92b9ccd3 369 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
dd4544f0 370
92b9ccd3
RM		 371 /* Unmap old skb, we'll pass it to the netfif */
372 dma_unmap_single(dma_dev, old_dma_addr,
373 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
374
375 skb_put(skb, BGMAC_RX_FRAME_OFFSET + len);
376 skb_pull(skb, BGMAC_RX_FRAME_OFFSET);
dd4544f0 377
92b9ccd3
RM		 378 skb_checksum_none_assert(skb);
379 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
380 netif_receive_skb(skb);
381 handled++;
382 } while (0);
dd4544f0
RM		 383
384 if (++ring->start >= BGMAC_RX_RING_SLOTS)
385 ring->start = 0;
386
387 if (handled >= weight) /* Should never be greater */
388 break;
389 }
390
391 return handled;
392}
393
394/* Does ring support unaligned addressing? */
395static bool bgmac_dma_unaligned(struct bgmac *bgmac,
396 struct bgmac_dma_ring *ring,
397 enum bgmac_dma_ring_type ring_type)
398{
399 switch (ring_type) {
400 case BGMAC_DMA_RING_TX:
401 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
402 0xff0);
403 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
404 return true;
405 break;
406 case BGMAC_DMA_RING_RX:
407 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
408 0xff0);
409 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
410 return true;
411 break;
412 }
413 return false;
414}
415
416static void bgmac_dma_ring_free(struct bgmac *bgmac,
417 struct bgmac_dma_ring *ring)
418{
419 struct device *dma_dev = bgmac->core->dma_dev;
420 struct bgmac_slot_info *slot;
421 int size;
422 int i;
423
424 for (i = 0; i < ring->num_slots; i++) {
425 slot = &ring->slots[i];
426 if (slot->skb) {
427 if (slot->dma_addr)
428 dma_unmap_single(dma_dev, slot->dma_addr,
429 slot->skb->len, DMA_TO_DEVICE);
430 dev_kfree_skb(slot->skb);
431 }
432 }
433
434 if (ring->cpu_base) {
435 /* Free ring of descriptors */
436 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
437 dma_free_coherent(dma_dev, size, ring->cpu_base,
438 ring->dma_base);
439 }
440}
441
442static void bgmac_dma_free(struct bgmac *bgmac)
443{
444 int i;
445
446 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
447 bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]);
448 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
449 bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]);
450}
451
452static int bgmac_dma_alloc(struct bgmac *bgmac)
453{
454 struct device *dma_dev = bgmac->core->dma_dev;
455 struct bgmac_dma_ring *ring;
456 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
457 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
458 int size; /* ring size: different for Tx and Rx */
459 int err;
460 int i;
461
462 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
463 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
464
465 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
466 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
467 return -ENOTSUPP;
468 }
469
470 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
471 ring = &bgmac->tx_ring[i];
472 ring->num_slots = BGMAC_TX_RING_SLOTS;
473 ring->mmio_base = ring_base[i];
dd4544f0
RM		 474
475 /* Alloc ring of descriptors */
476 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
477 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
478 &ring->dma_base,
479 GFP_KERNEL);
480 if (!ring->cpu_base) {
481 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
482 ring->mmio_base);
483 goto err_dma_free;
484 }
485 if (ring->dma_base & 0xC0000000)
486 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
487
9900303e
RM		 488 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
489 BGMAC_DMA_RING_TX);
490 if (ring->unaligned)
491 ring->index_base = lower_32_bits(ring->dma_base);
492 else
493 ring->index_base = 0;
494
dd4544f0
RM		 495 /* No need to alloc TX slots yet */
496 }
497
498 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
70a737b7
RM		 499 int j;
500
dd4544f0
RM		 501 ring = &bgmac->rx_ring[i];
502 ring->num_slots = BGMAC_RX_RING_SLOTS;
503 ring->mmio_base = ring_base[i];
dd4544f0
RM		 504
505 /* Alloc ring of descriptors */
506 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
507 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
508 &ring->dma_base,
509 GFP_KERNEL);
510 if (!ring->cpu_base) {
511 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
512 ring->mmio_base);
513 err = -ENOMEM;
514 goto err_dma_free;
515 }
516 if (ring->dma_base & 0xC0000000)
517 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
518
9900303e
RM		 519 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
520 BGMAC_DMA_RING_RX);
521 if (ring->unaligned)
522 ring->index_base = lower_32_bits(ring->dma_base);
523 else
524 ring->index_base = 0;
525
dd4544f0 526 /* Alloc RX slots */
70a737b7
RM		 527 for (j = 0; j < ring->num_slots; j++) {
528 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
dd4544f0
RM		 529 if (err) {
530 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n");
531 goto err_dma_free;
532 }
533 }
534 }
535
536 return 0;
537
538err_dma_free:
539 bgmac_dma_free(bgmac);
540 return -ENOMEM;
541}
542
543static void bgmac_dma_init(struct bgmac *bgmac)
544{
545 struct bgmac_dma_ring *ring;
dd4544f0
RM		 546 int i;
547
548 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
549 ring = &bgmac->tx_ring[i];
550
9900303e
RM		 551 if (!ring->unaligned)
552 bgmac_dma_tx_enable(bgmac, ring);
dd4544f0
RM		 553 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
554 lower_32_bits(ring->dma_base));
555 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
556 upper_32_bits(ring->dma_base));
9900303e
RM		 557 if (ring->unaligned)
558 bgmac_dma_tx_enable(bgmac, ring);
dd4544f0
RM		 559
560 ring->start = 0;
561 ring->end = 0; /* Points the slot that should *not* be read */
562 }
563
564 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
70a737b7
RM		 565 int j;
566
dd4544f0
RM		 567 ring = &bgmac->rx_ring[i];
568
9900303e
RM		 569 if (!ring->unaligned)
570 bgmac_dma_rx_enable(bgmac, ring);
dd4544f0
RM		 571 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
572 lower_32_bits(ring->dma_base));
573 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
574 upper_32_bits(ring->dma_base));
9900303e
RM		 575 if (ring->unaligned)
576 bgmac_dma_rx_enable(bgmac, ring);
dd4544f0 577
d549c76b
RM		 578 for (j = 0; j < ring->num_slots; j++)
579 bgmac_dma_rx_setup_desc(bgmac, ring, j);
dd4544f0
RM		 580
581 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
9900303e 582 ring->index_base +
dd4544f0
RM		 583 ring->num_slots * sizeof(struct bgmac_dma_desc));
584
585 ring->start = 0;
586 ring->end = 0;
587 }
588}
589
590/**************************************************
591 * PHY ops
592 **************************************************/
593
217a55a3 594static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
dd4544f0
RM		 595{
596 struct bcma_device *core;
597 u16 phy_access_addr;
598 u16 phy_ctl_addr;
599 u32 tmp;
600
601 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
602 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
603 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
604 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
605 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
606 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
607 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
608 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
609 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
610 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
611 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
612
613 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
614 core = bgmac->core->bus->drv_gmac_cmn.core;
615 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
616 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
617 } else {
618 core = bgmac->core;
619 phy_access_addr = BGMAC_PHY_ACCESS;
620 phy_ctl_addr = BGMAC_PHY_CNTL;
621 }
622
623 tmp = bcma_read32(core, phy_ctl_addr);
624 tmp &= ~BGMAC_PC_EPA_MASK;
625 tmp |= phyaddr;
626 bcma_write32(core, phy_ctl_addr, tmp);
627
628 tmp = BGMAC_PA_START;
629 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
630 tmp |= reg << BGMAC_PA_REG_SHIFT;
631 bcma_write32(core, phy_access_addr, tmp);
632
633 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
634 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
635 phyaddr, reg);
636 return 0xffff;
637 }
638
639 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
640}
641
642/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
217a55a3 643static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
dd4544f0
RM		 644{
645 struct bcma_device *core;
646 u16 phy_access_addr;
647 u16 phy_ctl_addr;
648 u32 tmp;
649
650 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
651 core = bgmac->core->bus->drv_gmac_cmn.core;
652 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
653 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
654 } else {
655 core = bgmac->core;
656 phy_access_addr = BGMAC_PHY_ACCESS;
657 phy_ctl_addr = BGMAC_PHY_CNTL;
658 }
659
660 tmp = bcma_read32(core, phy_ctl_addr);
661 tmp &= ~BGMAC_PC_EPA_MASK;
662 tmp |= phyaddr;
663 bcma_write32(core, phy_ctl_addr, tmp);
664
665 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
666 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
667 bgmac_warn(bgmac, "Error setting MDIO int\n");
668
669 tmp = BGMAC_PA_START;
670 tmp |= BGMAC_PA_WRITE;
671 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
672 tmp |= reg << BGMAC_PA_REG_SHIFT;
673 tmp |= value;
674 bcma_write32(core, phy_access_addr, tmp);
675
217a55a3 676 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
dd4544f0
RM		 677 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
678 phyaddr, reg);
217a55a3
RM		 679 return -ETIMEDOUT;
680 }
681
682 return 0;
dd4544f0
RM		 683}
684
dd4544f0
RM		 685/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
686static void bgmac_phy_init(struct bgmac *bgmac)
687{
688 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
689 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
690 u8 i;
691
692 if (ci->id == BCMA_CHIP_ID_BCM5356) {
693 for (i = 0; i < 5; i++) {
694 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
695 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
696 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
697 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
698 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
699 }
700 }
701 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
702 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
703 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
704 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
705 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
706 for (i = 0; i < 5; i++) {
707 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
708 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
709 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
710 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
711 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
712 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
713 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
714 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
715 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
716 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
717 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
718 }
719 }
720}
721
722/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
723static void bgmac_phy_reset(struct bgmac *bgmac)
724{
725 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
726 return;
727
728 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
729 BGMAC_PHY_CTL_RESET);
730 udelay(100);
731 if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
732 BGMAC_PHY_CTL_RESET)
733 bgmac_err(bgmac, "PHY reset failed\n");
734 bgmac_phy_init(bgmac);
735}
736
737/**************************************************
738 * Chip ops
739 **************************************************/
740
741/* TODO: can we just drop @force? Can we don't reset MAC at all if there is
742 * nothing to change? Try if after stabilizng driver.
743 */
744static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
745 bool force)
746{
747 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
748 u32 new_val = (cmdcfg & mask) | set;
749
750 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
751 udelay(2);
752
753 if (new_val != cmdcfg || force)
754 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
755
756 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
757 udelay(2);
758}
759
4e209001
HM		 760static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
761{
762 u32 tmp;
763
764 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
765 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
766 tmp = (addr[4] << 8) | addr[5];
767 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
768}
769
c6edfe10
HM		 770static void bgmac_set_rx_mode(struct net_device *net_dev)
771{
772 struct bgmac *bgmac = netdev_priv(net_dev);
773
774 if (net_dev->flags & IFF_PROMISC)
e9ba1039 775 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
c6edfe10 776 else
e9ba1039 777 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
c6edfe10
HM		 778}
779
dd4544f0
RM		 780#if 0 /* We don't use that regs yet */
781static void bgmac_chip_stats_update(struct bgmac *bgmac)
782{
783 int i;
784
785 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
786 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
787 bgmac->mib_tx_regs[i] =
788 bgmac_read(bgmac,
789 BGMAC_TX_GOOD_OCTETS + (i * 4));
790 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
791 bgmac->mib_rx_regs[i] =
792 bgmac_read(bgmac,
793 BGMAC_RX_GOOD_OCTETS + (i * 4));
794 }
795
796 /* TODO: what else? how to handle BCM4706? Specs are needed */
797}
798#endif
799
800static void bgmac_clear_mib(struct bgmac *bgmac)
801{
802 int i;
803
804 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
805 return;
806
807 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
808 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
809 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
810 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
811 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
812}
813
814/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
5824d2d1 815static void bgmac_mac_speed(struct bgmac *bgmac)
dd4544f0
RM		 816{
817 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
818 u32 set = 0;
819
5824d2d1
RM		 820 switch (bgmac->mac_speed) {
821 case SPEED_10:
dd4544f0 822 set |= BGMAC_CMDCFG_ES_10;
5824d2d1
RM		 823 break;
824 case SPEED_100:
dd4544f0 825 set |= BGMAC_CMDCFG_ES_100;
5824d2d1
RM		 826 break;
827 case SPEED_1000:
dd4544f0 828 set |= BGMAC_CMDCFG_ES_1000;
5824d2d1
RM		 829 break;
830 default:
831 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
832 }
833
834 if (bgmac->mac_duplex == DUPLEX_HALF)
dd4544f0 835 set |= BGMAC_CMDCFG_HD;
5824d2d1 836
dd4544f0
RM		 837 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
838}
839
840static void bgmac_miiconfig(struct bgmac *bgmac)
841{
842 u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
843 BGMAC_DS_MM_SHIFT;
844 if (imode == 0 || imode == 1) {
5824d2d1
RM		 845 bgmac->mac_speed = SPEED_100;
846 bgmac->mac_duplex = DUPLEX_FULL;
847 bgmac_mac_speed(bgmac);
dd4544f0
RM		 848 }
849}
850
851/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
852static void bgmac_chip_reset(struct bgmac *bgmac)
853{
854 struct bcma_device *core = bgmac->core;
855 struct bcma_bus *bus = core->bus;
856 struct bcma_chipinfo *ci = &bus->chipinfo;
857 u32 flags = 0;
858 u32 iost;
859 int i;
860
861 if (bcma_core_is_enabled(core)) {
862 if (!bgmac->stats_grabbed) {
863 /* bgmac_chip_stats_update(bgmac); */
864 bgmac->stats_grabbed = true;
865 }
866
867 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
868 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
869
870 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
871 udelay(1);
872
873 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
874 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
875
876 /* TODO: Clear software multicast filter list */
877 }
878
879 iost = bcma_aread32(core, BCMA_IOST);
880 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) ||
881 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
882 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9))
883 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
884
885 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
886 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
887 if (!bgmac->has_robosw)
888 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
889 }
890
891 bcma_core_enable(core, flags);
892
893 if (core->id.rev > 2) {
894 bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
895 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
896 1000);
897 }
898
899 if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 ||
900 ci->id == BCMA_CHIP_ID_BCM53572) {
901 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
902 u8 et_swtype = 0;
903 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
6a391e7b 904 BGMAC_CHIPCTL_1_IF_TYPE_MII;
3647268d 905 char buf[4];
dd4544f0 906
3647268d 907 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
dd4544f0
RM		 908 if (kstrtou8(buf, 0, &et_swtype))
909 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
910 buf);
911 et_swtype &= 0x0f;
912 et_swtype <<= 4;
913 sw_type = et_swtype;
914 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
915 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
b5a4c2f3
HM		 916 } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
917 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
918 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
919 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
dd4544f0
RM		 920 }
921 bcma_chipco_chipctl_maskset(cc, 1,
922 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
923 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
924 sw_type);
925 }
926
927 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
928 bcma_awrite32(core, BCMA_IOCTL,
929 bcma_aread32(core, BCMA_IOCTL) &
930 ~BGMAC_BCMA_IOCTL_SW_RESET);
931
932 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
933 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
934 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
935 * be keps until taking MAC out of the reset.
936 */
937 bgmac_cmdcfg_maskset(bgmac,
938 ~(BGMAC_CMDCFG_TE |
939 BGMAC_CMDCFG_RE |
940 BGMAC_CMDCFG_RPI |
941 BGMAC_CMDCFG_TAI |
942 BGMAC_CMDCFG_HD |
943 BGMAC_CMDCFG_ML |
944 BGMAC_CMDCFG_CFE |
945 BGMAC_CMDCFG_RL |
946 BGMAC_CMDCFG_RED |
947 BGMAC_CMDCFG_PE |
948 BGMAC_CMDCFG_TPI |
949 BGMAC_CMDCFG_PAD_EN |
950 BGMAC_CMDCFG_PF),
951 BGMAC_CMDCFG_PROM |
952 BGMAC_CMDCFG_NLC |
953 BGMAC_CMDCFG_CFE |
954 BGMAC_CMDCFG_SR,
955 false);
d469962f
RM		 956 bgmac->mac_speed = SPEED_UNKNOWN;
957 bgmac->mac_duplex = DUPLEX_UNKNOWN;
dd4544f0
RM		 958
959 bgmac_clear_mib(bgmac);
960 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
961 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
962 BCMA_GMAC_CMN_PC_MTE);
963 else
964 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
965 bgmac_miiconfig(bgmac);
966 bgmac_phy_init(bgmac);
967
49a467b4
HM		 968 netdev_reset_queue(bgmac->net_dev);
969
dd4544f0
RM		 970 bgmac->int_status = 0;
971}
972
973static void bgmac_chip_intrs_on(struct bgmac *bgmac)
974{
975 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
976}
977
978static void bgmac_chip_intrs_off(struct bgmac *bgmac)
979{
980 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
4160815f 981 bgmac_read(bgmac, BGMAC_INT_MASK);
dd4544f0
RM		 982}
983
984/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
985static void bgmac_enable(struct bgmac *bgmac)
986{
987 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
988 u32 cmdcfg;
989 u32 mode;
990 u32 rxq_ctl;
991 u32 fl_ctl;
992 u16 bp_clk;
993 u8 mdp;
994
995 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
996 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
997 BGMAC_CMDCFG_SR, true);
998 udelay(2);
999 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1000 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1001
1002 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1003 BGMAC_DS_MM_SHIFT;
1004 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1005 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1006 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1007 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1008 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1009
1010 switch (ci->id) {
1011 case BCMA_CHIP_ID_BCM5357:
1012 case BCMA_CHIP_ID_BCM4749:
1013 case BCMA_CHIP_ID_BCM53572:
1014 case BCMA_CHIP_ID_BCM4716:
1015 case BCMA_CHIP_ID_BCM47162:
1016 fl_ctl = 0x03cb04cb;
1017 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1018 ci->id == BCMA_CHIP_ID_BCM4749 ||
1019 ci->id == BCMA_CHIP_ID_BCM53572)
1020 fl_ctl = 0x2300e1;
1021 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1022 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1023 break;
1024 }
1025
1026 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1027 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1028 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
1029 mdp = (bp_clk * 128 / 1000) - 3;
1030 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1031 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1032}
1033
1034/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1035static void bgmac_chip_init(struct bgmac *bgmac, bool full_init)
1036{
1037 struct bgmac_dma_ring *ring;
dd4544f0
RM		 1038 int i;
1039
1040 /* 1 interrupt per received frame */
1041 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1042
1043 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1044 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1045
c6edfe10 1046 bgmac_set_rx_mode(bgmac->net_dev);
dd4544f0 1047
4e209001 1048 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
dd4544f0
RM		 1049
1050 if (bgmac->loopback)
e9ba1039 1051 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
dd4544f0 1052 else
e9ba1039 1053 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
dd4544f0
RM		 1054
1055 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1056
dd4544f0
RM		 1057 if (full_init) {
1058 bgmac_dma_init(bgmac);
1059 if (1) /* FIXME: is there any case we don't want IRQs? */
1060 bgmac_chip_intrs_on(bgmac);
1061 } else {
1062 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
1063 ring = &bgmac->rx_ring[i];
1064 bgmac_dma_rx_enable(bgmac, ring);
1065 }
1066 }
1067
1068 bgmac_enable(bgmac);
1069}
1070
1071static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1072{
1073 struct bgmac *bgmac = netdev_priv(dev_id);
1074
1075 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1076 int_status &= bgmac->int_mask;
1077
1078 if (!int_status)
1079 return IRQ_NONE;
1080
1081 /* Ack */
1082 bgmac_write(bgmac, BGMAC_INT_STATUS, int_status);
1083
1084 /* Disable new interrupts until handling existing ones */
1085 bgmac_chip_intrs_off(bgmac);
1086
1087 bgmac->int_status = int_status;
1088
1089 napi_schedule(&bgmac->napi);
1090
1091 return IRQ_HANDLED;
1092}
1093
1094static int bgmac_poll(struct napi_struct *napi, int weight)
1095{
1096 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1097 struct bgmac_dma_ring *ring;
1098 int handled = 0;
1099
1100 if (bgmac->int_status & BGMAC_IS_TX0) {
1101 ring = &bgmac->tx_ring[0];
1102 bgmac_dma_tx_free(bgmac, ring);
1103 bgmac->int_status &= ~BGMAC_IS_TX0;
1104 }
1105
1106 if (bgmac->int_status & BGMAC_IS_RX) {
1107 ring = &bgmac->rx_ring[0];
1108 handled += bgmac_dma_rx_read(bgmac, ring, weight);
1109 bgmac->int_status &= ~BGMAC_IS_RX;
1110 }
1111
1112 if (bgmac->int_status) {
1113 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status);
1114 bgmac->int_status = 0;
1115 }
1116
1117 if (handled < weight)
1118 napi_complete(napi);
1119
1120 bgmac_chip_intrs_on(bgmac);
1121
1122 return handled;
1123}
1124
1125/**************************************************
1126 * net_device_ops
1127 **************************************************/
1128
1129static int bgmac_open(struct net_device *net_dev)
1130{
1131 struct bgmac *bgmac = netdev_priv(net_dev);
1132 int err = 0;
1133
1134 bgmac_chip_reset(bgmac);
1135 /* Specs say about reclaiming rings here, but we do that in DMA init */
1136 bgmac_chip_init(bgmac, true);
1137
1138 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1139 KBUILD_MODNAME, net_dev);
1140 if (err < 0) {
1141 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
1142 goto err_out;
1143 }
1144 napi_enable(&bgmac->napi);
1145
4e34da4d
RM		 1146 phy_start(bgmac->phy_dev);
1147
dd4544f0
RM		 1148 netif_carrier_on(net_dev);
1149
1150err_out:
1151 return err;
1152}
1153
1154static int bgmac_stop(struct net_device *net_dev)
1155{
1156 struct bgmac *bgmac = netdev_priv(net_dev);
1157
1158 netif_carrier_off(net_dev);
1159
4e34da4d
RM		 1160 phy_stop(bgmac->phy_dev);
1161
dd4544f0
RM		 1162 napi_disable(&bgmac->napi);
1163 bgmac_chip_intrs_off(bgmac);
1164 free_irq(bgmac->core->irq, net_dev);
1165
1166 bgmac_chip_reset(bgmac);
1167
1168 return 0;
1169}
1170
1171static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1172 struct net_device *net_dev)
1173{
1174 struct bgmac *bgmac = netdev_priv(net_dev);
1175 struct bgmac_dma_ring *ring;
1176
1177 /* No QOS support yet */
1178 ring = &bgmac->tx_ring[0];
1179 return bgmac_dma_tx_add(bgmac, ring, skb);
1180}
1181
4e209001
HM		 1182static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1183{
1184 struct bgmac *bgmac = netdev_priv(net_dev);
1185 int ret;
1186
1187 ret = eth_prepare_mac_addr_change(net_dev, addr);
1188 if (ret < 0)
1189 return ret;
1190 bgmac_write_mac_address(bgmac, (u8 *)addr);
1191 eth_commit_mac_addr_change(net_dev, addr);
1192 return 0;
1193}
1194
dd4544f0
RM		 1195static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1196{
1197 struct bgmac *bgmac = netdev_priv(net_dev);
1198 struct mii_ioctl_data *data = if_mii(ifr);
1199
1200 switch (cmd) {
1201 case SIOCGMIIPHY:
1202 data->phy_id = bgmac->phyaddr;
1203 /* fallthru */
1204 case SIOCGMIIREG:
1205 if (!netif_running(net_dev))
1206 return -EAGAIN;
1207 data->val_out = bgmac_phy_read(bgmac, data->phy_id,
1208 data->reg_num & 0x1f);
1209 return 0;
1210 case SIOCSMIIREG:
1211 if (!netif_running(net_dev))
1212 return -EAGAIN;
1213 bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
1214 data->val_in);
1215 return 0;
1216 default:
1217 return -EOPNOTSUPP;
1218 }
1219}
1220
1221static const struct net_device_ops bgmac_netdev_ops = {
1222 .ndo_open = bgmac_open,
1223 .ndo_stop = bgmac_stop,
1224 .ndo_start_xmit = bgmac_start_xmit,
c6edfe10 1225 .ndo_set_rx_mode = bgmac_set_rx_mode,
4e209001 1226 .ndo_set_mac_address = bgmac_set_mac_address,
522c5907 1227 .ndo_validate_addr = eth_validate_addr,
dd4544f0
RM		 1228 .ndo_do_ioctl = bgmac_ioctl,
1229};
1230
1231/**************************************************
1232 * ethtool_ops
1233 **************************************************/
1234
1235static int bgmac_get_settings(struct net_device *net_dev,
1236 struct ethtool_cmd *cmd)
1237{
1238 struct bgmac *bgmac = netdev_priv(net_dev);
1239
5824d2d1 1240 return phy_ethtool_gset(bgmac->phy_dev, cmd);
dd4544f0
RM		 1241}
1242
dd4544f0
RM		 1243static int bgmac_set_settings(struct net_device *net_dev,
1244 struct ethtool_cmd *cmd)
1245{
1246 struct bgmac *bgmac = netdev_priv(net_dev);
1247
5824d2d1 1248 return phy_ethtool_sset(bgmac->phy_dev, cmd);
dd4544f0 1249}
dd4544f0
RM		 1250
1251static void bgmac_get_drvinfo(struct net_device *net_dev,
1252 struct ethtool_drvinfo *info)
1253{
1254 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1255 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1256}
1257
1258static const struct ethtool_ops bgmac_ethtool_ops = {
1259 .get_settings = bgmac_get_settings,
5824d2d1 1260 .set_settings = bgmac_set_settings,
dd4544f0
RM		 1261 .get_drvinfo = bgmac_get_drvinfo,
1262};
1263
11e5e76e
RM		 1264/**************************************************
1265 * MII
1266 **************************************************/
1267
1268static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1269{
1270 return bgmac_phy_read(bus->priv, mii_id, regnum);
1271}
1272
1273static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1274 u16 value)
1275{
1276 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1277}
1278
5824d2d1
RM		 1279static void bgmac_adjust_link(struct net_device *net_dev)
1280{
1281 struct bgmac *bgmac = netdev_priv(net_dev);
1282 struct phy_device *phy_dev = bgmac->phy_dev;
1283 bool update = false;
1284
1285 if (phy_dev->link) {
1286 if (phy_dev->speed != bgmac->mac_speed) {
1287 bgmac->mac_speed = phy_dev->speed;
1288 update = true;
1289 }
1290
1291 if (phy_dev->duplex != bgmac->mac_duplex) {
1292 bgmac->mac_duplex = phy_dev->duplex;
1293 update = true;
1294 }
1295 }
1296
1297 if (update) {
1298 bgmac_mac_speed(bgmac);
1299 phy_print_status(phy_dev);
1300 }
1301}
1302
11e5e76e
RM		 1303static int bgmac_mii_register(struct bgmac *bgmac)
1304{
1305 struct mii_bus *mii_bus;
5824d2d1
RM		 1306 struct phy_device *phy_dev;
1307 char bus_id[MII_BUS_ID_SIZE + 3];
11e5e76e
RM		 1308 int i, err = 0;
1309
1310 mii_bus = mdiobus_alloc();
1311 if (!mii_bus)
1312 return -ENOMEM;
1313
1314 mii_bus->name = "bgmac mii bus";
1315 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1316 bgmac->core->core_unit);
1317 mii_bus->priv = bgmac;
1318 mii_bus->read = bgmac_mii_read;
1319 mii_bus->write = bgmac_mii_write;
1320 mii_bus->parent = &bgmac->core->dev;
1321 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1322
1323 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1324 if (!mii_bus->irq) {
1325 err = -ENOMEM;
1326 goto err_free_bus;
1327 }
1328 for (i = 0; i < PHY_MAX_ADDR; i++)
1329 mii_bus->irq[i] = PHY_POLL;
1330
1331 err = mdiobus_register(mii_bus);
1332 if (err) {
1333 bgmac_err(bgmac, "Registration of mii bus failed\n");
1334 goto err_free_irq;
1335 }
1336
1337 bgmac->mii_bus = mii_bus;
1338
5824d2d1
RM		 1339 /* Connect to the PHY */
1340 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
1341 bgmac->phyaddr);
1342 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
1343 PHY_INTERFACE_MODE_MII);
1344 if (IS_ERR(phy_dev)) {
1345 bgmac_err(bgmac, "PHY connecton failed\n");
1346 err = PTR_ERR(phy_dev);
1347 goto err_unregister_bus;
1348 }
1349 bgmac->phy_dev = phy_dev;
1350
11e5e76e
RM		 1351 return err;
1352
5824d2d1
RM		 1353err_unregister_bus:
1354 mdiobus_unregister(mii_bus);
11e5e76e
RM		 1355err_free_irq:
1356 kfree(mii_bus->irq);
1357err_free_bus:
1358 mdiobus_free(mii_bus);
1359 return err;
1360}
1361
1362static void bgmac_mii_unregister(struct bgmac *bgmac)
1363{
1364 struct mii_bus *mii_bus = bgmac->mii_bus;
1365
1366 mdiobus_unregister(mii_bus);
1367 kfree(mii_bus->irq);
1368 mdiobus_free(mii_bus);
1369}
1370
dd4544f0
RM		 1371/**************************************************
1372 * BCMA bus ops
1373 **************************************************/
1374
1375/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1376static int bgmac_probe(struct bcma_device *core)
1377{
1378 struct net_device *net_dev;
1379 struct bgmac *bgmac;
1380 struct ssb_sprom *sprom = &core->bus->sprom;
1381 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
1382 int err;
1383
1384 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
1385 if (core->core_unit > 1) {
1386 pr_err("Unsupported core_unit %d\n", core->core_unit);
1387 return -ENOTSUPP;
1388 }
1389
d166f218
RM		 1390 if (!is_valid_ether_addr(mac)) {
1391 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1392 eth_random_addr(mac);
1393 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1394 }
1395
dd4544f0
RM		 1396 /* Allocation and references */
1397 net_dev = alloc_etherdev(sizeof(*bgmac));
1398 if (!net_dev)
1399 return -ENOMEM;
1400 net_dev->netdev_ops = &bgmac_netdev_ops;
1401 net_dev->irq = core->irq;
1402 SET_ETHTOOL_OPS(net_dev, &bgmac_ethtool_ops);
1403 bgmac = netdev_priv(net_dev);
1404 bgmac->net_dev = net_dev;
1405 bgmac->core = core;
1406 bcma_set_drvdata(core, bgmac);
1407
1408 /* Defaults */
dd4544f0
RM		 1409 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1410
1411 /* On BCM4706 we need common core to access PHY */
1412 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1413 !core->bus->drv_gmac_cmn.core) {
1414 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1415 err = -ENODEV;
1416 goto err_netdev_free;
1417 }
1418 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1419
1420 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
1421 sprom->et0phyaddr;
1422 bgmac->phyaddr &= BGMAC_PHY_MASK;
1423 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1424 bgmac_err(bgmac, "No PHY found\n");
1425 err = -ENODEV;
1426 goto err_netdev_free;
1427 }
1428 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1429 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1430
1431 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1432 bgmac_err(bgmac, "PCI setup not implemented\n");
1433 err = -ENOTSUPP;
1434 goto err_netdev_free;
1435 }
1436
1437 bgmac_chip_reset(bgmac);
1438
1439 err = bgmac_dma_alloc(bgmac);
1440 if (err) {
1441 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1442 goto err_netdev_free;
1443 }
1444
1445 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
edb15d83 1446 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
dd4544f0
RM		 1447 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1448
1449 /* TODO: reset the external phy. Specs are needed */
1450 bgmac_phy_reset(bgmac);
1451
1452 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1453 BGMAC_BFL_ENETROBO);
1454 if (bgmac->has_robosw)
1455 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1456
1457 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1458 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1459
11e5e76e
RM		 1460 err = bgmac_mii_register(bgmac);
1461 if (err) {
1462 bgmac_err(bgmac, "Cannot register MDIO\n");
1463 err = -ENOTSUPP;
1464 goto err_dma_free;
1465 }
1466
dd4544f0
RM		 1467 err = register_netdev(bgmac->net_dev);
1468 if (err) {
1469 bgmac_err(bgmac, "Cannot register net device\n");
1470 err = -ENOTSUPP;
11e5e76e 1471 goto err_mii_unregister;
dd4544f0
RM		 1472 }
1473
1474 netif_carrier_off(net_dev);
1475
1476 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1477
1478 return 0;
1479
11e5e76e
RM		 1480err_mii_unregister:
1481 bgmac_mii_unregister(bgmac);
dd4544f0
RM		 1482err_dma_free:
1483 bgmac_dma_free(bgmac);
1484
1485err_netdev_free:
1486 bcma_set_drvdata(core, NULL);
1487 free_netdev(net_dev);
1488
1489 return err;
1490}
1491
1492static void bgmac_remove(struct bcma_device *core)
1493{
1494 struct bgmac *bgmac = bcma_get_drvdata(core);
1495
1496 netif_napi_del(&bgmac->napi);
1497 unregister_netdev(bgmac->net_dev);
11e5e76e 1498 bgmac_mii_unregister(bgmac);
dd4544f0
RM		 1499 bgmac_dma_free(bgmac);
1500 bcma_set_drvdata(core, NULL);
1501 free_netdev(bgmac->net_dev);
1502}
1503
1504static struct bcma_driver bgmac_bcma_driver = {
1505 .name = KBUILD_MODNAME,
1506 .id_table = bgmac_bcma_tbl,
1507 .probe = bgmac_probe,
1508 .remove = bgmac_remove,
1509};
1510
1511static int __init bgmac_init(void)
1512{
1513 int err;
1514
1515 err = bcma_driver_register(&bgmac_bcma_driver);
1516 if (err)
1517 return err;
1518 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1519
1520 return 0;
1521}
1522
1523static void __exit bgmac_exit(void)
1524{
1525 bcma_driver_unregister(&bgmac_bcma_driver);
1526}
1527
1528module_init(bgmac_init)
1529module_exit(bgmac_exit)
1530
1531MODULE_AUTHOR("Rafał Miłecki");
1532MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)