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bgmac: fix DMA rx corruption
[linux-2.6-block.git] / drivers / net / ethernet / broadcom / bgmac.c
CommitLineData
dd4544f0
RM		 1/*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
9#include "bgmac.h"
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
11e5e76e 16#include <linux/phy.h>
c25b23b8 17#include <linux/phy_fixed.h>
dd4544f0
RM		 18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
edb15d83 20#include <bcm47xx_nvram.h>
dd4544f0
RM		 21
22static const struct bcma_device_id bgmac_bcma_tbl[] = {
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
f7219b52 25 {},
dd4544f0
RM		 26};
27MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
28
29static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
30 u32 value, int timeout)
31{
32 u32 val;
33 int i;
34
35 for (i = 0; i < timeout / 10; i++) {
36 val = bcma_read32(core, reg);
37 if ((val & mask) == value)
38 return true;
39 udelay(10);
40 }
41 pr_err("Timeout waiting for reg 0x%X\n", reg);
42 return false;
43}
44
45/**************************************************
46 * DMA
47 **************************************************/
48
49static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
50{
51 u32 val;
52 int i;
53
54 if (!ring->mmio_base)
55 return;
56
57 /* Suspend DMA TX ring first.
58 * bgmac_wait_value doesn't support waiting for any of few values, so
59 * implement whole loop here.
60 */
61 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
62 BGMAC_DMA_TX_SUSPEND);
63 for (i = 0; i < 10000 / 10; i++) {
64 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
65 val &= BGMAC_DMA_TX_STAT;
66 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
67 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
68 val == BGMAC_DMA_TX_STAT_STOPPED) {
69 i = 0;
70 break;
71 }
72 udelay(10);
73 }
74 if (i)
75 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
76 ring->mmio_base, val);
77
78 /* Remove SUSPEND bit */
79 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
80 if (!bgmac_wait_value(bgmac->core,
81 ring->mmio_base + BGMAC_DMA_TX_STATUS,
82 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
83 10000)) {
84 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
85 ring->mmio_base);
86 udelay(300);
87 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
88 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
89 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
90 ring->mmio_base);
91 }
92}
93
94static void bgmac_dma_tx_enable(struct bgmac *bgmac,
95 struct bgmac_dma_ring *ring)
96{
97 u32 ctl;
98
99 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
56ceecde
HM		 100 if (bgmac->core->id.rev >= 4) {
101 ctl &= ~BGMAC_DMA_TX_BL_MASK;
102 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
103
104 ctl &= ~BGMAC_DMA_TX_MR_MASK;
105 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
106
107 ctl &= ~BGMAC_DMA_TX_PC_MASK;
108 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
109
110 ctl &= ~BGMAC_DMA_TX_PT_MASK;
111 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
112 }
dd4544f0
RM		 113 ctl |= BGMAC_DMA_TX_ENABLE;
114 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
115 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
116}
117
9cde9450
FF		 118static void
119bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
120 int i, int len, u32 ctl0)
121{
122 struct bgmac_slot_info *slot;
123 struct bgmac_dma_desc *dma_desc;
124 u32 ctl1;
125
126 if (i == ring->num_slots - 1)
127 ctl0 |= BGMAC_DESC_CTL0_EOT;
128
129 ctl1 = len & BGMAC_DESC_CTL1_LEN;
130
131 slot = &ring->slots[i];
132 dma_desc = &ring->cpu_base[i];
133 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
134 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
135 dma_desc->ctl0 = cpu_to_le32(ctl0);
136 dma_desc->ctl1 = cpu_to_le32(ctl1);
137}
138
dd4544f0
RM		 139static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
140 struct bgmac_dma_ring *ring,
141 struct sk_buff *skb)
142{
143 struct device *dma_dev = bgmac->core->dma_dev;
144 struct net_device *net_dev = bgmac->net_dev;
b38c83dd
FF		 145 int index = ring->end % BGMAC_TX_RING_SLOTS;
146 struct bgmac_slot_info *slot = &ring->slots[index];
9cde9450
FF		 147 int nr_frags;
148 u32 flags;
9cde9450 149 int i;
dd4544f0
RM		 150
151 if (skb->len > BGMAC_DESC_CTL1_LEN) {
152 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
9cde9450 153 goto err_drop;
dd4544f0
RM		 154 }
155
9cde9450
FF		 156 if (skb->ip_summed == CHECKSUM_PARTIAL)
157 skb_checksum_help(skb);
158
159 nr_frags = skb_shinfo(skb)->nr_frags;
160
b38c83dd
FF		 161 /* ring->end - ring->start will return the number of valid slots,
162 * even when ring->end overflows
163 */
164 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
dd4544f0
RM		 165 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
166 netif_stop_queue(net_dev);
167 return NETDEV_TX_BUSY;
168 }
169
9cde9450 170 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
dd4544f0 171 DMA_TO_DEVICE);
9cde9450
FF		 172 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
173 goto err_dma_head;
dd4544f0 174
9cde9450
FF		 175 flags = BGMAC_DESC_CTL0_SOF;
176 if (!nr_frags)
177 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
dd4544f0 178
9cde9450
FF		 179 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
180 flags = 0;
181
182 for (i = 0; i < nr_frags; i++) {
183 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
184 int len = skb_frag_size(frag);
185
186 index = (index + 1) % BGMAC_TX_RING_SLOTS;
187 slot = &ring->slots[index];
188 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
189 len, DMA_TO_DEVICE);
190 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
191 goto err_dma;
192
193 if (i == nr_frags - 1)
194 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
195
196 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
197 }
198
199 slot->skb = skb;
b38c83dd 200 ring->end += nr_frags + 1;
49a467b4
HM		 201 netdev_sent_queue(net_dev, skb->len);
202
dd4544f0
RM		 203 wmb();
204
205 /* Increase ring->end to point empty slot. We tell hardware the first
206 * slot it should *not* read.
207 */
dd4544f0 208 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
9900303e 209 ring->index_base +
b38c83dd
FF		 210 (ring->end % BGMAC_TX_RING_SLOTS) *
211 sizeof(struct bgmac_dma_desc));
dd4544f0 212
b38c83dd 213 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
dd4544f0
RM		 214 netif_stop_queue(net_dev);
215
216 return NETDEV_TX_OK;
217
9cde9450
FF		 218err_dma:
219 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
220 DMA_TO_DEVICE);
221
222 while (i > 0) {
223 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
224 struct bgmac_slot_info *slot = &ring->slots[index];
225 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
226 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
227
228 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
229 }
230
231err_dma_head:
232 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
233 ring->mmio_base);
234
235err_drop:
dd4544f0
RM		 236 dev_kfree_skb(skb);
237 return NETDEV_TX_OK;
238}
239
240/* Free transmitted packets */
241static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
242{
243 struct device *dma_dev = bgmac->core->dma_dev;
244 int empty_slot;
245 bool freed = false;
49a467b4 246 unsigned bytes_compl = 0, pkts_compl = 0;
dd4544f0
RM		 247
248 /* The last slot that hardware didn't consume yet */
249 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
250 empty_slot &= BGMAC_DMA_TX_STATDPTR;
9900303e
RM		 251 empty_slot -= ring->index_base;
252 empty_slot &= BGMAC_DMA_TX_STATDPTR;
dd4544f0
RM		 253 empty_slot /= sizeof(struct bgmac_dma_desc);
254
b38c83dd
FF		 255 while (ring->start != ring->end) {
256 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
257 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
258 u32 ctl1;
259 int len;
dd4544f0 260
b38c83dd
FF		 261 if (slot_idx == empty_slot)
262 break;
9cde9450 263
b38c83dd
FF		 264 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
265 len = ctl1 & BGMAC_DESC_CTL1_LEN;
9cde9450 266 if (ctl1 & BGMAC_DESC_CTL0_SOF)
dd4544f0 267 /* Unmap no longer used buffer */
9cde9450
FF		 268 dma_unmap_single(dma_dev, slot->dma_addr, len,
269 DMA_TO_DEVICE);
270 else
271 dma_unmap_page(dma_dev, slot->dma_addr, len,
272 DMA_TO_DEVICE);
dd4544f0 273
9cde9450 274 if (slot->skb) {
49a467b4
HM		 275 bytes_compl += slot->skb->len;
276 pkts_compl++;
277
dd4544f0
RM		 278 /* Free memory! :) */
279 dev_kfree_skb(slot->skb);
280 slot->skb = NULL;
dd4544f0
RM		 281 }
282
9cde9450 283 slot->dma_addr = 0;
b38c83dd 284 ring->start++;
dd4544f0
RM		 285 freed = true;
286 }
287
9cde9450
FF		 288 if (!pkts_compl)
289 return;
290
49a467b4
HM		 291 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
292
9cde9450 293 if (netif_queue_stopped(bgmac->net_dev))
dd4544f0
RM		 294 netif_wake_queue(bgmac->net_dev);
295}
296
297static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
298{
299 if (!ring->mmio_base)
300 return;
301
302 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
303 if (!bgmac_wait_value(bgmac->core,
304 ring->mmio_base + BGMAC_DMA_RX_STATUS,
305 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
306 10000))
307 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
308 ring->mmio_base);
309}
310
311static void bgmac_dma_rx_enable(struct bgmac *bgmac,
312 struct bgmac_dma_ring *ring)
313{
314 u32 ctl;
315
316 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
56ceecde
HM		 317 if (bgmac->core->id.rev >= 4) {
318 ctl &= ~BGMAC_DMA_RX_BL_MASK;
319 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
320
321 ctl &= ~BGMAC_DMA_RX_PC_MASK;
322 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
323
324 ctl &= ~BGMAC_DMA_RX_PT_MASK;
325 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
326 }
dd4544f0
RM		 327 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
328 ctl |= BGMAC_DMA_RX_ENABLE;
329 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
330 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
331 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
332 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
333}
334
335static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
336 struct bgmac_slot_info *slot)
337{
338 struct device *dma_dev = bgmac->core->dma_dev;
b757a62e 339 dma_addr_t dma_addr;
dd4544f0 340 struct bgmac_rx_header *rx;
45c9b3c0 341 void *buf;
dd4544f0
RM		 342
343 /* Alloc skb */
45c9b3c0
FF		 344 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
345 if (!buf)
dd4544f0 346 return -ENOMEM;
dd4544f0
RM		 347
348 /* Poison - if everything goes fine, hardware will overwrite it */
4b62dce4 349 rx = buf + BGMAC_RX_BUF_OFFSET;
dd4544f0
RM		 350 rx->len = cpu_to_le16(0xdead);
351 rx->flags = cpu_to_le16(0xbeef);
352
353 /* Map skb for the DMA */
4b62dce4
FF		 354 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
355 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
b757a62e 356 if (dma_mapping_error(dma_dev, dma_addr)) {
dd4544f0 357 bgmac_err(bgmac, "DMA mapping error\n");
45c9b3c0 358 put_page(virt_to_head_page(buf));
dd4544f0
RM		 359 return -ENOMEM;
360 }
b757a62e
NH		 361
362 /* Update the slot */
45c9b3c0 363 slot->buf = buf;
b757a62e
NH		 364 slot->dma_addr = dma_addr;
365
dd4544f0
RM		 366 return 0;
367}
368
4668ae1f
FF		 369static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
370 struct bgmac_dma_ring *ring)
371{
372 dma_wmb();
373
374 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
375 ring->index_base +
376 ring->end * sizeof(struct bgmac_dma_desc));
377}
378
d549c76b
RM		 379static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
380 struct bgmac_dma_ring *ring, int desc_idx)
381{
382 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
383 u32 ctl0 = 0, ctl1 = 0;
384
385 if (desc_idx == ring->num_slots - 1)
386 ctl0 |= BGMAC_DESC_CTL0_EOT;
387 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
388 /* Is there any BGMAC device that requires extension? */
389 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
390 * B43_DMA64_DCTL1_ADDREXT_MASK;
391 */
392
393 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
394 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
395 dma_desc->ctl0 = cpu_to_le32(ctl0);
396 dma_desc->ctl1 = cpu_to_le32(ctl1);
4668ae1f
FF		 397
398 ring->end = desc_idx;
d549c76b
RM		 399}
400
56faacd0
FF		 401static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
402 struct bgmac_slot_info *slot)
403{
404 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
405
406 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
407 DMA_FROM_DEVICE);
408 rx->len = cpu_to_le16(0xdead);
409 rx->flags = cpu_to_le16(0xbeef);
410 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
411 DMA_FROM_DEVICE);
412}
413
dd4544f0
RM		 414static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
415 int weight)
416{
417 u32 end_slot;
418 int handled = 0;
419
420 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
421 end_slot &= BGMAC_DMA_RX_STATDPTR;
9900303e
RM		 422 end_slot -= ring->index_base;
423 end_slot &= BGMAC_DMA_RX_STATDPTR;
dd4544f0
RM		 424 end_slot /= sizeof(struct bgmac_dma_desc);
425
4668ae1f 426 while (ring->start != end_slot) {
dd4544f0
RM		 427 struct device *dma_dev = bgmac->core->dma_dev;
428 struct bgmac_slot_info *slot = &ring->slots[ring->start];
4b62dce4 429 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
45c9b3c0
FF		 430 struct sk_buff *skb;
431 void *buf = slot->buf;
56faacd0 432 dma_addr_t dma_addr = slot->dma_addr;
dd4544f0
RM		 433 u16 len, flags;
434
56faacd0
FF		 435 do {
436 /* Prepare new skb as replacement */
437 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
438 bgmac_dma_rx_poison_buf(dma_dev, slot);
439 break;
440 }
dd4544f0 441
56faacd0
FF		 442 /* Unmap buffer to make it accessible to the CPU */
443 dma_unmap_single(dma_dev, dma_addr,
444 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
dd4544f0 445
56faacd0
FF		 446 /* Get info from the header */
447 len = le16_to_cpu(rx->len);
448 flags = le16_to_cpu(rx->flags);
92b9ccd3
RM		 449
450 /* Check for poison and drop or pass the packet */
451 if (len == 0xdead && flags == 0xbeef) {
452 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
453 ring->start);
56faacd0 454 put_page(virt_to_head_page(buf));
92b9ccd3
RM		 455 break;
456 }
457
6a6c7084
FF		 458 if (len > BGMAC_RX_ALLOC_SIZE) {
459 bgmac_err(bgmac, "Found oversized packet at slot %d, DMA issue!\n",
460 ring->start);
461 put_page(virt_to_head_page(buf));
462 break;
463 }
464
02e71127
HM		 465 /* Omit CRC. */
466 len -= ETH_FCS_LEN;
467
45c9b3c0 468 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
4b62dce4
FF		 469 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
470 BGMAC_RX_BUF_OFFSET + len);
471 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
472 BGMAC_RX_BUF_OFFSET);
dd4544f0 473
92b9ccd3
RM		 474 skb_checksum_none_assert(skb);
475 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
45c9b3c0 476 napi_gro_receive(&bgmac->napi, skb);
92b9ccd3
RM		 477 handled++;
478 } while (0);
dd4544f0 479
56faacd0
FF		 480 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
481
dd4544f0
RM		 482 if (++ring->start >= BGMAC_RX_RING_SLOTS)
483 ring->start = 0;
484
485 if (handled >= weight) /* Should never be greater */
486 break;
487 }
488
4668ae1f
FF		 489 bgmac_dma_rx_update_index(bgmac, ring);
490
dd4544f0
RM		 491 return handled;
492}
493
494/* Does ring support unaligned addressing? */
495static bool bgmac_dma_unaligned(struct bgmac *bgmac,
496 struct bgmac_dma_ring *ring,
497 enum bgmac_dma_ring_type ring_type)
498{
499 switch (ring_type) {
500 case BGMAC_DMA_RING_TX:
501 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
502 0xff0);
503 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
504 return true;
505 break;
506 case BGMAC_DMA_RING_RX:
507 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
508 0xff0);
509 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
510 return true;
511 break;
512 }
513 return false;
514}
515
45c9b3c0
FF		 516static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
517 struct bgmac_dma_ring *ring)
dd4544f0
RM		 518{
519 struct device *dma_dev = bgmac->core->dma_dev;
9cde9450 520 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
dd4544f0 521 struct bgmac_slot_info *slot;
dd4544f0
RM		 522 int i;
523
524 for (i = 0; i < ring->num_slots; i++) {
9cde9450
FF		 525 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
526
dd4544f0 527 slot = &ring->slots[i];
9cde9450
FF		 528 dev_kfree_skb(slot->skb);
529
530 if (!slot->dma_addr)
531 continue;
532
533 if (slot->skb)
534 dma_unmap_single(dma_dev, slot->dma_addr,
535 len, DMA_TO_DEVICE);
536 else
537 dma_unmap_page(dma_dev, slot->dma_addr,
538 len, DMA_TO_DEVICE);
dd4544f0 539 }
45c9b3c0
FF		 540}
541
542static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
543 struct bgmac_dma_ring *ring)
544{
545 struct device *dma_dev = bgmac->core->dma_dev;
546 struct bgmac_slot_info *slot;
547 int i;
548
549 for (i = 0; i < ring->num_slots; i++) {
550 slot = &ring->slots[i];
56faacd0 551 if (!slot->dma_addr)
45c9b3c0 552 continue;
dd4544f0 553
56faacd0
FF		 554 dma_unmap_single(dma_dev, slot->dma_addr,
555 BGMAC_RX_BUF_SIZE,
556 DMA_FROM_DEVICE);
45c9b3c0 557 put_page(virt_to_head_page(slot->buf));
56faacd0 558 slot->dma_addr = 0;
dd4544f0
RM		 559 }
560}
561
45c9b3c0
FF		 562static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
563 struct bgmac_dma_ring *ring)
564{
565 struct device *dma_dev = bgmac->core->dma_dev;
566 int size;
567
568 if (!ring->cpu_base)
569 return;
570
571 /* Free ring of descriptors */
572 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
573 dma_free_coherent(dma_dev, size, ring->cpu_base,
574 ring->dma_base);
575}
576
74b6f291 577static void bgmac_dma_cleanup(struct bgmac *bgmac)
dd4544f0
RM		 578{
579 int i;
580
74b6f291 581 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
45c9b3c0 582 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
74b6f291
FF		 583
584 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
45c9b3c0 585 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
74b6f291
FF		 586}
587
588static void bgmac_dma_free(struct bgmac *bgmac)
589{
590 int i;
591
592 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
593 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]);
594
595 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
45c9b3c0 596 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]);
dd4544f0
RM		 597}
598
599static int bgmac_dma_alloc(struct bgmac *bgmac)
600{
601 struct device *dma_dev = bgmac->core->dma_dev;
602 struct bgmac_dma_ring *ring;
603 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
604 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
605 int size; /* ring size: different for Tx and Rx */
606 int err;
607 int i;
608
609 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
610 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
611
612 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
613 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
614 return -ENOTSUPP;
615 }
616
617 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
618 ring = &bgmac->tx_ring[i];
619 ring->num_slots = BGMAC_TX_RING_SLOTS;
620 ring->mmio_base = ring_base[i];
dd4544f0
RM		 621
622 /* Alloc ring of descriptors */
623 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
624 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
625 &ring->dma_base,
626 GFP_KERNEL);
627 if (!ring->cpu_base) {
628 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
629 ring->mmio_base);
630 goto err_dma_free;
631 }
dd4544f0 632
9900303e
RM		 633 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
634 BGMAC_DMA_RING_TX);
635 if (ring->unaligned)
636 ring->index_base = lower_32_bits(ring->dma_base);
637 else
638 ring->index_base = 0;
639
dd4544f0
RM		 640 /* No need to alloc TX slots yet */
641 }
642
643 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
644 ring = &bgmac->rx_ring[i];
645 ring->num_slots = BGMAC_RX_RING_SLOTS;
646 ring->mmio_base = ring_base[i];
dd4544f0
RM		 647
648 /* Alloc ring of descriptors */
649 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
650 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
651 &ring->dma_base,
652 GFP_KERNEL);
653 if (!ring->cpu_base) {
654 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
655 ring->mmio_base);
656 err = -ENOMEM;
657 goto err_dma_free;
658 }
dd4544f0 659
9900303e
RM		 660 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
661 BGMAC_DMA_RING_RX);
662 if (ring->unaligned)
663 ring->index_base = lower_32_bits(ring->dma_base);
664 else
665 ring->index_base = 0;
dd4544f0
RM		 666 }
667
668 return 0;
669
670err_dma_free:
671 bgmac_dma_free(bgmac);
672 return -ENOMEM;
673}
674
74b6f291 675static int bgmac_dma_init(struct bgmac *bgmac)
dd4544f0
RM		 676{
677 struct bgmac_dma_ring *ring;
74b6f291 678 int i, err;
dd4544f0
RM		 679
680 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
681 ring = &bgmac->tx_ring[i];
682
9900303e
RM		 683 if (!ring->unaligned)
684 bgmac_dma_tx_enable(bgmac, ring);
dd4544f0
RM		 685 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
686 lower_32_bits(ring->dma_base));
687 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
688 upper_32_bits(ring->dma_base));
9900303e
RM		 689 if (ring->unaligned)
690 bgmac_dma_tx_enable(bgmac, ring);
dd4544f0
RM		 691
692 ring->start = 0;
693 ring->end = 0; /* Points the slot that should *not* be read */
694 }
695
696 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
70a737b7
RM		 697 int j;
698
dd4544f0
RM		 699 ring = &bgmac->rx_ring[i];
700
9900303e
RM		 701 if (!ring->unaligned)
702 bgmac_dma_rx_enable(bgmac, ring);
dd4544f0
RM		 703 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
704 lower_32_bits(ring->dma_base));
705 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
706 upper_32_bits(ring->dma_base));
9900303e
RM		 707 if (ring->unaligned)
708 bgmac_dma_rx_enable(bgmac, ring);
dd4544f0 709
4668ae1f
FF		 710 ring->start = 0;
711 ring->end = 0;
74b6f291
FF		 712 for (j = 0; j < ring->num_slots; j++) {
713 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
714 if (err)
715 goto error;
716
d549c76b 717 bgmac_dma_rx_setup_desc(bgmac, ring, j);
74b6f291 718 }
dd4544f0 719
4668ae1f 720 bgmac_dma_rx_update_index(bgmac, ring);
dd4544f0 721 }
74b6f291
FF		 722
723 return 0;
724
725error:
726 bgmac_dma_cleanup(bgmac);
727 return err;
dd4544f0
RM		 728}
729
730/**************************************************
731 * PHY ops
732 **************************************************/
733
217a55a3 734static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
dd4544f0
RM		 735{
736 struct bcma_device *core;
737 u16 phy_access_addr;
738 u16 phy_ctl_addr;
739 u32 tmp;
740
741 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
742 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
743 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
744 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
745 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
746 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
747 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
748 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
749 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
750 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
751 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
752
753 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
754 core = bgmac->core->bus->drv_gmac_cmn.core;
755 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
756 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
757 } else {
758 core = bgmac->core;
759 phy_access_addr = BGMAC_PHY_ACCESS;
760 phy_ctl_addr = BGMAC_PHY_CNTL;
761 }
762
763 tmp = bcma_read32(core, phy_ctl_addr);
764 tmp &= ~BGMAC_PC_EPA_MASK;
765 tmp |= phyaddr;
766 bcma_write32(core, phy_ctl_addr, tmp);
767
768 tmp = BGMAC_PA_START;
769 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
770 tmp |= reg << BGMAC_PA_REG_SHIFT;
771 bcma_write32(core, phy_access_addr, tmp);
772
773 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
774 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
775 phyaddr, reg);
776 return 0xffff;
777 }
778
779 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
780}
781
782/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
217a55a3 783static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
dd4544f0
RM		 784{
785 struct bcma_device *core;
786 u16 phy_access_addr;
787 u16 phy_ctl_addr;
788 u32 tmp;
789
790 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
791 core = bgmac->core->bus->drv_gmac_cmn.core;
792 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
793 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
794 } else {
795 core = bgmac->core;
796 phy_access_addr = BGMAC_PHY_ACCESS;
797 phy_ctl_addr = BGMAC_PHY_CNTL;
798 }
799
800 tmp = bcma_read32(core, phy_ctl_addr);
801 tmp &= ~BGMAC_PC_EPA_MASK;
802 tmp |= phyaddr;
803 bcma_write32(core, phy_ctl_addr, tmp);
804
805 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
806 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
807 bgmac_warn(bgmac, "Error setting MDIO int\n");
808
809 tmp = BGMAC_PA_START;
810 tmp |= BGMAC_PA_WRITE;
811 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
812 tmp |= reg << BGMAC_PA_REG_SHIFT;
813 tmp |= value;
814 bcma_write32(core, phy_access_addr, tmp);
815
217a55a3 816 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
dd4544f0
RM		 817 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
818 phyaddr, reg);
217a55a3
RM		 819 return -ETIMEDOUT;
820 }
821
822 return 0;
dd4544f0
RM		 823}
824
dd4544f0
RM		 825/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
826static void bgmac_phy_init(struct bgmac *bgmac)
827{
828 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
829 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
830 u8 i;
831
832 if (ci->id == BCMA_CHIP_ID_BCM5356) {
833 for (i = 0; i < 5; i++) {
834 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
835 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
836 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
837 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
838 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
839 }
840 }
841 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
842 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
843 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
844 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
845 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
846 for (i = 0; i < 5; i++) {
847 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
848 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
849 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
850 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
851 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
852 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
853 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
854 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
855 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
856 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
857 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
858 }
859 }
860}
861
862/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
863static void bgmac_phy_reset(struct bgmac *bgmac)
864{
865 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
866 return;
867
5322dbf0 868 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
dd4544f0 869 udelay(100);
5322dbf0 870 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
dd4544f0
RM		 871 bgmac_err(bgmac, "PHY reset failed\n");
872 bgmac_phy_init(bgmac);
873}
874
875/**************************************************
876 * Chip ops
877 **************************************************/
878
879/* TODO: can we just drop @force? Can we don't reset MAC at all if there is
880 * nothing to change? Try if after stabilizng driver.
881 */
882static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
883 bool force)
884{
885 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
886 u32 new_val = (cmdcfg & mask) | set;
887
48e07fbe 888 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
dd4544f0
RM		 889 udelay(2);
890
891 if (new_val != cmdcfg || force)
892 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
893
48e07fbe 894 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
dd4544f0
RM		 895 udelay(2);
896}
897
4e209001
HM		 898static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
899{
900 u32 tmp;
901
902 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
903 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
904 tmp = (addr[4] << 8) | addr[5];
905 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
906}
907
c6edfe10
HM		 908static void bgmac_set_rx_mode(struct net_device *net_dev)
909{
910 struct bgmac *bgmac = netdev_priv(net_dev);
911
912 if (net_dev->flags & IFF_PROMISC)
e9ba1039 913 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
c6edfe10 914 else
e9ba1039 915 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
c6edfe10
HM		 916}
917
dd4544f0
RM		 918#if 0 /* We don't use that regs yet */
919static void bgmac_chip_stats_update(struct bgmac *bgmac)
920{
921 int i;
922
923 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
924 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
925 bgmac->mib_tx_regs[i] =
926 bgmac_read(bgmac,
927 BGMAC_TX_GOOD_OCTETS + (i * 4));
928 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
929 bgmac->mib_rx_regs[i] =
930 bgmac_read(bgmac,
931 BGMAC_RX_GOOD_OCTETS + (i * 4));
932 }
933
934 /* TODO: what else? how to handle BCM4706? Specs are needed */
935}
936#endif
937
938static void bgmac_clear_mib(struct bgmac *bgmac)
939{
940 int i;
941
942 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
943 return;
944
945 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
946 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
947 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
948 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
949 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
950}
951
952/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
5824d2d1 953static void bgmac_mac_speed(struct bgmac *bgmac)
dd4544f0
RM		 954{
955 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
956 u32 set = 0;
957
5824d2d1
RM		 958 switch (bgmac->mac_speed) {
959 case SPEED_10:
dd4544f0 960 set |= BGMAC_CMDCFG_ES_10;
5824d2d1
RM		 961 break;
962 case SPEED_100:
dd4544f0 963 set |= BGMAC_CMDCFG_ES_100;
5824d2d1
RM		 964 break;
965 case SPEED_1000:
dd4544f0 966 set |= BGMAC_CMDCFG_ES_1000;
5824d2d1 967 break;
6df4aff9
HM		 968 case SPEED_2500:
969 set |= BGMAC_CMDCFG_ES_2500;
970 break;
5824d2d1
RM		 971 default:
972 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
973 }
974
975 if (bgmac->mac_duplex == DUPLEX_HALF)
dd4544f0 976 set |= BGMAC_CMDCFG_HD;
5824d2d1 977
dd4544f0
RM		 978 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
979}
980
981static void bgmac_miiconfig(struct bgmac *bgmac)
982{
6df4aff9
HM		 983 struct bcma_device *core = bgmac->core;
984 struct bcma_chipinfo *ci = &core->bus->chipinfo;
985 u8 imode;
986
987 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
988 ci->id == BCMA_CHIP_ID_BCM53018) {
989 bcma_awrite32(core, BCMA_IOCTL,
990 bcma_aread32(core, BCMA_IOCTL) | 0x40 |
991 BGMAC_BCMA_IOCTL_SW_CLKEN);
992 bgmac->mac_speed = SPEED_2500;
5824d2d1
RM		 993 bgmac->mac_duplex = DUPLEX_FULL;
994 bgmac_mac_speed(bgmac);
6df4aff9
HM		 995 } else {
996 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
997 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
998 if (imode == 0 || imode == 1) {
999 bgmac->mac_speed = SPEED_100;
1000 bgmac->mac_duplex = DUPLEX_FULL;
1001 bgmac_mac_speed(bgmac);
1002 }
dd4544f0
RM		 1003 }
1004}
1005
1006/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
1007static void bgmac_chip_reset(struct bgmac *bgmac)
1008{
1009 struct bcma_device *core = bgmac->core;
1010 struct bcma_bus *bus = core->bus;
1011 struct bcma_chipinfo *ci = &bus->chipinfo;
6df4aff9 1012 u32 flags;
dd4544f0
RM		 1013 u32 iost;
1014 int i;
1015
1016 if (bcma_core_is_enabled(core)) {
1017 if (!bgmac->stats_grabbed) {
1018 /* bgmac_chip_stats_update(bgmac); */
1019 bgmac->stats_grabbed = true;
1020 }
1021
1022 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
1023 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
1024
1025 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1026 udelay(1);
1027
1028 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
1029 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
1030
1031 /* TODO: Clear software multicast filter list */
1032 }
1033
1034 iost = bcma_aread32(core, BCMA_IOST);
1a0ab767 1035 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
dd4544f0 1036 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1a0ab767 1037 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
dd4544f0
RM		 1038 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
1039
6df4aff9
HM		 1040 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
1041 if (ci->id != BCMA_CHIP_ID_BCM4707) {
1042 flags = 0;
1043 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
1044 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
1045 if (!bgmac->has_robosw)
1046 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
1047 }
1048 bcma_core_enable(core, flags);
dd4544f0
RM		 1049 }
1050
6df4aff9
HM		 1051 /* Request Misc PLL for corerev > 2 */
1052 if (core->id.rev > 2 &&
1053 ci->id != BCMA_CHIP_ID_BCM4707 &&
1054 ci->id != BCMA_CHIP_ID_BCM53018) {
1a0ab767
RM		 1055 bgmac_set(bgmac, BCMA_CLKCTLST,
1056 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
1057 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
1058 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1059 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
dd4544f0
RM		 1060 1000);
1061 }
1062
1a0ab767
RM		 1063 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1064 ci->id == BCMA_CHIP_ID_BCM4749 ||
dd4544f0
RM		 1065 ci->id == BCMA_CHIP_ID_BCM53572) {
1066 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
1067 u8 et_swtype = 0;
1068 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
6a391e7b 1069 BGMAC_CHIPCTL_1_IF_TYPE_MII;
3647268d 1070 char buf[4];
dd4544f0 1071
3647268d 1072 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
dd4544f0
RM		 1073 if (kstrtou8(buf, 0, &et_swtype))
1074 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
1075 buf);
1076 et_swtype &= 0x0f;
1077 et_swtype <<= 4;
1078 sw_type = et_swtype;
1a0ab767 1079 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
dd4544f0 1080 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
1a0ab767
RM		 1081 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1082 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1083 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
b5a4c2f3
HM		 1084 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
1085 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
dd4544f0
RM		 1086 }
1087 bcma_chipco_chipctl_maskset(cc, 1,
1088 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
1089 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
1090 sw_type);
1091 }
1092
1093 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
1094 bcma_awrite32(core, BCMA_IOCTL,
1095 bcma_aread32(core, BCMA_IOCTL) &
1096 ~BGMAC_BCMA_IOCTL_SW_RESET);
1097
1098 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
1099 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
1100 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
1101 * be keps until taking MAC out of the reset.
1102 */
1103 bgmac_cmdcfg_maskset(bgmac,
1104 ~(BGMAC_CMDCFG_TE |
1105 BGMAC_CMDCFG_RE |
1106 BGMAC_CMDCFG_RPI |
1107 BGMAC_CMDCFG_TAI |
1108 BGMAC_CMDCFG_HD |
1109 BGMAC_CMDCFG_ML |
1110 BGMAC_CMDCFG_CFE |
1111 BGMAC_CMDCFG_RL |
1112 BGMAC_CMDCFG_RED |
1113 BGMAC_CMDCFG_PE |
1114 BGMAC_CMDCFG_TPI |
1115 BGMAC_CMDCFG_PAD_EN |
1116 BGMAC_CMDCFG_PF),
1117 BGMAC_CMDCFG_PROM |
1118 BGMAC_CMDCFG_NLC |
1119 BGMAC_CMDCFG_CFE |
48e07fbe 1120 BGMAC_CMDCFG_SR(core->id.rev),
dd4544f0 1121 false);
d469962f
RM		 1122 bgmac->mac_speed = SPEED_UNKNOWN;
1123 bgmac->mac_duplex = DUPLEX_UNKNOWN;
dd4544f0
RM		 1124
1125 bgmac_clear_mib(bgmac);
1126 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
1127 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
1128 BCMA_GMAC_CMN_PC_MTE);
1129 else
1130 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1131 bgmac_miiconfig(bgmac);
1132 bgmac_phy_init(bgmac);
1133
49a467b4 1134 netdev_reset_queue(bgmac->net_dev);
dd4544f0
RM		 1135}
1136
1137static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1138{
1139 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1140}
1141
1142static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1143{
1144 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
4160815f 1145 bgmac_read(bgmac, BGMAC_INT_MASK);
dd4544f0
RM		 1146}
1147
1148/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1149static void bgmac_enable(struct bgmac *bgmac)
1150{
1151 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1152 u32 cmdcfg;
1153 u32 mode;
1154 u32 rxq_ctl;
1155 u32 fl_ctl;
1156 u16 bp_clk;
1157 u8 mdp;
1158
1159 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1160 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
48e07fbe 1161 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
dd4544f0
RM		 1162 udelay(2);
1163 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1164 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1165
1166 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1167 BGMAC_DS_MM_SHIFT;
1168 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1169 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1170 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1171 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1172 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1173
1174 switch (ci->id) {
1175 case BCMA_CHIP_ID_BCM5357:
1176 case BCMA_CHIP_ID_BCM4749:
1177 case BCMA_CHIP_ID_BCM53572:
1178 case BCMA_CHIP_ID_BCM4716:
1179 case BCMA_CHIP_ID_BCM47162:
1180 fl_ctl = 0x03cb04cb;
1181 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1182 ci->id == BCMA_CHIP_ID_BCM4749 ||
1183 ci->id == BCMA_CHIP_ID_BCM53572)
1184 fl_ctl = 0x2300e1;
1185 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1186 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1187 break;
1188 }
1189
6df4aff9
HM		 1190 if (ci->id != BCMA_CHIP_ID_BCM4707 &&
1191 ci->id != BCMA_CHIP_ID_BCM53018) {
1192 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1193 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1194 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
1195 1000000;
1196 mdp = (bp_clk * 128 / 1000) - 3;
1197 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1198 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1199 }
dd4544f0
RM		 1200}
1201
1202/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
74b6f291 1203static void bgmac_chip_init(struct bgmac *bgmac)
dd4544f0 1204{
dd4544f0
RM		 1205 /* 1 interrupt per received frame */
1206 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1207
1208 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1209 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1210
c6edfe10 1211 bgmac_set_rx_mode(bgmac->net_dev);
dd4544f0 1212
4e209001 1213 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
dd4544f0
RM		 1214
1215 if (bgmac->loopback)
e9ba1039 1216 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
dd4544f0 1217 else
e9ba1039 1218 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
dd4544f0
RM		 1219
1220 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1221
74b6f291 1222 bgmac_chip_intrs_on(bgmac);
dd4544f0
RM		 1223
1224 bgmac_enable(bgmac);
1225}
1226
1227static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1228{
1229 struct bgmac *bgmac = netdev_priv(dev_id);
1230
1231 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1232 int_status &= bgmac->int_mask;
1233
1234 if (!int_status)
1235 return IRQ_NONE;
1236
eb64e292
FF		 1237 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1238 if (int_status)
1239 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status);
dd4544f0
RM		 1240
1241 /* Disable new interrupts until handling existing ones */
1242 bgmac_chip_intrs_off(bgmac);
1243
dd4544f0
RM		 1244 napi_schedule(&bgmac->napi);
1245
1246 return IRQ_HANDLED;
1247}
1248
1249static int bgmac_poll(struct napi_struct *napi, int weight)
1250{
1251 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
dd4544f0
RM		 1252 int handled = 0;
1253
eb64e292
FF		 1254 /* Ack */
1255 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
dd4544f0 1256
eb64e292
FF		 1257 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1258 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
dd4544f0 1259
eb64e292
FF		 1260 /* Poll again if more events arrived in the meantime */
1261 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1262 return handled;
dd4544f0 1263
43f159c6 1264 if (handled < weight) {
dd4544f0 1265 napi_complete(napi);
43f159c6
HM		 1266 bgmac_chip_intrs_on(bgmac);
1267 }
dd4544f0
RM		 1268
1269 return handled;
1270}
1271
1272/**************************************************
1273 * net_device_ops
1274 **************************************************/
1275
1276static int bgmac_open(struct net_device *net_dev)
1277{
1278 struct bgmac *bgmac = netdev_priv(net_dev);
1279 int err = 0;
1280
1281 bgmac_chip_reset(bgmac);
74b6f291
FF		 1282
1283 err = bgmac_dma_init(bgmac);
1284 if (err)
1285 return err;
1286
dd4544f0 1287 /* Specs say about reclaiming rings here, but we do that in DMA init */
74b6f291 1288 bgmac_chip_init(bgmac);
dd4544f0
RM		 1289
1290 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1291 KBUILD_MODNAME, net_dev);
1292 if (err < 0) {
1293 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
74b6f291
FF		 1294 bgmac_dma_cleanup(bgmac);
1295 return err;
dd4544f0
RM		 1296 }
1297 napi_enable(&bgmac->napi);
1298
4e34da4d
RM		 1299 phy_start(bgmac->phy_dev);
1300
dd4544f0 1301 netif_carrier_on(net_dev);
74b6f291 1302 return 0;
dd4544f0
RM		 1303}
1304
1305static int bgmac_stop(struct net_device *net_dev)
1306{
1307 struct bgmac *bgmac = netdev_priv(net_dev);
1308
1309 netif_carrier_off(net_dev);
1310
4e34da4d
RM		 1311 phy_stop(bgmac->phy_dev);
1312
dd4544f0
RM		 1313 napi_disable(&bgmac->napi);
1314 bgmac_chip_intrs_off(bgmac);
1315 free_irq(bgmac->core->irq, net_dev);
1316
1317 bgmac_chip_reset(bgmac);
74b6f291 1318 bgmac_dma_cleanup(bgmac);
dd4544f0
RM		 1319
1320 return 0;
1321}
1322
1323static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1324 struct net_device *net_dev)
1325{
1326 struct bgmac *bgmac = netdev_priv(net_dev);
1327 struct bgmac_dma_ring *ring;
1328
1329 /* No QOS support yet */
1330 ring = &bgmac->tx_ring[0];
1331 return bgmac_dma_tx_add(bgmac, ring, skb);
1332}
1333
4e209001
HM		 1334static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1335{
1336 struct bgmac *bgmac = netdev_priv(net_dev);
1337 int ret;
1338
1339 ret = eth_prepare_mac_addr_change(net_dev, addr);
1340 if (ret < 0)
1341 return ret;
1342 bgmac_write_mac_address(bgmac, (u8 *)addr);
1343 eth_commit_mac_addr_change(net_dev, addr);
1344 return 0;
1345}
1346
dd4544f0
RM		 1347static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1348{
1349 struct bgmac *bgmac = netdev_priv(net_dev);
69c58852
HM		 1350
1351 if (!netif_running(net_dev))
1352 return -EINVAL;
1353
1354 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
dd4544f0
RM		 1355}
1356
1357static const struct net_device_ops bgmac_netdev_ops = {
1358 .ndo_open = bgmac_open,
1359 .ndo_stop = bgmac_stop,
1360 .ndo_start_xmit = bgmac_start_xmit,
c6edfe10 1361 .ndo_set_rx_mode = bgmac_set_rx_mode,
4e209001 1362 .ndo_set_mac_address = bgmac_set_mac_address,
522c5907 1363 .ndo_validate_addr = eth_validate_addr,
dd4544f0
RM		 1364 .ndo_do_ioctl = bgmac_ioctl,
1365};
1366
1367/**************************************************
1368 * ethtool_ops
1369 **************************************************/
1370
1371static int bgmac_get_settings(struct net_device *net_dev,
1372 struct ethtool_cmd *cmd)
1373{
1374 struct bgmac *bgmac = netdev_priv(net_dev);
1375
5824d2d1 1376 return phy_ethtool_gset(bgmac->phy_dev, cmd);
dd4544f0
RM		 1377}
1378
dd4544f0
RM		 1379static int bgmac_set_settings(struct net_device *net_dev,
1380 struct ethtool_cmd *cmd)
1381{
1382 struct bgmac *bgmac = netdev_priv(net_dev);
1383
5824d2d1 1384 return phy_ethtool_sset(bgmac->phy_dev, cmd);
dd4544f0 1385}
dd4544f0
RM		 1386
1387static void bgmac_get_drvinfo(struct net_device *net_dev,
1388 struct ethtool_drvinfo *info)
1389{
1390 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1391 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1392}
1393
1394static const struct ethtool_ops bgmac_ethtool_ops = {
1395 .get_settings = bgmac_get_settings,
5824d2d1 1396 .set_settings = bgmac_set_settings,
dd4544f0
RM		 1397 .get_drvinfo = bgmac_get_drvinfo,
1398};
1399
11e5e76e
RM		 1400/**************************************************
1401 * MII
1402 **************************************************/
1403
1404static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1405{
1406 return bgmac_phy_read(bus->priv, mii_id, regnum);
1407}
1408
1409static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1410 u16 value)
1411{
1412 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1413}
1414
5824d2d1
RM		 1415static void bgmac_adjust_link(struct net_device *net_dev)
1416{
1417 struct bgmac *bgmac = netdev_priv(net_dev);
1418 struct phy_device *phy_dev = bgmac->phy_dev;
1419 bool update = false;
1420
1421 if (phy_dev->link) {
1422 if (phy_dev->speed != bgmac->mac_speed) {
1423 bgmac->mac_speed = phy_dev->speed;
1424 update = true;
1425 }
1426
1427 if (phy_dev->duplex != bgmac->mac_duplex) {
1428 bgmac->mac_duplex = phy_dev->duplex;
1429 update = true;
1430 }
1431 }
1432
1433 if (update) {
1434 bgmac_mac_speed(bgmac);
1435 phy_print_status(phy_dev);
1436 }
1437}
1438
c25b23b8
RM		 1439static int bgmac_fixed_phy_register(struct bgmac *bgmac)
1440{
1441 struct fixed_phy_status fphy_status = {
1442 .link = 1,
1443 .speed = SPEED_1000,
1444 .duplex = DUPLEX_FULL,
1445 };
1446 struct phy_device *phy_dev;
1447 int err;
1448
1449 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
1450 if (!phy_dev || IS_ERR(phy_dev)) {
1451 bgmac_err(bgmac, "Failed to register fixed PHY device\n");
1452 return -ENODEV;
1453 }
1454
1455 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1456 PHY_INTERFACE_MODE_MII);
1457 if (err) {
1458 bgmac_err(bgmac, "Connecting PHY failed\n");
1459 return err;
1460 }
1461
1462 bgmac->phy_dev = phy_dev;
1463
1464 return err;
1465}
1466
11e5e76e
RM		 1467static int bgmac_mii_register(struct bgmac *bgmac)
1468{
c25b23b8 1469 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
11e5e76e 1470 struct mii_bus *mii_bus;
5824d2d1
RM		 1471 struct phy_device *phy_dev;
1472 char bus_id[MII_BUS_ID_SIZE + 3];
11e5e76e
RM		 1473 int i, err = 0;
1474
c25b23b8
RM		 1475 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
1476 ci->id == BCMA_CHIP_ID_BCM53018)
1477 return bgmac_fixed_phy_register(bgmac);
1478
11e5e76e
RM		 1479 mii_bus = mdiobus_alloc();
1480 if (!mii_bus)
1481 return -ENOMEM;
1482
1483 mii_bus->name = "bgmac mii bus";
1484 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1485 bgmac->core->core_unit);
1486 mii_bus->priv = bgmac;
1487 mii_bus->read = bgmac_mii_read;
1488 mii_bus->write = bgmac_mii_write;
1489 mii_bus->parent = &bgmac->core->dev;
1490 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1491
1492 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1493 if (!mii_bus->irq) {
1494 err = -ENOMEM;
1495 goto err_free_bus;
1496 }
1497 for (i = 0; i < PHY_MAX_ADDR; i++)
1498 mii_bus->irq[i] = PHY_POLL;
1499
1500 err = mdiobus_register(mii_bus);
1501 if (err) {
1502 bgmac_err(bgmac, "Registration of mii bus failed\n");
1503 goto err_free_irq;
1504 }
1505
1506 bgmac->mii_bus = mii_bus;
1507
5824d2d1
RM		 1508 /* Connect to the PHY */
1509 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
1510 bgmac->phyaddr);
1511 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
1512 PHY_INTERFACE_MODE_MII);
1513 if (IS_ERR(phy_dev)) {
1514 bgmac_err(bgmac, "PHY connecton failed\n");
1515 err = PTR_ERR(phy_dev);
1516 goto err_unregister_bus;
1517 }
1518 bgmac->phy_dev = phy_dev;
1519
11e5e76e
RM		 1520 return err;
1521
5824d2d1
RM		 1522err_unregister_bus:
1523 mdiobus_unregister(mii_bus);
11e5e76e
RM		 1524err_free_irq:
1525 kfree(mii_bus->irq);
1526err_free_bus:
1527 mdiobus_free(mii_bus);
1528 return err;
1529}
1530
1531static void bgmac_mii_unregister(struct bgmac *bgmac)
1532{
1533 struct mii_bus *mii_bus = bgmac->mii_bus;
1534
1535 mdiobus_unregister(mii_bus);
1536 kfree(mii_bus->irq);
1537 mdiobus_free(mii_bus);
1538}
1539
dd4544f0
RM		 1540/**************************************************
1541 * BCMA bus ops
1542 **************************************************/
1543
1544/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1545static int bgmac_probe(struct bcma_device *core)
1546{
21697336 1547 struct bcma_chipinfo *ci = &core->bus->chipinfo;
dd4544f0
RM		 1548 struct net_device *net_dev;
1549 struct bgmac *bgmac;
1550 struct ssb_sprom *sprom = &core->bus->sprom;
1551 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
1552 int err;
1553
1554 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
1555 if (core->core_unit > 1) {
1556 pr_err("Unsupported core_unit %d\n", core->core_unit);
1557 return -ENOTSUPP;
1558 }
1559
d166f218
RM		 1560 if (!is_valid_ether_addr(mac)) {
1561 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1562 eth_random_addr(mac);
1563 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1564 }
1565
dd4544f0
RM		 1566 /* Allocation and references */
1567 net_dev = alloc_etherdev(sizeof(*bgmac));
1568 if (!net_dev)
1569 return -ENOMEM;
1570 net_dev->netdev_ops = &bgmac_netdev_ops;
1571 net_dev->irq = core->irq;
7ad24ea4 1572 net_dev->ethtool_ops = &bgmac_ethtool_ops;
dd4544f0
RM		 1573 bgmac = netdev_priv(net_dev);
1574 bgmac->net_dev = net_dev;
1575 bgmac->core = core;
1576 bcma_set_drvdata(core, bgmac);
1577
1578 /* Defaults */
dd4544f0
RM		 1579 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1580
1581 /* On BCM4706 we need common core to access PHY */
1582 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1583 !core->bus->drv_gmac_cmn.core) {
1584 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1585 err = -ENODEV;
1586 goto err_netdev_free;
1587 }
1588 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1589
1590 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
1591 sprom->et0phyaddr;
1592 bgmac->phyaddr &= BGMAC_PHY_MASK;
1593 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1594 bgmac_err(bgmac, "No PHY found\n");
1595 err = -ENODEV;
1596 goto err_netdev_free;
1597 }
1598 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1599 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1600
1601 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1602 bgmac_err(bgmac, "PCI setup not implemented\n");
1603 err = -ENOTSUPP;
1604 goto err_netdev_free;
1605 }
1606
1607 bgmac_chip_reset(bgmac);
1608
622a521f 1609 /* For Northstar, we have to take all GMAC core out of reset */
21697336
RM		 1610 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
1611 ci->id == BCMA_CHIP_ID_BCM53018) {
622a521f
HM		 1612 struct bcma_device *ns_core;
1613 int ns_gmac;
1614
1615 /* Northstar has 4 GMAC cores */
1616 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
0e595934 1617 /* As Northstar requirement, we have to reset all GMACs
622a521f
HM		 1618 * before accessing one. bgmac_chip_reset() call
1619 * bcma_core_enable() for this core. Then the other
0e595934 1620 * three GMACs didn't reset. We do it here.
622a521f
HM		 1621 */
1622 ns_core = bcma_find_core_unit(core->bus,
1623 BCMA_CORE_MAC_GBIT,
1624 ns_gmac);
1625 if (ns_core && !bcma_core_is_enabled(ns_core))
1626 bcma_core_enable(ns_core, 0);
1627 }
1628 }
1629
dd4544f0
RM		 1630 err = bgmac_dma_alloc(bgmac);
1631 if (err) {
1632 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1633 goto err_netdev_free;
1634 }
1635
1636 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
edb15d83 1637 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
dd4544f0
RM		 1638 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1639
1640 /* TODO: reset the external phy. Specs are needed */
1641 bgmac_phy_reset(bgmac);
1642
1643 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1644 BGMAC_BFL_ENETROBO);
1645 if (bgmac->has_robosw)
1646 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1647
1648 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1649 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1650
6216642f
HM		 1651 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1652
11e5e76e
RM		 1653 err = bgmac_mii_register(bgmac);
1654 if (err) {
1655 bgmac_err(bgmac, "Cannot register MDIO\n");
11e5e76e
RM		 1656 goto err_dma_free;
1657 }
1658
9cde9450
FF		 1659 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1660 net_dev->hw_features = net_dev->features;
1661 net_dev->vlan_features = net_dev->features;
1662
dd4544f0
RM		 1663 err = register_netdev(bgmac->net_dev);
1664 if (err) {
1665 bgmac_err(bgmac, "Cannot register net device\n");
11e5e76e 1666 goto err_mii_unregister;
dd4544f0
RM		 1667 }
1668
1669 netif_carrier_off(net_dev);
1670
dd4544f0
RM		 1671 return 0;
1672
11e5e76e
RM		 1673err_mii_unregister:
1674 bgmac_mii_unregister(bgmac);
dd4544f0
RM		 1675err_dma_free:
1676 bgmac_dma_free(bgmac);
1677
1678err_netdev_free:
1679 bcma_set_drvdata(core, NULL);
1680 free_netdev(net_dev);
1681
1682 return err;
1683}
1684
1685static void bgmac_remove(struct bcma_device *core)
1686{
1687 struct bgmac *bgmac = bcma_get_drvdata(core);
1688
dd4544f0 1689 unregister_netdev(bgmac->net_dev);
11e5e76e 1690 bgmac_mii_unregister(bgmac);
6216642f 1691 netif_napi_del(&bgmac->napi);
dd4544f0
RM		 1692 bgmac_dma_free(bgmac);
1693 bcma_set_drvdata(core, NULL);
1694 free_netdev(bgmac->net_dev);
1695}
1696
1697static struct bcma_driver bgmac_bcma_driver = {
1698 .name = KBUILD_MODNAME,
1699 .id_table = bgmac_bcma_tbl,
1700 .probe = bgmac_probe,
1701 .remove = bgmac_remove,
1702};
1703
1704static int __init bgmac_init(void)
1705{
1706 int err;
1707
1708 err = bcma_driver_register(&bgmac_bcma_driver);
1709 if (err)
1710 return err;
1711 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1712
1713 return 0;
1714}
1715
1716static void __exit bgmac_exit(void)
1717{
1718 bcma_driver_unregister(&bgmac_bcma_driver);
1719}
1720
1721module_init(bgmac_init)
1722module_exit(bgmac_exit)
1723
1724MODULE_AUTHOR("Rafał Miłecki");
1725MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)