[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_main.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Applied Micro X-Gene SoC Ethernet Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Authors: Iyappan Subramanian <isubramanian@apm.com>
 *	    Ravi Patel <rapatel@apm.com>
 *	    Keyur Chudgar <kchudgar@apm.com>
 */

#ifndef __XGENE_ENET_MAIN_H__
#define __XGENE_ENET_MAIN_H__

#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/efi.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/platform_device.h>
#include <linux/mdio/mdio-xgene.h>
#include <linux/module.h>
#include <net/ip.h>
#include <linux/prefetch.h>
#include <linux/if_vlan.h>
#include <linux/phy.h>
#include "xgene_enet_hw.h"
#include "xgene_enet_cle.h"
#include "xgene_enet_ring2.h"

#define ETHER_MIN_PACKET	64
#define ETHER_STD_PACKET	1518
#define XGENE_ENET_STD_MTU	1536
#define XGENE_ENET_MAX_MTU	9600
#define SKB_BUFFER_SIZE		(XGENE_ENET_STD_MTU - NET_IP_ALIGN)

#define BUFLEN_16K	(16 * 1024)
#define NUM_PKT_BUF	1024
#define NUM_BUFPOOL	32
#define NUM_NXTBUFPOOL	8
#define MAX_EXP_BUFFS	256
#define NUM_MSS_REG	4
#define XGENE_MIN_ENET_FRAME_SIZE	60

#define XGENE_MAX_ENET_IRQ	16
#define XGENE_NUM_RX_RING	8
#define XGENE_NUM_TX_RING	8
#define XGENE_NUM_TXC_RING	8

#define START_CPU_BUFNUM_0	0
#define START_ETH_BUFNUM_0	2
#define START_BP_BUFNUM_0	0x22
#define START_RING_NUM_0	8
#define START_CPU_BUFNUM_1	12
#define START_ETH_BUFNUM_1	10
#define START_BP_BUFNUM_1	0x2A
#define START_RING_NUM_1	264

#define XG_START_CPU_BUFNUM_1	12
#define XG_START_ETH_BUFNUM_1	2
#define XG_START_BP_BUFNUM_1	0x22
#define XG_START_RING_NUM_1	264

#define X2_START_CPU_BUFNUM_0	0
#define X2_START_ETH_BUFNUM_0	0
#define X2_START_BP_BUFNUM_0	0x20
#define X2_START_RING_NUM_0	0
#define X2_START_CPU_BUFNUM_1	0xc
#define X2_START_ETH_BUFNUM_1	0
#define X2_START_BP_BUFNUM_1	0x20
#define X2_START_RING_NUM_1	256

#define IRQ_ID_SIZE		16

#define PHY_POLL_LINK_ON	(10 * HZ)
#define PHY_POLL_LINK_OFF	(PHY_POLL_LINK_ON / 5)

enum xgene_enet_id {
	XGENE_ENET1 = 1,
	XGENE_ENET2
};

enum xgene_enet_buf_len {
	SIZE_2K = 2048,
	SIZE_4K = 4096,
	SIZE_16K = 16384
};

/* software context of a descriptor ring */
struct xgene_enet_desc_ring {
	struct net_device *ndev;
	u16 id;
	u16 num;
	u16 head;
	u16 tail;
	u16 exp_buf_tail;
	u16 slots;
	u16 irq;
	char irq_name[IRQ_ID_SIZE];
	u32 size;
	u32 state[X2_NUM_RING_CONFIG];
	void __iomem *cmd_base;
	void __iomem *cmd;
	dma_addr_t dma;
	dma_addr_t irq_mbox_dma;
	void *irq_mbox_addr;
	u16 dst_ring_num;
	u16 nbufpool;
	int npagepool;
	u8 index;
	u32 flags;
	struct sk_buff *(*rx_skb);
	struct sk_buff *(*cp_skb);
	dma_addr_t *frag_dma_addr;
	struct page *(*frag_page);
	enum xgene_enet_ring_cfgsize cfgsize;
	struct xgene_enet_desc_ring *cp_ring;
	struct xgene_enet_desc_ring *buf_pool;
	struct xgene_enet_desc_ring *page_pool;
	struct napi_struct napi;
	union {
		void *desc_addr;
		struct xgene_enet_raw_desc *raw_desc;
		struct xgene_enet_raw_desc16 *raw_desc16;
	};
	__le64 *exp_bufs;
	u64 tx_packets;
	u64 tx_bytes;
	u64 tx_dropped;
	u64 tx_errors;
	u64 rx_packets;
	u64 rx_bytes;
	u64 rx_dropped;
	u64 rx_errors;
	u64 rx_length_errors;
	u64 rx_crc_errors;
	u64 rx_frame_errors;
	u64 rx_fifo_errors;
};

struct xgene_mac_ops {
	void (*init)(struct xgene_enet_pdata *pdata);
	void (*reset)(struct xgene_enet_pdata *pdata);
	void (*tx_enable)(struct xgene_enet_pdata *pdata);
	void (*rx_enable)(struct xgene_enet_pdata *pdata);
	void (*tx_disable)(struct xgene_enet_pdata *pdata);
	void (*rx_disable)(struct xgene_enet_pdata *pdata);
	void (*get_drop_cnt)(struct xgene_enet_pdata *pdata, u32 *rx, u32 *tx);
	void (*set_speed)(struct xgene_enet_pdata *pdata);
	void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
	void (*set_framesize)(struct xgene_enet_pdata *pdata, int framesize);
	void (*set_mss)(struct xgene_enet_pdata *pdata, u16 mss, u8 index);
	void (*link_state)(struct work_struct *work);
	void (*enable_tx_pause)(struct xgene_enet_pdata *pdata, bool enable);
	void (*flowctl_rx)(struct xgene_enet_pdata *pdata, bool enable);
	void (*flowctl_tx)(struct xgene_enet_pdata *pdata, bool enable);
};

struct xgene_port_ops {
	int (*reset)(struct xgene_enet_pdata *pdata);
	void (*clear)(struct xgene_enet_pdata *pdata,
		      struct xgene_enet_desc_ring *ring);
	void (*cle_bypass)(struct xgene_enet_pdata *pdata,
			   u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id);
	void (*shutdown)(struct xgene_enet_pdata *pdata);
};

struct xgene_ring_ops {
	u8 num_ring_config;
	u8 num_ring_id_shift;
	struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
	void (*clear)(struct xgene_enet_desc_ring *);
	void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
	u32 (*len)(struct xgene_enet_desc_ring *);
	void (*coalesce)(struct xgene_enet_desc_ring *);
};

struct xgene_cle_ops {
	int (*cle_init)(struct xgene_enet_pdata *pdata);
};

/* ethernet private data */
struct xgene_enet_pdata {
	struct net_device *ndev;
	struct mii_bus *mdio_bus;
	int phy_speed;
	struct clk *clk;
	struct platform_device *pdev;
	enum xgene_enet_id enet_id;
	struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
	struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
	u16 tx_level[XGENE_NUM_TX_RING];
	u16 txc_level[XGENE_NUM_TX_RING];
	char *dev_name;
	u32 rx_buff_cnt;
	u32 tx_qcnt_hi;
	u32 irqs[XGENE_MAX_ENET_IRQ];
	u8 rxq_cnt;
	u8 txq_cnt;
	u8 cq_cnt;
	void __iomem *eth_csr_addr;
	void __iomem *eth_ring_if_addr;
	void __iomem *eth_diag_csr_addr;
	void __iomem *mcx_mac_addr;
	void __iomem *mcx_mac_csr_addr;
	void __iomem *mcx_stats_addr;
	void __iomem *base_addr;
	void __iomem *pcs_addr;
	void __iomem *ring_csr_addr;
	void __iomem *ring_cmd_addr;
	int phy_mode;
	enum xgene_enet_rm rm;
	struct xgene_enet_cle cle;
	u64 *extd_stats;
	u64 false_rflr;
	u64 vlan_rjbr;
	spinlock_t stats_lock; /* statistics lock */
	const struct xgene_mac_ops *mac_ops;
	spinlock_t mac_lock; /* mac lock */
	const struct xgene_port_ops *port_ops;
	struct xgene_ring_ops *ring_ops;
	const struct xgene_cle_ops *cle_ops;
	struct delayed_work link_work;
	u32 port_id;
	u8 cpu_bufnum;
	u8 eth_bufnum;
	u8 bp_bufnum;
	u16 ring_num;
	u32 mss[NUM_MSS_REG];
	u32 mss_refcnt[NUM_MSS_REG];
	spinlock_t mss_lock;  /* mss lock */
	u8 tx_delay;
	u8 rx_delay;
	bool mdio_driver;
	struct gpio_desc *sfp_rdy;
	bool sfp_gpio_en;
	u32 pause_autoneg;
	bool tx_pause;
	bool rx_pause;
};

struct xgene_indirect_ctl {
	void __iomem *addr;
	void __iomem *ctl;
	void __iomem *cmd;
	void __iomem *cmd_done;
};

static inline struct device *ndev_to_dev(struct net_device *ndev)
{
	return ndev->dev.parent;
}

static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
{
	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);

	return ((u16)pdata->rm << 10) | ring->num;
}

void xgene_enet_set_ethtool_ops(struct net_device *netdev);
int xgene_extd_stats_init(struct xgene_enet_pdata *pdata);

#endif /* __XGENE_ENET_MAIN_H__ */
Commit	Line	Data
1ccea77e	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
e6ad7673 IS	2	/* Applied Micro X-Gene SoC Ethernet Driver
	3	*
	4	* Copyright (c) 2014, Applied Micro Circuits Corporation
	5	* Authors: Iyappan Subramanian <isubramanian@apm.com>
	6	* Ravi Patel <rapatel@apm.com>
	7	* Keyur Chudgar <kchudgar@apm.com>
e6ad7673 IS	8	*/
	9
	10	#ifndef __XGENE_ENET_MAIN_H__
	11	#define __XGENE_ENET_MAIN_H__
	12
de7b5b3d	13	#include <linux/acpi.h>
e6ad7673	14	#include <linux/clk.h>
de7b5b3d	15	#include <linux/efi.h>
b5d7a069	16	#include <linux/irq.h>
de7b5b3d	17	#include <linux/io.h>
b0377116	18	#include <linux/of.h>
e6ad7673 IS	19	#include <linux/of_net.h>
e6ad7673 IS	20	#include <linux/of_mdio.h>
b0377116	21	#include <linux/platform_device.h>
232e15e1	22	#include <linux/mdio/mdio-xgene.h>
e6ad7673 IS	23	#include <linux/module.h>
	24	#include <net/ip.h>
	25	#include <linux/prefetch.h>
	26	#include <linux/if_vlan.h>
	27	#include <linux/phy.h>
	28	#include "xgene_enet_hw.h"
76f94a9c	29	#include "xgene_enet_cle.h"
bc1b7c13	30	#include "xgene_enet_ring2.h"
e6ad7673	31
4902a922	32	#define ETHER_MIN_PACKET 64
61c759cd	33	#define ETHER_STD_PACKET 1518
a9380b0f IS	34	#define XGENE_ENET_STD_MTU 1536
	35	#define XGENE_ENET_MAX_MTU 9600
	36	#define SKB_BUFFER_SIZE (XGENE_ENET_STD_MTU - NET_IP_ALIGN)
	37
949c40bb	38	#define BUFLEN_16K (16 * 1024)
a9380b0f	39	#define NUM_PKT_BUF 1024
e6ad7673	40	#define NUM_BUFPOOL 32
a9380b0f	41	#define NUM_NXTBUFPOOL 8
9b00eb49	42	#define MAX_EXP_BUFFS 256
e3978673	43	#define NUM_MSS_REG 4
9b00eb49	44	#define XGENE_MIN_ENET_FRAME_SIZE 60
ca626454	45
1b090a48 IS	46	#define XGENE_MAX_ENET_IRQ 16
	47	#define XGENE_NUM_RX_RING 8
	48	#define XGENE_NUM_TX_RING 8
	49	#define XGENE_NUM_TXC_RING 8
107dec27	50
ca626454 KC	51	#define START_CPU_BUFNUM_0 0
	52	#define START_ETH_BUFNUM_0 2
	53	#define START_BP_BUFNUM_0 0x22
	54	#define START_RING_NUM_0 8
	55	#define START_CPU_BUFNUM_1 12
	56	#define START_ETH_BUFNUM_1 10
	57	#define START_BP_BUFNUM_1 0x2A
	58	#define START_RING_NUM_1 264
e6ad7673	59
149e9ab4 IS	60	#define XG_START_CPU_BUFNUM_1 12
	61	#define XG_START_ETH_BUFNUM_1 2
	62	#define XG_START_BP_BUFNUM_1 0x22
	63	#define XG_START_RING_NUM_1 264
	64
bc1b7c13 IS	65	#define X2_START_CPU_BUFNUM_0 0
	66	#define X2_START_ETH_BUFNUM_0 0
	67	#define X2_START_BP_BUFNUM_0 0x20
	68	#define X2_START_RING_NUM_0 0
bc1b7c13 IS	69	#define X2_START_CPU_BUFNUM_1 0xc
	70	#define X2_START_ETH_BUFNUM_1 0
	71	#define X2_START_BP_BUFNUM_1 0x20
	72	#define X2_START_RING_NUM_1 256
	73
6772b653	74	#define IRQ_ID_SIZE 16
6772b653	75
32f784b5 IS	76	#define PHY_POLL_LINK_ON (10 * HZ)
	77	#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
	78
bc1b7c13 IS	79	enum xgene_enet_id {
	80	XGENE_ENET1 = 1,
	81	XGENE_ENET2
	82	};
	83
a9380b0f IS	84	enum xgene_enet_buf_len {
	85	SIZE_2K = 2048,
	86	SIZE_4K = 4096,
	87	SIZE_16K = 16384
	88	};
	89
e6ad7673 IS	90	/* software context of a descriptor ring */
	91	struct xgene_enet_desc_ring {
	92	struct net_device *ndev;
	93	u16 id;
	94	u16 num;
	95	u16 head;
	96	u16 tail;
9b00eb49	97	u16 exp_buf_tail;
e6ad7673 IS	98	u16 slots;
e6ad7673 IS	99	u16 irq;
6772b653	100	char irq_name[IRQ_ID_SIZE];
e6ad7673	101	u32 size;
9dd3c797	102	u32 state[X2_NUM_RING_CONFIG];
e6ad7673 IS	103	void __iomem *cmd_base;
	104	void __iomem *cmd;
	105	dma_addr_t dma;
ed9b7da0 IS	106	dma_addr_t irq_mbox_dma;
ed9b7da0 IS	107	void *irq_mbox_addr;
e6ad7673	108	u16 dst_ring_num;
a9380b0f IS	109	u16 nbufpool;
a9380b0f IS	110	int npagepool;
107dec27	111	u8 index;
a9380b0f	112	u32 flags;
e6ad7673 IS	113	struct sk_buff (rx_skb);
e6ad7673 IS	114	struct sk_buff (cp_skb);
9b00eb49	115	dma_addr_t *frag_dma_addr;
a9380b0f	116	struct page (frag_page);
e6ad7673 IS	117	enum xgene_enet_ring_cfgsize cfgsize;
	118	struct xgene_enet_desc_ring *cp_ring;
	119	struct xgene_enet_desc_ring *buf_pool;
d6d48969	120	struct xgene_enet_desc_ring *page_pool;
e6ad7673 IS	121	struct napi_struct napi;
	122	union {
	123	void *desc_addr;
	124	struct xgene_enet_raw_desc *raw_desc;
	125	struct xgene_enet_raw_desc16 *raw_desc16;
	126	};
9b00eb49	127	__le64 *exp_bufs;
3bb502f8 IS	128	u64 tx_packets;
3bb502f8 IS	129	u64 tx_bytes;
089f97c7 QN	130	u64 tx_dropped;
089f97c7 QN	131	u64 tx_errors;
3bb502f8 IS	132	u64 rx_packets;
	133	u64 rx_bytes;
	134	u64 rx_dropped;
	135	u64 rx_errors;
	136	u64 rx_length_errors;
	137	u64 rx_crc_errors;
	138	u64 rx_frame_errors;
	139	u64 rx_fifo_errors;
e6ad7673 IS	140	};
e6ad7673 IS	141
d0eb7458 IS	142	struct xgene_mac_ops {
	143	void (init)(struct xgene_enet_pdata pdata);
	144	void (reset)(struct xgene_enet_pdata pdata);
	145	void (tx_enable)(struct xgene_enet_pdata pdata);
	146	void (rx_enable)(struct xgene_enet_pdata pdata);
	147	void (tx_disable)(struct xgene_enet_pdata pdata);
	148	void (rx_disable)(struct xgene_enet_pdata pdata);
ca6d550c	149	void (get_drop_cnt)(struct xgene_enet_pdata pdata, u32 rx, u32 tx);
9a8c5dde	150	void (set_speed)(struct xgene_enet_pdata pdata);
d0eb7458	151	void (set_mac_addr)(struct xgene_enet_pdata pdata);
350b4e33	152	void (set_framesize)(struct xgene_enet_pdata pdata, int framesize);
e3978673	153	void (set_mss)(struct xgene_enet_pdata pdata, u16 mss, u8 index);
dc8385f0	154	void (link_state)(struct work_struct work);
bb64fa09 IS	155	void (enable_tx_pause)(struct xgene_enet_pdata pdata, bool enable);
	156	void (flowctl_rx)(struct xgene_enet_pdata pdata, bool enable);
	157	void (flowctl_tx)(struct xgene_enet_pdata pdata, bool enable);
d0eb7458 IS	158	};
	159
	160	struct xgene_port_ops {
c3f4465d	161	int (reset)(struct xgene_enet_pdata pdata);
cb11c062 IS	162	void (clear)(struct xgene_enet_pdata pdata,
cb11c062 IS	163	struct xgene_enet_desc_ring *ring);
d0eb7458	164	void (cle_bypass)(struct xgene_enet_pdata pdata,
d6d48969	165	u32 dst_ring_num, u16 bufpool_id, u16 nxtbufpool_id);
d0eb7458 IS	166	void (shutdown)(struct xgene_enet_pdata pdata);
	167	};
	168
81cefb81 IS	169	struct xgene_ring_ops {
	170	u8 num_ring_config;
	171	u8 num_ring_id_shift;
	172	struct xgene_enet_desc_ring * (setup)(struct xgene_enet_desc_ring );
	173	void (clear)(struct xgene_enet_desc_ring );
	174	void (wr_cmd)(struct xgene_enet_desc_ring , int);
	175	u32 (len)(struct xgene_enet_desc_ring );
107dec27	176	void (coalesce)(struct xgene_enet_desc_ring );
81cefb81 IS	177	};
81cefb81 IS	178
76f94a9c IS	179	struct xgene_cle_ops {
	180	int (cle_init)(struct xgene_enet_pdata pdata);
	181	};
	182
e6ad7673 IS	183	/* ethernet private data */
	184	struct xgene_enet_pdata {
	185	struct net_device *ndev;
	186	struct mii_bus *mdio_bus;
e6ad7673 IS	187	int phy_speed;
	188	struct clk *clk;
	189	struct platform_device *pdev;
bc1b7c13	190	enum xgene_enet_id enet_id;
107dec27 IS	191	struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
	192	struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
	193	u16 tx_level[XGENE_NUM_TX_RING];
	194	u16 txc_level[XGENE_NUM_TX_RING];
e6ad7673 IS	195	char *dev_name;
	196	u32 rx_buff_cnt;
	197	u32 tx_qcnt_hi;
107dec27 IS	198	u32 irqs[XGENE_MAX_ENET_IRQ];
	199	u8 rxq_cnt;
	200	u8 txq_cnt;
6772b653	201	u8 cq_cnt;
e6ad7673 IS	202	void __iomem *eth_csr_addr;
	203	void __iomem *eth_ring_if_addr;
	204	void __iomem *eth_diag_csr_addr;
	205	void __iomem *mcx_mac_addr;
e6ad7673	206	void __iomem *mcx_mac_csr_addr;
2d07d8e4	207	void __iomem *mcx_stats_addr;
e6ad7673	208	void __iomem *base_addr;
3eb7cb9d	209	void __iomem *pcs_addr;
e6ad7673 IS	210	void __iomem *ring_csr_addr;
e6ad7673 IS	211	void __iomem *ring_cmd_addr;
e6ad7673	212	int phy_mode;
0148d38d	213	enum xgene_enet_rm rm;
76f94a9c	214	struct xgene_enet_cle cle;
2d07d8e4	215	u64 *extd_stats;
eaef62a4	216	u64 false_rflr;
61c759cd	217	u64 vlan_rjbr;
2d07d8e4	218	spinlock_t stats_lock; /* statistics lock */
3cdb7309	219	const struct xgene_mac_ops *mac_ops;
ae1aed95	220	spinlock_t mac_lock; /* mac lock */
3cdb7309	221	const struct xgene_port_ops *port_ops;
81cefb81	222	struct xgene_ring_ops *ring_ops;
b555a3d1	223	const struct xgene_cle_ops *cle_ops;
0148d38d	224	struct delayed_work link_work;
ca626454 KC	225	u32 port_id;
	226	u8 cpu_bufnum;
	227	u8 eth_bufnum;
	228	u8 bp_bufnum;
	229	u16 ring_num;
e3978673 IS	230	u32 mss[NUM_MSS_REG];
	231	u32 mss_refcnt[NUM_MSS_REG];
	232	spinlock_t mss_lock; /* mss lock */
16615a4c IS	233	u8 tx_delay;
16615a4c IS	234	u8 rx_delay;
8089a96f	235	bool mdio_driver;
27ecf87c	236	struct gpio_desc *sfp_rdy;
751d6fd1	237	bool sfp_gpio_en;
bb64fa09 IS	238	u32 pause_autoneg;
	239	bool tx_pause;
	240	bool rx_pause;
e6ad7673 IS	241	};
e6ad7673 IS	242
32f784b5 IS	243	struct xgene_indirect_ctl {
	244	void __iomem *addr;
	245	void __iomem *ctl;
	246	void __iomem *cmd;
	247	void __iomem *cmd_done;
	248	};
	249
e6ad7673 IS	250	static inline struct device ndev_to_dev(struct net_device ndev)
	251	{
	252	return ndev->dev.parent;
	253	}
	254
76f94a9c IS	255	static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
	256	{
	257	struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
	258
	259	return ((u16)pdata->rm << 10) \| ring->num;
	260	}
	261
e6ad7673	262	void xgene_enet_set_ethtool_ops(struct net_device *netdev);
2d07d8e4	263	int xgene_extd_stats_init(struct xgene_enet_pdata *pdata);
e6ad7673 IS	264
e6ad7673 IS	265	#endif /* __XGENE_ENET_MAIN_H__ */