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Merge tag 'mm-stable-2024-05-24-11-49' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_main.c
CommitLineData
1ccea77e 1// SPDX-License-Identifier: GPL-2.0-or-later
e6ad7673
IS		 2/* Applied Micro X-Gene SoC Ethernet Driver
3 *
4 * Copyright (c) 2014, Applied Micro Circuits Corporation
5 * Authors: Iyappan Subramanian <isubramanian@apm.com>
6 * Ravi Patel <rapatel@apm.com>
7 * Keyur Chudgar <kchudgar@apm.com>
e6ad7673
IS		 8 */
9
27ecf87c 10#include <linux/gpio.h>
e6ad7673
IS		 11#include "xgene_enet_main.h"
12#include "xgene_enet_hw.h"
32f784b5 13#include "xgene_enet_sgmac.h"
0148d38d 14#include "xgene_enet_xgmac.h"
e6ad7673 15
de7b5b3d
FK		 16#define RES_ENET_CSR 0
17#define RES_RING_CSR 1
18#define RES_RING_CMD 2
19
e6ad7673
IS		 20static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
21{
22 struct xgene_enet_raw_desc16 *raw_desc;
23 int i;
24
a9380b0f
IS		 25 if (!buf_pool)
26 return;
27
e6ad7673
IS		 28 for (i = 0; i < buf_pool->slots; i++) {
29 raw_desc = &buf_pool->raw_desc16[i];
30
31 /* Hardware expects descriptor in little endian format */
32 raw_desc->m0 = cpu_to_le64(i |
33 SET_VAL(FPQNUM, buf_pool->dst_ring_num) |
34 SET_VAL(STASH, 3));
35 }
36}
37
a9380b0f
IS		 38static u16 xgene_enet_get_data_len(u64 bufdatalen)
39{
40 u16 hw_len, mask;
41
42 hw_len = GET_VAL(BUFDATALEN, bufdatalen);
43
44 if (unlikely(hw_len == 0x7800)) {
45 return 0;
46 } else if (!(hw_len & BIT(14))) {
47 mask = GENMASK(13, 0);
48 return (hw_len & mask) ? (hw_len & mask) : SIZE_16K;
49 } else if (!(hw_len & GENMASK(13, 12))) {
50 mask = GENMASK(11, 0);
51 return (hw_len & mask) ? (hw_len & mask) : SIZE_4K;
52 } else {
53 mask = GENMASK(11, 0);
54 return (hw_len & mask) ? (hw_len & mask) : SIZE_2K;
55 }
56}
57
58static u16 xgene_enet_set_data_len(u32 size)
59{
60 u16 hw_len;
61
62 hw_len = (size == SIZE_4K) ? BIT(14) : 0;
63
64 return hw_len;
65}
66
67static int xgene_enet_refill_pagepool(struct xgene_enet_desc_ring *buf_pool,
68 u32 nbuf)
69{
70 struct xgene_enet_raw_desc16 *raw_desc;
71 struct xgene_enet_pdata *pdata;
72 struct net_device *ndev;
73 dma_addr_t dma_addr;
74 struct device *dev;
75 struct page *page;
76 u32 slots, tail;
77 u16 hw_len;
78 int i;
79
80 if (unlikely(!buf_pool))
81 return 0;
82
83 ndev = buf_pool->ndev;
84 pdata = netdev_priv(ndev);
85 dev = ndev_to_dev(ndev);
86 slots = buf_pool->slots - 1;
87 tail = buf_pool->tail;
88
89 for (i = 0; i < nbuf; i++) {
90 raw_desc = &buf_pool->raw_desc16[tail];
91
92 page = dev_alloc_page();
93 if (unlikely(!page))
94 return -ENOMEM;
95
96 dma_addr = dma_map_page(dev, page, 0,
97 PAGE_SIZE, DMA_FROM_DEVICE);
98 if (unlikely(dma_mapping_error(dev, dma_addr))) {
99 put_page(page);
100 return -ENOMEM;
101 }
102
103 hw_len = xgene_enet_set_data_len(PAGE_SIZE);
104 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
105 SET_VAL(BUFDATALEN, hw_len) |
106 SET_BIT(COHERENT));
107
108 buf_pool->frag_page[tail] = page;
109 tail = (tail + 1) & slots;
110 }
111
112 pdata->ring_ops->wr_cmd(buf_pool, nbuf);
113 buf_pool->tail = tail;
114
115 return 0;
116}
117
e6ad7673
IS		 118static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool,
119 u32 nbuf)
120{
121 struct sk_buff *skb;
122 struct xgene_enet_raw_desc16 *raw_desc;
81cefb81 123 struct xgene_enet_pdata *pdata;
e6ad7673
IS		 124 struct net_device *ndev;
125 struct device *dev;
126 dma_addr_t dma_addr;
127 u32 tail = buf_pool->tail;
128 u32 slots = buf_pool->slots - 1;
129 u16 bufdatalen, len;
130 int i;
131
132 ndev = buf_pool->ndev;
133 dev = ndev_to_dev(buf_pool->ndev);
81cefb81 134 pdata = netdev_priv(ndev);
a9380b0f 135
e6ad7673 136 bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));
a9380b0f 137 len = XGENE_ENET_STD_MTU;
e6ad7673
IS		 138
139 for (i = 0; i < nbuf; i++) {
140 raw_desc = &buf_pool->raw_desc16[tail];
141
142 skb = netdev_alloc_skb_ip_align(ndev, len);
143 if (unlikely(!skb))
144 return -ENOMEM;
e6ad7673
IS		 145
146 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
147 if (dma_mapping_error(dev, dma_addr)) {
148 netdev_err(ndev, "DMA mapping error\n");
149 dev_kfree_skb_any(skb);
150 return -EINVAL;
151 }
152
6e434627
IS		 153 buf_pool->rx_skb[tail] = skb;
154
e6ad7673
IS		 155 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
156 SET_VAL(BUFDATALEN, bufdatalen) |
157 SET_BIT(COHERENT));
158 tail = (tail + 1) & slots;
159 }
160
81cefb81 161 pdata->ring_ops->wr_cmd(buf_pool, nbuf);
e6ad7673
IS		 162 buf_pool->tail = tail;
163
164 return 0;
165}
166
e6ad7673
IS		 167static u8 xgene_enet_hdr_len(const void *data)
168{
169 const struct ethhdr *eth = data;
170
171 return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN;
172}
173
e6ad7673
IS		 174static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool)
175{
6e434627
IS		 176 struct device *dev = ndev_to_dev(buf_pool->ndev);
177 struct xgene_enet_raw_desc16 *raw_desc;
178 dma_addr_t dma_addr;
cb11c062 179 int i;
e6ad7673 180
cb11c062
IS		 181 /* Free up the buffers held by hardware */
182 for (i = 0; i < buf_pool->slots; i++) {
6e434627 183 if (buf_pool->rx_skb[i]) {
cb11c062 184 dev_kfree_skb_any(buf_pool->rx_skb[i]);
6e434627
IS		 185
186 raw_desc = &buf_pool->raw_desc16[i];
187 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1));
188 dma_unmap_single(dev, dma_addr, XGENE_ENET_MAX_MTU,
189 DMA_FROM_DEVICE);
190 }
e6ad7673 191 }
e6ad7673
IS		 192}
193
a9380b0f
IS		 194static void xgene_enet_delete_pagepool(struct xgene_enet_desc_ring *buf_pool)
195{
196 struct device *dev = ndev_to_dev(buf_pool->ndev);
197 dma_addr_t dma_addr;
198 struct page *page;
199 int i;
200
201 /* Free up the buffers held by hardware */
202 for (i = 0; i < buf_pool->slots; i++) {
203 page = buf_pool->frag_page[i];
204 if (page) {
205 dma_addr = buf_pool->frag_dma_addr[i];
206 dma_unmap_page(dev, dma_addr, PAGE_SIZE,
207 DMA_FROM_DEVICE);
208 put_page(page);
209 }
210 }
211}
212
e6ad7673
IS		 213static irqreturn_t xgene_enet_rx_irq(const int irq, void *data)
214{
215 struct xgene_enet_desc_ring *rx_ring = data;
216
217 if (napi_schedule_prep(&rx_ring->napi)) {
218 disable_irq_nosync(irq);
219 __napi_schedule(&rx_ring->napi);
220 }
221
222 return IRQ_HANDLED;
223}
224
225static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
226 struct xgene_enet_raw_desc *raw_desc)
227{
e3978673 228 struct xgene_enet_pdata *pdata = netdev_priv(cp_ring->ndev);
e6ad7673
IS		 229 struct sk_buff *skb;
230 struct device *dev;
9b00eb49
IS		 231 skb_frag_t *frag;
232 dma_addr_t *frag_dma_addr;
e6ad7673 233 u16 skb_index;
e3978673 234 u8 mss_index;
089f97c7
QN		 235 u8 status;
236 int i;
e6ad7673
IS		 237
238 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
239 skb = cp_ring->cp_skb[skb_index];
9b00eb49 240 frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS];
e6ad7673
IS		 241
242 dev = ndev_to_dev(cp_ring->ndev);
243 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
9b00eb49 244 skb_headlen(skb),
e6ad7673
IS		 245 DMA_TO_DEVICE);
246
9b00eb49
IS		 247 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
248 frag = &skb_shinfo(skb)->frags[i];
249 dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag),
250 DMA_TO_DEVICE);
251 }
252
e3978673
IS		 253 if (GET_BIT(ET, le64_to_cpu(raw_desc->m3))) {
254 mss_index = GET_VAL(MSS, le64_to_cpu(raw_desc->m3));
255 spin_lock(&pdata->mss_lock);
256 pdata->mss_refcnt[mss_index]--;
257 spin_unlock(&pdata->mss_lock);
258 }
259
e6ad7673
IS		 260 /* Checking for error */
261 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
262 if (unlikely(status > 2)) {
089f97c7
QN		 263 cp_ring->tx_dropped++;
264 cp_ring->tx_errors++;
e6ad7673
IS		 265 }
266
267 if (likely(skb)) {
268 dev_kfree_skb_any(skb);
269 } else {
270 netdev_err(cp_ring->ndev, "completion skb is NULL\n");
e6ad7673
IS		 271 }
272
089f97c7 273 return 0;
e6ad7673
IS		 274}
275
e3978673
IS		 276static int xgene_enet_setup_mss(struct net_device *ndev, u32 mss)
277{
278 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1b8c1012 279 int mss_index = -EBUSY;
e3978673
IS		 280 int i;
281
282 spin_lock(&pdata->mss_lock);
283
284 /* Reuse the slot if MSS matches */
1b8c1012 285 for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) {
e3978673
IS		 286 if (pdata->mss[i] == mss) {
287 pdata->mss_refcnt[i]++;
288 mss_index = i;
e3978673
IS		 289 }
290 }
291
292 /* Overwrite the slot with ref_count = 0 */
1b8c1012 293 for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) {
e3978673
IS		 294 if (!pdata->mss_refcnt[i]) {
295 pdata->mss_refcnt[i]++;
296 pdata->mac_ops->set_mss(pdata, mss, i);
297 pdata->mss[i] = mss;
298 mss_index = i;
e3978673
IS		 299 }
300 }
301
f006b2c5 302 spin_unlock(&pdata->mss_lock);
e3978673
IS		 303
304 return mss_index;
305}
306
307static int xgene_enet_work_msg(struct sk_buff *skb, u64 *hopinfo)
e6ad7673 308{
9b00eb49 309 struct net_device *ndev = skb->dev;
e6ad7673 310 struct iphdr *iph;
9b00eb49
IS		 311 u8 l3hlen = 0, l4hlen = 0;
312 u8 ethhdr, proto = 0, csum_enable = 0;
9b00eb49
IS		 313 u32 hdr_len, mss = 0;
314 u32 i, len, nr_frags;
e3978673 315 int mss_index;
9b00eb49
IS		 316
317 ethhdr = xgene_enet_hdr_len(skb->data);
e6ad7673
IS		 318
319 if (unlikely(skb->protocol != htons(ETH_P_IP)) &&
320 unlikely(skb->protocol != htons(ETH_P_8021Q)))
321 goto out;
322
323 if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM)))
324 goto out;
325
326 iph = ip_hdr(skb);
327 if (unlikely(ip_is_fragment(iph)))
328 goto out;
329
330 if (likely(iph->protocol == IPPROTO_TCP)) {
331 l4hlen = tcp_hdrlen(skb) >> 2;
332 csum_enable = 1;
333 proto = TSO_IPPROTO_TCP;
9b00eb49
IS		 334 if (ndev->features & NETIF_F_TSO) {
335 hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb);
336 mss = skb_shinfo(skb)->gso_size;
337
338 if (skb_is_nonlinear(skb)) {
339 len = skb_headlen(skb);
340 nr_frags = skb_shinfo(skb)->nr_frags;
341
342 for (i = 0; i < 2 && i < nr_frags; i++)
d7840976
MWO		 343 len += skb_frag_size(
344 &skb_shinfo(skb)->frags[i]);
9b00eb49
IS		 345
346 /* HW requires header must reside in 3 buffer */
347 if (unlikely(hdr_len > len)) {
348 if (skb_linearize(skb))
349 return 0;
350 }
351 }
352
353 if (!mss || ((skb->len - hdr_len) <= mss))
354 goto out;
355
e3978673
IS		 356 mss_index = xgene_enet_setup_mss(ndev, mss);
357 if (unlikely(mss_index < 0))
358 return -EBUSY;
359
360 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index);
9b00eb49 361 }
e6ad7673
IS		 362 } else if (iph->protocol == IPPROTO_UDP) {
363 l4hlen = UDP_HDR_SIZE;
364 csum_enable = 1;
365 }
366out:
367 l3hlen = ip_hdrlen(skb) >> 2;
e3978673
IS		 368 *hopinfo |= SET_VAL(TCPHDR, l4hlen) |
369 SET_VAL(IPHDR, l3hlen) |
370 SET_VAL(ETHHDR, ethhdr) |
371 SET_VAL(EC, csum_enable) |
372 SET_VAL(IS, proto) |
373 SET_BIT(IC) |
374 SET_BIT(TYPE_ETH_WORK_MESSAGE);
375
376 return 0;
e6ad7673
IS		 377}
378
949c40bb
IS		 379static u16 xgene_enet_encode_len(u16 len)
380{
381 return (len == BUFLEN_16K) ? 0 : len;
382}
383
9b00eb49
IS		 384static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len)
385{
386 desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) |
387 SET_VAL(BUFDATALEN, len));
388}
389
390static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring)
391{
392 __le64 *exp_bufs;
393
394 exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS];
395 memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS);
396 ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1);
397
398 return exp_bufs;
399}
400
401static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring)
402{
403 return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS];
404}
405
e6ad7673
IS		 406static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
407 struct sk_buff *skb)
408{
409 struct device *dev = ndev_to_dev(tx_ring->ndev);
67894eec 410 struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev);
e6ad7673 411 struct xgene_enet_raw_desc *raw_desc;
9b00eb49
IS		 412 __le64 *exp_desc = NULL, *exp_bufs = NULL;
413 dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr;
414 skb_frag_t *frag;
e6ad7673 415 u16 tail = tx_ring->tail;
e3978673 416 u64 hopinfo = 0;
949c40bb 417 u32 len, hw_len;
9b00eb49
IS		 418 u8 ll = 0, nv = 0, idx = 0;
419 bool split = false;
420 u32 size, offset, ell_bytes = 0;
421 u32 i, fidx, nr_frags, count = 1;
e3978673 422 int ret;
e6ad7673
IS		 423
424 raw_desc = &tx_ring->raw_desc[tail];
9b00eb49 425 tail = (tail + 1) & (tx_ring->slots - 1);
e6ad7673
IS		 426 memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
427
e3978673
IS		 428 ret = xgene_enet_work_msg(skb, &hopinfo);
429 if (ret)
430 return ret;
431
9b00eb49
IS		 432 raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
433 hopinfo);
434
949c40bb
IS		 435 len = skb_headlen(skb);
436 hw_len = xgene_enet_encode_len(len);
437
438 dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
e6ad7673
IS		 439 if (dma_mapping_error(dev, dma_addr)) {
440 netdev_err(tx_ring->ndev, "DMA mapping error\n");
441 return -EINVAL;
442 }
443
444 /* Hardware expects descriptor in little endian format */
e6ad7673 445 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
949c40bb 446 SET_VAL(BUFDATALEN, hw_len) |
e6ad7673 447 SET_BIT(COHERENT));
949c40bb 448
9b00eb49
IS		 449 if (!skb_is_nonlinear(skb))
450 goto out;
e6ad7673 451
9b00eb49
IS		 452 /* scatter gather */
453 nv = 1;
454 exp_desc = (void *)&tx_ring->raw_desc[tail];
949c40bb 455 tail = (tail + 1) & (tx_ring->slots - 1);
9b00eb49
IS		 456 memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc));
457
458 nr_frags = skb_shinfo(skb)->nr_frags;
459 for (i = nr_frags; i < 4 ; i++)
460 exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER);
461
462 frag_dma_addr = xgene_get_frag_dma_array(tx_ring);
463
464 for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) {
465 if (!split) {
466 frag = &skb_shinfo(skb)->frags[fidx];
467 size = skb_frag_size(frag);
468 offset = 0;
469
470 pbuf_addr = skb_frag_dma_map(dev, frag, 0, size,
471 DMA_TO_DEVICE);
472 if (dma_mapping_error(dev, pbuf_addr))
473 return -EINVAL;
474
475 frag_dma_addr[fidx] = pbuf_addr;
476 fidx++;
477
478 if (size > BUFLEN_16K)
479 split = true;
480 }
481
482 if (size > BUFLEN_16K) {
483 len = BUFLEN_16K;
484 size -= BUFLEN_16K;
485 } else {
486 len = size;
487 split = false;
488 }
489
490 dma_addr = pbuf_addr + offset;
491 hw_len = xgene_enet_encode_len(len);
492
493 switch (i) {
494 case 0:
495 case 1:
496 case 2:
497 xgene_set_addr_len(exp_desc, i, dma_addr, hw_len);
498 break;
499 case 3:
500 if (split || (fidx != nr_frags)) {
501 exp_bufs = xgene_enet_get_exp_bufs(tx_ring);
502 xgene_set_addr_len(exp_bufs, idx, dma_addr,
503 hw_len);
504 idx++;
505 ell_bytes += len;
506 } else {
507 xgene_set_addr_len(exp_desc, i, dma_addr,
508 hw_len);
509 }
510 break;
511 default:
512 xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len);
513 idx++;
514 ell_bytes += len;
515 break;
516 }
517
518 if (split)
519 offset += BUFLEN_16K;
520 }
521 count++;
522
523 if (idx) {
524 ll = 1;
525 dma_addr = dma_map_single(dev, exp_bufs,
526 sizeof(u64) * MAX_EXP_BUFFS,
527 DMA_TO_DEVICE);
528 if (dma_mapping_error(dev, dma_addr)) {
529 dev_kfree_skb_any(skb);
530 return -EINVAL;
531 }
532 i = ell_bytes >> LL_BYTES_LSB_LEN;
533 exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
534 SET_VAL(LL_BYTES_MSB, i) |
535 SET_VAL(LL_LEN, idx));
536 raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes));
537 }
538
539out:
540 raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) |
541 SET_VAL(USERINFO, tx_ring->tail));
542 tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb;
107dec27 543 pdata->tx_level[tx_ring->cp_ring->index] += count;
949c40bb
IS		 544 tx_ring->tail = tail;
545
546 return count;
e6ad7673
IS		 547}
548
549static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
550 struct net_device *ndev)
551{
552 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
107dec27
IS		 553 struct xgene_enet_desc_ring *tx_ring;
554 int index = skb->queue_mapping;
555 u32 tx_level = pdata->tx_level[index];
949c40bb 556 int count;
e6ad7673 557
107dec27
IS		 558 tx_ring = pdata->tx_ring[index];
559 if (tx_level < pdata->txc_level[index])
560 tx_level += ((typeof(pdata->tx_level[index]))~0U);
67894eec 561
107dec27
IS		 562 if ((tx_level - pdata->txc_level[index]) > pdata->tx_qcnt_hi) {
563 netif_stop_subqueue(ndev, index);
e6ad7673
IS		 564 return NETDEV_TX_BUSY;
565 }
566
9b00eb49
IS		 567 if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE))
568 return NETDEV_TX_OK;
569
949c40bb 570 count = xgene_enet_setup_tx_desc(tx_ring, skb);
e3978673
IS		 571 if (count == -EBUSY)
572 return NETDEV_TX_BUSY;
573
949c40bb 574 if (count <= 0) {
e6ad7673
IS		 575 dev_kfree_skb_any(skb);
576 return NETDEV_TX_OK;
577 }
578
e6ad7673 579 skb_tx_timestamp(skb);
e6ad7673 580
3bb502f8
IS		 581 tx_ring->tx_packets++;
582 tx_ring->tx_bytes += skb->len;
e6ad7673 583
9ffad80a 584 pdata->ring_ops->wr_cmd(tx_ring, count);
e6ad7673
IS		 585 return NETDEV_TX_OK;
586}
587
0a0400c3 588static void xgene_enet_rx_csum(struct sk_buff *skb)
e6ad7673 589{
0a0400c3 590 struct net_device *ndev = skb->dev;
e6ad7673
IS		 591 struct iphdr *iph = ip_hdr(skb);
592
0a0400c3
IS		 593 if (!(ndev->features & NETIF_F_RXCSUM))
594 return;
595
596 if (skb->protocol != htons(ETH_P_IP))
597 return;
598
599 if (ip_is_fragment(iph))
600 return;
601
602 if (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)
603 return;
604
605 skb->ip_summed = CHECKSUM_UNNECESSARY;
e6ad7673
IS		 606}
607
a9380b0f
IS		 608static void xgene_enet_free_pagepool(struct xgene_enet_desc_ring *buf_pool,
609 struct xgene_enet_raw_desc *raw_desc,
610 struct xgene_enet_raw_desc *exp_desc)
611{
612 __le64 *desc = (void *)exp_desc;
613 dma_addr_t dma_addr;
614 struct device *dev;
615 struct page *page;
616 u16 slots, head;
617 u32 frag_size;
618 int i;
619
620 if (!buf_pool || !raw_desc || !exp_desc ||
621 (!GET_VAL(NV, le64_to_cpu(raw_desc->m0))))
622 return;
623
624 dev = ndev_to_dev(buf_pool->ndev);
0b801290 625 slots = buf_pool->slots - 1;
a9380b0f
IS		 626 head = buf_pool->head;
627
628 for (i = 0; i < 4; i++) {
629 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1]));
630 if (!frag_size)
631 break;
632
633 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1]));
634 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
635
636 page = buf_pool->frag_page[head];
637 put_page(page);
638
639 buf_pool->frag_page[head] = NULL;
640 head = (head + 1) & slots;
641 }
642 buf_pool->head = head;
643}
644
61c759cd
QN		 645/* Errata 10GE_10 and ENET_15 - Fix duplicated HW statistic counters */
646static bool xgene_enet_errata_10GE_10(struct sk_buff *skb, u32 len, u8 status)
647{
648 if (status == INGRESS_CRC &&
649 len >= (ETHER_STD_PACKET + 1) &&
650 len <= (ETHER_STD_PACKET + 4) &&
651 skb->protocol == htons(ETH_P_8021Q))
652 return true;
653
654 return false;
655}
656
4902a922
IS		 657/* Errata 10GE_8 and ENET_11 - allow packet with length <=64B */
658static bool xgene_enet_errata_10GE_8(struct sk_buff *skb, u32 len, u8 status)
659{
660 if (status == INGRESS_PKT_LEN && len == ETHER_MIN_PACKET) {
661 if (ntohs(eth_hdr(skb)->h_proto) < 46)
662 return true;
663 }
664
665 return false;
666}
667
e6ad7673 668static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring,
a9380b0f
IS		 669 struct xgene_enet_raw_desc *raw_desc,
670 struct xgene_enet_raw_desc *exp_desc)
e6ad7673 671{
a9380b0f
IS		 672 struct xgene_enet_desc_ring *buf_pool, *page_pool;
673 u32 datalen, frag_size, skb_index;
4902a922 674 struct xgene_enet_pdata *pdata;
e6ad7673 675 struct net_device *ndev;
a9380b0f 676 dma_addr_t dma_addr;
e6ad7673 677 struct sk_buff *skb;
a9380b0f
IS		 678 struct device *dev;
679 struct page *page;
680 u16 slots, head;
681 int i, ret = 0;
682 __le64 *desc;
e6ad7673 683 u8 status;
a9380b0f 684 bool nv;
e6ad7673
IS		 685
686 ndev = rx_ring->ndev;
4902a922 687 pdata = netdev_priv(ndev);
e6ad7673
IS		 688 dev = ndev_to_dev(rx_ring->ndev);
689 buf_pool = rx_ring->buf_pool;
a9380b0f 690 page_pool = rx_ring->page_pool;
e6ad7673
IS		 691
692 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
a9380b0f 693 XGENE_ENET_STD_MTU, DMA_FROM_DEVICE);
e6ad7673
IS		 694 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
695 skb = buf_pool->rx_skb[skb_index];
cb11c062 696 buf_pool->rx_skb[skb_index] = NULL;
e6ad7673 697
4902a922 698 datalen = xgene_enet_get_data_len(le64_to_cpu(raw_desc->m1));
e9e6faea
SG		 699
700 /* strip off CRC as HW isn't doing this */
701 nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0));
702 if (!nv)
703 datalen -= 4;
704
4902a922
IS		 705 skb_put(skb, datalen);
706 prefetch(skb->data - NET_IP_ALIGN);
707 skb->protocol = eth_type_trans(skb, ndev);
708
e6ad7673 709 /* checking for error */
11623fce 710 status = (GET_VAL(ELERR, le64_to_cpu(raw_desc->m0)) << LERR_LEN) |
3bb502f8 711 GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
11623fce 712 if (unlikely(status)) {
61c759cd
QN		 713 if (xgene_enet_errata_10GE_8(skb, datalen, status)) {
714 pdata->false_rflr++;
715 } else if (xgene_enet_errata_10GE_10(skb, datalen, status)) {
716 pdata->vlan_rjbr++;
717 } else {
4902a922
IS		 718 dev_kfree_skb_any(skb);
719 xgene_enet_free_pagepool(page_pool, raw_desc, exp_desc);
089f97c7
QN		 720 xgene_enet_parse_error(rx_ring, status);
721 rx_ring->rx_dropped++;
4902a922
IS		 722 goto out;
723 }
e6ad7673
IS		 724 }
725
e9e6faea 726 if (!nv)
a9380b0f
IS		 727 goto skip_jumbo;
728
729 slots = page_pool->slots - 1;
730 head = page_pool->head;
731 desc = (void *)exp_desc;
732
733 for (i = 0; i < 4; i++) {
734 frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1]));
735 if (!frag_size)
736 break;
737
738 dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1]));
739 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE);
740
741 page = page_pool->frag_page[head];
742 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0,
743 frag_size, PAGE_SIZE);
744
745 datalen += frag_size;
746
747 page_pool->frag_page[head] = NULL;
748 head = (head + 1) & slots;
749 }
750
751 page_pool->head = head;
752 rx_ring->npagepool -= skb_shinfo(skb)->nr_frags;
e6ad7673 753
a9380b0f 754skip_jumbo:
e6ad7673 755 skb_checksum_none_assert(skb);
0a0400c3 756 xgene_enet_rx_csum(skb);
e6ad7673 757
3bb502f8
IS		 758 rx_ring->rx_packets++;
759 rx_ring->rx_bytes += datalen;
e6ad7673 760 napi_gro_receive(&rx_ring->napi, skb);
a9380b0f 761
e6ad7673 762out:
a9380b0f
IS		 763 if (rx_ring->npagepool <= 0) {
764 ret = xgene_enet_refill_pagepool(page_pool, NUM_NXTBUFPOOL);
765 rx_ring->npagepool = NUM_NXTBUFPOOL;
766 if (ret)
767 return ret;
768 }
769
e6ad7673
IS		 770 if (--rx_ring->nbufpool == 0) {
771 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL);
772 rx_ring->nbufpool = NUM_BUFPOOL;
773 }
774
775 return ret;
776}
777
778static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc)
779{
780 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false;
781}
782
783static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
784 int budget)
785{
107dec27
IS		 786 struct net_device *ndev = ring->ndev;
787 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
9b00eb49 788 struct xgene_enet_raw_desc *raw_desc, *exp_desc;
e6ad7673
IS		 789 u16 head = ring->head;
790 u16 slots = ring->slots - 1;
67894eec
IS		 791 int ret, desc_count, count = 0, processed = 0;
792 bool is_completion;
e6ad7673
IS		 793
794 do {
795 raw_desc = &ring->raw_desc[head];
67894eec
IS		 796 desc_count = 0;
797 is_completion = false;
9b00eb49 798 exp_desc = NULL;
e6ad7673
IS		 799 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc)))
800 break;
801
ecf6ba83
IS		 802 /* read fpqnum field after dataaddr field */
803 dma_rmb();
9b00eb49
IS		 804 if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) {
805 head = (head + 1) & slots;
806 exp_desc = &ring->raw_desc[head];
807
808 if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) {
809 head = (head - 1) & slots;
810 break;
811 }
812 dma_rmb();
813 count++;
67894eec 814 desc_count++;
9b00eb49 815 }
67894eec 816 if (is_rx_desc(raw_desc)) {
a9380b0f 817 ret = xgene_enet_rx_frame(ring, raw_desc, exp_desc);
67894eec 818 } else {
e6ad7673 819 ret = xgene_enet_tx_completion(ring, raw_desc);
67894eec
IS		 820 is_completion = true;
821 }
e6ad7673 822 xgene_enet_mark_desc_slot_empty(raw_desc);
9b00eb49
IS		 823 if (exp_desc)
824 xgene_enet_mark_desc_slot_empty(exp_desc);
e6ad7673
IS		 825
826 head = (head + 1) & slots;
827 count++;
67894eec 828 desc_count++;
9b00eb49 829 processed++;
67894eec 830 if (is_completion)
107dec27 831 pdata->txc_level[ring->index] += desc_count;
e6ad7673
IS		 832
833 if (ret)
834 break;
835 } while (--budget);
836
837 if (likely(count)) {
81cefb81 838 pdata->ring_ops->wr_cmd(ring, -count);
e6ad7673
IS		 839 ring->head = head;
840
107dec27
IS		 841 if (__netif_subqueue_stopped(ndev, ring->index))
842 netif_start_subqueue(ndev, ring->index);
e6ad7673
IS		 843 }
844
9b00eb49 845 return processed;
e6ad7673
IS		 846}
847
848static int xgene_enet_napi(struct napi_struct *napi, const int budget)
849{
850 struct xgene_enet_desc_ring *ring;
851 int processed;
852
853 ring = container_of(napi, struct xgene_enet_desc_ring, napi);
854 processed = xgene_enet_process_ring(ring, budget);
855
856 if (processed != budget) {
6ad20165 857 napi_complete_done(napi, processed);
e6ad7673
IS		 858 enable_irq(ring->irq);
859 }
860
861 return processed;
862}
863
0290bd29 864static void xgene_enet_timeout(struct net_device *ndev, unsigned int txqueue)
e6ad7673
IS		 865{
866 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
107dec27
IS		 867 struct netdev_queue *txq;
868 int i;
e6ad7673 869
d0eb7458 870 pdata->mac_ops->reset(pdata);
107dec27
IS		 871
872 for (i = 0; i < pdata->txq_cnt; i++) {
873 txq = netdev_get_tx_queue(ndev, i);
5337824f 874 txq_trans_cond_update(txq);
107dec27
IS		 875 netif_tx_start_queue(txq);
876 }
e6ad7673
IS		 877}
878
cb0366b7
IS		 879static void xgene_enet_set_irq_name(struct net_device *ndev)
880{
881 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
882 struct xgene_enet_desc_ring *ring;
883 int i;
884
885 for (i = 0; i < pdata->rxq_cnt; i++) {
886 ring = pdata->rx_ring[i];
887 if (!pdata->cq_cnt) {
888 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc",
889 ndev->name);
890 } else {
891 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-%d",
892 ndev->name, i);
893 }
894 }
895
896 for (i = 0; i < pdata->cq_cnt; i++) {
897 ring = pdata->tx_ring[i]->cp_ring;
898 snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-txc-%d",
899 ndev->name, i);
900 }
901}
902
e6ad7673
IS		 903static int xgene_enet_register_irq(struct net_device *ndev)
904{
905 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
906 struct device *dev = ndev_to_dev(ndev);
6772b653 907 struct xgene_enet_desc_ring *ring;
107dec27 908 int ret = 0, i;
e6ad7673 909
cb0366b7 910 xgene_enet_set_irq_name(ndev);
107dec27
IS		 911 for (i = 0; i < pdata->rxq_cnt; i++) {
912 ring = pdata->rx_ring[i];
913 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
914 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
46a22d29 915 0, ring->irq_name, ring);
107dec27
IS		 916 if (ret) {
917 netdev_err(ndev, "Failed to request irq %s\n",
918 ring->irq_name);
919 }
920 }
6772b653 921
107dec27
IS		 922 for (i = 0; i < pdata->cq_cnt; i++) {
923 ring = pdata->tx_ring[i]->cp_ring;
b5d7a069 924 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
6772b653 925 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
46a22d29 926 0, ring->irq_name, ring);
6772b653
IS		 927 if (ret) {
928 netdev_err(ndev, "Failed to request irq %s\n",
929 ring->irq_name);
930 }
e6ad7673
IS		 931 }
932
933 return ret;
934}
935
936static void xgene_enet_free_irq(struct net_device *ndev)
937{
938 struct xgene_enet_pdata *pdata;
b5d7a069 939 struct xgene_enet_desc_ring *ring;
e6ad7673 940 struct device *dev;
107dec27 941 int i;
e6ad7673
IS		 942
943 pdata = netdev_priv(ndev);
944 dev = ndev_to_dev(ndev);
6772b653 945
107dec27
IS		 946 for (i = 0; i < pdata->rxq_cnt; i++) {
947 ring = pdata->rx_ring[i];
948 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
949 devm_free_irq(dev, ring->irq, ring);
950 }
951
952 for (i = 0; i < pdata->cq_cnt; i++) {
953 ring = pdata->tx_ring[i]->cp_ring;
b5d7a069
IS		 954 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
955 devm_free_irq(dev, ring->irq, ring);
6772b653
IS		 956 }
957}
958
959static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata)
960{
961 struct napi_struct *napi;
107dec27 962 int i;
6772b653 963
107dec27
IS		 964 for (i = 0; i < pdata->rxq_cnt; i++) {
965 napi = &pdata->rx_ring[i]->napi;
966 napi_enable(napi);
967 }
6772b653 968
107dec27
IS		 969 for (i = 0; i < pdata->cq_cnt; i++) {
970 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 971 napi_enable(napi);
972 }
973}
974
975static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata)
976{
977 struct napi_struct *napi;
107dec27 978 int i;
6772b653 979
107dec27
IS		 980 for (i = 0; i < pdata->rxq_cnt; i++) {
981 napi = &pdata->rx_ring[i]->napi;
982 napi_disable(napi);
983 }
6772b653 984
107dec27
IS		 985 for (i = 0; i < pdata->cq_cnt; i++) {
986 napi = &pdata->tx_ring[i]->cp_ring->napi;
6772b653
IS		 987 napi_disable(napi);
988 }
e6ad7673
IS		 989}
990
991static int xgene_enet_open(struct net_device *ndev)
992{
993 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3cdb7309 994 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
e6ad7673
IS		 995 int ret;
996
107dec27
IS		 997 ret = netif_set_real_num_tx_queues(ndev, pdata->txq_cnt);
998 if (ret)
999 return ret;
1000
1001 ret = netif_set_real_num_rx_queues(ndev, pdata->rxq_cnt);
1002 if (ret)
1003 return ret;
1004
aeb20b6b 1005 xgene_enet_napi_enable(pdata);
e6ad7673 1006 ret = xgene_enet_register_irq(ndev);
ce9e57fe
ZS		 1007 if (ret) {
1008 xgene_enet_napi_disable(pdata);
e6ad7673 1009 return ret;
ce9e57fe 1010 }
e6ad7673 1011
971d3a44
PR		 1012 if (ndev->phydev) {
1013 phy_start(ndev->phydev);
47c62b6d 1014 } else {
0148d38d 1015 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
9a8c5dde
IS		 1016 netif_carrier_off(ndev);
1017 }
e6ad7673 1018
cb11c062
IS		 1019 mac_ops->tx_enable(pdata);
1020 mac_ops->rx_enable(pdata);
cb0366b7 1021 netif_tx_start_all_queues(ndev);
e6ad7673
IS		 1022
1023 return ret;
1024}
1025
1026static int xgene_enet_close(struct net_device *ndev)
1027{
1028 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3cdb7309 1029 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
107dec27 1030 int i;
e6ad7673 1031
cb0366b7 1032 netif_tx_stop_all_queues(ndev);
cb11c062
IS		 1033 mac_ops->tx_disable(pdata);
1034 mac_ops->rx_disable(pdata);
e6ad7673 1035
971d3a44
PR		 1036 if (ndev->phydev)
1037 phy_stop(ndev->phydev);
0148d38d
IS		 1038 else
1039 cancel_delayed_work_sync(&pdata->link_work);
e6ad7673 1040
aeb20b6b
IS		 1041 xgene_enet_free_irq(ndev);
1042 xgene_enet_napi_disable(pdata);
107dec27
IS		 1043 for (i = 0; i < pdata->rxq_cnt; i++)
1044 xgene_enet_process_ring(pdata->rx_ring[i], -1);
aeb20b6b 1045
e6ad7673
IS		 1046 return 0;
1047}
e6ad7673
IS		 1048static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring)
1049{
1050 struct xgene_enet_pdata *pdata;
1051 struct device *dev;
1052
1053 pdata = netdev_priv(ring->ndev);
1054 dev = ndev_to_dev(ring->ndev);
1055
81cefb81 1056 pdata->ring_ops->clear(ring);
cb0366b7 1057 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
e6ad7673
IS		 1058}
1059
1060static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata)
1061{
a9380b0f 1062 struct xgene_enet_desc_ring *buf_pool, *page_pool;
107dec27
IS		 1063 struct xgene_enet_desc_ring *ring;
1064 int i;
e6ad7673 1065
107dec27
IS		 1066 for (i = 0; i < pdata->txq_cnt; i++) {
1067 ring = pdata->tx_ring[i];
1068 if (ring) {
1069 xgene_enet_delete_ring(ring);
cb11c062
IS		 1070 pdata->port_ops->clear(pdata, ring);
1071 if (pdata->cq_cnt)
1072 xgene_enet_delete_ring(ring->cp_ring);
107dec27
IS		 1073 pdata->tx_ring[i] = NULL;
1074 }
a9380b0f 1075
e6ad7673
IS		 1076 }
1077
107dec27
IS		 1078 for (i = 0; i < pdata->rxq_cnt; i++) {
1079 ring = pdata->rx_ring[i];
1080 if (ring) {
a9380b0f
IS		 1081 page_pool = ring->page_pool;
1082 if (page_pool) {
1083 xgene_enet_delete_pagepool(page_pool);
1084 xgene_enet_delete_ring(page_pool);
1085 pdata->port_ops->clear(pdata, page_pool);
1086 }
1087
107dec27
IS		 1088 buf_pool = ring->buf_pool;
1089 xgene_enet_delete_bufpool(buf_pool);
1090 xgene_enet_delete_ring(buf_pool);
cb11c062 1091 pdata->port_ops->clear(pdata, buf_pool);
a9380b0f 1092
107dec27
IS		 1093 xgene_enet_delete_ring(ring);
1094 pdata->rx_ring[i] = NULL;
1095 }
a9380b0f 1096
e6ad7673
IS		 1097 }
1098}
1099
1100static int xgene_enet_get_ring_size(struct device *dev,
1101 enum xgene_enet_ring_cfgsize cfgsize)
1102{
1103 int size = -EINVAL;
1104
1105 switch (cfgsize) {
1106 case RING_CFGSIZE_512B:
1107 size = 0x200;
1108 break;
1109 case RING_CFGSIZE_2KB:
1110 size = 0x800;
1111 break;
1112 case RING_CFGSIZE_16KB:
1113 size = 0x4000;
1114 break;
1115 case RING_CFGSIZE_64KB:
1116 size = 0x10000;
1117 break;
1118 case RING_CFGSIZE_512KB:
1119 size = 0x80000;
1120 break;
1121 default:
1122 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize);
1123 break;
1124 }
1125
1126 return size;
1127}
1128
1129static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring)
1130{
81cefb81 1131 struct xgene_enet_pdata *pdata;
e6ad7673
IS		 1132 struct device *dev;
1133
1134 if (!ring)
1135 return;
1136
1137 dev = ndev_to_dev(ring->ndev);
81cefb81 1138 pdata = netdev_priv(ring->ndev);
e6ad7673
IS		 1139
1140 if (ring->desc_addr) {
81cefb81 1141 pdata->ring_ops->clear(ring);
cb0366b7 1142 dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
e6ad7673
IS		 1143 }
1144 devm_kfree(dev, ring);
1145}
1146
1147static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata)
1148{
a9380b0f 1149 struct xgene_enet_desc_ring *page_pool;
e6ad7673
IS		 1150 struct device *dev = &pdata->pdev->dev;
1151 struct xgene_enet_desc_ring *ring;
a9380b0f 1152 void *p;
107dec27 1153 int i;
e6ad7673 1154
107dec27
IS		 1155 for (i = 0; i < pdata->txq_cnt; i++) {
1156 ring = pdata->tx_ring[i];
1157 if (ring) {
1158 if (ring->cp_ring && ring->cp_ring->cp_skb)
1159 devm_kfree(dev, ring->cp_ring->cp_skb);
a9380b0f 1160
107dec27
IS		 1161 if (ring->cp_ring && pdata->cq_cnt)
1162 xgene_enet_free_desc_ring(ring->cp_ring);
a9380b0f 1163
107dec27
IS		 1164 xgene_enet_free_desc_ring(ring);
1165 }
a9380b0f 1166
107dec27
IS		 1167 }
1168
1169 for (i = 0; i < pdata->rxq_cnt; i++) {
1170 ring = pdata->rx_ring[i];
1171 if (ring) {
1172 if (ring->buf_pool) {
1173 if (ring->buf_pool->rx_skb)
1174 devm_kfree(dev, ring->buf_pool->rx_skb);
a9380b0f 1175
107dec27
IS		 1176 xgene_enet_free_desc_ring(ring->buf_pool);
1177 }
a9380b0f
IS		 1178
1179 page_pool = ring->page_pool;
1180 if (page_pool) {
1181 p = page_pool->frag_page;
1182 if (p)
1183 devm_kfree(dev, p);
1184
1185 p = page_pool->frag_dma_addr;
1186 if (p)
1187 devm_kfree(dev, p);
1188 }
1189
107dec27 1190 xgene_enet_free_desc_ring(ring);
c10e4caf 1191 }
c10e4caf 1192 }
e6ad7673
IS		 1193}
1194
bc1b7c13
IS		 1195static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata,
1196 struct xgene_enet_desc_ring *ring)
1197{
1198 if ((pdata->enet_id == XGENE_ENET2) &&
1199 (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) {
1200 return true;
1201 }
1202
1203 return false;
1204}
1205
1206static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata,
1207 struct xgene_enet_desc_ring *ring)
1208{
1209 u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift;
1210
1211 return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift);
1212}
1213
e6ad7673
IS		 1214static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
1215 struct net_device *ndev, u32 ring_num,
1216 enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
1217{
e6ad7673
IS		 1218 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1219 struct device *dev = ndev_to_dev(ndev);
cb0366b7
IS		 1220 struct xgene_enet_desc_ring *ring;
1221 void *irq_mbox_addr;
9b9ba821
TK		 1222 int size;
1223
1224 size = xgene_enet_get_ring_size(dev, cfgsize);
1225 if (size < 0)
1226 return NULL;
e6ad7673
IS		 1227
1228 ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring),
1229 GFP_KERNEL);
1230 if (!ring)
1231 return NULL;
1232
1233 ring->ndev = ndev;
1234 ring->num = ring_num;
1235 ring->cfgsize = cfgsize;
1236 ring->id = ring_id;
1237
cb0366b7
IS		 1238 ring->desc_addr = dmam_alloc_coherent(dev, size, &ring->dma,
1239 GFP_KERNEL | __GFP_ZERO);
e6ad7673
IS		 1240 if (!ring->desc_addr) {
1241 devm_kfree(dev, ring);
1242 return NULL;
1243 }
1244 ring->size = size;
1245
bc1b7c13 1246 if (is_irq_mbox_required(pdata, ring)) {
cb0366b7
IS		 1247 irq_mbox_addr = dmam_alloc_coherent(dev, INTR_MBOX_SIZE,
1248 &ring->irq_mbox_dma,
1249 GFP_KERNEL | __GFP_ZERO);
1250 if (!irq_mbox_addr) {
1251 dmam_free_coherent(dev, size, ring->desc_addr,
1252 ring->dma);
bc1b7c13
IS		 1253 devm_kfree(dev, ring);
1254 return NULL;
1255 }
cb0366b7 1256 ring->irq_mbox_addr = irq_mbox_addr;
bc1b7c13
IS		 1257 }
1258
1259 ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring);
e6ad7673 1260 ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
81cefb81 1261 ring = pdata->ring_ops->setup(ring);
e6ad7673
IS		 1262 netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
1263 ring->num, ring->size, ring->id, ring->slots);
1264
1265 return ring;
1266}
1267
1268static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum)
1269{
1270 return (owner << 6) | (bufnum & GENMASK(5, 0));
1271}
1272
bc1b7c13
IS		 1273static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p)
1274{
1275 enum xgene_ring_owner owner;
1276
1277 if (p->enet_id == XGENE_ENET1) {
1278 switch (p->phy_mode) {
1279 case PHY_INTERFACE_MODE_SGMII:
1280 owner = RING_OWNER_ETH0;
1281 break;
1282 default:
1283 owner = (!p->port_id) ? RING_OWNER_ETH0 :
1284 RING_OWNER_ETH1;
1285 break;
1286 }
1287 } else {
1288 owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1;
1289 }
1290
1291 return owner;
1292}
1293
2a37daa6
IS		 1294static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata)
1295{
1296 struct device *dev = &pdata->pdev->dev;
1297 u32 cpu_bufnum;
1298 int ret;
1299
1300 ret = device_property_read_u32(dev, "channel", &cpu_bufnum);
1301
1302 return (!ret) ? cpu_bufnum : pdata->cpu_bufnum;
1303}
1304
e6ad7673
IS		 1305static int xgene_enet_create_desc_rings(struct net_device *ndev)
1306{
e6ad7673 1307 struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
a9380b0f
IS		 1308 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1309 struct xgene_enet_desc_ring *page_pool = NULL;
e6ad7673 1310 struct xgene_enet_desc_ring *buf_pool = NULL;
a9380b0f 1311 struct device *dev = ndev_to_dev(ndev);
ca626454
KC		 1312 u8 eth_bufnum = pdata->eth_bufnum;
1313 u8 bp_bufnum = pdata->bp_bufnum;
1314 u16 ring_num = pdata->ring_num;
a9380b0f
IS		 1315 enum xgene_ring_owner owner;
1316 dma_addr_t dma_exp_bufs;
1317 u16 ring_id, slots;
cb0366b7 1318 __le64 *exp_bufs;
107dec27 1319 int i, ret, size;
a9380b0f 1320 u8 cpu_bufnum;
e6ad7673 1321
2a37daa6
IS		 1322 cpu_bufnum = xgene_start_cpu_bufnum(pdata);
1323
107dec27
IS		 1324 for (i = 0; i < pdata->rxq_cnt; i++) {
1325 /* allocate rx descriptor ring */
1326 owner = xgene_derive_ring_owner(pdata);
1327 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
1328 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1329 RING_CFGSIZE_16KB,
1330 ring_id);
1331 if (!rx_ring) {
1332 ret = -ENOMEM;
1333 goto err;
1334 }
e6ad7673 1335
107dec27
IS		 1336 /* allocate buffer pool for receiving packets */
1337 owner = xgene_derive_ring_owner(pdata);
1338 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1339 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
a9380b0f 1340 RING_CFGSIZE_16KB,
107dec27
IS		 1341 ring_id);
1342 if (!buf_pool) {
1343 ret = -ENOMEM;
1344 goto err;
1345 }
9b00eb49 1346
107dec27 1347 rx_ring->nbufpool = NUM_BUFPOOL;
a9380b0f 1348 rx_ring->npagepool = NUM_NXTBUFPOOL;
107dec27 1349 rx_ring->irq = pdata->irqs[i];
107dec27
IS		 1350 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots,
1351 sizeof(struct sk_buff *),
9b00eb49 1352 GFP_KERNEL);
107dec27
IS		 1353 if (!buf_pool->rx_skb) {
1354 ret = -ENOMEM;
1355 goto err;
1356 }
9b00eb49 1357
107dec27
IS		 1358 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool);
1359 rx_ring->buf_pool = buf_pool;
1360 pdata->rx_ring[i] = rx_ring;
a9380b0f
IS		 1361
1362 if ((pdata->enet_id == XGENE_ENET1 && pdata->rxq_cnt > 4) ||
1363 (pdata->enet_id == XGENE_ENET2 && pdata->rxq_cnt > 16)) {
1364 break;
1365 }
1366
1367 /* allocate next buffer pool for jumbo packets */
1368 owner = xgene_derive_ring_owner(pdata);
1369 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
1370 page_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
1371 RING_CFGSIZE_16KB,
1372 ring_id);
1373 if (!page_pool) {
1374 ret = -ENOMEM;
1375 goto err;
1376 }
1377
1378 slots = page_pool->slots;
1379 page_pool->frag_page = devm_kcalloc(dev, slots,
1380 sizeof(struct page *),
1381 GFP_KERNEL);
1382 if (!page_pool->frag_page) {
1383 ret = -ENOMEM;
1384 goto err;
1385 }
1386
1387 page_pool->frag_dma_addr = devm_kcalloc(dev, slots,
1388 sizeof(dma_addr_t),
1389 GFP_KERNEL);
1390 if (!page_pool->frag_dma_addr) {
1391 ret = -ENOMEM;
1392 goto err;
1393 }
1394
1395 page_pool->dst_ring_num = xgene_enet_dst_ring_num(page_pool);
1396 rx_ring->page_pool = page_pool;
107dec27 1397 }
e6ad7673 1398
107dec27
IS		 1399 for (i = 0; i < pdata->txq_cnt; i++) {
1400 /* allocate tx descriptor ring */
1401 owner = xgene_derive_ring_owner(pdata);
1402 ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++);
1403 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
6772b653
IS		 1404 RING_CFGSIZE_16KB,
1405 ring_id);
107dec27 1406 if (!tx_ring) {
6772b653
IS		 1407 ret = -ENOMEM;
1408 goto err;
1409 }
6772b653 1410
107dec27 1411 size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS;
cb0366b7
IS		 1412 exp_bufs = dmam_alloc_coherent(dev, size, &dma_exp_bufs,
1413 GFP_KERNEL | __GFP_ZERO);
1414 if (!exp_bufs) {
107dec27
IS		 1415 ret = -ENOMEM;
1416 goto err;
1417 }
cb0366b7 1418 tx_ring->exp_bufs = exp_bufs;
9b00eb49 1419
107dec27
IS		 1420 pdata->tx_ring[i] = tx_ring;
1421
1422 if (!pdata->cq_cnt) {
1423 cp_ring = pdata->rx_ring[i];
1424 } else {
1425 /* allocate tx completion descriptor ring */
1426 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU,
1427 cpu_bufnum++);
1428 cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1429 RING_CFGSIZE_16KB,
1430 ring_id);
1431 if (!cp_ring) {
1432 ret = -ENOMEM;
1433 goto err;
1434 }
9b00eb49 1435
107dec27
IS		 1436 cp_ring->irq = pdata->irqs[pdata->rxq_cnt + i];
1437 cp_ring->index = i;
107dec27
IS		 1438 }
1439
1440 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots,
1441 sizeof(struct sk_buff *),
1442 GFP_KERNEL);
1443 if (!cp_ring->cp_skb) {
1444 ret = -ENOMEM;
1445 goto err;
1446 }
e6ad7673 1447
107dec27
IS		 1448 size = sizeof(dma_addr_t) * MAX_SKB_FRAGS;
1449 cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots,
1450 size, GFP_KERNEL);
1451 if (!cp_ring->frag_dma_addr) {
1452 devm_kfree(dev, cp_ring->cp_skb);
1453 ret = -ENOMEM;
1454 goto err;
1455 }
1456
1457 tx_ring->cp_ring = cp_ring;
1458 tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring);
1459 }
1460
b5a4a3eb
IS		 1461 if (pdata->ring_ops->coalesce)
1462 pdata->ring_ops->coalesce(pdata->tx_ring[0]);
107dec27 1463 pdata->tx_qcnt_hi = pdata->tx_ring[0]->slots - 128;
e6ad7673
IS		 1464
1465 return 0;
1466
1467err:
1468 xgene_enet_free_desc_rings(pdata);
1469 return ret;
1470}
1471
bc1f4470 1472static void xgene_enet_get_stats64(
e6ad7673 1473 struct net_device *ndev,
3f5a2ef1 1474 struct rtnl_link_stats64 *stats)
e6ad7673
IS		 1475{
1476 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
3bb502f8
IS		 1477 struct xgene_enet_desc_ring *ring;
1478 int i;
e6ad7673 1479
3bb502f8
IS		 1480 for (i = 0; i < pdata->txq_cnt; i++) {
1481 ring = pdata->tx_ring[i];
1482 if (ring) {
1483 stats->tx_packets += ring->tx_packets;
1484 stats->tx_bytes += ring->tx_bytes;
089f97c7
QN		 1485 stats->tx_dropped += ring->tx_dropped;
1486 stats->tx_errors += ring->tx_errors;
3bb502f8
IS		 1487 }
1488 }
e6ad7673 1489
3bb502f8
IS		 1490 for (i = 0; i < pdata->rxq_cnt; i++) {
1491 ring = pdata->rx_ring[i];
1492 if (ring) {
1493 stats->rx_packets += ring->rx_packets;
1494 stats->rx_bytes += ring->rx_bytes;
089f97c7
QN		 1495 stats->rx_dropped += ring->rx_dropped;
1496 stats->rx_errors += ring->rx_errors +
1497 ring->rx_length_errors +
3bb502f8
IS		 1498 ring->rx_crc_errors +
1499 ring->rx_frame_errors +
1500 ring->rx_fifo_errors;
089f97c7
QN		 1501 stats->rx_length_errors += ring->rx_length_errors;
1502 stats->rx_crc_errors += ring->rx_crc_errors;
1503 stats->rx_frame_errors += ring->rx_frame_errors;
1504 stats->rx_fifo_errors += ring->rx_fifo_errors;
3bb502f8
IS		 1505 }
1506 }
e6ad7673
IS		 1507}
1508
1509static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr)
1510{
1511 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1512 int ret;
1513
1514 ret = eth_mac_addr(ndev, addr);
1515 if (ret)
1516 return ret;
d0eb7458 1517 pdata->mac_ops->set_mac_addr(pdata);
e6ad7673
IS		 1518
1519 return ret;
1520}
1521
350b4e33
IS		 1522static int xgene_change_mtu(struct net_device *ndev, int new_mtu)
1523{
1524 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1525 int frame_size;
1526
1527 if (!netif_running(ndev))
1528 return 0;
1529
1530 frame_size = (new_mtu > ETH_DATA_LEN) ? (new_mtu + 18) : 0x600;
1531
1532 xgene_enet_close(ndev);
1eb2cded 1533 WRITE_ONCE(ndev->mtu, new_mtu);
350b4e33
IS		 1534 pdata->mac_ops->set_framesize(pdata, frame_size);
1535 xgene_enet_open(ndev);
1536
1537 return 0;
1538}
1539
e6ad7673
IS		 1540static const struct net_device_ops xgene_ndev_ops = {
1541 .ndo_open = xgene_enet_open,
1542 .ndo_stop = xgene_enet_close,
1543 .ndo_start_xmit = xgene_enet_start_xmit,
1544 .ndo_tx_timeout = xgene_enet_timeout,
1545 .ndo_get_stats64 = xgene_enet_get_stats64,
350b4e33 1546 .ndo_change_mtu = xgene_change_mtu,
e6ad7673
IS		 1547 .ndo_set_mac_address = xgene_enet_set_mac_address,
1548};
1549
8beeef8d 1550#ifdef CONFIG_ACPI
724fe695 1551static void xgene_get_port_id_acpi(struct device *dev,
0738c54d
ST		 1552 struct xgene_enet_pdata *pdata)
1553{
1554 acpi_status status;
1555 u64 temp;
1556
1557 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp);
1558 if (ACPI_FAILURE(status)) {
1559 pdata->port_id = 0;
1560 } else {
1561 pdata->port_id = temp;
1562 }
1563
724fe695 1564 return;
0738c54d 1565}
8beeef8d 1566#endif
0738c54d 1567
724fe695 1568static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata)
ca626454
KC		 1569{
1570 u32 id = 0;
ca626454 1571
724fe695 1572 of_property_read_u32(dev->of_node, "port-id", &id);
ca626454 1573
724fe695
SS		 1574 pdata->port_id = id & BIT(0);
1575
1576 return;
ca626454
KC		 1577}
1578
16615a4c
IS		 1579static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata)
1580{
1581 struct device *dev = &pdata->pdev->dev;
1582 int delay, ret;
1583
9d7e72c0 1584 ret = device_property_read_u32(dev, "tx-delay", &delay);
16615a4c
IS		 1585 if (ret) {
1586 pdata->tx_delay = 4;
1587 return 0;
1588 }
1589
1590 if (delay < 0 || delay > 7) {
1591 dev_err(dev, "Invalid tx-delay specified\n");
1592 return -EINVAL;
1593 }
1594
1595 pdata->tx_delay = delay;
1596
1597 return 0;
1598}
1599
1600static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata)
1601{
1602 struct device *dev = &pdata->pdev->dev;
1603 int delay, ret;
1604
9d7e72c0 1605 ret = device_property_read_u32(dev, "rx-delay", &delay);
16615a4c
IS		 1606 if (ret) {
1607 pdata->rx_delay = 2;
1608 return 0;
1609 }
1610
1611 if (delay < 0 || delay > 7) {
1612 dev_err(dev, "Invalid rx-delay specified\n");
1613 return -EINVAL;
1614 }
1615
1616 pdata->rx_delay = delay;
1617
1618 return 0;
1619}
de7b5b3d 1620
107dec27
IS		 1621static int xgene_enet_get_irqs(struct xgene_enet_pdata *pdata)
1622{
1623 struct platform_device *pdev = pdata->pdev;
107dec27
IS		 1624 int i, ret, max_irqs;
1625
326dde3e 1626 if (phy_interface_mode_is_rgmii(pdata->phy_mode))
107dec27
IS		 1627 max_irqs = 1;
1628 else if (pdata->phy_mode == PHY_INTERFACE_MODE_SGMII)
1629 max_irqs = 2;
1630 else
1631 max_irqs = XGENE_MAX_ENET_IRQ;
1632
1633 for (i = 0; i < max_irqs; i++) {
1634 ret = platform_get_irq(pdev, i);
c1e9e5e0 1635 if (ret < 0) {
1b090a48
IS		 1636 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1637 max_irqs = i;
1638 pdata->rxq_cnt = max_irqs / 2;
1639 pdata->txq_cnt = max_irqs / 2;
1640 pdata->cq_cnt = max_irqs / 2;
1641 break;
1642 }
c1e9e5e0 1643 return ret;
107dec27
IS		 1644 }
1645 pdata->irqs[i] = ret;
1646 }
1647
1648 return 0;
1649}
1650
183db481 1651static void xgene_enet_check_phy_handle(struct xgene_enet_pdata *pdata)
8089a96f
IS		 1652{
1653 int ret;
1654
1655 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII)
183db481 1656 return;
8089a96f
IS		 1657
1658 if (!IS_ENABLED(CONFIG_MDIO_XGENE))
183db481 1659 return;
8089a96f
IS		 1660
1661 ret = xgene_enet_phy_connect(pdata->ndev);
1662 if (!ret)
1663 pdata->mdio_driver = true;
8089a96f
IS		 1664}
1665
27ecf87c
IS		 1666static void xgene_enet_gpiod_get(struct xgene_enet_pdata *pdata)
1667{
1668 struct device *dev = &pdata->pdev->dev;
1669
751d6fd1
IS		 1670 pdata->sfp_gpio_en = false;
1671 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII ||
1672 (!device_property_present(dev, "sfp-gpios") &&
1673 !device_property_present(dev, "rxlos-gpios")))
27ecf87c
IS		 1674 return;
1675
751d6fd1 1676 pdata->sfp_gpio_en = true;
27ecf87c
IS		 1677 pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN);
1678 if (IS_ERR(pdata->sfp_rdy))
1679 pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN);
1680}
1681
e6ad7673
IS		 1682static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
1683{
1684 struct platform_device *pdev;
1685 struct net_device *ndev;
1686 struct device *dev;
1687 struct resource *res;
1688 void __iomem *base_addr;
561fea6d 1689 u32 offset;
2e598712 1690 int ret = 0;
e6ad7673
IS		 1691
1692 pdev = pdata->pdev;
1693 dev = &pdev->dev;
1694 ndev = pdata->ndev;
1695
de7b5b3d
FK		 1696 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR);
1697 if (!res) {
1698 dev_err(dev, "Resource enet_csr not defined\n");
1699 return -ENODEV;
1700 }
1701 pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res));
3ec7a176 1702 if (!pdata->base_addr) {
e6ad7673 1703 dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
3ec7a176 1704 return -ENOMEM;
e6ad7673
IS		 1705 }
1706
de7b5b3d
FK		 1707 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR);
1708 if (!res) {
1709 dev_err(dev, "Resource ring_csr not defined\n");
1710 return -ENODEV;
1711 }
1712 pdata->ring_csr_addr = devm_ioremap(dev, res->start,
1713 resource_size(res));
3ec7a176 1714 if (!pdata->ring_csr_addr) {
e6ad7673 1715 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n");
3ec7a176 1716 return -ENOMEM;
e6ad7673
IS		 1717 }
1718
de7b5b3d
FK		 1719 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD);
1720 if (!res) {
1721 dev_err(dev, "Resource ring_cmd not defined\n");
1722 return -ENODEV;
1723 }
1724 pdata->ring_cmd_addr = devm_ioremap(dev, res->start,
1725 resource_size(res));
3ec7a176 1726 if (!pdata->ring_cmd_addr) {
e6ad7673 1727 dev_err(dev, "Unable to retrieve ENET Ring command region\n");
3ec7a176 1728 return -ENOMEM;
e6ad7673
IS		 1729 }
1730
0738c54d 1731 if (dev->of_node)
724fe695 1732 xgene_get_port_id_dt(dev, pdata);
0738c54d
ST		 1733#ifdef CONFIG_ACPI
1734 else
724fe695 1735 xgene_get_port_id_acpi(dev, pdata);
0738c54d 1736#endif
ca626454 1737
b8eeac56 1738 if (device_get_ethdev_address(dev, ndev))
e6ad7673 1739 eth_hw_addr_random(ndev);
de7b5b3d 1740
e6ad7673
IS		 1741 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
1742
938049e1 1743 pdata->phy_mode = device_get_phy_mode(dev);
e6ad7673 1744 if (pdata->phy_mode < 0) {
0148d38d
IS		 1745 dev_err(dev, "Unable to get phy-connection-type\n");
1746 return pdata->phy_mode;
1747 }
326dde3e 1748 if (!phy_interface_mode_is_rgmii(pdata->phy_mode) &&
32f784b5 1749 pdata->phy_mode != PHY_INTERFACE_MODE_SGMII &&
0148d38d
IS		 1750 pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
1751 dev_err(dev, "Incorrect phy-connection-type specified\n");
1752 return -ENODEV;
e6ad7673
IS		 1753 }
1754
16615a4c
IS		 1755 ret = xgene_get_tx_delay(pdata);
1756 if (ret)
1757 return ret;
1758
1759 ret = xgene_get_rx_delay(pdata);
1760 if (ret)
1761 return ret;
1762
107dec27
IS		 1763 ret = xgene_enet_get_irqs(pdata);
1764 if (ret)
6772b653 1765 return ret;
6772b653 1766
27ecf87c
IS		 1767 xgene_enet_gpiod_get(pdata);
1768
aaf83aec
TB		 1769 pdata->clk = devm_clk_get(&pdev->dev, NULL);
1770 if (IS_ERR(pdata->clk)) {
1771 if (pdata->phy_mode != PHY_INTERFACE_MODE_SGMII) {
0db01097
TB		 1772 /* Abort if the clock is defined but couldn't be
1773 * retrived. Always abort if the clock is missing on
1774 * DT system as the driver can't cope with this case.
1775 */
1776 if (PTR_ERR(pdata->clk) != -ENOENT || dev->of_node)
1777 return PTR_ERR(pdata->clk);
1778 /* Firmware may have set up the clock already. */
1779 dev_info(dev, "clocks have been setup already\n");
1780 }
e6ad7673
IS		 1781 }
1782
bc1b7c13
IS		 1783 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII)
1784 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET);
1785 else
1786 base_addr = pdata->base_addr;
e6ad7673 1787 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
76f94a9c 1788 pdata->cle.base = base_addr + BLOCK_ETH_CLE_CSR_OFFSET;
e6ad7673
IS		 1789 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
1790 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
326dde3e 1791 if (phy_interface_mode_is_rgmii(pdata->phy_mode) ||
32f784b5 1792 pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) {
ca626454 1793 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET;
2d07d8e4
QN		 1794 pdata->mcx_stats_addr =
1795 pdata->base_addr + BLOCK_ETH_STATS_OFFSET;
561fea6d
IS		 1796 offset = (pdata->enet_id == XGENE_ENET1) ?
1797 BLOCK_ETH_MAC_CSR_OFFSET :
1798 X2_BLOCK_ETH_MAC_CSR_OFFSET;
1799 pdata->mcx_mac_csr_addr = base_addr + offset;
0148d38d
IS		 1800 } else {
1801 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
2d07d8e4 1802 pdata->mcx_stats_addr = base_addr + BLOCK_AXG_STATS_OFFSET;
0148d38d 1803 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
3eb7cb9d 1804 pdata->pcs_addr = base_addr + BLOCK_PCS_OFFSET;
0148d38d 1805 }
e6ad7673
IS		 1806 pdata->rx_buff_cnt = NUM_PKT_BUF;
1807
0148d38d 1808 return 0;
e6ad7673
IS		 1809}
1810
1811static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
1812{
76f94a9c 1813 struct xgene_enet_cle *enet_cle = &pdata->cle;
d6d48969 1814 struct xgene_enet_desc_ring *page_pool;
e6ad7673
IS		 1815 struct net_device *ndev = pdata->ndev;
1816 struct xgene_enet_desc_ring *buf_pool;
d6d48969 1817 u16 dst_ring_num, ring_id;
107dec27 1818 int i, ret;
a9380b0f 1819 u32 count;
e6ad7673 1820
c3f4465d
IS		 1821 ret = pdata->port_ops->reset(pdata);
1822 if (ret)
1823 return ret;
e6ad7673
IS		 1824
1825 ret = xgene_enet_create_desc_rings(ndev);
1826 if (ret) {
1827 netdev_err(ndev, "Error in ring configuration\n");
1828 return ret;
1829 }
1830
1831 /* setup buffer pool */
107dec27
IS		 1832 for (i = 0; i < pdata->rxq_cnt; i++) {
1833 buf_pool = pdata->rx_ring[i]->buf_pool;
1834 xgene_enet_init_bufpool(buf_pool);
a9380b0f
IS		 1835 page_pool = pdata->rx_ring[i]->page_pool;
1836 xgene_enet_init_bufpool(page_pool);
1837
1838 count = pdata->rx_buff_cnt;
1839 ret = xgene_enet_refill_bufpool(buf_pool, count);
15e32296
IS		 1840 if (ret)
1841 goto err;
a9380b0f
IS		 1842
1843 ret = xgene_enet_refill_pagepool(page_pool, count);
1844 if (ret)
1845 goto err;
1846
e6ad7673
IS		 1847 }
1848
107dec27
IS		 1849 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1850 buf_pool = pdata->rx_ring[0]->buf_pool;
76f94a9c
IS		 1851 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1852 /* Initialize and Enable PreClassifier Tree */
1853 enet_cle->max_nodes = 512;
1854 enet_cle->max_dbptrs = 1024;
1855 enet_cle->parsers = 3;
1856 enet_cle->active_parser = PARSER_ALL;
1857 enet_cle->ptree.start_node = 0;
1858 enet_cle->ptree.start_dbptr = 0;
1859 enet_cle->jump_bytes = 8;
1860 ret = pdata->cle_ops->cle_init(pdata);
1861 if (ret) {
1862 netdev_err(ndev, "Preclass Tree init error\n");
15e32296 1863 goto err;
76f94a9c 1864 }
d6d48969 1865
76f94a9c 1866 } else {
d6d48969
IS		 1867 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
1868 buf_pool = pdata->rx_ring[0]->buf_pool;
1869 page_pool = pdata->rx_ring[0]->page_pool;
1870 ring_id = (page_pool) ? page_pool->id : 0;
1871 pdata->port_ops->cle_bypass(pdata, dst_ring_num,
1872 buf_pool->id, ring_id);
76f94a9c
IS		 1873 }
1874
350b4e33 1875 ndev->max_mtu = XGENE_ENET_MAX_MTU;
9a8c5dde 1876 pdata->phy_speed = SPEED_UNKNOWN;
0148d38d 1877 pdata->mac_ops->init(pdata);
e6ad7673
IS		 1878
1879 return ret;
15e32296
IS		 1880
1881err:
1882 xgene_enet_delete_desc_rings(pdata);
1883 return ret;
e6ad7673
IS		 1884}
1885
d0eb7458
IS		 1886static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
1887{
0148d38d
IS		 1888 switch (pdata->phy_mode) {
1889 case PHY_INTERFACE_MODE_RGMII:
326dde3e
IS		 1890 case PHY_INTERFACE_MODE_RGMII_ID:
1891 case PHY_INTERFACE_MODE_RGMII_RXID:
1892 case PHY_INTERFACE_MODE_RGMII_TXID:
0148d38d
IS		 1893 pdata->mac_ops = &xgene_gmac_ops;
1894 pdata->port_ops = &xgene_gport_ops;
dc8385f0 1895 pdata->rm = RM3;
107dec27
IS		 1896 pdata->rxq_cnt = 1;
1897 pdata->txq_cnt = 1;
1898 pdata->cq_cnt = 0;
0148d38d 1899 break;
32f784b5
IS		 1900 case PHY_INTERFACE_MODE_SGMII:
1901 pdata->mac_ops = &xgene_sgmac_ops;
1902 pdata->port_ops = &xgene_sgport_ops;
1903 pdata->rm = RM1;
107dec27
IS		 1904 pdata->rxq_cnt = 1;
1905 pdata->txq_cnt = 1;
1906 pdata->cq_cnt = 1;
32f784b5 1907 break;
0148d38d
IS		 1908 default:
1909 pdata->mac_ops = &xgene_xgmac_ops;
1910 pdata->port_ops = &xgene_xgport_ops;
76f94a9c 1911 pdata->cle_ops = &xgene_cle3in_ops;
dc8385f0 1912 pdata->rm = RM0;
1b090a48
IS		 1913 if (!pdata->rxq_cnt) {
1914 pdata->rxq_cnt = XGENE_NUM_RX_RING;
1915 pdata->txq_cnt = XGENE_NUM_TX_RING;
1916 pdata->cq_cnt = XGENE_NUM_TXC_RING;
1917 }
0148d38d
IS		 1918 break;
1919 }
ca626454 1920
bc1b7c13
IS		 1921 if (pdata->enet_id == XGENE_ENET1) {
1922 switch (pdata->port_id) {
1923 case 0:
1b090a48
IS		 1924 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1925 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1926 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1927 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1928 pdata->ring_num = START_RING_NUM_0;
1929 } else {
1930 pdata->cpu_bufnum = START_CPU_BUFNUM_0;
1931 pdata->eth_bufnum = START_ETH_BUFNUM_0;
1932 pdata->bp_bufnum = START_BP_BUFNUM_0;
1933 pdata->ring_num = START_RING_NUM_0;
1934 }
bc1b7c13
IS		 1935 break;
1936 case 1:
149e9ab4
IS		 1937 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1938 pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1;
1939 pdata->eth_bufnum = XG_START_ETH_BUFNUM_1;
1940 pdata->bp_bufnum = XG_START_BP_BUFNUM_1;
1941 pdata->ring_num = XG_START_RING_NUM_1;
1942 } else {
1943 pdata->cpu_bufnum = START_CPU_BUFNUM_1;
1944 pdata->eth_bufnum = START_ETH_BUFNUM_1;
1945 pdata->bp_bufnum = START_BP_BUFNUM_1;
1946 pdata->ring_num = START_RING_NUM_1;
1947 }
bc1b7c13
IS		 1948 break;
1949 default:
1950 break;
1951 }
1952 pdata->ring_ops = &xgene_ring1_ops;
1953 } else {
1954 switch (pdata->port_id) {
1955 case 0:
1956 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1957 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1958 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1959 pdata->ring_num = X2_START_RING_NUM_0;
1960 break;
1961 case 1:
1962 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1;
1963 pdata->eth_bufnum = X2_START_ETH_BUFNUM_1;
1964 pdata->bp_bufnum = X2_START_BP_BUFNUM_1;
1965 pdata->ring_num = X2_START_RING_NUM_1;
1966 break;
1967 default:
1968 break;
1969 }
1970 pdata->rm = RM0;
1971 pdata->ring_ops = &xgene_ring2_ops;
ca626454 1972 }
d0eb7458
IS		 1973}
1974
6772b653
IS		 1975static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata)
1976{
1977 struct napi_struct *napi;
107dec27 1978 int i;
6772b653 1979
107dec27
IS		 1980 for (i = 0; i < pdata->rxq_cnt; i++) {
1981 napi = &pdata->rx_ring[i]->napi;
b48b89f9 1982 netif_napi_add(pdata->ndev, napi, xgene_enet_napi);
107dec27 1983 }
6772b653 1984
107dec27
IS		 1985 for (i = 0; i < pdata->cq_cnt; i++) {
1986 napi = &pdata->tx_ring[i]->cp_ring->napi;
b48b89f9 1987 netif_napi_add(pdata->ndev, napi, xgene_enet_napi);
6772b653
IS		 1988 }
1989}
1990
1f3d6209
AB		 1991#ifdef CONFIG_ACPI
1992static const struct acpi_device_id xgene_enet_acpi_match[] = {
1993 { "APMC0D05", XGENE_ENET1},
1994 { "APMC0D30", XGENE_ENET1},
1995 { "APMC0D31", XGENE_ENET1},
1996 { "APMC0D3F", XGENE_ENET1},
1997 { "APMC0D26", XGENE_ENET2},
1998 { "APMC0D25", XGENE_ENET2},
1999 { }
2000};
2001MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match);
2002#endif
2003
2004static const struct of_device_id xgene_enet_of_match[] = {
2005 {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1},
2006 {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1},
2007 {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1},
2008 {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2},
2009 {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2},
2010 {},
2011};
2012
2013MODULE_DEVICE_TABLE(of, xgene_enet_of_match);
2014
e6ad7673
IS		 2015static int xgene_enet_probe(struct platform_device *pdev)
2016{
2017 struct net_device *ndev;
2018 struct xgene_enet_pdata *pdata;
2019 struct device *dev = &pdev->dev;
8089a96f 2020 void (*link_state)(struct work_struct *);
e6ad7673
IS		 2021 int ret;
2022
107dec27 2023 ndev = alloc_etherdev_mqs(sizeof(struct xgene_enet_pdata),
5a44c71c 2024 XGENE_NUM_TX_RING, XGENE_NUM_RX_RING);
e6ad7673
IS		 2025 if (!ndev)
2026 return -ENOMEM;
2027
2028 pdata = netdev_priv(ndev);
2029
2030 pdata->pdev = pdev;
2031 pdata->ndev = ndev;
2032 SET_NETDEV_DEV(ndev, dev);
2033 platform_set_drvdata(pdev, pdata);
2034 ndev->netdev_ops = &xgene_ndev_ops;
2035 xgene_enet_set_ethtool_ops(ndev);
2036 ndev->features |= NETIF_F_IP_CSUM |
2037 NETIF_F_GSO |
9b00eb49
IS		 2038 NETIF_F_GRO |
2039 NETIF_F_SG;
e6ad7673 2040
b0377116 2041 pdata->enet_id = (enum xgene_enet_id)device_get_match_data(&pdev->dev);
0738c54d 2042 if (!pdata->enet_id) {
cecd6e51
IS		 2043 ret = -ENODEV;
2044 goto err;
0738c54d 2045 }
bc1b7c13 2046
e6ad7673
IS		 2047 ret = xgene_enet_get_resources(pdata);
2048 if (ret)
2049 goto err;
2050
d0eb7458 2051 xgene_enet_setup_ops(pdata);
ae1aed95 2052 spin_lock_init(&pdata->mac_lock);
e6ad7673 2053
9b00eb49 2054 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
0a0400c3 2055 ndev->features |= NETIF_F_TSO | NETIF_F_RXCSUM;
e3978673 2056 spin_lock_init(&pdata->mss_lock);
9b00eb49
IS		 2057 }
2058 ndev->hw_features = ndev->features;
2059
aeb20b6b 2060 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
e6ad7673 2061 if (ret) {
aeb20b6b 2062 netdev_err(ndev, "No usable DMA configuration\n");
e6ad7673
IS		 2063 goto err;
2064 }
2065
183db481
QN		 2066 xgene_enet_check_phy_handle(pdata);
2067
e6ad7673
IS		 2068 ret = xgene_enet_init_hw(pdata);
2069 if (ret)
183db481 2070 goto err2;
e6ad7673 2071
8089a96f
IS		 2072 link_state = pdata->mac_ops->link_state;
2073 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
2074 INIT_DELAYED_WORK(&pdata->link_work, link_state);
2075 } else if (!pdata->mdio_driver) {
326dde3e 2076 if (phy_interface_mode_is_rgmii(pdata->phy_mode))
8089a96f
IS		 2077 ret = xgene_enet_mdio_config(pdata);
2078 else
2079 INIT_DELAYED_WORK(&pdata->link_work, link_state);
cecd6e51
IS		 2080
2081 if (ret)
2082 goto err1;
aeb20b6b 2083 }
e6ad7673 2084
2d07d8e4
QN		 2085 spin_lock_init(&pdata->stats_lock);
2086 ret = xgene_extd_stats_init(pdata);
2087 if (ret)
183db481 2088 goto err1;
2d07d8e4 2089
aeb20b6b 2090 xgene_enet_napi_add(pdata);
cb0366b7
IS		 2091 ret = register_netdev(ndev);
2092 if (ret) {
2093 netdev_err(ndev, "Failed to register netdev\n");
183db481 2094 goto err1;
cb0366b7
IS		 2095 }
2096
aeb20b6b 2097 return 0;
cb0366b7 2098
183db481 2099err1:
cecd6e51
IS		 2100 /*
2101 * If necessary, free_netdev() will call netif_napi_del() and undo
2102 * the effects of xgene_enet_napi_add()'s calls to netif_napi_add().
2103 */
2104
183db481
QN		 2105 xgene_enet_delete_desc_rings(pdata);
2106
2107err2:
cecd6e51
IS		 2108 if (pdata->mdio_driver)
2109 xgene_enet_phy_disconnect(pdata);
326dde3e 2110 else if (phy_interface_mode_is_rgmii(pdata->phy_mode))
cecd6e51 2111 xgene_enet_mdio_remove(pdata);
20decb7e 2112err:
e6ad7673
IS		 2113 free_netdev(ndev);
2114 return ret;
2115}
2116
61471264 2117static void xgene_enet_remove(struct platform_device *pdev)
e6ad7673
IS		 2118{
2119 struct xgene_enet_pdata *pdata;
2120 struct net_device *ndev;
2121
2122 pdata = platform_get_drvdata(pdev);
2123 ndev = pdata->ndev;
2124
cb0366b7
IS		 2125 rtnl_lock();
2126 if (netif_running(ndev))
2127 dev_close(ndev);
2128 rtnl_unlock();
2129
8089a96f
IS		 2130 if (pdata->mdio_driver)
2131 xgene_enet_phy_disconnect(pdata);
326dde3e 2132 else if (phy_interface_mode_is_rgmii(pdata->phy_mode))
ccc02ddb 2133 xgene_enet_mdio_remove(pdata);
8089a96f 2134
e6ad7673 2135 unregister_netdev(ndev);
cb11c062 2136 xgene_enet_delete_desc_rings(pdata);
8aba8474 2137 pdata->port_ops->shutdown(pdata);
e6ad7673 2138 free_netdev(ndev);
e6ad7673
IS		 2139}
2140
cb0366b7
IS		 2141static void xgene_enet_shutdown(struct platform_device *pdev)
2142{
2143 struct xgene_enet_pdata *pdata;
2144
2145 pdata = platform_get_drvdata(pdev);
2146 if (!pdata)
2147 return;
2148
2149 if (!pdata->ndev)
2150 return;
2151
2152 xgene_enet_remove(pdev);
2153}
2154
e6ad7673
IS		 2155static struct platform_driver xgene_enet_driver = {
2156 .driver = {
2157 .name = "xgene-enet",
d2ca43f3 2158 .of_match_table = xgene_enet_of_match,
de7b5b3d 2159 .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match),
e6ad7673
IS		 2160 },
2161 .probe = xgene_enet_probe,
61471264 2162 .remove_new = xgene_enet_remove,
cb0366b7 2163 .shutdown = xgene_enet_shutdown,
e6ad7673
IS		 2164};
2165
2166module_platform_driver(xgene_enet_driver);
2167
2168MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver");
d0eb7458 2169MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
e6ad7673
IS		 2170MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>");
2171MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)