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net/fsl: Add mEMAC MDIO support to XGMAC MDIO
[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_main.c
CommitLineData
e6ad7673
IS		 1/* Applied Micro X-Gene SoC Ethernet Driver
2 *
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include "xgene_enet_main.h"
23#include "xgene_enet_hw.h"
32f784b5 24#include "xgene_enet_sgmac.h"
0148d38d 25#include "xgene_enet_xgmac.h"
e6ad7673
IS		 26
27static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
28{
29 struct xgene_enet_raw_desc16 *raw_desc;
30 int i;
31
32 for (i = 0; i < buf_pool->slots; i++) {
33 raw_desc = &buf_pool->raw_desc16[i];
34
35 /* Hardware expects descriptor in little endian format */
36 raw_desc->m0 = cpu_to_le64(i |
37 SET_VAL(FPQNUM, buf_pool->dst_ring_num) |
38 SET_VAL(STASH, 3));
39 }
40}
41
42static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool,
43 u32 nbuf)
44{
45 struct sk_buff *skb;
46 struct xgene_enet_raw_desc16 *raw_desc;
47 struct net_device *ndev;
48 struct device *dev;
49 dma_addr_t dma_addr;
50 u32 tail = buf_pool->tail;
51 u32 slots = buf_pool->slots - 1;
52 u16 bufdatalen, len;
53 int i;
54
55 ndev = buf_pool->ndev;
56 dev = ndev_to_dev(buf_pool->ndev);
57 bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));
58 len = XGENE_ENET_MAX_MTU;
59
60 for (i = 0; i < nbuf; i++) {
61 raw_desc = &buf_pool->raw_desc16[tail];
62
63 skb = netdev_alloc_skb_ip_align(ndev, len);
64 if (unlikely(!skb))
65 return -ENOMEM;
66 buf_pool->rx_skb[tail] = skb;
67
68 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
69 if (dma_mapping_error(dev, dma_addr)) {
70 netdev_err(ndev, "DMA mapping error\n");
71 dev_kfree_skb_any(skb);
72 return -EINVAL;
73 }
74
75 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
76 SET_VAL(BUFDATALEN, bufdatalen) |
77 SET_BIT(COHERENT));
78 tail = (tail + 1) & slots;
79 }
80
81 iowrite32(nbuf, buf_pool->cmd);
82 buf_pool->tail = tail;
83
84 return 0;
85}
86
87static u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
88{
89 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
90
91 return ((u16)pdata->rm << 10) | ring->num;
92}
93
94static u8 xgene_enet_hdr_len(const void *data)
95{
96 const struct ethhdr *eth = data;
97
98 return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN;
99}
100
101static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)
102{
103 u32 __iomem *cmd_base = ring->cmd_base;
104 u32 ring_state, num_msgs;
105
106 ring_state = ioread32(&cmd_base[1]);
107 num_msgs = ring_state & CREATE_MASK(NUMMSGSINQ_POS, NUMMSGSINQ_LEN);
108
109 return num_msgs >> NUMMSGSINQ_POS;
110}
111
112static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool)
113{
114 struct xgene_enet_raw_desc16 *raw_desc;
115 u32 slots = buf_pool->slots - 1;
116 u32 tail = buf_pool->tail;
117 u32 userinfo;
118 int i, len;
119
120 len = xgene_enet_ring_len(buf_pool);
121 for (i = 0; i < len; i++) {
122 tail = (tail - 1) & slots;
123 raw_desc = &buf_pool->raw_desc16[tail];
124
125 /* Hardware stores descriptor in little endian format */
126 userinfo = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
127 dev_kfree_skb_any(buf_pool->rx_skb[userinfo]);
128 }
129
130 iowrite32(-len, buf_pool->cmd);
131 buf_pool->tail = tail;
132}
133
134static irqreturn_t xgene_enet_rx_irq(const int irq, void *data)
135{
136 struct xgene_enet_desc_ring *rx_ring = data;
137
138 if (napi_schedule_prep(&rx_ring->napi)) {
139 disable_irq_nosync(irq);
140 __napi_schedule(&rx_ring->napi);
141 }
142
143 return IRQ_HANDLED;
144}
145
146static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
147 struct xgene_enet_raw_desc *raw_desc)
148{
149 struct sk_buff *skb;
150 struct device *dev;
151 u16 skb_index;
152 u8 status;
153 int ret = 0;
154
155 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
156 skb = cp_ring->cp_skb[skb_index];
157
158 dev = ndev_to_dev(cp_ring->ndev);
159 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
160 GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1)),
161 DMA_TO_DEVICE);
162
163 /* Checking for error */
164 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
165 if (unlikely(status > 2)) {
166 xgene_enet_parse_error(cp_ring, netdev_priv(cp_ring->ndev),
167 status);
168 ret = -EIO;
169 }
170
171 if (likely(skb)) {
172 dev_kfree_skb_any(skb);
173 } else {
174 netdev_err(cp_ring->ndev, "completion skb is NULL\n");
175 ret = -EIO;
176 }
177
178 return ret;
179}
180
181static u64 xgene_enet_work_msg(struct sk_buff *skb)
182{
183 struct iphdr *iph;
184 u8 l3hlen, l4hlen = 0;
185 u8 csum_enable = 0;
186 u8 proto = 0;
187 u8 ethhdr;
188 u64 hopinfo;
189
190 if (unlikely(skb->protocol != htons(ETH_P_IP)) &&
191 unlikely(skb->protocol != htons(ETH_P_8021Q)))
192 goto out;
193
194 if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM)))
195 goto out;
196
197 iph = ip_hdr(skb);
198 if (unlikely(ip_is_fragment(iph)))
199 goto out;
200
201 if (likely(iph->protocol == IPPROTO_TCP)) {
202 l4hlen = tcp_hdrlen(skb) >> 2;
203 csum_enable = 1;
204 proto = TSO_IPPROTO_TCP;
205 } else if (iph->protocol == IPPROTO_UDP) {
206 l4hlen = UDP_HDR_SIZE;
207 csum_enable = 1;
208 }
209out:
210 l3hlen = ip_hdrlen(skb) >> 2;
211 ethhdr = xgene_enet_hdr_len(skb->data);
212 hopinfo = SET_VAL(TCPHDR, l4hlen) |
213 SET_VAL(IPHDR, l3hlen) |
214 SET_VAL(ETHHDR, ethhdr) |
215 SET_VAL(EC, csum_enable) |
216 SET_VAL(IS, proto) |
217 SET_BIT(IC) |
218 SET_BIT(TYPE_ETH_WORK_MESSAGE);
219
220 return hopinfo;
221}
222
223static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
224 struct sk_buff *skb)
225{
226 struct device *dev = ndev_to_dev(tx_ring->ndev);
227 struct xgene_enet_raw_desc *raw_desc;
228 dma_addr_t dma_addr;
229 u16 tail = tx_ring->tail;
230 u64 hopinfo;
231
232 raw_desc = &tx_ring->raw_desc[tail];
233 memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
234
235 dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
236 if (dma_mapping_error(dev, dma_addr)) {
237 netdev_err(tx_ring->ndev, "DMA mapping error\n");
238 return -EINVAL;
239 }
240
241 /* Hardware expects descriptor in little endian format */
242 raw_desc->m0 = cpu_to_le64(tail);
243 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
244 SET_VAL(BUFDATALEN, skb->len) |
245 SET_BIT(COHERENT));
246 hopinfo = xgene_enet_work_msg(skb);
247 raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
248 hopinfo);
249 tx_ring->cp_ring->cp_skb[tail] = skb;
250
251 return 0;
252}
253
254static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
255 struct net_device *ndev)
256{
257 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
258 struct xgene_enet_desc_ring *tx_ring = pdata->tx_ring;
259 struct xgene_enet_desc_ring *cp_ring = tx_ring->cp_ring;
260 u32 tx_level, cq_level;
261
262 tx_level = xgene_enet_ring_len(tx_ring);
263 cq_level = xgene_enet_ring_len(cp_ring);
264 if (unlikely(tx_level > pdata->tx_qcnt_hi ||
265 cq_level > pdata->cp_qcnt_hi)) {
266 netif_stop_queue(ndev);
267 return NETDEV_TX_BUSY;
268 }
269
270 if (xgene_enet_setup_tx_desc(tx_ring, skb)) {
271 dev_kfree_skb_any(skb);
272 return NETDEV_TX_OK;
273 }
274
275 iowrite32(1, tx_ring->cmd);
276 skb_tx_timestamp(skb);
277 tx_ring->tail = (tx_ring->tail + 1) & (tx_ring->slots - 1);
278
279 pdata->stats.tx_packets++;
280 pdata->stats.tx_bytes += skb->len;
281
282 return NETDEV_TX_OK;
283}
284
285static void xgene_enet_skip_csum(struct sk_buff *skb)
286{
287 struct iphdr *iph = ip_hdr(skb);
288
289 if (!ip_is_fragment(iph) ||
290 (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)) {
291 skb->ip_summed = CHECKSUM_UNNECESSARY;
292 }
293}
294
295static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring,
296 struct xgene_enet_raw_desc *raw_desc)
297{
298 struct net_device *ndev;
299 struct xgene_enet_pdata *pdata;
300 struct device *dev;
301 struct xgene_enet_desc_ring *buf_pool;
302 u32 datalen, skb_index;
303 struct sk_buff *skb;
304 u8 status;
305 int ret = 0;
306
307 ndev = rx_ring->ndev;
308 pdata = netdev_priv(ndev);
309 dev = ndev_to_dev(rx_ring->ndev);
310 buf_pool = rx_ring->buf_pool;
311
312 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
313 XGENE_ENET_MAX_MTU, DMA_FROM_DEVICE);
314 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
315 skb = buf_pool->rx_skb[skb_index];
316
317 /* checking for error */
318 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
319 if (unlikely(status > 2)) {
320 dev_kfree_skb_any(skb);
321 xgene_enet_parse_error(rx_ring, netdev_priv(rx_ring->ndev),
322 status);
323 pdata->stats.rx_dropped++;
324 ret = -EIO;
325 goto out;
326 }
327
328 /* strip off CRC as HW isn't doing this */
329 datalen = GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1));
330 datalen -= 4;
331 prefetch(skb->data - NET_IP_ALIGN);
332 skb_put(skb, datalen);
333
334 skb_checksum_none_assert(skb);
335 skb->protocol = eth_type_trans(skb, ndev);
336 if (likely((ndev->features & NETIF_F_IP_CSUM) &&
337 skb->protocol == htons(ETH_P_IP))) {
338 xgene_enet_skip_csum(skb);
339 }
340
341 pdata->stats.rx_packets++;
342 pdata->stats.rx_bytes += datalen;
343 napi_gro_receive(&rx_ring->napi, skb);
344out:
345 if (--rx_ring->nbufpool == 0) {
346 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL);
347 rx_ring->nbufpool = NUM_BUFPOOL;
348 }
349
350 return ret;
351}
352
353static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc)
354{
355 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false;
356}
357
358static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
359 int budget)
360{
361 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
362 struct xgene_enet_raw_desc *raw_desc;
363 u16 head = ring->head;
364 u16 slots = ring->slots - 1;
365 int ret, count = 0;
366
367 do {
368 raw_desc = &ring->raw_desc[head];
369 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc)))
370 break;
371
372 if (is_rx_desc(raw_desc))
373 ret = xgene_enet_rx_frame(ring, raw_desc);
374 else
375 ret = xgene_enet_tx_completion(ring, raw_desc);
376 xgene_enet_mark_desc_slot_empty(raw_desc);
377
378 head = (head + 1) & slots;
379 count++;
380
381 if (ret)
382 break;
383 } while (--budget);
384
385 if (likely(count)) {
386 iowrite32(-count, ring->cmd);
387 ring->head = head;
388
389 if (netif_queue_stopped(ring->ndev)) {
390 if (xgene_enet_ring_len(ring) < pdata->cp_qcnt_low)
391 netif_wake_queue(ring->ndev);
392 }
393 }
394
0148d38d 395 return count;
e6ad7673
IS		 396}
397
398static int xgene_enet_napi(struct napi_struct *napi, const int budget)
399{
400 struct xgene_enet_desc_ring *ring;
401 int processed;
402
403 ring = container_of(napi, struct xgene_enet_desc_ring, napi);
404 processed = xgene_enet_process_ring(ring, budget);
405
406 if (processed != budget) {
407 napi_complete(napi);
408 enable_irq(ring->irq);
409 }
410
411 return processed;
412}
413
414static void xgene_enet_timeout(struct net_device *ndev)
415{
416 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
417
d0eb7458 418 pdata->mac_ops->reset(pdata);
e6ad7673
IS		 419}
420
421static int xgene_enet_register_irq(struct net_device *ndev)
422{
423 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
424 struct device *dev = ndev_to_dev(ndev);
425 int ret;
426
427 ret = devm_request_irq(dev, pdata->rx_ring->irq, xgene_enet_rx_irq,
428 IRQF_SHARED, ndev->name, pdata->rx_ring);
429 if (ret) {
430 netdev_err(ndev, "rx%d interrupt request failed\n",
431 pdata->rx_ring->irq);
432 }
433
434 return ret;
435}
436
437static void xgene_enet_free_irq(struct net_device *ndev)
438{
439 struct xgene_enet_pdata *pdata;
440 struct device *dev;
441
442 pdata = netdev_priv(ndev);
443 dev = ndev_to_dev(ndev);
444 devm_free_irq(dev, pdata->rx_ring->irq, pdata->rx_ring);
445}
446
447static int xgene_enet_open(struct net_device *ndev)
448{
449 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
d0eb7458 450 struct xgene_mac_ops *mac_ops = pdata->mac_ops;
e6ad7673
IS		 451 int ret;
452
d0eb7458
IS		 453 mac_ops->tx_enable(pdata);
454 mac_ops->rx_enable(pdata);
e6ad7673
IS		 455
456 ret = xgene_enet_register_irq(ndev);
457 if (ret)
458 return ret;
459 napi_enable(&pdata->rx_ring->napi);
460
0148d38d 461 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
e6ad7673 462 phy_start(pdata->phy_dev);
0148d38d
IS		 463 else
464 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
e6ad7673
IS		 465
466 netif_start_queue(ndev);
467
468 return ret;
469}
470
471static int xgene_enet_close(struct net_device *ndev)
472{
473 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
d0eb7458 474 struct xgene_mac_ops *mac_ops = pdata->mac_ops;
e6ad7673
IS		 475
476 netif_stop_queue(ndev);
477
0148d38d 478 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
e6ad7673 479 phy_stop(pdata->phy_dev);
0148d38d
IS		 480 else
481 cancel_delayed_work_sync(&pdata->link_work);
e6ad7673
IS		 482
483 napi_disable(&pdata->rx_ring->napi);
484 xgene_enet_free_irq(ndev);
485 xgene_enet_process_ring(pdata->rx_ring, -1);
486
d0eb7458
IS		 487 mac_ops->tx_disable(pdata);
488 mac_ops->rx_disable(pdata);
e6ad7673
IS		 489
490 return 0;
491}
492
493static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring)
494{
495 struct xgene_enet_pdata *pdata;
496 struct device *dev;
497
498 pdata = netdev_priv(ring->ndev);
499 dev = ndev_to_dev(ring->ndev);
500
501 xgene_enet_clear_ring(ring);
502 dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
503}
504
505static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata)
506{
507 struct xgene_enet_desc_ring *buf_pool;
508
509 if (pdata->tx_ring) {
510 xgene_enet_delete_ring(pdata->tx_ring);
511 pdata->tx_ring = NULL;
512 }
513
514 if (pdata->rx_ring) {
515 buf_pool = pdata->rx_ring->buf_pool;
516 xgene_enet_delete_bufpool(buf_pool);
517 xgene_enet_delete_ring(buf_pool);
518 xgene_enet_delete_ring(pdata->rx_ring);
519 pdata->rx_ring = NULL;
520 }
521}
522
523static int xgene_enet_get_ring_size(struct device *dev,
524 enum xgene_enet_ring_cfgsize cfgsize)
525{
526 int size = -EINVAL;
527
528 switch (cfgsize) {
529 case RING_CFGSIZE_512B:
530 size = 0x200;
531 break;
532 case RING_CFGSIZE_2KB:
533 size = 0x800;
534 break;
535 case RING_CFGSIZE_16KB:
536 size = 0x4000;
537 break;
538 case RING_CFGSIZE_64KB:
539 size = 0x10000;
540 break;
541 case RING_CFGSIZE_512KB:
542 size = 0x80000;
543 break;
544 default:
545 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize);
546 break;
547 }
548
549 return size;
550}
551
552static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring)
553{
554 struct device *dev;
555
556 if (!ring)
557 return;
558
559 dev = ndev_to_dev(ring->ndev);
560
561 if (ring->desc_addr) {
562 xgene_enet_clear_ring(ring);
563 dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
564 }
565 devm_kfree(dev, ring);
566}
567
568static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata)
569{
570 struct device *dev = &pdata->pdev->dev;
571 struct xgene_enet_desc_ring *ring;
572
573 ring = pdata->tx_ring;
c10e4caf
IS		 574 if (ring) {
575 if (ring->cp_ring && ring->cp_ring->cp_skb)
576 devm_kfree(dev, ring->cp_ring->cp_skb);
577 xgene_enet_free_desc_ring(ring);
578 }
e6ad7673
IS		 579
580 ring = pdata->rx_ring;
c10e4caf
IS		 581 if (ring) {
582 if (ring->buf_pool) {
583 if (ring->buf_pool->rx_skb)
584 devm_kfree(dev, ring->buf_pool->rx_skb);
585 xgene_enet_free_desc_ring(ring->buf_pool);
586 }
587 xgene_enet_free_desc_ring(ring);
588 }
e6ad7673
IS		 589}
590
591static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
592 struct net_device *ndev, u32 ring_num,
593 enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
594{
595 struct xgene_enet_desc_ring *ring;
596 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
597 struct device *dev = ndev_to_dev(ndev);
9b9ba821
TK		 598 int size;
599
600 size = xgene_enet_get_ring_size(dev, cfgsize);
601 if (size < 0)
602 return NULL;
e6ad7673
IS		 603
604 ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring),
605 GFP_KERNEL);
606 if (!ring)
607 return NULL;
608
609 ring->ndev = ndev;
610 ring->num = ring_num;
611 ring->cfgsize = cfgsize;
612 ring->id = ring_id;
613
e6ad7673
IS		 614 ring->desc_addr = dma_zalloc_coherent(dev, size, &ring->dma,
615 GFP_KERNEL);
616 if (!ring->desc_addr) {
617 devm_kfree(dev, ring);
618 return NULL;
619 }
620 ring->size = size;
621
622 ring->cmd_base = pdata->ring_cmd_addr + (ring->num << 6);
623 ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
e6ad7673
IS		 624 ring = xgene_enet_setup_ring(ring);
625 netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
626 ring->num, ring->size, ring->id, ring->slots);
627
628 return ring;
629}
630
631static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum)
632{
633 return (owner << 6) | (bufnum & GENMASK(5, 0));
634}
635
636static int xgene_enet_create_desc_rings(struct net_device *ndev)
637{
638 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
639 struct device *dev = ndev_to_dev(ndev);
640 struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
641 struct xgene_enet_desc_ring *buf_pool = NULL;
bdd330f0
IS		 642 u8 cpu_bufnum = 0, eth_bufnum = START_ETH_BUFNUM;
643 u8 bp_bufnum = START_BP_BUFNUM;
644 u16 ring_id, ring_num = START_RING_NUM;
e6ad7673
IS		 645 int ret;
646
647 /* allocate rx descriptor ring */
648 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
649 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
650 RING_CFGSIZE_16KB, ring_id);
651 if (!rx_ring) {
652 ret = -ENOMEM;
653 goto err;
654 }
655
656 /* allocate buffer pool for receiving packets */
657 ring_id = xgene_enet_get_ring_id(RING_OWNER_ETH0, bp_bufnum++);
658 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
659 RING_CFGSIZE_2KB, ring_id);
660 if (!buf_pool) {
661 ret = -ENOMEM;
662 goto err;
663 }
664
665 rx_ring->nbufpool = NUM_BUFPOOL;
666 rx_ring->buf_pool = buf_pool;
667 rx_ring->irq = pdata->rx_irq;
668 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots,
669 sizeof(struct sk_buff *), GFP_KERNEL);
670 if (!buf_pool->rx_skb) {
671 ret = -ENOMEM;
672 goto err;
673 }
674
675 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool);
676 rx_ring->buf_pool = buf_pool;
677 pdata->rx_ring = rx_ring;
678
679 /* allocate tx descriptor ring */
680 ring_id = xgene_enet_get_ring_id(RING_OWNER_ETH0, eth_bufnum++);
681 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
682 RING_CFGSIZE_16KB, ring_id);
683 if (!tx_ring) {
684 ret = -ENOMEM;
685 goto err;
686 }
687 pdata->tx_ring = tx_ring;
688
689 cp_ring = pdata->rx_ring;
690 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots,
691 sizeof(struct sk_buff *), GFP_KERNEL);
692 if (!cp_ring->cp_skb) {
693 ret = -ENOMEM;
694 goto err;
695 }
696 pdata->tx_ring->cp_ring = cp_ring;
697 pdata->tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring);
698
699 pdata->tx_qcnt_hi = pdata->tx_ring->slots / 2;
700 pdata->cp_qcnt_hi = pdata->rx_ring->slots / 2;
701 pdata->cp_qcnt_low = pdata->cp_qcnt_hi / 2;
702
703 return 0;
704
705err:
706 xgene_enet_free_desc_rings(pdata);
707 return ret;
708}
709
710static struct rtnl_link_stats64 *xgene_enet_get_stats64(
711 struct net_device *ndev,
712 struct rtnl_link_stats64 *storage)
713{
714 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
715 struct rtnl_link_stats64 *stats = &pdata->stats;
716
717 stats->rx_errors += stats->rx_length_errors +
718 stats->rx_crc_errors +
719 stats->rx_frame_errors +
720 stats->rx_fifo_errors;
721 memcpy(storage, &pdata->stats, sizeof(struct rtnl_link_stats64));
722
723 return storage;
724}
725
726static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr)
727{
728 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
729 int ret;
730
731 ret = eth_mac_addr(ndev, addr);
732 if (ret)
733 return ret;
d0eb7458 734 pdata->mac_ops->set_mac_addr(pdata);
e6ad7673
IS		 735
736 return ret;
737}
738
739static const struct net_device_ops xgene_ndev_ops = {
740 .ndo_open = xgene_enet_open,
741 .ndo_stop = xgene_enet_close,
742 .ndo_start_xmit = xgene_enet_start_xmit,
743 .ndo_tx_timeout = xgene_enet_timeout,
744 .ndo_get_stats64 = xgene_enet_get_stats64,
745 .ndo_change_mtu = eth_change_mtu,
746 .ndo_set_mac_address = xgene_enet_set_mac_address,
747};
748
749static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
750{
751 struct platform_device *pdev;
752 struct net_device *ndev;
753 struct device *dev;
754 struct resource *res;
755 void __iomem *base_addr;
756 const char *mac;
757 int ret;
758
759 pdev = pdata->pdev;
760 dev = &pdev->dev;
761 ndev = pdata->ndev;
762
763 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "enet_csr");
e6ad7673
IS		 764 pdata->base_addr = devm_ioremap_resource(dev, res);
765 if (IS_ERR(pdata->base_addr)) {
766 dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
767 return PTR_ERR(pdata->base_addr);
768 }
769
770 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ring_csr");
e6ad7673
IS		 771 pdata->ring_csr_addr = devm_ioremap_resource(dev, res);
772 if (IS_ERR(pdata->ring_csr_addr)) {
773 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n");
774 return PTR_ERR(pdata->ring_csr_addr);
775 }
776
777 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ring_cmd");
e6ad7673
IS		 778 pdata->ring_cmd_addr = devm_ioremap_resource(dev, res);
779 if (IS_ERR(pdata->ring_cmd_addr)) {
780 dev_err(dev, "Unable to retrieve ENET Ring command region\n");
781 return PTR_ERR(pdata->ring_cmd_addr);
782 }
783
784 ret = platform_get_irq(pdev, 0);
785 if (ret <= 0) {
786 dev_err(dev, "Unable to get ENET Rx IRQ\n");
787 ret = ret ? : -ENXIO;
788 return ret;
789 }
790 pdata->rx_irq = ret;
791
792 mac = of_get_mac_address(dev->of_node);
793 if (mac)
794 memcpy(ndev->dev_addr, mac, ndev->addr_len);
795 else
796 eth_hw_addr_random(ndev);
797 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
798
799 pdata->phy_mode = of_get_phy_mode(pdev->dev.of_node);
800 if (pdata->phy_mode < 0) {
0148d38d
IS		 801 dev_err(dev, "Unable to get phy-connection-type\n");
802 return pdata->phy_mode;
803 }
804 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII &&
32f784b5 805 pdata->phy_mode != PHY_INTERFACE_MODE_SGMII &&
0148d38d
IS		 806 pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
807 dev_err(dev, "Incorrect phy-connection-type specified\n");
808 return -ENODEV;
e6ad7673
IS		 809 }
810
811 pdata->clk = devm_clk_get(&pdev->dev, NULL);
812 ret = IS_ERR(pdata->clk);
813 if (IS_ERR(pdata->clk)) {
814 dev_err(&pdev->dev, "can't get clock\n");
815 ret = PTR_ERR(pdata->clk);
816 return ret;
817 }
818
819 base_addr = pdata->base_addr;
820 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
821 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
822 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
32f784b5
IS		 823 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII ||
824 pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) {
0148d38d
IS		 825 pdata->mcx_mac_addr = base_addr + BLOCK_ETH_MAC_OFFSET;
826 pdata->mcx_mac_csr_addr = base_addr + BLOCK_ETH_MAC_CSR_OFFSET;
0148d38d
IS		 827 } else {
828 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
829 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
0148d38d 830 }
e6ad7673
IS		 831 pdata->rx_buff_cnt = NUM_PKT_BUF;
832
0148d38d 833 return 0;
e6ad7673
IS		 834}
835
836static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
837{
838 struct net_device *ndev = pdata->ndev;
839 struct xgene_enet_desc_ring *buf_pool;
840 u16 dst_ring_num;
841 int ret;
842
c3f4465d
IS		 843 ret = pdata->port_ops->reset(pdata);
844 if (ret)
845 return ret;
e6ad7673
IS		 846
847 ret = xgene_enet_create_desc_rings(ndev);
848 if (ret) {
849 netdev_err(ndev, "Error in ring configuration\n");
850 return ret;
851 }
852
853 /* setup buffer pool */
854 buf_pool = pdata->rx_ring->buf_pool;
855 xgene_enet_init_bufpool(buf_pool);
856 ret = xgene_enet_refill_bufpool(buf_pool, pdata->rx_buff_cnt);
857 if (ret) {
858 xgene_enet_delete_desc_rings(pdata);
859 return ret;
860 }
861
862 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring);
d0eb7458 863 pdata->port_ops->cle_bypass(pdata, dst_ring_num, buf_pool->id);
0148d38d 864 pdata->mac_ops->init(pdata);
e6ad7673
IS		 865
866 return ret;
867}
868
d0eb7458
IS		 869static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
870{
0148d38d
IS		 871 switch (pdata->phy_mode) {
872 case PHY_INTERFACE_MODE_RGMII:
873 pdata->mac_ops = &xgene_gmac_ops;
874 pdata->port_ops = &xgene_gport_ops;
dc8385f0 875 pdata->rm = RM3;
0148d38d 876 break;
32f784b5
IS		 877 case PHY_INTERFACE_MODE_SGMII:
878 pdata->mac_ops = &xgene_sgmac_ops;
879 pdata->port_ops = &xgene_sgport_ops;
880 pdata->rm = RM1;
881 break;
0148d38d
IS		 882 default:
883 pdata->mac_ops = &xgene_xgmac_ops;
884 pdata->port_ops = &xgene_xgport_ops;
dc8385f0 885 pdata->rm = RM0;
0148d38d
IS		 886 break;
887 }
d0eb7458
IS		 888}
889
e6ad7673
IS		 890static int xgene_enet_probe(struct platform_device *pdev)
891{
892 struct net_device *ndev;
893 struct xgene_enet_pdata *pdata;
894 struct device *dev = &pdev->dev;
895 struct napi_struct *napi;
dc8385f0 896 struct xgene_mac_ops *mac_ops;
e6ad7673
IS		 897 int ret;
898
899 ndev = alloc_etherdev(sizeof(struct xgene_enet_pdata));
900 if (!ndev)
901 return -ENOMEM;
902
903 pdata = netdev_priv(ndev);
904
905 pdata->pdev = pdev;
906 pdata->ndev = ndev;
907 SET_NETDEV_DEV(ndev, dev);
908 platform_set_drvdata(pdev, pdata);
909 ndev->netdev_ops = &xgene_ndev_ops;
910 xgene_enet_set_ethtool_ops(ndev);
911 ndev->features |= NETIF_F_IP_CSUM |
912 NETIF_F_GSO |
913 NETIF_F_GRO;
914
915 ret = xgene_enet_get_resources(pdata);
916 if (ret)
917 goto err;
918
d0eb7458 919 xgene_enet_setup_ops(pdata);
e6ad7673
IS		 920
921 ret = register_netdev(ndev);
922 if (ret) {
923 netdev_err(ndev, "Failed to register netdev\n");
924 goto err;
925 }
926
927 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
928 if (ret) {
929 netdev_err(ndev, "No usable DMA configuration\n");
930 goto err;
931 }
932
933 ret = xgene_enet_init_hw(pdata);
934 if (ret)
935 goto err;
936
937 napi = &pdata->rx_ring->napi;
938 netif_napi_add(ndev, napi, xgene_enet_napi, NAPI_POLL_WEIGHT);
dc8385f0 939 mac_ops = pdata->mac_ops;
0148d38d
IS		 940 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
941 ret = xgene_enet_mdio_config(pdata);
942 else
dc8385f0 943 INIT_DELAYED_WORK(&pdata->link_work, mac_ops->link_state);
e6ad7673
IS		 944
945 return ret;
946err:
c3f4465d 947 unregister_netdev(ndev);
e6ad7673
IS		 948 free_netdev(ndev);
949 return ret;
950}
951
952static int xgene_enet_remove(struct platform_device *pdev)
953{
954 struct xgene_enet_pdata *pdata;
d0eb7458 955 struct xgene_mac_ops *mac_ops;
e6ad7673
IS		 956 struct net_device *ndev;
957
958 pdata = platform_get_drvdata(pdev);
d0eb7458 959 mac_ops = pdata->mac_ops;
e6ad7673
IS		 960 ndev = pdata->ndev;
961
d0eb7458
IS		 962 mac_ops->rx_disable(pdata);
963 mac_ops->tx_disable(pdata);
e6ad7673
IS		 964
965 netif_napi_del(&pdata->rx_ring->napi);
966 xgene_enet_mdio_remove(pdata);
967 xgene_enet_delete_desc_rings(pdata);
968 unregister_netdev(ndev);
d0eb7458 969 pdata->port_ops->shutdown(pdata);
e6ad7673
IS		 970 free_netdev(ndev);
971
972 return 0;
973}
974
975static struct of_device_id xgene_enet_match[] = {
976 {.compatible = "apm,xgene-enet",},
977 {},
978};
979
980MODULE_DEVICE_TABLE(of, xgene_enet_match);
981
982static struct platform_driver xgene_enet_driver = {
983 .driver = {
984 .name = "xgene-enet",
985 .of_match_table = xgene_enet_match,
986 },
987 .probe = xgene_enet_probe,
988 .remove = xgene_enet_remove,
989};
990
991module_platform_driver(xgene_enet_driver);
992
993MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver");
994MODULE_VERSION(XGENE_DRV_VERSION);
d0eb7458 995MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
e6ad7673
IS		 996MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>");
997MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)