[linux-2.6-block.git] / drivers / net / ethernet / apm / xgene / xgene_enet_cle.h

/* Applied Micro X-Gene SoC Ethernet Classifier structures
 *
 * Copyright (c) 2016, Applied Micro Circuits Corporation
 * Authors: Khuong Dinh <kdinh@apm.com>
 *          Tanmay Inamdar <tinamdar@apm.com>
 *          Iyappan Subramanian <isubramanian@apm.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __XGENE_ENET_CLE_H__
#define __XGENE_ENET_CLE_H__

#include <linux/io.h>
#include <linux/random.h>

/* Register offsets */
#define INDADDR			0x04
#define INDCMD			0x08
#define INDCMD_STATUS		0x0c
#define DATA_RAM0		0x10
#define SNPTR0			0x0100
#define SPPTR0			0x0104
#define DFCLSRESDBPTR0		0x0108
#define DFCLSRESDB00		0x010c

#define CLE_CMD_TO		10	/* ms */
#define CLE_PKTRAM_SIZE		256	/* bytes */
#define CLE_PORT_OFFSET		0x200
#define CLE_DRAM_REGS		17

#define CLE_DN_TYPE_LEN		2
#define CLE_DN_TYPE_POS		0
#define CLE_DN_LASTN_LEN	1
#define CLE_DN_LASTN_POS	2
#define CLE_DN_HLS_LEN		1
#define CLE_DN_HLS_POS		3
#define CLE_DN_EXT_LEN		2
#define	CLE_DN_EXT_POS		4
#define CLE_DN_BSTOR_LEN	2
#define CLE_DN_BSTOR_POS	6
#define CLE_DN_SBSTOR_LEN	2
#define CLE_DN_SBSTOR_POS	8
#define CLE_DN_RPTR_LEN		12
#define CLE_DN_RPTR_POS		12

#define CLE_BR_VALID_LEN	1
#define CLE_BR_VALID_POS	0
#define CLE_BR_NPPTR_LEN	9
#define CLE_BR_NPPTR_POS	1
#define CLE_BR_JB_LEN		1
#define CLE_BR_JB_POS		10
#define CLE_BR_JR_LEN		1
#define CLE_BR_JR_POS		11
#define CLE_BR_OP_LEN		3
#define CLE_BR_OP_POS		12
#define CLE_BR_NNODE_LEN	9
#define CLE_BR_NNODE_POS	15
#define CLE_BR_NBR_LEN		5
#define CLE_BR_NBR_POS		24

#define CLE_BR_DATA_LEN		16
#define CLE_BR_DATA_POS		0
#define CLE_BR_MASK_LEN		16
#define CLE_BR_MASK_POS		16

#define CLE_KN_PRIO_POS		0
#define CLE_KN_PRIO_LEN		3
#define CLE_KN_RPTR_POS		3
#define CLE_KN_RPTR_LEN		10
#define CLE_TYPE_POS		0
#define CLE_TYPE_LEN		2

#define CLE_DSTQIDL_POS		25
#define CLE_DSTQIDL_LEN		7
#define CLE_DSTQIDH_POS		0
#define CLE_DSTQIDH_LEN		5
#define CLE_FPSEL_POS		21
#define CLE_FPSEL_LEN		4
#define CLE_PRIORITY_POS	5
#define CLE_PRIORITY_LEN	3

#define JMP_ABS			0
#define JMP_REL			1
#define JMP_FW			0
#define JMP_BW			1

enum xgene_cle_ptree_nodes {
	PKT_TYPE_NODE,
	LAST_NODE,
	MAX_NODES
};

enum xgene_cle_byte_store {
	NO_BYTE,
	FIRST_BYTE,
	SECOND_BYTE,
	BOTH_BYTES
};

/* Preclassification operation types */
enum xgene_cle_node_type {
	INV,
	KN,
	EWDN,
	RES_NODE
};

/* Preclassification operation types */
enum xgene_cle_op_type {
	EQT,
	NEQT,
	LTEQT,
	GTEQT,
	AND,
	NAND
};

enum xgene_cle_parser {
	PARSER0,
	PARSER1,
	PARSER2,
	PARSER_ALL
};

#define XGENE_CLE_DRAM(type)	(((type) & 0xf) << 28)
enum xgene_cle_dram_type {
	PKT_RAM,
	PTREE_RAM = 0xc,
	AVL_RAM,
	DB_RAM
};

enum xgene_cle_cmd_type {
	CLE_CMD_WR = 1,
	CLE_CMD_RD = 2,
	CLE_CMD_AVL_ADD = 8,
	CLE_CMD_AVL_DEL = 16,
	CLE_CMD_AVL_SRCH = 32
};

enum xgene_cle_ptree_dbptrs {
	DB_RES_DROP,
	DB_RES_DEF,
	DB_RES_ACCEPT,
	DB_MAX_PTRS
};

struct xgene_cle_ptree_branch {
	bool valid;
	u16 next_packet_pointer;
	bool jump_bw;
	bool jump_rel;
	u8 operation;
	u16 next_node;
	u8 next_branch;
	u16 data;
	u16 mask;
};

struct xgene_cle_ptree_ewdn {
	u8 node_type;
	bool last_node;
	bool hdr_len_store;
	u8 hdr_extn;
	u8 byte_store;
	u8 search_byte_store;
	u16 result_pointer;
	u8 num_branches;
	struct xgene_cle_ptree_branch branch[6];
};

struct xgene_cle_ptree_key {
	u8 priority;
	u16 result_pointer;
};

struct xgene_cle_ptree_kn {
	u8 node_type;
	u8 num_keys;
	struct xgene_cle_ptree_key key[32];
};

struct xgene_cle_dbptr {
	u8 split_boundary;
	u8 mirror_nxtfpsel;
	u8 mirror_fpsel;
	u16 mirror_dstqid;
	u8 drop;
	u8 mirror;
	u8 hdr_data_split;
	u64 hopinfomsbs;
	u8 DR;
	u8 HR;
	u64 hopinfomlsbs;
	u16 h0enq_num;
	u8 h0fpsel;
	u8 nxtfpsel;
	u8 fpsel;
	u16 dstqid;
	u8 cle_priority;
	u8 cle_flowgroup;
	u8 cle_perflow;
	u8 cle_insert_timestamp;
	u8 stash;
	u8 in;
	u8 perprioen;
	u8 perflowgroupen;
	u8 perflowen;
	u8 selhash;
	u8 selhdrext;
	u8 mirror_nxtfpsel_msb;
	u8 mirror_fpsel_msb;
	u8 hfpsel_msb;
	u8 nxtfpsel_msb;
	u8 fpsel_msb;
};

struct xgene_cle_ptree {
	struct xgene_cle_ptree_ewdn *dn;
	struct xgene_cle_ptree_kn *kn;
	struct xgene_cle_dbptr *dbptr;
	u32 num_dn;
	u32 num_kn;
	u32 num_dbptr;
	u32 start_node;
	u32 start_pkt;
	u32 start_dbptr;
};

struct xgene_enet_cle {
	void __iomem *base;
	struct xgene_cle_ptree ptree;
	enum xgene_cle_parser active_parser;
	u32 parsers;
	u32 max_nodes;
	u32 max_dbptrs;
	u32 jump_bytes;
};

extern struct xgene_cle_ops xgene_cle3in_ops;

#endif /* __XGENE_ENET_CLE_H__ */
Commit	Line	Data
76f94a9c IS	1	/* Applied Micro X-Gene SoC Ethernet Classifier structures
	2	*
	3	* Copyright (c) 2016, Applied Micro Circuits Corporation
	4	* Authors: Khuong Dinh <kdinh@apm.com>
	5	* Tanmay Inamdar <tinamdar@apm.com>
	6	* Iyappan Subramanian <isubramanian@apm.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef __XGENE_ENET_CLE_H__
	23	#define __XGENE_ENET_CLE_H__
	24
	25	#include <linux/io.h>
	26	#include <linux/random.h>
	27
	28	/* Register offsets */
	29	#define INDADDR 0x04
	30	#define INDCMD 0x08
	31	#define INDCMD_STATUS 0x0c
	32	#define DATA_RAM0 0x10
	33	#define SNPTR0 0x0100
	34	#define SPPTR0 0x0104
	35	#define DFCLSRESDBPTR0 0x0108
	36	#define DFCLSRESDB00 0x010c
	37
	38	#define CLE_CMD_TO 10 /* ms */
	39	#define CLE_PKTRAM_SIZE 256 /* bytes */
	40	#define CLE_PORT_OFFSET 0x200
	41	#define CLE_DRAM_REGS 17
	42
	43	#define CLE_DN_TYPE_LEN 2
	44	#define CLE_DN_TYPE_POS 0
	45	#define CLE_DN_LASTN_LEN 1
	46	#define CLE_DN_LASTN_POS 2
	47	#define CLE_DN_HLS_LEN 1
	48	#define CLE_DN_HLS_POS 3
	49	#define CLE_DN_EXT_LEN 2
	50	#define CLE_DN_EXT_POS 4
	51	#define CLE_DN_BSTOR_LEN 2
	52	#define CLE_DN_BSTOR_POS 6
	53	#define CLE_DN_SBSTOR_LEN 2
	54	#define CLE_DN_SBSTOR_POS 8
	55	#define CLE_DN_RPTR_LEN 12
	56	#define CLE_DN_RPTR_POS 12
	57
	58	#define CLE_BR_VALID_LEN 1
	59	#define CLE_BR_VALID_POS 0
	60	#define CLE_BR_NPPTR_LEN 9
	61	#define CLE_BR_NPPTR_POS 1
	62	#define CLE_BR_JB_LEN 1
	63	#define CLE_BR_JB_POS 10
	64	#define CLE_BR_JR_LEN 1
65	#define CLE_BR_JR_POS 11
66	#define CLE_BR_OP_LEN 3
67	#define CLE_BR_OP_POS 12
68	#define CLE_BR_NNODE_LEN 9
69	#define CLE_BR_NNODE_POS 15
70	#define CLE_BR_NBR_LEN 5
71	#define CLE_BR_NBR_POS 24
72
73	#define CLE_BR_DATA_LEN 16
74	#define CLE_BR_DATA_POS 0
75	#define CLE_BR_MASK_LEN 16
76	#define CLE_BR_MASK_POS 16
77
78	#define CLE_KN_PRIO_POS 0
79	#define CLE_KN_PRIO_LEN 3
80	#define CLE_KN_RPTR_POS 3
81	#define CLE_KN_RPTR_LEN 10
82	#define CLE_TYPE_POS 0
83	#define CLE_TYPE_LEN 2
84
85	#define CLE_DSTQIDL_POS 25
86	#define CLE_DSTQIDL_LEN 7
87	#define CLE_DSTQIDH_POS 0
88	#define CLE_DSTQIDH_LEN 5
89	#define CLE_FPSEL_POS 21
90	#define CLE_FPSEL_LEN 4
91	#define CLE_PRIORITY_POS 5
92	#define CLE_PRIORITY_LEN 3
93
94	#define JMP_ABS 0
95	#define JMP_REL 1
96	#define JMP_FW 0
97	#define JMP_BW 1
98
99	enum xgene_cle_ptree_nodes {
100	PKT_TYPE_NODE,
101	LAST_NODE,
102	MAX_NODES
103	};
104
105	enum xgene_cle_byte_store {
106	NO_BYTE,
107	FIRST_BYTE,
108	SECOND_BYTE,
109	BOTH_BYTES
110	};
111
112	/* Preclassification operation types */
113	enum xgene_cle_node_type {
114	INV,
115	KN,
116	EWDN,
117	RES_NODE
118	};
119
120	/* Preclassification operation types */
121	enum xgene_cle_op_type {
122	EQT,
123	NEQT,
124	LTEQT,
125	GTEQT,
126	AND,
127	NAND
128	};
129
130	enum xgene_cle_parser {
131	PARSER0,
132	PARSER1,
133	PARSER2,
134	PARSER_ALL
135	};
136
137	#define XGENE_CLE_DRAM(type) (((type) & 0xf) << 28)
138	enum xgene_cle_dram_type {
139	PKT_RAM,
140	PTREE_RAM = 0xc,
141	AVL_RAM,
142	DB_RAM
143	};
144
145	enum xgene_cle_cmd_type {
146	CLE_CMD_WR = 1,
147	CLE_CMD_RD = 2,
148	CLE_CMD_AVL_ADD = 8,
149	CLE_CMD_AVL_DEL = 16,
150	CLE_CMD_AVL_SRCH = 32
151	};
152
153	enum xgene_cle_ptree_dbptrs {
154	DB_RES_DROP,
155	DB_RES_DEF,
156	DB_RES_ACCEPT,
157	DB_MAX_PTRS
158	};
159
160	struct xgene_cle_ptree_branch {
161	bool valid;
162	u16 next_packet_pointer;
163	bool jump_bw;
164	bool jump_rel;
165	u8 operation;
166	u16 next_node;
167	u8 next_branch;
168	u16 data;
169	u16 mask;
170	};
171
172	struct xgene_cle_ptree_ewdn {
173	u8 node_type;
174	bool last_node;
175	bool hdr_len_store;
176	u8 hdr_extn;
177	u8 byte_store;
178	u8 search_byte_store;
179	u16 result_pointer;
180	u8 num_branches;
181	struct xgene_cle_ptree_branch branch[6];
182	};
183
184	struct xgene_cle_ptree_key {
185	u8 priority;
186	u16 result_pointer;
187	};
188
189	struct xgene_cle_ptree_kn {
190	u8 node_type;
191	u8 num_keys;
192	struct xgene_cle_ptree_key key[32];
193	};
194
195	struct xgene_cle_dbptr {
196	u8 split_boundary;
197	u8 mirror_nxtfpsel;
198	u8 mirror_fpsel;
199	u16 mirror_dstqid;
200	u8 drop;
201	u8 mirror;
202	u8 hdr_data_split;
203	u64 hopinfomsbs;
204	u8 DR;
205	u8 HR;
206	u64 hopinfomlsbs;
207	u16 h0enq_num;
208	u8 h0fpsel;
209	u8 nxtfpsel;
210	u8 fpsel;
211	u16 dstqid;
212	u8 cle_priority;
213	u8 cle_flowgroup;
214	u8 cle_perflow;
215	u8 cle_insert_timestamp;
216	u8 stash;
217	u8 in;
218	u8 perprioen;
219	u8 perflowgroupen;
220	u8 perflowen;
221	u8 selhash;
222	u8 selhdrext;
223	u8 mirror_nxtfpsel_msb;
224	u8 mirror_fpsel_msb;
225	u8 hfpsel_msb;
226	u8 nxtfpsel_msb;
227	u8 fpsel_msb;
228	};
229
230	struct xgene_cle_ptree {
231	struct xgene_cle_ptree_ewdn *dn;
232	struct xgene_cle_ptree_kn *kn;
233	struct xgene_cle_dbptr *dbptr;
234	u32 num_dn;
235	u32 num_kn;
236	u32 num_dbptr;
237	u32 start_node;
238	u32 start_pkt;
239	u32 start_dbptr;
240	};
241
242	struct xgene_enet_cle {
243	void __iomem *base;
244	struct xgene_cle_ptree ptree;
245	enum xgene_cle_parser active_parser;
246	u32 parsers;
247	u32 max_nodes;
248	u32 max_dbptrs;
249	u32 jump_bytes;
250	};
251
252	extern struct xgene_cle_ops xgene_cle3in_ops;
253
254	#endif /* __XGENE_ENET_CLE_H__ */