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Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / net / ethernet / amazon / ena / ena_netdev.c
CommitLineData
1738cd3e
NB		 1/*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#ifdef CONFIG_RFS_ACCEL
36#include <linux/cpu_rmap.h>
37#endif /* CONFIG_RFS_ACCEL */
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
1738cd3e
NB		 42#include <linux/numa.h>
43#include <linux/pci.h>
44#include <linux/utsname.h>
45#include <linux/version.h>
46#include <linux/vmalloc.h>
47#include <net/ip.h>
48
49#include "ena_netdev.h"
50#include "ena_pci_id_tbl.h"
51
52static char version[] = DEVICE_NAME " v" DRV_MODULE_VERSION "\n";
53
54MODULE_AUTHOR("Amazon.com, Inc. or its affiliates");
55MODULE_DESCRIPTION(DEVICE_NAME);
56MODULE_LICENSE("GPL");
57MODULE_VERSION(DRV_MODULE_VERSION);
58
59/* Time in jiffies before concluding the transmitter is hung. */
60#define TX_TIMEOUT (5 * HZ)
61
62#define ENA_NAPI_BUDGET 64
63
64#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | \
65 NETIF_MSG_TX_DONE | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR)
66static int debug = -1;
67module_param(debug, int, 0);
68MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70static struct ena_aenq_handlers aenq_handlers;
71
72static struct workqueue_struct *ena_wq;
73
74MODULE_DEVICE_TABLE(pci, ena_pci_tbl);
75
76static int ena_rss_init_default(struct ena_adapter *adapter);
ee4552aa 77static void check_for_admin_com_state(struct ena_adapter *adapter);
cfa324a5 78static void ena_destroy_device(struct ena_adapter *adapter, bool graceful);
ee4552aa 79static int ena_restore_device(struct ena_adapter *adapter);
1738cd3e
NB		 80
81static void ena_tx_timeout(struct net_device *dev)
82{
83 struct ena_adapter *adapter = netdev_priv(dev);
84
3f6159db
NB		 85 /* Change the state of the device to trigger reset
86 * Check that we are not in the middle or a trigger already
87 */
88
89 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
90 return;
91
e2eed0e3 92 adapter->reset_reason = ENA_REGS_RESET_OS_NETDEV_WD;
1738cd3e
NB		 93 u64_stats_update_begin(&adapter->syncp);
94 adapter->dev_stats.tx_timeout++;
95 u64_stats_update_end(&adapter->syncp);
96
97 netif_err(adapter, tx_err, dev, "Transmit time out\n");
1738cd3e
NB		 98}
99
100static void update_rx_ring_mtu(struct ena_adapter *adapter, int mtu)
101{
102 int i;
103
faa615f9 104 for (i = 0; i < adapter->num_io_queues; i++)
1738cd3e
NB		 105 adapter->rx_ring[i].mtu = mtu;
106}
107
108static int ena_change_mtu(struct net_device *dev, int new_mtu)
109{
110 struct ena_adapter *adapter = netdev_priv(dev);
111 int ret;
112
1738cd3e
NB		 113 ret = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu);
114 if (!ret) {
115 netif_dbg(adapter, drv, dev, "set MTU to %d\n", new_mtu);
116 update_rx_ring_mtu(adapter, new_mtu);
117 dev->mtu = new_mtu;
118 } else {
119 netif_err(adapter, drv, dev, "Failed to set MTU to %d\n",
120 new_mtu);
121 }
122
123 return ret;
124}
125
126static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter)
127{
128#ifdef CONFIG_RFS_ACCEL
129 u32 i;
130 int rc;
131
faa615f9 132 adapter->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(adapter->num_io_queues);
1738cd3e
NB		 133 if (!adapter->netdev->rx_cpu_rmap)
134 return -ENOMEM;
faa615f9 135 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 136 int irq_idx = ENA_IO_IRQ_IDX(i);
137
138 rc = irq_cpu_rmap_add(adapter->netdev->rx_cpu_rmap,
da6f4cf5 139 pci_irq_vector(adapter->pdev, irq_idx));
1738cd3e
NB		 140 if (rc) {
141 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
142 adapter->netdev->rx_cpu_rmap = NULL;
143 return rc;
144 }
145 }
146#endif /* CONFIG_RFS_ACCEL */
147 return 0;
148}
149
150static void ena_init_io_rings_common(struct ena_adapter *adapter,
151 struct ena_ring *ring, u16 qid)
152{
153 ring->qid = qid;
154 ring->pdev = adapter->pdev;
155 ring->dev = &adapter->pdev->dev;
156 ring->netdev = adapter->netdev;
157 ring->napi = &adapter->ena_napi[qid].napi;
158 ring->adapter = adapter;
159 ring->ena_dev = adapter->ena_dev;
160 ring->per_napi_packets = 0;
1738cd3e 161 ring->cpu = 0;
8510e1a3
NB		 162 ring->first_interrupt = false;
163 ring->no_interrupt_event_cnt = 0;
1738cd3e
NB		 164 u64_stats_init(&ring->syncp);
165}
166
167static void ena_init_io_rings(struct ena_adapter *adapter)
168{
169 struct ena_com_dev *ena_dev;
170 struct ena_ring *txr, *rxr;
171 int i;
172
173 ena_dev = adapter->ena_dev;
174
faa615f9 175 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 176 txr = &adapter->tx_ring[i];
177 rxr = &adapter->rx_ring[i];
178
179 /* TX/RX common ring state */
180 ena_init_io_rings_common(adapter, txr, i);
181 ena_init_io_rings_common(adapter, rxr, i);
182
183 /* TX specific ring state */
13ca32a6 184 txr->ring_size = adapter->requested_tx_ring_size;
1738cd3e
NB		 185 txr->tx_max_header_size = ena_dev->tx_max_header_size;
186 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type;
187 txr->sgl_size = adapter->max_tx_sgl_size;
188 txr->smoothed_interval =
189 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev);
190
191 /* RX specific ring state */
13ca32a6 192 rxr->ring_size = adapter->requested_rx_ring_size;
1738cd3e
NB		 193 rxr->rx_copybreak = adapter->rx_copybreak;
194 rxr->sgl_size = adapter->max_rx_sgl_size;
195 rxr->smoothed_interval =
196 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev);
a3af7c18 197 rxr->empty_rx_queue = 0;
282faf61 198 adapter->ena_napi[i].dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1738cd3e
NB		 199 }
200}
201
202/* ena_setup_tx_resources - allocate I/O Tx resources (Descriptors)
203 * @adapter: network interface device structure
204 * @qid: queue index
205 *
206 * Return 0 on success, negative on failure
207 */
208static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid)
209{
210 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
211 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
212 int size, i, node;
213
214 if (tx_ring->tx_buffer_info) {
215 netif_err(adapter, ifup,
216 adapter->netdev, "tx_buffer_info info is not NULL");
217 return -EEXIST;
218 }
219
220 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size;
221 node = cpu_to_node(ena_irq->cpu);
222
223 tx_ring->tx_buffer_info = vzalloc_node(size, node);
224 if (!tx_ring->tx_buffer_info) {
225 tx_ring->tx_buffer_info = vzalloc(size);
226 if (!tx_ring->tx_buffer_info)
8ee8ee7f 227 goto err_tx_buffer_info;
1738cd3e
NB		 228 }
229
230 size = sizeof(u16) * tx_ring->ring_size;
f9172498
SJ		 231 tx_ring->free_ids = vzalloc_node(size, node);
232 if (!tx_ring->free_ids) {
233 tx_ring->free_ids = vzalloc(size);
234 if (!tx_ring->free_ids)
235 goto err_tx_free_ids;
1738cd3e
NB		 236 }
237
38005ca8
AK		 238 size = tx_ring->tx_max_header_size;
239 tx_ring->push_buf_intermediate_buf = vzalloc_node(size, node);
240 if (!tx_ring->push_buf_intermediate_buf) {
241 tx_ring->push_buf_intermediate_buf = vzalloc(size);
8ee8ee7f
SJ		 242 if (!tx_ring->push_buf_intermediate_buf)
243 goto err_push_buf_intermediate_buf;
38005ca8
AK		 244 }
245
1738cd3e
NB		 246 /* Req id ring for TX out of order completions */
247 for (i = 0; i < tx_ring->ring_size; i++)
f9172498 248 tx_ring->free_ids[i] = i;
1738cd3e
NB		 249
250 /* Reset tx statistics */
251 memset(&tx_ring->tx_stats, 0x0, sizeof(tx_ring->tx_stats));
252
253 tx_ring->next_to_use = 0;
254 tx_ring->next_to_clean = 0;
255 tx_ring->cpu = ena_irq->cpu;
256 return 0;
8ee8ee7f
SJ		 257
258err_push_buf_intermediate_buf:
f9172498
SJ		 259 vfree(tx_ring->free_ids);
260 tx_ring->free_ids = NULL;
261err_tx_free_ids:
8ee8ee7f
SJ		 262 vfree(tx_ring->tx_buffer_info);
263 tx_ring->tx_buffer_info = NULL;
264err_tx_buffer_info:
265 return -ENOMEM;
1738cd3e
NB		 266}
267
268/* ena_free_tx_resources - Free I/O Tx Resources per Queue
269 * @adapter: network interface device structure
270 * @qid: queue index
271 *
272 * Free all transmit software resources
273 */
274static void ena_free_tx_resources(struct ena_adapter *adapter, int qid)
275{
276 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
277
278 vfree(tx_ring->tx_buffer_info);
279 tx_ring->tx_buffer_info = NULL;
280
f9172498
SJ		 281 vfree(tx_ring->free_ids);
282 tx_ring->free_ids = NULL;
38005ca8
AK		 283
284 vfree(tx_ring->push_buf_intermediate_buf);
285 tx_ring->push_buf_intermediate_buf = NULL;
1738cd3e
NB		 286}
287
288/* ena_setup_all_tx_resources - allocate I/O Tx queues resources for All queues
289 * @adapter: private structure
290 *
291 * Return 0 on success, negative on failure
292 */
293static int ena_setup_all_tx_resources(struct ena_adapter *adapter)
294{
295 int i, rc = 0;
296
faa615f9 297 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 298 rc = ena_setup_tx_resources(adapter, i);
299 if (rc)
300 goto err_setup_tx;
301 }
302
303 return 0;
304
305err_setup_tx:
306
307 netif_err(adapter, ifup, adapter->netdev,
308 "Tx queue %d: allocation failed\n", i);
309
310 /* rewind the index freeing the rings as we go */
311 while (i--)
312 ena_free_tx_resources(adapter, i);
313 return rc;
314}
315
316/* ena_free_all_io_tx_resources - Free I/O Tx Resources for All Queues
317 * @adapter: board private structure
318 *
319 * Free all transmit software resources
320 */
321static void ena_free_all_io_tx_resources(struct ena_adapter *adapter)
322{
323 int i;
324
faa615f9 325 for (i = 0; i < adapter->num_io_queues; i++)
1738cd3e
NB		 326 ena_free_tx_resources(adapter, i);
327}
328
c2b54204 329static int validate_rx_req_id(struct ena_ring *rx_ring, u16 req_id)
ad974bae
NB		 330{
331 if (likely(req_id < rx_ring->ring_size))
332 return 0;
333
334 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
335 "Invalid rx req_id: %hu\n", req_id);
336
337 u64_stats_update_begin(&rx_ring->syncp);
338 rx_ring->rx_stats.bad_req_id++;
339 u64_stats_update_end(&rx_ring->syncp);
340
341 /* Trigger device reset */
342 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
343 set_bit(ENA_FLAG_TRIGGER_RESET, &rx_ring->adapter->flags);
344 return -EFAULT;
345}
346
1738cd3e
NB		 347/* ena_setup_rx_resources - allocate I/O Rx resources (Descriptors)
348 * @adapter: network interface device structure
349 * @qid: queue index
350 *
351 * Returns 0 on success, negative on failure
352 */
353static int ena_setup_rx_resources(struct ena_adapter *adapter,
354 u32 qid)
355{
356 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
357 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
ad974bae 358 int size, node, i;
1738cd3e
NB		 359
360 if (rx_ring->rx_buffer_info) {
361 netif_err(adapter, ifup, adapter->netdev,
362 "rx_buffer_info is not NULL");
363 return -EEXIST;
364 }
365
366 /* alloc extra element so in rx path
367 * we can always prefetch rx_info + 1
368 */
369 size = sizeof(struct ena_rx_buffer) * (rx_ring->ring_size + 1);
370 node = cpu_to_node(ena_irq->cpu);
371
372 rx_ring->rx_buffer_info = vzalloc_node(size, node);
373 if (!rx_ring->rx_buffer_info) {
374 rx_ring->rx_buffer_info = vzalloc(size);
375 if (!rx_ring->rx_buffer_info)
376 return -ENOMEM;
377 }
378
ad974bae 379 size = sizeof(u16) * rx_ring->ring_size;
f9172498
SJ		 380 rx_ring->free_ids = vzalloc_node(size, node);
381 if (!rx_ring->free_ids) {
382 rx_ring->free_ids = vzalloc(size);
383 if (!rx_ring->free_ids) {
ad974bae 384 vfree(rx_ring->rx_buffer_info);
8ee8ee7f 385 rx_ring->rx_buffer_info = NULL;
ad974bae
NB		 386 return -ENOMEM;
387 }
388 }
389
390 /* Req id ring for receiving RX pkts out of order */
391 for (i = 0; i < rx_ring->ring_size; i++)
f9172498 392 rx_ring->free_ids[i] = i;
ad974bae 393
1738cd3e
NB		 394 /* Reset rx statistics */
395 memset(&rx_ring->rx_stats, 0x0, sizeof(rx_ring->rx_stats));
396
397 rx_ring->next_to_clean = 0;
398 rx_ring->next_to_use = 0;
399 rx_ring->cpu = ena_irq->cpu;
400
401 return 0;
402}
403
404/* ena_free_rx_resources - Free I/O Rx Resources
405 * @adapter: network interface device structure
406 * @qid: queue index
407 *
408 * Free all receive software resources
409 */
410static void ena_free_rx_resources(struct ena_adapter *adapter,
411 u32 qid)
412{
413 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
414
415 vfree(rx_ring->rx_buffer_info);
416 rx_ring->rx_buffer_info = NULL;
ad974bae 417
f9172498
SJ		 418 vfree(rx_ring->free_ids);
419 rx_ring->free_ids = NULL;
1738cd3e
NB		 420}
421
422/* ena_setup_all_rx_resources - allocate I/O Rx queues resources for all queues
423 * @adapter: board private structure
424 *
425 * Return 0 on success, negative on failure
426 */
427static int ena_setup_all_rx_resources(struct ena_adapter *adapter)
428{
429 int i, rc = 0;
430
faa615f9 431 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 432 rc = ena_setup_rx_resources(adapter, i);
433 if (rc)
434 goto err_setup_rx;
435 }
436
437 return 0;
438
439err_setup_rx:
440
441 netif_err(adapter, ifup, adapter->netdev,
442 "Rx queue %d: allocation failed\n", i);
443
444 /* rewind the index freeing the rings as we go */
445 while (i--)
446 ena_free_rx_resources(adapter, i);
447 return rc;
448}
449
450/* ena_free_all_io_rx_resources - Free I/O Rx Resources for All Queues
451 * @adapter: board private structure
452 *
453 * Free all receive software resources
454 */
455static void ena_free_all_io_rx_resources(struct ena_adapter *adapter)
456{
457 int i;
458
faa615f9 459 for (i = 0; i < adapter->num_io_queues; i++)
1738cd3e
NB		 460 ena_free_rx_resources(adapter, i);
461}
462
c2b54204 463static int ena_alloc_rx_page(struct ena_ring *rx_ring,
1738cd3e
NB		 464 struct ena_rx_buffer *rx_info, gfp_t gfp)
465{
466 struct ena_com_buf *ena_buf;
467 struct page *page;
468 dma_addr_t dma;
469
470 /* if previous allocated page is not used */
471 if (unlikely(rx_info->page))
472 return 0;
473
474 page = alloc_page(gfp);
475 if (unlikely(!page)) {
476 u64_stats_update_begin(&rx_ring->syncp);
477 rx_ring->rx_stats.page_alloc_fail++;
478 u64_stats_update_end(&rx_ring->syncp);
479 return -ENOMEM;
480 }
481
ef5b0771 482 dma = dma_map_page(rx_ring->dev, page, 0, ENA_PAGE_SIZE,
1738cd3e
NB		 483 DMA_FROM_DEVICE);
484 if (unlikely(dma_mapping_error(rx_ring->dev, dma))) {
485 u64_stats_update_begin(&rx_ring->syncp);
486 rx_ring->rx_stats.dma_mapping_err++;
487 u64_stats_update_end(&rx_ring->syncp);
488
489 __free_page(page);
490 return -EIO;
491 }
492 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
493 "alloc page %p, rx_info %p\n", page, rx_info);
494
495 rx_info->page = page;
496 rx_info->page_offset = 0;
497 ena_buf = &rx_info->ena_buf;
498 ena_buf->paddr = dma;
ef5b0771 499 ena_buf->len = ENA_PAGE_SIZE;
1738cd3e
NB		 500
501 return 0;
502}
503
504static void ena_free_rx_page(struct ena_ring *rx_ring,
505 struct ena_rx_buffer *rx_info)
506{
507 struct page *page = rx_info->page;
508 struct ena_com_buf *ena_buf = &rx_info->ena_buf;
509
510 if (unlikely(!page)) {
511 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
512 "Trying to free unallocated buffer\n");
513 return;
514 }
515
ef5b0771 516 dma_unmap_page(rx_ring->dev, ena_buf->paddr, ENA_PAGE_SIZE,
1738cd3e
NB		 517 DMA_FROM_DEVICE);
518
519 __free_page(page);
520 rx_info->page = NULL;
521}
522
523static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num)
524{
ad974bae 525 u16 next_to_use, req_id;
1738cd3e
NB		 526 u32 i;
527 int rc;
528
529 next_to_use = rx_ring->next_to_use;
530
531 for (i = 0; i < num; i++) {
ad974bae
NB		 532 struct ena_rx_buffer *rx_info;
533
f9172498 534 req_id = rx_ring->free_ids[next_to_use];
ad974bae
NB		 535 rc = validate_rx_req_id(rx_ring, req_id);
536 if (unlikely(rc < 0))
537 break;
538
539 rx_info = &rx_ring->rx_buffer_info[req_id];
540
1738cd3e
NB		 541
542 rc = ena_alloc_rx_page(rx_ring, rx_info,
453f85d4 543 GFP_ATOMIC | __GFP_COMP);
1738cd3e
NB		 544 if (unlikely(rc < 0)) {
545 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
546 "failed to alloc buffer for rx queue %d\n",
547 rx_ring->qid);
548 break;
549 }
550 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq,
551 &rx_info->ena_buf,
ad974bae 552 req_id);
1738cd3e
NB		 553 if (unlikely(rc)) {
554 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
555 "failed to add buffer for rx queue %d\n",
556 rx_ring->qid);
557 break;
558 }
559 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use,
560 rx_ring->ring_size);
561 }
562
563 if (unlikely(i < num)) {
564 u64_stats_update_begin(&rx_ring->syncp);
565 rx_ring->rx_stats.refil_partial++;
566 u64_stats_update_end(&rx_ring->syncp);
567 netdev_warn(rx_ring->netdev,
568 "refilled rx qid %d with only %d buffers (from %d)\n",
569 rx_ring->qid, i, num);
570 }
571
37dff155
NB		 572 /* ena_com_write_sq_doorbell issues a wmb() */
573 if (likely(i))
574 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq);
1738cd3e
NB		 575
576 rx_ring->next_to_use = next_to_use;
577
578 return i;
579}
580
581static void ena_free_rx_bufs(struct ena_adapter *adapter,
582 u32 qid)
583{
584 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
585 u32 i;
586
587 for (i = 0; i < rx_ring->ring_size; i++) {
588 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i];
589
590 if (rx_info->page)
591 ena_free_rx_page(rx_ring, rx_info);
592 }
593}
594
595/* ena_refill_all_rx_bufs - allocate all queues Rx buffers
596 * @adapter: board private structure
1738cd3e
NB		 597 */
598static void ena_refill_all_rx_bufs(struct ena_adapter *adapter)
599{
600 struct ena_ring *rx_ring;
601 int i, rc, bufs_num;
602
faa615f9 603 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 604 rx_ring = &adapter->rx_ring[i];
605 bufs_num = rx_ring->ring_size - 1;
606 rc = ena_refill_rx_bufs(rx_ring, bufs_num);
607
608 if (unlikely(rc != bufs_num))
609 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
610 "refilling Queue %d failed. allocated %d buffers from: %d\n",
611 i, rc, bufs_num);
612 }
613}
614
615static void ena_free_all_rx_bufs(struct ena_adapter *adapter)
616{
617 int i;
618
faa615f9 619 for (i = 0; i < adapter->num_io_queues; i++)
1738cd3e
NB		 620 ena_free_rx_bufs(adapter, i);
621}
622
c2b54204 623static void ena_unmap_tx_skb(struct ena_ring *tx_ring,
38005ca8
AK		 624 struct ena_tx_buffer *tx_info)
625{
626 struct ena_com_buf *ena_buf;
627 u32 cnt;
628 int i;
629
630 ena_buf = tx_info->bufs;
631 cnt = tx_info->num_of_bufs;
632
633 if (unlikely(!cnt))
634 return;
635
636 if (tx_info->map_linear_data) {
637 dma_unmap_single(tx_ring->dev,
638 dma_unmap_addr(ena_buf, paddr),
639 dma_unmap_len(ena_buf, len),
640 DMA_TO_DEVICE);
641 ena_buf++;
642 cnt--;
643 }
644
645 /* unmap remaining mapped pages */
646 for (i = 0; i < cnt; i++) {
647 dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
648 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
649 ena_buf++;
650 }
651}
652
1738cd3e
NB		 653/* ena_free_tx_bufs - Free Tx Buffers per Queue
654 * @tx_ring: TX ring for which buffers be freed
655 */
656static void ena_free_tx_bufs(struct ena_ring *tx_ring)
657{
5add6e4a 658 bool print_once = true;
1738cd3e
NB		 659 u32 i;
660
661 for (i = 0; i < tx_ring->ring_size; i++) {
662 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i];
1738cd3e
NB		 663
664 if (!tx_info->skb)
665 continue;
666
5add6e4a
NB		 667 if (print_once) {
668 netdev_notice(tx_ring->netdev,
669 "free uncompleted tx skb qid %d idx 0x%x\n",
670 tx_ring->qid, i);
671 print_once = false;
672 } else {
673 netdev_dbg(tx_ring->netdev,
674 "free uncompleted tx skb qid %d idx 0x%x\n",
675 tx_ring->qid, i);
676 }
1738cd3e 677
38005ca8 678 ena_unmap_tx_skb(tx_ring, tx_info);
1738cd3e
NB		 679
680 dev_kfree_skb_any(tx_info->skb);
681 }
682 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
683 tx_ring->qid));
684}
685
686static void ena_free_all_tx_bufs(struct ena_adapter *adapter)
687{
688 struct ena_ring *tx_ring;
689 int i;
690
faa615f9 691 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 692 tx_ring = &adapter->tx_ring[i];
693 ena_free_tx_bufs(tx_ring);
694 }
695}
696
697static void ena_destroy_all_tx_queues(struct ena_adapter *adapter)
698{
699 u16 ena_qid;
700 int i;
701
faa615f9 702 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 703 ena_qid = ENA_IO_TXQ_IDX(i);
704 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
705 }
706}
707
708static void ena_destroy_all_rx_queues(struct ena_adapter *adapter)
709{
710 u16 ena_qid;
711 int i;
712
faa615f9 713 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e 714 ena_qid = ENA_IO_RXQ_IDX(i);
282faf61 715 cancel_work_sync(&adapter->ena_napi[i].dim.work);
1738cd3e
NB		 716 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
717 }
718}
719
720static void ena_destroy_all_io_queues(struct ena_adapter *adapter)
721{
722 ena_destroy_all_tx_queues(adapter);
723 ena_destroy_all_rx_queues(adapter);
724}
725
726static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
727{
728 struct ena_tx_buffer *tx_info = NULL;
729
730 if (likely(req_id < tx_ring->ring_size)) {
731 tx_info = &tx_ring->tx_buffer_info[req_id];
732 if (likely(tx_info->skb))
733 return 0;
734 }
735
736 if (tx_info)
737 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
738 "tx_info doesn't have valid skb\n");
739 else
740 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
741 "Invalid req_id: %hu\n", req_id);
742
743 u64_stats_update_begin(&tx_ring->syncp);
744 tx_ring->tx_stats.bad_req_id++;
745 u64_stats_update_end(&tx_ring->syncp);
746
747 /* Trigger device reset */
e2eed0e3 748 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
1738cd3e
NB		 749 set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags);
750 return -EFAULT;
751}
752
753static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
754{
755 struct netdev_queue *txq;
756 bool above_thresh;
757 u32 tx_bytes = 0;
758 u32 total_done = 0;
759 u16 next_to_clean;
760 u16 req_id;
761 int tx_pkts = 0;
762 int rc;
763
764 next_to_clean = tx_ring->next_to_clean;
765 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->qid);
766
767 while (tx_pkts < budget) {
768 struct ena_tx_buffer *tx_info;
769 struct sk_buff *skb;
1738cd3e
NB		 770
771 rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq,
772 &req_id);
773 if (rc)
774 break;
775
776 rc = validate_tx_req_id(tx_ring, req_id);
777 if (rc)
778 break;
779
780 tx_info = &tx_ring->tx_buffer_info[req_id];
781 skb = tx_info->skb;
782
783 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
784 prefetch(&skb->end);
785
786 tx_info->skb = NULL;
787 tx_info->last_jiffies = 0;
788
38005ca8 789 ena_unmap_tx_skb(tx_ring, tx_info);
1738cd3e
NB		 790
791 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
792 "tx_poll: q %d skb %p completed\n", tx_ring->qid,
793 skb);
794
795 tx_bytes += skb->len;
796 dev_kfree_skb(skb);
797 tx_pkts++;
798 total_done += tx_info->tx_descs;
799
f9172498 800 tx_ring->free_ids[next_to_clean] = req_id;
1738cd3e
NB		 801 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,
802 tx_ring->ring_size);
803 }
804
805 tx_ring->next_to_clean = next_to_clean;
806 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done);
807 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
808
809 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
810
811 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
812 "tx_poll: q %d done. total pkts: %d\n",
813 tx_ring->qid, tx_pkts);
814
815 /* need to make the rings circular update visible to
816 * ena_start_xmit() before checking for netif_queue_stopped().
817 */
818 smp_mb();
819
689b2bda
AK		 820 above_thresh = ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
821 ENA_TX_WAKEUP_THRESH);
1738cd3e
NB		 822 if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) {
823 __netif_tx_lock(txq, smp_processor_id());
689b2bda
AK		 824 above_thresh =
825 ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
826 ENA_TX_WAKEUP_THRESH);
a53651ec
SJ		 827 if (netif_tx_queue_stopped(txq) && above_thresh &&
828 test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags)) {
1738cd3e
NB		 829 netif_tx_wake_queue(txq);
830 u64_stats_update_begin(&tx_ring->syncp);
831 tx_ring->tx_stats.queue_wakeup++;
832 u64_stats_update_end(&tx_ring->syncp);
833 }
834 __netif_tx_unlock(txq);
835 }
836
1738cd3e
NB		 837 return tx_pkts;
838}
839
4265114d
NB		 840static struct sk_buff *ena_alloc_skb(struct ena_ring *rx_ring, bool frags)
841{
842 struct sk_buff *skb;
843
844 if (frags)
845 skb = napi_get_frags(rx_ring->napi);
846 else
847 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
848 rx_ring->rx_copybreak);
849
850 if (unlikely(!skb)) {
851 u64_stats_update_begin(&rx_ring->syncp);
852 rx_ring->rx_stats.skb_alloc_fail++;
853 u64_stats_update_end(&rx_ring->syncp);
854 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev,
855 "Failed to allocate skb. frags: %d\n", frags);
856 return NULL;
857 }
858
859 return skb;
860}
861
1738cd3e
NB		 862static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,
863 struct ena_com_rx_buf_info *ena_bufs,
864 u32 descs,
865 u16 *next_to_clean)
866{
867 struct sk_buff *skb;
ad974bae
NB		 868 struct ena_rx_buffer *rx_info;
869 u16 len, req_id, buf = 0;
1738cd3e
NB		 870 void *va;
871
ad974bae
NB		 872 len = ena_bufs[buf].len;
873 req_id = ena_bufs[buf].req_id;
874 rx_info = &rx_ring->rx_buffer_info[req_id];
875
1738cd3e
NB		 876 if (unlikely(!rx_info->page)) {
877 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
878 "Page is NULL\n");
879 return NULL;
880 }
881
882 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
883 "rx_info %p page %p\n",
884 rx_info, rx_info->page);
885
886 /* save virt address of first buffer */
887 va = page_address(rx_info->page) + rx_info->page_offset;
888 prefetch(va + NET_IP_ALIGN);
889
890 if (len <= rx_ring->rx_copybreak) {
4265114d
NB		 891 skb = ena_alloc_skb(rx_ring, false);
892 if (unlikely(!skb))
1738cd3e 893 return NULL;
1738cd3e
NB		 894
895 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
896 "rx allocated small packet. len %d. data_len %d\n",
897 skb->len, skb->data_len);
898
899 /* sync this buffer for CPU use */
900 dma_sync_single_for_cpu(rx_ring->dev,
901 dma_unmap_addr(&rx_info->ena_buf, paddr),
902 len,
903 DMA_FROM_DEVICE);
904 skb_copy_to_linear_data(skb, va, len);
905 dma_sync_single_for_device(rx_ring->dev,
906 dma_unmap_addr(&rx_info->ena_buf, paddr),
907 len,
908 DMA_FROM_DEVICE);
909
910 skb_put(skb, len);
911 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
f9172498 912 rx_ring->free_ids[*next_to_clean] = req_id;
1738cd3e
NB		 913 *next_to_clean = ENA_RX_RING_IDX_ADD(*next_to_clean, descs,
914 rx_ring->ring_size);
915 return skb;
916 }
917
4265114d
NB		 918 skb = ena_alloc_skb(rx_ring, true);
919 if (unlikely(!skb))
1738cd3e 920 return NULL;
1738cd3e
NB		 921
922 do {
923 dma_unmap_page(rx_ring->dev,
924 dma_unmap_addr(&rx_info->ena_buf, paddr),
ef5b0771 925 ENA_PAGE_SIZE, DMA_FROM_DEVICE);
1738cd3e
NB		 926
927 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page,
ef5b0771 928 rx_info->page_offset, len, ENA_PAGE_SIZE);
1738cd3e
NB		 929
930 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
931 "rx skb updated. len %d. data_len %d\n",
932 skb->len, skb->data_len);
933
934 rx_info->page = NULL;
ad974bae 935
f9172498 936 rx_ring->free_ids[*next_to_clean] = req_id;
1738cd3e
NB		 937 *next_to_clean =
938 ENA_RX_RING_IDX_NEXT(*next_to_clean,
939 rx_ring->ring_size);
940 if (likely(--descs == 0))
941 break;
ad974bae
NB		 942
943 buf++;
944 len = ena_bufs[buf].len;
945 req_id = ena_bufs[buf].req_id;
946 rx_info = &rx_ring->rx_buffer_info[req_id];
1738cd3e
NB		 947 } while (1);
948
949 return skb;
950}
951
952/* ena_rx_checksum - indicate in skb if hw indicated a good cksum
953 * @adapter: structure containing adapter specific data
954 * @ena_rx_ctx: received packet context/metadata
955 * @skb: skb currently being received and modified
956 */
c2b54204 957static void ena_rx_checksum(struct ena_ring *rx_ring,
1738cd3e
NB		 958 struct ena_com_rx_ctx *ena_rx_ctx,
959 struct sk_buff *skb)
960{
961 /* Rx csum disabled */
962 if (unlikely(!(rx_ring->netdev->features & NETIF_F_RXCSUM))) {
963 skb->ip_summed = CHECKSUM_NONE;
964 return;
965 }
966
967 /* For fragmented packets the checksum isn't valid */
968 if (ena_rx_ctx->frag) {
969 skb->ip_summed = CHECKSUM_NONE;
970 return;
971 }
972
973 /* if IP and error */
974 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) &&
975 (ena_rx_ctx->l3_csum_err))) {
976 /* ipv4 checksum error */
977 skb->ip_summed = CHECKSUM_NONE;
978 u64_stats_update_begin(&rx_ring->syncp);
979 rx_ring->rx_stats.bad_csum++;
980 u64_stats_update_end(&rx_ring->syncp);
cd7aea18 981 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev,
1738cd3e
NB		 982 "RX IPv4 header checksum error\n");
983 return;
984 }
985
986 /* if TCP/UDP */
987 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
988 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) {
989 if (unlikely(ena_rx_ctx->l4_csum_err)) {
990 /* TCP/UDP checksum error */
991 u64_stats_update_begin(&rx_ring->syncp);
992 rx_ring->rx_stats.bad_csum++;
993 u64_stats_update_end(&rx_ring->syncp);
cd7aea18 994 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev,
1738cd3e
NB		 995 "RX L4 checksum error\n");
996 skb->ip_summed = CHECKSUM_NONE;
997 return;
998 }
999
cb36bb36
AK		 1000 if (likely(ena_rx_ctx->l4_csum_checked)) {
1001 skb->ip_summed = CHECKSUM_UNNECESSARY;
d2eecc6e
SJ		 1002 u64_stats_update_begin(&rx_ring->syncp);
1003 rx_ring->rx_stats.csum_good++;
1004 u64_stats_update_end(&rx_ring->syncp);
cb36bb36
AK		 1005 } else {
1006 u64_stats_update_begin(&rx_ring->syncp);
1007 rx_ring->rx_stats.csum_unchecked++;
1008 u64_stats_update_end(&rx_ring->syncp);
1009 skb->ip_summed = CHECKSUM_NONE;
1010 }
1011 } else {
1012 skb->ip_summed = CHECKSUM_NONE;
1013 return;
1738cd3e 1014 }
cb36bb36 1015
1738cd3e
NB		 1016}
1017
1018static void ena_set_rx_hash(struct ena_ring *rx_ring,
1019 struct ena_com_rx_ctx *ena_rx_ctx,
1020 struct sk_buff *skb)
1021{
1022 enum pkt_hash_types hash_type;
1023
1024 if (likely(rx_ring->netdev->features & NETIF_F_RXHASH)) {
1025 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
1026 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)))
1027
1028 hash_type = PKT_HASH_TYPE_L4;
1029 else
1030 hash_type = PKT_HASH_TYPE_NONE;
1031
1032 /* Override hash type if the packet is fragmented */
1033 if (ena_rx_ctx->frag)
1034 hash_type = PKT_HASH_TYPE_NONE;
1035
1036 skb_set_hash(skb, ena_rx_ctx->hash, hash_type);
1037 }
1038}
1039
1040/* ena_clean_rx_irq - Cleanup RX irq
1041 * @rx_ring: RX ring to clean
1042 * @napi: napi handler
1043 * @budget: how many packets driver is allowed to clean
1044 *
1045 * Returns the number of cleaned buffers.
1046 */
1047static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
1048 u32 budget)
1049{
1050 u16 next_to_clean = rx_ring->next_to_clean;
1051 u32 res_budget, work_done;
1052
1053 struct ena_com_rx_ctx ena_rx_ctx;
1054 struct ena_adapter *adapter;
1055 struct sk_buff *skb;
1056 int refill_required;
1057 int refill_threshold;
1058 int rc = 0;
1059 int total_len = 0;
1060 int rx_copybreak_pkt = 0;
ad974bae 1061 int i;
1738cd3e
NB		 1062
1063 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
1064 "%s qid %d\n", __func__, rx_ring->qid);
1065 res_budget = budget;
1066
1067 do {
1068 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1069 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
1070 ena_rx_ctx.descs = 0;
1071 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1072 rx_ring->ena_com_io_sq,
1073 &ena_rx_ctx);
1074 if (unlikely(rc))
1075 goto error;
1076
1077 if (unlikely(ena_rx_ctx.descs == 0))
1078 break;
1079
1080 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
1081 "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",
1082 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
1083 ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
1084
1085 /* allocate skb and fill it */
1086 skb = ena_rx_skb(rx_ring, rx_ring->ena_bufs, ena_rx_ctx.descs,
1087 &next_to_clean);
1088
1089 /* exit if we failed to retrieve a buffer */
1090 if (unlikely(!skb)) {
ad974bae 1091 for (i = 0; i < ena_rx_ctx.descs; i++) {
f9172498 1092 rx_ring->free_ids[next_to_clean] =
ad974bae
NB		 1093 rx_ring->ena_bufs[i].req_id;
1094 next_to_clean =
1095 ENA_RX_RING_IDX_NEXT(next_to_clean,
1096 rx_ring->ring_size);
1097 }
1738cd3e
NB		 1098 break;
1099 }
1100
1101 ena_rx_checksum(rx_ring, &ena_rx_ctx, skb);
1102
1103 ena_set_rx_hash(rx_ring, &ena_rx_ctx, skb);
1104
1105 skb_record_rx_queue(skb, rx_ring->qid);
1106
1107 if (rx_ring->ena_bufs[0].len <= rx_ring->rx_copybreak) {
1108 total_len += rx_ring->ena_bufs[0].len;
1109 rx_copybreak_pkt++;
1110 napi_gro_receive(napi, skb);
1111 } else {
1112 total_len += skb->len;
1113 napi_gro_frags(napi);
1114 }
1115
1116 res_budget--;
1117 } while (likely(res_budget));
1118
1119 work_done = budget - res_budget;
1738cd3e
NB		 1120 rx_ring->per_napi_packets += work_done;
1121 u64_stats_update_begin(&rx_ring->syncp);
1122 rx_ring->rx_stats.bytes += total_len;
1123 rx_ring->rx_stats.cnt += work_done;
1124 rx_ring->rx_stats.rx_copybreak_pkt += rx_copybreak_pkt;
1125 u64_stats_update_end(&rx_ring->syncp);
1126
1127 rx_ring->next_to_clean = next_to_clean;
1128
689b2bda 1129 refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq);
0574bb80
AK		 1130 refill_threshold =
1131 min_t(int, rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER,
1132 ENA_RX_REFILL_THRESH_PACKET);
1738cd3e
NB		 1133
1134 /* Optimization, try to batch new rx buffers */
1135 if (refill_required > refill_threshold) {
1136 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
1137 ena_refill_rx_bufs(rx_ring, refill_required);
1138 }
1139
1140 return work_done;
1141
1142error:
1143 adapter = netdev_priv(rx_ring->netdev);
1144
1145 u64_stats_update_begin(&rx_ring->syncp);
1146 rx_ring->rx_stats.bad_desc_num++;
1147 u64_stats_update_end(&rx_ring->syncp);
1148
1149 /* Too many desc from the device. Trigger reset */
e2eed0e3 1150 adapter->reset_reason = ENA_REGS_RESET_TOO_MANY_RX_DESCS;
1738cd3e
NB		 1151 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
1152
1153 return 0;
1154}
1155
282faf61 1156static void ena_dim_work(struct work_struct *w)
1738cd3e 1157{
282faf61
AK		 1158 struct dim *dim = container_of(w, struct dim, work);
1159 struct dim_cq_moder cur_moder =
1160 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1161 struct ena_napi *ena_napi = container_of(dim, struct ena_napi, dim);
1162
1163 ena_napi->rx_ring->smoothed_interval = cur_moder.usec;
1164 dim->state = DIM_START_MEASURE;
1165}
1166
1167static void ena_adjust_adaptive_rx_intr_moderation(struct ena_napi *ena_napi)
1168{
1169 struct dim_sample dim_sample;
1170 struct ena_ring *rx_ring = ena_napi->rx_ring;
1171
1172 if (!rx_ring->per_napi_packets)
1173 return;
1174
1175 rx_ring->non_empty_napi_events++;
1176
1177 dim_update_sample(rx_ring->non_empty_napi_events,
1178 rx_ring->rx_stats.cnt,
1179 rx_ring->rx_stats.bytes,
1180 &dim_sample);
1181
1182 net_dim(&ena_napi->dim, dim_sample);
1183
1738cd3e 1184 rx_ring->per_napi_packets = 0;
1738cd3e
NB		 1185}
1186
c2b54204 1187static void ena_unmask_interrupt(struct ena_ring *tx_ring,
418df30f
NB		 1188 struct ena_ring *rx_ring)
1189{
1190 struct ena_eth_io_intr_reg intr_reg;
7b8a2878
AK		 1191 u32 rx_interval = ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev) ?
1192 rx_ring->smoothed_interval :
1193 ena_com_get_nonadaptive_moderation_interval_rx(rx_ring->ena_dev);
418df30f
NB		 1194
1195 /* Update intr register: rx intr delay,
1196 * tx intr delay and interrupt unmask
1197 */
1198 ena_com_update_intr_reg(&intr_reg,
7b8a2878 1199 rx_interval,
418df30f
NB		 1200 tx_ring->smoothed_interval,
1201 true);
1202
1203 /* It is a shared MSI-X.
1204 * Tx and Rx CQ have pointer to it.
1205 * So we use one of them to reach the intr reg
1206 */
1207 ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg);
1208}
1209
c2b54204 1210static void ena_update_ring_numa_node(struct ena_ring *tx_ring,
1738cd3e
NB		 1211 struct ena_ring *rx_ring)
1212{
1213 int cpu = get_cpu();
1214 int numa_node;
1215
1216 /* Check only one ring since the 2 rings are running on the same cpu */
1217 if (likely(tx_ring->cpu == cpu))
1218 goto out;
1219
1220 numa_node = cpu_to_node(cpu);
1221 put_cpu();
1222
1223 if (numa_node != NUMA_NO_NODE) {
1224 ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node);
1225 ena_com_update_numa_node(rx_ring->ena_com_io_cq, numa_node);
1226 }
1227
1228 tx_ring->cpu = cpu;
1229 rx_ring->cpu = cpu;
1230
1231 return;
1232out:
1233 put_cpu();
1234}
1235
1236static int ena_io_poll(struct napi_struct *napi, int budget)
1237{
1238 struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);
1239 struct ena_ring *tx_ring, *rx_ring;
1738cd3e
NB		 1240
1241 u32 tx_work_done;
1242 u32 rx_work_done;
1243 int tx_budget;
1244 int napi_comp_call = 0;
1245 int ret;
1246
1247 tx_ring = ena_napi->tx_ring;
1248 rx_ring = ena_napi->rx_ring;
1249
1250 tx_budget = tx_ring->ring_size / ENA_TX_POLL_BUDGET_DIVIDER;
1251
3f6159db
NB		 1252 if (!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1253 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags)) {
1738cd3e
NB		 1254 napi_complete_done(napi, 0);
1255 return 0;
1256 }
1257
1258 tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget);
1259 rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget);
1260
b1669c9f
NB		 1261 /* If the device is about to reset or down, avoid unmask
1262 * the interrupt and return 0 so NAPI won't reschedule
1263 */
1264 if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1265 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags))) {
1266 napi_complete_done(napi, 0);
1267 ret = 0;
1738cd3e 1268
b1669c9f 1269 } else if ((budget > rx_work_done) && (tx_budget > tx_work_done)) {
1738cd3e 1270 napi_comp_call = 1;
1738cd3e 1271
b1669c9f
NB		 1272 /* Update numa and unmask the interrupt only when schedule
1273 * from the interrupt context (vs from sk_busy_loop)
1738cd3e 1274 */
b1669c9f 1275 if (napi_complete_done(napi, rx_work_done)) {
282faf61
AK		 1276 /* We apply adaptive moderation on Rx path only.
1277 * Tx uses static interrupt moderation.
1278 */
b1669c9f 1279 if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev))
282faf61 1280 ena_adjust_adaptive_rx_intr_moderation(ena_napi);
b1669c9f 1281
418df30f 1282 ena_unmask_interrupt(tx_ring, rx_ring);
b1669c9f 1283 }
1738cd3e 1284
1738cd3e
NB		 1285 ena_update_ring_numa_node(tx_ring, rx_ring);
1286
1287 ret = rx_work_done;
1288 } else {
1289 ret = budget;
1290 }
1291
1292 u64_stats_update_begin(&tx_ring->syncp);
1293 tx_ring->tx_stats.napi_comp += napi_comp_call;
1294 tx_ring->tx_stats.tx_poll++;
1295 u64_stats_update_end(&tx_ring->syncp);
1296
1297 return ret;
1298}
1299
1300static irqreturn_t ena_intr_msix_mgmnt(int irq, void *data)
1301{
1302 struct ena_adapter *adapter = (struct ena_adapter *)data;
1303
1304 ena_com_admin_q_comp_intr_handler(adapter->ena_dev);
1305
1306 /* Don't call the aenq handler before probe is done */
1307 if (likely(test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)))
1308 ena_com_aenq_intr_handler(adapter->ena_dev, data);
1309
1310 return IRQ_HANDLED;
1311}
1312
1313/* ena_intr_msix_io - MSI-X Interrupt Handler for Tx/Rx
1314 * @irq: interrupt number
1315 * @data: pointer to a network interface private napi device structure
1316 */
1317static irqreturn_t ena_intr_msix_io(int irq, void *data)
1318{
1319 struct ena_napi *ena_napi = data;
1320
8510e1a3
NB		 1321 ena_napi->tx_ring->first_interrupt = true;
1322 ena_napi->rx_ring->first_interrupt = true;
1323
e745dafa 1324 napi_schedule_irqoff(&ena_napi->napi);
1738cd3e
NB		 1325
1326 return IRQ_HANDLED;
1327}
1328
06443684
NB		 1329/* Reserve a single MSI-X vector for management (admin + aenq).
1330 * plus reserve one vector for each potential io queue.
1331 * the number of potential io queues is the minimum of what the device
1332 * supports and the number of vCPUs.
1333 */
4d192660 1334static int ena_enable_msix(struct ena_adapter *adapter)
1738cd3e 1335{
06443684
NB		 1336 int msix_vecs, irq_cnt;
1337
1338 if (test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) {
1339 netif_err(adapter, probe, adapter->netdev,
1340 "Error, MSI-X is already enabled\n");
1341 return -EPERM;
1342 }
1738cd3e
NB		 1343
1344 /* Reserved the max msix vectors we might need */
4d192660 1345 msix_vecs = ENA_MAX_MSIX_VEC(adapter->num_io_queues);
1738cd3e
NB		 1346 netif_dbg(adapter, probe, adapter->netdev,
1347 "trying to enable MSI-X, vectors %d\n", msix_vecs);
1348
06443684
NB		 1349 irq_cnt = pci_alloc_irq_vectors(adapter->pdev, ENA_MIN_MSIX_VEC,
1350 msix_vecs, PCI_IRQ_MSIX);
1351
1352 if (irq_cnt < 0) {
1738cd3e 1353 netif_err(adapter, probe, adapter->netdev,
06443684 1354 "Failed to enable MSI-X. irq_cnt %d\n", irq_cnt);
1738cd3e
NB		 1355 return -ENOSPC;
1356 }
1357
06443684
NB		 1358 if (irq_cnt != msix_vecs) {
1359 netif_notice(adapter, probe, adapter->netdev,
1360 "enable only %d MSI-X (out of %d), reduce the number of queues\n",
1361 irq_cnt, msix_vecs);
faa615f9 1362 adapter->num_io_queues = irq_cnt - ENA_ADMIN_MSIX_VEC;
1738cd3e
NB		 1363 }
1364
06443684
NB		 1365 if (ena_init_rx_cpu_rmap(adapter))
1366 netif_warn(adapter, probe, adapter->netdev,
1367 "Failed to map IRQs to CPUs\n");
1368
1369 adapter->msix_vecs = irq_cnt;
1370 set_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags);
1738cd3e
NB		 1371
1372 return 0;
1373}
1374
1375static void ena_setup_mgmnt_intr(struct ena_adapter *adapter)
1376{
1377 u32 cpu;
1378
1379 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name,
1380 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s",
1381 pci_name(adapter->pdev));
1382 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler =
1383 ena_intr_msix_mgmnt;
1384 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter;
1385 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector =
da6f4cf5 1386 pci_irq_vector(adapter->pdev, ENA_MGMNT_IRQ_IDX);
1738cd3e
NB		 1387 cpu = cpumask_first(cpu_online_mask);
1388 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].cpu = cpu;
1389 cpumask_set_cpu(cpu,
1390 &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].affinity_hint_mask);
1391}
1392
1393static void ena_setup_io_intr(struct ena_adapter *adapter)
1394{
1395 struct net_device *netdev;
1396 int irq_idx, i, cpu;
1397
1398 netdev = adapter->netdev;
1399
faa615f9 1400 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 1401 irq_idx = ENA_IO_IRQ_IDX(i);
1402 cpu = i % num_online_cpus();
1403
1404 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE,
1405 "%s-Tx-Rx-%d", netdev->name, i);
1406 adapter->irq_tbl[irq_idx].handler = ena_intr_msix_io;
1407 adapter->irq_tbl[irq_idx].data = &adapter->ena_napi[i];
1408 adapter->irq_tbl[irq_idx].vector =
da6f4cf5 1409 pci_irq_vector(adapter->pdev, irq_idx);
1738cd3e
NB		 1410 adapter->irq_tbl[irq_idx].cpu = cpu;
1411
1412 cpumask_set_cpu(cpu,
1413 &adapter->irq_tbl[irq_idx].affinity_hint_mask);
1414 }
1415}
1416
1417static int ena_request_mgmnt_irq(struct ena_adapter *adapter)
1418{
1419 unsigned long flags = 0;
1420 struct ena_irq *irq;
1421 int rc;
1422
1423 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1424 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1425 irq->data);
1426 if (rc) {
1427 netif_err(adapter, probe, adapter->netdev,
1428 "failed to request admin irq\n");
1429 return rc;
1430 }
1431
1432 netif_dbg(adapter, probe, adapter->netdev,
1433 "set affinity hint of mgmnt irq.to 0x%lx (irq vector: %d)\n",
1434 irq->affinity_hint_mask.bits[0], irq->vector);
1435
1436 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1437
1438 return rc;
1439}
1440
1441static int ena_request_io_irq(struct ena_adapter *adapter)
1442{
1443 unsigned long flags = 0;
1444 struct ena_irq *irq;
1445 int rc = 0, i, k;
1446
06443684
NB		 1447 if (!test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) {
1448 netif_err(adapter, ifup, adapter->netdev,
1449 "Failed to request I/O IRQ: MSI-X is not enabled\n");
1450 return -EINVAL;
1451 }
1452
1738cd3e
NB		 1453 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1454 irq = &adapter->irq_tbl[i];
1455 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1456 irq->data);
1457 if (rc) {
1458 netif_err(adapter, ifup, adapter->netdev,
1459 "Failed to request I/O IRQ. index %d rc %d\n",
1460 i, rc);
1461 goto err;
1462 }
1463
1464 netif_dbg(adapter, ifup, adapter->netdev,
1465 "set affinity hint of irq. index %d to 0x%lx (irq vector: %d)\n",
1466 i, irq->affinity_hint_mask.bits[0], irq->vector);
1467
1468 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1469 }
1470
1471 return rc;
1472
1473err:
1474 for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) {
1475 irq = &adapter->irq_tbl[k];
1476 free_irq(irq->vector, irq->data);
1477 }
1478
1479 return rc;
1480}
1481
1482static void ena_free_mgmnt_irq(struct ena_adapter *adapter)
1483{
1484 struct ena_irq *irq;
1485
1486 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1487 synchronize_irq(irq->vector);
1488 irq_set_affinity_hint(irq->vector, NULL);
1489 free_irq(irq->vector, irq->data);
1490}
1491
1492static void ena_free_io_irq(struct ena_adapter *adapter)
1493{
1494 struct ena_irq *irq;
1495 int i;
1496
1497#ifdef CONFIG_RFS_ACCEL
1498 if (adapter->msix_vecs >= 1) {
1499 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
1500 adapter->netdev->rx_cpu_rmap = NULL;
1501 }
1502#endif /* CONFIG_RFS_ACCEL */
1503
1504 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1505 irq = &adapter->irq_tbl[i];
1506 irq_set_affinity_hint(irq->vector, NULL);
1507 free_irq(irq->vector, irq->data);
1508 }
1509}
1510
06443684
NB		 1511static void ena_disable_msix(struct ena_adapter *adapter)
1512{
1513 if (test_and_clear_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags))
1514 pci_free_irq_vectors(adapter->pdev);
1515}
1516
1738cd3e
NB		 1517static void ena_disable_io_intr_sync(struct ena_adapter *adapter)
1518{
1519 int i;
1520
1521 if (!netif_running(adapter->netdev))
1522 return;
1523
1524 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++)
1525 synchronize_irq(adapter->irq_tbl[i].vector);
1526}
1527
1528static void ena_del_napi(struct ena_adapter *adapter)
1529{
1530 int i;
1531
faa615f9 1532 for (i = 0; i < adapter->num_io_queues; i++)
1738cd3e
NB		 1533 netif_napi_del(&adapter->ena_napi[i].napi);
1534}
1535
1536static void ena_init_napi(struct ena_adapter *adapter)
1537{
1538 struct ena_napi *napi;
1539 int i;
1540
faa615f9 1541 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 1542 napi = &adapter->ena_napi[i];
1543
1544 netif_napi_add(adapter->netdev,
1545 &adapter->ena_napi[i].napi,
1546 ena_io_poll,
1547 ENA_NAPI_BUDGET);
1548 napi->rx_ring = &adapter->rx_ring[i];
1549 napi->tx_ring = &adapter->tx_ring[i];
1550 napi->qid = i;
1551 }
1552}
1553
1554static void ena_napi_disable_all(struct ena_adapter *adapter)
1555{
1556 int i;
1557
faa615f9 1558 for (i = 0; i < adapter->num_io_queues; i++)
1738cd3e
NB		 1559 napi_disable(&adapter->ena_napi[i].napi);
1560}
1561
1562static void ena_napi_enable_all(struct ena_adapter *adapter)
1563{
1564 int i;
1565
faa615f9 1566 for (i = 0; i < adapter->num_io_queues; i++)
1738cd3e
NB		 1567 napi_enable(&adapter->ena_napi[i].napi);
1568}
1569
1738cd3e
NB		 1570/* Configure the Rx forwarding */
1571static int ena_rss_configure(struct ena_adapter *adapter)
1572{
1573 struct ena_com_dev *ena_dev = adapter->ena_dev;
1574 int rc;
1575
1576 /* In case the RSS table wasn't initialized by probe */
1577 if (!ena_dev->rss.tbl_log_size) {
1578 rc = ena_rss_init_default(adapter);
d1497638 1579 if (rc && (rc != -EOPNOTSUPP)) {
1738cd3e
NB		 1580 netif_err(adapter, ifup, adapter->netdev,
1581 "Failed to init RSS rc: %d\n", rc);
1582 return rc;
1583 }
1584 }
1585
1586 /* Set indirect table */
1587 rc = ena_com_indirect_table_set(ena_dev);
d1497638 1588 if (unlikely(rc && rc != -EOPNOTSUPP))
1738cd3e
NB		 1589 return rc;
1590
1591 /* Configure hash function (if supported) */
1592 rc = ena_com_set_hash_function(ena_dev);
d1497638 1593 if (unlikely(rc && (rc != -EOPNOTSUPP)))
1738cd3e
NB		 1594 return rc;
1595
1596 /* Configure hash inputs (if supported) */
1597 rc = ena_com_set_hash_ctrl(ena_dev);
d1497638 1598 if (unlikely(rc && (rc != -EOPNOTSUPP)))
1738cd3e
NB		 1599 return rc;
1600
1601 return 0;
1602}
1603
1604static int ena_up_complete(struct ena_adapter *adapter)
1605{
7853b49c 1606 int rc;
1738cd3e
NB		 1607
1608 rc = ena_rss_configure(adapter);
1609 if (rc)
1610 return rc;
1611
1738cd3e
NB		 1612 ena_change_mtu(adapter->netdev, adapter->netdev->mtu);
1613
1614 ena_refill_all_rx_bufs(adapter);
1615
1616 /* enable transmits */
1617 netif_tx_start_all_queues(adapter->netdev);
1618
1738cd3e
NB		 1619 ena_napi_enable_all(adapter);
1620
1738cd3e
NB		 1621 return 0;
1622}
1623
1624static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
1625{
38005ca8 1626 struct ena_com_create_io_ctx ctx;
1738cd3e
NB		 1627 struct ena_com_dev *ena_dev;
1628 struct ena_ring *tx_ring;
1629 u32 msix_vector;
1630 u16 ena_qid;
1631 int rc;
1632
1633 ena_dev = adapter->ena_dev;
1634
1635 tx_ring = &adapter->tx_ring[qid];
1636 msix_vector = ENA_IO_IRQ_IDX(qid);
1637 ena_qid = ENA_IO_TXQ_IDX(qid);
1638
38005ca8
AK		 1639 memset(&ctx, 0x0, sizeof(ctx));
1640
1738cd3e
NB		 1641 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1642 ctx.qid = ena_qid;
1643 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1644 ctx.msix_vector = msix_vector;
13ca32a6 1645 ctx.queue_size = tx_ring->ring_size;
1738cd3e
NB		 1646 ctx.numa_node = cpu_to_node(tx_ring->cpu);
1647
1648 rc = ena_com_create_io_queue(ena_dev, &ctx);
1649 if (rc) {
1650 netif_err(adapter, ifup, adapter->netdev,
1651 "Failed to create I/O TX queue num %d rc: %d\n",
1652 qid, rc);
1653 return rc;
1654 }
1655
1656 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1657 &tx_ring->ena_com_io_sq,
1658 &tx_ring->ena_com_io_cq);
1659 if (rc) {
1660 netif_err(adapter, ifup, adapter->netdev,
1661 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1662 qid, rc);
1663 ena_com_destroy_io_queue(ena_dev, ena_qid);
2d2c600a 1664 return rc;
1738cd3e
NB		 1665 }
1666
1667 ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node);
1668 return rc;
1669}
1670
1671static int ena_create_all_io_tx_queues(struct ena_adapter *adapter)
1672{
1673 struct ena_com_dev *ena_dev = adapter->ena_dev;
1674 int rc, i;
1675
faa615f9 1676 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 1677 rc = ena_create_io_tx_queue(adapter, i);
1678 if (rc)
1679 goto create_err;
1680 }
1681
1682 return 0;
1683
1684create_err:
1685 while (i--)
1686 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i));
1687
1688 return rc;
1689}
1690
1691static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
1692{
1693 struct ena_com_dev *ena_dev;
38005ca8 1694 struct ena_com_create_io_ctx ctx;
1738cd3e
NB		 1695 struct ena_ring *rx_ring;
1696 u32 msix_vector;
1697 u16 ena_qid;
1698 int rc;
1699
1700 ena_dev = adapter->ena_dev;
1701
1702 rx_ring = &adapter->rx_ring[qid];
1703 msix_vector = ENA_IO_IRQ_IDX(qid);
1704 ena_qid = ENA_IO_RXQ_IDX(qid);
1705
38005ca8
AK		 1706 memset(&ctx, 0x0, sizeof(ctx));
1707
1738cd3e
NB		 1708 ctx.qid = ena_qid;
1709 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1710 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1711 ctx.msix_vector = msix_vector;
13ca32a6 1712 ctx.queue_size = rx_ring->ring_size;
1738cd3e
NB		 1713 ctx.numa_node = cpu_to_node(rx_ring->cpu);
1714
1715 rc = ena_com_create_io_queue(ena_dev, &ctx);
1716 if (rc) {
1717 netif_err(adapter, ifup, adapter->netdev,
1718 "Failed to create I/O RX queue num %d rc: %d\n",
1719 qid, rc);
1720 return rc;
1721 }
1722
1723 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1724 &rx_ring->ena_com_io_sq,
1725 &rx_ring->ena_com_io_cq);
1726 if (rc) {
1727 netif_err(adapter, ifup, adapter->netdev,
1728 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1729 qid, rc);
1730 ena_com_destroy_io_queue(ena_dev, ena_qid);
2d2c600a 1731 return rc;
1738cd3e
NB		 1732 }
1733
1734 ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node);
1735
1736 return rc;
1737}
1738
1739static int ena_create_all_io_rx_queues(struct ena_adapter *adapter)
1740{
1741 struct ena_com_dev *ena_dev = adapter->ena_dev;
1742 int rc, i;
1743
faa615f9 1744 for (i = 0; i < adapter->num_io_queues; i++) {
1738cd3e
NB		 1745 rc = ena_create_io_rx_queue(adapter, i);
1746 if (rc)
1747 goto create_err;
282faf61 1748 INIT_WORK(&adapter->ena_napi[i].dim.work, ena_dim_work);
1738cd3e
NB		 1749 }
1750
1751 return 0;
1752
1753create_err:
282faf61
AK		 1754 while (i--) {
1755 cancel_work_sync(&adapter->ena_napi[i].dim.work);
1738cd3e 1756 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i));
282faf61 1757 }
1738cd3e
NB		 1758
1759 return rc;
1760}
1761
13ca32a6
SJ		 1762static void set_io_rings_size(struct ena_adapter *adapter,
1763 int new_tx_size, int new_rx_size)
1764{
1765 int i;
1766
faa615f9 1767 for (i = 0; i < adapter->num_io_queues; i++) {
13ca32a6
SJ		 1768 adapter->tx_ring[i].ring_size = new_tx_size;
1769 adapter->rx_ring[i].ring_size = new_rx_size;
1770 }
1771}
1772
1773/* This function allows queue allocation to backoff when the system is
1774 * low on memory. If there is not enough memory to allocate io queues
1775 * the driver will try to allocate smaller queues.
1776 *
1777 * The backoff algorithm is as follows:
1778 * 1. Try to allocate TX and RX and if successful.
1779 * 1.1. return success
1780 *
1781 * 2. Divide by 2 the size of the larger of RX and TX queues (or both if their size is the same).
1782 *
1783 * 3. If TX or RX is smaller than 256
1784 * 3.1. return failure.
1785 * 4. else
1786 * 4.1. go back to 1.
1787 */
1788static int create_queues_with_size_backoff(struct ena_adapter *adapter)
1789{
1790 int rc, cur_rx_ring_size, cur_tx_ring_size;
1791 int new_rx_ring_size, new_tx_ring_size;
1792
1793 /* current queue sizes might be set to smaller than the requested
1794 * ones due to past queue allocation failures.
1795 */
1796 set_io_rings_size(adapter, adapter->requested_tx_ring_size,
1797 adapter->requested_rx_ring_size);
1798
1799 while (1) {
1800 rc = ena_setup_all_tx_resources(adapter);
1801 if (rc)
1802 goto err_setup_tx;
1803
1804 rc = ena_create_all_io_tx_queues(adapter);
1805 if (rc)
1806 goto err_create_tx_queues;
1807
1808 rc = ena_setup_all_rx_resources(adapter);
1809 if (rc)
1810 goto err_setup_rx;
1811
1812 rc = ena_create_all_io_rx_queues(adapter);
1813 if (rc)
1814 goto err_create_rx_queues;
1815
1816 return 0;
1817
1818err_create_rx_queues:
1819 ena_free_all_io_rx_resources(adapter);
1820err_setup_rx:
1821 ena_destroy_all_tx_queues(adapter);
1822err_create_tx_queues:
1823 ena_free_all_io_tx_resources(adapter);
1824err_setup_tx:
1825 if (rc != -ENOMEM) {
1826 netif_err(adapter, ifup, adapter->netdev,
1827 "Queue creation failed with error code %d\n",
1828 rc);
1829 return rc;
1830 }
1831
1832 cur_tx_ring_size = adapter->tx_ring[0].ring_size;
1833 cur_rx_ring_size = adapter->rx_ring[0].ring_size;
1834
1835 netif_err(adapter, ifup, adapter->netdev,
1836 "Not enough memory to create queues with sizes TX=%d, RX=%d\n",
1837 cur_tx_ring_size, cur_rx_ring_size);
1838
1839 new_tx_ring_size = cur_tx_ring_size;
1840 new_rx_ring_size = cur_rx_ring_size;
1841
1842 /* Decrease the size of the larger queue, or
1843 * decrease both if they are the same size.
1844 */
1845 if (cur_rx_ring_size <= cur_tx_ring_size)
1846 new_tx_ring_size = cur_tx_ring_size / 2;
1847 if (cur_rx_ring_size >= cur_tx_ring_size)
1848 new_rx_ring_size = cur_rx_ring_size / 2;
1849
3e5bfb18
SJ		 1850 if (new_tx_ring_size < ENA_MIN_RING_SIZE ||
1851 new_rx_ring_size < ENA_MIN_RING_SIZE) {
13ca32a6
SJ		 1852 netif_err(adapter, ifup, adapter->netdev,
1853 "Queue creation failed with the smallest possible queue size of %d for both queues. Not retrying with smaller queues\n",
1854 ENA_MIN_RING_SIZE);
1855 return rc;
1856 }
1857
1858 netif_err(adapter, ifup, adapter->netdev,
1859 "Retrying queue creation with sizes TX=%d, RX=%d\n",
1860 new_tx_ring_size,
1861 new_rx_ring_size);
1862
1863 set_io_rings_size(adapter, new_tx_ring_size,
1864 new_rx_ring_size);
1865 }
1866}
1867
1738cd3e
NB		 1868static int ena_up(struct ena_adapter *adapter)
1869{
7853b49c 1870 int rc, i;
1738cd3e
NB		 1871
1872 netdev_dbg(adapter->netdev, "%s\n", __func__);
1873
1874 ena_setup_io_intr(adapter);
1875
78a55d05
AK		 1876 /* napi poll functions should be initialized before running
1877 * request_irq(), to handle a rare condition where there is a pending
1878 * interrupt, causing the ISR to fire immediately while the poll
1879 * function wasn't set yet, causing a null dereference
1880 */
1881 ena_init_napi(adapter);
1882
1738cd3e
NB		 1883 rc = ena_request_io_irq(adapter);
1884 if (rc)
1885 goto err_req_irq;
1886
13ca32a6 1887 rc = create_queues_with_size_backoff(adapter);
1738cd3e 1888 if (rc)
13ca32a6 1889 goto err_create_queues_with_backoff;
1738cd3e
NB		 1890
1891 rc = ena_up_complete(adapter);
1892 if (rc)
1893 goto err_up;
1894
1895 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
1896 netif_carrier_on(adapter->netdev);
1897
1898 u64_stats_update_begin(&adapter->syncp);
1899 adapter->dev_stats.interface_up++;
1900 u64_stats_update_end(&adapter->syncp);
1901
1902 set_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1903
7853b49c 1904 /* Enable completion queues interrupt */
faa615f9 1905 for (i = 0; i < adapter->num_io_queues; i++)
7853b49c
NB		 1906 ena_unmask_interrupt(&adapter->tx_ring[i],
1907 &adapter->rx_ring[i]);
1908
1909 /* schedule napi in case we had pending packets
1910 * from the last time we disable napi
1911 */
faa615f9 1912 for (i = 0; i < adapter->num_io_queues; i++)
7853b49c
NB		 1913 napi_schedule(&adapter->ena_napi[i].napi);
1914
1738cd3e
NB		 1915 return rc;
1916
1917err_up:
1738cd3e 1918 ena_destroy_all_tx_queues(adapter);
1738cd3e 1919 ena_free_all_io_tx_resources(adapter);
13ca32a6
SJ		 1920 ena_destroy_all_rx_queues(adapter);
1921 ena_free_all_io_rx_resources(adapter);
1922err_create_queues_with_backoff:
1738cd3e
NB		 1923 ena_free_io_irq(adapter);
1924err_req_irq:
b287cdbd 1925 ena_del_napi(adapter);
1738cd3e
NB		 1926
1927 return rc;
1928}
1929
1930static void ena_down(struct ena_adapter *adapter)
1931{
1932 netif_info(adapter, ifdown, adapter->netdev, "%s\n", __func__);
1933
1934 clear_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1935
1936 u64_stats_update_begin(&adapter->syncp);
1937 adapter->dev_stats.interface_down++;
1938 u64_stats_update_end(&adapter->syncp);
1939
1738cd3e
NB		 1940 netif_carrier_off(adapter->netdev);
1941 netif_tx_disable(adapter->netdev);
1942
3f6159db
NB		 1943 /* After this point the napi handler won't enable the tx queue */
1944 ena_napi_disable_all(adapter);
1945
1738cd3e 1946 /* After destroy the queue there won't be any new interrupts */
3f6159db
NB		 1947
1948 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) {
1949 int rc;
1950
e2eed0e3 1951 rc = ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason);
3f6159db
NB		 1952 if (rc)
1953 dev_err(&adapter->pdev->dev, "Device reset failed\n");
58a54b9c
AK		 1954 /* stop submitting admin commands on a device that was reset */
1955 ena_com_set_admin_running_state(adapter->ena_dev, false);
3f6159db
NB		 1956 }
1957
1738cd3e
NB		 1958 ena_destroy_all_io_queues(adapter);
1959
1960 ena_disable_io_intr_sync(adapter);
1961 ena_free_io_irq(adapter);
1962 ena_del_napi(adapter);
1963
1964 ena_free_all_tx_bufs(adapter);
1965 ena_free_all_rx_bufs(adapter);
1966 ena_free_all_io_tx_resources(adapter);
1967 ena_free_all_io_rx_resources(adapter);
1968}
1969
1970/* ena_open - Called when a network interface is made active
1971 * @netdev: network interface device structure
1972 *
1973 * Returns 0 on success, negative value on failure
1974 *
1975 * The open entry point is called when a network interface is made
1976 * active by the system (IFF_UP). At this point all resources needed
1977 * for transmit and receive operations are allocated, the interrupt
1978 * handler is registered with the OS, the watchdog timer is started,
1979 * and the stack is notified that the interface is ready.
1980 */
1981static int ena_open(struct net_device *netdev)
1982{
1983 struct ena_adapter *adapter = netdev_priv(netdev);
1984 int rc;
1985
1986 /* Notify the stack of the actual queue counts. */
faa615f9 1987 rc = netif_set_real_num_tx_queues(netdev, adapter->num_io_queues);
1738cd3e
NB		 1988 if (rc) {
1989 netif_err(adapter, ifup, netdev, "Can't set num tx queues\n");
1990 return rc;
1991 }
1992
faa615f9 1993 rc = netif_set_real_num_rx_queues(netdev, adapter->num_io_queues);
1738cd3e
NB		 1994 if (rc) {
1995 netif_err(adapter, ifup, netdev, "Can't set num rx queues\n");
1996 return rc;
1997 }
1998
1999 rc = ena_up(adapter);
2000 if (rc)
2001 return rc;
2002
2003 return rc;
2004}
2005
2006/* ena_close - Disables a network interface
2007 * @netdev: network interface device structure
2008 *
2009 * Returns 0, this is not allowed to fail
2010 *
2011 * The close entry point is called when an interface is de-activated
2012 * by the OS. The hardware is still under the drivers control, but
2013 * needs to be disabled. A global MAC reset is issued to stop the
2014 * hardware, and all transmit and receive resources are freed.
2015 */
2016static int ena_close(struct net_device *netdev)
2017{
2018 struct ena_adapter *adapter = netdev_priv(netdev);
2019
2020 netif_dbg(adapter, ifdown, netdev, "%s\n", __func__);
2021
58a54b9c
AK		 2022 if (!test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
2023 return 0;
2024
1738cd3e
NB		 2025 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2026 ena_down(adapter);
2027
ee4552aa
NB		 2028 /* Check for device status and issue reset if needed*/
2029 check_for_admin_com_state(adapter);
2030 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2031 netif_err(adapter, ifdown, adapter->netdev,
2032 "Destroy failure, restarting device\n");
2033 ena_dump_stats_to_dmesg(adapter);
2034 /* rtnl lock already obtained in dev_ioctl() layer */
cfa324a5 2035 ena_destroy_device(adapter, false);
ee4552aa
NB		 2036 ena_restore_device(adapter);
2037 }
2038
1738cd3e
NB		 2039 return 0;
2040}
2041
eece4d2a
SJ		 2042int ena_update_queue_sizes(struct ena_adapter *adapter,
2043 u32 new_tx_size,
2044 u32 new_rx_size)
2045{
2413ea97 2046 bool dev_was_up;
eece4d2a 2047
2413ea97 2048 dev_was_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
eece4d2a
SJ		 2049 ena_close(adapter->netdev);
2050 adapter->requested_tx_ring_size = new_tx_size;
2051 adapter->requested_rx_ring_size = new_rx_size;
2052 ena_init_io_rings(adapter);
2413ea97
SJ		 2053 return dev_was_up ? ena_up(adapter) : 0;
2054}
2055
2056int ena_update_queue_count(struct ena_adapter *adapter, u32 new_channel_count)
2057{
2058 struct ena_com_dev *ena_dev = adapter->ena_dev;
2059 bool dev_was_up;
2060
2061 dev_was_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
2062 ena_close(adapter->netdev);
2063 adapter->num_io_queues = new_channel_count;
2064 /* We need to destroy the rss table so that the indirection
2065 * table will be reinitialized by ena_up()
2066 */
2067 ena_com_rss_destroy(ena_dev);
2068 ena_init_io_rings(adapter);
2069 return dev_was_up ? ena_open(adapter->netdev) : 0;
eece4d2a
SJ		 2070}
2071
1738cd3e
NB		 2072static void ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct sk_buff *skb)
2073{
2074 u32 mss = skb_shinfo(skb)->gso_size;
2075 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
2076 u8 l4_protocol = 0;
2077
2078 if ((skb->ip_summed == CHECKSUM_PARTIAL) || mss) {
2079 ena_tx_ctx->l4_csum_enable = 1;
2080 if (mss) {
2081 ena_tx_ctx->tso_enable = 1;
2082 ena_meta->l4_hdr_len = tcp_hdr(skb)->doff;
2083 ena_tx_ctx->l4_csum_partial = 0;
2084 } else {
2085 ena_tx_ctx->tso_enable = 0;
2086 ena_meta->l4_hdr_len = 0;
2087 ena_tx_ctx->l4_csum_partial = 1;
2088 }
2089
2090 switch (ip_hdr(skb)->version) {
2091 case IPVERSION:
2092 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
2093 if (ip_hdr(skb)->frag_off & htons(IP_DF))
2094 ena_tx_ctx->df = 1;
2095 if (mss)
2096 ena_tx_ctx->l3_csum_enable = 1;
2097 l4_protocol = ip_hdr(skb)->protocol;
2098 break;
2099 case 6:
2100 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
2101 l4_protocol = ipv6_hdr(skb)->nexthdr;
2102 break;
2103 default:
2104 break;
2105 }
2106
2107 if (l4_protocol == IPPROTO_TCP)
2108 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
2109 else
2110 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
2111
2112 ena_meta->mss = mss;
2113 ena_meta->l3_hdr_len = skb_network_header_len(skb);
2114 ena_meta->l3_hdr_offset = skb_network_offset(skb);
2115 ena_tx_ctx->meta_valid = 1;
2116
2117 } else {
2118 ena_tx_ctx->meta_valid = 0;
2119 }
2120}
2121
2122static int ena_check_and_linearize_skb(struct ena_ring *tx_ring,
2123 struct sk_buff *skb)
2124{
2125 int num_frags, header_len, rc;
2126
2127 num_frags = skb_shinfo(skb)->nr_frags;
2128 header_len = skb_headlen(skb);
2129
2130 if (num_frags < tx_ring->sgl_size)
2131 return 0;
2132
2133 if ((num_frags == tx_ring->sgl_size) &&
2134 (header_len < tx_ring->tx_max_header_size))
2135 return 0;
2136
2137 u64_stats_update_begin(&tx_ring->syncp);
2138 tx_ring->tx_stats.linearize++;
2139 u64_stats_update_end(&tx_ring->syncp);
2140
2141 rc = skb_linearize(skb);
2142 if (unlikely(rc)) {
2143 u64_stats_update_begin(&tx_ring->syncp);
2144 tx_ring->tx_stats.linearize_failed++;
2145 u64_stats_update_end(&tx_ring->syncp);
2146 }
2147
2148 return rc;
2149}
2150
38005ca8
AK		 2151static int ena_tx_map_skb(struct ena_ring *tx_ring,
2152 struct ena_tx_buffer *tx_info,
2153 struct sk_buff *skb,
2154 void **push_hdr,
2155 u16 *header_len)
1738cd3e 2156{
38005ca8 2157 struct ena_adapter *adapter = tx_ring->adapter;
1738cd3e 2158 struct ena_com_buf *ena_buf;
1738cd3e 2159 dma_addr_t dma;
38005ca8
AK		 2160 u32 skb_head_len, frag_len, last_frag;
2161 u16 push_len = 0;
2162 u16 delta = 0;
2163 int i = 0;
1738cd3e 2164
38005ca8 2165 skb_head_len = skb_headlen(skb);
1738cd3e 2166 tx_info->skb = skb;
38005ca8 2167 ena_buf = tx_info->bufs;
1738cd3e
NB		 2168
2169 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
38005ca8
AK		 2170 /* When the device is LLQ mode, the driver will copy
2171 * the header into the device memory space.
2172 * the ena_com layer assume the header is in a linear
2173 * memory space.
2174 * This assumption might be wrong since part of the header
2175 * can be in the fragmented buffers.
2176 * Use skb_header_pointer to make sure the header is in a
2177 * linear memory space.
2178 */
2179
2180 push_len = min_t(u32, skb->len, tx_ring->tx_max_header_size);
2181 *push_hdr = skb_header_pointer(skb, 0, push_len,
2182 tx_ring->push_buf_intermediate_buf);
2183 *header_len = push_len;
2184 if (unlikely(skb->data != *push_hdr)) {
2185 u64_stats_update_begin(&tx_ring->syncp);
2186 tx_ring->tx_stats.llq_buffer_copy++;
2187 u64_stats_update_end(&tx_ring->syncp);
2188
2189 delta = push_len - skb_head_len;
2190 }
1738cd3e 2191 } else {
38005ca8
AK		 2192 *push_hdr = NULL;
2193 *header_len = min_t(u32, skb_head_len,
2194 tx_ring->tx_max_header_size);
1738cd3e
NB		 2195 }
2196
38005ca8 2197 netif_dbg(adapter, tx_queued, adapter->netdev,
1738cd3e 2198 "skb: %p header_buf->vaddr: %p push_len: %d\n", skb,
38005ca8 2199 *push_hdr, push_len);
1738cd3e 2200
38005ca8 2201 if (skb_head_len > push_len) {
1738cd3e 2202 dma = dma_map_single(tx_ring->dev, skb->data + push_len,
38005ca8
AK		 2203 skb_head_len - push_len, DMA_TO_DEVICE);
2204 if (unlikely(dma_mapping_error(tx_ring->dev, dma)))
1738cd3e
NB		 2205 goto error_report_dma_error;
2206
2207 ena_buf->paddr = dma;
38005ca8 2208 ena_buf->len = skb_head_len - push_len;
1738cd3e
NB		 2209
2210 ena_buf++;
2211 tx_info->num_of_bufs++;
38005ca8
AK		 2212 tx_info->map_linear_data = 1;
2213 } else {
2214 tx_info->map_linear_data = 0;
1738cd3e
NB		 2215 }
2216
2217 last_frag = skb_shinfo(skb)->nr_frags;
2218
2219 for (i = 0; i < last_frag; i++) {
2220 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2221
38005ca8
AK		 2222 frag_len = skb_frag_size(frag);
2223
2224 if (unlikely(delta >= frag_len)) {
2225 delta -= frag_len;
2226 continue;
2227 }
2228
2229 dma = skb_frag_dma_map(tx_ring->dev, frag, delta,
2230 frag_len - delta, DMA_TO_DEVICE);
2231 if (unlikely(dma_mapping_error(tx_ring->dev, dma)))
1738cd3e
NB		 2232 goto error_report_dma_error;
2233
2234 ena_buf->paddr = dma;
38005ca8 2235 ena_buf->len = frag_len - delta;
1738cd3e 2236 ena_buf++;
38005ca8
AK		 2237 tx_info->num_of_bufs++;
2238 delta = 0;
1738cd3e
NB		 2239 }
2240
38005ca8
AK		 2241 return 0;
2242
2243error_report_dma_error:
2244 u64_stats_update_begin(&tx_ring->syncp);
2245 tx_ring->tx_stats.dma_mapping_err++;
2246 u64_stats_update_end(&tx_ring->syncp);
2247 netdev_warn(adapter->netdev, "failed to map skb\n");
2248
2249 tx_info->skb = NULL;
2250
2251 tx_info->num_of_bufs += i;
2252 ena_unmap_tx_skb(tx_ring, tx_info);
2253
2254 return -EINVAL;
2255}
2256
2257/* Called with netif_tx_lock. */
2258static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
2259{
2260 struct ena_adapter *adapter = netdev_priv(dev);
2261 struct ena_tx_buffer *tx_info;
2262 struct ena_com_tx_ctx ena_tx_ctx;
2263 struct ena_ring *tx_ring;
2264 struct netdev_queue *txq;
2265 void *push_hdr;
2266 u16 next_to_use, req_id, header_len;
2267 int qid, rc, nb_hw_desc;
2268
2269 netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb);
2270 /* Determine which tx ring we will be placed on */
2271 qid = skb_get_queue_mapping(skb);
2272 tx_ring = &adapter->tx_ring[qid];
2273 txq = netdev_get_tx_queue(dev, qid);
2274
2275 rc = ena_check_and_linearize_skb(tx_ring, skb);
2276 if (unlikely(rc))
2277 goto error_drop_packet;
2278
2279 skb_tx_timestamp(skb);
2280
2281 next_to_use = tx_ring->next_to_use;
f9172498 2282 req_id = tx_ring->free_ids[next_to_use];
38005ca8
AK		 2283 tx_info = &tx_ring->tx_buffer_info[req_id];
2284 tx_info->num_of_bufs = 0;
2285
2286 WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id);
2287
2288 rc = ena_tx_map_skb(tx_ring, tx_info, skb, &push_hdr, &header_len);
2289 if (unlikely(rc))
2290 goto error_drop_packet;
1738cd3e
NB		 2291
2292 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2293 ena_tx_ctx.ena_bufs = tx_info->bufs;
2294 ena_tx_ctx.push_header = push_hdr;
2295 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2296 ena_tx_ctx.req_id = req_id;
2297 ena_tx_ctx.header_len = header_len;
2298
2299 /* set flags and meta data */
2300 ena_tx_csum(&ena_tx_ctx, skb);
2301
05d62ca2
SJ		 2302 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, &ena_tx_ctx))) {
2303 netif_dbg(adapter, tx_queued, dev,
2304 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2305 qid);
2306 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2307 }
2308
1738cd3e
NB		 2309 /* prepare the packet's descriptors to dma engine */
2310 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2311 &nb_hw_desc);
2312
38005ca8
AK		 2313 /* ena_com_prepare_tx() can't fail due to overflow of tx queue,
2314 * since the number of free descriptors in the queue is checked
2315 * after sending the previous packet. In case there isn't enough
2316 * space in the queue for the next packet, it is stopped
2317 * until there is again enough available space in the queue.
2318 * All other failure reasons of ena_com_prepare_tx() are fatal
2319 * and therefore require a device reset.
2320 */
1738cd3e
NB		 2321 if (unlikely(rc)) {
2322 netif_err(adapter, tx_queued, dev,
2323 "failed to prepare tx bufs\n");
2324 u64_stats_update_begin(&tx_ring->syncp);
1738cd3e
NB		 2325 tx_ring->tx_stats.prepare_ctx_err++;
2326 u64_stats_update_end(&tx_ring->syncp);
38005ca8
AK		 2327 adapter->reset_reason = ENA_REGS_RESET_DRIVER_INVALID_STATE;
2328 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
1738cd3e
NB		 2329 goto error_unmap_dma;
2330 }
2331
2332 netdev_tx_sent_queue(txq, skb->len);
2333
2334 u64_stats_update_begin(&tx_ring->syncp);
2335 tx_ring->tx_stats.cnt++;
2336 tx_ring->tx_stats.bytes += skb->len;
2337 u64_stats_update_end(&tx_ring->syncp);
2338
2339 tx_info->tx_descs = nb_hw_desc;
2340 tx_info->last_jiffies = jiffies;
800c55cb 2341 tx_info->print_once = 0;
1738cd3e
NB		 2342
2343 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use,
2344 tx_ring->ring_size);
2345
1738cd3e
NB		 2346 /* stop the queue when no more space available, the packet can have up
2347 * to sgl_size + 2. one for the meta descriptor and one for header
2348 * (if the header is larger than tx_max_header_size).
2349 */
689b2bda
AK		 2350 if (unlikely(!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2351 tx_ring->sgl_size + 2))) {
1738cd3e
NB		 2352 netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n",
2353 __func__, qid);
2354
2355 netif_tx_stop_queue(txq);
2356 u64_stats_update_begin(&tx_ring->syncp);
2357 tx_ring->tx_stats.queue_stop++;
2358 u64_stats_update_end(&tx_ring->syncp);
2359
2360 /* There is a rare condition where this function decide to
2361 * stop the queue but meanwhile clean_tx_irq updates
2362 * next_to_completion and terminates.
2363 * The queue will remain stopped forever.
37dff155
NB		 2364 * To solve this issue add a mb() to make sure that
2365 * netif_tx_stop_queue() write is vissible before checking if
2366 * there is additional space in the queue.
1738cd3e 2367 */
37dff155 2368 smp_mb();
1738cd3e 2369
689b2bda
AK		 2370 if (ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2371 ENA_TX_WAKEUP_THRESH)) {
1738cd3e
NB		 2372 netif_tx_wake_queue(txq);
2373 u64_stats_update_begin(&tx_ring->syncp);
2374 tx_ring->tx_stats.queue_wakeup++;
2375 u64_stats_update_end(&tx_ring->syncp);
2376 }
2377 }
2378
6b16f9ee 2379 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) {
37dff155
NB		 2380 /* trigger the dma engine. ena_com_write_sq_doorbell()
2381 * has a mb
2382 */
2383 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1738cd3e
NB		 2384 u64_stats_update_begin(&tx_ring->syncp);
2385 tx_ring->tx_stats.doorbells++;
2386 u64_stats_update_end(&tx_ring->syncp);
2387 }
2388
2389 return NETDEV_TX_OK;
2390
1738cd3e 2391error_unmap_dma:
38005ca8
AK		 2392 ena_unmap_tx_skb(tx_ring, tx_info);
2393 tx_info->skb = NULL;
1738cd3e
NB		 2394
2395error_drop_packet:
1738cd3e
NB		 2396 dev_kfree_skb(skb);
2397 return NETDEV_TX_OK;
2398}
2399
1738cd3e 2400static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb,
a350ecce 2401 struct net_device *sb_dev)
1738cd3e
NB		 2402{
2403 u16 qid;
2404 /* we suspect that this is good for in--kernel network services that
2405 * want to loop incoming skb rx to tx in normal user generated traffic,
2406 * most probably we will not get to this
2407 */
2408 if (skb_rx_queue_recorded(skb))
2409 qid = skb_get_rx_queue(skb);
2410 else
a350ecce 2411 qid = netdev_pick_tx(dev, skb, NULL);
1738cd3e
NB		 2412
2413 return qid;
2414}
2415
095f2f1f
AK		 2416static void ena_config_host_info(struct ena_com_dev *ena_dev,
2417 struct pci_dev *pdev)
1738cd3e
NB		 2418{
2419 struct ena_admin_host_info *host_info;
2420 int rc;
2421
2422 /* Allocate only the host info */
2423 rc = ena_com_allocate_host_info(ena_dev);
2424 if (rc) {
2425 pr_err("Cannot allocate host info\n");
2426 return;
2427 }
2428
2429 host_info = ena_dev->host_attr.host_info;
2430
095f2f1f 2431 host_info->bdf = (pdev->bus->number << 8) | pdev->devfn;
1738cd3e
NB		 2432 host_info->os_type = ENA_ADMIN_OS_LINUX;
2433 host_info->kernel_ver = LINUX_VERSION_CODE;
f9133088 2434 strlcpy(host_info->kernel_ver_str, utsname()->version,
1738cd3e
NB		 2435 sizeof(host_info->kernel_ver_str) - 1);
2436 host_info->os_dist = 0;
2437 strncpy(host_info->os_dist_str, utsname()->release,
2438 sizeof(host_info->os_dist_str) - 1);
2439 host_info->driver_version =
2440 (DRV_MODULE_VER_MAJOR) |
2441 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
095f2f1f
AK		 2442 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) |
2443 ("K"[0] << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT);
2444 host_info->num_cpus = num_online_cpus();
1738cd3e 2445
bd21b0cc
AK		 2446 host_info->driver_supported_features =
2447 ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
2448
1738cd3e
NB		 2449 rc = ena_com_set_host_attributes(ena_dev);
2450 if (rc) {
d1497638 2451 if (rc == -EOPNOTSUPP)
1738cd3e
NB		 2452 pr_warn("Cannot set host attributes\n");
2453 else
2454 pr_err("Cannot set host attributes\n");
2455
2456 goto err;
2457 }
2458
2459 return;
2460
2461err:
2462 ena_com_delete_host_info(ena_dev);
2463}
2464
2465static void ena_config_debug_area(struct ena_adapter *adapter)
2466{
2467 u32 debug_area_size;
2468 int rc, ss_count;
2469
2470 ss_count = ena_get_sset_count(adapter->netdev, ETH_SS_STATS);
2471 if (ss_count <= 0) {
2472 netif_err(adapter, drv, adapter->netdev,
2473 "SS count is negative\n");
2474 return;
2475 }
2476
2477 /* allocate 32 bytes for each string and 64bit for the value */
2478 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
2479
2480 rc = ena_com_allocate_debug_area(adapter->ena_dev, debug_area_size);
2481 if (rc) {
2482 pr_err("Cannot allocate debug area\n");
2483 return;
2484 }
2485
2486 rc = ena_com_set_host_attributes(adapter->ena_dev);
2487 if (rc) {
d1497638 2488 if (rc == -EOPNOTSUPP)
1738cd3e
NB		 2489 netif_warn(adapter, drv, adapter->netdev,
2490 "Cannot set host attributes\n");
2491 else
2492 netif_err(adapter, drv, adapter->netdev,
2493 "Cannot set host attributes\n");
2494 goto err;
2495 }
2496
2497 return;
2498err:
2499 ena_com_delete_debug_area(adapter->ena_dev);
2500}
2501
bc1f4470 2502static void ena_get_stats64(struct net_device *netdev,
2503 struct rtnl_link_stats64 *stats)
1738cd3e
NB		 2504{
2505 struct ena_adapter *adapter = netdev_priv(netdev);
d81db240
NB		 2506 struct ena_ring *rx_ring, *tx_ring;
2507 unsigned int start;
2508 u64 rx_drops;
2509 int i;
1738cd3e
NB		 2510
2511 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
bc1f4470 2512 return;
1738cd3e 2513
faa615f9 2514 for (i = 0; i < adapter->num_io_queues; i++) {
d81db240
NB		 2515 u64 bytes, packets;
2516
2517 tx_ring = &adapter->tx_ring[i];
1738cd3e 2518
d81db240
NB		 2519 do {
2520 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
2521 packets = tx_ring->tx_stats.cnt;
2522 bytes = tx_ring->tx_stats.bytes;
2523 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
1738cd3e 2524
d81db240
NB		 2525 stats->tx_packets += packets;
2526 stats->tx_bytes += bytes;
2527
2528 rx_ring = &adapter->rx_ring[i];
2529
2530 do {
2531 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
2532 packets = rx_ring->rx_stats.cnt;
2533 bytes = rx_ring->rx_stats.bytes;
2534 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
2535
2536 stats->rx_packets += packets;
2537 stats->rx_bytes += bytes;
2538 }
2539
2540 do {
2541 start = u64_stats_fetch_begin_irq(&adapter->syncp);
2542 rx_drops = adapter->dev_stats.rx_drops;
2543 } while (u64_stats_fetch_retry_irq(&adapter->syncp, start));
1738cd3e 2544
d81db240 2545 stats->rx_dropped = rx_drops;
1738cd3e
NB		 2546
2547 stats->multicast = 0;
2548 stats->collisions = 0;
2549
2550 stats->rx_length_errors = 0;
2551 stats->rx_crc_errors = 0;
2552 stats->rx_frame_errors = 0;
2553 stats->rx_fifo_errors = 0;
2554 stats->rx_missed_errors = 0;
2555 stats->tx_window_errors = 0;
2556
2557 stats->rx_errors = 0;
2558 stats->tx_errors = 0;
1738cd3e
NB		 2559}
2560
2561static const struct net_device_ops ena_netdev_ops = {
2562 .ndo_open = ena_open,
2563 .ndo_stop = ena_close,
2564 .ndo_start_xmit = ena_start_xmit,
2565 .ndo_select_queue = ena_select_queue,
2566 .ndo_get_stats64 = ena_get_stats64,
2567 .ndo_tx_timeout = ena_tx_timeout,
2568 .ndo_change_mtu = ena_change_mtu,
2569 .ndo_set_mac_address = NULL,
2570 .ndo_validate_addr = eth_validate_addr,
1738cd3e
NB		 2571};
2572
1738cd3e
NB		 2573static int ena_device_validate_params(struct ena_adapter *adapter,
2574 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2575{
2576 struct net_device *netdev = adapter->netdev;
2577 int rc;
2578
2579 rc = ether_addr_equal(get_feat_ctx->dev_attr.mac_addr,
2580 adapter->mac_addr);
2581 if (!rc) {
2582 netif_err(adapter, drv, netdev,
2583 "Error, mac address are different\n");
2584 return -EINVAL;
2585 }
2586
1738cd3e
NB		 2587 if (get_feat_ctx->dev_attr.max_mtu < netdev->mtu) {
2588 netif_err(adapter, drv, netdev,
2589 "Error, device max mtu is smaller than netdev MTU\n");
2590 return -EINVAL;
2591 }
2592
2593 return 0;
2594}
2595
2596static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
2597 struct ena_com_dev_get_features_ctx *get_feat_ctx,
2598 bool *wd_state)
2599{
2600 struct device *dev = &pdev->dev;
2601 bool readless_supported;
2602 u32 aenq_groups;
2603 int dma_width;
2604 int rc;
2605
2606 rc = ena_com_mmio_reg_read_request_init(ena_dev);
2607 if (rc) {
2608 dev_err(dev, "failed to init mmio read less\n");
2609 return rc;
2610 }
2611
2612 /* The PCIe configuration space revision id indicate if mmio reg
2613 * read is disabled
2614 */
2615 readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ);
2616 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
2617
e2eed0e3 2618 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1738cd3e
NB		 2619 if (rc) {
2620 dev_err(dev, "Can not reset device\n");
2621 goto err_mmio_read_less;
2622 }
2623
2624 rc = ena_com_validate_version(ena_dev);
2625 if (rc) {
2626 dev_err(dev, "device version is too low\n");
2627 goto err_mmio_read_less;
2628 }
2629
2630 dma_width = ena_com_get_dma_width(ena_dev);
2631 if (dma_width < 0) {
2632 dev_err(dev, "Invalid dma width value %d", dma_width);
6e22066f 2633 rc = dma_width;
1738cd3e
NB		 2634 goto err_mmio_read_less;
2635 }
2636
2637 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2638 if (rc) {
2639 dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc);
2640 goto err_mmio_read_less;
2641 }
2642
2643 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2644 if (rc) {
2645 dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n",
2646 rc);
2647 goto err_mmio_read_less;
2648 }
2649
2650 /* ENA admin level init */
f1e90f6e 2651 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1738cd3e
NB		 2652 if (rc) {
2653 dev_err(dev,
2654 "Can not initialize ena admin queue with device\n");
2655 goto err_mmio_read_less;
2656 }
2657
2658 /* To enable the msix interrupts the driver needs to know the number
2659 * of queues. So the driver uses polling mode to retrieve this
2660 * information
2661 */
2662 ena_com_set_admin_polling_mode(ena_dev, true);
2663
095f2f1f 2664 ena_config_host_info(ena_dev, pdev);
dd8427a7 2665
1738cd3e
NB		 2666 /* Get Device Attributes*/
2667 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
2668 if (rc) {
2669 dev_err(dev, "Cannot get attribute for ena device rc=%d\n", rc);
2670 goto err_admin_init;
2671 }
2672
2673 /* Try to turn all the available aenq groups */
2674 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
2675 BIT(ENA_ADMIN_FATAL_ERROR) |
2676 BIT(ENA_ADMIN_WARNING) |
2677 BIT(ENA_ADMIN_NOTIFICATION) |
2678 BIT(ENA_ADMIN_KEEP_ALIVE);
2679
2680 aenq_groups &= get_feat_ctx->aenq.supported_groups;
2681
2682 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
2683 if (rc) {
2684 dev_err(dev, "Cannot configure aenq groups rc= %d\n", rc);
2685 goto err_admin_init;
2686 }
2687
2688 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
2689
1738cd3e
NB		 2690 return 0;
2691
2692err_admin_init:
dd8427a7 2693 ena_com_delete_host_info(ena_dev);
1738cd3e
NB		 2694 ena_com_admin_destroy(ena_dev);
2695err_mmio_read_less:
2696 ena_com_mmio_reg_read_request_destroy(ena_dev);
2697
2698 return rc;
2699}
2700
4d192660 2701static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter)
1738cd3e
NB		 2702{
2703 struct ena_com_dev *ena_dev = adapter->ena_dev;
2704 struct device *dev = &adapter->pdev->dev;
2705 int rc;
2706
4d192660 2707 rc = ena_enable_msix(adapter);
1738cd3e
NB		 2708 if (rc) {
2709 dev_err(dev, "Can not reserve msix vectors\n");
2710 return rc;
2711 }
2712
2713 ena_setup_mgmnt_intr(adapter);
2714
2715 rc = ena_request_mgmnt_irq(adapter);
2716 if (rc) {
2717 dev_err(dev, "Can not setup management interrupts\n");
2718 goto err_disable_msix;
2719 }
2720
2721 ena_com_set_admin_polling_mode(ena_dev, false);
2722
2723 ena_com_admin_aenq_enable(ena_dev);
2724
2725 return 0;
2726
2727err_disable_msix:
06443684
NB		 2728 ena_disable_msix(adapter);
2729
1738cd3e
NB		 2730 return rc;
2731}
2732
cfa324a5 2733static void ena_destroy_device(struct ena_adapter *adapter, bool graceful)
1738cd3e 2734{
1738cd3e
NB		 2735 struct net_device *netdev = adapter->netdev;
2736 struct ena_com_dev *ena_dev = adapter->ena_dev;
8c5c7abd 2737 bool dev_up;
3f6159db 2738
fe870c77
NB		 2739 if (!test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
2740 return;
2741
3f6159db
NB		 2742 netif_carrier_off(netdev);
2743
1738cd3e
NB		 2744 del_timer_sync(&adapter->timer_service);
2745
1738cd3e 2746 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
8c5c7abd 2747 adapter->dev_up_before_reset = dev_up;
cfa324a5
NB		 2748 if (!graceful)
2749 ena_com_set_admin_running_state(ena_dev, false);
1738cd3e 2750
ee4552aa
NB		 2751 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2752 ena_down(adapter);
1738cd3e 2753
bd791175 2754 /* Stop the device from sending AENQ events (in case reset flag is set
58a54b9c 2755 * and device is up, ena_down() already reset the device.
8c5c7abd
NB		 2756 */
2757 if (!(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags) && dev_up))
2758 ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason);
2759
1738cd3e
NB		 2760 ena_free_mgmnt_irq(adapter);
2761
06443684 2762 ena_disable_msix(adapter);
1738cd3e
NB		 2763
2764 ena_com_abort_admin_commands(ena_dev);
2765
2766 ena_com_wait_for_abort_completion(ena_dev);
2767
2768 ena_com_admin_destroy(ena_dev);
2769
2770 ena_com_mmio_reg_read_request_destroy(ena_dev);
2771
e2eed0e3 2772 adapter->reset_reason = ENA_REGS_RESET_NORMAL;
8c5c7abd 2773
3f6159db 2774 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
fe870c77 2775 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
8c5c7abd 2776}
3f6159db 2777
8c5c7abd
NB		 2778static int ena_restore_device(struct ena_adapter *adapter)
2779{
2780 struct ena_com_dev_get_features_ctx get_feat_ctx;
2781 struct ena_com_dev *ena_dev = adapter->ena_dev;
2782 struct pci_dev *pdev = adapter->pdev;
2783 bool wd_state;
2784 int rc;
1738cd3e 2785
d18e4f68 2786 set_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags);
1738cd3e
NB		 2787 rc = ena_device_init(ena_dev, adapter->pdev, &get_feat_ctx, &wd_state);
2788 if (rc) {
2789 dev_err(&pdev->dev, "Can not initialize device\n");
2790 goto err;
2791 }
2792 adapter->wd_state = wd_state;
2793
2794 rc = ena_device_validate_params(adapter, &get_feat_ctx);
2795 if (rc) {
2796 dev_err(&pdev->dev, "Validation of device parameters failed\n");
2797 goto err_device_destroy;
2798 }
2799
4d192660 2800 rc = ena_enable_msix_and_set_admin_interrupts(adapter);
1738cd3e
NB		 2801 if (rc) {
2802 dev_err(&pdev->dev, "Enable MSI-X failed\n");
2803 goto err_device_destroy;
2804 }
2805 /* If the interface was up before the reset bring it up */
8c5c7abd 2806 if (adapter->dev_up_before_reset) {
1738cd3e
NB		 2807 rc = ena_up(adapter);
2808 if (rc) {
2809 dev_err(&pdev->dev, "Failed to create I/O queues\n");
2810 goto err_disable_msix;
2811 }
2812 }
2813
fe870c77 2814 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
e1f1bd9b
AK		 2815
2816 clear_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags);
2817 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
2818 netif_carrier_on(adapter->netdev);
2819
1738cd3e 2820 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
38005ca8
AK		 2821 dev_err(&pdev->dev,
2822 "Device reset completed successfully, Driver info: %s\n",
2823 version);
1738cd3e 2824
8c5c7abd 2825 return rc;
1738cd3e
NB		 2826err_disable_msix:
2827 ena_free_mgmnt_irq(adapter);
06443684 2828 ena_disable_msix(adapter);
1738cd3e 2829err_device_destroy:
d7703ddb
AK		 2830 ena_com_abort_admin_commands(ena_dev);
2831 ena_com_wait_for_abort_completion(ena_dev);
1738cd3e 2832 ena_com_admin_destroy(ena_dev);
d7703ddb 2833 ena_com_dev_reset(ena_dev, ENA_REGS_RESET_DRIVER_INVALID_STATE);
e76ad21d 2834 ena_com_mmio_reg_read_request_destroy(ena_dev);
1738cd3e 2835err:
22b331c9 2836 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
d18e4f68 2837 clear_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags);
1738cd3e
NB		 2838 dev_err(&pdev->dev,
2839 "Reset attempt failed. Can not reset the device\n");
8c5c7abd
NB		 2840
2841 return rc;
2842}
2843
2844static void ena_fw_reset_device(struct work_struct *work)
2845{
2846 struct ena_adapter *adapter =
2847 container_of(work, struct ena_adapter, reset_task);
2848 struct pci_dev *pdev = adapter->pdev;
2849
2850 if (unlikely(!test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2851 dev_err(&pdev->dev,
2852 "device reset schedule while reset bit is off\n");
2853 return;
2854 }
2855 rtnl_lock();
cfa324a5 2856 ena_destroy_device(adapter, false);
8c5c7abd
NB		 2857 ena_restore_device(adapter);
2858 rtnl_unlock();
1738cd3e
NB		 2859}
2860
8510e1a3
NB		 2861static int check_for_rx_interrupt_queue(struct ena_adapter *adapter,
2862 struct ena_ring *rx_ring)
2863{
2864 if (likely(rx_ring->first_interrupt))
2865 return 0;
2866
2867 if (ena_com_cq_empty(rx_ring->ena_com_io_cq))
2868 return 0;
2869
2870 rx_ring->no_interrupt_event_cnt++;
2871
2872 if (rx_ring->no_interrupt_event_cnt == ENA_MAX_NO_INTERRUPT_ITERATIONS) {
2873 netif_err(adapter, rx_err, adapter->netdev,
2874 "Potential MSIX issue on Rx side Queue = %d. Reset the device\n",
2875 rx_ring->qid);
2876 adapter->reset_reason = ENA_REGS_RESET_MISS_INTERRUPT;
2877 smp_mb__before_atomic();
2878 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2879 return -EIO;
2880 }
2881
2882 return 0;
2883}
2884
2885static int check_missing_comp_in_tx_queue(struct ena_adapter *adapter,
2886 struct ena_ring *tx_ring)
1738cd3e
NB		 2887{
2888 struct ena_tx_buffer *tx_buf;
2889 unsigned long last_jiffies;
800c55cb 2890 u32 missed_tx = 0;
11095fdb 2891 int i, rc = 0;
800c55cb
NB		 2892
2893 for (i = 0; i < tx_ring->ring_size; i++) {
2894 tx_buf = &tx_ring->tx_buffer_info[i];
2895 last_jiffies = tx_buf->last_jiffies;
8510e1a3
NB		 2896
2897 if (last_jiffies == 0)
2898 /* no pending Tx at this location */
2899 continue;
2900
2901 if (unlikely(!tx_ring->first_interrupt && time_is_before_jiffies(last_jiffies +
2902 2 * adapter->missing_tx_completion_to))) {
2903 /* If after graceful period interrupt is still not
2904 * received, we schedule a reset
2905 */
2906 netif_err(adapter, tx_err, adapter->netdev,
2907 "Potential MSIX issue on Tx side Queue = %d. Reset the device\n",
2908 tx_ring->qid);
2909 adapter->reset_reason = ENA_REGS_RESET_MISS_INTERRUPT;
2910 smp_mb__before_atomic();
2911 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2912 return -EIO;
2913 }
2914
2915 if (unlikely(time_is_before_jiffies(last_jiffies +
2916 adapter->missing_tx_completion_to))) {
800c55cb
NB		 2917 if (!tx_buf->print_once)
2918 netif_notice(adapter, tx_err, adapter->netdev,
2919 "Found a Tx that wasn't completed on time, qid %d, index %d.\n",
2920 tx_ring->qid, i);
2921
2922 tx_buf->print_once = 1;
2923 missed_tx++;
800c55cb
NB		 2924 }
2925 }
2926
11095fdb
NB		 2927 if (unlikely(missed_tx > adapter->missing_tx_completion_threshold)) {
2928 netif_err(adapter, tx_err, adapter->netdev,
2929 "The number of lost tx completions is above the threshold (%d > %d). Reset the device\n",
2930 missed_tx,
2931 adapter->missing_tx_completion_threshold);
2932 adapter->reset_reason =
2933 ENA_REGS_RESET_MISS_TX_CMPL;
2934 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2935 rc = -EIO;
2936 }
2937
2938 u64_stats_update_begin(&tx_ring->syncp);
2939 tx_ring->tx_stats.missed_tx = missed_tx;
2940 u64_stats_update_end(&tx_ring->syncp);
2941
2942 return rc;
800c55cb
NB		 2943}
2944
8510e1a3 2945static void check_for_missing_completions(struct ena_adapter *adapter)
800c55cb 2946{
1738cd3e 2947 struct ena_ring *tx_ring;
8510e1a3 2948 struct ena_ring *rx_ring;
800c55cb 2949 int i, budget, rc;
1738cd3e
NB		 2950
2951 /* Make sure the driver doesn't turn the device in other process */
2952 smp_rmb();
2953
2954 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2955 return;
2956
3f6159db
NB		 2957 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2958 return;
2959
82ef30f1
NB		 2960 if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
2961 return;
2962
1738cd3e
NB		 2963 budget = ENA_MONITORED_TX_QUEUES;
2964
faa615f9 2965 for (i = adapter->last_monitored_tx_qid; i < adapter->num_io_queues; i++) {
1738cd3e 2966 tx_ring = &adapter->tx_ring[i];
8510e1a3
NB		 2967 rx_ring = &adapter->rx_ring[i];
2968
2969 rc = check_missing_comp_in_tx_queue(adapter, tx_ring);
2970 if (unlikely(rc))
2971 return;
1738cd3e 2972
8510e1a3 2973 rc = check_for_rx_interrupt_queue(adapter, rx_ring);
800c55cb
NB		 2974 if (unlikely(rc))
2975 return;
1738cd3e
NB		 2976
2977 budget--;
2978 if (!budget)
2979 break;
2980 }
2981
faa615f9 2982 adapter->last_monitored_tx_qid = i % adapter->num_io_queues;
1738cd3e
NB		 2983}
2984
a3af7c18
NB		 2985/* trigger napi schedule after 2 consecutive detections */
2986#define EMPTY_RX_REFILL 2
2987/* For the rare case where the device runs out of Rx descriptors and the
2988 * napi handler failed to refill new Rx descriptors (due to a lack of memory
2989 * for example).
2990 * This case will lead to a deadlock:
2991 * The device won't send interrupts since all the new Rx packets will be dropped
2992 * The napi handler won't allocate new Rx descriptors so the device will be
2993 * able to send new packets.
2994 *
2995 * This scenario can happen when the kernel's vm.min_free_kbytes is too small.
2996 * It is recommended to have at least 512MB, with a minimum of 128MB for
2997 * constrained environment).
2998 *
2999 * When such a situation is detected - Reschedule napi
3000 */
3001static void check_for_empty_rx_ring(struct ena_adapter *adapter)
3002{
3003 struct ena_ring *rx_ring;
3004 int i, refill_required;
3005
3006 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
3007 return;
3008
3009 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
3010 return;
3011
faa615f9 3012 for (i = 0; i < adapter->num_io_queues; i++) {
a3af7c18
NB		 3013 rx_ring = &adapter->rx_ring[i];
3014
3015 refill_required =
689b2bda 3016 ena_com_free_desc(rx_ring->ena_com_io_sq);
a3af7c18
NB		 3017 if (unlikely(refill_required == (rx_ring->ring_size - 1))) {
3018 rx_ring->empty_rx_queue++;
3019
3020 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) {
3021 u64_stats_update_begin(&rx_ring->syncp);
3022 rx_ring->rx_stats.empty_rx_ring++;
3023 u64_stats_update_end(&rx_ring->syncp);
3024
3025 netif_err(adapter, drv, adapter->netdev,
3026 "trigger refill for ring %d\n", i);
3027
3028 napi_schedule(rx_ring->napi);
3029 rx_ring->empty_rx_queue = 0;
3030 }
3031 } else {
3032 rx_ring->empty_rx_queue = 0;
3033 }
3034 }
3035}
3036
1738cd3e
NB		 3037/* Check for keep alive expiration */
3038static void check_for_missing_keep_alive(struct ena_adapter *adapter)
3039{
3040 unsigned long keep_alive_expired;
3041
3042 if (!adapter->wd_state)
3043 return;
3044
82ef30f1
NB		 3045 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
3046 return;
3047
3048 keep_alive_expired = round_jiffies(adapter->last_keep_alive_jiffies +
3049 adapter->keep_alive_timeout);
1738cd3e
NB		 3050 if (unlikely(time_is_before_jiffies(keep_alive_expired))) {
3051 netif_err(adapter, drv, adapter->netdev,
3052 "Keep alive watchdog timeout.\n");
3053 u64_stats_update_begin(&adapter->syncp);
3054 adapter->dev_stats.wd_expired++;
3055 u64_stats_update_end(&adapter->syncp);
e2eed0e3 3056 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1738cd3e
NB		 3057 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
3058 }
3059}
3060
3061static void check_for_admin_com_state(struct ena_adapter *adapter)
3062{
3063 if (unlikely(!ena_com_get_admin_running_state(adapter->ena_dev))) {
3064 netif_err(adapter, drv, adapter->netdev,
3065 "ENA admin queue is not in running state!\n");
3066 u64_stats_update_begin(&adapter->syncp);
3067 adapter->dev_stats.admin_q_pause++;
3068 u64_stats_update_end(&adapter->syncp);
e2eed0e3 3069 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1738cd3e
NB		 3070 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
3071 }
3072}
3073
82ef30f1
NB		 3074static void ena_update_hints(struct ena_adapter *adapter,
3075 struct ena_admin_ena_hw_hints *hints)
3076{
3077 struct net_device *netdev = adapter->netdev;
3078
3079 if (hints->admin_completion_tx_timeout)
3080 adapter->ena_dev->admin_queue.completion_timeout =
3081 hints->admin_completion_tx_timeout * 1000;
3082
3083 if (hints->mmio_read_timeout)
3084 /* convert to usec */
3085 adapter->ena_dev->mmio_read.reg_read_to =
3086 hints->mmio_read_timeout * 1000;
3087
3088 if (hints->missed_tx_completion_count_threshold_to_reset)
3089 adapter->missing_tx_completion_threshold =
3090 hints->missed_tx_completion_count_threshold_to_reset;
3091
3092 if (hints->missing_tx_completion_timeout) {
3093 if (hints->missing_tx_completion_timeout == ENA_HW_HINTS_NO_TIMEOUT)
3094 adapter->missing_tx_completion_to = ENA_HW_HINTS_NO_TIMEOUT;
3095 else
3096 adapter->missing_tx_completion_to =
3097 msecs_to_jiffies(hints->missing_tx_completion_timeout);
3098 }
3099
3100 if (hints->netdev_wd_timeout)
3101 netdev->watchdog_timeo = msecs_to_jiffies(hints->netdev_wd_timeout);
3102
3103 if (hints->driver_watchdog_timeout) {
3104 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
3105 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
3106 else
3107 adapter->keep_alive_timeout =
3108 msecs_to_jiffies(hints->driver_watchdog_timeout);
3109 }
3110}
3111
1738cd3e
NB		 3112static void ena_update_host_info(struct ena_admin_host_info *host_info,
3113 struct net_device *netdev)
3114{
3115 host_info->supported_network_features[0] =
3116 netdev->features & GENMASK_ULL(31, 0);
3117 host_info->supported_network_features[1] =
3118 (netdev->features & GENMASK_ULL(63, 32)) >> 32;
3119}
3120
e99e88a9 3121static void ena_timer_service(struct timer_list *t)
1738cd3e 3122{
e99e88a9 3123 struct ena_adapter *adapter = from_timer(adapter, t, timer_service);
1738cd3e
NB		 3124 u8 *debug_area = adapter->ena_dev->host_attr.debug_area_virt_addr;
3125 struct ena_admin_host_info *host_info =
3126 adapter->ena_dev->host_attr.host_info;
3127
3128 check_for_missing_keep_alive(adapter);
3129
3130 check_for_admin_com_state(adapter);
3131
8510e1a3 3132 check_for_missing_completions(adapter);
1738cd3e 3133
a3af7c18
NB		 3134 check_for_empty_rx_ring(adapter);
3135
1738cd3e
NB		 3136 if (debug_area)
3137 ena_dump_stats_to_buf(adapter, debug_area);
3138
3139 if (host_info)
3140 ena_update_host_info(host_info, adapter->netdev);
3141
3f6159db 3142 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
1738cd3e
NB		 3143 netif_err(adapter, drv, adapter->netdev,
3144 "Trigger reset is on\n");
3145 ena_dump_stats_to_dmesg(adapter);
3146 queue_work(ena_wq, &adapter->reset_task);
3147 return;
3148 }
3149
3150 /* Reset the timer */
3151 mod_timer(&adapter->timer_service, jiffies + HZ);
3152}
3153
736ce3f4
SJ		 3154static int ena_calc_max_io_queue_num(struct pci_dev *pdev,
3155 struct ena_com_dev *ena_dev,
3156 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1738cd3e 3157{
736ce3f4 3158 int io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
31aa9857
SJ		 3159
3160 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
3161 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
3162 &get_feat_ctx->max_queue_ext.max_queue_ext;
736ce3f4 3163 io_rx_num = min_t(u32, max_queue_ext->max_rx_sq_num,
31aa9857 3164 max_queue_ext->max_rx_cq_num);
1738cd3e 3165
31aa9857
SJ		 3166 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
3167 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
3168 } else {
3169 struct ena_admin_queue_feature_desc *max_queues =
3170 &get_feat_ctx->max_queues;
3171 io_tx_sq_num = max_queues->max_sq_num;
3172 io_tx_cq_num = max_queues->max_cq_num;
736ce3f4 3173 io_rx_num = min_t(u32, io_tx_sq_num, io_tx_cq_num);
31aa9857
SJ		 3174 }
3175
3176 /* In case of LLQ use the llq fields for the tx SQ/CQ */
9fd25592 3177 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
31aa9857 3178 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1738cd3e 3179
736ce3f4
SJ		 3180 max_num_io_queues = min_t(u32, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES);
3181 max_num_io_queues = min_t(u32, max_num_io_queues, io_rx_num);
3182 max_num_io_queues = min_t(u32, max_num_io_queues, io_tx_sq_num);
3183 max_num_io_queues = min_t(u32, max_num_io_queues, io_tx_cq_num);
1738cd3e 3184 /* 1 IRQ for for mgmnt and 1 IRQs for each IO direction */
736ce3f4
SJ		 3185 max_num_io_queues = min_t(u32, max_num_io_queues, pci_msix_vec_count(pdev) - 1);
3186 if (unlikely(!max_num_io_queues)) {
1738cd3e
NB		 3187 dev_err(&pdev->dev, "The device doesn't have io queues\n");
3188 return -EFAULT;
3189 }
3190
736ce3f4 3191 return max_num_io_queues;
1738cd3e
NB		 3192}
3193
38005ca8
AK		 3194static int ena_set_queues_placement_policy(struct pci_dev *pdev,
3195 struct ena_com_dev *ena_dev,
3196 struct ena_admin_feature_llq_desc *llq,
3197 struct ena_llq_configurations *llq_default_configurations)
1738cd3e
NB		 3198{
3199 bool has_mem_bar;
38005ca8
AK		 3200 int rc;
3201 u32 llq_feature_mask;
3202
3203 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
3204 if (!(ena_dev->supported_features & llq_feature_mask)) {
3205 dev_err(&pdev->dev,
3206 "LLQ is not supported Fallback to host mode policy.\n");
3207 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
3208 return 0;
3209 }
1738cd3e
NB		 3210
3211 has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR);
3212
38005ca8
AK		 3213 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
3214 if (unlikely(rc)) {
3215 dev_err(&pdev->dev,
3216 "Failed to configure the device mode. Fallback to host mode policy.\n");
3217 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
3218 return 0;
3219 }
3220
3221 /* Nothing to config, exit */
3222 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
3223 return 0;
3224
3225 if (!has_mem_bar) {
3226 dev_err(&pdev->dev,
3227 "ENA device does not expose LLQ bar. Fallback to host mode policy.\n");
1738cd3e 3228 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
38005ca8
AK		 3229 return 0;
3230 }
3231
3232 ena_dev->mem_bar = devm_ioremap_wc(&pdev->dev,
3233 pci_resource_start(pdev, ENA_MEM_BAR),
3234 pci_resource_len(pdev, ENA_MEM_BAR));
3235
3236 if (!ena_dev->mem_bar)
3237 return -EFAULT;
3238
3239 return 0;
1738cd3e
NB		 3240}
3241
3242static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat,
3243 struct net_device *netdev)
3244{
3245 netdev_features_t dev_features = 0;
3246
3247 /* Set offload features */
3248 if (feat->offload.tx &
3249 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
3250 dev_features |= NETIF_F_IP_CSUM;
3251
3252 if (feat->offload.tx &
3253 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
3254 dev_features |= NETIF_F_IPV6_CSUM;
3255
3256 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
3257 dev_features |= NETIF_F_TSO;
3258
3259 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK)
3260 dev_features |= NETIF_F_TSO6;
3261
3262 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK)
3263 dev_features |= NETIF_F_TSO_ECN;
3264
3265 if (feat->offload.rx_supported &
3266 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
3267 dev_features |= NETIF_F_RXCSUM;
3268
3269 if (feat->offload.rx_supported &
3270 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
3271 dev_features |= NETIF_F_RXCSUM;
3272
3273 netdev->features =
3274 dev_features |
3275 NETIF_F_SG |
1738cd3e
NB		 3276 NETIF_F_RXHASH |
3277 NETIF_F_HIGHDMA;
3278
3279 netdev->hw_features |= netdev->features;
3280 netdev->vlan_features |= netdev->features;
3281}
3282
3283static void ena_set_conf_feat_params(struct ena_adapter *adapter,
3284 struct ena_com_dev_get_features_ctx *feat)
3285{
3286 struct net_device *netdev = adapter->netdev;
3287
3288 /* Copy mac address */
3289 if (!is_valid_ether_addr(feat->dev_attr.mac_addr)) {
3290 eth_hw_addr_random(netdev);
3291 ether_addr_copy(adapter->mac_addr, netdev->dev_addr);
3292 } else {
3293 ether_addr_copy(adapter->mac_addr, feat->dev_attr.mac_addr);
3294 ether_addr_copy(netdev->dev_addr, adapter->mac_addr);
3295 }
3296
3297 /* Set offload features */
3298 ena_set_dev_offloads(feat, netdev);
3299
3300 adapter->max_mtu = feat->dev_attr.max_mtu;
d894be57
JW		 3301 netdev->max_mtu = adapter->max_mtu;
3302 netdev->min_mtu = ENA_MIN_MTU;
1738cd3e
NB		 3303}
3304
3305static int ena_rss_init_default(struct ena_adapter *adapter)
3306{
3307 struct ena_com_dev *ena_dev = adapter->ena_dev;
3308 struct device *dev = &adapter->pdev->dev;
3309 int rc, i;
3310 u32 val;
3311
3312 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
3313 if (unlikely(rc)) {
3314 dev_err(dev, "Cannot init indirect table\n");
3315 goto err_rss_init;
3316 }
3317
3318 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
faa615f9 3319 val = ethtool_rxfh_indir_default(i, adapter->num_io_queues);
1738cd3e
NB		 3320 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
3321 ENA_IO_RXQ_IDX(val));
d1497638 3322 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
1738cd3e
NB		 3323 dev_err(dev, "Cannot fill indirect table\n");
3324 goto err_fill_indir;
3325 }
3326 }
3327
3328 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
3329 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
d1497638 3330 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
1738cd3e
NB		 3331 dev_err(dev, "Cannot fill hash function\n");
3332 goto err_fill_indir;
3333 }
3334
3335 rc = ena_com_set_default_hash_ctrl(ena_dev);
d1497638 3336 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
1738cd3e
NB		 3337 dev_err(dev, "Cannot fill hash control\n");
3338 goto err_fill_indir;
3339 }
3340
3341 return 0;
3342
3343err_fill_indir:
3344 ena_com_rss_destroy(ena_dev);
3345err_rss_init:
3346
3347 return rc;
3348}
3349
3350static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev)
3351{
d79c3888 3352 int release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
0857d92f 3353
1738cd3e
NB		 3354 pci_release_selected_regions(pdev, release_bars);
3355}
3356
c2b54204 3357static void set_default_llq_configurations(struct ena_llq_configurations *llq_config)
38005ca8
AK		 3358{
3359 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
3360 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
3361 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
3362 llq_config->llq_num_decs_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
3363 llq_config->llq_ring_entry_size_value = 128;
3364}
3365
4d192660 3366static int ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx)
1738cd3e 3367{
31aa9857
SJ		 3368 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
3369 struct ena_com_dev *ena_dev = ctx->ena_dev;
3370 u32 tx_queue_size = ENA_DEFAULT_RING_SIZE;
3371 u32 rx_queue_size = ENA_DEFAULT_RING_SIZE;
3372 u32 max_tx_queue_size;
3373 u32 max_rx_queue_size;
1738cd3e 3374
4d192660 3375 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
31aa9857
SJ		 3376 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
3377 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
3378 max_rx_queue_size = min_t(u32, max_queue_ext->max_rx_cq_depth,
3379 max_queue_ext->max_rx_sq_depth);
3380 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
1738cd3e 3381
31aa9857
SJ		 3382 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
3383 max_tx_queue_size = min_t(u32, max_tx_queue_size,
3384 llq->max_llq_depth);
3385 else
3386 max_tx_queue_size = min_t(u32, max_tx_queue_size,
3387 max_queue_ext->max_tx_sq_depth);
1738cd3e 3388
31aa9857
SJ		 3389 ctx->max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3390 max_queue_ext->max_per_packet_tx_descs);
3391 ctx->max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3392 max_queue_ext->max_per_packet_rx_descs);
3393 } else {
3394 struct ena_admin_queue_feature_desc *max_queues =
3395 &ctx->get_feat_ctx->max_queues;
3396 max_rx_queue_size = min_t(u32, max_queues->max_cq_depth,
3397 max_queues->max_sq_depth);
3398 max_tx_queue_size = max_queues->max_cq_depth;
3399
3400 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
3401 max_tx_queue_size = min_t(u32, max_tx_queue_size,
3402 llq->max_llq_depth);
3403 else
3404 max_tx_queue_size = min_t(u32, max_tx_queue_size,
3405 max_queues->max_sq_depth);
3406
3407 ctx->max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3408 max_queues->max_packet_tx_descs);
3409 ctx->max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3410 max_queues->max_packet_rx_descs);
3411 }
3412
3413 max_tx_queue_size = rounddown_pow_of_two(max_tx_queue_size);
3414 max_rx_queue_size = rounddown_pow_of_two(max_rx_queue_size);
1738cd3e 3415
13ca32a6
SJ		 3416 tx_queue_size = clamp_val(tx_queue_size, ENA_MIN_RING_SIZE,
3417 max_tx_queue_size);
3418 rx_queue_size = clamp_val(rx_queue_size, ENA_MIN_RING_SIZE,
3419 max_rx_queue_size);
31aa9857
SJ		 3420
3421 tx_queue_size = rounddown_pow_of_two(tx_queue_size);
3422 rx_queue_size = rounddown_pow_of_two(rx_queue_size);
3423
31aa9857
SJ		 3424 ctx->max_tx_queue_size = max_tx_queue_size;
3425 ctx->max_rx_queue_size = max_rx_queue_size;
3426 ctx->tx_queue_size = tx_queue_size;
3427 ctx->rx_queue_size = rx_queue_size;
1738cd3e 3428
31aa9857 3429 return 0;
1738cd3e
NB		 3430}
3431
3432/* ena_probe - Device Initialization Routine
3433 * @pdev: PCI device information struct
3434 * @ent: entry in ena_pci_tbl
3435 *
3436 * Returns 0 on success, negative on failure
3437 *
3438 * ena_probe initializes an adapter identified by a pci_dev structure.
3439 * The OS initialization, configuring of the adapter private structure,
3440 * and a hardware reset occur.
3441 */
3442static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3443{
3444 struct ena_com_dev_get_features_ctx get_feat_ctx;
31aa9857 3445 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
38005ca8 3446 struct ena_llq_configurations llq_config;
1738cd3e 3447 struct ena_com_dev *ena_dev = NULL;
83b92404 3448 struct ena_adapter *adapter;
83b92404
SJ		 3449 struct net_device *netdev;
3450 static int adapters_found;
736ce3f4 3451 u32 max_num_io_queues;
83b92404 3452 char *queue_type_str;
1738cd3e 3453 bool wd_state;
736ce3f4 3454 int bars, rc;
1738cd3e
NB		 3455
3456 dev_dbg(&pdev->dev, "%s\n", __func__);
3457
1e9c3fba 3458 dev_info_once(&pdev->dev, "%s", version);
1738cd3e
NB		 3459
3460 rc = pci_enable_device_mem(pdev);
3461 if (rc) {
3462 dev_err(&pdev->dev, "pci_enable_device_mem() failed!\n");
3463 return rc;
3464 }
3465
3466 pci_set_master(pdev);
3467
3468 ena_dev = vzalloc(sizeof(*ena_dev));
3469 if (!ena_dev) {
3470 rc = -ENOMEM;
3471 goto err_disable_device;
3472 }
3473
3474 bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
3475 rc = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME);
3476 if (rc) {
3477 dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n",
3478 rc);
3479 goto err_free_ena_dev;
3480 }
3481
0857d92f
NB		 3482 ena_dev->reg_bar = devm_ioremap(&pdev->dev,
3483 pci_resource_start(pdev, ENA_REG_BAR),
3484 pci_resource_len(pdev, ENA_REG_BAR));
1738cd3e
NB		 3485 if (!ena_dev->reg_bar) {
3486 dev_err(&pdev->dev, "failed to remap regs bar\n");
3487 rc = -EFAULT;
3488 goto err_free_region;
3489 }
3490
3491 ena_dev->dmadev = &pdev->dev;
3492
3493 rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state);
3494 if (rc) {
3495 dev_err(&pdev->dev, "ena device init failed\n");
3496 if (rc == -ETIME)
3497 rc = -EPROBE_DEFER;
3498 goto err_free_region;
3499 }
3500
38005ca8 3501 set_default_llq_configurations(&llq_config);
1738cd3e 3502
38005ca8
AK		 3503 rc = ena_set_queues_placement_policy(pdev, ena_dev, &get_feat_ctx.llq,
3504 &llq_config);
3505 if (rc) {
3506 dev_err(&pdev->dev, "ena device init failed\n");
3507 goto err_device_destroy;
1738cd3e
NB		 3508 }
3509
31aa9857
SJ		 3510 calc_queue_ctx.ena_dev = ena_dev;
3511 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
3512 calc_queue_ctx.pdev = pdev;
3513
15619e72 3514 /* Initial Tx and RX interrupt delay. Assumes 1 usec granularity.
4d192660
SJ		 3515 * Updated during device initialization with the real granularity
3516 */
1738cd3e 3517 ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS;
15619e72 3518 ena_dev->intr_moder_rx_interval = ENA_INTR_INITIAL_RX_INTERVAL_USECS;
79226cea 3519 ena_dev->intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
736ce3f4 3520 max_num_io_queues = ena_calc_max_io_queue_num(pdev, ena_dev, &get_feat_ctx);
4d192660 3521 rc = ena_calc_io_queue_size(&calc_queue_ctx);
736ce3f4 3522 if (rc || !max_num_io_queues) {
1738cd3e
NB		 3523 rc = -EFAULT;
3524 goto err_device_destroy;
3525 }
3526
1738cd3e 3527 /* dev zeroed in init_etherdev */
736ce3f4 3528 netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), max_num_io_queues);
1738cd3e
NB		 3529 if (!netdev) {
3530 dev_err(&pdev->dev, "alloc_etherdev_mq failed\n");
3531 rc = -ENOMEM;
3532 goto err_device_destroy;
3533 }
3534
3535 SET_NETDEV_DEV(netdev, &pdev->dev);
3536
3537 adapter = netdev_priv(netdev);
3538 pci_set_drvdata(pdev, adapter);
3539
3540 adapter->ena_dev = ena_dev;
3541 adapter->netdev = netdev;
3542 adapter->pdev = pdev;
3543
3544 ena_set_conf_feat_params(adapter, &get_feat_ctx);
3545
3546 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
e2eed0e3 3547 adapter->reset_reason = ENA_REGS_RESET_NORMAL;
1738cd3e 3548
13ca32a6
SJ		 3549 adapter->requested_tx_ring_size = calc_queue_ctx.tx_queue_size;
3550 adapter->requested_rx_ring_size = calc_queue_ctx.rx_queue_size;
9f9ae3f9
SJ		 3551 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
3552 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
31aa9857
SJ		 3553 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
3554 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1738cd3e 3555
736ce3f4
SJ		 3556 adapter->num_io_queues = max_num_io_queues;
3557 adapter->max_num_io_queues = max_num_io_queues;
3558
1738cd3e
NB		 3559 adapter->last_monitored_tx_qid = 0;
3560
3561 adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK;
3562 adapter->wd_state = wd_state;
3563
3564 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapters_found);
3565
3566 rc = ena_com_init_interrupt_moderation(adapter->ena_dev);
3567 if (rc) {
3568 dev_err(&pdev->dev,
3569 "Failed to query interrupt moderation feature\n");
3570 goto err_netdev_destroy;
3571 }
3572 ena_init_io_rings(adapter);
3573
3574 netdev->netdev_ops = &ena_netdev_ops;
3575 netdev->watchdog_timeo = TX_TIMEOUT;
3576 ena_set_ethtool_ops(netdev);
3577
3578 netdev->priv_flags |= IFF_UNICAST_FLT;
3579
3580 u64_stats_init(&adapter->syncp);
3581
4d192660 3582 rc = ena_enable_msix_and_set_admin_interrupts(adapter);
1738cd3e
NB		 3583 if (rc) {
3584 dev_err(&pdev->dev,
3585 "Failed to enable and set the admin interrupts\n");
3586 goto err_worker_destroy;
3587 }
3588 rc = ena_rss_init_default(adapter);
d1497638 3589 if (rc && (rc != -EOPNOTSUPP)) {
1738cd3e
NB		 3590 dev_err(&pdev->dev, "Cannot init RSS rc: %d\n", rc);
3591 goto err_free_msix;
3592 }
3593
3594 ena_config_debug_area(adapter);
3595
3596 memcpy(adapter->netdev->perm_addr, adapter->mac_addr, netdev->addr_len);
3597
3598 netif_carrier_off(netdev);
3599
3600 rc = register_netdev(netdev);
3601 if (rc) {
3602 dev_err(&pdev->dev, "Cannot register net device\n");
3603 goto err_rss;
3604 }
3605
1738cd3e
NB		 3606 INIT_WORK(&adapter->reset_task, ena_fw_reset_device);
3607
3608 adapter->last_keep_alive_jiffies = jiffies;
82ef30f1
NB		 3609 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
3610 adapter->missing_tx_completion_to = TX_TIMEOUT;
3611 adapter->missing_tx_completion_threshold = MAX_NUM_OF_TIMEOUTED_PACKETS;
3612
3613 ena_update_hints(adapter, &get_feat_ctx.hw_hints);
1738cd3e 3614
e99e88a9 3615 timer_setup(&adapter->timer_service, ena_timer_service, 0);
f850b4a7 3616 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
1738cd3e 3617
38005ca8
AK		 3618 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
3619 queue_type_str = "Regular";
3620 else
3621 queue_type_str = "Low Latency";
3622
3623 dev_info(&pdev->dev,
9f648f7b 3624 "%s found at mem %lx, mac addr %pM, Placement policy: %s\n",
1738cd3e 3625 DEVICE_NAME, (long)pci_resource_start(pdev, 0),
9f648f7b 3626 netdev->dev_addr, queue_type_str);
1738cd3e
NB		 3627
3628 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
3629
3630 adapters_found++;
3631
3632 return 0;
3633
3634err_rss:
3635 ena_com_delete_debug_area(ena_dev);
3636 ena_com_rss_destroy(ena_dev);
3637err_free_msix:
e2eed0e3 3638 ena_com_dev_reset(ena_dev, ENA_REGS_RESET_INIT_ERR);
58a54b9c
AK		 3639 /* stop submitting admin commands on a device that was reset */
3640 ena_com_set_admin_running_state(ena_dev, false);
1738cd3e 3641 ena_free_mgmnt_irq(adapter);
06443684 3642 ena_disable_msix(adapter);
1738cd3e 3643err_worker_destroy:
1738cd3e 3644 del_timer(&adapter->timer_service);
1738cd3e
NB		 3645err_netdev_destroy:
3646 free_netdev(netdev);
3647err_device_destroy:
3648 ena_com_delete_host_info(ena_dev);
3649 ena_com_admin_destroy(ena_dev);
3650err_free_region:
3651 ena_release_bars(ena_dev, pdev);
3652err_free_ena_dev:
1738cd3e
NB		 3653 vfree(ena_dev);
3654err_disable_device:
3655 pci_disable_device(pdev);
3656 return rc;
3657}
3658
1738cd3e
NB		 3659/*****************************************************************************/
3660
3661/* ena_remove - Device Removal Routine
3662 * @pdev: PCI device information struct
3663 *
3664 * ena_remove is called by the PCI subsystem to alert the driver
3665 * that it should release a PCI device.
3666 */
3667static void ena_remove(struct pci_dev *pdev)
3668{
3669 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3670 struct ena_com_dev *ena_dev;
3671 struct net_device *netdev;
3672
1738cd3e
NB		 3673 ena_dev = adapter->ena_dev;
3674 netdev = adapter->netdev;
3675
3676#ifdef CONFIG_RFS_ACCEL
3677 if ((adapter->msix_vecs >= 1) && (netdev->rx_cpu_rmap)) {
3678 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
3679 netdev->rx_cpu_rmap = NULL;
3680 }
3681#endif /* CONFIG_RFS_ACCEL */
1738cd3e
NB		 3682 del_timer_sync(&adapter->timer_service);
3683
3684 cancel_work_sync(&adapter->reset_task);
3685
944b28aa
NB		 3686 rtnl_lock();
3687 ena_destroy_device(adapter, true);
3688 rtnl_unlock();
1738cd3e 3689
58a54b9c
AK		 3690 unregister_netdev(netdev);
3691
1738cd3e
NB		 3692 free_netdev(netdev);
3693
1738cd3e
NB		 3694 ena_com_rss_destroy(ena_dev);
3695
3696 ena_com_delete_debug_area(ena_dev);
3697
3698 ena_com_delete_host_info(ena_dev);
3699
3700 ena_release_bars(ena_dev, pdev);
3701
1738cd3e
NB		 3702 pci_disable_device(pdev);
3703
1738cd3e
NB		 3704 vfree(ena_dev);
3705}
3706
8c5c7abd
NB		 3707#ifdef CONFIG_PM
3708/* ena_suspend - PM suspend callback
3709 * @pdev: PCI device information struct
3710 * @state:power state
3711 */
3712static int ena_suspend(struct pci_dev *pdev, pm_message_t state)
3713{
3714 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3715
3716 u64_stats_update_begin(&adapter->syncp);
3717 adapter->dev_stats.suspend++;
3718 u64_stats_update_end(&adapter->syncp);
3719
3720 rtnl_lock();
3721 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
3722 dev_err(&pdev->dev,
3723 "ignoring device reset request as the device is being suspended\n");
3724 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
3725 }
cfa324a5 3726 ena_destroy_device(adapter, true);
8c5c7abd
NB		 3727 rtnl_unlock();
3728 return 0;
3729}
3730
3731/* ena_resume - PM resume callback
3732 * @pdev: PCI device information struct
3733 *
3734 */
3735static int ena_resume(struct pci_dev *pdev)
3736{
3737 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3738 int rc;
3739
3740 u64_stats_update_begin(&adapter->syncp);
3741 adapter->dev_stats.resume++;
3742 u64_stats_update_end(&adapter->syncp);
3743
3744 rtnl_lock();
3745 rc = ena_restore_device(adapter);
3746 rtnl_unlock();
3747 return rc;
3748}
3749#endif
3750
1738cd3e
NB		 3751static struct pci_driver ena_pci_driver = {
3752 .name = DRV_MODULE_NAME,
3753 .id_table = ena_pci_tbl,
3754 .probe = ena_probe,
3755 .remove = ena_remove,
8c5c7abd
NB		 3756#ifdef CONFIG_PM
3757 .suspend = ena_suspend,
3758 .resume = ena_resume,
3759#endif
115ddc49 3760 .sriov_configure = pci_sriov_configure_simple,
1738cd3e
NB		 3761};
3762
3763static int __init ena_init(void)
3764{
3765 pr_info("%s", version);
3766
3767 ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME);
3768 if (!ena_wq) {
3769 pr_err("Failed to create workqueue\n");
3770 return -ENOMEM;
3771 }
3772
3773 return pci_register_driver(&ena_pci_driver);
3774}
3775
3776static void __exit ena_cleanup(void)
3777{
3778 pci_unregister_driver(&ena_pci_driver);
3779
3780 if (ena_wq) {
3781 destroy_workqueue(ena_wq);
3782 ena_wq = NULL;
3783 }
3784}
3785
3786/******************************************************************************
3787 ******************************** AENQ Handlers *******************************
3788 *****************************************************************************/
3789/* ena_update_on_link_change:
3790 * Notify the network interface about the change in link status
3791 */
3792static void ena_update_on_link_change(void *adapter_data,
3793 struct ena_admin_aenq_entry *aenq_e)
3794{
3795 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3796 struct ena_admin_aenq_link_change_desc *aenq_desc =
3797 (struct ena_admin_aenq_link_change_desc *)aenq_e;
3798 int status = aenq_desc->flags &
3799 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
3800
3801 if (status) {
3802 netdev_dbg(adapter->netdev, "%s\n", __func__);
3803 set_bit(ENA_FLAG_LINK_UP, &adapter->flags);
d18e4f68
NB		 3804 if (!test_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags))
3805 netif_carrier_on(adapter->netdev);
1738cd3e
NB		 3806 } else {
3807 clear_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3808 netif_carrier_off(adapter->netdev);
3809 }
3810}
3811
3812static void ena_keep_alive_wd(void *adapter_data,
3813 struct ena_admin_aenq_entry *aenq_e)
3814{
3815 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
11a9a460
NB		 3816 struct ena_admin_aenq_keep_alive_desc *desc;
3817 u64 rx_drops;
1738cd3e 3818
11a9a460 3819 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
1738cd3e 3820 adapter->last_keep_alive_jiffies = jiffies;
11a9a460
NB		 3821
3822 rx_drops = ((u64)desc->rx_drops_high << 32) | desc->rx_drops_low;
3823
3824 u64_stats_update_begin(&adapter->syncp);
3825 adapter->dev_stats.rx_drops = rx_drops;
3826 u64_stats_update_end(&adapter->syncp);
1738cd3e
NB		 3827}
3828
3829static void ena_notification(void *adapter_data,
3830 struct ena_admin_aenq_entry *aenq_e)
3831{
3832 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
82ef30f1 3833 struct ena_admin_ena_hw_hints *hints;
1738cd3e
NB		 3834
3835 WARN(aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION,
3836 "Invalid group(%x) expected %x\n",
3837 aenq_e->aenq_common_desc.group,
3838 ENA_ADMIN_NOTIFICATION);
3839
3840 switch (aenq_e->aenq_common_desc.syndrom) {
82ef30f1
NB		 3841 case ENA_ADMIN_UPDATE_HINTS:
3842 hints = (struct ena_admin_ena_hw_hints *)
3843 (&aenq_e->inline_data_w4);
3844 ena_update_hints(adapter, hints);
3845 break;
1738cd3e
NB		 3846 default:
3847 netif_err(adapter, drv, adapter->netdev,
3848 "Invalid aenq notification link state %d\n",
3849 aenq_e->aenq_common_desc.syndrom);
3850 }
3851}
3852
3853/* This handler will called for unknown event group or unimplemented handlers*/
3854static void unimplemented_aenq_handler(void *data,
3855 struct ena_admin_aenq_entry *aenq_e)
3856{
3857 struct ena_adapter *adapter = (struct ena_adapter *)data;
3858
3859 netif_err(adapter, drv, adapter->netdev,
3860 "Unknown event was received or event with unimplemented handler\n");
3861}
3862
3863static struct ena_aenq_handlers aenq_handlers = {
3864 .handlers = {
3865 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3866 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3867 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd,
3868 },
3869 .unimplemented_handler = unimplemented_aenq_handler
3870};
3871
3872module_init(ena_init);
3873module_exit(ena_cleanup);
Linux 6.x block layer and io_uring tree(s)