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ixgbe: Power down PHY during driver resets
[linux-2.6-block.git] / drivers / net / e1000e / e1000.h
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bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
c7e54b1b 4 Copyright(c) 1999 - 2009 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _E1000_H_
32#define _E1000_H_
33
34#include <linux/types.h>
35#include <linux/timer.h>
36#include <linux/workqueue.h>
37#include <linux/io.h>
38#include <linux/netdevice.h>
d8014dbc 39#include <linux/pci.h>
bc7f75fa
AK		 40
41#include "hw.h"
42
43struct e1000_info;
44
44defeb3
JK		 45#define e_printk(level, adapter, format, arg...) \
46 printk(level "%s: %s: " format, pci_name(adapter->pdev), \
47 adapter->netdev->name, ## arg)
bc7f75fa
AK		 48
49#ifdef DEBUG
44defeb3 50#define e_dbg(format, arg...) \
3bb99fe2 51 e_printk(KERN_DEBUG , hw->adapter, format, ## arg)
bc7f75fa 52#else
3bb99fe2 53#define e_dbg(format, arg...) do { (void)(hw); } while (0)
bc7f75fa
AK		 54#endif
55
44defeb3
JK		 56#define e_err(format, arg...) \
57 e_printk(KERN_ERR, adapter, format, ## arg)
58#define e_info(format, arg...) \
59 e_printk(KERN_INFO, adapter, format, ## arg)
60#define e_warn(format, arg...) \
61 e_printk(KERN_WARNING, adapter, format, ## arg)
62#define e_notice(format, arg...) \
63 e_printk(KERN_NOTICE, adapter, format, ## arg)
bc7f75fa
AK		 64
65
98a1708d 66/* Interrupt modes, as used by the IntMode parameter */
4662e82b
BA		 67#define E1000E_INT_MODE_LEGACY 0
68#define E1000E_INT_MODE_MSI 1
69#define E1000E_INT_MODE_MSIX 2
70
ad68076e 71/* Tx/Rx descriptor defines */
bc7f75fa
AK		 72#define E1000_DEFAULT_TXD 256
73#define E1000_MAX_TXD 4096
7b1be198 74#define E1000_MIN_TXD 64
bc7f75fa
AK		 75
76#define E1000_DEFAULT_RXD 256
77#define E1000_MAX_RXD 4096
7b1be198 78#define E1000_MIN_RXD 64
bc7f75fa 79
de5b3077
AK		 80#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
81#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
82
bc7f75fa
AK		 83/* Early Receive defines */
84#define E1000_ERT_2048 0x100
85
86#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
87
88/* How many Tx Descriptors do we need to call netif_wake_queue ? */
89/* How many Rx Buffers do we bundle into one write to the hardware ? */
90#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
91
92#define AUTO_ALL_MODES 0
93#define E1000_EEPROM_APME 0x0400
94
95#define E1000_MNG_VLAN_NONE (-1)
96
97/* Number of packet split data buffers (not including the header buffer) */
98#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
99
2adc55c9
BA		 100#define DEFAULT_JUMBO 9234
101
a4f58f54
BA		 102/* BM/HV Specific Registers */
103#define BM_PORT_CTRL_PAGE 769
104
105#define PHY_UPPER_SHIFT 21
106#define BM_PHY_REG(page, reg) \
107 (((reg) & MAX_PHY_REG_ADDRESS) |\
108 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
109 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
110
111/* PHY Wakeup Registers and defines */
112#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
113#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
114#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
115#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
116#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
117#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
118#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
119#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
120#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
121
122#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
123#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
124#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
125#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
126#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
127#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
128#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
129
130#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
131#define HV_SCC_LOWER PHY_REG(778, 17)
132#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
133#define HV_ECOL_LOWER PHY_REG(778, 19)
134#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
135#define HV_MCC_LOWER PHY_REG(778, 21)
136#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */
137#define HV_LATECOL_LOWER PHY_REG(778, 24)
138#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */
139#define HV_COLC_LOWER PHY_REG(778, 26)
140#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */
141#define HV_DC_LOWER PHY_REG(778, 28)
142#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
143#define HV_TNCRS_LOWER PHY_REG(778, 30)
144
38eb394e
BA		 145#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
146
1d5846b9
BA		 147/* BM PHY Copper Specific Status */
148#define BM_CS_STATUS 17
149#define BM_CS_STATUS_LINK_UP 0x0400
150#define BM_CS_STATUS_RESOLVED 0x0800
151#define BM_CS_STATUS_SPEED_MASK 0xC000
152#define BM_CS_STATUS_SPEED_1000 0x8000
153
154/* 82577 Mobile Phy Status Register */
155#define HV_M_STATUS 26
156#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
157#define HV_M_STATUS_SPEED_MASK 0x0300
158#define HV_M_STATUS_SPEED_1000 0x0200
159#define HV_M_STATUS_LINK_UP 0x0040
160
bc7f75fa
AK		 161enum e1000_boards {
162 board_82571,
163 board_82572,
164 board_82573,
4662e82b 165 board_82574,
8c81c9c3 166 board_82583,
bc7f75fa
AK		 167 board_80003es2lan,
168 board_ich8lan,
169 board_ich9lan,
f4187b56 170 board_ich10lan,
a4f58f54 171 board_pchlan,
bc7f75fa
AK		 172};
173
174struct e1000_queue_stats {
175 u64 packets;
176 u64 bytes;
177};
178
179struct e1000_ps_page {
180 struct page *page;
181 u64 dma; /* must be u64 - written to hw */
182};
183
184/*
185 * wrappers around a pointer to a socket buffer,
186 * so a DMA handle can be stored along with the buffer
187 */
188struct e1000_buffer {
189 dma_addr_t dma;
190 struct sk_buff *skb;
191 union {
ad68076e 192 /* Tx */
bc7f75fa
AK		 193 struct {
194 unsigned long time_stamp;
195 u16 length;
196 u16 next_to_watch;
03b1320d 197 u16 mapped_as_page;
bc7f75fa 198 };
ad68076e 199 /* Rx */
03b1320d
AD		 200 struct {
201 /* arrays of page information for packet split */
202 struct e1000_ps_page *ps_pages;
203 struct page *page;
204 };
bc7f75fa 205 };
bc7f75fa
AK		 206};
207
208struct e1000_ring {
209 void *desc; /* pointer to ring memory */
210 dma_addr_t dma; /* phys address of ring */
211 unsigned int size; /* length of ring in bytes */
212 unsigned int count; /* number of desc. in ring */
213
214 u16 next_to_use;
215 u16 next_to_clean;
216
217 u16 head;
218 u16 tail;
219
220 /* array of buffer information structs */
221 struct e1000_buffer *buffer_info;
222
4662e82b
BA		 223 char name[IFNAMSIZ + 5];
224 u32 ims_val;
225 u32 itr_val;
226 u16 itr_register;
227 int set_itr;
228
bc7f75fa
AK		 229 struct sk_buff *rx_skb_top;
230
231 struct e1000_queue_stats stats;
232};
233
7c25769f
BA		 234/* PHY register snapshot values */
235struct e1000_phy_regs {
236 u16 bmcr; /* basic mode control register */
237 u16 bmsr; /* basic mode status register */
238 u16 advertise; /* auto-negotiation advertisement */
239 u16 lpa; /* link partner ability register */
240 u16 expansion; /* auto-negotiation expansion reg */
241 u16 ctrl1000; /* 1000BASE-T control register */
242 u16 stat1000; /* 1000BASE-T status register */
243 u16 estatus; /* extended status register */
244};
245
bc7f75fa
AK		 246/* board specific private data structure */
247struct e1000_adapter {
248 struct timer_list watchdog_timer;
249 struct timer_list phy_info_timer;
250 struct timer_list blink_timer;
251
252 struct work_struct reset_task;
253 struct work_struct watchdog_task;
254
255 const struct e1000_info *ei;
256
257 struct vlan_group *vlgrp;
258 u32 bd_number;
259 u32 rx_buffer_len;
260 u16 mng_vlan_id;
261 u16 link_speed;
262 u16 link_duplex;
84527590 263 u16 eeprom_vers;
bc7f75fa 264
bc7f75fa
AK		 265 /* track device up/down/testing state */
266 unsigned long state;
267
268 /* Interrupt Throttle Rate */
269 u32 itr;
270 u32 itr_setting;
271 u16 tx_itr;
272 u16 rx_itr;
273
274 /*
ad68076e 275 * Tx
bc7f75fa
AK		 276 */
277 struct e1000_ring *tx_ring /* One per active queue */
278 ____cacheline_aligned_in_smp;
279
280 struct napi_struct napi;
281
bc7f75fa
AK		 282 unsigned int restart_queue;
283 u32 txd_cmd;
284
285 bool detect_tx_hung;
286 u8 tx_timeout_factor;
287
288 u32 tx_int_delay;
289 u32 tx_abs_int_delay;
290
291 unsigned int total_tx_bytes;
292 unsigned int total_tx_packets;
293 unsigned int total_rx_bytes;
294 unsigned int total_rx_packets;
295
ad68076e 296 /* Tx stats */
bc7f75fa
AK		 297 u64 tpt_old;
298 u64 colc_old;
7c25769f
BA		 299 u32 gotc;
300 u64 gotc_old;
bc7f75fa
AK		 301 u32 tx_timeout_count;
302 u32 tx_fifo_head;
303 u32 tx_head_addr;
304 u32 tx_fifo_size;
305 u32 tx_dma_failed;
306
307 /*
ad68076e 308 * Rx
bc7f75fa
AK		 309 */
310 bool (*clean_rx) (struct e1000_adapter *adapter,
311 int *work_done, int work_to_do)
312 ____cacheline_aligned_in_smp;
313 void (*alloc_rx_buf) (struct e1000_adapter *adapter,
314 int cleaned_count);
315 struct e1000_ring *rx_ring;
316
317 u32 rx_int_delay;
318 u32 rx_abs_int_delay;
319
ad68076e 320 /* Rx stats */
bc7f75fa
AK		 321 u64 hw_csum_err;
322 u64 hw_csum_good;
323 u64 rx_hdr_split;
7c25769f
BA		 324 u32 gorc;
325 u64 gorc_old;
bc7f75fa
AK		 326 u32 alloc_rx_buff_failed;
327 u32 rx_dma_failed;
328
329 unsigned int rx_ps_pages;
330 u16 rx_ps_bsize0;
318a94d6
JK		 331 u32 max_frame_size;
332 u32 min_frame_size;
bc7f75fa
AK		 333
334 /* OS defined structs */
335 struct net_device *netdev;
336 struct pci_dev *pdev;
bc7f75fa
AK		 337
338 /* structs defined in e1000_hw.h */
339 struct e1000_hw hw;
340
341 struct e1000_hw_stats stats;
342 struct e1000_phy_info phy_info;
343 struct e1000_phy_stats phy_stats;
344
7c25769f
BA		 345 /* Snapshot of PHY registers */
346 struct e1000_phy_regs phy_regs;
347
bc7f75fa
AK		 348 struct e1000_ring test_tx_ring;
349 struct e1000_ring test_rx_ring;
350 u32 test_icr;
351
352 u32 msg_enable;
4662e82b
BA		 353 struct msix_entry *msix_entries;
354 int int_mode;
355 u32 eiac_mask;
bc7f75fa
AK		 356
357 u32 eeprom_wol;
358 u32 wol;
359 u32 pba;
2adc55c9 360 u32 max_hw_frame_size;
bc7f75fa 361
318a94d6 362 bool fc_autoneg;
bc7f75fa
AK		 363
364 unsigned long led_status;
365
366 unsigned int flags;
eb7c3adb 367 unsigned int flags2;
a8f88ff5
JB		 368 struct work_struct downshift_task;
369 struct work_struct update_phy_task;
a4f58f54 370 struct work_struct led_blink_task;
41cec6f1 371 struct work_struct print_hang_task;
bc7f75fa
AK		 372};
373
374struct e1000_info {
375 enum e1000_mac_type mac;
376 unsigned int flags;
eb7c3adb 377 unsigned int flags2;
bc7f75fa 378 u32 pba;
2adc55c9 379 u32 max_hw_frame_size;
69e3fd8c 380 s32 (*get_variants)(struct e1000_adapter *);
bc7f75fa
AK		 381 struct e1000_mac_operations *mac_ops;
382 struct e1000_phy_operations *phy_ops;
383 struct e1000_nvm_operations *nvm_ops;
384};
385
386/* hardware capability, feature, and workaround flags */
387#define FLAG_HAS_AMT (1 << 0)
388#define FLAG_HAS_FLASH (1 << 1)
389#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
390#define FLAG_HAS_WOL (1 << 3)
391#define FLAG_HAS_ERT (1 << 4)
392#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
393#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
394#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
4a770358 395#define FLAG_READ_ONLY_NVM (1 << 8)
97ac8cae 396#define FLAG_IS_ICH (1 << 9)
4662e82b 397#define FLAG_HAS_MSIX (1 << 10)
bc7f75fa
AK		 398#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
399#define FLAG_IS_QUAD_PORT_A (1 << 12)
400#define FLAG_IS_QUAD_PORT (1 << 13)
401#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14)
402#define FLAG_APME_IN_WUC (1 << 15)
403#define FLAG_APME_IN_CTRL3 (1 << 16)
404#define FLAG_APME_CHECK_PORT_B (1 << 17)
405#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
406#define FLAG_NO_WAKE_UCAST (1 << 19)
407#define FLAG_MNG_PT_ENABLED (1 << 20)
408#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
409#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
410#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
411#define FLAG_RX_NEEDS_RESTART (1 << 24)
412#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
413#define FLAG_SMART_POWER_DOWN (1 << 26)
414#define FLAG_MSI_ENABLED (1 << 27)
415#define FLAG_RX_CSUM_ENABLED (1 << 28)
416#define FLAG_TSO_FORCE (1 << 29)
318a94d6 417#define FLAG_RX_RESTART_NOW (1 << 30)
f8d59f78 418#define FLAG_MSI_TEST_FAILED (1 << 31)
bc7f75fa 419
eb7c3adb
JK		 420/* CRC Stripping defines */
421#define FLAG2_CRC_STRIPPING (1 << 0)
a4f58f54 422#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
b94b5028 423#define FLAG2_IS_DISCARDING (1 << 2)
eb7c3adb 424
bc7f75fa
AK		 425#define E1000_RX_DESC_PS(R, i) \
426 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
427#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
428#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
429#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
430#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
431
432enum e1000_state_t {
433 __E1000_TESTING,
434 __E1000_RESETTING,
435 __E1000_DOWN
436};
437
438enum latency_range {
439 lowest_latency = 0,
440 low_latency = 1,
441 bulk_latency = 2,
442 latency_invalid = 255
443};
444
445extern char e1000e_driver_name[];
446extern const char e1000e_driver_version[];
447
448extern void e1000e_check_options(struct e1000_adapter *adapter);
449extern void e1000e_set_ethtool_ops(struct net_device *netdev);
450
451extern int e1000e_up(struct e1000_adapter *adapter);
452extern void e1000e_down(struct e1000_adapter *adapter);
453extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
454extern void e1000e_reset(struct e1000_adapter *adapter);
455extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
456extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);
457extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);
458extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);
459extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
460extern void e1000e_update_stats(struct e1000_adapter *adapter);
b405e8df 461extern bool e1000e_has_link(struct e1000_adapter *adapter);
4662e82b
BA		 462extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
463extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
bc7f75fa
AK		 464
465extern unsigned int copybreak;
466
467extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
468
469extern struct e1000_info e1000_82571_info;
470extern struct e1000_info e1000_82572_info;
471extern struct e1000_info e1000_82573_info;
4662e82b 472extern struct e1000_info e1000_82574_info;
8c81c9c3 473extern struct e1000_info e1000_82583_info;
bc7f75fa
AK		 474extern struct e1000_info e1000_ich8_info;
475extern struct e1000_info e1000_ich9_info;
f4187b56 476extern struct e1000_info e1000_ich10_info;
a4f58f54 477extern struct e1000_info e1000_pch_info;
bc7f75fa
AK		 478extern struct e1000_info e1000_es2_info;
479
69e3fd8c 480extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
bc7f75fa
AK		 481
482extern s32 e1000e_commit_phy(struct e1000_hw *hw);
483
484extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
485
486extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
487extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
488
4a770358 489extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 490extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
491 bool state);
492extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
493extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
97ac8cae 494extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
bb436b20 495extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
bc7f75fa
AK		 496
497extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
498extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
499extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
a4f58f54 500extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
bc7f75fa
AK		 501extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
502extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
503extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
504extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
f4d2dd4c
BA		 505extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
506extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
bc7f75fa
AK		 507extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
508extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
509extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
510extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
511extern s32 e1000e_id_led_init(struct e1000_hw *hw);
512extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
513extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
514extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
515extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
516extern s32 e1000e_setup_link(struct e1000_hw *hw);
caaddaf8 517extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
bc7f75fa 518extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
e2de3eb6
JK		 519extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
520 u8 *mc_addr_list,
ab8932f3 521 u32 mc_addr_count);
bc7f75fa
AK		 522extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
523extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
524extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
525extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
526extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
527extern void e1000e_config_collision_dist(struct e1000_hw *hw);
528extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
529extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
530extern s32 e1000e_blink_led(struct e1000_hw *hw);
caaddaf8 531extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
608f8a0d 532extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
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AK		 533extern void e1000e_reset_adaptive(struct e1000_hw *hw);
534extern void e1000e_update_adaptive(struct e1000_hw *hw);
535
536extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
537extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
538extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
539extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
540extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
541extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
542extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
543extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
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BA		 544extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
545 u16 *data);
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AK		 546extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
547extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
548extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
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BA		 549extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
550 u16 data);
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AK		 551extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
552extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
553extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
554extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
555extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
556extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
557extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
f4187b56 558extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
bc7f75fa 559extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
97ac8cae
BA		 560extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
561extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
562extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
4662e82b
BA		 563extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
564extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
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AK		 565extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
566extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
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BA		 567extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
568 u16 data);
bc7f75fa 569extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
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BA		 570extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
571 u16 *data);
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AK		 572extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
573 u32 usec_interval, bool *success);
574extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
17f208de
BA		 575extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
576extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
2d9498f3
DG		 577extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
578extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa 579extern s32 e1000e_check_downshift(struct e1000_hw *hw);
a4f58f54 580extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
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BA		 581extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
582 u16 *data);
a4f58f54 583extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 584extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
585 u16 data);
a4f58f54
BA		 586extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
587extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
588extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
589extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
590extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
591extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
bc7f75fa 592
0be84010
BA		 593extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
594extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
595extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
596extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
597extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
598
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AK		 599static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
600{
94d8186a 601 return hw->phy.ops.reset(hw);
bc7f75fa
AK		 602}
603
604static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
605{
606 return hw->phy.ops.check_reset_block(hw);
607}
608
609static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
610{
94d8186a 611 return hw->phy.ops.read_reg(hw, offset, data);
bc7f75fa
AK		 612}
613
614static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
615{
94d8186a 616 return hw->phy.ops.write_reg(hw, offset, data);
bc7f75fa
AK		 617}
618
619static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
620{
621 return hw->phy.ops.get_cable_length(hw);
622}
623
624extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
625extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
626extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
627extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
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AK		 628extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
629extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
630extern void e1000e_release_nvm(struct e1000_hw *hw);
631extern void e1000e_reload_nvm(struct e1000_hw *hw);
608f8a0d
BA		 632extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
633
634static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
635{
636 if (hw->mac.ops.read_mac_addr)
637 return hw->mac.ops.read_mac_addr(hw);
638
639 return e1000_read_mac_addr_generic(hw);
640}
bc7f75fa
AK		 641
642static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
643{
94d8186a 644 return hw->nvm.ops.validate(hw);
bc7f75fa
AK		 645}
646
647static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
648{
94d8186a 649 return hw->nvm.ops.update(hw);
bc7f75fa
AK		 650}
651
652static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
653{
94d8186a 654 return hw->nvm.ops.read(hw, offset, words, data);
bc7f75fa
AK		 655}
656
657static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
658{
94d8186a 659 return hw->nvm.ops.write(hw, offset, words, data);
bc7f75fa
AK		 660}
661
662static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
663{
94d8186a 664 return hw->phy.ops.get_info(hw);
bc7f75fa
AK		 665}
666
4662e82b
BA		 667static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw)
668{
669 return hw->mac.ops.check_mng_mode(hw);
670}
671
672extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
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AK		 673extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
674extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
675
676static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
677{
678 return readl(hw->hw_addr + reg);
679}
680
681static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
682{
683 writel(val, hw->hw_addr + reg);
684}
685
686#endif /* _E1000_H_ */
Linux 6.x block layer and io_uring tree(s)