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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
c7e54b1b | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
8c81c9c3 | 43 | * 82583V Gigabit Network Connection |
bc7f75fa AK |
44 | */ |
45 | ||
bc7f75fa AK |
46 | #include "e1000.h" |
47 | ||
48 | #define ID_LED_RESERVED_F746 0xF746 | |
49 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
50 | (ID_LED_OFF1_ON2 << 8) | \ | |
51 | (ID_LED_DEF1_DEF2 << 4) | \ | |
52 | (ID_LED_DEF1_DEF2)) | |
53 | ||
54 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
55 | ||
4662e82b BA |
56 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
57 | ||
bc7f75fa AK |
58 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
59 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
60 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
c9523379 | 61 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
bc7f75fa AK |
62 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
63 | u16 words, u16 *data); | |
64 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
65 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
66 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
67 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
caaddaf8 | 68 | static void e1000_clear_vfta_82571(struct e1000_hw *hw); |
4662e82b BA |
69 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
70 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
23a2d1b2 | 71 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
17f208de | 72 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); |
bc7f75fa AK |
73 | |
74 | /** | |
75 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
76 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
77 | **/ |
78 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
79 | { | |
80 | struct e1000_phy_info *phy = &hw->phy; | |
81 | s32 ret_val; | |
82 | ||
318a94d6 | 83 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
84 | phy->type = e1000_phy_none; |
85 | return 0; | |
86 | } | |
87 | ||
88 | phy->addr = 1; | |
89 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
90 | phy->reset_delay_us = 100; | |
91 | ||
17f208de BA |
92 | phy->ops.power_up = e1000_power_up_phy_copper; |
93 | phy->ops.power_down = e1000_power_down_phy_copper_82571; | |
94 | ||
bc7f75fa AK |
95 | switch (hw->mac.type) { |
96 | case e1000_82571: | |
97 | case e1000_82572: | |
98 | phy->type = e1000_phy_igp_2; | |
99 | break; | |
100 | case e1000_82573: | |
101 | phy->type = e1000_phy_m88; | |
102 | break; | |
4662e82b | 103 | case e1000_82574: |
8c81c9c3 | 104 | case e1000_82583: |
4662e82b BA |
105 | phy->type = e1000_phy_bm; |
106 | break; | |
bc7f75fa AK |
107 | default: |
108 | return -E1000_ERR_PHY; | |
109 | break; | |
110 | } | |
111 | ||
112 | /* This can only be done after all function pointers are setup. */ | |
113 | ret_val = e1000_get_phy_id_82571(hw); | |
114 | ||
115 | /* Verify phy id */ | |
116 | switch (hw->mac.type) { | |
117 | case e1000_82571: | |
118 | case e1000_82572: | |
119 | if (phy->id != IGP01E1000_I_PHY_ID) | |
120 | return -E1000_ERR_PHY; | |
121 | break; | |
122 | case e1000_82573: | |
123 | if (phy->id != M88E1111_I_PHY_ID) | |
124 | return -E1000_ERR_PHY; | |
125 | break; | |
4662e82b | 126 | case e1000_82574: |
8c81c9c3 | 127 | case e1000_82583: |
4662e82b BA |
128 | if (phy->id != BME1000_E_PHY_ID_R2) |
129 | return -E1000_ERR_PHY; | |
130 | break; | |
bc7f75fa AK |
131 | default: |
132 | return -E1000_ERR_PHY; | |
133 | break; | |
134 | } | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | /** | |
140 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
141 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
142 | **/ |
143 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
144 | { | |
145 | struct e1000_nvm_info *nvm = &hw->nvm; | |
146 | u32 eecd = er32(EECD); | |
147 | u16 size; | |
148 | ||
149 | nvm->opcode_bits = 8; | |
150 | nvm->delay_usec = 1; | |
151 | switch (nvm->override) { | |
152 | case e1000_nvm_override_spi_large: | |
153 | nvm->page_size = 32; | |
154 | nvm->address_bits = 16; | |
155 | break; | |
156 | case e1000_nvm_override_spi_small: | |
157 | nvm->page_size = 8; | |
158 | nvm->address_bits = 8; | |
159 | break; | |
160 | default: | |
161 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
162 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
163 | break; | |
164 | } | |
165 | ||
166 | switch (hw->mac.type) { | |
167 | case e1000_82573: | |
4662e82b | 168 | case e1000_82574: |
8c81c9c3 | 169 | case e1000_82583: |
bc7f75fa AK |
170 | if (((eecd >> 15) & 0x3) == 0x3) { |
171 | nvm->type = e1000_nvm_flash_hw; | |
172 | nvm->word_size = 2048; | |
ad68076e BA |
173 | /* |
174 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
175 | * to Flash update issue. |
176 | */ | |
177 | eecd &= ~E1000_EECD_AUPDEN; | |
178 | ew32(EECD, eecd); | |
179 | break; | |
180 | } | |
181 | /* Fall Through */ | |
182 | default: | |
ad68076e | 183 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
184 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
185 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
186 | /* |
187 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
188 | * for setting word_size. |
189 | */ | |
190 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
191 | |
192 | /* EEPROM access above 16k is unsupported */ | |
193 | if (size > 14) | |
194 | size = 14; | |
bc7f75fa AK |
195 | nvm->word_size = 1 << size; |
196 | break; | |
197 | } | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
202 | /** | |
203 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
204 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
205 | **/ |
206 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
207 | { | |
208 | struct e1000_hw *hw = &adapter->hw; | |
209 | struct e1000_mac_info *mac = &hw->mac; | |
210 | struct e1000_mac_operations *func = &mac->ops; | |
23a2d1b2 DG |
211 | u32 swsm = 0; |
212 | u32 swsm2 = 0; | |
213 | bool force_clear_smbi = false; | |
bc7f75fa AK |
214 | |
215 | /* Set media type */ | |
216 | switch (adapter->pdev->device) { | |
217 | case E1000_DEV_ID_82571EB_FIBER: | |
218 | case E1000_DEV_ID_82572EI_FIBER: | |
219 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 220 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
221 | break; |
222 | case E1000_DEV_ID_82571EB_SERDES: | |
223 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
224 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
225 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 226 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
227 | break; |
228 | default: | |
318a94d6 | 229 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
230 | break; |
231 | } | |
232 | ||
233 | /* Set mta register count */ | |
234 | mac->mta_reg_count = 128; | |
235 | /* Set rar entry count */ | |
236 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
237 | /* Set if manageability features are enabled. */ | |
564ea9bb BA |
238 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) |
239 | ? true : false; | |
f464ba87 BA |
240 | /* Adaptive IFS supported */ |
241 | mac->adaptive_ifs = true; | |
bc7f75fa AK |
242 | |
243 | /* check for link */ | |
318a94d6 | 244 | switch (hw->phy.media_type) { |
bc7f75fa AK |
245 | case e1000_media_type_copper: |
246 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
247 | func->check_for_link = e1000e_check_for_copper_link; | |
248 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
249 | break; | |
250 | case e1000_media_type_fiber: | |
ad68076e BA |
251 | func->setup_physical_interface = |
252 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 253 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
254 | func->get_link_up_info = |
255 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
256 | break; |
257 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
258 | func->setup_physical_interface = |
259 | e1000_setup_fiber_serdes_link_82571; | |
c9523379 | 260 | func->check_for_link = e1000_check_for_serdes_link_82571; |
ad68076e BA |
261 | func->get_link_up_info = |
262 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
263 | break; |
264 | default: | |
265 | return -E1000_ERR_CONFIG; | |
266 | break; | |
267 | } | |
268 | ||
4662e82b | 269 | switch (hw->mac.type) { |
f4d2dd4c BA |
270 | case e1000_82573: |
271 | func->set_lan_id = e1000_set_lan_id_single_port; | |
272 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
273 | func->led_on = e1000e_led_on_generic; | |
274 | break; | |
4662e82b | 275 | case e1000_82574: |
8c81c9c3 | 276 | case e1000_82583: |
f4d2dd4c | 277 | func->set_lan_id = e1000_set_lan_id_single_port; |
4662e82b BA |
278 | func->check_mng_mode = e1000_check_mng_mode_82574; |
279 | func->led_on = e1000_led_on_82574; | |
280 | break; | |
281 | default: | |
282 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
283 | func->led_on = e1000e_led_on_generic; | |
284 | break; | |
285 | } | |
286 | ||
23a2d1b2 DG |
287 | /* |
288 | * Ensure that the inter-port SWSM.SMBI lock bit is clear before | |
289 | * first NVM or PHY acess. This should be done for single-port | |
290 | * devices, and for one port only on dual-port devices so that | |
291 | * for those devices we can still use the SMBI lock to synchronize | |
292 | * inter-port accesses to the PHY & NVM. | |
293 | */ | |
294 | switch (hw->mac.type) { | |
295 | case e1000_82571: | |
296 | case e1000_82572: | |
297 | swsm2 = er32(SWSM2); | |
298 | ||
299 | if (!(swsm2 & E1000_SWSM2_LOCK)) { | |
300 | /* Only do this for the first interface on this card */ | |
301 | ew32(SWSM2, | |
302 | swsm2 | E1000_SWSM2_LOCK); | |
303 | force_clear_smbi = true; | |
304 | } else | |
305 | force_clear_smbi = false; | |
306 | break; | |
307 | default: | |
308 | force_clear_smbi = true; | |
309 | break; | |
310 | } | |
311 | ||
312 | if (force_clear_smbi) { | |
313 | /* Make sure SWSM.SMBI is clear */ | |
314 | swsm = er32(SWSM); | |
315 | if (swsm & E1000_SWSM_SMBI) { | |
316 | /* This bit should not be set on a first interface, and | |
317 | * indicates that the bootagent or EFI code has | |
318 | * improperly left this bit enabled | |
319 | */ | |
3bb99fe2 | 320 | e_dbg("Please update your 82571 Bootagent\n"); |
23a2d1b2 DG |
321 | } |
322 | ew32(SWSM, swsm & ~E1000_SWSM_SMBI); | |
323 | } | |
324 | ||
325 | /* | |
326 | * Initialze device specific counter of SMBI acquisition | |
327 | * timeouts. | |
328 | */ | |
329 | hw->dev_spec.e82571.smb_counter = 0; | |
330 | ||
bc7f75fa AK |
331 | return 0; |
332 | } | |
333 | ||
69e3fd8c | 334 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
335 | { |
336 | struct e1000_hw *hw = &adapter->hw; | |
337 | static int global_quad_port_a; /* global port a indication */ | |
338 | struct pci_dev *pdev = adapter->pdev; | |
339 | u16 eeprom_data = 0; | |
340 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; | |
341 | s32 rc; | |
342 | ||
343 | rc = e1000_init_mac_params_82571(adapter); | |
344 | if (rc) | |
345 | return rc; | |
346 | ||
347 | rc = e1000_init_nvm_params_82571(hw); | |
348 | if (rc) | |
349 | return rc; | |
350 | ||
351 | rc = e1000_init_phy_params_82571(hw); | |
352 | if (rc) | |
353 | return rc; | |
354 | ||
355 | /* tag quad port adapters first, it's used below */ | |
356 | switch (pdev->device) { | |
357 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
358 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
359 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 360 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
361 | adapter->flags |= FLAG_IS_QUAD_PORT; |
362 | /* mark the first port */ | |
363 | if (global_quad_port_a == 0) | |
364 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
365 | /* Reset for multiple quad port adapters */ | |
366 | global_quad_port_a++; | |
367 | if (global_quad_port_a == 4) | |
368 | global_quad_port_a = 0; | |
369 | break; | |
370 | default: | |
371 | break; | |
372 | } | |
373 | ||
374 | switch (adapter->hw.mac.type) { | |
375 | case e1000_82571: | |
376 | /* these dual ports don't have WoL on port B at all */ | |
377 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
378 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
379 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
380 | (is_port_b)) | |
381 | adapter->flags &= ~FLAG_HAS_WOL; | |
382 | /* quad ports only support WoL on port A */ | |
383 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 384 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 385 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
386 | /* Does not support WoL on any port */ |
387 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
388 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa AK |
389 | break; |
390 | ||
391 | case e1000_82573: | |
392 | if (pdev->device == E1000_DEV_ID_82573L) { | |
e243455d BA |
393 | if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, |
394 | &eeprom_data) < 0) | |
395 | break; | |
2adc55c9 BA |
396 | if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) { |
397 | adapter->flags |= FLAG_HAS_JUMBO_FRAMES; | |
398 | adapter->max_hw_frame_size = DEFAULT_JUMBO; | |
399 | } | |
bc7f75fa AK |
400 | } |
401 | break; | |
402 | default: | |
403 | break; | |
404 | } | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | /** | |
410 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
411 | * @hw: pointer to the HW structure | |
412 | * | |
413 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
414 | * revision in the hardware structure. | |
415 | **/ | |
416 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
417 | { | |
418 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
419 | s32 ret_val; |
420 | u16 phy_id = 0; | |
bc7f75fa AK |
421 | |
422 | switch (hw->mac.type) { | |
423 | case e1000_82571: | |
424 | case e1000_82572: | |
ad68076e BA |
425 | /* |
426 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
427 | * In this case, we cannot access the PHY until the |
428 | * configuration is done. So we explicitly set the | |
ad68076e BA |
429 | * PHY ID. |
430 | */ | |
bc7f75fa AK |
431 | phy->id = IGP01E1000_I_PHY_ID; |
432 | break; | |
433 | case e1000_82573: | |
434 | return e1000e_get_phy_id(hw); | |
435 | break; | |
4662e82b | 436 | case e1000_82574: |
8c81c9c3 | 437 | case e1000_82583: |
4662e82b BA |
438 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
439 | if (ret_val) | |
440 | return ret_val; | |
441 | ||
442 | phy->id = (u32)(phy_id << 16); | |
443 | udelay(20); | |
444 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
445 | if (ret_val) | |
446 | return ret_val; | |
447 | ||
448 | phy->id |= (u32)(phy_id); | |
449 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
450 | break; | |
bc7f75fa AK |
451 | default: |
452 | return -E1000_ERR_PHY; | |
453 | break; | |
454 | } | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | /** | |
460 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
461 | * @hw: pointer to the HW structure | |
462 | * | |
463 | * Acquire the HW semaphore to access the PHY or NVM | |
464 | **/ | |
465 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
466 | { | |
467 | u32 swsm; | |
23a2d1b2 DG |
468 | s32 sw_timeout = hw->nvm.word_size + 1; |
469 | s32 fw_timeout = hw->nvm.word_size + 1; | |
bc7f75fa AK |
470 | s32 i = 0; |
471 | ||
23a2d1b2 DG |
472 | /* |
473 | * If we have timedout 3 times on trying to acquire | |
474 | * the inter-port SMBI semaphore, there is old code | |
475 | * operating on the other port, and it is not | |
476 | * releasing SMBI. Modify the number of times that | |
477 | * we try for the semaphore to interwork with this | |
478 | * older code. | |
479 | */ | |
480 | if (hw->dev_spec.e82571.smb_counter > 2) | |
481 | sw_timeout = 1; | |
482 | ||
483 | /* Get the SW semaphore */ | |
484 | while (i < sw_timeout) { | |
485 | swsm = er32(SWSM); | |
486 | if (!(swsm & E1000_SWSM_SMBI)) | |
487 | break; | |
488 | ||
489 | udelay(50); | |
490 | i++; | |
491 | } | |
492 | ||
493 | if (i == sw_timeout) { | |
3bb99fe2 | 494 | e_dbg("Driver can't access device - SMBI bit is set.\n"); |
23a2d1b2 DG |
495 | hw->dev_spec.e82571.smb_counter++; |
496 | } | |
bc7f75fa | 497 | /* Get the FW semaphore. */ |
23a2d1b2 | 498 | for (i = 0; i < fw_timeout; i++) { |
bc7f75fa AK |
499 | swsm = er32(SWSM); |
500 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
501 | ||
502 | /* Semaphore acquired if bit latched */ | |
503 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
504 | break; | |
505 | ||
506 | udelay(50); | |
507 | } | |
508 | ||
23a2d1b2 | 509 | if (i == fw_timeout) { |
bc7f75fa | 510 | /* Release semaphores */ |
23a2d1b2 | 511 | e1000_put_hw_semaphore_82571(hw); |
3bb99fe2 | 512 | e_dbg("Driver can't access the NVM\n"); |
bc7f75fa AK |
513 | return -E1000_ERR_NVM; |
514 | } | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
519 | /** | |
520 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
521 | * @hw: pointer to the HW structure | |
522 | * | |
523 | * Release hardware semaphore used to access the PHY or NVM | |
524 | **/ | |
525 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
526 | { | |
527 | u32 swsm; | |
528 | ||
529 | swsm = er32(SWSM); | |
23a2d1b2 | 530 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
bc7f75fa AK |
531 | ew32(SWSM, swsm); |
532 | } | |
533 | ||
534 | /** | |
535 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
536 | * @hw: pointer to the HW structure | |
537 | * | |
538 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
539 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
540 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
541 | * hardware semaphore. | |
542 | **/ | |
543 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
544 | { | |
545 | s32 ret_val; | |
546 | ||
547 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
548 | if (ret_val) | |
549 | return ret_val; | |
550 | ||
8c81c9c3 AD |
551 | switch (hw->mac.type) { |
552 | case e1000_82573: | |
553 | case e1000_82574: | |
554 | case e1000_82583: | |
555 | break; | |
556 | default: | |
bc7f75fa | 557 | ret_val = e1000e_acquire_nvm(hw); |
8c81c9c3 AD |
558 | break; |
559 | } | |
bc7f75fa AK |
560 | |
561 | if (ret_val) | |
562 | e1000_put_hw_semaphore_82571(hw); | |
563 | ||
564 | return ret_val; | |
565 | } | |
566 | ||
567 | /** | |
568 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
569 | * @hw: pointer to the HW structure | |
570 | * | |
571 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
572 | **/ | |
573 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
574 | { | |
575 | e1000e_release_nvm(hw); | |
576 | e1000_put_hw_semaphore_82571(hw); | |
577 | } | |
578 | ||
579 | /** | |
580 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
581 | * @hw: pointer to the HW structure | |
582 | * @offset: offset within the EEPROM to be written to | |
583 | * @words: number of words to write | |
584 | * @data: 16 bit word(s) to be written to the EEPROM | |
585 | * | |
586 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
587 | * | |
588 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 589 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
590 | **/ |
591 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
592 | u16 *data) | |
593 | { | |
594 | s32 ret_val; | |
595 | ||
596 | switch (hw->mac.type) { | |
597 | case e1000_82573: | |
4662e82b | 598 | case e1000_82574: |
8c81c9c3 | 599 | case e1000_82583: |
bc7f75fa AK |
600 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
601 | break; | |
602 | case e1000_82571: | |
603 | case e1000_82572: | |
604 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
605 | break; | |
606 | default: | |
607 | ret_val = -E1000_ERR_NVM; | |
608 | break; | |
609 | } | |
610 | ||
611 | return ret_val; | |
612 | } | |
613 | ||
614 | /** | |
615 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
616 | * @hw: pointer to the HW structure | |
617 | * | |
618 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
619 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
620 | * value to the EEPROM. | |
621 | **/ | |
622 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
623 | { | |
624 | u32 eecd; | |
625 | s32 ret_val; | |
626 | u16 i; | |
627 | ||
628 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
629 | if (ret_val) | |
630 | return ret_val; | |
631 | ||
ad68076e BA |
632 | /* |
633 | * If our nvm is an EEPROM, then we're done | |
634 | * otherwise, commit the checksum to the flash NVM. | |
635 | */ | |
bc7f75fa AK |
636 | if (hw->nvm.type != e1000_nvm_flash_hw) |
637 | return ret_val; | |
638 | ||
639 | /* Check for pending operations. */ | |
640 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
641 | msleep(1); | |
642 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
643 | break; | |
644 | } | |
645 | ||
646 | if (i == E1000_FLASH_UPDATES) | |
647 | return -E1000_ERR_NVM; | |
648 | ||
649 | /* Reset the firmware if using STM opcode. */ | |
650 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
651 | /* |
652 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
653 | * in two write cycles. |
654 | */ | |
655 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
656 | e1e_flush(); | |
657 | ew32(HICR, E1000_HICR_FW_RESET); | |
658 | } | |
659 | ||
660 | /* Commit the write to flash */ | |
661 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
662 | ew32(EECD, eecd); | |
663 | ||
664 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
665 | msleep(1); | |
666 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
667 | break; | |
668 | } | |
669 | ||
670 | if (i == E1000_FLASH_UPDATES) | |
671 | return -E1000_ERR_NVM; | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
676 | /** | |
677 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
678 | * @hw: pointer to the HW structure | |
679 | * | |
680 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
681 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
682 | **/ | |
683 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
684 | { | |
685 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
686 | e1000_fix_nvm_checksum_82571(hw); | |
687 | ||
688 | return e1000e_validate_nvm_checksum_generic(hw); | |
689 | } | |
690 | ||
691 | /** | |
692 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
693 | * @hw: pointer to the HW structure | |
694 | * @offset: offset within the EEPROM to be written to | |
695 | * @words: number of words to write | |
696 | * @data: 16 bit word(s) to be written to the EEPROM | |
697 | * | |
698 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
699 | * command has completed before trying to write the next word. After write | |
700 | * poll for completion. | |
701 | * | |
702 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 703 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
704 | **/ |
705 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
706 | u16 words, u16 *data) | |
707 | { | |
708 | struct e1000_nvm_info *nvm = &hw->nvm; | |
a708dd88 | 709 | u32 i, eewr = 0; |
bc7f75fa AK |
710 | s32 ret_val = 0; |
711 | ||
ad68076e BA |
712 | /* |
713 | * A check for invalid values: offset too large, too many words, | |
714 | * and not enough words. | |
715 | */ | |
bc7f75fa AK |
716 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
717 | (words == 0)) { | |
3bb99fe2 | 718 | e_dbg("nvm parameter(s) out of bounds\n"); |
bc7f75fa AK |
719 | return -E1000_ERR_NVM; |
720 | } | |
721 | ||
722 | for (i = 0; i < words; i++) { | |
723 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
724 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
725 | E1000_NVM_RW_REG_START; | |
726 | ||
727 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
728 | if (ret_val) | |
729 | break; | |
730 | ||
731 | ew32(EEWR, eewr); | |
732 | ||
733 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
734 | if (ret_val) | |
735 | break; | |
736 | } | |
737 | ||
738 | return ret_val; | |
739 | } | |
740 | ||
741 | /** | |
742 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
743 | * @hw: pointer to the HW structure | |
744 | * | |
745 | * Reads the management control register for the config done bit to be set. | |
746 | **/ | |
747 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
748 | { | |
749 | s32 timeout = PHY_CFG_TIMEOUT; | |
750 | ||
751 | while (timeout) { | |
752 | if (er32(EEMNGCTL) & | |
753 | E1000_NVM_CFG_DONE_PORT_0) | |
754 | break; | |
755 | msleep(1); | |
756 | timeout--; | |
757 | } | |
758 | if (!timeout) { | |
3bb99fe2 | 759 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
760 | return -E1000_ERR_RESET; |
761 | } | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | /** | |
767 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
768 | * @hw: pointer to the HW structure | |
564ea9bb | 769 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
770 | * |
771 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
772 | * this function also disables smart speed and vice versa. LPLU will not be | |
773 | * activated unless the device autonegotiation advertisement meets standards | |
774 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
775 | * pointer entry point only called by PHY setup routines. | |
776 | **/ | |
777 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
778 | { | |
779 | struct e1000_phy_info *phy = &hw->phy; | |
780 | s32 ret_val; | |
781 | u16 data; | |
782 | ||
783 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
784 | if (ret_val) | |
785 | return ret_val; | |
786 | ||
787 | if (active) { | |
788 | data |= IGP02E1000_PM_D0_LPLU; | |
789 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
790 | if (ret_val) | |
791 | return ret_val; | |
792 | ||
793 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
794 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
795 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
796 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
797 | if (ret_val) | |
798 | return ret_val; | |
799 | } else { | |
800 | data &= ~IGP02E1000_PM_D0_LPLU; | |
801 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
802 | /* |
803 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
804 | * during Dx states where the power conservation is most |
805 | * important. During driver activity we should enable | |
ad68076e BA |
806 | * SmartSpeed, so performance is maintained. |
807 | */ | |
bc7f75fa AK |
808 | if (phy->smart_speed == e1000_smart_speed_on) { |
809 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 810 | &data); |
bc7f75fa AK |
811 | if (ret_val) |
812 | return ret_val; | |
813 | ||
814 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
815 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 816 | data); |
bc7f75fa AK |
817 | if (ret_val) |
818 | return ret_val; | |
819 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
820 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 821 | &data); |
bc7f75fa AK |
822 | if (ret_val) |
823 | return ret_val; | |
824 | ||
825 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
826 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 827 | data); |
bc7f75fa AK |
828 | if (ret_val) |
829 | return ret_val; | |
830 | } | |
831 | } | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
836 | /** | |
837 | * e1000_reset_hw_82571 - Reset hardware | |
838 | * @hw: pointer to the HW structure | |
839 | * | |
fe401674 | 840 | * This resets the hardware into a known state. |
bc7f75fa AK |
841 | **/ |
842 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
843 | { | |
a708dd88 | 844 | u32 ctrl, extcnf_ctrl, ctrl_ext, icr; |
bc7f75fa AK |
845 | s32 ret_val; |
846 | u16 i = 0; | |
847 | ||
ad68076e BA |
848 | /* |
849 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
850 | * on the last TLP read/write transaction when MAC is reset. |
851 | */ | |
852 | ret_val = e1000e_disable_pcie_master(hw); | |
853 | if (ret_val) | |
3bb99fe2 | 854 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 855 | |
3bb99fe2 | 856 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
857 | ew32(IMC, 0xffffffff); |
858 | ||
859 | ew32(RCTL, 0); | |
860 | ew32(TCTL, E1000_TCTL_PSP); | |
861 | e1e_flush(); | |
862 | ||
863 | msleep(10); | |
864 | ||
ad68076e BA |
865 | /* |
866 | * Must acquire the MDIO ownership before MAC reset. | |
867 | * Ownership defaults to firmware after a reset. | |
868 | */ | |
8c81c9c3 AD |
869 | switch (hw->mac.type) { |
870 | case e1000_82573: | |
871 | case e1000_82574: | |
872 | case e1000_82583: | |
bc7f75fa AK |
873 | extcnf_ctrl = er32(EXTCNF_CTRL); |
874 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
875 | ||
876 | do { | |
877 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
878 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
879 | ||
880 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
881 | break; | |
882 | ||
883 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
884 | ||
885 | msleep(2); | |
886 | i++; | |
887 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
8c81c9c3 AD |
888 | break; |
889 | default: | |
890 | break; | |
bc7f75fa AK |
891 | } |
892 | ||
893 | ctrl = er32(CTRL); | |
894 | ||
3bb99fe2 | 895 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa AK |
896 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
897 | ||
898 | if (hw->nvm.type == e1000_nvm_flash_hw) { | |
899 | udelay(10); | |
900 | ctrl_ext = er32(CTRL_EXT); | |
901 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
902 | ew32(CTRL_EXT, ctrl_ext); | |
903 | e1e_flush(); | |
904 | } | |
905 | ||
906 | ret_val = e1000e_get_auto_rd_done(hw); | |
907 | if (ret_val) | |
908 | /* We don't want to continue accessing MAC registers. */ | |
909 | return ret_val; | |
910 | ||
ad68076e BA |
911 | /* |
912 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
913 | * Need to wait for Phy configuration completion before accessing |
914 | * NVM and Phy. | |
915 | */ | |
8c81c9c3 AD |
916 | |
917 | switch (hw->mac.type) { | |
918 | case e1000_82573: | |
919 | case e1000_82574: | |
920 | case e1000_82583: | |
bc7f75fa | 921 | msleep(25); |
8c81c9c3 AD |
922 | break; |
923 | default: | |
924 | break; | |
925 | } | |
bc7f75fa AK |
926 | |
927 | /* Clear any pending interrupt events. */ | |
928 | ew32(IMC, 0xffffffff); | |
929 | icr = er32(ICR); | |
930 | ||
608f8a0d BA |
931 | /* Install any alternate MAC address into RAR0 */ |
932 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
933 | if (ret_val) | |
934 | return ret_val; | |
935 | ||
936 | e1000e_set_laa_state_82571(hw, true); | |
93ca1610 | 937 | |
c9523379 | 938 | /* Reinitialize the 82571 serdes link state machine */ |
939 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
940 | hw->mac.serdes_link_state = e1000_serdes_link_down; | |
941 | ||
bc7f75fa AK |
942 | return 0; |
943 | } | |
944 | ||
945 | /** | |
946 | * e1000_init_hw_82571 - Initialize hardware | |
947 | * @hw: pointer to the HW structure | |
948 | * | |
949 | * This inits the hardware readying it for operation. | |
950 | **/ | |
951 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
952 | { | |
953 | struct e1000_mac_info *mac = &hw->mac; | |
954 | u32 reg_data; | |
955 | s32 ret_val; | |
a708dd88 | 956 | u16 i, rar_count = mac->rar_entry_count; |
bc7f75fa AK |
957 | |
958 | e1000_initialize_hw_bits_82571(hw); | |
959 | ||
960 | /* Initialize identification LED */ | |
961 | ret_val = e1000e_id_led_init(hw); | |
de39b752 | 962 | if (ret_val) |
3bb99fe2 | 963 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 964 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
965 | |
966 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 967 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 968 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
969 | |
970 | /* Setup the receive address. */ | |
ad68076e BA |
971 | /* |
972 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
973 | * 82571, we must reserve a RAR for it to work around an issue where |
974 | * resetting one port will reload the MAC on the other port. | |
975 | */ | |
976 | if (e1000e_get_laa_state_82571(hw)) | |
977 | rar_count--; | |
978 | e1000e_init_rx_addrs(hw, rar_count); | |
979 | ||
980 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 981 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
982 | for (i = 0; i < mac->mta_reg_count; i++) |
983 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
984 | ||
985 | /* Setup link and flow control */ | |
986 | ret_val = e1000_setup_link_82571(hw); | |
987 | ||
988 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 989 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
990 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
991 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
992 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 993 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
994 | |
995 | /* ...for both queues. */ | |
8c81c9c3 AD |
996 | switch (mac->type) { |
997 | case e1000_82573: | |
998 | case e1000_82574: | |
999 | case e1000_82583: | |
1000 | e1000e_enable_tx_pkt_filtering(hw); | |
1001 | reg_data = er32(GCR); | |
1002 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
1003 | ew32(GCR, reg_data); | |
1004 | break; | |
1005 | default: | |
e9ec2c0f | 1006 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
1007 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1008 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1009 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1010 | ew32(TXDCTL(1), reg_data); |
8c81c9c3 | 1011 | break; |
bc7f75fa AK |
1012 | } |
1013 | ||
ad68076e BA |
1014 | /* |
1015 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1016 | * important that we do this after we have tried to establish link |
1017 | * because the symbol error count will increment wildly if there | |
1018 | * is no link. | |
1019 | */ | |
1020 | e1000_clear_hw_cntrs_82571(hw); | |
1021 | ||
1022 | return ret_val; | |
1023 | } | |
1024 | ||
1025 | /** | |
1026 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
1027 | * @hw: pointer to the HW structure | |
1028 | * | |
1029 | * Initializes required hardware-dependent bits needed for normal operation. | |
1030 | **/ | |
1031 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
1032 | { | |
1033 | u32 reg; | |
1034 | ||
1035 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1036 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1037 | reg |= (1 << 22); |
e9ec2c0f | 1038 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1039 | |
1040 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1041 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1042 | reg |= (1 << 22); |
e9ec2c0f | 1043 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1044 | |
1045 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1046 | reg = er32(TARC(0)); |
bc7f75fa AK |
1047 | reg &= ~(0xF << 27); /* 30:27 */ |
1048 | switch (hw->mac.type) { | |
1049 | case e1000_82571: | |
1050 | case e1000_82572: | |
1051 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
1052 | break; | |
1053 | default: | |
1054 | break; | |
1055 | } | |
e9ec2c0f | 1056 | ew32(TARC(0), reg); |
bc7f75fa AK |
1057 | |
1058 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1059 | reg = er32(TARC(1)); |
bc7f75fa AK |
1060 | switch (hw->mac.type) { |
1061 | case e1000_82571: | |
1062 | case e1000_82572: | |
1063 | reg &= ~((1 << 29) | (1 << 30)); | |
1064 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
1065 | if (er32(TCTL) & E1000_TCTL_MULR) | |
1066 | reg &= ~(1 << 28); | |
1067 | else | |
1068 | reg |= (1 << 28); | |
e9ec2c0f | 1069 | ew32(TARC(1), reg); |
bc7f75fa AK |
1070 | break; |
1071 | default: | |
1072 | break; | |
1073 | } | |
1074 | ||
1075 | /* Device Control */ | |
8c81c9c3 AD |
1076 | switch (hw->mac.type) { |
1077 | case e1000_82573: | |
1078 | case e1000_82574: | |
1079 | case e1000_82583: | |
bc7f75fa AK |
1080 | reg = er32(CTRL); |
1081 | reg &= ~(1 << 29); | |
1082 | ew32(CTRL, reg); | |
8c81c9c3 AD |
1083 | break; |
1084 | default: | |
1085 | break; | |
bc7f75fa AK |
1086 | } |
1087 | ||
1088 | /* Extended Device Control */ | |
8c81c9c3 AD |
1089 | switch (hw->mac.type) { |
1090 | case e1000_82573: | |
1091 | case e1000_82574: | |
1092 | case e1000_82583: | |
bc7f75fa AK |
1093 | reg = er32(CTRL_EXT); |
1094 | reg &= ~(1 << 23); | |
1095 | reg |= (1 << 22); | |
1096 | ew32(CTRL_EXT, reg); | |
8c81c9c3 AD |
1097 | break; |
1098 | default: | |
1099 | break; | |
bc7f75fa | 1100 | } |
4662e82b | 1101 | |
6ea7ae1d AD |
1102 | if (hw->mac.type == e1000_82571) { |
1103 | reg = er32(PBA_ECC); | |
1104 | reg |= E1000_PBA_ECC_CORR_EN; | |
1105 | ew32(PBA_ECC, reg); | |
1106 | } | |
5df3f0ea | 1107 | /* |
1108 | * Workaround for hardware errata. | |
1109 | * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 | |
1110 | */ | |
1111 | ||
1112 | if ((hw->mac.type == e1000_82571) || | |
1113 | (hw->mac.type == e1000_82572)) { | |
1114 | reg = er32(CTRL_EXT); | |
1115 | reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; | |
1116 | ew32(CTRL_EXT, reg); | |
1117 | } | |
1118 | ||
6ea7ae1d | 1119 | |
78272bba | 1120 | /* PCI-Ex Control Registers */ |
8c81c9c3 AD |
1121 | switch (hw->mac.type) { |
1122 | case e1000_82574: | |
1123 | case e1000_82583: | |
4662e82b BA |
1124 | reg = er32(GCR); |
1125 | reg |= (1 << 22); | |
1126 | ew32(GCR, reg); | |
78272bba | 1127 | |
84efb7b9 BA |
1128 | /* |
1129 | * Workaround for hardware errata. | |
1130 | * apply workaround for hardware errata documented in errata | |
1131 | * docs Fixes issue where some error prone or unreliable PCIe | |
1132 | * completions are occurring, particularly with ASPM enabled. | |
1133 | * Without fix, issue can cause tx timeouts. | |
1134 | */ | |
78272bba JB |
1135 | reg = er32(GCR2); |
1136 | reg |= 1; | |
1137 | ew32(GCR2, reg); | |
8c81c9c3 AD |
1138 | break; |
1139 | default: | |
1140 | break; | |
4662e82b BA |
1141 | } |
1142 | ||
1143 | return; | |
bc7f75fa AK |
1144 | } |
1145 | ||
1146 | /** | |
caaddaf8 | 1147 | * e1000_clear_vfta_82571 - Clear VLAN filter table |
bc7f75fa AK |
1148 | * @hw: pointer to the HW structure |
1149 | * | |
1150 | * Clears the register array which contains the VLAN filter table by | |
1151 | * setting all the values to 0. | |
1152 | **/ | |
caaddaf8 | 1153 | static void e1000_clear_vfta_82571(struct e1000_hw *hw) |
bc7f75fa AK |
1154 | { |
1155 | u32 offset; | |
1156 | u32 vfta_value = 0; | |
1157 | u32 vfta_offset = 0; | |
1158 | u32 vfta_bit_in_reg = 0; | |
1159 | ||
8c81c9c3 AD |
1160 | switch (hw->mac.type) { |
1161 | case e1000_82573: | |
1162 | case e1000_82574: | |
1163 | case e1000_82583: | |
bc7f75fa | 1164 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1165 | /* |
1166 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1167 | * a single VLAN ID. The following operations |
1168 | * determine which 32b entry (i.e. offset) into the | |
1169 | * array we want to set the VLAN ID (i.e. bit) of | |
1170 | * the manageability unit. | |
1171 | */ | |
1172 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1173 | E1000_VFTA_ENTRY_SHIFT) & | |
1174 | E1000_VFTA_ENTRY_MASK; | |
1175 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1176 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1177 | } | |
8c81c9c3 AD |
1178 | break; |
1179 | default: | |
1180 | break; | |
bc7f75fa AK |
1181 | } |
1182 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1183 | /* |
1184 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1185 | * manageability VLAN ID, then clear all bits except that of |
1186 | * the manageability unit. | |
1187 | */ | |
1188 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1189 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1190 | e1e_flush(); | |
1191 | } | |
1192 | } | |
1193 | ||
4662e82b BA |
1194 | /** |
1195 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1196 | * @hw: pointer to the HW structure | |
1197 | * | |
1198 | * Reads the NVM Initialization Control Word 2 and returns true | |
1199 | * (>0) if any manageability is enabled, else false (0). | |
1200 | **/ | |
1201 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1202 | { | |
1203 | u16 data; | |
1204 | ||
1205 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1206 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1207 | } | |
1208 | ||
1209 | /** | |
1210 | * e1000_led_on_82574 - Turn LED on | |
1211 | * @hw: pointer to the HW structure | |
1212 | * | |
1213 | * Turn LED on. | |
1214 | **/ | |
1215 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1216 | { | |
1217 | u32 ctrl; | |
1218 | u32 i; | |
1219 | ||
1220 | ctrl = hw->mac.ledctl_mode2; | |
1221 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1222 | /* | |
1223 | * If no link, then turn LED on by setting the invert bit | |
1224 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1225 | */ | |
1226 | for (i = 0; i < 4; i++) | |
1227 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1228 | E1000_LEDCTL_MODE_LED_ON) | |
1229 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1230 | } | |
1231 | ew32(LEDCTL, ctrl); | |
1232 | ||
1233 | return 0; | |
1234 | } | |
1235 | ||
bc7f75fa AK |
1236 | /** |
1237 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1238 | * @hw: pointer to the HW structure | |
1239 | * | |
1240 | * Determines which flow control settings to use, then configures flow | |
1241 | * control. Calls the appropriate media-specific link configuration | |
1242 | * function. Assuming the adapter has a valid link partner, a valid link | |
1243 | * should be established. Assumes the hardware has previously been reset | |
1244 | * and the transmitter and receiver are not enabled. | |
1245 | **/ | |
1246 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1247 | { | |
ad68076e BA |
1248 | /* |
1249 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1250 | * the default flow control setting, so we explicitly |
1251 | * set it to full. | |
1252 | */ | |
8c81c9c3 AD |
1253 | switch (hw->mac.type) { |
1254 | case e1000_82573: | |
1255 | case e1000_82574: | |
1256 | case e1000_82583: | |
1257 | if (hw->fc.requested_mode == e1000_fc_default) | |
1258 | hw->fc.requested_mode = e1000_fc_full; | |
1259 | break; | |
1260 | default: | |
1261 | break; | |
1262 | } | |
bc7f75fa AK |
1263 | |
1264 | return e1000e_setup_link(hw); | |
1265 | } | |
1266 | ||
1267 | /** | |
1268 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1269 | * @hw: pointer to the HW structure | |
1270 | * | |
1271 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1272 | * for link, once link is established calls to configure collision distance | |
1273 | * and flow control are called. | |
1274 | **/ | |
1275 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1276 | { | |
1277 | u32 ctrl; | |
bc7f75fa AK |
1278 | s32 ret_val; |
1279 | ||
1280 | ctrl = er32(CTRL); | |
1281 | ctrl |= E1000_CTRL_SLU; | |
1282 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1283 | ew32(CTRL, ctrl); | |
1284 | ||
1285 | switch (hw->phy.type) { | |
1286 | case e1000_phy_m88: | |
4662e82b | 1287 | case e1000_phy_bm: |
bc7f75fa AK |
1288 | ret_val = e1000e_copper_link_setup_m88(hw); |
1289 | break; | |
1290 | case e1000_phy_igp_2: | |
1291 | ret_val = e1000e_copper_link_setup_igp(hw); | |
bc7f75fa AK |
1292 | break; |
1293 | default: | |
1294 | return -E1000_ERR_PHY; | |
1295 | break; | |
1296 | } | |
1297 | ||
1298 | if (ret_val) | |
1299 | return ret_val; | |
1300 | ||
1301 | ret_val = e1000e_setup_copper_link(hw); | |
1302 | ||
1303 | return ret_val; | |
1304 | } | |
1305 | ||
1306 | /** | |
1307 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1308 | * @hw: pointer to the HW structure | |
1309 | * | |
1310 | * Configures collision distance and flow control for fiber and serdes links. | |
1311 | * Upon successful setup, poll for link. | |
1312 | **/ | |
1313 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1314 | { | |
1315 | switch (hw->mac.type) { | |
1316 | case e1000_82571: | |
1317 | case e1000_82572: | |
ad68076e BA |
1318 | /* |
1319 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1320 | * of reset to take the adapter out of that mode. So we |
1321 | * have to explicitly take the adapter out of loopback | |
489815ce | 1322 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1323 | * if another tool failed to take it out of loopback mode. |
1324 | */ | |
ad68076e | 1325 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1326 | break; |
1327 | default: | |
1328 | break; | |
1329 | } | |
1330 | ||
1331 | return e1000e_setup_fiber_serdes_link(hw); | |
1332 | } | |
1333 | ||
c9523379 | 1334 | /** |
1335 | * e1000_check_for_serdes_link_82571 - Check for link (Serdes) | |
1336 | * @hw: pointer to the HW structure | |
1337 | * | |
1a40d5c1 BA |
1338 | * Reports the link state as up or down. |
1339 | * | |
1340 | * If autonegotiation is supported by the link partner, the link state is | |
1341 | * determined by the result of autonegotiation. This is the most likely case. | |
1342 | * If autonegotiation is not supported by the link partner, and the link | |
1343 | * has a valid signal, force the link up. | |
1344 | * | |
1345 | * The link state is represented internally here by 4 states: | |
1346 | * | |
1347 | * 1) down | |
1348 | * 2) autoneg_progress | |
3ad2f3fb | 1349 | * 3) autoneg_complete (the link successfully autonegotiated) |
1a40d5c1 BA |
1350 | * 4) forced_up (the link has been forced up, it did not autonegotiate) |
1351 | * | |
c9523379 | 1352 | **/ |
f6370117 | 1353 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
c9523379 | 1354 | { |
1355 | struct e1000_mac_info *mac = &hw->mac; | |
1356 | u32 rxcw; | |
1357 | u32 ctrl; | |
1358 | u32 status; | |
1359 | s32 ret_val = 0; | |
1360 | ||
1361 | ctrl = er32(CTRL); | |
1362 | status = er32(STATUS); | |
1363 | rxcw = er32(RXCW); | |
1364 | ||
1365 | if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { | |
1366 | ||
1367 | /* Receiver is synchronized with no invalid bits. */ | |
1368 | switch (mac->serdes_link_state) { | |
1369 | case e1000_serdes_link_autoneg_complete: | |
1370 | if (!(status & E1000_STATUS_LU)) { | |
1371 | /* | |
1372 | * We have lost link, retry autoneg before | |
1373 | * reporting link failure | |
1374 | */ | |
1375 | mac->serdes_link_state = | |
1376 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1377 | mac->serdes_has_link = false; |
3bb99fe2 | 1378 | e_dbg("AN_UP -> AN_PROG\n"); |
c9523379 | 1379 | } |
1380 | break; | |
1381 | ||
1382 | case e1000_serdes_link_forced_up: | |
1383 | /* | |
1384 | * If we are receiving /C/ ordered sets, re-enable | |
1385 | * auto-negotiation in the TXCW register and disable | |
1386 | * forced link in the Device Control register in an | |
1387 | * attempt to auto-negotiate with our link partner. | |
1388 | */ | |
1389 | if (rxcw & E1000_RXCW_C) { | |
1390 | /* Enable autoneg, and unforce link up */ | |
1391 | ew32(TXCW, mac->txcw); | |
1a40d5c1 | 1392 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1393 | mac->serdes_link_state = |
1394 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1395 | mac->serdes_has_link = false; |
3bb99fe2 | 1396 | e_dbg("FORCED_UP -> AN_PROG\n"); |
c9523379 | 1397 | } |
1398 | break; | |
1399 | ||
1400 | case e1000_serdes_link_autoneg_progress: | |
1a40d5c1 BA |
1401 | if (rxcw & E1000_RXCW_C) { |
1402 | /* | |
1403 | * We received /C/ ordered sets, meaning the | |
1404 | * link partner has autonegotiated, and we can | |
1405 | * trust the Link Up (LU) status bit. | |
1406 | */ | |
1407 | if (status & E1000_STATUS_LU) { | |
1408 | mac->serdes_link_state = | |
1409 | e1000_serdes_link_autoneg_complete; | |
1410 | e_dbg("AN_PROG -> AN_UP\n"); | |
1411 | mac->serdes_has_link = true; | |
1412 | } else { | |
1413 | /* Autoneg completed, but failed. */ | |
1414 | mac->serdes_link_state = | |
1415 | e1000_serdes_link_down; | |
1416 | e_dbg("AN_PROG -> DOWN\n"); | |
1417 | } | |
c9523379 | 1418 | } else { |
1419 | /* | |
1a40d5c1 BA |
1420 | * The link partner did not autoneg. |
1421 | * Force link up and full duplex, and change | |
1422 | * state to forced. | |
c9523379 | 1423 | */ |
1a40d5c1 | 1424 | ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
c9523379 | 1425 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
1426 | ew32(CTRL, ctrl); | |
1427 | ||
1428 | /* Configure Flow Control after link up. */ | |
1a40d5c1 | 1429 | ret_val = e1000e_config_fc_after_link_up(hw); |
c9523379 | 1430 | if (ret_val) { |
3bb99fe2 | 1431 | e_dbg("Error config flow control\n"); |
c9523379 | 1432 | break; |
1433 | } | |
1434 | mac->serdes_link_state = | |
1435 | e1000_serdes_link_forced_up; | |
1a40d5c1 | 1436 | mac->serdes_has_link = true; |
3bb99fe2 | 1437 | e_dbg("AN_PROG -> FORCED_UP\n"); |
c9523379 | 1438 | } |
c9523379 | 1439 | break; |
1440 | ||
1441 | case e1000_serdes_link_down: | |
1442 | default: | |
1a40d5c1 BA |
1443 | /* |
1444 | * The link was down but the receiver has now gained | |
c9523379 | 1445 | * valid sync, so lets see if we can bring the link |
1a40d5c1 BA |
1446 | * up. |
1447 | */ | |
c9523379 | 1448 | ew32(TXCW, mac->txcw); |
1a40d5c1 | 1449 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1450 | mac->serdes_link_state = |
1451 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1452 | e_dbg("DOWN -> AN_PROG\n"); |
c9523379 | 1453 | break; |
1454 | } | |
1455 | } else { | |
1456 | if (!(rxcw & E1000_RXCW_SYNCH)) { | |
1457 | mac->serdes_has_link = false; | |
1458 | mac->serdes_link_state = e1000_serdes_link_down; | |
3bb99fe2 | 1459 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1460 | } else { |
1461 | /* | |
1a40d5c1 BA |
1462 | * We have sync, and can tolerate one invalid (IV) |
1463 | * codeword before declaring link down, so reread | |
1464 | * to look again. | |
c9523379 | 1465 | */ |
1466 | udelay(10); | |
1467 | rxcw = er32(RXCW); | |
1468 | if (rxcw & E1000_RXCW_IV) { | |
1469 | mac->serdes_link_state = e1000_serdes_link_down; | |
1470 | mac->serdes_has_link = false; | |
3bb99fe2 | 1471 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1472 | } |
1473 | } | |
1474 | } | |
1475 | ||
1476 | return ret_val; | |
1477 | } | |
1478 | ||
bc7f75fa AK |
1479 | /** |
1480 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1481 | * @hw: pointer to the HW structure | |
1482 | * @data: pointer to the NVM (EEPROM) | |
1483 | * | |
1484 | * Read the EEPROM for the current default LED configuration. If the | |
1485 | * LED configuration is not valid, set to a valid LED configuration. | |
1486 | **/ | |
1487 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1488 | { | |
1489 | s32 ret_val; | |
1490 | ||
1491 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1492 | if (ret_val) { | |
3bb99fe2 | 1493 | e_dbg("NVM Read Error\n"); |
bc7f75fa AK |
1494 | return ret_val; |
1495 | } | |
1496 | ||
8c81c9c3 AD |
1497 | switch (hw->mac.type) { |
1498 | case e1000_82573: | |
1499 | case e1000_82574: | |
1500 | case e1000_82583: | |
1501 | if (*data == ID_LED_RESERVED_F746) | |
1502 | *data = ID_LED_DEFAULT_82573; | |
1503 | break; | |
1504 | default: | |
1505 | if (*data == ID_LED_RESERVED_0000 || | |
1506 | *data == ID_LED_RESERVED_FFFF) | |
1507 | *data = ID_LED_DEFAULT; | |
1508 | break; | |
1509 | } | |
bc7f75fa AK |
1510 | |
1511 | return 0; | |
1512 | } | |
1513 | ||
1514 | /** | |
1515 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1516 | * @hw: pointer to the HW structure | |
1517 | * | |
489815ce | 1518 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1519 | **/ |
1520 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1521 | { | |
1522 | if (hw->mac.type != e1000_82571) | |
564ea9bb | 1523 | return false; |
bc7f75fa AK |
1524 | |
1525 | return hw->dev_spec.e82571.laa_is_present; | |
1526 | } | |
1527 | ||
1528 | /** | |
1529 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1530 | * @hw: pointer to the HW structure | |
1531 | * @state: enable/disable locally administered address | |
1532 | * | |
5ff5b664 | 1533 | * Enable/Disable the current locally administered address state. |
bc7f75fa AK |
1534 | **/ |
1535 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1536 | { | |
1537 | if (hw->mac.type != e1000_82571) | |
1538 | return; | |
1539 | ||
1540 | hw->dev_spec.e82571.laa_is_present = state; | |
1541 | ||
1542 | /* If workaround is activated... */ | |
1543 | if (state) | |
ad68076e BA |
1544 | /* |
1545 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1546 | * between the time RAR[0] gets clobbered and the time it |
1547 | * gets fixed, the actual LAA is in one of the RARs and no | |
1548 | * incoming packets directed to this port are dropped. | |
1549 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1550 | */ | |
1551 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1552 | } | |
1553 | ||
1554 | /** | |
1555 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1556 | * @hw: pointer to the HW structure | |
1557 | * | |
1558 | * Verifies that the EEPROM has completed the update. After updating the | |
1559 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1560 | * the checksum fix is not implemented, we need to set the bit and update | |
1561 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1562 | * we need to return bad checksum. | |
1563 | **/ | |
1564 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1565 | { | |
1566 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1567 | s32 ret_val; | |
1568 | u16 data; | |
1569 | ||
1570 | if (nvm->type != e1000_nvm_flash_hw) | |
1571 | return 0; | |
1572 | ||
ad68076e BA |
1573 | /* |
1574 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1575 | * 10h-12h. Checksum may need to be fixed. |
1576 | */ | |
1577 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1578 | if (ret_val) | |
1579 | return ret_val; | |
1580 | ||
1581 | if (!(data & 0x10)) { | |
ad68076e BA |
1582 | /* |
1583 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1584 | * when the checksum has already been fixed. If |
1585 | * the checksum is still wrong and this bit is a | |
1586 | * 1, we need to return bad checksum. Otherwise, | |
1587 | * we need to set this bit to a 1 and update the | |
1588 | * checksum. | |
1589 | */ | |
1590 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1591 | if (ret_val) | |
1592 | return ret_val; | |
1593 | ||
1594 | if (!(data & 0x8000)) { | |
1595 | data |= 0x8000; | |
1596 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1597 | if (ret_val) | |
1598 | return ret_val; | |
1599 | ret_val = e1000e_update_nvm_checksum(hw); | |
1600 | } | |
1601 | } | |
1602 | ||
1603 | return 0; | |
1604 | } | |
1605 | ||
608f8a0d BA |
1606 | /** |
1607 | * e1000_read_mac_addr_82571 - Read device MAC address | |
1608 | * @hw: pointer to the HW structure | |
1609 | **/ | |
1610 | static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) | |
1611 | { | |
1612 | s32 ret_val = 0; | |
1613 | ||
1614 | /* | |
1615 | * If there's an alternate MAC address place it in RAR0 | |
1616 | * so that it will override the Si installed default perm | |
1617 | * address. | |
1618 | */ | |
1619 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1620 | if (ret_val) | |
1621 | goto out; | |
1622 | ||
1623 | ret_val = e1000_read_mac_addr_generic(hw); | |
1624 | ||
1625 | out: | |
1626 | return ret_val; | |
1627 | } | |
1628 | ||
17f208de BA |
1629 | /** |
1630 | * e1000_power_down_phy_copper_82571 - Remove link during PHY power down | |
1631 | * @hw: pointer to the HW structure | |
1632 | * | |
1633 | * In the case of a PHY power down to save power, or to turn off link during a | |
1634 | * driver unload, or wake on lan is not enabled, remove the link. | |
1635 | **/ | |
1636 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) | |
1637 | { | |
1638 | struct e1000_phy_info *phy = &hw->phy; | |
1639 | struct e1000_mac_info *mac = &hw->mac; | |
1640 | ||
1641 | if (!(phy->ops.check_reset_block)) | |
1642 | return; | |
1643 | ||
1644 | /* If the management interface is not enabled, then power down */ | |
1645 | if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) | |
1646 | e1000_power_down_phy_copper(hw); | |
1647 | ||
1648 | return; | |
1649 | } | |
1650 | ||
bc7f75fa AK |
1651 | /** |
1652 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1653 | * @hw: pointer to the HW structure | |
1654 | * | |
1655 | * Clears the hardware counters by reading the counter registers. | |
1656 | **/ | |
1657 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1658 | { | |
bc7f75fa AK |
1659 | e1000e_clear_hw_cntrs_base(hw); |
1660 | ||
99673d9b BA |
1661 | er32(PRC64); |
1662 | er32(PRC127); | |
1663 | er32(PRC255); | |
1664 | er32(PRC511); | |
1665 | er32(PRC1023); | |
1666 | er32(PRC1522); | |
1667 | er32(PTC64); | |
1668 | er32(PTC127); | |
1669 | er32(PTC255); | |
1670 | er32(PTC511); | |
1671 | er32(PTC1023); | |
1672 | er32(PTC1522); | |
1673 | ||
1674 | er32(ALGNERRC); | |
1675 | er32(RXERRC); | |
1676 | er32(TNCRS); | |
1677 | er32(CEXTERR); | |
1678 | er32(TSCTC); | |
1679 | er32(TSCTFC); | |
1680 | ||
1681 | er32(MGTPRC); | |
1682 | er32(MGTPDC); | |
1683 | er32(MGTPTC); | |
1684 | ||
1685 | er32(IAC); | |
1686 | er32(ICRXOC); | |
1687 | ||
1688 | er32(ICRXPTC); | |
1689 | er32(ICRXATC); | |
1690 | er32(ICTXPTC); | |
1691 | er32(ICTXATC); | |
1692 | er32(ICTXQEC); | |
1693 | er32(ICTXQMTC); | |
1694 | er32(ICRXDMTC); | |
bc7f75fa AK |
1695 | } |
1696 | ||
1697 | static struct e1000_mac_operations e82571_mac_ops = { | |
4662e82b | 1698 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa | 1699 | /* .check_for_link: media type dependent */ |
a4f58f54 | 1700 | .id_led_init = e1000e_id_led_init, |
bc7f75fa AK |
1701 | .cleanup_led = e1000e_cleanup_led_generic, |
1702 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1703 | .get_bus_info = e1000e_get_bus_info_pcie, | |
f4d2dd4c | 1704 | .set_lan_id = e1000_set_lan_id_multi_port_pcie, |
bc7f75fa | 1705 | /* .get_link_up_info: media type dependent */ |
4662e82b | 1706 | /* .led_on: mac type dependent */ |
bc7f75fa | 1707 | .led_off = e1000e_led_off_generic, |
ab8932f3 | 1708 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
caaddaf8 BA |
1709 | .write_vfta = e1000_write_vfta_generic, |
1710 | .clear_vfta = e1000_clear_vfta_82571, | |
bc7f75fa AK |
1711 | .reset_hw = e1000_reset_hw_82571, |
1712 | .init_hw = e1000_init_hw_82571, | |
1713 | .setup_link = e1000_setup_link_82571, | |
1714 | /* .setup_physical_interface: media type dependent */ | |
a4f58f54 | 1715 | .setup_led = e1000e_setup_led_generic, |
608f8a0d | 1716 | .read_mac_addr = e1000_read_mac_addr_82571, |
bc7f75fa AK |
1717 | }; |
1718 | ||
1719 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
94d8186a | 1720 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1721 | .check_polarity = e1000_check_polarity_igp, |
bc7f75fa | 1722 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1723 | .commit = NULL, |
bc7f75fa AK |
1724 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
1725 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1726 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
94d8186a BA |
1727 | .get_info = e1000e_get_phy_info_igp, |
1728 | .read_reg = e1000e_read_phy_reg_igp, | |
1729 | .release = e1000_put_hw_semaphore_82571, | |
1730 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1731 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1732 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1733 | .write_reg = e1000e_write_phy_reg_igp, |
75eb0fad | 1734 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1735 | }; |
1736 | ||
1737 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
94d8186a | 1738 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1739 | .check_polarity = e1000_check_polarity_m88, |
bc7f75fa | 1740 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1741 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1742 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1743 | .get_cfg_done = e1000e_get_cfg_done, | |
1744 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1745 | .get_info = e1000e_get_phy_info_m88, |
1746 | .read_reg = e1000e_read_phy_reg_m88, | |
1747 | .release = e1000_put_hw_semaphore_82571, | |
1748 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1749 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1750 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1751 | .write_reg = e1000e_write_phy_reg_m88, |
75eb0fad | 1752 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1753 | }; |
1754 | ||
4662e82b | 1755 | static struct e1000_phy_operations e82_phy_ops_bm = { |
94d8186a | 1756 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1757 | .check_polarity = e1000_check_polarity_m88, |
4662e82b | 1758 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1759 | .commit = e1000e_phy_sw_reset, |
4662e82b BA |
1760 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1761 | .get_cfg_done = e1000e_get_cfg_done, | |
1762 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1763 | .get_info = e1000e_get_phy_info_m88, |
1764 | .read_reg = e1000e_read_phy_reg_bm2, | |
1765 | .release = e1000_put_hw_semaphore_82571, | |
1766 | .reset = e1000e_phy_hw_reset_generic, | |
4662e82b BA |
1767 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1768 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1769 | .write_reg = e1000e_write_phy_reg_bm2, |
75eb0fad | 1770 | .cfg_on_link_up = NULL, |
4662e82b BA |
1771 | }; |
1772 | ||
bc7f75fa | 1773 | static struct e1000_nvm_operations e82571_nvm_ops = { |
94d8186a BA |
1774 | .acquire = e1000_acquire_nvm_82571, |
1775 | .read = e1000e_read_nvm_eerd, | |
1776 | .release = e1000_release_nvm_82571, | |
1777 | .update = e1000_update_nvm_checksum_82571, | |
bc7f75fa | 1778 | .valid_led_default = e1000_valid_led_default_82571, |
94d8186a BA |
1779 | .validate = e1000_validate_nvm_checksum_82571, |
1780 | .write = e1000_write_nvm_82571, | |
bc7f75fa AK |
1781 | }; |
1782 | ||
1783 | struct e1000_info e1000_82571_info = { | |
1784 | .mac = e1000_82571, | |
1785 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1786 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1787 | | FLAG_HAS_WOL |
1788 | | FLAG_APME_IN_CTRL3 | |
1789 | | FLAG_RX_CSUM_ENABLED | |
1790 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1791 | | FLAG_HAS_SMART_POWER_DOWN |
1792 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1793 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1794 | | FLAG_APME_CHECK_PORT_B, | |
1795 | .pba = 38, | |
2adc55c9 | 1796 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1797 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1798 | .mac_ops = &e82571_mac_ops, |
1799 | .phy_ops = &e82_phy_ops_igp, | |
1800 | .nvm_ops = &e82571_nvm_ops, | |
1801 | }; | |
1802 | ||
1803 | struct e1000_info e1000_82572_info = { | |
1804 | .mac = e1000_82572, | |
1805 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1806 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1807 | | FLAG_HAS_WOL |
1808 | | FLAG_APME_IN_CTRL3 | |
1809 | | FLAG_RX_CSUM_ENABLED | |
1810 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1811 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
1812 | .pba = 38, | |
2adc55c9 | 1813 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1814 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1815 | .mac_ops = &e82571_mac_ops, |
1816 | .phy_ops = &e82_phy_ops_igp, | |
1817 | .nvm_ops = &e82571_nvm_ops, | |
1818 | }; | |
1819 | ||
1820 | struct e1000_info e1000_82573_info = { | |
1821 | .mac = e1000_82573, | |
1822 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1823 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1824 | | FLAG_HAS_WOL |
1825 | | FLAG_APME_IN_CTRL3 | |
1826 | | FLAG_RX_CSUM_ENABLED | |
bc7f75fa AK |
1827 | | FLAG_HAS_SMART_POWER_DOWN |
1828 | | FLAG_HAS_AMT | |
bc7f75fa AK |
1829 | | FLAG_HAS_ERT |
1830 | | FLAG_HAS_SWSM_ON_LOAD, | |
1831 | .pba = 20, | |
2adc55c9 | 1832 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 1833 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1834 | .mac_ops = &e82571_mac_ops, |
1835 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 1836 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
1837 | }; |
1838 | ||
4662e82b BA |
1839 | struct e1000_info e1000_82574_info = { |
1840 | .mac = e1000_82574, | |
1841 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1842 | | FLAG_HAS_MSIX | |
1843 | | FLAG_HAS_JUMBO_FRAMES | |
1844 | | FLAG_HAS_WOL | |
1845 | | FLAG_APME_IN_CTRL3 | |
1846 | | FLAG_RX_CSUM_ENABLED | |
1847 | | FLAG_HAS_SMART_POWER_DOWN | |
1848 | | FLAG_HAS_AMT | |
1849 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1850 | .pba = 20, | |
a825e00c | 1851 | .max_hw_frame_size = DEFAULT_JUMBO, |
4662e82b BA |
1852 | .get_variants = e1000_get_variants_82571, |
1853 | .mac_ops = &e82571_mac_ops, | |
1854 | .phy_ops = &e82_phy_ops_bm, | |
1855 | .nvm_ops = &e82571_nvm_ops, | |
1856 | }; | |
1857 | ||
8c81c9c3 AD |
1858 | struct e1000_info e1000_82583_info = { |
1859 | .mac = e1000_82583, | |
1860 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1861 | | FLAG_HAS_WOL | |
1862 | | FLAG_APME_IN_CTRL3 | |
1863 | | FLAG_RX_CSUM_ENABLED | |
1864 | | FLAG_HAS_SMART_POWER_DOWN | |
1865 | | FLAG_HAS_AMT | |
1866 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1867 | .pba = 20, | |
a825e00c | 1868 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
8c81c9c3 AD |
1869 | .get_variants = e1000_get_variants_82571, |
1870 | .mac_ops = &e82571_mac_ops, | |
1871 | .phy_ops = &e82_phy_ops_bm, | |
1872 | .nvm_ops = &e82571_nvm_ops, | |
1873 | }; | |
1874 |